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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2009-10-28 10:10:56 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2009-10-28 10:10:56 +0100 |
| commit | 40a5f3de4e19d43fd34ddd0d81542f73ec64a287 (patch) | |
| tree | 0ecbebaaa9ddec5dce11382cfce8b473517b4ae6 /include | |
| parent | 5b28d03dbbfda2409a8bff4b77d5f38824a74782 (diff) | |
| parent | daad436bf76ad8acdf66326b1cc3769434cca97f (diff) | |
| download | barebox-40a5f3de4e19d43fd34ddd0d81542f73ec64a287.tar.gz barebox-40a5f3de4e19d43fd34ddd0d81542f73ec64a287.tar.xz | |
Merge branch 'for-sascha' of git://uboot.jcrosoft.org/u-boot-v2 into from-jean
Conflicts:
board/a9m2440/a9m2440.c
board/pcm043/pcm043.c
drivers/nand/nand_imx.c
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'include')
238 files changed, 2 insertions, 60873 deletions
diff --git a/include/asm-arm/.gitignore b/include/asm-arm/.gitignore deleted file mode 100644 index 673849bfc9..0000000000 --- a/include/asm-arm/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -arch -proc diff --git a/include/asm-arm/arch-at91/at91_pio.h b/include/asm-arm/arch-at91/at91_pio.h deleted file mode 100644 index f6ce1f924e..0000000000 --- a/include/asm-arm/arch-at91/at91_pio.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h] - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Parallel I/O Controller (PIO) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PIO_H -#define AT91_PIO_H - -#define PIO_PER 0x00 /* Enable Register */ -#define PIO_PDR 0x04 /* Disable Register */ -#define PIO_PSR 0x08 /* Status Register */ -#define PIO_OER 0x10 /* Output Enable Register */ -#define PIO_ODR 0x14 /* Output Disable Register */ -#define PIO_OSR 0x18 /* Output Status Register */ -#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ -#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ -#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ -#define PIO_SODR 0x30 /* Set Output Data Register */ -#define PIO_CODR 0x34 /* Clear Output Data Register */ -#define PIO_ODSR 0x38 /* Output Data Status Register */ -#define PIO_PDSR 0x3c /* Pin Data Status Register */ -#define PIO_IER 0x40 /* Interrupt Enable Register */ -#define PIO_IDR 0x44 /* Interrupt Disable Register */ -#define PIO_IMR 0x48 /* Interrupt Mask Register */ -#define PIO_ISR 0x4c /* Interrupt Status Register */ -#define PIO_MDER 0x50 /* Multi-driver Enable Register */ -#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ -#define PIO_MDSR 0x58 /* Multi-driver Status Register */ -#define PIO_PUDR 0x60 /* Pull-up Disable Register */ -#define PIO_PUER 0x64 /* Pull-up Enable Register */ -#define PIO_PUSR 0x68 /* Pull-up Status Register */ -#define PIO_ASR 0x70 /* Peripheral A Select Register */ -#define PIO_BSR 0x74 /* Peripheral B Select Register */ -#define PIO_ABSR 0x78 /* AB Status Register */ -#define PIO_OWER 0xa0 /* Output Write Enable Register */ -#define PIO_OWDR 0xa4 /* Output Write Disable Register */ -#define PIO_OWSR 0xa8 /* Output Write Status Register */ - -#endif diff --git a/include/asm-arm/arch-at91/at91_pit.h b/include/asm-arm/arch-at91/at91_pit.h deleted file mode 100644 index 94dd242a5f..0000000000 --- a/include/asm-arm/arch-at91/at91_pit.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_pit.h] - * - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Periodic Interval Timer (PIT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PIT_H -#define AT91_PIT_H - -#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ -#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ -#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ -#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ - -#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ -#define AT91_PIT_PITS (1 << 0) /* Timer Status */ - -#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ -#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ -#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ -#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ - -#endif diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h deleted file mode 100644 index ed40b8bf6a..0000000000 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h] - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Power Management Controller (PMC) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PMC_H -#define AT91_PMC_H - -#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ -#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ - -#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ -#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ -#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ -#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ -#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */ -#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ -#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ -#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ -#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ -#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ -#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ - -#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ -#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ -#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ - -#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */ -#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ -#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ -#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ -#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ - -#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ -#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ -#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ - -#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ -#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ -#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ - -#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ -#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ -#define AT91_PMC_DIV (0xff << 0) /* Divider */ -#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ -#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ -#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ -#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ -#define AT91_PMC_USBDIV_1 (0 << 28) -#define AT91_PMC_USBDIV_2 (1 << 28) -#define AT91_PMC_USBDIV_4 (2 << 28) -#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ -#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ - -#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ -#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ -#define AT91_PMC_CSS_SLOW (0 << 0) -#define AT91_PMC_CSS_MAIN (1 << 0) -#define AT91_PMC_CSS_PLLA (2 << 0) -#define AT91_PMC_CSS_PLLB (3 << 0) -#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ -#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ -#define AT91_PMC_PRES_1 (0 << 2) -#define AT91_PMC_PRES_2 (1 << 2) -#define AT91_PMC_PRES_4 (2 << 2) -#define AT91_PMC_PRES_8 (3 << 2) -#define AT91_PMC_PRES_16 (4 << 2) -#define AT91_PMC_PRES_32 (5 << 2) -#define AT91_PMC_PRES_64 (6 << 2) -#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ -#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ -#define AT91RM9200_PMC_MDIV_2 (1 << 8) -#define AT91RM9200_PMC_MDIV_3 (2 << 8) -#define AT91RM9200_PMC_MDIV_4 (3 << 8) -#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ -#define AT91SAM9_PMC_MDIV_2 (1 << 8) -#define AT91SAM9_PMC_MDIV_4 (2 << 8) -#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ -#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ -#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ -#define AT91_PMC_PDIV_1 (0 << 12) -#define AT91_PMC_PDIV_2 (1 << 12) -#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ -#define AT91_PMC_PLLADIV2_OFF (0 << 12) -#define AT91_PMC_PLLADIV2_ON (1 << 12) - -#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */ -#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ -#define AT91_PMC_USBS_PLLA (0 << 0) -#define AT91_PMC_USBS_UPLL (1 << 0) -#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ - -#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ -#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ -#define AT91_PMC_CSSMCK_CSS (0 << 8) -#define AT91_PMC_CSSMCK_MCK (1 << 8) - -#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ -#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ -#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ -#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ -#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ -#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ -#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ -#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */ -#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ -#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ - -#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ -#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ - -#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ - -#endif diff --git a/include/asm-arm/arch-at91/at91_rstc.h b/include/asm-arm/arch-at91/at91_rstc.h deleted file mode 100644 index e49caef921..0000000000 --- a/include/asm-arm/arch-at91/at91_rstc.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h] - * - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Reset Controller (RSTC) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_RSTC_H -#define AT91_RSTC_H - -#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ -#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ -#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ -#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ -#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ - -#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ -#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ -#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ -#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) -#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) -#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) -#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) -#define AT91_RSTC_RSTTYP_USER (4 << 8) -#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ -#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ - -#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ -#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ -#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ -#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ - -#endif diff --git a/include/asm-arm/arch-at91/at91_wdt.h b/include/asm-arm/arch-at91/at91_wdt.h deleted file mode 100644 index 7e18537cfb..0000000000 --- a/include/asm-arm/arch-at91/at91_wdt.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] - * - * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Watchdog Timer (WDT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_WDT_H -#define AT91_WDT_H - -#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ -#define AT91_WDT_WDRSTT (1 << 0) /* Restart */ -#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ - -#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ -#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ -#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ -#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ -#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ -#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ -#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ -#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ -#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ - -#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ -#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ -#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h deleted file mode 100644 index 7d166b7a89..0000000000 --- a/include/asm-arm/arch-at91/at91sam9260.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h] - * - * (C) 2006 Andrew Victor - * - * Common definitions. - * Based on AT91SAM9260 datasheet revision A (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9260_H -#define AT91SAM9260_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ -#define AT91SAM9260_ID_US0 6 /* USART 0 */ -#define AT91SAM9260_ID_US1 7 /* USART 1 */ -#define AT91SAM9260_ID_US2 8 /* USART 2 */ -#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ -#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9260_ID_UHP 20 /* USB Host port */ -#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ -#define AT91SAM9260_ID_US3 23 /* USART 3 */ -#define AT91SAM9260_ID_US4 24 /* USART 4 */ -#define AT91SAM9260_ID_US5 25 /* USART 5 */ -#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ -#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ -#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ -#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9260_BASE_TCB0 0xfffa0000 -#define AT91SAM9260_BASE_TC0 0xfffa0000 -#define AT91SAM9260_BASE_TC1 0xfffa0040 -#define AT91SAM9260_BASE_TC2 0xfffa0080 -#define AT91SAM9260_BASE_UDP 0xfffa4000 -#define AT91SAM9260_BASE_MCI 0xfffa8000 -#define AT91SAM9260_BASE_TWI 0xfffac000 -#define AT91SAM9260_BASE_US0 0xfffb0000 -#define AT91SAM9260_BASE_US1 0xfffb4000 -#define AT91SAM9260_BASE_US2 0xfffb8000 -#define AT91SAM9260_BASE_SSC 0xfffbc000 -#define AT91SAM9260_BASE_ISI 0xfffc0000 -#define AT91SAM9260_BASE_EMAC 0xfffc4000 -#define AT91SAM9260_BASE_SPI0 0xfffc8000 -#define AT91SAM9260_BASE_SPI1 0xfffcc000 -#define AT91SAM9260_BASE_US3 0xfffd0000 -#define AT91SAM9260_BASE_US4 0xfffd4000 -#define AT91SAM9260_BASE_US5 0xfffd8000 -#define AT91SAM9260_BASE_TCB1 0xfffdc000 -#define AT91SAM9260_BASE_TC3 0xfffdc000 -#define AT91SAM9260_BASE_TC4 0xfffdc040 -#define AT91SAM9260_BASE_TC5 0xfffdc080 -#define AT91SAM9260_BASE_ADC 0xfffe0000 -#define AT91_BASE_SYS 0xffffe800 - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9260_BASE_US0 -#define AT91_USART1 AT91SAM9260_BASE_US1 -#define AT91_USART2 AT91SAM9260_BASE_US2 -#define AT91_USART3 AT91SAM9260_BASE_US3 -#define AT91_USART4 AT91SAM9260_BASE_US4 -#define AT91_USART5 AT91SAM9260_BASE_US5 - -#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 -#define AT91_BASE_TWI AT91SAM9260_BASE_TWI -#define AT91_ID_UHP AT91SAM9260_ID_UHP -#define AT91_PMC_UHP AT91SAM926x_PMC_UHP - -/* - * Internal Memory. - */ -#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ -#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ - -#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ - -#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ -#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ - -/* - * Cpu Name - */ -#if defined(CONFIG_AT91SAM9260) -#define AT91_CPU_NAME "AT91SAM9260" -#elif defined(CONFIG_AT91SAM9G20) -#define AT91_CPU_NAME "AT91SAM9G20" -#endif - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9260_matrix.h b/include/asm-arm/arch-at91/at91sam9260_matrix.h deleted file mode 100644 index 020f02ed92..0000000000 --- a/include/asm-arm/arch-at91/at91sam9260_matrix.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91sam9260_matrix.h - * - * Copyright (C) 2007 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9260 datasheet revision B. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9260_MATRIX_H -#define AT91SAM9260_MATRIX_H - -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ - -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ - -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h deleted file mode 100644 index 7bab1a4b10..0000000000 --- a/include/asm-arm/arch-at91/at91sam9263.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] - * - * (C) 2007 Atmel Corporation. - * - * Common definitions. - * Based on AT91SAM9263 datasheet revision B (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9263_H -#define AT91SAM9263_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ -#define AT91SAM9263_ID_US0 7 /* USART 0 */ -#define AT91SAM9263_ID_US1 8 /* USART 1 */ -#define AT91SAM9263_ID_US2 9 /* USART 2 */ -#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ -#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ -#define AT91SAM9263_ID_CAN 12 /* CAN */ -#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ -#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ -#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ -#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ -#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ -#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ -#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ -#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ -#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ -#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ -#define AT91SAM9263_ID_UHP 29 /* USB Host port */ -#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9263_BASE_UDP 0xfff78000 -#define AT91SAM9263_BASE_TCB0 0xfff7c000 -#define AT91SAM9263_BASE_TC0 0xfff7c000 -#define AT91SAM9263_BASE_TC1 0xfff7c040 -#define AT91SAM9263_BASE_TC2 0xfff7c080 -#define AT91SAM9263_BASE_MCI0 0xfff80000 -#define AT91SAM9263_BASE_MCI1 0xfff84000 -#define AT91SAM9263_BASE_TWI 0xfff88000 -#define AT91SAM9263_BASE_US0 0xfff8c000 -#define AT91SAM9263_BASE_US1 0xfff90000 -#define AT91SAM9263_BASE_US2 0xfff94000 -#define AT91SAM9263_BASE_SSC0 0xfff98000 -#define AT91SAM9263_BASE_SSC1 0xfff9c000 -#define AT91SAM9263_BASE_AC97C 0xfffa0000 -#define AT91SAM9263_BASE_SPI0 0xfffa4000 -#define AT91SAM9263_BASE_SPI1 0xfffa8000 -#define AT91SAM9263_BASE_CAN 0xfffac000 -#define AT91SAM9263_BASE_PWMC 0xfffb8000 -#define AT91SAM9263_BASE_EMAC 0xfffbc000 -#define AT91SAM9263_BASE_ISI 0xfffc4000 -#define AT91SAM9263_BASE_2DGE 0xfffc8000 -#define AT91_BASE_SYS 0xffffe000 - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) -#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) -#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) -#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) -#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9263_BASE_US0 -#define AT91_USART1 AT91SAM9263_BASE_US1 -#define AT91_USART2 AT91SAM9263_BASE_US2 - -#define AT91_SMC AT91_SMC0 -#define AT91_SDRAMC AT91_SDRAMC0 - -#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0 -#define AT91_BASE_TWI AT91SAM9263_BASE_TWI -#define AT91_ID_UHP AT91SAM9263_ID_UHP -#define AT91_PMC_UHP AT91SAM926x_PMC_UHP - -/* - * Internal Memory. - */ -#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ -#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ - -#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ - -#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ -#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ - -#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ -#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ -#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ - -/* - * Cpu Name - */ -#define AT91_CPU_NAME "AT91SAM9263" - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9263_matrix.h b/include/asm-arm/arch-at91/at91sam9263_matrix.h deleted file mode 100644 index 83aaaab773..0000000000 --- a/include/asm-arm/arch-at91/at91sam9263_matrix.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h] - * - * Copyright (C) 2006 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9263 datasheet revision B (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9263_MATRIX_H -#define AT91SAM9263_MATRIX_H - -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ -#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ -#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ -#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ -#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ -#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ -#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ -#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ -#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ - -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) - -#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_16 (5 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_16 (5 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) - -#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ -#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4) -#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5) -#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) - -#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ -#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3) -#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9_matrix.h b/include/asm-arm/arch-at91/at91sam9_matrix.h deleted file mode 100644 index 56600c741b..0000000000 --- a/include/asm-arm/arch-at91/at91sam9_matrix.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jrosoft.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_AT91SAM9_MATRIX_H -#define __ASM_ARCH_AT91SAM9_MATRIX_H - -#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) -#include <asm/arch/at91sam9260_matrix.h> -#elif defined(CONFIG_ARCH_AT91SAM9261) -#include <asm/arch/at91sam9261_matrix.h> -#elif defined(CONFIG_ARCH_AT91SAM9263) -#include <asm/arch/at91sam9263_matrix.h> -#elif defined(CONFIG_ARCH_AT91SAM9RL) -#include <asm/arch/at91sam9rl_matrix.h> -#elif defined(CONFIG_ARCH_AT91CAP9) -#include <asm/arch/at91cap9_matrix.h> -#elif defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT91SAM9M10G45) -#include <asm/arch/at91sam9g45_matrix.h> -#else -#error "Unsupported AT91SAM9/CAP9 processor" -#endif - -#endif /* __ASM_ARCH_AT91SAM9_MATRIX_H */ diff --git a/include/asm-arm/arch-at91/at91sam9_sdramc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h deleted file mode 100644 index 5af2b54b12..0000000000 --- a/include/asm-arm/arch-at91/at91sam9_sdramc.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] - * - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * SDRAM Controllers (SDRAMC) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9_SDRAMC_H -#define AT91SAM9_SDRAMC_H - -/* SDRAM Controller (SDRAMC) registers */ -#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ -#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ -#define AT91_SDRAMC_MODE_NORMAL 0 -#define AT91_SDRAMC_MODE_NOP 1 -#define AT91_SDRAMC_MODE_PRECHARGE 2 -#define AT91_SDRAMC_MODE_LMR 3 -#define AT91_SDRAMC_MODE_REFRESH 4 -#define AT91_SDRAMC_MODE_EXT_LMR 5 -#define AT91_SDRAMC_MODE_DEEP 6 - -#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ -#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ - -#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ -#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ -#define AT91_SDRAMC_NC_8 (0 << 0) -#define AT91_SDRAMC_NC_9 (1 << 0) -#define AT91_SDRAMC_NC_10 (2 << 0) -#define AT91_SDRAMC_NC_11 (3 << 0) -#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ -#define AT91_SDRAMC_NR_11 (0 << 2) -#define AT91_SDRAMC_NR_12 (1 << 2) -#define AT91_SDRAMC_NR_13 (2 << 2) -#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ -#define AT91_SDRAMC_NB_2 (0 << 4) -#define AT91_SDRAMC_NB_4 (1 << 4) -#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ -#define AT91_SDRAMC_CAS_1 (1 << 5) -#define AT91_SDRAMC_CAS_2 (2 << 5) -#define AT91_SDRAMC_CAS_3 (3 << 5) -#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ -#define AT91_SDRAMC_DBW_32 (0 << 7) -#define AT91_SDRAMC_DBW_16 (1 << 7) -#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ -#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ -#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ -#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ -#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ -#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ - -#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ -#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ -#define AT91_SDRAMC_LPCB_DISABLE 0 -#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 -#define AT91_SDRAMC_LPCB_POWER_DOWN 2 -#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 -#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ -#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ -#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */ -#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ -#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) -#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) -#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) - -#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ -#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ -#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ -#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ -#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ - -#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ -#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ -#define AT91_SDRAMC_MD_SDRAM 0 -#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 - - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9_smc.h b/include/asm-arm/arch-at91/at91sam9_smc.h deleted file mode 100644 index d64511b36d..0000000000 --- a/include/asm-arm/arch-at91/at91sam9_smc.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h] - * - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Static Memory Controllers (SMC) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9_SMC_H -#define AT91SAM9_SMC_H - -#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ -#define AT91_SMC_NWESETUP_(x) ((x) << 0) -#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ -#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) -#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ -#define AT91_SMC_NRDSETUP_(x) ((x) << 16) -#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ -#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) - -#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ -#define AT91_SMC_NWEPULSE_(x) ((x) << 0) -#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ -#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) -#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ -#define AT91_SMC_NRDPULSE_(x) ((x) << 16) -#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ -#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) - -#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ -#define AT91_SMC_NWECYCLE_(x) ((x) << 0) -#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ -#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) - -#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ -#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ -#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ -#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) -#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) -#define AT91_SMC_EXNWMODE_READY (3 << 4) -#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ -#define AT91_SMC_BAT_SELECT (0 << 8) -#define AT91_SMC_BAT_WRITE (1 << 8) -#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ -#define AT91_SMC_DBW_8 (0 << 12) -#define AT91_SMC_DBW_16 (1 << 12) -#define AT91_SMC_DBW_32 (2 << 12) -#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ -#define AT91_SMC_TDF_(x) ((x) << 16) -#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ -#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ -#define AT91_SMC_PS (3 << 28) /* Page Size */ -#define AT91_SMC_PS_4 (0 << 28) -#define AT91_SMC_PS_8 (1 << 28) -#define AT91_SMC_PS_16 (2 << 28) -#define AT91_SMC_PS_32 (3 << 28) - -#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ -#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#endif - -#endif diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h deleted file mode 100644 index 1ab05ade87..0000000000 --- a/include/asm-arm/arch-at91/board.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * [origin Linux: arch/arm/mach-at91/include/mach/board.h] - * - * Copyright (C) 2005 HP Labs - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_BOARD_H -#define __ASM_ARCH_BOARD_H - -#include <linux/mtd/mtd.h> - -void atmel_nand_load_image(void *dest, int size, int pagesize, int blocksize); - - /* NAND / SmartMedia */ -struct atmel_nand_data { - void __iomem *ecc_base; - u8 enable_pin; /* chip enable */ - u8 det_pin; /* card detect */ - u8 rdy_pin; /* ready/busy */ - u8 ale; /* address line number connected to ALE */ - u8 cle; /* address line number connected to CLE */ - u8 bus_width_16; /* buswidth is 16 bit */ - u8 ecc_mode; /* NAND_ECC_* */ -}; - -void at91_add_device_nand(struct atmel_nand_data *data); - - /* Ethernet (EMAC & MACB) */ -#define AT91SAM_ETHER_MII (0 << 0) -#define AT91SAM_ETHER_RMII (1 << 0) -#define AT91SAM_ETHER_FORCE_LINK (1 << 1) - -struct at91_ether_platform_data { - unsigned int flags; - int phy_addr; -}; - -void at91_add_device_eth(struct at91_ether_platform_data *data); - -/* SDRAM */ -void at91_add_device_sdram(u32 size); - - /* Serial */ -#define ATMEL_UART_CTS 0x01 -#define ATMEL_UART_RTS 0x02 -#define ATMEL_UART_DSR 0x04 -#define ATMEL_UART_DTR 0x08 -#define ATMEL_UART_DCD 0x10 -#define ATMEL_UART_RI 0x20 - -void at91_register_uart(unsigned id, unsigned pins); -#endif diff --git a/include/asm-arm/arch-at91/clk.h b/include/asm-arm/arch-at91/clk.h deleted file mode 100644 index f67b4356d9..0000000000 --- a/include/asm-arm/arch-at91/clk.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2007 - * Stelian Pop <stelian.pop@leadtechdesign.com> - * Lead Tech Design <www.leadtechdesign.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_CLK_H__ -#define __ASM_ARM_ARCH_CLK_H__ - -#include <asm/arch/hardware.h> - -static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) -{ - return AT91_MASTER_CLOCK; -} - -static inline unsigned long get_usart_clk_rate(unsigned int dev_id) -{ - return AT91_MASTER_CLOCK; -} - -#endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/include/asm-arm/arch-at91/gpio.h b/include/asm-arm/arch-at91/gpio.h deleted file mode 100644 index 1b0238c4cb..0000000000 --- a/include/asm-arm/arch-at91/gpio.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h] - * - * Copyright (C) 2005 HP Labs - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_AT91_GPIO_H -#define __ASM_ARCH_AT91_GPIO_H - -#include <asm/io.h> -#include <asm-generic/errno.h> -#include <asm/arch/at91_pio.h> -#include <asm/arch/hardware.h> - -#define PIN_BASE 32 - -/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ - -#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) -#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) -#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) -#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) -#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) -#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) -#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) -#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) -#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) -#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) -#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) -#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) -#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) -#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) -#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) -#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) -#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) -#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) -#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) -#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) -#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) -#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) -#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) -#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) -#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) -#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) -#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) -#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) -#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) -#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) -#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) -#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) - -#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) -#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) -#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) -#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) -#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) -#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) -#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) -#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) -#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) -#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) -#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) -#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) -#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) -#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) -#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) -#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) -#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) -#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) -#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) -#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) -#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) -#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) -#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) -#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) -#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) -#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) -#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) -#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) -#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) -#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) -#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) -#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) - -#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) -#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) -#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) -#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) -#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) -#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) -#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) -#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) -#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) -#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) -#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) -#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) -#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) -#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) -#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) -#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) -#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) -#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) -#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) -#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) -#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) -#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) -#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) -#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) -#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) -#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) -#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) -#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) -#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) -#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) -#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) -#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) - -#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) -#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) -#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) -#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) -#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) -#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) -#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) -#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) -#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) -#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) -#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) -#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) -#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) -#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) -#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) -#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) -#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) -#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) -#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) -#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) -#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) -#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) -#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) -#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) -#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) -#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) -#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) -#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) -#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) -#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) -#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) -#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) - -#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0) -#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1) -#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2) -#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3) -#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4) -#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5) -#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6) -#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7) -#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8) -#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9) -#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10) -#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11) -#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12) -#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13) -#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14) -#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15) -#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16) -#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17) -#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18) -#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19) -#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20) -#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21) -#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22) -#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23) -#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24) -#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25) -#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26) -#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27) -#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28) -#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29) -#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30) -#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) - -/* - * mux the pin to the "GPIO" peripheral role. - */ -int at91_set_GPIO_periph(unsigned pin, int use_pullup); - - -/* - * mux the pin to the "A" internal peripheral role. - */ -int at91_set_A_periph(unsigned pin, int use_pullup); - -/* - * mux the pin to the "B" internal peripheral role. - */ -int at91_set_B_periph(unsigned pin, int use_pullup); -/* - * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and - * configure it for an input. - */ -int at91_set_gpio_input(unsigned pin, int use_pullup); - -/* - * mux the pin to the gpio controller (instead of "A" or "B" peripheral), - * and configure it for an output. - */ -int at91_set_gpio_output(unsigned pin, int value); - -/* - * enable/disable the glitch filter; mostly used with IRQ handling. - */ -int at91_set_deglitch(unsigned pin, int is_on); - -/* - * enable/disable the multi-driver; This is only valid for output and - * allows the output pin to run as an open collector output. - */ -int at91_set_multi_drive(unsigned pin, int is_on); - -/* - * assuming the pin is muxed as a gpio output, set its value. - */ -int at91_set_gpio_value(unsigned pin, int value); - -/* - * read the pin's value (works even if it's not muxed as a gpio). - */ -int at91_get_gpio_value(unsigned pin); - -struct at91_gpio_bank { - unsigned chipbase; /* bank's first GPIO number */ - void __iomem *regbase; /* base of register bank */ - struct at91_gpio_bank *next; /* bank sharing same IRQ/clock/... */ - unsigned short id; /* peripheral ID */ - unsigned long offset; /* offset from system peripheral base */ -}; - -extern int at91_gpio_init(struct at91_gpio_bank *data, int nr_banks); - -static inline int gpio_request(unsigned gpio, const char *label) -{ - return 0; -} - -static inline void gpio_free(unsigned gpio) -{ -} - -extern int gpio_direction_input(unsigned gpio); -extern int gpio_direction_output(unsigned gpio, int value); -#define gpio_get_value at91_get_gpio_value -#define gpio_set_value at91_set_gpio_value - -#endif /* __ASM_ARCH_AT91SAM9_GPIO_H */ diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h deleted file mode 100644 index 6f48c3439e..0000000000 --- a/include/asm-arm/arch-at91/hardware.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/hardware.h] - * - * Copyright (C) 2003 SAN People - * Copyright (C) 2003 ATMEL - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#if defined(CONFIG_ARCH_AT91RM9200) -#include <asm/arch/at91rm9200.h> -#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) -#include <asm/arch/at91sam9260.h> -#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10) -#include <asm/arch/at91sam9261.h> -#elif defined(CONFIG_ARCH_AT91SAM9263) -#include <asm/arch/at91sam9263.h> -#elif defined(CONFIG_ARCH_AT91SAM9RL) -#include <asm/arch/at91sam9rl.h> -#elif defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT91SAM9M10G45) -#include <asm/arch/at91sam9g45.h> -#elif defined(CONFIG_ARCH_AT91CAP9) -#include <asm/arch/at91cap9.h> -#elif defined(CONFIG_ARCH_AT91X40) -#include <asm/arch/at91x40.h> -#else -#error "Unsupported AT91 processor" -#endif - -/* External Memory Map */ -#define AT91_CHIPSELECT_0 0x10000000 -#define AT91_CHIPSELECT_1 0x20000000 -#define AT91_CHIPSELECT_2 0x30000000 -#define AT91_CHIPSELECT_3 0x40000000 -#define AT91_CHIPSELECT_4 0x50000000 -#define AT91_CHIPSELECT_5 0x60000000 -#define AT91_CHIPSELECT_6 0x70000000 -#define AT91_CHIPSELECT_7 0x80000000 - -/* SDRAM */ -#ifdef CONFIG_DRAM_BASE -#define AT91_SDRAM_BASE CONFIG_DRAM_BASE -#else -#define AT91_SDRAM_BASE AT91_CHIPSELECT_1 -#endif - -/* Clocks */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#endif diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h deleted file mode 100644 index f09b2df0e3..0000000000 --- a/include/asm-arm/arch-at91/io.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/io.h] - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include <asm/io.h> - -static inline unsigned int at91_sys_read(unsigned int reg_offset) -{ - void *addr = (void *)AT91_BASE_SYS; - - return __raw_readl(addr + reg_offset); -} - -static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) -{ - void *addr = (void *)AT91_BASE_SYS; - - __raw_writel(value, addr + reg_offset); -} - -#endif diff --git a/include/asm-arm/arch-at91/sam9_smc.h b/include/asm-arm/arch-at91/sam9_smc.h deleted file mode 100644 index bf72cfb345..0000000000 --- a/include/asm-arm/arch-at91/sam9_smc.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * linux/arch/arm/mach-at91/sam9_smc. - * - * Copyright (C) 2008 Andrew Victor - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -struct sam9_smc_config { - /* Setup register */ - u8 ncs_read_setup; - u8 nrd_setup; - u8 ncs_write_setup; - u8 nwe_setup; - - /* Pulse register */ - u8 ncs_read_pulse; - u8 nrd_pulse; - u8 ncs_write_pulse; - u8 nwe_pulse; - - /* Cycle register */ - u16 read_cycle; - u16 write_cycle; - - /* Mode register */ - u32 mode; - u8 tdf_cycles:4; -}; - -extern void __init sam9_smc_configure(int cs, struct sam9_smc_config* config); diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h deleted file mode 100644 index 97d470484c..0000000000 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ /dev/null @@ -1,762 +0,0 @@ -/* - * (C) Copyright 2003 - * AT91RM9200 definitions - * Author : ATMEL AT91 application group - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef AT91RM9200_H -#define AT91RM9200_H - -typedef volatile unsigned int AT91_REG; /* Hardware register definition */ - -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ -/******************************************************************************/ -typedef struct _AT91S_TC -{ - AT91_REG TC_CCR; /* Channel Control Register */ - AT91_REG TC_CMR; /* Channel Mode Register */ - AT91_REG Reserved0[2]; /* */ - AT91_REG TC_CV; /* Counter Value */ - AT91_REG TC_RA; /* Register A */ - AT91_REG TC_RB; /* Register B */ - AT91_REG TC_RC; /* Register C */ - AT91_REG TC_SR; /* Status Register */ - AT91_REG TC_IER; /* Interrupt Enable Register */ - AT91_REG TC_IDR; /* Interrupt Disable Register */ - AT91_REG TC_IMR; /* Interrupt Mask Register */ -} AT91S_TC, *AT91PS_TC; - -#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ -#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ -#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ -#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ -#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */ -#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ -#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ -#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ - -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Usart */ -/******************************************************************************/ -typedef struct _AT91S_USART -{ - AT91_REG US_CR; /* Control Register */ - AT91_REG US_MR; /* Mode Register */ - AT91_REG US_IER; /* Interrupt Enable Register */ - AT91_REG US_IDR; /* Interrupt Disable Register */ - AT91_REG US_IMR; /* Interrupt Mask Register */ - AT91_REG US_CSR; /* Channel Status Register */ - AT91_REG US_RHR; /* Receiver Holding Register */ - AT91_REG US_THR; /* Transmitter Holding Register */ - AT91_REG US_BRGR; /* Baud Rate Generator Register */ - AT91_REG US_RTOR; /* Receiver Time-out Register */ - AT91_REG US_TTGR; /* Transmitter Time-guard Register */ - AT91_REG Reserved0[5]; /* */ - AT91_REG US_FIDI; /* FI_DI_Ratio Register */ - AT91_REG US_NER; /* Nb Errors Register */ - AT91_REG US_XXR; /* XON_XOFF Register */ - AT91_REG US_IF; /* IRDA_FILTER Register */ - AT91_REG Reserved1[44]; /* */ - AT91_REG US_RPR; /* Receive Pointer Register */ - AT91_REG US_RCR; /* Receive Counter Register */ - AT91_REG US_TPR; /* Transmit Pointer Register */ - AT91_REG US_TCR; /* Transmit Counter Register */ - AT91_REG US_RNPR; /* Receive Next Pointer Register */ - AT91_REG US_RNCR; /* Receive Next Counter Register */ - AT91_REG US_TNPR; /* Transmit Next Pointer Register */ - AT91_REG US_TNCR; /* Transmit Next Counter Register */ - AT91_REG US_PTCR; /* PDC Transfer Control Register */ - AT91_REG US_PTSR; /* PDC Transfer Status Register */ -} AT91S_USART, *AT91PS_USART; - -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Clock Generator Controler */ -/******************************************************************************/ -typedef struct _AT91S_CKGR -{ - AT91_REG CKGR_MOR; /* Main Oscillator Register */ - AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ - AT91_REG CKGR_PLLAR; /* PLL A Register */ - AT91_REG CKGR_PLLBR; /* PLL B Register */ -} AT91S_CKGR, *AT91PS_CKGR; - -/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */ -#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */ -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */ - -/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */ -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */ - -/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */ -#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ -#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ -#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ -#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter */ -#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range */ -#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */ -#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */ - -/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */ -#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ -#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ -#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ -#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter */ -#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range */ -#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier */ -#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */ -#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */ - -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ -/******************************************************************************/ -typedef struct _AT91S_PIO -{ - AT91_REG PIO_PER; /* PIO Enable Register */ - AT91_REG PIO_PDR; /* PIO Disable Register */ - AT91_REG PIO_PSR; /* PIO Status Register */ - AT91_REG Reserved0[1]; /* */ - AT91_REG PIO_OER; /* Output Enable Register */ - AT91_REG PIO_ODR; /* Output Disable Registerr */ - AT91_REG PIO_OSR; /* Output Status Register */ - AT91_REG Reserved1[1]; /* */ - AT91_REG PIO_IFER; /* Input Filter Enable Register */ - AT91_REG PIO_IFDR; /* Input Filter Disable Register */ - AT91_REG PIO_IFSR; /* Input Filter Status Register */ - AT91_REG Reserved2[1]; /* */ - AT91_REG PIO_SODR; /* Set Output Data Register */ - AT91_REG PIO_CODR; /* Clear Output Data Register */ - AT91_REG PIO_ODSR; /* Output Data Status Register */ - AT91_REG PIO_PDSR; /* Pin Data Status Register */ - AT91_REG PIO_IER; /* Interrupt Enable Register */ - AT91_REG PIO_IDR; /* Interrupt Disable Register */ - AT91_REG PIO_IMR; /* Interrupt Mask Register */ - AT91_REG PIO_ISR; /* Interrupt Status Register */ - AT91_REG PIO_MDER; /* Multi-driver Enable Register */ - AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ - AT91_REG PIO_MDSR; /* Multi-driver Status Register */ - AT91_REG Reserved3[1]; /* */ - AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ - AT91_REG PIO_PPUER; /* Pull-up Enable Register */ - AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ - AT91_REG Reserved4[1]; /* */ - AT91_REG PIO_ASR; /* Select A Register */ - AT91_REG PIO_BSR; /* Select B Register */ - AT91_REG PIO_ABSR; /* AB Select Status Register */ - AT91_REG Reserved5[9]; /* */ - AT91_REG PIO_OWER; /* Output Write Enable Register */ - AT91_REG PIO_OWDR; /* Output Write Disable Register */ - AT91_REG PIO_OWSR; /* Output Write Status Register */ -} AT91S_PIO, *AT91PS_PIO; - - -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Debug Unit */ -/******************************************************************************/ -typedef struct _AT91S_DBGU -{ - AT91_REG DBGU_CR; /* Control Register */ - AT91_REG DBGU_MR; /* Mode Register */ - AT91_REG DBGU_IER; /* Interrupt Enable Register */ - AT91_REG DBGU_IDR; /* Interrupt Disable Register */ - AT91_REG DBGU_IMR; /* Interrupt Mask Register */ - AT91_REG DBGU_CSR; /* Channel Status Register */ - AT91_REG DBGU_RHR; /* Receiver Holding Register */ - AT91_REG DBGU_THR; /* Transmitter Holding Register */ - AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ - AT91_REG Reserved0[7]; /* */ - AT91_REG DBGU_C1R; /* Chip ID1 Register */ - AT91_REG DBGU_C2R; /* Chip ID2 Register */ - AT91_REG DBGU_FNTR; /* Force NTRST Register */ - AT91_REG Reserved1[45]; /* */ - AT91_REG DBGU_RPR; /* Receive Pointer Register */ - AT91_REG DBGU_RCR; /* Receive Counter Register */ - AT91_REG DBGU_TPR; /* Transmit Pointer Register */ - AT91_REG DBGU_TCR; /* Transmit Counter Register */ - AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ - AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ - AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ - AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ - AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ - AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ -} AT91S_DBGU, *AT91PS_DBGU; - -/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */ -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */ -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */ -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */ -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */ -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */ -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */ -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */ -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */ -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */ -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */ -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */ - -/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */ -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */ -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */ -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */ -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */ -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */ - -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */ -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */ -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */ -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */ - -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ -/******************************************************************************/ -typedef struct _AT91S_SMC2 -{ - AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ -} AT91S_SMC2, *AT91PS_SMC2; - -/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */ -#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */ -#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ -#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */ -#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */ -#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */ -#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */ -#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ -#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */ -#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */ -#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ -#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */ -#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */ -#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */ -#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */ -#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */ - -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Power Management Controler */ -/******************************************************************************/ -typedef struct _AT91S_PMC -{ - AT91_REG PMC_SCER; /* System Clock Enable Register */ - AT91_REG PMC_SCDR; /* System Clock Disable Register */ - AT91_REG PMC_SCSR; /* System Clock Status Register */ - AT91_REG Reserved0[1]; /* */ - AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ - AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ - AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ - AT91_REG Reserved1[5]; /* */ - AT91_REG PMC_MCKR; /* Master Clock Register */ - AT91_REG Reserved2[3]; /* */ - AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ - AT91_REG PMC_IER; /* Interrupt Enable Register */ - AT91_REG PMC_IDR; /* Interrupt Disable Register */ - AT91_REG PMC_SR; /* Status Register */ - AT91_REG PMC_IMR; /* Interrupt Mask Register */ -} AT91S_PMC, *AT91PS_PMC; - -/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/ -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */ -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */ -#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */ -#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */ -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */ -/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/ -/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/ -/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/ -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */ -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */ -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */ -#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */ -#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */ -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */ -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */ -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */ -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */ -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */ -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */ -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */ -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */ -#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */ -#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */ -#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */ -#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */ -#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */ -/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/ -/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/ -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */ -#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */ -#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */ -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */ -/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/ -/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/ -/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/ - -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Ethernet MAC */ -/******************************************************************************/ -typedef struct _AT91S_EMAC -{ - AT91_REG EMAC_CTL; /* Network Control Register */ - AT91_REG EMAC_CFG; /* Network Configuration Register */ - AT91_REG EMAC_SR; /* Network Status Register */ - AT91_REG EMAC_TAR; /* Transmit Address Register */ - AT91_REG EMAC_TCR; /* Transmit Control Register */ - AT91_REG EMAC_TSR; /* Transmit Status Register */ - AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ - AT91_REG Reserved0[1]; /* */ - AT91_REG EMAC_RSR; /* Receive Status Register */ - AT91_REG EMAC_ISR; /* Interrupt Status Register */ - AT91_REG EMAC_IER; /* Interrupt Enable Register */ - AT91_REG EMAC_IDR; /* Interrupt Disable Register */ - AT91_REG EMAC_IMR; /* Interrupt Mask Register */ - AT91_REG EMAC_MAN; /* PHY Maintenance Register */ - AT91_REG Reserved1[2]; /* */ - AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */ - AT91_REG EMAC_SCOL; /* Single Collision Frame Register */ - AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */ - AT91_REG EMAC_OK; /* Frames Received OK Register */ - AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */ - AT91_REG EMAC_ALE; /* Alignment Error Register */ - AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */ - AT91_REG EMAC_LCOL; /* Late Collision Register */ - AT91_REG EMAC_ECOL; /* Excessive Collision Register */ - AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ - AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */ - AT91_REG EMAC_CDE; /* Code Error Register */ - AT91_REG EMAC_ELR; /* Excessive Length Error Register */ - AT91_REG EMAC_RJB; /* Receive Jabber Register */ - AT91_REG EMAC_USF; /* Undersize Frame Register */ - AT91_REG EMAC_SQEE; /* SQE Test Error Register */ - AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */ - AT91_REG Reserved2[3]; /* */ - AT91_REG EMAC_HSH; /* Hash Address High[63:32] */ - AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */ - AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */ - AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */ - AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */ - AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */ - AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */ - AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */ - AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */ - AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */ -} AT91S_EMAC, *AT91PS_EMAC; - -/* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */ -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ -#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) /* (EMAC) Loopback local. */ -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */ -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */ -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */ -#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */ -#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) /* (EMAC) Increment statistics registers. */ -#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) /* (EMAC) Write enable for statistics registers. */ -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */ - -/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */ -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */ -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */ -#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) /* (EMAC) Bit rate. */ -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */ -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */ -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) /* (EMAC) Multicast hash enable */ -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) /* (EMAC) Unicast hash enable. */ -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) /* (EMAC) Receive 1522 bytes. */ -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) /* (EMAC) External address match enable. */ -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */ -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */ -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */ -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */ -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */ -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) /* (EMAC) */ -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */ - -/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- */ -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */ - -/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */ -#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */ -#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */ - -/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */ -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */ -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */ -#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) /* (EMAC) */ -#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */ -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */ -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) /* (EMAC) */ - -/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */ -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */ - -/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ -#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */ -#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */ -#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) /* (EMAC) */ -#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) /* (EMAC) */ -#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) /* (EMAC) */ -#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) /* (EMAC) */ -#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) /* (EMAC) */ -#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) /* (EMAC) */ -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */ -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */ -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */ - -/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ -/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ -/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ -/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */ -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */ -#define AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */ -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */ -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) /* (EMAC) */ -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) /* (EMAC) */ -#define AT91C_EMAC_RW_R ((unsigned int) 0x2 << 28) /* (EMAC) Read Operation */ -#define AT91C_EMAC_RW_W ((unsigned int) 0x1 << 28) /* (EMAC) Write Operation */ -#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */ -#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */ - -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ -/******************************************************************************/ -typedef struct _AT91S_SPI -{ - AT91_REG SPI_CR; /* Control Register */ - AT91_REG SPI_MR; /* Mode Register */ - AT91_REG SPI_RDR; /* Receive Data Register */ - AT91_REG SPI_TDR; /* Transmit Data Register */ - AT91_REG SPI_SR; /* Status Register */ - AT91_REG SPI_IER; /* Interrupt Enable Register */ - AT91_REG SPI_IDR; /* Interrupt Disable Register */ - AT91_REG SPI_IMR; /* Interrupt Mask Register */ - AT91_REG Reserved0[4]; /* */ - AT91_REG SPI_CSR[4]; /* Chip Select Register */ - AT91_REG Reserved1[48]; /* */ - AT91_REG SPI_RPR; /* Receive Pointer Register */ - AT91_REG SPI_RCR; /* Receive Counter Register */ - AT91_REG SPI_TPR; /* Transmit Pointer Register */ - AT91_REG SPI_TCR; /* Transmit Counter Register */ - AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ - AT91_REG SPI_RNCR; /* Receive Next Counter Register */ - AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ - AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ - AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ - AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ -} AT91S_SPI, *AT91PS_SPI; - -/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */ -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */ -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */ - -/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */ -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */ -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) /* (SPI) Fixed Peripheral Select */ -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) /* (SPI) Variable Peripheral Select */ -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) /* (SPI) Chip Select Decode */ -#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) /* (SPI) Clock Selection */ -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) /* (SPI) Mode Fault Detection */ -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */ -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */ -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */ - -/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */ -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ - -/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */ -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ - -/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */ -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */ -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) /* (SPI) Mode Fault Error */ -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) /* (SPI) Overrun Error Status */ -#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) /* (SPI) End of Receiver Transfer */ -#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) /* (SPI) End of Receiver Transfer */ -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */ -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */ -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */ - -/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ -/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ -/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */ -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) /* (SPI) Clock Phase */ -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) /* (SPI) Bits Per Transfer */ -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) /* (SPI) 8 Bits Per transfer */ -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) /* (SPI) 9 Bits Per transfer */ -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) /* (SPI) 10 Bits Per transfer */ -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) /* (SPI) 11 Bits Per transfer */ -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) /* (SPI) 12 Bits Per transfer */ -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) /* (SPI) 13 Bits Per transfer */ -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) /* (SPI) 14 Bits Per transfer */ -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) /* (SPI) 15 Bits Per transfer */ -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) /* (SPI) 16 Bits Per transfer */ -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) /* (SPI) Serial Clock Baud Rate */ -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */ -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */ - -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ -/******************************************************************************/ -typedef struct _AT91S_PDC -{ - AT91_REG PDC_RPR; /* Receive Pointer Register */ - AT91_REG PDC_RCR; /* Receive Counter Register */ - AT91_REG PDC_TPR; /* Transmit Pointer Register */ - AT91_REG PDC_TCR; /* Transmit Counter Register */ - AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ - AT91_REG PDC_RNCR; /* Receive Next Counter Register */ - AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ - AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ - AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ - AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ -} AT91S_PDC, *AT91PS_PDC; - -/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */ -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) /* (PDC) Receiver Transfer Disable */ -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) /* (PDC) Transmitter Transfer Enable */ -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) /* (PDC) Transmitter Transfer Disable */ -/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ - -/* ========== Register definition ==================================== */ -#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) /* (SPI) Chip Select Register */ -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */ -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */ -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */ -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */ -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) /* (PIOA) PIO Enable Register */ -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */ -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) /* (PIOA) PIO Status Register */ -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) /* (PIOA) PIO Output Enable Register */ -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) /* (PIOA) PIO Output Disable Register */ -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) /* (PIOA) PIO Output Status Register */ -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */ -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */ -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */ -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) /* (PIOA) PIO Set Output Data Register */ -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */ -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) /* (PIOA) PIO Output Data Status Register */ -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */ -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */ -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */ -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */ -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */ -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */ -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */ -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */ -#define AT91C_PIOA_PUDR ((AT91_REG *) 0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */ -#define AT91C_PIOA_PUER ((AT91_REG *) 0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */ -#define AT91C_PIOA_PUSR ((AT91_REG *) 0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */ -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */ -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */ -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */ -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */ -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */ -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */ -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ - -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */ -#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */ -#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */ -#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */ -#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */ -#define AT91C_PA25_TWD ((unsigned int) 1 << 25) -#define AT91C_PA26_TWCK ((unsigned int) 1 << 26) -#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */ -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) /* Pin Controlled by PA17 */ -#define AT91C_PA17_TXD0 AT91C_PIO_PA17 /* USART0 Transmit Data */ -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) /* Pin Controlled by PA18 */ -#define AT91C_PA18_RXD0 AT91C_PIO_PA18 /* USART0 Receive Data */ -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) /* Pin Controlled by PB20 */ -#define AT91C_PB20_RXD1 AT91C_PIO_PB20 /* USART1 Receive Data */ -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) /* Pin Controlled by PB21 */ -#define AT91C_PB21_TXD1 AT91C_PIO_PB21 /* USART1 Transmit Data */ - -#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */ -#define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */ -#define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */ -#define AT91C_ID_PIOC ((unsigned int) 4) /* PIO port C */ -#define AT91C_ID_USART0 ((unsigned int) 6) /* USART 0 */ -#define AT91C_ID_USART1 ((unsigned int) 7) /* USART 1 */ -#define AT91C_ID_TWI ((unsigned int) 12) /* Two Wire Interface */ -#define AT91C_ID_SPI ((unsigned int) 13) /* Serial Peripheral Interface */ -#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */ -#define AT91C_ID_UHP ((unsigned int) 23) /* OHCI USB Host Port */ -#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */ - -#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */ -#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */ -#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */ -#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */ -#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */ -#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */ -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */ - -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */ -#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */ - -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) /* Pin Controlled by PA0 */ -#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) /* SPI Master In Slave */ -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) /* Pin Controlled by PA1 */ -#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) /* SPI Master Out Slave */ -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) /* Pin Controlled by PA2 */ -#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) /* SPI Serial Clock */ -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) /* Pin Controlled by PA3 */ -#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) /* SPI Peripheral Chip Select 0 */ -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) /* Pin Controlled by PA4 */ -#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) /* SPI Peripheral Chip Select 1 */ -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) /* Pin Controlled by PA5 */ -#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) /* SPI Peripheral Chip Select 2 */ -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */ -#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */ - -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */ -#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */ -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */ -#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */ -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */ -#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */ -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */ -#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */ -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */ -#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */ -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */ -#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */ -#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */ -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */ -#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */ -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */ -#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */ -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */ -#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */ - -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */ -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */ -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */ -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */ -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ -#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ -#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */ -#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */ -#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */ -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */ -#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */ -#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */ -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */ -#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */ -#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */ -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */ -#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */ -#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */ -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */ -#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */ -#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */ -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */ -#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */ -#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */ -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */ -#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */ -#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */ -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */ -#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */ -#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */ - -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */ -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ - -#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */ -#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ -#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ -#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ -#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */ -#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */ -#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ -#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */ - -#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */ -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */ -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */ -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */ -#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */ -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */ -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */ -#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */ -#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */ -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */ -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */ -#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */ -#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ -#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ -#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */ -#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ - -#endif diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h deleted file mode 100644 index a84c60a992..0000000000 --- a/include/asm-arm/arch-at91rm9200/hardware.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * linux/include/asm-arm/arch-at91/hardware.h - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <sizes.h> - -#ifndef __ASSEMBLY__ -#include "AT91RM9200.h" -#else -#include "AT91RM9200_inc.h" -#endif - -/* Virtual and Physical base address for system peripherals */ -#define AT91_SYS_BASE 0xFFFFF000 /*4K */ - -/* Virtual and Physical base addresses of user peripherals */ -#define AT91_SPI_BASE 0xFFFE0000 /*16K */ -#define AT91_SSC2_BASE 0xFFFD8000 /*16K */ -#define AT91_SSC1_BASE 0xFFFD4000 /*16K */ -#define AT91_SSC0_BASE 0xFFFD0000 /*16K */ -#define AT91_USART3_BASE 0xFFFCC000 /*16K */ -#define AT91_USART2_BASE 0xFFFC8000 /*16K */ -#define AT91_USART1_BASE 0xFFFC4000 /*16K */ -#define AT91_USART0_BASE 0xFFFC0000 /*16K */ -#define AT91_EMAC_BASE 0xFFFBC000 /*16K */ -#define AT91_TWI_BASE 0xFFFB8000 /*16K */ -#define AT91_MCI_BASE 0xFFFB4000 /*16K */ -#define AT91_UDP_BASE 0xFFFB0000 /*16K */ -#define AT91_TCB1_BASE 0xFFFA4000 /*16K */ -#define AT91_TCB0_BASE 0xFFFA0000 /*16K */ - -#define AT91_USB_HOST_BASE 0x00300000 -#define CFG_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE - -/* - * Where in virtual memory the IO devices (timers, system controllers - * and so on) - */ -#define AT91_IO_BASE 0xF0000000 /* Virt/Phys Address of IO */ - -/* FLASH */ -#define AT91_FLASH_BASE 0x10000000 /* NCS0 */ - -/* SDRAM */ -#define AT91_SDRAM_BASE 0x20000000 /* NCS1 */ - -/* SmartMedia */ -#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3 */ - -/* Definition of interrupt priority levels */ -#define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST -#define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1) -#define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2) -#define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3) -#define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4) -#define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5) -#define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6) -#define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGEST - -#endif diff --git a/include/asm-arm/arch-imx/clock-imx1.h b/include/asm-arm/arch-imx/clock-imx1.h deleted file mode 100644 index 8d456b84b2..0000000000 --- a/include/asm-arm/arch-imx/clock-imx1.h +++ /dev/null @@ -1,5 +0,0 @@ -#ifndef ASM_ARCH_CLOCK_IMX1_H -#define ASM_ARCH_CLOCK_IMX1_H - -#endif /* ASM_ARCH_CLOCK_IMX1_H */ - diff --git a/include/asm-arm/arch-imx/clock.h b/include/asm-arm/arch-imx/clock.h deleted file mode 100644 index c60417922b..0000000000 --- a/include/asm-arm/arch-imx/clock.h +++ /dev/null @@ -1,34 +0,0 @@ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H -unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); - -ulong imx_get_mpllclk(void); - -#ifdef CONFIG_ARCH_IMX27 -ulong imx_get_armclk(void); -#endif -#ifdef CONFIG_ARCH_IMX1 -static inline ulong imx_get_armclk(void) -{ - return imx_get_mpllclk(); -} -#endif - -ulong imx_get_spllclk(void); -ulong imx_get_fclk(void); -ulong imx_get_hclk(void); -ulong imx_get_bclk(void); -ulong imx_get_perclk1(void); -ulong imx_get_perclk2(void); -ulong imx_get_perclk3(void); -ulong imx_get_ahbclk(void); -ulong imx_get_fecclk(void); -ulong imx_get_gptclk(void); -ulong imx_get_uartclk(void); -ulong imx_get_lcdclk(void); - -int imx_clko_set_div(int div); -void imx_clko_set_src(int src); - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/include/asm-arm/arch-imx/esdctl.h b/include/asm-arm/arch-imx/esdctl.h deleted file mode 100644 index 7f3c66fc62..0000000000 --- a/include/asm-arm/arch-imx/esdctl.h +++ /dev/null @@ -1,34 +0,0 @@ - -/* SDRAM Controller registers */ -#define ESDCTL0 __REG(IMX_ESD_BASE + 0x00) /* Enhanced SDRAM Control Register 0 */ -#define ESDCFG0 __REG(IMX_ESD_BASE + 0x04) /* Enhanced SDRAM Configuration Register 0 */ -#define ESDCTL1 __REG(IMX_ESD_BASE + 0x08) /* Enhanced SDRAM Control Register 1 */ -#define ESDCFG1 __REG(IMX_ESD_BASE + 0x0C) /* Enhanced SDRAM Configuration Register 1 */ -#define ESDMISC __REG(IMX_ESD_BASE + 0x10) /* Enhanced SDRAM Miscellanious Register */ - -#define ESDCTL0_SDE (1 << 31) -#define ESDCTL0_SMODE_NORMAL (0 << 28) -#define ESDCTL0_SMODE_PRECHARGE (1 << 28) -#define ESDCTL0_SMODE_AUTO_REFRESH (2 << 28) -#define ESDCTL0_SMODE_LOAD_MODE (3 << 28) -#define ESDCTL0_SMODE_MANUAL_SELF_REFRESH (4 << 28) -#define ESDCTL0_SP (1 << 27) -#define ESDCTL0_ROW11 (0 << 24) -#define ESDCTL0_ROW12 (1 << 24) -#define ESDCTL0_ROW13 (2 << 24) -#define ESDCTL0_ROW14 (3 << 24) -#define ESDCTL0_ROW15 (4 << 24) -#define ESDCTL0_COL8 (0 << 20) -#define ESDCTL0_COL9 (1 << 20) -#define ESDCTL0_COL10 (2 << 20) -#define ESDCTL0_DSIZ_31_16 (0 << 16) -#define ESDCTL0_DSIZ_15_0 (1 << 16) -#define ESDCTL0_DSIZ_31_0 (2 << 16) -#define ESDCTL0_REF1 (1 << 13) -#define ESDCTL0_REF2 (2 << 13) -#define ESDCTL0_REF4 (3 << 13) -#define ESDCTL0_REF8 (4 << 13) -#define ESDCTL0_REF16 (5 << 13) -#define ESDCTL0_FP (1 << 8) -#define ESDCTL0_BL (1 << 7) - diff --git a/include/asm-arm/arch-imx/generic.h b/include/asm-arm/arch-imx/generic.h deleted file mode 100644 index 99a53a49a4..0000000000 --- a/include/asm-arm/arch-imx/generic.h +++ /dev/null @@ -1,41 +0,0 @@ - -int imx_silicon_revision(void); -#define IMX27_CHIP_REVISION_1_0 0 -#define IMX27_CHIP_REVISION_2_0 1 - -#ifdef CONFIG_ARCH_IMX1 -#define cpu_is_mx1() (1) -#else -#define cpu_is_mx1() (0) -#endif - -#ifdef CONFIG_ARCH_IMX21 -#define cpu_is_mx21() (1) -#else -#define cpu_is_mx21() (0) -#endif - -#ifdef CONFIG_ARCH_IMX25 -#define cpu_is_mx25() (1) -#else -#define cpu_is_mx25() (0) -#endif - -#ifdef CONFIG_ARCH_IMX27 -#define cpu_is_mx27() (1) -#else -#define cpu_is_mx27() (0) -#endif - -#ifdef CONFIG_ARCH_IMX31 -#define cpu_is_mx31() (1) -#else -#define cpu_is_mx31() (0) -#endif - -#ifdef CONFIG_ARCH_IMX35 -#define cpu_is_mx35() (1) -#else -#define cpu_is_mx35() (0) -#endif - diff --git a/include/asm-arm/arch-imx/gpio.h b/include/asm-arm/arch-imx/gpio.h deleted file mode 100644 index 71298f4e54..0000000000 --- a/include/asm-arm/arch-imx/gpio.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -void imx_gpio_mode(int gpio_mode); -void gpio_set_value(unsigned gpio, int value); -int gpio_direction_output(unsigned gpio, int value); -int gpio_direction_input(unsigned gpio); - -#endif /* __ASM_ARCH_GPIO_H */ - diff --git a/include/asm-arm/arch-imx/imx-nand.h b/include/asm-arm/arch-imx/imx-nand.h deleted file mode 100644 index 3fdd8bf342..0000000000 --- a/include/asm-arm/arch-imx/imx-nand.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef __ASM_ARCH_NAND_H -#define __ASM_ARCH_NAND_H - -#include <linux/mtd/mtd.h> - -void imx_nand_load_image(void *dest, int size); - -struct imx_nand_platform_data { - int width; - int hw_ecc:1; - int flash_bbt:1; -}; -#endif /* __ASM_ARCH_NAND_H */ - diff --git a/include/asm-arm/arch-imx/imx-pll.h b/include/asm-arm/arch-imx/imx-pll.h deleted file mode 100644 index df7e73efea..0000000000 --- a/include/asm-arm/arch-imx/imx-pll.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __INCLUDE_ASM_ARCH_IMX_PLL_H -#define __INCLUDE_ASM_ARCH_IMX_PLL_H - -/* - * This can be used for various PLLs found on - * i.MX SoCs. - * - * mfi + mfn / (mfd + 1) - * fpll = 2 * fref * --------------------- - * pd + 1 - */ -#define IMX_PLL_PD(x) (((x) & 0xf) << 26) -#define IMX_PLL_MFD(x) (((x) & 0x3ff) << 16) -#define IMX_PLL_MFI(x) (((x) & 0xf) << 10) -#define IMX_PLL_MFN(x) (((x) & 0x3ff) << 0) -#define IMX_PLL_BRMO (1 << 31) - -#endif /* __INCLUDE_ASM_ARCH_IMX_PLL_H*/ diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h deleted file mode 100644 index b7a83a4e25..0000000000 --- a/include/asm-arm/arch-imx/imx-regs.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _IMX_REGS_H -#define _IMX_REGS_H - -/* ------------------------------------------------------------------------ - * Motorola IMX system registers - * ------------------------------------------------------------------------ - */ - -# ifndef __ASSEMBLY__ -# define __REG(x) (*((volatile u32 *)(x))) -# define __REG16(x) (*(volatile u16 *)(x)) -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) -# else -# define __REG(x) (x) -# define __REG16(x) (x) -# define __REG2(x,y) ((x)+(y)) -#endif - -#ifdef CONFIG_ARCH_IMX1 -# include <asm/arch/imx1-regs.h> -#elif defined CONFIG_ARCH_IMX21 -# include <asm/arch/imx21-regs.h> -#elif defined CONFIG_ARCH_IMX27 -# include <asm/arch/imx27-regs.h> -#elif defined CONFIG_ARCH_IMX31 -# include <asm/arch/imx31-regs.h> -#elif defined CONFIG_ARCH_IMX35 -# include <asm/arch/imx35-regs.h> -#elif defined CONFIG_ARCH_IMX25 -# include <asm/arch/imx25-regs.h> -#else -# error "unknown i.MX soc type" -#endif - -/* - * GPIO Module and I/O Multiplexer - * x = 0..3 for reg_A, reg_B, reg_C, reg_D - * - * i.MX1 and i.MXL: 0 <= x <= 3 - * i.MX27 : 0 <= x <= 5 - */ -#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 7) << 8) -#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 7) << 8) -#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 7) << 8) -#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 7) << 8) -#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 7) << 8) -#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 7) << 8) -#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 7) << 8) -#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 7) << 8) -#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 7) << 8) -#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 7) << 8) -#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 7) << 8) -#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 7) << 8) -#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 7) << 8) -#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 7) << 8) -#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 7) << 8) -#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 7) << 8) -#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 7) << 8) - -#define GPIO_PIN_MASK 0x1f - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) - -#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) -#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) -#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) -#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) -#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) -#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) - -#define GPIO_OUT (1 << 8) -#define GPIO_IN (0 << 8) -#define GPIO_PUEN (1 << 9) - -#define GPIO_PF (1 << 10) -#define GPIO_AF (1 << 11) - -#define GPIO_OCR_SHIFT 12 -#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) -#define GPIO_AIN (0 << GPIO_OCR_SHIFT) -#define GPIO_BIN (1 << GPIO_OCR_SHIFT) -#define GPIO_CIN (2 << GPIO_OCR_SHIFT) -#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) - -#define GPIO_AOUT_SHIFT 14 -#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) - -#define GPIO_BOUT_SHIFT 16 -#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) - -#define GPIO_GIUS (1<<16) - -#endif /* _IMX_REGS_H */ diff --git a/include/asm-arm/arch-imx/imx1-regs.h b/include/asm-arm/arch-imx/imx1-regs.h deleted file mode 100644 index 0d6fd9200e..0000000000 --- a/include/asm-arm/arch-imx/imx1-regs.h +++ /dev/null @@ -1,241 +0,0 @@ -#ifndef _IMX1_REGS_H -#define _IMX1_REGS_H - -#ifndef _IMX_REGS_H -#error "Please do not include directly" -#endif - -#define IMX_IO_BASE 0x00200000 - -/* - * Register BASEs, based on OFFSETs - */ -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) -#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) -#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) -#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) -#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) -#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) -#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) -#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) -#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) -#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) -#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) -#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) -#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) -#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) -#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) -#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) -#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) -#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) -#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) -#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) -#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) -#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) -#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) -#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) - -/* Watchdog Registers*/ -#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ -#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */ -#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */ - -/* important definition of some bits of WCR */ -#define WCR_WDE 0x01 - -/* SYSCTRL Registers */ -#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */ -#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */ -#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */ - -/* SDRAM controller registers */ - -#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */ -#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */ -#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */ -#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */ - -/* PLL registers */ -#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ -#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ -#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ -#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ -#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ -#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ - -#define CSCR_MPLL_RESTART (1<<21) - -/* Chip Select Registers */ -#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */ -#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */ -#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */ -#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */ -#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */ -#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */ -#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */ -#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */ -#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */ -#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */ -#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */ -#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */ -#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */ - -/* assignements for GPIO alternate/primary functions */ - -/* FIXME: This list is not completed. The correct directions are - * missing on some (many) pins - */ -#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 ) -#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 ) -#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) -#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 ) -#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) -#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) -#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) -#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) -#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) -#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) -#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) -#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) -#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) -#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) -#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) -#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) -#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) -#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) -#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) -#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) -#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) -#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 ) -#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) -#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) -#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) -#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) -#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) -#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) -#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) -#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) -#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) -#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) -#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) -#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) -#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) -#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) -#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) -#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) -#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) -#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) -#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) -#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) -#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) -#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) -#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) -#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) -#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) -#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) -#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) -#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) -#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 ) -#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) -#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 ) -#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) -#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 ) -#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) -#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) -#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) -#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) -#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) -#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) -#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) -#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) -#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) -#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) -#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) -#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) -#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) -#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) -#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) -#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) -#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) -#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) -#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) -#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) -#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) -#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) -#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) -#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) -#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) -#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) -#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) -#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) -#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) -#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) -#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) -#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) -#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) -#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) -#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) -#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) -#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) -#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 ) -#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) -#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) -#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 ) -#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) -#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) -#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 ) -#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) -#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) -#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 ) -#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) -#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) -#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) -#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) -#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) -#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) -#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) -#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) -#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) -#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) -#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) -#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) -#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) -#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) -#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) -#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) -#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) -#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) -#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) -#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) -#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) -#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 ) - -/* - * Definitions for the clocksource driver - */ -/* Part 1: Registers */ -# define GPT_TCTL 0x00 -# define GPT_TPRER 0x04 -# define GPT_TCMP 0x08 -# define GPT_TCR 0x0c -# define GPT_TCN 0x10 -# define GPT_TSTAT 0x14 - -/* Part 2: Bitfields */ -#define TCTL_SWR (1<<15) /* Software reset */ -#define TCTL_FRR (1<<8) /* Freerun / restart */ -#define TCTL_CAP (3<<6) /* Capture Edge */ -#define TCTL_OM (1<<5) /* output mode */ -#define TCTL_IRQEN (1<<4) /* interrupt enable */ -#define TCTL_CLKSOURCE (1) /* Clock source bit position */ -#define TCTL_TEN (1) /* Timer enable */ -#define TPRER_PRES (0xff) /* Prescale */ -#define TSTAT_CAPT (1<<1) /* Capture event */ -#define TSTAT_COMP (1) /* Compare event */ - -#endif /* _IMX1_REGS_H */ diff --git a/include/asm-arm/arch-imx/imx21-regs.h b/include/asm-arm/arch-imx/imx21-regs.h deleted file mode 100644 index b8cb06075f..0000000000 --- a/include/asm-arm/arch-imx/imx21-regs.h +++ /dev/null @@ -1,150 +0,0 @@ -#ifndef _IMX21_REGS_H -#define _IMX21_REGS_H - -#ifndef _IMX_REGS_H -#error "Please do not include directly" -#endif - -#define IMX_IO_BASE 0x10000000 - -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) -#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) -#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) -#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) -#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) -#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) -#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) -#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) - -#define IMX_SDRAM_BASE (0xdf000000) -#define IMX_EIM_BASE (0xdf001000) -#define IMX_NFC_BASE (0xdf003000) - -/* AIPI */ -#define AIPI1_PSR0 __REG(IMX_AIPI1_BASE + 0x00) -#define AIPI1_PSR1 __REG(IMX_AIPI1_BASE + 0x04) -#define AIPI2_PSR0 __REG(IMX_AIPI2_BASE + 0x00) -#define AIPI2_PSR1 __REG(IMX_AIPI2_BASE + 0x04) - -/* System Control */ -#define SUID0 __REG(IMX_SYSTEM_CTL_BASE + 0x4) /* Silicon ID Register (12 bytes) */ -#define SUID1 __REG(IMX_SYSTEM_CTL_BASE + 0x8) /* Silicon ID Register (12 bytes) */ -#define CID __REG(IMX_SYSTEM_CTL_BASE + 0xC) /* Silicon ID Register (12 bytes) */ -#define FMCR __REG(IMX_SYSTEM_CTL_BASE + 0x14) /* Function Multeplexing Control Register */ -#define GPCR __REG(IMX_SYSTEM_CTL_BASE + 0x18) /* Global Peripheral Control Register */ -#define WBCR __REG(IMX_SYSTEM_CTL_BASE + 0x1C) /* Well Bias Control Register */ -#define DSCR(x) __REG(IMX_SYSTEM_CTL_BASE + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ - -#define GPCR_BOOT_SHIFT 16 -#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT) -#define GPCR_BOOT_UART_USB 0 -#define GPCR_BOOT_8BIT_NAND_2k 2 -#define GPCR_BOOT_16BIT_NAND_2k 3 -#define GPCR_BOOT_16BIT_NAND_512 4 -#define GPCR_BOOT_16BIT_CS0 5 -#define GPCR_BOOT_32BIT_CS0 6 -#define GPCR_BOOT_8BIT_NAND_512 7 - -/* SDRAM Controller registers bitfields */ -#define SDCTL0 __REG(IMX_SDRAM_BASE + 0x00) /* SDRAM 0 Control Register */ -#define SDCTL1 __REG(IMX_SDRAM_BASE + 0x04) /* SDRAM 0 Control Register */ -#define SDRST __REG(IMX_SDRAM_BASE + 0x18) /* SDRAM Reset Register */ -#define SDMISC __REG(IMX_SDRAM_BASE + 0x14) /* SDRAM Miscellaneous Register */ - - -/* Chip Select Registers */ -#define CS0U __REG(IMX_EIM_BASE + 0x00) /* Chip Select 0 Upper Register */ -#define CS0L __REG(IMX_EIM_BASE + 0x04) /* Chip Select 0 Lower Register */ -#define CS1U __REG(IMX_EIM_BASE + 0x08) /* Chip Select 1 Upper Register */ -#define CS1L __REG(IMX_EIM_BASE + 0x0C) /* Chip Select 1 Lower Register */ -#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */ -#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */ -#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */ -#define CS3L __REG(IMX_EIM_BASE + 0x1C) /* Chip Select 3 Lower Register */ -#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */ -#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */ -#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */ -#define CS5L __REG(IMX_EIM_BASE + 0x2C) /* Chip Select 5 Lower Register */ -#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */ - -/* Watchdog Registers*/ -#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ -#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ -#define WRSR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Reset Status Register */ - -/* important definition of some bits of WCR */ -#define WCR_WDE 0x04 - -/* PLL registers */ -#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */ -#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */ -#define MPCTL1 __REG(IMX_PLL_BASE + 0x08) /* MCU PLL Control Register 1 */ -#define SPCTL0 __REG(IMX_PLL_BASE + 0x0c) /* System PLL Control Register 0 */ -#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ -#define OSC26MCTL __REG(IMX_PLL_BASE + 0x14) /* Oscillator 26M Register */ -#define PCDR0 __REG(IMX_PLL_BASE + 0x18) /* Peripheral Clock Divider Register 0 */ -#define PCDR1 __REG(IMX_PLL_BASE + 0x1c) /* Peripheral Clock Divider Register 1 */ -#define PCCR0 __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Control Register 0 */ -#define PCCR1 __REG(IMX_PLL_BASE + 0x24) /* Peripheral Clock Control Register 1 */ -#define CCSR __REG(IMX_PLL_BASE + 0x28) /* Clock Control Status Register */ - -#define CSCR_MPEN (1 << 0) -#define CSCR_SPEN (1 << 1) -#define CSCR_FPM_EN (1 << 2) -#define CSCR_OSC26M_DIS (1 << 3) -#define CSCR_OSC26M_DIV1P5 (1 << 4) -#define CSCR_MCU_SEL (1 << 16) -#define CSCR_SP_SEL (1 << 17) -#define CSCR_SD_CNT(d) (((d) & 0x3) << 24) -#define CSCR_USB_DIV(d) (((d) & 0x7) << 26) -#define CSCR_PRESC(d) (((d) & 0x7) << 29) - -#define MPCTL1_BRMO (1 << 6) -#define MPCTL1_LF (1 << 15) - -#define PCCR1_GPT1_EN (1 << 25) - -#define CCSR_32K_SR (1 << 15) - -#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) -#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) -#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) -#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) - -/* - * Definitions for the clocksource driver - */ -/* Part 1: Registers */ -# define GPT_TCTL 0x00 -# define GPT_TPRER 0x04 -# define GPT_TCMP 0x08 -# define GPT_TCR 0x0c -# define GPT_TCN 0x10 -# define GPT_TSTAT 0x14 - -/* Part 2: Bitfields */ -#define TCTL_SWR (1<<15) /* Software reset */ -#define TCTL_CC (1<<10) /* counter clear */ -#define TCTL_FRR (1<<8) /* Freerun / restart */ -#define TCTL_CAP (3<<6) /* Capture Edge */ -#define TCTL_CAPEN (1<<5) /* compare interrupt enable */ -#define TCTL_COMPEN (1<<4) /* compare interrupt enable */ -#define TCTL_CLKSOURCE (1) /* Clock source bit position */ -#define TCTL_TEN (1) /* Timer enable */ -#define TPRER_PRES (0xff) /* Prescale */ -#define TSTAT_CAPT (1<<1) /* Capture event */ -#define TSTAT_COMP (1) /* Compare event */ - -#define IMX_CS0_BASE 0xC8000000 -#define IMX_CS1_BASE 0xCC000000 -#define IMX_CS2_BASE 0xD0000000 -#define IMX_CS3_BASE 0xD1000000 -#define IMX_CS4_BASE 0xD2000000 -#define IMX_CS5_BASE 0xD3000000 - -#endif /* _IMX21_REGS_H */ diff --git a/include/asm-arm/arch-imx/imx25-flash-header.h b/include/asm-arm/arch-imx/imx25-flash-header.h deleted file mode 100644 index 59860dbda7..0000000000 --- a/include/asm-arm/arch-imx/imx25-flash-header.h +++ /dev/null @@ -1,44 +0,0 @@ - -#define __flash_header_start __section(.flash_header_start) -#define __flash_header __section(.flash_header) -#define __dcd_entry __section(.dcd_entry) -#define __image_len __section(.image_len) - -struct mx25_dcd_entry { - unsigned long ptr_type; - unsigned long addr; - unsigned long val; -}; - -#define DCD_BARKER 0xb17219e9 - -struct mx25_dcd_header { - unsigned long barker; - unsigned long block_len; -}; - -struct mx25_rsa_public_key { - unsigned char rsa_exponent[4]; - unsigned char *rsa_modululs; - unsigned short *exponent_size; - unsigned short modulus_size; - unsigned char init_flag; -}; - -#define APP_CODE_BARKER 0x000000b1 - -struct mx25_flash_header { - void *app_code_jump_vector; - unsigned long app_code_barker; - void *app_code_csf; - struct mx25_dcd_header **dcd_ptr_ptr; - struct mx25_rsa_public_key *super_root_key; - struct mx25_dcd_header *dcd; - void *app_dest; -}; - -struct mx25_nand_flash_header { - struct mx25_flash_header flash_header; - struct mx25_dcd_header dcd_header; -}; - diff --git a/include/asm-arm/arch-imx/imx25-regs.h b/include/asm-arm/arch-imx/imx25-regs.h deleted file mode 100644 index 001b5157e1..0000000000 --- a/include/asm-arm/arch-imx/imx25-regs.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MX25_REGS_H -#define __ASM_ARCH_MX35_REGS_H - -/* - * sanity check - */ -#ifndef _IMX_REGS_H -# error "Please do not include directly. Use imx-regs.h instead." -#endif - -#define IMX_L2CC_BASE 0x30000000 -#define IMX_UART1_BASE 0x43F90000 -#define IMX_UART2_BASE 0x43F94000 -#define IMX_TIM1_BASE 0x53F90000 -#define IMX_IOMUXC_BASE 0x43FAC000 -#define IMX_WDT_BASE 0x53FDC000 -#define IMX_MAX_BASE 0x43F04000 -#define IMX_ESD_BASE 0xb8001000 -#define IMX_AIPS1_BASE 0x43F00000 -#define IMX_AIPS2_BASE 0x53F00000 -#define IMX_CCM_BASE 0x53F80000 -#define IMX_IIM_BASE 0x53FF0000 -#define IMX_OTG_BASE 0x53FF4000 -#define IMX_M3IF_BASE 0xB8003000 -#define IMX_NFC_BASE 0xBB000000 - -/* - * Clock Controller Module (CCM) - */ -#define CCM_MPCTL 0x00 -#define CCM_UPCTL 0x04 -#define CCM_CCTL 0x08 -#define CCM_CGCR0 0x0C -#define CCM_CGCR1 0x10 -#define CCM_CGCR2 0x14 -#define CCM_PCDR0 0x18 -#define CCM_PCDR1 0x1C -#define CCM_PCDR2 0x20 -#define CCM_PCDR3 0x24 -#define CCM_RCSR 0x28 -#define CCM_CRDR 0x2C -#define CCM_DCVR0 0x30 -#define CCM_DCVR1 0x34 -#define CCM_DCVR2 0x38 -#define CCM_DCVR3 0x3c -#define CCM_LTR0 0x40 -#define CCM_LTR1 0x44 -#define CCM_LTR2 0x48 -#define CCM_LTR3 0x4c - -#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) -#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) -#define PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16) -#define PDR0_HSP_PODF(x) (((x) & 0x3) << 20) -#define PDR0_AUTO_CON (1 << 0) -#define PDR0_PER_SEL (1 << 26) - -/* - * Adresses and ranges of the external chip select lines - */ -#define IMX_CS0_BASE 0xA0000000 -#define IMX_CS0_RANGE (128 * 1024 * 1024) -#define IMX_CS1_BASE 0xA8000000 -#define IMX_CS1_RANGE (128 * 1024 * 1024) -#define IMX_CS2_BASE 0xB0000000 -#define IMX_CS2_RANGE (32 * 1024 * 1024) -#define IMX_CS3_BASE 0xB2000000 -#define IMX_CS3_RANGE (32 * 1024 * 1024) -#define IMX_CS4_BASE 0xB4000000 -#define IMX_CS4_RANGE (32 * 1024 * 1024) -#define IMX_CS5_BASE 0xB6000000 -#define IMX_CS5_RANGE (32 * 1024 * 1024) - -#define IMX_SDRAM_CS0 0x80000000 -#define IMX_SDRAM_CS1 0x90000000 - -#define WEIM_BASE 0xb8002000 -#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) -#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) -#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) - -/* - * Definitions for the clocksource driver - * - * These defines are using the i.MX1/27 notation - * to reuse the clocksource code for these CPUs - * on the i.MX35 - */ -/* Part 1: Registers */ -#define GPT_TCTL 0x00 -#define GPT_TPRER 0x04 -#define GPT_TCMP 0x10 -#define GPT_TCR 0x1c -#define GPT_TCN 0x24 -#define GPT_TSTAT 0x08 - -/* Part 2: Bitfields */ -#define TCTL_SWR (1<<15) /* Software reset */ -#define TCTL_FRR (1<<9) /* Freerun / restart */ -#define TCTL_CAP (3<<6) /* Capture Edge */ -#define TCTL_OM (1<<5) /* output mode */ -#define TCTL_IRQEN (1<<4) /* interrupt enable */ -#define TCTL_CLKSOURCE (6) /* Clock source bit position */ -#define TCTL_TEN (1) /* Timer enable */ -#define TPRER_PRES (0xff) /* Prescale */ -#define TSTAT_CAPT (1<<1) /* Capture event */ -#define TSTAT_COMP (1) /* Compare event */ - -/* - * Watchdog Registers - */ -#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ -#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ -#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */ - -/* important definition of some bits of WCR */ -#define WCR_WDE 0x04 - -#endif /* __ASM_ARCH_MX25_REGS_H */ - diff --git a/include/asm-arm/arch-imx/imx27-regs.h b/include/asm-arm/arch-imx/imx27-regs.h deleted file mode 100644 index 33d67d6f50..0000000000 --- a/include/asm-arm/arch-imx/imx27-regs.h +++ /dev/null @@ -1,354 +0,0 @@ -#ifndef _IMX27_REGS_H -#define _IMX27_REGS_H - -#ifndef _IMX_REGS_H -#error "Please do not include directly" -#endif - -#define IMX_IO_BASE 0x10000000 - -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) -#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) -#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) -#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) -#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) -#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) -#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) -#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) -#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) -#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) -#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) -#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) -#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) -#define IMX_OTG_BASE (0x24000 + IMX_IO_BASE) - -#define IMX_NFC_BASE (0xd8000000) -#define IMX_ESD_BASE (0xd8001000) -#define IMX_WEIM_BASE (0xd8002000) - -/* AIPI */ -#define AIPI1_PSR0 __REG(IMX_AIPI1_BASE + 0x00) -#define AIPI1_PSR1 __REG(IMX_AIPI1_BASE + 0x04) -#define AIPI2_PSR0 __REG(IMX_AIPI2_BASE + 0x00) -#define AIPI2_PSR1 __REG(IMX_AIPI2_BASE + 0x04) - -/* System Control */ -#define CID __REG(IMX_SYSTEM_CTL_BASE + 0x0) /* Chip ID Register */ -#define FMCR __REG(IMX_SYSTEM_CTL_BASE + 0x14) /* Function Multeplexing Control Register */ -#define GPCR __REG(IMX_SYSTEM_CTL_BASE + 0x18) /* Global Peripheral Control Register */ -#define WBCR __REG(IMX_SYSTEM_CTL_BASE + 0x1C) /* Well Bias Control Register */ -#define DSCR(x) __REG(IMX_SYSTEM_CTL_BASE + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ - -#define GPCR_BOOT_SHIFT 16 -#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT) -#define GPCR_BOOT_UART_USB 0 -#define GPCR_BOOT_8BIT_NAND_2k 2 -#define GPCR_BOOT_16BIT_NAND_2k 3 -#define GPCR_BOOT_16BIT_NAND_512 4 -#define GPCR_BOOT_16BIT_CS0 5 -#define GPCR_BOOT_32BIT_CS0 6 -#define GPCR_BOOT_8BIT_NAND_512 7 - -/* Chip Select Registers */ -#define CS0U __REG(IMX_WEIM_BASE + 0x00) /* Chip Select 0 Upper Register */ -#define CS0L __REG(IMX_WEIM_BASE + 0x04) /* Chip Select 0 Lower Register */ -#define CS0A __REG(IMX_WEIM_BASE + 0x08) /* Chip Select 0 Addition Register */ -#define CS1U __REG(IMX_WEIM_BASE + 0x10) /* Chip Select 1 Upper Register */ -#define CS1L __REG(IMX_WEIM_BASE + 0x14) /* Chip Select 1 Lower Register */ -#define CS1A __REG(IMX_WEIM_BASE + 0x18) /* Chip Select 1 Addition Register */ -#define CS2U __REG(IMX_WEIM_BASE + 0x20) /* Chip Select 2 Upper Register */ -#define CS2L __REG(IMX_WEIM_BASE + 0x24) /* Chip Select 2 Lower Register */ -#define CS2A __REG(IMX_WEIM_BASE + 0x28) /* Chip Select 2 Addition Register */ -#define CS3U __REG(IMX_WEIM_BASE + 0x30) /* Chip Select 3 Upper Register */ -#define CS3L __REG(IMX_WEIM_BASE + 0x34) /* Chip Select 3 Lower Register */ -#define CS3A __REG(IMX_WEIM_BASE + 0x38) /* Chip Select 3 Addition Register */ -#define CS4U __REG(IMX_WEIM_BASE + 0x40) /* Chip Select 4 Upper Register */ -#define CS4L __REG(IMX_WEIM_BASE + 0x44) /* Chip Select 4 Lower Register */ -#define CS4A __REG(IMX_WEIM_BASE + 0x48) /* Chip Select 4 Addition Register */ -#define CS5U __REG(IMX_WEIM_BASE + 0x50) /* Chip Select 5 Upper Register */ -#define CS5L __REG(IMX_WEIM_BASE + 0x54) /* Chip Select 5 Lower Register */ -#define CS5A __REG(IMX_WEIM_BASE + 0x58) /* Chip Select 5 Addition Register */ -#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */ - -#include "esdctl.h" - -/* Watchdog Registers*/ -#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ -#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */ -#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */ - -/* important definition of some bits of WCR */ -#define WCR_WDE 0x04 - -/* PLL registers */ -#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */ -#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */ -#define MPCTL1 __REG(IMX_PLL_BASE + 0x08) /* MCU PLL Control Register 1 */ -#define SPCTL0 __REG(IMX_PLL_BASE + 0x0c) /* System PLL Control Register 0 */ -#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ -#define OSC26MCTL __REG(IMX_PLL_BASE + 0x14) /* Oscillator 26M Register */ -#define PCDR0 __REG(IMX_PLL_BASE + 0x18) /* Peripheral Clock Divider Register 0 */ -#define PCDR1 __REG(IMX_PLL_BASE + 0x1c) /* Peripheral Clock Divider Register 1 */ -#define PCCR0 __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Control Register 0 */ -#define PCCR1 __REG(IMX_PLL_BASE + 0x24) /* Peripheral Clock Control Register 1 */ -#define CCSR __REG(IMX_PLL_BASE + 0x28) /* Clock Control Status Register */ - -#define CSCR_MPEN (1 << 0) -#define CSCR_SPEN (1 << 1) -#define CSCR_FPM_EN (1 << 2) -#define CSCR_OSC26M_DIS (1 << 3) -#define CSCR_OSC26M_DIV1P5 (1 << 4) -#define CSCR_AHB_DIV(d) (((d) & 0x3) << 8) -#define CSCR_ARM_DIV(d) (((d) & 0x3) << 12) -#define CSCR_ARM_SRC_MPLL (1 << 15) -#define CSCR_MCU_SEL (1 << 16) -#define CSCR_SP_SEL (1 << 17) -#define CSCR_MPLL_RESTART (1 << 18) -#define CSCR_SPLL_RESTART (1 << 19) -#define CSCR_MSHC_SEL (1 << 20) -#define CSCR_H264_SEL (1 << 21) -#define CSCR_SSI1_SEL (1 << 22) -#define CSCR_SSI2_SEL (1 << 23) -#define CSCR_SD_CNT(d) (((d) & 0x3) << 24) -#define CSCR_USB_DIV(d) (((d) & 0x7) << 28) -#define CSCR_UPDATE_DIS (1 << 31) - -#define MPCTL1_BRMO (1 << 6) -#define MPCTL1_LF (1 << 15) - -#define PCCR0_SSI2_EN (1 << 0) -#define PCCR0_SSI1_EN (1 << 1) -#define PCCR0_SLCDC_EN (1 << 2) -#define PCCR0_SDHC3_EN (1 << 3) -#define PCCR0_SDHC2_EN (1 << 4) -#define PCCR0_SDHC1_EN (1 << 5) -#define PCCR0_SDC_EN (1 << 6) -#define PCCR0_SAHARA_EN (1 << 7) -#define PCCR0_RTIC_EN (1 << 8) -#define PCCR0_RTC_EN (1 << 9) -#define PCCR0_PWM_EN (1 << 11) -#define PCCR0_OWIRE_EN (1 << 12) -#define PCCR0_MSHC_EN (1 << 13) -#define PCCR0_LCDC_EN (1 << 14) -#define PCCR0_KPP_EN (1 << 15) -#define PCCR0_IIM_EN (1 << 16) -#define PCCR0_I2C2_EN (1 << 17) -#define PCCR0_I2C1_EN (1 << 18) -#define PCCR0_GPT6_EN (1 << 19) -#define PCCR0_GPT5_EN (1 << 20) -#define PCCR0_GPT4_EN (1 << 21) -#define PCCR0_GPT3_EN (1 << 22) -#define PCCR0_GPT2_EN (1 << 23) -#define PCCR0_GPT1_EN (1 << 24) -#define PCCR0_GPIO_EN (1 << 25) -#define PCCR0_FEC_EN (1 << 26) -#define PCCR0_EMMA_EN (1 << 27) -#define PCCR0_DMA_EN (1 << 28) -#define PCCR0_CSPI3_EN (1 << 29) -#define PCCR0_CSPI2_EN (1 << 30) -#define PCCR0_CSPI1_EN (1 << 31) - -#define PCCR1_MSHC_BAUDEN (1 << 2) -#define PCCR1_NFC_BAUDEN (1 << 3) -#define PCCR1_SSI2_BAUDEN (1 << 4) -#define PCCR1_SSI1_BAUDEN (1 << 5) -#define PCCR1_H264_BAUDEN (1 << 6) -#define PCCR1_PERCLK4_EN (1 << 7) -#define PCCR1_PERCLK3_EN (1 << 8) -#define PCCR1_PERCLK2_EN (1 << 9) -#define PCCR1_PERCLK1_EN (1 << 10) -#define PCCR1_HCLK_USB (1 << 11) -#define PCCR1_HCLK_SLCDC (1 << 12) -#define PCCR1_HCLK_SAHARA (1 << 13) -#define PCCR1_HCLK_RTIC (1 << 14) -#define PCCR1_HCLK_LCDC (1 << 15) -#define PCCR1_HCLK_H264 (1 << 16) -#define PCCR1_HCLK_FEC (1 << 17) -#define PCCR1_HCLK_EMMA (1 << 18) -#define PCCR1_HCLK_EMI (1 << 19) -#define PCCR1_HCLK_DMA (1 << 20) -#define PCCR1_HCLK_CSI (1 << 21) -#define PCCR1_HCLK_BROM (1 << 22) -#define PCCR1_HCLK_ATA (1 << 23) -#define PCCR1_WDT_EN (1 << 24) -#define PCCR1_USB_EN (1 << 25) -#define PCCR1_UART6_EN (1 << 26) -#define PCCR1_UART5_EN (1 << 27) -#define PCCR1_UART4_EN (1 << 28) -#define PCCR1_UART3_EN (1 << 29) -#define PCCR1_UART2_EN (1 << 30) -#define PCCR1_UART1_EN (1 << 31) - -#define CCSR_32K_SR (1 << 15) - -/* SDRAM Controller registers bitfields */ -#define ESDCTL_PRCT(x) (((x) & 3f) << 0) -#define ESDCTL_BL (1 << 7) -#define ESDCTL_FP (1 << 8) -#define ESDCTL_PWDT(x) (((x) & 3) << 10) -#define ESDCTL_SREFR(x) (((x) & 7) << 13) -#define ESDCTL_DSIZ_16_UPPER (0 << 16) -#define ESDCTL_DSIZ_16_LOWER (0 << 16) -#define ESDCTL_DSIZ_32 (0 << 16) -#define ESDCTL_COL8 (0 << 20) -#define ESDCTL_COL9 (1 << 20) -#define ESDCTL_COL10 (2 << 20) -#define ESDCTL_ROW11 (0 << 24) -#define ESDCTL_ROW12 (1 << 24) -#define ESDCTL_ROW13 (2 << 24) -#define ESDCTL_ROW14 (3 << 24) -#define ESDCTL_ROW15 (4 << 24) -#define ESDCTL_SP (1 << 27) -#define ESDCTL_SMODE_NORMAL (0 << 28) -#define ESDCTL_SMODE_PRECHAGRE (1 << 28) -#define ESDCTL_SMODE_AUTO_REF (2 << 28) -#define ESDCTL_SMODE_LOAD_MODE (3 << 28) -#define ESDCTL_SMODE_MAN_REF (4 << 28) -#define ESDCTL_SDE (1 << 31) - -#define ESDCFG_TRC(x) (((x) & 0xf) << 0) -#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) -#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) -#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) -#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) -#define ESDCFG_TWR (1 << 15) -#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) -#define ESDCFG_TRP(x) (((x) & 0x3) << 18) -#define ESDCFG_TWTR (1 << 20) -#define ESDCFG_TXP(x) (((x) & 0x3) << 21) - -#define ESDMISC_RST (1 << 1) -#define ESDMISC_MDDREN (1 << 2) -#define ESDMISC_MDDR_DL_RST (1 << 3) -#define ESDMISC_MDDR_MDIS (1 << 4) -#define ESDMISC_LHD (1 << 5) -#define ESDMISC_MA10_SHARE (1 << 6) -#define ESDMISC_SDRAM_RDY (1 << 6) - -#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) -#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) -#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) -#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) -#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) -#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) -#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) -#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) -#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) -#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) -#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) -#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) -#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) -#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) -#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) -#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) -#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) -#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) -#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) -#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) -#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) -#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) -#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) -#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) -#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) -#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) -#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) -#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) -#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) -#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) -#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) -#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) -#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) -#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) -#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) -#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) -#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) -#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) -#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) -#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) -#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) -#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) -#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) -#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) -#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) -#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) -#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) -#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) -#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) -#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) -#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) -#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) -#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) -#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) -#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) -#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) -#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) -#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25) -#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26) -#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) -#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27) -#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28) -#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29) -#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30) -#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31) -#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) -#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) -#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) -#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) -#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) -#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) -#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) -#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) -#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) -#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) -#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) -#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) -#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) -#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) -#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) -#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) -#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) -#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) -#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) -#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) -#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) -#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) -#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) -#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) -#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) - -/* - * Definitions for the clocksource driver - */ -/* Part 1: Registers */ -# define GPT_TCTL 0x00 -# define GPT_TPRER 0x04 -# define GPT_TCMP 0x08 -# define GPT_TCR 0x0c -# define GPT_TCN 0x10 -# define GPT_TSTAT 0x14 - -/* Part 2: Bitfields */ -#define TCTL_SWR (1<<15) /* Software reset */ -#define TCTL_FRR (1<<8) /* Freerun / restart */ -#define TCTL_CAP (3<<6) /* Capture Edge */ -#define TCTL_OM (1<<5) /* output mode */ -#define TCTL_IRQEN (1<<4) /* interrupt enable */ -#define TCTL_CLKSOURCE (1) /* Clock source bit position */ -#define TCTL_TEN (1) /* Timer enable */ -#define TPRER_PRES (0xff) /* Prescale */ -#define TSTAT_CAPT (1<<1) /* Capture event */ -#define TSTAT_COMP (1) /* Compare event */ - -#define IMX_CS0_BASE 0xC0000000 -#define IMX_CS1_BASE 0xC8000000 -#define IMX_CS2_BASE 0xD0000000 -#define IMX_CS3_BASE 0xD2000000 -#define IMX_CS4_BASE 0xD4000000 -#define IMX_CS5_BASE 0xD6000000 - -#endif /* _IMX27_REGS_H */ diff --git a/include/asm-arm/arch-imx/imx31-regs.h b/include/asm-arm/arch-imx/imx31-regs.h deleted file mode 100644 index 3cae3a21db..0000000000 --- a/include/asm-arm/arch-imx/imx31-regs.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MX31_REGS_H -#define __ASM_ARCH_MX31_REGS_H - -/* - * sanity check - */ -#ifndef _IMX_REGS_H -# error "Please do not include directly. Use imx-regs.h instead." -#endif - -#define IMX_OTG_BASE 0x43F88000 -#define IMX_UART1_BASE 0x43F90000 -#define IMX_UART2_BASE 0x43F94000 -#define IMX_WDT_BASE 0x53FDC000 -#define IMX_RTC_BASE 0x53FD8000 -#define IMX_TIM1_BASE 0x53F90000 -#define IMX_IIM_BASE 0x5001C000 - -#define IMX_SDRAM_CS0 0x80000000 -#define IMX_SDRAM_CS1 0x90000000 - -/* - * Adresses and ranges of the external chip select lines - */ -#define IMX_CS0_BASE 0xA0000000 -#define IMX_CS0_RANGE (128 * 1024 * 1024) -#define IMX_CS1_BASE 0xA8000000 -#define IMX_CS1_RANGE (128 * 1024 * 1024) -#define IMX_CS2_BASE 0xB0000000 -#define IMX_CS2_RANGE (32 * 1024 * 1024) -#define IMX_CS3_BASE 0xB2000000 -#define IMX_CS3_RANGE (32 * 1024 * 1024) -#define IMX_CS4_BASE 0xB4000000 -#define IMX_CS4_RANGE (32 * 1024 * 1024) -#define IMX_CS5_BASE 0xB6000000 -#define IMX_CS5_RANGE (32 * 1024 * 1024) - -/* - * Definitions for the clocksource driver - * - * These defines are using the i.MX1/27 notation - * to reuse the clocksource code for these CPUs - * on the i.MX31 - */ -/* Part 1: Registers */ -#define GPT_TCTL 0x00 -#define GPT_TPRER 0x04 -#define GPT_TCMP 0x10 -#define GPT_TCR 0x1c -#define GPT_TCN 0x24 -#define GPT_TSTAT 0x08 - -/* Part 2: Bitfields */ -#define TCTL_SWR (1<<15) /* Software reset */ -#define TCTL_FRR (1<<9) /* Freerun / restart */ -#define TCTL_CAP (3<<6) /* Capture Edge */ -#define TCTL_OM (1<<5) /* output mode */ -#define TCTL_IRQEN (1<<4) /* interrupt enable */ -#define TCTL_CLKSOURCE (6) /* Clock source bit position */ -#define TCTL_TEN (1) /* Timer enable */ -#define TPRER_PRES (0xff) /* Prescale */ -#define TSTAT_CAPT (1<<1) /* Capture event */ -#define TSTAT_COMP (1) /* Compare event */ - -#if 0 -#define IMX_IO_BASE 0x00200000 - -/* - * Register BASEs, based on OFFSETs - */ -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define (0x01000 + IMX_IO_BASE) - (0x02000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) - (0x04000 + IMX_IO_BASE) -#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) -#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) -#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) -#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) -#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) -#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) -#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) -#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) -#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) -#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) -#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) -#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) -#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) -#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) -#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) -#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) -#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) -#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) -#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) -#endif - -/* - * Watchdog Registers - */ -#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ -#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ -#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */ - -/* important definition of some bits of WCR */ -#define WCR_WDE 0x04 - -/* - * Clock Controller Module (CCM) - */ -#define IMX_CCM_BASE 0x53f80000 -#define CCM_CCMR 0x00 -#define CCM_PDR0 0x04 -#define CCM_PDR1 0x08 -#define CCM_RCSR 0x0c -#define CCM_MPCTL 0x10 -#define CCM_UPCTL 0x10 -#define CCM_SPCTL 0x18 -#define CCM_COSR 0x1C - -/* - * ????????????? - */ -#define CCMR_MDS (1 << 7) -#define CCMR_SBYCS (1 << 4) -#define CCMR_MPE (1 << 3) -#define CCMR_PRCS_MASK (3 << 1) -#define CCMR_FPM (1 << 1) -#define CCMR_CKIH (2 << 1) - -#define RCSR_NFMS (1 << 30) - -/* - * ????????????? - */ -#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) -#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) -#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) -#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) -#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6) -#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) -#define PDR0_MCU_PODF(x) ((x) & 0x7) - -#define IMX_ESD_BASE 0xb8001000 -#include "esdctl.h" - -/* - * NFC Registers - */ -#define IMX_NFC_BASE (0xb8000000) - -/* - * Chip Select Registers - */ -#define WEIM_BASE 0xb8002000 -#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) -#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) -#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) - -/* - * ??????????? - */ -#define IOMUXC_BASE 0x43FAC000 -#define IOMUXC_GPR (IOMUXC_BASE + 0x8) -#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) -#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) - -#define IPU_BASE 0x53fc0000 -#define IPU_CONF IPU_BASE - -#define IPU_CONF_PXL_ENDIAN (1<<8) -#define IPU_CONF_DU_EN (1<<7) -#define IPU_CONF_DI_EN (1<<6) -#define IPU_CONF_ADC_EN (1<<5) -#define IPU_CONF_SDC_EN (1<<4) -#define IPU_CONF_PF_EN (1<<3) -#define IPU_CONF_ROT_EN (1<<2) -#define IPU_CONF_IC_EN (1<<1) -#define IPU_CONF_SCI_EN (1<<0) - -#define WDOG_BASE 0x53FDC000 - -/* - * Signal Multiplexing (IOMUX) - */ - -/* bits in the SW_MUX_CTL registers */ -#define MUX_CTL_OUT_GPIO_DR (0 << 4) -#define MUX_CTL_OUT_FUNC (1 << 4) -#define MUX_CTL_OUT_ALT1 (2 << 4) -#define MUX_CTL_OUT_ALT2 (3 << 4) -#define MUX_CTL_OUT_ALT3 (4 << 4) -#define MUX_CTL_OUT_ALT4 (5 << 4) -#define MUX_CTL_OUT_ALT5 (6 << 4) -#define MUX_CTL_OUT_ALT6 (7 << 4) -#define MUX_CTL_IN_NONE (0 << 0) -#define MUX_CTL_IN_GPIO (1 << 0) -#define MUX_CTL_IN_FUNC (2 << 0) -#define MUX_CTL_IN_ALT1 (4 << 0) -#define MUX_CTL_IN_ALT2 (8 << 0) - -#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC) -#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1) -#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2) -#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO) - -/* Register offsets based on IOMUXC_BASE */ -/* 0x00 .. 0x7b */ -#define MUX_CTL_RTS1 0x7c -#define MUX_CTL_CTS1 0x7d -#define MUX_CTL_DTR_DCE1 0x7e -#define MUX_CTL_DSR_DCE1 0x7f -#define MUX_CTL_CSPI2_SCLK 0x80 -#define MUX_CTL_CSPI2_SPI_RDY 0x81 -#define MUX_CTL_RXD1 0x82 -#define MUX_CTL_TXD1 0x83 -#define MUX_CTL_CSPI2_MISO 0x84 -/* 0x85 .. 0x8a */ -#define MUX_CTL_CSPI2_MOSI 0x8b - -/* The modes a specific pin can be in - * these macros can be used in mx31_gpio_mux() and have the form - * MUX_[contact name]__[pin function] - */ -#define MUX_RXD1_UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1) -#define MUX_TXD1_UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1) -#define MUX_RTS1_UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1) -#define MUX_RTS1_UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1) - -#define MUX_CSPI2_MOSI_I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI) -#define MUX_CSPI2_MISO_I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO) - -#endif /* __ASM_ARCH_MX31_REGS_H */ - diff --git a/include/asm-arm/arch-imx/imx35-regs.h b/include/asm-arm/arch-imx/imx35-regs.h deleted file mode 100644 index a9b363868d..0000000000 --- a/include/asm-arm/arch-imx/imx35-regs.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MX35_REGS_H -#define __ASM_ARCH_MX35_REGS_H - -/* - * sanity check - */ -#ifndef _IMX_REGS_H -# error "Please do not include directly. Use imx-regs.h instead." -#endif - -#define IMX_L2CC_BASE 0x30000000 -#define IMX_UART1_BASE 0x43F90000 -#define IMX_UART2_BASE 0x43F94000 -#define IMX_TIM1_BASE 0x53F90000 -#define IMX_IOMUXC_BASE 0x43FAC000 -#define IMX_WDT_BASE 0x53FDC000 -#define IMX_MAX_BASE 0x43F04000 -#define IMX_ESD_BASE 0xb8001000 -#define IMX_AIPS1_BASE 0x43F00000 -#define IMX_AIPS2_BASE 0x53F00000 -#define IMX_CCM_BASE 0x53F80000 -#define IMX_IIM_BASE 0x53FF0000 -#define IMX_M3IF_BASE 0xB8003000 -#define IMX_NFC_BASE 0xBB000000 - -/* - * Clock Controller Module (CCM) - */ -#define CCM_CCMR 0x00 -#define CCM_PDR0 0x04 -#define CCM_PDR1 0x08 -#define CCM_PDR2 0x0C -#define CCM_PDR3 0x10 -#define CCM_PDR4 0x14 -#define CCM_RCSR 0x18 -#define CCM_MPCTL 0x1C -#define CCM_PPCTL 0x20 -#define CCM_ACMR 0x24 -#define CCM_COSR 0x28 -#define CCM_CGR0 0x2C -#define CCM_CGR1 0x30 -#define CCM_CGR2 0x34 -#define CCM_CGR3 0x38 - -#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) -#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) -#define PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16) -#define PDR0_HSP_PODF(x) (((x) & 0x3) << 20) -#define PDR0_AUTO_CON (1 << 0) -#define PDR0_PER_SEL (1 << 26) - -/* - * Adresses and ranges of the external chip select lines - */ -#define IMX_CS0_BASE 0xA0000000 -#define IMX_CS0_RANGE (128 * 1024 * 1024) -#define IMX_CS1_BASE 0xA8000000 -#define IMX_CS1_RANGE (128 * 1024 * 1024) -#define IMX_CS2_BASE 0xB0000000 -#define IMX_CS2_RANGE (32 * 1024 * 1024) -#define IMX_CS3_BASE 0xB2000000 -#define IMX_CS3_RANGE (32 * 1024 * 1024) -#define IMX_CS4_BASE 0xB4000000 -#define IMX_CS4_RANGE (32 * 1024 * 1024) -#define IMX_CS5_BASE 0xB6000000 -#define IMX_CS5_RANGE (32 * 1024 * 1024) - -#define IMX_SDRAM_CS0 0x80000000 -#define IMX_SDRAM_CS1 0x90000000 - -#define WEIM_BASE 0xb8002000 -#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) -#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) -#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) - -/* - * Definitions for the clocksource driver - * - * These defines are using the i.MX1/27 notation - * to reuse the clocksource code for these CPUs - * on the i.MX35 - */ -/* Part 1: Registers */ -#define GPT_TCTL 0x00 -#define GPT_TPRER 0x04 -#define GPT_TCMP 0x10 -#define GPT_TCR 0x1c -#define GPT_TCN 0x24 -#define GPT_TSTAT 0x08 - -/* Part 2: Bitfields */ -#define TCTL_SWR (1<<15) /* Software reset */ -#define TCTL_FRR (1<<9) /* Freerun / restart */ -#define TCTL_CAP (3<<6) /* Capture Edge */ -#define TCTL_OM (1<<5) /* output mode */ -#define TCTL_IRQEN (1<<4) /* interrupt enable */ -#define TCTL_CLKSOURCE (6) /* Clock source bit position */ -#define TCTL_TEN (1) /* Timer enable */ -#define TPRER_PRES (0xff) /* Prescale */ -#define TSTAT_CAPT (1<<1) /* Capture event */ -#define TSTAT_COMP (1) /* Compare event */ - -/* - * Watchdog Registers - */ -#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ -#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ -#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */ - -/* important definition of some bits of WCR */ -#define WCR_WDE 0x04 - -#endif /* __ASM_ARCH_MX35_REGS_H */ - diff --git a/include/asm-arm/arch-imx/imxfb.h b/include/asm-arm/arch-imx/imxfb.h deleted file mode 100644 index ca7ea32fb4..0000000000 --- a/include/asm-arm/arch-imx/imxfb.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This structure describes the machine which we are running on. - */ - -#include <fb.h> - -#define PCR_TFT (1 << 31) -#define PCR_COLOR (1 << 30) -#define PCR_PBSIZ_1 (0 << 28) -#define PCR_PBSIZ_2 (1 << 28) -#define PCR_PBSIZ_4 (2 << 28) -#define PCR_PBSIZ_8 (3 << 28) -#define PCR_BPIX_1 (0 << 25) -#define PCR_BPIX_2 (1 << 25) -#define PCR_BPIX_4 (2 << 25) -#define PCR_BPIX_8 (3 << 25) -#define PCR_BPIX_12 (4 << 25) -#define PCR_BPIX_16 (5 << 25) -#define PCR_BPIX_18 (6 << 25) -#define PCR_PIXPOL (1 << 24) -#define PCR_FLMPOL (1 << 23) -#define PCR_LPPOL (1 << 22) -#define PCR_CLKPOL (1 << 21) -#define PCR_OEPOL (1 << 20) -#define PCR_SCLKIDLE (1 << 19) -#define PCR_END_SEL (1 << 18) -#define PCR_END_BYTE_SWAP (1 << 17) -#define PCR_REV_VS (1 << 16) -#define PCR_ACD_SEL (1 << 15) -#define PCR_ACD(x) (((x) & 0x7f) << 8) -#define PCR_SCLK_SEL (1 << 7) -#define PCR_SHARP (1 << 6) -#define PCR_PCD(x) ((x) & 0x3f) - -#define PWMR_CLS(x) (((x) & 0x1ff) << 16) -#define PWMR_LDMSK (1 << 15) -#define PWMR_SCR1 (1 << 10) -#define PWMR_SCR0 (1 << 9) -#define PWMR_CC_EN (1 << 8) -#define PWMR_PW(x) ((x) & 0xff) - -#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) -#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) -#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) -#define LSCR1_GRAY2(x) (((x) & 0xf) << 4) -#define LSCR1_GRAY1(x) (((x) & 0xf)) - -#define DMACR_BURST (1 << 31) -#define DMACR_HM(x) (((x) & 0xf) << 16) -#define DMACR_TM(x) ((x) & 0xf) - -struct imx_fb_videomode { - struct fb_videomode mode; - u32 pcr; - unsigned char bpp; -}; - -struct imx_fb_platform_data { - struct imx_fb_videomode *mode; - - u_int cmap_greyscale:1, - cmap_inverse:1, - cmap_static:1, - unused:29; - - u_int pwmr; - u_int lscr1; - u_int dmacr; - - void *framebuffer; - void *framebuffer_ovl; -}; - -void set_imx_fb_info(struct imx_fb_platform_data *); - diff --git a/include/asm-arm/arch-imx/iomux-mx25.h b/include/asm-arm/arch-imx/iomux-mx25.h deleted file mode 100644 index aaacc3e722..0000000000 --- a/include/asm-arm/arch-imx/iomux-mx25.h +++ /dev/null @@ -1,773 +0,0 @@ -#ifndef __MACH_IOMUX_MX25_H__ -#define __MACH_IOMUX_MX25_H__ - -#include <asm/arch/iomux-v3.h> - -#define SRE (1 << 0) -#define DSE_STD (0 << 1) -#define DSE_HIGH (1 << 1) -#define DSE_MAX (2 << 1) -#define ODE (1 << 3) -#define PUS_100K_DOWN (0 << 4) -#define PUS_47K_UP (1 << 4) -#define PUS_100K_UP (2 << 4) -#define PUS_22K_UP (3 << 4) -#define PUE (1 << 6) -#define PKE (1 << 7) -#define HYS (1 << 8) -#define DVS (1 << 13) - -#define MX25_PAD_A10__EIM_DA_H10 IOMUX_PAD(0x000, 0x8, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A10__GPIO0 IOMUX_PAD(0x000, 0x8, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A13__EIM_DA_H13 IOMUX_PAD(0x22c, 0xc, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A13__GPIO1 IOMUX_PAD(0x22c, 0xc, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A13__LCDC_CLS IOMUX_PAD(0x22c, 0xc, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A14__EIM_DA_H214 IOMUX_PAD(0x230, 0x10, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A14__GPIO0 IOMUX_PAD(0x230, 0x10, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A14__CLK1 IOMUX_PAD(0x230, 0x10, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A14__LCDC_SPL IOMUX_PAD(0x230, 0x10, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A15__EIM_DA_H215 IOMUX_PAD(0x234, 0x14, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A15__GPIO1 IOMUX_PAD(0x234, 0x14, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A15__RST1 IOMUX_PAD(0x234, 0x14, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A15__LCDC_PS IOMUX_PAD(0x234, 0x14, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A16__EIM_A16 IOMUX_PAD(0x000, 0x18, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A16__GPIO2 IOMUX_PAD(0x000, 0x18, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A16__VEN1 IOMUX_PAD(0x000, 0x18, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A16__LCDC_REV IOMUX_PAD(0x000, 0x18, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A17__EIM_A17 IOMUX_PAD(0x238, 0x1c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A17__GPIO3 IOMUX_PAD(0x238, 0x1c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A17__TX1 IOMUX_PAD(0x238, 0x1c, 6, 0x554, 0, NO_PAD_CTRL) -#define MX25_PAD_A17__TX_ERR IOMUX_PAD(0x238, 0x1c, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A18__EIM_A18 IOMUX_PAD(0x23c, 0x20, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A18__GPIO4 IOMUX_PAD(0x23c, 0x20, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A18__PD1 IOMUX_PAD(0x23c, 0x20, 6, 0x550, 0, NO_PAD_CTRL) -#define MX25_PAD_A18__COL IOMUX_PAD(0x23c, 0x20, 7, 0x504, 0, NO_PAD_CTRL) -#define MX25_PAD_A19__EIM_A19 IOMUX_PAD(0x240, 0x24, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A19__GPIO5 IOMUX_PAD(0x240, 0x24, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A19__RX1 IOMUX_PAD(0x240, 0x24, 6, 0x54c, 0, NO_PAD_CTRL) -#define MX25_PAD_A19__RX_ERR IOMUX_PAD(0x240, 0x24, 7, 0x518, 0, NO_PAD_CTRL) -#define MX25_PAD_A20__EIM_A20 IOMUX_PAD(0x244, 0x28, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A20__GPIO6 IOMUX_PAD(0x244, 0x28, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A20__CLK1 IOMUX_PAD(0x244, 0x28, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A20__RDATA2 IOMUX_PAD(0x244, 0x28, 7, 0x50c, 0, NO_PAD_CTRL) -#define MX25_PAD_A21__EIM_A21 IOMUX_PAD(0x248, 0x2c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A21__GPIO7 IOMUX_PAD(0x248, 0x2c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A21__RST1 IOMUX_PAD(0x248, 0x2c, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A21__RDATA3 IOMUX_PAD(0x248, 0x2c, 7, 0x510, 0, NO_PAD_CTRL) -#define MX25_PAD_A22__EIM_A22 IOMUX_PAD(0x000, 0x30, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A22__GPIO8 IOMUX_PAD(0x000, 0x30, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A22__VEN1 IOMUX_PAD(0x000, 0x30, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A22__TDATA2 IOMUX_PAD(0x000, 0x30, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A23__EIM_A23 IOMUX_PAD(0x24c, 0x34, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A23__GPIO9 IOMUX_PAD(0x24c, 0x34, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A23__TX1 IOMUX_PAD(0x24c, 0x34, 6, 0x560, 0, NO_PAD_CTRL) -#define MX25_PAD_A23__TDATA3 IOMUX_PAD(0x24c, 0x34, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A24__EIM_A24 IOMUX_PAD(0x250, 0x38, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A24__GPIO10 IOMUX_PAD(0x250, 0x38, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A24__PD1 IOMUX_PAD(0x250, 0x38, 6, 0x55c, 0, NO_PAD_CTRL) -#define MX25_PAD_A24__RX_CLK IOMUX_PAD(0x250, 0x38, 7, 0x514, 0, NO_PAD_CTRL) -#define MX25_PAD_A25__EIM_A25 IOMUX_PAD(0x254, 0x3c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A25__GPIO11 IOMUX_PAD(0x254, 0x3c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A25__RX1 IOMUX_PAD(0x254, 0x3c, 6, 0x558, 0, NO_PAD_CTRL) -#define MX25_PAD_A25__CRS IOMUX_PAD(0x254, 0x3c, 7, 0x508, 0, NO_PAD_CTRL) -#define MX25_PAD_BCLK__EIM_BCLK IOMUX_PAD(0x000, 0x68, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_BCLK__GPIO4 IOMUX_PAD(0x000, 0x68, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_BOOT_MODE0__GPIO30 IOMUX_PAD(0x000, 0x224, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_BOOT_MODE1__GPIO31 IOMUX_PAD(0x000, 0x228, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CLKO__CLKO IOMUX_PAD(0x414, 0x220, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CLKO__GPIO21 IOMUX_PAD(0x414, 0x220, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CONTRAST__LCDC_CONTRAST IOMUX_PAD(0x310, 0x118, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CONTRAST__CAPIN1 IOMUX_PAD(0x310, 0x118, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CONTRAST__SS1 IOMUX_PAD(0x310, 0x118, 2, 0x4a8, 0, NO_PAD_CTRL) -#define MX25_PAD_CONTRAST__DA_2 IOMUX_PAD(0x310, 0x118, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CONTRAST__PWMO IOMUX_PAD(0x310, 0x118, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CONTRAST__CRS IOMUX_PAD(0x310, 0x118, 5, 0x508, 1, NO_PAD_CTRL) -#define MX25_PAD_CONTRAST__USBH2_PWR IOMUX_PAD(0x310, 0x118, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CONTRAST__WDOG_B IOMUX_PAD(0x310, 0x118, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS0__EIM_CS0 IOMUX_PAD(0x000, 0x4c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS0__GPIO2 IOMUX_PAD(0x000, 0x4c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS1__EIM_CS1 IOMUX_PAD(0x000, 0x50, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS1__NANDF_CE3 IOMUX_PAD(0x000, 0x50, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS1__GPIO3 IOMUX_PAD(0x000, 0x50, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS4__EIM_CS4 IOMUX_PAD(0x264, 0x54, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS4__NANDF_CE1 IOMUX_PAD(0x264, 0x54, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS4__CTS IOMUX_PAD(0x264, 0x54, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS4__AUD4_RXC IOMUX_PAD(0x264, 0x54, 4, 0x468, 0, NO_PAD_CTRL) -#define MX25_PAD_CS4__GPIO20 IOMUX_PAD(0x264, 0x54, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS4__MOSI IOMUX_PAD(0x264, 0x54, 6, 0x4b8, 0, NO_PAD_CTRL) -#define MX25_PAD_CS4__TRSYNC IOMUX_PAD(0x264, 0x54, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS5__EIM_CS5 IOMUX_PAD(0x268, 0x58, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS5__NANDF_CE2 IOMUX_PAD(0x268, 0x58, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS5__DTACK_B IOMUX_PAD(0x268, 0x58, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS5__RTS IOMUX_PAD(0x268, 0x58, 3, 0x574, 0, NO_PAD_CTRL) -#define MX25_PAD_CS5__AUD4_RXFS IOMUX_PAD(0x268, 0x58, 4, 0x46c, 0, NO_PAD_CTRL) -#define MX25_PAD_CS5__GPIO21 IOMUX_PAD(0x268, 0x58, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS5__MISO IOMUX_PAD(0x268, 0x58, 6, 0x4b4, 0, NO_PAD_CTRL) -#define MX25_PAD_CS5__TRCLK IOMUX_PAD(0x268, 0x58, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D2__CSI_D2 IOMUX_PAD(0x318, 0x120, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D2__RXD_MUX IOMUX_PAD(0x318, 0x120, 1, 0x578, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D2__DAT4 IOMUX_PAD(0x318, 0x120, 2, 0x4f4, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D2__SCKR IOMUX_PAD(0x318, 0x120, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D2__CLK0 IOMUX_PAD(0x318, 0x120, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D2__GPIO27 IOMUX_PAD(0x318, 0x120, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D2__MOSI IOMUX_PAD(0x318, 0x120, 7, 0x4b8, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D2__USBOTG_DATA0 IOMUX_PAD(0x318, 0x120, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D3__CSI_D3 IOMUX_PAD(0x31c, 0x124, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D3__TXD_MUX IOMUX_PAD(0x31c, 0x124, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D3__DAT5 IOMUX_PAD(0x31c, 0x124, 2, 0x4f8, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D3__FSR IOMUX_PAD(0x31c, 0x124, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D3__RST0 IOMUX_PAD(0x31c, 0x124, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D3__GPIO28 IOMUX_PAD(0x31c, 0x124, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D3__MISO IOMUX_PAD(0x31c, 0x124, 7, 0x4b4, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D3__USBOTG_DATA1 IOMUX_PAD(0x31c, 0x124, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D4__CSI_D4 IOMUX_PAD(0x320, 0x128, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D4__RTS IOMUX_PAD(0x320, 0x128, 1, 0x574, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D4__DAT6 IOMUX_PAD(0x320, 0x128, 2, 0x4fc, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D4__HCKR IOMUX_PAD(0x320, 0x128, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D4__VEN0 IOMUX_PAD(0x320, 0x128, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D4__GPIO29 IOMUX_PAD(0x320, 0x128, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D4__USBOTG_DATA2 IOMUX_PAD(0x320, 0x128, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D4__SCLK IOMUX_PAD(0x320, 0x128, 7, 0x4ac, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D5__CSI_D5 IOMUX_PAD(0x324, 0x12c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D5__CTS IOMUX_PAD(0x324, 0x12c, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D5__DAT7 IOMUX_PAD(0x324, 0x12c, 2, 0x500, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D5__SCKT IOMUX_PAD(0x324, 0x12c, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D5__TX0 IOMUX_PAD(0x324, 0x12c, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D5__GPIO30 IOMUX_PAD(0x324, 0x12c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D5__USBOTG_DATA3 IOMUX_PAD(0x324, 0x12c, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D5__RDY IOMUX_PAD(0x324, 0x12c, 7, 0x4b0, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D6__CSI_D6 IOMUX_PAD(0x328, 0x130, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D6__ROW6 IOMUX_PAD(0x328, 0x130, 1, 0x544, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D6__CMD IOMUX_PAD(0x328, 0x130, 2, 0x4e0, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D6__FST IOMUX_PAD(0x328, 0x130, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D6__PD0 IOMUX_PAD(0x328, 0x130, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D6__GPIO31 IOMUX_PAD(0x328, 0x130, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D6__USBOTG_DATA4 IOMUX_PAD(0x328, 0x130, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D6__SS0 IOMUX_PAD(0x328, 0x130, 7, 0x4bc, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D7__CSI_D7 IOMUX_PAD(0x32c, 0x134, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D7__ROW7 IOMUX_PAD(0x32c, 0x134, 1, 0x548, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D7__CLK IOMUX_PAD(0x32c, 0x134, 2, 0x4dc, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D7__HCKT IOMUX_PAD(0x32c, 0x134, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D7__RX0 IOMUX_PAD(0x32c, 0x134, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D7__GPIO6 IOMUX_PAD(0x32c, 0x134, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D7__USBOTG_DATA5 IOMUX_PAD(0x32c, 0x134, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D7__SS1 IOMUX_PAD(0x32c, 0x134, 7, 0x4c0, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D8__CSI_D8 IOMUX_PAD(0x330, 0x138, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D8__COL6 IOMUX_PAD(0x330, 0x138, 1, 0x534, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D8__AUD6_RXC IOMUX_PAD(0x330, 0x138, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D8__TX5_RX0 IOMUX_PAD(0x330, 0x138, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D8__CLK0 IOMUX_PAD(0x330, 0x138, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D8__GPIO7 IOMUX_PAD(0x330, 0x138, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D8__USBOTG_DATA6 IOMUX_PAD(0x330, 0x138, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D8__SS2 IOMUX_PAD(0x330, 0x138, 7, 0x4c4, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D9__CSI_D9 IOMUX_PAD(0x334, 0x13c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D9__COL7 IOMUX_PAD(0x334, 0x13c, 1, 0x538, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D9__AUD6_RXFS IOMUX_PAD(0x334, 0x13c, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D9__TX4_RX1 IOMUX_PAD(0x334, 0x13c, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D9__RST0 IOMUX_PAD(0x334, 0x13c, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D9__GPIO21 IOMUX_PAD(0x334, 0x13c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D9__USBOTG_DATA7 IOMUX_PAD(0x334, 0x13c, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D9__SS3 IOMUX_PAD(0x334, 0x13c, 7, 0x4c8, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_HSYNC__CSI_HSYNC IOMUX_PAD(0x340, 0x148, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_HSYNC__AUD6_TXC IOMUX_PAD(0x340, 0x148, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_HSYNC__DAT2 IOMUX_PAD(0x340, 0x148, 2, 0x4ec, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_HSYNC__TX1 IOMUX_PAD(0x340, 0x148, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_HSYNC__PD0 IOMUX_PAD(0x340, 0x148, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_HSYNC__GPIO10 IOMUX_PAD(0x340, 0x148, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_HSYNC__USBOTG_NXT IOMUX_PAD(0x340, 0x148, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_HSYNC__BT_RES2 IOMUX_PAD(0x340, 0x148, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_MCLK__CSI_MCLK IOMUX_PAD(0x338, 0x140, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_MCLK__AUD6_TXD IOMUX_PAD(0x338, 0x140, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_MCLK__DAT0 IOMUX_PAD(0x338, 0x140, 2, 0x4e4, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_MCLK__TX3_RX2 IOMUX_PAD(0x338, 0x140, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_MCLK__VEN0 IOMUX_PAD(0x338, 0x140, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_MCLK__GPIO8 IOMUX_PAD(0x338, 0x140, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_MCLK__USBOTG_DIR IOMUX_PAD(0x338, 0x140, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_MCLK__BT_RES0 IOMUX_PAD(0x338, 0x140, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS IOMUX_PAD(0x344, 0x14c, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_PIXCLK__DAT3 IOMUX_PAD(0x344, 0x14c, 2, 0x4f0, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_PIXCLK__TX0 IOMUX_PAD(0x344, 0x14c, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_PIXCLK__RX0 IOMUX_PAD(0x344, 0x14c, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_PIXCLK__GPIO11 IOMUX_PAD(0x344, 0x14c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_PIXCLK__USBOTG_CLK IOMUX_PAD(0x344, 0x14c, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_PIXCLK__BT_RES3 IOMUX_PAD(0x344, 0x14c, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_VSYNC__CSI_VSYNC IOMUX_PAD(0x33c, 0x144, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_VSYNC__AUD6_RXD IOMUX_PAD(0x33c, 0x144, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_VSYNC__DAT1 IOMUX_PAD(0x33c, 0x144, 2, 0x4e8, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_VSYNC__TX2_RX3 IOMUX_PAD(0x33c, 0x144, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_VSYNC__TX0 IOMUX_PAD(0x33c, 0x144, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_VSYNC__GPIO9 IOMUX_PAD(0x33c, 0x144, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_VSYNC__USBOTG_STP IOMUX_PAD(0x33c, 0x144, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_VSYNC__BT_RES1 IOMUX_PAD(0x33c, 0x144, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MISO__MISO IOMUX_PAD(0x354, 0x15c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MISO__TXD_MUX IOMUX_PAD(0x354, 0x15c, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MISO__SDMA_DBG_EVT_1 IOMUX_PAD(0x354, 0x15c, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MISO__GPIO15 IOMUX_PAD(0x354, 0x15c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MISO__SLCDC_DATA13 IOMUX_PAD(0x354, 0x15c, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MISO__TRACE5 IOMUX_PAD(0x354, 0x15c, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MOSI__MOSI IOMUX_PAD(0x350, 0x158, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MOSI__RXD_MUX IOMUX_PAD(0x350, 0x158, 2, 0x568, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MOSI__SDMA_DBG_EVT_0 IOMUX_PAD(0x350, 0x158, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MOSI__GPIO14 IOMUX_PAD(0x350, 0x158, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MOSI__SLCDC_DATA12 IOMUX_PAD(0x350, 0x158, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MOSI__TRACE4 IOMUX_PAD(0x350, 0x158, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_RDY__RDY IOMUX_PAD(0x364, 0x16c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_RDY__SDMA_DBG_EVT_5 IOMUX_PAD(0x364, 0x16c, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_RDY__GPIO22 IOMUX_PAD(0x364, 0x16c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_RDY__SLCDC_DATA15 IOMUX_PAD(0x364, 0x16c, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_RDY__TRACE9 IOMUX_PAD(0x364, 0x16c, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SCLK__SCLK IOMUX_PAD(0x360, 0x168, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SCLK__CTS IOMUX_PAD(0x360, 0x168, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SCLK__SDMA_DBG_EVT_4 IOMUX_PAD(0x360, 0x168, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SCLK__GPIO18 IOMUX_PAD(0x360, 0x168, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SCLK__SLCDC_DATA14 IOMUX_PAD(0x360, 0x168, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SCLK__TRACE8 IOMUX_PAD(0x360, 0x168, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS0__SS0 IOMUX_PAD(0x358, 0x160, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS0__LCDC_LD16 IOMUX_PAD(0x358, 0x160, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS0__PWMO IOMUX_PAD(0x358, 0x160, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS0__SDMA_DBG_EVT_2 IOMUX_PAD(0x358, 0x160, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS0__GPIO16 IOMUX_PAD(0x358, 0x160, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS0__SLCDC_CS IOMUX_PAD(0x358, 0x160, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS0__TRACE6 IOMUX_PAD(0x358, 0x160, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS1__SS1 IOMUX_PAD(0x35c, 0x164, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS1__SDA IOMUX_PAD(0x35c, 0x164, 1, 0x528, 1, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS1__RTS IOMUX_PAD(0x35c, 0x164, 2, 0x564, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS1__SDMA_DBG_EVT_3 IOMUX_PAD(0x35c, 0x164, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS1__GPIO17 IOMUX_PAD(0x35c, 0x164, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS1__SLCDC_RS IOMUX_PAD(0x35c, 0x164, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS1__TRACE7 IOMUX_PAD(0x35c, 0x164, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D0__EIM_D0 IOMUX_PAD(0x2bc, 0xc4, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D0__GPIO20 IOMUX_PAD(0x2bc, 0xc4, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D10__EIM_D10 IOMUX_PAD(0x294, 0x9c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D10__LCDC_LD21 IOMUX_PAD(0x294, 0x9c, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D10__GPIO10 IOMUX_PAD(0x294, 0x9c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D10__USBOTG_OC IOMUX_PAD(0x294, 0x9c, 6, 0x57c, 0, NO_PAD_CTRL) -#define MX25_PAD_D11__EIM_D11 IOMUX_PAD(0x290, 0x98, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D11__LCDC_LD20 IOMUX_PAD(0x290, 0x98, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D11__GPIO9 IOMUX_PAD(0x290, 0x98, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D11__USBOTG_PWR IOMUX_PAD(0x290, 0x98, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D12__EIM_D12 IOMUX_PAD(0x28c, 0x94, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D12__GPIO8 IOMUX_PAD(0x28c, 0x94, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D12__DAT4 IOMUX_PAD(0x28c, 0x94, 6, 0x4cc, 0, NO_PAD_CTRL) -#define MX25_PAD_D12__LCDC_LD19 IOMUX_PAD(0x28c, 0x94, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D13__EIM_D13 IOMUX_PAD(0x288, 0x90, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D13__LCDC_LD18 IOMUX_PAD(0x288, 0x90, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D13__GPIO7 IOMUX_PAD(0x288, 0x90, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D13__DAT5 IOMUX_PAD(0x288, 0x90, 6, 0x4d0, 0, NO_PAD_CTRL) -#define MX25_PAD_D14__EIM_D14 IOMUX_PAD(0x284, 0x8c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D14__LCDC_LD17 IOMUX_PAD(0x284, 0x8c, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D14__GPIO6 IOMUX_PAD(0x284, 0x8c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D14__DAT6 IOMUX_PAD(0x284, 0x8c, 6, 0x4d4, 0, NO_PAD_CTRL) -#define MX25_PAD_D15__EIM_D15 IOMUX_PAD(0x280, 0x88, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D15__LCDC_LD16 IOMUX_PAD(0x280, 0x88, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D15__GPIO5 IOMUX_PAD(0x280, 0x88, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D15__DAT7 IOMUX_PAD(0x280, 0x88, 6, 0x4d8, 0, NO_PAD_CTRL) -#define MX25_PAD_D1__EIM_D1 IOMUX_PAD(0x2b8, 0xc0, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D1__GPIO19 IOMUX_PAD(0x2b8, 0xc0, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D2__EIM_D2 IOMUX_PAD(0x2b4, 0xbc, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D2__GPIO18 IOMUX_PAD(0x2b4, 0xbc, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D3__EIM_D3 IOMUX_PAD(0x2b0, 0xb8, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D3__GPIO17 IOMUX_PAD(0x2b0, 0xb8, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D4__EIM_D4 IOMUX_PAD(0x2ac, 0xb4, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D4__GPIO16 IOMUX_PAD(0x2ac, 0xb4, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D5__EIM_D5 IOMUX_PAD(0x2a8, 0xb0, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D5__GPIO15 IOMUX_PAD(0x2a8, 0xb0, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D6__EIM_D6 IOMUX_PAD(0x2a4, 0xac, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D6__GPIO14 IOMUX_PAD(0x2a4, 0xac, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D7__EIM_D7 IOMUX_PAD(0x2a0, 0xa8, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D7__GPIO13 IOMUX_PAD(0x2a0, 0xa8, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D8__EIM_D8 IOMUX_PAD(0x29c, 0xa4, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D8__LCDC_LD23 IOMUX_PAD(0x29c, 0xa4, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D8__GPIO12 IOMUX_PAD(0x29c, 0xa4, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D8__USBH2_OC IOMUX_PAD(0x29c, 0xa4, 6, 0x580, 0, 0x1c0) -#define MX25_PAD_D9__EIM_D9 IOMUX_PAD(0x298, 0xa0, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D9__LCDC_LD22 IOMUX_PAD(0x298, 0xa0, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D9__GPIO11 IOMUX_PAD(0x298, 0xa0, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D9__USBH2_PWR IOMUX_PAD(0x298, 0xa0, 6, 0, 0, 0x60) -#define MX25_PAD_DE_B__DE_B IOMUX_PAD(0x3ec, 0x1f0, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_DE_B__GPIO20 IOMUX_PAD(0x3ec, 0x1f0, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_EB0__EIM_EB0_B IOMUX_PAD(0x258, 0x40, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x40, 4, 0x464, 0, NO_PAD_CTRL) -#define MX25_PAD_EB0__GPIO12 IOMUX_PAD(0x258, 0x40, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_EB0__SS0 IOMUX_PAD(0x258, 0x40, 6, 0x4bc, 0, NO_PAD_CTRL) -#define MX25_PAD_EB1__EIM_EB1_B IOMUX_PAD(0x25c, 0x44, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_EB1__AUD4_RXD IOMUX_PAD(0x25c, 0x44, 4, 0x460, 0, NO_PAD_CTRL) -#define MX25_PAD_EB1__GPIO13 IOMUX_PAD(0x25c, 0x44, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_EB1__SS1 IOMUX_PAD(0x25c, 0x44, 6, 0x4c0, 0, NO_PAD_CTRL) -#define MX25_PAD_ECB__EIM_ECB IOMUX_PAD(0x270, 0x60, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_ECB__TXD_MUX IOMUX_PAD(0x270, 0x60, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_ECB__GPIO23 IOMUX_PAD(0x270, 0x60, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_ECB__SCLK IOMUX_PAD(0x270, 0x60, 6, 0x4ac, 0, NO_PAD_CTRL) -#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_EXT_ARMCLK__GPIO15 IOMUX_PAD(0x000, 0x20c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDC__MDC IOMUX_PAD(0x3c0, 0x1c8, 0, 0, 0, PUE) -#define MX25_PAD_FEC_MDC__CMD IOMUX_PAD(0x3c0, 0x1c8, 1, 0x4e0, 2, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 2, 0x464, 1, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDC__DIOR IOMUX_PAD(0x3c0, 0x1c8, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDC__GPIO5 IOMUX_PAD(0x3c0, 0x1c8, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDC__SDMA_DBG_PC_8 IOMUX_PAD(0x3c0, 0x1c8, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDC__LCDC_LD16 IOMUX_PAD(0x3c0, 0x1c8, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDIO__MDIO IOMUX_PAD(0x3c4, 0x1cc, 0, 0, 0, (HYS | PKE | PUE | PUS_22K_UP)) -#define MX25_PAD_FEC_MDIO__CLK IOMUX_PAD(0x3c4, 0x1cc, 1, 0x4dc, 2, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 2, 0x460, 1, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDIO__DIOW IOMUX_PAD(0x3c4, 0x1cc, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDIO__GPIO6 IOMUX_PAD(0x3c4, 0x1cc, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDIO__SDMA_DBG_PC_9 IOMUX_PAD(0x3c4, 0x1cc, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDIO__LCDC_LD17 IOMUX_PAD(0x3c4, 0x1cc, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA0__RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0, 0, 0, (HYS | PKE | PUE)) -#define MX25_PAD_FEC_RDATA0__DAT3 IOMUX_PAD(0x3d4, 0x1dc, 1, 0x4f0, 2, NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA0__AUD4_RXFS IOMUX_PAD(0x3d4, 0x1dc, 2, 0x46c, 1, NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA0__INTRQ IOMUX_PAD(0x3d4, 0x1dc, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA0__RXCAN IOMUX_PAD(0x3d4, 0x1dc, 4, 0x480, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA0__GPIO10 IOMUX_PAD(0x3d4, 0x1dc, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA0__ROW5 IOMUX_PAD(0x3d4, 0x1dc, 6, 0x540, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA0__LCDC_LD21 IOMUX_PAD(0x3d4, 0x1dc, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA1__RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0, 0, 0, (HYS | PKE | PUE)) -#define MX25_PAD_FEC_RDATA1__SCL IOMUX_PAD(0x3d8, 0x1e0, 1, 0x51c, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA1__DAT4 IOMUX_PAD(0x3d8, 0x1e0, 2, 0x4f4, 1, NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA1__CS0 IOMUX_PAD(0x3d8, 0x1e0, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA1__TXCAN IOMUX_PAD(0x3d8, 0x1e0, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA1__GPIO11 IOMUX_PAD(0x3d8, 0x1e0, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA1__COL4 IOMUX_PAD(0x3d8, 0x1e0, 6, 0x52c, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA1__LCDC_LD22 IOMUX_PAD(0x3d8, 0x1e0, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RX_DV__RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0, 0, 0, (HYS | PKE | PUE)) -#define MX25_PAD_FEC_RX_DV__SDA IOMUX_PAD(0x3dc, 0x1e4, 1, 0x520, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RX_DV__DAT5 IOMUX_PAD(0x3dc, 0x1e4, 2, 0x4f8, 1, NO_PAD_CTRL) -#define MX25_PAD_FEC_RX_DV__CS1 IOMUX_PAD(0x3dc, 0x1e4, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RX_DV__RXCAN IOMUX_PAD(0x3dc, 0x1e4, 4, 0x484, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RX_DV__GPIO12 IOMUX_PAD(0x3dc, 0x1e4, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RX_DV__COL5 IOMUX_PAD(0x3dc, 0x1e4, 6, 0x530, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_RX_DV__LCDC_LD23 IOMUX_PAD(0x3dc, 0x1e4, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA0__TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0, 0, 0, PUE) -#define MX25_PAD_FEC_TDATA0__DAT0 IOMUX_PAD(0x3c8, 0x1d0, 1, 0x4e4, 2, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA0__AUD4_TXC IOMUX_PAD(0x3c8, 0x1d0, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA0__DMACK IOMUX_PAD(0x3c8, 0x1d0, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA0__GPIO7 IOMUX_PAD(0x3c8, 0x1d0, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA0__SDMA_DBG_PC_10 IOMUX_PAD(0x3c8, 0x1d0, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA0__LCDC_LD18 IOMUX_PAD(0x3c8, 0x1d0, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA1__TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0, 0, 0, PUE) -#define MX25_PAD_FEC_TDATA1__DAT1 IOMUX_PAD(0x3cc, 0x1d4, 1, 0x4e8, 2, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 2, 0x474, 1, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA1__RESET_B IOMUX_PAD(0x3cc, 0x1d4, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA1__GPIO8 IOMUX_PAD(0x3cc, 0x1d4, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA1__SDMA_DBG_PC_11 IOMUX_PAD(0x3cc, 0x1d4, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA1__LCDC_LD19 IOMUX_PAD(0x3cc, 0x1d4, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_CLK__TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0, 0, 0, (HYS | PKE | PUE)) -#define MX25_PAD_FEC_TX_CLK__PWMO IOMUX_PAD(0x3e0, 0x1e8, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_CLK__DAT6 IOMUX_PAD(0x3e0, 0x1e8, 2, 0x4fc, 1, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_CLK__LCDC_LD16 IOMUX_PAD(0x3e0, 0x1e8, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_CLK__GPIO13 IOMUX_PAD(0x3e0, 0x1e8, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_CLK__SDMA_DBG_PC_12 IOMUX_PAD(0x3e0, 0x1e8, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_CLK__M3IF_CHOSEN_MASTER_0 IOMUX_PAD(0x3e0, 0x1e8, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_EN__TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0, 0, 0, PUE) -#define MX25_PAD_FEC_TX_EN__DAT2 IOMUX_PAD(0x3d0, 0x1d8, 1, 0x4ec, 2, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_EN__AUD4_RXC IOMUX_PAD(0x3d0, 0x1d8, 2, 0x468, 1, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_EN__IORDY IOMUX_PAD(0x3d0, 0x1d8, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_EN__TXCAN IOMUX_PAD(0x3d0, 0x1d8, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_EN__GPIO9 IOMUX_PAD(0x3d0, 0x1d8, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_EN__ROW4 IOMUX_PAD(0x3d0, 0x1d8, 6, 0x53c, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_EN__LCDC_LD20 IOMUX_PAD(0x3d0, 0x1d8, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_A__GPIO0 IOMUX_PAD(0x3f0, 0x1f4, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_A__PWMO IOMUX_PAD(0x3f0, 0x1f4, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_A__USBOTG_PWR IOMUX_PAD(0x3f0, 0x1f4, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_A__ROW4 IOMUX_PAD(0x3f0, 0x1f4, 3, 0x53c, 1, NO_PAD_CTRL) -#define MX25_PAD_GPIO_A__SCL IOMUX_PAD(0x3f0, 0x1f4, 4, 0x524, 1, NO_PAD_CTRL) -#define MX25_PAD_GPIO_A__TXCAN IOMUX_PAD(0x3f0, 0x1f4, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_A__INT_MUX_OUT IOMUX_PAD(0x3f0, 0x1f4, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_B__GPIO1 IOMUX_PAD(0x3f4, 0x1f8, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_B__PWMO IOMUX_PAD(0x3f4, 0x1f8, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_B__USBOTG_OC IOMUX_PAD(0x3f4, 0x1f8, 2, 0x57c, 1, NO_PAD_CTRL) -#define MX25_PAD_GPIO_B__ROW5 IOMUX_PAD(0x3f4, 0x1f8, 3, 0x540, 1, NO_PAD_CTRL) -#define MX25_PAD_GPIO_B__SDA IOMUX_PAD(0x3f4, 0x1f8, 4, 0x528, 2, NO_PAD_CTRL) -#define MX25_PAD_GPIO_B__RXCAN IOMUX_PAD(0x3f4, 0x1f8, 6, 0x480, 1, NO_PAD_CTRL) -#define MX25_PAD_GPIO_C__GPIO2 IOMUX_PAD(0x3f8, 0x1fc, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_C__PWMO IOMUX_PAD(0x3f8, 0x1fc, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_C__SCL IOMUX_PAD(0x3f8, 0x1fc, 2, 0x51c, 1, NO_PAD_CTRL) -#define MX25_PAD_GPIO_C__COL4 IOMUX_PAD(0x3f8, 0x1fc, 3, 0x52c, 1, NO_PAD_CTRL) -#define MX25_PAD_GPIO_C__CAPIN1 IOMUX_PAD(0x3f8, 0x1fc, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_C__CSPI1_SS2 IOMUX_PAD(0x3f8, 0x1fc, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_C__TXCAN IOMUX_PAD(0x3f8, 0x1fc, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_C__CSPI2_SS2 IOMUX_PAD(0x3f8, 0x1fc, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_D__GPIO3 IOMUX_PAD(0x3fc, 0x200, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_D__WDOG_B IOMUX_PAD(0x3fc, 0x200, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_D__SDA IOMUX_PAD(0x3fc, 0x200, 2, 0x520, 1, NO_PAD_CTRL) -#define MX25_PAD_GPIO_D__COL5 IOMUX_PAD(0x3fc, 0x200, 3, 0x530, 1, NO_PAD_CTRL) -#define MX25_PAD_GPIO_D__CMPOUT1 IOMUX_PAD(0x3fc, 0x200, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_D__RXCAN IOMUX_PAD(0x3fc, 0x200, 6, 0x484, 1, NO_PAD_CTRL) -#define MX25_PAD_GPIO_D__SS2 IOMUX_PAD(0x3fc, 0x200, 7, 0x4c4, 1, NO_PAD_CTRL) -#define MX25_PAD_GPIO_E__GPIO4 IOMUX_PAD(0x400, 0x204, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_E__SCL IOMUX_PAD(0x400, 0x204, 1, 0x524, 2, NO_PAD_CTRL) -#define MX25_PAD_GPIO_E__LCDC_LD16 IOMUX_PAD(0x400, 0x204, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_E__RXD_MUX IOMUX_PAD(0x400, 0x204, 6, 0x570, 2, NO_PAD_CTRL) -#define MX25_PAD_GPIO_E__CTI_TRIG_IN0_6 IOMUX_PAD(0x400, 0x204, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_F__GPIO5 IOMUX_PAD(0x404, 0x208, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_F__LCDC_LD17 IOMUX_PAD(0x404, 0x208, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_F__EPITO IOMUX_PAD(0x404, 0x208, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_F__AUD7_TXC IOMUX_PAD(0x404, 0x208, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_F__TXD_MUX IOMUX_PAD(0x404, 0x208, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_F__CTI_TRIG_OUT0_6 IOMUX_PAD(0x404, 0x208, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_HSYNC__LCDC_HSYN IOMUX_PAD(0x300, 0x108, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_HSYNC__SCL IOMUX_PAD(0x300, 0x108, 2, 0x524, 0, NO_PAD_CTRL) -#define MX25_PAD_HSYNC__BUFFER_EN IOMUX_PAD(0x300, 0x108, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_HSYNC__VEN1 IOMUX_PAD(0x300, 0x108, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_HSYNC__GPIO22 IOMUX_PAD(0x300, 0x108, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_HSYNC__USBH2_DATA4 IOMUX_PAD(0x300, 0x108, 6, 0, 0, 0xe5) -#define MX25_PAD_HSYNC__BT_UART_SRC1 IOMUX_PAD(0x300, 0x108, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_I2C1_CLK__SCL IOMUX_PAD(0x348, 0x150, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_I2C1_CLK__GPIO12 IOMUX_PAD(0x348, 0x150, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_I2C1_CLK__SLCDC_DATA6 IOMUX_PAD(0x348, 0x150, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_I2C1_DAT__SDA IOMUX_PAD(0x34c, 0x154, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_I2C1_DAT__GPIO13 IOMUX_PAD(0x34c, 0x154, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_I2C1_DAT__SLCDC_DATA7 IOMUX_PAD(0x34c, 0x154, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL0__COL0 IOMUX_PAD(0x3b0, 0x1b8, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL0__RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 1, 0x570, 1, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL0__AUD5_TXD IOMUX_PAD(0x3b0, 0x1b8, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL0__GPIO1 IOMUX_PAD(0x3b0, 0x1b8, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL0__SDMA_DBG_PC_4 IOMUX_PAD(0x3b0, 0x1b8, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL1__COL1 IOMUX_PAD(0x3b4, 0x1bc, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL1__TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL1__AUD5_RXD IOMUX_PAD(0x3b4, 0x1bc, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL1__GPIO2 IOMUX_PAD(0x3b4, 0x1bc, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL1__SDMA_DBG_PC_5 IOMUX_PAD(0x3b4, 0x1bc, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL2__COL2 IOMUX_PAD(0x3b8, 0x1c0, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL2__RTS IOMUX_PAD(0x3b8, 0x1c0, 1, 0x56c, 1, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL2__AUD5_TXC IOMUX_PAD(0x3b8, 0x1c0, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL2__GPIO3 IOMUX_PAD(0x3b8, 0x1c0, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL2__SDMA_DBG_PC_6 IOMUX_PAD(0x3b8, 0x1c0, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL2__M3IF_CHOSEN_MASTER_1 IOMUX_PAD(0x3b8, 0x1c0, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL3__COL3 IOMUX_PAD(0x3bc, 0x1c4, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL3__CTS IOMUX_PAD(0x3bc, 0x1c4, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL3__AUD5_TXFS IOMUX_PAD(0x3bc, 0x1c4, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL3__GPIO4 IOMUX_PAD(0x3bc, 0x1c4, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL3__SDMA_DBG_PC_7 IOMUX_PAD(0x3bc, 0x1c4, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL3__M3IF_CHOSEN_MASTER_2 IOMUX_PAD(0x3bc, 0x1c4, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW0__RXD_MUX IOMUX_PAD(0x3a0, 0x1a8, 1, 0x568, 1, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW0__ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW0__DTR IOMUX_PAD(0x3a0, 0x1a8, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW0__GPIO29 IOMUX_PAD(0x3a0, 0x1a8, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW0__SDMA_DBG_PC_0 IOMUX_PAD(0x3a0, 0x1a8, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW1__ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW1__TXD_MUX IOMUX_PAD(0x3a4, 0x1ac, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW1__DSR IOMUX_PAD(0x3a4, 0x1ac, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW1__GPIO30 IOMUX_PAD(0x3a4, 0x1ac, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW1__SDMA_DBG_PC_1 IOMUX_PAD(0x3a4, 0x1ac, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW2__ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW2__RTS IOMUX_PAD(0x3a8, 0x1b0, 1, 0x564, 1, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW2__AUD5_RXC IOMUX_PAD(0x3a8, 0x1b0, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 3, 0x488, 2, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW2__DCD IOMUX_PAD(0x3a8, 0x1b0, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW2__GPIO31 IOMUX_PAD(0x3a8, 0x1b0, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW2__SDMA_DBG_PC_2 IOMUX_PAD(0x3a8, 0x1b0, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW3__ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW3__CTS IOMUX_PAD(0x3ac, 0x1b4, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW3__AUD5_RXFS IOMUX_PAD(0x3ac, 0x1b4, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW3__CSI_D1 IOMUX_PAD(0x3ac, 0x1b4, 3, 0x48c, 2, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW3__RI IOMUX_PAD(0x3ac, 0x1b4, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW3__GPIO0 IOMUX_PAD(0x3ac, 0x1b4, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW3__SDMA_DBG_PC_3 IOMUX_PAD(0x3ac, 0x1b4, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LBA__EIM_LBA IOMUX_PAD(0x274, 0x64, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LBA__RXD_MUX IOMUX_PAD(0x274, 0x64, 3, 0x578, 0, NO_PAD_CTRL) -#define MX25_PAD_LBA__GPIO24 IOMUX_PAD(0x274, 0x64, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LBA__RDY IOMUX_PAD(0x274, 0x64, 6, 0x4b0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD0__LCDC_LD0 IOMUX_PAD(0x2c0, 0xc8, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD0__SLCDC_DATA0 IOMUX_PAD(0x2c0, 0xc8, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD0__CSI_D0 IOMUX_PAD(0x2c0, 0xc8, 2, 0x488, 0, NO_PAD_CTRL) -#define MX25_PAD_LD0__DATA0 IOMUX_PAD(0x2c0, 0xc8, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD0__CLK1 IOMUX_PAD(0x2c0, 0xc8, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD0__GPIO15 IOMUX_PAD(0x2c0, 0xc8, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD0__USBH2_CLK IOMUX_PAD(0x2c0, 0xc8, 6, 0, 0, 0xe0) -#define MX25_PAD_LD0__BT_MEM_CTRL0 IOMUX_PAD(0x2c0, 0xc8, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD10__LCDC_LD10 IOMUX_PAD(0x2e8, 0xf0, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD10__SLCDC_DATA10 IOMUX_PAD(0x2e8, 0xf0, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD10__RTS IOMUX_PAD(0x2e8, 0xf0, 2, 0x56c, 0, NO_PAD_CTRL) -#define MX25_PAD_LD10__DATA10 IOMUX_PAD(0x2e8, 0xf0, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD10__AUD3_TXC IOMUX_PAD(0x2e8, 0xf0, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD10__DAT0 IOMUX_PAD(0x2e8, 0xf0, 6, 0x4e4, 0, NO_PAD_CTRL) -#define MX25_PAD_LD10__RX_ERR IOMUX_PAD(0x2e8, 0xf0, 5, 0x518, 1, NO_PAD_CTRL) -#define MX25_PAD_LD10__BT_MLC_SEL IOMUX_PAD(0x2e8, 0xf0, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD11__LCDC_LD11 IOMUX_PAD(0x2ec, 0xf4, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD11__SLCDC_DATA11 IOMUX_PAD(0x2ec, 0xf4, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD11__CTS IOMUX_PAD(0x2ec, 0xf4, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD11__DATA11 IOMUX_PAD(0x2ec, 0xf4, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD11__AUD3_TXFS IOMUX_PAD(0x2ec, 0xf4, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD11__RDATA2 IOMUX_PAD(0x2ec, 0xf4, 5, 0x50c, 1, NO_PAD_CTRL) -#define MX25_PAD_LD11__DAT1 IOMUX_PAD(0x2ec, 0xf4, 6, 0x4e8, 0, NO_PAD_CTRL) -#define MX25_PAD_LD11__BT_SPARE_SIZE IOMUX_PAD(0x2ec, 0xf4, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD12__LCDC_LD12 IOMUX_PAD(0x2f0, 0xf8, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD12__SLCDC_DATA12 IOMUX_PAD(0x2f0, 0xf8, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD12__MOSI IOMUX_PAD(0x2f0, 0xf8, 2, 0x4a0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD12__DATA12 IOMUX_PAD(0x2f0, 0xf8, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD12__ROW6 IOMUX_PAD(0x2f0, 0xf8, 4, 0x544, 0, NO_PAD_CTRL) -#define MX25_PAD_LD12__RDATA3 IOMUX_PAD(0x2f0, 0xf8, 5, 0x510, 1, NO_PAD_CTRL) -#define MX25_PAD_LD12__DAT2 IOMUX_PAD(0x2f0, 0xf8, 6, 0x4ec, 0, NO_PAD_CTRL) -#define MX25_PAD_LD12__BT_SRC0 IOMUX_PAD(0x2f0, 0xf8, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD13__LCDC_LD13 IOMUX_PAD(0x2f4, 0xfc, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD13__SLCDC_DATA13 IOMUX_PAD(0x2f4, 0xfc, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD13__MISO IOMUX_PAD(0x2f4, 0xfc, 2, 0x49c, 0, NO_PAD_CTRL) -#define MX25_PAD_LD13__DATA13 IOMUX_PAD(0x2f4, 0xfc, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD13__ROW7 IOMUX_PAD(0x2f4, 0xfc, 4, 0x548, 0, NO_PAD_CTRL) -#define MX25_PAD_LD13__TDATA2 IOMUX_PAD(0x2f4, 0xfc, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD13__DAT3 IOMUX_PAD(0x2f4, 0xfc, 6, 0x4f0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD13__BT_SRC1 IOMUX_PAD(0x2f4, 0xfc, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD14__LCDC_LD14 IOMUX_PAD(0x2f8, 0x100, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD14__SLCDC_DATA14 IOMUX_PAD(0x2f8, 0x100, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD14__SCLK IOMUX_PAD(0x2f8, 0x100, 2, 0x494, 0, NO_PAD_CTRL) -#define MX25_PAD_LD14__DATA14 IOMUX_PAD(0x2f8, 0x100, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD14__COL6 IOMUX_PAD(0x2f8, 0x100, 4, 0x534, 0, NO_PAD_CTRL) -#define MX25_PAD_LD14__TDATA3 IOMUX_PAD(0x2f8, 0x100, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD14__AUD3_RXC IOMUX_PAD(0x2f8, 0x100, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD14__BT_EEPROM_CFG IOMUX_PAD(0x2f8, 0x100, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD15__LCDC_LD15 IOMUX_PAD(0x2fc, 0x104, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD15__SLCDC_DATA15 IOMUX_PAD(0x2fc, 0x104, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD15__RDY IOMUX_PAD(0x2fc, 0x104, 2, 0x498, 0, NO_PAD_CTRL) -#define MX25_PAD_LD15__DATA15 IOMUX_PAD(0x2fc, 0x104, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD15__COL7 IOMUX_PAD(0x2fc, 0x104, 4, 0x538, 0, NO_PAD_CTRL) -#define MX25_PAD_LD15__RX_CLK IOMUX_PAD(0x2fc, 0x104, 5, 0x514, 1, NO_PAD_CTRL) -#define MX25_PAD_LD15__AUD3_RXFS IOMUX_PAD(0x2fc, 0x104, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD15__BT_UART_SRC0 IOMUX_PAD(0x2fc, 0x104, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD1__LCDC_LD1 IOMUX_PAD(0x2c4, 0xcc, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD1__SLCDC_DATA1 IOMUX_PAD(0x2c4, 0xcc, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD1__CSI_D1 IOMUX_PAD(0x2c4, 0xcc, 2, 0x48c, 0, NO_PAD_CTRL) -#define MX25_PAD_LD1__DATA1 IOMUX_PAD(0x2c4, 0xcc, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD1__RST1 IOMUX_PAD(0x2c4, 0xcc, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD1__GPIO16 IOMUX_PAD(0x2c4, 0xcc, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD1__USBH2_DIR IOMUX_PAD(0x2c4, 0xcc, 6, 0, 0, 0xe0) -#define MX25_PAD_LD1__BT_MEM_CTRL1 IOMUX_PAD(0x2c4, 0xcc, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD2__LCDC_LD2 IOMUX_PAD(0x2c8, 0xd0, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD2__SLCDC_DATA2 IOMUX_PAD(0x2c8, 0xd0, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD2__CSI_D15 IOMUX_PAD(0x2c8, 0xd0, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD2__DATA2 IOMUX_PAD(0x2c8, 0xd0, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD2__VEN1 IOMUX_PAD(0x2c8, 0xd0, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD2__GPIO17 IOMUX_PAD(0x2c8, 0xd0, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD2__USBH2_STP IOMUX_PAD(0x2c8, 0xd0, 6, 0, 0, 0xe5) -#define MX25_PAD_LD2__BT_MEM_TYPE0 IOMUX_PAD(0x2c8, 0xd0, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD3__LCDC_LD3 IOMUX_PAD(0x2cc, 0xd4, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD3__SLCDC_DATA3 IOMUX_PAD(0x2cc, 0xd4, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD3__CSI_D14 IOMUX_PAD(0x2cc, 0xd4, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD3__DATA3 IOMUX_PAD(0x2cc, 0xd4, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD3__TX1 IOMUX_PAD(0x2cc, 0xd4, 4, 0x554, 1, NO_PAD_CTRL) -#define MX25_PAD_LD3__GPIO18 IOMUX_PAD(0x2cc, 0xd4, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD3__USBH2_NXT IOMUX_PAD(0x2cc, 0xd4, 6, 0, 0, 0xe0) -#define MX25_PAD_LD3__BT_MEM_TYPE1 IOMUX_PAD(0x2cc, 0xd4, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD4__LCDC_LD4 IOMUX_PAD(0x2d0, 0xd8, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD4__SLCDC_DATA4 IOMUX_PAD(0x2d0, 0xd8, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD4__CSI_D13 IOMUX_PAD(0x2d0, 0xd8, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD4__DATA4 IOMUX_PAD(0x2d0, 0xd8, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD4__PD1 IOMUX_PAD(0x2d0, 0xd8, 4, 0x550, 1, NO_PAD_CTRL) -#define MX25_PAD_LD4__GPIO19 IOMUX_PAD(0x2d0, 0xd8, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD4__USBH2_DATA0 IOMUX_PAD(0x2d0, 0xd8, 6, 0, 0, 0xe5) -#define MX25_PAD_LD4__BT_PAGE_SIZE0 IOMUX_PAD(0x2d0, 0xd8, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD5__LCDC_LD5 IOMUX_PAD(0x2d4, 0xdc, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD5__SLCDC_DATA5 IOMUX_PAD(0x2d4, 0xdc, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD5__CSI_D12 IOMUX_PAD(0x2d4, 0xdc, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD5__DATA5 IOMUX_PAD(0x2d4, 0xdc, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD5__RX1 IOMUX_PAD(0x2d4, 0xdc, 4, 0x54c, 1, NO_PAD_CTRL) -#define MX25_PAD_LD5__GPIO19 IOMUX_PAD(0x2d4, 0xdc, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD5__USBH2_DATA1 IOMUX_PAD(0x2d4, 0xdc, 6, 0, 0, 0xe5) -#define MX25_PAD_LD5__BT_PAGE_SIZE1 IOMUX_PAD(0x2d4, 0xdc, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD6__LCDC_LD6 IOMUX_PAD(0x2d8, 0xe0, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD6__SLCDC_DATA6 IOMUX_PAD(0x2d8, 0xe0, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD6__CSI_D11 IOMUX_PAD(0x2d8, 0xe0, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD6__DATA6 IOMUX_PAD(0x2d8, 0xe0, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD6__CLK1 IOMUX_PAD(0x2d8, 0xe0, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD6__GPIO20 IOMUX_PAD(0x2d8, 0xe0, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD6__USBH2_DATA2 IOMUX_PAD(0x2d8, 0xe0, 6, 0, 0, 0xe5) -#define MX25_PAD_LD6__BT_BUS_WIDTH0 IOMUX_PAD(0x2d8, 0xe0, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD7__LCDC_LD7 IOMUX_PAD(0x2dc, 0xe4, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD7__SLCDC_DATA7 IOMUX_PAD(0x2dc, 0xe4, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD7__CSI_D10 IOMUX_PAD(0x2dc, 0xe4, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD7__DATA7 IOMUX_PAD(0x2dc, 0xe4, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD7__RST1 IOMUX_PAD(0x2dc, 0xe4, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD7__GPIO21 IOMUX_PAD(0x2dc, 0xe4, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD7__USBH2_DATA3 IOMUX_PAD(0x2dc, 0xe4, 6, 0, 0, 0xe5) -#define MX25_PAD_LD7__BT_BUS_WIDTH1 IOMUX_PAD(0x2dc, 0xe4, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD8__LCDC_LD8 IOMUX_PAD(0x2e0, 0xe8, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD8__SLCDC_DATA8 IOMUX_PAD(0x2e0, 0xe8, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD8__RXD_MUX IOMUX_PAD(0x2e0, 0xe8, 2, 0x570, 0, NO_PAD_CTRL) -#define MX25_PAD_LD8__DATA8 IOMUX_PAD(0x2e0, 0xe8, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD8__AUD3_TXD IOMUX_PAD(0x2e0, 0xe8, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD8__TX_ERR IOMUX_PAD(0x2e0, 0xe8, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD8__CMD IOMUX_PAD(0x2e0, 0xe8, 6, 0x4e0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD8__BT_USB_SRC0 IOMUX_PAD(0x2e0, 0xe8, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD9__LCDC_LD9 IOMUX_PAD(0x2e4, 0xec, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD9__SLCDC_DATA9 IOMUX_PAD(0x2e4, 0xec, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD9__TXD_MUX IOMUX_PAD(0x2e4, 0xec, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD9__DATA9 IOMUX_PAD(0x2e4, 0xec, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD9__AUD3_RXD IOMUX_PAD(0x2e4, 0xec, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LD9__COL IOMUX_PAD(0x2e4, 0xec, 5, 0x504, 1, NO_PAD_CTRL) -#define MX25_PAD_LD9__CLK IOMUX_PAD(0x2e4, 0xec, 6, 0x4dc, 0, NO_PAD_CTRL) -#define MX25_PAD_LD9__BT_USB_SRC1 IOMUX_PAD(0x2e4, 0xec, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LSCLK__LCDC_LSCLK IOMUX_PAD(0x308, 0x110, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LSCLK__SLCDC_CS IOMUX_PAD(0x308, 0x110, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LSCLK__DA_0 IOMUX_PAD(0x308, 0x110, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LSCLK__PD1 IOMUX_PAD(0x308, 0x110, 4, 0x55c, 1, NO_PAD_CTRL) -#define MX25_PAD_LSCLK__GPIO24 IOMUX_PAD(0x308, 0x110, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LSCLK__USBH2_DATA6 IOMUX_PAD(0x308, 0x110, 6, 0, 0, 0xe5) -#define MX25_PAD_LSCLK__BT_LPB_FREQ0 IOMUX_PAD(0x308, 0x110, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFALE__NANDF_ALE IOMUX_PAD(0x000, 0x78, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFALE__GPIO28 IOMUX_PAD(0x000, 0x78, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFALE__PIPESTAT0 IOMUX_PAD(0x000, 0x78, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NF_CE0__NANDF_CE0 IOMUX_PAD(0x26c, 0x5c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NF_CE0__SS3 IOMUX_PAD(0x26c, 0x5c, 1, 0x490, 0, NO_PAD_CTRL) -#define MX25_PAD_NF_CE0__GPIO22 IOMUX_PAD(0x26c, 0x5c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NF_CE0__TRACE3 IOMUX_PAD(0x26c, 0x5c, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFCLE__NANDF_CLE IOMUX_PAD(0x000, 0x7c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFCLE__GPIO29 IOMUX_PAD(0x000, 0x7c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFCLE__TRACE0 IOMUX_PAD(0x000, 0x7c, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFRB__NANDF_RB IOMUX_PAD(0x27c, 0x84, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFRB__GPIO31 IOMUX_PAD(0x27c, 0x84, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFRB__TRACE2 IOMUX_PAD(0x27c, 0x84, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFRE_B__NANDF_RE_B IOMUX_PAD(0x000, 0x74, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFRE_B__GPIO27 IOMUX_PAD(0x000, 0x74, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFRE_B__PIPESTAT1 IOMUX_PAD(0x000, 0x74, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFWE_B__NANDF_WE_B IOMUX_PAD(0x000, 0x70, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFWE_B__GPIO26 IOMUX_PAD(0x000, 0x70, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFWE_B__PIPESTAT2 IOMUX_PAD(0x000, 0x70, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFWP_B__NANDF_WP_B IOMUX_PAD(0x000, 0x80, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFWP_B__GPIO30 IOMUX_PAD(0x000, 0x80, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFWP_B__TRACE1 IOMUX_PAD(0x000, 0x80, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE_ACD__LCDC_OE_ACD IOMUX_PAD(0x30c, 0x114, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE_ACD__SLCDC_RS IOMUX_PAD(0x30c, 0x114, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE_ACD__SS0 IOMUX_PAD(0x30c, 0x114, 2, 0x4a4, 0, NO_PAD_CTRL) -#define MX25_PAD_OE_ACD__DA_1 IOMUX_PAD(0x30c, 0x114, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE_ACD__RX1 IOMUX_PAD(0x30c, 0x114, 4, 0x558, 1, NO_PAD_CTRL) -#define MX25_PAD_OE_ACD__GPIO25 IOMUX_PAD(0x30c, 0x114, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE_ACD__USBH2_DATA7 IOMUX_PAD(0x30c, 0x114, 6, 0, 0, 0xe5) -#define MX25_PAD_OE_ACD__BT_LPB_FREQ1 IOMUX_PAD(0x30c, 0x114, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE__EIM_OE IOMUX_PAD(0x260, 0x48, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE__AUD4_TXC IOMUX_PAD(0x260, 0x48, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE__GPIO14 IOMUX_PAD(0x260, 0x48, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_POWER_FAIL__POWER_FAIL_INT IOMUX_PAD(0x410, 0x21c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_POWER_FAIL__AUD7_RXD IOMUX_PAD(0x410, 0x21c, 4, 0x478, 1, NO_PAD_CTRL) -#define MX25_PAD_POWER_FAIL__GPIO19 IOMUX_PAD(0x410, 0x21c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_POWER_FAIL__CTS IOMUX_PAD(0x410, 0x21c, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_PWM__PWMO IOMUX_PAD(0x314, 0x11c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_PWM__CMPOUT1 IOMUX_PAD(0x314, 0x11c, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_PWM__GPIO26 IOMUX_PAD(0x314, 0x11c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_PWM__USBH2_OC IOMUX_PAD(0x314, 0x11c, 6, 0x580, 1, NO_PAD_CTRL) -#define MX25_PAD_PWM__BT_LPB_FREQ2 IOMUX_PAD(0x314, 0x11c, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_RTCK__RTCK IOMUX_PAD(0x3e4, 0x1ec, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_RTCK__LINE IOMUX_PAD(0x3e4, 0x1ec, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_RTCK__DAT7 IOMUX_PAD(0x3e4, 0x1ec, 2, 0x500, 1, NO_PAD_CTRL) -#define MX25_PAD_RTCK__GPIO14 IOMUX_PAD(0x3e4, 0x1ec, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_RTCK__SDMA_DBG_PC_13 IOMUX_PAD(0x3e4, 0x1ec, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_RW__EIM_RW IOMUX_PAD(0x278, 0x6c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_RW__AUD4_TXFS IOMUX_PAD(0x278, 0x6c, 4, 0x474, 0, NO_PAD_CTRL) -#define MX25_PAD_RW__GPIO25 IOMUX_PAD(0x278, 0x6c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_CLK__CLK IOMUX_PAD(0x38c, 0x194, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_CLK__MISO IOMUX_PAD(0x38c, 0x194, 1, 0x49c, 1, NO_PAD_CTRL) -#define MX25_PAD_SD1_CLK__RDATA3 IOMUX_PAD(0x38c, 0x194, 2, 0x510, 2, NO_PAD_CTRL) -#define MX25_PAD_SD1_CLK__SDMA_DBG_STAT_0 IOMUX_PAD(0x38c, 0x194, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_CLK__GPIO24 IOMUX_PAD(0x38c, 0x194, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_CLK__SLCDC_DATA1 IOMUX_PAD(0x38c, 0x194, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_CLK__TRACE11 IOMUX_PAD(0x38c, 0x194, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_CMD__CMD IOMUX_PAD(0x388, 0x190, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_CMD__MOSI IOMUX_PAD(0x388, 0x190, 1, 0x4a0, 1, NO_PAD_CTRL) -#define MX25_PAD_SD1_CMD__RDATA2 IOMUX_PAD(0x388, 0x190, 2, 0x50c, 2, NO_PAD_CTRL) -#define MX25_PAD_SD1_CMD__SDMA_DBG_EVT_SEL IOMUX_PAD(0x388, 0x190, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_CMD__GPIO23 IOMUX_PAD(0x388, 0x190, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_CMD__SLCDC_DATA0 IOMUX_PAD(0x388, 0x190, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_CMD__TRACE10 IOMUX_PAD(0x388, 0x190, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA0__DAT0 IOMUX_PAD(0x390, 0x198, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA0__SCLK IOMUX_PAD(0x390, 0x198, 1, 0x494, 1, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA0__TDATA2 IOMUX_PAD(0x390, 0x198, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA0__AUD7_TXFS IOMUX_PAD(0x390, 0x198, 3, 0x47c, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA0__SDMA_DBG_STAT_1 IOMUX_PAD(0x390, 0x198, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA0__GPIO25 IOMUX_PAD(0x390, 0x198, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA0__SLCDC_DATA2 IOMUX_PAD(0x390, 0x198, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA0__TRACE12 IOMUX_PAD(0x390, 0x198, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA1__DAT1 IOMUX_PAD(0x394, 0x19c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA1__RDY IOMUX_PAD(0x394, 0x19c, 1, 0x498, 1, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA1__TDATA3 IOMUX_PAD(0x394, 0x19c, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA1__AUD7_RXD IOMUX_PAD(0x394, 0x19c, 3, 0x478, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA1__SDMA_DBG_STAT_2 IOMUX_PAD(0x394, 0x19c, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA1__GPIO26 IOMUX_PAD(0x394, 0x19c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA1__SLCDC_DATA3 IOMUX_PAD(0x394, 0x19c, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA1__TRACE13 IOMUX_PAD(0x394, 0x19c, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA2__DAT2 IOMUX_PAD(0x398, 0x1a0, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA2__SS0 IOMUX_PAD(0x398, 0x1a0, 1, 0x4a4, 1, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA2__RX_CLK IOMUX_PAD(0x398, 0x1a0, 2, 0x514, 2, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA2__AUD7_RXC IOMUX_PAD(0x398, 0x1a0, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA2__SDMA_DBG_STAT_3 IOMUX_PAD(0x398, 0x1a0, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA2__GPIO27 IOMUX_PAD(0x398, 0x1a0, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA2__SLCDC_DATA4 IOMUX_PAD(0x398, 0x1a0, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA2__TRACE14 IOMUX_PAD(0x398, 0x1a0, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA3__DAT3 IOMUX_PAD(0x39c, 0x1a4, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA3__SS1 IOMUX_PAD(0x39c, 0x1a4, 1, 0x4a8, 1, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA3__CRS IOMUX_PAD(0x39c, 0x1a4, 2, 0x508, 2, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA3__AUD7_RXFS IOMUX_PAD(0x39c, 0x1a4, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA3__GPIO28 IOMUX_PAD(0x39c, 0x1a4, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA3__SLCDC_DATA5 IOMUX_PAD(0x39c, 0x1a4, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA3__TRACE15 IOMUX_PAD(0x39c, 0x1a4, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_CTS__CTS IOMUX_PAD(0x374, 0x17c, 0, 0, 0, 0x40) -#define MX25_PAD_UART1_CTS__CSI_D1 IOMUX_PAD(0x374, 0x17c, 1, 0x48c, 1, NO_PAD_CTRL) -#define MX25_PAD_UART1_CTS__CMPOUT1 IOMUX_PAD(0x374, 0x17c, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_CTS__RI IOMUX_PAD(0x374, 0x17c, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_CTS__LCDC_REV IOMUX_PAD(0x374, 0x17c, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_CTS__GPIO25 IOMUX_PAD(0x374, 0x17c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_CTS__SLCDC_DATA11 IOMUX_PAD(0x374, 0x17c, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_RTS__RTS IOMUX_PAD(0x370, 0x178, 0, 0, 0, 0x1E0) -#define MX25_PAD_UART1_RTS__CSI_D0 IOMUX_PAD(0x370, 0x178, 1, 0x488, 1, NO_PAD_CTRL) -#define MX25_PAD_UART1_RTS__CAPIN1 IOMUX_PAD(0x370, 0x178, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_RTS__DCD IOMUX_PAD(0x370, 0x178, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_RTS__LCDC_PS IOMUX_PAD(0x370, 0x178, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_RTS__GPIO24 IOMUX_PAD(0x370, 0x178, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_RTS__SLCDC_DATA10 IOMUX_PAD(0x370, 0x178, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_RXD__RXD_MUX IOMUX_PAD(0x368, 0x170, 0, 0, 0, 0x1e0) -#define MX25_PAD_UART1_RXD__DTR IOMUX_PAD(0x368, 0x170, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_RXD__LCDC_CLS IOMUX_PAD(0x368, 0x170, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_RXD__GPIO22 IOMUX_PAD(0x368, 0x170, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_RXD__SLCDC_DATA8 IOMUX_PAD(0x368, 0x170, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_TXD__TXD_MUX IOMUX_PAD(0x36c, 0x174, 0, 0, 0, 0x40) -#define MX25_PAD_UART1_TXD__DSR IOMUX_PAD(0x36c, 0x174, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_TXD__LCDC_SPL IOMUX_PAD(0x36c, 0x174, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_TXD__GPIO23 IOMUX_PAD(0x36c, 0x174, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_TXD__SLCDC_DATA9 IOMUX_PAD(0x36c, 0x174, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_CTS__CTS IOMUX_PAD(0x384, 0x18c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_CTS__DAT4 IOMUX_PAD(0x384, 0x18c, 1, 0x4cc, 1, NO_PAD_CTRL) -#define MX25_PAD_UART2_CTS__RX_ERR IOMUX_PAD(0x384, 0x18c, 2, 0x518, 2, NO_PAD_CTRL) -#define MX25_PAD_UART2_CTS__CMPOUT1 IOMUX_PAD(0x384, 0x18c, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_CTS__GPIO29 IOMUX_PAD(0x384, 0x18c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_CTS__SS3 IOMUX_PAD(0x384, 0x18c, 6, 0x4c8, 1, NO_PAD_CTRL) -#define MX25_PAD_UART2_CTS__EXTDMA_2 IOMUX_PAD(0x384, 0x18c, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_RTS__RTS IOMUX_PAD(0x380, 0x188, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_RTS__DAT5 IOMUX_PAD(0x380, 0x188, 1, 0x4d0, 1, NO_PAD_CTRL) -#define MX25_PAD_UART2_RTS__COL IOMUX_PAD(0x380, 0x188, 2, 0x504, 2, NO_PAD_CTRL) -#define MX25_PAD_UART2_RTS__CAPIN1 IOMUX_PAD(0x380, 0x188, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_RTS__EPITO IOMUX_PAD(0x380, 0x188, 4, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_RTS__GPIO28 IOMUX_PAD(0x380, 0x188, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_RTS__SS3 IOMUX_PAD(0x380, 0x188, 6, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_RTS__EXTDMA_1 IOMUX_PAD(0x380, 0x188, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_RXD__RXD_MUX IOMUX_PAD(0x378, 0x180, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_RXD__DAT7 IOMUX_PAD(0x378, 0x180, 1, 0x4d8, 1, NO_PAD_CTRL) -#define MX25_PAD_UART2_RXD__GPIO26 IOMUX_PAD(0x378, 0x180, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_TXD__TXD_MUX IOMUX_PAD(0x37c, 0x184, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_TXD__DAT6 IOMUX_PAD(0x37c, 0x184, 1, 0x4d4, 1, NO_PAD_CTRL) -#define MX25_PAD_UART2_TXD__TX_ERR IOMUX_PAD(0x37c, 0x184, 2, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_TXD__GPIO27 IOMUX_PAD(0x37c, 0x184, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_TXD__EXTDMA_0 IOMUX_PAD(0x37c, 0x184, 7, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UPLL_BYPCLK__GPIO16 IOMUX_PAD(0x000, 0x210, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_ACK__hreset_b IOMUX_PAD(0x40c, 0x218, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_ACK__VSTBY_ACK IOMUX_PAD(0x40c, 0x218, 1, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_ACK__SS3 IOMUX_PAD(0x40c, 0x218, 2, 0x490, 1, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_ACK__EPITO IOMUX_PAD(0x40c, 0x218, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_ACK__GPIO18 IOMUX_PAD(0x40c, 0x218, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_REQ__VSTBY_REQ IOMUX_PAD(0x408, 0x214, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_REQ__AUD7_TXFS IOMUX_PAD(0x408, 0x214, 4, 0x47c, 1, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_REQ__GPIO17 IOMUX_PAD(0x408, 0x214, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_REQ__RTS IOMUX_PAD(0x408, 0x214, 6, 0x56c, 2, NO_PAD_CTRL) -#define MX25_PAD_VSYNC__LCDC_VSYN IOMUX_PAD(0x304, 0x10c, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSYNC__SDA IOMUX_PAD(0x304, 0x10c, 2, 0x528, 0, NO_PAD_CTRL) -#define MX25_PAD_VSYNC__DMARQ IOMUX_PAD(0x304, 0x10c, 3, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSYNC__TX1 IOMUX_PAD(0x304, 0x10c, 4, 0x560, 1, NO_PAD_CTRL) -#define MX25_PAD_VSYNC__GPIO23 IOMUX_PAD(0x304, 0x10c, 5, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSYNC__USBH2_DATA5 IOMUX_PAD(0x304, 0x10c, 6, 0, 0, 0xe5) -#define MX25_PAD_VSYNC__BT_UART_SRC2 IOMUX_PAD(0x304, 0x10c, 7, 0, 0, NO_PAD_CTRL) - -#endif /* __MACH_IOMUX_MX25_H__ */ - diff --git a/include/asm-arm/arch-imx/iomux-mx31.h b/include/asm-arm/arch-imx/iomux-mx31.h deleted file mode 100644 index 16c8e51e8c..0000000000 --- a/include/asm-arm/arch-imx/iomux-mx31.h +++ /dev/null @@ -1,553 +0,0 @@ -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_MX31_IOMUX_H__ -#define __MACH_MX31_IOMUX_H__ - -#include <linux/types.h> - -/* - * various IOMUX output functions - */ - -#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */ -#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */ -#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */ -#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */ -#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */ -#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ -#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ -#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ -#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ -#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ -#define IOMUX_ICONFIG_FUNC 2 /* used as function */ -#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ -#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */ - -#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO) -#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC) -#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1) -#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2) - -/* - * various IOMUX pad functions - */ -enum iomux_pad_config { - PAD_CTL_NOLOOPBACK = 0x0 << 9, - PAD_CTL_LOOPBACK = 0x1 << 9, - PAD_CTL_PKE_NONE = 0x0 << 8, - PAD_CTL_PKE_ENABLE = 0x1 << 8, - PAD_CTL_PUE_KEEPER = 0x0 << 7, - PAD_CTL_PUE_PUD = 0x1 << 7, - PAD_CTL_100K_PD = 0x0 << 5, - PAD_CTL_100K_PU = 0x1 << 5, - PAD_CTL_47K_PU = 0x2 << 5, - PAD_CTL_22K_PU = 0x3 << 5, - PAD_CTL_HYS_CMOS = 0x0 << 4, - PAD_CTL_HYS_SCHMITZ = 0x1 << 4, - PAD_CTL_ODE_CMOS = 0x0 << 3, - PAD_CTL_ODE_OpenDrain = 0x1 << 3, - PAD_CTL_DRV_NORMAL = 0x0 << 1, - PAD_CTL_DRV_HIGH = 0x1 << 1, - PAD_CTL_DRV_MAX = 0x2 << 1, - PAD_CTL_SRE_SLOW = 0x0 << 0, - PAD_CTL_SRE_FAST = 0x1 << 0 -}; - -/* - * various IOMUX general purpose functions - */ -enum iomux_gp_func { - MUX_PGP_FIRI = 1 << 0, - MUX_DDR_MODE = 1 << 1, - MUX_PGP_CSPI_BB = 1 << 2, - MUX_PGP_ATA_1 = 1 << 3, - MUX_PGP_ATA_2 = 1 << 4, - MUX_PGP_ATA_3 = 1 << 5, - MUX_PGP_ATA_4 = 1 << 6, - MUX_PGP_ATA_5 = 1 << 7, - MUX_PGP_ATA_6 = 1 << 8, - MUX_PGP_ATA_7 = 1 << 9, - MUX_PGP_ATA_8 = 1 << 10, - MUX_PGP_UH2 = 1 << 11, - MUX_SDCTL_CSD0_SEL = 1 << 12, - MUX_SDCTL_CSD1_SEL = 1 << 13, - MUX_CSPI1_UART3 = 1 << 14, - MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, - MUX_TAMPER_DETECT_EN = 1 << 16, - MUX_PGP_USB_4WIRE = 1 << 17, - MUX_PGB_USB_COMMON = 1 << 18, - MUX_SDHC_MEMSTICK1 = 1 << 19, - MUX_SDHC_MEMSTICK2 = 1 << 20, - MUX_PGP_SPLL_BYP = 1 << 21, - MUX_PGP_UPLL_BYP = 1 << 22, - MUX_PGP_MSHC1_CLK_SEL = 1 << 23, - MUX_PGP_MSHC2_CLK_SEL = 1 << 24, - MUX_CSPI3_UART5_SEL = 1 << 25, - MUX_PGP_ATA_9 = 1 << 26, - MUX_PGP_USB_SUSPEND = 1 << 27, - MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, - MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, - MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, - MUX_CLKO_DDR_MODE = 1 << 31, -}; - -/* - * This function enables/disables the general purpose function for a particular - * signal. - */ -void iomux_config_gpr(enum iomux_gp_func , int); - -/* - * set the mode for a IOMUX pin. - */ -int mxc_iomux_mode(unsigned int); - -/* - * This function enables/disables the general purpose function for a particular - * signal. - */ -void mxc_iomux_set_gpr(enum iomux_gp_func, int); - -#define IOMUX_PADNUM_MASK 0x1ff -#define IOMUX_GPIONUM_SHIFT 9 -#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) -#define IOMUX_MODE_SHIFT 17 -#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT) - -#define IOMUX_PIN(gpionum, padnum) \ - (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \ - (padnum & IOMUX_PADNUM_MASK)) - -#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT) - -#define IOMUX_TO_GPIO(iomux_pin) \ - ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) -#define IOMUX_TO_IRQ(iomux_pin) \ - (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \ - MXC_GPIO_INT_BASE) - -/* - * This enumeration is constructed based on the Section - * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated - * value is constructed based on the rules described above. - */ - -enum iomux_pins { - MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), - MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), - MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), - MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), - MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), - MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), - MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), - MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), - MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), - MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), - MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), - MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), - MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), - MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), - MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), - MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), - MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), - MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), - MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), - MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), - MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), - MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), - MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), - MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), - MX31_PIN_READ = IOMUX_PIN(0xff, 24), - MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), - MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), - MX31_PIN_SER_RS = IOMUX_PIN(89, 27), - MX31_PIN_LCS1 = IOMUX_PIN(88, 28), - MX31_PIN_LCS0 = IOMUX_PIN(87, 29), - MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), - MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), - MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), - MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), - MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), - MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), - MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), - MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), - MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), - MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), - MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), - MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), - MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), - MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), - MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), - MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), - MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), - MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), - MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), - MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), - MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), - MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), - MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), - MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), - MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), - MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), - MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), - MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), - MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), - MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), - MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), - MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), - MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), - MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), - MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), - MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), - MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), - MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), - MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), - MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), - MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), - MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), - MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), - MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), - MX31_PIN_USB_OC = IOMUX_PIN(30, 74), - MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), - MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), - MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), - MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), - MX31_PIN_TDO = IOMUX_PIN(0xff, 79), - MX31_PIN_TDI = IOMUX_PIN(0xff, 80), - MX31_PIN_TMS = IOMUX_PIN(0xff, 81), - MX31_PIN_TCK = IOMUX_PIN(0xff, 82), - MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), - MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), - MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), - MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), - MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), - MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), - MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), - MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), - MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), - MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), - MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), - MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), - MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), - MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), - MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), - MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), - MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), - MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), - MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), - MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), - MX31_PIN_TXD2 = IOMUX_PIN(28, 103), - MX31_PIN_RXD2 = IOMUX_PIN(27, 104), - MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), - MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), - MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), - MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), - MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), - MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), - MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), - MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), - MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), - MX31_PIN_CTS1 = IOMUX_PIN(39, 114), - MX31_PIN_RTS1 = IOMUX_PIN(38, 115), - MX31_PIN_TXD1 = IOMUX_PIN(37, 116), - MX31_PIN_RXD1 = IOMUX_PIN(36, 117), - MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), - MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), - MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), - MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), - MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), - MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), - MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), - MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), - MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), - MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), - MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), - MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), - MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), - MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), - MX31_PIN_SFS6 = IOMUX_PIN(26, 132), - MX31_PIN_SCK6 = IOMUX_PIN(25, 133), - MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), - MX31_PIN_STXD6 = IOMUX_PIN(23, 135), - MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), - MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), - MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), - MX31_PIN_STXD5 = IOMUX_PIN(21, 139), - MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), - MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), - MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), - MX31_PIN_STXD4 = IOMUX_PIN(19, 143), - MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), - MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), - MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), - MX31_PIN_STXD3 = IOMUX_PIN(17, 147), - MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), - MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), - MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), - MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), - MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), - MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), - MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), - MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), - MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), - MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), - MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), - MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), - MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), - MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), - MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), - MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), - MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), - MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), - MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), - MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), - MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), - MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), - MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), - MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), - MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), - MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), - MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), - MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), - MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), - MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), - MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), - MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), - MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), - MX31_PIN_D0 = IOMUX_PIN(0xff, 181), - MX31_PIN_D1 = IOMUX_PIN(0xff, 182), - MX31_PIN_D2 = IOMUX_PIN(0xff, 183), - MX31_PIN_D3 = IOMUX_PIN(0xff, 184), - MX31_PIN_D4 = IOMUX_PIN(0xff, 185), - MX31_PIN_D5 = IOMUX_PIN(0xff, 186), - MX31_PIN_D6 = IOMUX_PIN(0xff, 187), - MX31_PIN_D7 = IOMUX_PIN(0xff, 188), - MX31_PIN_D8 = IOMUX_PIN(0xff, 189), - MX31_PIN_D9 = IOMUX_PIN(0xff, 190), - MX31_PIN_D10 = IOMUX_PIN(0xff, 191), - MX31_PIN_D11 = IOMUX_PIN(0xff, 192), - MX31_PIN_D12 = IOMUX_PIN(0xff, 193), - MX31_PIN_D13 = IOMUX_PIN(0xff, 194), - MX31_PIN_D14 = IOMUX_PIN(0xff, 195), - MX31_PIN_D15 = IOMUX_PIN(0xff, 196), - MX31_PIN_NFRB = IOMUX_PIN(16, 197), - MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), - MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), - MX31_PIN_NFCLE = IOMUX_PIN(13, 200), - MX31_PIN_NFALE = IOMUX_PIN(12, 201), - MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), - MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), - MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), - MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), - MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), - MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), - MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), - MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), - MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), - MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), - MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), - MX31_PIN_CAS = IOMUX_PIN(0xff, 213), - MX31_PIN_RAS = IOMUX_PIN(0xff, 214), - MX31_PIN_RW = IOMUX_PIN(0xff, 215), - MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), - MX31_PIN_LBA = IOMUX_PIN(0xff, 217), - MX31_PIN_ECB = IOMUX_PIN(0xff, 218), - MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), - MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), - MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), - MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), - MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), - MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), - MX31_PIN_OE = IOMUX_PIN(0xff, 225), - MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), - MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), - MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), - MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), - MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), - MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), - MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), - MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), - MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), - MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), - MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), - MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), - MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), - MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), - MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), - MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), - MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), - MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), - MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), - MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), - MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), - MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), - MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), - MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), - MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), - MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), - MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), - MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), - MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), - MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), - MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), - MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), - MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), - MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), - MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), - MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), - MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), - MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), - MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), - MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), - MX31_PIN_A25 = IOMUX_PIN(0xff, 266), - MX31_PIN_A24 = IOMUX_PIN(0xff, 267), - MX31_PIN_A23 = IOMUX_PIN(0xff, 268), - MX31_PIN_A22 = IOMUX_PIN(0xff, 269), - MX31_PIN_A21 = IOMUX_PIN(0xff, 270), - MX31_PIN_A20 = IOMUX_PIN(0xff, 271), - MX31_PIN_A19 = IOMUX_PIN(0xff, 272), - MX31_PIN_A18 = IOMUX_PIN(0xff, 273), - MX31_PIN_A17 = IOMUX_PIN(0xff, 274), - MX31_PIN_A16 = IOMUX_PIN(0xff, 275), - MX31_PIN_A14 = IOMUX_PIN(0xff, 276), - MX31_PIN_A15 = IOMUX_PIN(0xff, 277), - MX31_PIN_A13 = IOMUX_PIN(0xff, 278), - MX31_PIN_A12 = IOMUX_PIN(0xff, 279), - MX31_PIN_A11 = IOMUX_PIN(0xff, 280), - MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), - MX31_PIN_A10 = IOMUX_PIN(0xff, 282), - MX31_PIN_A9 = IOMUX_PIN(0xff, 283), - MX31_PIN_A8 = IOMUX_PIN(0xff, 284), - MX31_PIN_A7 = IOMUX_PIN(0xff, 285), - MX31_PIN_A6 = IOMUX_PIN(0xff, 286), - MX31_PIN_A5 = IOMUX_PIN(0xff, 287), - MX31_PIN_A4 = IOMUX_PIN(0xff, 288), - MX31_PIN_A3 = IOMUX_PIN(0xff, 289), - MX31_PIN_A2 = IOMUX_PIN(0xff, 290), - MX31_PIN_A1 = IOMUX_PIN(0xff, 291), - MX31_PIN_A0 = IOMUX_PIN(0xff, 292), - MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), - MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), - MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), - MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), - MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), - MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), - MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), - MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), - MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), - MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), - MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), - MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), - MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), - MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), - MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), - MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), - MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), - MX31_PIN_SRX0 = IOMUX_PIN(34, 310), - MX31_PIN_STX0 = IOMUX_PIN(33, 311), - MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), - MX31_PIN_SRST0 = IOMUX_PIN(67, 313), - MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), - MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), - MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), - MX31_PIN_GPIO1_6 = IOMUX_PIN( 6, 317), - MX31_PIN_GPIO1_5 = IOMUX_PIN( 5, 318), - MX31_PIN_GPIO1_4 = IOMUX_PIN( 4, 319), - MX31_PIN_GPIO1_3 = IOMUX_PIN( 3, 320), - MX31_PIN_GPIO1_2 = IOMUX_PIN( 2, 321), - MX31_PIN_GPIO1_1 = IOMUX_PIN( 1, 322), - MX31_PIN_GPIO1_0 = IOMUX_PIN( 0, 323), - MX31_PIN_PWMO = IOMUX_PIN( 9, 324), - MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), - MX31_PIN_COMPARE = IOMUX_PIN( 8, 326), - MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), -}; - -/* - * Convenience values for use with mxc_iomux_mode() - * - * Format here is MX31_PIN_(pin name)__(function) - */ -#define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) -#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) -#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) -#define MX31_PIN_PC_BVD1__RXD5 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_CSPI1_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC) -#define MX31_PIN_BATT_LINE__OWIRE IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CS4__CS4 IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA3__SD1_DATA3 IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA2__SD1_DATA2 IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA1__SD1_DATA1 IOMUX_MODE(MX31_PIN_SD1_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) - -/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 - * cspi1_ss1*/ - -/* - * This function configures the pad value for a IOMUX pin. - */ -int imx_iomux_mode(unsigned int pin_mode); -void imx_iomux_set_pad(enum iomux_pins pin, u32 config); -void imx_iomux_set_gpr(enum iomux_gp_func gp, int en); - -#endif - - diff --git a/include/asm-arm/arch-imx/iomux-mx35.h b/include/asm-arm/arch-imx/iomux-mx35.h deleted file mode 100644 index 16a109a156..0000000000 --- a/include/asm-arm/arch-imx/iomux-mx35.h +++ /dev/null @@ -1,1268 +0,0 @@ -/* - * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option, NO_PAD_CTRL) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_IOMUX_MX35_H__ -#define __MACH_IOMUX_MX35_H__ - -#include <asm/arch/iomux-v3.h> - -/* - * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named - * GPIO_<unit>_<num> see also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH */ -#define MX35_PAD_CAPTURE__GPT_CAPIN1 IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__GPT_CMPOUT2 IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__CSPI2_SS1 IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__EPIT1_EPITO IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__CCM_CLK32K IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__GPIO1_4 IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL) - -#define MX35_PAD_COMPARE__GPT_CMPOUT1 IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__GPT_CAPIN2 IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__GPT_CMPOUT3 IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__EPIT2_EPITO IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__GPIO1_5 IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_WDOG_RST__WDOG_WDOG_B IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_WDOG_RST__GPIO1_6 IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_0__OWIRE_LINE IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__PWM_PWMO IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__CSPI1_SS2 IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO2_0__GPIO2_0 IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO3_0__GPIO3_0 IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_POR_B__CCM_POR_B IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CLKO__CCM_CLKO IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CLKO__GPIO1_8 IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL) - -#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_VSTBY__CCM_VSTBY IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_VSTBY__GPIO1_7 IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL) - -#define MX35_PAD_A0__EMI_EIM_DA_L_0 IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A1__EMI_EIM_DA_L_1 IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A2__EMI_EIM_DA_L_2 IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A3__EMI_EIM_DA_L_3 IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A4__EMI_EIM_DA_L_4 IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A5__EMI_EIM_DA_L_5 IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A6__EMI_EIM_DA_L_6 IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A7__EMI_EIM_DA_L_7 IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A8__EMI_EIM_DA_H_8 IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A9__EMI_EIM_DA_H_9 IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A10__EMI_EIM_DA_H_10 IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_MA10__EMI_MA10 IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A11__EMI_EIM_DA_H_11 IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A12__EMI_EIM_DA_H_12 IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A13__EMI_EIM_DA_H_13 IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A14__EMI_EIM_DA_H2_14 IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A15__EMI_EIM_DA_H2_15 IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A16__EMI_EIM_A_16 IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A17__EMI_EIM_A_17 IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A18__EMI_EIM_A_18 IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A19__EMI_EIM_A_19 IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A20__EMI_EIM_A_20 IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A21__EMI_EIM_A_21 IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A22__EMI_EIM_A_22 IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A23__EMI_EIM_A_23 IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A24__EMI_EIM_A_24 IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A25__EMI_EIM_A_25 IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD0__EMI_DRAM_D_0 IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1__EMI_DRAM_D_1 IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD2__EMI_DRAM_D_2 IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD3__EMI_DRAM_D_3 IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD4__EMI_DRAM_D_4 IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD5__EMI_DRAM_D_5 IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD6__EMI_DRAM_D_6 IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD7__EMI_DRAM_D_7 IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD8__EMI_DRAM_D_8 IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD9__EMI_DRAM_D_9 IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD10__EMI_DRAM_D_10 IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD11__EMI_DRAM_D_11 IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD12__EMI_DRAM_D_12 IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD13__EMI_DRAM_D_13 IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD14__EMI_DRAM_D_14 IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD15__EMI_DRAM_D_15 IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD16__EMI_DRAM_D_16 IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD17__EMI_DRAM_D_17 IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD18__EMI_DRAM_D_18 IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD19__EMI_DRAM_D_19 IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD20__EMI_DRAM_D_20 IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD21__EMI_DRAM_D_21 IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD22__EMI_DRAM_D_22 IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD23__EMI_DRAM_D_23 IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD24__EMI_DRAM_D_24 IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD25__EMI_DRAM_D_25 IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD26__EMI_DRAM_D_26 IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD27__EMI_DRAM_D_27 IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD28__EMI_DRAM_D_28 IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD29__EMI_DRAM_D_29 IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD30__EMI_DRAM_D_30 IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD31__EMI_DRAM_D_31 IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_EB0__EMI_EIM_EB0_B IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_EB1__EMI_EIM_EB1_B IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_OE__EMI_EIM_OE IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS0__EMI_EIM_CS0 IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS1__EMI_EIM_CS1 IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS1__EMI_NANDF_CE3 IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS2__EMI_EIM_CS2 IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS3__EMI_EIM_CS3 IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS4__EMI_EIM_CS4 IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS4__EMI_DTACK_B IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL) -#define MX35_PAD_CS4__EMI_NANDF_CE1 IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS4__GPIO1_20 IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS5__EMI_EIM_CS5 IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS5__CSPI2_SS2 IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL) -#define MX35_PAD_CS5__CSPI1_SS2 IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL) -#define MX35_PAD_CS5__EMI_NANDF_CE2 IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS5__GPIO1_21 IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL) - -#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NF_CE0__GPIO1_22 IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL) - -#define MX35_PAD_ECB__EMI_EIM_ECB IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LBA__EMI_EIM_LBA IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_BCLK__EMI_EIM_BCLK IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RW__EMI_EIM_RW IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RAS__EMI_DRAM_RAS IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CAS__EMI_DRAM_CAS IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDWE__EMI_DRAM_SDWE IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__GPIO2_18 IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__GPIO2_19 IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFALE__EMI_NANDF_ALE IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__USB_TOP_USBH2_STP IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__IPU_DISPB_CS0 IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__GPIO2_20 IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFCLE__EMI_NANDF_CLE IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__GPIO2_21 IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__IPU_DISPB_WR IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__GPIO2_22 IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFRB__EMI_NANDF_RB IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRB__IPU_DISPB_RD IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRB__GPIO2_23 IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D15__EMI_EIM_D_15 IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D14__EMI_EIM_D_14 IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D13__EMI_EIM_D_13 IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D12__EMI_EIM_D_12 IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D11__EMI_EIM_D_11 IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D10__EMI_EIM_D_10 IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D9__EMI_EIM_D_9 IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D8__EMI_EIM_D_8 IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D7__EMI_EIM_D_7 IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D6__EMI_EIM_D_6 IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D5__EMI_EIM_D_5 IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D4__EMI_EIM_D_4 IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3__EMI_EIM_D_3 IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D2__EMI_EIM_D_2 IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D1__EMI_EIM_D_1 IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D0__EMI_EIM_D_0 IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D8__IPU_CSI_D_8 IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D8__KPP_COL_0 IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D8__GPIO1_20 IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL) -#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D9__IPU_CSI_D_9 IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D9__KPP_COL_1 IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D9__GPIO1_21 IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL) -#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D10__IPU_CSI_D_10 IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D10__KPP_COL_2 IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D10__GPIO1_22 IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL) -#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D11__IPU_CSI_D_11 IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D11__KPP_COL_3 IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D11__GPIO1_23 IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D12__IPU_CSI_D_12 IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D12__KPP_ROW_0 IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D12__GPIO1_24 IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D13__IPU_CSI_D_13 IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D13__KPP_ROW_1 IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D13__GPIO1_25 IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D14__IPU_CSI_D_14 IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D14__KPP_ROW_2 IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D14__GPIO1_26 IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D15__IPU_CSI_D_15 IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D15__KPP_ROW_3 IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D15__GPIO1_27 IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_MCLK__GPIO1_28 IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_VSYNC__GPIO1_29 IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_HSYNC__GPIO1_30 IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_PIXCLK__GPIO1_31 IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C1_CLK__I2C1_SCL IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C1_CLK__GPIO2_24 IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C1_DAT__I2C1_SDA IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C1_DAT__GPIO2_25 IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C2_CLK__I2C2_SCL IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__CAN1_TXCAN IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__GPIO2_26 IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C2_DAT__I2C2_SDA IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__CAN1_RXCAN IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__GPIO2_27 IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD4__GPIO2_28 IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD4__GPIO2_29 IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK4__GPIO2_30 IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS4__GPIO2_31 IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD5__CSPI2_MOSI IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD5__GPIO1_0 IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL) -#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__CSPI2_MISO IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__GPIO1_1 IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__CSPI2_SCLK IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__GPIO1_2 IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS5__CSPI2_RDY IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS5__GPIO1_3 IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCKR__ESAI_SCKR IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCKR__GPIO1_4 IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL) -#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FSR__ESAI_FSR IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FSR__GPIO1_5 IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL) -#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_HCKR__ESAI_HCKR IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__CSPI2_SS0 IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__IPU_FLASH_STROBE IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__GPIO1_6 IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL) -#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCKT__ESAI_SCKT IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCKT__GPIO1_7 IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL) -#define MX35_PAD_SCKT__IPU_CSI_D_0 IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL) -#define MX35_PAD_SCKT__KPP_ROW_2 IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL) - -#define MX35_PAD_FST__ESAI_FST IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FST__GPIO1_8 IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL) -#define MX35_PAD_FST__IPU_CSI_D_1 IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL) -#define MX35_PAD_FST__KPP_ROW_3 IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL) - -#define MX35_PAD_HCKT__ESAI_HCKT IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__GPIO1_9 IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__IPU_CSI_D_2 IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__KPP_COL_3 IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__CSPI2_SS2 IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__CAN2_TXCAN IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__UART2_DTR IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__GPIO1_10 IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__CSPI2_SS3 IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__CAN2_RXCAN IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__UART2_DSR IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__GPIO1_11 IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__KPP_ROW_0 IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__I2C3_SCL IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__GPIO1_12 IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__KPP_ROW_1 IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__I2C3_SDA IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__GPIO1_13 IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__KPP_COL_0 IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX1__ESAI_TX1 IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__CCM_PMIC_RDY IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL) -#define MX35_PAD_TX1__CSPI1_SS2 IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL) -#define MX35_PAD_TX1__EMI_NANDF_CE3 IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__UART2_RI IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__GPIO1_14 IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__IPU_CSI_D_6 IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__KPP_COL_1 IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX0__ESAI_TX0 IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL) -#define MX35_PAD_TX0__CSPI1_SS3 IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__EMI_DTACK_B IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL) -#define MX35_PAD_TX0__UART2_DCD IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__GPIO1_15 IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__IPU_CSI_D_7 IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__KPP_COL_2 IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MOSI__GPIO1_16 IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MISO__GPIO1_17 IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__OWIRE_LINE IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__GPIO1_18 IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__PWM_PWMO IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__CCM_CLK32K IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__GPIO1_19 IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SCLK__GPIO3_4 IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RXD1__UART1_RXD_MUX IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD1__CSPI2_MOSI IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL) -#define MX35_PAD_RXD1__KPP_COL_4 IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD1__GPIO3_6 IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TXD1__UART1_TXD_MUX IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD1__CSPI2_MISO IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL) -#define MX35_PAD_TXD1__KPP_COL_5 IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD1__GPIO3_7 IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RTS1__UART1_RTS IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__CSPI2_SCLK IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS1__I2C3_SCL IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS1__IPU_CSI_D_0 IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS1__KPP_COL_6 IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__GPIO3_8 IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__EMI_NANDF_CE1 IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CTS1__UART1_CTS IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__CSPI2_RDY IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS1__I2C3_SDA IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS1__IPU_CSI_D_1 IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS1__KPP_COL_7 IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__GPIO3_9 IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__EMI_NANDF_CE2 IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RXD2__UART2_RXD_MUX IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD2__KPP_ROW_4 IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD2__GPIO3_10 IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL) - -#define MX35_PAD_TXD2__UART2_TXD_MUX IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL) -#define MX35_PAD_TXD2__KPP_ROW_5 IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD2__GPIO3_11 IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RTS2__UART2_RTS IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS2__CAN2_RXCAN IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS2__IPU_CSI_D_2 IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS2__KPP_ROW_6 IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__GPIO3_12 IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__UART3_RXD_MUX IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CTS2__UART2_CTS IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__CAN2_TXCAN IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__IPU_CSI_D_3 IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS2__KPP_ROW_7 IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__GPIO3_13 IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__UART3_TXD_MUX IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RTCK__ARM11P_TOP_RTCK IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TCK__SJC_TCK IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TMS__SJC_TMS IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TDI__SJC_TDI IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TDO__SJC_TDO IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TRSTB__SJC_TRSTB IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DE_B__SJC_DE_B IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SJC_MOD__SJC_MOD IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_PWR__GPIO3_14 IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL) - -#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_OC__GPIO3_15 IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD0__IPU_DISPB_DAT_0 IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD0__GPIO2_0 IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL) -#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD1__IPU_DISPB_DAT_1 IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD1__GPIO2_1 IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL) -#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD2__IPU_DISPB_DAT_2 IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD2__GPIO2_2 IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD3__IPU_DISPB_DAT_3 IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD3__GPIO2_3 IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL) -#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD4__IPU_DISPB_DAT_4 IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD4__GPIO2_4 IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD5__IPU_DISPB_DAT_5 IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD5__GPIO2_5 IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL) -#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD6__IPU_DISPB_DAT_6 IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD6__GPIO2_6 IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL) -#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD7__IPU_DISPB_DAT_7 IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD7__GPIO2_7 IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL) -#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD8__IPU_DISPB_DAT_8 IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD8__GPIO2_8 IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4 0, NO_PAD_CTRL) -#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD10__GPIO2_10 IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD11__IPU_DISPB_DAT_11 IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD11__GPIO2_11 IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL) -#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD12__IPU_DISPB_DAT_12 IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD12__GPIO2_12 IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL) -#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD13__IPU_DISPB_DAT_13 IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD13__GPIO2_13 IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL) -#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD14__IPU_DISPB_DAT_14 IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD14__GPIO2_14 IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD15__IPU_DISPB_DAT_15 IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD15__GPIO2_15 IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL) -#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD16__IPU_DISPB_DAT_16 IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__GPIO2_16 IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD17__IPU_DISPB_DAT_17 IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__IPU_DISPB_CS2 IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__GPIO2_17 IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD18__IPU_DISPB_DAT_18 IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL) -#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL) -#define MX35_PAD_LD18__ESDHC3_CMD IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__GPIO3_24 IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD19__IPU_DISPB_DAT_19 IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__IPU_DISPB_BCLK IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__IPU_DISPB_CS1 IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__ESDHC3_CLK IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__GPIO3_25 IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD20__IPU_DISPB_DAT_20 IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__IPU_DISPB_CS0 IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__IPU_DISPB_SD_CLK IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__ESDHC3_DAT0 IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__GPIO3_26 IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD21__IPU_DISPB_DAT_21 IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__IPU_DISPB_PAR_RS IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__IPU_DISPB_SER_RS IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__ESDHC3_DAT1 IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__USB_TOP_USBOTG_STP IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__GPIO3_27 IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD22__IPU_DISPB_DAT_22 IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__IPU_DISPB_WR IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__IPU_DISPB_SD_D_I IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__ESDHC3_DAT2 IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__GPIO3_28 IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__ARM11P_TOP_TRCTL IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD23__IPU_DISPB_DAT_23 IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__IPU_DISPB_RD IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL) -#define MX35_PAD_LD23__ESDHC3_DAT3 IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__GPIO3_29 IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__ARM11P_TOP_TRCLK IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__GPIO3_30 IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__GPIO3_31 IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__GPIO1_0 IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CONTRAST__GPIO1_1 IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL) -#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__GPIO1_2 IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__GPIO1_3 IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__GPIO1_4 IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__GPIO1_5 IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__MSHC_SCLK IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__GPIO1_6 IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__MSHC_BS IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__GPIO1_7 IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__GPIO1_8 IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__GPIO1_9 IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__GPIO1_10 IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__GPIO1_11 IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__I2C3_SCL IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__GPIO2_0 IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL) - -#define MX35_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__I2C3_SDA IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__GPIO2_1 IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__GPIO2_2 IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__GPIO2_3 IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__UART3_RTS IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__CAN1_RXCAN IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__GPIO2_4 IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__UART3_CTS IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__CAN1_TXCAN IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__GPIO2_5 IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL) - -#define MX35_PAD_ATA_CS0__ATA_CS0 IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__CSPI1_SS3 IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__GPIO2_6 IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_CS1__ATA_CS1 IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__CSPI2_SS0 IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__GPIO2_7 IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DIOR__ATA_DIOR IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__CSPI2_SS1 IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__GPIO2_8 IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DIOW__ATA_DIOW IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__CSPI2_MOSI IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__GPIO2_9 IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DMACK__ATA_DMACK IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__CSPI2_MISO IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__GPIO2_10 IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_RESET_B__ATA_RESET_B IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__CSPI2_RDY IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__GPIO2_11 IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_IORDY__ATA_IORDY IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__GPIO2_12 IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA0__ATA_DATA_0 IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__GPIO2_13 IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA1__ATA_DATA_1 IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__GPIO2_14 IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA2__ATA_DATA_2 IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__GPIO2_15 IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA3__ATA_DATA_3 IOMUX_PAD(0x6e8, 0x288, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__ESDHC3_CLK IOMUX_PAD(0x6e8, 0x288, 1, 0x814, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x6e8, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__CSPI2_SCLK IOMUX_PAD(0x6e8, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__GPIO2_16 IOMUX_PAD(0x6e8, 0x288, 5, 0x884, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 IOMUX_PAD(0x6e8, 0x288, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 IOMUX_PAD(0x6e8, 0x288, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA4__ATA_DATA_4 IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__ESDHC3_CMD IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__GPIO2_17 IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA5__ATA_DATA_5 IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__GPIO2_18 IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA6__ATA_DATA_6 IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__CAN1_TXCAN IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__UART1_DTR IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__GPIO2_19 IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA7__ATA_DATA_7 IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__CAN1_RXCAN IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__UART1_DSR IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__GPIO2_20 IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA8__ATA_DATA_8 IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__UART3_RTS IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__UART1_RI IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__GPIO2_21 IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA9__ATA_DATA_9 IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__UART3_CTS IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__UART1_DCD IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__GPIO2_22 IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA10__ATA_DATA_10 IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__GPIO2_23 IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA11__ATA_DATA_11 IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__GPIO2_24 IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA12__ATA_DATA_12 IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA12__I2C3_SCL IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA12__GPIO2_25 IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA13__ATA_DATA_13 IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA13__I2C3_SDA IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA13__GPIO2_26 IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA14__ATA_DATA_14 IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__KPP_ROW_0 IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__GPIO2_27 IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA15__ATA_DATA_15 IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__KPP_ROW_1 IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__GPIO2_28 IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_INTRQ__ATA_INTRQ IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__GPIO2_29 IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DMARQ__ATA_DMARQ IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__KPP_COL_0 IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__GPIO2_31 IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DA0__ATA_DA_0 IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__KPP_COL_1 IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__GPIO3_0 IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DA1__ATA_DA_1 IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__KPP_COL_2 IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__GPIO3_1 IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DA2__ATA_DA_2 IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__KPP_COL_3 IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__GPIO3_2 IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_MLB_CLK__MLB_MLBCLK IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_MLB_CLK__GPIO3_3 IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_MLB_DAT__MLB_MLBDAT IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_MLB_DAT__GPIO3_4 IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL) - -#define MX35_PAD_MLB_SIG__MLB_MLBSIG IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_MLB_SIG__GPIO3_5 IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__GPIO3_6 IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__GPIO3_7 IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__UART3_RTS IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__GPIO3_8 IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_COL__FEC_COL IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__ESDHC1_DAT7 IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__UART3_CTS IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__CSPI2_RDY IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__GPIO3_9 IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__PWM_PWMO IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__UART3_DTR IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__GPIO3_10 IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__UART3_DSR IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__GPIO3_11 IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__UART3_RI IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__GPIO3_12 IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__CAN2_TXCAN IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__UART3_DCD IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__GPIO3_13 IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__IPU_DISPB_WR IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__CAN2_RXCAN IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__GPIO3_14 IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__GPIO3_15 IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__GPIO3_16 IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL) - -#define MX35_PAD_FEC_CRS__FEC_CRS IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__KPP_COL_5 IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__GPIO3_17 IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__KPP_COL_6 IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__GPIO3_18 IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__KPP_COL_7 IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__GPIO3_19 IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__GPIO3_20 IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__GPIO3_21 IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__GPIO3_22 IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__GPIO3_23 IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TEST_MODE__TCU_TEST_MODE IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - - -#endif /* __MACH_IOMUX_MX35_H__ */ - diff --git a/include/asm-arm/arch-imx/iomux-v3.h b/include/asm-arm/arch-imx/iomux-v3.h deleted file mode 100644 index 8b2f1ae7f9..0000000000 --- a/include/asm-arm/arch-imx/iomux-v3.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_IOMUX_V3_H__ -#define __MACH_IOMUX_V3_H__ - -/* - * build IOMUX_PAD structure - * - * This iomux scheme is based around pads, which are the physical balls - * on the processor. - * - * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls - * things like driving strength and pullup/pulldown. - * - Each pad can have but not necessarily does have an output routing register - * (IOMUXC_SW_MUX_CTL_PAD_x). - * - Each pad can have but not necessarily does have an input routing register - * (IOMUXC_x_SELECT_INPUT) - * - * The three register sets do not have a fixed offset to each other, - * hence we order this table by pad control registers (which all pads - * have) and put the optional i/o routing registers into additional - * fields. - * - * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named - * GPIO_<unit>_<num> - * - */ - -struct pad_desc { - unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */ - unsigned mux_mode:8; - unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */ -#define NO_PAD_CTRL (1 << 16) - unsigned pad_ctrl:17; - unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */ - unsigned select_input:3; -}; - -#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \ - _select_input, _pad_ctrl) \ - { \ - .mux_ctrl_ofs = _mux_ctrl_ofs, \ - .mux_mode = _mux_mode, \ - .pad_ctrl_ofs = _pad_ctrl_ofs, \ - .pad_ctrl = _pad_ctrl, \ - .select_input_ofs = _select_input_ofs, \ - .select_input = _select_input, \ - } - -/* - * Use to set PAD control - */ -#define PAD_CTL_DRIVE_VOLTAGE_3_3_V 0 -#define PAD_CTL_DRIVE_VOLTAGE_1_8_V 1 - -#define PAD_CTL_NO_HYSTERESIS 0 -#define PAD_CTL_HYSTERESIS 1 - -#define PAD_CTL_PULL_DISABLED 0x0 -#define PAD_CTL_PULL_KEEPER 0xa -#define PAD_CTL_PULL_DOWN_100K 0xc -#define PAD_CTL_PULL_UP_47K 0xd -#define PAD_CTL_PULL_UP_100K 0xe -#define PAD_CTL_PULL_UP_22K 0xf - -#define PAD_CTL_OUTPUT_CMOS 0 -#define PAD_CTL_OUTPUT_OPEN_DRAIN 1 - -#define PAD_CTL_DRIVE_STRENGTH_NORM 0 -#define PAD_CTL_DRIVE_STRENGTH_HIGH 1 -#define PAD_CTL_DRIVE_STRENGTH_MAX 2 - -#define PAD_CTL_SLEW_RATE_SLOW 0 -#define PAD_CTL_SLEW_RATE_FAST 1 - -/* - * setups a single pad: - * - reserves the pad so that it is not claimed by another driver - * - setups the iomux according to the configuration - */ -int mxc_iomux_v3_setup_pad(struct pad_desc *pad); - -/* - * setups mutliple pads - * convenient way to call the above function with tables - */ -int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); - -#endif /* __MACH_IOMUX_V3_H__*/ diff --git a/include/asm-arm/arch-imx/pmic.h b/include/asm-arm/arch-imx/pmic.h deleted file mode 100644 index e9a951bd38..0000000000 --- a/include/asm-arm/arch-imx/pmic.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __ASM_ARCH_PMIC_H -#define __ASM_ARCH_PMIC_H - -/* The only function the PMIC driver currently exports. It's purpose - * is to adjust the switchers to 1.45V in order to speed up the CPU - * to 400MHz. This is probably board dependent, so we have to think - * about a proper API for the PMIC - */ -int pmic_power(void); - -#endif /* __ASM_ARCH_PMIC_H */ diff --git a/include/asm-arm/arch-imx/spi.h b/include/asm-arm/arch-imx/spi.h deleted file mode 100644 index 08be445e8e..0000000000 --- a/include/asm-arm/arch-imx/spi.h +++ /dev/null @@ -1,27 +0,0 @@ - -#ifndef __MACH_SPI_H_ -#define __MACH_SPI_H_ - -/* - * struct spi_imx_master - device.platform_data for SPI controller devices. - * @chipselect: Array of chipselects for this master. Numbers >= 0 mean gpio - * pins, numbers < 0 mean internal CSPI chipselects according - * to MXC_SPI_CS(). Normally you want to use gpio based chip - * selects as the CSPI module tries to be intelligent about - * when to assert the chipselect: The CSPI module deasserts the - * chipselect once it runs out of input data. The other problem - * is that it is not possible to mix between high active and low - * active chipselects on one single bus using the internal - * chipselects. Unfortunately Freescale decided to put some - * chipselects on dedicated pins which are not usable as gpios, - * so we have to support the internal chipselects. - * @num_chipselect: ARRAY_SIZE(chipselect) - */ -struct spi_imx_master { - int *chipselect; - int num_chipselect; -}; - -#define MXC_SPI_CS(no) ((no) - 32) - -#endif /* __MACH_SPI_H_*/ diff --git a/include/asm-arm/arch-imx/u-boot.lds.h b/include/asm-arm/arch-imx/u-boot.lds.h deleted file mode 100644 index 52eb458f0f..0000000000 --- a/include/asm-arm/arch-imx/u-boot.lds.h +++ /dev/null @@ -1,9 +0,0 @@ - -#define PRE_IMAGE .pre_image : { \ - KEEP(*(.flash_header_start*)) \ - . = ALIGN(0x400); \ - KEEP(*(.flash_header*)) \ - KEEP(*(.dcd_entry*)) \ - KEEP(*(.image_len*)) \ - } - diff --git a/include/asm-arm/arch-netx/netx-cm.h b/include/asm-arm/arch-netx/netx-cm.h deleted file mode 100644 index 37cf76d1f9..0000000000 --- a/include/asm-arm/arch-netx/netx-cm.h +++ /dev/null @@ -1,32 +0,0 @@ - -#ifndef __AT_CM_USERAREAS_H__ -#define __AT_CM_USERAREAS_H__ - -int netx_cm_init(void); - -struct netx_cm_userarea_1 { - unsigned short signature; /* configuration block signature */ - unsigned short version; /* version information */ - unsigned short crc16; /* crc16 checksum over all 3 areas, including the reserved blocks */ - unsigned char mac[4][6]; /* mac addresses */ - unsigned char reserved[2]; /* reserved, must be 0 */ -}; - -struct netx_cm_userarea_2 { - unsigned long sdram_size; /* sdram size in bytes */ - unsigned long sdram_control; /* sdram control register value (sdram_general_ctrl) */ - unsigned long sdram_timing; /* sdram timing register value (sdram_timing_ctrl) */ - unsigned char reserved0[20]; /* reserved, must be 0 */ -}; - -struct netx_cm_userarea_3 { - unsigned char reserved[32]; /* reserved, must be 0 */ -}; - -struct netx_cm_userarea { - struct netx_cm_userarea_1 area_1; - struct netx_cm_userarea_2 area_2; - struct netx_cm_userarea_3 area_3; -}; - -#endif /* __AT_CM_USERAREAS_H__ */ diff --git a/include/asm-arm/arch-netx/netx-eth.h b/include/asm-arm/arch-netx/netx-eth.h deleted file mode 100644 index 654cfe73d3..0000000000 --- a/include/asm-arm/arch-netx/netx-eth.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _ASM_ARCH_NETX_ETH_H -#define _ASM_ARCH_NETX_ETH_H - -struct netx_eth_platform_data { - int xcno; -}; - -#endif /* _ASM_ARCH_NETX_ETH_H */ - diff --git a/include/asm-arm/arch-netx/netx-regs.h b/include/asm-arm/arch-netx/netx-regs.h deleted file mode 100644 index c2278cdc48..0000000000 --- a/include/asm-arm/arch-netx/netx-regs.h +++ /dev/null @@ -1,322 +0,0 @@ -/* - * include/asm-arm/arch-netx/netx-regs.h - * - * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_NETX_REGS_H -#define __ASM_ARCH_NETX_REGS_H - -#define NETX_IO_PHYS 0x00100000 -#define io_p2v(x) (x) -#define __REG(base,ofs) (*((volatile unsigned long *)(io_p2v(base) + ofs))) - -#define XPEC_MEM_SIZE 0x4000 -#define XMAC_MEM_SIZE 0x1000 -#define SRAM_MEM_SIZE 0x8000 - -/* offsets relative to the beginning of the io space */ -#define NETX_OFS_SYSTEM 0x00000 -#define NETX_OFS_MEMCR 0x00100 -#define NETX_OFS_DPRAM 0x03000 -#define NETX_OFS_GPIO 0x00800 -#define NETX_OFS_PIO 0x00900 -#define NETX_OFS_UART0 0x00a00 -#define NETX_OFS_UART1 0x00a40 -#define NETX_OFS_UART2 0x00a80 -#define NETX_OF_MIIMU 0x00b00 -#define NETX_OFS_SPI 0x00c00 -#define NETX_OFS_I2C 0x00d00 -#define NETX_OFS_SYSTIME 0x01100 -#define NETX_OFS_RTC 0x01200 -#define NETX_OFS_LCD 0x04000 -#define NETX_OFS_USB 0x20000 -#define NETX_OFS_XMAC0 0x60000 -#define NETX_OFS_XMAC1 0x61000 -#define NETX_OFS_XMAC2 0x62000 -#define NETX_OFS_XMAC3 0x63000 -#define NETX_OFS_XMAC(no) (0x60000 + (no) * 0x1000) -#define NETX_OFS_PFIFO 0x64000 -#define NETX_OFS_XPEC0 0x70000 -#define NETX_OFS_XPEC1 0x74000 -#define NETX_OFS_XPEC2 0x78000 -#define NETX_OFS_XPEC3 0x7c000 -#define NETX_OFS_XPEC(no) (0x70000 + (no) * 0x4000) -#define NETX_OFS_VIC 0xff000 - -#define NETX_PA_SYSTEM (NETX_IO_PHYS + NETX_OFS_SYSTEM) -#define NETX_PA_MEMCR (NETX_IO_PHYS + NETX_OFS_MEMCR) -#define NETX_PA_DPRAM (NETX_IO_PHYS + NETX_OFS_DPRAM) -#define NETX_PA_GPIO (NETX_IO_PHYS + NETX_OFS_GPIO) -#define NETX_PA_PIO (NETX_IO_PHYS + NETX_OFS_PIO) -#define NETX_PA_UART0 (NETX_IO_PHYS + NETX_OFS_UART0) -#define NETX_PA_UART1 (NETX_IO_PHYS + NETX_OFS_UART1) -#define NETX_PA_UART2 (NETX_IO_PHYS + NETX_OFS_UART2) -#define NETX_PA_MIIMU (NETX_IO_PHYS + NETX_OF_MIIMU) -#define NETX_PA_SPI (NETX_IO_PHYS + NETX_OFS_SPI) -#define NETX_PA_I2C (NETX_IO_PHYS + NETX_OFS_I2C) -#define NETX_PA_SYSTIME (NETX_IO_PHYS + NETX_OFS_SYSTIME) -#define NETX_PA_RTC (NETX_IO_PHYS + NETX_OFS_RTC) -#define NETX_PA_LCD (NETX_IO_PHYS + NETX_OFS_LCD) -#define NETX_PA_USB (NETX_IO_PHYS + NETX_OFS_USB) -#define NETX_PA_XMAC0 (NETX_IO_PHYS + NETX_OFS_XMAC0) -#define NETX_PA_XMAC1 (NETX_IO_PHYS + NETX_OFS_XMAC1) -#define NETX_PA_XMAC2 (NETX_IO_PHYS + NETX_OFS_XMAC2) -#define NETX_PA_XMAC3 (NETX_IO_PHYS + NETX_OFS_XMAC3) -#define NETX_PA_XMAC(no) (NETX_IO_PHYS + NETX_OFS_XMAC(no)) -#define NETX_PA_PFIFO (NETX_IO_PHYS + NETX_OFS_PFIFO) -#define NETX_PA_XPEC0 (NETX_IO_PHYS + NETX_OFS_XPEC0) -#define NETX_PA_XPEC1 (NETX_IO_PHYS + NETX_OFS_XPEC1) -#define NETX_PA_XPEC2 (NETX_IO_PHYS + NETX_OFS_XPEC2) -#define NETX_PA_XPEC3 (NETX_IO_PHYS + NETX_OFS_XPEC3) -#define NETX_PA_XPEC(no) (NETX_IO_PHYS + NETX_OFS_XPEC(no)) -#define NETX_PA_VIC (NETX_IO_PHYS + NETX_OFS_VIC) - -/********************************* - * System functions * - *********************************/ - -#define SYSTEM_REG(x) __REG(NETX_PA_SYSTEM, (x)) -#define SYSTEM_BOO_SR 0x00 -#define SYSTEM_IOC_CR 0x04 -#define SYSTEM_IOC_MR 0x08 -#define SYSTEM_RES_CR 0x0c -#define SYSTEM_PHY_CONTROL 0x10 -#define SYSTEM_REV 0x34 -#define SYSTEM_IOC_ACCESS_KEY 0x70 -#define SYSTEM_WDG_TR 0x200 -#define SYSTEM_WDG_CTR 0x204 -#define SYSTEM_WDG_IRQ_TIMEOUT 0x208 -#define SYSTEM_WDG_RES_TIMEOUT 0x20c - -#define PHY_CONTROL_RESET (1<<31) -#define PHY_CONTROL_SIM_BYP (1<<30) -#define PHY_CONTROL_CLK_XLATIN (1<<29) -#define PHY_CONTROL_PHY1_EN (1<<21) -#define PHY_CONTROL_PHY1_NP_MSG_CODE -#define PHY_CONTROL_PHY1_AUTOMDIX (1<<17) -#define PHY_CONTROL_PHY1_FIXMODE (1<<16) -#define PHY_CONTROL_PHY1_MODE(mode) (((mode) & 0x7) << 13) -#define PHY_CONTROL_PHY0_EN (1<<12) -#define PHY_CONTROL_PHY0_NP_MSG_CODE -#define PHY_CONTROL_PHY0_AUTOMDIX (1<<8) -#define PHY_CONTROL_PHY0_FIXMODE (1<<7) -#define PHY_CONTROL_PHY0_MODE(mode) (((mode) & 0x7) << 4) -#define PHY_CONTROL_PHY_ADDRESS(adr) ((adr) & 0xf) - -#define PHY_MODE_10BASE_T_HALF 0 -#define PHY_MODE_10BASE_T_FULL 1 -#define PHY_MODE_100BASE_TX_FX_FULL 2 -#define PHY_MODE_100BASE_TX_FX_HALF 3 -#define PHY_MODE_100BASE_TX_HALF 4 -#define PHY_MODE_REPEATER 5 -#define PHY_MODE_POWER_DOWN 6 -#define PHY_MODE_ALL 7 - -/********************************* - * Vector interrupt controller * - *********************************/ - -/* Registers */ -#define VIC_REG(x) __REG(NETX_PA_VIC, (x)) -#define VIC_IRQ_STATUS 0x00 -#define VIC_FIQ_STATUS 0x04 -#define VIC_IRQ_RAW_STATUS 0x08 -#define VIC_INT_SELECT 0x0C /* 1 = FIQ, 0 = IRQ */ -#define VIC_IRQ_ENABLE 0x10 /* 1 = enable, 0 = disable */ -#define VIC_IRQ_ENABLE_CLEAR 0x14 -#define VIC_IRQ_SOFT 0x18 -#define VIC_IRQ_SOFT_CLEAR 0x1C -#define VIC_PROTECT 0x20 -#define VIC_VECT_ADDR 0x30 -#define VIC_DEF_VECT_ADDR 0x34 -#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */ -#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */ -#define VIC_ITCR 0x300 /* VIC test control register */ - -/* Bits */ -#define VECT_CNTL_ENABLE (1 << 5) - -/******************************* - * GPIO and timer module * - *******************************/ - -/* Registers */ -#define GPIO_REG(x) __REG(NETX_PA_GPIO, (x)) -#define GPIO_CFG(gpio) (0x0 + ((gpio)<<2)) -#define GPIO_THRESHOLD_CAPTURE(gpio) (0x40 + ((gpio)<<2)) -#define GPIO_COUNTER_CTRL(counter) (0x80 + ((counter)<<2)) -#define GPIO_COUNTER_MAX(counter) (0x94 + ((counter)<<2)) -#define GPIO_COUNTER_CURRENT(counter) (0xa8 + ((counter)<<2)) -#define GPIO_IRQ_ENABLE (0xbc) -#define GPIO_IRQ_DISABLE (0xc0) -#define GPIO_SYSTIME_NS_CMP (0xc4) -#define GPIO_LINE (0xc8) -#define GPIO_IRQ (0xd0) - -/* Bits */ -#define CFG_IOCFG_GP_INPUT (0x0) -#define CFG_IOCFG_GP_OUTPUT (0x1) -#define CFG_IOCFG_GP_UART (0x2) -#define CFG_INV (1<<2) -#define CFG_MODE_INPUT_READ (0<<3) -#define CFG_MODE_INPUT_CAPTURE_CONT_RISING (1<<3) -#define CFG_MODE_INPUT_CAPTURE_ONCE_RISING (2<<3) -#define CFG_MODE_INPUT_CAPTURE_HIGH_LEVEL (3<<3) -#define CFG_COUNT_REF_COUNTER0 (0<<5) -#define CFG_COUNT_REF_COUNTER1 (1<<5) -#define CFG_COUNT_REF_COUNTER2 (2<<5) -#define CFG_COUNT_REF_COUNTER3 (3<<5) -#define CFG_COUNT_REF_COUNTER4 (4<<5) -#define CFG_COUNT_REF_SYSTIME (7<<5) - -#define COUNTER_CTRL_RUN (1<<0) -#define COUNTER_CTRL_SYM (1<<1) -#define COUNTER_CTRL_ONCE (1<<2) -#define COUNTER_CTRL_IRQ_EN (1<<3) -#define COUNTER_CTRL_CNT_EVENT (1<<4) -#define COUNTER_CTRL_RST_EN (1<<5) -#define COUNTER_CTRL_SEL_EVENT (1<<6) -#define COUNTER_CTRL_GPIO_REF /* FIXME */ - -#define GPIO_BIT(gpio) (1<<(gpio)) -#define COUNTER_BIT(counter) ((1<<16)<<(counter)) - -/******************************* - * PIO * - *******************************/ - -/* Registers */ -#define NETX_PIO_REG(ofs) __REG(NETX_PA_PIO, ofs) -#define NETX_PIO_INPIO NETX_PIO_REG(0x0) -#define NETX_PIO_OUTPIO NETX_PIO_REG(0x4) -#define NETX_PIO_OEPIO NETX_PIO_REG(0x8) - -/******************************* - * MII Unit * - *******************************/ -#define MIIMU_REG __REG(NETX_PA_MIIMU, 0) -/* Bits */ -#define MIIMU_SNRDY (1<<0) -#define MIIMU_PREAMBLE (1<<1) -#define MIIMU_OPMODE_WRITE (1<<2) -#define MIIMU_MDC_PERIOD (1<<3) -#define MIIMU_PHY_NRES (1<<4) -#define MIIMU_RTA (1<<5) -#define MIIMU_REGADDR(adr) (((adr) & 0x1f) << 6) -#define MIIMU_PHYADDR(adr) (((adr) & 0x1f) << 11) -#define MIIMU_DATA(data) (((data) & 0xffff) << 16) - -/******************************* - * xmac / xpec * - *******************************/ -#define XPEC_REG(no, reg) __REG(NETX_PA_XPEC(no), (reg)) -#define XPEC_R0 0x00 -#define XPEC_R1 0x04 -#define XPEC_R2 0x08 -#define XPEC_R3 0x0c -#define XPEC_R4 0x10 -#define XPEC_R5 0x14 -#define XPEC_R6 0x18 -#define XPEC_R7 0x1c -#define XPEC_RANGE01 0x20 -#define XPEC_RANGE23 0x24 -#define XPEC_RANGE45 0x28 -#define XPEC_RANGE67 0x2c -#define XPEC_PC 0x48 -#define XPEC_TIMER(timer) (0x30 + ((timer)<<2)) -#define XPEC_IRQ 0x8c -#define XPEC_SYSTIME_NS 0x90 -#define XPEC_FIFO_DATA 0x94 -#define XPEC_SYSTIME_S 0x98 -#define XPEC_ADC 0x9c -#define XPEC_URX_COUNT 0x40 -#define XPEC_UTX_COUNT 0x44 -#define XPEC_PC 0x48 -#define XPEC_ZERO 0x4c -#define XPEC_STATCFG 0x50 -#define XPEC_EC_MASKA 0x54 -#define XPEC_EC_MASKB 0x58 -#define XPEC_EC_MASK0 0x5c -#define XPEC_EC_MASK8 0x7c -#define XPEC_EC_MASK9 0x80 -#define XPEC_XPU_HOLD_PC 0x100 -#define XPEC_RAM_START 0x2000 - -#define XPU_HOLD_PC (1<<0) - -#define XMAC_REG(no, reg) __REG(NETX_PA_XMAC(no), (reg)) -#define XMAC_RPU_PROGRAM_START 0x000 -#define XMAC_RPU_PROGRAM_END 0x3ff -#define XMAC_TPU_PROGRAM_START 0x400 -#define XMAC_TPU_PROGRAM_END 0x7ff -#define XMAC_RPU_HOLD_PC 0xa00 -#define XMAC_TPU_HOLD_PC 0xa04 - -#define RPU_HOLD_PC (1<<15) -#define TPU_HOLD_PC (1<<15) -/******************************* - * Pointer FIFO * - *******************************/ -#define PFIFO_REG(x) __REG(NETX_PA_PFIFO, (x)) -#define PFIFO_BASE(pfifo) (0x00 + ((pfifo)<<2) ) -#define PFIFO_BORDER_BASE(pfifo) (0x80 + ((pfifo)<<2) ) -#define PFIFO_RESET 0x100 -#define PFIFO_FULL 0x104 -#define PFIFO_EMPTY 0x108 -#define PFIFO_OVEFLOW 0x10c -#define PFIFO_UNDERRUN 0x110 -#define PFIFO_FILL_LEVEL(pfifo) (0x180 + ((pfifo)<<2)) - -/******************************* - * Dual Port Memory * - *******************************/ - -/* Registers */ -#define NETX_DPMAS_REG(ofs) __REG(NETX_PA_DPMAS, (ofs)) -#define NETX_DPMAS_IF_CONF0_REG NETX_DPMAS_REG(0x608) -#define NETX_DPMAS_IF_CONF1_REG NETX_DPMAS_REG(0x60c) -#define NETX_DPMAS_EXT_CONFIG0_REG NETX_DPMAS_REG(0x610) -#define NETX_DPMAS_EXT_CONFIG1_REG NETX_DPMAS_REG(0x614) -#define NETX_DPMAS_EXT_CONFIG2_REG NETX_DPMAS_REG(0x618) -#define NETX_DPMAS_EXT_CONFIG3_REG NETX_DPMAS_REG(0x61c) -#define NETX_DPMAS_IO_MODE0_REG NETX_DPMAS_REG(0x620) /* I/O 32..63 */ -#define NETX_DPMAS_DRV_EN0_REG NETX_DPMAS_REG(0x624) -#define NETX_DPMAS_DATA0_REG NETX_DPMAS_REG(0x628) -#define NETX_DPMAS_IO_MODE1_REG NETX_DPMAS_REG(0x630) /* I/O 64..84 */ -#define NETX_DPMAS_DRV_EN1_REG NETX_DPMAS_REG(0x634) -#define NETX_DPMAS_DATA1_REG NETX_DPMAS_REG(0x638) - -/* Bits */ -#define IF_CONF0_HIF_DISABLED (0<<28) -#define IF_CONF0_HIF_EXT_BUS (1<<28) -#define IF_CONF0_HIF_UP_8BIT (2<<28) -#define IF_CONF0_HIF_UP_16BIT (3<<28) -#define IF_CONF0_HIF_IO (4<<28) - -#define IO_MODE1_SAMPLE_NPOR (0<<30) -#define IO_MODE1_SAMPLE_100MHZ (1<<30) -#define IO_MODE1_SAMPLE_NPIO36 (2<<30) -#define IO_MODE1_SAMPLE_PIO36 (3<<30) - -/******************************* - * I2C * - *******************************/ -#define NETX_I2C_REG(ofs) __REG(NETX_PA_I2C, (ofs)) -#define NETX_I2C_CTRL_REG NETX_I2C_REG(0x0) -#define NETX_I2C_DATA_REG NETX_I2C_REG(0x4) - -#endif /* __ASM_ARCH_NETX_REGS_H */ diff --git a/include/asm-arm/arch-netx/netx-xc.h b/include/asm-arm/arch-netx/netx-xc.h deleted file mode 100644 index 060a9b3b02..0000000000 --- a/include/asm-arm/arch-netx/netx-xc.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_ARCH_NETX_XC_H -#define __ASM_ARCH_NETX_XC_H - -int loadxc(int); - -#endif diff --git a/include/asm-arm/arch-omap/clocks.h b/include/asm-arm/arch-omap/clocks.h deleted file mode 100644 index 042f777ac2..0000000000 --- a/include/asm-arm/arch-omap/clocks.h +++ /dev/null @@ -1,48 +0,0 @@ -/** - * @file - * @brief Generic Clock wrapper header. - * - * FileName: include/asm-arm/arch-omap/clocks.h - * - * This includes each of the architecture Clock definitions under it. - * - * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz - */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __OMAP_CLOCKS_H_ -#define __OMAP_CLOCKS_H_ - -#define LDELAY 12000000 - -/* Standard defines for Various clocks */ -#define S12M 12000000 -#define S13M 13000000 -#define S19_2M 19200000 -#define S24M 24000000 -#define S26M 26000000 -#define S38_4M 38400000 - -#ifdef CONFIG_ARCH_OMAP3 -#include <asm/arch/omap3-clock.h> -#endif - -#endif /* __OMAP_CLOCKS_H_ */ diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h deleted file mode 100644 index 8301ead5f0..0000000000 --- a/include/asm-arm/arch-omap/control.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * @file - * @brief This file contains the Control register defines - * - * FileName: include/asm-arm/arch-omap/control.h - * - * Originally from Linux kernel: - * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz - * include/asm-arm/arch-omap/omap34xx.h - */ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * Copyright (C) 2007 Texas Instruments, <www.ti.com> - * Copyright (C) 2007 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_OMAP_CONTROL_H -#define __ASM_ARCH_OMAP_CONTROL_H - -/** - * Control register defintion which unwraps to the real register - * offset + base address - */ -#define CONTROL_REG(REGNAME) (OMAP_CTRL_BASE + CONTROL_##REGNAME) - -#define CONTROL_SCALABLE_OMAP_STATUS (0x44C) -#define CONTROL_SCALABLE_OMAP_OCP (0x534) -#define CONTROL_SCRATCHPAD_BASE (0x910) -#define CONTROL_SCRATCHPAD_ROM_BASE (0x860) -#define CONTROL_STATUS (0x2f0) -#define CONTROL_SYSCONFIG (0x010) -#define CONTROL_DEVCONF0 (0x274) -#define CONTROL_DEVCONF1 (0x2D8) -#define CONTROL_IVA2_BOOTMOD (0x404) -#define CONTROL_IVA2_BOOTADDR (0x400) -#define CONTROL_PBIAS_1 (0x520) -#define CONTROL_GENERAL_PURPOSE_STATUS (0x2F4) -#define CONTROL_MEM_DFTRW0 (0x278) -#define CONTROL_MEM_DFTRW1 (0x27C) -#define CONTROL_MSUSPENDMUX_0 (0x290) -#define CONTROL_MSUSPENDMUX_1 (0x294) -#define CONTROL_MSUSPENDMUX_2 (0x298) -#define CONTROL_MSUSPENDMUX_3 (0x29C) -#define CONTROL_MSUSPENDMUX_4 (0x2A0) -#define CONTROL_MSUSPENDMUX_5 (0x2A4) -#define CONTROL_SEC_CTRL (0x2B0) -#define CONTROL_CSIRXFE (0x2DC) -#define CONTROL_DEBOBS_0 (0x420) -#define CONTROL_DEBOBS_1 (0x424) -#define CONTROL_DEBOBS_2 (0x428) -#define CONTROL_DEBOBS_3 (0x42C) -#define CONTROL_DEBOBS_4 (0x430) -#define CONTROL_DEBOBS_5 (0x434) -#define CONTROL_DEBOBS_6 (0x438) -#define CONTROL_DEBOBS_7 (0x43C) -#define CONTROL_DEBOBS_8 (0x440) -#define CONTROL_PROG_IO0 (0x444) -#define CONTROL_PROG_IO1 (0x448) -#define CONTROL_DSS_DPLL_SPREADING (0x450) -#define CONTROL_CORE_DPLL_SPREADING (0x454) -#define CONTROL_PER_DPLL_SPREADING (0x458) -#define CONTROL_USBHOST_DPLL_SPREADING (0x45C) -#define CONTROL_TEMP_SENSOR (0x524) -#define CONTROL_SRAMLDO4 (0x528) -#define CONTROL_SRAMLDO5 (0x52C) -#define CONTROL_CSI (0x530) -#define CONTROL_SCALABLE_OMAP_OCP (0x534) -#define CONTROL_SCALABLE_OMAP_STATUS (0x44C) - -/** Provide the Regoffset, Value */ -#define MUX_VAL(OFFSET,VALUE)\ - writew((VALUE), OMAP_CTRL_BASE + (OFFSET)) - -/** - * macro for Padconfig Registers @see - * include/asm/arch-arm/arch-omap/omap3-mux.h - */ -#define CP(X) (CONTROL_PADCONF_##X) - -#endif /* __ASM_ARCH_OMAP_CONTROL_H */ diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h deleted file mode 100644 index a658cf00e7..0000000000 --- a/include/asm-arm/arch-omap/gpmc.h +++ /dev/null @@ -1,161 +0,0 @@ -/** - * @file - * @brief This file contains the GPMC's generic definitions - * - * FileName: include/asm-arm/arch-omap/gpmc.h - * - * OMAP's General Purpose Memory Controller(GPMC) provides features - * allowing us to communicate with memory devices such as NOR, NAND, - * OneNAND, SRAM etc.. This file defines certain generic parameters - * allowing us to configure the same painlessly. - * - */ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * Originally from Linux kernel: - * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz - * include/asm-arm/arch-omap/omap34xx.h - * - * Copyright (C) 2007 Texas Instruments, <www.ti.com> - * Copyright (C) 2007 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_OMAP_GPMC_H -#define __ASM_ARCH_OMAP_GPMC_H - -/** GPMC Reg Wrapper */ -#define GPMC_REG(REGNAME) (OMAP_GPMC_BASE + GPMC_##REGNAME) - -#define GPMC_SYS_CONFIG (0x10) -#define GPMC_SYS_STATUS (0x14) -#define GPMC_IRQSTATUS (0x18) -#define GPMC_IRQ_ENABLE (0x1C) -#define GPMC_TIMEOUT_CONTROL (0x40) -#define GPMC_CFG (0x50) -#define GPMC_STATUS (0x54) -#define GPMC_PREFETCH_CONFIG_1 (0x1E0) -#define GPMC_PREFETCH_CONFIG_2 (0x1E4) -#define GPMC_PREFETCH_CTRL (0x1EC) -#define GPMC_ECC_CONFIG (0x1F4) -#define GPMC_ECC_CONTROL (0x1F8) -#define GPMC_ECC_SIZE_CONFIG (0x1FC) -#define GPMC_ECC1_RESULT (0x200) -#define GPMC_ECC2_RESULT (0x204) -#define GPMC_ECC3_RESULT (0x208) -#define GPMC_ECC4_RESULT (0x20C) -#define GPMC_ECC5_RESULT (0x210) -#define GPMC_ECC6_RESULT (0x214) -#define GPMC_ECC7_RESULT (0x218) -#define GPMC_ECC8_RESULT (0x21C) -#define GPMC_ECC9_RESULT (0x220) - -#define GPMC_CONFIG1_0 (0x60) -#define GPMC_CONFIG1_1 (0x90) -#define GPMC_CONFIG1_2 (0xC0) -#define GPMC_CONFIG1_3 (0xF0) -#define GPMC_CONFIG1_4 (0x120) -#define GPMC_CONFIG1_5 (0x150) -#define GPMC_CONFIG1_6 (0x180) -#define GPMC_CONFIG1_7 (0x1B0) -#define GPMC_CONFIG2_0 (0x64) -#define GPMC_CONFIG2_1 (0x94) -#define GPMC_CONFIG2_2 (0xC4) -#define GPMC_CONFIG2_3 (0xF4) -#define GPMC_CONFIG2_4 (0x124) -#define GPMC_CONFIG2_5 (0x154) -#define GPMC_CONFIG2_6 (0x184) -#define GPMC_CONFIG2_7 (0x1B4) -#define GPMC_CONFIG3_0 (0x68) -#define GPMC_CONFIG3_1 (0x98) -#define GPMC_CONFIG3_2 (0xC8) -#define GPMC_CONFIG3_3 (0xF8) -#define GPMC_CONFIG3_4 (0x128) -#define GPMC_CONFIG3_5 (0x158) -#define GPMC_CONFIG3_6 (0x188) -#define GPMC_CONFIG3_7 (0x1B8) -#define GPMC_CONFIG4_0 (0x6C) -#define GPMC_CONFIG4_1 (0x9C) -#define GPMC_CONFIG4_2 (0xCC) -#define GPMC_CONFIG4_3 (0xFC) -#define GPMC_CONFIG4_4 (0x12C) -#define GPMC_CONFIG4_5 (0x15C) -#define GPMC_CONFIG4_6 (0x18C) -#define GPMC_CONFIG4_7 (0x1BC) -#define GPMC_CONFIG5_0 (0x70) -#define GPMC_CONFIG5_1 (0xA0) -#define GPMC_CONFIG5_2 (0xD0) -#define GPMC_CONFIG5_3 (0x100) -#define GPMC_CONFIG5_4 (0x130) -#define GPMC_CONFIG5_5 (0x160) -#define GPMC_CONFIG5_6 (0x190) -#define GPMC_CONFIG5_7 (0x1C0) -#define GPMC_CONFIG6_0 (0x74) -#define GPMC_CONFIG6_1 (0xA4) -#define GPMC_CONFIG6_2 (0xD4) -#define GPMC_CONFIG6_3 (0x104) -#define GPMC_CONFIG6_4 (0x134) -#define GPMC_CONFIG6_5 (0x164) -#define GPMC_CONFIG6_6 (0x194) -#define GPMC_CONFIG6_7 (0x1C4) -#define GPMC_CONFIG7_0 (0x78) -#define GPMC_CONFIG7_1 (0xA8) -#define GPMC_CONFIG7_2 (0xD8) -#define GPMC_CONFIG7_3 (0x108) -#define GPMC_CONFIG7_4 (0x138) -#define GPMC_CONFIG7_5 (0x168) -#define GPMC_CONFIG7_6 (0x198) -#define GPMC_CONFIG7_7 (0x1C8) - -#define GPMC_NUM_CS 8 -#define GPMC_CONFIG_CS_SIZE (GPMC_CONFIG1_1 - GPMC_CONFIG1_0) -#define GPMC_CONFIG_REG_OFF (GPMC_CONFIG2_0 - GPMC_CONFIG1_0) - -#define GPMC_CS_NAND_COMMAND (0x1C) -#define GPMC_CS_NAND_ADDRESS (0x20) -#define GPMC_CS_NAND_DATA (0x24) - -#define GPMC_SIZE_128M 0x08 -#define GPMC_SIZE_64M 0x0C -#define GPMC_SIZE_32M 0x0E -#define GPMC_SIZE_16M 0x0F - -#define NAND_WP_BIT 0x00000010 - -#ifndef __ASSEMBLY__ - -/** Generic GPMC configuration structure to be used to configure a - * chip select - */ -struct gpmc_config { - unsigned int cfg[6]; - unsigned int base; - unsigned char size; -}; - -/** Generic configuration - will reset all the cs configs. */ -void gpmc_generic_init(unsigned int cfg); - -/** Configuration for a specific chip select */ -void gpmc_cs_config(char cs, struct gpmc_config *config); - -#endif - -#endif /* __ASM_ARCH_OMAP_GPMC_H */ diff --git a/include/asm-arm/arch-omap/gpmc_nand.h b/include/asm-arm/arch-omap/gpmc_nand.h deleted file mode 100644 index c6c51d5d52..0000000000 --- a/include/asm-arm/arch-omap/gpmc_nand.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - * @file - * @brief This file contains exported structure for NAND - * - * FileName: include/asm-arm/arch-omap/gpmc_nand.h - * - * OMAP's General Purpose Memory Controller (GPMC) has a NAND controller - * embedded. this file provides the platform data structure required to - * hook on to it. - * - */ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * Originally from Linux kernel: - * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.3.tar.gz - * include/asm-arm/arch-omap/nand.h - * - * Copyright (C) 2006 Micron Technology Inc. - * Author: Shahrom Sharif-Kashani - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_OMAP_NAND_GPMC_H -#define __ASM_OMAP_NAND_GPMC_H - -#include <linux/mtd/mtd.h> -#include <linux/mtd/nand.h> -#include <linux/mtd/nand_ecc.h> - -/** omap nand platform data structure */ -struct gpmc_nand_platform_data { - /** Chip select you want to use */ - int cs; - struct mtd_partition *parts; - int nr_parts; - /** If there are any special setups you'd want to do */ - int (*nand_setup) (struct gpmc_nand_platform_data *); - - /** set up if we want H/w ECC here and other - * platform specific configs here - */ - unsigned short plat_options; - /** setup any special options */ - unsigned int options; - /** set up device access as 8,16 as per GPMC config */ - char device_width; - /** Set this to WAITx+1, so GPMC WAIT0 will be 1 and so on. */ - char wait_mon_pin; - /** Set this to the max timeout for the device */ - uint64_t max_timeout; - - /* if you like a custom oob use this. */ - struct nand_ecclayout *oob; - /** platform specific private data */ - void *priv; -}; - -/** Platform specific options definitions */ -/** plat_options: Wait montioring pin low */ -#define NAND_WAITPOL_LOW (0 << 0) -/** plat_options: Wait montioring pin high */ -#define NAND_WAITPOL_HIGH (1 << 0) -#define NAND_WAITPOL_MASK (1 << 0) - -#ifdef CONFIG_NAND_OMAP_GPMC_HWECC -/** plat_options: hw ecc enabled */ -#define NAND_HWECC_ENABLE (1 << 1) -#endif -/** plat_options: hw ecc disabled */ -#define NAND_HWECC_DISABLE (0 << 1) -#define NAND_HWECC_MASK (1 << 1) - -/* Typical BOOTROM oob layouts-requires hwecc **/ -#ifdef CONFIG_NAND_OMAP_GPMC_HWECC -/** Large Page x8 NAND device Layout */ -#define GPMC_NAND_ECC_LP_x8_LAYOUT {\ - .eccbytes = 12,\ - .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\ - 9, 10, 11, 12},\ - .oobfree = {\ - {.offset = 60,\ - .length = 2 } } \ -} - -/** Large Page x16 NAND device Layout */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT {\ - .eccbytes = 12,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13},\ - .oobfree = {\ - {.offset = 60,\ - .length = 2 } } \ -} - -/** Small Page x8 NAND device Layout */ -#define GPMC_NAND_ECC_SP_x8_LAYOUT {\ - .eccbytes = 3,\ - .eccpos = {1, 2, 3},\ - .oobfree = {\ - {.offset = 14,\ - .length = 2 } } \ -} - -/** Small Page x16 NAND device Layout */ -#define GPMC_NAND_ECC_SP_x16_LAYOUT {\ - .eccbytes = 3,\ - .eccpos = {2, 3, 4},\ - .oobfree = {\ - {.offset = 14,\ - .length = 2 } } \ -} - -#endif /* CONFIG_NAND_OMAP_GPMC_HWECC */ - -#endif /* __ASM_OMAP_NAND_GPMC_H */ diff --git a/include/asm-arm/arch-omap/intc.h b/include/asm-arm/arch-omap/intc.h deleted file mode 100644 index 48fcf3d1d6..0000000000 --- a/include/asm-arm/arch-omap/intc.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * @file - * @brief This file contains the Interrupt controller register defines - * - * FileName: include/asm-arm/arch-omap/intc.h - * - * Originally from Linux kernel: - * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz - * include/asm-arm/arch-omap/omap34xx.h - */ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * Copyright (C) 2007 Texas Instruments, <www.ti.com> - * Copyright (C) 2007 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_OMAP_INTC_H -#define __ASM_ARCH_OMAP_INTC_H - -/** Interrupt Controller Register wrapper */ -#define INTC_REG(REGNAME) (OMAP_INTC_BASE + INTC_##REGNAME) - -#define INTC_MIR_0 (0x084) -#define INTC_MIR_1 (0x0A4) -#define INTC_MIR_2 (0x0C4) -#define INTC_MIR_SET_0 (0x08C) -#define INTC_MIR_SET_1 (0x0AC) -#define INTC_MIR_SET_2 (0x0CC) -#define INTC_MIR_CLEAR_0 (0x094) -#define INTC_MIR_CLEAR_1 (0x0B4) -#define INTC_MIR_CLEAR_2 (0x0D4) -#define INTC_PS_SYSCONFIG (0x010) -#define INTC_PS_PROTECTION (0x04C) -#define INTC_PS_IDLE (0x050) -#define INTC_PS_THRESHOLD (0x068) -#define INTC_PS_PENDING_IRQ0 (0x098) -#define INTC_PS_PENDING_IRQ1 (0x0B8) -#define INTC_PS_PENDING_IRQ2 (0x0D8) - -#endif /* __ASM_ARCH_OMAP_INTC_H */ diff --git a/include/asm-arm/arch-omap/omap3-clock.h b/include/asm-arm/arch-omap/omap3-clock.h deleted file mode 100644 index 22694f2367..0000000000 --- a/include/asm-arm/arch-omap/omap3-clock.h +++ /dev/null @@ -1,124 +0,0 @@ -/** - * @file - * @brief Contains the PRM and CM definitions - * - * FileName: include/asm-arm/arch-omap/omap3-clock.h - * - * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz - * - */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP343X_CLOCKS_H_ -#define _OMAP343X_CLOCKS_H_ - -/** CM Clock Regs Wrapper */ -#define CM_REG(REGNAME) (OMAP_CM_BASE + CM_##REGNAME) - -#define CM_FCLKEN_IVA2 0X0000 -#define CM_CLKEN_PLL_IVA2 0X0004 -#define CM_IDLEST_PLL_IVA2 0X0024 -#define CM_CLKSEL1_PLL_IVA2 0X0040 -#define CM_CLKSEL2_PLL_IVA2 0X0044 -#define CM_CLKEN_PLL_MPU 0X0904 -#define CM_IDLEST_PLL_MPU 0X0924 -#define CM_CLKSEL1_PLL_MPU 0X0940 -#define CM_CLKSEL2_PLL_MPU 0X0944 -#define CM_FCLKEN1_CORE 0X0A00 -#define CM_ICLKEN1_CORE 0X0A10 -#define CM_ICLKEN2_CORE 0X0A14 -#define CM_CLKSEL_CORE 0X0A40 -#define CM_FCLKEN_GFX 0X0B00 -#define CM_ICLKEN_GFX 0X0B10 -#define CM_CLKSEL_GFX 0X0B40 -#define CM_FCLKEN_WKUP 0X0C00 -#define CM_ICLKEN_WKUP 0X0C10 -#define CM_CLKSEL_WKUP 0X0C40 -#define CM_IDLEST_WKUP 0X0C20 -#define CM_CLKEN_PLL 0X0D00 -#define CM_IDLEST_CKGEN 0X0D20 -#define CM_CLKSEL1_PLL 0X0D40 -#define CM_CLKSEL2_PLL 0X0D44 -#define CM_CLKSEL3_PLL 0X0D48 -#define CM_FCLKEN_DSS 0X0E00 -#define CM_ICLKEN_DSS 0X0E10 -#define CM_CLKSEL_DSS 0X0E40 -#define CM_FCLKEN_CAM 0X0F00 -#define CM_ICLKEN_CAM 0X0F10 -#define CM_CLKSEL_CAM 0X0f40 -#define CM_FCLKEN_PER 0X1000 -#define CM_ICLKEN_PER 0X1010 -#define CM_CLKSEL_PER 0X1040 -#define CM_CLKSEL1_EMU 0X1140 - -/** PRM Clock Regs */ -#define PRM_REG(REGNAME) (OMAP_PRM_BASE + PRM_##REGNAME) -#define PRM_CLKSEL 0x0D40 -#define PRM_RSTCTRL 0x1250 -#define PRM_CLKSRC_CTRL 0x1270 - -/*************** Clock Values */ -#define PLL_STOP 1 /* PER & IVA */ -#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ -#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ -#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ - -/* The following configurations are OPP and SysClk value independant - * and hence are defined here. - */ - -/* CORE DPLL */ -#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ -#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ -#define CORE_FUSB_DIV 2 /* 41.5MHz: */ -#define CORE_L4_DIV 2 /* 83MHz : L4 */ -#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ -#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ -#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ - -/* PER DPLL */ -#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ -#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ -#define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */ -#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ - -#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50)) - -#define MAX_SIL_INDEX 1 - -#ifndef __ASSEMBLY__ -void prcm_init(void); -/* Used to index into DPLL parameter tables -See TRM for further details */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; -/* External functions see omap3_clock_core.S */ -extern struct dpll_param *get_mpu_dpll_param(void); -extern struct dpll_param *get_iva_dpll_param(void); -extern struct dpll_param *get_core_dpll_param(void); -extern struct dpll_param *get_per_dpll_param(void); - -#endif /* __ASSEMBLY__ */ - -#endif /* endif _OMAP343X_CLOCKS_H_ */ diff --git a/include/asm-arm/arch-omap/omap3-mux.h b/include/asm-arm/arch-omap/omap3-mux.h deleted file mode 100644 index 2badc3f851..0000000000 --- a/include/asm-arm/arch-omap/omap3-mux.h +++ /dev/null @@ -1,423 +0,0 @@ -/** - * @file - * @brief Mux Configuration Register defines for OMAP3 - * - * FileName: include/asm-arm/arch-omap/omap3-mux.h - * - * This file defines the various Pin Mux registers - * @see include/asm-arm/arch-omap/control.h - * The @ref MUX_VAL macro uses the defines from this file - * - * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz - */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _ASM_ARCH_OMAP3_MUX_H_ -#define _ASM_ARCH_OMAP3_MUX_H_ - -/** - * Pin Mux Enable Defines - * - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0-7 - Mode 0-7 - * - * @see MUX_VAL - */ -#define IEN (1 << 8) - -#define IDIS (0 << 8) -#define PTU (1 << 4) -#define PTD (0 << 4) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -/* - * To get the actual address the offset has to added - * with OMAP_CTRL_BASE to get the actual address - */ - -/* SDRC */ -#define CONTROL_PADCONF_SDRC_D0 0x0030 -#define CONTROL_PADCONF_SDRC_D1 0x0032 -#define CONTROL_PADCONF_SDRC_D2 0x0034 -#define CONTROL_PADCONF_SDRC_D3 0x0036 -#define CONTROL_PADCONF_SDRC_D4 0x0038 -#define CONTROL_PADCONF_SDRC_D5 0x003A -#define CONTROL_PADCONF_SDRC_D6 0x003C -#define CONTROL_PADCONF_SDRC_D7 0x003E -#define CONTROL_PADCONF_SDRC_D8 0x0040 -#define CONTROL_PADCONF_SDRC_D9 0x0042 -#define CONTROL_PADCONF_SDRC_D10 0x0044 -#define CONTROL_PADCONF_SDRC_D11 0x0046 -#define CONTROL_PADCONF_SDRC_D12 0x0048 -#define CONTROL_PADCONF_SDRC_D13 0x004A -#define CONTROL_PADCONF_SDRC_D14 0x004C -#define CONTROL_PADCONF_SDRC_D15 0x004E -#define CONTROL_PADCONF_SDRC_D16 0x0050 -#define CONTROL_PADCONF_SDRC_D17 0x0052 -#define CONTROL_PADCONF_SDRC_D18 0x0054 -#define CONTROL_PADCONF_SDRC_D19 0x0056 -#define CONTROL_PADCONF_SDRC_D20 0x0058 -#define CONTROL_PADCONF_SDRC_D21 0x005A -#define CONTROL_PADCONF_SDRC_D22 0x005C -#define CONTROL_PADCONF_SDRC_D23 0x005E -#define CONTROL_PADCONF_SDRC_D24 0x0060 -#define CONTROL_PADCONF_SDRC_D25 0x0062 -#define CONTROL_PADCONF_SDRC_D26 0x0064 -#define CONTROL_PADCONF_SDRC_D27 0x0066 -#define CONTROL_PADCONF_SDRC_D28 0x0068 -#define CONTROL_PADCONF_SDRC_D29 0x006A -#define CONTROL_PADCONF_SDRC_D30 0x006C -#define CONTROL_PADCONF_SDRC_D31 0x006E -#define CONTROL_PADCONF_SDRC_CLK 0x0070 -#define CONTROL_PADCONF_SDRC_DQS0 0x0072 -#define CONTROL_PADCONF_SDRC_DQS1 0x0074 -#define CONTROL_PADCONF_SDRC_DQS2 0x0076 -#define CONTROL_PADCONF_SDRC_DQS3 0x0078 -/* GPMC */ -#define CONTROL_PADCONF_GPMC_A1 0x007A -#define CONTROL_PADCONF_GPMC_A2 0x007C -#define CONTROL_PADCONF_GPMC_A3 0x007E -#define CONTROL_PADCONF_GPMC_A4 0x0080 -#define CONTROL_PADCONF_GPMC_A5 0x0082 -#define CONTROL_PADCONF_GPMC_A6 0x0084 -#define CONTROL_PADCONF_GPMC_A7 0x0086 -#define CONTROL_PADCONF_GPMC_A8 0x0088 -#define CONTROL_PADCONF_GPMC_A9 0x008A -#define CONTROL_PADCONF_GPMC_A10 0x008C -#define CONTROL_PADCONF_GPMC_D0 0x008E -#define CONTROL_PADCONF_GPMC_D1 0x0090 -#define CONTROL_PADCONF_GPMC_D2 0x0092 -#define CONTROL_PADCONF_GPMC_D3 0x0094 -#define CONTROL_PADCONF_GPMC_D4 0x0096 -#define CONTROL_PADCONF_GPMC_D5 0x0098 -#define CONTROL_PADCONF_GPMC_D6 0x009A -#define CONTROL_PADCONF_GPMC_D7 0x009C -#define CONTROL_PADCONF_GPMC_D8 0x009E -#define CONTROL_PADCONF_GPMC_D9 0x00A0 -#define CONTROL_PADCONF_GPMC_D10 0x00A2 -#define CONTROL_PADCONF_GPMC_D11 0x00A4 -#define CONTROL_PADCONF_GPMC_D12 0x00A6 -#define CONTROL_PADCONF_GPMC_D13 0x00A8 -#define CONTROL_PADCONF_GPMC_D14 0x00AA -#define CONTROL_PADCONF_GPMC_D15 0x00AC -#define CONTROL_PADCONF_GPMC_NCS0 0x00AE -#define CONTROL_PADCONF_GPMC_NCS1 0x00B0 -#define CONTROL_PADCONF_GPMC_NCS2 0x00B2 -#define CONTROL_PADCONF_GPMC_NCS3 0x00B4 -#define CONTROL_PADCONF_GPMC_NCS4 0x00B6 -#define CONTROL_PADCONF_GPMC_NCS5 0x00B8 -#define CONTROL_PADCONF_GPMC_NCS6 0x00BA -#define CONTROL_PADCONF_GPMC_NCS7 0x00BC -#define CONTROL_PADCONF_GPMC_CLK 0x00BE -#define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0 -#define CONTROL_PADCONF_GPMC_NOE 0x00C2 -#define CONTROL_PADCONF_GPMC_NWE 0x00C4 -#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6 -#define CONTROL_PADCONF_GPMC_NBE1 0x00C8 -#define CONTROL_PADCONF_GPMC_NWP 0x00CA -#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC -#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE -#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 -#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 -/* DSS */ -#define CONTROL_PADCONF_DSS_PCLK 0x00D4 -#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 -#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 -#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA -#define CONTROL_PADCONF_DSS_DATA0 0x00DC -#define CONTROL_PADCONF_DSS_DATA1 0x00DE -#define CONTROL_PADCONF_DSS_DATA2 0x00E0 -#define CONTROL_PADCONF_DSS_DATA3 0x00E2 -#define CONTROL_PADCONF_DSS_DATA4 0x00E4 -#define CONTROL_PADCONF_DSS_DATA5 0x00E6 -#define CONTROL_PADCONF_DSS_DATA6 0x00E8 -#define CONTROL_PADCONF_DSS_DATA7 0x00EA -#define CONTROL_PADCONF_DSS_DATA8 0x00EC -#define CONTROL_PADCONF_DSS_DATA9 0x00EE -#define CONTROL_PADCONF_DSS_DATA10 0x00F0 -#define CONTROL_PADCONF_DSS_DATA11 0x00F2 -#define CONTROL_PADCONF_DSS_DATA12 0x00F4 -#define CONTROL_PADCONF_DSS_DATA13 0x00F6 -#define CONTROL_PADCONF_DSS_DATA14 0x00F8 -#define CONTROL_PADCONF_DSS_DATA15 0x00FA -#define CONTROL_PADCONF_DSS_DATA16 0x00FC -#define CONTROL_PADCONF_DSS_DATA17 0x00FE -#define CONTROL_PADCONF_DSS_DATA18 0x0100 -#define CONTROL_PADCONF_DSS_DATA19 0x0102 -#define CONTROL_PADCONF_DSS_DATA20 0x0104 -#define CONTROL_PADCONF_DSS_DATA21 0x0106 -#define CONTROL_PADCONF_DSS_DATA22 0x0108 -#define CONTROL_PADCONF_DSS_DATA23 0x010A -/* CAMERA */ -#define CONTROL_PADCONF_CAM_HS 0x010C -#define CONTROL_PADCONF_CAM_VS 0x010E -#define CONTROL_PADCONF_CAM_XCLKA 0x0110 -#define CONTROL_PADCONF_CAM_PCLK 0x0112 -#define CONTROL_PADCONF_CAM_FLD 0x0114 -#define CONTROL_PADCONF_CAM_D0 0x0116 -#define CONTROL_PADCONF_CAM_D1 0x0118 -#define CONTROL_PADCONF_CAM_D2 0x011A -#define CONTROL_PADCONF_CAM_D3 0x011C -#define CONTROL_PADCONF_CAM_D4 0x011E -#define CONTROL_PADCONF_CAM_D5 0x0120 -#define CONTROL_PADCONF_CAM_D6 0x0122 -#define CONTROL_PADCONF_CAM_D7 0x0124 -#define CONTROL_PADCONF_CAM_D8 0x0126 -#define CONTROL_PADCONF_CAM_D9 0x0128 -#define CONTROL_PADCONF_CAM_D10 0x012A -#define CONTROL_PADCONF_CAM_D11 0x012C -#define CONTROL_PADCONF_CAM_XCLKB 0x012E -#define CONTROL_PADCONF_CAM_WEN 0x0130 -#define CONTROL_PADCONF_CAM_STROBE 0x0132 -#define CONTROL_PADCONF_CSI2_DX0 0x0134 -#define CONTROL_PADCONF_CSI2_DY0 0x0136 -#define CONTROL_PADCONF_CSI2_DX1 0x0138 -#define CONTROL_PADCONF_CSI2_DY1 0x013A -/* Audio Interface */ -#define CONTROL_PADCONF_MCBSP2_FSX 0x013C -#define CONTROL_PADCONF_MCBSP2_CLKX 0x013E -#define CONTROL_PADCONF_MCBSP2_DR 0x0140 -#define CONTROL_PADCONF_MCBSP2_DX 0x0142 -#define CONTROL_PADCONF_ -#define CONTROL_PADCONF_MMC1_CLK 0x0144 -#define CONTROL_PADCONF_MMC1_CMD 0x0146 -#define CONTROL_PADCONF_MMC1_DAT0 0x0148 -#define CONTROL_PADCONF_MMC1_DAT1 0x014A -#define CONTROL_PADCONF_MMC1_DAT2 0x014C -#define CONTROL_PADCONF_MMC1_DAT3 0x014E -#define CONTROL_PADCONF_MMC1_DAT4 0x0150 -#define CONTROL_PADCONF_MMC1_DAT5 0x0152 -#define CONTROL_PADCONF_MMC1_DAT6 0x0154 -#define CONTROL_PADCONF_MMC1_DAT7 0x0156 -/* WirelesS LAN */ -#define CONTROL_PADCONF_MMC2_CLK 0x0158 -#define CONTROL_PADCONF_MMC2_CMD 0x015A -#define CONTROL_PADCONF_MMC2_DAT0 0x015C -#define CONTROL_PADCONF_MMC2_DAT1 0x015E -#define CONTROL_PADCONF_MMC2_DAT2 0x0160 -#define CONTROL_PADCONF_MMC2_DAT3 0x0162 -#define CONTROL_PADCONF_MMC2_DAT4 0x0164 -#define CONTROL_PADCONF_MMC2_DAT5 0x0166 -#define CONTROL_PADCONF_MMC2_DAT6 0x0168 -#define CONTROL_PADCONF_MMC2_DAT7 0x016A -/* Bluetooth */ -#define CONTROL_PADCONF_MCBSP3_DX 0x016C -#define CONTROL_PADCONF_MCBSP3_DR 0x016E -#define CONTROL_PADCONF_MCBSP3_CLKX 0x0170 -#define CONTROL_PADCONF_MCBSP3_FSX 0x0172 -#define CONTROL_PADCONF_UART2_CTS 0x0174 -#define CONTROL_PADCONF_UART2_RTS 0x0176 -#define CONTROL_PADCONF_UART2_TX 0x0178 -#define CONTROL_PADCONF_UART2_RX 0x017A -/* Modem Interface */ -#define CONTROL_PADCONF_UART1_TX 0x017C -#define CONTROL_PADCONF_UART1_RTS 0x017E -#define CONTROL_PADCONF_UART1_CTS 0x0180 -#define CONTROL_PADCONF_UART1_RX 0x0182 -#define CONTROL_PADCONF_MCBSP4_CLKX 0x0184 -#define CONTROL_PADCONF_MCBSP4_DR 0x0186 -#define CONTROL_PADCONF_MCBSP4_DX 0x0188 -#define CONTROL_PADCONF_MCBSP4_FSX 0x018A -#define CONTROL_PADCONF_MCBSP1_CLKR 0x018C -#define CONTROL_PADCONF_MCBSP1_FSR 0x018E -#define CONTROL_PADCONF_MCBSP1_DX 0x0190 -#define CONTROL_PADCONF_MCBSP1_DR 0x0192 -#define CONTROL_PADCONF_MCBSP_CLKS 0x0194 -#define CONTROL_PADCONF_MCBSP1_FSX 0x0196 -#define CONTROL_PADCONF_MCBSP1_CLKX 0x0198 -/* Serial Interface */ -#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A -#define CONTROL_PADCONF_UART3_RTS_SD 0x019C -#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E -#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 -#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 -#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 -#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 -#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 -#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA -#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC -#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE -#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 -#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 -#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 -#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 -#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 -#define CONTROL_PADCONF_I2C1_SCL 0x01BA -#define CONTROL_PADCONF_I2C1_SDA 0x01BC -#define CONTROL_PADCONF_I2C2_SCL 0x01BE -#define CONTROL_PADCONF_I2C2_SDA 0x01C0 -#define CONTROL_PADCONF_I2C3_SCL 0x01C2 -#define CONTROL_PADCONF_I2C3_SDA 0x01C4 -#define CONTROL_PADCONF_I2C4_SCL 0x0A00 -#define CONTROL_PADCONF_I2C4_SDA 0x0A02 -#define CONTROL_PADCONF_HDQ_SIO 0x01C6 -#define CONTROL_PADCONF_MCSPI1_CLK 0x01C8 -#define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA -#define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC -#define CONTROL_PADCONF_MCSPI1_CS0 0x01CE -#define CONTROL_PADCONF_MCSPI1_CS1 0x01D0 -#define CONTROL_PADCONF_MCSPI1_CS2 0x01D2 -#define CONTROL_PADCONF_MCSPI1_CS3 0x01D4 -#define CONTROL_PADCONF_MCSPI2_CLK 0x01D6 -#define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8 -#define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA -#define CONTROL_PADCONF_MCSPI2_CS0 0x01DC -#define CONTROL_PADCONF_MCSPI2_CS1 0x01DE -/* Control and debug */ -#define CONTROL_PADCONF_SYS_32K 0x0A04 -#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 -#define CONTROL_PADCONF_SYS_NIRQ 0x01E0 -#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A -#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C -#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E -#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 -#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 -#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 -#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 -#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 -#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A -#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 -#define CONTROL_PADCONF_JTAG_NTRST 0x0A1C -#define CONTROL_PADCONF_JTAG_TCK 0x0A1E -#define CONTROL_PADCONF_JTAG_TMS 0x0A20 -#define CONTROL_PADCONF_JTAG_TDI 0x0A22 -#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 -#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 -#define CONTROL_PADCONF_ETK_CLK 0x0A28 -#define CONTROL_PADCONF_ETK_CTL 0x0A2A -#define CONTROL_PADCONF_ETK_D0 0x0A2C -#define CONTROL_PADCONF_ETK_D1 0x0A2E -#define CONTROL_PADCONF_ETK_D2 0x0A30 -#define CONTROL_PADCONF_ETK_D3 0x0A32 -#define CONTROL_PADCONF_ETK_D4 0x0A34 -#define CONTROL_PADCONF_ETK_D5 0x0A36 -#define CONTROL_PADCONF_ETK_D6 0x0A38 -#define CONTROL_PADCONF_ETK_D7 0x0A3A -#define CONTROL_PADCONF_ETK_D8 0x0A3C -#define CONTROL_PADCONF_ETK_D9 0x0A3E -#define CONTROL_PADCONF_ETK_D10 0x0A40 -#define CONTROL_PADCONF_ETK_D11 0x0A42 -#define CONTROL_PADCONF_ETK_D12 0x0A44 -#define CONTROL_PADCONF_ETK_D13 0x0A46 -#define CONTROL_PADCONF_ETK_D14 0x0A48 -#define CONTROL_PADCONF_ETK_D15 0x0A4A -#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 -#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA -#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC -#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE -#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 -#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 -#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 -#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 -#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 -#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA -#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC -#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE -#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 -#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 -#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 -#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 -#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 -#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA -/* Die to die */ -#define CONTROL_PADCONF_D2D_MCAD0 0x01E4 -#define CONTROL_PADCONF_D2D_MCAD1 0x01E6 -#define CONTROL_PADCONF_D2D_MCAD2 0x01E8 -#define CONTROL_PADCONF_D2D_MCAD3 0x01EA -#define CONTROL_PADCONF_D2D_MCAD4 0x01EC -#define CONTROL_PADCONF_D2D_MCAD5 0x01EE -#define CONTROL_PADCONF_D2D_MCAD6 0x01F0 -#define CONTROL_PADCONF_D2D_MCAD7 0x01F2 -#define CONTROL_PADCONF_D2D_MCAD8 0x01F4 -#define CONTROL_PADCONF_D2D_MCAD9 0x01F6 -#define CONTROL_PADCONF_D2D_MCAD10 0x01F8 -#define CONTROL_PADCONF_D2D_MCAD11 0x01FA -#define CONTROL_PADCONF_D2D_MCAD12 0x01FC -#define CONTROL_PADCONF_D2D_MCAD13 0x01FE -#define CONTROL_PADCONF_D2D_MCAD14 0x0200 -#define CONTROL_PADCONF_D2D_MCAD15 0x0202 -#define CONTROL_PADCONF_D2D_MCAD16 0x0204 -#define CONTROL_PADCONF_D2D_MCAD17 0x0206 -#define CONTROL_PADCONF_D2D_MCAD18 0x0208 -#define CONTROL_PADCONF_D2D_MCAD19 0x020A -#define CONTROL_PADCONF_D2D_MCAD20 0x020C -#define CONTROL_PADCONF_D2D_MCAD21 0x020E -#define CONTROL_PADCONF_D2D_MCAD22 0x0210 -#define CONTROL_PADCONF_D2D_MCAD23 0x0212 -#define CONTROL_PADCONF_D2D_MCAD24 0x0214 -#define CONTROL_PADCONF_D2D_MCAD25 0x0216 -#define CONTROL_PADCONF_D2D_MCAD26 0x0218 -#define CONTROL_PADCONF_D2D_MCAD27 0x021A -#define CONTROL_PADCONF_D2D_MCAD28 0x021C -#define CONTROL_PADCONF_D2D_MCAD29 0x021E -#define CONTROL_PADCONF_D2D_MCAD30 0x0220 -#define CONTROL_PADCONF_D2D_MCAD31 0x0222 -#define CONTROL_PADCONF_D2D_MCAD32 0x0224 -#define CONTROL_PADCONF_D2D_MCAD33 0x0226 -#define CONTROL_PADCONF_D2D_MCAD34 0x0228 -#define CONTROL_PADCONF_D2D_MCAD35 0x022A -#define CONTROL_PADCONF_D2D_MCAD36 0x022C -#define CONTROL_PADCONF_D2D_CLK26MI 0x022E -#define CONTROL_PADCONF_D2D_NRESPWRON 0x0230 -#define CONTROL_PADCONF_D2D_NRESWARM 0x0232 -#define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234 -#define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236 -#define CONTROL_PADCONF_D2D_SPINT 0x0238 -#define CONTROL_PADCONF_D2D_FRINT 0x023A -#define CONTROL_PADCONF_D2D_DMAREQ0 0x023C -#define CONTROL_PADCONF_D2D_DMAREQ1 0x023E -#define CONTROL_PADCONF_D2D_DMAREQ2 0x0240 -#define CONTROL_PADCONF_D2D_DMAREQ3 0x0242 -#define CONTROL_PADCONF_D2D_N3GTRST 0x0244 -#define CONTROL_PADCONF_D2D_N3GTDI 0x0246 -#define CONTROL_PADCONF_D2D_N3GTDO 0x0248 -#define CONTROL_PADCONF_D2D_N3GTMS 0x024A -#define CONTROL_PADCONF_D2D_N3GTCK 0x024C -#define CONTROL_PADCONF_D2D_N3GRTCK 0x024E -#define CONTROL_PADCONF_D2D_MSTDBY 0x0250 -#define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C -#define CONTROL_PADCONF_D2D_IDLEREQ 0x0252 -#define CONTROL_PADCONF_D2D_IDLEACK 0x0254 -#define CONTROL_PADCONF_D2D_MWRITE 0x0256 -#define CONTROL_PADCONF_D2D_SWRITE 0x0258 -#define CONTROL_PADCONF_D2D_MREAD 0x025A -#define CONTROL_PADCONF_D2D_SREAD 0x025C -#define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E -#define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260 -#define CONTROL_PADCONF_SDRC_CKE0 0x0262 -#define CONTROL_PADCONF_SDRC_CKE1 0x0264 - -#endif /* _ASM_ARCH_OMAP3_MUX_H_ */ diff --git a/include/asm-arm/arch-omap/omap3-silicon.h b/include/asm-arm/arch-omap/omap3-silicon.h deleted file mode 100644 index dde241272f..0000000000 --- a/include/asm-arm/arch-omap/omap3-silicon.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * @file - * @brief This file contains the processor specific definitions of - * the TI OMAP34XX. For more info on OMAP34XX, - * See http://focus.ti.com/pdfs/wtbu/swpu114g.pdf - * - * FileName: include/asm-arm/arch-omap/omap3-silicon.h - * - * OMAP34XX base address defines go here. - * - * Originally from Linux kernel: - * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz - * include/asm-arm/arch-omap/omap3-silicon.h - */ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * Copyright (C) 2007 Texas Instruments, <www.ti.com> - * Copyright (C) 2007 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_OMAP3_H -#define __ASM_ARCH_OMAP3_H - -/* PLEASE PLACE ONLY BASE DEFINES HERE */ - -/** OMAP Internal Bus Base addresses */ -#define OMAP_L4_CORE_BASE 0x48000000 -#define OMAP_INTC_BASE 0x48200000 -#define OMAP_L4_WKUP_BASE 0x48300000 -#define OMAP_L4_PER_BASE 0x49000000 -#define OMAP_L4_EMU_BASE 0x54000000 -#define OMAP_SGX_BASE 0x50000000 -#define OMAP_IVA_BASE 0x5C000000 -#define OMAP_SMX_APE_BASE 0x68000000 -#define OMAP_SMS_BASE 0x6C000000 -#define OMAP_SDRC_BASE 0x6D000000 -#define OMAP_GPMC_BASE 0x6E000000 - -/** Peripheral Base Addresses */ -#define OMAP_CTRL_BASE (OMAP_L4_CORE_BASE + 0x02000) -#define OMAP_CM_BASE (OMAP_L4_CORE_BASE + 0x04000) -#define OMAP_PRM_BASE (OMAP_L4_WKUP_BASE + 0x06000) - -#define OMAP_UART1_BASE (OMAP_L4_CORE_BASE + 0x6A000) -#define OMAP_UART2_BASE (OMAP_L4_CORE_BASE + 0x6C000) -#define OMAP_UART3_BASE (OMAP_L4_PER_BASE + 0x20000) - -#define OMAP_I2C1_BASE (OMAP_L4_CORE_BASE + 0x70000) -#define OMAP_I2C2_BASE (OMAP_L4_CORE_BASE + 0x72000) -#define OMAP_I2C3_BASE (OMAP_L4_CORE_BASE + 0x60000) - -#define OMAP_GPTIMER1_BASE (OMAP_L4_WKUP_BASE + 0x18000) -#define OMAP_GPTIMER2_BASE (OMAP_L4_PER_BASE + 0x32000) -#define OMAP_GPTIMER3_BASE (OMAP_L4_PER_BASE + 0x34000) -#define OMAP_GPTIMER4_BASE (OMAP_L4_PER_BASE + 0x36000) -#define OMAP_GPTIMER5_BASE (OMAP_L4_PER_BASE + 0x38000) -#define OMAP_GPTIMER6_BASE (OMAP_L4_PER_BASE + 0x3A000) -#define OMAP_GPTIMER7_BASE (OMAP_L4_PER_BASE + 0x3C000) -#define OMAP_GPTIMER8_BASE (OMAP_L4_PER_BASE + 0x3E000) -#define OMAP_GPTIMER9_BASE (OMAP_L4_PER_BASE + 0x40000) -#define OMAP_GPTIMER10_BASE (OMAP_L4_CORE_BASE + 0x86000) -#define OMAP_GPTIMER11_BASE (OMAP_L4_CORE_BASE + 0x88000) - -#define OMAP_WDTIMER2_BASE (OMAP_L4_WKUP_BASE + 0x14000) -#define OMAP_WDTIMER3_BASE (OMAP_L4_PER_BASE + 0x30000) - -#define OMAP_32KTIMER_BASE (OMAP_L4_WKUP_BASE + 0x20000) - -#define OMAP_MMC1_BASE (OMAP_L4_CORE_BASE + 0x9C000) -#define OMAP_MMC2_BASE (OMAP_L4_CORE_BASE + 0xB4000) -#define OMAP_MMC3_BASE (OMAP_L4_CORE_BASE + 0xAD000) - -#define OMAP_MUSB0_BASE (OMAP_L4_CORE_BASE + 0xAB000) - -#define OMAP_GPIO1_BASE (OMAP_L4_WKUP_BASE + 0x10000) -#define OMAP_GPIO2_BASE (OMAP_L4_PER_BASE + 0x50000) -#define OMAP_GPIO3_BASE (OMAP_L4_PER_BASE + 0x52000) -#define OMAP_GPIO4_BASE (OMAP_L4_PER_BASE + 0x54000) -#define OMAP_GPIO5_BASE (OMAP_L4_PER_BASE + 0x56000) -#define OMAP_GPIO6_BASE (OMAP_L4_PER_BASE + 0x58000) - -/** MPU WDT Definition */ -#define OMAP_MPU_WDTIMER_BASE OMAP_WDTIMER2_BASE - -/** Interrupt Vector base address */ -#define OMAP_SRAM_INTVECT 0x4020F800 -#define OMAP_SRAM_INTVECT_COPYSIZE 0x64 -/** Temporary stack for us to use C calls in low_level_init */ -#define OMAP_SRAM_STACK 0x4020FFFC - -/** Gives the silicon revision */ -#define OMAP_TAP_BASE (OMAP_L4_WKUP_BASE + 0xA000) -#define IDCODE_REG (OMAP_TAP_BASE + 0x204) - -/************ Generic Chip specific Definitions **********/ -/** - * CHIP F number HAWKEYE (hex) - * OMAP3430 ES1.0 F771609 B6D6 - * OMAP3430 ES2.0 F771609A B7AE - */ -#define HAWKEYE_ES1 0x0B6D6000 -#define HAWKEYE_ES2 0x0B7AE000 -#define HAWKEYE_ES2_1 0x1B7AE000 -#define HAWKEYE_MASK 0x0FFFF000 -#define VERSION_MASK 0xF0000000 -#define DEVICE_MASK ((0x1 << 8)|(0x1 << 9)|(0x1 << 10)) - -#define OMAP_SDRC_CS0 0x80000000 -#define OMAP_SDRC_CS1 0xA0000000 - -#endif /* __ASM_ARCH_OMAP3_H */ - diff --git a/include/asm-arm/arch-omap/omap3-smx.h b/include/asm-arm/arch-omap/omap3-smx.h deleted file mode 100644 index 78cff95f5b..0000000000 --- a/include/asm-arm/arch-omap/omap3-smx.h +++ /dev/null @@ -1,69 +0,0 @@ -/** - * @file - * @brief This file contains the SMX specific register definitions - * - * FileName: include/asm-arm/arch-omap/omap3-smx.h - * - * Originally from Linux kernel: - * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz - * include/asm-arm/arch-omap/omap34xx.h - */ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * Copyright (C) 2007 Texas Instruments, <www.ti.com> - * Copyright (C) 2007 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_OMAP_SMX_H -#define __ASM_ARCH_OMAP_SMX_H - -/* SMX-APE */ -#define PM_RT_APE_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x10000) -#define PM_GPMC_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12400) -#define PM_OCM_RAM_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12800) -#define PM_OCM_ROM_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12C00) -#define PM_IVA2_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x14000) - -#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) -#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) -#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) -#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) - -#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) -#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) -#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) - -#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) -#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) -#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) -#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) - -/* IVA2 */ -#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) -#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) -#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) - -/* SMS */ -#define SMS_SYSCONFIG (OMAP_SMS_BASE + 0x10) -#define SMS_RG_ATT0 (OMAP_SMS_BASE + 0x48) -#define SMS_CLASS_ARB0 (OMAP_SMS_BASE + 0xD0) -#define BURSTCOMPLETE_GROUP7 (0x1 << 31) - -#endif /* __ASM_ARCH_OMAP_SMX_H */ diff --git a/include/asm-arm/arch-omap/sdrc.h b/include/asm-arm/arch-omap/sdrc.h deleted file mode 100644 index 9d2d2d1107..0000000000 --- a/include/asm-arm/arch-omap/sdrc.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * @file - * @brief This file contains the SDRC specific register definitions - * - * FileName: include/asm-arm/arch-omap/sdrc.h - * - * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz - */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_ARCH_SDRC_H -#define _ASM_ARCH_SDRC_H - -#define SDRC_REG(REGNAME) (OMAP_SDRC_BASE + OMAP_SDRC_##REGNAME) -#define OMAP_SDRC_SYSCONFIG (0x10) -#define OMAP_SDRC_STATUS (0x14) -#define OMAP_SDRC_CS_CFG (0x40) -#define OMAP_SDRC_SHARING (0x44) -#define OMAP_SDRC_DLLA_CTRL (0x60) -#define OMAP_SDRC_DLLA_STATUS (0x64) -#define OMAP_SDRC_DLLB_CTRL (0x68) -#define OMAP_SDRC_DLLB_STATUS (0x6C) -#define DLLPHASE (0x1 << 1) -#define LOADDLL (0x1 << 2) -#define DLL_DELAY_MASK 0xFF00 -#define DLL_NO_FILTER_MASK ((0x1 << 8)|(0x1 << 9)) - -#define OMAP_SDRC_POWER (0x70) -#define WAKEUPPROC (0x1 << 26) - -#define OMAP_SDRC_MCFG_0 (0x80) -#define OMAP_SDRC_MCFG_1 (0xB0) -#define OMAP_SDRC_MR_0 (0x84) -#define OMAP_SDRC_MR_1 (0xB4) -#define OMAP_SDRC_ACTIM_CTRLA_0 (0x9C) -#define OMAP_SDRC_ACTIM_CTRLB_0 (0xA0) -#define OMAP_SDRC_ACTIM_CTRLA_1 (0xC4) -#define OMAP_SDRC_ACTIM_CTRLB_1 (0xC8) -#define OMAP_SDRC_RFR_CTRL_0 (0xA4) -#define OMAP_SDRC_RFR_CTRL_1 (0xD4) -#define OMAP_SDRC_MANUAL_0 (0xA8) -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET (0x1 << 1) -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - -#define SDRC_CS0_OSET 0x0 -/* Mirror CS1 regs appear offset 0x30 from CS0 */ -#define SDRC_CS1_OSET 0x30 - -#define SDRC_STACKED 0 -#define SDRC_IP_DDR 1 -#define SDRC_COMBO_DDR 2 -#define SDRC_IP_SDR 3 - - -#define SDRC_B_R_C (0 << 6) /* bank-row-column */ -#define SDRC_B1_R_B0_C (1 << 6) /* bank1-row-bank0-column */ -#define SDRC_R_B_C (2 << 6) /* row-bank-column */ - -#define DLL_OFFSET 0 -#define DLL_WRITEDDRCLKX2DIS 1 -#define DLL_ENADLL 1 -#define DLL_LOCKDLL 0 -#define DLL_DLLPHASE_72 0 -#define DLL_DLLPHASE_90 1 - -#endif /* _ASM_ARCH_SDRC_H */ diff --git a/include/asm-arm/arch-omap/silicon.h b/include/asm-arm/arch-omap/silicon.h deleted file mode 100644 index df41a74f2f..0000000000 --- a/include/asm-arm/arch-omap/silicon.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_OMAP_SILICON_H -#define __ASM_ARCH_OMAP_SILICON_H - -/* Each platform silicon header comes here */ -#ifdef CONFIG_ARCH_OMAP3 -#include <asm/arch/omap3-silicon.h> -#endif - -/* If Architecture specific init functions are present */ -#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT -#ifndef __ASSEMBLY__ -void a_init(void); -#endif /* __ASSEMBLY__ */ -#endif - -#endif /* __ASM_ARCH_OMAP_SILICON_H */ diff --git a/include/asm-arm/arch-omap/sys_info.h b/include/asm-arm/arch-omap/sys_info.h deleted file mode 100644 index 43967209f1..0000000000 --- a/include/asm-arm/arch-omap/sys_info.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * @file - * @brief This file defines the macros apis which are useful for most OMAP - * platforms. - * - * FileName: include/asm-arm/arch-omap/sys_info.h - * - * These are implemented by the System specific code in omapX-generic.c - * - * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz - */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_SYS_INFO_H_ -#define __ASM_ARCH_SYS_INFO_H_ - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module*/ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_3430 0x3430 -#define CPU_2430 0x2430 -#define CPU_2420 0x2420 -#define CPU_1710 0x1710 -#define CPU_1610 0x1610 - -/** - * CPU revision - */ -#define CPU_ES1 1 -#define CPU_ES1P1 2 -#define CPU_ES1P2 3 -#define CPU_ES2 4 -#define CPU_ES2P1 5 -#define CPU_ES2P2 6 -#define CPU_ES3 7 -#define CPU_ES3P1 8 -#define CPU_ES3P2 9 -#define CPU_ES4 10 -#define CPU_ES4P1 11 -#define CPU_ES4P2 12 - -#define GPMC_MUXED 1 -#define GPMC_NONMUXED 0 - -#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ -#define TYPE_NOR 0x000 -#define TYPE_ONENAND 0x800 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/** These are implemented by the System specific code in omapX-generic.c */ -u32 get_cpu_type(void); -u32 get_cpu_rev(void); -u32 get_sdr_cs_size(u32 offset); -inline u32 get_sysboot_value(void); -u32 get_gpmc0_base(void); -u32 get_base(void); -u32 running_in_flash(void); -u32 running_in_sram(void); -u32 running_in_sdram(void); -u32 get_boot_type(void); -u32 get_device_type(void); - -#endif /*__ASM_ARCH_SYS_INFO_H_ */ diff --git a/include/asm-arm/arch-omap/syslib.h b/include/asm-arm/arch-omap/syslib.h deleted file mode 100644 index c89f50b816..0000000000 --- a/include/asm-arm/arch-omap/syslib.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * @file - * @brief These Apis are OMAP independent support functions - * - * FileName: include/asm-arm/arch-omap/syslib.h - * - * Implemented by arch/arm/mach-omap/syslib.c - * - * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz - */ -/* - * (C) Copyright 2004-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_OMAP_SYSLIB_H_ -#define __ASM_ARCH_OMAP_SYSLIB_H_ - -/** System Independent functions */ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value); -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); -void sdelay(unsigned long loops); - -/** All architectures need to implement these */ -void omap_uart_write(unsigned int val, unsigned long base, - unsigned char reg_idx); -unsigned int omap_uart_read(unsigned long base, unsigned char reg_idx); -#endif /* __ASM_ARCH_OMAP_SYSLIB_H_ */ diff --git a/include/asm-arm/arch-omap/timers.h b/include/asm-arm/arch-omap/timers.h deleted file mode 100644 index a93824378c..0000000000 --- a/include/asm-arm/arch-omap/timers.h +++ /dev/null @@ -1,60 +0,0 @@ -/** - * @file - * @brief This defines the Register defines for OMAP GPTimers and Sync32 timers. - * - * FileName: include/asm-arm/arch-omap/timers.h - * - * Originally from Linux kernel: - * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz - * - */ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * Copyright (C) 2007 Texas Instruments, <www.ti.com> - * Copyright (C) 2007 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_GPT_H -#define __ASM_ARCH_GPT_H - -/** General Purpose timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ -/* Enable sys_clk NO-prescale /1 */ -#define GPT_EN ((0 << 2) | (0x1 << 1) | (0x1 << 0)) - -/** Sync 32Khz Timer registers */ -#define S32K_CR (OMAP_32KTIMER_BASE + 0x10) -#define S32K_FREQUENCY 32768 - -#endif /*__ASM_ARCH_GPT_H */ diff --git a/include/asm-arm/arch-omap/wdt.h b/include/asm-arm/arch-omap/wdt.h deleted file mode 100644 index 532252d080..0000000000 --- a/include/asm-arm/arch-omap/wdt.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file - * @brief This file contains the Watchdog timer specific register definitions - * - * FileName: include/asm-arm/arch-omap/wdt.h - * - */ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_OMAP_WDT_H -#define __ASM_ARCH_OMAP_WDT_H - -/** Watchdog Register defines */ -#define WDT_REG(REGNAME) (OMAP_MPU_WDTIMER_BASE + OMAP_WDT_##REGNAME) -#define OMAP_WDT_WIDR (0x000) -#define OMAP_WDT_SYSCONFIG (0x010) -#define OMAP_WDT_WD_SYSSTATUS (0x014) -#define OMAP_WDT_WISR (0x018) -#define OMAP_WDT_WIER (0x01C) -#define OMAP_WDT_WCLR (0x024) -#define OMAP_WDT_WCRR (0x028) -#define OMAP_WDT_WLDR (0x02C) -#define OMAP_WDT_WTGR (0x030) -#define OMAP_WDT_WWPS (0x034) -#define OMAP_WDT_WSPR (0x048) - -/* Unlock Code for Watchdog timer to disable the same */ -#define WDT_DISABLE_CODE1 0xAAAA -#define WDT_DISABLE_CODE2 0x5555 - -#endif /* __ASM_ARCH_OMAP_WDT_H */ diff --git a/include/asm-arm/arch-s3c24xx/s3c24x0-iomap.h b/include/asm-arm/arch-s3c24xx/s3c24x0-iomap.h deleted file mode 100644 index ab3dc4f20a..0000000000 --- a/include/asm-arm/arch-s3c24xx/s3c24x0-iomap.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* S3C2410 device base addresses */ -#define S3C24X0_SDRAM_BASE 0x30000000 -#define S3C24X0_SDRAM_END 0x40000000 -#define S3C24X0_MEMCTL_BASE 0x48000000 -#define S3C2410_USB_HOST_BASE 0x49000000 -#define S3C2410_INTERRUPT_BASE 0x4A000000 -#define S3C2410_DMA_BASE 0x4B000000 -#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 -#define S3C2410_LCD_BASE 0x4D000000 -#define S3C24X0_NAND_BASE 0x4E000000 -#define S3C24X0_UART_BASE 0x50000000 -#define S3C24X0_TIMER_BASE 0x51000000 -#define S3C2410_USB_DEVICE_BASE 0x52000140 -#define S3C24X0_WATCHDOG_BASE 0x53000000 -#define S3C2410_I2C_BASE 0x54000000 -#define S3C2410_I2S_BASE 0x55000000 -#define S3C24X0_GPIO_BASE 0x56000000 -#define S3C2410_RTC_BASE 0x57000000 -#define S3C2410_ADC_BASE 0x58000000 -#define S3C2410_SPI_BASE 0x59000000 -#define S3C2410_SDI_BASE 0x5A000000 - -/* Clock control (direct access) */ - -#define LOCKTIME (S3C24X0_CLOCK_POWER_BASE) -#define MPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x4) -#define UPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x8) -#define CLKCON (S3C24X0_CLOCK_POWER_BASE + 0xc) -#define CLKSLOW (S3C24X0_CLOCK_POWER_BASE + 0x10) -#define CLKDIVN (S3C24X0_CLOCK_POWER_BASE + 0x14) - -/* Timer (direct access) */ -#define TCFG0 (S3C24X0_TIMER_BASE + 0x00) -#define TCFG1 (S3C24X0_TIMER_BASE + 0x04) -#define TCON (S3C24X0_TIMER_BASE + 0x08) -#define TCNTB0 (S3C24X0_TIMER_BASE + 0x0c) -#define TCMPB0 (S3C24X0_TIMER_BASE + 0x10) -#define TCNTO0 (S3C24X0_TIMER_BASE + 0x14) -#define TCNTB1 (S3C24X0_TIMER_BASE + 0x18) -#define TCMPB1 (S3C24X0_TIMER_BASE + 0x1c) -#define TCNTO1 (S3C24X0_TIMER_BASE + 0x20) -#define TCNTB2 (S3C24X0_TIMER_BASE + 0x24) -#define TCMPB2 (S3C24X0_TIMER_BASE + 0x28) -#define TCNTO2 (S3C24X0_TIMER_BASE + 0x2c) -#define TCNTB3 (S3C24X0_TIMER_BASE + 0x30) -#define TCMPB3 (S3C24X0_TIMER_BASE + 0x34) -#define TCNTO3 (S3C24X0_TIMER_BASE + 0x38) -#define TCNTB4 (S3C24X0_TIMER_BASE + 0x3c) -#define TCNTO4 (S3C24X0_TIMER_BASE + 0x40) - -/* Watchdog (direct access) */ -#define WTCON (S3C24X0_WATCHDOG_BASE) -#define WTDAT (S3C24X0_WATCHDOG_BASE + 0x04) -#define WTCNT (S3C24X0_WATCHDOG_BASE + 0x08) - -/* - * if we are booting from NAND, its internal SRAM occures at - * a different address than without this feature - */ -#ifdef CONFIG_S3C24XX_NAND_BOOT -# define NFC_RAM_AREA 0x00000000 -#else -# define NFC_RAM_AREA 0x40000000 -#endif -#define NFC_RAM_SIZE 4096 - -/* internal UARTs (driver based) */ -#define UART1_BASE (S3C24X0_UART_BASE) -#define UART1_SIZE 0x4000 -#define UART2_BASE (S3C24X0_UART_BASE + 0x4000) -#define UART3_SIZE 0x4000 -#define UART3_BASE (S3C24X0_UART_BASE + 0x8000) -#define UART3_SIZE 0x4000 - -/* CS configuration (direct access) */ -#define BWSCON (S3C24X0_MEMCTL_BASE) -#define BANKCON0 (S3C24X0_MEMCTL_BASE + 0x04) -#define BANKCON1 (S3C24X0_MEMCTL_BASE + 0x08) -#define BANKCON2 (S3C24X0_MEMCTL_BASE + 0x0c) -#define BANKCON3 (S3C24X0_MEMCTL_BASE + 0x10) -#define BANKCON4 (S3C24X0_MEMCTL_BASE + 0x14) -#define BANKCON5 (S3C24X0_MEMCTL_BASE + 0x18) -#define BANKCON6 (S3C24X0_MEMCTL_BASE + 0x1c) -#define BANKCON7 (S3C24X0_MEMCTL_BASE + 0x20) -#define REFRESH (S3C24X0_MEMCTL_BASE + 0x24) -#define BANKSIZE (S3C24X0_MEMCTL_BASE + 0x28) -#define MRSRB6 (S3C24X0_MEMCTL_BASE + 0x2c) -#define MRSRB7 (S3C24X0_MEMCTL_BASE + 0x30) - -/* GPIO registers (direct access) */ -#define GPACON (S3C24X0_GPIO_BASE) -#define GPADAT (S3C24X0_GPIO_BASE + 0x04) - -#define GPBCON (S3C24X0_GPIO_BASE + 0x10) -#define GPBDAT (S3C24X0_GPIO_BASE + 0x14) -#define GPBUP (S3C24X0_GPIO_BASE + 0x18) - -#define GPCCON (S3C24X0_GPIO_BASE + 0x20) -#define GPCDAT (S3C24X0_GPIO_BASE + 0x24) -#define GPCUP (S3C24X0_GPIO_BASE + 0x28) - -#define GPDCON (S3C24X0_GPIO_BASE + 0x30) -#define GPDDAT (S3C24X0_GPIO_BASE + 0x34) -#define GPDUP (S3C24X0_GPIO_BASE + 0x38) - -#define GPECON (S3C24X0_GPIO_BASE + 0x40) -#define GPEDAT (S3C24X0_GPIO_BASE + 0x44) -#define GPEUP (S3C24X0_GPIO_BASE + 0x48) - -#define GPFCON (S3C24X0_GPIO_BASE + 0x50) -#define GPFDAT (S3C24X0_GPIO_BASE + 0x54) -#define GPFUP (S3C24X0_GPIO_BASE + 0x58) - -#define GPGCON (S3C24X0_GPIO_BASE + 0x60) -#define GPGDAT (S3C24X0_GPIO_BASE + 0x64) -#define GPGUP (S3C24X0_GPIO_BASE + 0x68) - -#define GPHCON (S3C24X0_GPIO_BASE + 0x70) -#define GPHDAT (S3C24X0_GPIO_BASE + 0x74) -#define GPHUP (S3C24X0_GPIO_BASE + 0x78) - -#ifdef CONFIG_CPU_S3C2440 -# define GPJCON (S3C24X0_GPIO_BASE + 0xd0) -# define GPJDAT (S3C24X0_GPIO_BASE + 0xd4) -# define GPJUP (S3C24X0_GPIO_BASE + 0xd8) -#endif - -#define MISCCR (S3C24X0_GPIO_BASE + 0x80) -#define DCLKCON (S3C24X0_GPIO_BASE + 0x84) -#define EXTINT0 (S3C24X0_GPIO_BASE + 0x88) -#define EXTINT1 (S3C24X0_GPIO_BASE + 0x8c) -#define EXTINT2 (S3C24X0_GPIO_BASE + 0x90) -#define EINTFLT0 (S3C24X0_GPIO_BASE + 0x94) -#define EINTFLT1 (S3C24X0_GPIO_BASE + 0x98) -#define EINTFLT2 (S3C24X0_GPIO_BASE + 0x9c) -#define EINTFLT3 (S3C24X0_GPIO_BASE + 0xa0) -#define EINTMASK (S3C24X0_GPIO_BASE + 0xa4) -#define EINTPEND (S3C24X0_GPIO_BASE + 0xa8) -#define GSTATUS0 (S3C24X0_GPIO_BASE + 0xac) -#define GSTATUS1 (S3C24X0_GPIO_BASE + 0xb0) -#define GSTATUS2 (S3C24X0_GPIO_BASE + 0xb4) -#define GSTATUS3 (S3C24X0_GPIO_BASE + 0xb8) -#define GSTATUS4 (S3C24X0_GPIO_BASE + 0xbc) - -#ifdef CONFIG_CPU_S3C2440 -# define DSC0 (S3C24X0_GPIO_BASE + 0xc4) -# define DSC1 (S3C24X0_GPIO_BASE + 0xc8) -#endif - -/* external IO space */ -#define CS0_BASE 0x00000000 -#define CS1_BASE 0x08000000 -#define CS2_BASE 0x10000000 -#define CS3_BASE 0x18000000 -#define CS4_BASE 0x20000000 -#define CS5_BASE 0x28000000 -#define CS6_BASE 0x30000000 diff --git a/include/asm-arm/arch-s3c24xx/s3c24x0-nand.h b/include/asm-arm/arch-s3c24xx/s3c24x0-nand.h deleted file mode 100644 index 05f9cf0fd1..0000000000 --- a/include/asm-arm/arch-s3c24xx/s3c24x0-nand.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifdef CONFIG_S3C24XX_NAND_BOOT -extern void s3c24x0_nand_load_image(void*, int, int, int); -#endif - -/** - * Locate the timing bits for the NFCONF register - * @param setup is the TACLS clock count - * @param access is the TWRPH0 clock count - * @param hold is the TWRPH1 clock count - * - * @note A clock count of 0 means always 1 HCLK clock. - * @note Clock count settings depend on the NAND flash requirements and the current HCLK speed - */ -#ifdef CONFIG_CPU_S3C2410 -# define CALC_NFCONF_TIMING(setup, access, hold) \ - ((setup << 8) + (access << 4) + (hold << 0)) -#endif -#ifdef CONFIG_CPU_S3C2440 -# define CALC_NFCONF_TIMING(setup, access, hold) \ - ((setup << 12) + (access << 8) + (hold << 4)) -#endif - -/** - * Define platform specific data for the NAND controller and its device - */ -struct s3c24x0_nand_platform_data { - uint32_t nand_timing; /**< value for the NFCONF register (timing bits only) */ -}; - -/** - * @file - * @brief Basic declaration to use the s3c24x0 NAND driver - */ diff --git a/include/asm-arm/arch-s3c24xx/s3c24xx-generic.h b/include/asm-arm/arch-s3c24xx/s3c24xx-generic.h deleted file mode 100644 index b8abcf1d9c..0000000000 --- a/include/asm-arm/arch-s3c24xx/s3c24xx-generic.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2009 - * Juergen Beisert, Pengutronix - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -uint32_t s3c24xx_get_mpllclk(void); -uint32_t s3c24xx_get_upllclk(void); -uint32_t s3c24xx_get_fclk(void); -uint32_t s3c24xx_get_hclk(void); -uint32_t s3c24xx_get_pclk(void); -uint32_t s3c24xx_get_uclk(void); -uint32_t s3c24x0_get_memory_size(void); diff --git a/include/asm-arm/armlinux.h b/include/asm-arm/armlinux.h deleted file mode 100644 index cfe57f4f71..0000000000 --- a/include/asm-arm/armlinux.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __ARCH_ARMLINUX_H -#define __ARCH_ARMLINUX_H - -#if defined CONFIG_CMD_BOOTM || defined CONFIG_CMD_BOOTZ || \ - defined CONFIG_CMD_BOOTU -void armlinux_set_bootparams(void *params); -void armlinux_set_architecture(int architecture); -void armlinux_add_dram(struct device_d *dev); -#else -static inline void armlinux_set_bootparams(void *params) -{ -} - -static inline void armlinux_set_architecture(int architecture) -{ -} - -static inline void armlinux_add_dram(struct device_d *dev) -{ -} -#endif - -#endif /* __ARCH_ARMLINUX_H */ diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h deleted file mode 100644 index 6116e4893c..0000000000 --- a/include/asm-arm/assembler.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * arch/arm/include/asm/assembler.h - * - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This file contains arm architecture specific defines - * for the different processors. - * - * Do not include any C declarations in this file - it is included by - * assembler source. - */ -#ifndef __ASSEMBLY__ -#error "Only include this from assembly code" -#endif - -#include <asm/ptrace.h> - -/* - * Endian independent macros for shifting bytes within registers. - */ -#ifndef __ARMEB__ -#define pull lsr -#define push lsl -#define get_byte_0 lsl #0 -#define get_byte_1 lsr #8 -#define get_byte_2 lsr #16 -#define get_byte_3 lsr #24 -#define put_byte_0 lsl #0 -#define put_byte_1 lsl #8 -#define put_byte_2 lsl #16 -#define put_byte_3 lsl #24 -#else -#define pull lsl -#define push lsr -#define get_byte_0 lsr #24 -#define get_byte_1 lsr #16 -#define get_byte_2 lsr #8 -#define get_byte_3 lsl #0 -#define put_byte_0 lsl #24 -#define put_byte_1 lsl #16 -#define put_byte_2 lsl #8 -#define put_byte_3 lsl #0 -#endif - -/* - * Data preload for architectures that support it - */ -#if __LINUX_ARM_ARCH__ >= 5 -#define PLD(code...) code -#else -#define PLD(code...) -#endif - -/* - * This can be used to enable code to cacheline align the destination - * pointer when bulk writing to memory. Experiments on StrongARM and - * XScale didn't show this a worthwhile thing to do when the cache is not - * set to write-allocate (this would need further testing on XScale when WA - * is used). - * - * On Feroceon there is much to gain however, regardless of cache mode. - */ -#ifdef CONFIG_CPU_FEROCEON -#define CALGN(code...) code -#else -#define CALGN(code...) -#endif - -/* - * Enable and disable interrupts - */ -#if __LINUX_ARM_ARCH__ >= 6 - .macro disable_irq - cpsid i - .endm - - .macro enable_irq - cpsie i - .endm -#else - .macro disable_irq - msr cpsr_c, #PSR_I_BIT | SVC_MODE - .endm - - .macro enable_irq - msr cpsr_c, #SVC_MODE - .endm -#endif - -/* - * Save the current IRQ state and disable IRQs. Note that this macro - * assumes FIQs are enabled, and that the processor is in SVC mode. - */ - .macro save_and_disable_irqs, oldcpsr - mrs \oldcpsr, cpsr - disable_irq - .endm - -/* - * Restore interrupt state previously stored in a register. We don't - * guarantee that this will preserve the flags. - */ - .macro restore_irqs, oldcpsr - msr cpsr_c, \oldcpsr - .endm - -#define USER(x...) \ -9999: x; \ - .section __ex_table,"a"; \ - .align 3; \ - .long 9999b,9001f; \ - .previous diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h deleted file mode 100644 index 138ebe2d8c..0000000000 --- a/include/asm-arm/bitops.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright 1995, Russell King. - * Various bits and pieces copyrights include: - * Linus Torvalds (test_bit). - * - * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). - * - * Please note that the code in this file should never be included - * from user space. Many of these are not implemented in assembler - * since they would be too costly. Also, they require priviledged - * instructions (which are not available from user mode) to ensure - * that they are atomic. - */ - -#ifndef __ASM_ARM_BITOPS_H -#define __ASM_ARM_BITOPS_H - -#ifndef _LINUX_BITOPS_H -#error only <linux/bitops.h> can be included directly -#endif - -/* - * Functions equivalent of ops.h - */ -static inline void __set_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7)); -} - -static inline void __clear_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7)); -} - -static inline void __change_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] ^= (1U << (nr & 7)); -} - -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; - - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval | mask; - return oldval & mask; -} - -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; - - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval & ~mask; - return oldval & mask; -} - -static inline int __test_and_change_bit(int nr, volatile void *addr) -{ - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; - - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval ^ mask; - return oldval & mask; -} - -/* - * This routine doesn't need to be atomic. - */ -static inline int test_bit(int nr, const void * addr) -{ - return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); -} - -#define set_bit(x, y) __set_bit(x, y) -#define clear_bit(x, y) __clear_bit(x, y) -#define change_bit(x, y) __change_bit(x, y) -#define test_and_set_bit(x, y) __test_and_set_bit(x, y) -#define test_and_clear_bit(x, y) __test_and_clear_bit(x, y) -#define test_and_change_bit(x, y) __test_and_change_bit(x, y) - -#ifndef __ARMEB__ -/* - * These are the little endian definitions. - */ -extern int _find_first_zero_bit_le(const void *p, unsigned size); -extern int _find_next_zero_bit_le(const void *p, int size, int offset); -extern int _find_first_bit_le(const unsigned long *p, unsigned size); -extern int _find_next_bit_le(const unsigned long *p, int size, int offset); -#define find_first_zero_bit(p, sz) _find_first_zero_bit_le(p, sz) -#define find_next_zero_bit(p, sz, off) _find_next_zero_bit_le(p, sz, off) -#define find_first_bit(p, sz) _find_first_bit_le(p, sz) -#define find_next_bit(p, sz, off) _find_next_bit_le(p, sz, off) - -#define WORD_BITOFF_TO_LE(x) ((x)) - -#else /* ! __ARMEB__ */ - -/* - * These are the big endian definitions. - */ -extern int _find_first_zero_bit_be(const void *p, unsigned size); -extern int _find_next_zero_bit_be(const void *p, int size, int offset); -extern int _find_first_bit_be(const unsigned long *p, unsigned size); -extern int _find_next_bit_be(const unsigned long *p, int size, int offset); -#define find_first_zero_bit(p, sz) _find_first_zero_bit_be(p, sz) -#define find_next_zero_bit(p, sz, off) _find_next_zero_bit_be(p, sz, off) -#define find_first_bit(p, sz) _find_first_bit_be(p, sz) -#define find_next_bit(p, sz, off) _find_next_bit_be(p, sz, off) - -#define WORD_BITOFF_TO_LE(x) ((x) ^ 0x18) - -#endif /* __ARMEB__ */ - -#if defined(__LINUX_ARM_ARCH__) && (__LINUX_ARM_ARCH__ >= 5) -static inline int constant_fls(int x) -{ - int r = 32; - - if (!x) - return 0; - if (!(x & 0xffff0000u)) { - x <<= 16; - r -= 16; - } - if (!(x & 0xff000000u)) { - x <<= 8; - r -= 8; - } - if (!(x & 0xf0000000u)) { - x <<= 4; - r -= 4; - } - if (!(x & 0xc0000000u)) { - x <<= 2; - r -= 2; - } - if (!(x & 0x80000000u)) { - x <<= 1; - r -= 1; - } - return r; -} - -/* - * On ARMv5 and above those functions can be implemented around - * the clz instruction for much better code efficiency. - */ -#define fls(x) \ - (__builtin_constant_p(x) ? constant_fls(x) : \ - ({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; })) -#define ffs(x) ({ unsigned long __t = (x); fls(__t &-__t); }) -#define __ffs(x) (ffs(x) - 1) -#define ffz(x) __ffs(~(x)) -#else /* ! __ARM__USE_GENERIC_FF */ -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz(unsigned long word) -{ - int k; - - word = ~word; - k = 31; - if (word & 0x0000ffff) { k -= 16; word <<= 16; } - if (word & 0x00ff0000) { k -= 8; word <<= 8; } - if (word & 0x0f000000) { k -= 4; word <<= 4; } - if (word & 0x30000000) { k -= 2; word <<= 2; } - if (word & 0x40000000) { k -= 1; } - return k; -} -#include <asm-generic/bitops/__ffs.h> -#include <asm-generic/bitops/ffs.h> -#include <asm-generic/bitops/fls.h> -#endif /* __ARM__USE_GENERIC_FF */ -#include <asm-generic/bitops/fls64.h> - -#include <asm-generic/bitops/hweight.h> - -#endif /* _ARM_BITOPS_H */ diff --git a/include/asm-arm/byteorder.h b/include/asm-arm/byteorder.h deleted file mode 100644 index c3489f1e1f..0000000000 --- a/include/asm-arm/byteorder.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * linux/include/asm-arm/byteorder.h - * - * ARM Endian-ness. In little endian mode, the data bus is connected such - * that byte accesses appear as: - * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 - * and word accesses (data or instruction) appear as: - * d0...d31 - * - * When in big endian mode, byte accesses appear as: - * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 - * and word accesses (data or instruction) appear as: - * d0...d31 - */ -#ifndef __ASM_ARM_BYTEORDER_H -#define __ASM_ARM_BYTEORDER_H - - -#include <asm/types.h> - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#ifdef __ARMEB__ -#include <linux/byteorder/big_endian.h> -#else -#include <linux/byteorder/little_endian.h> -#endif - -#endif diff --git a/include/asm-arm/cache-l2x0.h b/include/asm-arm/cache-l2x0.h deleted file mode 100644 index 19c3ba42ae..0000000000 --- a/include/asm-arm/cache-l2x0.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * arch/arm/include/asm/hardware/cache-l2x0.h - * - * Copyright (C) 2007 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARM_HARDWARE_L2X0_H -#define __ASM_ARM_HARDWARE_L2X0_H - -#define L2X0_CACHE_ID 0x000 -#define L2X0_CACHE_TYPE 0x004 -#define L2X0_CTRL 0x100 -#define L2X0_AUX_CTRL 0x104 -#define L2X0_EVENT_CNT_CTRL 0x200 -#define L2X0_EVENT_CNT1_CFG 0x204 -#define L2X0_EVENT_CNT0_CFG 0x208 -#define L2X0_EVENT_CNT1_VAL 0x20C -#define L2X0_EVENT_CNT0_VAL 0x210 -#define L2X0_INTR_MASK 0x214 -#define L2X0_MASKED_INTR_STAT 0x218 -#define L2X0_RAW_INTR_STAT 0x21C -#define L2X0_INTR_CLEAR 0x220 -#define L2X0_CACHE_SYNC 0x730 -#define L2X0_INV_LINE_PA 0x770 -#define L2X0_INV_WAY 0x77C -#define L2X0_CLEAN_LINE_PA 0x7B0 -#define L2X0_CLEAN_LINE_IDX 0x7B8 -#define L2X0_CLEAN_WAY 0x7BC -#define L2X0_CLEAN_INV_LINE_PA 0x7F0 -#define L2X0_CLEAN_INV_LINE_IDX 0x7F8 -#define L2X0_CLEAN_INV_WAY 0x7FC -#define L2X0_LOCKDOWN_WAY_D 0x900 -#define L2X0_LOCKDOWN_WAY_I 0x904 -#define L2X0_TEST_OPERATION 0xF00 -#define L2X0_LINE_DATA 0xF10 -#define L2X0_LINE_TAG 0xF30 -#define L2X0_DEBUG_CTRL 0xF40 - -#endif diff --git a/include/asm-arm/common.h b/include/asm-arm/common.h deleted file mode 100644 index da84fa5f6b..0000000000 --- a/include/asm-arm/common.h +++ /dev/null @@ -1 +0,0 @@ -/* nothing */ diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h deleted file mode 100644 index 724ebb0787..0000000000 --- a/include/asm-arm/elf.h +++ /dev/null @@ -1,119 +0,0 @@ -#ifndef __ASMARM_ELF_H -#define __ASMARM_ELF_H - -//#include <asm/hwcap.h> - -#ifndef __ASSEMBLY__ -/* - * ELF register definitions.. - */ -#include <asm/ptrace.h> -//#include <asm/user.h> - -typedef unsigned long elf_greg_t; -typedef unsigned long elf_freg_t[3]; - -#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -typedef struct user_fp elf_fpregset_t; -#endif - -#define EM_ARM 40 -#define EF_ARM_APCS26 0x08 -#define EF_ARM_SOFT_FLOAT 0x200 -#define EF_ARM_EABI_MASK 0xFF000000 - -#define R_ARM_NONE 0 -#define R_ARM_PC24 1 -#define R_ARM_ABS32 2 -#define R_ARM_CALL 28 -#define R_ARM_JUMP24 29 - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 -#ifdef __ARMEB__ -#define ELF_DATA ELFDATA2MSB -#else -#define ELF_DATA ELFDATA2LSB -#endif -#define ELF_ARCH EM_ARM - -#ifdef __KERNEL__ -#ifndef __ASSEMBLY__ -/* - * This yields a string that ld.so will use to load implementation - * specific libraries for optimization. This is more specific in - * intent than poking at uname or /proc/cpuinfo. - * - * For now we just provide a fairly general string that describes the - * processor family. This could be made more specific later if someone - * implemented optimisations that require it. 26-bit CPUs give you - * "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't - * supported). 32-bit CPUs give you "v3[lb]" for anything based on an - * ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1 - * core. - */ -#define ELF_PLATFORM_SIZE 8 -#define ELF_PLATFORM (elf_platform) - -extern char elf_platform[]; -#endif - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) ((x)->e_machine == EM_ARM && ELF_PROC_OK(x)) - -/* - * 32-bit code is always OK. Some cpus can do 26-bit, some can't. - */ -#define ELF_PROC_OK(x) (ELF_THUMB_OK(x) && ELF_26BIT_OK(x)) - -#define ELF_THUMB_OK(x) \ - ((elf_hwcap & HWCAP_THUMB && ((x)->e_entry & 1) == 1) || \ - ((x)->e_entry & 3) == 0) - -#define ELF_26BIT_OK(x) \ - ((elf_hwcap & HWCAP_26BIT && (x)->e_flags & EF_ARM_APCS26) || \ - ((x)->e_flags & EF_ARM_APCS26) == 0) - -#define USE_ELF_CORE_DUMP -#define ELF_EXEC_PAGESIZE 4096 - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) - -/* When the program starts, a1 contains a pointer to a function to be - registered with atexit, as per the SVR4 ABI. A value of 0 means we - have no such handler. */ -#define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0 - -/* - * Since the FPA coprocessor uses CP1 and CP2, and iWMMXt uses CP0 - * and CP1, we only enable access to the iWMMXt coprocessor if the - * binary is EABI or softfloat (and thus, guaranteed not to use - * FPA instructions.) - */ -#define SET_PERSONALITY(ex, ibcs2) \ - do { \ - if ((ex).e_flags & EF_ARM_APCS26) { \ - set_personality(PER_LINUX); \ - } else { \ - set_personality(PER_LINUX_32BIT); \ - if (elf_hwcap & HWCAP_IWMMXT && (ex).e_flags & (EF_ARM_EABI_MASK | EF_ARM_SOFT_FLOAT)) \ - set_thread_flag(TIF_USING_IWMMXT); \ - else \ - clear_thread_flag(TIF_USING_IWMMXT); \ - } \ - } while (0) - -#endif - -#endif diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h deleted file mode 100644 index 51d9405d65..0000000000 --- a/include/asm-arm/global_data.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H -typedef struct global_data gd_t; - -#define DECLARE_GLOBAL_DATA_PTR - -#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-arm/gpio.h b/include/asm-arm/gpio.h deleted file mode 100644 index fff4f800ee..0000000000 --- a/include/asm-arm/gpio.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _ARCH_ARM_GPIO_H -#define _ARCH_ARM_GPIO_H - -/* not all ARM platforms necessarily support this API ... */ -#include <asm/arch/gpio.h> - -#endif /* _ARCH_ARM_GPIO_H */ diff --git a/include/asm-arm/hardware.h b/include/asm-arm/hardware.h deleted file mode 100644 index 1fd1a5b650..0000000000 --- a/include/asm-arm/hardware.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * linux/include/asm-arm/hardware.h - * - * Copyright (C) 1996 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Common hardware definitions - */ - -#ifndef __ASM_HARDWARE_H -#define __ASM_HARDWARE_H - -#include <asm/arch/hardware.h> - -#endif diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h deleted file mode 100644 index c7f4b62c44..0000000000 --- a/include/asm-arm/io.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * linux/include/asm-arm/io.h - * - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Modifications: - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions - */ - -/** - * @file - * @brief ARM IO access functions - */ - -#ifndef __ASM_ARM_IO_H -#define __ASM_ARM_IO_H - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - -#define writeb(v,a) __raw_writeb(v,a) -#define writew(v,a) __raw_writew(v,a) -#define writel(v,a) __raw_writel(v,a) - -#define readb(a) __raw_readb(a) -#define readw(a) __raw_readw(a) -#define readl(a) __raw_readl(a) - -/* for the ARM architecture the string functions are library based */ -extern void writesb(void __iomem*, const void*, int); -extern void writesw(void __iomem*, const void*, int); -extern void writesl(void __iomem*, const void*, int); -extern void readsb(const void __iomem*, void*, int); -extern void readsw(const void __iomem*, void*, int); -extern void readsl(const void __iomem*, void*, int); - -#endif /* __ASM_ARM_IO_H */ diff --git a/include/asm-arm/linkage.h b/include/asm-arm/linkage.h deleted file mode 100644 index 5a25632b1b..0000000000 --- a/include/asm-arm/linkage.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __ASM_LINKAGE_H -#define __ASM_LINKAGE_H - -#define __ALIGN .align 0 -#define __ALIGN_STR ".align 0" - -#define ENDPROC(name) \ - .type name, %function; \ - END(name) - -#endif diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h deleted file mode 100644 index f9df50a70c..0000000000 --- a/include/asm-arm/mach-types.h +++ /dev/null @@ -1,26622 +0,0 @@ -/* - * This was automagically generated from arch/arm/tools/mach-types! - * Do NOT edit - */ - -#ifndef __ASM_ARM_MACH_TYPE_H -#define __ASM_ARM_MACH_TYPE_H - -#ifndef __ASSEMBLY__ -/* The type of machine we're running on */ -extern unsigned int __machine_arch_type; -#endif - -/* see arch/arm/kernel/arch.c for a description of these */ -#define MACH_TYPE_EBSA110 0 -#define MACH_TYPE_RISCPC 1 -#define MACH_TYPE_NEXUSPCI 3 -#define MACH_TYPE_EBSA285 4 -#define MACH_TYPE_NETWINDER 5 -#define MACH_TYPE_CATS 6 -#define MACH_TYPE_TBOX 7 -#define MACH_TYPE_CO285 8 -#define MACH_TYPE_CLPS7110 9 -#define MACH_TYPE_ARCHIMEDES 10 -#define MACH_TYPE_A5K 11 -#define MACH_TYPE_ETOILE 12 -#define MACH_TYPE_LACIE_NAS 13 -#define MACH_TYPE_CLPS7500 14 -#define MACH_TYPE_SHARK 15 -#define MACH_TYPE_BRUTUS 16 -#define MACH_TYPE_PERSONAL_SERVER 17 -#define MACH_TYPE_ITSY 18 -#define MACH_TYPE_L7200 19 -#define MACH_TYPE_PLEB 20 -#define MACH_TYPE_INTEGRATOR 21 -#define MACH_TYPE_H3600 22 -#define MACH_TYPE_IXP1200 23 -#define MACH_TYPE_P720T 24 -#define MACH_TYPE_ASSABET 25 -#define MACH_TYPE_VICTOR 26 -#define MACH_TYPE_LART 27 -#define MACH_TYPE_RANGER 28 -#define MACH_TYPE_GRAPHICSCLIENT 29 -#define MACH_TYPE_XP860 30 -#define MACH_TYPE_CERF 31 -#define MACH_TYPE_NANOENGINE 32 -#define MACH_TYPE_FPIC 33 -#define MACH_TYPE_EXTENEX1 34 -#define MACH_TYPE_SHERMAN 35 -#define MACH_TYPE_ACCELENT_SA 36 -#define MACH_TYPE_ACCELENT_L7200 37 -#define MACH_TYPE_NETPORT 38 -#define MACH_TYPE_PANGOLIN 39 -#define MACH_TYPE_YOPY 40 -#define MACH_TYPE_COOLIDGE 41 -#define MACH_TYPE_HUW_WEBPANEL 42 -#define MACH_TYPE_SPOTME 43 -#define MACH_TYPE_FREEBIRD 44 -#define MACH_TYPE_TI925 45 -#define MACH_TYPE_RISCSTATION 46 -#define MACH_TYPE_CAVY 47 -#define MACH_TYPE_JORNADA720 48 -#define MACH_TYPE_OMNIMETER 49 -#define MACH_TYPE_EDB7211 50 -#define MACH_TYPE_CITYGO 51 -#define MACH_TYPE_PFS168 52 -#define MACH_TYPE_SPOT 53 -#define MACH_TYPE_FLEXANET 54 -#define MACH_TYPE_WEBPAL 55 -#define MACH_TYPE_LINPDA 56 -#define MACH_TYPE_ANAKIN 57 -#define MACH_TYPE_MVI 58 -#define MACH_TYPE_JUPITER 59 -#define MACH_TYPE_PSIONW 60 -#define MACH_TYPE_ALN 61 -#define MACH_TYPE_CAMELOT 62 -#define MACH_TYPE_GDS2200 63 -#define MACH_TYPE_PSION_SERIES7 64 -#define MACH_TYPE_XFILE 65 -#define MACH_TYPE_ACCELENT_EP9312 66 -#define MACH_TYPE_IC200 67 -#define MACH_TYPE_CREDITLART 68 -#define MACH_TYPE_HTM 69 -#define MACH_TYPE_IQ80310 70 -#define MACH_TYPE_FREEBOT 71 -#define MACH_TYPE_ENTEL 72 -#define MACH_TYPE_ENP3510 73 -#define MACH_TYPE_TRIZEPS 74 -#define MACH_TYPE_NESA 75 -#define MACH_TYPE_VENUS 76 -#define MACH_TYPE_TARDIS 77 -#define MACH_TYPE_MERCURY 78 -#define MACH_TYPE_EMPEG 79 -#define MACH_TYPE_I80200FCC 80 -#define MACH_TYPE_ITT_CPB 81 -#define MACH_TYPE_SVC 82 -#define MACH_TYPE_ALPHA2 84 -#define MACH_TYPE_ALPHA1 85 -#define MACH_TYPE_NETARM 86 -#define MACH_TYPE_SIMPAD 87 -#define MACH_TYPE_PDA1 88 -#define MACH_TYPE_LUBBOCK 89 -#define MACH_TYPE_ANIKO 90 -#define MACH_TYPE_CLEP7212 91 -#define MACH_TYPE_CS89712 92 -#define MACH_TYPE_WEARARM 93 -#define MACH_TYPE_POSSIO_PX 94 -#define MACH_TYPE_SIDEARM 95 -#define MACH_TYPE_STORK 96 -#define MACH_TYPE_SHANNON 97 -#define MACH_TYPE_ACE 98 -#define MACH_TYPE_BALLYARM 99 -#define MACH_TYPE_SIMPUTER 100 -#define MACH_TYPE_NEXTERM 101 -#define MACH_TYPE_SA1100_ELF 102 -#define MACH_TYPE_GATOR 103 -#define MACH_TYPE_GRANITE 104 -#define MACH_TYPE_CONSUS 105 -#define MACH_TYPE_AAED2000 106 -#define MACH_TYPE_CDB89712 107 -#define MACH_TYPE_GRAPHICSMASTER 108 -#define MACH_TYPE_ADSBITSY 109 -#define MACH_TYPE_PXA_IDP 110 -#define MACH_TYPE_PLCE 111 -#define MACH_TYPE_PT_SYSTEM3 112 -#define MACH_TYPE_MEDALB 113 -#define MACH_TYPE_EAGLE 114 -#define MACH_TYPE_DSC21 115 -#define MACH_TYPE_DSC24 116 -#define MACH_TYPE_TI5472 117 -#define MACH_TYPE_AUTCPU12 118 -#define MACH_TYPE_UENGINE 119 -#define MACH_TYPE_BLUESTEM 120 -#define MACH_TYPE_XINGU8 121 -#define MACH_TYPE_BUSHSTB 122 -#define MACH_TYPE_EPSILON1 123 -#define MACH_TYPE_BALLOON 124 -#define MACH_TYPE_PUPPY 125 -#define MACH_TYPE_ELROY 126 -#define MACH_TYPE_GMS720 127 -#define MACH_TYPE_S24X 128 -#define MACH_TYPE_JTEL_CLEP7312 129 -#define MACH_TYPE_CX821XX 130 -#define MACH_TYPE_EDB7312 131 -#define MACH_TYPE_BSA1110 132 -#define MACH_TYPE_POWERPIN 133 -#define MACH_TYPE_OPENARM 134 -#define MACH_TYPE_WHITECHAPEL 135 -#define MACH_TYPE_H3100 136 -#define MACH_TYPE_H3800 137 -#define MACH_TYPE_BLUE_V1 138 -#define MACH_TYPE_PXA_CERF 139 -#define MACH_TYPE_ARM7TEVB 140 -#define MACH_TYPE_D7400 141 -#define MACH_TYPE_PIRANHA 142 -#define MACH_TYPE_SBCAMELOT 143 -#define MACH_TYPE_KINGS 144 -#define MACH_TYPE_SMDK2400 145 -#define MACH_TYPE_COLLIE 146 -#define MACH_TYPE_IDR 147 -#define MACH_TYPE_BADGE4 148 -#define MACH_TYPE_WEBNET 149 -#define MACH_TYPE_D7300 150 -#define MACH_TYPE_CEP 151 -#define MACH_TYPE_FORTUNET 152 -#define MACH_TYPE_VC547X 153 -#define MACH_TYPE_FILEWALKER 154 -#define MACH_TYPE_NETGATEWAY 155 -#define MACH_TYPE_SYMBOL2800 156 -#define MACH_TYPE_SUNS 157 -#define MACH_TYPE_FRODO 158 -#define MACH_TYPE_MACH_TYTE_MS301 159 -#define MACH_TYPE_MX1ADS 160 -#define MACH_TYPE_H7201 161 -#define MACH_TYPE_H7202 162 -#define MACH_TYPE_AMICO 163 -#define MACH_TYPE_IAM 164 -#define MACH_TYPE_TT530 165 -#define MACH_TYPE_SAM2400 166 -#define MACH_TYPE_JORNADA56X 167 -#define MACH_TYPE_ACTIVE 168 -#define MACH_TYPE_IQ80321 169 -#define MACH_TYPE_WID 170 -#define MACH_TYPE_SABINAL 171 -#define MACH_TYPE_IXP425_MATACUMBE 172 -#define MACH_TYPE_MINIPRINT 173 -#define MACH_TYPE_ADM510X 174 -#define MACH_TYPE_SVS200 175 -#define MACH_TYPE_ATG_TCU 176 -#define MACH_TYPE_JORNADA820 177 -#define MACH_TYPE_S3C44B0 178 -#define MACH_TYPE_MARGIS2 179 -#define MACH_TYPE_KS8695 180 -#define MACH_TYPE_BRH 181 -#define MACH_TYPE_S3C2410 182 -#define MACH_TYPE_POSSIO_PX30 183 -#define MACH_TYPE_S3C2800 184 -#define MACH_TYPE_FLEETWOOD 185 -#define MACH_TYPE_OMAHA 186 -#define MACH_TYPE_TA7 187 -#define MACH_TYPE_NOVA 188 -#define MACH_TYPE_HMK 189 -#define MACH_TYPE_KARO 190 -#define MACH_TYPE_FESTER 191 -#define MACH_TYPE_GPI 192 -#define MACH_TYPE_SMDK2410 193 -#define MACH_TYPE_I519 194 -#define MACH_TYPE_NEXIO 195 -#define MACH_TYPE_BITBOX 196 -#define MACH_TYPE_G200 197 -#define MACH_TYPE_GILL 198 -#define MACH_TYPE_PXA_MERCURY 199 -#define MACH_TYPE_CEIVA 200 -#define MACH_TYPE_FRET 201 -#define MACH_TYPE_EMAILPHONE 202 -#define MACH_TYPE_H3900 203 -#define MACH_TYPE_PXA1 204 -#define MACH_TYPE_KOAN369 205 -#define MACH_TYPE_COGENT 206 -#define MACH_TYPE_ESL_SIMPUTER 207 -#define MACH_TYPE_ESL_SIMPUTER_CLR 208 -#define MACH_TYPE_ESL_SIMPUTER_BW 209 -#define MACH_TYPE_HHP_CRADLE 210 -#define MACH_TYPE_HE500 211 -#define MACH_TYPE_INHANDELF2 212 -#define MACH_TYPE_INHANDFTIP 213 -#define MACH_TYPE_DNP1110 214 -#define MACH_TYPE_PNP1110 215 -#define MACH_TYPE_CSB226 216 -#define MACH_TYPE_ARNOLD 217 -#define MACH_TYPE_VOICEBLUE 218 -#define MACH_TYPE_JZ8028 219 -#define MACH_TYPE_H5400 220 -#define MACH_TYPE_FORTE 221 -#define MACH_TYPE_ACAM 222 -#define MACH_TYPE_ABOX 223 -#define MACH_TYPE_ATMEL 224 -#define MACH_TYPE_SITSANG 225 -#define MACH_TYPE_CPU1110LCDNET 226 -#define MACH_TYPE_MPL_VCMA9 227 -#define MACH_TYPE_OPUS_A1 228 -#define MACH_TYPE_DAYTONA 229 -#define MACH_TYPE_KILLBEAR 230 -#define MACH_TYPE_YOHO 231 -#define MACH_TYPE_JASPER 232 -#define MACH_TYPE_DSC25 233 -#define MACH_TYPE_OMAP_INNOVATOR 234 -#define MACH_TYPE_RAMSES 235 -#define MACH_TYPE_S28X 236 -#define MACH_TYPE_MPORT3 237 -#define MACH_TYPE_PXA_EAGLE250 238 -#define MACH_TYPE_PDB 239 -#define MACH_TYPE_BLUE_2G 240 -#define MACH_TYPE_BLUEARCH 241 -#define MACH_TYPE_IXDP2400 242 -#define MACH_TYPE_IXDP2800 243 -#define MACH_TYPE_EXPLORER 244 -#define MACH_TYPE_IXDP425 245 -#define MACH_TYPE_CHIMP 246 -#define MACH_TYPE_STORK_NEST 247 -#define MACH_TYPE_STORK_EGG 248 -#define MACH_TYPE_WISMO 249 -#define MACH_TYPE_EZLINX 250 -#define MACH_TYPE_AT91RM9200 251 -#define MACH_TYPE_ADTECH_ORION 252 -#define MACH_TYPE_NEPTUNE 253 -#define MACH_TYPE_HACKKIT 254 -#define MACH_TYPE_PXA_WINS30 255 -#define MACH_TYPE_LAVINNA 256 -#define MACH_TYPE_PXA_UENGINE 257 -#define MACH_TYPE_INNOKOM 258 -#define MACH_TYPE_BMS 259 -#define MACH_TYPE_IXCDP1100 260 -#define MACH_TYPE_PRPMC1100 261 -#define MACH_TYPE_AT91RM9200DK 262 -#define MACH_TYPE_ARMSTICK 263 -#define MACH_TYPE_ARMONIE 264 -#define MACH_TYPE_MPORT1 265 -#define MACH_TYPE_S3C5410 266 -#define MACH_TYPE_ZCP320A 267 -#define MACH_TYPE_I_BOX 268 -#define MACH_TYPE_STLC1502 269 -#define MACH_TYPE_SIREN 270 -#define MACH_TYPE_GREENLAKE 271 -#define MACH_TYPE_ARGUS 272 -#define MACH_TYPE_COMBADGE 273 -#define MACH_TYPE_ROKEPXA 274 -#define MACH_TYPE_CINTEGRATOR 275 -#define MACH_TYPE_GUIDEA07 276 -#define MACH_TYPE_TAT257 277 -#define MACH_TYPE_IGP2425 278 -#define MACH_TYPE_BLUEGRAMMA 279 -#define MACH_TYPE_IPOD 280 -#define MACH_TYPE_ADSBITSYX 281 -#define MACH_TYPE_TRIZEPS2 282 -#define MACH_TYPE_VIPER 283 -#define MACH_TYPE_ADSBITSYPLUS 284 -#define MACH_TYPE_ADSAGC 285 -#define MACH_TYPE_STP7312 286 -#define MACH_TYPE_NX_PHNX 287 -#define MACH_TYPE_WEP_EP250 288 -#define MACH_TYPE_INHANDELF3 289 -#define MACH_TYPE_ADI_COYOTE 290 -#define MACH_TYPE_IYONIX 291 -#define MACH_TYPE_DAMICAM_SA1110 292 -#define MACH_TYPE_MEG03 293 -#define MACH_TYPE_PXA_WHITECHAPEL 294 -#define MACH_TYPE_NWSC 295 -#define MACH_TYPE_NWLARM 296 -#define MACH_TYPE_IXP425_MGUARD 297 -#define MACH_TYPE_PXA_NETDCU4 298 -#define MACH_TYPE_IXDP2401 299 -#define MACH_TYPE_IXDP2801 300 -#define MACH_TYPE_ZODIAC 301 -#define MACH_TYPE_ARMMODUL 302 -#define MACH_TYPE_KETOP 303 -#define MACH_TYPE_AV7200 304 -#define MACH_TYPE_ARCH_TI925 305 -#define MACH_TYPE_ACQ200 306 -#define MACH_TYPE_PT_DAFIT 307 -#define MACH_TYPE_IHBA 308 -#define MACH_TYPE_QUINQUE 309 -#define MACH_TYPE_NIMBRAONE 310 -#define MACH_TYPE_NIMBRA29X 311 -#define MACH_TYPE_NIMBRA210 312 -#define MACH_TYPE_HHP_D95XX 313 -#define MACH_TYPE_LABARM 314 -#define MACH_TYPE_M825XX 315 -#define MACH_TYPE_M7100 316 -#define MACH_TYPE_NIPC2 317 -#define MACH_TYPE_FU7202 318 -#define MACH_TYPE_ADSAGX 319 -#define MACH_TYPE_PXA_POOH 320 -#define MACH_TYPE_BANDON 321 -#define MACH_TYPE_PCM7210 322 -#define MACH_TYPE_NMS9200 323 -#define MACH_TYPE_LOGODL 324 -#define MACH_TYPE_M7140 325 -#define MACH_TYPE_KOREBOT 326 -#define MACH_TYPE_IQ31244 327 -#define MACH_TYPE_KOAN393 328 -#define MACH_TYPE_INHANDFTIP3 329 -#define MACH_TYPE_GONZO 330 -#define MACH_TYPE_BAST 331 -#define MACH_TYPE_SCANPASS 332 -#define MACH_TYPE_EP7312_POOH 333 -#define MACH_TYPE_TA7S 334 -#define MACH_TYPE_TA7V 335 -#define MACH_TYPE_ICARUS 336 -#define MACH_TYPE_H1900 337 -#define MACH_TYPE_GEMINI 338 -#define MACH_TYPE_AXIM 339 -#define MACH_TYPE_AUDIOTRON 340 -#define MACH_TYPE_H2200 341 -#define MACH_TYPE_LOOX600 342 -#define MACH_TYPE_NIOP 343 -#define MACH_TYPE_DM310 344 -#define MACH_TYPE_SEEDPXA_C2 345 -#define MACH_TYPE_IXP4XX_MGUARD_PCI 346 -#define MACH_TYPE_H1940 347 -#define MACH_TYPE_SCORPIO 348 -#define MACH_TYPE_VIVA 349 -#define MACH_TYPE_PXA_XCARD 350 -#define MACH_TYPE_CSB335 351 -#define MACH_TYPE_IXRD425 352 -#define MACH_TYPE_IQ80315 353 -#define MACH_TYPE_NMP7312 354 -#define MACH_TYPE_CX861XX 355 -#define MACH_TYPE_ENP2611 356 -#define MACH_TYPE_XDA 357 -#define MACH_TYPE_CSIR_IMS 358 -#define MACH_TYPE_IXP421_DNAEETH 359 -#define MACH_TYPE_POCKETSERV9200 360 -#define MACH_TYPE_TOTO 361 -#define MACH_TYPE_S3C2440 362 -#define MACH_TYPE_KS8695P 363 -#define MACH_TYPE_SE4000 364 -#define MACH_TYPE_QUADRICEPS 365 -#define MACH_TYPE_BRONCO 366 -#define MACH_TYPE_ESL_WIRELESS_TAB 367 -#define MACH_TYPE_ESL_SOFCOMP 368 -#define MACH_TYPE_S5C7375 369 -#define MACH_TYPE_SPEARHEAD 370 -#define MACH_TYPE_PANTERA 371 -#define MACH_TYPE_PRAYOGLITE 372 -#define MACH_TYPE_GUMSTIX 373 -#define MACH_TYPE_RCUBE 374 -#define MACH_TYPE_REA_OLV 375 -#define MACH_TYPE_PXA_IPHONE 376 -#define MACH_TYPE_S3C3410 377 -#define MACH_TYPE_ESPD_4510B 378 -#define MACH_TYPE_MP1X 379 -#define MACH_TYPE_AT91RM9200TB 380 -#define MACH_TYPE_ADSVGX 381 -#define MACH_TYPE_OMAP_H2 382 -#define MACH_TYPE_PELEE 383 -#define MACH_TYPE_E740 384 -#define MACH_TYPE_IQ80331 385 -#define MACH_TYPE_VERSATILE_PB 387 -#define MACH_TYPE_KEV7A400 388 -#define MACH_TYPE_LPD7A400 389 -#define MACH_TYPE_LPD7A404 390 -#define MACH_TYPE_FUJITSU_CAMELOT 391 -#define MACH_TYPE_JANUS2M 392 -#define MACH_TYPE_EMBTF 393 -#define MACH_TYPE_HPM 394 -#define MACH_TYPE_SMDK2410TK 395 -#define MACH_TYPE_SMDK2410AJ 396 -#define MACH_TYPE_STREETRACER 397 -#define MACH_TYPE_EFRAME 398 -#define MACH_TYPE_CSB337 399 -#define MACH_TYPE_PXA_LARK 400 -#define MACH_TYPE_PNP2110 401 -#define MACH_TYPE_TCC72X 402 -#define MACH_TYPE_ALTAIR 403 -#define MACH_TYPE_KC3 404 -#define MACH_TYPE_SINTEFTD 405 -#define MACH_TYPE_MAINSTONE 406 -#define MACH_TYPE_ADAY4X 407 -#define MACH_TYPE_LITE300 408 -#define MACH_TYPE_S5C7376 409 -#define MACH_TYPE_MT02 410 -#define MACH_TYPE_MPORT3S 411 -#define MACH_TYPE_RA_ALPHA 412 -#define MACH_TYPE_XCEP 413 -#define MACH_TYPE_ARCOM_VULCAN 414 -#define MACH_TYPE_STARGATE 415 -#define MACH_TYPE_ARMADILLOJ 416 -#define MACH_TYPE_ELROY_JACK 417 -#define MACH_TYPE_BACKEND 418 -#define MACH_TYPE_S5LINBOX 419 -#define MACH_TYPE_NOMADIK 420 -#define MACH_TYPE_IA_CPU_9200 421 -#define MACH_TYPE_AT91_BJA1 422 -#define MACH_TYPE_CORGI 423 -#define MACH_TYPE_POODLE 424 -#define MACH_TYPE_TEN 425 -#define MACH_TYPE_ROVERP5P 426 -#define MACH_TYPE_SC2700 427 -#define MACH_TYPE_EX_EAGLE 428 -#define MACH_TYPE_NX_PXA12 429 -#define MACH_TYPE_NX_PXA5 430 -#define MACH_TYPE_BLACKBOARD2 431 -#define MACH_TYPE_I819 432 -#define MACH_TYPE_IXMB995E 433 -#define MACH_TYPE_SKYRIDER 434 -#define MACH_TYPE_SKYHAWK 435 -#define MACH_TYPE_ENTERPRISE 436 -#define MACH_TYPE_DEP2410 437 -#define MACH_TYPE_ARMCORE 438 -#define MACH_TYPE_HOBBIT 439 -#define MACH_TYPE_H7210 440 -#define MACH_TYPE_PXA_NETDCU5 441 -#define MACH_TYPE_ACC 442 -#define MACH_TYPE_ESL_SARVA 443 -#define MACH_TYPE_XM250 444 -#define MACH_TYPE_T6TC1XB 445 -#define MACH_TYPE_ESS710 446 -#define MACH_TYPE_MX31ADS 447 -#define MACH_TYPE_HIMALAYA 448 -#define MACH_TYPE_BOLFENK 449 -#define MACH_TYPE_AT91RM9200KR 450 -#define MACH_TYPE_EDB9312 451 -#define MACH_TYPE_OMAP_GENERIC 452 -#define MACH_TYPE_AXIMX3 453 -#define MACH_TYPE_EB67XDIP 454 -#define MACH_TYPE_WEBTXS 455 -#define MACH_TYPE_HAWK 456 -#define MACH_TYPE_CCAT91SBC001 457 -#define MACH_TYPE_EXPRESSO 458 -#define MACH_TYPE_H4000 459 -#define MACH_TYPE_DINO 460 -#define MACH_TYPE_ML675K 461 -#define MACH_TYPE_EDB9301 462 -#define MACH_TYPE_EDB9315 463 -#define MACH_TYPE_RECIVA_TT 464 -#define MACH_TYPE_CSTCB01 465 -#define MACH_TYPE_CSTCB1 466 -#define MACH_TYPE_SHADWELL 467 -#define MACH_TYPE_GOEPEL263 468 -#define MACH_TYPE_ACQ100 469 -#define MACH_TYPE_MX1FS2 470 -#define MACH_TYPE_HIPTOP_G1 471 -#define MACH_TYPE_SPARKY 472 -#define MACH_TYPE_NS9750 473 -#define MACH_TYPE_PHOENIX 474 -#define MACH_TYPE_VR1000 475 -#define MACH_TYPE_DEISTERPXA 476 -#define MACH_TYPE_BCM1160 477 -#define MACH_TYPE_PCM022 478 -#define MACH_TYPE_ADSGCX 479 -#define MACH_TYPE_DREADNAUGHT 480 -#define MACH_TYPE_DM320 481 -#define MACH_TYPE_MARKOV 482 -#define MACH_TYPE_COS7A400 483 -#define MACH_TYPE_MILANO 484 -#define MACH_TYPE_UE9328 485 -#define MACH_TYPE_UEX255 486 -#define MACH_TYPE_UE2410 487 -#define MACH_TYPE_A620 488 -#define MACH_TYPE_OCELOT 489 -#define MACH_TYPE_CHEETAH 490 -#define MACH_TYPE_OMAP_PERSEUS2 491 -#define MACH_TYPE_ZVUE 492 -#define MACH_TYPE_ROVERP1 493 -#define MACH_TYPE_ASIDIAL2 494 -#define MACH_TYPE_S3C24A0 495 -#define MACH_TYPE_E800 496 -#define MACH_TYPE_E750 497 -#define MACH_TYPE_S3C5500 498 -#define MACH_TYPE_SMDK5500 499 -#define MACH_TYPE_SIGNALSYNC 500 -#define MACH_TYPE_NBC 501 -#define MACH_TYPE_KODIAK 502 -#define MACH_TYPE_NETBOOKPRO 503 -#define MACH_TYPE_HW90200 504 -#define MACH_TYPE_CONDOR 505 -#define MACH_TYPE_CUP 506 -#define MACH_TYPE_KITE 507 -#define MACH_TYPE_SCB9328 508 -#define MACH_TYPE_OMAP_H3 509 -#define MACH_TYPE_OMAP_H4 510 -#define MACH_TYPE_N10 511 -#define MACH_TYPE_MONTAJADE 512 -#define MACH_TYPE_SG560 513 -#define MACH_TYPE_DP1000 514 -#define MACH_TYPE_OMAP_OSK 515 -#define MACH_TYPE_RG100V3 516 -#define MACH_TYPE_MX2ADS 517 -#define MACH_TYPE_PXA_KILO 518 -#define MACH_TYPE_IXP4XX_EAGLE 519 -#define MACH_TYPE_TOSA 520 -#define MACH_TYPE_MB2520F 521 -#define MACH_TYPE_EMC1000 522 -#define MACH_TYPE_TIDSC25 523 -#define MACH_TYPE_AKCPMXL 524 -#define MACH_TYPE_AV3XX 525 -#define MACH_TYPE_AVILA 526 -#define MACH_TYPE_PXA_MPM10 527 -#define MACH_TYPE_PXA_KYANITE 528 -#define MACH_TYPE_SGOLD 529 -#define MACH_TYPE_OSCAR 530 -#define MACH_TYPE_EPXA4USB2 531 -#define MACH_TYPE_XSENGINE 532 -#define MACH_TYPE_IP600 533 -#define MACH_TYPE_MCAN2 534 -#define MACH_TYPE_DDI_BLUERIDGE 535 -#define MACH_TYPE_SKYMINDER 536 -#define MACH_TYPE_LPD79520 537 -#define MACH_TYPE_EDB9302 538 -#define MACH_TYPE_HW90340 539 -#define MACH_TYPE_CIP_BOX 540 -#define MACH_TYPE_IVPN 541 -#define MACH_TYPE_RSOC2 542 -#define MACH_TYPE_HUSKY 543 -#define MACH_TYPE_BOXER 544 -#define MACH_TYPE_SHEPHERD 545 -#define MACH_TYPE_AML42800AA 546 -#define MACH_TYPE_LPC2294 548 -#define MACH_TYPE_SWITCHGRASS 549 -#define MACH_TYPE_ENS_CMU 550 -#define MACH_TYPE_MM6_SDB 551 -#define MACH_TYPE_SATURN 552 -#define MACH_TYPE_I30030EVB 553 -#define MACH_TYPE_MXC27530EVB 554 -#define MACH_TYPE_SMDK2800 555 -#define MACH_TYPE_MTWILSON 556 -#define MACH_TYPE_ZITI 557 -#define MACH_TYPE_GRANDFATHER 558 -#define MACH_TYPE_TENGINE 559 -#define MACH_TYPE_S3C2460 560 -#define MACH_TYPE_PDM 561 -#define MACH_TYPE_H4700 562 -#define MACH_TYPE_H6300 563 -#define MACH_TYPE_RZ1700 564 -#define MACH_TYPE_A716 565 -#define MACH_TYPE_ESTK2440A 566 -#define MACH_TYPE_ATWIXP425 567 -#define MACH_TYPE_CSB336 568 -#define MACH_TYPE_RIRM2 569 -#define MACH_TYPE_CX23518 570 -#define MACH_TYPE_CX2351X 571 -#define MACH_TYPE_COMPUTIME 572 -#define MACH_TYPE_IZARUS 573 -#define MACH_TYPE_RTS 574 -#define MACH_TYPE_SE5100 575 -#define MACH_TYPE_S3C2510 576 -#define MACH_TYPE_CSB437TL 577 -#define MACH_TYPE_SLAUSON 578 -#define MACH_TYPE_PEARLRIVER 579 -#define MACH_TYPE_TDC_P210 580 -#define MACH_TYPE_SG580 581 -#define MACH_TYPE_WRSBCARM7 582 -#define MACH_TYPE_IPD 583 -#define MACH_TYPE_PXA_DNP2110 584 -#define MACH_TYPE_XAENIAX 585 -#define MACH_TYPE_SOMN4250 586 -#define MACH_TYPE_PLEB2 587 -#define MACH_TYPE_CORNWALLIS 588 -#define MACH_TYPE_GURNEY_DRV 589 -#define MACH_TYPE_CHAFFEE 590 -#define MACH_TYPE_RMS101 591 -#define MACH_TYPE_RX3715 592 -#define MACH_TYPE_SWIFT 593 -#define MACH_TYPE_ROVERP7 594 -#define MACH_TYPE_PR818S 595 -#define MACH_TYPE_TRXPRO 596 -#define MACH_TYPE_NSLU2 597 -#define MACH_TYPE_E400 598 -#define MACH_TYPE_TRAB 599 -#define MACH_TYPE_CMC_PU2 600 -#define MACH_TYPE_FULCRUM 601 -#define MACH_TYPE_NETGATE42X 602 -#define MACH_TYPE_STR710 603 -#define MACH_TYPE_IXDPG425 604 -#define MACH_TYPE_TOMTOMGO 605 -#define MACH_TYPE_VERSATILE_AB 606 -#define MACH_TYPE_EDB9307 607 -#define MACH_TYPE_SG565 608 -#define MACH_TYPE_LPD79524 609 -#define MACH_TYPE_LPD79525 610 -#define MACH_TYPE_RMS100 611 -#define MACH_TYPE_KB9200 612 -#define MACH_TYPE_SX1 613 -#define MACH_TYPE_HMS39C7092 614 -#define MACH_TYPE_ARMADILLO 615 -#define MACH_TYPE_IPCU 616 -#define MACH_TYPE_LOOX720 617 -#define MACH_TYPE_IXDP465 618 -#define MACH_TYPE_IXDP2351 619 -#define MACH_TYPE_ADSVIX 620 -#define MACH_TYPE_DM270 621 -#define MACH_TYPE_SOCLTPLUS 622 -#define MACH_TYPE_ECIA 623 -#define MACH_TYPE_CM4008 624 -#define MACH_TYPE_P2001 625 -#define MACH_TYPE_TWISTER 626 -#define MACH_TYPE_MUDSHARK 627 -#define MACH_TYPE_HB2 628 -#define MACH_TYPE_IQ80332 629 -#define MACH_TYPE_SENDT 630 -#define MACH_TYPE_MX2JAZZ 631 -#define MACH_TYPE_MULTIIO 632 -#define MACH_TYPE_HRDISPLAY 633 -#define MACH_TYPE_MXC27530ADS 634 -#define MACH_TYPE_TRIZEPS3 635 -#define MACH_TYPE_ZEFEERDZA 636 -#define MACH_TYPE_ZEFEERDZB 637 -#define MACH_TYPE_ZEFEERDZG 638 -#define MACH_TYPE_ZEFEERDZN 639 -#define MACH_TYPE_ZEFEERDZQ 640 -#define MACH_TYPE_GTWX5715 641 -#define MACH_TYPE_ASTRO_JACK 643 -#define MACH_TYPE_TIP03 644 -#define MACH_TYPE_A9200EC 645 -#define MACH_TYPE_PNX0105 646 -#define MACH_TYPE_ADCPOECPU 647 -#define MACH_TYPE_CSB637 648 -#define MACH_TYPE_MB9200 650 -#define MACH_TYPE_KULUN 651 -#define MACH_TYPE_SNAPPER 652 -#define MACH_TYPE_OPTIMA 653 -#define MACH_TYPE_DLHSBC 654 -#define MACH_TYPE_X30 655 -#define MACH_TYPE_N30 656 -#define MACH_TYPE_MANGA_KS8695 657 -#define MACH_TYPE_AJAX 658 -#define MACH_TYPE_NEC_MP900 659 -#define MACH_TYPE_VVTK1000 661 -#define MACH_TYPE_KAFA 662 -#define MACH_TYPE_VVTK3000 663 -#define MACH_TYPE_PIMX1 664 -#define MACH_TYPE_OLLIE 665 -#define MACH_TYPE_SKYMAX 666 -#define MACH_TYPE_JAZZ 667 -#define MACH_TYPE_TEL_T3 668 -#define MACH_TYPE_AISINO_FCR255 669 -#define MACH_TYPE_BTWEB 670 -#define MACH_TYPE_DBG_LH79520 671 -#define MACH_TYPE_CM41XX 672 -#define MACH_TYPE_TS72XX 673 -#define MACH_TYPE_NGGPXA 674 -#define MACH_TYPE_CSB535 675 -#define MACH_TYPE_CSB536 676 -#define MACH_TYPE_PXA_TRAKPOD 677 -#define MACH_TYPE_PRAXIS 678 -#define MACH_TYPE_LH75411 679 -#define MACH_TYPE_OTOM 680 -#define MACH_TYPE_NEXCODER_2440 681 -#define MACH_TYPE_LOOX410 682 -#define MACH_TYPE_WESTLAKE 683 -#define MACH_TYPE_NSB 684 -#define MACH_TYPE_ESL_SARVA_STN 685 -#define MACH_TYPE_ESL_SARVA_TFT 686 -#define MACH_TYPE_ESL_SARVA_IAD 687 -#define MACH_TYPE_ESL_SARVA_ACC 688 -#define MACH_TYPE_TYPHOON 689 -#define MACH_TYPE_CNAV 690 -#define MACH_TYPE_A730 691 -#define MACH_TYPE_NETSTAR 692 -#define MACH_TYPE_PHASEFALE_SUPERCON 693 -#define MACH_TYPE_SHIVA1100 694 -#define MACH_TYPE_ETEXSC 695 -#define MACH_TYPE_IXDPG465 696 -#define MACH_TYPE_A9M2410 697 -#define MACH_TYPE_A9M2440 698 -#define MACH_TYPE_A9M9750 699 -#define MACH_TYPE_A9M9360 700 -#define MACH_TYPE_UNC90 701 -#define MACH_TYPE_ECO920 702 -#define MACH_TYPE_SATVIEW 703 -#define MACH_TYPE_ROADRUNNER 704 -#define MACH_TYPE_AT91RM9200EK 705 -#define MACH_TYPE_GP32 706 -#define MACH_TYPE_GEM 707 -#define MACH_TYPE_I858 708 -#define MACH_TYPE_HX2750 709 -#define MACH_TYPE_MXC91131EVB 710 -#define MACH_TYPE_P700 711 -#define MACH_TYPE_CPE 712 -#define MACH_TYPE_SPITZ 713 -#define MACH_TYPE_NIMBRA340 714 -#define MACH_TYPE_LPC22XX 715 -#define MACH_TYPE_COMET3 716 -#define MACH_TYPE_COMET4 717 -#define MACH_TYPE_CSB625 718 -#define MACH_TYPE_FORTUNET2 719 -#define MACH_TYPE_S5H2200 720 -#define MACH_TYPE_OPTORM920 721 -#define MACH_TYPE_ADSBITSYXB 722 -#define MACH_TYPE_ADSSPHERE 723 -#define MACH_TYPE_ADSPORTAL 724 -#define MACH_TYPE_LN2410SBC 725 -#define MACH_TYPE_CB3RUFC 726 -#define MACH_TYPE_MP2USB 727 -#define MACH_TYPE_NTNP425C 728 -#define MACH_TYPE_COLIBRI 729 -#define MACH_TYPE_PCM7220 730 -#define MACH_TYPE_GATEWAY7001 731 -#define MACH_TYPE_PCM027 732 -#define MACH_TYPE_CMPXA 733 -#define MACH_TYPE_ANUBIS 734 -#define MACH_TYPE_ITE8152 735 -#define MACH_TYPE_LPC3XXX 736 -#define MACH_TYPE_PUPPETEER 737 -#define MACH_TYPE_E570 739 -#define MACH_TYPE_X50 740 -#define MACH_TYPE_RECON 741 -#define MACH_TYPE_XBOARDGP8 742 -#define MACH_TYPE_FPIC2 743 -#define MACH_TYPE_AKITA 744 -#define MACH_TYPE_A81 745 -#define MACH_TYPE_SVM_SC25X 746 -#define MACH_TYPE_VADATECH020 747 -#define MACH_TYPE_TLI 748 -#define MACH_TYPE_EDB9315LC 749 -#define MACH_TYPE_PASSEC 750 -#define MACH_TYPE_DS_TIGER 751 -#define MACH_TYPE_E310 752 -#define MACH_TYPE_E330 753 -#define MACH_TYPE_RT3000 754 -#define MACH_TYPE_NOKIA770 755 -#define MACH_TYPE_PNX0106 756 -#define MACH_TYPE_HX21XX 757 -#define MACH_TYPE_FARADAY 758 -#define MACH_TYPE_SBC9312 759 -#define MACH_TYPE_BATMAN 760 -#define MACH_TYPE_JPD201 761 -#define MACH_TYPE_MIPSA 762 -#define MACH_TYPE_KACOM 763 -#define MACH_TYPE_SWARCOCPU 764 -#define MACH_TYPE_SWARCODSL 765 -#define MACH_TYPE_BLUEANGEL 766 -#define MACH_TYPE_HAIRYGRAMA 767 -#define MACH_TYPE_BANFF 768 -#define MACH_TYPE_CARMEVA 769 -#define MACH_TYPE_SAM255 770 -#define MACH_TYPE_PPM10 771 -#define MACH_TYPE_EDB9315A 772 -#define MACH_TYPE_SUNSET 773 -#define MACH_TYPE_STARGATE2 774 -#define MACH_TYPE_INTELMOTE2 775 -#define MACH_TYPE_TRIZEPS4 776 -#define MACH_TYPE_MAINSTONE2 777 -#define MACH_TYPE_EZ_IXP42X 778 -#define MACH_TYPE_TAPWAVE_ZODIAC 779 -#define MACH_TYPE_UNIVERSALMETER 780 -#define MACH_TYPE_HICOARM9 781 -#define MACH_TYPE_PNX4008 782 -#define MACH_TYPE_KWS6000 783 -#define MACH_TYPE_PORTUX920T 784 -#define MACH_TYPE_EZ_X5 785 -#define MACH_TYPE_OMAP_RUDOLPH 786 -#define MACH_TYPE_CPUAT91 787 -#define MACH_TYPE_REA9200 788 -#define MACH_TYPE_ACTS_PUNE_SA1110 789 -#define MACH_TYPE_IXP425 790 -#define MACH_TYPE_I30030ADS 791 -#define MACH_TYPE_PERCH 792 -#define MACH_TYPE_EIS05R1 793 -#define MACH_TYPE_PEPPERPAD 794 -#define MACH_TYPE_SB3010 795 -#define MACH_TYPE_RM9200 796 -#define MACH_TYPE_DMA03 797 -#define MACH_TYPE_ROAD_S101 798 -#define MACH_TYPE_IQ81340SC 799 -#define MACH_TYPE_IQ_NEXTGEN_B 800 -#define MACH_TYPE_IQ81340MC 801 -#define MACH_TYPE_IQ_NEXTGEN_D 802 -#define MACH_TYPE_IQ_NEXTGEN_E 803 -#define MACH_TYPE_MALLOW_AT91 804 -#define MACH_TYPE_CYBERTRACKER_I 805 -#define MACH_TYPE_GESBC931X 806 -#define MACH_TYPE_CENTIPAD 807 -#define MACH_TYPE_ARMSOC 808 -#define MACH_TYPE_SE4200 809 -#define MACH_TYPE_EMS197A 810 -#define MACH_TYPE_MICRO9 811 -#define MACH_TYPE_MICRO9L 812 -#define MACH_TYPE_UC5471DSP 813 -#define MACH_TYPE_SJ5471ENG 814 -#define MACH_TYPE_CMPXA26X 815 -#define MACH_TYPE_NC 816 -#define MACH_TYPE_OMAP_PALMTE 817 -#define MACH_TYPE_AJAX52X 818 -#define MACH_TYPE_SIRIUSTAR 819 -#define MACH_TYPE_IODATA_HDLG 820 -#define MACH_TYPE_AT91RM9200UTL 821 -#define MACH_TYPE_BIOSAFE 822 -#define MACH_TYPE_MP1000 823 -#define MACH_TYPE_PARSY 824 -#define MACH_TYPE_CCXP 825 -#define MACH_TYPE_OMAP_GSAMPLE 826 -#define MACH_TYPE_REALVIEW_EB 827 -#define MACH_TYPE_SAMOA 828 -#define MACH_TYPE_PALMT3 829 -#define MACH_TYPE_I878 830 -#define MACH_TYPE_BORZOI 831 -#define MACH_TYPE_GECKO 832 -#define MACH_TYPE_DS101 833 -#define MACH_TYPE_OMAP_PALMTT2 834 -#define MACH_TYPE_PALMLD 835 -#define MACH_TYPE_CC9C 836 -#define MACH_TYPE_SBC1670 837 -#define MACH_TYPE_IXDP28X5 838 -#define MACH_TYPE_OMAP_PALMTT 839 -#define MACH_TYPE_ML696K 840 -#define MACH_TYPE_ARCOM_ZEUS 841 -#define MACH_TYPE_OSIRIS 842 -#define MACH_TYPE_MAESTRO 843 -#define MACH_TYPE_PALMTE2 844 -#define MACH_TYPE_IXBBM 845 -#define MACH_TYPE_MX27ADS 846 -#define MACH_TYPE_AX8004 847 -#define MACH_TYPE_AT91SAM9261EK 848 -#define MACH_TYPE_LOFT 849 -#define MACH_TYPE_MAGPIE 850 -#define MACH_TYPE_MX21ADS 851 -#define MACH_TYPE_MB87M3400 852 -#define MACH_TYPE_MGUARD_DELTA 853 -#define MACH_TYPE_DAVINCI_DVDP 854 -#define MACH_TYPE_HTCUNIVERSAL 855 -#define MACH_TYPE_TPAD 856 -#define MACH_TYPE_ROVERP3 857 -#define MACH_TYPE_JORNADA928 858 -#define MACH_TYPE_MV88FXX81 859 -#define MACH_TYPE_STMP36XX 860 -#define MACH_TYPE_SXNI79524 861 -#define MACH_TYPE_AMS_DELTA 862 -#define MACH_TYPE_URANIUM 863 -#define MACH_TYPE_UCON 864 -#define MACH_TYPE_NAS100D 865 -#define MACH_TYPE_L083_1000 866 -#define MACH_TYPE_EZX 867 -#define MACH_TYPE_PNX5220 868 -#define MACH_TYPE_BUTTE 869 -#define MACH_TYPE_SRM2 870 -#define MACH_TYPE_DSBR 871 -#define MACH_TYPE_CRYSTALBALL 872 -#define MACH_TYPE_TINYPXA27X 873 -#define MACH_TYPE_HERBIE 874 -#define MACH_TYPE_MAGICIAN 875 -#define MACH_TYPE_CM4002 876 -#define MACH_TYPE_B4 877 -#define MACH_TYPE_MAUI 878 -#define MACH_TYPE_CYBERTRACKER_G 879 -#define MACH_TYPE_NXDKN 880 -#define MACH_TYPE_MIO8390 881 -#define MACH_TYPE_OMI_BOARD 882 -#define MACH_TYPE_MX21CIV 883 -#define MACH_TYPE_MAHI_CDAC 884 -#define MACH_TYPE_PALMTX 885 -#define MACH_TYPE_S3C2413 887 -#define MACH_TYPE_SAMSYS_EP0 888 -#define MACH_TYPE_WG302V1 889 -#define MACH_TYPE_WG302V2 890 -#define MACH_TYPE_EB42X 891 -#define MACH_TYPE_IQ331ES 892 -#define MACH_TYPE_COSYDSP 893 -#define MACH_TYPE_UPLAT7D 894 -#define MACH_TYPE_PTDAVINCI 895 -#define MACH_TYPE_MBUS 896 -#define MACH_TYPE_NADIA2VB 897 -#define MACH_TYPE_R1000 898 -#define MACH_TYPE_HW90250 899 -#define MACH_TYPE_OMAP_2430SDP 900 -#define MACH_TYPE_DAVINCI_EVM 901 -#define MACH_TYPE_OMAP_TORNADO 902 -#define MACH_TYPE_OLOCREEK 903 -#define MACH_TYPE_PALMZ72 904 -#define MACH_TYPE_NXDB500 905 -#define MACH_TYPE_APF9328 906 -#define MACH_TYPE_OMAP_WIPOQ 907 -#define MACH_TYPE_OMAP_TWIP 908 -#define MACH_TYPE_PALMT650 909 -#define MACH_TYPE_ACUMEN 910 -#define MACH_TYPE_XP100 911 -#define MACH_TYPE_FS2410 912 -#define MACH_TYPE_PXA270_CERF 913 -#define MACH_TYPE_SQ2FTLPALM 914 -#define MACH_TYPE_BSEMSERVER 915 -#define MACH_TYPE_NETCLIENT 916 -#define MACH_TYPE_PALMT5 917 -#define MACH_TYPE_PALMTC 918 -#define MACH_TYPE_OMAP_APOLLON 919 -#define MACH_TYPE_MXC30030EVB 920 -#define MACH_TYPE_REA_2D 921 -#define MACH_TYPE_TI3E524 922 -#define MACH_TYPE_ATEB9200 923 -#define MACH_TYPE_AUCKLAND 924 -#define MACH_TYPE_AK3320M 925 -#define MACH_TYPE_DURAMAX 926 -#define MACH_TYPE_N35 927 -#define MACH_TYPE_PRONGHORN 928 -#define MACH_TYPE_FUNDY 929 -#define MACH_TYPE_LOGICPD_PXA270 930 -#define MACH_TYPE_CPU777 931 -#define MACH_TYPE_SIMICON9201 932 -#define MACH_TYPE_LEAP2_HPM 933 -#define MACH_TYPE_CM922TXA10 934 -#define MACH_TYPE_PXA 935 -#define MACH_TYPE_SANDGATE2 936 -#define MACH_TYPE_SANDGATE2G 937 -#define MACH_TYPE_SANDGATE2P 938 -#define MACH_TYPE_FRED_JACK 939 -#define MACH_TYPE_TTG_COLOR1 940 -#define MACH_TYPE_NXEB500HMI 941 -#define MACH_TYPE_NETDCU8 942 -#define MACH_TYPE_NG_FVX538 944 -#define MACH_TYPE_NG_FVS338 945 -#define MACH_TYPE_PNX4103 946 -#define MACH_TYPE_HESDB 947 -#define MACH_TYPE_XSILO 948 -#define MACH_TYPE_ESPRESSO 949 -#define MACH_TYPE_EMLC 950 -#define MACH_TYPE_SISTERON 951 -#define MACH_TYPE_RX1950 952 -#define MACH_TYPE_TSC_VENUS 953 -#define MACH_TYPE_DS101J 954 -#define MACH_TYPE_MXC30030ADS 955 -#define MACH_TYPE_FUJITSU_WIMAXSOC 956 -#define MACH_TYPE_DUALPCMODEM 957 -#define MACH_TYPE_GESBC9312 958 -#define MACH_TYPE_HTCAPACHE 959 -#define MACH_TYPE_IXDP435 960 -#define MACH_TYPE_CATPROVT100 961 -#define MACH_TYPE_PICOTUX1XX 962 -#define MACH_TYPE_PICOTUX2XX 963 -#define MACH_TYPE_DSMG600 964 -#define MACH_TYPE_EMPC2 965 -#define MACH_TYPE_VENTURA 966 -#define MACH_TYPE_PHIDGET_SBC 967 -#define MACH_TYPE_IJ3K 968 -#define MACH_TYPE_PISGAH 969 -#define MACH_TYPE_OMAP_FSAMPLE 970 -#define MACH_TYPE_SG720 971 -#define MACH_TYPE_REDFOX 972 -#define MACH_TYPE_MYSH_EP9315_1 973 -#define MACH_TYPE_TPF106 974 -#define MACH_TYPE_AT91RM9200KG 975 -#define MACH_TYPE_SLEDB 976 -#define MACH_TYPE_ONTRACK 977 -#define MACH_TYPE_PM1200 978 -#define MACH_TYPE_ESS24XXX 979 -#define MACH_TYPE_COREMP7 980 -#define MACH_TYPE_NEXCODER_6446 981 -#define MACH_TYPE_STVC8380 982 -#define MACH_TYPE_TEKLYNX 983 -#define MACH_TYPE_CARBONADO 984 -#define MACH_TYPE_SYSMOS_MP730 985 -#define MACH_TYPE_SNAPPER_CL15 986 -#define MACH_TYPE_PGIGIM 987 -#define MACH_TYPE_PTX9160P2 988 -#define MACH_TYPE_DCORE1 989 -#define MACH_TYPE_VICTORPXA 990 -#define MACH_TYPE_MX2DTB 991 -#define MACH_TYPE_PXA_IREX_ER0100 992 -#define MACH_TYPE_OMAP_PALMZ71 993 -#define MACH_TYPE_BARTEC_DEG 994 -#define MACH_TYPE_HW50251 995 -#define MACH_TYPE_IBOX 996 -#define MACH_TYPE_ATLASLH7A404 997 -#define MACH_TYPE_PT2026 998 -#define MACH_TYPE_HTCALPINE 999 -#define MACH_TYPE_BARTEC_VTU 1000 -#define MACH_TYPE_VCOREII 1001 -#define MACH_TYPE_PDNB3 1002 -#define MACH_TYPE_HTCBEETLES 1003 -#define MACH_TYPE_S3C6400 1004 -#define MACH_TYPE_S3C2443 1005 -#define MACH_TYPE_OMAP_LDK 1006 -#define MACH_TYPE_SMDK2460 1007 -#define MACH_TYPE_SMDK2440 1008 -#define MACH_TYPE_SMDK2412 1009 -#define MACH_TYPE_WEBBOX 1010 -#define MACH_TYPE_CWWNDP 1011 -#define MACH_TYPE_DRAGON 1012 -#define MACH_TYPE_OPENDO_CPU_BOARD 1013 -#define MACH_TYPE_CCM2200 1014 -#define MACH_TYPE_ETWARM 1015 -#define MACH_TYPE_M93030 1016 -#define MACH_TYPE_CC7U 1017 -#define MACH_TYPE_MTT_RANGER 1018 -#define MACH_TYPE_NEXUS 1019 -#define MACH_TYPE_DESMAN 1020 -#define MACH_TYPE_BKDE303 1021 -#define MACH_TYPE_SMDK2413 1022 -#define MACH_TYPE_AML_M7200 1023 -#define MACH_TYPE_AML_M5900 1024 -#define MACH_TYPE_SG640 1025 -#define MACH_TYPE_EDG79524 1026 -#define MACH_TYPE_AI2410 1027 -#define MACH_TYPE_IXP465 1028 -#define MACH_TYPE_BALLOON3 1029 -#define MACH_TYPE_HEINS 1030 -#define MACH_TYPE_MPLUSEVA 1031 -#define MACH_TYPE_RT042 1032 -#define MACH_TYPE_CWIEM 1033 -#define MACH_TYPE_CM_X270 1034 -#define MACH_TYPE_CM_X255 1035 -#define MACH_TYPE_ESH_AT91 1036 -#define MACH_TYPE_SANDGATE3 1037 -#define MACH_TYPE_PRIMO 1038 -#define MACH_TYPE_GEMSTONE 1039 -#define MACH_TYPE_PRONGHORNMETRO 1040 -#define MACH_TYPE_SIDEWINDER 1041 -#define MACH_TYPE_PICOMOD1 1042 -#define MACH_TYPE_SG590 1043 -#define MACH_TYPE_AKAI9307 1044 -#define MACH_TYPE_FONTAINE 1045 -#define MACH_TYPE_WOMBAT 1046 -#define MACH_TYPE_ACQ300 1047 -#define MACH_TYPE_MOD_270 1048 -#define MACH_TYPE_VC0820 1049 -#define MACH_TYPE_ANI_AIM 1050 -#define MACH_TYPE_JELLYFISH 1051 -#define MACH_TYPE_AMANITA 1052 -#define MACH_TYPE_VLINK 1053 -#define MACH_TYPE_DEXFLEX 1054 -#define MACH_TYPE_EIGEN_TTQ 1055 -#define MACH_TYPE_ARCOM_TITAN 1056 -#define MACH_TYPE_TABLA 1057 -#define MACH_TYPE_MDIRAC3 1058 -#define MACH_TYPE_MRHFBP2 1059 -#define MACH_TYPE_AT91RM9200RB 1060 -#define MACH_TYPE_ANI_APM 1061 -#define MACH_TYPE_ELLA1 1062 -#define MACH_TYPE_INHAND_PXA27X 1063 -#define MACH_TYPE_INHAND_PXA25X 1064 -#define MACH_TYPE_EMPOS_XM 1065 -#define MACH_TYPE_EMPOS 1066 -#define MACH_TYPE_EMPOS_TINY 1067 -#define MACH_TYPE_EMPOS_SM 1068 -#define MACH_TYPE_EGRET 1069 -#define MACH_TYPE_OSTRICH 1070 -#define MACH_TYPE_N50 1071 -#define MACH_TYPE_ECBAT91 1072 -#define MACH_TYPE_STAREAST 1073 -#define MACH_TYPE_DSPG_DW 1074 -#define MACH_TYPE_ONEARM 1075 -#define MACH_TYPE_MRG110_6 1076 -#define MACH_TYPE_WRT300NV2 1077 -#define MACH_TYPE_XM_BULVERDE 1078 -#define MACH_TYPE_MSM6100 1079 -#define MACH_TYPE_ETI_B1 1080 -#define MACH_TYPE_ZILOG_ZA9L 1081 -#define MACH_TYPE_BIT2440 1082 -#define MACH_TYPE_NBI 1083 -#define MACH_TYPE_SMDK2443 1084 -#define MACH_TYPE_VDAVINCI 1085 -#define MACH_TYPE_ATC6 1086 -#define MACH_TYPE_MULTMDW 1087 -#define MACH_TYPE_MBA2440 1088 -#define MACH_TYPE_ECSD 1089 -#define MACH_TYPE_PALMZ31 1090 -#define MACH_TYPE_FSG 1091 -#define MACH_TYPE_RAZOR101 1092 -#define MACH_TYPE_OPERA_TDM 1093 -#define MACH_TYPE_COMCERTO 1094 -#define MACH_TYPE_TB0319 1095 -#define MACH_TYPE_KWS8000 1096 -#define MACH_TYPE_B2 1097 -#define MACH_TYPE_LCL54 1098 -#define MACH_TYPE_AT91SAM9260EK 1099 -#define MACH_TYPE_GLANTANK 1100 -#define MACH_TYPE_N2100 1101 -#define MACH_TYPE_N4100 1102 -#define MACH_TYPE_VERTICAL_RSC4 1103 -#define MACH_TYPE_SG8100 1104 -#define MACH_TYPE_IM42XX 1105 -#define MACH_TYPE_FTXX 1106 -#define MACH_TYPE_LWFUSION 1107 -#define MACH_TYPE_QT2410 1108 -#define MACH_TYPE_KIXRP435 1109 -#define MACH_TYPE_CCW9C 1110 -#define MACH_TYPE_DABHS 1111 -#define MACH_TYPE_GZMX 1112 -#define MACH_TYPE_IPNW100AP 1113 -#define MACH_TYPE_CC9P9360DEV 1114 -#define MACH_TYPE_CC9P9750DEV 1115 -#define MACH_TYPE_CC9P9360VAL 1116 -#define MACH_TYPE_CC9P9750VAL 1117 -#define MACH_TYPE_NX70V 1118 -#define MACH_TYPE_AT91RM9200DF 1119 -#define MACH_TYPE_SE_PILOT2 1120 -#define MACH_TYPE_MTCN_T800 1121 -#define MACH_TYPE_VCMX212 1122 -#define MACH_TYPE_LYNX 1123 -#define MACH_TYPE_AT91SAM9260ID 1124 -#define MACH_TYPE_HW86052 1125 -#define MACH_TYPE_PILZ_PMI3 1126 -#define MACH_TYPE_EDB9302A 1127 -#define MACH_TYPE_EDB9307A 1128 -#define MACH_TYPE_CT_DFS 1129 -#define MACH_TYPE_PILZ_PMI4 1130 -#define MACH_TYPE_XCEEDNP_IXP 1131 -#define MACH_TYPE_SMDK2442B 1132 -#define MACH_TYPE_XNODE 1133 -#define MACH_TYPE_AIDX270 1134 -#define MACH_TYPE_REMA 1135 -#define MACH_TYPE_BPS1000 1136 -#define MACH_TYPE_HW90350 1137 -#define MACH_TYPE_OMAP_3430SDP 1138 -#define MACH_TYPE_BLUETOUCH 1139 -#define MACH_TYPE_VSTMS 1140 -#define MACH_TYPE_XSBASE270 1141 -#define MACH_TYPE_AT91SAM9260EK_CN 1142 -#define MACH_TYPE_ADSTURBOXB 1143 -#define MACH_TYPE_OTI4110 1144 -#define MACH_TYPE_HME_PXA 1145 -#define MACH_TYPE_DEISTERDCA 1146 -#define MACH_TYPE_CES_SSEM2 1147 -#define MACH_TYPE_CES_MTR 1148 -#define MACH_TYPE_TDS_AVNG_SBC 1149 -#define MACH_TYPE_EVEREST 1150 -#define MACH_TYPE_PNX4010 1151 -#define MACH_TYPE_OXNAS 1152 -#define MACH_TYPE_FIORI 1153 -#define MACH_TYPE_ML1200 1154 -#define MACH_TYPE_PECOS 1155 -#define MACH_TYPE_NB2XXX 1156 -#define MACH_TYPE_HW6900 1157 -#define MACH_TYPE_CDCS_QUOLL 1158 -#define MACH_TYPE_QUICKSILVER 1159 -#define MACH_TYPE_UPLAT926 1160 -#define MACH_TYPE_DEP2410_THOMAS 1161 -#define MACH_TYPE_DTK2410 1162 -#define MACH_TYPE_CHILI 1163 -#define MACH_TYPE_DEMETER 1164 -#define MACH_TYPE_DIONYSUS 1165 -#define MACH_TYPE_AS352X 1166 -#define MACH_TYPE_SERVICE 1167 -#define MACH_TYPE_CS_E9301 1168 -#define MACH_TYPE_MICRO9M 1169 -#define MACH_TYPE_IA_MOSPCK 1170 -#define MACH_TYPE_QL201B 1171 -#define MACH_TYPE_BBM 1174 -#define MACH_TYPE_EXXX 1175 -#define MACH_TYPE_WMA11B 1176 -#define MACH_TYPE_PELCO_ATLAS 1177 -#define MACH_TYPE_G500 1178 -#define MACH_TYPE_BUG 1179 -#define MACH_TYPE_MX33ADS 1180 -#define MACH_TYPE_CHUB 1181 -#define MACH_TYPE_NEO1973_GTA01 1182 -#define MACH_TYPE_W90N740 1183 -#define MACH_TYPE_MEDALLION_SA2410 1184 -#define MACH_TYPE_IA_CPU_9200_2 1185 -#define MACH_TYPE_DIMMRM9200 1186 -#define MACH_TYPE_PM9261 1187 -#define MACH_TYPE_ML7304 1189 -#define MACH_TYPE_UCP250 1190 -#define MACH_TYPE_INTBOARD 1191 -#define MACH_TYPE_GULFSTREAM 1192 -#define MACH_TYPE_LABQUEST 1193 -#define MACH_TYPE_VCMX313 1194 -#define MACH_TYPE_URG200 1195 -#define MACH_TYPE_CPUX255LCDNET 1196 -#define MACH_TYPE_NETDCU9 1197 -#define MACH_TYPE_NETDCU10 1198 -#define MACH_TYPE_DSPG_DGA 1199 -#define MACH_TYPE_DSPG_DVW 1200 -#define MACH_TYPE_SOLOS 1201 -#define MACH_TYPE_AT91SAM9263EK 1202 -#define MACH_TYPE_OSSTBOX 1203 -#define MACH_TYPE_KBAT9261 1204 -#define MACH_TYPE_CT1100 1205 -#define MACH_TYPE_AKCPPXA 1206 -#define MACH_TYPE_OCHAYA1020 1207 -#define MACH_TYPE_HITRACK 1208 -#define MACH_TYPE_SYME1 1209 -#define MACH_TYPE_SYHL1 1210 -#define MACH_TYPE_EMPCA400 1211 -#define MACH_TYPE_EM7210 1212 -#define MACH_TYPE_HTCHERMES 1213 -#define MACH_TYPE_ETI_C1 1214 -#define MACH_TYPE_AC100 1216 -#define MACH_TYPE_SNEETCH 1217 -#define MACH_TYPE_STUDENTMATE 1218 -#define MACH_TYPE_ZIR2410 1219 -#define MACH_TYPE_ZIR2413 1220 -#define MACH_TYPE_DLONIP3 1221 -#define MACH_TYPE_INSTREAM 1222 -#define MACH_TYPE_AMBARELLA 1223 -#define MACH_TYPE_NEVIS 1224 -#define MACH_TYPE_HTC_TRINITY 1225 -#define MACH_TYPE_QL202B 1226 -#define MACH_TYPE_VPAC270 1227 -#define MACH_TYPE_RD129 1228 -#define MACH_TYPE_HTCWIZARD 1229 -#define MACH_TYPE_XSCALE_TREO680 1230 -#define MACH_TYPE_TECON_TMEZON 1231 -#define MACH_TYPE_ZYLONITE 1233 -#define MACH_TYPE_GENE1270 1234 -#define MACH_TYPE_ZIR2412 1235 -#define MACH_TYPE_MX31LITE 1236 -#define MACH_TYPE_T700WX 1237 -#define MACH_TYPE_VF100 1238 -#define MACH_TYPE_NSB2 1239 -#define MACH_TYPE_NXHMI_BB 1240 -#define MACH_TYPE_NXHMI_RE 1241 -#define MACH_TYPE_N4100PRO 1242 -#define MACH_TYPE_SAM9260 1243 -#define MACH_TYPE_OMAP_TREO600 1244 -#define MACH_TYPE_INDY2410 1245 -#define MACH_TYPE_NELT_A 1246 -#define MACH_TYPE_N311 1248 -#define MACH_TYPE_AT91SAM9260VGK 1249 -#define MACH_TYPE_AT91LEPPE 1250 -#define MACH_TYPE_AT91LEPCCN 1251 -#define MACH_TYPE_APC7100 1252 -#define MACH_TYPE_STARGAZER 1253 -#define MACH_TYPE_SONATA 1254 -#define MACH_TYPE_SCHMOOGIE 1255 -#define MACH_TYPE_AZTOOL 1256 -#define MACH_TYPE_MIOA701 1257 -#define MACH_TYPE_SXNI9260 1258 -#define MACH_TYPE_MXC27520EVB 1259 -#define MACH_TYPE_ARMADILLO5X0 1260 -#define MACH_TYPE_MB9260 1261 -#define MACH_TYPE_MB9263 1262 -#define MACH_TYPE_IPAC9302 1263 -#define MACH_TYPE_CC9P9360JS 1264 -#define MACH_TYPE_GALLIUM 1265 -#define MACH_TYPE_MSC2410 1266 -#define MACH_TYPE_GHI270 1267 -#define MACH_TYPE_DAVINCI_LEONARDO 1268 -#define MACH_TYPE_OIAB 1269 -#define MACH_TYPE_SMDK6400 1270 -#define MACH_TYPE_NOKIA_N800 1271 -#define MACH_TYPE_GREENPHONE 1272 -#define MACH_TYPE_COMPEXWP18 1273 -#define MACH_TYPE_XMATE 1274 -#define MACH_TYPE_ENERGIZER 1275 -#define MACH_TYPE_IME1 1276 -#define MACH_TYPE_SWEDATMS 1277 -#define MACH_TYPE_NTNP435C 1278 -#define MACH_TYPE_SPECTRO2 1279 -#define MACH_TYPE_H6039 1280 -#define MACH_TYPE_EP80219 1281 -#define MACH_TYPE_SAMOA_II 1282 -#define MACH_TYPE_CWMXL 1283 -#define MACH_TYPE_AS9200 1284 -#define MACH_TYPE_SFX1149 1285 -#define MACH_TYPE_NAVI010 1286 -#define MACH_TYPE_MULTMDP 1287 -#define MACH_TYPE_SCB9520 1288 -#define MACH_TYPE_HTCATHENA 1289 -#define MACH_TYPE_XP179 1290 -#define MACH_TYPE_H4300 1291 -#define MACH_TYPE_GORAMO_MLR 1292 -#define MACH_TYPE_MXC30020EVB 1293 -#define MACH_TYPE_ADSBITSYG5 1294 -#define MACH_TYPE_ADSPORTALPLUS 1295 -#define MACH_TYPE_MMSP2PLUS 1296 -#define MACH_TYPE_EM_X270 1297 -#define MACH_TYPE_TPP302 1298 -#define MACH_TYPE_TPM104 1299 -#define MACH_TYPE_TPM102 1300 -#define MACH_TYPE_TPM109 1301 -#define MACH_TYPE_FBXO1 1302 -#define MACH_TYPE_HXD8 1303 -#define MACH_TYPE_NEO1973_GTA02 1304 -#define MACH_TYPE_EMTEST 1305 -#define MACH_TYPE_AD6900 1306 -#define MACH_TYPE_EUROPA 1307 -#define MACH_TYPE_METROCONNECT 1308 -#define MACH_TYPE_EZ_S2410 1309 -#define MACH_TYPE_EZ_S2440 1310 -#define MACH_TYPE_EZ_EP9312 1311 -#define MACH_TYPE_EZ_EP9315 1312 -#define MACH_TYPE_EZ_X7 1313 -#define MACH_TYPE_GODOTDB 1314 -#define MACH_TYPE_MISTRAL 1315 -#define MACH_TYPE_MSM 1316 -#define MACH_TYPE_CT5910 1317 -#define MACH_TYPE_CT5912 1318 -#define MACH_TYPE_HYNET_INE 1319 -#define MACH_TYPE_HYNET_APP 1320 -#define MACH_TYPE_MSM7200 1321 -#define MACH_TYPE_MSM7600 1322 -#define MACH_TYPE_CEB255 1323 -#define MACH_TYPE_CIEL 1324 -#define MACH_TYPE_SLM5650 1325 -#define MACH_TYPE_AT91SAM9RLEK 1326 -#define MACH_TYPE_COMTECH_ROUTER 1327 -#define MACH_TYPE_SBC2410X 1328 -#define MACH_TYPE_AT4X0BD 1329 -#define MACH_TYPE_CBIFR 1330 -#define MACH_TYPE_ARCOM_QUANTUM 1331 -#define MACH_TYPE_MATRIX520 1332 -#define MACH_TYPE_MATRIX510 1333 -#define MACH_TYPE_MATRIX500 1334 -#define MACH_TYPE_M501 1335 -#define MACH_TYPE_AAEON1270 1336 -#define MACH_TYPE_MATRIX500EV 1337 -#define MACH_TYPE_PAC500 1338 -#define MACH_TYPE_PNX8181 1339 -#define MACH_TYPE_COLIBRI320 1340 -#define MACH_TYPE_AZTOOLBB 1341 -#define MACH_TYPE_AZTOOLG2 1342 -#define MACH_TYPE_DVLHOST 1343 -#define MACH_TYPE_ZIR9200 1344 -#define MACH_TYPE_ZIR9260 1345 -#define MACH_TYPE_COCOPAH 1346 -#define MACH_TYPE_NDS 1347 -#define MACH_TYPE_ROSENCRANTZ 1348 -#define MACH_TYPE_FTTX_ODSC 1349 -#define MACH_TYPE_CLASSE_R6904 1350 -#define MACH_TYPE_CAM60 1351 -#define MACH_TYPE_MXC30031ADS 1352 -#define MACH_TYPE_DATACALL 1353 -#define MACH_TYPE_AT91EB01 1354 -#define MACH_TYPE_RTY 1355 -#define MACH_TYPE_DWL2100 1356 -#define MACH_TYPE_VINSI 1357 -#define MACH_TYPE_DB88F5281 1358 -#define MACH_TYPE_CSB726 1359 -#define MACH_TYPE_TIK27 1360 -#define MACH_TYPE_MX_UC7420 1361 -#define MACH_TYPE_RIRM3 1362 -#define MACH_TYPE_PELCO_ODYSSEY 1363 -#define MACH_TYPE_ADX_ABOX 1365 -#define MACH_TYPE_ADX_TPID 1366 -#define MACH_TYPE_MINICHECK 1367 -#define MACH_TYPE_IDAM 1368 -#define MACH_TYPE_MARIO_MX 1369 -#define MACH_TYPE_VI1888 1370 -#define MACH_TYPE_ZR4230 1371 -#define MACH_TYPE_T1_IX_BLUE 1372 -#define MACH_TYPE_SYHQ2 1373 -#define MACH_TYPE_COMPUTIME_R3 1374 -#define MACH_TYPE_ORATIS 1375 -#define MACH_TYPE_MIKKO 1376 -#define MACH_TYPE_HOLON 1377 -#define MACH_TYPE_OLIP8 1378 -#define MACH_TYPE_GHI270HG 1379 -#define MACH_TYPE_DAVINCI_DM6467_EVM 1380 -#define MACH_TYPE_DAVINCI_DM355_EVM 1381 -#define MACH_TYPE_BLACKRIVER 1383 -#define MACH_TYPE_SANDGATEWP 1384 -#define MACH_TYPE_CDOTBWSG 1385 -#define MACH_TYPE_QUARK963 1386 -#define MACH_TYPE_CSB735 1387 -#define MACH_TYPE_LITTLETON 1388 -#define MACH_TYPE_MIO_P550 1389 -#define MACH_TYPE_MOTION2440 1390 -#define MACH_TYPE_IMM500 1391 -#define MACH_TYPE_HOMEMATIC 1392 -#define MACH_TYPE_ERMINE 1393 -#define MACH_TYPE_KB9202B 1394 -#define MACH_TYPE_HS1XX 1395 -#define MACH_TYPE_STUDENTMATE2440 1396 -#define MACH_TYPE_ARVOO_L1_Z1 1397 -#define MACH_TYPE_DEP2410K 1398 -#define MACH_TYPE_XXSVIDEO 1399 -#define MACH_TYPE_IM4004 1400 -#define MACH_TYPE_OCHAYA1050 1401 -#define MACH_TYPE_LEP9261 1402 -#define MACH_TYPE_SVENMEB 1403 -#define MACH_TYPE_FORTUNET2NE 1404 -#define MACH_TYPE_NXHX 1406 -#define MACH_TYPE_REALVIEW_PB11MP 1407 -#define MACH_TYPE_IDS500 1408 -#define MACH_TYPE_ORS_N725 1409 -#define MACH_TYPE_HSDARM 1410 -#define MACH_TYPE_SHA_PON003 1411 -#define MACH_TYPE_SHA_PON004 1412 -#define MACH_TYPE_SHA_PON007 1413 -#define MACH_TYPE_SHA_PON011 1414 -#define MACH_TYPE_H6042 1415 -#define MACH_TYPE_H6043 1416 -#define MACH_TYPE_LOOXC550 1417 -#define MACH_TYPE_CNTY_TITAN 1418 -#define MACH_TYPE_APP3XX 1419 -#define MACH_TYPE_SIDEOATSGRAMA 1420 -#define MACH_TYPE_PALMTREO700P 1421 -#define MACH_TYPE_PALMTREO700W 1422 -#define MACH_TYPE_PALMTREO750 1423 -#define MACH_TYPE_PALMTREO755P 1424 -#define MACH_TYPE_EZREGANUT9200 1425 -#define MACH_TYPE_SARGE 1426 -#define MACH_TYPE_A696 1427 -#define MACH_TYPE_TURTLE 1428 -#define MACH_TYPE_MX27_3DS 1430 -#define MACH_TYPE_BISHOP 1431 -#define MACH_TYPE_PXX 1432 -#define MACH_TYPE_REDWOOD 1433 -#define MACH_TYPE_OMAP_2430DLP 1436 -#define MACH_TYPE_OMAP_2430OSK 1437 -#define MACH_TYPE_SARDINE 1438 -#define MACH_TYPE_HALIBUT 1439 -#define MACH_TYPE_TROUT 1440 -#define MACH_TYPE_GOLDFISH 1441 -#define MACH_TYPE_GESBC2440 1442 -#define MACH_TYPE_NOMAD 1443 -#define MACH_TYPE_ROSALIND 1444 -#define MACH_TYPE_CC9P9215 1445 -#define MACH_TYPE_CC9P9210 1446 -#define MACH_TYPE_CC9P9215JS 1447 -#define MACH_TYPE_CC9P9210JS 1448 -#define MACH_TYPE_NASFFE 1449 -#define MACH_TYPE_TN2X0BD 1450 -#define MACH_TYPE_GWMPXA 1451 -#define MACH_TYPE_EXYPLUS 1452 -#define MACH_TYPE_JADOO21 1453 -#define MACH_TYPE_LOOXN560 1454 -#define MACH_TYPE_BONSAI 1455 -#define MACH_TYPE_ADSMILGATO 1456 -#define MACH_TYPE_GBA 1457 -#define MACH_TYPE_H6044 1458 -#define MACH_TYPE_APP 1459 -#define MACH_TYPE_TCT_HAMMER 1460 -#define MACH_TYPE_HERMES 1461 -#define MACH_TYPE_ARTEMIS 1462 -#define MACH_TYPE_HTCTITAN 1463 -#define MACH_TYPE_QRANIUM 1464 -#define MACH_TYPE_ADX_WSC2 1465 -#define MACH_TYPE_ADX_MEDCOM 1466 -#define MACH_TYPE_BBOARD 1467 -#define MACH_TYPE_CAMBRIA 1468 -#define MACH_TYPE_MT7XXX 1469 -#define MACH_TYPE_MATRIX512 1470 -#define MACH_TYPE_MATRIX522 1471 -#define MACH_TYPE_IPAC5010 1472 -#define MACH_TYPE_SAKURA 1473 -#define MACH_TYPE_GROCX 1474 -#define MACH_TYPE_PM9263 1475 -#define MACH_TYPE_SIM_ONE 1476 -#define MACH_TYPE_ACQ132 1477 -#define MACH_TYPE_DATR 1478 -#define MACH_TYPE_ACTUX1 1479 -#define MACH_TYPE_ACTUX2 1480 -#define MACH_TYPE_ACTUX3 1481 -#define MACH_TYPE_FLEXIT 1482 -#define MACH_TYPE_BH2X0BD 1483 -#define MACH_TYPE_ATB2002 1484 -#define MACH_TYPE_XENON 1485 -#define MACH_TYPE_FM607 1486 -#define MACH_TYPE_MATRIX514 1487 -#define MACH_TYPE_MATRIX524 1488 -#define MACH_TYPE_INPOD 1489 -#define MACH_TYPE_JIVE 1490 -#define MACH_TYPE_TLL_MX21 1491 -#define MACH_TYPE_SBC2800 1492 -#define MACH_TYPE_CC7UCAMRY 1493 -#define MACH_TYPE_UBISYS_P9_SC15 1494 -#define MACH_TYPE_UBISYS_P9_SSC2D10 1495 -#define MACH_TYPE_UBISYS_P9_RCU3 1496 -#define MACH_TYPE_AML_M8000 1497 -#define MACH_TYPE_SNAPPER_270 1498 -#define MACH_TYPE_OMAP_BBX 1499 -#define MACH_TYPE_UCN2410 1500 -#define MACH_TYPE_SAM9_L9260 1501 -#define MACH_TYPE_ETI_C2 1502 -#define MACH_TYPE_AVALANCHE 1503 -#define MACH_TYPE_REALVIEW_PB1176 1504 -#define MACH_TYPE_DP1500 1505 -#define MACH_TYPE_APPLE_IPHONE 1506 -#define MACH_TYPE_YL9200 1507 -#define MACH_TYPE_RD88F5182 1508 -#define MACH_TYPE_KUROBOX_PRO 1509 -#define MACH_TYPE_SE_POET 1510 -#define MACH_TYPE_MX31_3DS 1511 -#define MACH_TYPE_R270 1512 -#define MACH_TYPE_ARMOUR21 1513 -#define MACH_TYPE_DT2 1514 -#define MACH_TYPE_VT4 1515 -#define MACH_TYPE_TYCO320 1516 -#define MACH_TYPE_ADMA 1517 -#define MACH_TYPE_WP188 1518 -#define MACH_TYPE_CORSICA 1519 -#define MACH_TYPE_BIGEYE 1520 -#define MACH_TYPE_TLL5000 1522 -#define MACH_TYPE_BEBOT 1523 -#define MACH_TYPE_QONG 1524 -#define MACH_TYPE_TCOMPACT 1525 -#define MACH_TYPE_PUMA5 1526 -#define MACH_TYPE_ELARA 1527 -#define MACH_TYPE_ELLINGTON 1528 -#define MACH_TYPE_XDA_ATOM 1529 -#define MACH_TYPE_ENERGIZER2 1530 -#define MACH_TYPE_ODIN 1531 -#define MACH_TYPE_ACTUX4 1532 -#define MACH_TYPE_ESL_OMAP 1533 -#define MACH_TYPE_OMAP2EVM 1534 -#define MACH_TYPE_OMAP3EVM 1535 -#define MACH_TYPE_ADX_PCU57 1536 -#define MACH_TYPE_MONACO 1537 -#define MACH_TYPE_LEVANTE 1538 -#define MACH_TYPE_TMXIPX425 1539 -#define MACH_TYPE_LEEP 1540 -#define MACH_TYPE_RAAD 1541 -#define MACH_TYPE_DNS323 1542 -#define MACH_TYPE_AP1000 1543 -#define MACH_TYPE_A9SAM6432 1544 -#define MACH_TYPE_SHINY 1545 -#define MACH_TYPE_OMAP3_BEAGLE 1546 -#define MACH_TYPE_CSR_BDB2 1547 -#define MACH_TYPE_NOKIA_N810 1548 -#define MACH_TYPE_C270 1549 -#define MACH_TYPE_SENTRY 1550 -#define MACH_TYPE_PCM038 1551 -#define MACH_TYPE_ANC300 1552 -#define MACH_TYPE_HTCKAISER 1553 -#define MACH_TYPE_SBAT100 1554 -#define MACH_TYPE_MODUNORM 1555 -#define MACH_TYPE_PELOS_TWARM 1556 -#define MACH_TYPE_FLANK 1557 -#define MACH_TYPE_SIRLOIN 1558 -#define MACH_TYPE_BRISKET 1559 -#define MACH_TYPE_CHUCK 1560 -#define MACH_TYPE_OTTER 1561 -#define MACH_TYPE_DAVINCI_LDK 1562 -#define MACH_TYPE_PHREEDOM 1563 -#define MACH_TYPE_SG310 1564 -#define MACH_TYPE_TS209 1565 -#define MACH_TYPE_AT91CAP9ADK 1566 -#define MACH_TYPE_TION9315 1567 -#define MACH_TYPE_MAST 1568 -#define MACH_TYPE_PFW 1569 -#define MACH_TYPE_YL_P2440 1570 -#define MACH_TYPE_ZSBC32 1571 -#define MACH_TYPE_OMAP_PACE2 1572 -#define MACH_TYPE_IMX_PACE2 1573 -#define MACH_TYPE_MX31MOBOARD 1574 -#define MACH_TYPE_MX37_3DS 1575 -#define MACH_TYPE_RCC 1576 -#define MACH_TYPE_ARM9 1577 -#define MACH_TYPE_VISION_EP9307 1578 -#define MACH_TYPE_SCLY1000 1579 -#define MACH_TYPE_FONTEL_EP 1580 -#define MACH_TYPE_VOICEBLUE3G 1581 -#define MACH_TYPE_TT9200 1582 -#define MACH_TYPE_DIGI2410 1583 -#define MACH_TYPE_TERASTATION_PRO2 1584 -#define MACH_TYPE_LINKSTATION_PRO 1585 -#define MACH_TYPE_MOTOROLA_A780 1587 -#define MACH_TYPE_MOTOROLA_E6 1588 -#define MACH_TYPE_MOTOROLA_E2 1589 -#define MACH_TYPE_MOTOROLA_E680 1590 -#define MACH_TYPE_UR2410 1591 -#define MACH_TYPE_TAS9261 1592 -#define MACH_TYPE_HERMES_HD 1593 -#define MACH_TYPE_PERSEO_HD 1594 -#define MACH_TYPE_STARGAZER2 1595 -#define MACH_TYPE_E350 1596 -#define MACH_TYPE_WPCM450 1597 -#define MACH_TYPE_CARTESIO 1598 -#define MACH_TYPE_TOYBOX 1599 -#define MACH_TYPE_TX27 1600 -#define MACH_TYPE_TS409 1601 -#define MACH_TYPE_P300 1602 -#define MACH_TYPE_XDACOMET 1603 -#define MACH_TYPE_DEXFLEX2 1604 -#define MACH_TYPE_OW 1605 -#define MACH_TYPE_ARMEBS3 1606 -#define MACH_TYPE_U3 1607 -#define MACH_TYPE_SMDK2450 1608 -#define MACH_TYPE_RSI_EWS 1609 -#define MACH_TYPE_TNB 1610 -#define MACH_TYPE_TOEPATH 1611 -#define MACH_TYPE_KB9263 1612 -#define MACH_TYPE_MT7108 1613 -#define MACH_TYPE_SMTR2440 1614 -#define MACH_TYPE_MANAO 1615 -#define MACH_TYPE_CM_X300 1616 -#define MACH_TYPE_GULFSTREAM_KP 1617 -#define MACH_TYPE_LANREADYFN522 1618 -#define MACH_TYPE_ARMA37 1619 -#define MACH_TYPE_MENDEL 1620 -#define MACH_TYPE_PELCO_ILIAD 1621 -#define MACH_TYPE_UNIT2P 1622 -#define MACH_TYPE_INC20OTTER 1623 -#define MACH_TYPE_AT91SAM9G20EK 1624 -#define MACH_TYPE_STORCENTER 1625 -#define MACH_TYPE_SMDK6410 1626 -#define MACH_TYPE_U300 1627 -#define MACH_TYPE_U500 1628 -#define MACH_TYPE_DS9260 1629 -#define MACH_TYPE_RIVERROCK 1630 -#define MACH_TYPE_SCIBATH 1631 -#define MACH_TYPE_AT91SAM7SE512EK 1632 -#define MACH_TYPE_WRT350N_V2 1633 -#define MACH_TYPE_MULTIMEDIA 1634 -#define MACH_TYPE_MARVIN 1635 -#define MACH_TYPE_X500 1636 -#define MACH_TYPE_AWLUG4LCU 1637 -#define MACH_TYPE_PALERMOC 1638 -#define MACH_TYPE_OMAP_LDP 1639 -#define MACH_TYPE_IP500 1640 -#define MACH_TYPE_ASE2 1642 -#define MACH_TYPE_MX35EVB 1643 -#define MACH_TYPE_AML_M8050 1644 -#define MACH_TYPE_MX35_3DS 1645 -#define MACH_TYPE_MARS 1646 -#define MACH_TYPE_NTOSD_644XA 1647 -#define MACH_TYPE_BADGER 1648 -#define MACH_TYPE_TRIZEPS4WL 1649 -#define MACH_TYPE_TRIZEPS5 1650 -#define MACH_TYPE_MARLIN 1651 -#define MACH_TYPE_TS78XX 1652 -#define MACH_TYPE_HPIPAQ214 1653 -#define MACH_TYPE_AT572D940DCM 1654 -#define MACH_TYPE_NE1BOARD 1655 -#define MACH_TYPE_ZANTE 1656 -#define MACH_TYPE_SFFSDR 1657 -#define MACH_TYPE_TW2662 1658 -#define MACH_TYPE_VF10XX 1659 -#define MACH_TYPE_ZORAN43XX 1660 -#define MACH_TYPE_SONIX926 1661 -#define MACH_TYPE_CELESTIALSEMI 1662 -#define MACH_TYPE_CC9M2443 1663 -#define MACH_TYPE_TW5334 1664 -#define MACH_TYPE_HTCARTEMIS 1665 -#define MACH_TYPE_NAL_HLITE 1666 -#define MACH_TYPE_HTCVOGUE 1667 -#define MACH_TYPE_SMARTWEB 1668 -#define MACH_TYPE_MV86XX 1669 -#define MACH_TYPE_MV87XX 1670 -#define MACH_TYPE_SONGYOUNGHO 1671 -#define MACH_TYPE_YOUNGHOTEMA 1672 -#define MACH_TYPE_PCM037 1673 -#define MACH_TYPE_MMVP 1674 -#define MACH_TYPE_MMAP 1675 -#define MACH_TYPE_PTID2410 1676 -#define MACH_TYPE_JAMES_926 1677 -#define MACH_TYPE_FM6000 1678 -#define MACH_TYPE_DB88F6281_BP 1680 -#define MACH_TYPE_RD88F6192_NAS 1681 -#define MACH_TYPE_RD88F6281 1682 -#define MACH_TYPE_DB78X00_BP 1683 -#define MACH_TYPE_SMDK2416 1685 -#define MACH_TYPE_OCE_SPIDER_SI 1686 -#define MACH_TYPE_OCE_SPIDER_SK 1687 -#define MACH_TYPE_ROVERN6 1688 -#define MACH_TYPE_PELCO_EVOLUTION 1689 -#define MACH_TYPE_WBD111 1690 -#define MACH_TYPE_ELARACPE 1691 -#define MACH_TYPE_MABV3 1692 -#define MACH_TYPE_MV2120 1693 -#define MACH_TYPE_CSB737 1695 -#define MACH_TYPE_MX51_3DS 1696 -#define MACH_TYPE_G900 1697 -#define MACH_TYPE_APF27 1698 -#define MACH_TYPE_GGUS2000 1699 -#define MACH_TYPE_OMAP_2430_MIMIC 1700 -#define MACH_TYPE_IMX27LITE 1701 -#define MACH_TYPE_ALMEX 1702 -#define MACH_TYPE_CONTROL 1703 -#define MACH_TYPE_MBA2410 1704 -#define MACH_TYPE_VOLCANO 1705 -#define MACH_TYPE_ZENITH 1706 -#define MACH_TYPE_MUCHIP 1707 -#define MACH_TYPE_MAGELLAN 1708 -#define MACH_TYPE_USB_A9260 1709 -#define MACH_TYPE_USB_A9263 1710 -#define MACH_TYPE_QIL_A9260 1711 -#define MACH_TYPE_CME9210 1712 -#define MACH_TYPE_HCZH4 1713 -#define MACH_TYPE_SPEARBASIC 1714 -#define MACH_TYPE_DEP2440 1715 -#define MACH_TYPE_HDL_GXR 1716 -#define MACH_TYPE_HDL_GT 1717 -#define MACH_TYPE_HDL_4G 1718 -#define MACH_TYPE_S3C6000 1719 -#define MACH_TYPE_MMSP2_MDK 1720 -#define MACH_TYPE_MPX220 1721 -#define MACH_TYPE_KZM_ARM11_01 1722 -#define MACH_TYPE_HTC_POLARIS 1723 -#define MACH_TYPE_HTC_KAISER 1724 -#define MACH_TYPE_LG_KS20 1725 -#define MACH_TYPE_HHGPS 1726 -#define MACH_TYPE_NOKIA_N810_WIMAX 1727 -#define MACH_TYPE_INSIGHT 1728 -#define MACH_TYPE_SAPPHIRE 1729 -#define MACH_TYPE_CSB637XO 1730 -#define MACH_TYPE_EVISIONG 1731 -#define MACH_TYPE_STMP37XX 1732 -#define MACH_TYPE_STMP38XX 1733 -#define MACH_TYPE_TNT 1734 -#define MACH_TYPE_TBXT 1735 -#define MACH_TYPE_PLAYMATE 1736 -#define MACH_TYPE_PNS10 1737 -#define MACH_TYPE_EZNAVI 1738 -#define MACH_TYPE_PS4000 1739 -#define MACH_TYPE_EZX_A780 1740 -#define MACH_TYPE_EZX_E680 1741 -#define MACH_TYPE_EZX_A1200 1742 -#define MACH_TYPE_EZX_E6 1743 -#define MACH_TYPE_EZX_E2 1744 -#define MACH_TYPE_EZX_A910 1745 -#define MACH_TYPE_CWMX31 1746 -#define MACH_TYPE_SL2312 1747 -#define MACH_TYPE_BLENNY 1748 -#define MACH_TYPE_DS107 1749 -#define MACH_TYPE_DSX07 1750 -#define MACH_TYPE_PICOCOM1 1751 -#define MACH_TYPE_LYNX_WOLVERINE 1752 -#define MACH_TYPE_UBISYS_P9_SC19 1753 -#define MACH_TYPE_KRATOS_LOW 1754 -#define MACH_TYPE_M700 1755 -#define MACH_TYPE_EDMINI_V2 1756 -#define MACH_TYPE_ZIPIT2 1757 -#define MACH_TYPE_HSLFEMTOCELL 1758 -#define MACH_TYPE_DAINTREE_AT91 1759 -#define MACH_TYPE_SG560USB 1760 -#define MACH_TYPE_OMAP3_PANDORA 1761 -#define MACH_TYPE_USR8200 1762 -#define MACH_TYPE_S1S65K 1763 -#define MACH_TYPE_S2S65A 1764 -#define MACH_TYPE_ICORE 1765 -#define MACH_TYPE_MSS2 1766 -#define MACH_TYPE_BELMONT 1767 -#define MACH_TYPE_ASUSP525 1768 -#define MACH_TYPE_LB88RC8480 1769 -#define MACH_TYPE_HIPXA 1770 -#define MACH_TYPE_MX25_3DS 1771 -#define MACH_TYPE_M800 1772 -#define MACH_TYPE_OMAP3530_LV_SOM 1773 -#define MACH_TYPE_PRIMA_EVB 1774 -#define MACH_TYPE_MX31BT1 1775 -#define MACH_TYPE_ATLAS4_EVB 1776 -#define MACH_TYPE_MX31CICADA 1777 -#define MACH_TYPE_MI424WR 1778 -#define MACH_TYPE_AXS_ULTRAX 1779 -#define MACH_TYPE_AT572D940DEB 1780 -#define MACH_TYPE_DAVINCI_DA8XX_EVM 1781 -#define MACH_TYPE_EP9302 1782 -#define MACH_TYPE_AT572D940HFEB 1783 -#define MACH_TYPE_CYBOOK3 1784 -#define MACH_TYPE_WDG002 1785 -#define MACH_TYPE_SG560ADSL 1786 -#define MACH_TYPE_NEXTIO_N2800_ICA 1787 -#define MACH_TYPE_MARVELL_NEWDB 1789 -#define MACH_TYPE_VANDIHUD 1790 -#define MACH_TYPE_MAGX_E8 1791 -#define MACH_TYPE_MAGX_Z6 1792 -#define MACH_TYPE_MAGX_V8 1793 -#define MACH_TYPE_MAGX_U9 1794 -#define MACH_TYPE_TOUGHCF08 1795 -#define MACH_TYPE_ZW4400 1796 -#define MACH_TYPE_MARAT91 1797 -#define MACH_TYPE_OVERO 1798 -#define MACH_TYPE_AT2440EVB 1799 -#define MACH_TYPE_NEOCORE926 1800 -#define MACH_TYPE_WNR854T 1801 -#define MACH_TYPE_IMX27 1802 -#define MACH_TYPE_MOOSE_DB 1803 -#define MACH_TYPE_FAB4 1804 -#define MACH_TYPE_HTCDIAMOND 1805 -#define MACH_TYPE_FIONA 1806 -#define MACH_TYPE_MXC30030_X 1807 -#define MACH_TYPE_BMP1000 1808 -#define MACH_TYPE_LOGI9200 1809 -#define MACH_TYPE_TQMA31 1810 -#define MACH_TYPE_CCW9P9215JS 1811 -#define MACH_TYPE_RD88F5181L_GE 1812 -#define MACH_TYPE_SIFMAIN 1813 -#define MACH_TYPE_SAM9_L9261 1814 -#define MACH_TYPE_CC9M2443JS 1815 -#define MACH_TYPE_XARIA300 1816 -#define MACH_TYPE_IT9200 1817 -#define MACH_TYPE_RD88F5181L_FXO 1818 -#define MACH_TYPE_KRISS_SENSOR 1819 -#define MACH_TYPE_PILZ_PMI5 1820 -#define MACH_TYPE_JADE 1821 -#define MACH_TYPE_KS8695_SOFTPLC 1822 -#define MACH_TYPE_GPRISC3 1823 -#define MACH_TYPE_STAMP9G20 1824 -#define MACH_TYPE_SMDK6430 1825 -#define MACH_TYPE_SMDKC100 1826 -#define MACH_TYPE_TAVOREVB 1827 -#define MACH_TYPE_SAAR 1828 -#define MACH_TYPE_DEISTER_EYECAM 1829 -#define MACH_TYPE_AT91SAM9M10EK 1830 -#define MACH_TYPE_LINKSTATION_PRODUO 1831 -#define MACH_TYPE_HIT_B0 1832 -#define MACH_TYPE_ADX_RMU 1833 -#define MACH_TYPE_XG_CPE_MAIN 1834 -#define MACH_TYPE_EDB9407A 1835 -#define MACH_TYPE_DTB9608 1836 -#define MACH_TYPE_EM104V1 1837 -#define MACH_TYPE_DEMO 1838 -#define MACH_TYPE_LOGI9260 1839 -#define MACH_TYPE_MX31_EXM32 1840 -#define MACH_TYPE_USB_A9G20 1841 -#define MACH_TYPE_PICPROJE2008 1842 -#define MACH_TYPE_CS_E9315 1843 -#define MACH_TYPE_QIL_A9G20 1844 -#define MACH_TYPE_SHA_PON020 1845 -#define MACH_TYPE_NAD 1846 -#define MACH_TYPE_SBC35_A9260 1847 -#define MACH_TYPE_SBC35_A9G20 1848 -#define MACH_TYPE_DAVINCI_BEGINNING 1849 -#define MACH_TYPE_UWC 1850 -#define MACH_TYPE_MXLADS 1851 -#define MACH_TYPE_HTCNIKE 1852 -#define MACH_TYPE_DEISTER_PXA270 1853 -#define MACH_TYPE_CME9210JS 1854 -#define MACH_TYPE_CC9P9360 1855 -#define MACH_TYPE_MOCHA 1856 -#define MACH_TYPE_WAPD170AG 1857 -#define MACH_TYPE_LINKSTATION_MINI 1858 -#define MACH_TYPE_AFEB9260 1859 -#define MACH_TYPE_W90X900 1860 -#define MACH_TYPE_W90X700 1861 -#define MACH_TYPE_KT300IP 1862 -#define MACH_TYPE_KT300IP_G20 1863 -#define MACH_TYPE_SRCM 1864 -#define MACH_TYPE_WLNX_9260 1865 -#define MACH_TYPE_OPENMOKO_GTA03 1866 -#define MACH_TYPE_OSPREY2 1867 -#define MACH_TYPE_KBIO9260 1868 -#define MACH_TYPE_GINZA 1869 -#define MACH_TYPE_A636N 1870 -#define MACH_TYPE_IMX27IPCAM 1871 -#define MACH_TYPE_NEMOC 1872 -#define MACH_TYPE_GENEVA 1873 -#define MACH_TYPE_HTCPHAROS 1874 -#define MACH_TYPE_NEONC 1875 -#define MACH_TYPE_NAS7100 1876 -#define MACH_TYPE_TEUPHONE 1877 -#define MACH_TYPE_ANNAX_ETH2 1878 -#define MACH_TYPE_CSB733 1879 -#define MACH_TYPE_BK3 1880 -#define MACH_TYPE_OMAP_EM32 1881 -#define MACH_TYPE_ET9261CP 1882 -#define MACH_TYPE_JASPERC 1883 -#define MACH_TYPE_ISSI_ARM9 1884 -#define MACH_TYPE_UED 1885 -#define MACH_TYPE_ESIBLADE 1886 -#define MACH_TYPE_EYE02 1887 -#define MACH_TYPE_IMX27KBD 1888 -#define MACH_TYPE_SST61VC010_FPGA 1889 -#define MACH_TYPE_KIXVP435 1890 -#define MACH_TYPE_KIXNP435 1891 -#define MACH_TYPE_AFRICA 1892 -#define MACH_TYPE_NH233 1893 -#define MACH_TYPE_RD88F6183AP_GE 1894 -#define MACH_TYPE_BCM4760 1895 -#define MACH_TYPE_EDDY_V2 1896 -#define MACH_TYPE_REALVIEW_PBA8 1897 -#define MACH_TYPE_HID_A7 1898 -#define MACH_TYPE_HERO 1899 -#define MACH_TYPE_OMAP_POSEIDON 1900 -#define MACH_TYPE_REALVIEW_PBX 1901 -#define MACH_TYPE_MICRO9S 1902 -#define MACH_TYPE_MAKO 1903 -#define MACH_TYPE_XDAFLAME 1904 -#define MACH_TYPE_PHIDGET_SBC2 1905 -#define MACH_TYPE_LIMESTONE 1906 -#define MACH_TYPE_IPROBE_C32 1907 -#define MACH_TYPE_RUT100 1908 -#define MACH_TYPE_ASUSP535 1909 -#define MACH_TYPE_HTCRAPHAEL 1910 -#define MACH_TYPE_SYGDG1 1911 -#define MACH_TYPE_SYGDG2 1912 -#define MACH_TYPE_SEOUL 1913 -#define MACH_TYPE_SALERNO 1914 -#define MACH_TYPE_UCN_S3C64XX 1915 -#define MACH_TYPE_MSM7201A 1916 -#define MACH_TYPE_LPR1 1917 -#define MACH_TYPE_ARMADILLO500FX 1918 -#define MACH_TYPE_G3EVM 1919 -#define MACH_TYPE_Z3_DM355 1920 -#define MACH_TYPE_W90P910EVB 1921 -#define MACH_TYPE_W90P920EVB 1922 -#define MACH_TYPE_W90P950EVB 1923 -#define MACH_TYPE_W90N960EVB 1924 -#define MACH_TYPE_CAMHD 1925 -#define MACH_TYPE_MVC100 1926 -#define MACH_TYPE_ELECTRUM_200 1927 -#define MACH_TYPE_HTCJADE 1928 -#define MACH_TYPE_MEMPHIS 1929 -#define MACH_TYPE_IMX27SBC 1930 -#define MACH_TYPE_LEXTAR 1931 -#define MACH_TYPE_MV88F6281GTW_GE 1932 -#define MACH_TYPE_NCP 1933 -#define MACH_TYPE_Z32AN 1934 -#define MACH_TYPE_TMQ_CAPD 1935 -#define MACH_TYPE_OMAP3_WL 1936 -#define MACH_TYPE_CHUMBY 1937 -#define MACH_TYPE_ATSARM9 1938 -#define MACH_TYPE_DAVINCI_DM365_EVM 1939 -#define MACH_TYPE_BAHAMAS 1940 -#define MACH_TYPE_DAS 1941 -#define MACH_TYPE_MINIDAS 1942 -#define MACH_TYPE_VK1000 1943 -#define MACH_TYPE_CENTRO 1944 -#define MACH_TYPE_CTERA_2BAY 1945 -#define MACH_TYPE_EDGECONNECT 1946 -#define MACH_TYPE_ND27000 1947 -#define MACH_TYPE_GEMALTO_COBRA 1948 -#define MACH_TYPE_INGELABS_COMET 1949 -#define MACH_TYPE_POLLUX_WIZ 1950 -#define MACH_TYPE_BLACKSTONE 1951 -#define MACH_TYPE_TOPAZ 1952 -#define MACH_TYPE_AIXLE 1953 -#define MACH_TYPE_MW998 1954 -#define MACH_TYPE_NOKIA_RX51 1955 -#define MACH_TYPE_VSC5605EV 1956 -#define MACH_TYPE_NT98700DK 1957 -#define MACH_TYPE_ICONTACT 1958 -#define MACH_TYPE_SWARCO_FRCPU 1959 -#define MACH_TYPE_SWARCO_SCPU 1960 -#define MACH_TYPE_BBOX_P16 1961 -#define MACH_TYPE_BSTD 1962 -#define MACH_TYPE_SBC2440II 1963 -#define MACH_TYPE_PCM034 1964 -#define MACH_TYPE_NESO 1965 -#define MACH_TYPE_WLNX_9G20 1966 -#define MACH_TYPE_OMAP_ZOOM2 1967 -#define MACH_TYPE_TOTEMNOVA 1968 -#define MACH_TYPE_C5000 1969 -#define MACH_TYPE_UNIPO_AT91SAM9263 1970 -#define MACH_TYPE_ETHERNUT5 1971 -#define MACH_TYPE_ARM11 1972 -#define MACH_TYPE_CPUAT9260 1973 -#define MACH_TYPE_CPUPXA255 1974 -#define MACH_TYPE_CPUIMX27 1975 -#define MACH_TYPE_CHEFLUX 1976 -#define MACH_TYPE_EB_CPUX9K2 1977 -#define MACH_TYPE_OPCOTEC 1978 -#define MACH_TYPE_YT 1979 -#define MACH_TYPE_MOTOQ 1980 -#define MACH_TYPE_BSB1 1981 -#define MACH_TYPE_ACS5K 1982 -#define MACH_TYPE_MILAN 1983 -#define MACH_TYPE_QUARTZV2 1984 -#define MACH_TYPE_RSVP 1985 -#define MACH_TYPE_RMP200 1986 -#define MACH_TYPE_SNAPPER_9260 1987 -#define MACH_TYPE_DSM320 1988 -#define MACH_TYPE_ADSGCM 1989 -#define MACH_TYPE_ASE2_400 1990 -#define MACH_TYPE_PIZZA 1991 -#define MACH_TYPE_SPOT_NGPL 1992 -#define MACH_TYPE_ARMATA 1993 -#define MACH_TYPE_EXEDA 1994 -#define MACH_TYPE_MX31SF005 1995 -#define MACH_TYPE_F5D8231_4_V2 1996 -#define MACH_TYPE_Q2440 1997 -#define MACH_TYPE_QQ2440 1998 -#define MACH_TYPE_MINI2440 1999 -#define MACH_TYPE_COLIBRI300 2000 -#define MACH_TYPE_JADES 2001 -#define MACH_TYPE_SPARK 2002 -#define MACH_TYPE_BENZINA 2003 -#define MACH_TYPE_BLAZE 2004 -#define MACH_TYPE_LINKSTATION_LS_HGL 2005 -#define MACH_TYPE_HTCVENUS 2006 -#define MACH_TYPE_SONY_PRS505 2007 -#define MACH_TYPE_HANLIN_V3 2008 -#define MACH_TYPE_SAPPHIRA 2009 -#define MACH_TYPE_DACK_SDA_01 2010 -#define MACH_TYPE_ARMBOX 2011 -#define MACH_TYPE_HARRIS_RVP 2012 -#define MACH_TYPE_RIBALDO 2013 -#define MACH_TYPE_AGORA 2014 -#define MACH_TYPE_OMAP3_MINI 2015 -#define MACH_TYPE_A9SAM6432_B 2016 -#define MACH_TYPE_USG2410 2017 -#define MACH_TYPE_PC72052_I10_REVB 2018 -#define MACH_TYPE_MX35_EXM32 2019 -#define MACH_TYPE_TOPAS910 2020 -#define MACH_TYPE_HYENA 2021 -#define MACH_TYPE_POSPAX 2022 -#define MACH_TYPE_HDL_GX 2023 -#define MACH_TYPE_CTERA_4BAY 2024 -#define MACH_TYPE_CTERA_PLUG_C 2025 -#define MACH_TYPE_CRWEA_PLUG_I 2026 -#define MACH_TYPE_EGAUGE2 2027 -#define MACH_TYPE_DIDJ 2028 -#define MACH_TYPE_MEISTER 2029 -#define MACH_TYPE_HTCBLACKSTONE 2030 -#define MACH_TYPE_CPUAT9G20 2031 -#define MACH_TYPE_SMDK6440 2032 -#define MACH_TYPE_OMAP_35XX_MVP 2033 -#define MACH_TYPE_CTERA_PLUG_I 2034 -#define MACH_TYPE_PVG610 2035 -#define MACH_TYPE_HPRW6815 2036 -#define MACH_TYPE_OMAP3_OSWALD 2037 -#define MACH_TYPE_NAS4220B 2038 -#define MACH_TYPE_HTCRAPHAEL_CDMA 2039 -#define MACH_TYPE_HTCDIAMOND_CDMA 2040 -#define MACH_TYPE_SCALER 2041 -#define MACH_TYPE_ZYLONITE2 2042 -#define MACH_TYPE_ASPENITE 2043 -#define MACH_TYPE_TETON 2044 -#define MACH_TYPE_TTC_DKB 2045 -#define MACH_TYPE_BISHOP2 2046 -#define MACH_TYPE_IPPV5 2047 -#define MACH_TYPE_FARM926 2048 -#define MACH_TYPE_MMCCPU 2049 -#define MACH_TYPE_SGMSFL 2050 -#define MACH_TYPE_TT8000 2051 -#define MACH_TYPE_ZRN4300LP 2052 -#define MACH_TYPE_MPTC 2053 -#define MACH_TYPE_H6051 2054 -#define MACH_TYPE_PVG610_101 2055 -#define MACH_TYPE_STAMP9261_PC_EVB 2056 -#define MACH_TYPE_PELCO_ODYSSEUS 2057 -#define MACH_TYPE_TNY_A9260 2058 -#define MACH_TYPE_TNY_A9G20 2059 -#define MACH_TYPE_AESOP_MP2530F 2060 -#define MACH_TYPE_DX900 2061 -#define MACH_TYPE_CPODC2 2062 -#define MACH_TYPE_TILT_8925 2063 -#define MACH_TYPE_DAVINCI_DM357_EVM 2064 -#define MACH_TYPE_SWORDFISH 2065 -#define MACH_TYPE_CORVUS 2066 -#define MACH_TYPE_TAURUS 2067 -#define MACH_TYPE_AXM 2068 -#define MACH_TYPE_AXC 2069 -#define MACH_TYPE_BABY 2070 -#define MACH_TYPE_MP200 2071 -#define MACH_TYPE_PCM043 2072 -#define MACH_TYPE_HANLIN_V3C 2073 -#define MACH_TYPE_KBK9G20 2074 - -#ifdef CONFIG_ARCH_EBSA110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EBSA110 -# endif -# define machine_is_ebsa110() (machine_arch_type == MACH_TYPE_EBSA110) -#else -# define machine_is_ebsa110() (0) -#endif - -#ifdef CONFIG_ARCH_RPC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RISCPC -# endif -# define machine_is_riscpc() (machine_arch_type == MACH_TYPE_RISCPC) -#else -# define machine_is_riscpc() (0) -#endif - -#ifdef CONFIG_ARCH_NEXUSPCI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXUSPCI -# endif -# define machine_is_nexuspci() (machine_arch_type == MACH_TYPE_NEXUSPCI) -#else -# define machine_is_nexuspci() (0) -#endif - -#ifdef CONFIG_ARCH_EBSA285 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EBSA285 -# endif -# define machine_is_ebsa285() (machine_arch_type == MACH_TYPE_EBSA285) -#else -# define machine_is_ebsa285() (0) -#endif - -#ifdef CONFIG_ARCH_NETWINDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETWINDER -# endif -# define machine_is_netwinder() (machine_arch_type == MACH_TYPE_NETWINDER) -#else -# define machine_is_netwinder() (0) -#endif - -#ifdef CONFIG_ARCH_CATS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CATS -# endif -# define machine_is_cats() (machine_arch_type == MACH_TYPE_CATS) -#else -# define machine_is_cats() (0) -#endif - -#ifdef CONFIG_ARCH_TBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TBOX -# endif -# define machine_is_tbox() (machine_arch_type == MACH_TYPE_TBOX) -#else -# define machine_is_tbox() (0) -#endif - -#ifdef CONFIG_ARCH_CO285 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CO285 -# endif -# define machine_is_co285() (machine_arch_type == MACH_TYPE_CO285) -#else -# define machine_is_co285() (0) -#endif - -#ifdef CONFIG_ARCH_CLPS7110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLPS7110 -# endif -# define machine_is_clps7110() (machine_arch_type == MACH_TYPE_CLPS7110) -#else -# define machine_is_clps7110() (0) -#endif - -#ifdef CONFIG_ARCH_ARC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCHIMEDES -# endif -# define machine_is_archimedes() (machine_arch_type == MACH_TYPE_ARCHIMEDES) -#else -# define machine_is_archimedes() (0) -#endif - -#ifdef CONFIG_ARCH_A5K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A5K -# endif -# define machine_is_a5k() (machine_arch_type == MACH_TYPE_A5K) -#else -# define machine_is_a5k() (0) -#endif - -#ifdef CONFIG_ARCH_ETOILE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETOILE -# endif -# define machine_is_etoile() (machine_arch_type == MACH_TYPE_ETOILE) -#else -# define machine_is_etoile() (0) -#endif - -#ifdef CONFIG_ARCH_LACIE_NAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LACIE_NAS -# endif -# define machine_is_lacie_nas() (machine_arch_type == MACH_TYPE_LACIE_NAS) -#else -# define machine_is_lacie_nas() (0) -#endif - -#ifdef CONFIG_ARCH_CLPS7500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLPS7500 -# endif -# define machine_is_clps7500() (machine_arch_type == MACH_TYPE_CLPS7500) -#else -# define machine_is_clps7500() (0) -#endif - -#ifdef CONFIG_ARCH_SHARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHARK -# endif -# define machine_is_shark() (machine_arch_type == MACH_TYPE_SHARK) -#else -# define machine_is_shark() (0) -#endif - -#ifdef CONFIG_SA1100_BRUTUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRUTUS -# endif -# define machine_is_brutus() (machine_arch_type == MACH_TYPE_BRUTUS) -#else -# define machine_is_brutus() (0) -#endif - -#ifdef CONFIG_ARCH_PERSONAL_SERVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PERSONAL_SERVER -# endif -# define machine_is_personal_server() (machine_arch_type == MACH_TYPE_PERSONAL_SERVER) -#else -# define machine_is_personal_server() (0) -#endif - -#ifdef CONFIG_SA1100_ITSY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ITSY -# endif -# define machine_is_itsy() (machine_arch_type == MACH_TYPE_ITSY) -#else -# define machine_is_itsy() (0) -#endif - -#ifdef CONFIG_ARCH_L7200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_L7200 -# endif -# define machine_is_l7200() (machine_arch_type == MACH_TYPE_L7200) -#else -# define machine_is_l7200() (0) -#endif - -#ifdef CONFIG_SA1100_PLEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLEB -# endif -# define machine_is_pleb() (machine_arch_type == MACH_TYPE_PLEB) -#else -# define machine_is_pleb() (0) -#endif - -#ifdef CONFIG_ARCH_INTEGRATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INTEGRATOR -# endif -# define machine_is_integrator() (machine_arch_type == MACH_TYPE_INTEGRATOR) -#else -# define machine_is_integrator() (0) -#endif - -#ifdef CONFIG_SA1100_H3600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H3600 -# endif -# define machine_is_h3600() (machine_arch_type == MACH_TYPE_H3600) -#else -# define machine_is_h3600() (0) -#endif - -#ifdef CONFIG_ARCH_IXP1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP1200 -# endif -# define machine_is_ixp1200() (machine_arch_type == MACH_TYPE_IXP1200) -#else -# define machine_is_ixp1200() (0) -#endif - -#ifdef CONFIG_ARCH_P720T -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P720T -# endif -# define machine_is_p720t() (machine_arch_type == MACH_TYPE_P720T) -#else -# define machine_is_p720t() (0) -#endif - -#ifdef CONFIG_SA1100_ASSABET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASSABET -# endif -# define machine_is_assabet() (machine_arch_type == MACH_TYPE_ASSABET) -#else -# define machine_is_assabet() (0) -#endif - -#ifdef CONFIG_SA1100_VICTOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VICTOR -# endif -# define machine_is_victor() (machine_arch_type == MACH_TYPE_VICTOR) -#else -# define machine_is_victor() (0) -#endif - -#ifdef CONFIG_SA1100_LART -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LART -# endif -# define machine_is_lart() (machine_arch_type == MACH_TYPE_LART) -#else -# define machine_is_lart() (0) -#endif - -#ifdef CONFIG_SA1100_RANGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RANGER -# endif -# define machine_is_ranger() (machine_arch_type == MACH_TYPE_RANGER) -#else -# define machine_is_ranger() (0) -#endif - -#ifdef CONFIG_SA1100_GRAPHICSCLIENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRAPHICSCLIENT -# endif -# define machine_is_graphicsclient() (machine_arch_type == MACH_TYPE_GRAPHICSCLIENT) -#else -# define machine_is_graphicsclient() (0) -#endif - -#ifdef CONFIG_SA1100_XP860 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XP860 -# endif -# define machine_is_xp860() (machine_arch_type == MACH_TYPE_XP860) -#else -# define machine_is_xp860() (0) -#endif - -#ifdef CONFIG_SA1100_CERF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CERF -# endif -# define machine_is_cerf() (machine_arch_type == MACH_TYPE_CERF) -#else -# define machine_is_cerf() (0) -#endif - -#ifdef CONFIG_SA1100_NANOENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NANOENGINE -# endif -# define machine_is_nanoengine() (machine_arch_type == MACH_TYPE_NANOENGINE) -#else -# define machine_is_nanoengine() (0) -#endif - -#ifdef CONFIG_SA1100_FPIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FPIC -# endif -# define machine_is_fpic() (machine_arch_type == MACH_TYPE_FPIC) -#else -# define machine_is_fpic() (0) -#endif - -#ifdef CONFIG_SA1100_EXTENEX1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXTENEX1 -# endif -# define machine_is_extenex1() (machine_arch_type == MACH_TYPE_EXTENEX1) -#else -# define machine_is_extenex1() (0) -#endif - -#ifdef CONFIG_SA1100_SHERMAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHERMAN -# endif -# define machine_is_sherman() (machine_arch_type == MACH_TYPE_SHERMAN) -#else -# define machine_is_sherman() (0) -#endif - -#ifdef CONFIG_SA1100_ACCELENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACCELENT_SA -# endif -# define machine_is_accelent_sa() (machine_arch_type == MACH_TYPE_ACCELENT_SA) -#else -# define machine_is_accelent_sa() (0) -#endif - -#ifdef CONFIG_ARCH_L7200_ACCELENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACCELENT_L7200 -# endif -# define machine_is_accelent_l7200() (machine_arch_type == MACH_TYPE_ACCELENT_L7200) -#else -# define machine_is_accelent_l7200() (0) -#endif - -#ifdef CONFIG_SA1100_NETPORT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETPORT -# endif -# define machine_is_netport() (machine_arch_type == MACH_TYPE_NETPORT) -#else -# define machine_is_netport() (0) -#endif - -#ifdef CONFIG_SA1100_PANGOLIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PANGOLIN -# endif -# define machine_is_pangolin() (machine_arch_type == MACH_TYPE_PANGOLIN) -#else -# define machine_is_pangolin() (0) -#endif - -#ifdef CONFIG_SA1100_YOPY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YOPY -# endif -# define machine_is_yopy() (machine_arch_type == MACH_TYPE_YOPY) -#else -# define machine_is_yopy() (0) -#endif - -#ifdef CONFIG_SA1100_COOLIDGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COOLIDGE -# endif -# define machine_is_coolidge() (machine_arch_type == MACH_TYPE_COOLIDGE) -#else -# define machine_is_coolidge() (0) -#endif - -#ifdef CONFIG_SA1100_HUW_WEBPANEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUW_WEBPANEL -# endif -# define machine_is_huw_webpanel() (machine_arch_type == MACH_TYPE_HUW_WEBPANEL) -#else -# define machine_is_huw_webpanel() (0) -#endif - -#ifdef CONFIG_ARCH_SPOTME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPOTME -# endif -# define machine_is_spotme() (machine_arch_type == MACH_TYPE_SPOTME) -#else -# define machine_is_spotme() (0) -#endif - -#ifdef CONFIG_ARCH_FREEBIRD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FREEBIRD -# endif -# define machine_is_freebird() (machine_arch_type == MACH_TYPE_FREEBIRD) -#else -# define machine_is_freebird() (0) -#endif - -#ifdef CONFIG_ARCH_TI925 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TI925 -# endif -# define machine_is_ti925() (machine_arch_type == MACH_TYPE_TI925) -#else -# define machine_is_ti925() (0) -#endif - -#ifdef CONFIG_ARCH_RISCSTATION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RISCSTATION -# endif -# define machine_is_riscstation() (machine_arch_type == MACH_TYPE_RISCSTATION) -#else -# define machine_is_riscstation() (0) -#endif - -#ifdef CONFIG_SA1100_CAVY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAVY -# endif -# define machine_is_cavy() (machine_arch_type == MACH_TYPE_CAVY) -#else -# define machine_is_cavy() (0) -#endif - -#ifdef CONFIG_SA1100_JORNADA720 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JORNADA720 -# endif -# define machine_is_jornada720() (machine_arch_type == MACH_TYPE_JORNADA720) -#else -# define machine_is_jornada720() (0) -#endif - -#ifdef CONFIG_SA1100_OMNIMETER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMNIMETER -# endif -# define machine_is_omnimeter() (machine_arch_type == MACH_TYPE_OMNIMETER) -#else -# define machine_is_omnimeter() (0) -#endif - -#ifdef CONFIG_ARCH_EDB7211 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB7211 -# endif -# define machine_is_edb7211() (machine_arch_type == MACH_TYPE_EDB7211) -#else -# define machine_is_edb7211() (0) -#endif - -#ifdef CONFIG_SA1100_CITYGO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CITYGO -# endif -# define machine_is_citygo() (machine_arch_type == MACH_TYPE_CITYGO) -#else -# define machine_is_citygo() (0) -#endif - -#ifdef CONFIG_SA1100_PFS168 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PFS168 -# endif -# define machine_is_pfs168() (machine_arch_type == MACH_TYPE_PFS168) -#else -# define machine_is_pfs168() (0) -#endif - -#ifdef CONFIG_SA1100_SPOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPOT -# endif -# define machine_is_spot() (machine_arch_type == MACH_TYPE_SPOT) -#else -# define machine_is_spot() (0) -#endif - -#ifdef CONFIG_SA1100_FLEXANET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLEXANET -# endif -# define machine_is_flexanet() (machine_arch_type == MACH_TYPE_FLEXANET) -#else -# define machine_is_flexanet() (0) -#endif - -#ifdef CONFIG_ARCH_WEBPAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEBPAL -# endif -# define machine_is_webpal() (machine_arch_type == MACH_TYPE_WEBPAL) -#else -# define machine_is_webpal() (0) -#endif - -#ifdef CONFIG_SA1100_LINPDA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINPDA -# endif -# define machine_is_linpda() (machine_arch_type == MACH_TYPE_LINPDA) -#else -# define machine_is_linpda() (0) -#endif - -#ifdef CONFIG_ARCH_ANAKIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANAKIN -# endif -# define machine_is_anakin() (machine_arch_type == MACH_TYPE_ANAKIN) -#else -# define machine_is_anakin() (0) -#endif - -#ifdef CONFIG_SA1100_MVI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MVI -# endif -# define machine_is_mvi() (machine_arch_type == MACH_TYPE_MVI) -#else -# define machine_is_mvi() (0) -#endif - -#ifdef CONFIG_SA1100_JUPITER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JUPITER -# endif -# define machine_is_jupiter() (machine_arch_type == MACH_TYPE_JUPITER) -#else -# define machine_is_jupiter() (0) -#endif - -#ifdef CONFIG_ARCH_PSIONW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PSIONW -# endif -# define machine_is_psionw() (machine_arch_type == MACH_TYPE_PSIONW) -#else -# define machine_is_psionw() (0) -#endif - -#ifdef CONFIG_SA1100_ALN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALN -# endif -# define machine_is_aln() (machine_arch_type == MACH_TYPE_ALN) -#else -# define machine_is_aln() (0) -#endif - -#ifdef CONFIG_ARCH_CAMELOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAMELOT -# endif -# define machine_is_epxa() (machine_arch_type == MACH_TYPE_CAMELOT) -#else -# define machine_is_epxa() (0) -#endif - -#ifdef CONFIG_SA1100_GDS2200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GDS2200 -# endif -# define machine_is_gds2200() (machine_arch_type == MACH_TYPE_GDS2200) -#else -# define machine_is_gds2200() (0) -#endif - -#ifdef CONFIG_SA1100_PSION_SERIES7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PSION_SERIES7 -# endif -# define machine_is_netbook() (machine_arch_type == MACH_TYPE_PSION_SERIES7) -#else -# define machine_is_netbook() (0) -#endif - -#ifdef CONFIG_SA1100_XFILE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XFILE -# endif -# define machine_is_xfile() (machine_arch_type == MACH_TYPE_XFILE) -#else -# define machine_is_xfile() (0) -#endif - -#ifdef CONFIG_ARCH_ACCELENT_EP9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACCELENT_EP9312 -# endif -# define machine_is_accelent_ep9312() (machine_arch_type == MACH_TYPE_ACCELENT_EP9312) -#else -# define machine_is_accelent_ep9312() (0) -#endif - -#ifdef CONFIG_ARCH_IC200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IC200 -# endif -# define machine_is_ic200() (machine_arch_type == MACH_TYPE_IC200) -#else -# define machine_is_ic200() (0) -#endif - -#ifdef CONFIG_SA1100_CREDITLART -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CREDITLART -# endif -# define machine_is_creditlart() (machine_arch_type == MACH_TYPE_CREDITLART) -#else -# define machine_is_creditlart() (0) -#endif - -#ifdef CONFIG_SA1100_HTM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTM -# endif -# define machine_is_htm() (machine_arch_type == MACH_TYPE_HTM) -#else -# define machine_is_htm() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80310 -# endif -# define machine_is_iq80310() (machine_arch_type == MACH_TYPE_IQ80310) -#else -# define machine_is_iq80310() (0) -#endif - -#ifdef CONFIG_SA1100_FREEBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FREEBOT -# endif -# define machine_is_freebot() (machine_arch_type == MACH_TYPE_FREEBOT) -#else -# define machine_is_freebot() (0) -#endif - -#ifdef CONFIG_ARCH_ENTEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENTEL -# endif -# define machine_is_entel() (machine_arch_type == MACH_TYPE_ENTEL) -#else -# define machine_is_entel() (0) -#endif - -#ifdef CONFIG_ARCH_ENP3510 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENP3510 -# endif -# define machine_is_enp3510() (machine_arch_type == MACH_TYPE_ENP3510) -#else -# define machine_is_enp3510() (0) -#endif - -#ifdef CONFIG_SA1100_TRIZEPS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS -# endif -# define machine_is_trizeps() (machine_arch_type == MACH_TYPE_TRIZEPS) -#else -# define machine_is_trizeps() (0) -#endif - -#ifdef CONFIG_SA1100_NESA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NESA -# endif -# define machine_is_nesa() (machine_arch_type == MACH_TYPE_NESA) -#else -# define machine_is_nesa() (0) -#endif - -#ifdef CONFIG_ARCH_VENUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VENUS -# endif -# define machine_is_venus() (machine_arch_type == MACH_TYPE_VENUS) -#else -# define machine_is_venus() (0) -#endif - -#ifdef CONFIG_ARCH_TARDIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TARDIS -# endif -# define machine_is_tardis() (machine_arch_type == MACH_TYPE_TARDIS) -#else -# define machine_is_tardis() (0) -#endif - -#ifdef CONFIG_ARCH_MERCURY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MERCURY -# endif -# define machine_is_mercury() (machine_arch_type == MACH_TYPE_MERCURY) -#else -# define machine_is_mercury() (0) -#endif - -#ifdef CONFIG_SA1100_EMPEG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPEG -# endif -# define machine_is_empeg() (machine_arch_type == MACH_TYPE_EMPEG) -#else -# define machine_is_empeg() (0) -#endif - -#ifdef CONFIG_ARCH_I80200FCC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I80200FCC -# endif -# define machine_is_adi_evb() (machine_arch_type == MACH_TYPE_I80200FCC) -#else -# define machine_is_adi_evb() (0) -#endif - -#ifdef CONFIG_SA1100_ITT_CPB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ITT_CPB -# endif -# define machine_is_itt_cpb() (machine_arch_type == MACH_TYPE_ITT_CPB) -#else -# define machine_is_itt_cpb() (0) -#endif - -#ifdef CONFIG_SA1100_SVC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVC -# endif -# define machine_is_svc() (machine_arch_type == MACH_TYPE_SVC) -#else -# define machine_is_svc() (0) -#endif - -#ifdef CONFIG_SA1100_ALPHA2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALPHA2 -# endif -# define machine_is_alpha2() (machine_arch_type == MACH_TYPE_ALPHA2) -#else -# define machine_is_alpha2() (0) -#endif - -#ifdef CONFIG_SA1100_ALPHA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALPHA1 -# endif -# define machine_is_alpha1() (machine_arch_type == MACH_TYPE_ALPHA1) -#else -# define machine_is_alpha1() (0) -#endif - -#ifdef CONFIG_ARCH_NETARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETARM -# endif -# define machine_is_netarm() (machine_arch_type == MACH_TYPE_NETARM) -#else -# define machine_is_netarm() (0) -#endif - -#ifdef CONFIG_SA1100_SIMPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIMPAD -# endif -# define machine_is_simpad() (machine_arch_type == MACH_TYPE_SIMPAD) -#else -# define machine_is_simpad() (0) -#endif - -#ifdef CONFIG_ARCH_PDA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PDA1 -# endif -# define machine_is_pda1() (machine_arch_type == MACH_TYPE_PDA1) -#else -# define machine_is_pda1() (0) -#endif - -#ifdef CONFIG_ARCH_LUBBOCK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LUBBOCK -# endif -# define machine_is_lubbock() (machine_arch_type == MACH_TYPE_LUBBOCK) -#else -# define machine_is_lubbock() (0) -#endif - -#ifdef CONFIG_ARCH_ANIKO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANIKO -# endif -# define machine_is_aniko() (machine_arch_type == MACH_TYPE_ANIKO) -#else -# define machine_is_aniko() (0) -#endif - -#ifdef CONFIG_ARCH_CLEP7212 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLEP7212 -# endif -# define machine_is_clep7212() (machine_arch_type == MACH_TYPE_CLEP7212) -#else -# define machine_is_clep7212() (0) -#endif - -#ifdef CONFIG_ARCH_CS89712 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CS89712 -# endif -# define machine_is_cs89712() (machine_arch_type == MACH_TYPE_CS89712) -#else -# define machine_is_cs89712() (0) -#endif - -#ifdef CONFIG_SA1100_WEARARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEARARM -# endif -# define machine_is_weararm() (machine_arch_type == MACH_TYPE_WEARARM) -#else -# define machine_is_weararm() (0) -#endif - -#ifdef CONFIG_SA1100_POSSIO_PX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POSSIO_PX -# endif -# define machine_is_possio_px() (machine_arch_type == MACH_TYPE_POSSIO_PX) -#else -# define machine_is_possio_px() (0) -#endif - -#ifdef CONFIG_SA1100_SIDEARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIDEARM -# endif -# define machine_is_sidearm() (machine_arch_type == MACH_TYPE_SIDEARM) -#else -# define machine_is_sidearm() (0) -#endif - -#ifdef CONFIG_SA1100_STORK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STORK -# endif -# define machine_is_stork() (machine_arch_type == MACH_TYPE_STORK) -#else -# define machine_is_stork() (0) -#endif - -#ifdef CONFIG_SA1100_SHANNON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHANNON -# endif -# define machine_is_shannon() (machine_arch_type == MACH_TYPE_SHANNON) -#else -# define machine_is_shannon() (0) -#endif - -#ifdef CONFIG_ARCH_ACE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACE -# endif -# define machine_is_ace() (machine_arch_type == MACH_TYPE_ACE) -#else -# define machine_is_ace() (0) -#endif - -#ifdef CONFIG_SA1100_BALLYARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BALLYARM -# endif -# define machine_is_ballyarm() (machine_arch_type == MACH_TYPE_BALLYARM) -#else -# define machine_is_ballyarm() (0) -#endif - -#ifdef CONFIG_SA1100_SIMPUTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIMPUTER -# endif -# define machine_is_simputer() (machine_arch_type == MACH_TYPE_SIMPUTER) -#else -# define machine_is_simputer() (0) -#endif - -#ifdef CONFIG_SA1100_NEXTERM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXTERM -# endif -# define machine_is_nexterm() (machine_arch_type == MACH_TYPE_NEXTERM) -#else -# define machine_is_nexterm() (0) -#endif - -#ifdef CONFIG_SA1100_SA1100_ELF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SA1100_ELF -# endif -# define machine_is_sa1100_elf() (machine_arch_type == MACH_TYPE_SA1100_ELF) -#else -# define machine_is_sa1100_elf() (0) -#endif - -#ifdef CONFIG_SA1100_GATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GATOR -# endif -# define machine_is_gator() (machine_arch_type == MACH_TYPE_GATOR) -#else -# define machine_is_gator() (0) -#endif - -#ifdef CONFIG_ARCH_GRANITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRANITE -# endif -# define machine_is_granite() (machine_arch_type == MACH_TYPE_GRANITE) -#else -# define machine_is_granite() (0) -#endif - -#ifdef CONFIG_SA1100_CONSUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CONSUS -# endif -# define machine_is_consus() (machine_arch_type == MACH_TYPE_CONSUS) -#else -# define machine_is_consus() (0) -#endif - -#ifdef CONFIG_ARCH_AAED2000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AAED2000 -# endif -# define machine_is_aaed2000() (machine_arch_type == MACH_TYPE_AAED2000) -#else -# define machine_is_aaed2000() (0) -#endif - -#ifdef CONFIG_ARCH_CDB89712 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CDB89712 -# endif -# define machine_is_cdb89712() (machine_arch_type == MACH_TYPE_CDB89712) -#else -# define machine_is_cdb89712() (0) -#endif - -#ifdef CONFIG_SA1100_GRAPHICSMASTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRAPHICSMASTER -# endif -# define machine_is_graphicsmaster() (machine_arch_type == MACH_TYPE_GRAPHICSMASTER) -#else -# define machine_is_graphicsmaster() (0) -#endif - -#ifdef CONFIG_SA1100_ADSBITSY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSY -# endif -# define machine_is_adsbitsy() (machine_arch_type == MACH_TYPE_ADSBITSY) -#else -# define machine_is_adsbitsy() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_IDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_IDP -# endif -# define machine_is_pxa_idp() (machine_arch_type == MACH_TYPE_PXA_IDP) -#else -# define machine_is_pxa_idp() (0) -#endif - -#ifdef CONFIG_ARCH_PLCE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLCE -# endif -# define machine_is_plce() (machine_arch_type == MACH_TYPE_PLCE) -#else -# define machine_is_plce() (0) -#endif - -#ifdef CONFIG_SA1100_PT_SYSTEM3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PT_SYSTEM3 -# endif -# define machine_is_pt_system3() (machine_arch_type == MACH_TYPE_PT_SYSTEM3) -#else -# define machine_is_pt_system3() (0) -#endif - -#ifdef CONFIG_ARCH_MEDALB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEDALB -# endif -# define machine_is_murphy() (machine_arch_type == MACH_TYPE_MEDALB) -#else -# define machine_is_murphy() (0) -#endif - -#ifdef CONFIG_ARCH_EAGLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EAGLE -# endif -# define machine_is_eagle() (machine_arch_type == MACH_TYPE_EAGLE) -#else -# define machine_is_eagle() (0) -#endif - -#ifdef CONFIG_ARCH_DSC21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSC21 -# endif -# define machine_is_dsc21() (machine_arch_type == MACH_TYPE_DSC21) -#else -# define machine_is_dsc21() (0) -#endif - -#ifdef CONFIG_ARCH_DSC24 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSC24 -# endif -# define machine_is_dsc24() (machine_arch_type == MACH_TYPE_DSC24) -#else -# define machine_is_dsc24() (0) -#endif - -#ifdef CONFIG_ARCH_TI5472 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TI5472 -# endif -# define machine_is_ti5472() (machine_arch_type == MACH_TYPE_TI5472) -#else -# define machine_is_ti5472() (0) -#endif - -#ifdef CONFIG_ARCH_AUTCPU12 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AUTCPU12 -# endif -# define machine_is_autcpu12() (machine_arch_type == MACH_TYPE_AUTCPU12) -#else -# define machine_is_autcpu12() (0) -#endif - -#ifdef CONFIG_ARCH_UENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UENGINE -# endif -# define machine_is_uengine() (machine_arch_type == MACH_TYPE_UENGINE) -#else -# define machine_is_uengine() (0) -#endif - -#ifdef CONFIG_SA1100_BLUESTEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUESTEM -# endif -# define machine_is_bluestem() (machine_arch_type == MACH_TYPE_BLUESTEM) -#else -# define machine_is_bluestem() (0) -#endif - -#ifdef CONFIG_ARCH_XINGU8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XINGU8 -# endif -# define machine_is_xingu8() (machine_arch_type == MACH_TYPE_XINGU8) -#else -# define machine_is_xingu8() (0) -#endif - -#ifdef CONFIG_ARCH_BUSHSTB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUSHSTB -# endif -# define machine_is_bushstb() (machine_arch_type == MACH_TYPE_BUSHSTB) -#else -# define machine_is_bushstb() (0) -#endif - -#ifdef CONFIG_SA1100_EPSILON1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EPSILON1 -# endif -# define machine_is_epsilon1() (machine_arch_type == MACH_TYPE_EPSILON1) -#else -# define machine_is_epsilon1() (0) -#endif - -#ifdef CONFIG_SA1100_BALLOON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BALLOON -# endif -# define machine_is_balloon() (machine_arch_type == MACH_TYPE_BALLOON) -#else -# define machine_is_balloon() (0) -#endif - -#ifdef CONFIG_ARCH_PUPPY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PUPPY -# endif -# define machine_is_puppy() (machine_arch_type == MACH_TYPE_PUPPY) -#else -# define machine_is_puppy() (0) -#endif - -#ifdef CONFIG_SA1100_ELROY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELROY -# endif -# define machine_is_elroy() (machine_arch_type == MACH_TYPE_ELROY) -#else -# define machine_is_elroy() (0) -#endif - -#ifdef CONFIG_ARCH_GMS720 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GMS720 -# endif -# define machine_is_gms720() (machine_arch_type == MACH_TYPE_GMS720) -#else -# define machine_is_gms720() (0) -#endif - -#ifdef CONFIG_ARCH_S24X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S24X -# endif -# define machine_is_s24x() (machine_arch_type == MACH_TYPE_S24X) -#else -# define machine_is_s24x() (0) -#endif - -#ifdef CONFIG_ARCH_JTEL_CLEP7312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JTEL_CLEP7312 -# endif -# define machine_is_jtel_clep7312() (machine_arch_type == MACH_TYPE_JTEL_CLEP7312) -#else -# define machine_is_jtel_clep7312() (0) -#endif - -#ifdef CONFIG_ARCH_CX821XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CX821XX -# endif -# define machine_is_cx821xx() (machine_arch_type == MACH_TYPE_CX821XX) -#else -# define machine_is_cx821xx() (0) -#endif - -#ifdef CONFIG_ARCH_EDB7312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB7312 -# endif -# define machine_is_edb7312() (machine_arch_type == MACH_TYPE_EDB7312) -#else -# define machine_is_edb7312() (0) -#endif - -#ifdef CONFIG_SA1100_BSA1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BSA1110 -# endif -# define machine_is_bsa1110() (machine_arch_type == MACH_TYPE_BSA1110) -#else -# define machine_is_bsa1110() (0) -#endif - -#ifdef CONFIG_ARCH_POWERPIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POWERPIN -# endif -# define machine_is_powerpin() (machine_arch_type == MACH_TYPE_POWERPIN) -#else -# define machine_is_powerpin() (0) -#endif - -#ifdef CONFIG_ARCH_OPENARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENARM -# endif -# define machine_is_openarm() (machine_arch_type == MACH_TYPE_OPENARM) -#else -# define machine_is_openarm() (0) -#endif - -#ifdef CONFIG_SA1100_WHITECHAPEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WHITECHAPEL -# endif -# define machine_is_whitechapel() (machine_arch_type == MACH_TYPE_WHITECHAPEL) -#else -# define machine_is_whitechapel() (0) -#endif - -#ifdef CONFIG_SA1100_H3100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H3100 -# endif -# define machine_is_h3100() (machine_arch_type == MACH_TYPE_H3100) -#else -# define machine_is_h3100() (0) -#endif - -#ifdef CONFIG_SA1100_H3800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H3800 -# endif -# define machine_is_h3800() (machine_arch_type == MACH_TYPE_H3800) -#else -# define machine_is_h3800() (0) -#endif - -#ifdef CONFIG_ARCH_BLUE_V1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUE_V1 -# endif -# define machine_is_blue_v1() (machine_arch_type == MACH_TYPE_BLUE_V1) -#else -# define machine_is_blue_v1() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_CERF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_CERF -# endif -# define machine_is_pxa_cerf() (machine_arch_type == MACH_TYPE_PXA_CERF) -#else -# define machine_is_pxa_cerf() (0) -#endif - -#ifdef CONFIG_ARCH_ARM7TEVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM7TEVB -# endif -# define machine_is_arm7tevb() (machine_arch_type == MACH_TYPE_ARM7TEVB) -#else -# define machine_is_arm7tevb() (0) -#endif - -#ifdef CONFIG_SA1100_D7400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_D7400 -# endif -# define machine_is_d7400() (machine_arch_type == MACH_TYPE_D7400) -#else -# define machine_is_d7400() (0) -#endif - -#ifdef CONFIG_ARCH_PIRANHA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PIRANHA -# endif -# define machine_is_piranha() (machine_arch_type == MACH_TYPE_PIRANHA) -#else -# define machine_is_piranha() (0) -#endif - -#ifdef CONFIG_SA1100_SBCAMELOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBCAMELOT -# endif -# define machine_is_sbcamelot() (machine_arch_type == MACH_TYPE_SBCAMELOT) -#else -# define machine_is_sbcamelot() (0) -#endif - -#ifdef CONFIG_SA1100_KINGS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KINGS -# endif -# define machine_is_kings() (machine_arch_type == MACH_TYPE_KINGS) -#else -# define machine_is_kings() (0) -#endif - -#ifdef CONFIG_ARCH_SMDK2400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2400 -# endif -# define machine_is_smdk2400() (machine_arch_type == MACH_TYPE_SMDK2400) -#else -# define machine_is_smdk2400() (0) -#endif - -#ifdef CONFIG_SA1100_COLLIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLLIE -# endif -# define machine_is_collie() (machine_arch_type == MACH_TYPE_COLLIE) -#else -# define machine_is_collie() (0) -#endif - -#ifdef CONFIG_ARCH_IDR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IDR -# endif -# define machine_is_idr() (machine_arch_type == MACH_TYPE_IDR) -#else -# define machine_is_idr() (0) -#endif - -#ifdef CONFIG_SA1100_BADGE4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BADGE4 -# endif -# define machine_is_badge4() (machine_arch_type == MACH_TYPE_BADGE4) -#else -# define machine_is_badge4() (0) -#endif - -#ifdef CONFIG_ARCH_WEBNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEBNET -# endif -# define machine_is_webnet() (machine_arch_type == MACH_TYPE_WEBNET) -#else -# define machine_is_webnet() (0) -#endif - -#ifdef CONFIG_SA1100_D7300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_D7300 -# endif -# define machine_is_d7300() (machine_arch_type == MACH_TYPE_D7300) -#else -# define machine_is_d7300() (0) -#endif - -#ifdef CONFIG_SA1100_CEP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CEP -# endif -# define machine_is_cep() (machine_arch_type == MACH_TYPE_CEP) -#else -# define machine_is_cep() (0) -#endif - -#ifdef CONFIG_ARCH_FORTUNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FORTUNET -# endif -# define machine_is_fortunet() (machine_arch_type == MACH_TYPE_FORTUNET) -#else -# define machine_is_fortunet() (0) -#endif - -#ifdef CONFIG_ARCH_VC547X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VC547X -# endif -# define machine_is_vc547x() (machine_arch_type == MACH_TYPE_VC547X) -#else -# define machine_is_vc547x() (0) -#endif - -#ifdef CONFIG_SA1100_FILEWALKER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FILEWALKER -# endif -# define machine_is_filewalker() (machine_arch_type == MACH_TYPE_FILEWALKER) -#else -# define machine_is_filewalker() (0) -#endif - -#ifdef CONFIG_SA1100_NETGATEWAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETGATEWAY -# endif -# define machine_is_netgateway() (machine_arch_type == MACH_TYPE_NETGATEWAY) -#else -# define machine_is_netgateway() (0) -#endif - -#ifdef CONFIG_SA1100_SYMBOL2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYMBOL2800 -# endif -# define machine_is_symbol2800() (machine_arch_type == MACH_TYPE_SYMBOL2800) -#else -# define machine_is_symbol2800() (0) -#endif - -#ifdef CONFIG_SA1100_SUNS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUNS -# endif -# define machine_is_suns() (machine_arch_type == MACH_TYPE_SUNS) -#else -# define machine_is_suns() (0) -#endif - -#ifdef CONFIG_SA1100_FRODO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FRODO -# endif -# define machine_is_frodo() (machine_arch_type == MACH_TYPE_FRODO) -#else -# define machine_is_frodo() (0) -#endif - -#ifdef CONFIG_SA1100_MACH_TYTE_MS301 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MACH_TYTE_MS301 -# endif -# define machine_is_ms301() (machine_arch_type == MACH_TYPE_MACH_TYTE_MS301) -#else -# define machine_is_ms301() (0) -#endif - -#ifdef CONFIG_ARCH_MX1ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX1ADS -# endif -# define machine_is_mx1ads() (machine_arch_type == MACH_TYPE_MX1ADS) -#else -# define machine_is_mx1ads() (0) -#endif - -#ifdef CONFIG_ARCH_H7201 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H7201 -# endif -# define machine_is_h7201() (machine_arch_type == MACH_TYPE_H7201) -#else -# define machine_is_h7201() (0) -#endif - -#ifdef CONFIG_ARCH_H7202 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H7202 -# endif -# define machine_is_h7202() (machine_arch_type == MACH_TYPE_H7202) -#else -# define machine_is_h7202() (0) -#endif - -#ifdef CONFIG_ARCH_AMICO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AMICO -# endif -# define machine_is_amico() (machine_arch_type == MACH_TYPE_AMICO) -#else -# define machine_is_amico() (0) -#endif - -#ifdef CONFIG_SA1100_IAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IAM -# endif -# define machine_is_iam() (machine_arch_type == MACH_TYPE_IAM) -#else -# define machine_is_iam() (0) -#endif - -#ifdef CONFIG_SA1100_TT530 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TT530 -# endif -# define machine_is_tt530() (machine_arch_type == MACH_TYPE_TT530) -#else -# define machine_is_tt530() (0) -#endif - -#ifdef CONFIG_ARCH_SAM2400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM2400 -# endif -# define machine_is_sam2400() (machine_arch_type == MACH_TYPE_SAM2400) -#else -# define machine_is_sam2400() (0) -#endif - -#ifdef CONFIG_SA1100_JORNADA56X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JORNADA56X -# endif -# define machine_is_jornada56x() (machine_arch_type == MACH_TYPE_JORNADA56X) -#else -# define machine_is_jornada56x() (0) -#endif - -#ifdef CONFIG_SA1100_ACTIVE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTIVE -# endif -# define machine_is_active() (machine_arch_type == MACH_TYPE_ACTIVE) -#else -# define machine_is_active() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80321 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80321 -# endif -# define machine_is_iq80321() (machine_arch_type == MACH_TYPE_IQ80321) -#else -# define machine_is_iq80321() (0) -#endif - -#ifdef CONFIG_SA1100_WID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WID -# endif -# define machine_is_wid() (machine_arch_type == MACH_TYPE_WID) -#else -# define machine_is_wid() (0) -#endif - -#ifdef CONFIG_ARCH_SABINAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SABINAL -# endif -# define machine_is_sabinal() (machine_arch_type == MACH_TYPE_SABINAL) -#else -# define machine_is_sabinal() (0) -#endif - -#ifdef CONFIG_ARCH_IXP425_MATACUMBE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP425_MATACUMBE -# endif -# define machine_is_ixp425_matacumbe() (machine_arch_type == MACH_TYPE_IXP425_MATACUMBE) -#else -# define machine_is_ixp425_matacumbe() (0) -#endif - -#ifdef CONFIG_SA1100_MINIPRINT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINIPRINT -# endif -# define machine_is_miniprint() (machine_arch_type == MACH_TYPE_MINIPRINT) -#else -# define machine_is_miniprint() (0) -#endif - -#ifdef CONFIG_ARCH_ADM510X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADM510X -# endif -# define machine_is_adm510x() (machine_arch_type == MACH_TYPE_ADM510X) -#else -# define machine_is_adm510x() (0) -#endif - -#ifdef CONFIG_SA1100_SVS200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVS200 -# endif -# define machine_is_svs200() (machine_arch_type == MACH_TYPE_SVS200) -#else -# define machine_is_svs200() (0) -#endif - -#ifdef CONFIG_ARCH_ATG_TCU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATG_TCU -# endif -# define machine_is_atg_tcu() (machine_arch_type == MACH_TYPE_ATG_TCU) -#else -# define machine_is_atg_tcu() (0) -#endif - -#ifdef CONFIG_SA1100_JORNADA820 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JORNADA820 -# endif -# define machine_is_jornada820() (machine_arch_type == MACH_TYPE_JORNADA820) -#else -# define machine_is_jornada820() (0) -#endif - -#ifdef CONFIG_ARCH_S3C44B0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C44B0 -# endif -# define machine_is_s3c44b0() (machine_arch_type == MACH_TYPE_S3C44B0) -#else -# define machine_is_s3c44b0() (0) -#endif - -#ifdef CONFIG_ARCH_MARGIS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARGIS2 -# endif -# define machine_is_margis2() (machine_arch_type == MACH_TYPE_MARGIS2) -#else -# define machine_is_margis2() (0) -#endif - -#ifdef CONFIG_ARCH_KS8695 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KS8695 -# endif -# define machine_is_ks8695() (machine_arch_type == MACH_TYPE_KS8695) -#else -# define machine_is_ks8695() (0) -#endif - -#ifdef CONFIG_ARCH_BRH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRH -# endif -# define machine_is_brh() (machine_arch_type == MACH_TYPE_BRH) -#else -# define machine_is_brh() (0) -#endif - -#ifdef CONFIG_ARCH_S3C2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2410 -# endif -# define machine_is_s3c2410() (machine_arch_type == MACH_TYPE_S3C2410) -#else -# define machine_is_s3c2410() (0) -#endif - -#ifdef CONFIG_ARCH_POSSIO_PX30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POSSIO_PX30 -# endif -# define machine_is_possio_px30() (machine_arch_type == MACH_TYPE_POSSIO_PX30) -#else -# define machine_is_possio_px30() (0) -#endif - -#ifdef CONFIG_ARCH_S3C2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2800 -# endif -# define machine_is_s3c2800() (machine_arch_type == MACH_TYPE_S3C2800) -#else -# define machine_is_s3c2800() (0) -#endif - -#ifdef CONFIG_SA1100_FLEETWOOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLEETWOOD -# endif -# define machine_is_fleetwood() (machine_arch_type == MACH_TYPE_FLEETWOOD) -#else -# define machine_is_fleetwood() (0) -#endif - -#ifdef CONFIG_ARCH_OMAHA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAHA -# endif -# define machine_is_omaha() (machine_arch_type == MACH_TYPE_OMAHA) -#else -# define machine_is_omaha() (0) -#endif - -#ifdef CONFIG_ARCH_TA7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TA7 -# endif -# define machine_is_ta7() (machine_arch_type == MACH_TYPE_TA7) -#else -# define machine_is_ta7() (0) -#endif - -#ifdef CONFIG_SA1100_NOVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOVA -# endif -# define machine_is_nova() (machine_arch_type == MACH_TYPE_NOVA) -#else -# define machine_is_nova() (0) -#endif - -#ifdef CONFIG_ARCH_HMK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HMK -# endif -# define machine_is_hmk() (machine_arch_type == MACH_TYPE_HMK) -#else -# define machine_is_hmk() (0) -#endif - -#ifdef CONFIG_ARCH_KARO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KARO -# endif -# define machine_is_karo() (machine_arch_type == MACH_TYPE_KARO) -#else -# define machine_is_karo() (0) -#endif - -#ifdef CONFIG_SA1100_FESTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FESTER -# endif -# define machine_is_fester() (machine_arch_type == MACH_TYPE_FESTER) -#else -# define machine_is_fester() (0) -#endif - -#ifdef CONFIG_ARCH_GPI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GPI -# endif -# define machine_is_gpi() (machine_arch_type == MACH_TYPE_GPI) -#else -# define machine_is_gpi() (0) -#endif - -#ifdef CONFIG_ARCH_SMDK2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2410 -# endif -# define machine_is_smdk2410() (machine_arch_type == MACH_TYPE_SMDK2410) -#else -# define machine_is_smdk2410() (0) -#endif - -#ifdef CONFIG_ARCH_I519 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I519 -# endif -# define machine_is_i519() (machine_arch_type == MACH_TYPE_I519) -#else -# define machine_is_i519() (0) -#endif - -#ifdef CONFIG_SA1100_NEXIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXIO -# endif -# define machine_is_nexio() (machine_arch_type == MACH_TYPE_NEXIO) -#else -# define machine_is_nexio() (0) -#endif - -#ifdef CONFIG_SA1100_BITBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BITBOX -# endif -# define machine_is_bitbox() (machine_arch_type == MACH_TYPE_BITBOX) -#else -# define machine_is_bitbox() (0) -#endif - -#ifdef CONFIG_SA1100_G200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G200 -# endif -# define machine_is_g200() (machine_arch_type == MACH_TYPE_G200) -#else -# define machine_is_g200() (0) -#endif - -#ifdef CONFIG_SA1100_GILL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GILL -# endif -# define machine_is_gill() (machine_arch_type == MACH_TYPE_GILL) -#else -# define machine_is_gill() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_MERCURY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_MERCURY -# endif -# define machine_is_pxa_mercury() (machine_arch_type == MACH_TYPE_PXA_MERCURY) -#else -# define machine_is_pxa_mercury() (0) -#endif - -#ifdef CONFIG_ARCH_CEIVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CEIVA -# endif -# define machine_is_ceiva() (machine_arch_type == MACH_TYPE_CEIVA) -#else -# define machine_is_ceiva() (0) -#endif - -#ifdef CONFIG_SA1100_FRET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FRET -# endif -# define machine_is_fret() (machine_arch_type == MACH_TYPE_FRET) -#else -# define machine_is_fret() (0) -#endif - -#ifdef CONFIG_SA1100_EMAILPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMAILPHONE -# endif -# define machine_is_emailphone() (machine_arch_type == MACH_TYPE_EMAILPHONE) -#else -# define machine_is_emailphone() (0) -#endif - -#ifdef CONFIG_ARCH_H3900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H3900 -# endif -# define machine_is_h3900() (machine_arch_type == MACH_TYPE_H3900) -#else -# define machine_is_h3900() (0) -#endif - -#ifdef CONFIG_ARCH_PXA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA1 -# endif -# define machine_is_pxa1() (machine_arch_type == MACH_TYPE_PXA1) -#else -# define machine_is_pxa1() (0) -#endif - -#ifdef CONFIG_SA1100_KOAN369 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KOAN369 -# endif -# define machine_is_koan369() (machine_arch_type == MACH_TYPE_KOAN369) -#else -# define machine_is_koan369() (0) -#endif - -#ifdef CONFIG_ARCH_COGENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COGENT -# endif -# define machine_is_cogent() (machine_arch_type == MACH_TYPE_COGENT) -#else -# define machine_is_cogent() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_SIMPUTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SIMPUTER -# endif -# define machine_is_esl_simputer() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER) -#else -# define machine_is_esl_simputer() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_SIMPUTER_CLR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SIMPUTER_CLR -# endif -# define machine_is_esl_simputer_clr() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER_CLR) -#else -# define machine_is_esl_simputer_clr() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_SIMPUTER_BW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SIMPUTER_BW -# endif -# define machine_is_esl_simputer_bw() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER_BW) -#else -# define machine_is_esl_simputer_bw() (0) -#endif - -#ifdef CONFIG_ARCH_HHP_CRADLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HHP_CRADLE -# endif -# define machine_is_hhp_cradle() (machine_arch_type == MACH_TYPE_HHP_CRADLE) -#else -# define machine_is_hhp_cradle() (0) -#endif - -#ifdef CONFIG_ARCH_HE500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HE500 -# endif -# define machine_is_he500() (machine_arch_type == MACH_TYPE_HE500) -#else -# define machine_is_he500() (0) -#endif - -#ifdef CONFIG_SA1100_INHANDELF2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHANDELF2 -# endif -# define machine_is_inhandelf2() (machine_arch_type == MACH_TYPE_INHANDELF2) -#else -# define machine_is_inhandelf2() (0) -#endif - -#ifdef CONFIG_SA1100_INHANDFTIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHANDFTIP -# endif -# define machine_is_inhandftip() (machine_arch_type == MACH_TYPE_INHANDFTIP) -#else -# define machine_is_inhandftip() (0) -#endif - -#ifdef CONFIG_SA1100_DNP1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DNP1110 -# endif -# define machine_is_dnp1110() (machine_arch_type == MACH_TYPE_DNP1110) -#else -# define machine_is_dnp1110() (0) -#endif - -#ifdef CONFIG_SA1100_PNP1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNP1110 -# endif -# define machine_is_pnp1110() (machine_arch_type == MACH_TYPE_PNP1110) -#else -# define machine_is_pnp1110() (0) -#endif - -#ifdef CONFIG_ARCH_CSB226 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB226 -# endif -# define machine_is_csb226() (machine_arch_type == MACH_TYPE_CSB226) -#else -# define machine_is_csb226() (0) -#endif - -#ifdef CONFIG_SA1100_ARNOLD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARNOLD -# endif -# define machine_is_arnold() (machine_arch_type == MACH_TYPE_ARNOLD) -#else -# define machine_is_arnold() (0) -#endif - -#ifdef CONFIG_MACH_VOICEBLUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VOICEBLUE -# endif -# define machine_is_voiceblue() (machine_arch_type == MACH_TYPE_VOICEBLUE) -#else -# define machine_is_voiceblue() (0) -#endif - -#ifdef CONFIG_ARCH_JZ8028 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JZ8028 -# endif -# define machine_is_jz8028() (machine_arch_type == MACH_TYPE_JZ8028) -#else -# define machine_is_jz8028() (0) -#endif - -#ifdef CONFIG_ARCH_H5400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H5400 -# endif -# define machine_is_h5400() (machine_arch_type == MACH_TYPE_H5400) -#else -# define machine_is_h5400() (0) -#endif - -#ifdef CONFIG_SA1100_FORTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FORTE -# endif -# define machine_is_forte() (machine_arch_type == MACH_TYPE_FORTE) -#else -# define machine_is_forte() (0) -#endif - -#ifdef CONFIG_SA1100_ACAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACAM -# endif -# define machine_is_acam() (machine_arch_type == MACH_TYPE_ACAM) -#else -# define machine_is_acam() (0) -#endif - -#ifdef CONFIG_SA1100_ABOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ABOX -# endif -# define machine_is_abox() (machine_arch_type == MACH_TYPE_ABOX) -#else -# define machine_is_abox() (0) -#endif - -#ifdef CONFIG_ARCH_ATMEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATMEL -# endif -# define machine_is_atmel() (machine_arch_type == MACH_TYPE_ATMEL) -#else -# define machine_is_atmel() (0) -#endif - -#ifdef CONFIG_ARCH_SITSANG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SITSANG -# endif -# define machine_is_sitsang() (machine_arch_type == MACH_TYPE_SITSANG) -#else -# define machine_is_sitsang() (0) -#endif - -#ifdef CONFIG_SA1100_CPU1110LCDNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPU1110LCDNET -# endif -# define machine_is_cpu1110lcdnet() (machine_arch_type == MACH_TYPE_CPU1110LCDNET) -#else -# define machine_is_cpu1110lcdnet() (0) -#endif - -#ifdef CONFIG_ARCH_MPL_VCMA9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPL_VCMA9 -# endif -# define machine_is_mpl_vcma9() (machine_arch_type == MACH_TYPE_MPL_VCMA9) -#else -# define machine_is_mpl_vcma9() (0) -#endif - -#ifdef CONFIG_ARCH_OPUS_A1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPUS_A1 -# endif -# define machine_is_opus_a1() (machine_arch_type == MACH_TYPE_OPUS_A1) -#else -# define machine_is_opus_a1() (0) -#endif - -#ifdef CONFIG_ARCH_DAYTONA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAYTONA -# endif -# define machine_is_daytona() (machine_arch_type == MACH_TYPE_DAYTONA) -#else -# define machine_is_daytona() (0) -#endif - -#ifdef CONFIG_SA1100_KILLBEAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KILLBEAR -# endif -# define machine_is_killbear() (machine_arch_type == MACH_TYPE_KILLBEAR) -#else -# define machine_is_killbear() (0) -#endif - -#ifdef CONFIG_ARCH_YOHO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YOHO -# endif -# define machine_is_yoho() (machine_arch_type == MACH_TYPE_YOHO) -#else -# define machine_is_yoho() (0) -#endif - -#ifdef CONFIG_ARCH_JASPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JASPER -# endif -# define machine_is_jasper() (machine_arch_type == MACH_TYPE_JASPER) -#else -# define machine_is_jasper() (0) -#endif - -#ifdef CONFIG_ARCH_DSC25 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSC25 -# endif -# define machine_is_dsc25() (machine_arch_type == MACH_TYPE_DSC25) -#else -# define machine_is_dsc25() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_INNOVATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_INNOVATOR -# endif -# define machine_is_omap_innovator() (machine_arch_type == MACH_TYPE_OMAP_INNOVATOR) -#else -# define machine_is_omap_innovator() (0) -#endif - -#ifdef CONFIG_ARCH_RAMSES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAMSES -# endif -# define machine_is_mnci() (machine_arch_type == MACH_TYPE_RAMSES) -#else -# define machine_is_mnci() (0) -#endif - -#ifdef CONFIG_ARCH_S28X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S28X -# endif -# define machine_is_s28x() (machine_arch_type == MACH_TYPE_S28X) -#else -# define machine_is_s28x() (0) -#endif - -#ifdef CONFIG_ARCH_MPORT3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPORT3 -# endif -# define machine_is_mport3() (machine_arch_type == MACH_TYPE_MPORT3) -#else -# define machine_is_mport3() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_EAGLE250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_EAGLE250 -# endif -# define machine_is_pxa_eagle250() (machine_arch_type == MACH_TYPE_PXA_EAGLE250) -#else -# define machine_is_pxa_eagle250() (0) -#endif - -#ifdef CONFIG_ARCH_PDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PDB -# endif -# define machine_is_pdb() (machine_arch_type == MACH_TYPE_PDB) -#else -# define machine_is_pdb() (0) -#endif - -#ifdef CONFIG_SA1100_BLUE_2G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUE_2G -# endif -# define machine_is_blue_2g() (machine_arch_type == MACH_TYPE_BLUE_2G) -#else -# define machine_is_blue_2g() (0) -#endif - -#ifdef CONFIG_SA1100_BLUEARCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUEARCH -# endif -# define machine_is_bluearch() (machine_arch_type == MACH_TYPE_BLUEARCH) -#else -# define machine_is_bluearch() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2400 -# endif -# define machine_is_ixdp2400() (machine_arch_type == MACH_TYPE_IXDP2400) -#else -# define machine_is_ixdp2400() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2800 -# endif -# define machine_is_ixdp2800() (machine_arch_type == MACH_TYPE_IXDP2800) -#else -# define machine_is_ixdp2800() (0) -#endif - -#ifdef CONFIG_SA1100_EXPLORER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXPLORER -# endif -# define machine_is_explorer() (machine_arch_type == MACH_TYPE_EXPLORER) -#else -# define machine_is_explorer() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP425 -# endif -# define machine_is_ixdp425() (machine_arch_type == MACH_TYPE_IXDP425) -#else -# define machine_is_ixdp425() (0) -#endif - -#ifdef CONFIG_ARCH_CHIMP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHIMP -# endif -# define machine_is_chimp() (machine_arch_type == MACH_TYPE_CHIMP) -#else -# define machine_is_chimp() (0) -#endif - -#ifdef CONFIG_ARCH_STORK_NEST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STORK_NEST -# endif -# define machine_is_stork_nest() (machine_arch_type == MACH_TYPE_STORK_NEST) -#else -# define machine_is_stork_nest() (0) -#endif - -#ifdef CONFIG_ARCH_STORK_EGG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STORK_EGG -# endif -# define machine_is_stork_egg() (machine_arch_type == MACH_TYPE_STORK_EGG) -#else -# define machine_is_stork_egg() (0) -#endif - -#ifdef CONFIG_SA1100_WISMO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WISMO -# endif -# define machine_is_wismo() (machine_arch_type == MACH_TYPE_WISMO) -#else -# define machine_is_wismo() (0) -#endif - -#ifdef CONFIG_ARCH_EZLINX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZLINX -# endif -# define machine_is_ezlinx() (machine_arch_type == MACH_TYPE_EZLINX) -#else -# define machine_is_ezlinx() (0) -#endif - -#ifdef CONFIG_ARCH_AT91RM9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200 -# endif -# define machine_is_at91rm9200() (machine_arch_type == MACH_TYPE_AT91RM9200) -#else -# define machine_is_at91rm9200() (0) -#endif - -#ifdef CONFIG_ARCH_ADTECH_ORION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADTECH_ORION -# endif -# define machine_is_adtech_orion() (machine_arch_type == MACH_TYPE_ADTECH_ORION) -#else -# define machine_is_adtech_orion() (0) -#endif - -#ifdef CONFIG_ARCH_NEPTUNE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEPTUNE -# endif -# define machine_is_neptune() (machine_arch_type == MACH_TYPE_NEPTUNE) -#else -# define machine_is_neptune() (0) -#endif - -#ifdef CONFIG_SA1100_HACKKIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HACKKIT -# endif -# define machine_is_hackkit() (machine_arch_type == MACH_TYPE_HACKKIT) -#else -# define machine_is_hackkit() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_WINS30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_WINS30 -# endif -# define machine_is_pxa_wins30() (machine_arch_type == MACH_TYPE_PXA_WINS30) -#else -# define machine_is_pxa_wins30() (0) -#endif - -#ifdef CONFIG_SA1100_LAVINNA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LAVINNA -# endif -# define machine_is_lavinna() (machine_arch_type == MACH_TYPE_LAVINNA) -#else -# define machine_is_lavinna() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_UENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_UENGINE -# endif -# define machine_is_pxa_uengine() (machine_arch_type == MACH_TYPE_PXA_UENGINE) -#else -# define machine_is_pxa_uengine() (0) -#endif - -#ifdef CONFIG_ARCH_INNOKOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INNOKOM -# endif -# define machine_is_innokom() (machine_arch_type == MACH_TYPE_INNOKOM) -#else -# define machine_is_innokom() (0) -#endif - -#ifdef CONFIG_ARCH_BMS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BMS -# endif -# define machine_is_bms() (machine_arch_type == MACH_TYPE_BMS) -#else -# define machine_is_bms() (0) -#endif - -#ifdef CONFIG_ARCH_IXCDP1100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXCDP1100 -# endif -# define machine_is_ixcdp1100() (machine_arch_type == MACH_TYPE_IXCDP1100) -#else -# define machine_is_ixcdp1100() (0) -#endif - -#ifdef CONFIG_ARCH_PRPMC1100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRPMC1100 -# endif -# define machine_is_prpmc1100() (machine_arch_type == MACH_TYPE_PRPMC1100) -#else -# define machine_is_prpmc1100() (0) -#endif - -#ifdef CONFIG_ARCH_AT91RM9200DK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200DK -# endif -# define machine_is_at91rm9200dk() (machine_arch_type == MACH_TYPE_AT91RM9200DK) -#else -# define machine_is_at91rm9200dk() (0) -#endif - -#ifdef CONFIG_ARCH_ARMSTICK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMSTICK -# endif -# define machine_is_armstick() (machine_arch_type == MACH_TYPE_ARMSTICK) -#else -# define machine_is_armstick() (0) -#endif - -#ifdef CONFIG_ARCH_ARMONIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMONIE -# endif -# define machine_is_armonie() (machine_arch_type == MACH_TYPE_ARMONIE) -#else -# define machine_is_armonie() (0) -#endif - -#ifdef CONFIG_ARCH_MPORT1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPORT1 -# endif -# define machine_is_mport1() (machine_arch_type == MACH_TYPE_MPORT1) -#else -# define machine_is_mport1() (0) -#endif - -#ifdef CONFIG_ARCH_S3C5410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C5410 -# endif -# define machine_is_s3c5410() (machine_arch_type == MACH_TYPE_S3C5410) -#else -# define machine_is_s3c5410() (0) -#endif - -#ifdef CONFIG_ARCH_ZCP320A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZCP320A -# endif -# define machine_is_zcp320a() (machine_arch_type == MACH_TYPE_ZCP320A) -#else -# define machine_is_zcp320a() (0) -#endif - -#ifdef CONFIG_ARCH_I_BOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I_BOX -# endif -# define machine_is_i_box() (machine_arch_type == MACH_TYPE_I_BOX) -#else -# define machine_is_i_box() (0) -#endif - -#ifdef CONFIG_ARCH_STLC1502 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STLC1502 -# endif -# define machine_is_stlc1502() (machine_arch_type == MACH_TYPE_STLC1502) -#else -# define machine_is_stlc1502() (0) -#endif - -#ifdef CONFIG_ARCH_SIREN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIREN -# endif -# define machine_is_siren() (machine_arch_type == MACH_TYPE_SIREN) -#else -# define machine_is_siren() (0) -#endif - -#ifdef CONFIG_ARCH_GREENLAKE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GREENLAKE -# endif -# define machine_is_greenlake() (machine_arch_type == MACH_TYPE_GREENLAKE) -#else -# define machine_is_greenlake() (0) -#endif - -#ifdef CONFIG_ARCH_ARGUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARGUS -# endif -# define machine_is_argus() (machine_arch_type == MACH_TYPE_ARGUS) -#else -# define machine_is_argus() (0) -#endif - -#ifdef CONFIG_SA1100_COMBADGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMBADGE -# endif -# define machine_is_combadge() (machine_arch_type == MACH_TYPE_COMBADGE) -#else -# define machine_is_combadge() (0) -#endif - -#ifdef CONFIG_ARCH_ROKEPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROKEPXA -# endif -# define machine_is_rokepxa() (machine_arch_type == MACH_TYPE_ROKEPXA) -#else -# define machine_is_rokepxa() (0) -#endif - -#ifdef CONFIG_ARCH_CINTEGRATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CINTEGRATOR -# endif -# define machine_is_cintegrator() (machine_arch_type == MACH_TYPE_CINTEGRATOR) -#else -# define machine_is_cintegrator() (0) -#endif - -#ifdef CONFIG_ARCH_GUIDEA07 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GUIDEA07 -# endif -# define machine_is_guidea07() (machine_arch_type == MACH_TYPE_GUIDEA07) -#else -# define machine_is_guidea07() (0) -#endif - -#ifdef CONFIG_ARCH_TAT257 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAT257 -# endif -# define machine_is_tat257() (machine_arch_type == MACH_TYPE_TAT257) -#else -# define machine_is_tat257() (0) -#endif - -#ifdef CONFIG_ARCH_IGP2425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IGP2425 -# endif -# define machine_is_igp2425() (machine_arch_type == MACH_TYPE_IGP2425) -#else -# define machine_is_igp2425() (0) -#endif - -#ifdef CONFIG_ARCH_BLUEGRAMMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUEGRAMMA -# endif -# define machine_is_bluegrama() (machine_arch_type == MACH_TYPE_BLUEGRAMMA) -#else -# define machine_is_bluegrama() (0) -#endif - -#ifdef CONFIG_ARCH_IPOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPOD -# endif -# define machine_is_ipod() (machine_arch_type == MACH_TYPE_IPOD) -#else -# define machine_is_ipod() (0) -#endif - -#ifdef CONFIG_ARCH_ADSBITSYX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSYX -# endif -# define machine_is_adsbitsyx() (machine_arch_type == MACH_TYPE_ADSBITSYX) -#else -# define machine_is_adsbitsyx() (0) -#endif - -#ifdef CONFIG_ARCH_TRIZEPS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS2 -# endif -# define machine_is_trizeps2() (machine_arch_type == MACH_TYPE_TRIZEPS2) -#else -# define machine_is_trizeps2() (0) -#endif - -#ifdef CONFIG_ARCH_VIPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VIPER -# endif -# define machine_is_viper() (machine_arch_type == MACH_TYPE_VIPER) -#else -# define machine_is_viper() (0) -#endif - -#ifdef CONFIG_SA1100_ADSBITSYPLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSYPLUS -# endif -# define machine_is_adsbitsyplus() (machine_arch_type == MACH_TYPE_ADSBITSYPLUS) -#else -# define machine_is_adsbitsyplus() (0) -#endif - -#ifdef CONFIG_SA1100_ADSAGC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSAGC -# endif -# define machine_is_adsagc() (machine_arch_type == MACH_TYPE_ADSAGC) -#else -# define machine_is_adsagc() (0) -#endif - -#ifdef CONFIG_ARCH_STP7312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STP7312 -# endif -# define machine_is_stp7312() (machine_arch_type == MACH_TYPE_STP7312) -#else -# define machine_is_stp7312() (0) -#endif - -#ifdef CONFIG_MACH_NX_PHNX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NX_PHNX -# endif -# define machine_is_nx_phnx() (machine_arch_type == MACH_TYPE_NX_PHNX) -#else -# define machine_is_nx_phnx() (0) -#endif - -#ifdef CONFIG_ARCH_WEP_EP250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEP_EP250 -# endif -# define machine_is_wep_ep250() (machine_arch_type == MACH_TYPE_WEP_EP250) -#else -# define machine_is_wep_ep250() (0) -#endif - -#ifdef CONFIG_ARCH_INHANDELF3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHANDELF3 -# endif -# define machine_is_inhandelf3() (machine_arch_type == MACH_TYPE_INHANDELF3) -#else -# define machine_is_inhandelf3() (0) -#endif - -#ifdef CONFIG_ARCH_ADI_COYOTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADI_COYOTE -# endif -# define machine_is_adi_coyote() (machine_arch_type == MACH_TYPE_ADI_COYOTE) -#else -# define machine_is_adi_coyote() (0) -#endif - -#ifdef CONFIG_ARCH_IYONIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IYONIX -# endif -# define machine_is_iyonix() (machine_arch_type == MACH_TYPE_IYONIX) -#else -# define machine_is_iyonix() (0) -#endif - -#ifdef CONFIG_ARCH_DAMICAM_SA1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAMICAM_SA1110 -# endif -# define machine_is_damicam1() (machine_arch_type == MACH_TYPE_DAMICAM_SA1110) -#else -# define machine_is_damicam1() (0) -#endif - -#ifdef CONFIG_ARCH_MEG03 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEG03 -# endif -# define machine_is_meg03() (machine_arch_type == MACH_TYPE_MEG03) -#else -# define machine_is_meg03() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_WHITECHAPEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_WHITECHAPEL -# endif -# define machine_is_pxa_whitechapel() (machine_arch_type == MACH_TYPE_PXA_WHITECHAPEL) -#else -# define machine_is_pxa_whitechapel() (0) -#endif - -#ifdef CONFIG_ARCH_NWSC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NWSC -# endif -# define machine_is_nwsc() (machine_arch_type == MACH_TYPE_NWSC) -#else -# define machine_is_nwsc() (0) -#endif - -#ifdef CONFIG_ARCH_NWLARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NWLARM -# endif -# define machine_is_nwlarm() (machine_arch_type == MACH_TYPE_NWLARM) -#else -# define machine_is_nwlarm() (0) -#endif - -#ifdef CONFIG_ARCH_IXP425_MGUARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP425_MGUARD -# endif -# define machine_is_ixp425_mguard() (machine_arch_type == MACH_TYPE_IXP425_MGUARD) -#else -# define machine_is_ixp425_mguard() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_NETDCU4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_NETDCU4 -# endif -# define machine_is_pxa_netdcu4() (machine_arch_type == MACH_TYPE_PXA_NETDCU4) -#else -# define machine_is_pxa_netdcu4() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2401 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2401 -# endif -# define machine_is_ixdp2401() (machine_arch_type == MACH_TYPE_IXDP2401) -#else -# define machine_is_ixdp2401() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2801 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2801 -# endif -# define machine_is_ixdp2801() (machine_arch_type == MACH_TYPE_IXDP2801) -#else -# define machine_is_ixdp2801() (0) -#endif - -#ifdef CONFIG_ARCH_ZODIAC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZODIAC -# endif -# define machine_is_zodiac() (machine_arch_type == MACH_TYPE_ZODIAC) -#else -# define machine_is_zodiac() (0) -#endif - -#ifdef CONFIG_ARCH_ARMMODUL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMMODUL -# endif -# define machine_is_armmodul() (machine_arch_type == MACH_TYPE_ARMMODUL) -#else -# define machine_is_armmodul() (0) -#endif - -#ifdef CONFIG_SA1100_KETOP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KETOP -# endif -# define machine_is_ketop() (machine_arch_type == MACH_TYPE_KETOP) -#else -# define machine_is_ketop() (0) -#endif - -#ifdef CONFIG_ARCH_AV7200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AV7200 -# endif -# define machine_is_av7200() (machine_arch_type == MACH_TYPE_AV7200) -#else -# define machine_is_av7200() (0) -#endif - -#ifdef CONFIG_ARCH_ARCH_TI925 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCH_TI925 -# endif -# define machine_is_arch_ti925() (machine_arch_type == MACH_TYPE_ARCH_TI925) -#else -# define machine_is_arch_ti925() (0) -#endif - -#ifdef CONFIG_ARCH_ACQ200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACQ200 -# endif -# define machine_is_acq200() (machine_arch_type == MACH_TYPE_ACQ200) -#else -# define machine_is_acq200() (0) -#endif - -#ifdef CONFIG_SA1100_PT_DAFIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PT_DAFIT -# endif -# define machine_is_pt_dafit() (machine_arch_type == MACH_TYPE_PT_DAFIT) -#else -# define machine_is_pt_dafit() (0) -#endif - -#ifdef CONFIG_ARCH_IHBA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IHBA -# endif -# define machine_is_ihba() (machine_arch_type == MACH_TYPE_IHBA) -#else -# define machine_is_ihba() (0) -#endif - -#ifdef CONFIG_ARCH_QUINQUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUINQUE -# endif -# define machine_is_quinque() (machine_arch_type == MACH_TYPE_QUINQUE) -#else -# define machine_is_quinque() (0) -#endif - -#ifdef CONFIG_ARCH_NIMBRAONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIMBRAONE -# endif -# define machine_is_nimbraone() (machine_arch_type == MACH_TYPE_NIMBRAONE) -#else -# define machine_is_nimbraone() (0) -#endif - -#ifdef CONFIG_ARCH_NIMBRA29X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIMBRA29X -# endif -# define machine_is_nimbra29x() (machine_arch_type == MACH_TYPE_NIMBRA29X) -#else -# define machine_is_nimbra29x() (0) -#endif - -#ifdef CONFIG_ARCH_NIMBRA210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIMBRA210 -# endif -# define machine_is_nimbra210() (machine_arch_type == MACH_TYPE_NIMBRA210) -#else -# define machine_is_nimbra210() (0) -#endif - -#ifdef CONFIG_ARCH_HHP_D95XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HHP_D95XX -# endif -# define machine_is_hhp_d95xx() (machine_arch_type == MACH_TYPE_HHP_D95XX) -#else -# define machine_is_hhp_d95xx() (0) -#endif - -#ifdef CONFIG_ARCH_LABARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LABARM -# endif -# define machine_is_labarm() (machine_arch_type == MACH_TYPE_LABARM) -#else -# define machine_is_labarm() (0) -#endif - -#ifdef CONFIG_ARCH_M825XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M825XX -# endif -# define machine_is_m825xx() (machine_arch_type == MACH_TYPE_M825XX) -#else -# define machine_is_m825xx() (0) -#endif - -#ifdef CONFIG_SA1100_M7100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M7100 -# endif -# define machine_is_m7100() (machine_arch_type == MACH_TYPE_M7100) -#else -# define machine_is_m7100() (0) -#endif - -#ifdef CONFIG_ARCH_NIPC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIPC2 -# endif -# define machine_is_nipc2() (machine_arch_type == MACH_TYPE_NIPC2) -#else -# define machine_is_nipc2() (0) -#endif - -#ifdef CONFIG_ARCH_FU7202 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FU7202 -# endif -# define machine_is_fu7202() (machine_arch_type == MACH_TYPE_FU7202) -#else -# define machine_is_fu7202() (0) -#endif - -#ifdef CONFIG_ARCH_ADSAGX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSAGX -# endif -# define machine_is_adsagx() (machine_arch_type == MACH_TYPE_ADSAGX) -#else -# define machine_is_adsagx() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_POOH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_POOH -# endif -# define machine_is_pxa_pooh() (machine_arch_type == MACH_TYPE_PXA_POOH) -#else -# define machine_is_pxa_pooh() (0) -#endif - -#ifdef CONFIG_ARCH_BANDON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BANDON -# endif -# define machine_is_bandon() (machine_arch_type == MACH_TYPE_BANDON) -#else -# define machine_is_bandon() (0) -#endif - -#ifdef CONFIG_ARCH_PCM7210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM7210 -# endif -# define machine_is_pcm7210() (machine_arch_type == MACH_TYPE_PCM7210) -#else -# define machine_is_pcm7210() (0) -#endif - -#ifdef CONFIG_ARCH_NMS9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NMS9200 -# endif -# define machine_is_nms9200() (machine_arch_type == MACH_TYPE_NMS9200) -#else -# define machine_is_nms9200() (0) -#endif - -#ifdef CONFIG_ARCH_LOGODL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOGODL -# endif -# define machine_is_logodl() (machine_arch_type == MACH_TYPE_LOGODL) -#else -# define machine_is_logodl() (0) -#endif - -#ifdef CONFIG_SA1100_M7140 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M7140 -# endif -# define machine_is_m7140() (machine_arch_type == MACH_TYPE_M7140) -#else -# define machine_is_m7140() (0) -#endif - -#ifdef CONFIG_ARCH_KOREBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KOREBOT -# endif -# define machine_is_korebot() (machine_arch_type == MACH_TYPE_KOREBOT) -#else -# define machine_is_korebot() (0) -#endif - -#ifdef CONFIG_ARCH_IQ31244 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ31244 -# endif -# define machine_is_iq31244() (machine_arch_type == MACH_TYPE_IQ31244) -#else -# define machine_is_iq31244() (0) -#endif - -#ifdef CONFIG_SA1100_KOAN393 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KOAN393 -# endif -# define machine_is_koan393() (machine_arch_type == MACH_TYPE_KOAN393) -#else -# define machine_is_koan393() (0) -#endif - -#ifdef CONFIG_ARCH_INHANDFTIP3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHANDFTIP3 -# endif -# define machine_is_inhandftip3() (machine_arch_type == MACH_TYPE_INHANDFTIP3) -#else -# define machine_is_inhandftip3() (0) -#endif - -#ifdef CONFIG_ARCH_GONZO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GONZO -# endif -# define machine_is_gonzo() (machine_arch_type == MACH_TYPE_GONZO) -#else -# define machine_is_gonzo() (0) -#endif - -#ifdef CONFIG_ARCH_BAST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BAST -# endif -# define machine_is_bast() (machine_arch_type == MACH_TYPE_BAST) -#else -# define machine_is_bast() (0) -#endif - -#ifdef CONFIG_ARCH_SCANPASS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCANPASS -# endif -# define machine_is_scanpass() (machine_arch_type == MACH_TYPE_SCANPASS) -#else -# define machine_is_scanpass() (0) -#endif - -#ifdef CONFIG_ARCH_EP7312_POOH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EP7312_POOH -# endif -# define machine_is_ep7312_pooh() (machine_arch_type == MACH_TYPE_EP7312_POOH) -#else -# define machine_is_ep7312_pooh() (0) -#endif - -#ifdef CONFIG_ARCH_TA7S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TA7S -# endif -# define machine_is_ta7s() (machine_arch_type == MACH_TYPE_TA7S) -#else -# define machine_is_ta7s() (0) -#endif - -#ifdef CONFIG_ARCH_TA7V -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TA7V -# endif -# define machine_is_ta7v() (machine_arch_type == MACH_TYPE_TA7V) -#else -# define machine_is_ta7v() (0) -#endif - -#ifdef CONFIG_SA1100_ICARUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICARUS -# endif -# define machine_is_icarus() (machine_arch_type == MACH_TYPE_ICARUS) -#else -# define machine_is_icarus() (0) -#endif - -#ifdef CONFIG_ARCH_H1900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H1900 -# endif -# define machine_is_h1900() (machine_arch_type == MACH_TYPE_H1900) -#else -# define machine_is_h1900() (0) -#endif - -#ifdef CONFIG_SA1100_GEMINI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEMINI -# endif -# define machine_is_gemini() (machine_arch_type == MACH_TYPE_GEMINI) -#else -# define machine_is_gemini() (0) -#endif - -#ifdef CONFIG_ARCH_AXIM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXIM -# endif -# define machine_is_axim() (machine_arch_type == MACH_TYPE_AXIM) -#else -# define machine_is_axim() (0) -#endif - -#ifdef CONFIG_ARCH_AUDIOTRON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AUDIOTRON -# endif -# define machine_is_audiotron() (machine_arch_type == MACH_TYPE_AUDIOTRON) -#else -# define machine_is_audiotron() (0) -#endif - -#ifdef CONFIG_ARCH_H2200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H2200 -# endif -# define machine_is_h2200() (machine_arch_type == MACH_TYPE_H2200) -#else -# define machine_is_h2200() (0) -#endif - -#ifdef CONFIG_ARCH_LOOX600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOX600 -# endif -# define machine_is_loox600() (machine_arch_type == MACH_TYPE_LOOX600) -#else -# define machine_is_loox600() (0) -#endif - -#ifdef CONFIG_ARCH_NIOP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIOP -# endif -# define machine_is_niop() (machine_arch_type == MACH_TYPE_NIOP) -#else -# define machine_is_niop() (0) -#endif - -#ifdef CONFIG_ARCH_DM310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM310 -# endif -# define machine_is_dm310() (machine_arch_type == MACH_TYPE_DM310) -#else -# define machine_is_dm310() (0) -#endif - -#ifdef CONFIG_ARCH_SEEDPXA_C2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SEEDPXA_C2 -# endif -# define machine_is_seedpxa_c2() (machine_arch_type == MACH_TYPE_SEEDPXA_C2) -#else -# define machine_is_seedpxa_c2() (0) -#endif - -#ifdef CONFIG_ARCH_IXP4XX_MGUARD_PCI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP4XX_MGUARD_PCI -# endif -# define machine_is_ixp4xx_mguardpci() (machine_arch_type == MACH_TYPE_IXP4XX_MGUARD_PCI) -#else -# define machine_is_ixp4xx_mguardpci() (0) -#endif - -#ifdef CONFIG_ARCH_H1940 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H1940 -# endif -# define machine_is_h1940() (machine_arch_type == MACH_TYPE_H1940) -#else -# define machine_is_h1940() (0) -#endif - -#ifdef CONFIG_ARCH_SCORPIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCORPIO -# endif -# define machine_is_scorpio() (machine_arch_type == MACH_TYPE_SCORPIO) -#else -# define machine_is_scorpio() (0) -#endif - -#ifdef CONFIG_ARCH_VIVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VIVA -# endif -# define machine_is_viva() (machine_arch_type == MACH_TYPE_VIVA) -#else -# define machine_is_viva() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_XCARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_XCARD -# endif -# define machine_is_pxa_xcard() (machine_arch_type == MACH_TYPE_PXA_XCARD) -#else -# define machine_is_pxa_xcard() (0) -#endif - -#ifdef CONFIG_ARCH_CSB335 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB335 -# endif -# define machine_is_csb335() (machine_arch_type == MACH_TYPE_CSB335) -#else -# define machine_is_csb335() (0) -#endif - -#ifdef CONFIG_ARCH_IXRD425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXRD425 -# endif -# define machine_is_ixrd425() (machine_arch_type == MACH_TYPE_IXRD425) -#else -# define machine_is_ixrd425() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80315 -# endif -# define machine_is_iq80315() (machine_arch_type == MACH_TYPE_IQ80315) -#else -# define machine_is_iq80315() (0) -#endif - -#ifdef CONFIG_ARCH_NMP7312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NMP7312 -# endif -# define machine_is_nmp7312() (machine_arch_type == MACH_TYPE_NMP7312) -#else -# define machine_is_nmp7312() (0) -#endif - -#ifdef CONFIG_ARCH_CX861XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CX861XX -# endif -# define machine_is_cx861xx() (machine_arch_type == MACH_TYPE_CX861XX) -#else -# define machine_is_cx861xx() (0) -#endif - -#ifdef CONFIG_ARCH_ENP2611 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENP2611 -# endif -# define machine_is_enp2611() (machine_arch_type == MACH_TYPE_ENP2611) -#else -# define machine_is_enp2611() (0) -#endif - -#ifdef CONFIG_SA1100_XDA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XDA -# endif -# define machine_is_xda() (machine_arch_type == MACH_TYPE_XDA) -#else -# define machine_is_xda() (0) -#endif - -#ifdef CONFIG_ARCH_CSIR_IMS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSIR_IMS -# endif -# define machine_is_csir_ims() (machine_arch_type == MACH_TYPE_CSIR_IMS) -#else -# define machine_is_csir_ims() (0) -#endif - -#ifdef CONFIG_ARCH_IXP421_DNAEETH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP421_DNAEETH -# endif -# define machine_is_ixp421_dnaeeth() (machine_arch_type == MACH_TYPE_IXP421_DNAEETH) -#else -# define machine_is_ixp421_dnaeeth() (0) -#endif - -#ifdef CONFIG_ARCH_POCKETSERV9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POCKETSERV9200 -# endif -# define machine_is_pocketserv9200() (machine_arch_type == MACH_TYPE_POCKETSERV9200) -#else -# define machine_is_pocketserv9200() (0) -#endif - -#ifdef CONFIG_ARCH_TOTO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOTO -# endif -# define machine_is_toto() (machine_arch_type == MACH_TYPE_TOTO) -#else -# define machine_is_toto() (0) -#endif - -#ifdef CONFIG_ARCH_S3C2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2440 -# endif -# define machine_is_s3c2440() (machine_arch_type == MACH_TYPE_S3C2440) -#else -# define machine_is_s3c2440() (0) -#endif - -#ifdef CONFIG_ARCH_KS8695P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KS8695P -# endif -# define machine_is_ks8695p() (machine_arch_type == MACH_TYPE_KS8695P) -#else -# define machine_is_ks8695p() (0) -#endif - -#ifdef CONFIG_ARCH_SE4000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE4000 -# endif -# define machine_is_se4000() (machine_arch_type == MACH_TYPE_SE4000) -#else -# define machine_is_se4000() (0) -#endif - -#ifdef CONFIG_ARCH_QUADRICEPS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUADRICEPS -# endif -# define machine_is_quadriceps() (machine_arch_type == MACH_TYPE_QUADRICEPS) -#else -# define machine_is_quadriceps() (0) -#endif - -#ifdef CONFIG_ARCH_BRONCO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRONCO -# endif -# define machine_is_bronco() (machine_arch_type == MACH_TYPE_BRONCO) -#else -# define machine_is_bronco() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_WIRELESS_TAB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_WIRELESS_TAB -# endif -# define machine_is_esl_wireless_tab() (machine_arch_type == MACH_TYPE_ESL_WIRELESS_TAB) -#else -# define machine_is_esl_wireless_tab() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_SOFCOMP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SOFCOMP -# endif -# define machine_is_esl_sofcomp() (machine_arch_type == MACH_TYPE_ESL_SOFCOMP) -#else -# define machine_is_esl_sofcomp() (0) -#endif - -#ifdef CONFIG_ARCH_S5C7375 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5C7375 -# endif -# define machine_is_s5c7375() (machine_arch_type == MACH_TYPE_S5C7375) -#else -# define machine_is_s5c7375() (0) -#endif - -#ifdef CONFIG_ARCH_SPEARHEAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEARHEAD -# endif -# define machine_is_spearhead() (machine_arch_type == MACH_TYPE_SPEARHEAD) -#else -# define machine_is_spearhead() (0) -#endif - -#ifdef CONFIG_ARCH_PANTERA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PANTERA -# endif -# define machine_is_pantera() (machine_arch_type == MACH_TYPE_PANTERA) -#else -# define machine_is_pantera() (0) -#endif - -#ifdef CONFIG_ARCH_PRAYOGLITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRAYOGLITE -# endif -# define machine_is_prayoglite() (machine_arch_type == MACH_TYPE_PRAYOGLITE) -#else -# define machine_is_prayoglite() (0) -#endif - -#ifdef CONFIG_ARCH_GUMSTIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GUMSTIX -# endif -# define machine_is_gumstix() (machine_arch_type == MACH_TYPE_GUMSTIX) -#else -# define machine_is_gumstix() (0) -#endif - -#ifdef CONFIG_ARCH_RCUBE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RCUBE -# endif -# define machine_is_rcube() (machine_arch_type == MACH_TYPE_RCUBE) -#else -# define machine_is_rcube() (0) -#endif - -#ifdef CONFIG_ARCH_REA_OLV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REA_OLV -# endif -# define machine_is_rea_olv() (machine_arch_type == MACH_TYPE_REA_OLV) -#else -# define machine_is_rea_olv() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_IPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_IPHONE -# endif -# define machine_is_pxa_iphone() (machine_arch_type == MACH_TYPE_PXA_IPHONE) -#else -# define machine_is_pxa_iphone() (0) -#endif - -#ifdef CONFIG_ARCH_S3C3410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C3410 -# endif -# define machine_is_s3c3410() (machine_arch_type == MACH_TYPE_S3C3410) -#else -# define machine_is_s3c3410() (0) -#endif - -#ifdef CONFIG_ARCH_ESPD_4510B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESPD_4510B -# endif -# define machine_is_espd_4510b() (machine_arch_type == MACH_TYPE_ESPD_4510B) -#else -# define machine_is_espd_4510b() (0) -#endif - -#ifdef CONFIG_ARCH_MP1X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MP1X -# endif -# define machine_is_mp1x() (machine_arch_type == MACH_TYPE_MP1X) -#else -# define machine_is_mp1x() (0) -#endif - -#ifdef CONFIG_ARCH_AT91RM9200TB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200TB -# endif -# define machine_is_at91rm9200tb() (machine_arch_type == MACH_TYPE_AT91RM9200TB) -#else -# define machine_is_at91rm9200tb() (0) -#endif - -#ifdef CONFIG_ARCH_ADSVGX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSVGX -# endif -# define machine_is_adsvgx() (machine_arch_type == MACH_TYPE_ADSVGX) -#else -# define machine_is_adsvgx() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_H2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_H2 -# endif -# define machine_is_omap_h2() (machine_arch_type == MACH_TYPE_OMAP_H2) -#else -# define machine_is_omap_h2() (0) -#endif - -#ifdef CONFIG_ARCH_PELEE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELEE -# endif -# define machine_is_pelee() (machine_arch_type == MACH_TYPE_PELEE) -#else -# define machine_is_pelee() (0) -#endif - -#ifdef CONFIG_MACH_E740 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E740 -# endif -# define machine_is_e740() (machine_arch_type == MACH_TYPE_E740) -#else -# define machine_is_e740() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80331 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80331 -# endif -# define machine_is_iq80331() (machine_arch_type == MACH_TYPE_IQ80331) -#else -# define machine_is_iq80331() (0) -#endif - -#ifdef CONFIG_ARCH_VERSATILE_PB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VERSATILE_PB -# endif -# define machine_is_versatile_pb() (machine_arch_type == MACH_TYPE_VERSATILE_PB) -#else -# define machine_is_versatile_pb() (0) -#endif - -#ifdef CONFIG_MACH_KEV7A400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KEV7A400 -# endif -# define machine_is_kev7a400() (machine_arch_type == MACH_TYPE_KEV7A400) -#else -# define machine_is_kev7a400() (0) -#endif - -#ifdef CONFIG_MACH_LPD7A400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD7A400 -# endif -# define machine_is_lpd7a400() (machine_arch_type == MACH_TYPE_LPD7A400) -#else -# define machine_is_lpd7a400() (0) -#endif - -#ifdef CONFIG_MACH_LPD7A404 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD7A404 -# endif -# define machine_is_lpd7a404() (machine_arch_type == MACH_TYPE_LPD7A404) -#else -# define machine_is_lpd7a404() (0) -#endif - -#ifdef CONFIG_ARCH_FUJITSU_CAMELOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FUJITSU_CAMELOT -# endif -# define machine_is_fujitsu_camelot() (machine_arch_type == MACH_TYPE_FUJITSU_CAMELOT) -#else -# define machine_is_fujitsu_camelot() (0) -#endif - -#ifdef CONFIG_ARCH_JANUS2M -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JANUS2M -# endif -# define machine_is_janus2m() (machine_arch_type == MACH_TYPE_JANUS2M) -#else -# define machine_is_janus2m() (0) -#endif - -#ifdef CONFIG_MACH_EMBTF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMBTF -# endif -# define machine_is_embtf() (machine_arch_type == MACH_TYPE_EMBTF) -#else -# define machine_is_embtf() (0) -#endif - -#ifdef CONFIG_MACH_HPM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HPM -# endif -# define machine_is_hpm() (machine_arch_type == MACH_TYPE_HPM) -#else -# define machine_is_hpm() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2410TK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2410TK -# endif -# define machine_is_smdk2410tk() (machine_arch_type == MACH_TYPE_SMDK2410TK) -#else -# define machine_is_smdk2410tk() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2410AJ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2410AJ -# endif -# define machine_is_smdk2410aj() (machine_arch_type == MACH_TYPE_SMDK2410AJ) -#else -# define machine_is_smdk2410aj() (0) -#endif - -#ifdef CONFIG_MACH_STREETRACER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STREETRACER -# endif -# define machine_is_streetracer() (machine_arch_type == MACH_TYPE_STREETRACER) -#else -# define machine_is_streetracer() (0) -#endif - -#ifdef CONFIG_MACH_EFRAME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EFRAME -# endif -# define machine_is_eframe() (machine_arch_type == MACH_TYPE_EFRAME) -#else -# define machine_is_eframe() (0) -#endif - -#ifdef CONFIG_MACH_CSB337 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB337 -# endif -# define machine_is_csb337() (machine_arch_type == MACH_TYPE_CSB337) -#else -# define machine_is_csb337() (0) -#endif - -#ifdef CONFIG_MACH_PXA_LARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_LARK -# endif -# define machine_is_pxa_lark() (machine_arch_type == MACH_TYPE_PXA_LARK) -#else -# define machine_is_pxa_lark() (0) -#endif - -#ifdef CONFIG_MACH_PNP2110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNP2110 -# endif -# define machine_is_pxa_pnp2110() (machine_arch_type == MACH_TYPE_PNP2110) -#else -# define machine_is_pxa_pnp2110() (0) -#endif - -#ifdef CONFIG_MACH_TCC72X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TCC72X -# endif -# define machine_is_tcc72x() (machine_arch_type == MACH_TYPE_TCC72X) -#else -# define machine_is_tcc72x() (0) -#endif - -#ifdef CONFIG_MACH_ALTAIR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALTAIR -# endif -# define machine_is_altair() (machine_arch_type == MACH_TYPE_ALTAIR) -#else -# define machine_is_altair() (0) -#endif - -#ifdef CONFIG_MACH_KC3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KC3 -# endif -# define machine_is_kc3() (machine_arch_type == MACH_TYPE_KC3) -#else -# define machine_is_kc3() (0) -#endif - -#ifdef CONFIG_MACH_SINTEFTD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SINTEFTD -# endif -# define machine_is_sinteftd() (machine_arch_type == MACH_TYPE_SINTEFTD) -#else -# define machine_is_sinteftd() (0) -#endif - -#ifdef CONFIG_MACH_MAINSTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAINSTONE -# endif -# define machine_is_mainstone() (machine_arch_type == MACH_TYPE_MAINSTONE) -#else -# define machine_is_mainstone() (0) -#endif - -#ifdef CONFIG_MACH_ADAY4X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADAY4X -# endif -# define machine_is_aday4x() (machine_arch_type == MACH_TYPE_ADAY4X) -#else -# define machine_is_aday4x() (0) -#endif - -#ifdef CONFIG_MACH_LITE300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LITE300 -# endif -# define machine_is_lite300() (machine_arch_type == MACH_TYPE_LITE300) -#else -# define machine_is_lite300() (0) -#endif - -#ifdef CONFIG_MACH_S5C7376 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5C7376 -# endif -# define machine_is_s5c7376() (machine_arch_type == MACH_TYPE_S5C7376) -#else -# define machine_is_s5c7376() (0) -#endif - -#ifdef CONFIG_MACH_MT02 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MT02 -# endif -# define machine_is_mt02() (machine_arch_type == MACH_TYPE_MT02) -#else -# define machine_is_mt02() (0) -#endif - -#ifdef CONFIG_MACH_MPORT3S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPORT3S -# endif -# define machine_is_mport3s() (machine_arch_type == MACH_TYPE_MPORT3S) -#else -# define machine_is_mport3s() (0) -#endif - -#ifdef CONFIG_MACH_RA_ALPHA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RA_ALPHA -# endif -# define machine_is_ra_alpha() (machine_arch_type == MACH_TYPE_RA_ALPHA) -#else -# define machine_is_ra_alpha() (0) -#endif - -#ifdef CONFIG_MACH_XCEP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XCEP -# endif -# define machine_is_xcep() (machine_arch_type == MACH_TYPE_XCEP) -#else -# define machine_is_xcep() (0) -#endif - -#ifdef CONFIG_MACH_ARCOM_VULCAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCOM_VULCAN -# endif -# define machine_is_arcom_vulcan() (machine_arch_type == MACH_TYPE_ARCOM_VULCAN) -#else -# define machine_is_arcom_vulcan() (0) -#endif - -#ifdef CONFIG_MACH_STARGATE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STARGATE -# endif -# define machine_is_stargate() (machine_arch_type == MACH_TYPE_STARGATE) -#else -# define machine_is_stargate() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLOJ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLOJ -# endif -# define machine_is_armadilloj() (machine_arch_type == MACH_TYPE_ARMADILLOJ) -#else -# define machine_is_armadilloj() (0) -#endif - -#ifdef CONFIG_MACH_ELROY_JACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELROY_JACK -# endif -# define machine_is_elroy_jack() (machine_arch_type == MACH_TYPE_ELROY_JACK) -#else -# define machine_is_elroy_jack() (0) -#endif - -#ifdef CONFIG_MACH_BACKEND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BACKEND -# endif -# define machine_is_backend() (machine_arch_type == MACH_TYPE_BACKEND) -#else -# define machine_is_backend() (0) -#endif - -#ifdef CONFIG_MACH_S5LINBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5LINBOX -# endif -# define machine_is_s5linbox() (machine_arch_type == MACH_TYPE_S5LINBOX) -#else -# define machine_is_s5linbox() (0) -#endif - -#ifdef CONFIG_MACH_NOMADIK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOMADIK -# endif -# define machine_is_nomadik() (machine_arch_type == MACH_TYPE_NOMADIK) -#else -# define machine_is_nomadik() (0) -#endif - -#ifdef CONFIG_MACH_IA_CPU_9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IA_CPU_9200 -# endif -# define machine_is_ia_cpu_9200() (machine_arch_type == MACH_TYPE_IA_CPU_9200) -#else -# define machine_is_ia_cpu_9200() (0) -#endif - -#ifdef CONFIG_MACH_AT91_BJA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91_BJA1 -# endif -# define machine_is_at91_bja1() (machine_arch_type == MACH_TYPE_AT91_BJA1) -#else -# define machine_is_at91_bja1() (0) -#endif - -#ifdef CONFIG_MACH_CORGI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORGI -# endif -# define machine_is_corgi() (machine_arch_type == MACH_TYPE_CORGI) -#else -# define machine_is_corgi() (0) -#endif - -#ifdef CONFIG_MACH_POODLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POODLE -# endif -# define machine_is_poodle() (machine_arch_type == MACH_TYPE_POODLE) -#else -# define machine_is_poodle() (0) -#endif - -#ifdef CONFIG_MACH_TEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEN -# endif -# define machine_is_ten() (machine_arch_type == MACH_TYPE_TEN) -#else -# define machine_is_ten() (0) -#endif - -#ifdef CONFIG_MACH_ROVERP5P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERP5P -# endif -# define machine_is_roverp5p() (machine_arch_type == MACH_TYPE_ROVERP5P) -#else -# define machine_is_roverp5p() (0) -#endif - -#ifdef CONFIG_MACH_SC2700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SC2700 -# endif -# define machine_is_sc2700() (machine_arch_type == MACH_TYPE_SC2700) -#else -# define machine_is_sc2700() (0) -#endif - -#ifdef CONFIG_MACH_EX_EAGLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EX_EAGLE -# endif -# define machine_is_ex_eagle() (machine_arch_type == MACH_TYPE_EX_EAGLE) -#else -# define machine_is_ex_eagle() (0) -#endif - -#ifdef CONFIG_MACH_NX_PXA12 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NX_PXA12 -# endif -# define machine_is_nx_pxa12() (machine_arch_type == MACH_TYPE_NX_PXA12) -#else -# define machine_is_nx_pxa12() (0) -#endif - -#ifdef CONFIG_MACH_NX_PXA5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NX_PXA5 -# endif -# define machine_is_nx_pxa5() (machine_arch_type == MACH_TYPE_NX_PXA5) -#else -# define machine_is_nx_pxa5() (0) -#endif - -#ifdef CONFIG_MACH_BLACKBOARD2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLACKBOARD2 -# endif -# define machine_is_blackboard2() (machine_arch_type == MACH_TYPE_BLACKBOARD2) -#else -# define machine_is_blackboard2() (0) -#endif - -#ifdef CONFIG_MACH_I819 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I819 -# endif -# define machine_is_i819() (machine_arch_type == MACH_TYPE_I819) -#else -# define machine_is_i819() (0) -#endif - -#ifdef CONFIG_MACH_IXMB995E -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXMB995E -# endif -# define machine_is_ixmb995e() (machine_arch_type == MACH_TYPE_IXMB995E) -#else -# define machine_is_ixmb995e() (0) -#endif - -#ifdef CONFIG_MACH_SKYRIDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SKYRIDER -# endif -# define machine_is_skyrider() (machine_arch_type == MACH_TYPE_SKYRIDER) -#else -# define machine_is_skyrider() (0) -#endif - -#ifdef CONFIG_MACH_SKYHAWK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SKYHAWK -# endif -# define machine_is_skyhawk() (machine_arch_type == MACH_TYPE_SKYHAWK) -#else -# define machine_is_skyhawk() (0) -#endif - -#ifdef CONFIG_MACH_ENTERPRISE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENTERPRISE -# endif -# define machine_is_enterprise() (machine_arch_type == MACH_TYPE_ENTERPRISE) -#else -# define machine_is_enterprise() (0) -#endif - -#ifdef CONFIG_MACH_DEP2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEP2410 -# endif -# define machine_is_dep2410() (machine_arch_type == MACH_TYPE_DEP2410) -#else -# define machine_is_dep2410() (0) -#endif - -#ifdef CONFIG_MACH_ARMCORE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMCORE -# endif -# define machine_is_armcore() (machine_arch_type == MACH_TYPE_ARMCORE) -#else -# define machine_is_armcore() (0) -#endif - -#ifdef CONFIG_MACH_HOBBIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HOBBIT -# endif -# define machine_is_hobbit() (machine_arch_type == MACH_TYPE_HOBBIT) -#else -# define machine_is_hobbit() (0) -#endif - -#ifdef CONFIG_MACH_H7210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H7210 -# endif -# define machine_is_h7210() (machine_arch_type == MACH_TYPE_H7210) -#else -# define machine_is_h7210() (0) -#endif - -#ifdef CONFIG_MACH_PXA_NETDCU5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_NETDCU5 -# endif -# define machine_is_pxa_netdcu5() (machine_arch_type == MACH_TYPE_PXA_NETDCU5) -#else -# define machine_is_pxa_netdcu5() (0) -#endif - -#ifdef CONFIG_MACH_ACC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACC -# endif -# define machine_is_acc() (machine_arch_type == MACH_TYPE_ACC) -#else -# define machine_is_acc() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA -# endif -# define machine_is_esl_sarva() (machine_arch_type == MACH_TYPE_ESL_SARVA) -#else -# define machine_is_esl_sarva() (0) -#endif - -#ifdef CONFIG_MACH_XM250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XM250 -# endif -# define machine_is_xm250() (machine_arch_type == MACH_TYPE_XM250) -#else -# define machine_is_xm250() (0) -#endif - -#ifdef CONFIG_MACH_T6TC1XB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T6TC1XB -# endif -# define machine_is_t6tc1xb() (machine_arch_type == MACH_TYPE_T6TC1XB) -#else -# define machine_is_t6tc1xb() (0) -#endif - -#ifdef CONFIG_MACH_ESS710 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESS710 -# endif -# define machine_is_ess710() (machine_arch_type == MACH_TYPE_ESS710) -#else -# define machine_is_ess710() (0) -#endif - -#ifdef CONFIG_MACH_MX31ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31ADS -# endif -# define machine_is_mx31ads() (machine_arch_type == MACH_TYPE_MX31ADS) -#else -# define machine_is_mx31ads() (0) -#endif - -#ifdef CONFIG_MACH_HIMALAYA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIMALAYA -# endif -# define machine_is_himalaya() (machine_arch_type == MACH_TYPE_HIMALAYA) -#else -# define machine_is_himalaya() (0) -#endif - -#ifdef CONFIG_MACH_BOLFENK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BOLFENK -# endif -# define machine_is_bolfenk() (machine_arch_type == MACH_TYPE_BOLFENK) -#else -# define machine_is_bolfenk() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200KR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200KR -# endif -# define machine_is_at91rm9200kr() (machine_arch_type == MACH_TYPE_AT91RM9200KR) -#else -# define machine_is_at91rm9200kr() (0) -#endif - -#ifdef CONFIG_MACH_EDB9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9312 -# endif -# define machine_is_edb9312() (machine_arch_type == MACH_TYPE_EDB9312) -#else -# define machine_is_edb9312() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_GENERIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_GENERIC -# endif -# define machine_is_omap_generic() (machine_arch_type == MACH_TYPE_OMAP_GENERIC) -#else -# define machine_is_omap_generic() (0) -#endif - -#ifdef CONFIG_MACH_AXIMX3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXIMX3 -# endif -# define machine_is_aximx3() (machine_arch_type == MACH_TYPE_AXIMX3) -#else -# define machine_is_aximx3() (0) -#endif - -#ifdef CONFIG_MACH_EB67XDIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EB67XDIP -# endif -# define machine_is_eb67xdip() (machine_arch_type == MACH_TYPE_EB67XDIP) -#else -# define machine_is_eb67xdip() (0) -#endif - -#ifdef CONFIG_MACH_WEBTXS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEBTXS -# endif -# define machine_is_webtxs() (machine_arch_type == MACH_TYPE_WEBTXS) -#else -# define machine_is_webtxs() (0) -#endif - -#ifdef CONFIG_MACH_HAWK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HAWK -# endif -# define machine_is_hawk() (machine_arch_type == MACH_TYPE_HAWK) -#else -# define machine_is_hawk() (0) -#endif - -#ifdef CONFIG_MACH_CCAT91SBC001 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCAT91SBC001 -# endif -# define machine_is_ccat91sbc001() (machine_arch_type == MACH_TYPE_CCAT91SBC001) -#else -# define machine_is_ccat91sbc001() (0) -#endif - -#ifdef CONFIG_MACH_EXPRESSO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXPRESSO -# endif -# define machine_is_expresso() (machine_arch_type == MACH_TYPE_EXPRESSO) -#else -# define machine_is_expresso() (0) -#endif - -#ifdef CONFIG_MACH_H4000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H4000 -# endif -# define machine_is_h4000() (machine_arch_type == MACH_TYPE_H4000) -#else -# define machine_is_h4000() (0) -#endif - -#ifdef CONFIG_MACH_DINO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DINO -# endif -# define machine_is_dino() (machine_arch_type == MACH_TYPE_DINO) -#else -# define machine_is_dino() (0) -#endif - -#ifdef CONFIG_MACH_ML675K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ML675K -# endif -# define machine_is_ml675k() (machine_arch_type == MACH_TYPE_ML675K) -#else -# define machine_is_ml675k() (0) -#endif - -#ifdef CONFIG_MACH_EDB9301 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9301 -# endif -# define machine_is_edb9301() (machine_arch_type == MACH_TYPE_EDB9301) -#else -# define machine_is_edb9301() (0) -#endif - -#ifdef CONFIG_MACH_EDB9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9315 -# endif -# define machine_is_edb9315() (machine_arch_type == MACH_TYPE_EDB9315) -#else -# define machine_is_edb9315() (0) -#endif - -#ifdef CONFIG_MACH_RECIVA_TT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RECIVA_TT -# endif -# define machine_is_reciva_tt() (machine_arch_type == MACH_TYPE_RECIVA_TT) -#else -# define machine_is_reciva_tt() (0) -#endif - -#ifdef CONFIG_MACH_CSTCB01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSTCB01 -# endif -# define machine_is_cstcb01() (machine_arch_type == MACH_TYPE_CSTCB01) -#else -# define machine_is_cstcb01() (0) -#endif - -#ifdef CONFIG_MACH_CSTCB1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSTCB1 -# endif -# define machine_is_cstcb1() (machine_arch_type == MACH_TYPE_CSTCB1) -#else -# define machine_is_cstcb1() (0) -#endif - -#ifdef CONFIG_MACH_SHADWELL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHADWELL -# endif -# define machine_is_shadwell() (machine_arch_type == MACH_TYPE_SHADWELL) -#else -# define machine_is_shadwell() (0) -#endif - -#ifdef CONFIG_MACH_GOEPEL263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GOEPEL263 -# endif -# define machine_is_goepel263() (machine_arch_type == MACH_TYPE_GOEPEL263) -#else -# define machine_is_goepel263() (0) -#endif - -#ifdef CONFIG_MACH_ACQ100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACQ100 -# endif -# define machine_is_acq100() (machine_arch_type == MACH_TYPE_ACQ100) -#else -# define machine_is_acq100() (0) -#endif - -#ifdef CONFIG_MACH_MX1FS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX1FS2 -# endif -# define machine_is_mx1fs2() (machine_arch_type == MACH_TYPE_MX1FS2) -#else -# define machine_is_mx1fs2() (0) -#endif - -#ifdef CONFIG_MACH_HIPTOP_G1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIPTOP_G1 -# endif -# define machine_is_hiptop_g1() (machine_arch_type == MACH_TYPE_HIPTOP_G1) -#else -# define machine_is_hiptop_g1() (0) -#endif - -#ifdef CONFIG_MACH_SPARKY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPARKY -# endif -# define machine_is_sparky() (machine_arch_type == MACH_TYPE_SPARKY) -#else -# define machine_is_sparky() (0) -#endif - -#ifdef CONFIG_MACH_NS9750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NS9750 -# endif -# define machine_is_ns9750() (machine_arch_type == MACH_TYPE_NS9750) -#else -# define machine_is_ns9750() (0) -#endif - -#ifdef CONFIG_MACH_PHOENIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHOENIX -# endif -# define machine_is_phoenix() (machine_arch_type == MACH_TYPE_PHOENIX) -#else -# define machine_is_phoenix() (0) -#endif - -#ifdef CONFIG_MACH_VR1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VR1000 -# endif -# define machine_is_vr1000() (machine_arch_type == MACH_TYPE_VR1000) -#else -# define machine_is_vr1000() (0) -#endif - -#ifdef CONFIG_MACH_DEISTERPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEISTERPXA -# endif -# define machine_is_deisterpxa() (machine_arch_type == MACH_TYPE_DEISTERPXA) -#else -# define machine_is_deisterpxa() (0) -#endif - -#ifdef CONFIG_MACH_BCM1160 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCM1160 -# endif -# define machine_is_bcm1160() (machine_arch_type == MACH_TYPE_BCM1160) -#else -# define machine_is_bcm1160() (0) -#endif - -#ifdef CONFIG_MACH_PCM022 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM022 -# endif -# define machine_is_pcm022() (machine_arch_type == MACH_TYPE_PCM022) -#else -# define machine_is_pcm022() (0) -#endif - -#ifdef CONFIG_MACH_ADSGCX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSGCX -# endif -# define machine_is_adsgcx() (machine_arch_type == MACH_TYPE_ADSGCX) -#else -# define machine_is_adsgcx() (0) -#endif - -#ifdef CONFIG_MACH_DREADNAUGHT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DREADNAUGHT -# endif -# define machine_is_dreadnaught() (machine_arch_type == MACH_TYPE_DREADNAUGHT) -#else -# define machine_is_dreadnaught() (0) -#endif - -#ifdef CONFIG_MACH_DM320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM320 -# endif -# define machine_is_dm320() (machine_arch_type == MACH_TYPE_DM320) -#else -# define machine_is_dm320() (0) -#endif - -#ifdef CONFIG_MACH_MARKOV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARKOV -# endif -# define machine_is_markov() (machine_arch_type == MACH_TYPE_MARKOV) -#else -# define machine_is_markov() (0) -#endif - -#ifdef CONFIG_MACH_COS7A400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COS7A400 -# endif -# define machine_is_cos7a400() (machine_arch_type == MACH_TYPE_COS7A400) -#else -# define machine_is_cos7a400() (0) -#endif - -#ifdef CONFIG_MACH_MILANO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MILANO -# endif -# define machine_is_milano() (machine_arch_type == MACH_TYPE_MILANO) -#else -# define machine_is_milano() (0) -#endif - -#ifdef CONFIG_MACH_UE9328 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UE9328 -# endif -# define machine_is_ue9328() (machine_arch_type == MACH_TYPE_UE9328) -#else -# define machine_is_ue9328() (0) -#endif - -#ifdef CONFIG_MACH_UEX255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UEX255 -# endif -# define machine_is_uex255() (machine_arch_type == MACH_TYPE_UEX255) -#else -# define machine_is_uex255() (0) -#endif - -#ifdef CONFIG_MACH_UE2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UE2410 -# endif -# define machine_is_ue2410() (machine_arch_type == MACH_TYPE_UE2410) -#else -# define machine_is_ue2410() (0) -#endif - -#ifdef CONFIG_MACH_A620 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A620 -# endif -# define machine_is_a620() (machine_arch_type == MACH_TYPE_A620) -#else -# define machine_is_a620() (0) -#endif - -#ifdef CONFIG_MACH_OCELOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCELOT -# endif -# define machine_is_ocelot() (machine_arch_type == MACH_TYPE_OCELOT) -#else -# define machine_is_ocelot() (0) -#endif - -#ifdef CONFIG_MACH_CHEETAH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHEETAH -# endif -# define machine_is_cheetah() (machine_arch_type == MACH_TYPE_CHEETAH) -#else -# define machine_is_cheetah() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PERSEUS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PERSEUS2 -# endif -# define machine_is_omap_perseus2() (machine_arch_type == MACH_TYPE_OMAP_PERSEUS2) -#else -# define machine_is_omap_perseus2() (0) -#endif - -#ifdef CONFIG_MACH_ZVUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZVUE -# endif -# define machine_is_zvue() (machine_arch_type == MACH_TYPE_ZVUE) -#else -# define machine_is_zvue() (0) -#endif - -#ifdef CONFIG_MACH_ROVERP1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERP1 -# endif -# define machine_is_roverp1() (machine_arch_type == MACH_TYPE_ROVERP1) -#else -# define machine_is_roverp1() (0) -#endif - -#ifdef CONFIG_MACH_ASIDIAL2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASIDIAL2 -# endif -# define machine_is_asidial2() (machine_arch_type == MACH_TYPE_ASIDIAL2) -#else -# define machine_is_asidial2() (0) -#endif - -#ifdef CONFIG_MACH_S3C24A0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C24A0 -# endif -# define machine_is_s3c24a0() (machine_arch_type == MACH_TYPE_S3C24A0) -#else -# define machine_is_s3c24a0() (0) -#endif - -#ifdef CONFIG_MACH_E800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E800 -# endif -# define machine_is_e800() (machine_arch_type == MACH_TYPE_E800) -#else -# define machine_is_e800() (0) -#endif - -#ifdef CONFIG_MACH_E750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E750 -# endif -# define machine_is_e750() (machine_arch_type == MACH_TYPE_E750) -#else -# define machine_is_e750() (0) -#endif - -#ifdef CONFIG_MACH_S3C5500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C5500 -# endif -# define machine_is_s3c5500() (machine_arch_type == MACH_TYPE_S3C5500) -#else -# define machine_is_s3c5500() (0) -#endif - -#ifdef CONFIG_MACH_SMDK5500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK5500 -# endif -# define machine_is_smdk5500() (machine_arch_type == MACH_TYPE_SMDK5500) -#else -# define machine_is_smdk5500() (0) -#endif - -#ifdef CONFIG_MACH_SIGNALSYNC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIGNALSYNC -# endif -# define machine_is_signalsync() (machine_arch_type == MACH_TYPE_SIGNALSYNC) -#else -# define machine_is_signalsync() (0) -#endif - -#ifdef CONFIG_MACH_NBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NBC -# endif -# define machine_is_nbc() (machine_arch_type == MACH_TYPE_NBC) -#else -# define machine_is_nbc() (0) -#endif - -#ifdef CONFIG_MACH_KODIAK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KODIAK -# endif -# define machine_is_kodiak() (machine_arch_type == MACH_TYPE_KODIAK) -#else -# define machine_is_kodiak() (0) -#endif - -#ifdef CONFIG_MACH_NETBOOKPRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETBOOKPRO -# endif -# define machine_is_netbookpro() (machine_arch_type == MACH_TYPE_NETBOOKPRO) -#else -# define machine_is_netbookpro() (0) -#endif - -#ifdef CONFIG_MACH_HW90200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW90200 -# endif -# define machine_is_hw90200() (machine_arch_type == MACH_TYPE_HW90200) -#else -# define machine_is_hw90200() (0) -#endif - -#ifdef CONFIG_MACH_CONDOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CONDOR -# endif -# define machine_is_condor() (machine_arch_type == MACH_TYPE_CONDOR) -#else -# define machine_is_condor() (0) -#endif - -#ifdef CONFIG_MACH_CUP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CUP -# endif -# define machine_is_cup() (machine_arch_type == MACH_TYPE_CUP) -#else -# define machine_is_cup() (0) -#endif - -#ifdef CONFIG_MACH_KITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KITE -# endif -# define machine_is_kite() (machine_arch_type == MACH_TYPE_KITE) -#else -# define machine_is_kite() (0) -#endif - -#ifdef CONFIG_MACH_SCB9328 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCB9328 -# endif -# define machine_is_scb9328() (machine_arch_type == MACH_TYPE_SCB9328) -#else -# define machine_is_scb9328() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_H3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_H3 -# endif -# define machine_is_omap_h3() (machine_arch_type == MACH_TYPE_OMAP_H3) -#else -# define machine_is_omap_h3() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_H4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_H4 -# endif -# define machine_is_omap_h4() (machine_arch_type == MACH_TYPE_OMAP_H4) -#else -# define machine_is_omap_h4() (0) -#endif - -#ifdef CONFIG_MACH_N10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N10 -# endif -# define machine_is_n10() (machine_arch_type == MACH_TYPE_N10) -#else -# define machine_is_n10() (0) -#endif - -#ifdef CONFIG_MACH_MONTAJADE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MONTAJADE -# endif -# define machine_is_montejade() (machine_arch_type == MACH_TYPE_MONTAJADE) -#else -# define machine_is_montejade() (0) -#endif - -#ifdef CONFIG_MACH_SG560 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG560 -# endif -# define machine_is_sg560() (machine_arch_type == MACH_TYPE_SG560) -#else -# define machine_is_sg560() (0) -#endif - -#ifdef CONFIG_MACH_DP1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DP1000 -# endif -# define machine_is_dp1000() (machine_arch_type == MACH_TYPE_DP1000) -#else -# define machine_is_dp1000() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_OSK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_OSK -# endif -# define machine_is_omap_osk() (machine_arch_type == MACH_TYPE_OMAP_OSK) -#else -# define machine_is_omap_osk() (0) -#endif - -#ifdef CONFIG_MACH_RG100V3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RG100V3 -# endif -# define machine_is_rg100v3() (machine_arch_type == MACH_TYPE_RG100V3) -#else -# define machine_is_rg100v3() (0) -#endif - -#ifdef CONFIG_MACH_MX2ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX2ADS -# endif -# define machine_is_mx2ads() (machine_arch_type == MACH_TYPE_MX2ADS) -#else -# define machine_is_mx2ads() (0) -#endif - -#ifdef CONFIG_MACH_PXA_KILO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_KILO -# endif -# define machine_is_pxa_kilo() (machine_arch_type == MACH_TYPE_PXA_KILO) -#else -# define machine_is_pxa_kilo() (0) -#endif - -#ifdef CONFIG_MACH_IXP4XX_EAGLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP4XX_EAGLE -# endif -# define machine_is_ixp4xx_eagle() (machine_arch_type == MACH_TYPE_IXP4XX_EAGLE) -#else -# define machine_is_ixp4xx_eagle() (0) -#endif - -#ifdef CONFIG_MACH_TOSA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOSA -# endif -# define machine_is_tosa() (machine_arch_type == MACH_TYPE_TOSA) -#else -# define machine_is_tosa() (0) -#endif - -#ifdef CONFIG_MACH_MB2520F -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB2520F -# endif -# define machine_is_mb2520f() (machine_arch_type == MACH_TYPE_MB2520F) -#else -# define machine_is_mb2520f() (0) -#endif - -#ifdef CONFIG_MACH_EMC1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMC1000 -# endif -# define machine_is_emc1000() (machine_arch_type == MACH_TYPE_EMC1000) -#else -# define machine_is_emc1000() (0) -#endif - -#ifdef CONFIG_MACH_TIDSC25 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TIDSC25 -# endif -# define machine_is_tidsc25() (machine_arch_type == MACH_TYPE_TIDSC25) -#else -# define machine_is_tidsc25() (0) -#endif - -#ifdef CONFIG_MACH_AKCPMXL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AKCPMXL -# endif -# define machine_is_akcpmxl() (machine_arch_type == MACH_TYPE_AKCPMXL) -#else -# define machine_is_akcpmxl() (0) -#endif - -#ifdef CONFIG_MACH_AV3XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AV3XX -# endif -# define machine_is_av3xx() (machine_arch_type == MACH_TYPE_AV3XX) -#else -# define machine_is_av3xx() (0) -#endif - -#ifdef CONFIG_MACH_AVILA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVILA -# endif -# define machine_is_avila() (machine_arch_type == MACH_TYPE_AVILA) -#else -# define machine_is_avila() (0) -#endif - -#ifdef CONFIG_MACH_PXA_MPM10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_MPM10 -# endif -# define machine_is_pxa_mpm10() (machine_arch_type == MACH_TYPE_PXA_MPM10) -#else -# define machine_is_pxa_mpm10() (0) -#endif - -#ifdef CONFIG_MACH_PXA_KYANITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_KYANITE -# endif -# define machine_is_pxa_kyanite() (machine_arch_type == MACH_TYPE_PXA_KYANITE) -#else -# define machine_is_pxa_kyanite() (0) -#endif - -#ifdef CONFIG_MACH_SGOLD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SGOLD -# endif -# define machine_is_sgold() (machine_arch_type == MACH_TYPE_SGOLD) -#else -# define machine_is_sgold() (0) -#endif - -#ifdef CONFIG_MACH_OSCAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSCAR -# endif -# define machine_is_oscar() (machine_arch_type == MACH_TYPE_OSCAR) -#else -# define machine_is_oscar() (0) -#endif - -#ifdef CONFIG_MACH_EPXA4USB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EPXA4USB2 -# endif -# define machine_is_epxa4usb2() (machine_arch_type == MACH_TYPE_EPXA4USB2) -#else -# define machine_is_epxa4usb2() (0) -#endif - -#ifdef CONFIG_MACH_XSENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XSENGINE -# endif -# define machine_is_xsengine() (machine_arch_type == MACH_TYPE_XSENGINE) -#else -# define machine_is_xsengine() (0) -#endif - -#ifdef CONFIG_MACH_IP600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IP600 -# endif -# define machine_is_ip600() (machine_arch_type == MACH_TYPE_IP600) -#else -# define machine_is_ip600() (0) -#endif - -#ifdef CONFIG_MACH_MCAN2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MCAN2 -# endif -# define machine_is_mcan2() (machine_arch_type == MACH_TYPE_MCAN2) -#else -# define machine_is_mcan2() (0) -#endif - -#ifdef CONFIG_MACH_DDI_BLUERIDGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DDI_BLUERIDGE -# endif -# define machine_is_ddi_blueridge() (machine_arch_type == MACH_TYPE_DDI_BLUERIDGE) -#else -# define machine_is_ddi_blueridge() (0) -#endif - -#ifdef CONFIG_MACH_SKYMINDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SKYMINDER -# endif -# define machine_is_skyminder() (machine_arch_type == MACH_TYPE_SKYMINDER) -#else -# define machine_is_skyminder() (0) -#endif - -#ifdef CONFIG_MACH_LPD79520 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD79520 -# endif -# define machine_is_lpd79520() (machine_arch_type == MACH_TYPE_LPD79520) -#else -# define machine_is_lpd79520() (0) -#endif - -#ifdef CONFIG_MACH_EDB9302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9302 -# endif -# define machine_is_edb9302() (machine_arch_type == MACH_TYPE_EDB9302) -#else -# define machine_is_edb9302() (0) -#endif - -#ifdef CONFIG_MACH_HW90340 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW90340 -# endif -# define machine_is_hw90340() (machine_arch_type == MACH_TYPE_HW90340) -#else -# define machine_is_hw90340() (0) -#endif - -#ifdef CONFIG_MACH_CIP_BOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CIP_BOX -# endif -# define machine_is_cip_box() (machine_arch_type == MACH_TYPE_CIP_BOX) -#else -# define machine_is_cip_box() (0) -#endif - -#ifdef CONFIG_MACH_IVPN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IVPN -# endif -# define machine_is_ivpn() (machine_arch_type == MACH_TYPE_IVPN) -#else -# define machine_is_ivpn() (0) -#endif - -#ifdef CONFIG_MACH_RSOC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RSOC2 -# endif -# define machine_is_rsoc2() (machine_arch_type == MACH_TYPE_RSOC2) -#else -# define machine_is_rsoc2() (0) -#endif - -#ifdef CONFIG_MACH_HUSKY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUSKY -# endif -# define machine_is_husky() (machine_arch_type == MACH_TYPE_HUSKY) -#else -# define machine_is_husky() (0) -#endif - -#ifdef CONFIG_MACH_BOXER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BOXER -# endif -# define machine_is_boxer() (machine_arch_type == MACH_TYPE_BOXER) -#else -# define machine_is_boxer() (0) -#endif - -#ifdef CONFIG_MACH_SHEPHERD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHEPHERD -# endif -# define machine_is_shepherd() (machine_arch_type == MACH_TYPE_SHEPHERD) -#else -# define machine_is_shepherd() (0) -#endif - -#ifdef CONFIG_MACH_AML42800AA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML42800AA -# endif -# define machine_is_aml42800aa() (machine_arch_type == MACH_TYPE_AML42800AA) -#else -# define machine_is_aml42800aa() (0) -#endif - -#ifdef CONFIG_MACH_LPC2294 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC2294 -# endif -# define machine_is_lpc2294() (machine_arch_type == MACH_TYPE_LPC2294) -#else -# define machine_is_lpc2294() (0) -#endif - -#ifdef CONFIG_MACH_SWITCHGRASS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWITCHGRASS -# endif -# define machine_is_switchgrass() (machine_arch_type == MACH_TYPE_SWITCHGRASS) -#else -# define machine_is_switchgrass() (0) -#endif - -#ifdef CONFIG_MACH_ENS_CMU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENS_CMU -# endif -# define machine_is_ens_cmu() (machine_arch_type == MACH_TYPE_ENS_CMU) -#else -# define machine_is_ens_cmu() (0) -#endif - -#ifdef CONFIG_MACH_MM6_SDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MM6_SDB -# endif -# define machine_is_mm6_sdb() (machine_arch_type == MACH_TYPE_MM6_SDB) -#else -# define machine_is_mm6_sdb() (0) -#endif - -#ifdef CONFIG_MACH_SATURN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SATURN -# endif -# define machine_is_saturn() (machine_arch_type == MACH_TYPE_SATURN) -#else -# define machine_is_saturn() (0) -#endif - -#ifdef CONFIG_MACH_I30030EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I30030EVB -# endif -# define machine_is_i30030evb() (machine_arch_type == MACH_TYPE_I30030EVB) -#else -# define machine_is_i30030evb() (0) -#endif - -#ifdef CONFIG_MACH_MXC27530EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC27530EVB -# endif -# define machine_is_mxc27530evb() (machine_arch_type == MACH_TYPE_MXC27530EVB) -#else -# define machine_is_mxc27530evb() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2800 -# endif -# define machine_is_smdk2800() (machine_arch_type == MACH_TYPE_SMDK2800) -#else -# define machine_is_smdk2800() (0) -#endif - -#ifdef CONFIG_MACH_MTWILSON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MTWILSON -# endif -# define machine_is_mtwilson() (machine_arch_type == MACH_TYPE_MTWILSON) -#else -# define machine_is_mtwilson() (0) -#endif - -#ifdef CONFIG_MACH_ZITI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZITI -# endif -# define machine_is_ziti() (machine_arch_type == MACH_TYPE_ZITI) -#else -# define machine_is_ziti() (0) -#endif - -#ifdef CONFIG_MACH_GRANDFATHER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRANDFATHER -# endif -# define machine_is_grandfather() (machine_arch_type == MACH_TYPE_GRANDFATHER) -#else -# define machine_is_grandfather() (0) -#endif - -#ifdef CONFIG_MACH_TENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TENGINE -# endif -# define machine_is_tengine() (machine_arch_type == MACH_TYPE_TENGINE) -#else -# define machine_is_tengine() (0) -#endif - -#ifdef CONFIG_MACH_S3C2460 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2460 -# endif -# define machine_is_s3c2460() (machine_arch_type == MACH_TYPE_S3C2460) -#else -# define machine_is_s3c2460() (0) -#endif - -#ifdef CONFIG_MACH_PDM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PDM -# endif -# define machine_is_pdm() (machine_arch_type == MACH_TYPE_PDM) -#else -# define machine_is_pdm() (0) -#endif - -#ifdef CONFIG_MACH_H4700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H4700 -# endif -# define machine_is_h4700() (machine_arch_type == MACH_TYPE_H4700) -#else -# define machine_is_h4700() (0) -#endif - -#ifdef CONFIG_MACH_H6300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6300 -# endif -# define machine_is_h6300() (machine_arch_type == MACH_TYPE_H6300) -#else -# define machine_is_h6300() (0) -#endif - -#ifdef CONFIG_MACH_RZ1700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RZ1700 -# endif -# define machine_is_rz1700() (machine_arch_type == MACH_TYPE_RZ1700) -#else -# define machine_is_rz1700() (0) -#endif - -#ifdef CONFIG_MACH_A716 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A716 -# endif -# define machine_is_a716() (machine_arch_type == MACH_TYPE_A716) -#else -# define machine_is_a716() (0) -#endif - -#ifdef CONFIG_MACH_ESTK2440A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESTK2440A -# endif -# define machine_is_estk2440a() (machine_arch_type == MACH_TYPE_ESTK2440A) -#else -# define machine_is_estk2440a() (0) -#endif - -#ifdef CONFIG_MACH_ATWIXP425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATWIXP425 -# endif -# define machine_is_atwixp425() (machine_arch_type == MACH_TYPE_ATWIXP425) -#else -# define machine_is_atwixp425() (0) -#endif - -#ifdef CONFIG_MACH_CSB336 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB336 -# endif -# define machine_is_csb336() (machine_arch_type == MACH_TYPE_CSB336) -#else -# define machine_is_csb336() (0) -#endif - -#ifdef CONFIG_MACH_RIRM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIRM2 -# endif -# define machine_is_rirm2() (machine_arch_type == MACH_TYPE_RIRM2) -#else -# define machine_is_rirm2() (0) -#endif - -#ifdef CONFIG_MACH_CX23518 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CX23518 -# endif -# define machine_is_cx23518() (machine_arch_type == MACH_TYPE_CX23518) -#else -# define machine_is_cx23518() (0) -#endif - -#ifdef CONFIG_MACH_CX2351X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CX2351X -# endif -# define machine_is_cx2351x() (machine_arch_type == MACH_TYPE_CX2351X) -#else -# define machine_is_cx2351x() (0) -#endif - -#ifdef CONFIG_MACH_COMPUTIME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMPUTIME -# endif -# define machine_is_computime() (machine_arch_type == MACH_TYPE_COMPUTIME) -#else -# define machine_is_computime() (0) -#endif - -#ifdef CONFIG_MACH_IZARUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IZARUS -# endif -# define machine_is_izarus() (machine_arch_type == MACH_TYPE_IZARUS) -#else -# define machine_is_izarus() (0) -#endif - -#ifdef CONFIG_MACH_RTS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RTS -# endif -# define machine_is_pxa_rts() (machine_arch_type == MACH_TYPE_RTS) -#else -# define machine_is_pxa_rts() (0) -#endif - -#ifdef CONFIG_MACH_SE5100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE5100 -# endif -# define machine_is_se5100() (machine_arch_type == MACH_TYPE_SE5100) -#else -# define machine_is_se5100() (0) -#endif - -#ifdef CONFIG_MACH_S3C2510 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2510 -# endif -# define machine_is_s3c2510() (machine_arch_type == MACH_TYPE_S3C2510) -#else -# define machine_is_s3c2510() (0) -#endif - -#ifdef CONFIG_MACH_CSB437TL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB437TL -# endif -# define machine_is_csb437tl() (machine_arch_type == MACH_TYPE_CSB437TL) -#else -# define machine_is_csb437tl() (0) -#endif - -#ifdef CONFIG_MACH_SLAUSON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SLAUSON -# endif -# define machine_is_slauson() (machine_arch_type == MACH_TYPE_SLAUSON) -#else -# define machine_is_slauson() (0) -#endif - -#ifdef CONFIG_MACH_PEARLRIVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PEARLRIVER -# endif -# define machine_is_pearlriver() (machine_arch_type == MACH_TYPE_PEARLRIVER) -#else -# define machine_is_pearlriver() (0) -#endif - -#ifdef CONFIG_MACH_TDC_P210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TDC_P210 -# endif -# define machine_is_tdc_p210() (machine_arch_type == MACH_TYPE_TDC_P210) -#else -# define machine_is_tdc_p210() (0) -#endif - -#ifdef CONFIG_MACH_SG580 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG580 -# endif -# define machine_is_sg580() (machine_arch_type == MACH_TYPE_SG580) -#else -# define machine_is_sg580() (0) -#endif - -#ifdef CONFIG_MACH_WRSBCARM7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WRSBCARM7 -# endif -# define machine_is_wrsbcarm7() (machine_arch_type == MACH_TYPE_WRSBCARM7) -#else -# define machine_is_wrsbcarm7() (0) -#endif - -#ifdef CONFIG_MACH_IPD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPD -# endif -# define machine_is_ipd() (machine_arch_type == MACH_TYPE_IPD) -#else -# define machine_is_ipd() (0) -#endif - -#ifdef CONFIG_MACH_PXA_DNP2110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_DNP2110 -# endif -# define machine_is_pxa_dnp2110() (machine_arch_type == MACH_TYPE_PXA_DNP2110) -#else -# define machine_is_pxa_dnp2110() (0) -#endif - -#ifdef CONFIG_MACH_XAENIAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XAENIAX -# endif -# define machine_is_xaeniax() (machine_arch_type == MACH_TYPE_XAENIAX) -#else -# define machine_is_xaeniax() (0) -#endif - -#ifdef CONFIG_MACH_SOMN4250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOMN4250 -# endif -# define machine_is_somn4250() (machine_arch_type == MACH_TYPE_SOMN4250) -#else -# define machine_is_somn4250() (0) -#endif - -#ifdef CONFIG_MACH_PLEB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLEB2 -# endif -# define machine_is_pleb2() (machine_arch_type == MACH_TYPE_PLEB2) -#else -# define machine_is_pleb2() (0) -#endif - -#ifdef CONFIG_MACH_CORNWALLIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORNWALLIS -# endif -# define machine_is_cornwallis() (machine_arch_type == MACH_TYPE_CORNWALLIS) -#else -# define machine_is_cornwallis() (0) -#endif - -#ifdef CONFIG_MACH_GURNEY_DRV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GURNEY_DRV -# endif -# define machine_is_gurney_drv() (machine_arch_type == MACH_TYPE_GURNEY_DRV) -#else -# define machine_is_gurney_drv() (0) -#endif - -#ifdef CONFIG_MACH_CHAFFEE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHAFFEE -# endif -# define machine_is_chaffee() (machine_arch_type == MACH_TYPE_CHAFFEE) -#else -# define machine_is_chaffee() (0) -#endif - -#ifdef CONFIG_MACH_RMS101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RMS101 -# endif -# define machine_is_rms101() (machine_arch_type == MACH_TYPE_RMS101) -#else -# define machine_is_rms101() (0) -#endif - -#ifdef CONFIG_MACH_RX3715 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RX3715 -# endif -# define machine_is_rx3715() (machine_arch_type == MACH_TYPE_RX3715) -#else -# define machine_is_rx3715() (0) -#endif - -#ifdef CONFIG_MACH_SWIFT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWIFT -# endif -# define machine_is_swift() (machine_arch_type == MACH_TYPE_SWIFT) -#else -# define machine_is_swift() (0) -#endif - -#ifdef CONFIG_MACH_ROVERP7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERP7 -# endif -# define machine_is_roverp7() (machine_arch_type == MACH_TYPE_ROVERP7) -#else -# define machine_is_roverp7() (0) -#endif - -#ifdef CONFIG_MACH_PR818S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PR818S -# endif -# define machine_is_pr818s() (machine_arch_type == MACH_TYPE_PR818S) -#else -# define machine_is_pr818s() (0) -#endif - -#ifdef CONFIG_MACH_TRXPRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRXPRO -# endif -# define machine_is_trxpro() (machine_arch_type == MACH_TYPE_TRXPRO) -#else -# define machine_is_trxpro() (0) -#endif - -#ifdef CONFIG_MACH_NSLU2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSLU2 -# endif -# define machine_is_nslu2() (machine_arch_type == MACH_TYPE_NSLU2) -#else -# define machine_is_nslu2() (0) -#endif - -#ifdef CONFIG_MACH_E400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E400 -# endif -# define machine_is_e400() (machine_arch_type == MACH_TYPE_E400) -#else -# define machine_is_e400() (0) -#endif - -#ifdef CONFIG_MACH_TRAB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRAB -# endif -# define machine_is_trab() (machine_arch_type == MACH_TYPE_TRAB) -#else -# define machine_is_trab() (0) -#endif - -#ifdef CONFIG_MACH_CMC_PU2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CMC_PU2 -# endif -# define machine_is_cmc_pu2() (machine_arch_type == MACH_TYPE_CMC_PU2) -#else -# define machine_is_cmc_pu2() (0) -#endif - -#ifdef CONFIG_MACH_FULCRUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FULCRUM -# endif -# define machine_is_fulcrum() (machine_arch_type == MACH_TYPE_FULCRUM) -#else -# define machine_is_fulcrum() (0) -#endif - -#ifdef CONFIG_MACH_NETGATE42X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETGATE42X -# endif -# define machine_is_netgate42x() (machine_arch_type == MACH_TYPE_NETGATE42X) -#else -# define machine_is_netgate42x() (0) -#endif - -#ifdef CONFIG_MACH_STR710 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STR710 -# endif -# define machine_is_str710() (machine_arch_type == MACH_TYPE_STR710) -#else -# define machine_is_str710() (0) -#endif - -#ifdef CONFIG_MACH_IXDPG425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDPG425 -# endif -# define machine_is_ixdpg425() (machine_arch_type == MACH_TYPE_IXDPG425) -#else -# define machine_is_ixdpg425() (0) -#endif - -#ifdef CONFIG_MACH_TOMTOMGO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOMTOMGO -# endif -# define machine_is_tomtomgo() (machine_arch_type == MACH_TYPE_TOMTOMGO) -#else -# define machine_is_tomtomgo() (0) -#endif - -#ifdef CONFIG_MACH_VERSATILE_AB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VERSATILE_AB -# endif -# define machine_is_versatile_ab() (machine_arch_type == MACH_TYPE_VERSATILE_AB) -#else -# define machine_is_versatile_ab() (0) -#endif - -#ifdef CONFIG_MACH_EDB9307 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9307 -# endif -# define machine_is_edb9307() (machine_arch_type == MACH_TYPE_EDB9307) -#else -# define machine_is_edb9307() (0) -#endif - -#ifdef CONFIG_MACH_SG565 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG565 -# endif -# define machine_is_sg565() (machine_arch_type == MACH_TYPE_SG565) -#else -# define machine_is_sg565() (0) -#endif - -#ifdef CONFIG_MACH_LPD79524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD79524 -# endif -# define machine_is_lpd79524() (machine_arch_type == MACH_TYPE_LPD79524) -#else -# define machine_is_lpd79524() (0) -#endif - -#ifdef CONFIG_MACH_LPD79525 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD79525 -# endif -# define machine_is_lpd79525() (machine_arch_type == MACH_TYPE_LPD79525) -#else -# define machine_is_lpd79525() (0) -#endif - -#ifdef CONFIG_MACH_RMS100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RMS100 -# endif -# define machine_is_rms100() (machine_arch_type == MACH_TYPE_RMS100) -#else -# define machine_is_rms100() (0) -#endif - -#ifdef CONFIG_MACH_KB9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KB9200 -# endif -# define machine_is_kb9200() (machine_arch_type == MACH_TYPE_KB9200) -#else -# define machine_is_kb9200() (0) -#endif - -#ifdef CONFIG_MACH_SX1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SX1 -# endif -# define machine_is_sx1() (machine_arch_type == MACH_TYPE_SX1) -#else -# define machine_is_sx1() (0) -#endif - -#ifdef CONFIG_MACH_HMS39C7092 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HMS39C7092 -# endif -# define machine_is_hms39c7092() (machine_arch_type == MACH_TYPE_HMS39C7092) -#else -# define machine_is_hms39c7092() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO -# endif -# define machine_is_armadillo() (machine_arch_type == MACH_TYPE_ARMADILLO) -#else -# define machine_is_armadillo() (0) -#endif - -#ifdef CONFIG_MACH_IPCU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPCU -# endif -# define machine_is_ipcu() (machine_arch_type == MACH_TYPE_IPCU) -#else -# define machine_is_ipcu() (0) -#endif - -#ifdef CONFIG_MACH_LOOX720 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOX720 -# endif -# define machine_is_loox720() (machine_arch_type == MACH_TYPE_LOOX720) -#else -# define machine_is_loox720() (0) -#endif - -#ifdef CONFIG_MACH_IXDP465 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP465 -# endif -# define machine_is_ixdp465() (machine_arch_type == MACH_TYPE_IXDP465) -#else -# define machine_is_ixdp465() (0) -#endif - -#ifdef CONFIG_MACH_IXDP2351 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2351 -# endif -# define machine_is_ixdp2351() (machine_arch_type == MACH_TYPE_IXDP2351) -#else -# define machine_is_ixdp2351() (0) -#endif - -#ifdef CONFIG_MACH_ADSVIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSVIX -# endif -# define machine_is_adsvix() (machine_arch_type == MACH_TYPE_ADSVIX) -#else -# define machine_is_adsvix() (0) -#endif - -#ifdef CONFIG_MACH_DM270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM270 -# endif -# define machine_is_dm270() (machine_arch_type == MACH_TYPE_DM270) -#else -# define machine_is_dm270() (0) -#endif - -#ifdef CONFIG_MACH_SOCLTPLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOCLTPLUS -# endif -# define machine_is_socltplus() (machine_arch_type == MACH_TYPE_SOCLTPLUS) -#else -# define machine_is_socltplus() (0) -#endif - -#ifdef CONFIG_MACH_ECIA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECIA -# endif -# define machine_is_ecia() (machine_arch_type == MACH_TYPE_ECIA) -#else -# define machine_is_ecia() (0) -#endif - -#ifdef CONFIG_MACH_CM4008 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM4008 -# endif -# define machine_is_cm4008() (machine_arch_type == MACH_TYPE_CM4008) -#else -# define machine_is_cm4008() (0) -#endif - -#ifdef CONFIG_MACH_P2001 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P2001 -# endif -# define machine_is_p2001() (machine_arch_type == MACH_TYPE_P2001) -#else -# define machine_is_p2001() (0) -#endif - -#ifdef CONFIG_MACH_TWISTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TWISTER -# endif -# define machine_is_twister() (machine_arch_type == MACH_TYPE_TWISTER) -#else -# define machine_is_twister() (0) -#endif - -#ifdef CONFIG_MACH_MUDSHARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MUDSHARK -# endif -# define machine_is_mudshark() (machine_arch_type == MACH_TYPE_MUDSHARK) -#else -# define machine_is_mudshark() (0) -#endif - -#ifdef CONFIG_MACH_HB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HB2 -# endif -# define machine_is_hb2() (machine_arch_type == MACH_TYPE_HB2) -#else -# define machine_is_hb2() (0) -#endif - -#ifdef CONFIG_MACH_IQ80332 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80332 -# endif -# define machine_is_iq80332() (machine_arch_type == MACH_TYPE_IQ80332) -#else -# define machine_is_iq80332() (0) -#endif - -#ifdef CONFIG_MACH_SENDT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SENDT -# endif -# define machine_is_sendt() (machine_arch_type == MACH_TYPE_SENDT) -#else -# define machine_is_sendt() (0) -#endif - -#ifdef CONFIG_MACH_MX2JAZZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX2JAZZ -# endif -# define machine_is_mx2jazz() (machine_arch_type == MACH_TYPE_MX2JAZZ) -#else -# define machine_is_mx2jazz() (0) -#endif - -#ifdef CONFIG_MACH_MULTIIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTIIO -# endif -# define machine_is_multiio() (machine_arch_type == MACH_TYPE_MULTIIO) -#else -# define machine_is_multiio() (0) -#endif - -#ifdef CONFIG_MACH_HRDISPLAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HRDISPLAY -# endif -# define machine_is_hrdisplay() (machine_arch_type == MACH_TYPE_HRDISPLAY) -#else -# define machine_is_hrdisplay() (0) -#endif - -#ifdef CONFIG_MACH_MXC27530ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC27530ADS -# endif -# define machine_is_mxc27530ads() (machine_arch_type == MACH_TYPE_MXC27530ADS) -#else -# define machine_is_mxc27530ads() (0) -#endif - -#ifdef CONFIG_MACH_TRIZEPS3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS3 -# endif -# define machine_is_trizeps3() (machine_arch_type == MACH_TYPE_TRIZEPS3) -#else -# define machine_is_trizeps3() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZA -# endif -# define machine_is_zefeerdza() (machine_arch_type == MACH_TYPE_ZEFEERDZA) -#else -# define machine_is_zefeerdza() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZB -# endif -# define machine_is_zefeerdzb() (machine_arch_type == MACH_TYPE_ZEFEERDZB) -#else -# define machine_is_zefeerdzb() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZG -# endif -# define machine_is_zefeerdzg() (machine_arch_type == MACH_TYPE_ZEFEERDZG) -#else -# define machine_is_zefeerdzg() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZN -# endif -# define machine_is_zefeerdzn() (machine_arch_type == MACH_TYPE_ZEFEERDZN) -#else -# define machine_is_zefeerdzn() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZQ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZQ -# endif -# define machine_is_zefeerdzq() (machine_arch_type == MACH_TYPE_ZEFEERDZQ) -#else -# define machine_is_zefeerdzq() (0) -#endif - -#ifdef CONFIG_MACH_GTWX5715 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GTWX5715 -# endif -# define machine_is_gtwx5715() (machine_arch_type == MACH_TYPE_GTWX5715) -#else -# define machine_is_gtwx5715() (0) -#endif - -#ifdef CONFIG_MACH_ASTRO_JACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASTRO_JACK -# endif -# define machine_is_astro_jack() (machine_arch_type == MACH_TYPE_ASTRO_JACK) -#else -# define machine_is_astro_jack() (0) -#endif - -#ifdef CONFIG_MACH_TIP03 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TIP03 -# endif -# define machine_is_tip03() (machine_arch_type == MACH_TYPE_TIP03) -#else -# define machine_is_tip03() (0) -#endif - -#ifdef CONFIG_MACH_A9200EC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9200EC -# endif -# define machine_is_a9200ec() (machine_arch_type == MACH_TYPE_A9200EC) -#else -# define machine_is_a9200ec() (0) -#endif - -#ifdef CONFIG_MACH_PNX0105 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX0105 -# endif -# define machine_is_pnx0105() (machine_arch_type == MACH_TYPE_PNX0105) -#else -# define machine_is_pnx0105() (0) -#endif - -#ifdef CONFIG_MACH_ADCPOECPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADCPOECPU -# endif -# define machine_is_adcpoecpu() (machine_arch_type == MACH_TYPE_ADCPOECPU) -#else -# define machine_is_adcpoecpu() (0) -#endif - -#ifdef CONFIG_MACH_CSB637 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB637 -# endif -# define machine_is_csb637() (machine_arch_type == MACH_TYPE_CSB637) -#else -# define machine_is_csb637() (0) -#endif - -#ifdef CONFIG_MACH_MB9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB9200 -# endif -# define machine_is_mb9200() (machine_arch_type == MACH_TYPE_MB9200) -#else -# define machine_is_mb9200() (0) -#endif - -#ifdef CONFIG_MACH_KULUN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KULUN -# endif -# define machine_is_kulun() (machine_arch_type == MACH_TYPE_KULUN) -#else -# define machine_is_kulun() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPER -# endif -# define machine_is_snapper() (machine_arch_type == MACH_TYPE_SNAPPER) -#else -# define machine_is_snapper() (0) -#endif - -#ifdef CONFIG_MACH_OPTIMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPTIMA -# endif -# define machine_is_optima() (machine_arch_type == MACH_TYPE_OPTIMA) -#else -# define machine_is_optima() (0) -#endif - -#ifdef CONFIG_MACH_DLHSBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DLHSBC -# endif -# define machine_is_dlhsbc() (machine_arch_type == MACH_TYPE_DLHSBC) -#else -# define machine_is_dlhsbc() (0) -#endif - -#ifdef CONFIG_MACH_X30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_X30 -# endif -# define machine_is_x30() (machine_arch_type == MACH_TYPE_X30) -#else -# define machine_is_x30() (0) -#endif - -#ifdef CONFIG_MACH_N30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N30 -# endif -# define machine_is_n30() (machine_arch_type == MACH_TYPE_N30) -#else -# define machine_is_n30() (0) -#endif - -#ifdef CONFIG_MACH_MANGA_KS8695 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MANGA_KS8695 -# endif -# define machine_is_manga_ks8695() (machine_arch_type == MACH_TYPE_MANGA_KS8695) -#else -# define machine_is_manga_ks8695() (0) -#endif - -#ifdef CONFIG_MACH_AJAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AJAX -# endif -# define machine_is_ajax() (machine_arch_type == MACH_TYPE_AJAX) -#else -# define machine_is_ajax() (0) -#endif - -#ifdef CONFIG_MACH_NEC_MP900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEC_MP900 -# endif -# define machine_is_nec_mp900() (machine_arch_type == MACH_TYPE_NEC_MP900) -#else -# define machine_is_nec_mp900() (0) -#endif - -#ifdef CONFIG_MACH_VVTK1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VVTK1000 -# endif -# define machine_is_vvtk1000() (machine_arch_type == MACH_TYPE_VVTK1000) -#else -# define machine_is_vvtk1000() (0) -#endif - -#ifdef CONFIG_MACH_KAFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KAFA -# endif -# define machine_is_kafa() (machine_arch_type == MACH_TYPE_KAFA) -#else -# define machine_is_kafa() (0) -#endif - -#ifdef CONFIG_MACH_VVTK3000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VVTK3000 -# endif -# define machine_is_vvtk3000() (machine_arch_type == MACH_TYPE_VVTK3000) -#else -# define machine_is_vvtk3000() (0) -#endif - -#ifdef CONFIG_MACH_PIMX1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PIMX1 -# endif -# define machine_is_pimx1() (machine_arch_type == MACH_TYPE_PIMX1) -#else -# define machine_is_pimx1() (0) -#endif - -#ifdef CONFIG_MACH_OLLIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OLLIE -# endif -# define machine_is_ollie() (machine_arch_type == MACH_TYPE_OLLIE) -#else -# define machine_is_ollie() (0) -#endif - -#ifdef CONFIG_MACH_SKYMAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SKYMAX -# endif -# define machine_is_skymax() (machine_arch_type == MACH_TYPE_SKYMAX) -#else -# define machine_is_skymax() (0) -#endif - -#ifdef CONFIG_MACH_JAZZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JAZZ -# endif -# define machine_is_jazz() (machine_arch_type == MACH_TYPE_JAZZ) -#else -# define machine_is_jazz() (0) -#endif - -#ifdef CONFIG_MACH_TEL_T3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEL_T3 -# endif -# define machine_is_tel_t3() (machine_arch_type == MACH_TYPE_TEL_T3) -#else -# define machine_is_tel_t3() (0) -#endif - -#ifdef CONFIG_MACH_AISINO_FCR255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AISINO_FCR255 -# endif -# define machine_is_aisino_fcr255() (machine_arch_type == MACH_TYPE_AISINO_FCR255) -#else -# define machine_is_aisino_fcr255() (0) -#endif - -#ifdef CONFIG_MACH_BTWEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BTWEB -# endif -# define machine_is_btweb() (machine_arch_type == MACH_TYPE_BTWEB) -#else -# define machine_is_btweb() (0) -#endif - -#ifdef CONFIG_MACH_DBG_LH79520 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DBG_LH79520 -# endif -# define machine_is_dbg_lh79520() (machine_arch_type == MACH_TYPE_DBG_LH79520) -#else -# define machine_is_dbg_lh79520() (0) -#endif - -#ifdef CONFIG_MACH_CM41XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM41XX -# endif -# define machine_is_cm41xx() (machine_arch_type == MACH_TYPE_CM41XX) -#else -# define machine_is_cm41xx() (0) -#endif - -#ifdef CONFIG_MACH_TS72XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS72XX -# endif -# define machine_is_ts72xx() (machine_arch_type == MACH_TYPE_TS72XX) -#else -# define machine_is_ts72xx() (0) -#endif - -#ifdef CONFIG_MACH_NGGPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NGGPXA -# endif -# define machine_is_nggpxa() (machine_arch_type == MACH_TYPE_NGGPXA) -#else -# define machine_is_nggpxa() (0) -#endif - -#ifdef CONFIG_MACH_CSB535 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB535 -# endif -# define machine_is_csb535() (machine_arch_type == MACH_TYPE_CSB535) -#else -# define machine_is_csb535() (0) -#endif - -#ifdef CONFIG_MACH_CSB536 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB536 -# endif -# define machine_is_csb536() (machine_arch_type == MACH_TYPE_CSB536) -#else -# define machine_is_csb536() (0) -#endif - -#ifdef CONFIG_MACH_PXA_TRAKPOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_TRAKPOD -# endif -# define machine_is_pxa_trakpod() (machine_arch_type == MACH_TYPE_PXA_TRAKPOD) -#else -# define machine_is_pxa_trakpod() (0) -#endif - -#ifdef CONFIG_MACH_PRAXIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRAXIS -# endif -# define machine_is_praxis() (machine_arch_type == MACH_TYPE_PRAXIS) -#else -# define machine_is_praxis() (0) -#endif - -#ifdef CONFIG_MACH_LH75411 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LH75411 -# endif -# define machine_is_lh75411() (machine_arch_type == MACH_TYPE_LH75411) -#else -# define machine_is_lh75411() (0) -#endif - -#ifdef CONFIG_MACH_OTOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OTOM -# endif -# define machine_is_otom() (machine_arch_type == MACH_TYPE_OTOM) -#else -# define machine_is_otom() (0) -#endif - -#ifdef CONFIG_MACH_NEXCODER_2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXCODER_2440 -# endif -# define machine_is_nexcoder_2440() (machine_arch_type == MACH_TYPE_NEXCODER_2440) -#else -# define machine_is_nexcoder_2440() (0) -#endif - -#ifdef CONFIG_MACH_LOOX410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOX410 -# endif -# define machine_is_loox410() (machine_arch_type == MACH_TYPE_LOOX410) -#else -# define machine_is_loox410() (0) -#endif - -#ifdef CONFIG_MACH_WESTLAKE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WESTLAKE -# endif -# define machine_is_westlake() (machine_arch_type == MACH_TYPE_WESTLAKE) -#else -# define machine_is_westlake() (0) -#endif - -#ifdef CONFIG_MACH_NSB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSB -# endif -# define machine_is_nsb() (machine_arch_type == MACH_TYPE_NSB) -#else -# define machine_is_nsb() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA_STN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA_STN -# endif -# define machine_is_esl_sarva_stn() (machine_arch_type == MACH_TYPE_ESL_SARVA_STN) -#else -# define machine_is_esl_sarva_stn() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA_TFT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA_TFT -# endif -# define machine_is_esl_sarva_tft() (machine_arch_type == MACH_TYPE_ESL_SARVA_TFT) -#else -# define machine_is_esl_sarva_tft() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA_IAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA_IAD -# endif -# define machine_is_esl_sarva_iad() (machine_arch_type == MACH_TYPE_ESL_SARVA_IAD) -#else -# define machine_is_esl_sarva_iad() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA_ACC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA_ACC -# endif -# define machine_is_esl_sarva_acc() (machine_arch_type == MACH_TYPE_ESL_SARVA_ACC) -#else -# define machine_is_esl_sarva_acc() (0) -#endif - -#ifdef CONFIG_MACH_TYPHOON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TYPHOON -# endif -# define machine_is_typhoon() (machine_arch_type == MACH_TYPE_TYPHOON) -#else -# define machine_is_typhoon() (0) -#endif - -#ifdef CONFIG_MACH_CNAV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CNAV -# endif -# define machine_is_cnav() (machine_arch_type == MACH_TYPE_CNAV) -#else -# define machine_is_cnav() (0) -#endif - -#ifdef CONFIG_MACH_A730 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A730 -# endif -# define machine_is_a730() (machine_arch_type == MACH_TYPE_A730) -#else -# define machine_is_a730() (0) -#endif - -#ifdef CONFIG_MACH_NETSTAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETSTAR -# endif -# define machine_is_netstar() (machine_arch_type == MACH_TYPE_NETSTAR) -#else -# define machine_is_netstar() (0) -#endif - -#ifdef CONFIG_MACH_PHASEFALE_SUPERCON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHASEFALE_SUPERCON -# endif -# define machine_is_supercon() (machine_arch_type == MACH_TYPE_PHASEFALE_SUPERCON) -#else -# define machine_is_supercon() (0) -#endif - -#ifdef CONFIG_MACH_SHIVA1100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHIVA1100 -# endif -# define machine_is_shiva1100() (machine_arch_type == MACH_TYPE_SHIVA1100) -#else -# define machine_is_shiva1100() (0) -#endif - -#ifdef CONFIG_MACH_ETEXSC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETEXSC -# endif -# define machine_is_etexsc() (machine_arch_type == MACH_TYPE_ETEXSC) -#else -# define machine_is_etexsc() (0) -#endif - -#ifdef CONFIG_MACH_IXDPG465 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDPG465 -# endif -# define machine_is_ixdpg465() (machine_arch_type == MACH_TYPE_IXDPG465) -#else -# define machine_is_ixdpg465() (0) -#endif - -#ifdef CONFIG_MACH_A9M2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9M2410 -# endif -# define machine_is_a9m2410() (machine_arch_type == MACH_TYPE_A9M2410) -#else -# define machine_is_a9m2410() (0) -#endif - -#ifdef CONFIG_MACH_A9M2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9M2440 -# endif -# define machine_is_a9m2440() (machine_arch_type == MACH_TYPE_A9M2440) -#else -# define machine_is_a9m2440() (0) -#endif - -#ifdef CONFIG_MACH_A9M9750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9M9750 -# endif -# define machine_is_a9m9750() (machine_arch_type == MACH_TYPE_A9M9750) -#else -# define machine_is_a9m9750() (0) -#endif - -#ifdef CONFIG_MACH_A9M9360 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9M9360 -# endif -# define machine_is_a9m9360() (machine_arch_type == MACH_TYPE_A9M9360) -#else -# define machine_is_a9m9360() (0) -#endif - -#ifdef CONFIG_MACH_UNC90 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNC90 -# endif -# define machine_is_unc90() (machine_arch_type == MACH_TYPE_UNC90) -#else -# define machine_is_unc90() (0) -#endif - -#ifdef CONFIG_MACH_ECO920 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECO920 -# endif -# define machine_is_eco920() (machine_arch_type == MACH_TYPE_ECO920) -#else -# define machine_is_eco920() (0) -#endif - -#ifdef CONFIG_MACH_SATVIEW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SATVIEW -# endif -# define machine_is_satview() (machine_arch_type == MACH_TYPE_SATVIEW) -#else -# define machine_is_satview() (0) -#endif - -#ifdef CONFIG_MACH_ROADRUNNER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROADRUNNER -# endif -# define machine_is_roadrunner() (machine_arch_type == MACH_TYPE_ROADRUNNER) -#else -# define machine_is_roadrunner() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200EK -# endif -# define machine_is_at91rm9200ek() (machine_arch_type == MACH_TYPE_AT91RM9200EK) -#else -# define machine_is_at91rm9200ek() (0) -#endif - -#ifdef CONFIG_MACH_GP32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GP32 -# endif -# define machine_is_gp32() (machine_arch_type == MACH_TYPE_GP32) -#else -# define machine_is_gp32() (0) -#endif - -#ifdef CONFIG_MACH_GEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEM -# endif -# define machine_is_gem() (machine_arch_type == MACH_TYPE_GEM) -#else -# define machine_is_gem() (0) -#endif - -#ifdef CONFIG_MACH_I858 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I858 -# endif -# define machine_is_i858() (machine_arch_type == MACH_TYPE_I858) -#else -# define machine_is_i858() (0) -#endif - -#ifdef CONFIG_MACH_HX2750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HX2750 -# endif -# define machine_is_hx2750() (machine_arch_type == MACH_TYPE_HX2750) -#else -# define machine_is_hx2750() (0) -#endif - -#ifdef CONFIG_MACH_MXC91131EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC91131EVB -# endif -# define machine_is_mxc91131evb() (machine_arch_type == MACH_TYPE_MXC91131EVB) -#else -# define machine_is_mxc91131evb() (0) -#endif - -#ifdef CONFIG_MACH_P700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P700 -# endif -# define machine_is_p700() (machine_arch_type == MACH_TYPE_P700) -#else -# define machine_is_p700() (0) -#endif - -#ifdef CONFIG_MACH_CPE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPE -# endif -# define machine_is_cpe() (machine_arch_type == MACH_TYPE_CPE) -#else -# define machine_is_cpe() (0) -#endif - -#ifdef CONFIG_MACH_SPITZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPITZ -# endif -# define machine_is_spitz() (machine_arch_type == MACH_TYPE_SPITZ) -#else -# define machine_is_spitz() (0) -#endif - -#ifdef CONFIG_MACH_NIMBRA340 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIMBRA340 -# endif -# define machine_is_nimbra340() (machine_arch_type == MACH_TYPE_NIMBRA340) -#else -# define machine_is_nimbra340() (0) -#endif - -#ifdef CONFIG_MACH_LPC22XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC22XX -# endif -# define machine_is_lpc22xx() (machine_arch_type == MACH_TYPE_LPC22XX) -#else -# define machine_is_lpc22xx() (0) -#endif - -#ifdef CONFIG_MACH_COMET3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMET3 -# endif -# define machine_is_omap_comet3() (machine_arch_type == MACH_TYPE_COMET3) -#else -# define machine_is_omap_comet3() (0) -#endif - -#ifdef CONFIG_MACH_COMET4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMET4 -# endif -# define machine_is_omap_comet4() (machine_arch_type == MACH_TYPE_COMET4) -#else -# define machine_is_omap_comet4() (0) -#endif - -#ifdef CONFIG_MACH_CSB625 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB625 -# endif -# define machine_is_csb625() (machine_arch_type == MACH_TYPE_CSB625) -#else -# define machine_is_csb625() (0) -#endif - -#ifdef CONFIG_MACH_FORTUNET2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FORTUNET2 -# endif -# define machine_is_fortunet2() (machine_arch_type == MACH_TYPE_FORTUNET2) -#else -# define machine_is_fortunet2() (0) -#endif - -#ifdef CONFIG_MACH_S5H2200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5H2200 -# endif -# define machine_is_s5h2200() (machine_arch_type == MACH_TYPE_S5H2200) -#else -# define machine_is_s5h2200() (0) -#endif - -#ifdef CONFIG_MACH_OPTORM920 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPTORM920 -# endif -# define machine_is_optorm920() (machine_arch_type == MACH_TYPE_OPTORM920) -#else -# define machine_is_optorm920() (0) -#endif - -#ifdef CONFIG_MACH_ADSBITSYXB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSYXB -# endif -# define machine_is_adsbitsyxb() (machine_arch_type == MACH_TYPE_ADSBITSYXB) -#else -# define machine_is_adsbitsyxb() (0) -#endif - -#ifdef CONFIG_MACH_ADSSPHERE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSSPHERE -# endif -# define machine_is_adssphere() (machine_arch_type == MACH_TYPE_ADSSPHERE) -#else -# define machine_is_adssphere() (0) -#endif - -#ifdef CONFIG_MACH_ADSPORTAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSPORTAL -# endif -# define machine_is_adsportal() (machine_arch_type == MACH_TYPE_ADSPORTAL) -#else -# define machine_is_adsportal() (0) -#endif - -#ifdef CONFIG_MACH_LN2410SBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LN2410SBC -# endif -# define machine_is_ln2410sbc() (machine_arch_type == MACH_TYPE_LN2410SBC) -#else -# define machine_is_ln2410sbc() (0) -#endif - -#ifdef CONFIG_MACH_CB3RUFC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CB3RUFC -# endif -# define machine_is_cb3rufc() (machine_arch_type == MACH_TYPE_CB3RUFC) -#else -# define machine_is_cb3rufc() (0) -#endif - -#ifdef CONFIG_MACH_MP2USB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MP2USB -# endif -# define machine_is_mp2usb() (machine_arch_type == MACH_TYPE_MP2USB) -#else -# define machine_is_mp2usb() (0) -#endif - -#ifdef CONFIG_MACH_NTNP425C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NTNP425C -# endif -# define machine_is_ntnp425c() (machine_arch_type == MACH_TYPE_NTNP425C) -#else -# define machine_is_ntnp425c() (0) -#endif - -#ifdef CONFIG_MACH_COLIBRI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLIBRI -# endif -# define machine_is_colibri() (machine_arch_type == MACH_TYPE_COLIBRI) -#else -# define machine_is_colibri() (0) -#endif - -#ifdef CONFIG_MACH_PCM7220 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM7220 -# endif -# define machine_is_pcm7220() (machine_arch_type == MACH_TYPE_PCM7220) -#else -# define machine_is_pcm7220() (0) -#endif - -#ifdef CONFIG_MACH_GATEWAY7001 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GATEWAY7001 -# endif -# define machine_is_gateway7001() (machine_arch_type == MACH_TYPE_GATEWAY7001) -#else -# define machine_is_gateway7001() (0) -#endif - -#ifdef CONFIG_MACH_PCM027 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM027 -# endif -# define machine_is_pcm027() (machine_arch_type == MACH_TYPE_PCM027) -#else -# define machine_is_pcm027() (0) -#endif - -#ifdef CONFIG_MACH_CMPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CMPXA -# endif -# define machine_is_cmpxa() (machine_arch_type == MACH_TYPE_CMPXA) -#else -# define machine_is_cmpxa() (0) -#endif - -#ifdef CONFIG_MACH_ANUBIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANUBIS -# endif -# define machine_is_anubis() (machine_arch_type == MACH_TYPE_ANUBIS) -#else -# define machine_is_anubis() (0) -#endif - -#ifdef CONFIG_MACH_ITE8152 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ITE8152 -# endif -# define machine_is_ite8152() (machine_arch_type == MACH_TYPE_ITE8152) -#else -# define machine_is_ite8152() (0) -#endif - -#ifdef CONFIG_MACH_LPC3XXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC3XXX -# endif -# define machine_is_lpc3xxx() (machine_arch_type == MACH_TYPE_LPC3XXX) -#else -# define machine_is_lpc3xxx() (0) -#endif - -#ifdef CONFIG_MACH_PUPPETEER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PUPPETEER -# endif -# define machine_is_puppeteer() (machine_arch_type == MACH_TYPE_PUPPETEER) -#else -# define machine_is_puppeteer() (0) -#endif - -#ifdef CONFIG_MACH_E570 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E570 -# endif -# define machine_is_e570() (machine_arch_type == MACH_TYPE_E570) -#else -# define machine_is_e570() (0) -#endif - -#ifdef CONFIG_MACH_X50 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_X50 -# endif -# define machine_is_x50() (machine_arch_type == MACH_TYPE_X50) -#else -# define machine_is_x50() (0) -#endif - -#ifdef CONFIG_MACH_RECON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RECON -# endif -# define machine_is_recon() (machine_arch_type == MACH_TYPE_RECON) -#else -# define machine_is_recon() (0) -#endif - -#ifdef CONFIG_MACH_XBOARDGP8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XBOARDGP8 -# endif -# define machine_is_xboardgp8() (machine_arch_type == MACH_TYPE_XBOARDGP8) -#else -# define machine_is_xboardgp8() (0) -#endif - -#ifdef CONFIG_MACH_FPIC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FPIC2 -# endif -# define machine_is_fpic2() (machine_arch_type == MACH_TYPE_FPIC2) -#else -# define machine_is_fpic2() (0) -#endif - -#ifdef CONFIG_MACH_AKITA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AKITA -# endif -# define machine_is_akita() (machine_arch_type == MACH_TYPE_AKITA) -#else -# define machine_is_akita() (0) -#endif - -#ifdef CONFIG_MACH_A81 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A81 -# endif -# define machine_is_a81() (machine_arch_type == MACH_TYPE_A81) -#else -# define machine_is_a81() (0) -#endif - -#ifdef CONFIG_MACH_SVM_SC25X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVM_SC25X -# endif -# define machine_is_svm_sc25x() (machine_arch_type == MACH_TYPE_SVM_SC25X) -#else -# define machine_is_svm_sc25x() (0) -#endif - -#ifdef CONFIG_MACH_VADATECH020 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VADATECH020 -# endif -# define machine_is_vt020() (machine_arch_type == MACH_TYPE_VADATECH020) -#else -# define machine_is_vt020() (0) -#endif - -#ifdef CONFIG_MACH_TLI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TLI -# endif -# define machine_is_tli() (machine_arch_type == MACH_TYPE_TLI) -#else -# define machine_is_tli() (0) -#endif - -#ifdef CONFIG_MACH_EDB9315LC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9315LC -# endif -# define machine_is_edb9315lc() (machine_arch_type == MACH_TYPE_EDB9315LC) -#else -# define machine_is_edb9315lc() (0) -#endif - -#ifdef CONFIG_MACH_PASSEC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PASSEC -# endif -# define machine_is_passec() (machine_arch_type == MACH_TYPE_PASSEC) -#else -# define machine_is_passec() (0) -#endif - -#ifdef CONFIG_MACH_DS_TIGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS_TIGER -# endif -# define machine_is_ds_tiger() (machine_arch_type == MACH_TYPE_DS_TIGER) -#else -# define machine_is_ds_tiger() (0) -#endif - -#ifdef CONFIG_MACH_E310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E310 -# endif -# define machine_is_e310() (machine_arch_type == MACH_TYPE_E310) -#else -# define machine_is_e310() (0) -#endif - -#ifdef CONFIG_MACH_E330 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E330 -# endif -# define machine_is_e330() (machine_arch_type == MACH_TYPE_E330) -#else -# define machine_is_e330() (0) -#endif - -#ifdef CONFIG_MACH_RT3000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RT3000 -# endif -# define machine_is_rt3000() (machine_arch_type == MACH_TYPE_RT3000) -#else -# define machine_is_rt3000() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA770 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA770 -# endif -# define machine_is_nokia770() (machine_arch_type == MACH_TYPE_NOKIA770) -#else -# define machine_is_nokia770() (0) -#endif - -#ifdef CONFIG_MACH_PNX0106 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX0106 -# endif -# define machine_is_pnx0106() (machine_arch_type == MACH_TYPE_PNX0106) -#else -# define machine_is_pnx0106() (0) -#endif - -#ifdef CONFIG_MACH_HX21XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HX21XX -# endif -# define machine_is_hx21xx() (machine_arch_type == MACH_TYPE_HX21XX) -#else -# define machine_is_hx21xx() (0) -#endif - -#ifdef CONFIG_MACH_FARADAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FARADAY -# endif -# define machine_is_faraday() (machine_arch_type == MACH_TYPE_FARADAY) -#else -# define machine_is_faraday() (0) -#endif - -#ifdef CONFIG_MACH_SBC9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC9312 -# endif -# define machine_is_sbc9312() (machine_arch_type == MACH_TYPE_SBC9312) -#else -# define machine_is_sbc9312() (0) -#endif - -#ifdef CONFIG_MACH_BATMAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BATMAN -# endif -# define machine_is_batman() (machine_arch_type == MACH_TYPE_BATMAN) -#else -# define machine_is_batman() (0) -#endif - -#ifdef CONFIG_MACH_JPD201 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JPD201 -# endif -# define machine_is_jpd201() (machine_arch_type == MACH_TYPE_JPD201) -#else -# define machine_is_jpd201() (0) -#endif - -#ifdef CONFIG_MACH_MIPSA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIPSA -# endif -# define machine_is_mipsa() (machine_arch_type == MACH_TYPE_MIPSA) -#else -# define machine_is_mipsa() (0) -#endif - -#ifdef CONFIG_MACH_KACOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KACOM -# endif -# define machine_is_kacom() (machine_arch_type == MACH_TYPE_KACOM) -#else -# define machine_is_kacom() (0) -#endif - -#ifdef CONFIG_MACH_SWARCOCPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCOCPU -# endif -# define machine_is_swarcocpu() (machine_arch_type == MACH_TYPE_SWARCOCPU) -#else -# define machine_is_swarcocpu() (0) -#endif - -#ifdef CONFIG_MACH_SWARCODSL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCODSL -# endif -# define machine_is_swarcodsl() (machine_arch_type == MACH_TYPE_SWARCODSL) -#else -# define machine_is_swarcodsl() (0) -#endif - -#ifdef CONFIG_MACH_BLUEANGEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUEANGEL -# endif -# define machine_is_blueangel() (machine_arch_type == MACH_TYPE_BLUEANGEL) -#else -# define machine_is_blueangel() (0) -#endif - -#ifdef CONFIG_MACH_HAIRYGRAMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HAIRYGRAMA -# endif -# define machine_is_hairygrama() (machine_arch_type == MACH_TYPE_HAIRYGRAMA) -#else -# define machine_is_hairygrama() (0) -#endif - -#ifdef CONFIG_MACH_BANFF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BANFF -# endif -# define machine_is_banff() (machine_arch_type == MACH_TYPE_BANFF) -#else -# define machine_is_banff() (0) -#endif - -#ifdef CONFIG_MACH_CARMEVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARMEVA -# endif -# define machine_is_carmeva() (machine_arch_type == MACH_TYPE_CARMEVA) -#else -# define machine_is_carmeva() (0) -#endif - -#ifdef CONFIG_MACH_SAM255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM255 -# endif -# define machine_is_sam255() (machine_arch_type == MACH_TYPE_SAM255) -#else -# define machine_is_sam255() (0) -#endif - -#ifdef CONFIG_MACH_PPM10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PPM10 -# endif -# define machine_is_ppm10() (machine_arch_type == MACH_TYPE_PPM10) -#else -# define machine_is_ppm10() (0) -#endif - -#ifdef CONFIG_MACH_EDB9315A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9315A -# endif -# define machine_is_edb9315a() (machine_arch_type == MACH_TYPE_EDB9315A) -#else -# define machine_is_edb9315a() (0) -#endif - -#ifdef CONFIG_MACH_SUNSET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUNSET -# endif -# define machine_is_sunset() (machine_arch_type == MACH_TYPE_SUNSET) -#else -# define machine_is_sunset() (0) -#endif - -#ifdef CONFIG_MACH_STARGATE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STARGATE2 -# endif -# define machine_is_stargate2() (machine_arch_type == MACH_TYPE_STARGATE2) -#else -# define machine_is_stargate2() (0) -#endif - -#ifdef CONFIG_MACH_INTELMOTE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INTELMOTE2 -# endif -# define machine_is_intelmote2() (machine_arch_type == MACH_TYPE_INTELMOTE2) -#else -# define machine_is_intelmote2() (0) -#endif - -#ifdef CONFIG_MACH_TRIZEPS4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS4 -# endif -# define machine_is_trizeps4() (machine_arch_type == MACH_TYPE_TRIZEPS4) -#else -# define machine_is_trizeps4() (0) -#endif - -#ifdef CONFIG_MACH_MAINSTONE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAINSTONE2 -# endif -# define machine_is_mainstone2() (machine_arch_type == MACH_TYPE_MAINSTONE2) -#else -# define machine_is_mainstone2() (0) -#endif - -#ifdef CONFIG_MACH_EZ_IXP42X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_IXP42X -# endif -# define machine_is_ez_ixp42x() (machine_arch_type == MACH_TYPE_EZ_IXP42X) -#else -# define machine_is_ez_ixp42x() (0) -#endif - -#ifdef CONFIG_MACH_TAPWAVE_ZODIAC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAPWAVE_ZODIAC -# endif -# define machine_is_tapwave_zodiac() (machine_arch_type == MACH_TYPE_TAPWAVE_ZODIAC) -#else -# define machine_is_tapwave_zodiac() (0) -#endif - -#ifdef CONFIG_MACH_UNIVERSALMETER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNIVERSALMETER -# endif -# define machine_is_universalmeter() (machine_arch_type == MACH_TYPE_UNIVERSALMETER) -#else -# define machine_is_universalmeter() (0) -#endif - -#ifdef CONFIG_MACH_HICOARM9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HICOARM9 -# endif -# define machine_is_hicoarm9() (machine_arch_type == MACH_TYPE_HICOARM9) -#else -# define machine_is_hicoarm9() (0) -#endif - -#ifdef CONFIG_MACH_PNX4008 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX4008 -# endif -# define machine_is_pnx4008() (machine_arch_type == MACH_TYPE_PNX4008) -#else -# define machine_is_pnx4008() (0) -#endif - -#ifdef CONFIG_MACH_KWS6000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KWS6000 -# endif -# define machine_is_kws6000() (machine_arch_type == MACH_TYPE_KWS6000) -#else -# define machine_is_kws6000() (0) -#endif - -#ifdef CONFIG_MACH_PORTUX920T -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PORTUX920T -# endif -# define machine_is_portux920t() (machine_arch_type == MACH_TYPE_PORTUX920T) -#else -# define machine_is_portux920t() (0) -#endif - -#ifdef CONFIG_MACH_EZ_X5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_X5 -# endif -# define machine_is_ez_x5() (machine_arch_type == MACH_TYPE_EZ_X5) -#else -# define machine_is_ez_x5() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_RUDOLPH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_RUDOLPH -# endif -# define machine_is_omap_rudolph() (machine_arch_type == MACH_TYPE_OMAP_RUDOLPH) -#else -# define machine_is_omap_rudolph() (0) -#endif - -#ifdef CONFIG_MACH_CPUAT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUAT91 -# endif -# define machine_is_cpuat91() (machine_arch_type == MACH_TYPE_CPUAT91) -#else -# define machine_is_cpuat91() (0) -#endif - -#ifdef CONFIG_MACH_REA9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REA9200 -# endif -# define machine_is_rea9200() (machine_arch_type == MACH_TYPE_REA9200) -#else -# define machine_is_rea9200() (0) -#endif - -#ifdef CONFIG_MACH_ACTS_PUNE_SA1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTS_PUNE_SA1110 -# endif -# define machine_is_acts_pune_sa1110() (machine_arch_type == MACH_TYPE_ACTS_PUNE_SA1110) -#else -# define machine_is_acts_pune_sa1110() (0) -#endif - -#ifdef CONFIG_MACH_IXP425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP425 -# endif -# define machine_is_ixp425() (machine_arch_type == MACH_TYPE_IXP425) -#else -# define machine_is_ixp425() (0) -#endif - -#ifdef CONFIG_MACH_I30030ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I30030ADS -# endif -# define machine_is_i30030ads() (machine_arch_type == MACH_TYPE_I30030ADS) -#else -# define machine_is_i30030ads() (0) -#endif - -#ifdef CONFIG_MACH_PERCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PERCH -# endif -# define machine_is_perch() (machine_arch_type == MACH_TYPE_PERCH) -#else -# define machine_is_perch() (0) -#endif - -#ifdef CONFIG_MACH_EIS05R1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EIS05R1 -# endif -# define machine_is_eis05r1() (machine_arch_type == MACH_TYPE_EIS05R1) -#else -# define machine_is_eis05r1() (0) -#endif - -#ifdef CONFIG_MACH_PEPPERPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PEPPERPAD -# endif -# define machine_is_pepperpad() (machine_arch_type == MACH_TYPE_PEPPERPAD) -#else -# define machine_is_pepperpad() (0) -#endif - -#ifdef CONFIG_MACH_SB3010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SB3010 -# endif -# define machine_is_sb3010() (machine_arch_type == MACH_TYPE_SB3010) -#else -# define machine_is_sb3010() (0) -#endif - -#ifdef CONFIG_MACH_RM9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RM9200 -# endif -# define machine_is_rm9200() (machine_arch_type == MACH_TYPE_RM9200) -#else -# define machine_is_rm9200() (0) -#endif - -#ifdef CONFIG_MACH_DMA03 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DMA03 -# endif -# define machine_is_dma03() (machine_arch_type == MACH_TYPE_DMA03) -#else -# define machine_is_dma03() (0) -#endif - -#ifdef CONFIG_MACH_ROAD_S101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROAD_S101 -# endif -# define machine_is_road_s101() (machine_arch_type == MACH_TYPE_ROAD_S101) -#else -# define machine_is_road_s101() (0) -#endif - -#ifdef CONFIG_MACH_IQ81340SC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ81340SC -# endif -# define machine_is_iq81340sc() (machine_arch_type == MACH_TYPE_IQ81340SC) -#else -# define machine_is_iq81340sc() (0) -#endif - -#ifdef CONFIG_MACH_IQ_NEXTGEN_B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_B -# endif -# define machine_is_iq_nextgen_b() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_B) -#else -# define machine_is_iq_nextgen_b() (0) -#endif - -#ifdef CONFIG_MACH_IQ81340MC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ81340MC -# endif -# define machine_is_iq81340mc() (machine_arch_type == MACH_TYPE_IQ81340MC) -#else -# define machine_is_iq81340mc() (0) -#endif - -#ifdef CONFIG_MACH_IQ_NEXTGEN_D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_D -# endif -# define machine_is_iq_nextgen_d() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_D) -#else -# define machine_is_iq_nextgen_d() (0) -#endif - -#ifdef CONFIG_MACH_IQ_NEXTGEN_E -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_E -# endif -# define machine_is_iq_nextgen_e() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_E) -#else -# define machine_is_iq_nextgen_e() (0) -#endif - -#ifdef CONFIG_MACH_MALLOW_AT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MALLOW_AT91 -# endif -# define machine_is_mallow_at91() (machine_arch_type == MACH_TYPE_MALLOW_AT91) -#else -# define machine_is_mallow_at91() (0) -#endif - -#ifdef CONFIG_MACH_CYBERTRACKER_I -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYBERTRACKER_I -# endif -# define machine_is_cybertracker_i() (machine_arch_type == MACH_TYPE_CYBERTRACKER_I) -#else -# define machine_is_cybertracker_i() (0) -#endif - -#ifdef CONFIG_MACH_GESBC931X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GESBC931X -# endif -# define machine_is_gesbc931x() (machine_arch_type == MACH_TYPE_GESBC931X) -#else -# define machine_is_gesbc931x() (0) -#endif - -#ifdef CONFIG_MACH_CENTIPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CENTIPAD -# endif -# define machine_is_centipad() (machine_arch_type == MACH_TYPE_CENTIPAD) -#else -# define machine_is_centipad() (0) -#endif - -#ifdef CONFIG_MACH_ARMSOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMSOC -# endif -# define machine_is_armsoc() (machine_arch_type == MACH_TYPE_ARMSOC) -#else -# define machine_is_armsoc() (0) -#endif - -#ifdef CONFIG_MACH_SE4200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE4200 -# endif -# define machine_is_se4200() (machine_arch_type == MACH_TYPE_SE4200) -#else -# define machine_is_se4200() (0) -#endif - -#ifdef CONFIG_MACH_EMS197A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMS197A -# endif -# define machine_is_ems197a() (machine_arch_type == MACH_TYPE_EMS197A) -#else -# define machine_is_ems197a() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9 -# endif -# define machine_is_micro9() (machine_arch_type == MACH_TYPE_MICRO9) -#else -# define machine_is_micro9() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9L -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9L -# endif -# define machine_is_micro9l() (machine_arch_type == MACH_TYPE_MICRO9L) -#else -# define machine_is_micro9l() (0) -#endif - -#ifdef CONFIG_MACH_UC5471DSP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UC5471DSP -# endif -# define machine_is_uc5471dsp() (machine_arch_type == MACH_TYPE_UC5471DSP) -#else -# define machine_is_uc5471dsp() (0) -#endif - -#ifdef CONFIG_MACH_SJ5471ENG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SJ5471ENG -# endif -# define machine_is_sj5471eng() (machine_arch_type == MACH_TYPE_SJ5471ENG) -#else -# define machine_is_sj5471eng() (0) -#endif - -#ifdef CONFIG_MACH_CMPXA26X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CMPXA26X -# endif -# define machine_is_none() (machine_arch_type == MACH_TYPE_CMPXA26X) -#else -# define machine_is_none() (0) -#endif - -#ifdef CONFIG_MACH_NC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NC -# endif -# define machine_is_nc1() (machine_arch_type == MACH_TYPE_NC) -#else -# define machine_is_nc1() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMTE -# endif -# define machine_is_omap_palmte() (machine_arch_type == MACH_TYPE_OMAP_PALMTE) -#else -# define machine_is_omap_palmte() (0) -#endif - -#ifdef CONFIG_MACH_AJAX52X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AJAX52X -# endif -# define machine_is_ajax52x() (machine_arch_type == MACH_TYPE_AJAX52X) -#else -# define machine_is_ajax52x() (0) -#endif - -#ifdef CONFIG_MACH_SIRIUSTAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIRIUSTAR -# endif -# define machine_is_siriustar() (machine_arch_type == MACH_TYPE_SIRIUSTAR) -#else -# define machine_is_siriustar() (0) -#endif - -#ifdef CONFIG_MACH_IODATA_HDLG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IODATA_HDLG -# endif -# define machine_is_iodata_hdlg() (machine_arch_type == MACH_TYPE_IODATA_HDLG) -#else -# define machine_is_iodata_hdlg() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200UTL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200UTL -# endif -# define machine_is_at91rm9200utl() (machine_arch_type == MACH_TYPE_AT91RM9200UTL) -#else -# define machine_is_at91rm9200utl() (0) -#endif - -#ifdef CONFIG_MACH_BIOSAFE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIOSAFE -# endif -# define machine_is_biosafe() (machine_arch_type == MACH_TYPE_BIOSAFE) -#else -# define machine_is_biosafe() (0) -#endif - -#ifdef CONFIG_MACH_MP1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MP1000 -# endif -# define machine_is_mp1000() (machine_arch_type == MACH_TYPE_MP1000) -#else -# define machine_is_mp1000() (0) -#endif - -#ifdef CONFIG_MACH_PARSY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PARSY -# endif -# define machine_is_parsy() (machine_arch_type == MACH_TYPE_PARSY) -#else -# define machine_is_parsy() (0) -#endif - -#ifdef CONFIG_MACH_CCXP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCXP -# endif -# define machine_is_ccxp270() (machine_arch_type == MACH_TYPE_CCXP) -#else -# define machine_is_ccxp270() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_GSAMPLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_GSAMPLE -# endif -# define machine_is_omap_gsample() (machine_arch_type == MACH_TYPE_OMAP_GSAMPLE) -#else -# define machine_is_omap_gsample() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_EB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_EB -# endif -# define machine_is_realview_eb() (machine_arch_type == MACH_TYPE_REALVIEW_EB) -#else -# define machine_is_realview_eb() (0) -#endif - -#ifdef CONFIG_MACH_SAMOA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAMOA -# endif -# define machine_is_samoa() (machine_arch_type == MACH_TYPE_SAMOA) -#else -# define machine_is_samoa() (0) -#endif - -#ifdef CONFIG_MACH_PALMT3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMT3 -# endif -# define machine_is_palmt3() (machine_arch_type == MACH_TYPE_PALMT3) -#else -# define machine_is_palmt3() (0) -#endif - -#ifdef CONFIG_MACH_I878 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I878 -# endif -# define machine_is_i878() (machine_arch_type == MACH_TYPE_I878) -#else -# define machine_is_i878() (0) -#endif - -#ifdef CONFIG_MACH_BORZOI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BORZOI -# endif -# define machine_is_borzoi() (machine_arch_type == MACH_TYPE_BORZOI) -#else -# define machine_is_borzoi() (0) -#endif - -#ifdef CONFIG_MACH_GECKO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GECKO -# endif -# define machine_is_gecko() (machine_arch_type == MACH_TYPE_GECKO) -#else -# define machine_is_gecko() (0) -#endif - -#ifdef CONFIG_MACH_DS101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS101 -# endif -# define machine_is_ds101() (machine_arch_type == MACH_TYPE_DS101) -#else -# define machine_is_ds101() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMTT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMTT2 -# endif -# define machine_is_omap_palmtt2() (machine_arch_type == MACH_TYPE_OMAP_PALMTT2) -#else -# define machine_is_omap_palmtt2() (0) -#endif - -#ifdef CONFIG_MACH_PALMLD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMLD -# endif -# define machine_is_palmld() (machine_arch_type == MACH_TYPE_PALMLD) -#else -# define machine_is_palmld() (0) -#endif - -#ifdef CONFIG_MACH_CC9C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9C -# endif -# define machine_is_cc9c() (machine_arch_type == MACH_TYPE_CC9C) -#else -# define machine_is_cc9c() (0) -#endif - -#ifdef CONFIG_MACH_SBC1670 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC1670 -# endif -# define machine_is_sbc1670() (machine_arch_type == MACH_TYPE_SBC1670) -#else -# define machine_is_sbc1670() (0) -#endif - -#ifdef CONFIG_MACH_IXDP28X5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP28X5 -# endif -# define machine_is_ixdp28x5() (machine_arch_type == MACH_TYPE_IXDP28X5) -#else -# define machine_is_ixdp28x5() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMTT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMTT -# endif -# define machine_is_omap_palmtt() (machine_arch_type == MACH_TYPE_OMAP_PALMTT) -#else -# define machine_is_omap_palmtt() (0) -#endif - -#ifdef CONFIG_MACH_ML696K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ML696K -# endif -# define machine_is_ml696k() (machine_arch_type == MACH_TYPE_ML696K) -#else -# define machine_is_ml696k() (0) -#endif - -#ifdef CONFIG_MACH_ARCOM_ZEUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCOM_ZEUS -# endif -# define machine_is_arcom_zeus() (machine_arch_type == MACH_TYPE_ARCOM_ZEUS) -#else -# define machine_is_arcom_zeus() (0) -#endif - -#ifdef CONFIG_MACH_OSIRIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSIRIS -# endif -# define machine_is_osiris() (machine_arch_type == MACH_TYPE_OSIRIS) -#else -# define machine_is_osiris() (0) -#endif - -#ifdef CONFIG_MACH_MAESTRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAESTRO -# endif -# define machine_is_maestro() (machine_arch_type == MACH_TYPE_MAESTRO) -#else -# define machine_is_maestro() (0) -#endif - -#ifdef CONFIG_MACH_PALMTE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTE2 -# endif -# define machine_is_palmte2() (machine_arch_type == MACH_TYPE_PALMTE2) -#else -# define machine_is_palmte2() (0) -#endif - -#ifdef CONFIG_MACH_IXBBM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXBBM -# endif -# define machine_is_ixbbm() (machine_arch_type == MACH_TYPE_IXBBM) -#else -# define machine_is_ixbbm() (0) -#endif - -#ifdef CONFIG_MACH_MX27ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX27ADS -# endif -# define machine_is_mx27ads() (machine_arch_type == MACH_TYPE_MX27ADS) -#else -# define machine_is_mx27ads() (0) -#endif - -#ifdef CONFIG_MACH_AX8004 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AX8004 -# endif -# define machine_is_ax8004() (machine_arch_type == MACH_TYPE_AX8004) -#else -# define machine_is_ax8004() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9261EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9261EK -# endif -# define machine_is_at91sam9261ek() (machine_arch_type == MACH_TYPE_AT91SAM9261EK) -#else -# define machine_is_at91sam9261ek() (0) -#endif - -#ifdef CONFIG_MACH_LOFT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOFT -# endif -# define machine_is_loft() (machine_arch_type == MACH_TYPE_LOFT) -#else -# define machine_is_loft() (0) -#endif - -#ifdef CONFIG_MACH_MAGPIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGPIE -# endif -# define machine_is_magpie() (machine_arch_type == MACH_TYPE_MAGPIE) -#else -# define machine_is_magpie() (0) -#endif - -#ifdef CONFIG_MACH_MX21ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX21ADS -# endif -# define machine_is_mx21ads() (machine_arch_type == MACH_TYPE_MX21ADS) -#else -# define machine_is_mx21ads() (0) -#endif - -#ifdef CONFIG_MACH_MB87M3400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB87M3400 -# endif -# define machine_is_mb87m3400() (machine_arch_type == MACH_TYPE_MB87M3400) -#else -# define machine_is_mb87m3400() (0) -#endif - -#ifdef CONFIG_MACH_MGUARD_DELTA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MGUARD_DELTA -# endif -# define machine_is_mguard_delta() (machine_arch_type == MACH_TYPE_MGUARD_DELTA) -#else -# define machine_is_mguard_delta() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DVDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DVDP -# endif -# define machine_is_davinci_dvdp() (machine_arch_type == MACH_TYPE_DAVINCI_DVDP) -#else -# define machine_is_davinci_dvdp() (0) -#endif - -#ifdef CONFIG_MACH_HTCUNIVERSAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCUNIVERSAL -# endif -# define machine_is_htcuniversal() (machine_arch_type == MACH_TYPE_HTCUNIVERSAL) -#else -# define machine_is_htcuniversal() (0) -#endif - -#ifdef CONFIG_MACH_TPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPAD -# endif -# define machine_is_tpad() (machine_arch_type == MACH_TYPE_TPAD) -#else -# define machine_is_tpad() (0) -#endif - -#ifdef CONFIG_MACH_ROVERP3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERP3 -# endif -# define machine_is_roverp3() (machine_arch_type == MACH_TYPE_ROVERP3) -#else -# define machine_is_roverp3() (0) -#endif - -#ifdef CONFIG_MACH_JORNADA928 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JORNADA928 -# endif -# define machine_is_jornada928() (machine_arch_type == MACH_TYPE_JORNADA928) -#else -# define machine_is_jornada928() (0) -#endif - -#ifdef CONFIG_MACH_MV88FXX81 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV88FXX81 -# endif -# define machine_is_mv88fxx81() (machine_arch_type == MACH_TYPE_MV88FXX81) -#else -# define machine_is_mv88fxx81() (0) -#endif - -#ifdef CONFIG_MACH_STMP36XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STMP36XX -# endif -# define machine_is_stmp36xx() (machine_arch_type == MACH_TYPE_STMP36XX) -#else -# define machine_is_stmp36xx() (0) -#endif - -#ifdef CONFIG_MACH_SXNI79524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SXNI79524 -# endif -# define machine_is_sxni79524() (machine_arch_type == MACH_TYPE_SXNI79524) -#else -# define machine_is_sxni79524() (0) -#endif - -#ifdef CONFIG_MACH_AMS_DELTA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AMS_DELTA -# endif -# define machine_is_ams_delta() (machine_arch_type == MACH_TYPE_AMS_DELTA) -#else -# define machine_is_ams_delta() (0) -#endif - -#ifdef CONFIG_MACH_URANIUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_URANIUM -# endif -# define machine_is_uranium() (machine_arch_type == MACH_TYPE_URANIUM) -#else -# define machine_is_uranium() (0) -#endif - -#ifdef CONFIG_MACH_UCON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UCON -# endif -# define machine_is_ucon() (machine_arch_type == MACH_TYPE_UCON) -#else -# define machine_is_ucon() (0) -#endif - -#ifdef CONFIG_MACH_NAS100D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAS100D -# endif -# define machine_is_nas100d() (machine_arch_type == MACH_TYPE_NAS100D) -#else -# define machine_is_nas100d() (0) -#endif - -#ifdef CONFIG_MACH_L083_1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_L083_1000 -# endif -# define machine_is_l083() (machine_arch_type == MACH_TYPE_L083_1000) -#else -# define machine_is_l083() (0) -#endif - -#ifdef CONFIG_MACH_EZX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX -# endif -# define machine_is_ezx() (machine_arch_type == MACH_TYPE_EZX) -#else -# define machine_is_ezx() (0) -#endif - -#ifdef CONFIG_MACH_PNX5220 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX5220 -# endif -# define machine_is_pnx5220() (machine_arch_type == MACH_TYPE_PNX5220) -#else -# define machine_is_pnx5220() (0) -#endif - -#ifdef CONFIG_MACH_BUTTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUTTE -# endif -# define machine_is_butte() (machine_arch_type == MACH_TYPE_BUTTE) -#else -# define machine_is_butte() (0) -#endif - -#ifdef CONFIG_MACH_SRM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SRM2 -# endif -# define machine_is_srm2() (machine_arch_type == MACH_TYPE_SRM2) -#else -# define machine_is_srm2() (0) -#endif - -#ifdef CONFIG_MACH_DSBR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSBR -# endif -# define machine_is_dsbr() (machine_arch_type == MACH_TYPE_DSBR) -#else -# define machine_is_dsbr() (0) -#endif - -#ifdef CONFIG_MACH_CRYSTALBALL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CRYSTALBALL -# endif -# define machine_is_crystalball() (machine_arch_type == MACH_TYPE_CRYSTALBALL) -#else -# define machine_is_crystalball() (0) -#endif - -#ifdef CONFIG_MACH_TINYPXA27X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TINYPXA27X -# endif -# define machine_is_tinypxa27x() (machine_arch_type == MACH_TYPE_TINYPXA27X) -#else -# define machine_is_tinypxa27x() (0) -#endif - -#ifdef CONFIG_MACH_HERBIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERBIE -# endif -# define machine_is_herbie() (machine_arch_type == MACH_TYPE_HERBIE) -#else -# define machine_is_herbie() (0) -#endif - -#ifdef CONFIG_MACH_MAGICIAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGICIAN -# endif -# define machine_is_magician() (machine_arch_type == MACH_TYPE_MAGICIAN) -#else -# define machine_is_magician() (0) -#endif - -#ifdef CONFIG_MACH_CM4002 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM4002 -# endif -# define machine_is_cm4002() (machine_arch_type == MACH_TYPE_CM4002) -#else -# define machine_is_cm4002() (0) -#endif - -#ifdef CONFIG_MACH_B4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_B4 -# endif -# define machine_is_b4() (machine_arch_type == MACH_TYPE_B4) -#else -# define machine_is_b4() (0) -#endif - -#ifdef CONFIG_MACH_MAUI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAUI -# endif -# define machine_is_maui() (machine_arch_type == MACH_TYPE_MAUI) -#else -# define machine_is_maui() (0) -#endif - -#ifdef CONFIG_MACH_CYBERTRACKER_G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYBERTRACKER_G -# endif -# define machine_is_cybertracker_g() (machine_arch_type == MACH_TYPE_CYBERTRACKER_G) -#else -# define machine_is_cybertracker_g() (0) -#endif - -#ifdef CONFIG_MACH_NXDKN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXDKN -# endif -# define machine_is_nxdkn() (machine_arch_type == MACH_TYPE_NXDKN) -#else -# define machine_is_nxdkn() (0) -#endif - -#ifdef CONFIG_MACH_MIO8390 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIO8390 -# endif -# define machine_is_mio8390() (machine_arch_type == MACH_TYPE_MIO8390) -#else -# define machine_is_mio8390() (0) -#endif - -#ifdef CONFIG_MACH_OMI_BOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMI_BOARD -# endif -# define machine_is_omi_board() (machine_arch_type == MACH_TYPE_OMI_BOARD) -#else -# define machine_is_omi_board() (0) -#endif - -#ifdef CONFIG_MACH_MX21CIV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX21CIV -# endif -# define machine_is_mx21civ() (machine_arch_type == MACH_TYPE_MX21CIV) -#else -# define machine_is_mx21civ() (0) -#endif - -#ifdef CONFIG_MACH_MAHI_CDAC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAHI_CDAC -# endif -# define machine_is_mahi_cdac() (machine_arch_type == MACH_TYPE_MAHI_CDAC) -#else -# define machine_is_mahi_cdac() (0) -#endif - -#ifdef CONFIG_MACH_PALMTX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTX -# endif -# define machine_is_palmtx() (machine_arch_type == MACH_TYPE_PALMTX) -#else -# define machine_is_palmtx() (0) -#endif - -#ifdef CONFIG_MACH_S3C2413 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2413 -# endif -# define machine_is_s3c2413() (machine_arch_type == MACH_TYPE_S3C2413) -#else -# define machine_is_s3c2413() (0) -#endif - -#ifdef CONFIG_MACH_SAMSYS_EP0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAMSYS_EP0 -# endif -# define machine_is_samsys_ep0() (machine_arch_type == MACH_TYPE_SAMSYS_EP0) -#else -# define machine_is_samsys_ep0() (0) -#endif - -#ifdef CONFIG_MACH_WG302V1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WG302V1 -# endif -# define machine_is_wg302v1() (machine_arch_type == MACH_TYPE_WG302V1) -#else -# define machine_is_wg302v1() (0) -#endif - -#ifdef CONFIG_MACH_WG302V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WG302V2 -# endif -# define machine_is_wg302v2() (machine_arch_type == MACH_TYPE_WG302V2) -#else -# define machine_is_wg302v2() (0) -#endif - -#ifdef CONFIG_MACH_EB42X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EB42X -# endif -# define machine_is_eb42x() (machine_arch_type == MACH_TYPE_EB42X) -#else -# define machine_is_eb42x() (0) -#endif - -#ifdef CONFIG_MACH_IQ331ES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ331ES -# endif -# define machine_is_iq331es() (machine_arch_type == MACH_TYPE_IQ331ES) -#else -# define machine_is_iq331es() (0) -#endif - -#ifdef CONFIG_MACH_COSYDSP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COSYDSP -# endif -# define machine_is_cosydsp() (machine_arch_type == MACH_TYPE_COSYDSP) -#else -# define machine_is_cosydsp() (0) -#endif - -#ifdef CONFIG_MACH_UPLAT7D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UPLAT7D -# endif -# define machine_is_uplat7d_proto() (machine_arch_type == MACH_TYPE_UPLAT7D) -#else -# define machine_is_uplat7d_proto() (0) -#endif - -#ifdef CONFIG_MACH_PTDAVINCI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PTDAVINCI -# endif -# define machine_is_ptdavinci() (machine_arch_type == MACH_TYPE_PTDAVINCI) -#else -# define machine_is_ptdavinci() (0) -#endif - -#ifdef CONFIG_MACH_MBUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MBUS -# endif -# define machine_is_mbus() (machine_arch_type == MACH_TYPE_MBUS) -#else -# define machine_is_mbus() (0) -#endif - -#ifdef CONFIG_MACH_NADIA2VB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NADIA2VB -# endif -# define machine_is_nadia2vb() (machine_arch_type == MACH_TYPE_NADIA2VB) -#else -# define machine_is_nadia2vb() (0) -#endif - -#ifdef CONFIG_MACH_R1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_R1000 -# endif -# define machine_is_r1000() (machine_arch_type == MACH_TYPE_R1000) -#else -# define machine_is_r1000() (0) -#endif - -#ifdef CONFIG_MACH_HW90250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW90250 -# endif -# define machine_is_hw90250() (machine_arch_type == MACH_TYPE_HW90250) -#else -# define machine_is_hw90250() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_2430SDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_2430SDP -# endif -# define machine_is_omap_2430sdp() (machine_arch_type == MACH_TYPE_OMAP_2430SDP) -#else -# define machine_is_omap_2430sdp() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_EVM -# endif -# define machine_is_davinci_evm() (machine_arch_type == MACH_TYPE_DAVINCI_EVM) -#else -# define machine_is_davinci_evm() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_TORNADO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_TORNADO -# endif -# define machine_is_omap_tornado() (machine_arch_type == MACH_TYPE_OMAP_TORNADO) -#else -# define machine_is_omap_tornado() (0) -#endif - -#ifdef CONFIG_MACH_OLOCREEK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OLOCREEK -# endif -# define machine_is_olocreek() (machine_arch_type == MACH_TYPE_OLOCREEK) -#else -# define machine_is_olocreek() (0) -#endif - -#ifdef CONFIG_MACH_PALMZ72 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMZ72 -# endif -# define machine_is_palmz72() (machine_arch_type == MACH_TYPE_PALMZ72) -#else -# define machine_is_palmz72() (0) -#endif - -#ifdef CONFIG_MACH_NXDB500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXDB500 -# endif -# define machine_is_nxdb500() (machine_arch_type == MACH_TYPE_NXDB500) -#else -# define machine_is_nxdb500() (0) -#endif - -#ifdef CONFIG_MACH_APF9328 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APF9328 -# endif -# define machine_is_apf9328() (machine_arch_type == MACH_TYPE_APF9328) -#else -# define machine_is_apf9328() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_WIPOQ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_WIPOQ -# endif -# define machine_is_omap_wipoq() (machine_arch_type == MACH_TYPE_OMAP_WIPOQ) -#else -# define machine_is_omap_wipoq() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_TWIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_TWIP -# endif -# define machine_is_omap_twip() (machine_arch_type == MACH_TYPE_OMAP_TWIP) -#else -# define machine_is_omap_twip() (0) -#endif - -#ifdef CONFIG_MACH_PALMT650 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMT650 -# endif -# define machine_is_palmt650() (machine_arch_type == MACH_TYPE_PALMT650) -#else -# define machine_is_palmt650() (0) -#endif - -#ifdef CONFIG_MACH_ACUMEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACUMEN -# endif -# define machine_is_acumen() (machine_arch_type == MACH_TYPE_ACUMEN) -#else -# define machine_is_acumen() (0) -#endif - -#ifdef CONFIG_MACH_XP100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XP100 -# endif -# define machine_is_xp100() (machine_arch_type == MACH_TYPE_XP100) -#else -# define machine_is_xp100() (0) -#endif - -#ifdef CONFIG_MACH_FS2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FS2410 -# endif -# define machine_is_fs2410() (machine_arch_type == MACH_TYPE_FS2410) -#else -# define machine_is_fs2410() (0) -#endif - -#ifdef CONFIG_MACH_PXA270_CERF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA270_CERF -# endif -# define machine_is_pxa270_cerf() (machine_arch_type == MACH_TYPE_PXA270_CERF) -#else -# define machine_is_pxa270_cerf() (0) -#endif - -#ifdef CONFIG_MACH_SQ2FTLPALM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SQ2FTLPALM -# endif -# define machine_is_sq2ftlpalm() (machine_arch_type == MACH_TYPE_SQ2FTLPALM) -#else -# define machine_is_sq2ftlpalm() (0) -#endif - -#ifdef CONFIG_MACH_BSEMSERVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BSEMSERVER -# endif -# define machine_is_bsemserver() (machine_arch_type == MACH_TYPE_BSEMSERVER) -#else -# define machine_is_bsemserver() (0) -#endif - -#ifdef CONFIG_MACH_NETCLIENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETCLIENT -# endif -# define machine_is_netclient() (machine_arch_type == MACH_TYPE_NETCLIENT) -#else -# define machine_is_netclient() (0) -#endif - -#ifdef CONFIG_MACH_PALMT5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMT5 -# endif -# define machine_is_palmt5() (machine_arch_type == MACH_TYPE_PALMT5) -#else -# define machine_is_palmt5() (0) -#endif - -#ifdef CONFIG_MACH_PALMTC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTC -# endif -# define machine_is_palmtc() (machine_arch_type == MACH_TYPE_PALMTC) -#else -# define machine_is_palmtc() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_APOLLON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_APOLLON -# endif -# define machine_is_omap_apollon() (machine_arch_type == MACH_TYPE_OMAP_APOLLON) -#else -# define machine_is_omap_apollon() (0) -#endif - -#ifdef CONFIG_MACH_MXC30030EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30030EVB -# endif -# define machine_is_mxc30030evb() (machine_arch_type == MACH_TYPE_MXC30030EVB) -#else -# define machine_is_mxc30030evb() (0) -#endif - -#ifdef CONFIG_MACH_REA_2D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REA_2D -# endif -# define machine_is_rea_2d() (machine_arch_type == MACH_TYPE_REA_2D) -#else -# define machine_is_rea_2d() (0) -#endif - -#ifdef CONFIG_MACH_TI3E524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TI3E524 -# endif -# define machine_is_eti3e524() (machine_arch_type == MACH_TYPE_TI3E524) -#else -# define machine_is_eti3e524() (0) -#endif - -#ifdef CONFIG_MACH_ATEB9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATEB9200 -# endif -# define machine_is_ateb9200() (machine_arch_type == MACH_TYPE_ATEB9200) -#else -# define machine_is_ateb9200() (0) -#endif - -#ifdef CONFIG_MACH_AUCKLAND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AUCKLAND -# endif -# define machine_is_auckland() (machine_arch_type == MACH_TYPE_AUCKLAND) -#else -# define machine_is_auckland() (0) -#endif - -#ifdef CONFIG_MACH_AK3320M -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AK3320M -# endif -# define machine_is_ak3220m() (machine_arch_type == MACH_TYPE_AK3320M) -#else -# define machine_is_ak3220m() (0) -#endif - -#ifdef CONFIG_MACH_DURAMAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DURAMAX -# endif -# define machine_is_duramax() (machine_arch_type == MACH_TYPE_DURAMAX) -#else -# define machine_is_duramax() (0) -#endif - -#ifdef CONFIG_MACH_N35 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N35 -# endif -# define machine_is_n35() (machine_arch_type == MACH_TYPE_N35) -#else -# define machine_is_n35() (0) -#endif - -#ifdef CONFIG_MACH_PRONGHORN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRONGHORN -# endif -# define machine_is_pronghorn() (machine_arch_type == MACH_TYPE_PRONGHORN) -#else -# define machine_is_pronghorn() (0) -#endif - -#ifdef CONFIG_MACH_FUNDY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FUNDY -# endif -# define machine_is_fundy() (machine_arch_type == MACH_TYPE_FUNDY) -#else -# define machine_is_fundy() (0) -#endif - -#ifdef CONFIG_MACH_LOGICPD_PXA270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOGICPD_PXA270 -# endif -# define machine_is_logicpd_pxa270() (machine_arch_type == MACH_TYPE_LOGICPD_PXA270) -#else -# define machine_is_logicpd_pxa270() (0) -#endif - -#ifdef CONFIG_MACH_CPU777 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPU777 -# endif -# define machine_is_cpu777() (machine_arch_type == MACH_TYPE_CPU777) -#else -# define machine_is_cpu777() (0) -#endif - -#ifdef CONFIG_MACH_SIMICON9201 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIMICON9201 -# endif -# define machine_is_simicon9201() (machine_arch_type == MACH_TYPE_SIMICON9201) -#else -# define machine_is_simicon9201() (0) -#endif - -#ifdef CONFIG_MACH_LEAP2_HPM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEAP2_HPM -# endif -# define machine_is_leap2_hpm() (machine_arch_type == MACH_TYPE_LEAP2_HPM) -#else -# define machine_is_leap2_hpm() (0) -#endif - -#ifdef CONFIG_MACH_CM922TXA10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM922TXA10 -# endif -# define machine_is_cm922txa10() (machine_arch_type == MACH_TYPE_CM922TXA10) -#else -# define machine_is_cm922txa10() (0) -#endif - -#ifdef CONFIG_MACH_PXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA -# endif -# define machine_is_sandgate() (machine_arch_type == MACH_TYPE_PXA) -#else -# define machine_is_sandgate() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATE2 -# endif -# define machine_is_sandgate2() (machine_arch_type == MACH_TYPE_SANDGATE2) -#else -# define machine_is_sandgate2() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATE2G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATE2G -# endif -# define machine_is_sandgate2g() (machine_arch_type == MACH_TYPE_SANDGATE2G) -#else -# define machine_is_sandgate2g() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATE2P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATE2P -# endif -# define machine_is_sandgate2p() (machine_arch_type == MACH_TYPE_SANDGATE2P) -#else -# define machine_is_sandgate2p() (0) -#endif - -#ifdef CONFIG_MACH_FRED_JACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FRED_JACK -# endif -# define machine_is_fred_jack() (machine_arch_type == MACH_TYPE_FRED_JACK) -#else -# define machine_is_fred_jack() (0) -#endif - -#ifdef CONFIG_MACH_TTG_COLOR1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TTG_COLOR1 -# endif -# define machine_is_ttg_color1() (machine_arch_type == MACH_TYPE_TTG_COLOR1) -#else -# define machine_is_ttg_color1() (0) -#endif - -#ifdef CONFIG_MACH_NXEB500HMI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXEB500HMI -# endif -# define machine_is_nxeb500hmi() (machine_arch_type == MACH_TYPE_NXEB500HMI) -#else -# define machine_is_nxeb500hmi() (0) -#endif - -#ifdef CONFIG_MACH_NETDCU8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETDCU8 -# endif -# define machine_is_netdcu8() (machine_arch_type == MACH_TYPE_NETDCU8) -#else -# define machine_is_netdcu8() (0) -#endif - -#ifdef CONFIG_MACH_NG_FVX538 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NG_FVX538 -# endif -# define machine_is_ng_fvx538() (machine_arch_type == MACH_TYPE_NG_FVX538) -#else -# define machine_is_ng_fvx538() (0) -#endif - -#ifdef CONFIG_MACH_NG_FVS338 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NG_FVS338 -# endif -# define machine_is_ng_fvs338() (machine_arch_type == MACH_TYPE_NG_FVS338) -#else -# define machine_is_ng_fvs338() (0) -#endif - -#ifdef CONFIG_MACH_PNX4103 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX4103 -# endif -# define machine_is_pnx4103() (machine_arch_type == MACH_TYPE_PNX4103) -#else -# define machine_is_pnx4103() (0) -#endif - -#ifdef CONFIG_MACH_HESDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HESDB -# endif -# define machine_is_hesdb() (machine_arch_type == MACH_TYPE_HESDB) -#else -# define machine_is_hesdb() (0) -#endif - -#ifdef CONFIG_MACH_XSILO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XSILO -# endif -# define machine_is_xsilo() (machine_arch_type == MACH_TYPE_XSILO) -#else -# define machine_is_xsilo() (0) -#endif - -#ifdef CONFIG_MACH_ESPRESSO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESPRESSO -# endif -# define machine_is_espresso() (machine_arch_type == MACH_TYPE_ESPRESSO) -#else -# define machine_is_espresso() (0) -#endif - -#ifdef CONFIG_MACH_EMLC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMLC -# endif -# define machine_is_emlc() (machine_arch_type == MACH_TYPE_EMLC) -#else -# define machine_is_emlc() (0) -#endif - -#ifdef CONFIG_MACH_SISTERON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SISTERON -# endif -# define machine_is_sisteron() (machine_arch_type == MACH_TYPE_SISTERON) -#else -# define machine_is_sisteron() (0) -#endif - -#ifdef CONFIG_MACH_RX1950 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RX1950 -# endif -# define machine_is_rx1950() (machine_arch_type == MACH_TYPE_RX1950) -#else -# define machine_is_rx1950() (0) -#endif - -#ifdef CONFIG_MACH_TSC_VENUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TSC_VENUS -# endif -# define machine_is_tsc_venus() (machine_arch_type == MACH_TYPE_TSC_VENUS) -#else -# define machine_is_tsc_venus() (0) -#endif - -#ifdef CONFIG_MACH_DS101J -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS101J -# endif -# define machine_is_ds101j() (machine_arch_type == MACH_TYPE_DS101J) -#else -# define machine_is_ds101j() (0) -#endif - -#ifdef CONFIG_MACH_MXC30030ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30030ADS -# endif -# define machine_is_mxc30030ads() (machine_arch_type == MACH_TYPE_MXC30030ADS) -#else -# define machine_is_mxc30030ads() (0) -#endif - -#ifdef CONFIG_MACH_FUJITSU_WIMAXSOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FUJITSU_WIMAXSOC -# endif -# define machine_is_fujitsu_wimaxsoc() (machine_arch_type == MACH_TYPE_FUJITSU_WIMAXSOC) -#else -# define machine_is_fujitsu_wimaxsoc() (0) -#endif - -#ifdef CONFIG_MACH_DUALPCMODEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DUALPCMODEM -# endif -# define machine_is_dualpcmodem() (machine_arch_type == MACH_TYPE_DUALPCMODEM) -#else -# define machine_is_dualpcmodem() (0) -#endif - -#ifdef CONFIG_MACH_GESBC9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GESBC9312 -# endif -# define machine_is_gesbc9312() (machine_arch_type == MACH_TYPE_GESBC9312) -#else -# define machine_is_gesbc9312() (0) -#endif - -#ifdef CONFIG_MACH_HTCAPACHE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCAPACHE -# endif -# define machine_is_htcapache() (machine_arch_type == MACH_TYPE_HTCAPACHE) -#else -# define machine_is_htcapache() (0) -#endif - -#ifdef CONFIG_MACH_IXDP435 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP435 -# endif -# define machine_is_ixdp435() (machine_arch_type == MACH_TYPE_IXDP435) -#else -# define machine_is_ixdp435() (0) -#endif - -#ifdef CONFIG_MACH_CATPROVT100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CATPROVT100 -# endif -# define machine_is_catprovt100() (machine_arch_type == MACH_TYPE_CATPROVT100) -#else -# define machine_is_catprovt100() (0) -#endif - -#ifdef CONFIG_MACH_PICOTUX1XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOTUX1XX -# endif -# define machine_is_picotux1xx() (machine_arch_type == MACH_TYPE_PICOTUX1XX) -#else -# define machine_is_picotux1xx() (0) -#endif - -#ifdef CONFIG_MACH_PICOTUX2XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOTUX2XX -# endif -# define machine_is_picotux2xx() (machine_arch_type == MACH_TYPE_PICOTUX2XX) -#else -# define machine_is_picotux2xx() (0) -#endif - -#ifdef CONFIG_MACH_DSMG600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSMG600 -# endif -# define machine_is_dsmg600() (machine_arch_type == MACH_TYPE_DSMG600) -#else -# define machine_is_dsmg600() (0) -#endif - -#ifdef CONFIG_MACH_EMPC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPC2 -# endif -# define machine_is_empc2() (machine_arch_type == MACH_TYPE_EMPC2) -#else -# define machine_is_empc2() (0) -#endif - -#ifdef CONFIG_MACH_VENTURA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VENTURA -# endif -# define machine_is_ventura() (machine_arch_type == MACH_TYPE_VENTURA) -#else -# define machine_is_ventura() (0) -#endif - -#ifdef CONFIG_MACH_PHIDGET_SBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHIDGET_SBC -# endif -# define machine_is_phidget_sbc() (machine_arch_type == MACH_TYPE_PHIDGET_SBC) -#else -# define machine_is_phidget_sbc() (0) -#endif - -#ifdef CONFIG_MACH_IJ3K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IJ3K -# endif -# define machine_is_ij3k() (machine_arch_type == MACH_TYPE_IJ3K) -#else -# define machine_is_ij3k() (0) -#endif - -#ifdef CONFIG_MACH_PISGAH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PISGAH -# endif -# define machine_is_pisgah() (machine_arch_type == MACH_TYPE_PISGAH) -#else -# define machine_is_pisgah() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_FSAMPLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_FSAMPLE -# endif -# define machine_is_omap_fsample() (machine_arch_type == MACH_TYPE_OMAP_FSAMPLE) -#else -# define machine_is_omap_fsample() (0) -#endif - -#ifdef CONFIG_MACH_SG720 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG720 -# endif -# define machine_is_sg720() (machine_arch_type == MACH_TYPE_SG720) -#else -# define machine_is_sg720() (0) -#endif - -#ifdef CONFIG_MACH_REDFOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REDFOX -# endif -# define machine_is_redfox() (machine_arch_type == MACH_TYPE_REDFOX) -#else -# define machine_is_redfox() (0) -#endif - -#ifdef CONFIG_MACH_MYSH_EP9315_1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MYSH_EP9315_1 -# endif -# define machine_is_mysh_ep9315_1() (machine_arch_type == MACH_TYPE_MYSH_EP9315_1) -#else -# define machine_is_mysh_ep9315_1() (0) -#endif - -#ifdef CONFIG_MACH_TPF106 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPF106 -# endif -# define machine_is_tpf106() (machine_arch_type == MACH_TYPE_TPF106) -#else -# define machine_is_tpf106() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200KG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200KG -# endif -# define machine_is_at91rm9200kg() (machine_arch_type == MACH_TYPE_AT91RM9200KG) -#else -# define machine_is_at91rm9200kg() (0) -#endif - -#ifdef CONFIG_MACH_SLEDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SLEDB -# endif -# define machine_is_rcmt2() (machine_arch_type == MACH_TYPE_SLEDB) -#else -# define machine_is_rcmt2() (0) -#endif - -#ifdef CONFIG_MACH_ONTRACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ONTRACK -# endif -# define machine_is_ontrack() (machine_arch_type == MACH_TYPE_ONTRACK) -#else -# define machine_is_ontrack() (0) -#endif - -#ifdef CONFIG_MACH_PM1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PM1200 -# endif -# define machine_is_pm1200() (machine_arch_type == MACH_TYPE_PM1200) -#else -# define machine_is_pm1200() (0) -#endif - -#ifdef CONFIG_MACH_ESS24XXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESS24XXX -# endif -# define machine_is_ess24562() (machine_arch_type == MACH_TYPE_ESS24XXX) -#else -# define machine_is_ess24562() (0) -#endif - -#ifdef CONFIG_MACH_COREMP7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COREMP7 -# endif -# define machine_is_coremp7() (machine_arch_type == MACH_TYPE_COREMP7) -#else -# define machine_is_coremp7() (0) -#endif - -#ifdef CONFIG_MACH_NEXCODER_6446 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXCODER_6446 -# endif -# define machine_is_nexcoder_6446() (machine_arch_type == MACH_TYPE_NEXCODER_6446) -#else -# define machine_is_nexcoder_6446() (0) -#endif - -#ifdef CONFIG_MACH_STVC8380 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STVC8380 -# endif -# define machine_is_stvc8380() (machine_arch_type == MACH_TYPE_STVC8380) -#else -# define machine_is_stvc8380() (0) -#endif - -#ifdef CONFIG_MACH_TEKLYNX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEKLYNX -# endif -# define machine_is_teklynx() (machine_arch_type == MACH_TYPE_TEKLYNX) -#else -# define machine_is_teklynx() (0) -#endif - -#ifdef CONFIG_MACH_CARBONADO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARBONADO -# endif -# define machine_is_carbonado() (machine_arch_type == MACH_TYPE_CARBONADO) -#else -# define machine_is_carbonado() (0) -#endif - -#ifdef CONFIG_MACH_SYSMOS_MP730 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYSMOS_MP730 -# endif -# define machine_is_sysmos_mp730() (machine_arch_type == MACH_TYPE_SYSMOS_MP730) -#else -# define machine_is_sysmos_mp730() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPER_CL15 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPER_CL15 -# endif -# define machine_is_snapper_cl15() (machine_arch_type == MACH_TYPE_SNAPPER_CL15) -#else -# define machine_is_snapper_cl15() (0) -#endif - -#ifdef CONFIG_MACH_PGIGIM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PGIGIM -# endif -# define machine_is_pgigim() (machine_arch_type == MACH_TYPE_PGIGIM) -#else -# define machine_is_pgigim() (0) -#endif - -#ifdef CONFIG_MACH_PTX9160P2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PTX9160P2 -# endif -# define machine_is_ptx9160p2() (machine_arch_type == MACH_TYPE_PTX9160P2) -#else -# define machine_is_ptx9160p2() (0) -#endif - -#ifdef CONFIG_MACH_DCORE1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DCORE1 -# endif -# define machine_is_dcore1() (machine_arch_type == MACH_TYPE_DCORE1) -#else -# define machine_is_dcore1() (0) -#endif - -#ifdef CONFIG_MACH_VICTORPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VICTORPXA -# endif -# define machine_is_victorpxa() (machine_arch_type == MACH_TYPE_VICTORPXA) -#else -# define machine_is_victorpxa() (0) -#endif - -#ifdef CONFIG_MACH_MX2DTB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX2DTB -# endif -# define machine_is_mx2dtb() (machine_arch_type == MACH_TYPE_MX2DTB) -#else -# define machine_is_mx2dtb() (0) -#endif - -#ifdef CONFIG_MACH_PXA_IREX_ER0100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_IREX_ER0100 -# endif -# define machine_is_pxa_irex_er0100() (machine_arch_type == MACH_TYPE_PXA_IREX_ER0100) -#else -# define machine_is_pxa_irex_er0100() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMZ71 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMZ71 -# endif -# define machine_is_omap_palmz71() (machine_arch_type == MACH_TYPE_OMAP_PALMZ71) -#else -# define machine_is_omap_palmz71() (0) -#endif - -#ifdef CONFIG_MACH_BARTEC_DEG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BARTEC_DEG -# endif -# define machine_is_bartec_deg() (machine_arch_type == MACH_TYPE_BARTEC_DEG) -#else -# define machine_is_bartec_deg() (0) -#endif - -#ifdef CONFIG_MACH_HW50251 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW50251 -# endif -# define machine_is_hw50251() (machine_arch_type == MACH_TYPE_HW50251) -#else -# define machine_is_hw50251() (0) -#endif - -#ifdef CONFIG_MACH_IBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IBOX -# endif -# define machine_is_ibox() (machine_arch_type == MACH_TYPE_IBOX) -#else -# define machine_is_ibox() (0) -#endif - -#ifdef CONFIG_MACH_ATLASLH7A404 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATLASLH7A404 -# endif -# define machine_is_atlaslh7a404() (machine_arch_type == MACH_TYPE_ATLASLH7A404) -#else -# define machine_is_atlaslh7a404() (0) -#endif - -#ifdef CONFIG_MACH_PT2026 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PT2026 -# endif -# define machine_is_pt2026() (machine_arch_type == MACH_TYPE_PT2026) -#else -# define machine_is_pt2026() (0) -#endif - -#ifdef CONFIG_MACH_HTCALPINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCALPINE -# endif -# define machine_is_htcalpine() (machine_arch_type == MACH_TYPE_HTCALPINE) -#else -# define machine_is_htcalpine() (0) -#endif - -#ifdef CONFIG_MACH_BARTEC_VTU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BARTEC_VTU -# endif -# define machine_is_bartec_vtu() (machine_arch_type == MACH_TYPE_BARTEC_VTU) -#else -# define machine_is_bartec_vtu() (0) -#endif - -#ifdef CONFIG_MACH_VCOREII -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VCOREII -# endif -# define machine_is_vcoreii() (machine_arch_type == MACH_TYPE_VCOREII) -#else -# define machine_is_vcoreii() (0) -#endif - -#ifdef CONFIG_MACH_PDNB3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PDNB3 -# endif -# define machine_is_pdnb3() (machine_arch_type == MACH_TYPE_PDNB3) -#else -# define machine_is_pdnb3() (0) -#endif - -#ifdef CONFIG_MACH_HTCBEETLES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCBEETLES -# endif -# define machine_is_htcbeetles() (machine_arch_type == MACH_TYPE_HTCBEETLES) -#else -# define machine_is_htcbeetles() (0) -#endif - -#ifdef CONFIG_MACH_S3C6400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C6400 -# endif -# define machine_is_s3c6400() (machine_arch_type == MACH_TYPE_S3C6400) -#else -# define machine_is_s3c6400() (0) -#endif - -#ifdef CONFIG_MACH_S3C2443 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2443 -# endif -# define machine_is_s3c2443() (machine_arch_type == MACH_TYPE_S3C2443) -#else -# define machine_is_s3c2443() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_LDK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_LDK -# endif -# define machine_is_omap_ldk() (machine_arch_type == MACH_TYPE_OMAP_LDK) -#else -# define machine_is_omap_ldk() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2460 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2460 -# endif -# define machine_is_smdk2460() (machine_arch_type == MACH_TYPE_SMDK2460) -#else -# define machine_is_smdk2460() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2440 -# endif -# define machine_is_smdk2440() (machine_arch_type == MACH_TYPE_SMDK2440) -#else -# define machine_is_smdk2440() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2412 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2412 -# endif -# define machine_is_smdk2412() (machine_arch_type == MACH_TYPE_SMDK2412) -#else -# define machine_is_smdk2412() (0) -#endif - -#ifdef CONFIG_MACH_WEBBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEBBOX -# endif -# define machine_is_webbox() (machine_arch_type == MACH_TYPE_WEBBOX) -#else -# define machine_is_webbox() (0) -#endif - -#ifdef CONFIG_MACH_CWWNDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWWNDP -# endif -# define machine_is_cwwndp() (machine_arch_type == MACH_TYPE_CWWNDP) -#else -# define machine_is_cwwndp() (0) -#endif - -#ifdef CONFIG_MACH_DRAGON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DRAGON -# endif -# define machine_is_i839() (machine_arch_type == MACH_TYPE_DRAGON) -#else -# define machine_is_i839() (0) -#endif - -#ifdef CONFIG_MACH_OPENDO_CPU_BOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENDO_CPU_BOARD -# endif -# define machine_is_opendo_cpu_board() (machine_arch_type == MACH_TYPE_OPENDO_CPU_BOARD) -#else -# define machine_is_opendo_cpu_board() (0) -#endif - -#ifdef CONFIG_MACH_CCM2200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCM2200 -# endif -# define machine_is_ccm2200() (machine_arch_type == MACH_TYPE_CCM2200) -#else -# define machine_is_ccm2200() (0) -#endif - -#ifdef CONFIG_MACH_ETWARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETWARM -# endif -# define machine_is_etwarm() (machine_arch_type == MACH_TYPE_ETWARM) -#else -# define machine_is_etwarm() (0) -#endif - -#ifdef CONFIG_MACH_M93030 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M93030 -# endif -# define machine_is_m93030() (machine_arch_type == MACH_TYPE_M93030) -#else -# define machine_is_m93030() (0) -#endif - -#ifdef CONFIG_MACH_CC7U -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC7U -# endif -# define machine_is_cc7u() (machine_arch_type == MACH_TYPE_CC7U) -#else -# define machine_is_cc7u() (0) -#endif - -#ifdef CONFIG_MACH_MTT_RANGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MTT_RANGER -# endif -# define machine_is_mtt_ranger() (machine_arch_type == MACH_TYPE_MTT_RANGER) -#else -# define machine_is_mtt_ranger() (0) -#endif - -#ifdef CONFIG_MACH_NEXUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXUS -# endif -# define machine_is_nexus() (machine_arch_type == MACH_TYPE_NEXUS) -#else -# define machine_is_nexus() (0) -#endif - -#ifdef CONFIG_MACH_DESMAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DESMAN -# endif -# define machine_is_desman() (machine_arch_type == MACH_TYPE_DESMAN) -#else -# define machine_is_desman() (0) -#endif - -#ifdef CONFIG_MACH_BKDE303 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BKDE303 -# endif -# define machine_is_bkde303() (machine_arch_type == MACH_TYPE_BKDE303) -#else -# define machine_is_bkde303() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2413 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2413 -# endif -# define machine_is_smdk2413() (machine_arch_type == MACH_TYPE_SMDK2413) -#else -# define machine_is_smdk2413() (0) -#endif - -#ifdef CONFIG_MACH_AML_M7200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML_M7200 -# endif -# define machine_is_aml_m7200() (machine_arch_type == MACH_TYPE_AML_M7200) -#else -# define machine_is_aml_m7200() (0) -#endif - -#ifdef CONFIG_MACH_AML_M5900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML_M5900 -# endif -# define machine_is_aml_m5900() (machine_arch_type == MACH_TYPE_AML_M5900) -#else -# define machine_is_aml_m5900() (0) -#endif - -#ifdef CONFIG_MACH_SG640 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG640 -# endif -# define machine_is_sg640() (machine_arch_type == MACH_TYPE_SG640) -#else -# define machine_is_sg640() (0) -#endif - -#ifdef CONFIG_MACH_EDG79524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDG79524 -# endif -# define machine_is_edg79524() (machine_arch_type == MACH_TYPE_EDG79524) -#else -# define machine_is_edg79524() (0) -#endif - -#ifdef CONFIG_MACH_AI2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AI2410 -# endif -# define machine_is_ai2410() (machine_arch_type == MACH_TYPE_AI2410) -#else -# define machine_is_ai2410() (0) -#endif - -#ifdef CONFIG_MACH_IXP465 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP465 -# endif -# define machine_is_ixp465() (machine_arch_type == MACH_TYPE_IXP465) -#else -# define machine_is_ixp465() (0) -#endif - -#ifdef CONFIG_MACH_BALLOON3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BALLOON3 -# endif -# define machine_is_balloon3() (machine_arch_type == MACH_TYPE_BALLOON3) -#else -# define machine_is_balloon3() (0) -#endif - -#ifdef CONFIG_MACH_HEINS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HEINS -# endif -# define machine_is_heins() (machine_arch_type == MACH_TYPE_HEINS) -#else -# define machine_is_heins() (0) -#endif - -#ifdef CONFIG_MACH_MPLUSEVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPLUSEVA -# endif -# define machine_is_mpluseva() (machine_arch_type == MACH_TYPE_MPLUSEVA) -#else -# define machine_is_mpluseva() (0) -#endif - -#ifdef CONFIG_MACH_RT042 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RT042 -# endif -# define machine_is_rt042() (machine_arch_type == MACH_TYPE_RT042) -#else -# define machine_is_rt042() (0) -#endif - -#ifdef CONFIG_MACH_CWIEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWIEM -# endif -# define machine_is_cwiem() (machine_arch_type == MACH_TYPE_CWIEM) -#else -# define machine_is_cwiem() (0) -#endif - -#ifdef CONFIG_MACH_CM_X270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_X270 -# endif -# define machine_is_cm_x270() (machine_arch_type == MACH_TYPE_CM_X270) -#else -# define machine_is_cm_x270() (0) -#endif - -#ifdef CONFIG_MACH_CM_X255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_X255 -# endif -# define machine_is_cm_x255() (machine_arch_type == MACH_TYPE_CM_X255) -#else -# define machine_is_cm_x255() (0) -#endif - -#ifdef CONFIG_MACH_ESH_AT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESH_AT91 -# endif -# define machine_is_esh_at91() (machine_arch_type == MACH_TYPE_ESH_AT91) -#else -# define machine_is_esh_at91() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATE3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATE3 -# endif -# define machine_is_sandgate3() (machine_arch_type == MACH_TYPE_SANDGATE3) -#else -# define machine_is_sandgate3() (0) -#endif - -#ifdef CONFIG_MACH_PRIMO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRIMO -# endif -# define machine_is_primo() (machine_arch_type == MACH_TYPE_PRIMO) -#else -# define machine_is_primo() (0) -#endif - -#ifdef CONFIG_MACH_GEMSTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEMSTONE -# endif -# define machine_is_gemstone() (machine_arch_type == MACH_TYPE_GEMSTONE) -#else -# define machine_is_gemstone() (0) -#endif - -#ifdef CONFIG_MACH_PRONGHORNMETRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRONGHORNMETRO -# endif -# define machine_is_pronghorn_metro() (machine_arch_type == MACH_TYPE_PRONGHORNMETRO) -#else -# define machine_is_pronghorn_metro() (0) -#endif - -#ifdef CONFIG_MACH_SIDEWINDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIDEWINDER -# endif -# define machine_is_sidewinder() (machine_arch_type == MACH_TYPE_SIDEWINDER) -#else -# define machine_is_sidewinder() (0) -#endif - -#ifdef CONFIG_MACH_PICOMOD1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOMOD1 -# endif -# define machine_is_picomod1() (machine_arch_type == MACH_TYPE_PICOMOD1) -#else -# define machine_is_picomod1() (0) -#endif - -#ifdef CONFIG_MACH_SG590 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG590 -# endif -# define machine_is_sg590() (machine_arch_type == MACH_TYPE_SG590) -#else -# define machine_is_sg590() (0) -#endif - -#ifdef CONFIG_MACH_AKAI9307 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AKAI9307 -# endif -# define machine_is_akai9307() (machine_arch_type == MACH_TYPE_AKAI9307) -#else -# define machine_is_akai9307() (0) -#endif - -#ifdef CONFIG_MACH_FONTAINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FONTAINE -# endif -# define machine_is_fontaine() (machine_arch_type == MACH_TYPE_FONTAINE) -#else -# define machine_is_fontaine() (0) -#endif - -#ifdef CONFIG_MACH_WOMBAT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WOMBAT -# endif -# define machine_is_wombat() (machine_arch_type == MACH_TYPE_WOMBAT) -#else -# define machine_is_wombat() (0) -#endif - -#ifdef CONFIG_MACH_ACQ300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACQ300 -# endif -# define machine_is_acq300() (machine_arch_type == MACH_TYPE_ACQ300) -#else -# define machine_is_acq300() (0) -#endif - -#ifdef CONFIG_MACH_MOD_270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOD_270 -# endif -# define machine_is_mod272() (machine_arch_type == MACH_TYPE_MOD_270) -#else -# define machine_is_mod272() (0) -#endif - -#ifdef CONFIG_MACH_VC0820 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VC0820 -# endif -# define machine_is_vmc_vc0820() (machine_arch_type == MACH_TYPE_VC0820) -#else -# define machine_is_vmc_vc0820() (0) -#endif - -#ifdef CONFIG_MACH_ANI_AIM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANI_AIM -# endif -# define machine_is_ani_aim() (machine_arch_type == MACH_TYPE_ANI_AIM) -#else -# define machine_is_ani_aim() (0) -#endif - -#ifdef CONFIG_MACH_JELLYFISH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JELLYFISH -# endif -# define machine_is_jellyfish() (machine_arch_type == MACH_TYPE_JELLYFISH) -#else -# define machine_is_jellyfish() (0) -#endif - -#ifdef CONFIG_MACH_AMANITA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AMANITA -# endif -# define machine_is_amanita() (machine_arch_type == MACH_TYPE_AMANITA) -#else -# define machine_is_amanita() (0) -#endif - -#ifdef CONFIG_MACH_VLINK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VLINK -# endif -# define machine_is_vlink() (machine_arch_type == MACH_TYPE_VLINK) -#else -# define machine_is_vlink() (0) -#endif - -#ifdef CONFIG_MACH_DEXFLEX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEXFLEX -# endif -# define machine_is_dexflex() (machine_arch_type == MACH_TYPE_DEXFLEX) -#else -# define machine_is_dexflex() (0) -#endif - -#ifdef CONFIG_MACH_EIGEN_TTQ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EIGEN_TTQ -# endif -# define machine_is_eigen_ttq() (machine_arch_type == MACH_TYPE_EIGEN_TTQ) -#else -# define machine_is_eigen_ttq() (0) -#endif - -#ifdef CONFIG_MACH_ARCOM_TITAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCOM_TITAN -# endif -# define machine_is_arcom_titan() (machine_arch_type == MACH_TYPE_ARCOM_TITAN) -#else -# define machine_is_arcom_titan() (0) -#endif - -#ifdef CONFIG_MACH_TABLA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TABLA -# endif -# define machine_is_tabla() (machine_arch_type == MACH_TYPE_TABLA) -#else -# define machine_is_tabla() (0) -#endif - -#ifdef CONFIG_MACH_MDIRAC3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MDIRAC3 -# endif -# define machine_is_mdirac3() (machine_arch_type == MACH_TYPE_MDIRAC3) -#else -# define machine_is_mdirac3() (0) -#endif - -#ifdef CONFIG_MACH_MRHFBP2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MRHFBP2 -# endif -# define machine_is_mrhfbp2() (machine_arch_type == MACH_TYPE_MRHFBP2) -#else -# define machine_is_mrhfbp2() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200RB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200RB -# endif -# define machine_is_at91rm9200rb() (machine_arch_type == MACH_TYPE_AT91RM9200RB) -#else -# define machine_is_at91rm9200rb() (0) -#endif - -#ifdef CONFIG_MACH_ANI_APM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANI_APM -# endif -# define machine_is_ani_apm() (machine_arch_type == MACH_TYPE_ANI_APM) -#else -# define machine_is_ani_apm() (0) -#endif - -#ifdef CONFIG_MACH_ELLA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELLA1 -# endif -# define machine_is_ella1() (machine_arch_type == MACH_TYPE_ELLA1) -#else -# define machine_is_ella1() (0) -#endif - -#ifdef CONFIG_MACH_INHAND_PXA27X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHAND_PXA27X -# endif -# define machine_is_inhand_pxa27x() (machine_arch_type == MACH_TYPE_INHAND_PXA27X) -#else -# define machine_is_inhand_pxa27x() (0) -#endif - -#ifdef CONFIG_MACH_INHAND_PXA25X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHAND_PXA25X -# endif -# define machine_is_inhand_pxa25x() (machine_arch_type == MACH_TYPE_INHAND_PXA25X) -#else -# define machine_is_inhand_pxa25x() (0) -#endif - -#ifdef CONFIG_MACH_EMPOS_XM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPOS_XM -# endif -# define machine_is_empos_xm() (machine_arch_type == MACH_TYPE_EMPOS_XM) -#else -# define machine_is_empos_xm() (0) -#endif - -#ifdef CONFIG_MACH_EMPOS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPOS -# endif -# define machine_is_empos() (machine_arch_type == MACH_TYPE_EMPOS) -#else -# define machine_is_empos() (0) -#endif - -#ifdef CONFIG_MACH_EMPOS_TINY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPOS_TINY -# endif -# define machine_is_empos_tiny() (machine_arch_type == MACH_TYPE_EMPOS_TINY) -#else -# define machine_is_empos_tiny() (0) -#endif - -#ifdef CONFIG_MACH_EMPOS_SM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPOS_SM -# endif -# define machine_is_empos_sm() (machine_arch_type == MACH_TYPE_EMPOS_SM) -#else -# define machine_is_empos_sm() (0) -#endif - -#ifdef CONFIG_MACH_EGRET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EGRET -# endif -# define machine_is_egret() (machine_arch_type == MACH_TYPE_EGRET) -#else -# define machine_is_egret() (0) -#endif - -#ifdef CONFIG_MACH_OSTRICH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSTRICH -# endif -# define machine_is_ostrich() (machine_arch_type == MACH_TYPE_OSTRICH) -#else -# define machine_is_ostrich() (0) -#endif - -#ifdef CONFIG_MACH_N50 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N50 -# endif -# define machine_is_n50() (machine_arch_type == MACH_TYPE_N50) -#else -# define machine_is_n50() (0) -#endif - -#ifdef CONFIG_MACH_ECBAT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECBAT91 -# endif -# define machine_is_ecbat91() (machine_arch_type == MACH_TYPE_ECBAT91) -#else -# define machine_is_ecbat91() (0) -#endif - -#ifdef CONFIG_MACH_STAREAST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STAREAST -# endif -# define machine_is_stareast() (machine_arch_type == MACH_TYPE_STAREAST) -#else -# define machine_is_stareast() (0) -#endif - -#ifdef CONFIG_MACH_DSPG_DW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSPG_DW -# endif -# define machine_is_dspg_dw() (machine_arch_type == MACH_TYPE_DSPG_DW) -#else -# define machine_is_dspg_dw() (0) -#endif - -#ifdef CONFIG_MACH_ONEARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ONEARM -# endif -# define machine_is_onearm() (machine_arch_type == MACH_TYPE_ONEARM) -#else -# define machine_is_onearm() (0) -#endif - -#ifdef CONFIG_MACH_MRG110_6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MRG110_6 -# endif -# define machine_is_mrg110_6() (machine_arch_type == MACH_TYPE_MRG110_6) -#else -# define machine_is_mrg110_6() (0) -#endif - -#ifdef CONFIG_MACH_WRT300NV2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WRT300NV2 -# endif -# define machine_is_wrt300nv2() (machine_arch_type == MACH_TYPE_WRT300NV2) -#else -# define machine_is_wrt300nv2() (0) -#endif - -#ifdef CONFIG_MACH_XM_BULVERDE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XM_BULVERDE -# endif -# define machine_is_xm_bulverde() (machine_arch_type == MACH_TYPE_XM_BULVERDE) -#else -# define machine_is_xm_bulverde() (0) -#endif - -#ifdef CONFIG_MACH_MSM6100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM6100 -# endif -# define machine_is_msm6100() (machine_arch_type == MACH_TYPE_MSM6100) -#else -# define machine_is_msm6100() (0) -#endif - -#ifdef CONFIG_MACH_ETI_B1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETI_B1 -# endif -# define machine_is_eti_b1() (machine_arch_type == MACH_TYPE_ETI_B1) -#else -# define machine_is_eti_b1() (0) -#endif - -#ifdef CONFIG_MACH_ZILOG_ZA9L -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZILOG_ZA9L -# endif -# define machine_is_za9l_series() (machine_arch_type == MACH_TYPE_ZILOG_ZA9L) -#else -# define machine_is_za9l_series() (0) -#endif - -#ifdef CONFIG_MACH_BIT2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIT2440 -# endif -# define machine_is_bit2440() (machine_arch_type == MACH_TYPE_BIT2440) -#else -# define machine_is_bit2440() (0) -#endif - -#ifdef CONFIG_MACH_NBI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NBI -# endif -# define machine_is_nbi() (machine_arch_type == MACH_TYPE_NBI) -#else -# define machine_is_nbi() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2443 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2443 -# endif -# define machine_is_smdk2443() (machine_arch_type == MACH_TYPE_SMDK2443) -#else -# define machine_is_smdk2443() (0) -#endif - -#ifdef CONFIG_MACH_VDAVINCI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VDAVINCI -# endif -# define machine_is_vdavinci() (machine_arch_type == MACH_TYPE_VDAVINCI) -#else -# define machine_is_vdavinci() (0) -#endif - -#ifdef CONFIG_MACH_ATC6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATC6 -# endif -# define machine_is_atc6() (machine_arch_type == MACH_TYPE_ATC6) -#else -# define machine_is_atc6() (0) -#endif - -#ifdef CONFIG_MACH_MULTMDW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTMDW -# endif -# define machine_is_multmdw() (machine_arch_type == MACH_TYPE_MULTMDW) -#else -# define machine_is_multmdw() (0) -#endif - -#ifdef CONFIG_MACH_MBA2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MBA2440 -# endif -# define machine_is_mba2440() (machine_arch_type == MACH_TYPE_MBA2440) -#else -# define machine_is_mba2440() (0) -#endif - -#ifdef CONFIG_MACH_ECSD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECSD -# endif -# define machine_is_ecsd() (machine_arch_type == MACH_TYPE_ECSD) -#else -# define machine_is_ecsd() (0) -#endif - -#ifdef CONFIG_MACH_PALMZ31 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMZ31 -# endif -# define machine_is_palmz31() (machine_arch_type == MACH_TYPE_PALMZ31) -#else -# define machine_is_palmz31() (0) -#endif - -#ifdef CONFIG_MACH_FSG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FSG -# endif -# define machine_is_fsg() (machine_arch_type == MACH_TYPE_FSG) -#else -# define machine_is_fsg() (0) -#endif - -#ifdef CONFIG_MACH_RAZOR101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAZOR101 -# endif -# define machine_is_razor101() (machine_arch_type == MACH_TYPE_RAZOR101) -#else -# define machine_is_razor101() (0) -#endif - -#ifdef CONFIG_MACH_OPERA_TDM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPERA_TDM -# endif -# define machine_is_opera_tdm() (machine_arch_type == MACH_TYPE_OPERA_TDM) -#else -# define machine_is_opera_tdm() (0) -#endif - -#ifdef CONFIG_MACH_COMCERTO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMCERTO -# endif -# define machine_is_comcerto() (machine_arch_type == MACH_TYPE_COMCERTO) -#else -# define machine_is_comcerto() (0) -#endif - -#ifdef CONFIG_MACH_TB0319 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TB0319 -# endif -# define machine_is_tb0319() (machine_arch_type == MACH_TYPE_TB0319) -#else -# define machine_is_tb0319() (0) -#endif - -#ifdef CONFIG_MACH_KWS8000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KWS8000 -# endif -# define machine_is_kws8000() (machine_arch_type == MACH_TYPE_KWS8000) -#else -# define machine_is_kws8000() (0) -#endif - -#ifdef CONFIG_MACH_B2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_B2 -# endif -# define machine_is_b2() (machine_arch_type == MACH_TYPE_B2) -#else -# define machine_is_b2() (0) -#endif - -#ifdef CONFIG_MACH_LCL54 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LCL54 -# endif -# define machine_is_lcl54() (machine_arch_type == MACH_TYPE_LCL54) -#else -# define machine_is_lcl54() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9260EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9260EK -# endif -# define machine_is_at91sam9260ek() (machine_arch_type == MACH_TYPE_AT91SAM9260EK) -#else -# define machine_is_at91sam9260ek() (0) -#endif - -#ifdef CONFIG_MACH_GLANTANK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GLANTANK -# endif -# define machine_is_glantank() (machine_arch_type == MACH_TYPE_GLANTANK) -#else -# define machine_is_glantank() (0) -#endif - -#ifdef CONFIG_MACH_N2100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N2100 -# endif -# define machine_is_n2100() (machine_arch_type == MACH_TYPE_N2100) -#else -# define machine_is_n2100() (0) -#endif - -#ifdef CONFIG_MACH_N4100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N4100 -# endif -# define machine_is_n4100() (machine_arch_type == MACH_TYPE_N4100) -#else -# define machine_is_n4100() (0) -#endif - -#ifdef CONFIG_MACH_VERTICAL_RSC4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VERTICAL_RSC4 -# endif -# define machine_is_rsc4() (machine_arch_type == MACH_TYPE_VERTICAL_RSC4) -#else -# define machine_is_rsc4() (0) -#endif - -#ifdef CONFIG_MACH_SG8100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG8100 -# endif -# define machine_is_sg8100() (machine_arch_type == MACH_TYPE_SG8100) -#else -# define machine_is_sg8100() (0) -#endif - -#ifdef CONFIG_MACH_IM42XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IM42XX -# endif -# define machine_is_im42xx() (machine_arch_type == MACH_TYPE_IM42XX) -#else -# define machine_is_im42xx() (0) -#endif - -#ifdef CONFIG_MACH_FTXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FTXX -# endif -# define machine_is_ftxx() (machine_arch_type == MACH_TYPE_FTXX) -#else -# define machine_is_ftxx() (0) -#endif - -#ifdef CONFIG_MACH_LWFUSION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LWFUSION -# endif -# define machine_is_lwfusion() (machine_arch_type == MACH_TYPE_LWFUSION) -#else -# define machine_is_lwfusion() (0) -#endif - -#ifdef CONFIG_MACH_QT2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QT2410 -# endif -# define machine_is_qt2410() (machine_arch_type == MACH_TYPE_QT2410) -#else -# define machine_is_qt2410() (0) -#endif - -#ifdef CONFIG_MACH_KIXRP435 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KIXRP435 -# endif -# define machine_is_kixrp435() (machine_arch_type == MACH_TYPE_KIXRP435) -#else -# define machine_is_kixrp435() (0) -#endif - -#ifdef CONFIG_MACH_CCW9C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCW9C -# endif -# define machine_is_ccw9c() (machine_arch_type == MACH_TYPE_CCW9C) -#else -# define machine_is_ccw9c() (0) -#endif - -#ifdef CONFIG_MACH_DABHS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DABHS -# endif -# define machine_is_dabhs() (machine_arch_type == MACH_TYPE_DABHS) -#else -# define machine_is_dabhs() (0) -#endif - -#ifdef CONFIG_MACH_GZMX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GZMX -# endif -# define machine_is_gzmx() (machine_arch_type == MACH_TYPE_GZMX) -#else -# define machine_is_gzmx() (0) -#endif - -#ifdef CONFIG_MACH_IPNW100AP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPNW100AP -# endif -# define machine_is_ipnw100ap() (machine_arch_type == MACH_TYPE_IPNW100AP) -#else -# define machine_is_ipnw100ap() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9360DEV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9360DEV -# endif -# define machine_is_cc9p9360dev() (machine_arch_type == MACH_TYPE_CC9P9360DEV) -#else -# define machine_is_cc9p9360dev() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9750DEV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9750DEV -# endif -# define machine_is_cc9p9750dev() (machine_arch_type == MACH_TYPE_CC9P9750DEV) -#else -# define machine_is_cc9p9750dev() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9360VAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9360VAL -# endif -# define machine_is_cc9p9360val() (machine_arch_type == MACH_TYPE_CC9P9360VAL) -#else -# define machine_is_cc9p9360val() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9750VAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9750VAL -# endif -# define machine_is_cc9p9750val() (machine_arch_type == MACH_TYPE_CC9P9750VAL) -#else -# define machine_is_cc9p9750val() (0) -#endif - -#ifdef CONFIG_MACH_NX70V -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NX70V -# endif -# define machine_is_nx70v() (machine_arch_type == MACH_TYPE_NX70V) -#else -# define machine_is_nx70v() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200DF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200DF -# endif -# define machine_is_at91rm9200df() (machine_arch_type == MACH_TYPE_AT91RM9200DF) -#else -# define machine_is_at91rm9200df() (0) -#endif - -#ifdef CONFIG_MACH_SE_PILOT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE_PILOT2 -# endif -# define machine_is_se_pilot2() (machine_arch_type == MACH_TYPE_SE_PILOT2) -#else -# define machine_is_se_pilot2() (0) -#endif - -#ifdef CONFIG_MACH_MTCN_T800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MTCN_T800 -# endif -# define machine_is_mtcn_t800() (machine_arch_type == MACH_TYPE_MTCN_T800) -#else -# define machine_is_mtcn_t800() (0) -#endif - -#ifdef CONFIG_MACH_VCMX212 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VCMX212 -# endif -# define machine_is_vcmx212() (machine_arch_type == MACH_TYPE_VCMX212) -#else -# define machine_is_vcmx212() (0) -#endif - -#ifdef CONFIG_MACH_LYNX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LYNX -# endif -# define machine_is_lynx() (machine_arch_type == MACH_TYPE_LYNX) -#else -# define machine_is_lynx() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9260ID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9260ID -# endif -# define machine_is_at91sam9260id() (machine_arch_type == MACH_TYPE_AT91SAM9260ID) -#else -# define machine_is_at91sam9260id() (0) -#endif - -#ifdef CONFIG_MACH_HW86052 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW86052 -# endif -# define machine_is_hw86052() (machine_arch_type == MACH_TYPE_HW86052) -#else -# define machine_is_hw86052() (0) -#endif - -#ifdef CONFIG_MACH_PILZ_PMI3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PILZ_PMI3 -# endif -# define machine_is_pilz_pmi3() (machine_arch_type == MACH_TYPE_PILZ_PMI3) -#else -# define machine_is_pilz_pmi3() (0) -#endif - -#ifdef CONFIG_MACH_EDB9302A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9302A -# endif -# define machine_is_edb9302a() (machine_arch_type == MACH_TYPE_EDB9302A) -#else -# define machine_is_edb9302a() (0) -#endif - -#ifdef CONFIG_MACH_EDB9307A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9307A -# endif -# define machine_is_edb9307a() (machine_arch_type == MACH_TYPE_EDB9307A) -#else -# define machine_is_edb9307a() (0) -#endif - -#ifdef CONFIG_MACH_CT_DFS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CT_DFS -# endif -# define machine_is_ct_dfs() (machine_arch_type == MACH_TYPE_CT_DFS) -#else -# define machine_is_ct_dfs() (0) -#endif - -#ifdef CONFIG_MACH_PILZ_PMI4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PILZ_PMI4 -# endif -# define machine_is_pilz_pmi4() (machine_arch_type == MACH_TYPE_PILZ_PMI4) -#else -# define machine_is_pilz_pmi4() (0) -#endif - -#ifdef CONFIG_MACH_XCEEDNP_IXP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XCEEDNP_IXP -# endif -# define machine_is_xceednp_ixp() (machine_arch_type == MACH_TYPE_XCEEDNP_IXP) -#else -# define machine_is_xceednp_ixp() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2442B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2442B -# endif -# define machine_is_smdk2442b() (machine_arch_type == MACH_TYPE_SMDK2442B) -#else -# define machine_is_smdk2442b() (0) -#endif - -#ifdef CONFIG_MACH_XNODE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XNODE -# endif -# define machine_is_xnode() (machine_arch_type == MACH_TYPE_XNODE) -#else -# define machine_is_xnode() (0) -#endif - -#ifdef CONFIG_MACH_AIDX270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AIDX270 -# endif -# define machine_is_aidx270() (machine_arch_type == MACH_TYPE_AIDX270) -#else -# define machine_is_aidx270() (0) -#endif - -#ifdef CONFIG_MACH_REMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REMA -# endif -# define machine_is_rema() (machine_arch_type == MACH_TYPE_REMA) -#else -# define machine_is_rema() (0) -#endif - -#ifdef CONFIG_MACH_BPS1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BPS1000 -# endif -# define machine_is_bps1000() (machine_arch_type == MACH_TYPE_BPS1000) -#else -# define machine_is_bps1000() (0) -#endif - -#ifdef CONFIG_MACH_HW90350 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW90350 -# endif -# define machine_is_hw90350() (machine_arch_type == MACH_TYPE_HW90350) -#else -# define machine_is_hw90350() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_3430SDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_3430SDP -# endif -# define machine_is_omap_3430sdp() (machine_arch_type == MACH_TYPE_OMAP_3430SDP) -#else -# define machine_is_omap_3430sdp() (0) -#endif - -#ifdef CONFIG_MACH_BLUETOUCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUETOUCH -# endif -# define machine_is_bluetouch() (machine_arch_type == MACH_TYPE_BLUETOUCH) -#else -# define machine_is_bluetouch() (0) -#endif - -#ifdef CONFIG_MACH_VSTMS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VSTMS -# endif -# define machine_is_vstms() (machine_arch_type == MACH_TYPE_VSTMS) -#else -# define machine_is_vstms() (0) -#endif - -#ifdef CONFIG_MACH_XSBASE270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XSBASE270 -# endif -# define machine_is_xsbase270() (machine_arch_type == MACH_TYPE_XSBASE270) -#else -# define machine_is_xsbase270() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9260EK_CN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9260EK_CN -# endif -# define machine_is_at91sam9260ek_cn() (machine_arch_type == MACH_TYPE_AT91SAM9260EK_CN) -#else -# define machine_is_at91sam9260ek_cn() (0) -#endif - -#ifdef CONFIG_MACH_ADSTURBOXB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSTURBOXB -# endif -# define machine_is_adsturboxb() (machine_arch_type == MACH_TYPE_ADSTURBOXB) -#else -# define machine_is_adsturboxb() (0) -#endif - -#ifdef CONFIG_MACH_OTI4110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OTI4110 -# endif -# define machine_is_oti4110() (machine_arch_type == MACH_TYPE_OTI4110) -#else -# define machine_is_oti4110() (0) -#endif - -#ifdef CONFIG_MACH_HME_PXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HME_PXA -# endif -# define machine_is_hme_pxa() (machine_arch_type == MACH_TYPE_HME_PXA) -#else -# define machine_is_hme_pxa() (0) -#endif - -#ifdef CONFIG_MACH_DEISTERDCA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEISTERDCA -# endif -# define machine_is_deisterdca() (machine_arch_type == MACH_TYPE_DEISTERDCA) -#else -# define machine_is_deisterdca() (0) -#endif - -#ifdef CONFIG_MACH_CES_SSEM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CES_SSEM2 -# endif -# define machine_is_ces_ssem2() (machine_arch_type == MACH_TYPE_CES_SSEM2) -#else -# define machine_is_ces_ssem2() (0) -#endif - -#ifdef CONFIG_MACH_CES_MTR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CES_MTR -# endif -# define machine_is_ces_mtr() (machine_arch_type == MACH_TYPE_CES_MTR) -#else -# define machine_is_ces_mtr() (0) -#endif - -#ifdef CONFIG_MACH_TDS_AVNG_SBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TDS_AVNG_SBC -# endif -# define machine_is_tds_avng_sbc() (machine_arch_type == MACH_TYPE_TDS_AVNG_SBC) -#else -# define machine_is_tds_avng_sbc() (0) -#endif - -#ifdef CONFIG_MACH_EVEREST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EVEREST -# endif -# define machine_is_everest() (machine_arch_type == MACH_TYPE_EVEREST) -#else -# define machine_is_everest() (0) -#endif - -#ifdef CONFIG_MACH_PNX4010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX4010 -# endif -# define machine_is_pnx4010() (machine_arch_type == MACH_TYPE_PNX4010) -#else -# define machine_is_pnx4010() (0) -#endif - -#ifdef CONFIG_MACH_OXNAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OXNAS -# endif -# define machine_is_oxnas() (machine_arch_type == MACH_TYPE_OXNAS) -#else -# define machine_is_oxnas() (0) -#endif - -#ifdef CONFIG_MACH_FIORI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FIORI -# endif -# define machine_is_fiori() (machine_arch_type == MACH_TYPE_FIORI) -#else -# define machine_is_fiori() (0) -#endif - -#ifdef CONFIG_MACH_ML1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ML1200 -# endif -# define machine_is_ml1200() (machine_arch_type == MACH_TYPE_ML1200) -#else -# define machine_is_ml1200() (0) -#endif - -#ifdef CONFIG_MACH_PECOS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PECOS -# endif -# define machine_is_pecos() (machine_arch_type == MACH_TYPE_PECOS) -#else -# define machine_is_pecos() (0) -#endif - -#ifdef CONFIG_MACH_NB2XXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NB2XXX -# endif -# define machine_is_nb2xxx() (machine_arch_type == MACH_TYPE_NB2XXX) -#else -# define machine_is_nb2xxx() (0) -#endif - -#ifdef CONFIG_MACH_HW6900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW6900 -# endif -# define machine_is_hw6900() (machine_arch_type == MACH_TYPE_HW6900) -#else -# define machine_is_hw6900() (0) -#endif - -#ifdef CONFIG_MACH_CDCS_QUOLL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CDCS_QUOLL -# endif -# define machine_is_cdcs_quoll() (machine_arch_type == MACH_TYPE_CDCS_QUOLL) -#else -# define machine_is_cdcs_quoll() (0) -#endif - -#ifdef CONFIG_MACH_QUICKSILVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUICKSILVER -# endif -# define machine_is_quicksilver() (machine_arch_type == MACH_TYPE_QUICKSILVER) -#else -# define machine_is_quicksilver() (0) -#endif - -#ifdef CONFIG_MACH_UPLAT926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UPLAT926 -# endif -# define machine_is_uplat926() (machine_arch_type == MACH_TYPE_UPLAT926) -#else -# define machine_is_uplat926() (0) -#endif - -#ifdef CONFIG_MACH_DEP2410_THOMAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEP2410_THOMAS -# endif -# define machine_is_dep2410_dep2410() (machine_arch_type == MACH_TYPE_DEP2410_THOMAS) -#else -# define machine_is_dep2410_dep2410() (0) -#endif - -#ifdef CONFIG_MACH_DTK2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DTK2410 -# endif -# define machine_is_dtk2410() (machine_arch_type == MACH_TYPE_DTK2410) -#else -# define machine_is_dtk2410() (0) -#endif - -#ifdef CONFIG_MACH_CHILI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHILI -# endif -# define machine_is_chili() (machine_arch_type == MACH_TYPE_CHILI) -#else -# define machine_is_chili() (0) -#endif - -#ifdef CONFIG_MACH_DEMETER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEMETER -# endif -# define machine_is_demeter() (machine_arch_type == MACH_TYPE_DEMETER) -#else -# define machine_is_demeter() (0) -#endif - -#ifdef CONFIG_MACH_DIONYSUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIONYSUS -# endif -# define machine_is_dionysus() (machine_arch_type == MACH_TYPE_DIONYSUS) -#else -# define machine_is_dionysus() (0) -#endif - -#ifdef CONFIG_MACH_AS352X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AS352X -# endif -# define machine_is_as352x() (machine_arch_type == MACH_TYPE_AS352X) -#else -# define machine_is_as352x() (0) -#endif - -#ifdef CONFIG_MACH_SERVICE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SERVICE -# endif -# define machine_is_service() (machine_arch_type == MACH_TYPE_SERVICE) -#else -# define machine_is_service() (0) -#endif - -#ifdef CONFIG_MACH_CS_E9301 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CS_E9301 -# endif -# define machine_is_cs_e9301() (machine_arch_type == MACH_TYPE_CS_E9301) -#else -# define machine_is_cs_e9301() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9M -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9M -# endif -# define machine_is_micro9m() (machine_arch_type == MACH_TYPE_MICRO9M) -#else -# define machine_is_micro9m() (0) -#endif - -#ifdef CONFIG_MACH_IA_MOSPCK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IA_MOSPCK -# endif -# define machine_is_ia_mospck() (machine_arch_type == MACH_TYPE_IA_MOSPCK) -#else -# define machine_is_ia_mospck() (0) -#endif - -#ifdef CONFIG_MACH_QL201B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QL201B -# endif -# define machine_is_ql201b() (machine_arch_type == MACH_TYPE_QL201B) -#else -# define machine_is_ql201b() (0) -#endif - -#ifdef CONFIG_MACH_BBM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BBM -# endif -# define machine_is_bbm() (machine_arch_type == MACH_TYPE_BBM) -#else -# define machine_is_bbm() (0) -#endif - -#ifdef CONFIG_MACH_EXXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXXX -# endif -# define machine_is_exxx() (machine_arch_type == MACH_TYPE_EXXX) -#else -# define machine_is_exxx() (0) -#endif - -#ifdef CONFIG_MACH_WMA11B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WMA11B -# endif -# define machine_is_wma11b() (machine_arch_type == MACH_TYPE_WMA11B) -#else -# define machine_is_wma11b() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_ATLAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_ATLAS -# endif -# define machine_is_pelco_atlas() (machine_arch_type == MACH_TYPE_PELCO_ATLAS) -#else -# define machine_is_pelco_atlas() (0) -#endif - -#ifdef CONFIG_MACH_G500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G500 -# endif -# define machine_is_g500() (machine_arch_type == MACH_TYPE_G500) -#else -# define machine_is_g500() (0) -#endif - -#ifdef CONFIG_MACH_BUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUG -# endif -# define machine_is_bug() (machine_arch_type == MACH_TYPE_BUG) -#else -# define machine_is_bug() (0) -#endif - -#ifdef CONFIG_MACH_MX33ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX33ADS -# endif -# define machine_is_mx33ads() (machine_arch_type == MACH_TYPE_MX33ADS) -#else -# define machine_is_mx33ads() (0) -#endif - -#ifdef CONFIG_MACH_CHUB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHUB -# endif -# define machine_is_chub() (machine_arch_type == MACH_TYPE_CHUB) -#else -# define machine_is_chub() (0) -#endif - -#ifdef CONFIG_MACH_NEO1973_GTA01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEO1973_GTA01 -# endif -# define machine_is_neo1973_gta01() (machine_arch_type == MACH_TYPE_NEO1973_GTA01) -#else -# define machine_is_neo1973_gta01() (0) -#endif - -#ifdef CONFIG_MACH_W90N740 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90N740 -# endif -# define machine_is_w90n740() (machine_arch_type == MACH_TYPE_W90N740) -#else -# define machine_is_w90n740() (0) -#endif - -#ifdef CONFIG_MACH_MEDALLION_SA2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEDALLION_SA2410 -# endif -# define machine_is_medallion_sa2410() (machine_arch_type == MACH_TYPE_MEDALLION_SA2410) -#else -# define machine_is_medallion_sa2410() (0) -#endif - -#ifdef CONFIG_MACH_IA_CPU_9200_2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IA_CPU_9200_2 -# endif -# define machine_is_ia_cpu_9200_2() (machine_arch_type == MACH_TYPE_IA_CPU_9200_2) -#else -# define machine_is_ia_cpu_9200_2() (0) -#endif - -#ifdef CONFIG_MACH_DIMMRM9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIMMRM9200 -# endif -# define machine_is_dimmrm9200() (machine_arch_type == MACH_TYPE_DIMMRM9200) -#else -# define machine_is_dimmrm9200() (0) -#endif - -#ifdef CONFIG_MACH_PM9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PM9261 -# endif -# define machine_is_pm9261() (machine_arch_type == MACH_TYPE_PM9261) -#else -# define machine_is_pm9261() (0) -#endif - -#ifdef CONFIG_MACH_ML7304 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ML7304 -# endif -# define machine_is_ml7304() (machine_arch_type == MACH_TYPE_ML7304) -#else -# define machine_is_ml7304() (0) -#endif - -#ifdef CONFIG_MACH_UCP250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UCP250 -# endif -# define machine_is_ucp250() (machine_arch_type == MACH_TYPE_UCP250) -#else -# define machine_is_ucp250() (0) -#endif - -#ifdef CONFIG_MACH_INTBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INTBOARD -# endif -# define machine_is_intboard() (machine_arch_type == MACH_TYPE_INTBOARD) -#else -# define machine_is_intboard() (0) -#endif - -#ifdef CONFIG_MACH_GULFSTREAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GULFSTREAM -# endif -# define machine_is_gulfstream() (machine_arch_type == MACH_TYPE_GULFSTREAM) -#else -# define machine_is_gulfstream() (0) -#endif - -#ifdef CONFIG_MACH_LABQUEST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LABQUEST -# endif -# define machine_is_labquest() (machine_arch_type == MACH_TYPE_LABQUEST) -#else -# define machine_is_labquest() (0) -#endif - -#ifdef CONFIG_MACH_VCMX313 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VCMX313 -# endif -# define machine_is_vcmx313() (machine_arch_type == MACH_TYPE_VCMX313) -#else -# define machine_is_vcmx313() (0) -#endif - -#ifdef CONFIG_MACH_URG200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_URG200 -# endif -# define machine_is_urg200() (machine_arch_type == MACH_TYPE_URG200) -#else -# define machine_is_urg200() (0) -#endif - -#ifdef CONFIG_MACH_CPUX255LCDNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUX255LCDNET -# endif -# define machine_is_cpux255lcdnet() (machine_arch_type == MACH_TYPE_CPUX255LCDNET) -#else -# define machine_is_cpux255lcdnet() (0) -#endif - -#ifdef CONFIG_MACH_NETDCU9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETDCU9 -# endif -# define machine_is_netdcu9() (machine_arch_type == MACH_TYPE_NETDCU9) -#else -# define machine_is_netdcu9() (0) -#endif - -#ifdef CONFIG_MACH_NETDCU10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETDCU10 -# endif -# define machine_is_netdcu10() (machine_arch_type == MACH_TYPE_NETDCU10) -#else -# define machine_is_netdcu10() (0) -#endif - -#ifdef CONFIG_MACH_DSPG_DGA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSPG_DGA -# endif -# define machine_is_dspg_dga() (machine_arch_type == MACH_TYPE_DSPG_DGA) -#else -# define machine_is_dspg_dga() (0) -#endif - -#ifdef CONFIG_MACH_DSPG_DVW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSPG_DVW -# endif -# define machine_is_dspg_dvw() (machine_arch_type == MACH_TYPE_DSPG_DVW) -#else -# define machine_is_dspg_dvw() (0) -#endif - -#ifdef CONFIG_MACH_SOLOS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOLOS -# endif -# define machine_is_solos() (machine_arch_type == MACH_TYPE_SOLOS) -#else -# define machine_is_solos() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9263EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9263EK -# endif -# define machine_is_at91sam9263ek() (machine_arch_type == MACH_TYPE_AT91SAM9263EK) -#else -# define machine_is_at91sam9263ek() (0) -#endif - -#ifdef CONFIG_MACH_OSSTBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSSTBOX -# endif -# define machine_is_osstbox() (machine_arch_type == MACH_TYPE_OSSTBOX) -#else -# define machine_is_osstbox() (0) -#endif - -#ifdef CONFIG_MACH_KBAT9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KBAT9261 -# endif -# define machine_is_kbat9261() (machine_arch_type == MACH_TYPE_KBAT9261) -#else -# define machine_is_kbat9261() (0) -#endif - -#ifdef CONFIG_MACH_CT1100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CT1100 -# endif -# define machine_is_ct1100() (machine_arch_type == MACH_TYPE_CT1100) -#else -# define machine_is_ct1100() (0) -#endif - -#ifdef CONFIG_MACH_AKCPPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AKCPPXA -# endif -# define machine_is_akcppxa() (machine_arch_type == MACH_TYPE_AKCPPXA) -#else -# define machine_is_akcppxa() (0) -#endif - -#ifdef CONFIG_MACH_OCHAYA1020 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCHAYA1020 -# endif -# define machine_is_ochaya1020() (machine_arch_type == MACH_TYPE_OCHAYA1020) -#else -# define machine_is_ochaya1020() (0) -#endif - -#ifdef CONFIG_MACH_HITRACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HITRACK -# endif -# define machine_is_hitrack() (machine_arch_type == MACH_TYPE_HITRACK) -#else -# define machine_is_hitrack() (0) -#endif - -#ifdef CONFIG_MACH_SYME1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYME1 -# endif -# define machine_is_syme1() (machine_arch_type == MACH_TYPE_SYME1) -#else -# define machine_is_syme1() (0) -#endif - -#ifdef CONFIG_MACH_SYHL1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYHL1 -# endif -# define machine_is_syhl1() (machine_arch_type == MACH_TYPE_SYHL1) -#else -# define machine_is_syhl1() (0) -#endif - -#ifdef CONFIG_MACH_EMPCA400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPCA400 -# endif -# define machine_is_empca400() (machine_arch_type == MACH_TYPE_EMPCA400) -#else -# define machine_is_empca400() (0) -#endif - -#ifdef CONFIG_MACH_EM7210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EM7210 -# endif -# define machine_is_em7210() (machine_arch_type == MACH_TYPE_EM7210) -#else -# define machine_is_em7210() (0) -#endif - -#ifdef CONFIG_MACH_HTCHERMES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCHERMES -# endif -# define machine_is_htchermes() (machine_arch_type == MACH_TYPE_HTCHERMES) -#else -# define machine_is_htchermes() (0) -#endif - -#ifdef CONFIG_MACH_ETI_C1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETI_C1 -# endif -# define machine_is_eti_c1() (machine_arch_type == MACH_TYPE_ETI_C1) -#else -# define machine_is_eti_c1() (0) -#endif - -#ifdef CONFIG_MACH_AC100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AC100 -# endif -# define machine_is_ac100() (machine_arch_type == MACH_TYPE_AC100) -#else -# define machine_is_ac100() (0) -#endif - -#ifdef CONFIG_MACH_SNEETCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNEETCH -# endif -# define machine_is_sneetch() (machine_arch_type == MACH_TYPE_SNEETCH) -#else -# define machine_is_sneetch() (0) -#endif - -#ifdef CONFIG_MACH_STUDENTMATE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STUDENTMATE -# endif -# define machine_is_studentmate() (machine_arch_type == MACH_TYPE_STUDENTMATE) -#else -# define machine_is_studentmate() (0) -#endif - -#ifdef CONFIG_MACH_ZIR2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR2410 -# endif -# define machine_is_zir2410() (machine_arch_type == MACH_TYPE_ZIR2410) -#else -# define machine_is_zir2410() (0) -#endif - -#ifdef CONFIG_MACH_ZIR2413 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR2413 -# endif -# define machine_is_zir2413() (machine_arch_type == MACH_TYPE_ZIR2413) -#else -# define machine_is_zir2413() (0) -#endif - -#ifdef CONFIG_MACH_DLONIP3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DLONIP3 -# endif -# define machine_is_dlonip3() (machine_arch_type == MACH_TYPE_DLONIP3) -#else -# define machine_is_dlonip3() (0) -#endif - -#ifdef CONFIG_MACH_INSTREAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INSTREAM -# endif -# define machine_is_instream() (machine_arch_type == MACH_TYPE_INSTREAM) -#else -# define machine_is_instream() (0) -#endif - -#ifdef CONFIG_MACH_AMBARELLA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AMBARELLA -# endif -# define machine_is_ambarella() (machine_arch_type == MACH_TYPE_AMBARELLA) -#else -# define machine_is_ambarella() (0) -#endif - -#ifdef CONFIG_MACH_NEVIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEVIS -# endif -# define machine_is_nevis() (machine_arch_type == MACH_TYPE_NEVIS) -#else -# define machine_is_nevis() (0) -#endif - -#ifdef CONFIG_MACH_HTC_TRINITY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_TRINITY -# endif -# define machine_is_htc_trinity() (machine_arch_type == MACH_TYPE_HTC_TRINITY) -#else -# define machine_is_htc_trinity() (0) -#endif - -#ifdef CONFIG_MACH_QL202B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QL202B -# endif -# define machine_is_ql202b() (machine_arch_type == MACH_TYPE_QL202B) -#else -# define machine_is_ql202b() (0) -#endif - -#ifdef CONFIG_MACH_VPAC270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VPAC270 -# endif -# define machine_is_vpac270() (machine_arch_type == MACH_TYPE_VPAC270) -#else -# define machine_is_vpac270() (0) -#endif - -#ifdef CONFIG_MACH_RD129 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD129 -# endif -# define machine_is_rd129() (machine_arch_type == MACH_TYPE_RD129) -#else -# define machine_is_rd129() (0) -#endif - -#ifdef CONFIG_MACH_HTCWIZARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCWIZARD -# endif -# define machine_is_htcwizard() (machine_arch_type == MACH_TYPE_HTCWIZARD) -#else -# define machine_is_htcwizard() (0) -#endif - -#ifdef CONFIG_MACH_XSCALE_TREO680 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XSCALE_TREO680 -# endif -# define machine_is_xscale_treo680() (machine_arch_type == MACH_TYPE_XSCALE_TREO680) -#else -# define machine_is_xscale_treo680() (0) -#endif - -#ifdef CONFIG_MACH_TECON_TMEZON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TECON_TMEZON -# endif -# define machine_is_tecon_tmezon() (machine_arch_type == MACH_TYPE_TECON_TMEZON) -#else -# define machine_is_tecon_tmezon() (0) -#endif - -#ifdef CONFIG_MACH_ZYLONITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZYLONITE -# endif -# define machine_is_zylonite() (machine_arch_type == MACH_TYPE_ZYLONITE) -#else -# define machine_is_zylonite() (0) -#endif - -#ifdef CONFIG_MACH_GENE1270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GENE1270 -# endif -# define machine_is_gene1270() (machine_arch_type == MACH_TYPE_GENE1270) -#else -# define machine_is_gene1270() (0) -#endif - -#ifdef CONFIG_MACH_ZIR2412 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR2412 -# endif -# define machine_is_zir2412() (machine_arch_type == MACH_TYPE_ZIR2412) -#else -# define machine_is_zir2412() (0) -#endif - -#ifdef CONFIG_MACH_MX31LITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31LITE -# endif -# define machine_is_mx31lite() (machine_arch_type == MACH_TYPE_MX31LITE) -#else -# define machine_is_mx31lite() (0) -#endif - -#ifdef CONFIG_MACH_T700WX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T700WX -# endif -# define machine_is_t700wx() (machine_arch_type == MACH_TYPE_T700WX) -#else -# define machine_is_t700wx() (0) -#endif - -#ifdef CONFIG_MACH_VF100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VF100 -# endif -# define machine_is_vf100() (machine_arch_type == MACH_TYPE_VF100) -#else -# define machine_is_vf100() (0) -#endif - -#ifdef CONFIG_MACH_NSB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSB2 -# endif -# define machine_is_nsb2() (machine_arch_type == MACH_TYPE_NSB2) -#else -# define machine_is_nsb2() (0) -#endif - -#ifdef CONFIG_MACH_NXHMI_BB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXHMI_BB -# endif -# define machine_is_nxhmi_bb() (machine_arch_type == MACH_TYPE_NXHMI_BB) -#else -# define machine_is_nxhmi_bb() (0) -#endif - -#ifdef CONFIG_MACH_NXHMI_RE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXHMI_RE -# endif -# define machine_is_nxhmi_re() (machine_arch_type == MACH_TYPE_NXHMI_RE) -#else -# define machine_is_nxhmi_re() (0) -#endif - -#ifdef CONFIG_MACH_N4100PRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N4100PRO -# endif -# define machine_is_n4100pro() (machine_arch_type == MACH_TYPE_N4100PRO) -#else -# define machine_is_n4100pro() (0) -#endif - -#ifdef CONFIG_MACH_SAM9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM9260 -# endif -# define machine_is_sam9260() (machine_arch_type == MACH_TYPE_SAM9260) -#else -# define machine_is_sam9260() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_TREO600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_TREO600 -# endif -# define machine_is_omap_treo600() (machine_arch_type == MACH_TYPE_OMAP_TREO600) -#else -# define machine_is_omap_treo600() (0) -#endif - -#ifdef CONFIG_MACH_INDY2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INDY2410 -# endif -# define machine_is_indy2410() (machine_arch_type == MACH_TYPE_INDY2410) -#else -# define machine_is_indy2410() (0) -#endif - -#ifdef CONFIG_MACH_NELT_A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NELT_A -# endif -# define machine_is_nelt_a() (machine_arch_type == MACH_TYPE_NELT_A) -#else -# define machine_is_nelt_a() (0) -#endif - -#ifdef CONFIG_MACH_N311 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N311 -# endif -# define machine_is_n311() (machine_arch_type == MACH_TYPE_N311) -#else -# define machine_is_n311() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9260VGK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9260VGK -# endif -# define machine_is_at91sam9260vgk() (machine_arch_type == MACH_TYPE_AT91SAM9260VGK) -#else -# define machine_is_at91sam9260vgk() (0) -#endif - -#ifdef CONFIG_MACH_AT91LEPPE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91LEPPE -# endif -# define machine_is_at91leppe() (machine_arch_type == MACH_TYPE_AT91LEPPE) -#else -# define machine_is_at91leppe() (0) -#endif - -#ifdef CONFIG_MACH_AT91LEPCCN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91LEPCCN -# endif -# define machine_is_at91lepccn() (machine_arch_type == MACH_TYPE_AT91LEPCCN) -#else -# define machine_is_at91lepccn() (0) -#endif - -#ifdef CONFIG_MACH_APC7100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APC7100 -# endif -# define machine_is_apc7100() (machine_arch_type == MACH_TYPE_APC7100) -#else -# define machine_is_apc7100() (0) -#endif - -#ifdef CONFIG_MACH_STARGAZER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STARGAZER -# endif -# define machine_is_stargazer() (machine_arch_type == MACH_TYPE_STARGAZER) -#else -# define machine_is_stargazer() (0) -#endif - -#ifdef CONFIG_MACH_SONATA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SONATA -# endif -# define machine_is_sonata() (machine_arch_type == MACH_TYPE_SONATA) -#else -# define machine_is_sonata() (0) -#endif - -#ifdef CONFIG_MACH_SCHMOOGIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCHMOOGIE -# endif -# define machine_is_schmoogie() (machine_arch_type == MACH_TYPE_SCHMOOGIE) -#else -# define machine_is_schmoogie() (0) -#endif - -#ifdef CONFIG_MACH_AZTOOL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AZTOOL -# endif -# define machine_is_aztool() (machine_arch_type == MACH_TYPE_AZTOOL) -#else -# define machine_is_aztool() (0) -#endif - -#ifdef CONFIG_MACH_MIOA701 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIOA701 -# endif -# define machine_is_mioa701() (machine_arch_type == MACH_TYPE_MIOA701) -#else -# define machine_is_mioa701() (0) -#endif - -#ifdef CONFIG_MACH_SXNI9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SXNI9260 -# endif -# define machine_is_sxni9260() (machine_arch_type == MACH_TYPE_SXNI9260) -#else -# define machine_is_sxni9260() (0) -#endif - -#ifdef CONFIG_MACH_MXC27520EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC27520EVB -# endif -# define machine_is_mxc27520evb() (machine_arch_type == MACH_TYPE_MXC27520EVB) -#else -# define machine_is_mxc27520evb() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO5X0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO5X0 -# endif -# define machine_is_armadillo5x0() (machine_arch_type == MACH_TYPE_ARMADILLO5X0) -#else -# define machine_is_armadillo5x0() (0) -#endif - -#ifdef CONFIG_MACH_MB9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB9260 -# endif -# define machine_is_mb9260() (machine_arch_type == MACH_TYPE_MB9260) -#else -# define machine_is_mb9260() (0) -#endif - -#ifdef CONFIG_MACH_MB9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB9263 -# endif -# define machine_is_mb9263() (machine_arch_type == MACH_TYPE_MB9263) -#else -# define machine_is_mb9263() (0) -#endif - -#ifdef CONFIG_MACH_IPAC9302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPAC9302 -# endif -# define machine_is_ipac9302() (machine_arch_type == MACH_TYPE_IPAC9302) -#else -# define machine_is_ipac9302() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9360JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9360JS -# endif -# define machine_is_cc9p9360js() (machine_arch_type == MACH_TYPE_CC9P9360JS) -#else -# define machine_is_cc9p9360js() (0) -#endif - -#ifdef CONFIG_MACH_GALLIUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GALLIUM -# endif -# define machine_is_gallium() (machine_arch_type == MACH_TYPE_GALLIUM) -#else -# define machine_is_gallium() (0) -#endif - -#ifdef CONFIG_MACH_MSC2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSC2410 -# endif -# define machine_is_msc2410() (machine_arch_type == MACH_TYPE_MSC2410) -#else -# define machine_is_msc2410() (0) -#endif - -#ifdef CONFIG_MACH_GHI270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GHI270 -# endif -# define machine_is_ghi270() (machine_arch_type == MACH_TYPE_GHI270) -#else -# define machine_is_ghi270() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_LEONARDO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_LEONARDO -# endif -# define machine_is_davinci_leonardo() (machine_arch_type == MACH_TYPE_DAVINCI_LEONARDO) -#else -# define machine_is_davinci_leonardo() (0) -#endif - -#ifdef CONFIG_MACH_OIAB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OIAB -# endif -# define machine_is_oiab() (machine_arch_type == MACH_TYPE_OIAB) -#else -# define machine_is_oiab() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6400 -# endif -# define machine_is_smdk6400() (machine_arch_type == MACH_TYPE_SMDK6400) -#else -# define machine_is_smdk6400() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_N800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_N800 -# endif -# define machine_is_nokia_n800() (machine_arch_type == MACH_TYPE_NOKIA_N800) -#else -# define machine_is_nokia_n800() (0) -#endif - -#ifdef CONFIG_MACH_GREENPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GREENPHONE -# endif -# define machine_is_greenphone() (machine_arch_type == MACH_TYPE_GREENPHONE) -#else -# define machine_is_greenphone() (0) -#endif - -#ifdef CONFIG_MACH_COMPEXWP18 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMPEXWP18 -# endif -# define machine_is_compex42x() (machine_arch_type == MACH_TYPE_COMPEXWP18) -#else -# define machine_is_compex42x() (0) -#endif - -#ifdef CONFIG_MACH_XMATE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XMATE -# endif -# define machine_is_xmate() (machine_arch_type == MACH_TYPE_XMATE) -#else -# define machine_is_xmate() (0) -#endif - -#ifdef CONFIG_MACH_ENERGIZER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENERGIZER -# endif -# define machine_is_energizer() (machine_arch_type == MACH_TYPE_ENERGIZER) -#else -# define machine_is_energizer() (0) -#endif - -#ifdef CONFIG_MACH_IME1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IME1 -# endif -# define machine_is_ime1() (machine_arch_type == MACH_TYPE_IME1) -#else -# define machine_is_ime1() (0) -#endif - -#ifdef CONFIG_MACH_SWEDATMS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWEDATMS -# endif -# define machine_is_sweda_tms() (machine_arch_type == MACH_TYPE_SWEDATMS) -#else -# define machine_is_sweda_tms() (0) -#endif - -#ifdef CONFIG_MACH_NTNP435C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NTNP435C -# endif -# define machine_is_ntnp435c() (machine_arch_type == MACH_TYPE_NTNP435C) -#else -# define machine_is_ntnp435c() (0) -#endif - -#ifdef CONFIG_MACH_SPECTRO2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPECTRO2 -# endif -# define machine_is_spectro2() (machine_arch_type == MACH_TYPE_SPECTRO2) -#else -# define machine_is_spectro2() (0) -#endif - -#ifdef CONFIG_MACH_H6039 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6039 -# endif -# define machine_is_h6039() (machine_arch_type == MACH_TYPE_H6039) -#else -# define machine_is_h6039() (0) -#endif - -#ifdef CONFIG_MACH_EP80219 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EP80219 -# endif -# define machine_is_ep80219() (machine_arch_type == MACH_TYPE_EP80219) -#else -# define machine_is_ep80219() (0) -#endif - -#ifdef CONFIG_MACH_SAMOA_II -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAMOA_II -# endif -# define machine_is_samoa_ii() (machine_arch_type == MACH_TYPE_SAMOA_II) -#else -# define machine_is_samoa_ii() (0) -#endif - -#ifdef CONFIG_MACH_CWMXL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWMXL -# endif -# define machine_is_cwmxl() (machine_arch_type == MACH_TYPE_CWMXL) -#else -# define machine_is_cwmxl() (0) -#endif - -#ifdef CONFIG_MACH_AS9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AS9200 -# endif -# define machine_is_as9200() (machine_arch_type == MACH_TYPE_AS9200) -#else -# define machine_is_as9200() (0) -#endif - -#ifdef CONFIG_MACH_SFX1149 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SFX1149 -# endif -# define machine_is_sfx1149() (machine_arch_type == MACH_TYPE_SFX1149) -#else -# define machine_is_sfx1149() (0) -#endif - -#ifdef CONFIG_MACH_NAVI010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAVI010 -# endif -# define machine_is_navi010() (machine_arch_type == MACH_TYPE_NAVI010) -#else -# define machine_is_navi010() (0) -#endif - -#ifdef CONFIG_MACH_MULTMDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTMDP -# endif -# define machine_is_multmdp() (machine_arch_type == MACH_TYPE_MULTMDP) -#else -# define machine_is_multmdp() (0) -#endif - -#ifdef CONFIG_MACH_SCB9520 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCB9520 -# endif -# define machine_is_scb9520() (machine_arch_type == MACH_TYPE_SCB9520) -#else -# define machine_is_scb9520() (0) -#endif - -#ifdef CONFIG_MACH_HTCATHENA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCATHENA -# endif -# define machine_is_htcathena() (machine_arch_type == MACH_TYPE_HTCATHENA) -#else -# define machine_is_htcathena() (0) -#endif - -#ifdef CONFIG_MACH_XP179 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XP179 -# endif -# define machine_is_xp179() (machine_arch_type == MACH_TYPE_XP179) -#else -# define machine_is_xp179() (0) -#endif - -#ifdef CONFIG_MACH_H4300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H4300 -# endif -# define machine_is_h4300() (machine_arch_type == MACH_TYPE_H4300) -#else -# define machine_is_h4300() (0) -#endif - -#ifdef CONFIG_MACH_GORAMO_MLR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GORAMO_MLR -# endif -# define machine_is_goramo_mlr() (machine_arch_type == MACH_TYPE_GORAMO_MLR) -#else -# define machine_is_goramo_mlr() (0) -#endif - -#ifdef CONFIG_MACH_MXC30020EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30020EVB -# endif -# define machine_is_mxc30020evb() (machine_arch_type == MACH_TYPE_MXC30020EVB) -#else -# define machine_is_mxc30020evb() (0) -#endif - -#ifdef CONFIG_MACH_ADSBITSYG5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSYG5 -# endif -# define machine_is_adsbitsyg5() (machine_arch_type == MACH_TYPE_ADSBITSYG5) -#else -# define machine_is_adsbitsyg5() (0) -#endif - -#ifdef CONFIG_MACH_ADSPORTALPLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSPORTALPLUS -# endif -# define machine_is_adsportalplus() (machine_arch_type == MACH_TYPE_ADSPORTALPLUS) -#else -# define machine_is_adsportalplus() (0) -#endif - -#ifdef CONFIG_MACH_MMSP2PLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMSP2PLUS -# endif -# define machine_is_mmsp2plus() (machine_arch_type == MACH_TYPE_MMSP2PLUS) -#else -# define machine_is_mmsp2plus() (0) -#endif - -#ifdef CONFIG_MACH_EM_X270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EM_X270 -# endif -# define machine_is_em_x270() (machine_arch_type == MACH_TYPE_EM_X270) -#else -# define machine_is_em_x270() (0) -#endif - -#ifdef CONFIG_MACH_TPP302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPP302 -# endif -# define machine_is_tpp302() (machine_arch_type == MACH_TYPE_TPP302) -#else -# define machine_is_tpp302() (0) -#endif - -#ifdef CONFIG_MACH_TPM104 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPM104 -# endif -# define machine_is_tpp104() (machine_arch_type == MACH_TYPE_TPM104) -#else -# define machine_is_tpp104() (0) -#endif - -#ifdef CONFIG_MACH_TPM102 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPM102 -# endif -# define machine_is_tpm102() (machine_arch_type == MACH_TYPE_TPM102) -#else -# define machine_is_tpm102() (0) -#endif - -#ifdef CONFIG_MACH_TPM109 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPM109 -# endif -# define machine_is_tpm109() (machine_arch_type == MACH_TYPE_TPM109) -#else -# define machine_is_tpm109() (0) -#endif - -#ifdef CONFIG_MACH_FBXO1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FBXO1 -# endif -# define machine_is_fbxo1() (machine_arch_type == MACH_TYPE_FBXO1) -#else -# define machine_is_fbxo1() (0) -#endif - -#ifdef CONFIG_MACH_HXD8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HXD8 -# endif -# define machine_is_hxd8() (machine_arch_type == MACH_TYPE_HXD8) -#else -# define machine_is_hxd8() (0) -#endif - -#ifdef CONFIG_MACH_NEO1973_GTA02 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEO1973_GTA02 -# endif -# define machine_is_neo1973_gta02() (machine_arch_type == MACH_TYPE_NEO1973_GTA02) -#else -# define machine_is_neo1973_gta02() (0) -#endif - -#ifdef CONFIG_MACH_EMTEST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMTEST -# endif -# define machine_is_emtest() (machine_arch_type == MACH_TYPE_EMTEST) -#else -# define machine_is_emtest() (0) -#endif - -#ifdef CONFIG_MACH_AD6900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AD6900 -# endif -# define machine_is_ad6900() (machine_arch_type == MACH_TYPE_AD6900) -#else -# define machine_is_ad6900() (0) -#endif - -#ifdef CONFIG_MACH_EUROPA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EUROPA -# endif -# define machine_is_europa() (machine_arch_type == MACH_TYPE_EUROPA) -#else -# define machine_is_europa() (0) -#endif - -#ifdef CONFIG_MACH_METROCONNECT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_METROCONNECT -# endif -# define machine_is_metroconnect() (machine_arch_type == MACH_TYPE_METROCONNECT) -#else -# define machine_is_metroconnect() (0) -#endif - -#ifdef CONFIG_MACH_EZ_S2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_S2410 -# endif -# define machine_is_ez_s2410() (machine_arch_type == MACH_TYPE_EZ_S2410) -#else -# define machine_is_ez_s2410() (0) -#endif - -#ifdef CONFIG_MACH_EZ_S2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_S2440 -# endif -# define machine_is_ez_s2440() (machine_arch_type == MACH_TYPE_EZ_S2440) -#else -# define machine_is_ez_s2440() (0) -#endif - -#ifdef CONFIG_MACH_EZ_EP9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_EP9312 -# endif -# define machine_is_ez_ep9312() (machine_arch_type == MACH_TYPE_EZ_EP9312) -#else -# define machine_is_ez_ep9312() (0) -#endif - -#ifdef CONFIG_MACH_EZ_EP9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_EP9315 -# endif -# define machine_is_ez_ep9315() (machine_arch_type == MACH_TYPE_EZ_EP9315) -#else -# define machine_is_ez_ep9315() (0) -#endif - -#ifdef CONFIG_MACH_EZ_X7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_X7 -# endif -# define machine_is_ez_x7() (machine_arch_type == MACH_TYPE_EZ_X7) -#else -# define machine_is_ez_x7() (0) -#endif - -#ifdef CONFIG_MACH_GODOTDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GODOTDB -# endif -# define machine_is_godotdb() (machine_arch_type == MACH_TYPE_GODOTDB) -#else -# define machine_is_godotdb() (0) -#endif - -#ifdef CONFIG_MACH_MISTRAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MISTRAL -# endif -# define machine_is_mistral() (machine_arch_type == MACH_TYPE_MISTRAL) -#else -# define machine_is_mistral() (0) -#endif - -#ifdef CONFIG_MACH_MSM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM -# endif -# define machine_is_msm() (machine_arch_type == MACH_TYPE_MSM) -#else -# define machine_is_msm() (0) -#endif - -#ifdef CONFIG_MACH_CT5910 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CT5910 -# endif -# define machine_is_ct5910() (machine_arch_type == MACH_TYPE_CT5910) -#else -# define machine_is_ct5910() (0) -#endif - -#ifdef CONFIG_MACH_CT5912 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CT5912 -# endif -# define machine_is_ct5912() (machine_arch_type == MACH_TYPE_CT5912) -#else -# define machine_is_ct5912() (0) -#endif - -#ifdef CONFIG_MACH_HYNET_INE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HYNET_INE -# endif -# define machine_is_hynet_ine() (machine_arch_type == MACH_TYPE_HYNET_INE) -#else -# define machine_is_hynet_ine() (0) -#endif - -#ifdef CONFIG_MACH_HYNET_APP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HYNET_APP -# endif -# define machine_is_hynet_app() (machine_arch_type == MACH_TYPE_HYNET_APP) -#else -# define machine_is_hynet_app() (0) -#endif - -#ifdef CONFIG_MACH_MSM7200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7200 -# endif -# define machine_is_msm7200() (machine_arch_type == MACH_TYPE_MSM7200) -#else -# define machine_is_msm7200() (0) -#endif - -#ifdef CONFIG_MACH_MSM7600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7600 -# endif -# define machine_is_msm7600() (machine_arch_type == MACH_TYPE_MSM7600) -#else -# define machine_is_msm7600() (0) -#endif - -#ifdef CONFIG_MACH_CEB255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CEB255 -# endif -# define machine_is_ceb255() (machine_arch_type == MACH_TYPE_CEB255) -#else -# define machine_is_ceb255() (0) -#endif - -#ifdef CONFIG_MACH_CIEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CIEL -# endif -# define machine_is_ciel() (machine_arch_type == MACH_TYPE_CIEL) -#else -# define machine_is_ciel() (0) -#endif - -#ifdef CONFIG_MACH_SLM5650 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SLM5650 -# endif -# define machine_is_slm5650() (machine_arch_type == MACH_TYPE_SLM5650) -#else -# define machine_is_slm5650() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9RLEK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9RLEK -# endif -# define machine_is_at91sam9rlek() (machine_arch_type == MACH_TYPE_AT91SAM9RLEK) -#else -# define machine_is_at91sam9rlek() (0) -#endif - -#ifdef CONFIG_MACH_COMTECH_ROUTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMTECH_ROUTER -# endif -# define machine_is_comtech_router() (machine_arch_type == MACH_TYPE_COMTECH_ROUTER) -#else -# define machine_is_comtech_router() (0) -#endif - -#ifdef CONFIG_MACH_SBC2410X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC2410X -# endif -# define machine_is_sbc2410x() (machine_arch_type == MACH_TYPE_SBC2410X) -#else -# define machine_is_sbc2410x() (0) -#endif - -#ifdef CONFIG_MACH_AT4X0BD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT4X0BD -# endif -# define machine_is_at4x0bd() (machine_arch_type == MACH_TYPE_AT4X0BD) -#else -# define machine_is_at4x0bd() (0) -#endif - -#ifdef CONFIG_MACH_CBIFR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CBIFR -# endif -# define machine_is_cbifr() (machine_arch_type == MACH_TYPE_CBIFR) -#else -# define machine_is_cbifr() (0) -#endif - -#ifdef CONFIG_MACH_ARCOM_QUANTUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCOM_QUANTUM -# endif -# define machine_is_arcom_quantum() (machine_arch_type == MACH_TYPE_ARCOM_QUANTUM) -#else -# define machine_is_arcom_quantum() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX520 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX520 -# endif -# define machine_is_matrix520() (machine_arch_type == MACH_TYPE_MATRIX520) -#else -# define machine_is_matrix520() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX510 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX510 -# endif -# define machine_is_matrix510() (machine_arch_type == MACH_TYPE_MATRIX510) -#else -# define machine_is_matrix510() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX500 -# endif -# define machine_is_matrix500() (machine_arch_type == MACH_TYPE_MATRIX500) -#else -# define machine_is_matrix500() (0) -#endif - -#ifdef CONFIG_MACH_M501 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M501 -# endif -# define machine_is_m501() (machine_arch_type == MACH_TYPE_M501) -#else -# define machine_is_m501() (0) -#endif - -#ifdef CONFIG_MACH_AAEON1270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AAEON1270 -# endif -# define machine_is_aaeon1270() (machine_arch_type == MACH_TYPE_AAEON1270) -#else -# define machine_is_aaeon1270() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX500EV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX500EV -# endif -# define machine_is_matrix500ev() (machine_arch_type == MACH_TYPE_MATRIX500EV) -#else -# define machine_is_matrix500ev() (0) -#endif - -#ifdef CONFIG_MACH_PAC500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PAC500 -# endif -# define machine_is_pac500() (machine_arch_type == MACH_TYPE_PAC500) -#else -# define machine_is_pac500() (0) -#endif - -#ifdef CONFIG_MACH_PNX8181 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX8181 -# endif -# define machine_is_pnx8181() (machine_arch_type == MACH_TYPE_PNX8181) -#else -# define machine_is_pnx8181() (0) -#endif - -#ifdef CONFIG_MACH_COLIBRI320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLIBRI320 -# endif -# define machine_is_colibri320() (machine_arch_type == MACH_TYPE_COLIBRI320) -#else -# define machine_is_colibri320() (0) -#endif - -#ifdef CONFIG_MACH_AZTOOLBB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AZTOOLBB -# endif -# define machine_is_aztoolbb() (machine_arch_type == MACH_TYPE_AZTOOLBB) -#else -# define machine_is_aztoolbb() (0) -#endif - -#ifdef CONFIG_MACH_AZTOOLG2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AZTOOLG2 -# endif -# define machine_is_aztoolg2() (machine_arch_type == MACH_TYPE_AZTOOLG2) -#else -# define machine_is_aztoolg2() (0) -#endif - -#ifdef CONFIG_MACH_DVLHOST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DVLHOST -# endif -# define machine_is_dvlhost() (machine_arch_type == MACH_TYPE_DVLHOST) -#else -# define machine_is_dvlhost() (0) -#endif - -#ifdef CONFIG_MACH_ZIR9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR9200 -# endif -# define machine_is_zir9200() (machine_arch_type == MACH_TYPE_ZIR9200) -#else -# define machine_is_zir9200() (0) -#endif - -#ifdef CONFIG_MACH_ZIR9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR9260 -# endif -# define machine_is_zir9260() (machine_arch_type == MACH_TYPE_ZIR9260) -#else -# define machine_is_zir9260() (0) -#endif - -#ifdef CONFIG_MACH_COCOPAH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COCOPAH -# endif -# define machine_is_cocopah() (machine_arch_type == MACH_TYPE_COCOPAH) -#else -# define machine_is_cocopah() (0) -#endif - -#ifdef CONFIG_MACH_NDS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NDS -# endif -# define machine_is_nds() (machine_arch_type == MACH_TYPE_NDS) -#else -# define machine_is_nds() (0) -#endif - -#ifdef CONFIG_MACH_ROSENCRANTZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROSENCRANTZ -# endif -# define machine_is_rosencrantz() (machine_arch_type == MACH_TYPE_ROSENCRANTZ) -#else -# define machine_is_rosencrantz() (0) -#endif - -#ifdef CONFIG_MACH_FTTX_ODSC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FTTX_ODSC -# endif -# define machine_is_fttx_odsc() (machine_arch_type == MACH_TYPE_FTTX_ODSC) -#else -# define machine_is_fttx_odsc() (0) -#endif - -#ifdef CONFIG_MACH_CLASSE_R6904 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLASSE_R6904 -# endif -# define machine_is_classe_r6904() (machine_arch_type == MACH_TYPE_CLASSE_R6904) -#else -# define machine_is_classe_r6904() (0) -#endif - -#ifdef CONFIG_MACH_CAM60 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAM60 -# endif -# define machine_is_cam60() (machine_arch_type == MACH_TYPE_CAM60) -#else -# define machine_is_cam60() (0) -#endif - -#ifdef CONFIG_MACH_MXC30031ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30031ADS -# endif -# define machine_is_mxc30031ads() (machine_arch_type == MACH_TYPE_MXC30031ADS) -#else -# define machine_is_mxc30031ads() (0) -#endif - -#ifdef CONFIG_MACH_DATACALL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DATACALL -# endif -# define machine_is_datacall() (machine_arch_type == MACH_TYPE_DATACALL) -#else -# define machine_is_datacall() (0) -#endif - -#ifdef CONFIG_MACH_AT91EB01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91EB01 -# endif -# define machine_is_at91eb01() (machine_arch_type == MACH_TYPE_AT91EB01) -#else -# define machine_is_at91eb01() (0) -#endif - -#ifdef CONFIG_MACH_RTY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RTY -# endif -# define machine_is_rty() (machine_arch_type == MACH_TYPE_RTY) -#else -# define machine_is_rty() (0) -#endif - -#ifdef CONFIG_MACH_DWL2100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DWL2100 -# endif -# define machine_is_dwl2100() (machine_arch_type == MACH_TYPE_DWL2100) -#else -# define machine_is_dwl2100() (0) -#endif - -#ifdef CONFIG_MACH_VINSI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VINSI -# endif -# define machine_is_vinsi() (machine_arch_type == MACH_TYPE_VINSI) -#else -# define machine_is_vinsi() (0) -#endif - -#ifdef CONFIG_MACH_DB88F5281 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DB88F5281 -# endif -# define machine_is_db88f5281() (machine_arch_type == MACH_TYPE_DB88F5281) -#else -# define machine_is_db88f5281() (0) -#endif - -#ifdef CONFIG_MACH_CSB726 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB726 -# endif -# define machine_is_csb726() (machine_arch_type == MACH_TYPE_CSB726) -#else -# define machine_is_csb726() (0) -#endif - -#ifdef CONFIG_MACH_TIK27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TIK27 -# endif -# define machine_is_tik27() (machine_arch_type == MACH_TYPE_TIK27) -#else -# define machine_is_tik27() (0) -#endif - -#ifdef CONFIG_MACH_MX_UC7420 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX_UC7420 -# endif -# define machine_is_mx_uc7420() (machine_arch_type == MACH_TYPE_MX_UC7420) -#else -# define machine_is_mx_uc7420() (0) -#endif - -#ifdef CONFIG_MACH_RIRM3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIRM3 -# endif -# define machine_is_rirm3() (machine_arch_type == MACH_TYPE_RIRM3) -#else -# define machine_is_rirm3() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_ODYSSEY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_ODYSSEY -# endif -# define machine_is_pelco_odyssey() (machine_arch_type == MACH_TYPE_PELCO_ODYSSEY) -#else -# define machine_is_pelco_odyssey() (0) -#endif - -#ifdef CONFIG_MACH_ADX_ABOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_ABOX -# endif -# define machine_is_adx_abox() (machine_arch_type == MACH_TYPE_ADX_ABOX) -#else -# define machine_is_adx_abox() (0) -#endif - -#ifdef CONFIG_MACH_ADX_TPID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_TPID -# endif -# define machine_is_adx_tpid() (machine_arch_type == MACH_TYPE_ADX_TPID) -#else -# define machine_is_adx_tpid() (0) -#endif - -#ifdef CONFIG_MACH_MINICHECK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINICHECK -# endif -# define machine_is_minicheck() (machine_arch_type == MACH_TYPE_MINICHECK) -#else -# define machine_is_minicheck() (0) -#endif - -#ifdef CONFIG_MACH_IDAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IDAM -# endif -# define machine_is_idam() (machine_arch_type == MACH_TYPE_IDAM) -#else -# define machine_is_idam() (0) -#endif - -#ifdef CONFIG_MACH_MARIO_MX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARIO_MX -# endif -# define machine_is_mario_mx() (machine_arch_type == MACH_TYPE_MARIO_MX) -#else -# define machine_is_mario_mx() (0) -#endif - -#ifdef CONFIG_MACH_VI1888 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VI1888 -# endif -# define machine_is_vi1888() (machine_arch_type == MACH_TYPE_VI1888) -#else -# define machine_is_vi1888() (0) -#endif - -#ifdef CONFIG_MACH_ZR4230 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZR4230 -# endif -# define machine_is_zr4230() (machine_arch_type == MACH_TYPE_ZR4230) -#else -# define machine_is_zr4230() (0) -#endif - -#ifdef CONFIG_MACH_T1_IX_BLUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T1_IX_BLUE -# endif -# define machine_is_t1_ix_blue() (machine_arch_type == MACH_TYPE_T1_IX_BLUE) -#else -# define machine_is_t1_ix_blue() (0) -#endif - -#ifdef CONFIG_MACH_SYHQ2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYHQ2 -# endif -# define machine_is_syhq2() (machine_arch_type == MACH_TYPE_SYHQ2) -#else -# define machine_is_syhq2() (0) -#endif - -#ifdef CONFIG_MACH_COMPUTIME_R3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMPUTIME_R3 -# endif -# define machine_is_computime_r3() (machine_arch_type == MACH_TYPE_COMPUTIME_R3) -#else -# define machine_is_computime_r3() (0) -#endif - -#ifdef CONFIG_MACH_ORATIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATIS -# endif -# define machine_is_oratis() (machine_arch_type == MACH_TYPE_ORATIS) -#else -# define machine_is_oratis() (0) -#endif - -#ifdef CONFIG_MACH_MIKKO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIKKO -# endif -# define machine_is_mikko() (machine_arch_type == MACH_TYPE_MIKKO) -#else -# define machine_is_mikko() (0) -#endif - -#ifdef CONFIG_MACH_HOLON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HOLON -# endif -# define machine_is_holon() (machine_arch_type == MACH_TYPE_HOLON) -#else -# define machine_is_holon() (0) -#endif - -#ifdef CONFIG_MACH_OLIP8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OLIP8 -# endif -# define machine_is_olip8() (machine_arch_type == MACH_TYPE_OLIP8) -#else -# define machine_is_olip8() (0) -#endif - -#ifdef CONFIG_MACH_GHI270HG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GHI270HG -# endif -# define machine_is_ghi270hg() (machine_arch_type == MACH_TYPE_GHI270HG) -#else -# define machine_is_ghi270hg() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM6467_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM6467_EVM -# endif -# define machine_is_davinci_dm6467_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467_EVM) -#else -# define machine_is_davinci_dm6467_evm() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM355_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM355_EVM -# endif -# define machine_is_davinci_dm355_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM355_EVM) -#else -# define machine_is_davinci_dm355_evm() (0) -#endif - -#ifdef CONFIG_MACH_BLACKRIVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLACKRIVER -# endif -# define machine_is_blackriver() (machine_arch_type == MACH_TYPE_BLACKRIVER) -#else -# define machine_is_blackriver() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATEWP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATEWP -# endif -# define machine_is_sandgate_wp() (machine_arch_type == MACH_TYPE_SANDGATEWP) -#else -# define machine_is_sandgate_wp() (0) -#endif - -#ifdef CONFIG_MACH_CDOTBWSG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CDOTBWSG -# endif -# define machine_is_cdotbwsg() (machine_arch_type == MACH_TYPE_CDOTBWSG) -#else -# define machine_is_cdotbwsg() (0) -#endif - -#ifdef CONFIG_MACH_QUARK963 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUARK963 -# endif -# define machine_is_quark963() (machine_arch_type == MACH_TYPE_QUARK963) -#else -# define machine_is_quark963() (0) -#endif - -#ifdef CONFIG_MACH_CSB735 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB735 -# endif -# define machine_is_csb735() (machine_arch_type == MACH_TYPE_CSB735) -#else -# define machine_is_csb735() (0) -#endif - -#ifdef CONFIG_MACH_LITTLETON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LITTLETON -# endif -# define machine_is_littleton() (machine_arch_type == MACH_TYPE_LITTLETON) -#else -# define machine_is_littleton() (0) -#endif - -#ifdef CONFIG_MACH_MIO_P550 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIO_P550 -# endif -# define machine_is_mio_p550() (machine_arch_type == MACH_TYPE_MIO_P550) -#else -# define machine_is_mio_p550() (0) -#endif - -#ifdef CONFIG_MACH_MOTION2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTION2440 -# endif -# define machine_is_motion2440() (machine_arch_type == MACH_TYPE_MOTION2440) -#else -# define machine_is_motion2440() (0) -#endif - -#ifdef CONFIG_MACH_IMM500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMM500 -# endif -# define machine_is_imm500() (machine_arch_type == MACH_TYPE_IMM500) -#else -# define machine_is_imm500() (0) -#endif - -#ifdef CONFIG_MACH_HOMEMATIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HOMEMATIC -# endif -# define machine_is_homematic() (machine_arch_type == MACH_TYPE_HOMEMATIC) -#else -# define machine_is_homematic() (0) -#endif - -#ifdef CONFIG_MACH_ERMINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ERMINE -# endif -# define machine_is_ermine() (machine_arch_type == MACH_TYPE_ERMINE) -#else -# define machine_is_ermine() (0) -#endif - -#ifdef CONFIG_MACH_KB9202B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KB9202B -# endif -# define machine_is_kb9202b() (machine_arch_type == MACH_TYPE_KB9202B) -#else -# define machine_is_kb9202b() (0) -#endif - -#ifdef CONFIG_MACH_HS1XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HS1XX -# endif -# define machine_is_hs1xx() (machine_arch_type == MACH_TYPE_HS1XX) -#else -# define machine_is_hs1xx() (0) -#endif - -#ifdef CONFIG_MACH_STUDENTMATE2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STUDENTMATE2440 -# endif -# define machine_is_studentmate2440() (machine_arch_type == MACH_TYPE_STUDENTMATE2440) -#else -# define machine_is_studentmate2440() (0) -#endif - -#ifdef CONFIG_MACH_ARVOO_L1_Z1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARVOO_L1_Z1 -# endif -# define machine_is_arvoo_l1_z1() (machine_arch_type == MACH_TYPE_ARVOO_L1_Z1) -#else -# define machine_is_arvoo_l1_z1() (0) -#endif - -#ifdef CONFIG_MACH_DEP2410K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEP2410K -# endif -# define machine_is_dep2410k() (machine_arch_type == MACH_TYPE_DEP2410K) -#else -# define machine_is_dep2410k() (0) -#endif - -#ifdef CONFIG_MACH_XXSVIDEO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XXSVIDEO -# endif -# define machine_is_xxsvideo() (machine_arch_type == MACH_TYPE_XXSVIDEO) -#else -# define machine_is_xxsvideo() (0) -#endif - -#ifdef CONFIG_MACH_IM4004 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IM4004 -# endif -# define machine_is_im4004() (machine_arch_type == MACH_TYPE_IM4004) -#else -# define machine_is_im4004() (0) -#endif - -#ifdef CONFIG_MACH_OCHAYA1050 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCHAYA1050 -# endif -# define machine_is_ochaya1050() (machine_arch_type == MACH_TYPE_OCHAYA1050) -#else -# define machine_is_ochaya1050() (0) -#endif - -#ifdef CONFIG_MACH_LEP9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEP9261 -# endif -# define machine_is_lep9261() (machine_arch_type == MACH_TYPE_LEP9261) -#else -# define machine_is_lep9261() (0) -#endif - -#ifdef CONFIG_MACH_SVENMEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVENMEB -# endif -# define machine_is_svenmeb() (machine_arch_type == MACH_TYPE_SVENMEB) -#else -# define machine_is_svenmeb() (0) -#endif - -#ifdef CONFIG_MACH_FORTUNET2NE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FORTUNET2NE -# endif -# define machine_is_fortunet2ne() (machine_arch_type == MACH_TYPE_FORTUNET2NE) -#else -# define machine_is_fortunet2ne() (0) -#endif - -#ifdef CONFIG_MACH_NXHX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXHX -# endif -# define machine_is_nxhx() (machine_arch_type == MACH_TYPE_NXHX) -#else -# define machine_is_nxhx() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PB11MP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PB11MP -# endif -# define machine_is_realview_pb11mp() (machine_arch_type == MACH_TYPE_REALVIEW_PB11MP) -#else -# define machine_is_realview_pb11mp() (0) -#endif - -#ifdef CONFIG_MACH_IDS500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IDS500 -# endif -# define machine_is_ids500() (machine_arch_type == MACH_TYPE_IDS500) -#else -# define machine_is_ids500() (0) -#endif - -#ifdef CONFIG_MACH_ORS_N725 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORS_N725 -# endif -# define machine_is_ors_n725() (machine_arch_type == MACH_TYPE_ORS_N725) -#else -# define machine_is_ors_n725() (0) -#endif - -#ifdef CONFIG_MACH_HSDARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HSDARM -# endif -# define machine_is_hsdarm() (machine_arch_type == MACH_TYPE_HSDARM) -#else -# define machine_is_hsdarm() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON003 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON003 -# endif -# define machine_is_sha_pon003() (machine_arch_type == MACH_TYPE_SHA_PON003) -#else -# define machine_is_sha_pon003() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON004 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON004 -# endif -# define machine_is_sha_pon004() (machine_arch_type == MACH_TYPE_SHA_PON004) -#else -# define machine_is_sha_pon004() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON007 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON007 -# endif -# define machine_is_sha_pon007() (machine_arch_type == MACH_TYPE_SHA_PON007) -#else -# define machine_is_sha_pon007() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON011 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON011 -# endif -# define machine_is_sha_pon011() (machine_arch_type == MACH_TYPE_SHA_PON011) -#else -# define machine_is_sha_pon011() (0) -#endif - -#ifdef CONFIG_MACH_H6042 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6042 -# endif -# define machine_is_h6042() (machine_arch_type == MACH_TYPE_H6042) -#else -# define machine_is_h6042() (0) -#endif - -#ifdef CONFIG_MACH_H6043 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6043 -# endif -# define machine_is_h6043() (machine_arch_type == MACH_TYPE_H6043) -#else -# define machine_is_h6043() (0) -#endif - -#ifdef CONFIG_MACH_LOOXC550 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOXC550 -# endif -# define machine_is_looxc550() (machine_arch_type == MACH_TYPE_LOOXC550) -#else -# define machine_is_looxc550() (0) -#endif - -#ifdef CONFIG_MACH_CNTY_TITAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CNTY_TITAN -# endif -# define machine_is_cnty_titan() (machine_arch_type == MACH_TYPE_CNTY_TITAN) -#else -# define machine_is_cnty_titan() (0) -#endif - -#ifdef CONFIG_MACH_APP3XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APP3XX -# endif -# define machine_is_app3xx() (machine_arch_type == MACH_TYPE_APP3XX) -#else -# define machine_is_app3xx() (0) -#endif - -#ifdef CONFIG_MACH_SIDEOATSGRAMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIDEOATSGRAMA -# endif -# define machine_is_sideoatsgrama() (machine_arch_type == MACH_TYPE_SIDEOATSGRAMA) -#else -# define machine_is_sideoatsgrama() (0) -#endif - -#ifdef CONFIG_MACH_PALMTREO700P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTREO700P -# endif -# define machine_is_palmtreo700p() (machine_arch_type == MACH_TYPE_PALMTREO700P) -#else -# define machine_is_palmtreo700p() (0) -#endif - -#ifdef CONFIG_MACH_PALMTREO700W -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTREO700W -# endif -# define machine_is_palmtreo700w() (machine_arch_type == MACH_TYPE_PALMTREO700W) -#else -# define machine_is_palmtreo700w() (0) -#endif - -#ifdef CONFIG_MACH_PALMTREO750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTREO750 -# endif -# define machine_is_palmtreo750() (machine_arch_type == MACH_TYPE_PALMTREO750) -#else -# define machine_is_palmtreo750() (0) -#endif - -#ifdef CONFIG_MACH_PALMTREO755P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTREO755P -# endif -# define machine_is_palmtreo755p() (machine_arch_type == MACH_TYPE_PALMTREO755P) -#else -# define machine_is_palmtreo755p() (0) -#endif - -#ifdef CONFIG_MACH_EZREGANUT9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZREGANUT9200 -# endif -# define machine_is_ezreganut9200() (machine_arch_type == MACH_TYPE_EZREGANUT9200) -#else -# define machine_is_ezreganut9200() (0) -#endif - -#ifdef CONFIG_MACH_SARGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SARGE -# endif -# define machine_is_sarge() (machine_arch_type == MACH_TYPE_SARGE) -#else -# define machine_is_sarge() (0) -#endif - -#ifdef CONFIG_MACH_A696 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A696 -# endif -# define machine_is_a696() (machine_arch_type == MACH_TYPE_A696) -#else -# define machine_is_a696() (0) -#endif - -#ifdef CONFIG_MACH_TURTLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TURTLE -# endif -# define machine_is_turtle1916() (machine_arch_type == MACH_TYPE_TURTLE) -#else -# define machine_is_turtle1916() (0) -#endif - -#ifdef CONFIG_MACH_MX27_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX27_3DS -# endif -# define machine_is_mx27_3ds() (machine_arch_type == MACH_TYPE_MX27_3DS) -#else -# define machine_is_mx27_3ds() (0) -#endif - -#ifdef CONFIG_MACH_BISHOP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BISHOP -# endif -# define machine_is_bishop() (machine_arch_type == MACH_TYPE_BISHOP) -#else -# define machine_is_bishop() (0) -#endif - -#ifdef CONFIG_MACH_PXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXX -# endif -# define machine_is_pxx() (machine_arch_type == MACH_TYPE_PXX) -#else -# define machine_is_pxx() (0) -#endif - -#ifdef CONFIG_MACH_REDWOOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REDWOOD -# endif -# define machine_is_redwood() (machine_arch_type == MACH_TYPE_REDWOOD) -#else -# define machine_is_redwood() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_2430DLP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_2430DLP -# endif -# define machine_is_omap_2430dlp() (machine_arch_type == MACH_TYPE_OMAP_2430DLP) -#else -# define machine_is_omap_2430dlp() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_2430OSK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_2430OSK -# endif -# define machine_is_omap_2430osk() (machine_arch_type == MACH_TYPE_OMAP_2430OSK) -#else -# define machine_is_omap_2430osk() (0) -#endif - -#ifdef CONFIG_MACH_SARDINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SARDINE -# endif -# define machine_is_sardine() (machine_arch_type == MACH_TYPE_SARDINE) -#else -# define machine_is_sardine() (0) -#endif - -#ifdef CONFIG_MACH_HALIBUT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HALIBUT -# endif -# define machine_is_halibut() (machine_arch_type == MACH_TYPE_HALIBUT) -#else -# define machine_is_halibut() (0) -#endif - -#ifdef CONFIG_MACH_TROUT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TROUT -# endif -# define machine_is_trout() (machine_arch_type == MACH_TYPE_TROUT) -#else -# define machine_is_trout() (0) -#endif - -#ifdef CONFIG_MACH_GOLDFISH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GOLDFISH -# endif -# define machine_is_goldfish() (machine_arch_type == MACH_TYPE_GOLDFISH) -#else -# define machine_is_goldfish() (0) -#endif - -#ifdef CONFIG_MACH_GESBC2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GESBC2440 -# endif -# define machine_is_gesbc2440() (machine_arch_type == MACH_TYPE_GESBC2440) -#else -# define machine_is_gesbc2440() (0) -#endif - -#ifdef CONFIG_MACH_NOMAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOMAD -# endif -# define machine_is_nomad() (machine_arch_type == MACH_TYPE_NOMAD) -#else -# define machine_is_nomad() (0) -#endif - -#ifdef CONFIG_MACH_ROSALIND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROSALIND -# endif -# define machine_is_rosalind() (machine_arch_type == MACH_TYPE_ROSALIND) -#else -# define machine_is_rosalind() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9215 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9215 -# endif -# define machine_is_cc9p9215() (machine_arch_type == MACH_TYPE_CC9P9215) -#else -# define machine_is_cc9p9215() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9210 -# endif -# define machine_is_cc9p9210() (machine_arch_type == MACH_TYPE_CC9P9210) -#else -# define machine_is_cc9p9210() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9215JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9215JS -# endif -# define machine_is_cc9p9215js() (machine_arch_type == MACH_TYPE_CC9P9215JS) -#else -# define machine_is_cc9p9215js() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9210JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9210JS -# endif -# define machine_is_cc9p9210js() (machine_arch_type == MACH_TYPE_CC9P9210JS) -#else -# define machine_is_cc9p9210js() (0) -#endif - -#ifdef CONFIG_MACH_NASFFE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NASFFE -# endif -# define machine_is_nasffe() (machine_arch_type == MACH_TYPE_NASFFE) -#else -# define machine_is_nasffe() (0) -#endif - -#ifdef CONFIG_MACH_TN2X0BD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TN2X0BD -# endif -# define machine_is_tn2x0bd() (machine_arch_type == MACH_TYPE_TN2X0BD) -#else -# define machine_is_tn2x0bd() (0) -#endif - -#ifdef CONFIG_MACH_GWMPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GWMPXA -# endif -# define machine_is_gwmpxa() (machine_arch_type == MACH_TYPE_GWMPXA) -#else -# define machine_is_gwmpxa() (0) -#endif - -#ifdef CONFIG_MACH_EXYPLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXYPLUS -# endif -# define machine_is_exyplus() (machine_arch_type == MACH_TYPE_EXYPLUS) -#else -# define machine_is_exyplus() (0) -#endif - -#ifdef CONFIG_MACH_JADOO21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JADOO21 -# endif -# define machine_is_jadoo21() (machine_arch_type == MACH_TYPE_JADOO21) -#else -# define machine_is_jadoo21() (0) -#endif - -#ifdef CONFIG_MACH_LOOXN560 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOXN560 -# endif -# define machine_is_looxn560() (machine_arch_type == MACH_TYPE_LOOXN560) -#else -# define machine_is_looxn560() (0) -#endif - -#ifdef CONFIG_MACH_BONSAI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BONSAI -# endif -# define machine_is_bonsai() (machine_arch_type == MACH_TYPE_BONSAI) -#else -# define machine_is_bonsai() (0) -#endif - -#ifdef CONFIG_MACH_ADSMILGATO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSMILGATO -# endif -# define machine_is_adsmilgato() (machine_arch_type == MACH_TYPE_ADSMILGATO) -#else -# define machine_is_adsmilgato() (0) -#endif - -#ifdef CONFIG_MACH_GBA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GBA -# endif -# define machine_is_gba() (machine_arch_type == MACH_TYPE_GBA) -#else -# define machine_is_gba() (0) -#endif - -#ifdef CONFIG_MACH_H6044 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6044 -# endif -# define machine_is_h6044() (machine_arch_type == MACH_TYPE_H6044) -#else -# define machine_is_h6044() (0) -#endif - -#ifdef CONFIG_MACH_APP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APP -# endif -# define machine_is_app() (machine_arch_type == MACH_TYPE_APP) -#else -# define machine_is_app() (0) -#endif - -#ifdef CONFIG_MACH_TCT_HAMMER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TCT_HAMMER -# endif -# define machine_is_tct_hammer() (machine_arch_type == MACH_TYPE_TCT_HAMMER) -#else -# define machine_is_tct_hammer() (0) -#endif - -#ifdef CONFIG_MACH_HERMES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERMES -# endif -# define machine_is_herald() (machine_arch_type == MACH_TYPE_HERMES) -#else -# define machine_is_herald() (0) -#endif - -#ifdef CONFIG_MACH_ARTEMIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARTEMIS -# endif -# define machine_is_artemis() (machine_arch_type == MACH_TYPE_ARTEMIS) -#else -# define machine_is_artemis() (0) -#endif - -#ifdef CONFIG_MACH_HTCTITAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCTITAN -# endif -# define machine_is_htctitan() (machine_arch_type == MACH_TYPE_HTCTITAN) -#else -# define machine_is_htctitan() (0) -#endif - -#ifdef CONFIG_MACH_QRANIUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QRANIUM -# endif -# define machine_is_qranium() (machine_arch_type == MACH_TYPE_QRANIUM) -#else -# define machine_is_qranium() (0) -#endif - -#ifdef CONFIG_MACH_ADX_WSC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_WSC2 -# endif -# define machine_is_adx_wsc2() (machine_arch_type == MACH_TYPE_ADX_WSC2) -#else -# define machine_is_adx_wsc2() (0) -#endif - -#ifdef CONFIG_MACH_ADX_MEDCOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_MEDCOM -# endif -# define machine_is_adx_medcom() (machine_arch_type == MACH_TYPE_ADX_MEDCOM) -#else -# define machine_is_adx_medcom() (0) -#endif - -#ifdef CONFIG_MACH_BBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BBOARD -# endif -# define machine_is_bboard() (machine_arch_type == MACH_TYPE_BBOARD) -#else -# define machine_is_bboard() (0) -#endif - -#ifdef CONFIG_MACH_CAMBRIA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAMBRIA -# endif -# define machine_is_cambria() (machine_arch_type == MACH_TYPE_CAMBRIA) -#else -# define machine_is_cambria() (0) -#endif - -#ifdef CONFIG_MACH_MT7XXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MT7XXX -# endif -# define machine_is_mt7xxx() (machine_arch_type == MACH_TYPE_MT7XXX) -#else -# define machine_is_mt7xxx() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX512 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX512 -# endif -# define machine_is_matrix512() (machine_arch_type == MACH_TYPE_MATRIX512) -#else -# define machine_is_matrix512() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX522 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX522 -# endif -# define machine_is_matrix522() (machine_arch_type == MACH_TYPE_MATRIX522) -#else -# define machine_is_matrix522() (0) -#endif - -#ifdef CONFIG_MACH_IPAC5010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPAC5010 -# endif -# define machine_is_ipac5010() (machine_arch_type == MACH_TYPE_IPAC5010) -#else -# define machine_is_ipac5010() (0) -#endif - -#ifdef CONFIG_MACH_SAKURA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAKURA -# endif -# define machine_is_sakura() (machine_arch_type == MACH_TYPE_SAKURA) -#else -# define machine_is_sakura() (0) -#endif - -#ifdef CONFIG_MACH_GROCX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GROCX -# endif -# define machine_is_grocx() (machine_arch_type == MACH_TYPE_GROCX) -#else -# define machine_is_grocx() (0) -#endif - -#ifdef CONFIG_MACH_PM9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PM9263 -# endif -# define machine_is_pm9263() (machine_arch_type == MACH_TYPE_PM9263) -#else -# define machine_is_pm9263() (0) -#endif - -#ifdef CONFIG_MACH_SIM_ONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIM_ONE -# endif -# define machine_is_sim_one() (machine_arch_type == MACH_TYPE_SIM_ONE) -#else -# define machine_is_sim_one() (0) -#endif - -#ifdef CONFIG_MACH_ACQ132 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACQ132 -# endif -# define machine_is_acq132() (machine_arch_type == MACH_TYPE_ACQ132) -#else -# define machine_is_acq132() (0) -#endif - -#ifdef CONFIG_MACH_DATR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DATR -# endif -# define machine_is_datr() (machine_arch_type == MACH_TYPE_DATR) -#else -# define machine_is_datr() (0) -#endif - -#ifdef CONFIG_MACH_ACTUX1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTUX1 -# endif -# define machine_is_actux1() (machine_arch_type == MACH_TYPE_ACTUX1) -#else -# define machine_is_actux1() (0) -#endif - -#ifdef CONFIG_MACH_ACTUX2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTUX2 -# endif -# define machine_is_actux2() (machine_arch_type == MACH_TYPE_ACTUX2) -#else -# define machine_is_actux2() (0) -#endif - -#ifdef CONFIG_MACH_ACTUX3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTUX3 -# endif -# define machine_is_actux3() (machine_arch_type == MACH_TYPE_ACTUX3) -#else -# define machine_is_actux3() (0) -#endif - -#ifdef CONFIG_MACH_FLEXIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLEXIT -# endif -# define machine_is_flexit() (machine_arch_type == MACH_TYPE_FLEXIT) -#else -# define machine_is_flexit() (0) -#endif - -#ifdef CONFIG_MACH_BH2X0BD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BH2X0BD -# endif -# define machine_is_bh2x0bd() (machine_arch_type == MACH_TYPE_BH2X0BD) -#else -# define machine_is_bh2x0bd() (0) -#endif - -#ifdef CONFIG_MACH_ATB2002 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATB2002 -# endif -# define machine_is_atb2002() (machine_arch_type == MACH_TYPE_ATB2002) -#else -# define machine_is_atb2002() (0) -#endif - -#ifdef CONFIG_MACH_XENON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XENON -# endif -# define machine_is_xenon() (machine_arch_type == MACH_TYPE_XENON) -#else -# define machine_is_xenon() (0) -#endif - -#ifdef CONFIG_MACH_FM607 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FM607 -# endif -# define machine_is_fm607() (machine_arch_type == MACH_TYPE_FM607) -#else -# define machine_is_fm607() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX514 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX514 -# endif -# define machine_is_matrix514() (machine_arch_type == MACH_TYPE_MATRIX514) -#else -# define machine_is_matrix514() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX524 -# endif -# define machine_is_matrix524() (machine_arch_type == MACH_TYPE_MATRIX524) -#else -# define machine_is_matrix524() (0) -#endif - -#ifdef CONFIG_MACH_INPOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INPOD -# endif -# define machine_is_inpod() (machine_arch_type == MACH_TYPE_INPOD) -#else -# define machine_is_inpod() (0) -#endif - -#ifdef CONFIG_MACH_JIVE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JIVE -# endif -# define machine_is_jive() (machine_arch_type == MACH_TYPE_JIVE) -#else -# define machine_is_jive() (0) -#endif - -#ifdef CONFIG_MACH_TLL_MX21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TLL_MX21 -# endif -# define machine_is_tll_mx21() (machine_arch_type == MACH_TYPE_TLL_MX21) -#else -# define machine_is_tll_mx21() (0) -#endif - -#ifdef CONFIG_MACH_SBC2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC2800 -# endif -# define machine_is_sbc2800() (machine_arch_type == MACH_TYPE_SBC2800) -#else -# define machine_is_sbc2800() (0) -#endif - -#ifdef CONFIG_MACH_CC7UCAMRY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC7UCAMRY -# endif -# define machine_is_cc7ucamry() (machine_arch_type == MACH_TYPE_CC7UCAMRY) -#else -# define machine_is_cc7ucamry() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9_SC15 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9_SC15 -# endif -# define machine_is_ubisys_p9_sc15() (machine_arch_type == MACH_TYPE_UBISYS_P9_SC15) -#else -# define machine_is_ubisys_p9_sc15() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9_SSC2D10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9_SSC2D10 -# endif -# define machine_is_ubisys_p9_ssc2d10() (machine_arch_type == MACH_TYPE_UBISYS_P9_SSC2D10) -#else -# define machine_is_ubisys_p9_ssc2d10() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9_RCU3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9_RCU3 -# endif -# define machine_is_ubisys_p9_rcu3() (machine_arch_type == MACH_TYPE_UBISYS_P9_RCU3) -#else -# define machine_is_ubisys_p9_rcu3() (0) -#endif - -#ifdef CONFIG_MACH_AML_M8000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML_M8000 -# endif -# define machine_is_aml_m8000() (machine_arch_type == MACH_TYPE_AML_M8000) -#else -# define machine_is_aml_m8000() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPER_270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPER_270 -# endif -# define machine_is_snapper_270() (machine_arch_type == MACH_TYPE_SNAPPER_270) -#else -# define machine_is_snapper_270() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_BBX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_BBX -# endif -# define machine_is_omap_bbx() (machine_arch_type == MACH_TYPE_OMAP_BBX) -#else -# define machine_is_omap_bbx() (0) -#endif - -#ifdef CONFIG_MACH_UCN2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UCN2410 -# endif -# define machine_is_ucn2410() (machine_arch_type == MACH_TYPE_UCN2410) -#else -# define machine_is_ucn2410() (0) -#endif - -#ifdef CONFIG_MACH_SAM9_L9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM9_L9260 -# endif -# define machine_is_sam9_l9260() (machine_arch_type == MACH_TYPE_SAM9_L9260) -#else -# define machine_is_sam9_l9260() (0) -#endif - -#ifdef CONFIG_MACH_ETI_C2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETI_C2 -# endif -# define machine_is_eti_c2() (machine_arch_type == MACH_TYPE_ETI_C2) -#else -# define machine_is_eti_c2() (0) -#endif - -#ifdef CONFIG_MACH_AVALANCHE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVALANCHE -# endif -# define machine_is_avalanche() (machine_arch_type == MACH_TYPE_AVALANCHE) -#else -# define machine_is_avalanche() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PB1176 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PB1176 -# endif -# define machine_is_realview_pb1176() (machine_arch_type == MACH_TYPE_REALVIEW_PB1176) -#else -# define machine_is_realview_pb1176() (0) -#endif - -#ifdef CONFIG_MACH_DP1500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DP1500 -# endif -# define machine_is_dp1500() (machine_arch_type == MACH_TYPE_DP1500) -#else -# define machine_is_dp1500() (0) -#endif - -#ifdef CONFIG_MACH_APPLE_IPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APPLE_IPHONE -# endif -# define machine_is_apple_iphone() (machine_arch_type == MACH_TYPE_APPLE_IPHONE) -#else -# define machine_is_apple_iphone() (0) -#endif - -#ifdef CONFIG_MACH_YL9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YL9200 -# endif -# define machine_is_yl9200() (machine_arch_type == MACH_TYPE_YL9200) -#else -# define machine_is_yl9200() (0) -#endif - -#ifdef CONFIG_MACH_RD88F5182 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F5182 -# endif -# define machine_is_rd88f5182() (machine_arch_type == MACH_TYPE_RD88F5182) -#else -# define machine_is_rd88f5182() (0) -#endif - -#ifdef CONFIG_MACH_KUROBOX_PRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KUROBOX_PRO -# endif -# define machine_is_kurobox_pro() (machine_arch_type == MACH_TYPE_KUROBOX_PRO) -#else -# define machine_is_kurobox_pro() (0) -#endif - -#ifdef CONFIG_MACH_SE_POET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE_POET -# endif -# define machine_is_se_poet() (machine_arch_type == MACH_TYPE_SE_POET) -#else -# define machine_is_se_poet() (0) -#endif - -#ifdef CONFIG_MACH_MX31_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31_3DS -# endif -# define machine_is_mx31_3ds() (machine_arch_type == MACH_TYPE_MX31_3DS) -#else -# define machine_is_mx31_3ds() (0) -#endif - -#ifdef CONFIG_MACH_R270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_R270 -# endif -# define machine_is_r270() (machine_arch_type == MACH_TYPE_R270) -#else -# define machine_is_r270() (0) -#endif - -#ifdef CONFIG_MACH_ARMOUR21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMOUR21 -# endif -# define machine_is_armour21() (machine_arch_type == MACH_TYPE_ARMOUR21) -#else -# define machine_is_armour21() (0) -#endif - -#ifdef CONFIG_MACH_DT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DT2 -# endif -# define machine_is_dt2() (machine_arch_type == MACH_TYPE_DT2) -#else -# define machine_is_dt2() (0) -#endif - -#ifdef CONFIG_MACH_VT4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VT4 -# endif -# define machine_is_vt4() (machine_arch_type == MACH_TYPE_VT4) -#else -# define machine_is_vt4() (0) -#endif - -#ifdef CONFIG_MACH_TYCO320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TYCO320 -# endif -# define machine_is_tyco320() (machine_arch_type == MACH_TYPE_TYCO320) -#else -# define machine_is_tyco320() (0) -#endif - -#ifdef CONFIG_MACH_ADMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADMA -# endif -# define machine_is_adma() (machine_arch_type == MACH_TYPE_ADMA) -#else -# define machine_is_adma() (0) -#endif - -#ifdef CONFIG_MACH_WP188 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WP188 -# endif -# define machine_is_wp188() (machine_arch_type == MACH_TYPE_WP188) -#else -# define machine_is_wp188() (0) -#endif - -#ifdef CONFIG_MACH_CORSICA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORSICA -# endif -# define machine_is_corsica() (machine_arch_type == MACH_TYPE_CORSICA) -#else -# define machine_is_corsica() (0) -#endif - -#ifdef CONFIG_MACH_BIGEYE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIGEYE -# endif -# define machine_is_bigeye() (machine_arch_type == MACH_TYPE_BIGEYE) -#else -# define machine_is_bigeye() (0) -#endif - -#ifdef CONFIG_MACH_TLL5000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TLL5000 -# endif -# define machine_is_tll5000() (machine_arch_type == MACH_TYPE_TLL5000) -#else -# define machine_is_tll5000() (0) -#endif - -#ifdef CONFIG_MACH_BEBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BEBOT -# endif -# define machine_is_bebot() (machine_arch_type == MACH_TYPE_BEBOT) -#else -# define machine_is_bebot() (0) -#endif - -#ifdef CONFIG_MACH_QONG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QONG -# endif -# define machine_is_qong() (machine_arch_type == MACH_TYPE_QONG) -#else -# define machine_is_qong() (0) -#endif - -#ifdef CONFIG_MACH_TCOMPACT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TCOMPACT -# endif -# define machine_is_tcompact() (machine_arch_type == MACH_TYPE_TCOMPACT) -#else -# define machine_is_tcompact() (0) -#endif - -#ifdef CONFIG_MACH_PUMA5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PUMA5 -# endif -# define machine_is_puma5() (machine_arch_type == MACH_TYPE_PUMA5) -#else -# define machine_is_puma5() (0) -#endif - -#ifdef CONFIG_MACH_ELARA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELARA -# endif -# define machine_is_elara() (machine_arch_type == MACH_TYPE_ELARA) -#else -# define machine_is_elara() (0) -#endif - -#ifdef CONFIG_MACH_ELLINGTON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELLINGTON -# endif -# define machine_is_ellington() (machine_arch_type == MACH_TYPE_ELLINGTON) -#else -# define machine_is_ellington() (0) -#endif - -#ifdef CONFIG_MACH_XDA_ATOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XDA_ATOM -# endif -# define machine_is_xda_atom() (machine_arch_type == MACH_TYPE_XDA_ATOM) -#else -# define machine_is_xda_atom() (0) -#endif - -#ifdef CONFIG_MACH_ENERGIZER2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENERGIZER2 -# endif -# define machine_is_energizer2() (machine_arch_type == MACH_TYPE_ENERGIZER2) -#else -# define machine_is_energizer2() (0) -#endif - -#ifdef CONFIG_MACH_ODIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ODIN -# endif -# define machine_is_odin() (machine_arch_type == MACH_TYPE_ODIN) -#else -# define machine_is_odin() (0) -#endif - -#ifdef CONFIG_MACH_ACTUX4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTUX4 -# endif -# define machine_is_actux4() (machine_arch_type == MACH_TYPE_ACTUX4) -#else -# define machine_is_actux4() (0) -#endif - -#ifdef CONFIG_MACH_ESL_OMAP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_OMAP -# endif -# define machine_is_esl_omap() (machine_arch_type == MACH_TYPE_ESL_OMAP) -#else -# define machine_is_esl_omap() (0) -#endif - -#ifdef CONFIG_MACH_OMAP2EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP2EVM -# endif -# define machine_is_omap2evm() (machine_arch_type == MACH_TYPE_OMAP2EVM) -#else -# define machine_is_omap2evm() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3EVM -# endif -# define machine_is_omap3evm() (machine_arch_type == MACH_TYPE_OMAP3EVM) -#else -# define machine_is_omap3evm() (0) -#endif - -#ifdef CONFIG_MACH_ADX_PCU57 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_PCU57 -# endif -# define machine_is_adx_pcu57() (machine_arch_type == MACH_TYPE_ADX_PCU57) -#else -# define machine_is_adx_pcu57() (0) -#endif - -#ifdef CONFIG_MACH_MONACO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MONACO -# endif -# define machine_is_monaco() (machine_arch_type == MACH_TYPE_MONACO) -#else -# define machine_is_monaco() (0) -#endif - -#ifdef CONFIG_MACH_LEVANTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEVANTE -# endif -# define machine_is_levante() (machine_arch_type == MACH_TYPE_LEVANTE) -#else -# define machine_is_levante() (0) -#endif - -#ifdef CONFIG_MACH_TMXIPX425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TMXIPX425 -# endif -# define machine_is_tmxipx425() (machine_arch_type == MACH_TYPE_TMXIPX425) -#else -# define machine_is_tmxipx425() (0) -#endif - -#ifdef CONFIG_MACH_LEEP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEEP -# endif -# define machine_is_leep() (machine_arch_type == MACH_TYPE_LEEP) -#else -# define machine_is_leep() (0) -#endif - -#ifdef CONFIG_MACH_RAAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAAD -# endif -# define machine_is_raad() (machine_arch_type == MACH_TYPE_RAAD) -#else -# define machine_is_raad() (0) -#endif - -#ifdef CONFIG_MACH_DNS323 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DNS323 -# endif -# define machine_is_dns323() (machine_arch_type == MACH_TYPE_DNS323) -#else -# define machine_is_dns323() (0) -#endif - -#ifdef CONFIG_MACH_AP1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AP1000 -# endif -# define machine_is_ap1000() (machine_arch_type == MACH_TYPE_AP1000) -#else -# define machine_is_ap1000() (0) -#endif - -#ifdef CONFIG_MACH_A9SAM6432 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9SAM6432 -# endif -# define machine_is_a9sam6432() (machine_arch_type == MACH_TYPE_A9SAM6432) -#else -# define machine_is_a9sam6432() (0) -#endif - -#ifdef CONFIG_MACH_SHINY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHINY -# endif -# define machine_is_shiny() (machine_arch_type == MACH_TYPE_SHINY) -#else -# define machine_is_shiny() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_BEAGLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_BEAGLE -# endif -# define machine_is_omap3_beagle() (machine_arch_type == MACH_TYPE_OMAP3_BEAGLE) -#else -# define machine_is_omap3_beagle() (0) -#endif - -#ifdef CONFIG_MACH_CSR_BDB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSR_BDB2 -# endif -# define machine_is_csr_bdb2() (machine_arch_type == MACH_TYPE_CSR_BDB2) -#else -# define machine_is_csr_bdb2() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_N810 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_N810 -# endif -# define machine_is_nokia_n810() (machine_arch_type == MACH_TYPE_NOKIA_N810) -#else -# define machine_is_nokia_n810() (0) -#endif - -#ifdef CONFIG_MACH_C270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_C270 -# endif -# define machine_is_c270() (machine_arch_type == MACH_TYPE_C270) -#else -# define machine_is_c270() (0) -#endif - -#ifdef CONFIG_MACH_SENTRY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SENTRY -# endif -# define machine_is_sentry() (machine_arch_type == MACH_TYPE_SENTRY) -#else -# define machine_is_sentry() (0) -#endif - -#ifdef CONFIG_MACH_PCM038 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM038 -# endif -# define machine_is_pcm038() (machine_arch_type == MACH_TYPE_PCM038) -#else -# define machine_is_pcm038() (0) -#endif - -#ifdef CONFIG_MACH_ANC300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANC300 -# endif -# define machine_is_anc300() (machine_arch_type == MACH_TYPE_ANC300) -#else -# define machine_is_anc300() (0) -#endif - -#ifdef CONFIG_MACH_HTCKAISER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCKAISER -# endif -# define machine_is_htckaiser() (machine_arch_type == MACH_TYPE_HTCKAISER) -#else -# define machine_is_htckaiser() (0) -#endif - -#ifdef CONFIG_MACH_SBAT100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBAT100 -# endif -# define machine_is_sbat100() (machine_arch_type == MACH_TYPE_SBAT100) -#else -# define machine_is_sbat100() (0) -#endif - -#ifdef CONFIG_MACH_MODUNORM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MODUNORM -# endif -# define machine_is_modunorm() (machine_arch_type == MACH_TYPE_MODUNORM) -#else -# define machine_is_modunorm() (0) -#endif - -#ifdef CONFIG_MACH_PELOS_TWARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELOS_TWARM -# endif -# define machine_is_pelos_twarm() (machine_arch_type == MACH_TYPE_PELOS_TWARM) -#else -# define machine_is_pelos_twarm() (0) -#endif - -#ifdef CONFIG_MACH_FLANK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLANK -# endif -# define machine_is_flank() (machine_arch_type == MACH_TYPE_FLANK) -#else -# define machine_is_flank() (0) -#endif - -#ifdef CONFIG_MACH_SIRLOIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIRLOIN -# endif -# define machine_is_sirloin() (machine_arch_type == MACH_TYPE_SIRLOIN) -#else -# define machine_is_sirloin() (0) -#endif - -#ifdef CONFIG_MACH_BRISKET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRISKET -# endif -# define machine_is_brisket() (machine_arch_type == MACH_TYPE_BRISKET) -#else -# define machine_is_brisket() (0) -#endif - -#ifdef CONFIG_MACH_CHUCK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHUCK -# endif -# define machine_is_chuck() (machine_arch_type == MACH_TYPE_CHUCK) -#else -# define machine_is_chuck() (0) -#endif - -#ifdef CONFIG_MACH_OTTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OTTER -# endif -# define machine_is_otter() (machine_arch_type == MACH_TYPE_OTTER) -#else -# define machine_is_otter() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_LDK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_LDK -# endif -# define machine_is_davinci_ldk() (machine_arch_type == MACH_TYPE_DAVINCI_LDK) -#else -# define machine_is_davinci_ldk() (0) -#endif - -#ifdef CONFIG_MACH_PHREEDOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHREEDOM -# endif -# define machine_is_phreedom() (machine_arch_type == MACH_TYPE_PHREEDOM) -#else -# define machine_is_phreedom() (0) -#endif - -#ifdef CONFIG_MACH_SG310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG310 -# endif -# define machine_is_sg310() (machine_arch_type == MACH_TYPE_SG310) -#else -# define machine_is_sg310() (0) -#endif - -#ifdef CONFIG_MACH_TS209 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS209 -# endif -# define machine_is_ts_x09() (machine_arch_type == MACH_TYPE_TS209) -#else -# define machine_is_ts_x09() (0) -#endif - -#ifdef CONFIG_MACH_AT91CAP9ADK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91CAP9ADK -# endif -# define machine_is_at91cap9adk() (machine_arch_type == MACH_TYPE_AT91CAP9ADK) -#else -# define machine_is_at91cap9adk() (0) -#endif - -#ifdef CONFIG_MACH_TION9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TION9315 -# endif -# define machine_is_tion9315() (machine_arch_type == MACH_TYPE_TION9315) -#else -# define machine_is_tion9315() (0) -#endif - -#ifdef CONFIG_MACH_MAST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAST -# endif -# define machine_is_mast() (machine_arch_type == MACH_TYPE_MAST) -#else -# define machine_is_mast() (0) -#endif - -#ifdef CONFIG_MACH_PFW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PFW -# endif -# define machine_is_pfw() (machine_arch_type == MACH_TYPE_PFW) -#else -# define machine_is_pfw() (0) -#endif - -#ifdef CONFIG_MACH_YL_P2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YL_P2440 -# endif -# define machine_is_yl_p2440() (machine_arch_type == MACH_TYPE_YL_P2440) -#else -# define machine_is_yl_p2440() (0) -#endif - -#ifdef CONFIG_MACH_ZSBC32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZSBC32 -# endif -# define machine_is_zsbc32() (machine_arch_type == MACH_TYPE_ZSBC32) -#else -# define machine_is_zsbc32() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PACE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PACE2 -# endif -# define machine_is_omap_pace2() (machine_arch_type == MACH_TYPE_OMAP_PACE2) -#else -# define machine_is_omap_pace2() (0) -#endif - -#ifdef CONFIG_MACH_IMX_PACE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX_PACE2 -# endif -# define machine_is_imx_pace2() (machine_arch_type == MACH_TYPE_IMX_PACE2) -#else -# define machine_is_imx_pace2() (0) -#endif - -#ifdef CONFIG_MACH_MX31MOBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31MOBOARD -# endif -# define machine_is_mx31moboard() (machine_arch_type == MACH_TYPE_MX31MOBOARD) -#else -# define machine_is_mx31moboard() (0) -#endif - -#ifdef CONFIG_MACH_MX37_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX37_3DS -# endif -# define machine_is_mx37_3ds() (machine_arch_type == MACH_TYPE_MX37_3DS) -#else -# define machine_is_mx37_3ds() (0) -#endif - -#ifdef CONFIG_MACH_RCC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RCC -# endif -# define machine_is_rcc() (machine_arch_type == MACH_TYPE_RCC) -#else -# define machine_is_rcc() (0) -#endif - -#ifdef CONFIG_MACH_ARM9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM9 -# endif -# define machine_is_dmp() (machine_arch_type == MACH_TYPE_ARM9) -#else -# define machine_is_dmp() (0) -#endif - -#ifdef CONFIG_MACH_VISION_EP9307 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VISION_EP9307 -# endif -# define machine_is_vision_ep9307() (machine_arch_type == MACH_TYPE_VISION_EP9307) -#else -# define machine_is_vision_ep9307() (0) -#endif - -#ifdef CONFIG_MACH_SCLY1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCLY1000 -# endif -# define machine_is_scly1000() (machine_arch_type == MACH_TYPE_SCLY1000) -#else -# define machine_is_scly1000() (0) -#endif - -#ifdef CONFIG_MACH_FONTEL_EP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FONTEL_EP -# endif -# define machine_is_fontel_ep() (machine_arch_type == MACH_TYPE_FONTEL_EP) -#else -# define machine_is_fontel_ep() (0) -#endif - -#ifdef CONFIG_MACH_VOICEBLUE3G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VOICEBLUE3G -# endif -# define machine_is_voiceblue3g() (machine_arch_type == MACH_TYPE_VOICEBLUE3G) -#else -# define machine_is_voiceblue3g() (0) -#endif - -#ifdef CONFIG_MACH_TT9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TT9200 -# endif -# define machine_is_tt9200() (machine_arch_type == MACH_TYPE_TT9200) -#else -# define machine_is_tt9200() (0) -#endif - -#ifdef CONFIG_MACH_DIGI2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIGI2410 -# endif -# define machine_is_digi2410() (machine_arch_type == MACH_TYPE_DIGI2410) -#else -# define machine_is_digi2410() (0) -#endif - -#ifdef CONFIG_MACH_TERASTATION_PRO2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TERASTATION_PRO2 -# endif -# define machine_is_terastation_pro2() (machine_arch_type == MACH_TYPE_TERASTATION_PRO2) -#else -# define machine_is_terastation_pro2() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_PRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_PRO -# endif -# define machine_is_linkstation_pro() (machine_arch_type == MACH_TYPE_LINKSTATION_PRO) -#else -# define machine_is_linkstation_pro() (0) -#endif - -#ifdef CONFIG_MACH_MOTOROLA_A780 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOROLA_A780 -# endif -# define machine_is_motorola_a780() (machine_arch_type == MACH_TYPE_MOTOROLA_A780) -#else -# define machine_is_motorola_a780() (0) -#endif - -#ifdef CONFIG_MACH_MOTOROLA_E6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOROLA_E6 -# endif -# define machine_is_motorola_e6() (machine_arch_type == MACH_TYPE_MOTOROLA_E6) -#else -# define machine_is_motorola_e6() (0) -#endif - -#ifdef CONFIG_MACH_MOTOROLA_E2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOROLA_E2 -# endif -# define machine_is_motorola_e2() (machine_arch_type == MACH_TYPE_MOTOROLA_E2) -#else -# define machine_is_motorola_e2() (0) -#endif - -#ifdef CONFIG_MACH_MOTOROLA_E680 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOROLA_E680 -# endif -# define machine_is_motorola_e680() (machine_arch_type == MACH_TYPE_MOTOROLA_E680) -#else -# define machine_is_motorola_e680() (0) -#endif - -#ifdef CONFIG_MACH_UR2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UR2410 -# endif -# define machine_is_ur2410() (machine_arch_type == MACH_TYPE_UR2410) -#else -# define machine_is_ur2410() (0) -#endif - -#ifdef CONFIG_MACH_TAS9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAS9261 -# endif -# define machine_is_tas9261() (machine_arch_type == MACH_TYPE_TAS9261) -#else -# define machine_is_tas9261() (0) -#endif - -#ifdef CONFIG_MACH_HERMES_HD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERMES_HD -# endif -# define machine_is_davinci_hermes_hd() (machine_arch_type == MACH_TYPE_HERMES_HD) -#else -# define machine_is_davinci_hermes_hd() (0) -#endif - -#ifdef CONFIG_MACH_PERSEO_HD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PERSEO_HD -# endif -# define machine_is_davinci_perseo_hd() (machine_arch_type == MACH_TYPE_PERSEO_HD) -#else -# define machine_is_davinci_perseo_hd() (0) -#endif - -#ifdef CONFIG_MACH_STARGAZER2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STARGAZER2 -# endif -# define machine_is_stargazer2() (machine_arch_type == MACH_TYPE_STARGAZER2) -#else -# define machine_is_stargazer2() (0) -#endif - -#ifdef CONFIG_MACH_E350 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E350 -# endif -# define machine_is_e350() (machine_arch_type == MACH_TYPE_E350) -#else -# define machine_is_e350() (0) -#endif - -#ifdef CONFIG_MACH_WPCM450 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WPCM450 -# endif -# define machine_is_wpcm450() (machine_arch_type == MACH_TYPE_WPCM450) -#else -# define machine_is_wpcm450() (0) -#endif - -#ifdef CONFIG_MACH_CARTESIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARTESIO -# endif -# define machine_is_cartesio() (machine_arch_type == MACH_TYPE_CARTESIO) -#else -# define machine_is_cartesio() (0) -#endif - -#ifdef CONFIG_MACH_TOYBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOYBOX -# endif -# define machine_is_toybox() (machine_arch_type == MACH_TYPE_TOYBOX) -#else -# define machine_is_toybox() (0) -#endif - -#ifdef CONFIG_MACH_TX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TX27 -# endif -# define machine_is_tx27() (machine_arch_type == MACH_TYPE_TX27) -#else -# define machine_is_tx27() (0) -#endif - -#ifdef CONFIG_MACH_TS409 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS409 -# endif -# define machine_is_ts409() (machine_arch_type == MACH_TYPE_TS409) -#else -# define machine_is_ts409() (0) -#endif - -#ifdef CONFIG_MACH_P300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P300 -# endif -# define machine_is_p300() (machine_arch_type == MACH_TYPE_P300) -#else -# define machine_is_p300() (0) -#endif - -#ifdef CONFIG_MACH_XDACOMET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XDACOMET -# endif -# define machine_is_xdacomet() (machine_arch_type == MACH_TYPE_XDACOMET) -#else -# define machine_is_xdacomet() (0) -#endif - -#ifdef CONFIG_MACH_DEXFLEX2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEXFLEX2 -# endif -# define machine_is_dexflex2() (machine_arch_type == MACH_TYPE_DEXFLEX2) -#else -# define machine_is_dexflex2() (0) -#endif - -#ifdef CONFIG_MACH_OW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OW -# endif -# define machine_is_ow() (machine_arch_type == MACH_TYPE_OW) -#else -# define machine_is_ow() (0) -#endif - -#ifdef CONFIG_MACH_ARMEBS3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMEBS3 -# endif -# define machine_is_armebs3() (machine_arch_type == MACH_TYPE_ARMEBS3) -#else -# define machine_is_armebs3() (0) -#endif - -#ifdef CONFIG_MACH_U3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U3 -# endif -# define machine_is_u3() (machine_arch_type == MACH_TYPE_U3) -#else -# define machine_is_u3() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2450 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2450 -# endif -# define machine_is_smdk2450() (machine_arch_type == MACH_TYPE_SMDK2450) -#else -# define machine_is_smdk2450() (0) -#endif - -#ifdef CONFIG_MACH_RSI_EWS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RSI_EWS -# endif -# define machine_is_rsi_ews() (machine_arch_type == MACH_TYPE_RSI_EWS) -#else -# define machine_is_rsi_ews() (0) -#endif - -#ifdef CONFIG_MACH_TNB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNB -# endif -# define machine_is_tnb() (machine_arch_type == MACH_TYPE_TNB) -#else -# define machine_is_tnb() (0) -#endif - -#ifdef CONFIG_MACH_TOEPATH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOEPATH -# endif -# define machine_is_toepath() (machine_arch_type == MACH_TYPE_TOEPATH) -#else -# define machine_is_toepath() (0) -#endif - -#ifdef CONFIG_MACH_KB9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KB9263 -# endif -# define machine_is_kb9263() (machine_arch_type == MACH_TYPE_KB9263) -#else -# define machine_is_kb9263() (0) -#endif - -#ifdef CONFIG_MACH_MT7108 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MT7108 -# endif -# define machine_is_mt7108() (machine_arch_type == MACH_TYPE_MT7108) -#else -# define machine_is_mt7108() (0) -#endif - -#ifdef CONFIG_MACH_SMTR2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMTR2440 -# endif -# define machine_is_smtr2440() (machine_arch_type == MACH_TYPE_SMTR2440) -#else -# define machine_is_smtr2440() (0) -#endif - -#ifdef CONFIG_MACH_MANAO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MANAO -# endif -# define machine_is_manao() (machine_arch_type == MACH_TYPE_MANAO) -#else -# define machine_is_manao() (0) -#endif - -#ifdef CONFIG_MACH_CM_X300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_X300 -# endif -# define machine_is_cm_x300() (machine_arch_type == MACH_TYPE_CM_X300) -#else -# define machine_is_cm_x300() (0) -#endif - -#ifdef CONFIG_MACH_GULFSTREAM_KP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GULFSTREAM_KP -# endif -# define machine_is_gulfstream_kp() (machine_arch_type == MACH_TYPE_GULFSTREAM_KP) -#else -# define machine_is_gulfstream_kp() (0) -#endif - -#ifdef CONFIG_MACH_LANREADYFN522 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LANREADYFN522 -# endif -# define machine_is_lanreadyfn522() (machine_arch_type == MACH_TYPE_LANREADYFN522) -#else -# define machine_is_lanreadyfn522() (0) -#endif - -#ifdef CONFIG_MACH_ARMA37 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMA37 -# endif -# define machine_is_arma37() (machine_arch_type == MACH_TYPE_ARMA37) -#else -# define machine_is_arma37() (0) -#endif - -#ifdef CONFIG_MACH_MENDEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MENDEL -# endif -# define machine_is_mendel() (machine_arch_type == MACH_TYPE_MENDEL) -#else -# define machine_is_mendel() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_ILIAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_ILIAD -# endif -# define machine_is_pelco_iliad() (machine_arch_type == MACH_TYPE_PELCO_ILIAD) -#else -# define machine_is_pelco_iliad() (0) -#endif - -#ifdef CONFIG_MACH_UNIT2P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNIT2P -# endif -# define machine_is_unit2p() (machine_arch_type == MACH_TYPE_UNIT2P) -#else -# define machine_is_unit2p() (0) -#endif - -#ifdef CONFIG_MACH_INC20OTTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INC20OTTER -# endif -# define machine_is_inc20otter() (machine_arch_type == MACH_TYPE_INC20OTTER) -#else -# define machine_is_inc20otter() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G20EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G20EK -# endif -# define machine_is_at91sam9g20ek() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK) -#else -# define machine_is_at91sam9g20ek() (0) -#endif - -#ifdef CONFIG_MACH_STORCENTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STORCENTER -# endif -# define machine_is_sc_ge2() (machine_arch_type == MACH_TYPE_STORCENTER) -#else -# define machine_is_sc_ge2() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6410 -# endif -# define machine_is_smdk6410() (machine_arch_type == MACH_TYPE_SMDK6410) -#else -# define machine_is_smdk6410() (0) -#endif - -#ifdef CONFIG_MACH_U300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U300 -# endif -# define machine_is_u300() (machine_arch_type == MACH_TYPE_U300) -#else -# define machine_is_u300() (0) -#endif - -#ifdef CONFIG_MACH_U500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U500 -# endif -# define machine_is_u500() (machine_arch_type == MACH_TYPE_U500) -#else -# define machine_is_u500() (0) -#endif - -#ifdef CONFIG_MACH_DS9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS9260 -# endif -# define machine_is_ds9260() (machine_arch_type == MACH_TYPE_DS9260) -#else -# define machine_is_ds9260() (0) -#endif - -#ifdef CONFIG_MACH_RIVERROCK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIVERROCK -# endif -# define machine_is_riverrock() (machine_arch_type == MACH_TYPE_RIVERROCK) -#else -# define machine_is_riverrock() (0) -#endif - -#ifdef CONFIG_MACH_SCIBATH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCIBATH -# endif -# define machine_is_scibath() (machine_arch_type == MACH_TYPE_SCIBATH) -#else -# define machine_is_scibath() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM7SE512EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM7SE512EK -# endif -# define machine_is_at91sam7se() (machine_arch_type == MACH_TYPE_AT91SAM7SE512EK) -#else -# define machine_is_at91sam7se() (0) -#endif - -#ifdef CONFIG_MACH_WRT350N_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WRT350N_V2 -# endif -# define machine_is_wrt350n_v2() (machine_arch_type == MACH_TYPE_WRT350N_V2) -#else -# define machine_is_wrt350n_v2() (0) -#endif - -#ifdef CONFIG_MACH_MULTIMEDIA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTIMEDIA -# endif -# define machine_is_multimedia() (machine_arch_type == MACH_TYPE_MULTIMEDIA) -#else -# define machine_is_multimedia() (0) -#endif - -#ifdef CONFIG_MACH_MARVIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARVIN -# endif -# define machine_is_marvin() (machine_arch_type == MACH_TYPE_MARVIN) -#else -# define machine_is_marvin() (0) -#endif - -#ifdef CONFIG_MACH_X500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_X500 -# endif -# define machine_is_x500() (machine_arch_type == MACH_TYPE_X500) -#else -# define machine_is_x500() (0) -#endif - -#ifdef CONFIG_MACH_AWLUG4LCU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AWLUG4LCU -# endif -# define machine_is_awlug4lcu() (machine_arch_type == MACH_TYPE_AWLUG4LCU) -#else -# define machine_is_awlug4lcu() (0) -#endif - -#ifdef CONFIG_MACH_PALERMOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALERMOC -# endif -# define machine_is_palermoc() (machine_arch_type == MACH_TYPE_PALERMOC) -#else -# define machine_is_palermoc() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_LDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_LDP -# endif -# define machine_is_omap_ldp() (machine_arch_type == MACH_TYPE_OMAP_LDP) -#else -# define machine_is_omap_ldp() (0) -#endif - -#ifdef CONFIG_MACH_IP500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IP500 -# endif -# define machine_is_ip500() (machine_arch_type == MACH_TYPE_IP500) -#else -# define machine_is_ip500() (0) -#endif - -#ifdef CONFIG_MACH_ASE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASE2 -# endif -# define machine_is_ase2() (machine_arch_type == MACH_TYPE_ASE2) -#else -# define machine_is_ase2() (0) -#endif - -#ifdef CONFIG_MACH_MX35EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX35EVB -# endif -# define machine_is_mx35evb() (machine_arch_type == MACH_TYPE_MX35EVB) -#else -# define machine_is_mx35evb() (0) -#endif - -#ifdef CONFIG_MACH_AML_M8050 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML_M8050 -# endif -# define machine_is_aml_m8050() (machine_arch_type == MACH_TYPE_AML_M8050) -#else -# define machine_is_aml_m8050() (0) -#endif - -#ifdef CONFIG_MACH_MX35_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX35_3DS -# endif -# define machine_is_mx35_3ds() (machine_arch_type == MACH_TYPE_MX35_3DS) -#else -# define machine_is_mx35_3ds() (0) -#endif - -#ifdef CONFIG_MACH_MARS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARS -# endif -# define machine_is_mars() (machine_arch_type == MACH_TYPE_MARS) -#else -# define machine_is_mars() (0) -#endif - -#ifdef CONFIG_MACH_NTOSD_644XA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NTOSD_644XA -# endif -# define machine_is_ntosd_644xa() (machine_arch_type == MACH_TYPE_NTOSD_644XA) -#else -# define machine_is_ntosd_644xa() (0) -#endif - -#ifdef CONFIG_MACH_BADGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BADGER -# endif -# define machine_is_badger() (machine_arch_type == MACH_TYPE_BADGER) -#else -# define machine_is_badger() (0) -#endif - -#ifdef CONFIG_MACH_TRIZEPS4WL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS4WL -# endif -# define machine_is_trizeps4wl() (machine_arch_type == MACH_TYPE_TRIZEPS4WL) -#else -# define machine_is_trizeps4wl() (0) -#endif - -#ifdef CONFIG_MACH_TRIZEPS5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS5 -# endif -# define machine_is_trizeps5() (machine_arch_type == MACH_TYPE_TRIZEPS5) -#else -# define machine_is_trizeps5() (0) -#endif - -#ifdef CONFIG_MACH_MARLIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARLIN -# endif -# define machine_is_marlin() (machine_arch_type == MACH_TYPE_MARLIN) -#else -# define machine_is_marlin() (0) -#endif - -#ifdef CONFIG_MACH_TS78XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS78XX -# endif -# define machine_is_ts78xx() (machine_arch_type == MACH_TYPE_TS78XX) -#else -# define machine_is_ts78xx() (0) -#endif - -#ifdef CONFIG_MACH_HPIPAQ214 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HPIPAQ214 -# endif -# define machine_is_hpipaq214() (machine_arch_type == MACH_TYPE_HPIPAQ214) -#else -# define machine_is_hpipaq214() (0) -#endif - -#ifdef CONFIG_MACH_AT572D940DCM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT572D940DCM -# endif -# define machine_is_at572d940dcm() (machine_arch_type == MACH_TYPE_AT572D940DCM) -#else -# define machine_is_at572d940dcm() (0) -#endif - -#ifdef CONFIG_MACH_NE1BOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NE1BOARD -# endif -# define machine_is_ne1board() (machine_arch_type == MACH_TYPE_NE1BOARD) -#else -# define machine_is_ne1board() (0) -#endif - -#ifdef CONFIG_MACH_ZANTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZANTE -# endif -# define machine_is_zante() (machine_arch_type == MACH_TYPE_ZANTE) -#else -# define machine_is_zante() (0) -#endif - -#ifdef CONFIG_MACH_SFFSDR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SFFSDR -# endif -# define machine_is_sffsdr() (machine_arch_type == MACH_TYPE_SFFSDR) -#else -# define machine_is_sffsdr() (0) -#endif - -#ifdef CONFIG_MACH_TW2662 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TW2662 -# endif -# define machine_is_tw2662() (machine_arch_type == MACH_TYPE_TW2662) -#else -# define machine_is_tw2662() (0) -#endif - -#ifdef CONFIG_MACH_VF10XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VF10XX -# endif -# define machine_is_vf10xx() (machine_arch_type == MACH_TYPE_VF10XX) -#else -# define machine_is_vf10xx() (0) -#endif - -#ifdef CONFIG_MACH_ZORAN43XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZORAN43XX -# endif -# define machine_is_zoran43xx() (machine_arch_type == MACH_TYPE_ZORAN43XX) -#else -# define machine_is_zoran43xx() (0) -#endif - -#ifdef CONFIG_MACH_SONIX926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SONIX926 -# endif -# define machine_is_sonix926() (machine_arch_type == MACH_TYPE_SONIX926) -#else -# define machine_is_sonix926() (0) -#endif - -#ifdef CONFIG_MACH_CELESTIALSEMI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CELESTIALSEMI -# endif -# define machine_is_celestialsemi() (machine_arch_type == MACH_TYPE_CELESTIALSEMI) -#else -# define machine_is_celestialsemi() (0) -#endif - -#ifdef CONFIG_MACH_CC9M2443 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9M2443 -# endif -# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443) -#else -# define machine_is_cc9m2443() (0) -#endif - -#ifdef CONFIG_MACH_TW5334 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TW5334 -# endif -# define machine_is_tw5334() (machine_arch_type == MACH_TYPE_TW5334) -#else -# define machine_is_tw5334() (0) -#endif - -#ifdef CONFIG_MACH_HTCARTEMIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCARTEMIS -# endif -# define machine_is_omap_htcartemis() (machine_arch_type == MACH_TYPE_HTCARTEMIS) -#else -# define machine_is_omap_htcartemis() (0) -#endif - -#ifdef CONFIG_MACH_NAL_HLITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAL_HLITE -# endif -# define machine_is_nal_hlite() (machine_arch_type == MACH_TYPE_NAL_HLITE) -#else -# define machine_is_nal_hlite() (0) -#endif - -#ifdef CONFIG_MACH_HTCVOGUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCVOGUE -# endif -# define machine_is_htcvogue() (machine_arch_type == MACH_TYPE_HTCVOGUE) -#else -# define machine_is_htcvogue() (0) -#endif - -#ifdef CONFIG_MACH_SMARTWEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTWEB -# endif -# define machine_is_smartweb() (machine_arch_type == MACH_TYPE_SMARTWEB) -#else -# define machine_is_smartweb() (0) -#endif - -#ifdef CONFIG_MACH_MV86XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV86XX -# endif -# define machine_is_mv86xx() (machine_arch_type == MACH_TYPE_MV86XX) -#else -# define machine_is_mv86xx() (0) -#endif - -#ifdef CONFIG_MACH_MV87XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV87XX -# endif -# define machine_is_mv87xx() (machine_arch_type == MACH_TYPE_MV87XX) -#else -# define machine_is_mv87xx() (0) -#endif - -#ifdef CONFIG_MACH_SONGYOUNGHO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SONGYOUNGHO -# endif -# define machine_is_songyoungho() (machine_arch_type == MACH_TYPE_SONGYOUNGHO) -#else -# define machine_is_songyoungho() (0) -#endif - -#ifdef CONFIG_MACH_YOUNGHOTEMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YOUNGHOTEMA -# endif -# define machine_is_younghotema() (machine_arch_type == MACH_TYPE_YOUNGHOTEMA) -#else -# define machine_is_younghotema() (0) -#endif - -#ifdef CONFIG_MACH_PCM037 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM037 -# endif -# define machine_is_pcm037() (machine_arch_type == MACH_TYPE_PCM037) -#else -# define machine_is_pcm037() (0) -#endif - -#ifdef CONFIG_MACH_MMVP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMVP -# endif -# define machine_is_mmvp() (machine_arch_type == MACH_TYPE_MMVP) -#else -# define machine_is_mmvp() (0) -#endif - -#ifdef CONFIG_MACH_MMAP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMAP -# endif -# define machine_is_mmap() (machine_arch_type == MACH_TYPE_MMAP) -#else -# define machine_is_mmap() (0) -#endif - -#ifdef CONFIG_MACH_PTID2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PTID2410 -# endif -# define machine_is_ptid2410() (machine_arch_type == MACH_TYPE_PTID2410) -#else -# define machine_is_ptid2410() (0) -#endif - -#ifdef CONFIG_MACH_JAMES_926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JAMES_926 -# endif -# define machine_is_james_926() (machine_arch_type == MACH_TYPE_JAMES_926) -#else -# define machine_is_james_926() (0) -#endif - -#ifdef CONFIG_MACH_FM6000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FM6000 -# endif -# define machine_is_fm6000() (machine_arch_type == MACH_TYPE_FM6000) -#else -# define machine_is_fm6000() (0) -#endif - -#ifdef CONFIG_MACH_DB88F6281_BP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DB88F6281_BP -# endif -# define machine_is_db88f6281_bp() (machine_arch_type == MACH_TYPE_DB88F6281_BP) -#else -# define machine_is_db88f6281_bp() (0) -#endif - -#ifdef CONFIG_MACH_RD88F6192_NAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F6192_NAS -# endif -# define machine_is_rd88f6192_nas() (machine_arch_type == MACH_TYPE_RD88F6192_NAS) -#else -# define machine_is_rd88f6192_nas() (0) -#endif - -#ifdef CONFIG_MACH_RD88F6281 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F6281 -# endif -# define machine_is_rd88f6281() (machine_arch_type == MACH_TYPE_RD88F6281) -#else -# define machine_is_rd88f6281() (0) -#endif - -#ifdef CONFIG_MACH_DB78X00_BP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DB78X00_BP -# endif -# define machine_is_db78x00_bp() (machine_arch_type == MACH_TYPE_DB78X00_BP) -#else -# define machine_is_db78x00_bp() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2416 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2416 -# endif -# define machine_is_smdk2416() (machine_arch_type == MACH_TYPE_SMDK2416) -#else -# define machine_is_smdk2416() (0) -#endif - -#ifdef CONFIG_MACH_OCE_SPIDER_SI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCE_SPIDER_SI -# endif -# define machine_is_oce_spider_si() (machine_arch_type == MACH_TYPE_OCE_SPIDER_SI) -#else -# define machine_is_oce_spider_si() (0) -#endif - -#ifdef CONFIG_MACH_OCE_SPIDER_SK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCE_SPIDER_SK -# endif -# define machine_is_oce_spider_sk() (machine_arch_type == MACH_TYPE_OCE_SPIDER_SK) -#else -# define machine_is_oce_spider_sk() (0) -#endif - -#ifdef CONFIG_MACH_ROVERN6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERN6 -# endif -# define machine_is_rovern6() (machine_arch_type == MACH_TYPE_ROVERN6) -#else -# define machine_is_rovern6() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_EVOLUTION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_EVOLUTION -# endif -# define machine_is_pelco_evolution() (machine_arch_type == MACH_TYPE_PELCO_EVOLUTION) -#else -# define machine_is_pelco_evolution() (0) -#endif - -#ifdef CONFIG_MACH_WBD111 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WBD111 -# endif -# define machine_is_wbd111() (machine_arch_type == MACH_TYPE_WBD111) -#else -# define machine_is_wbd111() (0) -#endif - -#ifdef CONFIG_MACH_ELARACPE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELARACPE -# endif -# define machine_is_elaracpe() (machine_arch_type == MACH_TYPE_ELARACPE) -#else -# define machine_is_elaracpe() (0) -#endif - -#ifdef CONFIG_MACH_MABV3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MABV3 -# endif -# define machine_is_mabv3() (machine_arch_type == MACH_TYPE_MABV3) -#else -# define machine_is_mabv3() (0) -#endif - -#ifdef CONFIG_MACH_MV2120 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV2120 -# endif -# define machine_is_mv2120() (machine_arch_type == MACH_TYPE_MV2120) -#else -# define machine_is_mv2120() (0) -#endif - -#ifdef CONFIG_MACH_CSB737 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB737 -# endif -# define machine_is_csb737() (machine_arch_type == MACH_TYPE_CSB737) -#else -# define machine_is_csb737() (0) -#endif - -#ifdef CONFIG_MACH_MX51_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_3DS -# endif -# define machine_is_mx51_3ds() (machine_arch_type == MACH_TYPE_MX51_3DS) -#else -# define machine_is_mx51_3ds() (0) -#endif - -#ifdef CONFIG_MACH_G900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G900 -# endif -# define machine_is_g900() (machine_arch_type == MACH_TYPE_G900) -#else -# define machine_is_g900() (0) -#endif - -#ifdef CONFIG_MACH_APF27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APF27 -# endif -# define machine_is_apf27() (machine_arch_type == MACH_TYPE_APF27) -#else -# define machine_is_apf27() (0) -#endif - -#ifdef CONFIG_MACH_GGUS2000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GGUS2000 -# endif -# define machine_is_ggus2000() (machine_arch_type == MACH_TYPE_GGUS2000) -#else -# define machine_is_ggus2000() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_2430_MIMIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_2430_MIMIC -# endif -# define machine_is_omap_2430_mimic() (machine_arch_type == MACH_TYPE_OMAP_2430_MIMIC) -#else -# define machine_is_omap_2430_mimic() (0) -#endif - -#ifdef CONFIG_MACH_IMX27LITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27LITE -# endif -# define machine_is_imx27lite() (machine_arch_type == MACH_TYPE_IMX27LITE) -#else -# define machine_is_imx27lite() (0) -#endif - -#ifdef CONFIG_MACH_ALMEX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALMEX -# endif -# define machine_is_almex() (machine_arch_type == MACH_TYPE_ALMEX) -#else -# define machine_is_almex() (0) -#endif - -#ifdef CONFIG_MACH_CONTROL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CONTROL -# endif -# define machine_is_control() (machine_arch_type == MACH_TYPE_CONTROL) -#else -# define machine_is_control() (0) -#endif - -#ifdef CONFIG_MACH_MBA2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MBA2410 -# endif -# define machine_is_mba2410() (machine_arch_type == MACH_TYPE_MBA2410) -#else -# define machine_is_mba2410() (0) -#endif - -#ifdef CONFIG_MACH_VOLCANO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VOLCANO -# endif -# define machine_is_volcano() (machine_arch_type == MACH_TYPE_VOLCANO) -#else -# define machine_is_volcano() (0) -#endif - -#ifdef CONFIG_MACH_ZENITH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZENITH -# endif -# define machine_is_zenith() (machine_arch_type == MACH_TYPE_ZENITH) -#else -# define machine_is_zenith() (0) -#endif - -#ifdef CONFIG_MACH_MUCHIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MUCHIP -# endif -# define machine_is_muchip() (machine_arch_type == MACH_TYPE_MUCHIP) -#else -# define machine_is_muchip() (0) -#endif - -#ifdef CONFIG_MACH_MAGELLAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGELLAN -# endif -# define machine_is_magellan() (machine_arch_type == MACH_TYPE_MAGELLAN) -#else -# define machine_is_magellan() (0) -#endif - -#ifdef CONFIG_MACH_USB_A9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USB_A9260 -# endif -# define machine_is_usb_a9260() (machine_arch_type == MACH_TYPE_USB_A9260) -#else -# define machine_is_usb_a9260() (0) -#endif - -#ifdef CONFIG_MACH_USB_A9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USB_A9263 -# endif -# define machine_is_usb_a9263() (machine_arch_type == MACH_TYPE_USB_A9263) -#else -# define machine_is_usb_a9263() (0) -#endif - -#ifdef CONFIG_MACH_QIL_A9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QIL_A9260 -# endif -# define machine_is_qil_a9260() (machine_arch_type == MACH_TYPE_QIL_A9260) -#else -# define machine_is_qil_a9260() (0) -#endif - -#ifdef CONFIG_MACH_CME9210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CME9210 -# endif -# define machine_is_cme9210() (machine_arch_type == MACH_TYPE_CME9210) -#else -# define machine_is_cme9210() (0) -#endif - -#ifdef CONFIG_MACH_HCZH4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HCZH4 -# endif -# define machine_is_hczh4() (machine_arch_type == MACH_TYPE_HCZH4) -#else -# define machine_is_hczh4() (0) -#endif - -#ifdef CONFIG_MACH_SPEARBASIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEARBASIC -# endif -# define machine_is_spearbasic() (machine_arch_type == MACH_TYPE_SPEARBASIC) -#else -# define machine_is_spearbasic() (0) -#endif - -#ifdef CONFIG_MACH_DEP2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEP2440 -# endif -# define machine_is_dep2440() (machine_arch_type == MACH_TYPE_DEP2440) -#else -# define machine_is_dep2440() (0) -#endif - -#ifdef CONFIG_MACH_HDL_GXR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDL_GXR -# endif -# define machine_is_hdl_gxr() (machine_arch_type == MACH_TYPE_HDL_GXR) -#else -# define machine_is_hdl_gxr() (0) -#endif - -#ifdef CONFIG_MACH_HDL_GT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDL_GT -# endif -# define machine_is_hdl_gt() (machine_arch_type == MACH_TYPE_HDL_GT) -#else -# define machine_is_hdl_gt() (0) -#endif - -#ifdef CONFIG_MACH_HDL_4G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDL_4G -# endif -# define machine_is_hdl_4g() (machine_arch_type == MACH_TYPE_HDL_4G) -#else -# define machine_is_hdl_4g() (0) -#endif - -#ifdef CONFIG_MACH_S3C6000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C6000 -# endif -# define machine_is_s3c6000() (machine_arch_type == MACH_TYPE_S3C6000) -#else -# define machine_is_s3c6000() (0) -#endif - -#ifdef CONFIG_MACH_MMSP2_MDK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMSP2_MDK -# endif -# define machine_is_mmsp2_mdk() (machine_arch_type == MACH_TYPE_MMSP2_MDK) -#else -# define machine_is_mmsp2_mdk() (0) -#endif - -#ifdef CONFIG_MACH_MPX220 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPX220 -# endif -# define machine_is_mpx220() (machine_arch_type == MACH_TYPE_MPX220) -#else -# define machine_is_mpx220() (0) -#endif - -#ifdef CONFIG_MACH_KZM_ARM11_01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KZM_ARM11_01 -# endif -# define machine_is_kzm_arm11_01() (machine_arch_type == MACH_TYPE_KZM_ARM11_01) -#else -# define machine_is_kzm_arm11_01() (0) -#endif - -#ifdef CONFIG_MACH_HTC_POLARIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_POLARIS -# endif -# define machine_is_htc_polaris() (machine_arch_type == MACH_TYPE_HTC_POLARIS) -#else -# define machine_is_htc_polaris() (0) -#endif - -#ifdef CONFIG_MACH_HTC_KAISER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_KAISER -# endif -# define machine_is_htc_kaiser() (machine_arch_type == MACH_TYPE_HTC_KAISER) -#else -# define machine_is_htc_kaiser() (0) -#endif - -#ifdef CONFIG_MACH_LG_KS20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LG_KS20 -# endif -# define machine_is_lg_ks20() (machine_arch_type == MACH_TYPE_LG_KS20) -#else -# define machine_is_lg_ks20() (0) -#endif - -#ifdef CONFIG_MACH_HHGPS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HHGPS -# endif -# define machine_is_hhgps() (machine_arch_type == MACH_TYPE_HHGPS) -#else -# define machine_is_hhgps() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_N810_WIMAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_N810_WIMAX -# endif -# define machine_is_nokia_n810_wimax() (machine_arch_type == MACH_TYPE_NOKIA_N810_WIMAX) -#else -# define machine_is_nokia_n810_wimax() (0) -#endif - -#ifdef CONFIG_MACH_INSIGHT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INSIGHT -# endif -# define machine_is_insight() (machine_arch_type == MACH_TYPE_INSIGHT) -#else -# define machine_is_insight() (0) -#endif - -#ifdef CONFIG_MACH_SAPPHIRE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAPPHIRE -# endif -# define machine_is_sapphire() (machine_arch_type == MACH_TYPE_SAPPHIRE) -#else -# define machine_is_sapphire() (0) -#endif - -#ifdef CONFIG_MACH_CSB637XO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB637XO -# endif -# define machine_is_csb637xo() (machine_arch_type == MACH_TYPE_CSB637XO) -#else -# define machine_is_csb637xo() (0) -#endif - -#ifdef CONFIG_MACH_EVISIONG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EVISIONG -# endif -# define machine_is_evisiong() (machine_arch_type == MACH_TYPE_EVISIONG) -#else -# define machine_is_evisiong() (0) -#endif - -#ifdef CONFIG_MACH_STMP37XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STMP37XX -# endif -# define machine_is_stmp37xx() (machine_arch_type == MACH_TYPE_STMP37XX) -#else -# define machine_is_stmp37xx() (0) -#endif - -#ifdef CONFIG_MACH_STMP38XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STMP38XX -# endif -# define machine_is_stmp378x() (machine_arch_type == MACH_TYPE_STMP38XX) -#else -# define machine_is_stmp378x() (0) -#endif - -#ifdef CONFIG_MACH_TNT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNT -# endif -# define machine_is_tnt() (machine_arch_type == MACH_TYPE_TNT) -#else -# define machine_is_tnt() (0) -#endif - -#ifdef CONFIG_MACH_TBXT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TBXT -# endif -# define machine_is_tbxt() (machine_arch_type == MACH_TYPE_TBXT) -#else -# define machine_is_tbxt() (0) -#endif - -#ifdef CONFIG_MACH_PLAYMATE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLAYMATE -# endif -# define machine_is_playmate() (machine_arch_type == MACH_TYPE_PLAYMATE) -#else -# define machine_is_playmate() (0) -#endif - -#ifdef CONFIG_MACH_PNS10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNS10 -# endif -# define machine_is_pns10() (machine_arch_type == MACH_TYPE_PNS10) -#else -# define machine_is_pns10() (0) -#endif - -#ifdef CONFIG_MACH_EZNAVI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZNAVI -# endif -# define machine_is_eznavi() (machine_arch_type == MACH_TYPE_EZNAVI) -#else -# define machine_is_eznavi() (0) -#endif - -#ifdef CONFIG_MACH_PS4000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PS4000 -# endif -# define machine_is_ps4000() (machine_arch_type == MACH_TYPE_PS4000) -#else -# define machine_is_ps4000() (0) -#endif - -#ifdef CONFIG_MACH_EZX_A780 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_A780 -# endif -# define machine_is_ezx_a780() (machine_arch_type == MACH_TYPE_EZX_A780) -#else -# define machine_is_ezx_a780() (0) -#endif - -#ifdef CONFIG_MACH_EZX_E680 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_E680 -# endif -# define machine_is_ezx_e680() (machine_arch_type == MACH_TYPE_EZX_E680) -#else -# define machine_is_ezx_e680() (0) -#endif - -#ifdef CONFIG_MACH_EZX_A1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_A1200 -# endif -# define machine_is_ezx_a1200() (machine_arch_type == MACH_TYPE_EZX_A1200) -#else -# define machine_is_ezx_a1200() (0) -#endif - -#ifdef CONFIG_MACH_EZX_E6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_E6 -# endif -# define machine_is_ezx_e6() (machine_arch_type == MACH_TYPE_EZX_E6) -#else -# define machine_is_ezx_e6() (0) -#endif - -#ifdef CONFIG_MACH_EZX_E2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_E2 -# endif -# define machine_is_ezx_e2() (machine_arch_type == MACH_TYPE_EZX_E2) -#else -# define machine_is_ezx_e2() (0) -#endif - -#ifdef CONFIG_MACH_EZX_A910 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_A910 -# endif -# define machine_is_ezx_a910() (machine_arch_type == MACH_TYPE_EZX_A910) -#else -# define machine_is_ezx_a910() (0) -#endif - -#ifdef CONFIG_MACH_CWMX31 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWMX31 -# endif -# define machine_is_cwmx31() (machine_arch_type == MACH_TYPE_CWMX31) -#else -# define machine_is_cwmx31() (0) -#endif - -#ifdef CONFIG_MACH_SL2312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SL2312 -# endif -# define machine_is_sl2312() (machine_arch_type == MACH_TYPE_SL2312) -#else -# define machine_is_sl2312() (0) -#endif - -#ifdef CONFIG_MACH_BLENNY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLENNY -# endif -# define machine_is_blenny() (machine_arch_type == MACH_TYPE_BLENNY) -#else -# define machine_is_blenny() (0) -#endif - -#ifdef CONFIG_MACH_DS107 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS107 -# endif -# define machine_is_ds107() (machine_arch_type == MACH_TYPE_DS107) -#else -# define machine_is_ds107() (0) -#endif - -#ifdef CONFIG_MACH_DSX07 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSX07 -# endif -# define machine_is_dsx07() (machine_arch_type == MACH_TYPE_DSX07) -#else -# define machine_is_dsx07() (0) -#endif - -#ifdef CONFIG_MACH_PICOCOM1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOCOM1 -# endif -# define machine_is_picocom1() (machine_arch_type == MACH_TYPE_PICOCOM1) -#else -# define machine_is_picocom1() (0) -#endif - -#ifdef CONFIG_MACH_LYNX_WOLVERINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LYNX_WOLVERINE -# endif -# define machine_is_lynx_wolverine() (machine_arch_type == MACH_TYPE_LYNX_WOLVERINE) -#else -# define machine_is_lynx_wolverine() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9_SC19 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9_SC19 -# endif -# define machine_is_ubisys_p9_sc19() (machine_arch_type == MACH_TYPE_UBISYS_P9_SC19) -#else -# define machine_is_ubisys_p9_sc19() (0) -#endif - -#ifdef CONFIG_MACH_KRATOS_LOW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KRATOS_LOW -# endif -# define machine_is_kratos_low() (machine_arch_type == MACH_TYPE_KRATOS_LOW) -#else -# define machine_is_kratos_low() (0) -#endif - -#ifdef CONFIG_MACH_M700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M700 -# endif -# define machine_is_m700() (machine_arch_type == MACH_TYPE_M700) -#else -# define machine_is_m700() (0) -#endif - -#ifdef CONFIG_MACH_EDMINI_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDMINI_V2 -# endif -# define machine_is_edmini_v2() (machine_arch_type == MACH_TYPE_EDMINI_V2) -#else -# define machine_is_edmini_v2() (0) -#endif - -#ifdef CONFIG_MACH_ZIPIT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIPIT2 -# endif -# define machine_is_zipit2() (machine_arch_type == MACH_TYPE_ZIPIT2) -#else -# define machine_is_zipit2() (0) -#endif - -#ifdef CONFIG_MACH_HSLFEMTOCELL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HSLFEMTOCELL -# endif -# define machine_is_hslfemtocell() (machine_arch_type == MACH_TYPE_HSLFEMTOCELL) -#else -# define machine_is_hslfemtocell() (0) -#endif - -#ifdef CONFIG_MACH_DAINTREE_AT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAINTREE_AT91 -# endif -# define machine_is_daintree_at91() (machine_arch_type == MACH_TYPE_DAINTREE_AT91) -#else -# define machine_is_daintree_at91() (0) -#endif - -#ifdef CONFIG_MACH_SG560USB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG560USB -# endif -# define machine_is_sg560usb() (machine_arch_type == MACH_TYPE_SG560USB) -#else -# define machine_is_sg560usb() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_PANDORA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_PANDORA -# endif -# define machine_is_omap3_pandora() (machine_arch_type == MACH_TYPE_OMAP3_PANDORA) -#else -# define machine_is_omap3_pandora() (0) -#endif - -#ifdef CONFIG_MACH_USR8200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USR8200 -# endif -# define machine_is_usr8200() (machine_arch_type == MACH_TYPE_USR8200) -#else -# define machine_is_usr8200() (0) -#endif - -#ifdef CONFIG_MACH_S1S65K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S1S65K -# endif -# define machine_is_s1s65k() (machine_arch_type == MACH_TYPE_S1S65K) -#else -# define machine_is_s1s65k() (0) -#endif - -#ifdef CONFIG_MACH_S2S65A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S2S65A -# endif -# define machine_is_s2s65a() (machine_arch_type == MACH_TYPE_S2S65A) -#else -# define machine_is_s2s65a() (0) -#endif - -#ifdef CONFIG_MACH_ICORE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICORE -# endif -# define machine_is_icore() (machine_arch_type == MACH_TYPE_ICORE) -#else -# define machine_is_icore() (0) -#endif - -#ifdef CONFIG_MACH_MSS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSS2 -# endif -# define machine_is_mss2() (machine_arch_type == MACH_TYPE_MSS2) -#else -# define machine_is_mss2() (0) -#endif - -#ifdef CONFIG_MACH_BELMONT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BELMONT -# endif -# define machine_is_belmont() (machine_arch_type == MACH_TYPE_BELMONT) -#else -# define machine_is_belmont() (0) -#endif - -#ifdef CONFIG_MACH_ASUSP525 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASUSP525 -# endif -# define machine_is_asusp525() (machine_arch_type == MACH_TYPE_ASUSP525) -#else -# define machine_is_asusp525() (0) -#endif - -#ifdef CONFIG_MACH_LB88RC8480 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LB88RC8480 -# endif -# define machine_is_lb88rc8480() (machine_arch_type == MACH_TYPE_LB88RC8480) -#else -# define machine_is_lb88rc8480() (0) -#endif - -#ifdef CONFIG_MACH_HIPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIPXA -# endif -# define machine_is_hipxa() (machine_arch_type == MACH_TYPE_HIPXA) -#else -# define machine_is_hipxa() (0) -#endif - -#ifdef CONFIG_MACH_MX25_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX25_3DS -# endif -# define machine_is_mx25_3ds() (machine_arch_type == MACH_TYPE_MX25_3DS) -#else -# define machine_is_mx25_3ds() (0) -#endif - -#ifdef CONFIG_MACH_M800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M800 -# endif -# define machine_is_m800() (machine_arch_type == MACH_TYPE_M800) -#else -# define machine_is_m800() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3530_LV_SOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3530_LV_SOM -# endif -# define machine_is_omap3530_lv_som() (machine_arch_type == MACH_TYPE_OMAP3530_LV_SOM) -#else -# define machine_is_omap3530_lv_som() (0) -#endif - -#ifdef CONFIG_MACH_PRIMA_EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRIMA_EVB -# endif -# define machine_is_prima_evb() (machine_arch_type == MACH_TYPE_PRIMA_EVB) -#else -# define machine_is_prima_evb() (0) -#endif - -#ifdef CONFIG_MACH_MX31BT1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31BT1 -# endif -# define machine_is_mx31bt1() (machine_arch_type == MACH_TYPE_MX31BT1) -#else -# define machine_is_mx31bt1() (0) -#endif - -#ifdef CONFIG_MACH_ATLAS4_EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATLAS4_EVB -# endif -# define machine_is_atlas4_evb() (machine_arch_type == MACH_TYPE_ATLAS4_EVB) -#else -# define machine_is_atlas4_evb() (0) -#endif - -#ifdef CONFIG_MACH_MX31CICADA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31CICADA -# endif -# define machine_is_mx31cicada() (machine_arch_type == MACH_TYPE_MX31CICADA) -#else -# define machine_is_mx31cicada() (0) -#endif - -#ifdef CONFIG_MACH_MI424WR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MI424WR -# endif -# define machine_is_mi424wr() (machine_arch_type == MACH_TYPE_MI424WR) -#else -# define machine_is_mi424wr() (0) -#endif - -#ifdef CONFIG_MACH_AXS_ULTRAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXS_ULTRAX -# endif -# define machine_is_axs_ultrax() (machine_arch_type == MACH_TYPE_AXS_ULTRAX) -#else -# define machine_is_axs_ultrax() (0) -#endif - -#ifdef CONFIG_MACH_AT572D940DEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT572D940DEB -# endif -# define machine_is_at572d940deb() (machine_arch_type == MACH_TYPE_AT572D940DEB) -#else -# define machine_is_at572d940deb() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DA8XX_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DA8XX_EVM -# endif -# define machine_is_davinci_da8xx_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA8XX_EVM) -#else -# define machine_is_davinci_da8xx_evm() (0) -#endif - -#ifdef CONFIG_MACH_EP9302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EP9302 -# endif -# define machine_is_ep9302() (machine_arch_type == MACH_TYPE_EP9302) -#else -# define machine_is_ep9302() (0) -#endif - -#ifdef CONFIG_MACH_AT572D940HFEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT572D940HFEB -# endif -# define machine_is_at572d940hfek() (machine_arch_type == MACH_TYPE_AT572D940HFEB) -#else -# define machine_is_at572d940hfek() (0) -#endif - -#ifdef CONFIG_MACH_CYBOOK3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYBOOK3 -# endif -# define machine_is_cybook3() (machine_arch_type == MACH_TYPE_CYBOOK3) -#else -# define machine_is_cybook3() (0) -#endif - -#ifdef CONFIG_MACH_WDG002 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WDG002 -# endif -# define machine_is_wdg002() (machine_arch_type == MACH_TYPE_WDG002) -#else -# define machine_is_wdg002() (0) -#endif - -#ifdef CONFIG_MACH_SG560ADSL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG560ADSL -# endif -# define machine_is_sg560adsl() (machine_arch_type == MACH_TYPE_SG560ADSL) -#else -# define machine_is_sg560adsl() (0) -#endif - -#ifdef CONFIG_MACH_NEXTIO_N2800_ICA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXTIO_N2800_ICA -# endif -# define machine_is_nextio_n2800_ica() (machine_arch_type == MACH_TYPE_NEXTIO_N2800_ICA) -#else -# define machine_is_nextio_n2800_ica() (0) -#endif - -#ifdef CONFIG_MACH_MARVELL_NEWDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARVELL_NEWDB -# endif -# define machine_is_marvell_newdb() (machine_arch_type == MACH_TYPE_MARVELL_NEWDB) -#else -# define machine_is_marvell_newdb() (0) -#endif - -#ifdef CONFIG_MACH_VANDIHUD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VANDIHUD -# endif -# define machine_is_vandihud() (machine_arch_type == MACH_TYPE_VANDIHUD) -#else -# define machine_is_vandihud() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_E8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_E8 -# endif -# define machine_is_magx_e8() (machine_arch_type == MACH_TYPE_MAGX_E8) -#else -# define machine_is_magx_e8() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_Z6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_Z6 -# endif -# define machine_is_magx_z6() (machine_arch_type == MACH_TYPE_MAGX_Z6) -#else -# define machine_is_magx_z6() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_V8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_V8 -# endif -# define machine_is_magx_v8() (machine_arch_type == MACH_TYPE_MAGX_V8) -#else -# define machine_is_magx_v8() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_U9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_U9 -# endif -# define machine_is_magx_u9() (machine_arch_type == MACH_TYPE_MAGX_U9) -#else -# define machine_is_magx_u9() (0) -#endif - -#ifdef CONFIG_MACH_TOUGHCF08 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOUGHCF08 -# endif -# define machine_is_toughcf08() (machine_arch_type == MACH_TYPE_TOUGHCF08) -#else -# define machine_is_toughcf08() (0) -#endif - -#ifdef CONFIG_MACH_ZW4400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZW4400 -# endif -# define machine_is_zw4400() (machine_arch_type == MACH_TYPE_ZW4400) -#else -# define machine_is_zw4400() (0) -#endif - -#ifdef CONFIG_MACH_MARAT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARAT91 -# endif -# define machine_is_marat91() (machine_arch_type == MACH_TYPE_MARAT91) -#else -# define machine_is_marat91() (0) -#endif - -#ifdef CONFIG_MACH_OVERO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OVERO -# endif -# define machine_is_overo() (machine_arch_type == MACH_TYPE_OVERO) -#else -# define machine_is_overo() (0) -#endif - -#ifdef CONFIG_MACH_AT2440EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT2440EVB -# endif -# define machine_is_at2440evb() (machine_arch_type == MACH_TYPE_AT2440EVB) -#else -# define machine_is_at2440evb() (0) -#endif - -#ifdef CONFIG_MACH_NEOCORE926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEOCORE926 -# endif -# define machine_is_neocore926() (machine_arch_type == MACH_TYPE_NEOCORE926) -#else -# define machine_is_neocore926() (0) -#endif - -#ifdef CONFIG_MACH_WNR854T -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WNR854T -# endif -# define machine_is_wnr854t() (machine_arch_type == MACH_TYPE_WNR854T) -#else -# define machine_is_wnr854t() (0) -#endif - -#ifdef CONFIG_MACH_IMX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27 -# endif -# define machine_is_imx27() (machine_arch_type == MACH_TYPE_IMX27) -#else -# define machine_is_imx27() (0) -#endif - -#ifdef CONFIG_MACH_MOOSE_DB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOOSE_DB -# endif -# define machine_is_moose_db() (machine_arch_type == MACH_TYPE_MOOSE_DB) -#else -# define machine_is_moose_db() (0) -#endif - -#ifdef CONFIG_MACH_FAB4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FAB4 -# endif -# define machine_is_fab4() (machine_arch_type == MACH_TYPE_FAB4) -#else -# define machine_is_fab4() (0) -#endif - -#ifdef CONFIG_MACH_HTCDIAMOND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCDIAMOND -# endif -# define machine_is_htcdiamond() (machine_arch_type == MACH_TYPE_HTCDIAMOND) -#else -# define machine_is_htcdiamond() (0) -#endif - -#ifdef CONFIG_MACH_FIONA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FIONA -# endif -# define machine_is_fiona() (machine_arch_type == MACH_TYPE_FIONA) -#else -# define machine_is_fiona() (0) -#endif - -#ifdef CONFIG_MACH_MXC30030_X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30030_X -# endif -# define machine_is_mxc30030_x() (machine_arch_type == MACH_TYPE_MXC30030_X) -#else -# define machine_is_mxc30030_x() (0) -#endif - -#ifdef CONFIG_MACH_BMP1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BMP1000 -# endif -# define machine_is_bmp1000() (machine_arch_type == MACH_TYPE_BMP1000) -#else -# define machine_is_bmp1000() (0) -#endif - -#ifdef CONFIG_MACH_LOGI9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOGI9200 -# endif -# define machine_is_logi9200() (machine_arch_type == MACH_TYPE_LOGI9200) -#else -# define machine_is_logi9200() (0) -#endif - -#ifdef CONFIG_MACH_TQMA31 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TQMA31 -# endif -# define machine_is_tqma31() (machine_arch_type == MACH_TYPE_TQMA31) -#else -# define machine_is_tqma31() (0) -#endif - -#ifdef CONFIG_MACH_CCW9P9215JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCW9P9215JS -# endif -# define machine_is_ccw9p9215js() (machine_arch_type == MACH_TYPE_CCW9P9215JS) -#else -# define machine_is_ccw9p9215js() (0) -#endif - -#ifdef CONFIG_MACH_RD88F5181L_GE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F5181L_GE -# endif -# define machine_is_rd88f5181l_ge() (machine_arch_type == MACH_TYPE_RD88F5181L_GE) -#else -# define machine_is_rd88f5181l_ge() (0) -#endif - -#ifdef CONFIG_MACH_SIFMAIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIFMAIN -# endif -# define machine_is_sifmain() (machine_arch_type == MACH_TYPE_SIFMAIN) -#else -# define machine_is_sifmain() (0) -#endif - -#ifdef CONFIG_MACH_SAM9_L9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM9_L9261 -# endif -# define machine_is_sam9_l9261() (machine_arch_type == MACH_TYPE_SAM9_L9261) -#else -# define machine_is_sam9_l9261() (0) -#endif - -#ifdef CONFIG_MACH_CC9M2443JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9M2443JS -# endif -# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS) -#else -# define machine_is_cc9m2443js() (0) -#endif - -#ifdef CONFIG_MACH_XARIA300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XARIA300 -# endif -# define machine_is_xaria300() (machine_arch_type == MACH_TYPE_XARIA300) -#else -# define machine_is_xaria300() (0) -#endif - -#ifdef CONFIG_MACH_IT9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IT9200 -# endif -# define machine_is_it9200() (machine_arch_type == MACH_TYPE_IT9200) -#else -# define machine_is_it9200() (0) -#endif - -#ifdef CONFIG_MACH_RD88F5181L_FXO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F5181L_FXO -# endif -# define machine_is_rd88f5181l_fxo() (machine_arch_type == MACH_TYPE_RD88F5181L_FXO) -#else -# define machine_is_rd88f5181l_fxo() (0) -#endif - -#ifdef CONFIG_MACH_KRISS_SENSOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KRISS_SENSOR -# endif -# define machine_is_kriss_sensor() (machine_arch_type == MACH_TYPE_KRISS_SENSOR) -#else -# define machine_is_kriss_sensor() (0) -#endif - -#ifdef CONFIG_MACH_PILZ_PMI5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PILZ_PMI5 -# endif -# define machine_is_pilz_pmi5() (machine_arch_type == MACH_TYPE_PILZ_PMI5) -#else -# define machine_is_pilz_pmi5() (0) -#endif - -#ifdef CONFIG_MACH_JADE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JADE -# endif -# define machine_is_jade() (machine_arch_type == MACH_TYPE_JADE) -#else -# define machine_is_jade() (0) -#endif - -#ifdef CONFIG_MACH_KS8695_SOFTPLC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KS8695_SOFTPLC -# endif -# define machine_is_ks8695_softplc() (machine_arch_type == MACH_TYPE_KS8695_SOFTPLC) -#else -# define machine_is_ks8695_softplc() (0) -#endif - -#ifdef CONFIG_MACH_GPRISC3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GPRISC3 -# endif -# define machine_is_gprisc3() (machine_arch_type == MACH_TYPE_GPRISC3) -#else -# define machine_is_gprisc3() (0) -#endif - -#ifdef CONFIG_MACH_STAMP9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STAMP9G20 -# endif -# define machine_is_stamp9g20() (machine_arch_type == MACH_TYPE_STAMP9G20) -#else -# define machine_is_stamp9g20() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6430 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6430 -# endif -# define machine_is_smdk6430() (machine_arch_type == MACH_TYPE_SMDK6430) -#else -# define machine_is_smdk6430() (0) -#endif - -#ifdef CONFIG_MACH_SMDKC100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDKC100 -# endif -# define machine_is_smdkc100() (machine_arch_type == MACH_TYPE_SMDKC100) -#else -# define machine_is_smdkc100() (0) -#endif - -#ifdef CONFIG_MACH_TAVOREVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAVOREVB -# endif -# define machine_is_tavorevb() (machine_arch_type == MACH_TYPE_TAVOREVB) -#else -# define machine_is_tavorevb() (0) -#endif - -#ifdef CONFIG_MACH_SAAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAAR -# endif -# define machine_is_saar() (machine_arch_type == MACH_TYPE_SAAR) -#else -# define machine_is_saar() (0) -#endif - -#ifdef CONFIG_MACH_DEISTER_EYECAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEISTER_EYECAM -# endif -# define machine_is_deister_eyecam() (machine_arch_type == MACH_TYPE_DEISTER_EYECAM) -#else -# define machine_is_deister_eyecam() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9M10EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9M10EK -# endif -# define machine_is_at91sam9m10ek() (machine_arch_type == MACH_TYPE_AT91SAM9M10EK) -#else -# define machine_is_at91sam9m10ek() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_PRODUO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_PRODUO -# endif -# define machine_is_linkstation_produo() (machine_arch_type == MACH_TYPE_LINKSTATION_PRODUO) -#else -# define machine_is_linkstation_produo() (0) -#endif - -#ifdef CONFIG_MACH_HIT_B0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIT_B0 -# endif -# define machine_is_hit_b0() (machine_arch_type == MACH_TYPE_HIT_B0) -#else -# define machine_is_hit_b0() (0) -#endif - -#ifdef CONFIG_MACH_ADX_RMU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_RMU -# endif -# define machine_is_adx_rmu() (machine_arch_type == MACH_TYPE_ADX_RMU) -#else -# define machine_is_adx_rmu() (0) -#endif - -#ifdef CONFIG_MACH_XG_CPE_MAIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XG_CPE_MAIN -# endif -# define machine_is_xg_cpe_main() (machine_arch_type == MACH_TYPE_XG_CPE_MAIN) -#else -# define machine_is_xg_cpe_main() (0) -#endif - -#ifdef CONFIG_MACH_EDB9407A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9407A -# endif -# define machine_is_edb9407a() (machine_arch_type == MACH_TYPE_EDB9407A) -#else -# define machine_is_edb9407a() (0) -#endif - -#ifdef CONFIG_MACH_DTB9608 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DTB9608 -# endif -# define machine_is_dtb9608() (machine_arch_type == MACH_TYPE_DTB9608) -#else -# define machine_is_dtb9608() (0) -#endif - -#ifdef CONFIG_MACH_EM104V1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EM104V1 -# endif -# define machine_is_em104v1() (machine_arch_type == MACH_TYPE_EM104V1) -#else -# define machine_is_em104v1() (0) -#endif - -#ifdef CONFIG_MACH_DEMO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEMO -# endif -# define machine_is_demo() (machine_arch_type == MACH_TYPE_DEMO) -#else -# define machine_is_demo() (0) -#endif - -#ifdef CONFIG_MACH_LOGI9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOGI9260 -# endif -# define machine_is_logi9260() (machine_arch_type == MACH_TYPE_LOGI9260) -#else -# define machine_is_logi9260() (0) -#endif - -#ifdef CONFIG_MACH_MX31_EXM32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31_EXM32 -# endif -# define machine_is_mx31_exm32() (machine_arch_type == MACH_TYPE_MX31_EXM32) -#else -# define machine_is_mx31_exm32() (0) -#endif - -#ifdef CONFIG_MACH_USB_A9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USB_A9G20 -# endif -# define machine_is_usb_a9g20() (machine_arch_type == MACH_TYPE_USB_A9G20) -#else -# define machine_is_usb_a9g20() (0) -#endif - -#ifdef CONFIG_MACH_PICPROJE2008 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICPROJE2008 -# endif -# define machine_is_picproje2008() (machine_arch_type == MACH_TYPE_PICPROJE2008) -#else -# define machine_is_picproje2008() (0) -#endif - -#ifdef CONFIG_MACH_CS_E9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CS_E9315 -# endif -# define machine_is_cs_e9315() (machine_arch_type == MACH_TYPE_CS_E9315) -#else -# define machine_is_cs_e9315() (0) -#endif - -#ifdef CONFIG_MACH_QIL_A9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QIL_A9G20 -# endif -# define machine_is_qil_a9g20() (machine_arch_type == MACH_TYPE_QIL_A9G20) -#else -# define machine_is_qil_a9g20() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON020 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON020 -# endif -# define machine_is_sha_pon020() (machine_arch_type == MACH_TYPE_SHA_PON020) -#else -# define machine_is_sha_pon020() (0) -#endif - -#ifdef CONFIG_MACH_NAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAD -# endif -# define machine_is_nad() (machine_arch_type == MACH_TYPE_NAD) -#else -# define machine_is_nad() (0) -#endif - -#ifdef CONFIG_MACH_SBC35_A9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC35_A9260 -# endif -# define machine_is_sbc35_a9260() (machine_arch_type == MACH_TYPE_SBC35_A9260) -#else -# define machine_is_sbc35_a9260() (0) -#endif - -#ifdef CONFIG_MACH_SBC35_A9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC35_A9G20 -# endif -# define machine_is_sbc35_a9g20() (machine_arch_type == MACH_TYPE_SBC35_A9G20) -#else -# define machine_is_sbc35_a9g20() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_BEGINNING -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_BEGINNING -# endif -# define machine_is_davinci_beginning() (machine_arch_type == MACH_TYPE_DAVINCI_BEGINNING) -#else -# define machine_is_davinci_beginning() (0) -#endif - -#ifdef CONFIG_MACH_UWC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UWC -# endif -# define machine_is_uwc() (machine_arch_type == MACH_TYPE_UWC) -#else -# define machine_is_uwc() (0) -#endif - -#ifdef CONFIG_MACH_MXLADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXLADS -# endif -# define machine_is_mxlads() (machine_arch_type == MACH_TYPE_MXLADS) -#else -# define machine_is_mxlads() (0) -#endif - -#ifdef CONFIG_MACH_HTCNIKE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCNIKE -# endif -# define machine_is_htcnike() (machine_arch_type == MACH_TYPE_HTCNIKE) -#else -# define machine_is_htcnike() (0) -#endif - -#ifdef CONFIG_MACH_DEISTER_PXA270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEISTER_PXA270 -# endif -# define machine_is_deister_pxa270() (machine_arch_type == MACH_TYPE_DEISTER_PXA270) -#else -# define machine_is_deister_pxa270() (0) -#endif - -#ifdef CONFIG_MACH_CME9210JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CME9210JS -# endif -# define machine_is_cme9210js() (machine_arch_type == MACH_TYPE_CME9210JS) -#else -# define machine_is_cme9210js() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9360 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9360 -# endif -# define machine_is_cc9p9360() (machine_arch_type == MACH_TYPE_CC9P9360) -#else -# define machine_is_cc9p9360() (0) -#endif - -#ifdef CONFIG_MACH_MOCHA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOCHA -# endif -# define machine_is_mocha() (machine_arch_type == MACH_TYPE_MOCHA) -#else -# define machine_is_mocha() (0) -#endif - -#ifdef CONFIG_MACH_WAPD170AG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WAPD170AG -# endif -# define machine_is_wapd170ag() (machine_arch_type == MACH_TYPE_WAPD170AG) -#else -# define machine_is_wapd170ag() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_MINI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_MINI -# endif -# define machine_is_linkstation_mini() (machine_arch_type == MACH_TYPE_LINKSTATION_MINI) -#else -# define machine_is_linkstation_mini() (0) -#endif - -#ifdef CONFIG_MACH_AFEB9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AFEB9260 -# endif -# define machine_is_afeb9260() (machine_arch_type == MACH_TYPE_AFEB9260) -#else -# define machine_is_afeb9260() (0) -#endif - -#ifdef CONFIG_MACH_W90X900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90X900 -# endif -# define machine_is_w90x900() (machine_arch_type == MACH_TYPE_W90X900) -#else -# define machine_is_w90x900() (0) -#endif - -#ifdef CONFIG_MACH_W90X700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90X700 -# endif -# define machine_is_w90x700() (machine_arch_type == MACH_TYPE_W90X700) -#else -# define machine_is_w90x700() (0) -#endif - -#ifdef CONFIG_MACH_KT300IP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KT300IP -# endif -# define machine_is_kt300ip() (machine_arch_type == MACH_TYPE_KT300IP) -#else -# define machine_is_kt300ip() (0) -#endif - -#ifdef CONFIG_MACH_KT300IP_G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KT300IP_G20 -# endif -# define machine_is_kt300ip_g20() (machine_arch_type == MACH_TYPE_KT300IP_G20) -#else -# define machine_is_kt300ip_g20() (0) -#endif - -#ifdef CONFIG_MACH_SRCM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SRCM -# endif -# define machine_is_srcm() (machine_arch_type == MACH_TYPE_SRCM) -#else -# define machine_is_srcm() (0) -#endif - -#ifdef CONFIG_MACH_WLNX_9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WLNX_9260 -# endif -# define machine_is_wlnx_9260() (machine_arch_type == MACH_TYPE_WLNX_9260) -#else -# define machine_is_wlnx_9260() (0) -#endif - -#ifdef CONFIG_MACH_OPENMOKO_GTA03 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENMOKO_GTA03 -# endif -# define machine_is_openmoko_gta03() (machine_arch_type == MACH_TYPE_OPENMOKO_GTA03) -#else -# define machine_is_openmoko_gta03() (0) -#endif - -#ifdef CONFIG_MACH_OSPREY2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSPREY2 -# endif -# define machine_is_osprey2() (machine_arch_type == MACH_TYPE_OSPREY2) -#else -# define machine_is_osprey2() (0) -#endif - -#ifdef CONFIG_MACH_KBIO9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KBIO9260 -# endif -# define machine_is_kbio9260() (machine_arch_type == MACH_TYPE_KBIO9260) -#else -# define machine_is_kbio9260() (0) -#endif - -#ifdef CONFIG_MACH_GINZA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GINZA -# endif -# define machine_is_ginza() (machine_arch_type == MACH_TYPE_GINZA) -#else -# define machine_is_ginza() (0) -#endif - -#ifdef CONFIG_MACH_A636N -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A636N -# endif -# define machine_is_a636n() (machine_arch_type == MACH_TYPE_A636N) -#else -# define machine_is_a636n() (0) -#endif - -#ifdef CONFIG_MACH_IMX27IPCAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27IPCAM -# endif -# define machine_is_imx27ipcam() (machine_arch_type == MACH_TYPE_IMX27IPCAM) -#else -# define machine_is_imx27ipcam() (0) -#endif - -#ifdef CONFIG_MACH_NEMOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEMOC -# endif -# define machine_is_nemoc() (machine_arch_type == MACH_TYPE_NEMOC) -#else -# define machine_is_nemoc() (0) -#endif - -#ifdef CONFIG_MACH_GENEVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GENEVA -# endif -# define machine_is_geneva() (machine_arch_type == MACH_TYPE_GENEVA) -#else -# define machine_is_geneva() (0) -#endif - -#ifdef CONFIG_MACH_HTCPHAROS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCPHAROS -# endif -# define machine_is_htcpharos() (machine_arch_type == MACH_TYPE_HTCPHAROS) -#else -# define machine_is_htcpharos() (0) -#endif - -#ifdef CONFIG_MACH_NEONC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEONC -# endif -# define machine_is_neonc() (machine_arch_type == MACH_TYPE_NEONC) -#else -# define machine_is_neonc() (0) -#endif - -#ifdef CONFIG_MACH_NAS7100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAS7100 -# endif -# define machine_is_nas7100() (machine_arch_type == MACH_TYPE_NAS7100) -#else -# define machine_is_nas7100() (0) -#endif - -#ifdef CONFIG_MACH_TEUPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEUPHONE -# endif -# define machine_is_teuphone() (machine_arch_type == MACH_TYPE_TEUPHONE) -#else -# define machine_is_teuphone() (0) -#endif - -#ifdef CONFIG_MACH_ANNAX_ETH2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANNAX_ETH2 -# endif -# define machine_is_annax_eth2() (machine_arch_type == MACH_TYPE_ANNAX_ETH2) -#else -# define machine_is_annax_eth2() (0) -#endif - -#ifdef CONFIG_MACH_CSB733 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB733 -# endif -# define machine_is_csb733() (machine_arch_type == MACH_TYPE_CSB733) -#else -# define machine_is_csb733() (0) -#endif - -#ifdef CONFIG_MACH_BK3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BK3 -# endif -# define machine_is_bk3() (machine_arch_type == MACH_TYPE_BK3) -#else -# define machine_is_bk3() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_EM32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_EM32 -# endif -# define machine_is_omap_em32() (machine_arch_type == MACH_TYPE_OMAP_EM32) -#else -# define machine_is_omap_em32() (0) -#endif - -#ifdef CONFIG_MACH_ET9261CP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ET9261CP -# endif -# define machine_is_et9261cp() (machine_arch_type == MACH_TYPE_ET9261CP) -#else -# define machine_is_et9261cp() (0) -#endif - -#ifdef CONFIG_MACH_JASPERC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JASPERC -# endif -# define machine_is_jasperc() (machine_arch_type == MACH_TYPE_JASPERC) -#else -# define machine_is_jasperc() (0) -#endif - -#ifdef CONFIG_MACH_ISSI_ARM9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ISSI_ARM9 -# endif -# define machine_is_issi_arm9() (machine_arch_type == MACH_TYPE_ISSI_ARM9) -#else -# define machine_is_issi_arm9() (0) -#endif - -#ifdef CONFIG_MACH_UED -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UED -# endif -# define machine_is_ued() (machine_arch_type == MACH_TYPE_UED) -#else -# define machine_is_ued() (0) -#endif - -#ifdef CONFIG_MACH_ESIBLADE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESIBLADE -# endif -# define machine_is_esiblade() (machine_arch_type == MACH_TYPE_ESIBLADE) -#else -# define machine_is_esiblade() (0) -#endif - -#ifdef CONFIG_MACH_EYE02 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EYE02 -# endif -# define machine_is_eye02() (machine_arch_type == MACH_TYPE_EYE02) -#else -# define machine_is_eye02() (0) -#endif - -#ifdef CONFIG_MACH_IMX27KBD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27KBD -# endif -# define machine_is_imx27kbd() (machine_arch_type == MACH_TYPE_IMX27KBD) -#else -# define machine_is_imx27kbd() (0) -#endif - -#ifdef CONFIG_MACH_SST61VC010_FPGA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SST61VC010_FPGA -# endif -# define machine_is_sst61vc010_fpga() (machine_arch_type == MACH_TYPE_SST61VC010_FPGA) -#else -# define machine_is_sst61vc010_fpga() (0) -#endif - -#ifdef CONFIG_MACH_KIXVP435 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KIXVP435 -# endif -# define machine_is_kixvp435() (machine_arch_type == MACH_TYPE_KIXVP435) -#else -# define machine_is_kixvp435() (0) -#endif - -#ifdef CONFIG_MACH_KIXNP435 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KIXNP435 -# endif -# define machine_is_kixnp435() (machine_arch_type == MACH_TYPE_KIXNP435) -#else -# define machine_is_kixnp435() (0) -#endif - -#ifdef CONFIG_MACH_AFRICA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AFRICA -# endif -# define machine_is_africa() (machine_arch_type == MACH_TYPE_AFRICA) -#else -# define machine_is_africa() (0) -#endif - -#ifdef CONFIG_MACH_NH233 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NH233 -# endif -# define machine_is_nh233() (machine_arch_type == MACH_TYPE_NH233) -#else -# define machine_is_nh233() (0) -#endif - -#ifdef CONFIG_MACH_RD88F6183AP_GE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F6183AP_GE -# endif -# define machine_is_rd88f6183ap_ge() (machine_arch_type == MACH_TYPE_RD88F6183AP_GE) -#else -# define machine_is_rd88f6183ap_ge() (0) -#endif - -#ifdef CONFIG_MACH_BCM4760 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCM4760 -# endif -# define machine_is_bcm4760() (machine_arch_type == MACH_TYPE_BCM4760) -#else -# define machine_is_bcm4760() (0) -#endif - -#ifdef CONFIG_MACH_EDDY_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDDY_V2 -# endif -# define machine_is_eddy_v2() (machine_arch_type == MACH_TYPE_EDDY_V2) -#else -# define machine_is_eddy_v2() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PBA8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PBA8 -# endif -# define machine_is_realview_pba8() (machine_arch_type == MACH_TYPE_REALVIEW_PBA8) -#else -# define machine_is_realview_pba8() (0) -#endif - -#ifdef CONFIG_MACH_HID_A7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HID_A7 -# endif -# define machine_is_hid_a7() (machine_arch_type == MACH_TYPE_HID_A7) -#else -# define machine_is_hid_a7() (0) -#endif - -#ifdef CONFIG_MACH_HERO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERO -# endif -# define machine_is_hero() (machine_arch_type == MACH_TYPE_HERO) -#else -# define machine_is_hero() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_POSEIDON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_POSEIDON -# endif -# define machine_is_omap_poseidon() (machine_arch_type == MACH_TYPE_OMAP_POSEIDON) -#else -# define machine_is_omap_poseidon() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PBX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PBX -# endif -# define machine_is_realview_pbx() (machine_arch_type == MACH_TYPE_REALVIEW_PBX) -#else -# define machine_is_realview_pbx() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9S -# endif -# define machine_is_micro9s() (machine_arch_type == MACH_TYPE_MICRO9S) -#else -# define machine_is_micro9s() (0) -#endif - -#ifdef CONFIG_MACH_MAKO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAKO -# endif -# define machine_is_mako() (machine_arch_type == MACH_TYPE_MAKO) -#else -# define machine_is_mako() (0) -#endif - -#ifdef CONFIG_MACH_XDAFLAME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XDAFLAME -# endif -# define machine_is_xdaflame() (machine_arch_type == MACH_TYPE_XDAFLAME) -#else -# define machine_is_xdaflame() (0) -#endif - -#ifdef CONFIG_MACH_PHIDGET_SBC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHIDGET_SBC2 -# endif -# define machine_is_phidget_sbc2() (machine_arch_type == MACH_TYPE_PHIDGET_SBC2) -#else -# define machine_is_phidget_sbc2() (0) -#endif - -#ifdef CONFIG_MACH_LIMESTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LIMESTONE -# endif -# define machine_is_limestone() (machine_arch_type == MACH_TYPE_LIMESTONE) -#else -# define machine_is_limestone() (0) -#endif - -#ifdef CONFIG_MACH_IPROBE_C32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPROBE_C32 -# endif -# define machine_is_iprobe_c32() (machine_arch_type == MACH_TYPE_IPROBE_C32) -#else -# define machine_is_iprobe_c32() (0) -#endif - -#ifdef CONFIG_MACH_RUT100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RUT100 -# endif -# define machine_is_rut100() (machine_arch_type == MACH_TYPE_RUT100) -#else -# define machine_is_rut100() (0) -#endif - -#ifdef CONFIG_MACH_ASUSP535 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASUSP535 -# endif -# define machine_is_asusp535() (machine_arch_type == MACH_TYPE_ASUSP535) -#else -# define machine_is_asusp535() (0) -#endif - -#ifdef CONFIG_MACH_HTCRAPHAEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCRAPHAEL -# endif -# define machine_is_htcraphael() (machine_arch_type == MACH_TYPE_HTCRAPHAEL) -#else -# define machine_is_htcraphael() (0) -#endif - -#ifdef CONFIG_MACH_SYGDG1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYGDG1 -# endif -# define machine_is_sygdg1() (machine_arch_type == MACH_TYPE_SYGDG1) -#else -# define machine_is_sygdg1() (0) -#endif - -#ifdef CONFIG_MACH_SYGDG2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYGDG2 -# endif -# define machine_is_sygdg2() (machine_arch_type == MACH_TYPE_SYGDG2) -#else -# define machine_is_sygdg2() (0) -#endif - -#ifdef CONFIG_MACH_SEOUL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SEOUL -# endif -# define machine_is_seoul() (machine_arch_type == MACH_TYPE_SEOUL) -#else -# define machine_is_seoul() (0) -#endif - -#ifdef CONFIG_MACH_SALERNO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SALERNO -# endif -# define machine_is_salerno() (machine_arch_type == MACH_TYPE_SALERNO) -#else -# define machine_is_salerno() (0) -#endif - -#ifdef CONFIG_MACH_UCN_S3C64XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UCN_S3C64XX -# endif -# define machine_is_ucn_s3c64xx() (machine_arch_type == MACH_TYPE_UCN_S3C64XX) -#else -# define machine_is_ucn_s3c64xx() (0) -#endif - -#ifdef CONFIG_MACH_MSM7201A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7201A -# endif -# define machine_is_msm7201a() (machine_arch_type == MACH_TYPE_MSM7201A) -#else -# define machine_is_msm7201a() (0) -#endif - -#ifdef CONFIG_MACH_LPR1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPR1 -# endif -# define machine_is_lpr1() (machine_arch_type == MACH_TYPE_LPR1) -#else -# define machine_is_lpr1() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO500FX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO500FX -# endif -# define machine_is_armadillo500fx() (machine_arch_type == MACH_TYPE_ARMADILLO500FX) -#else -# define machine_is_armadillo500fx() (0) -#endif - -#ifdef CONFIG_MACH_G3EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G3EVM -# endif -# define machine_is_g3evm() (machine_arch_type == MACH_TYPE_G3EVM) -#else -# define machine_is_g3evm() (0) -#endif - -#ifdef CONFIG_MACH_Z3_DM355 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_Z3_DM355 -# endif -# define machine_is_z3_dm355() (machine_arch_type == MACH_TYPE_Z3_DM355) -#else -# define machine_is_z3_dm355() (0) -#endif - -#ifdef CONFIG_MACH_W90P910EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90P910EVB -# endif -# define machine_is_w90p910evb() (machine_arch_type == MACH_TYPE_W90P910EVB) -#else -# define machine_is_w90p910evb() (0) -#endif - -#ifdef CONFIG_MACH_W90P920EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90P920EVB -# endif -# define machine_is_w90p920evb() (machine_arch_type == MACH_TYPE_W90P920EVB) -#else -# define machine_is_w90p920evb() (0) -#endif - -#ifdef CONFIG_MACH_W90P950EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90P950EVB -# endif -# define machine_is_w90p950evb() (machine_arch_type == MACH_TYPE_W90P950EVB) -#else -# define machine_is_w90p950evb() (0) -#endif - -#ifdef CONFIG_MACH_W90N960EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90N960EVB -# endif -# define machine_is_w90n960evb() (machine_arch_type == MACH_TYPE_W90N960EVB) -#else -# define machine_is_w90n960evb() (0) -#endif - -#ifdef CONFIG_MACH_CAMHD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAMHD -# endif -# define machine_is_camhd() (machine_arch_type == MACH_TYPE_CAMHD) -#else -# define machine_is_camhd() (0) -#endif - -#ifdef CONFIG_MACH_MVC100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MVC100 -# endif -# define machine_is_mvc100() (machine_arch_type == MACH_TYPE_MVC100) -#else -# define machine_is_mvc100() (0) -#endif - -#ifdef CONFIG_MACH_ELECTRUM_200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELECTRUM_200 -# endif -# define machine_is_electrum_200() (machine_arch_type == MACH_TYPE_ELECTRUM_200) -#else -# define machine_is_electrum_200() (0) -#endif - -#ifdef CONFIG_MACH_HTCJADE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCJADE -# endif -# define machine_is_htcjade() (machine_arch_type == MACH_TYPE_HTCJADE) -#else -# define machine_is_htcjade() (0) -#endif - -#ifdef CONFIG_MACH_MEMPHIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEMPHIS -# endif -# define machine_is_memphis() (machine_arch_type == MACH_TYPE_MEMPHIS) -#else -# define machine_is_memphis() (0) -#endif - -#ifdef CONFIG_MACH_IMX27SBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27SBC -# endif -# define machine_is_imx27sbc() (machine_arch_type == MACH_TYPE_IMX27SBC) -#else -# define machine_is_imx27sbc() (0) -#endif - -#ifdef CONFIG_MACH_LEXTAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEXTAR -# endif -# define machine_is_lextar() (machine_arch_type == MACH_TYPE_LEXTAR) -#else -# define machine_is_lextar() (0) -#endif - -#ifdef CONFIG_MACH_MV88F6281GTW_GE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV88F6281GTW_GE -# endif -# define machine_is_mv88f6281gtw_ge() (machine_arch_type == MACH_TYPE_MV88F6281GTW_GE) -#else -# define machine_is_mv88f6281gtw_ge() (0) -#endif - -#ifdef CONFIG_MACH_NCP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NCP -# endif -# define machine_is_ncp() (machine_arch_type == MACH_TYPE_NCP) -#else -# define machine_is_ncp() (0) -#endif - -#ifdef CONFIG_MACH_Z32AN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_Z32AN -# endif -# define machine_is_z32an_series() (machine_arch_type == MACH_TYPE_Z32AN) -#else -# define machine_is_z32an_series() (0) -#endif - -#ifdef CONFIG_MACH_TMQ_CAPD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TMQ_CAPD -# endif -# define machine_is_tmq_capd() (machine_arch_type == MACH_TYPE_TMQ_CAPD) -#else -# define machine_is_tmq_capd() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_WL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_WL -# endif -# define machine_is_omap3_wl() (machine_arch_type == MACH_TYPE_OMAP3_WL) -#else -# define machine_is_omap3_wl() (0) -#endif - -#ifdef CONFIG_MACH_CHUMBY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHUMBY -# endif -# define machine_is_chumby() (machine_arch_type == MACH_TYPE_CHUMBY) -#else -# define machine_is_chumby() (0) -#endif - -#ifdef CONFIG_MACH_ATSARM9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATSARM9 -# endif -# define machine_is_atsarm9() (machine_arch_type == MACH_TYPE_ATSARM9) -#else -# define machine_is_atsarm9() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM365_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM365_EVM -# endif -# define machine_is_davinci_dm365_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_EVM) -#else -# define machine_is_davinci_dm365_evm() (0) -#endif - -#ifdef CONFIG_MACH_BAHAMAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BAHAMAS -# endif -# define machine_is_bahamas() (machine_arch_type == MACH_TYPE_BAHAMAS) -#else -# define machine_is_bahamas() (0) -#endif - -#ifdef CONFIG_MACH_DAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAS -# endif -# define machine_is_das() (machine_arch_type == MACH_TYPE_DAS) -#else -# define machine_is_das() (0) -#endif - -#ifdef CONFIG_MACH_MINIDAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINIDAS -# endif -# define machine_is_minidas() (machine_arch_type == MACH_TYPE_MINIDAS) -#else -# define machine_is_minidas() (0) -#endif - -#ifdef CONFIG_MACH_VK1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VK1000 -# endif -# define machine_is_vk1000() (machine_arch_type == MACH_TYPE_VK1000) -#else -# define machine_is_vk1000() (0) -#endif - -#ifdef CONFIG_MACH_CENTRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CENTRO -# endif -# define machine_is_centro() (machine_arch_type == MACH_TYPE_CENTRO) -#else -# define machine_is_centro() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_2BAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_2BAY -# endif -# define machine_is_ctera_2bay() (machine_arch_type == MACH_TYPE_CTERA_2BAY) -#else -# define machine_is_ctera_2bay() (0) -#endif - -#ifdef CONFIG_MACH_EDGECONNECT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDGECONNECT -# endif -# define machine_is_edgeconnect() (machine_arch_type == MACH_TYPE_EDGECONNECT) -#else -# define machine_is_edgeconnect() (0) -#endif - -#ifdef CONFIG_MACH_ND27000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ND27000 -# endif -# define machine_is_nd27000() (machine_arch_type == MACH_TYPE_ND27000) -#else -# define machine_is_nd27000() (0) -#endif - -#ifdef CONFIG_MACH_GEMALTO_COBRA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEMALTO_COBRA -# endif -# define machine_is_cobra() (machine_arch_type == MACH_TYPE_GEMALTO_COBRA) -#else -# define machine_is_cobra() (0) -#endif - -#ifdef CONFIG_MACH_INGELABS_COMET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INGELABS_COMET -# endif -# define machine_is_ingelabs_comet() (machine_arch_type == MACH_TYPE_INGELABS_COMET) -#else -# define machine_is_ingelabs_comet() (0) -#endif - -#ifdef CONFIG_MACH_POLLUX_WIZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POLLUX_WIZ -# endif -# define machine_is_pollux_wiz() (machine_arch_type == MACH_TYPE_POLLUX_WIZ) -#else -# define machine_is_pollux_wiz() (0) -#endif - -#ifdef CONFIG_MACH_BLACKSTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLACKSTONE -# endif -# define machine_is_blackstone() (machine_arch_type == MACH_TYPE_BLACKSTONE) -#else -# define machine_is_blackstone() (0) -#endif - -#ifdef CONFIG_MACH_TOPAZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOPAZ -# endif -# define machine_is_topaz() (machine_arch_type == MACH_TYPE_TOPAZ) -#else -# define machine_is_topaz() (0) -#endif - -#ifdef CONFIG_MACH_AIXLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AIXLE -# endif -# define machine_is_aixle() (machine_arch_type == MACH_TYPE_AIXLE) -#else -# define machine_is_aixle() (0) -#endif - -#ifdef CONFIG_MACH_MW998 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MW998 -# endif -# define machine_is_mw998() (machine_arch_type == MACH_TYPE_MW998) -#else -# define machine_is_mw998() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_RX51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_RX51 -# endif -# define machine_is_nokia_rx51() (machine_arch_type == MACH_TYPE_NOKIA_RX51) -#else -# define machine_is_nokia_rx51() (0) -#endif - -#ifdef CONFIG_MACH_VSC5605EV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VSC5605EV -# endif -# define machine_is_vsc5605ev() (machine_arch_type == MACH_TYPE_VSC5605EV) -#else -# define machine_is_vsc5605ev() (0) -#endif - -#ifdef CONFIG_MACH_NT98700DK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NT98700DK -# endif -# define machine_is_nt98700dk() (machine_arch_type == MACH_TYPE_NT98700DK) -#else -# define machine_is_nt98700dk() (0) -#endif - -#ifdef CONFIG_MACH_ICONTACT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICONTACT -# endif -# define machine_is_icontact() (machine_arch_type == MACH_TYPE_ICONTACT) -#else -# define machine_is_icontact() (0) -#endif - -#ifdef CONFIG_MACH_SWARCO_FRCPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCO_FRCPU -# endif -# define machine_is_swarco_frcpu() (machine_arch_type == MACH_TYPE_SWARCO_FRCPU) -#else -# define machine_is_swarco_frcpu() (0) -#endif - -#ifdef CONFIG_MACH_SWARCO_SCPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCO_SCPU -# endif -# define machine_is_swarco_scpu() (machine_arch_type == MACH_TYPE_SWARCO_SCPU) -#else -# define machine_is_swarco_scpu() (0) -#endif - -#ifdef CONFIG_MACH_BBOX_P16 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BBOX_P16 -# endif -# define machine_is_bbox_p16() (machine_arch_type == MACH_TYPE_BBOX_P16) -#else -# define machine_is_bbox_p16() (0) -#endif - -#ifdef CONFIG_MACH_BSTD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BSTD -# endif -# define machine_is_bstd() (machine_arch_type == MACH_TYPE_BSTD) -#else -# define machine_is_bstd() (0) -#endif - -#ifdef CONFIG_MACH_SBC2440II -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC2440II -# endif -# define machine_is_sbc2440ii() (machine_arch_type == MACH_TYPE_SBC2440II) -#else -# define machine_is_sbc2440ii() (0) -#endif - -#ifdef CONFIG_MACH_PCM034 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM034 -# endif -# define machine_is_pcm034() (machine_arch_type == MACH_TYPE_PCM034) -#else -# define machine_is_pcm034() (0) -#endif - -#ifdef CONFIG_MACH_NESO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NESO -# endif -# define machine_is_neso() (machine_arch_type == MACH_TYPE_NESO) -#else -# define machine_is_neso() (0) -#endif - -#ifdef CONFIG_MACH_WLNX_9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WLNX_9G20 -# endif -# define machine_is_wlnx_9g20() (machine_arch_type == MACH_TYPE_WLNX_9G20) -#else -# define machine_is_wlnx_9g20() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_ZOOM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_ZOOM2 -# endif -# define machine_is_omap_zoom2() (machine_arch_type == MACH_TYPE_OMAP_ZOOM2) -#else -# define machine_is_omap_zoom2() (0) -#endif - -#ifdef CONFIG_MACH_TOTEMNOVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOTEMNOVA -# endif -# define machine_is_totemnova() (machine_arch_type == MACH_TYPE_TOTEMNOVA) -#else -# define machine_is_totemnova() (0) -#endif - -#ifdef CONFIG_MACH_C5000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_C5000 -# endif -# define machine_is_c5000() (machine_arch_type == MACH_TYPE_C5000) -#else -# define machine_is_c5000() (0) -#endif - -#ifdef CONFIG_MACH_UNIPO_AT91SAM9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNIPO_AT91SAM9263 -# endif -# define machine_is_unipo_at91sam9263() (machine_arch_type == MACH_TYPE_UNIPO_AT91SAM9263) -#else -# define machine_is_unipo_at91sam9263() (0) -#endif - -#ifdef CONFIG_MACH_ETHERNUT5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETHERNUT5 -# endif -# define machine_is_ethernut5() (machine_arch_type == MACH_TYPE_ETHERNUT5) -#else -# define machine_is_ethernut5() (0) -#endif - -#ifdef CONFIG_MACH_ARM11 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM11 -# endif -# define machine_is_arm11() (machine_arch_type == MACH_TYPE_ARM11) -#else -# define machine_is_arm11() (0) -#endif - -#ifdef CONFIG_MACH_CPUAT9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUAT9260 -# endif -# define machine_is_cpuat9260() (machine_arch_type == MACH_TYPE_CPUAT9260) -#else -# define machine_is_cpuat9260() (0) -#endif - -#ifdef CONFIG_MACH_CPUPXA255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUPXA255 -# endif -# define machine_is_cpupxa255() (machine_arch_type == MACH_TYPE_CPUPXA255) -#else -# define machine_is_cpupxa255() (0) -#endif - -#ifdef CONFIG_MACH_CPUIMX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUIMX27 -# endif -# define machine_is_cpuimx27() (machine_arch_type == MACH_TYPE_CPUIMX27) -#else -# define machine_is_cpuimx27() (0) -#endif - -#ifdef CONFIG_MACH_CHEFLUX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHEFLUX -# endif -# define machine_is_cheflux() (machine_arch_type == MACH_TYPE_CHEFLUX) -#else -# define machine_is_cheflux() (0) -#endif - -#ifdef CONFIG_MACH_EB_CPUX9K2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EB_CPUX9K2 -# endif -# define machine_is_eb_cpux9k2() (machine_arch_type == MACH_TYPE_EB_CPUX9K2) -#else -# define machine_is_eb_cpux9k2() (0) -#endif - -#ifdef CONFIG_MACH_OPCOTEC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPCOTEC -# endif -# define machine_is_opcotec() (machine_arch_type == MACH_TYPE_OPCOTEC) -#else -# define machine_is_opcotec() (0) -#endif - -#ifdef CONFIG_MACH_YT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YT -# endif -# define machine_is_yt() (machine_arch_type == MACH_TYPE_YT) -#else -# define machine_is_yt() (0) -#endif - -#ifdef CONFIG_MACH_MOTOQ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOQ -# endif -# define machine_is_motoq() (machine_arch_type == MACH_TYPE_MOTOQ) -#else -# define machine_is_motoq() (0) -#endif - -#ifdef CONFIG_MACH_BSB1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BSB1 -# endif -# define machine_is_bsb1() (machine_arch_type == MACH_TYPE_BSB1) -#else -# define machine_is_bsb1() (0) -#endif - -#ifdef CONFIG_MACH_ACS5K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACS5K -# endif -# define machine_is_acs5k() (machine_arch_type == MACH_TYPE_ACS5K) -#else -# define machine_is_acs5k() (0) -#endif - -#ifdef CONFIG_MACH_MILAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MILAN -# endif -# define machine_is_milan() (machine_arch_type == MACH_TYPE_MILAN) -#else -# define machine_is_milan() (0) -#endif - -#ifdef CONFIG_MACH_QUARTZV2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUARTZV2 -# endif -# define machine_is_quartzv2() (machine_arch_type == MACH_TYPE_QUARTZV2) -#else -# define machine_is_quartzv2() (0) -#endif - -#ifdef CONFIG_MACH_RSVP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RSVP -# endif -# define machine_is_rsvp() (machine_arch_type == MACH_TYPE_RSVP) -#else -# define machine_is_rsvp() (0) -#endif - -#ifdef CONFIG_MACH_RMP200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RMP200 -# endif -# define machine_is_rmp200() (machine_arch_type == MACH_TYPE_RMP200) -#else -# define machine_is_rmp200() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPER_9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPER_9260 -# endif -# define machine_is_snapper_9260() (machine_arch_type == MACH_TYPE_SNAPPER_9260) -#else -# define machine_is_snapper_9260() (0) -#endif - -#ifdef CONFIG_MACH_DSM320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSM320 -# endif -# define machine_is_dsm320() (machine_arch_type == MACH_TYPE_DSM320) -#else -# define machine_is_dsm320() (0) -#endif - -#ifdef CONFIG_MACH_ADSGCM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSGCM -# endif -# define machine_is_adsgcm() (machine_arch_type == MACH_TYPE_ADSGCM) -#else -# define machine_is_adsgcm() (0) -#endif - -#ifdef CONFIG_MACH_ASE2_400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASE2_400 -# endif -# define machine_is_ase2_400() (machine_arch_type == MACH_TYPE_ASE2_400) -#else -# define machine_is_ase2_400() (0) -#endif - -#ifdef CONFIG_MACH_PIZZA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PIZZA -# endif -# define machine_is_pizza() (machine_arch_type == MACH_TYPE_PIZZA) -#else -# define machine_is_pizza() (0) -#endif - -#ifdef CONFIG_MACH_SPOT_NGPL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPOT_NGPL -# endif -# define machine_is_spot_ngpl() (machine_arch_type == MACH_TYPE_SPOT_NGPL) -#else -# define machine_is_spot_ngpl() (0) -#endif - -#ifdef CONFIG_MACH_ARMATA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMATA -# endif -# define machine_is_armata() (machine_arch_type == MACH_TYPE_ARMATA) -#else -# define machine_is_armata() (0) -#endif - -#ifdef CONFIG_MACH_EXEDA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXEDA -# endif -# define machine_is_exeda() (machine_arch_type == MACH_TYPE_EXEDA) -#else -# define machine_is_exeda() (0) -#endif - -#ifdef CONFIG_MACH_MX31SF005 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31SF005 -# endif -# define machine_is_mx31sf005() (machine_arch_type == MACH_TYPE_MX31SF005) -#else -# define machine_is_mx31sf005() (0) -#endif - -#ifdef CONFIG_MACH_F5D8231_4_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_F5D8231_4_V2 -# endif -# define machine_is_f5d8231_4_v2() (machine_arch_type == MACH_TYPE_F5D8231_4_V2) -#else -# define machine_is_f5d8231_4_v2() (0) -#endif - -#ifdef CONFIG_MACH_Q2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_Q2440 -# endif -# define machine_is_q2440() (machine_arch_type == MACH_TYPE_Q2440) -#else -# define machine_is_q2440() (0) -#endif - -#ifdef CONFIG_MACH_QQ2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QQ2440 -# endif -# define machine_is_qq2440() (machine_arch_type == MACH_TYPE_QQ2440) -#else -# define machine_is_qq2440() (0) -#endif - -#ifdef CONFIG_MACH_MINI2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINI2440 -# endif -# define machine_is_mini2440() (machine_arch_type == MACH_TYPE_MINI2440) -#else -# define machine_is_mini2440() (0) -#endif - -#ifdef CONFIG_MACH_COLIBRI300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLIBRI300 -# endif -# define machine_is_colibri300() (machine_arch_type == MACH_TYPE_COLIBRI300) -#else -# define machine_is_colibri300() (0) -#endif - -#ifdef CONFIG_MACH_JADES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JADES -# endif -# define machine_is_jades() (machine_arch_type == MACH_TYPE_JADES) -#else -# define machine_is_jades() (0) -#endif - -#ifdef CONFIG_MACH_SPARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPARK -# endif -# define machine_is_spark() (machine_arch_type == MACH_TYPE_SPARK) -#else -# define machine_is_spark() (0) -#endif - -#ifdef CONFIG_MACH_BENZINA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BENZINA -# endif -# define machine_is_benzina() (machine_arch_type == MACH_TYPE_BENZINA) -#else -# define machine_is_benzina() (0) -#endif - -#ifdef CONFIG_MACH_BLAZE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLAZE -# endif -# define machine_is_blaze() (machine_arch_type == MACH_TYPE_BLAZE) -#else -# define machine_is_blaze() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_LS_HGL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_LS_HGL -# endif -# define machine_is_linkstation_ls_hgl() (machine_arch_type == MACH_TYPE_LINKSTATION_LS_HGL) -#else -# define machine_is_linkstation_ls_hgl() (0) -#endif - -#ifdef CONFIG_MACH_HTCVENUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCVENUS -# endif -# define machine_is_htckovsky() (machine_arch_type == MACH_TYPE_HTCVENUS) -#else -# define machine_is_htckovsky() (0) -#endif - -#ifdef CONFIG_MACH_SONY_PRS505 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SONY_PRS505 -# endif -# define machine_is_sony_prs505() (machine_arch_type == MACH_TYPE_SONY_PRS505) -#else -# define machine_is_sony_prs505() (0) -#endif - -#ifdef CONFIG_MACH_HANLIN_V3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HANLIN_V3 -# endif -# define machine_is_hanlin_v3() (machine_arch_type == MACH_TYPE_HANLIN_V3) -#else -# define machine_is_hanlin_v3() (0) -#endif - -#ifdef CONFIG_MACH_SAPPHIRA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAPPHIRA -# endif -# define machine_is_sapphira() (machine_arch_type == MACH_TYPE_SAPPHIRA) -#else -# define machine_is_sapphira() (0) -#endif - -#ifdef CONFIG_MACH_DACK_SDA_01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DACK_SDA_01 -# endif -# define machine_is_dack_sda_01() (machine_arch_type == MACH_TYPE_DACK_SDA_01) -#else -# define machine_is_dack_sda_01() (0) -#endif - -#ifdef CONFIG_MACH_ARMBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMBOX -# endif -# define machine_is_armbox() (machine_arch_type == MACH_TYPE_ARMBOX) -#else -# define machine_is_armbox() (0) -#endif - -#ifdef CONFIG_MACH_HARRIS_RVP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HARRIS_RVP -# endif -# define machine_is_harris_rvp() (machine_arch_type == MACH_TYPE_HARRIS_RVP) -#else -# define machine_is_harris_rvp() (0) -#endif - -#ifdef CONFIG_MACH_RIBALDO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIBALDO -# endif -# define machine_is_ribaldo() (machine_arch_type == MACH_TYPE_RIBALDO) -#else -# define machine_is_ribaldo() (0) -#endif - -#ifdef CONFIG_MACH_AGORA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AGORA -# endif -# define machine_is_agora() (machine_arch_type == MACH_TYPE_AGORA) -#else -# define machine_is_agora() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_MINI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_MINI -# endif -# define machine_is_omap3_mini() (machine_arch_type == MACH_TYPE_OMAP3_MINI) -#else -# define machine_is_omap3_mini() (0) -#endif - -#ifdef CONFIG_MACH_A9SAM6432_B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9SAM6432_B -# endif -# define machine_is_a9sam6432_b() (machine_arch_type == MACH_TYPE_A9SAM6432_B) -#else -# define machine_is_a9sam6432_b() (0) -#endif - -#ifdef CONFIG_MACH_USG2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USG2410 -# endif -# define machine_is_usg2410() (machine_arch_type == MACH_TYPE_USG2410) -#else -# define machine_is_usg2410() (0) -#endif - -#ifdef CONFIG_MACH_PC72052_I10_REVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PC72052_I10_REVB -# endif -# define machine_is_pc72052_i10_revb() (machine_arch_type == MACH_TYPE_PC72052_I10_REVB) -#else -# define machine_is_pc72052_i10_revb() (0) -#endif - -#ifdef CONFIG_MACH_MX35_EXM32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX35_EXM32 -# endif -# define machine_is_mx35_exm32() (machine_arch_type == MACH_TYPE_MX35_EXM32) -#else -# define machine_is_mx35_exm32() (0) -#endif - -#ifdef CONFIG_MACH_TOPAS910 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOPAS910 -# endif -# define machine_is_topas910() (machine_arch_type == MACH_TYPE_TOPAS910) -#else -# define machine_is_topas910() (0) -#endif - -#ifdef CONFIG_MACH_HYENA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HYENA -# endif -# define machine_is_hyena() (machine_arch_type == MACH_TYPE_HYENA) -#else -# define machine_is_hyena() (0) -#endif - -#ifdef CONFIG_MACH_POSPAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POSPAX -# endif -# define machine_is_pospax() (machine_arch_type == MACH_TYPE_POSPAX) -#else -# define machine_is_pospax() (0) -#endif - -#ifdef CONFIG_MACH_HDL_GX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDL_GX -# endif -# define machine_is_hdl_gx() (machine_arch_type == MACH_TYPE_HDL_GX) -#else -# define machine_is_hdl_gx() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_4BAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_4BAY -# endif -# define machine_is_ctera_4bay() (machine_arch_type == MACH_TYPE_CTERA_4BAY) -#else -# define machine_is_ctera_4bay() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_PLUG_C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_PLUG_C -# endif -# define machine_is_ctera_plug_c() (machine_arch_type == MACH_TYPE_CTERA_PLUG_C) -#else -# define machine_is_ctera_plug_c() (0) -#endif - -#ifdef CONFIG_MACH_CRWEA_PLUG_I -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CRWEA_PLUG_I -# endif -# define machine_is_crwea_plug_i() (machine_arch_type == MACH_TYPE_CRWEA_PLUG_I) -#else -# define machine_is_crwea_plug_i() (0) -#endif - -#ifdef CONFIG_MACH_EGAUGE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EGAUGE2 -# endif -# define machine_is_egauge2() (machine_arch_type == MACH_TYPE_EGAUGE2) -#else -# define machine_is_egauge2() (0) -#endif - -#ifdef CONFIG_MACH_DIDJ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIDJ -# endif -# define machine_is_didj() (machine_arch_type == MACH_TYPE_DIDJ) -#else -# define machine_is_didj() (0) -#endif - -#ifdef CONFIG_MACH_MEISTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEISTER -# endif -# define machine_is_meister() (machine_arch_type == MACH_TYPE_MEISTER) -#else -# define machine_is_meister() (0) -#endif - -#ifdef CONFIG_MACH_HTCBLACKSTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCBLACKSTONE -# endif -# define machine_is_htcblackstone() (machine_arch_type == MACH_TYPE_HTCBLACKSTONE) -#else -# define machine_is_htcblackstone() (0) -#endif - -#ifdef CONFIG_MACH_CPUAT9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUAT9G20 -# endif -# define machine_is_cpuat9g20() (machine_arch_type == MACH_TYPE_CPUAT9G20) -#else -# define machine_is_cpuat9g20() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6440 -# endif -# define machine_is_smdk6440() (machine_arch_type == MACH_TYPE_SMDK6440) -#else -# define machine_is_smdk6440() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_35XX_MVP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_35XX_MVP -# endif -# define machine_is_omap_35xx_mvp() (machine_arch_type == MACH_TYPE_OMAP_35XX_MVP) -#else -# define machine_is_omap_35xx_mvp() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_PLUG_I -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_PLUG_I -# endif -# define machine_is_ctera_plug_i() (machine_arch_type == MACH_TYPE_CTERA_PLUG_I) -#else -# define machine_is_ctera_plug_i() (0) -#endif - -#ifdef CONFIG_MACH_PVG610 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PVG610 -# endif -# define machine_is_pvg610_100() (machine_arch_type == MACH_TYPE_PVG610) -#else -# define machine_is_pvg610_100() (0) -#endif - -#ifdef CONFIG_MACH_HPRW6815 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HPRW6815 -# endif -# define machine_is_hprw6815() (machine_arch_type == MACH_TYPE_HPRW6815) -#else -# define machine_is_hprw6815() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_OSWALD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_OSWALD -# endif -# define machine_is_omap3_oswald() (machine_arch_type == MACH_TYPE_OMAP3_OSWALD) -#else -# define machine_is_omap3_oswald() (0) -#endif - -#ifdef CONFIG_MACH_NAS4220B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAS4220B -# endif -# define machine_is_nas4220b() (machine_arch_type == MACH_TYPE_NAS4220B) -#else -# define machine_is_nas4220b() (0) -#endif - -#ifdef CONFIG_MACH_HTCRAPHAEL_CDMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCRAPHAEL_CDMA -# endif -# define machine_is_htcraphael_cdma() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_CDMA) -#else -# define machine_is_htcraphael_cdma() (0) -#endif - -#ifdef CONFIG_MACH_HTCDIAMOND_CDMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCDIAMOND_CDMA -# endif -# define machine_is_htcdiamond_cdma() (machine_arch_type == MACH_TYPE_HTCDIAMOND_CDMA) -#else -# define machine_is_htcdiamond_cdma() (0) -#endif - -#ifdef CONFIG_MACH_SCALER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCALER -# endif -# define machine_is_scaler() (machine_arch_type == MACH_TYPE_SCALER) -#else -# define machine_is_scaler() (0) -#endif - -#ifdef CONFIG_MACH_ZYLONITE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZYLONITE2 -# endif -# define machine_is_zylonite2() (machine_arch_type == MACH_TYPE_ZYLONITE2) -#else -# define machine_is_zylonite2() (0) -#endif - -#ifdef CONFIG_MACH_ASPENITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASPENITE -# endif -# define machine_is_aspenite() (machine_arch_type == MACH_TYPE_ASPENITE) -#else -# define machine_is_aspenite() (0) -#endif - -#ifdef CONFIG_MACH_TETON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TETON -# endif -# define machine_is_teton() (machine_arch_type == MACH_TYPE_TETON) -#else -# define machine_is_teton() (0) -#endif - -#ifdef CONFIG_MACH_TTC_DKB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TTC_DKB -# endif -# define machine_is_ttc_dkb() (machine_arch_type == MACH_TYPE_TTC_DKB) -#else -# define machine_is_ttc_dkb() (0) -#endif - -#ifdef CONFIG_MACH_BISHOP2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BISHOP2 -# endif -# define machine_is_bishop2() (machine_arch_type == MACH_TYPE_BISHOP2) -#else -# define machine_is_bishop2() (0) -#endif - -#ifdef CONFIG_MACH_IPPV5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPPV5 -# endif -# define machine_is_ippv5() (machine_arch_type == MACH_TYPE_IPPV5) -#else -# define machine_is_ippv5() (0) -#endif - -#ifdef CONFIG_MACH_FARM926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FARM926 -# endif -# define machine_is_farm926() (machine_arch_type == MACH_TYPE_FARM926) -#else -# define machine_is_farm926() (0) -#endif - -#ifdef CONFIG_MACH_MMCCPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMCCPU -# endif -# define machine_is_mmccpu() (machine_arch_type == MACH_TYPE_MMCCPU) -#else -# define machine_is_mmccpu() (0) -#endif - -#ifdef CONFIG_MACH_SGMSFL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SGMSFL -# endif -# define machine_is_sgmsfl() (machine_arch_type == MACH_TYPE_SGMSFL) -#else -# define machine_is_sgmsfl() (0) -#endif - -#ifdef CONFIG_MACH_TT8000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TT8000 -# endif -# define machine_is_tt8000() (machine_arch_type == MACH_TYPE_TT8000) -#else -# define machine_is_tt8000() (0) -#endif - -#ifdef CONFIG_MACH_ZRN4300LP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZRN4300LP -# endif -# define machine_is_zrn4300lp() (machine_arch_type == MACH_TYPE_ZRN4300LP) -#else -# define machine_is_zrn4300lp() (0) -#endif - -#ifdef CONFIG_MACH_MPTC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPTC -# endif -# define machine_is_mptc() (machine_arch_type == MACH_TYPE_MPTC) -#else -# define machine_is_mptc() (0) -#endif - -#ifdef CONFIG_MACH_H6051 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6051 -# endif -# define machine_is_h6051() (machine_arch_type == MACH_TYPE_H6051) -#else -# define machine_is_h6051() (0) -#endif - -#ifdef CONFIG_MACH_PVG610_101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PVG610_101 -# endif -# define machine_is_pvg610_101() (machine_arch_type == MACH_TYPE_PVG610_101) -#else -# define machine_is_pvg610_101() (0) -#endif - -#ifdef CONFIG_MACH_STAMP9261_PC_EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STAMP9261_PC_EVB -# endif -# define machine_is_stamp9261_pc_evb() (machine_arch_type == MACH_TYPE_STAMP9261_PC_EVB) -#else -# define machine_is_stamp9261_pc_evb() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_ODYSSEUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_ODYSSEUS -# endif -# define machine_is_pelco_odysseus() (machine_arch_type == MACH_TYPE_PELCO_ODYSSEUS) -#else -# define machine_is_pelco_odysseus() (0) -#endif - -#ifdef CONFIG_MACH_TNY_A9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNY_A9260 -# endif -# define machine_is_tny_a9260() (machine_arch_type == MACH_TYPE_TNY_A9260) -#else -# define machine_is_tny_a9260() (0) -#endif - -#ifdef CONFIG_MACH_TNY_A9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNY_A9G20 -# endif -# define machine_is_tny_a9g20() (machine_arch_type == MACH_TYPE_TNY_A9G20) -#else -# define machine_is_tny_a9g20() (0) -#endif - -#ifdef CONFIG_MACH_AESOP_MP2530F -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AESOP_MP2530F -# endif -# define machine_is_aesop_mp2530f() (machine_arch_type == MACH_TYPE_AESOP_MP2530F) -#else -# define machine_is_aesop_mp2530f() (0) -#endif - -#ifdef CONFIG_MACH_DX900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DX900 -# endif -# define machine_is_dx900() (machine_arch_type == MACH_TYPE_DX900) -#else -# define machine_is_dx900() (0) -#endif - -#ifdef CONFIG_MACH_CPODC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPODC2 -# endif -# define machine_is_cpodc2() (machine_arch_type == MACH_TYPE_CPODC2) -#else -# define machine_is_cpodc2() (0) -#endif - -#ifdef CONFIG_MACH_TILT_8925 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TILT_8925 -# endif -# define machine_is_tilt_8925() (machine_arch_type == MACH_TYPE_TILT_8925) -#else -# define machine_is_tilt_8925() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM357_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM357_EVM -# endif -# define machine_is_davinci_dm357_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM357_EVM) -#else -# define machine_is_davinci_dm357_evm() (0) -#endif - -#ifdef CONFIG_MACH_SWORDFISH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWORDFISH -# endif -# define machine_is_swordfish() (machine_arch_type == MACH_TYPE_SWORDFISH) -#else -# define machine_is_swordfish() (0) -#endif - -#ifdef CONFIG_MACH_CORVUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORVUS -# endif -# define machine_is_corvus() (machine_arch_type == MACH_TYPE_CORVUS) -#else -# define machine_is_corvus() (0) -#endif - -#ifdef CONFIG_MACH_TAURUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAURUS -# endif -# define machine_is_taurus() (machine_arch_type == MACH_TYPE_TAURUS) -#else -# define machine_is_taurus() (0) -#endif - -#ifdef CONFIG_MACH_AXM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXM -# endif -# define machine_is_axm() (machine_arch_type == MACH_TYPE_AXM) -#else -# define machine_is_axm() (0) -#endif - -#ifdef CONFIG_MACH_AXC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXC -# endif -# define machine_is_axc() (machine_arch_type == MACH_TYPE_AXC) -#else -# define machine_is_axc() (0) -#endif - -#ifdef CONFIG_MACH_BABY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BABY -# endif -# define machine_is_baby() (machine_arch_type == MACH_TYPE_BABY) -#else -# define machine_is_baby() (0) -#endif - -#ifdef CONFIG_MACH_MP200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MP200 -# endif -# define machine_is_mp200() (machine_arch_type == MACH_TYPE_MP200) -#else -# define machine_is_mp200() (0) -#endif - -#ifdef CONFIG_MACH_PCM043 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM043 -# endif -# define machine_is_pcm043() (machine_arch_type == MACH_TYPE_PCM043) -#else -# define machine_is_pcm043() (0) -#endif - -#ifdef CONFIG_MACH_HANLIN_V3C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HANLIN_V3C -# endif -# define machine_is_hanlin_v3c() (machine_arch_type == MACH_TYPE_HANLIN_V3C) -#else -# define machine_is_hanlin_v3c() (0) -#endif - -#ifdef CONFIG_MACH_KBK9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KBK9G20 -# endif -# define machine_is_kbk9g20() (machine_arch_type == MACH_TYPE_KBK9G20) -#else -# define machine_is_kbk9g20() (0) -#endif - -/* - * These have not yet been registered - */ - -#ifndef machine_arch_type -#define machine_arch_type __machine_arch_type -#endif - -#endif diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h deleted file mode 100644 index f746bc241f..0000000000 --- a/include/asm-arm/memory.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * linux/include/asm-arm/memory.h - * - * Copyright (C) 2000-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Note: this file should not be included by non-asm/.h files - */ -#ifndef __ASM_ARM_MEMORY_H -#define __ASM_ARM_MEMORY_H - - -#endif /* __ASM_ARM_MEMORY_H */ diff --git a/include/asm-arm/mmu.h b/include/asm-arm/mmu.h deleted file mode 100644 index 0dd3fa826c..0000000000 --- a/include/asm-arm/mmu.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef __ASM_MMU_H -#define __ASM_MMU_H - -#include <asm/pgtable.h> -#include <malloc.h> - -#define PMD_SECT_DEF_UNCACHED (PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT) -#define PMD_SECT_DEF_CACHED (PMD_SECT_WB | PMD_SECT_DEF_UNCACHED) - -void mmu_init(void); -void mmu_enable(void); -void mmu_disable(void); -void arm_create_section(unsigned long virt, unsigned long phys, int size_m, - unsigned int flags); - -void setup_dma_coherent(unsigned long offset); - -#ifdef CONFIG_MMU -void *dma_alloc_coherent(size_t size); -void dma_free_coherent(void *mem); - -void dma_clean_range(const void *, const void *); -void dma_flush_range(const void *, const void *); -void dma_inv_range(const void *, const void *); -unsigned long virt_to_phys(void *virt); -void *phys_to_virt(unsigned long phys); - -#else -static inline void *dma_alloc_coherent(size_t size) -{ - return malloc(size); -} - -static inline void dma_free_coherent(void *mem) -{ - free(mem); -} - -static inline void *phys_to_virt(unsigned long phys) -{ - return (void *)phys; -} - -static inline unsigned long virt_to_phys(void *mem) -{ - return (unsigned long)mem; -} - -static inline void dma_clean_range(const void *s, const void *e) -{ -} - -static inline void dma_flush_range(const void *s, const void *e) -{ -} - -static inline void dma_inv_range(const void *s, const void *e) -{ -} - -#endif - -#endif /* __ASM_MMU_H */ - diff --git a/include/asm-arm/module.h b/include/asm-arm/module.h deleted file mode 100644 index 5b4d1a3f36..0000000000 --- a/include/asm-arm/module.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _ASM_ARM_MODULE_H -#define _ASM_ARM_MODULE_H - -struct mod_arch_specific -{ - int foo; -}; - -#define Elf_Shdr Elf32_Shdr -#define Elf_Sym Elf32_Sym -#define Elf_Ehdr Elf32_Ehdr - -#endif /* _ASM_ARM_MODULE_H */ diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h deleted file mode 100644 index fd1521d5cb..0000000000 --- a/include/asm-arm/pgtable.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * arch/arm/include/asm/pgtable-hwdef.h - * - * Copyright (C) 1995-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef _ASMARM_PGTABLE_HWDEF_H -#define _ASMARM_PGTABLE_HWDEF_H - -/* - * Hardware page table definitions. - * - * + Level 1 descriptor (PMD) - * - common - */ -#define PMD_TYPE_MASK (3 << 0) -#define PMD_TYPE_FAULT (0 << 0) -#define PMD_TYPE_TABLE (1 << 0) -#define PMD_TYPE_SECT (2 << 0) -#define PMD_BIT4 (1 << 4) -#define PMD_DOMAIN(x) ((x) << 5) -#define PMD_PROTECTION (1 << 9) /* v5 */ -/* - * - section - */ -#define PMD_SECT_BUFFERABLE (1 << 2) -#define PMD_SECT_CACHEABLE (1 << 3) -#define PMD_SECT_XN (1 << 4) /* v6 */ -#define PMD_SECT_AP_WRITE (1 << 10) -#define PMD_SECT_AP_READ (1 << 11) -#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */ -#define PMD_SECT_APX (1 << 15) /* v6 */ -#define PMD_SECT_S (1 << 16) /* v6 */ -#define PMD_SECT_nG (1 << 17) /* v6 */ -#define PMD_SECT_SUPER (1 << 18) /* v6 */ - -#define PMD_SECT_UNCACHED (0) -#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE) -#define PMD_SECT_WT (PMD_SECT_CACHEABLE) -#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) -#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE) -#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) -#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2)) - -/* - * - coarse table (not used) - */ - -/* - * + Level 2 descriptor (PTE) - * - common - */ -#define PTE_TYPE_MASK (3 << 0) -#define PTE_TYPE_FAULT (0 << 0) -#define PTE_TYPE_LARGE (1 << 0) -#define PTE_TYPE_SMALL (2 << 0) -#define PTE_TYPE_EXT (3 << 0) /* v5 */ -#define PTE_BUFFERABLE (1 << 2) -#define PTE_CACHEABLE (1 << 3) - -/* - * - extended small page/tiny page - */ -#define PTE_EXT_XN (1 << 0) /* v6 */ -#define PTE_EXT_AP_MASK (3 << 4) -#define PTE_EXT_AP0 (1 << 4) -#define PTE_EXT_AP1 (2 << 4) -#define PTE_EXT_AP_UNO_SRO (0 << 4) -#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) -#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) -#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) -#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ -#define PTE_EXT_APX (1 << 9) /* v6 */ -#define PTE_EXT_COHERENT (1 << 9) /* XScale3 */ -#define PTE_EXT_SHARED (1 << 10) /* v6 */ -#define PTE_EXT_NG (1 << 11) /* v6 */ - -/* - * - small page - */ -#define PTE_SMALL_AP_MASK (0xff << 4) -#define PTE_SMALL_AP_UNO_SRO (0x00 << 4) -#define PTE_SMALL_AP_UNO_SRW (0x55 << 4) -#define PTE_SMALL_AP_URO_SRW (0xaa << 4) -#define PTE_SMALL_AP_URW_SRW (0xff << 4) - -#endif diff --git a/include/asm-arm/posix_types.h b/include/asm-arm/posix_types.h deleted file mode 100644 index c412486db5..0000000000 --- a/include/asm-arm/posix_types.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * linux/include/asm-arm/posix_types.h - * - * Copyright (C) 1996-1998 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 27-06-1996 RMK Created - */ -#ifndef __ARCH_ARM_POSIX_TYPES_H -#define __ARCH_ARM_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -#define __FD_SET(fd, fdsetp) \ - (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) - -#undef __FD_CLR -#define __FD_CLR(fd, fdsetp) \ - (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) - -#undef __FD_ISSET -#define __FD_ISSET(fd, fdsetp) \ - ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) \ - (memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp))) - -#endif - -#endif diff --git a/include/asm-arm/proc-armv/ptrace.h b/include/asm-arm/proc-armv/ptrace.h deleted file mode 100644 index a060ee67e3..0000000000 --- a/include/asm-arm/proc-armv/ptrace.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * linux/include/asm-arm/proc-armv/ptrace.h - * - * Copyright (C) 1996-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_PROC_PTRACE_H -#define __ASM_PROC_PTRACE_H - -#define USR26_MODE 0x00 -#define FIQ26_MODE 0x01 -#define IRQ26_MODE 0x02 -#define SVC26_MODE 0x03 -#define USR_MODE 0x10 -#define FIQ_MODE 0x11 -#define IRQ_MODE 0x12 -#define SVC_MODE 0x13 -#define ABT_MODE 0x17 -#define UND_MODE 0x1b -#define SYSTEM_MODE 0x1f -#define MODE_MASK 0x1f -#define T_BIT 0x20 -#define F_BIT 0x40 -#define I_BIT 0x80 -#define CC_V_BIT (1 << 28) -#define CC_C_BIT (1 << 29) -#define CC_Z_BIT (1 << 30) -#define CC_N_BIT (1 << 31) -#define PCMASK 0 - -#ifndef __ASSEMBLY__ - -/* this struct defines the way the registers are stored on the - stack during a system call. */ - -struct pt_regs { - long uregs[18]; -}; - -#define ARM_cpsr uregs[16] -#define ARM_pc uregs[15] -#define ARM_lr uregs[14] -#define ARM_sp uregs[13] -#define ARM_ip uregs[12] -#define ARM_fp uregs[11] -#define ARM_r10 uregs[10] -#define ARM_r9 uregs[9] -#define ARM_r8 uregs[8] -#define ARM_r7 uregs[7] -#define ARM_r6 uregs[6] -#define ARM_r5 uregs[5] -#define ARM_r4 uregs[4] -#define ARM_r3 uregs[3] -#define ARM_r2 uregs[2] -#define ARM_r1 uregs[1] -#define ARM_r0 uregs[0] -#define ARM_ORIG_r0 uregs[17] - -#ifdef __KERNEL__ - -#define user_mode(regs) \ - (((regs)->ARM_cpsr & 0xf) == 0) - -#ifdef CONFIG_ARM_THUMB -#define thumb_mode(regs) \ - (((regs)->ARM_cpsr & T_BIT)) -#else -#define thumb_mode(regs) (0) -#endif - -#define processor_mode(regs) \ - ((regs)->ARM_cpsr & MODE_MASK) - -#define interrupts_enabled(regs) \ - (!((regs)->ARM_cpsr & I_BIT)) - -#define fast_interrupts_enabled(regs) \ - (!((regs)->ARM_cpsr & F_BIT)) - -#define condition_codes(regs) \ - ((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT)) - -/* Are the current registers suitable for user mode? - * (used to maintain security in signal handlers) - */ -static inline int valid_user_regs(struct pt_regs *regs) -{ - if ((regs->ARM_cpsr & 0xf) == 0 && - (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0) - return 1; - - /* - * Force CPSR to something logical... - */ - regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10); - - return 0; -} - -#endif /* __KERNEL__ */ - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h deleted file mode 100644 index d5dbab0ac2..0000000000 --- a/include/asm-arm/processor.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * linux/include/asm-arm/processor.h - * - * Copyright (C) 1995-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARM_PROCESSOR_H -#define __ASM_ARM_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -#define FP_SIZE 35 - -struct fp_hard_struct { - unsigned int save[FP_SIZE]; /* as yet undefined */ -}; - -struct fp_soft_struct { - unsigned int save[FP_SIZE]; /* undefined information */ -}; - -union fp_state { - struct fp_hard_struct hard; - struct fp_soft_struct soft; -}; - -typedef unsigned long mm_segment_t; /* domain register */ - -#ifdef __KERNEL__ - -#define EISA_bus 0 -#define MCA_bus 0 -#define MCA_bus__is_a_macro - -#include <asm/atomic.h> -#include <asm/ptrace.h> -#include <asm/proc/processor.h> -#include <asm/types.h> - -union debug_insn { - u32 arm; - u16 thumb; -}; - -struct debug_entry { - u32 address; - union debug_insn insn; -}; - -struct debug_info { - int nsaved; - struct debug_entry bp[2]; -}; - -struct thread_struct { - atomic_t refcount; - /* fault info */ - unsigned long address; - unsigned long trap_no; - unsigned long error_code; - /* floating point */ - union fp_state fpstate; - /* debugging */ - struct debug_info debug; - /* context info */ - struct context_save_struct *save; - EXTRA_THREAD_STRUCT -}; - -#define INIT_THREAD { \ - refcount: ATOMIC_INIT(1), \ - EXTRA_THREAD_STRUCT_INIT \ -} - -/* - * Return saved PC of a blocked thread. - */ -static inline unsigned long thread_saved_pc(struct thread_struct *t) -{ - return t->save ? pc_pointer(t->save->pc) : 0; -} - -static inline unsigned long thread_saved_fp(struct thread_struct *t) -{ - return t->save ? t->save->fp : 0; -} - -/* Forward declaration, a strange C thing */ -struct task_struct; - -/* Free all resources held by a thread. */ -extern void release_thread(struct task_struct *); - -/* Copy and release all segment info associated with a VM */ -#define copy_segments(tsk, mm) do { } while (0) -#define release_segments(mm) do { } while (0) - -unsigned long get_wchan(struct task_struct *p); - -#define THREAD_SIZE (8192) - -extern struct task_struct *alloc_task_struct(void); -extern void __free_task_struct(struct task_struct *); -#define get_task_struct(p) atomic_inc(&(p)->thread.refcount) -#define free_task_struct(p) \ - do { \ - if (atomic_dec_and_test(&(p)->thread.refcount)) \ - __free_task_struct((p)); \ - } while (0) - -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) - -#define cpu_relax() barrier() - -/* - * Create a new kernel thread - */ -extern int arch_kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); - -#endif - -#endif /* __ASM_ARM_PROCESSOR_H */ diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h deleted file mode 100644 index 73c9087b50..0000000000 --- a/include/asm-arm/ptrace.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __ASM_ARM_PTRACE_H -#define __ASM_ARM_PTRACE_H - -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 - -#define PTRACE_SETOPTIONS 21 - -/* options set using PTRACE_SETOPTIONS */ -#define PTRACE_O_TRACESYSGOOD 0x00000001 - -#include <asm/proc/ptrace.h> - -#ifndef __ASSEMBLY__ -#define pc_pointer(v) \ - ((v) & ~PCMASK) - -#define instruction_pointer(regs) \ - (pc_pointer((regs)->ARM_pc)) - -#ifdef __KERNEL__ -extern void show_regs(struct pt_regs *); - -#define predicate(x) (x & 0xf0000000) -#define PREDICATE_ALWAYS 0xe0000000 - -#endif - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-arm/setup.h b/include/asm-arm/setup.h deleted file mode 100644 index 89df4dc708..0000000000 --- a/include/asm-arm/setup.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * linux/include/asm/setup.h - * - * Copyright (C) 1997-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Structure passed to kernel to tell it about the - * hardware it's running on. See linux/Documentation/arm/Setup - * for more info. - * - * NOTE: - * This file contains two ways to pass information from the boot - * loader to the kernel. The old struct param_struct is deprecated, - * but it will be kept in the kernel for 5 years from now - * (2001). This will allow boot loaders to convert to the new struct - * tag way. - */ -#ifndef __ASMARM_SETUP_H -#define __ASMARM_SETUP_H - -/* - * Usage: - * - do not go blindly adding fields, add them at the end - * - when adding fields, don't rely on the address until - * a patch from me has been released - * - unused fields should be zero (for future expansion) - * - this structure is relatively short-lived - only - * guaranteed to contain useful data in setup_arch() - */ -#define COMMAND_LINE_SIZE 1024 - -/* This is the old deprecated way to pass parameters to the kernel */ -struct param_struct { - union { - struct { - unsigned long page_size; /* 0 */ - unsigned long nr_pages; /* 4 */ - unsigned long ramdisk_size; /* 8 */ - unsigned long flags; /* 12 */ -#define FLAG_READONLY 1 -#define FLAG_RDLOAD 4 -#define FLAG_RDPROMPT 8 - unsigned long rootdev; /* 16 */ - unsigned long video_num_cols; /* 20 */ - unsigned long video_num_rows; /* 24 */ - unsigned long video_x; /* 28 */ - unsigned long video_y; /* 32 */ - unsigned long memc_control_reg; /* 36 */ - unsigned char sounddefault; /* 40 */ - unsigned char adfsdrives; /* 41 */ - unsigned char bytes_per_char_h; /* 42 */ - unsigned char bytes_per_char_v; /* 43 */ - unsigned long pages_in_bank[4]; /* 44 */ - unsigned long pages_in_vram; /* 60 */ - unsigned long initrd_start; /* 64 */ - unsigned long initrd_size; /* 68 */ - unsigned long rd_start; /* 72 */ - unsigned long system_rev; /* 76 */ - unsigned long system_serial_low; /* 80 */ - unsigned long system_serial_high; /* 84 */ - unsigned long mem_fclk_21285; /* 88 */ - } s; - char unused[256]; - } u1; - union { - char paths[8][128]; - struct { - unsigned long magic; - char n[1024 - sizeof(unsigned long)]; - } s; - } u2; - char commandline[COMMAND_LINE_SIZE]; -}; - - -/* - * The new way of passing information: a list of tagged entries - */ - -/* The list ends with an ATAG_NONE node. */ -#define ATAG_NONE 0x00000000 - -struct tag_header { - u32 size; - u32 tag; -}; - -/* The list must start with an ATAG_CORE node */ -#define ATAG_CORE 0x54410001 - -struct tag_core { - u32 flags; /* bit 0 = read-only */ - u32 pagesize; - u32 rootdev; -}; - -/* it is allowed to have multiple ATAG_MEM nodes */ -#define ATAG_MEM 0x54410002 - -struct tag_mem32 { - u32 size; - u32 start; /* physical start address */ -}; - -/* VGA text type displays */ -#define ATAG_VIDEOTEXT 0x54410003 - -struct tag_videotext { - u8 x; - u8 y; - u16 video_page; - u8 video_mode; - u8 video_cols; - u16 video_ega_bx; - u8 video_lines; - u8 video_isvga; - u16 video_points; -}; - -/* describes how the ramdisk will be used in kernel */ -#define ATAG_RAMDISK 0x54410004 - -struct tag_ramdisk { - u32 flags; /* bit 0 = load, bit 1 = prompt */ - u32 size; /* decompressed ramdisk size in _kilo_ bytes */ - u32 start; /* starting block of floppy-based RAM disk image */ -}; - -/* describes where the compressed ramdisk image lives (virtual address) */ -/* - * this one accidentally used virtual addresses - as such, - * its depreciated. - */ -#define ATAG_INITRD 0x54410005 - -/* describes where the compressed ramdisk image lives (physical address) */ -#define ATAG_INITRD2 0x54420005 - -struct tag_initrd { - u32 start; /* physical start address */ - u32 size; /* size of compressed ramdisk image in bytes */ -}; - -/* board serial number. "64 bits should be enough for everybody" */ -#define ATAG_SERIAL 0x54410006 - -struct tag_serialnr { - u32 low; - u32 high; -}; - -/* board revision */ -#define ATAG_REVISION 0x54410007 - -struct tag_revision { - u32 rev; -}; - -/* initial values for vesafb-type framebuffers. see struct screen_info - * in include/linux/tty.h - */ -#define ATAG_VIDEOLFB 0x54410008 - -struct tag_videolfb { - u16 lfb_width; - u16 lfb_height; - u16 lfb_depth; - u16 lfb_linelength; - u32 lfb_base; - u32 lfb_size; - u8 red_size; - u8 red_pos; - u8 green_size; - u8 green_pos; - u8 blue_size; - u8 blue_pos; - u8 rsvd_size; - u8 rsvd_pos; -}; - -/* command line: \0 terminated string */ -#define ATAG_CMDLINE 0x54410009 - -struct tag_cmdline { - char cmdline[1]; /* this is the minimum size */ -}; - -/* acorn RiscPC specific information */ -#define ATAG_ACORN 0x41000101 - -struct tag_acorn { - u32 memc_control_reg; - u32 vram_pages; - u8 sounddefault; - u8 adfsdrives; -}; - -/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ -#define ATAG_MEMCLK 0x41000402 - -struct tag_memclk { - u32 fmemclk; -}; - -struct tag { - struct tag_header hdr; - union { - struct tag_core core; - struct tag_mem32 mem; - struct tag_videotext videotext; - struct tag_ramdisk ramdisk; - struct tag_initrd initrd; - struct tag_serialnr serialnr; - struct tag_revision revision; - struct tag_videolfb videolfb; - struct tag_cmdline cmdline; - - /* - * Acorn specific - */ - struct tag_acorn acorn; - - /* - * DC21285 specific - */ - struct tag_memclk memclk; - } u; -}; - -struct tagtable { - u32 tag; - int (*parse)(const struct tag *); -}; - -#define __tag __attribute__((unused, __section__(".taglist"))) -#define __tagtable(tag, fn) \ -static struct tagtable __tagtable_##fn __tag = { tag, fn } - -#define tag_member_present(tag,member) \ - ((unsigned long)(&((struct tag *)0L)->member + 1) \ - <= (tag)->hdr.size * 4) - -#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) -#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) - -#define for_each_tag(t,base) \ - for (t = base; t->hdr.size; t = tag_next(t)) - -/* - * Memory map description - */ -#define NR_BANKS 8 - -struct meminfo { - int nr_banks; - unsigned long end; - struct { - unsigned long start; - unsigned long size; - int node; - } bank[NR_BANKS]; -}; - -extern struct meminfo meminfo; - -#endif diff --git a/include/asm-arm/string.h b/include/asm-arm/string.h deleted file mode 100644 index 435647abda..0000000000 --- a/include/asm-arm/string.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __ASM_ARM_STRING_H -#define __ASM_ARM_STRING_H - -#ifdef CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS - -#define __HAVE_ARCH_MEMCPY -extern void *memcpy(void *, const void *, __kernel_size_t); -#define __HAVE_ARCH_MEMSET -extern void *memset(void *, int, __kernel_size_t); - -#endif - -#endif diff --git a/include/asm-arm/types.h b/include/asm-arm/types.h deleted file mode 100644 index 81bd357ada..0000000000 --- a/include/asm-arm/types.h +++ /dev/null @@ -1,59 +0,0 @@ -#ifndef __ASM_ARM_TYPES_H -#define __ASM_ARM_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG 32 - -#ifndef __ASSEMBLY__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; -typedef u32 dma64_addr_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h deleted file mode 100644 index 539135add0..0000000000 --- a/include/asm-arm/u-boot-arm.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _U_BOOT_ARM_H_ -#define _U_BOOT_ARM_H_ 1 - -/* for the following variables, see start.S */ -extern ulong _armboot_start; /* code start */ -extern ulong _bss_start; /* code + data end == BSS start */ -extern ulong _bss_end; /* BSS end */ - -/* cpu/.../cpu.c */ -int cleanup_before_linux(void); - -/* board/.../... */ -int board_init(void); -int dram_init (void); - -#endif /* _U_BOOT_ARM_H_ */ diff --git a/include/asm-arm/u-boot.h b/include/asm-arm/u-boot.h deleted file mode 100644 index 298f9e37b1..0000000000 --- a/include/asm-arm/u-boot.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef _U_BOOT_H_ -#define _U_BOOT_H_ 1 - -//typedef struct bd_info {} bd_t; - -#endif /* _U_BOOT_H_ */ diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h deleted file mode 100644 index 39410de4e6..0000000000 --- a/include/asm-blackfin/bitops.h +++ /dev/null @@ -1,365 +0,0 @@ -/* - * U-boot - bitops.h Routines for bit operations - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_BITOPS_H -#define _BLACKFIN_BITOPS_H - -/* - * Copyright 1992, Linus Torvalds. - */ - -#include <asm/byteorder.h> -#include <asm/system.h> - -#ifdef __KERNEL__ -/* - * Function prototypes to keep gcc -Wall happy - */ - -/* - * The __ functions are not atomic - */ - -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static __inline__ unsigned long ffz(unsigned long word) -{ - unsigned long result = 0; - - while (word & 1) { - result++; - word >>= 1; - } - return result; -} - -static __inline__ void set_bit(int nr, volatile void *addr) -{ - int *a = (int *) addr; - int mask; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_and_cli(flags); - *a |= mask; - restore_flags(flags); -} - -static __inline__ void __set_bit(int nr, volatile void *addr) -{ - int *a = (int *) addr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - *a |= mask; -} - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - -static __inline__ void clear_bit(int nr, volatile void *addr) -{ - int *a = (int *) addr; - int mask; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_and_cli(flags); - *a &= ~mask; - restore_flags(flags); -} - -static __inline__ void change_bit(int nr, volatile void *addr) -{ - int mask, flags; - unsigned long *ADDR = (unsigned long *) addr; - - ADDR += nr >> 5; - mask = 1 << (nr & 31); - save_and_cli(flags); - *ADDR ^= mask; - restore_flags(flags); -} - -static __inline__ void __change_bit(int nr, volatile void *addr) -{ - int mask; - unsigned long *ADDR = (unsigned long *) addr; - - ADDR += nr >> 5; - mask = 1 << (nr & 31); - *ADDR ^= mask; -} - -static __inline__ int test_and_set_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_and_cli(flags); - retval = (mask & *a) != 0; - *a |= mask; - restore_flags(flags); - - return retval; -} - -static __inline__ int __test_and_set_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a |= mask; - return retval; -} - -static __inline__ int test_and_clear_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_and_cli(flags); - retval = (mask & *a) != 0; - *a &= ~mask; - restore_flags(flags); - - return retval; -} - -static __inline__ int __test_and_clear_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a &= ~mask; - return retval; -} - -static __inline__ int test_and_change_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_and_cli(flags); - retval = (mask & *a) != 0; - *a ^= mask; - restore_flags(flags); - - return retval; -} - -static __inline__ int __test_and_change_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a ^= mask; - return retval; -} - -/* - * This routine doesn't need to be atomic. - */ -static __inline__ int __constant_test_bit(int nr, - const volatile void *addr) -{ - return ((1UL << (nr & 31)) & - (((const volatile unsigned int *) addr)[nr >> 5])) != 0; -} - -static __inline__ int __test_bit(int nr, volatile void *addr) -{ - int *a = (int *) addr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - return ((mask & *a) != 0); -} - -#define test_bit(nr,addr) \ -(__builtin_constant_p(nr) ? \ - __constant_test_bit((nr),(addr)) : \ - __test_bit((nr),(addr))) - -#define find_first_zero_bit(addr, size) \ - find_next_zero_bit((addr), (size), 0) - -static __inline__ int find_next_zero_bit(void *addr, int size, int offset) -{ - unsigned long *p = ((unsigned long *) addr) + (offset >> 5); - unsigned long result = offset & ~31UL; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = *(p++); - tmp |= ~0UL >> (32 - offset); - if (size < 32) - goto found_first; - if (~tmp) - goto found_middle; - size -= 32; - result += 32; - } - while (size & ~31UL) { - if (~(tmp = *(p++))) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = *p; - - found_first: - tmp |= ~0UL >> size; - found_middle: - return result + ffz(tmp); -} - -#include <asm-generic/bitops/ffs.h> -#include <asm-generic/bitops/hweight.h> - -static __inline__ int ext2_set_bit(int nr, volatile void *addr) -{ - int mask, retval; - unsigned long flags; - volatile unsigned char *ADDR = (unsigned char *) addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - save_and_cli(flags); - retval = (mask & *ADDR) != 0; - *ADDR |= mask; - restore_flags(flags); - return retval; -} - -static __inline__ int ext2_clear_bit(int nr, volatile void *addr) -{ - int mask, retval; - unsigned long flags; - volatile unsigned char *ADDR = (unsigned char *) addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - save_and_cli(flags); - retval = (mask & *ADDR) != 0; - *ADDR &= ~mask; - restore_flags(flags); - return retval; -} - -static __inline__ int ext2_test_bit(int nr, const volatile void *addr) -{ - int mask; - const volatile unsigned char *ADDR = (const unsigned char *) addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - return ((mask & *ADDR) != 0); -} - -#define ext2_find_first_zero_bit(addr, size) \ - ext2_find_next_zero_bit((addr), (size), 0) - -static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, - unsigned long size, - unsigned long - offset) -{ - unsigned long *p = ((unsigned long *) addr) + (offset >> 5); - unsigned long result = offset & ~31UL; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = *(p++); - tmp |= ~0UL >> (32 - offset); - if (size < 32) - goto found_first; - if (~tmp) - goto found_middle; - size -= 32; - result += 32; - } - while (size & ~31UL) { - if (~(tmp = *(p++))) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = *p; - - found_first: - tmp |= ~0UL >> size; - found_middle: - return result + ffz(tmp); -} - -/* Bitmap functions for the minix filesystem. */ -#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) -#define minix_set_bit(nr,addr) set_bit(nr,addr) -#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) -#define minix_test_bit(nr,addr) test_bit(nr,addr) -#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) - -#endif - -#endif diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h deleted file mode 100644 index f2d1e65be7..0000000000 --- a/include/asm-blackfin/blackfin.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * U-boot - blackfin.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_H_ -#define _BLACKFIN_H_ - -#define lo(con32) ((con32) & 0xFFFF) -#define hi(con32) (((con32) >> 16) & 0xFFFF) - -#ifdef CONFIG_BF561 - -#include <asm/cpu/defBF561.h> -#include <asm/cpu/defBF561_extn.h> -#ifndef __ASSEMBLY__ -#include <asm/cpu/cdef_LPBlackfin.h> -#include <asm/cpu/cdefBF561.h> -#endif - -#endif - -#ifndef __ASSEMBLY__ -/* Get the System clock */ -ulong get_sclk(void); -#endif - -#if ( CONFIG_CLKIN_HALF == 0 ) -#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) -#else -#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) -#endif - -#if (CONFIG_PLL_BYPASS == 0) -#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) -#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) -#else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ -#endif - -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif - -#endif - diff --git a/include/asm-blackfin/blackfin_defs.h b/include/asm-blackfin/blackfin_defs.h deleted file mode 100644 index 2190215971..0000000000 --- a/include/asm-blackfin/blackfin_defs.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * U-boot - blackfin_defs.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __BLACKFIN_DEFS_H__ -#define __BLACKFIN_DEFS_H__ - -#define TS_MAGICKEY 0x5a5a5a5a -#define TASK_STATE 0 -#define TASK_FLAGS 4 -#define TASK_PTRACE 24 -#define TASK_BLOCKED 636 -#define TASK_COUNTER 32 -#define TASK_SIGPENDING 8 -#define TASK_NEEDRESCHED 20 -#define TASK_THREAD 600 -#define TASK_MM 44 -#define TASK_ACTIVE_MM 80 -#define THREAD_KSP 0 -#define THREAD_USP 4 -#define THREAD_SR 8 -#define THREAD_ESP0 12 -#define THREAD_PC 16 -#define PT_ORIG_R0 208 -#define PT_R0 204 -#define PT_R1 200 -#define PT_R2 196 -#define PT_R3 192 -#define PT_R4 188 -#define PT_R5 184 -#define PT_R6 180 -#define PT_R7 176 -#define PT_P0 172 -#define PT_P1 168 -#define PT_P2 164 -#define PT_P3 160 -#define PT_P4 156 -#define PT_P5 152 -#define PT_A0w 72 -#define PT_A1w 64 -#define PT_A0x 76 -#define PT_A1x 68 -#define PT_RETS 28 -#define PT_RESERVED 32 -#define PT_ASTAT 36 -#define PT_SEQSTAT 8 -#define PT_PC 24 -#define PT_IPEND 0 -#define PT_USP 144 -#define PT_FP 148 -#define PT_SYSCFG 4 -#define IRQ_HANDLER 0 -#define IRQ_DEVID 8 -#define IRQ_NEXT 16 -#define STAT_IRQ 5148 -#define SIGSEGV 11 -#define SEGV_MAPERR 196609 -#define SIGTRAP 5 -#define PT_PTRACED 1 -#define PT_TRACESYS 2 -#define PT_DTRACE 4 - -#endif diff --git a/include/asm-blackfin/byteorder.h b/include/asm-blackfin/byteorder.h deleted file mode 100644 index 3b4df4e134..0000000000 --- a/include/asm-blackfin/byteorder.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * U-boot - byteorder.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_BYTEORDER_H -#define _BLACKFIN_BYTEORDER_H - -#include <asm/types.h> - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#include <linux/byteorder/little_endian.h> - -#endif diff --git a/include/asm-blackfin/common.h b/include/asm-blackfin/common.h deleted file mode 100644 index 2ab1954176..0000000000 --- a/include/asm-blackfin/common.h +++ /dev/null @@ -1,5 +0,0 @@ - -/* We have to disable instruction cache before - * executing an external program - */ -#define ARCH_HAS_EXECUTE diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h deleted file mode 100644 index 7715f645de..0000000000 --- a/include/asm-blackfin/cplb.h +++ /dev/null @@ -1,48 +0,0 @@ -/************************************************************************ - * - * cplb.h - * - * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. - * - ************************************************************************/ - -/* Defines necessary for cplb initialisation routines. */ - -#ifndef _CPLB_H -#define _CPLB_H - -#define CPLB_ENABLE_ICACHE_P 0 -#define CPLB_ENABLE_DCACHE_P 1 -#define CPLB_ENABLE_DCACHE2_P 2 -#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated!*/ -#define CPLB_ENABLE_ICPLBS_P 4 -#define CPLB_ENABLE_DCPLBS_P 5 - -#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P) -#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P) -#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P) -#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P) -#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P) -#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P) -#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \ - CPLB_ENABLE_ICPLBS | \ - CPLB_ENABLE_DCPLBS - -#define CPLB_RELOADED 0x0000 -#define CPLB_NO_UNLOCKED 0x0001 -#define CPLB_NO_ADDR_MATCH 0x0002 -#define CPLB_PROT_VIOL 0x0003 - -#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT -#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY - -#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR - -#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID -#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID -#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID -#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE -#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID -#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL - -#endif /* _CPLB_H */ diff --git a/include/asm-blackfin/cpu.h b/include/asm-blackfin/cpu.h deleted file mode 100644 index 586e3cf181..0000000000 --- a/include/asm-blackfin/cpu.h +++ /dev/null @@ -1,74 +0,0 @@ - -/* - * U-boot - cpu.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _CPU_H_ -#define _CPU_H_ - -#include <asm/ptrace.h> - -#if defined(CONFIG_BF561) -#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4) /* SDRAM +L1 + ASYNC_Memory */ -#else -#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM + L1 + ASYNC_Memory */ -#endif - -/* we cover everything with 4 meg pages, and need an extra for L1 */ -extern unsigned int icplb_table[page_descriptor_table_size][2] ; -extern unsigned int dcplb_table[page_descriptor_table_size][2] ; - -#define INTERNAL_IRQS (32) -#define NUM_IRQ_NODES 16 -#define DEF_INTERRUPT_FLAGS 1 -#define MAX_TIM_LOAD 0xFFFFFFFF - -void blackfin_irq_panic(int reason, struct pt_regs *reg); -extern void dump_regs(struct pt_regs *regs); -void display_excp(void); -void evt_nmi(void); -void evt_exception(void); -void trap(void); -void evt_ivhw(void); -void evt_rst(void); -void evt_timer(void); -void evt_evt7(void); -void evt_evt8(void); -void evt_evt9(void); -void evt_evt10(void); -void evt_evt11(void); -void evt_evt12(void); -void evt_evt13(void); -void evt_soft_int1(void); -void evt_system_call(void); - -void flush_data_cache(void); -void flush_instruction_cache(void); -void dcache_disable(void); -void icache_enable(void); -void dcache_enable(void); -int icache_status(void); -void icache_disable (void); -int dcache_status(void); - -#endif diff --git a/include/asm-blackfin/cpu/cdefBF531.h b/include/asm-blackfin/cpu/cdefBF531.h deleted file mode 100644 index 68d841d185..0000000000 --- a/include/asm-blackfin/cpu/cdefBF531.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * cdefBF531.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _CDEFBF531_H -#define _CDEFBF531_H - -#include <cdefBF532.h> - -#endif /* _CDEFBF531_H */ diff --git a/include/asm-blackfin/cpu/cdefBF532.h b/include/asm-blackfin/cpu/cdefBF532.h deleted file mode 100644 index a4d422f765..0000000000 --- a/include/asm-blackfin/cpu/cdefBF532.h +++ /dev/null @@ -1,398 +0,0 @@ -/* - * cdefBF532.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _CDEF_BF532_H -#define _CDEF_BF532_H - -/* - * #if !defined(__ADSPLPBLACKFIN__) - * #warning cdefBF532.h should only be included for 532 compatible chips. - * #endif - */ - -/* include all Core registers and bit definitions */ -#include <asm/cpu/defBF532.h> - -/* include core specific register pointer definitions */ -#include <asm/cpu/cdef_LPBlackfin.h> - -/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ -#define pPLL_CTL ((volatile unsigned short *)PLL_CTL) -#define pPLL_STAT ((volatile unsigned short *)PLL_STAT) -#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT) -#define pCHIPID ((volatile unsigned long *)CHIPID) -#define pSWRST ((volatile unsigned short *)SWRST) -#define pSYSCR ((volatile unsigned short *)SYSCR) -#define pPLL_DIV ((volatile unsigned short *)PLL_DIV) -#define pVR_CTL ((volatile unsigned short *)VR_CTL) - -/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ -#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0) -#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1) -#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2) -#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3) -#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK) -#define pSIC_ISR ((volatile unsigned long *)SIC_ISR) -#define pSIC_IWR ((volatile unsigned long *)SIC_IWR) - -/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */ -#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL) -#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT) -#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT) - -/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */ -#define pRTC_STAT ((volatile unsigned long *)RTC_STAT) -#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL) -#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT) -#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT) -#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM) -#define pRTC_FAST ((volatile unsigned short *)RTC_FAST) -#define pRTC_PREN ((volatile unsigned short *)RTC_PREN) - -/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ -#define pFIO_DIR ((volatile unsigned short *)FIO_DIR) -#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C) -#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S) -#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C) -#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S) -#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C) -#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S) -#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR) -#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE) -#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH) -#define pFIO_INEN ((volatile unsigned short *)FIO_INEN) -#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D) -#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T) -#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D) -#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T) -#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D) -#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T) - -/* DMA Test Registers */ -#define pDMA_CCOMP ((volatile unsigned long *)DMA_CCOMP) -#define pDMA_ACOMP ((volatile unsigned long *)DMA_ACOMP) -#define pDMA_MISR ((volatile unsigned long *)DMA_MISR) -#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER) -#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT) -#define pDMA_TMODE ((volatile unsigned short *)DMA_TMODE) -#define pDMA_TMCHAN ((volatile unsigned short *)DMA_TMCHAN) -#define pDMA_TMSTAT ((volatile unsigned short *)DMA_TMSTAT) -#define pDMA_TMBD ((volatile unsigned short *)DMA_TMBD) -#define pDMA_TMM0D ((volatile unsigned short *)DMA_TMM0D) -#define pDMA_TMM1D ((volatile unsigned short *)DMA_TMM1D) -#define pDMA_TMMA ((volatile void **)DMA_TMMA) - -/* DMA Controller */ -#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG) -#define pDMA0_NEXT_DESC_PTR ((volatile void **)DMA0_NEXT_DESC_PTR) -#define pDMA0_START_ADDR ((volatile void **)DMA0_START_ADDR) -#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT) -#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT) -#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY) -#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY) -#define pDMA0_CURR_DESC_PTR ((volatile void **)DMA0_CURR_DESC_PTR) -#define pDMA0_CURR_ADDR ((volatile void **)DMA0_CURR_ADDR) -#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT) -#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT) -#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS) -#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP) - -#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG) -#define pDMA1_NEXT_DESC_PTR ((volatile void **)DMA1_NEXT_DESC_PTR) -#define pDMA1_START_ADDR ((volatile void **)DMA1_START_ADDR) -#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT) -#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT) -#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY) -#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY) -#define pDMA1_CURR_DESC_PTR ((volatile void **)DMA1_CURR_DESC_PTR) -#define pDMA1_CURR_ADDR ((volatile void **)DMA1_CURR_ADDR) -#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT) -#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT) -#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS) -#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP) - -#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG) -#define pDMA2_NEXT_DESC_PTR ((volatile void **)DMA2_NEXT_DESC_PTR) -#define pDMA2_START_ADDR ((volatile void **)DMA2_START_ADDR) -#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT) -#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT) -#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY) -#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY) -#define pDMA2_CURR_DESC_PTR ((volatile void **)DMA2_CURR_DESC_PTR) -#define pDMA2_CURR_ADDR ((volatile void **)DMA2_CURR_ADDR) -#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT) -#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT) -#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS) -#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP) - -#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG) -#define pDMA3_NEXT_DESC_PTR ((volatile void **)DMA3_NEXT_DESC_PTR) -#define pDMA3_START_ADDR ((volatile void **)DMA3_START_ADDR) -#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT) -#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT) -#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY) -#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY) -#define pDMA3_CURR_DESC_PTR ((volatile void **)DMA3_CURR_DESC_PTR) -#define pDMA3_CURR_ADDR ((volatile void **)DMA3_CURR_ADDR) -#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT) -#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT) -#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS) -#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP) - -#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG) -#define pDMA4_NEXT_DESC_PTR ((volatile void **)DMA4_NEXT_DESC_PTR) -#define pDMA4_START_ADDR ((volatile void **)DMA4_START_ADDR) -#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT) -#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT) -#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY) -#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY) -#define pDMA4_CURR_DESC_PTR ((volatile void **)DMA4_CURR_DESC_PTR) -#define pDMA4_CURR_ADDR ((volatile void **)DMA4_CURR_ADDR) -#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT) -#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT) -#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS) -#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP) - -#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG) -#define pDMA5_NEXT_DESC_PTR ((volatile void **)DMA5_NEXT_DESC_PTR) -#define pDMA5_START_ADDR ((volatile void **)DMA5_START_ADDR) -#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT) -#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT) -#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY) -#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY) -#define pDMA5_CURR_DESC_PTR ((volatile void **)DMA5_CURR_DESC_PTR) -#define pDMA5_CURR_ADDR ((volatile void **)DMA5_CURR_ADDR) -#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT) -#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT) -#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS) -#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP) - -#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG) -#define pDMA6_NEXT_DESC_PTR ((volatile void **)DMA6_NEXT_DESC_PTR) -#define pDMA6_START_ADDR ((volatile void **)DMA6_START_ADDR) -#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT) -#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT) -#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY) -#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY) -#define pDMA6_CURR_DESC_PTR ((volatile void **)DMA6_CURR_DESC_PTR) -#define pDMA6_CURR_ADDR ((volatile void **)DMA6_CURR_ADDR) -#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT) -#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT) -#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS) -#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP) - -#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG) -#define pDMA7_NEXT_DESC_PTR ((volatile void **)DMA7_NEXT_DESC_PTR) -#define pDMA7_START_ADDR ((volatile void **)DMA7_START_ADDR) -#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT) -#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT) -#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY) -#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY) -#define pDMA7_CURR_DESC_PTR ((volatile void **)DMA7_CURR_DESC_PTR) -#define pDMA7_CURR_ADDR ((volatile void **)DMA7_CURR_ADDR) -#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT) -#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT) -#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS) -#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP) - -#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG) -#define pMDMA_D1_NEXT_DESC_PTR ((volatile void **)MDMA_D1_NEXT_DESC_PTR) -#define pMDMA_D1_START_ADDR ((volatile void **)MDMA_D1_START_ADDR) -#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT) -#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT) -#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY) -#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY) -#define pMDMA_D1_CURR_DESC_PTR ((volatile void **)MDMA_D1_CURR_DESC_PTR) -#define pMDMA_D1_CURR_ADDR ((volatile void **)MDMA_D1_CURR_ADDR) -#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT) -#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT) -#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS) -#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP) - -#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG) -#define pMDMA_S1_NEXT_DESC_PTR ((volatile void **)MDMA_S1_NEXT_DESC_PTR) -#define pMDMA_S1_START_ADDR ((volatile void **)MDMA_S1_START_ADDR) -#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT) -#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT) -#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY) -#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY) -#define pMDMA_S1_CURR_DESC_PTR ((volatile void **)MDMA_S1_CURR_DESC_PTR) -#define pMDMA_S1_CURR_ADDR ((volatile void **)MDMA_S1_CURR_ADDR) -#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT) -#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT) -#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS) -#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP) - -#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG) -#define pMDMA_D0_NEXT_DESC_PTR ((volatile void **)MDMA_D0_NEXT_DESC_PTR) -#define pMDMA_D0_START_ADDR ((volatile void **)MDMA_D0_START_ADDR) -#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT) -#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT) -#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY) -#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY) -#define pMDMA_D0_CURR_DESC_PTR ((volatile void **)MDMA_D0_CURR_DESC_PTR) -#define pMDMA_D0_CURR_ADDR ((volatile void **)MDMA_D0_CURR_ADDR) -#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT) -#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT) -#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS) -#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP) - -#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG) -#define pMDMA_S0_NEXT_DESC_PTR ((volatile void **)MDMA_S0_NEXT_DESC_PTR) -#define pMDMA_S0_START_ADDR ((volatile void **)MDMA_S0_START_ADDR) -#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT) -#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT) -#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY) -#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY) -#define pMDMA_S0_CURR_DESC_PTR ((volatile void **)MDMA_S0_CURR_DESC_PTR) -#define pMDMA_S0_CURR_ADDR ((volatile void **)MDMA_S0_CURR_ADDR) -#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT) -#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT) -#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS) -#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP) - -/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */ -#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL) -#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0) -#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1) - -/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */ -/* #define L1SBAR 0xFFC04840 */ /* L1 SRAM Base Address Register */ -/* #define L1CSR 0xFFC04844 */ /* L1 SRAM Control Initialization Register */ - -/* - * #define pDB_ACOMP ((volatile void **)DB_ACOMP) - * #define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP) - */ - -/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */ -#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL) -#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC) -#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT) -#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL) - -/* UART Controller */ -#define pUART_THR ((volatile unsigned short *)UART_THR) -#define pUART_RBR ((volatile unsigned short *)UART_RBR) -#define pUART_DLL ((volatile unsigned short *)UART_DLL) -#define pUART_IER ((volatile unsigned short *)UART_IER) -#define pUART_DLH ((volatile unsigned short *)UART_DLH) -#define pUART_IIR ((volatile unsigned short *)UART_IIR) -#define pUART_LCR ((volatile unsigned short *)UART_LCR) -#define pUART_MCR ((volatile unsigned short *)UART_MCR) -#define pUART_LSR ((volatile unsigned short *)UART_LSR) - -/* - * #define UART_MSR - */ -#define pUART_SCR ((volatile unsigned short *)UART_SCR) -#define pUART_GCTL ((volatile unsigned short *)UART_GCTL) - -/* SPI Controller */ -#define pSPI_CTL ((volatile unsigned short *)SPI_CTL) -#define pSPI_FLG ((volatile unsigned short *)SPI_FLG) -#define pSPI_STAT ((volatile unsigned short *)SPI_STAT) -#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR) -#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR) -#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD) -#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW) - -/* TIMER 0, 1, 2 Registers */ -#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG) -#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER) -#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD) -#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH) - -#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG) -#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER) -#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD) -#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH) - -#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG) -#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER) -#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD) -#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH) - -#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE) -#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE) -#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS) - -/* SPORT0 Controller */ -#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1) -#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2) -#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV) -#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV) -#define pSPORT0_TX ((volatile long *)SPORT0_TX) -#define pSPORT0_RX ((volatile long *)SPORT0_RX) -#define pSPORT0_TX32 ((volatile long *)SPORT0_TX) -#define pSPORT0_RX32 ((volatile long *)SPORT0_RX) -#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX) -#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX) -#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1) -#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2) -#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV) -#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV) -#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT) -#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL) -#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1) -#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2) -#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0) -#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1) -#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2) -#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3) -#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0) -#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1) -#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2) -#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3) - -/* SPORT1 Controller */ -#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1) -#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2) -#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV) -#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV) -#define pSPORT1_TX ((volatile long *)SPORT1_TX) -#define pSPORT1_RX ((volatile long *)SPORT1_RX) -#define pSPORT1_TX32 ((volatile long *)SPORT1_TX) -#define pSPORT1_RX32 ((volatile long *)SPORT1_RX) -#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX) -#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX) -#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1) -#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2) -#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV) -#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV) -#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT) -#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL) -#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1) -#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2) -#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0) -#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1) -#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2) -#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3) -#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0) -#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1) -#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2) -#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3) - -/* Parallel Peripheral Interface (PPI) */ -#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL) -#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS) -#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY) -#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT) -#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME) - -#endif /* _CDEF_BF532_H */ diff --git a/include/asm-blackfin/cpu/cdefBF533.h b/include/asm-blackfin/cpu/cdefBF533.h deleted file mode 100644 index 8c751e6073..0000000000 --- a/include/asm-blackfin/cpu/cdefBF533.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * cdefBF533.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _CDEFBF533_H -#define _CDEFBF533_H - -#include <asm/cpu/cdefBF532.h> - -#endif /* _CDEFBF533_H */ diff --git a/include/asm-blackfin/cpu/cdefBF53x.h b/include/asm-blackfin/cpu/cdefBF53x.h deleted file mode 100644 index db4eaa9cf2..0000000000 --- a/include/asm-blackfin/cpu/cdefBF53x.h +++ /dev/null @@ -1,32 +0,0 @@ -/************************************************************************ - * - * cdefBF53x.h - * - * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. - * - ************************************************************************/ - -#ifndef _CDEFBF53x_H -#define _CDEFBF53x_H - -#if defined(__ADSPBF531__) - #include <asm/cpu/cdefBF531.h> -#elif defined(__ADSPBF532__) - #include <asm/cpu/cdefBF532.h> -#elif defined(__ADSPBF533__) - #include <asm/cpu/cdefBF533.h> -#elif defined(__ADSPBF561__) - #include <asm/cpu/cdefBF561.h> -#elif defined(__ADSPBF535__) - #include <asm/cpu/cdefBF535.h> -#elif defined(__AD6532__) - #include <sam/cpu/cdefAD6532.h> -#else - #if defined(__ADSPLPBLACKFIN__) - #include <asm/cpu/cdefBF532.h> - #else - #include <asm/cpu/cdefBF535.h> - #endif -#endif - -#endif /* _CDEFBF53x_H */ diff --git a/include/asm-blackfin/cpu/cdefBF561.h b/include/asm-blackfin/cpu/cdefBF561.h deleted file mode 100644 index 60fdf1eb79..0000000000 --- a/include/asm-blackfin/cpu/cdefBF561.h +++ /dev/null @@ -1,1001 +0,0 @@ -/************************************************************************ - * - * cdefBF561.h - * - * (c) Copyright 2001-2004 Analog Devices, Inc. All rights reserved. - * - ************************************************************************/ - -/* C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */ - -#ifndef _CDEF_BF561_H -#define _CDEF_BF561_H - -/* - * #if !defined(__ADSPBF561__) - * #warning cdefBF561.h should only be included for BF561 chip. - * #endif - */ - -// include all Core registers and bit definitions -#include <asm/cpu/defBF561.h> -//#include <asm/arch-common/cdef_LPBlackfin.h> - -/* - * System MMR Register Map - */ - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define pPLL_CTL (volatile unsigned short *)PLL_CTL -#define pPLL_DIV (volatile unsigned short *)PLL_DIV -#define pVR_CTL (volatile unsigned short *)VR_CTL -#define pPLL_STAT (volatile unsigned short *)PLL_STAT -#define pPLL_LOCKCNT (volatile unsigned short *)PLL_LOCKCNT - -/* - * System Reset and Interrupt Controller registers for - * core A (0xFFC0 0100-0xFFC0 01FF) - */ -#define pSICA_SWRST (volatile unsigned short *)SICA_SWRST -#define pSICA_SYSCR (volatile unsigned short *)SICA_SYSCR -#define pSICA_RVECT (volatile unsigned short *)SICA_RVECT -#define pSICA_IMASK (volatile unsigned long *)SICA_IMASK -#define pSICA_IMASK0 (volatile unsigned long *)SICA_IMASK0 -#define pSICA_IMASK1 (volatile unsigned long *)SICA_IMASK1 -#define pSICA_IAR0 (volatile unsigned long *)SICA_IAR0 -#define pSICA_IAR1 (volatile unsigned long *)SICA_IAR1 -#define pSICA_IAR2 (volatile unsigned long *)SICA_IAR2 -#define pSICA_IAR3 (volatile unsigned long *)SICA_IAR3 -#define pSICA_IAR4 (volatile unsigned long *)SICA_IAR4 -#define pSICA_IAR5 (volatile unsigned long *)SICA_IAR5 -#define pSICA_IAR6 (volatile unsigned long *)SICA_IAR6 -#define pSICA_IAR7 (volatile unsigned long *)SICA_IAR7 -#define pSICA_ISR0 (volatile unsigned long *)SICA_ISR0 -#define pSICA_ISR1 (volatile unsigned long *)SICA_ISR1 -#define pSICA_IWR0 (volatile unsigned long *)SICA_IWR0 -#define pSICA_IWR1 (volatile unsigned long *)SICA_IWR1 - -/* - * System Reset and Interrupt Controller registers for - * Core B (0xFFC0 1100-0xFFC0 11FF) - */ -#define pSICB_SWRST (volatile unsigned short *)SICB_SWRST -#define pSICB_SYSCR (volatile unsigned short *)SICB_SYSCR -#define pSICB_RVECT (volatile unsigned short *)SICB_RVECT -#define pSICB_IMASK0 (volatile unsigned long *)SICB_IMASK0 -#define pSICB_IMASK1 (volatile unsigned long *)SICB_IMASK1 -#define pSICB_IAR0 (volatile unsigned long *)SICB_IAR0 -#define pSICB_IAR1 (volatile unsigned long *)SICB_IAR1 -#define pSICB_IAR2 (volatile unsigned long *)SICB_IAR2 -#define pSICB_IAR3 (volatile unsigned long *)SICB_IAR3 -#define pSICB_IAR4 (volatile unsigned long *)SICB_IAR4 -#define pSICB_IAR5 (volatile unsigned long *)SICB_IAR5 -#define pSICB_IAR6 (volatile unsigned long *)SICB_IAR6 -#define pSICB_IAR7 (volatile unsigned long *)SICB_IAR7 -#define pSICB_ISR0 (volatile unsigned long *)SICB_ISR0 -#define pSICB_ISR1 (volatile unsigned long *)SICB_ISR1 -#define pSICB_IWR0 (volatile unsigned long *)SICB_IWR0 -#define pSICB_IWR1 (volatile unsigned long *)SICB_IWR1 - -/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ -#define pWDOGA_CTL (volatile unsigned short *)WDOGA_CTL -#define pWDOGA_CNT (volatile unsigned long *)WDOGA_CNT -#define pWDOGA_STAT (volatile unsigned long *)WDOGA_STAT - -/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */ -#define pWDOGB_CTL (volatile unsigned short *)WDOGB_CTL -#define pWDOGB_CNT (volatile unsigned long *)WDOGB_CNT -#define pWDOGB_STAT (volatile unsigned long *)WDOGB_STAT - -/* UART Controller (0xFFC00400 - 0xFFC004FF) */ -#define pUART_THR (volatile unsigned short *)UART_THR -#define pUART_RBR (volatile unsigned short *)UART_RBR -#define pUART_DLL (volatile unsigned short *)UART_DLL -#define pUART_IER (volatile unsigned short *)UART_IER -#define pUART_DLH (volatile unsigned short *)UART_DLH -#define pUART_IIR (volatile unsigned short *)UART_IIR -#define pUART_LCR (volatile unsigned short *)UART_LCR -#define pUART_MCR (volatile unsigned short *)UART_MCR -#define pUART_LSR (volatile unsigned short *)UART_LSR -#define pUART_MSR (volatile unsigned short *)UART_MSR -#define pUART_SCR (volatile unsigned short *)UART_SCR -#define pUART_GCTL (volatile unsigned short *)UART_GCTL - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define pSPI_CTL (volatile unsigned short *)SPI_CTL -#define pSPI_FLG (volatile unsigned short *)SPI_FLG -#define pSPI_STAT (volatile unsigned short *)SPI_STAT -#define pSPI_TDBR (volatile unsigned short *)SPI_TDBR -#define pSPI_RDBR (volatile unsigned short *)SPI_RDBR -#define pSPI_BAUD (volatile unsigned short *)SPI_BAUD -#define pSPI_SHADOW (volatile unsigned short *)SPI_SHADOW - -/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */ -#define pTIMER0_CONFIG (volatile unsigned short *)TIMER0_CONFIG -#define pTIMER0_COUNTER (volatile unsigned long *)TIMER0_COUNTER -#define pTIMER0_PERIOD (volatile unsigned long *)TIMER0_PERIOD -#define pTIMER0_WIDTH (volatile unsigned long *)TIMER0_WIDTH -#define pTIMER1_CONFIG (volatile unsigned short *)TIMER1_CONFIG -#define pTIMER1_COUNTER (volatile unsigned long *)TIMER1_COUNTER -#define pTIMER1_PERIOD (volatile unsigned long *)TIMER1_PERIOD -#define pTIMER1_WIDTH (volatile unsigned long *)TIMER1_WIDTH -#define pTIMER2_CONFIG (volatile unsigned short *)TIMER2_CONFIG -#define pTIMER2_COUNTER (volatile unsigned long *)TIMER2_COUNTER -#define pTIMER2_PERIOD (volatile unsigned long *)TIMER2_PERIOD -#define pTIMER2_WIDTH (volatile unsigned long *)TIMER2_WIDTH -#define pTIMER3_CONFIG (volatile unsigned short *)TIMER3_CONFIG -#define pTIMER3_COUNTER (volatile unsigned long *)TIMER3_COUNTER -#define pTIMER3_PERIOD (volatile unsigned long *)TIMER3_PERIOD -#define pTIMER3_WIDTH (volatile unsigned long *)TIMER3_WIDTH -#define pTIMER4_CONFIG (volatile unsigned short *)TIMER4_CONFIG -#define pTIMER4_COUNTER (volatile unsigned long *)TIMER4_COUNTER -#define pTIMER4_PERIOD (volatile unsigned long *)TIMER4_PERIOD -#define pTIMER4_WIDTH (volatile unsigned long *)TIMER4_WIDTH -#define pTIMER5_CONFIG (volatile unsigned short *)TIMER5_CONFIG -#define pTIMER5_COUNTER (volatile unsigned long *)TIMER5_COUNTER -#define pTIMER5_PERIOD (volatile unsigned long *)TIMER5_PERIOD -#define pTIMER5_WIDTH (volatile unsigned long *)TIMER5_WIDTH -#define pTIMER6_CONFIG (volatile unsigned short *)TIMER6_CONFIG -#define pTIMER6_COUNTER (volatile unsigned long *)TIMER6_COUNTER -#define pTIMER6_PERIOD (volatile unsigned long *)TIMER6_PERIOD -#define pTIMER6_WIDTH (volatile unsigned long *)TIMER6_WIDTH -#define pTIMER7_CONFIG (volatile unsigned short *)TIMER7_CONFIG -#define pTIMER7_COUNTER (volatile unsigned long *)TIMER7_COUNTER -#define pTIMER7_PERIOD (volatile unsigned long *)TIMER7_PERIOD -#define pTIMER7_WIDTH (volatile unsigned long *)TIMER7_WIDTH - -/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */ -#define pTMRS8_ENABLE (volatile unsigned short *)TMRS8_ENABLE -#define pTMRS8_DISABLE (volatile unsigned short *)TMRS8_DISABLE -#define pTMRS8_STATUS (volatile unsigned long *)TMRS8_STATUS -#define pTIMER8_CONFIG (volatile unsigned short *)TIMER8_CONFIG -#define pTIMER8_COUNTER (volatile unsigned long *)TIMER8_COUNTER -#define pTIMER8_PERIOD (volatile unsigned long *)TIMER8_PERIOD -#define pTIMER8_WIDTH (volatile unsigned long *)TIMER8_WIDTH -#define pTIMER9_CONFIG (volatile unsigned short *)TIMER9_CONFIG -#define pTIMER9_COUNTER (volatile unsigned long *)TIMER9_COUNTER -#define pTIMER9_PERIOD (volatile unsigned long *)TIMER9_PERIOD -#define pTIMER9_WIDTH (volatile unsigned long *)TIMER9_WIDTH -#define pTIMER10_CONFIG (volatile unsigned short *)TIMER10_CONFIG -#define pTIMER10_COUNTER (volatile unsigned long *)TIMER10_COUNTER -#define pTIMER10_PERIOD (volatile unsigned long *)TIMER10_PERIOD -#define pTIMER10_WIDTH (volatile unsigned long *)TIMER10_WIDTH -#define pTIMER11_CONFIG (volatile unsigned short *)TIMER11_CONFIG -#define pTIMER11_COUNTER (volatile unsigned long *)TIMER11_COUNTER -#define pTIMER11_PERIOD (volatile unsigned long *)TIMER11_PERIOD -#define pTIMER11_WIDTH (volatile unsigned long *)TIMER11_WIDTH -#define pTMRS4_ENABLE (volatile unsigned short *)TMRS4_ENABLE -#define pTMRS4_DISABLE (volatile unsigned short *)TMRS4_DISABLE -#define pTMRS4_STATUS (volatile unsigned long *)TMRS4_STATUS - -/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ -#define pFIO0_FLAG_D (volatile unsigned short *)FIO0_FLAG_D -#define pFIO0_FLAG_C (volatile unsigned short *)FIO0_FLAG_C -#define pFIO0_FLAG_S (volatile unsigned short *)FIO0_FLAG_S -#define pFIO0_FLAG_T (volatile unsigned short *)FIO0_FLAG_T -#define pFIO0_MASKA_D (volatile unsigned short *)FIO0_MASKA_D -#define pFIO0_MASKA_C (volatile unsigned short *)FIO0_MASKA_C -#define pFIO0_MASKA_S (volatile unsigned short *)FIO0_MASKA_S -#define pFIO0_MASKA_T (volatile unsigned short *)FIO0_MASKA_T -#define pFIO0_MASKB_D (volatile unsigned short *)FIO0_MASKB_D -#define pFIO0_MASKB_C (volatile unsigned short *)FIO0_MASKB_C -#define pFIO0_MASKB_S (volatile unsigned short *)FIO0_MASKB_S -#define pFIO0_MASKB_T (volatile unsigned short *)FIO0_MASKB_T -#define pFIO0_DIR (volatile unsigned short *)FIO0_DIR -#define pFIO0_POLAR (volatile unsigned short *)FIO0_POLAR -#define pFIO0_EDGE (volatile unsigned short *)FIO0_EDGE -#define pFIO0_BOTH (volatile unsigned short *)FIO0_BOTH -#define pFIO0_INEN (volatile unsigned short *)FIO0_INEN - -/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */ -#define pFIO1_FLAG_D (volatile unsigned short *)FIO1_FLAG_D -#define pFIO1_FLAG_C (volatile unsigned short *)FIO1_FLAG_C -#define pFIO1_FLAG_S (volatile unsigned short *)FIO1_FLAG_S -#define pFIO1_FLAG_T (volatile unsigned short *)FIO1_FLAG_T -#define pFIO1_MASKA_D (volatile unsigned short *)FIO1_MASKA_D -#define pFIO1_MASKA_C (volatile unsigned short *)FIO1_MASKA_C -#define pFIO1_MASKA_S (volatile unsigned short *)FIO1_MASKA_S -#define pFIO1_MASKA_T (volatile unsigned short *)FIO1_MASKA_T -#define pFIO1_MASKB_D (volatile unsigned short *)FIO1_MASKB_D -#define pFIO1_MASKB_C (volatile unsigned short *)FIO1_MASKB_C -#define pFIO1_MASKB_S (volatile unsigned short *)FIO1_MASKB_S -#define pFIO1_MASKB_T (volatile unsigned short *)FIO1_MASKB_T -#define pFIO1_DIR (volatile unsigned short *)FIO1_DIR -#define pFIO1_POLAR (volatile unsigned short *)FIO1_POLAR -#define pFIO1_EDGE (volatile unsigned short *)FIO1_EDGE -#define pFIO1_BOTH (volatile unsigned short *)FIO1_BOTH -#define pFIO1_INEN (volatile unsigned short *)FIO1_INEN - -/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */ -#define pFIO2_FLAG_D (volatile unsigned short *)FIO2_FLAG_D -#define pFIO2_FLAG_C (volatile unsigned short *)FIO2_FLAG_C -#define pFIO2_FLAG_S (volatile unsigned short *)FIO2_FLAG_S -#define pFIO2_FLAG_T (volatile unsigned short *)FIO2_FLAG_T -#define pFIO2_MASKA_D (volatile unsigned short *)FIO2_MASKA_D -#define pFIO2_MASKA_C (volatile unsigned short *)FIO2_MASKA_C -#define pFIO2_MASKA_S (volatile unsigned short *)FIO2_MASKA_S -#define pFIO2_MASKA_T (volatile unsigned short *)FIO2_MASKA_T -#define pFIO2_MASKB_D (volatile unsigned short *)FIO2_MASKB_D -#define pFIO2_MASKB_C (volatile unsigned short *)FIO2_MASKB_C -#define pFIO2_MASKB_S (volatile unsigned short *)FIO2_MASKB_S -#define pFIO2_MASKB_T (volatile unsigned short *)FIO2_MASKB_T -#define pFIO2_DIR (volatile unsigned short *)FIO2_DIR -#define pFIO2_POLAR (volatile unsigned short *)FIO2_POLAR -#define pFIO2_EDGE (volatile unsigned short *)FIO2_EDGE -#define pFIO2_BOTH (volatile unsigned short *)FIO2_BOTH -#define pFIO2_INEN (volatile unsigned short *)FIO2_INEN - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define pSPORT0_TCR1 (volatile unsigned short *)SPORT0_TCR1 -#define pSPORT0_TCR2 (volatile unsigned short *)SPORT0_TCR2 -#define pSPORT0_TCLKDIV (volatile unsigned short *)SPORT0_TCLKDIV -#define pSPORT0_TFSDIV (volatile unsigned short *)SPORT0_TFSDIV -#define pSPORT0_TX (volatile unsigned long *)SPORT0_TX -#define pSPORT0_RX (volatile unsigned long *)SPORT0_RX -#define pSPORT0_TX32 ((volatile long *)SPORT0_TX) -#define pSPORT0_RX32 ((volatile long *)SPORT0_RX) -#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX) -#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX) -#define pSPORT0_RCR1 (volatile unsigned short *)SPORT0_RCR1 -#define pSPORT0_RCR2 (volatile unsigned short *)SPORT0_RCR2 -#define pSPORT0_RCLKDIV (volatile unsigned short *)SPORT0_RCLKDIV -#define pSPORT0_RFSDIV (volatile unsigned short *)SPORT0_RFSDIV -#define pSPORT0_STAT (volatile unsigned short *)SPORT0_STAT -#define pSPORT0_CHNL (volatile unsigned short *)SPORT0_CHNL -#define pSPORT0_MCMC1 (volatile unsigned short *)SPORT0_MCMC1 -#define pSPORT0_MCMC2 (volatile unsigned short *)SPORT0_MCMC2 -#define pSPORT0_MTCS0 (volatile unsigned long *)SPORT0_MTCS0 -#define pSPORT0_MTCS1 (volatile unsigned long *)SPORT0_MTCS1 -#define pSPORT0_MTCS2 (volatile unsigned long *)SPORT0_MTCS2 -#define pSPORT0_MTCS3 (volatile unsigned long *)SPORT0_MTCS3 -#define pSPORT0_MRCS0 (volatile unsigned long *)SPORT0_MRCS0 -#define pSPORT0_MRCS1 (volatile unsigned long *)SPORT0_MRCS1 -#define pSPORT0_MRCS2 (volatile unsigned long *)SPORT0_MRCS2 -#define pSPORT0_MRCS3 (volatile unsigned long *)SPORT0_MRCS3 - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define pSPORT1_TCR1 (volatile unsigned short *)SPORT1_TCR1 -#define pSPORT1_TCR2 (volatile unsigned short *)SPORT1_TCR2 -#define pSPORT1_TCLKDIV (volatile unsigned short *)SPORT1_TCLKDIV -#define pSPORT1_TFSDIV (volatile unsigned short *)SPORT1_TFSDIV -#define pSPORT1_TX (volatile unsigned long *)SPORT1_TX -#define pSPORT1_RX (volatile unsigned long *)SPORT1_RX -#define pSPORT1_TX32 ((volatile long *)SPORT1_TX) -#define pSPORT1_RX32 ((volatile long *)SPORT1_RX) -#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX) -#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX) -#define pSPORT1_RCR1 (volatile unsigned short *)SPORT1_RCR1 -#define pSPORT1_RCR2 (volatile unsigned short *)SPORT1_RCR2 -#define pSPORT1_RCLKDIV (volatile unsigned short *)SPORT1_RCLKDIV -#define pSPORT1_RFSDIV (volatile unsigned short *)SPORT1_RFSDIV -#define pSPORT1_STAT (volatile unsigned short *)SPORT1_STAT -#define pSPORT1_CHNL (volatile unsigned short *)SPORT1_CHNL -#define pSPORT1_MCMC1 (volatile unsigned short *)SPORT1_MCMC1 -#define pSPORT1_MCMC2 (volatile unsigned short *)SPORT1_MCMC2 -#define pSPORT1_MTCS0 (volatile unsigned long *)SPORT1_MTCS0 -#define pSPORT1_MTCS1 (volatile unsigned long *)SPORT1_MTCS1 -#define pSPORT1_MTCS2 (volatile unsigned long *)SPORT1_MTCS2 -#define pSPORT1_MTCS3 (volatile unsigned long *)SPORT1_MTCS3 -#define pSPORT1_MRCS0 (volatile unsigned long *)SPORT1_MRCS0 -#define pSPORT1_MRCS1 (volatile unsigned long *)SPORT1_MRCS1 -#define pSPORT1_MRCS2 (volatile unsigned long *)SPORT1_MRCS2 -#define pSPORT1_MRCS3 (volatile unsigned long *)SPORT1_MRCS3 - -/* Asynchronous Memory Controller - External Bus Interface Unit */ -#define pEBIU_AMGCTL (volatile unsigned short *)EBIU_AMGCTL -#define pEBIU_AMBCTL0 (volatile unsigned long *)EBIU_AMBCTL0 -#define pEBIU_AMBCTL1 (volatile unsigned long *)EBIU_AMBCTL1 - -/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define pEBIU_SDGCTL (volatile unsigned long *)EBIU_SDGCTL -#define pEBIU_SDBCTL (volatile unsigned long *)EBIU_SDBCTL -#define pEBIU_SDRRC (volatile unsigned short *)EBIU_SDRRC -#define pEBIU_SDSTAT (volatile unsigned short *)EBIU_SDSTAT - -/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/ -#define pPPI0_CONTROL (volatile unsigned short *)PPI0_CONTROL -#define pPPI0_STATUS (volatile unsigned short *)PPI0_STATUS -#define pPPI0_COUNT (volatile unsigned short *)PPI0_COUNT -#define pPPI0_DELAY (volatile unsigned short *)PPI0_DELAY -#define pPPI0_FRAME (volatile unsigned short *)PPI0_FRAME - -/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF)*/ -#define pPPI1_CONTROL (volatile unsigned short *)PPI1_CONTROL -#define pPPI1_STATUS (volatile unsigned short *)PPI1_STATUS -#define pPPI1_COUNT (volatile unsigned short *)PPI1_COUNT -#define pPPI1_DELAY (volatile unsigned short *)PPI1_DELAY -#define pPPI1_FRAME (volatile unsigned short *)PPI1_FRAME - -/*DMA Traffic controls*/ -#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER) -#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT) -#define pDMA_TC_PER ((volatile unsigned short *)DMA_TC_PER) -#define pDMA_TC_CNT ((volatile unsigned short *)DMA_TC_CNT) - -/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ -#define pDMA1_0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG -#define pDMA1_0_NEXT_DESC_PTR (volatile void **)DMA1_0_NEXT_DESC_PTR -#define pDMA1_0_START_ADDR (volatile void **)DMA1_0_START_ADDR -#define pDMA1_0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT -#define pDMA1_0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT -#define pDMA1_0_X_MODIFY (volatile unsigned short *)DMA1_0_X_MODIFY -#define pDMA1_0_Y_MODIFY (volatile unsigned short *)DMA1_0_Y_MODIFY -#define pDMA1_0_CURR_DESC_PTR (volatile void **)DMA1_0_CURR_DESC_PTR -#define pDMA1_0_CURR_ADDR (volatile void **)DMA1_0_CURR_ADDR -#define pDMA1_0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT -#define pDMA1_0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT -#define pDMA1_0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS -#define pDMA1_0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP -#define pDMA1_1_CONFIG (volatile unsigned short *)DMA1_1_CONFIG -#define pDMA1_1_NEXT_DESC_PTR (volatile void **)DMA1_1_NEXT_DESC_PTR -#define pDMA1_1_START_ADDR (volatile void **)DMA1_1_START_ADDR -#define pDMA1_1_X_COUNT (volatile unsigned short *)DMA1_1_X_COUNT -#define pDMA1_1_Y_COUNT (volatile unsigned short *)DMA1_1_Y_COUNT -#define pDMA1_1_X_MODIFY (volatile unsigned short *)DMA1_1_X_MODIFY -#define pDMA1_1_Y_MODIFY (volatile unsigned short *)DMA1_1_Y_MODIFY -#define pDMA1_1_CURR_DESC_PTR (volatile void **)DMA1_1_CURR_DESC_PTR -#define pDMA1_1_CURR_ADDR (volatile void **)DMA1_1_CURR_ADDR -#define pDMA1_1_CURR_X_COUNT (volatile unsigned short *)DMA1_1_CURR_X_COUNT -#define pDMA1_1_CURR_Y_COUNT (volatile unsigned short *)DMA1_1_CURR_Y_COUNT -#define pDMA1_1_IRQ_STATUS (volatile unsigned short *)DMA1_1_IRQ_STATUS -#define pDMA1_1_PERIPHERAL_MAP (volatile unsigned short *)DMA1_1_PERIPHERAL_MAP -#define pDMA1_2_CONFIG (volatile unsigned short *)DMA1_2_CONFIG -#define pDMA1_2_NEXT_DESC_PTR (volatile void **)DMA1_2_NEXT_DESC_PTR -#define pDMA1_2_START_ADDR (volatile void **)DMA1_2_START_ADDR -#define pDMA1_2_X_COUNT (volatile unsigned short *)DMA1_2_X_COUNT -#define pDMA1_2_Y_COUNT (volatile unsigned short *)DMA1_2_Y_COUNT -#define pDMA1_2_X_MODIFY (volatile unsigned short *)DMA1_2_X_MODIFY -#define pDMA1_2_Y_MODIFY (volatile unsigned short *)DMA1_2_Y_MODIFY -#define pDMA1_2_CURR_DESC_PTR (volatile void **)DMA1_2_CURR_DESC_PTR -#define pDMA1_2_CURR_ADDR (volatile void **)DMA1_2_CURR_ADDR -#define pDMA1_2_CURR_X_COUNT (volatile unsigned short *)DMA1_2_CURR_X_COUNT -#define pDMA1_2_CURR_Y_COUNT (volatile unsigned short *)DMA1_2_CURR_Y_COUNT -#define pDMA1_2_IRQ_STATUS (volatile unsigned short *)DMA1_2_IRQ_STATUS -#define pDMA1_2_PERIPHERAL_MAP (volatile unsigned short *)DMA1_2_PERIPHERAL_MAP -#define pDMA1_3_CONFIG (volatile unsigned short *)DMA1_3_CONFIG -#define pDMA1_3_NEXT_DESC_PTR (volatile void **)DMA1_3_NEXT_DESC_PTR -#define pDMA1_3_START_ADDR (volatile void **)DMA1_3_START_ADDR -#define pDMA1_3_X_COUNT (volatile unsigned short *)DMA1_3_X_COUNT -#define pDMA1_3_Y_COUNT (volatile unsigned short *)DMA1_3_Y_COUNT -#define pDMA1_3_X_MODIFY (volatile unsigned short *)DMA1_3_X_MODIFY -#define pDMA1_3_Y_MODIFY (volatile unsigned short *)DMA1_3_Y_MODIFY -#define pDMA1_3_CURR_DESC_PTR (volatile void **)DMA1_3_CURR_DESC_PTR -#define pDMA1_3_CURR_ADDR (volatile void **)DMA1_3_CURR_ADDR -#define pDMA1_3_CURR_X_COUNT (volatile unsigned short *)DMA1_3_CURR_X_COUNT -#define pDMA1_3_CURR_Y_COUNT (volatile unsigned short *)DMA1_3_CURR_Y_COUNT -#define pDMA1_3_IRQ_STATUS (volatile unsigned short *)DMA1_3_IRQ_STATUS -#define pDMA1_3_PERIPHERAL_MAP (volatile unsigned short *)DMA1_3_PERIPHERAL_MAP -#define pDMA1_4_CONFIG (volatile unsigned short *)DMA1_4_CONFIG -#define pDMA1_4_NEXT_DESC_PTR (volatile void **)DMA1_4_NEXT_DESC_PTR -#define pDMA1_4_START_ADDR (volatile void **)DMA1_4_START_ADDR -#define pDMA1_4_X_COUNT (volatile unsigned short *)DMA1_4_X_COUNT -#define pDMA1_4_Y_COUNT (volatile unsigned short *)DMA1_4_Y_COUNT -#define pDMA1_4_X_MODIFY (volatile unsigned short *)DMA1_4_X_MODIFY -#define pDMA1_4_Y_MODIFY (volatile unsigned short *)DMA1_4_Y_MODIFY -#define pDMA1_4_CURR_DESC_PTR (volatile void **)DMA1_4_CURR_DESC_PTR -#define pDMA1_4_CURR_ADDR (volatile void **)DMA1_4_CURR_ADDR -#define pDMA1_4_CURR_X_COUNT (volatile unsigned short *)DMA1_4_CURR_X_COUNT -#define pDMA1_4_CURR_Y_COUNT (volatile unsigned short *)DMA1_4_CURR_Y_COUNT -#define pDMA1_4_IRQ_STATUS (volatile unsigned short *)DMA1_4_IRQ_STATUS -#define pDMA1_4_PERIPHERAL_MAP (volatile unsigned short *)DMA1_4_PERIPHERAL_MAP -#define pDMA1_5_CONFIG (volatile unsigned short *)DMA1_5_CONFIG -#define pDMA1_5_NEXT_DESC_PTR (volatile void **)DMA1_5_NEXT_DESC_PTR -#define pDMA1_5_START_ADDR (volatile void **)DMA1_5_START_ADDR -#define pDMA1_5_X_COUNT (volatile unsigned short *)DMA1_5_X_COUNT -#define pDMA1_5_Y_COUNT (volatile unsigned short *)DMA1_5_Y_COUNT -#define pDMA1_5_X_MODIFY (volatile unsigned short *)DMA1_5_X_MODIFY -#define pDMA1_5_Y_MODIFY (volatile unsigned short *)DMA1_5_Y_MODIFY -#define pDMA1_5_CURR_DESC_PTR (volatile void **)DMA1_5_CURR_DESC_PTR -#define pDMA1_5_CURR_ADDR (volatile void **)DMA1_5_CURR_ADDR -#define pDMA1_5_CURR_X_COUNT (volatile unsigned short *)DMA1_5_CURR_X_COUNT -#define pDMA1_5_CURR_Y_COUNT (volatile unsigned short *)DMA1_5_CURR_Y_COUNT -#define pDMA1_5_IRQ_STATUS (volatile unsigned short *)DMA1_5_IRQ_STATUS -#define pDMA1_5_PERIPHERAL_MAP (volatile unsigned short *)DMA1_5_PERIPHERAL_MAP -#define pDMA1_6_CONFIG (volatile unsigned short *)DMA1_6_CONFIG -#define pDMA1_6_NEXT_DESC_PTR (volatile void **)DMA1_6_NEXT_DESC_PTR -#define pDMA1_6_START_ADDR (volatile void **)DMA1_6_START_ADDR -#define pDMA1_6_X_COUNT (volatile unsigned short *)DMA1_6_X_COUNT -#define pDMA1_6_Y_COUNT (volatile unsigned short *)DMA1_6_Y_COUNT -#define pDMA1_6_X_MODIFY (volatile unsigned short *)DMA1_6_X_MODIFY -#define pDMA1_6_Y_MODIFY (volatile unsigned short *)DMA1_6_Y_MODIFY -#define pDMA1_6_CURR_DESC_PTR (volatile void **)DMA1_6_CURR_DESC_PTR -#define pDMA1_6_CURR_ADDR (volatile void **)DMA1_6_CURR_ADDR -#define pDMA1_6_CURR_X_COUNT (volatile unsigned short *)DMA1_6_CURR_X_COUNT -#define pDMA1_6_CURR_Y_COUNT (volatile unsigned short *)DMA1_6_CURR_Y_COUNT -#define pDMA1_6_IRQ_STATUS (volatile unsigned short *)DMA1_6_IRQ_STATUS -#define pDMA1_6_PERIPHERAL_MAP (volatile unsigned short *)DMA1_6_PERIPHERAL_MAP -#define pDMA1_7_CONFIG (volatile unsigned short *)DMA1_7_CONFIG -#define pDMA1_7_NEXT_DESC_PTR (volatile void **)DMA1_7_NEXT_DESC_PTR -#define pDMA1_7_START_ADDR (volatile void **)DMA1_7_START_ADDR -#define pDMA1_7_X_COUNT (volatile unsigned short *)DMA1_7_X_COUNT -#define pDMA1_7_Y_COUNT (volatile unsigned short *)DMA1_7_Y_COUNT -#define pDMA1_7_X_MODIFY (volatile unsigned short *)DMA1_7_X_MODIFY -#define pDMA1_7_Y_MODIFY (volatile unsigned short *)DMA1_7_Y_MODIFY -#define pDMA1_7_CURR_DESC_PTR (volatile void **)DMA1_7_CURR_DESC_PTR -#define pDMA1_7_CURR_ADDR (volatile void **)DMA1_7_CURR_ADDR -#define pDMA1_7_CURR_X_COUNT (volatile unsigned short *)DMA1_7_CURR_X_COUNT -#define pDMA1_7_CURR_Y_COUNT (volatile unsigned short *)DMA1_7_CURR_Y_COUNT -#define pDMA1_7_IRQ_STATUS (volatile unsigned short *)DMA1_7_IRQ_STATUS -#define pDMA1_7_PERIPHERAL_MAP (volatile unsigned short *)DMA1_7_PERIPHERAL_MAP -#define pDMA1_8_CONFIG (volatile unsigned short *)DMA1_8_CONFIG -#define pDMA1_8_NEXT_DESC_PTR (volatile void **)DMA1_8_NEXT_DESC_PTR -#define pDMA1_8_START_ADDR (volatile void **)DMA1_8_START_ADDR -#define pDMA1_8_X_COUNT (volatile unsigned short *)DMA1_8_X_COUNT -#define pDMA1_8_Y_COUNT (volatile unsigned short *)DMA1_8_Y_COUNT -#define pDMA1_8_X_MODIFY (volatile unsigned short *)DMA1_8_X_MODIFY -#define pDMA1_8_Y_MODIFY (volatile unsigned short *)DMA1_8_Y_MODIFY -#define pDMA1_8_CURR_DESC_PTR (volatile void **)DMA1_8_CURR_DESC_PTR -#define pDMA1_8_CURR_ADDR (volatile void **)DMA1_8_CURR_ADDR -#define pDMA1_8_CURR_X_COUNT (volatile unsigned short *)DMA1_8_CURR_X_COUNT -#define pDMA1_8_CURR_Y_COUNT (volatile unsigned short *)DMA1_8_CURR_Y_COUNT -#define pDMA1_8_IRQ_STATUS (volatile unsigned short *)DMA1_8_IRQ_STATUS -#define pDMA1_8_PERIPHERAL_MAP (volatile unsigned short *)DMA1_8_PERIPHERAL_MAP -#define pDMA1_9_CONFIG (volatile unsigned short *)DMA1_9_CONFIG -#define pDMA1_9_NEXT_DESC_PTR (volatile void **)DMA1_9_NEXT_DESC_PTR -#define pDMA1_9_START_ADDR (volatile void **)DMA1_9_START_ADDR -#define pDMA1_9_X_COUNT (volatile unsigned short *)DMA1_9_X_COUNT -#define pDMA1_9_Y_COUNT (volatile unsigned short *)DMA1_9_Y_COUNT -#define pDMA1_9_X_MODIFY (volatile unsigned short *)DMA1_9_X_MODIFY -#define pDMA1_9_Y_MODIFY (volatile unsigned short *)DMA1_9_Y_MODIFY -#define pDMA1_9_CURR_DESC_PTR (volatile void **)DMA1_9_CURR_DESC_PTR -#define pDMA1_9_CURR_ADDR (volatile void **)DMA1_9_CURR_ADDR -#define pDMA1_9_CURR_X_COUNT (volatile unsigned short *)DMA1_9_CURR_X_COUNT -#define pDMA1_9_CURR_Y_COUNT (volatile unsigned short *)DMA1_9_CURR_Y_COUNT -#define pDMA1_9_IRQ_STATUS (volatile unsigned short *)DMA1_9_IRQ_STATUS -#define pDMA1_9_PERIPHERAL_MAP (volatile unsigned short *)DMA1_9_PERIPHERAL_MAP -#define pDMA1_10_CONFIG (volatile unsigned short *)DMA1_10_CONFIG -#define pDMA1_10_NEXT_DESC_PTR (volatile void **)DMA1_10_NEXT_DESC_PTR -#define pDMA1_10_START_ADDR (volatile void **)DMA1_10_START_ADDR -#define pDMA1_10_X_COUNT (volatile unsigned short *)DMA1_10_X_COUNT -#define pDMA1_10_Y_COUNT (volatile unsigned short *)DMA1_10_Y_COUNT -#define pDMA1_10_X_MODIFY (volatile unsigned short *)DMA1_10_X_MODIFY -#define pDMA1_10_Y_MODIFY (volatile unsigned short *)DMA1_10_Y_MODIFY -#define pDMA1_10_CURR_DESC_PTR (volatile void **)DMA1_10_CURR_DESC_PTR -#define pDMA1_10_CURR_ADDR (volatile void **)DMA1_10_CURR_ADDR -#define pDMA1_10_CURR_X_COUNT (volatile unsigned short *)DMA1_10_CURR_X_COUNT -#define pDMA1_10_CURR_Y_COUNT (volatile unsigned short *)DMA1_10_CURR_Y_COUNT -#define pDMA1_10_IRQ_STATUS (volatile unsigned short *)DMA1_10_IRQ_STATUS -#define pDMA1_10_PERIPHERAL_MAP (volatile unsigned short *)DMA1_10_PERIPHERAL_MAP -#define pDMA1_11_CONFIG (volatile unsigned short *)DMA1_11_CONFIG -#define pDMA1_11_NEXT_DESC_PTR (volatile void **)DMA1_11_NEXT_DESC_PTR -#define pDMA1_11_START_ADDR (volatile void **)DMA1_11_START_ADDR -#define pDMA1_11_X_COUNT (volatile unsigned short *)DMA1_11_X_COUNT -#define pDMA1_11_Y_COUNT (volatile unsigned short *)DMA1_11_Y_COUNT -#define pDMA1_11_X_MODIFY (volatile signed short *)DMA1_11_X_MODIFY -#define pDMA1_11_Y_MODIFY (volatile signed short *)DMA1_11_Y_MODIFY -#define pDMA1_11_CURR_DESC_PTR (volatile void **)DMA1_11_CURR_DESC_PTR -#define pDMA1_11_CURR_ADDR (volatile void **)DMA1_11_CURR_ADDR -#define pDMA1_11_CURR_X_COUNT (volatile unsigned short *)DMA1_11_CURR_X_COUNT -#define pDMA1_11_CURR_Y_COUNT (volatile unsigned short *)DMA1_11_CURR_Y_COUNT -#define pDMA1_11_IRQ_STATUS (volatile unsigned short *)DMA1_11_IRQ_STATUS -#define pDMA1_11_PERIPHERAL_MAP (volatile unsigned short *)DMA1_11_PERIPHERAL_MAP - -/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF)*/ -#define pMDMA1_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG -#define pMDMA1_D0_NEXT_DESC_PTR (volatile void **)MDMA1_D0_NEXT_DESC_PTR -#define pMDMA1_D0_START_ADDR (volatile void **)MDMA1_D0_START_ADDR -#define pMDMA1_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT -#define pMDMA1_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT -#define pMDMA1_D0_X_MODIFY (volatile signed short *)MDMA1_D0_X_MODIFY -#define pMDMA1_D0_Y_MODIFY (volatile signed short *)MDMA1_D0_Y_MODIFY -#define pMDMA1_D0_CURR_DESC_PTR (volatile void **)MDMA1_D0_CURR_DESC_PTR -#define pMDMA1_D0_CURR_ADDR (volatile void **)MDMA1_D0_CURR_ADDR -#define pMDMA1_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT -#define pMDMA1_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT -#define pMDMA1_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS -#define pMDMA1_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP -#define pMDMA1_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG -#define pMDMA1_S0_NEXT_DESC_PTR (volatile void **)MDMA1_S0_NEXT_DESC_PTR -#define pMDMA1_S0_START_ADDR (volatile void **)MDMA1_S0_START_ADDR -#define pMDMA1_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT -#define pMDMA1_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT -#define pMDMA1_S0_X_MODIFY (volatile signed short *)MDMA1_S0_X_MODIFY -#define pMDMA1_S0_Y_MODIFY (volatile signed short *)MDMA1_S0_Y_MODIFY -#define pMDMA1_S0_CURR_DESC_PTR (volatile void **)MDMA1_S0_CURR_DESC_PTR -#define pMDMA1_S0_CURR_ADDR (volatile void **)MDMA1_S0_CURR_ADDR -#define pMDMA1_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT -#define pMDMA1_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT -#define pMDMA1_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS -#define pMDMA1_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP -#define pMDMA1_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG -#define pMDMA1_D1_NEXT_DESC_PTR (volatile void **)MDMA1_D1_NEXT_DESC_PTR -#define pMDMA1_D1_START_ADDR (volatile void **)MDMA1_D1_START_ADDR -#define pMDMA1_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT -#define pMDMA1_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT -#define pMDMA1_D1_X_MODIFY (volatile signed short *)MDMA1_D1_X_MODIFY -#define pMDMA1_D1_Y_MODIFY (volatile signed short *)MDMA1_D1_Y_MODIFY -#define pMDMA1_D1_CURR_DESC_PTR (volatile void **)MDMA1_D1_CURR_DESC_PTR -#define pMDMA1_D1_CURR_ADDR (volatile void **)MDMA1_D1_CURR_ADDR -#define pMDMA1_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT -#define pMDMA1_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT -#define pMDMA1_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS -#define pMDMA1_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP -#define pMDMA1_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG -#define pMDMA1_S1_NEXT_DESC_PTR (volatile void **)MDMA1_S1_NEXT_DESC_PTR -#define pMDMA1_S1_START_ADDR (volatile void **)MDMA1_S1_START_ADDR -#define pMDMA1_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT -#define pMDMA1_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT -#define pMDMA1_S1_X_MODIFY (volatile signed short *)MDMA1_S1_X_MODIFY -#define pMDMA1_S1_Y_MODIFY (volatile signed short *)MDMA1_S1_Y_MODIFY -#define pMDMA1_S1_CURR_DESC_PTR (volatile void **)MDMA1_S1_CURR_DESC_PTR -#define pMDMA1_S1_CURR_ADDR (volatile void **)MDMA1_S1_CURR_ADDR -#define pMDMA1_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT -#define pMDMA1_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT -#define pMDMA1_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS -#define pMDMA1_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP - -/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ -#define pDMA2_0_CONFIG (volatile unsigned short *)DMA2_0_CONFIG -#define pDMA2_0_NEXT_DESC_PTR (volatile void **)DMA2_0_NEXT_DESC_PTR -#define pDMA2_0_START_ADDR (volatile void **)DMA2_0_START_ADDR -#define pDMA2_0_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT -#define pDMA2_0_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT -#define pDMA2_0_X_MODIFY (volatile signed short *)DMA2_0_X_MODIFY -#define pDMA2_0_Y_MODIFY (volatile signed short *)DMA2_0_Y_MODIFY -#define pDMA2_0_CURR_DESC_PTR (volatile void **)DMA2_0_CURR_DESC_PTR -#define pDMA2_0_CURR_ADDR (volatile void **)DMA2_0_CURR_ADDR -#define pDMA2_0_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT -#define pDMA2_0_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT -#define pDMA2_0_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS -#define pDMA2_0_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP -#define pDMA2_1_CONFIG (volatile unsigned short *)DMA2_1_CONFIG -#define pDMA2_1_NEXT_DESC_PTR (volatile void **)DMA2_1_NEXT_DESC_PTR -#define pDMA2_1_START_ADDR (volatile void **)DMA2_1_START_ADDR -#define pDMA2_1_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT -#define pDMA2_1_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT -#define pDMA2_1_X_MODIFY (volatile signed short *)DMA2_1_X_MODIFY -#define pDMA2_1_Y_MODIFY (volatile signed short *)DMA2_1_Y_MODIFY -#define pDMA2_1_CURR_DESC_PTR (volatile void **)DMA2_1_CURR_DESC_PTR -#define pDMA2_1_CURR_ADDR (volatile void **)DMA2_1_CURR_ADDR -#define pDMA2_1_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT -#define pDMA2_1_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT -#define pDMA2_1_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS -#define pDMA2_1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP -#define pDMA2_2_CONFIG (volatile unsigned short *)DMA2_2_CONFIG -#define pDMA2_2_NEXT_DESC_PTR (volatile void **)DMA2_2_NEXT_DESC_PTR -#define pDMA2_2_START_ADDR (volatile void **)DMA2_2_START_ADDR -#define pDMA2_2_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT -#define pDMA2_2_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT -#define pDMA2_2_X_MODIFY (volatile signed short *)DMA2_2_X_MODIFY -#define pDMA2_2_Y_MODIFY (volatile signed short *)DMA2_2_Y_MODIFY -#define pDMA2_2_CURR_DESC_PTR (volatile void **)DMA2_2_CURR_DESC_PTR -#define pDMA2_2_CURR_ADDR (volatile void **)DMA2_2_CURR_ADDR -#define pDMA2_2_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT -#define pDMA2_2_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT -#define pDMA2_2_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS -#define pDMA2_2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP -#define pDMA2_3_CONFIG (volatile unsigned short *)DMA2_3_CONFIG -#define pDMA2_3_NEXT_DESC_PTR (volatile void **)DMA2_3_NEXT_DESC_PTR -#define pDMA2_3_START_ADDR (volatile void **)DMA2_3_START_ADDR -#define pDMA2_3_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT -#define pDMA2_3_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT -#define pDMA2_3_X_MODIFY (volatile signed short *)DMA2_3_X_MODIFY -#define pDMA2_3_Y_MODIFY (volatile signed short *)DMA2_3_Y_MODIFY -#define pDMA2_3_CURR_DESC_PTR (volatile void **)DMA2_3_CURR_DESC_PTR -#define pDMA2_3_CURR_ADDR (volatile void **)DMA2_3_CURR_ADDR -#define pDMA2_3_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT -#define pDMA2_3_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT -#define pDMA2_3_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS -#define pDMA2_3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP -#define pDMA2_4_CONFIG (volatile unsigned short *)DMA2_4_CONFIG -#define pDMA2_4_NEXT_DESC_PTR (volatile void **)DMA2_4_NEXT_DESC_PTR -#define pDMA2_4_START_ADDR (volatile void **)DMA2_4_START_ADDR -#define pDMA2_4_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT -#define pDMA2_4_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT -#define pDMA2_4_X_MODIFY (volatile signed short *)DMA2_4_X_MODIFY -#define pDMA2_4_Y_MODIFY (volatile signed short *)DMA2_4_Y_MODIFY -#define pDMA2_4_CURR_DESC_PTR (volatile void **)DMA2_4_CURR_DESC_PTR -#define pDMA2_4_CURR_ADDR (volatile void **)DMA2_4_CURR_ADDR -#define pDMA2_4_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT -#define pDMA2_4_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT -#define pDMA2_4_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS -#define pDMA2_4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP -#define pDMA2_5_CONFIG (volatile unsigned short *)DMA2_5_CONFIG -#define pDMA2_5_NEXT_DESC_PTR (volatile void **)DMA2_5_NEXT_DESC_PTR -#define pDMA2_5_START_ADDR (volatile void **)DMA2_5_START_ADDR -#define pDMA2_5_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT -#define pDMA2_5_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT -#define pDMA2_5_X_MODIFY (volatile signed short *)DMA2_5_X_MODIFY -#define pDMA2_5_Y_MODIFY (volatile signed short *)DMA2_5_Y_MODIFY -#define pDMA2_5_CURR_DESC_PTR (volatile void **)DMA2_5_CURR_DESC_PTR -#define pDMA2_5_CURR_ADDR (volatile void **)DMA2_5_CURR_ADDR -#define pDMA2_5_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT -#define pDMA2_5_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT -#define pDMA2_5_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS -#define pDMA2_5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP -#define pDMA2_6_CONFIG (volatile unsigned short *)DMA2_6_CONFIG -#define pDMA2_6_NEXT_DESC_PTR (volatile void **)DMA2_6_NEXT_DESC_PTR -#define pDMA2_6_START_ADDR (volatile void **)DMA2_6_START_ADDR -#define pDMA2_6_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT -#define pDMA2_6_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT -#define pDMA2_6_X_MODIFY (volatile signed short *)DMA2_6_X_MODIFY -#define pDMA2_6_Y_MODIFY (volatile signed short *)DMA2_6_Y_MODIFY -#define pDMA2_6_CURR_DESC_PTR (volatile void **)DMA2_6_CURR_DESC_PTR -#define pDMA2_6_CURR_ADDR (volatile void **)DMA2_6_CURR_ADDR -#define pDMA2_6_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT -#define pDMA2_6_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT -#define pDMA2_6_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS -#define pDMA2_6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP -#define pDMA2_7_CONFIG (volatile unsigned short *)DMA2_7_CONFIG -#define pDMA2_7_NEXT_DESC_PTR (volatile void **)DMA2_7_NEXT_DESC_PTR -#define pDMA2_7_START_ADDR (volatile void **)DMA2_7_START_ADDR -#define pDMA2_7_X_COUNT (volatile unsigned short *)DMA2_7_X_COUNT -#define pDMA2_7_Y_COUNT (volatile unsigned short *)DMA2_7_Y_COUNT -#define pDMA2_7_X_MODIFY (volatile signed short *)DMA2_7_X_MODIFY -#define pDMA2_7_Y_MODIFY (volatile signed short *)DMA2_7_Y_MODIFY -#define pDMA2_7_CURR_DESC_PTR (volatile void **)DMA2_7_CURR_DESC_PTR -#define pDMA2_7_CURR_ADDR (volatile void **)DMA2_7_CURR_ADDR -#define pDMA2_7_CURR_X_COUNT (volatile unsigned short *)DMA2_7_CURR_X_COUNT -#define pDMA2_7_CURR_Y_COUNT (volatile unsigned short *)DMA2_7_CURR_Y_COUNT -#define pDMA2_7_IRQ_STATUS (volatile unsigned short *)DMA2_7_IRQ_STATUS -#define pDMA2_7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_7_PERIPHERAL_MAP -#define pDMA2_8_CONFIG (volatile unsigned short *)DMA2_8_CONFIG -#define pDMA2_8_NEXT_DESC_PTR (volatile void **)DMA2_8_NEXT_DESC_PTR -#define pDMA2_8_START_ADDR (volatile void **)DMA2_8_START_ADDR -#define pDMA2_8_X_COUNT (volatile unsigned short *)DMA2_8_X_COUNT -#define pDMA2_8_Y_COUNT (volatile unsigned short *)DMA2_8_Y_COUNT -#define pDMA2_8_X_MODIFY (volatile signed short *)DMA2_8_X_MODIFY -#define pDMA2_8_Y_MODIFY (volatile signed short *)DMA2_8_Y_MODIFY -#define pDMA2_8_CURR_DESC_PTR (volatile void **)DMA2_8_CURR_DESC_PTR -#define pDMA2_8_CURR_ADDR (volatile void **)DMA2_8_CURR_ADDR -#define pDMA2_8_CURR_X_COUNT (volatile unsigned short *)DMA2_8_CURR_X_COUNT -#define pDMA2_8_CURR_Y_COUNT (volatile unsigned short *)DMA2_8_CURR_Y_COUNT -#define pDMA2_8_IRQ_STATUS (volatile unsigned short *)DMA2_8_IRQ_STATUS -#define pDMA2_8_PERIPHERAL_MAP (volatile unsigned short *)DMA2_8_PERIPHERAL_MAP -#define pDMA2_9_CONFIG (volatile unsigned short *)DMA2_9_CONFIG -#define pDMA2_9_NEXT_DESC_PTR (volatile void **)DMA2_9_NEXT_DESC_PTR -#define pDMA2_9_START_ADDR (volatile void **)DMA2_9_START_ADDR -#define pDMA2_9_X_COUNT (volatile unsigned short *)DMA2_9_X_COUNT -#define pDMA2_9_Y_COUNT (volatile unsigned short *)DMA2_9_Y_COUNT -#define pDMA2_9_X_MODIFY (volatile signed short *)DMA2_9_X_MODIFY -#define pDMA2_9_Y_MODIFY (volatile signed short *)DMA2_9_Y_MODIFY -#define pDMA2_9_CURR_DESC_PTR (volatile void **)DMA2_9_CURR_DESC_PTR -#define pDMA2_9_CURR_ADDR (volatile void **)DMA2_9_CURR_ADDR -#define pDMA2_9_CURR_X_COUNT (volatile unsigned short *)DMA2_9_CURR_X_COUNT -#define pDMA2_9_CURR_Y_COUNT (volatile unsigned short *)DMA2_9_CURR_Y_COUNT -#define pDMA2_9_IRQ_STATUS (volatile unsigned short *)DMA2_9_IRQ_STATUS -#define pDMA2_9_PERIPHERAL_MAP (volatile unsigned short *)DMA2_9_PERIPHERAL_MAP -#define pDMA2_10_CONFIG (volatile unsigned short *)DMA2_10_CONFIG -#define pDMA2_10_NEXT_DESC_PTR (volatile void **)DMA2_10_NEXT_DESC_PTR -#define pDMA2_10_START_ADDR (volatile void **)DMA2_10_START_ADDR -#define pDMA2_10_X_COUNT (volatile unsigned short *)DMA2_10_X_COUNT -#define pDMA2_10_Y_COUNT (volatile unsigned short *)DMA2_10_Y_COUNT -#define pDMA2_10_X_MODIFY (volatile signed short *)DMA2_10_X_MODIFY -#define pDMA2_10_Y_MODIFY (volatile signed short *)DMA2_10_Y_MODIFY -#define pDMA2_10_CURR_DESC_PTR (volatile void **)DMA2_10_CURR_DESC_PTR -#define pDMA2_10_CURR_ADDR (volatile void **)DMA2_10_CURR_ADDR -#define pDMA2_10_CURR_X_COUNT (volatile unsigned short *)DMA2_10_CURR_X_COUNT -#define pDMA2_10_CURR_Y_COUNT (volatile unsigned short *)DMA2_10_CURR_Y_COUNT -#define pDMA2_10_IRQ_STATUS (volatile unsigned short *)DMA2_10_IRQ_STATUS -#define pDMA2_10_PERIPHERAL_MAP (volatile unsigned short *)DMA2_10_PERIPHERAL_MAP -#define pDMA2_11_CONFIG (volatile unsigned short *)DMA2_11_CONFIG -#define pDMA2_11_NEXT_DESC_PTR (volatile void **)DMA2_11_NEXT_DESC_PTR -#define pDMA2_11_START_ADDR (volatile void **)DMA2_11_START_ADDR -#define pDMA2_11_X_COUNT (volatile unsigned short *)DMA2_11_X_COUNT -#define pDMA2_11_Y_COUNT (volatile unsigned short *)DMA2_11_Y_COUNT -#define pDMA2_11_X_MODIFY (volatile signed short *)DMA2_11_X_MODIFY -#define pDMA2_11_Y_MODIFY (volatile signed short *)DMA2_11_Y_MODIFY -#define pDMA2_11_CURR_DESC_PTR (volatile void **)DMA2_11_CURR_DESC_PTR -#define pDMA2_11_CURR_ADDR (volatile void **)DMA2_11_CURR_ADDR -#define pDMA2_11_CURR_X_COUNT (volatile unsigned short *)DMA2_11_CURR_X_COUNT -#define pDMA2_11_CURR_Y_COUNT (volatile unsigned short *)DMA2_11_CURR_Y_COUNT -#define pDMA2_11_IRQ_STATUS (volatile unsigned short *)DMA2_11_IRQ_STATUS -#define pDMA2_11_PERIPHERAL_MAP (volatile unsigned short *)DMA2_11_PERIPHERAL_MAP - -/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ -#define pMDMA2_D0_CONFIG (volatile unsigned short *)MDMA2_D0_CONFIG -#define pMDMA2_D0_NEXT_DESC_PTR (volatile void **)MDMA2_D0_NEXT_DESC_PTR -#define pMDMA2_D0_START_ADDR (volatile void **)MDMA2_D0_START_ADDR -#define pMDMA2_D0_X_COUNT (volatile unsigned short *)MDMA2_D0_X_COUNT -#define pMDMA2_D0_Y_COUNT (volatile unsigned short *)MDMA2_D0_Y_COUNT -#define pMDMA2_D0_X_MODIFY (volatile signed short *)MDMA2_D0_X_MODIFY -#define pMDMA2_D0_Y_MODIFY (volatile signed short *)MDMA2_D0_Y_MODIFY -#define pMDMA2_D0_CURR_DESC_PTR (volatile void **)MDMA2_D0_CURR_DESC_PTR -#define pMDMA2_D0_CURR_ADDR (volatile void **)MDMA2_D0_CURR_ADDR -#define pMDMA2_D0_CURR_X_COUNT (volatile unsigned short *)MDMA2_D0_CURR_X_COUNT -#define pMDMA2_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D0_CURR_Y_COUNT -#define pMDMA2_D0_IRQ_STATUS (volatile unsigned short *)MDMA2_D0_IRQ_STATUS -#define pMDMA2_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D0_PERIPHERAL_MAP -#define pMDMA2_S0_CONFIG (volatile unsigned short *)MDMA2_S0_CONFIG -#define pMDMA2_S0_NEXT_DESC_PTR (volatile void **)MDMA2_S0_NEXT_DESC_PTR -#define pMDMA2_S0_START_ADDR (volatile void **)MDMA2_S0_START_ADDR -#define pMDMA2_S0_X_COUNT (volatile unsigned short *)MDMA2_S0_X_COUNT -#define pMDMA2_S0_Y_COUNT (volatile unsigned short *)MDMA2_S0_Y_COUNT -#define pMDMA2_S0_X_MODIFY (volatile signed short *)MDMA2_S0_X_MODIFY -#define pMDMA2_S0_Y_MODIFY (volatile signed short *)MDMA2_S0_Y_MODIFY -#define pMDMA2_S0_CURR_DESC_PTR (volatile void **)MDMA2_S0_CURR_DESC_PTR -#define pMDMA2_S0_CURR_ADDR (volatile void **)MDMA2_S0_CURR_ADDR -#define pMDMA2_S0_CURR_X_COUNT (volatile unsigned short *)MDMA2_S0_CURR_X_COUNT -#define pMDMA2_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S0_CURR_Y_COUNT -#define pMDMA2_S0_IRQ_STATUS (volatile unsigned short *)MDMA2_S0_IRQ_STATUS -#define pMDMA2_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S0_PERIPHERAL_MAP -#define pMDMA2_D1_CONFIG (volatile unsigned short *)MDMA2_D1_CONFIG -#define pMDMA2_D1_NEXT_DESC_PTR (volatile void **)MDMA2_D1_NEXT_DESC_PTR -#define pMDMA2_D1_START_ADDR (volatile void **)MDMA2_D1_START_ADDR -#define pMDMA2_D1_X_COUNT (volatile unsigned short *)MDMA2_D1_X_COUNT -#define pMDMA2_D1_Y_COUNT (volatile unsigned short *)MDMA2_D1_Y_COUNT -#define pMDMA2_D1_X_MODIFY (volatile signed short *)MDMA2_D1_X_MODIFY -#define pMDMA2_D1_Y_MODIFY (volatile signed short *)MDMA2_D1_Y_MODIFY -#define pMDMA2_D1_CURR_DESC_PTR (volatile void **)MDMA2_D1_CURR_DESC_PTR -#define pMDMA2_D1_CURR_ADDR (volatile void **)MDMA2_D1_CURR_ADDR -#define pMDMA2_D1_CURR_X_COUNT (volatile unsigned short *)MDMA2_D1_CURR_X_COUNT -#define pMDMA2_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D1_CURR_Y_COUNT -#define pMDMA2_D1_IRQ_STATUS (volatile unsigned short *)MDMA2_D1_IRQ_STATUS -#define pMDMA2_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D1_PERIPHERAL_MAP -#define pMDMA2_S1_CONFIG (volatile unsigned short *)MDMA2_S1_CONFIG -#define pMDMA2_S1_NEXT_DESC_PTR (volatile void **)MDMA2_S1_NEXT_DESC_PTR -#define pMDMA2_S1_START_ADDR (volatile void **)MDMA2_S1_START_ADDR -#define pMDMA2_S1_X_COUNT (volatile unsigned short *)MDMA2_S1_X_COUNT -#define pMDMA2_S1_Y_COUNT (volatile unsigned short *)MDMA2_S1_Y_COUNT -#define pMDMA2_S1_X_MODIFY (volatile signed short *)MDMA2_S1_X_MODIFY -#define pMDMA2_S1_Y_MODIFY (volatile signed short *)MDMA2_S1_Y_MODIFY -#define pMDMA2_S1_CURR_DESC_PTR (volatile void **)MDMA2_S1_CURR_DESC_PTR -#define pMDMA2_S1_CURR_ADDR (volatile void **)MDMA2_S1_CURR_ADDR -#define pMDMA2_S1_CURR_X_COUNT (volatile unsigned short *)MDMA2_S1_CURR_X_COUNT -#define pMDMA2_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S1_CURR_Y_COUNT -#define pMDMA2_S1_IRQ_STATUS (volatile unsigned short *)MDMA2_S1_IRQ_STATUS -#define pMDMA2_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S1_PERIPHERAL_MAP - -/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ -#define pIMDMA_D0_CONFIG (volatile unsigned short *)IMDMA_D0_CONFIG -#define pIMDMA_D0_NEXT_DESC_PTR (volatile void **)IMDMA_D0_NEXT_DESC_PTR -#define pIMDMA_D0_START_ADDR (volatile void **)IMDMA_D0_START_ADDR -#define pIMDMA_D0_X_COUNT (volatile unsigned short *)IMDMA_D0_X_COUNT -#define pIMDMA_D0_Y_COUNT (volatile unsigned short *)IMDMA_D0_Y_COUNT -#define pIMDMA_D0_X_MODIFY (volatile signed short *)IMDMA_D0_X_MODIFY -#define pIMDMA_D0_Y_MODIFY (volatile signed short *)IMDMA_D0_Y_MODIFY -#define pIMDMA_D0_CURR_DESC_PTR (volatile void **)IMDMA_D0_CURR_DESC_PTR -#define pIMDMA_D0_CURR_ADDR (volatile void **)IMDMA_D0_CURR_ADDR -#define pIMDMA_D0_CURR_X_COUNT (volatile unsigned short *)IMDMA_D0_CURR_X_COUNT -#define pIMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D0_CURR_Y_COUNT -#define pIMDMA_D0_IRQ_STATUS (volatile unsigned short *)IMDMA_D0_IRQ_STATUS -#define pIMDMA_S0_CONFIG (volatile unsigned short *)IMDMA_S0_CONFIG -#define pIMDMA_S0_NEXT_DESC_PTR (volatile void **)IMDMA_S0_NEXT_DESC_PTR -#define pIMDMA_S0_START_ADDR (volatile void **)IMDMA_S0_START_ADDR -#define pIMDMA_S0_X_COUNT (volatile unsigned short *)IMDMA_S0_X_COUNT -#define pIMDMA_S0_Y_COUNT (volatile unsigned short *)IMDMA_S0_Y_COUNT -#define pIMDMA_S0_X_MODIFY (volatile signed short *)IMDMA_S0_X_MODIFY -#define pIMDMA_S0_Y_MODIFY (volatile signed short *)IMDMA_S0_Y_MODIFY -#define pIMDMA_S0_CURR_DESC_PTR (volatile void **)IMDMA_S0_CURR_DESC_PTR -#define pIMDMA_S0_CURR_ADDR (volatile void **)IMDMA_S0_CURR_ADDR -#define pIMDMA_S0_CURR_X_COUNT (volatile unsigned short *)IMDMA_S0_CURR_X_COUNT -#define pIMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S0_CURR_Y_COUNT -#define pIMDMA_S0_IRQ_STATUS (volatile unsigned short *)IMDMA_S0_IRQ_STATUS -#define pIMDMA_D1_CONFIG (volatile unsigned short *)IMDMA_D1_CONFIG -#define pIMDMA_D1_NEXT_DESC_PTR (volatile void **)IMDMA_D1_NEXT_DESC_PTR -#define pIMDMA_D1_START_ADDR (volatile void **)IMDMA_D1_START_ADDR -#define pIMDMA_D1_X_COUNT (volatile unsigned short *)IMDMA_D1_X_COUNT -#define pIMDMA_D1_Y_COUNT (volatile unsigned short *)IMDMA_D1_Y_COUNT -#define pIMDMA_D1_X_MODIFY (volatile signed short *)IMDMA_D1_X_MODIFY -#define pIMDMA_D1_Y_MODIFY (volatile signed short *)IMDMA_D1_Y_MODIFY -#define pIMDMA_D1_CURR_DESC_PTR (volatile void **)IMDMA_D1_CURR_DESC_PTR -#define pIMDMA_D1_CURR_ADDR (volatile void **)IMDMA_D1_CURR_ADDR -#define pIMDMA_D1_CURR_X_COUNT (volatile unsigned short *)IMDMA_D1_CURR_X_COUNT -#define pIMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D1_CURR_Y_COUNT -#define pIMDMA_D1_IRQ_STATUS (volatile unsigned short *)IMDMA_D1_IRQ_STATUS -#define pIMDMA_S1_CONFIG (volatile unsigned short *)IMDMA_S1_CONFIG -#define pIMDMA_S1_NEXT_DESC_PTR (volatile void **)IMDMA_S1_NEXT_DESC_PTR -#define pIMDMA_S1_START_ADDR (volatile void **)IMDMA_S1_START_ADDR -#define pIMDMA_S1_X_COUNT (volatile unsigned short *)IMDMA_S1_X_COUNT -#define pIMDMA_S1_Y_COUNT (volatile unsigned short *)IMDMA_S1_Y_COUNT -#define pIMDMA_S1_X_MODIFY (volatile signed short *)IMDMA_S1_X_MODIFY -#define pIMDMA_S1_Y_MODIFY (volatile signed short *)IMDMA_S1_Y_MODIFY -#define pIMDMA_S1_CURR_DESC_PTR (volatile void **)IMDMA_S1_CURR_DESC_PTR -#define pIMDMA_S1_CURR_ADDR (volatile void **)IMDMA_S1_CURR_ADDR -#define pIMDMA_S1_CURR_X_COUNT (volatile unsigned short *)IMDMA_S1_CURR_X_COUNT -#define pIMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S1_CURR_Y_COUNT -#define pIMDMA_S1_IRQ_STATUS (volatile unsigned short *)IMDMA_S1_IRQ_STATUS - -#if 1 /* comment by mhfan */ -/* - * System Reset and Interrupt Controller registers for - * core A (0xFFC0 0100-0xFFC0 01FF) - */ -#define pSWRST (volatile unsigned short *)SICA_SWRST -#define pSYSCR (volatile unsigned short *)SICA_SYSCR -#define pRVECT (volatile unsigned short *)SICA_RVECT -#define pSIC_SWRST (volatile unsigned short *)SICA_SWRST -#define pSIC_SYSCR (volatile unsigned short *)SICA_SYSCR -#define pSIC_RVECT (volatile unsigned short *)SICA_RVECT -#define pSIC_IMASK (volatile unsigned long *)SICA_IMASK -#define pSIC_IAR0 ((volatile unsigned long *)SICA_IAR0) -#define pSIC_IAR1 (volatile unsigned long *)SICA_IAR1 -#define pSIC_IAR2 (volatile unsigned long *)SICA_IAR2 -#define pSIC_ISR (volatile unsigned long *)SICA_ISR0 -#define pSIC_IWR (volatile unsigned long *)SICA_IWR0 - -/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ -#define pWDOG_CTL (volatile unsigned short *)WDOGA_CTL -#define pWDOG_CNT (volatile unsigned long *)WDOGA_CNT -#define pWDOG_STAT (volatile unsigned long *)WDOGA_STAT -#endif /* comment by mhfan */ - -/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ -#define pFIO_FLAG_D (volatile unsigned short *)FIO0_FLAG_D -#define pFIO_FLAG_C (volatile unsigned short *)FIO0_FLAG_C -#define pFIO_FLAG_S (volatile unsigned short *)FIO0_FLAG_S -#define pFIO_FLAG_T (volatile unsigned short *)FIO0_FLAG_T -#define pFIO_MASKA_D (volatile unsigned short *)FIO0_MASKA_D -#define pFIO_MASKA_C (volatile unsigned short *)FIO0_MASKA_C -#define pFIO_MASKA_S (volatile unsigned short *)FIO0_MASKA_S -#define pFIO_MASKA_T (volatile unsigned short *)FIO0_MASKA_T -#define pFIO_MASKB_D (volatile unsigned short *)FIO0_MASKB_D -#define pFIO_MASKB_C (volatile unsigned short *)FIO0_MASKB_C -#define pFIO_MASKB_S (volatile unsigned short *)FIO0_MASKB_S -#define pFIO_MASKB_T (volatile unsigned short *)FIO0_MASKB_T -#define pFIO_DIR (volatile unsigned short *)FIO0_DIR -#define pFIO_POLAR (volatile unsigned short *)FIO0_POLAR -#define pFIO_EDGE (volatile unsigned short *)FIO0_EDGE -#define pFIO_BOTH (volatile unsigned short *)FIO0_BOTH -#define pFIO_INEN (volatile unsigned short *)FIO0_INEN - -/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/ -#define pPPI_CONTROL (volatile unsigned short *)PPI0_CONTROL -#define pPPI_STATUS (volatile unsigned short *)PPI0_STATUS -#define pPPI_COUNT (volatile unsigned short *)PPI0_COUNT -#define pPPI_DELAY (volatile unsigned short *)PPI0_DELAY -#define pPPI_FRAME (volatile unsigned short *)PPI0_FRAME - -/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ -#define pDMA0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG -#define pDMA0_NEXT_DESC_PTR (volatile void **)DMA1_0_NEXT_DESC_PTR -#define pDMA0_START_ADDR (volatile void **)DMA1_0_START_ADDR -#define pDMA0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT -#define pDMA0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT -#define pDMA0_X_MODIFY (volatile unsigned short *)DMA1_0_X_MODIFY -#define pDMA0_Y_MODIFY (volatile unsigned short *)DMA1_0_Y_MODIFY -#define pDMA0_CURR_DESC_PTR (volatile void **)DMA1_0_CURR_DESC_PTR -#define pDMA0_CURR_ADDR (volatile void **)DMA1_0_CURR_ADDR -#define pDMA0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT -#define pDMA0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT -#define pDMA0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS -#define pDMA0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP - -/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ -#define pMDMA_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG -#define pMDMA_D0_NEXT_DESC_PTR (volatile void **)MDMA1_D0_NEXT_DESC_PTR -#define pMDMA_D0_START_ADDR (volatile void **)MDMA1_D0_START_ADDR -#define pMDMA_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT -#define pMDMA_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT -#define pMDMA_D0_X_MODIFY (volatile unsigned short *)MDMA1_D0_X_MODIFY -#define pMDMA_D0_Y_MODIFY (volatile unsigned short *)MDMA1_D0_Y_MODIFY -#define pMDMA_D0_CURR_DESC_PTR (volatile void **)MDMA1_D0_CURR_DESC_PTR -#define pMDMA_D0_CURR_ADDR (volatile void **)MDMA1_D0_CURR_ADDR -#define pMDMA_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT -#define pMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT -#define pMDMA_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS -#define pMDMA_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP -#define pMDMA_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG -#define pMDMA_S0_NEXT_DESC_PTR (volatile void **)MDMA1_S0_NEXT_DESC_PTR -#define pMDMA_S0_START_ADDR (volatile void **)MDMA1_S0_START_ADDR -#define pMDMA_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT -#define pMDMA_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT -#define pMDMA_S0_X_MODIFY (volatile unsigned short *)MDMA1_S0_X_MODIFY -#define pMDMA_S0_Y_MODIFY (volatile unsigned short *)MDMA1_S0_Y_MODIFY -#define pMDMA_S0_CURR_DESC_PTR (volatile void **)MDMA1_S0_CURR_DESC_PTR -#define pMDMA_S0_CURR_ADDR (volatile void **)MDMA1_S0_CURR_ADDR -#define pMDMA_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT -#define pMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT -#define pMDMA_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS -#define pMDMA_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP -#define pMDMA_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG -#define pMDMA_D1_NEXT_DESC_PTR (volatile void **)MDMA1_D1_NEXT_DESC_PTR -#define pMDMA_D1_START_ADDR (volatile void **)MDMA1_D1_START_ADDR -#define pMDMA_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT -#define pMDMA_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT -#define pMDMA_D1_X_MODIFY (volatile unsigned short *)MDMA1_D1_X_MODIFY -#define pMDMA_D1_Y_MODIFY (volatile unsigned short *)MDMA1_D1_Y_MODIFY -#define pMDMA_D1_CURR_DESC_PTR (volatile void **)MDMA1_D1_CURR_DESC_PTR -#define pMDMA_D1_CURR_ADDR (volatile void **)MDMA1_D1_CURR_ADDR -#define pMDMA_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT -#define pMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT -#define pMDMA_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS -#define pMDMA_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP -#define pMDMA_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG -#define pMDMA_S1_NEXT_DESC_PTR (volatile void **)MDMA1_S1_NEXT_DESC_PTR -#define pMDMA_S1_START_ADDR (volatile void **)MDMA1_S1_START_ADDR -#define pMDMA_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT -#define pMDMA_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT -#define pMDMA_S1_X_MODIFY (volatile unsigned short *)MDMA1_S1_X_MODIFY -#define pMDMA_S1_Y_MODIFY (volatile unsigned short *)MDMA1_S1_Y_MODIFY -#define pMDMA_S1_CURR_DESC_PTR (volatile void **)MDMA1_S1_CURR_DESC_PTR -#define pMDMA_S1_CURR_ADDR (volatile void **)MDMA1_S1_CURR_ADDR -#define pMDMA_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT -#define pMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT -#define pMDMA_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS -#define pMDMA_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP - -/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ -#define pDMA1_CONFIG (volatile unsigned short *)DMA2_0_CONFIG -#define pDMA1_NEXT_DESC_PTR (volatile void **)DMA2_0_NEXT_DESC_PTR -#define pDMA1_START_ADDR (volatile void **)DMA2_0_START_ADDR -#define pDMA1_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT -#define pDMA1_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT -#define pDMA1_X_MODIFY (volatile unsigned short *)DMA2_0_X_MODIFY -#define pDMA1_Y_MODIFY (volatile unsigned short *)DMA2_0_Y_MODIFY -#define pDMA1_CURR_DESC_PTR (volatile void **)DMA2_0_CURR_DESC_PTR -#define pDMA1_CURR_ADDR (volatile void **)DMA2_0_CURR_ADDR -#define pDMA1_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT -#define pDMA1_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT -#define pDMA1_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS -#define pDMA1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP -#define pDMA2_CONFIG (volatile unsigned short *)DMA2_1_CONFIG -#define pDMA2_NEXT_DESC_PTR (volatile void **)DMA2_1_NEXT_DESC_PTR -#define pDMA2_START_ADDR (volatile void **)DMA2_1_START_ADDR -#define pDMA2_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT -#define pDMA2_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT -#define pDMA2_X_MODIFY (volatile unsigned short *)DMA2_1_X_MODIFY -#define pDMA2_Y_MODIFY (volatile unsigned short *)DMA2_1_Y_MODIFY -#define pDMA2_CURR_DESC_PTR (volatile void **)DMA2_1_CURR_DESC_PTR -#define pDMA2_CURR_ADDR (volatile void **)DMA2_1_CURR_ADDR -#define pDMA2_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT -#define pDMA2_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT -#define pDMA2_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS -#define pDMA2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP -#define pDMA3_CONFIG (volatile unsigned short *)DMA2_2_CONFIG -#define pDMA3_NEXT_DESC_PTR (volatile void **)DMA2_2_NEXT_DESC_PTR -#define pDMA3_START_ADDR (volatile void **)DMA2_2_START_ADDR -#define pDMA3_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT -#define pDMA3_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT -#define pDMA3_X_MODIFY (volatile unsigned short *)DMA2_2_X_MODIFY -#define pDMA3_Y_MODIFY (volatile unsigned short *)DMA2_2_Y_MODIFY -#define pDMA3_CURR_DESC_PTR (volatile void **)DMA2_2_CURR_DESC_PTR -#define pDMA3_CURR_ADDR (volatile void **)DMA2_2_CURR_ADDR -#define pDMA3_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT -#define pDMA3_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT -#define pDMA3_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS -#define pDMA3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP -#define pDMA4_CONFIG (volatile unsigned short *)DMA2_3_CONFIG -#define pDMA4_NEXT_DESC_PTR (volatile void **)DMA2_3_NEXT_DESC_PTR -#define pDMA4_START_ADDR (volatile void **)DMA2_3_START_ADDR -#define pDMA4_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT -#define pDMA4_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT -#define pDMA4_X_MODIFY (volatile unsigned short *)DMA2_3_X_MODIFY -#define pDMA4_Y_MODIFY (volatile unsigned short *)DMA2_3_Y_MODIFY -#define pDMA4_CURR_DESC_PTR (volatile void **)DMA2_3_CURR_DESC_PTR -#define pDMA4_CURR_ADDR (volatile void **)DMA2_3_CURR_ADDR -#define pDMA4_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT -#define pDMA4_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT -#define pDMA4_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS -#define pDMA4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP -#define pDMA5_CONFIG (volatile unsigned short *)DMA2_4_CONFIG -#define pDMA5_NEXT_DESC_PTR (volatile void **)DMA2_4_NEXT_DESC_PTR -#define pDMA5_START_ADDR (volatile void **)DMA2_4_START_ADDR -#define pDMA5_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT -#define pDMA5_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT -#define pDMA5_X_MODIFY (volatile unsigned short *)DMA2_4_X_MODIFY -#define pDMA5_Y_MODIFY (volatile unsigned short *)DMA2_4_Y_MODIFY -#define pDMA5_CURR_DESC_PTR (volatile void **)DMA2_4_CURR_DESC_PTR -#define pDMA5_CURR_ADDR (volatile void **)DMA2_4_CURR_ADDR -#define pDMA5_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT -#define pDMA5_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT -#define pDMA5_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS -#define pDMA5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP -#define pDMA6_CONFIG (volatile unsigned short *)DMA2_5_CONFIG -#define pDMA6_NEXT_DESC_PTR (volatile void **)DMA2_5_NEXT_DESC_PTR -#define pDMA6_START_ADDR (volatile void **)DMA2_5_START_ADDR -#define pDMA6_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT -#define pDMA6_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT -#define pDMA6_X_MODIFY (volatile unsigned short *)DMA2_5_X_MODIFY -#define pDMA6_Y_MODIFY (volatile unsigned short *)DMA2_5_Y_MODIFY -#define pDMA6_CURR_DESC_PTR (volatile void **)DMA2_5_CURR_DESC_PTR -#define pDMA6_CURR_ADDR (volatile void **)DMA2_5_CURR_ADDR -#define pDMA6_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT -#define pDMA6_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT -#define pDMA6_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS -#define pDMA6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP -#define pDMA7_CONFIG (volatile unsigned short *)DMA2_6_CONFIG -#define pDMA7_NEXT_DESC_PTR (volatile void **)DMA2_6_NEXT_DESC_PTR -#define pDMA7_START_ADDR (volatile void **)DMA2_6_START_ADDR -#define pDMA7_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT -#define pDMA7_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT -#define pDMA7_X_MODIFY (volatile unsigned short *)DMA2_6_X_MODIFY -#define pDMA7_Y_MODIFY (volatile unsigned short *)DMA2_6_Y_MODIFY -#define pDMA7_CURR_DESC_PTR (volatile void **)DMA2_6_CURR_DESC_PTR -#define pDMA7_CURR_ADDR (volatile void **)DMA2_6_CURR_ADDR -#define pDMA7_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT -#define pDMA7_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT -#define pDMA7_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS -#define pDMA7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP - -#endif /* _CDEF_BF561_H */ diff --git a/include/asm-blackfin/cpu/cdef_LPBlackfin.h b/include/asm-blackfin/cpu/cdef_LPBlackfin.h deleted file mode 100644 index e6471cbcb3..0000000000 --- a/include/asm-blackfin/cpu/cdef_LPBlackfin.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * cdef_LPBlackfin.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _CDEF_LPBLACKFIN_H -#define _CDEF_LPBLACKFIN_H - -/* - * #if !defined(__ADSPLPBLACKFIN__) - * #warning cdef_LPBlackfin.h should only be included for 532 compatible chips. - * #endif - */ -#include <asm/cpu/def_LPBlackfin.h> - -/* Cache & SRAM Memory */ -#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS) -#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL) -#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS) -#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR) - -/* #define MMR_TIMEOUT 0xFFE00010 */ /* Memory-Mapped Register Timeout Register */ -#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0) -#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1) -#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2) -#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3) -#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4) -#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5) -#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6) -#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7) -#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8) -#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9) -#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10) -#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11) -#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12) -#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13) -#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14) -#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15) -#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0) -#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1) -#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2) -#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3) -#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4) -#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5) -#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6) -#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7) -#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8) -#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9) -#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10) -#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11) -#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12) -#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13) -#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14) -#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15) -#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND) - -/* #define DTEST_INDEX 0xFFE00304 */ /* Data Test Index Register */ -#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0) -#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1) - -/* - * # define DTEST_DATA2 0xFFE00408 Data Test Data Register - * #define DTEST_DATA3 0xFFE0040C Data Test Data Register - */ -#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL) -#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS) -#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR) -#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0) -#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1) -#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2) -#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3) -#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4) -#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5) -#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6) -#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7) -#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8) -#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9) -#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10) -#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11) -#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12) -#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13) -#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14) -#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15) -#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0) -#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1) -#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2) -#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3) -#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4) -#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5) -#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6) -#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7) -#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8) -#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9) -#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10) -#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11) -#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12) -#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13) -#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14) -#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15) -#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND) - -/* #define ITEST_INDEX 0xFFE01304 */ /* Instruction Test Index Register */ -#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0) -#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1) - -/* Event/Interrupt Registers */ -#define pEVT0 ((volatile void **)EVT0) -#define pEVT1 ((volatile void **)EVT1) -#define pEVT2 ((volatile void **)EVT2) -#define pEVT3 ((volatile void **)EVT3) -#define pEVT4 ((volatile void **)EVT4) -#define pEVT5 ((volatile void **)EVT5) -#define pEVT6 ((volatile void **)EVT6) -#define pEVT7 ((volatile void **)EVT7) -#define pEVT8 ((volatile void **)EVT8) -#define pEVT9 ((volatile void **)EVT9) -#define pEVT10 ((volatile void **)EVT10) -#define pEVT11 ((volatile void **)EVT11) -#define pEVT12 ((volatile void **)EVT12) -#define pEVT13 ((volatile void **)EVT13) -#define pEVT14 ((volatile void **)EVT14) -#define pEVT15 ((volatile void **)EVT15) -#define pIMASK ((volatile unsigned long *)IMASK) -#define pIPEND ((volatile unsigned long *)IPEND) -#define pILAT ((volatile unsigned long *)ILAT) - -/* Core Timer Registers */ -#define pTCNTL ((volatile unsigned long *)TCNTL) -#define pTPERIOD ((volatile unsigned long *)TPERIOD) -#define pTSCALE ((volatile unsigned long *)TSCALE) -#define pTCOUNT ((volatile unsigned long *)TCOUNT) - -/* Debug/MP/Emulation Registers */ -#define pDSPID ((volatile unsigned long *)DSPID) -#define pDBGCTL ((volatile unsigned long *)DBGCTL) -#define pDBGSTAT ((volatile unsigned long *)DBGSTAT) -#define pEMUDAT ((volatile unsigned long *)EMUDAT) - -/* Trace Buffer Registers */ -#define pTBUFCTL ((volatile unsigned long *)TBUFCTL) -#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT) -#define pTBUF ((volatile void **)TBUF) - -/* Watch Point Control Registers */ -#define pWPIACTL ((volatile unsigned long *)WPIACTL) -#define pWPIA0 ((volatile void **)WPIA0) -#define pWPIA1 ((volatile void **)WPIA1) -#define pWPIA2 ((volatile void **)WPIA2) -#define pWPIA3 ((volatile void **)WPIA3) -#define pWPIA4 ((volatile void **)WPIA4) -#define pWPIA5 ((volatile void **)WPIA5) -#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0) -#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1) -#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2) -#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3) -#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4) -#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5) -#define pWPDACTL ((volatile unsigned long *)WPDACTL) -#define pWPDA0 ((volatile void **)WPDA0) -#define pWPDA1 ((volatile void **)WPDA1) -#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0) -#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1) -#define pWPSTAT ((volatile unsigned long *)WPSTAT) - -/* Performance Monitor Registers */ -#define pPFCTL ((volatile unsigned long *)PFCTL) -#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0) -#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1) - -/* #define IPRIO 0xFFE02110 */ /* Core Interrupt Priority Register */ - -#endif /* _CDEF_LPBLACKFIN_H */ diff --git a/include/asm-blackfin/cpu/defBF531.h b/include/asm-blackfin/cpu/defBF531.h deleted file mode 100644 index 6c7cd5a6db..0000000000 --- a/include/asm-blackfin/cpu/defBF531.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * defBF531.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _DEFBF531_H -#define _DEFBF531_H - -#include <defBF532.h> - -#endif /* _DEFBF531_H */ diff --git a/include/asm-blackfin/cpu/defBF532.h b/include/asm-blackfin/cpu/defBF532.h deleted file mode 100644 index 65853ed434..0000000000 --- a/include/asm-blackfin/cpu/defBF532.h +++ /dev/null @@ -1,1148 +0,0 @@ -/* - * defBF532.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ - -#ifndef _DEF_BF532_H -#define _DEF_BF532_H - -/* - * #if !defined(__ADSPLPBLACKFIN__) - * #warning defBF532.h should only be included for 532 compatible chips - * #endif - */ - -/* include all Core registers and bit definitions */ -#include <asm/cpu/def_LPBlackfin.h> - -/* - * System MMR Register Map - */ - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ -#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ -#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */ -#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ -#define SYSCR 0xFFC00104 /* System Configuration register */ - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ -#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ - -/* UART Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART_THR 0xFFC00400 /* Transmit Holding register */ -#define UART_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART_LCR 0xFFC0040C /* Line Control Register */ -#define UART_MCR 0xFFC00410 /* Modem Control Register */ -#define UART_LSR 0xFFC00414 /* Line Status Register */ -/* #define UART_MSR 0xFFC00418 */ /* Modem Status Register (UNUSED in ADSP-BF532) */ -#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART_GCTL 0xFFC00424 /* Global Control Register */ - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ - -/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ - -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ - -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ - -#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */ -#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ -#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ -#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ -#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ -#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ -#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ -#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ -#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ -#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ -#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ -#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ -#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ -#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ -#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ -#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ -#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ -#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - -/* Asynchronous Memory Controller - External Bus Interface Unit */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ - -/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - -/* DMA Test Registers */ -#define DMA_CCOMP 0xFFC00B04 /* DMA Cycle Count Register */ -#define DMA_ACOMP 0xFFC00B00 /* Debug Compare Address Register */ -#define DMA_MISR 0xFFC00B08 /* MISR Register */ -#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ -#define DMA_TMODE 0xFFC00B14 /* DMA Test Modes Register */ -#define DMA_TMCHAN 0xFFC00B18 /* DMA Testmode Selected Channel Register */ -#define DMA_TMSTAT 0xFFC00B1C /* DMA Testmode Channel Status Register */ -#define DMA_TMBD 0xFFC00B20 /* DMA Testmode DAB Bus Data Register */ -#define DMA_TMM0D 0xFFC00B24 /* DMA Testmode Mem0 Data Register */ -#define DMA_TMM1D 0xFFC00B28 /* DMA Testmode Mem1 Data Register */ -#define DMA_TMMA 0xFFC00B2C /* DMA Testmode Memory Address Register */ - -/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ - -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ - -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ - -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ - -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ - -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ - -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ - -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ - -#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */ - -#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */ - -#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */ - -#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */ - -/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ - -/* - * System MMR Register Bits - */ -/* - * PLL AND RESET MASKS - */ - -/* PLL_CTL Masks */ -#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ -#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ -#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ -#define STOPCK_OFF 0x00000008 /* Core clock off */ -#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ -#define BYPASS 0x00000100 /* Bypass the PLL */ - -/* PLL_DIV Masks */ -#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ - -#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ -#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ -#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ -#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ - -/* SWRST Mask */ -#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ - -/* - * SYSTEM INTERRUPT CONTROLLER MASKS - */ - -/* SIC_IAR0 Masks */ -#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */ -#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ -#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ -#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */ -#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ -#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ -#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ -#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ - -/* SIC_IAR1 Masks */ -#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */ -#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ -#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ -#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */ -#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ -#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ -#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ -#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ - -/* SIC_IAR2 Masks */ -#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */ -#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ -#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ -#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */ -#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ -#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ -#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ -#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ - -/* SIC_IMASK Masks */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ - -/* SIC_IWR Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ - -/* - * WATCHDOG TIMER MASKS - */ -/* Watchdog Timer WDOG_CTL Register */ -#define ICTL(x) ((x<<1) & 0x0006) -#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */ -#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */ -#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */ -#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */ - -#define TMR_EN 0x0000 -#define TMR_DIS 0x0AD0 -#define TRO 0x8000 - -#define ICTL_P0 0x01 -#define ICTL_P1 0x02 -#define TRO_P 0x0F - -/* RTC_STAT and RTC_ALARM register */ -#define RTSEC 0x0000003F /* Real-Time Clock Seconds */ -#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */ -#define RTHR 0x0001F000 /* Real-Time Clock Hours */ -#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */ - -/* RTC_ICTL register */ -#define SWIE 0x0001 /* Stopwatch Interrupt Enable */ -#define AIE 0x0002 /* Alarm Interrupt Enable */ -#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */ -#define MIE 0x0008 /* Minutes Interrupt Enable */ -#define HIE 0x0010 /* Hours Interrupt Enable */ -#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */ -#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ -#define WCIE 0x8000 /* Write Complete Interrupt Enable */ - -/* RTC_ISTAT register */ -#define SWEF 0x0001 /* Stopwatch Event Flag */ -#define AEF 0x0002 /* Alarm Event Flag */ -#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */ -#define MEF 0x0008 /* Minutes Event Flag */ -#define HEF 0x0010 /* Hours Event Flag */ -#define DEF 0x0020 /* 24 Hours (Days) Event Flag */ -#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */ -#define WPS 0x4000 /* Write Pending Status (RO) */ -#define WCOM 0x8000 /* Write Complete */ - -/* RTC_FAST Mask (RTC_PREN Mask) */ -#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */ -#define PREN 0x00000001 /* ** Must be set after power-up for proper operation of RTC */ - -/* - * UART CONTROLLER MASKS - */ - -/* UART_LCR Register */ -#define DLAB 0x80 -#define SB 0x40 -#define STP 0x20 -#define EPS 0x10 -#define PEN 0x08 -#define STB 0x04 -#define WLS(x) ((x-5) & 0x03) - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -/* UART_MCR Register */ -#define LOOP_ENA 0x10 -#define LOOP_ENA_P 0x04 - -/* UART_LSR Register */ -#define TEMT 0x40 -#define THRE 0x20 -#define BI 0x10 -#define FE 0x08 -#define PE 0x04 -#define OE 0x02 -#define DR 0x01 - -#define TEMP_P 0x06 -#define THRE_P 0x05 -#define BI_P 0x04 -#define FE_P 0x03 -#define PE_P 0x02 -#define OE_P 0x01 -#define DR_P 0x00 - -/* UART_IER Register */ -#define ELSI 0x04 -#define ETBEI 0x02 -#define ERBFI 0x01 - -#define ELSI_P 0x02 -#define ETBEI_P 0x01 -#define ERBFI_P 0x00 - -/* UART_IIR Register */ -#define STATUS(x) ((x << 1) & 0x06) -#define NINT 0x01 -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 -#define NINT_P 0x00 - -/* UART_GCTL Register */ -#define FFE 0x20 -#define FPE 0x10 -#define RPOLC 0x08 -#define TPOLC 0x04 -#define IREN 0x02 -#define UCEN 0x01 - -#define FFE_P 0x05 -#define FPE_P 0x04 -#define RPOLC_P 0x03 -#define TPOLC_P 0x02 -#define IREN_P 0x01 -#define UCEN_P 0x00 - -/* - * SERIAL PORT MASKS - */ -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 /* TX enable */ -#define ITCLK 0x0002 /* Internal TX Clock Select */ -#define TDTYPE 0x000C /* TX Data Formatting Select */ -#define TLSBIT 0x0010 /* TX Bit Order */ -#define ITFS 0x0200 /* Internal TX Frame Sync Select */ -#define TFSR 0x0400 /* TX Frame Sync Required Select */ -#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ -#define LTFS 0x1000 /* Low TX Frame Sync Select */ -#define LATFS 0x2000 /* Late TX Frame Sync Select */ -#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ - -/* SPORTx_TCR2 Masks */ -#define SLEN 0x001F /*TX Word Length */ -#define TXSE 0x0100 /*TX Secondary Enable */ -#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ -#define TRFST 0x0400 /*TX Right-First Data Order */ - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 /* RX enable */ -#define IRCLK 0x0002 /* Internal RX Clock Select */ -#define RDTYPE 0x000C /* RX Data Formatting Select */ -#define RULAW 0x0008 /* u-Law enable */ -#define RALAW 0x000C /* A-Law enable */ -#define RLSBIT 0x0010 /* RX Bit Order */ -#define IRFS 0x0200 /* Internal RX Frame Sync Select */ -#define RFSR 0x0400 /* RX Frame Sync Required Select */ -#define LRFS 0x1000 /* Low RX Frame Sync Select */ -#define LARFS 0x2000 /* Late RX Frame Sync Select */ -#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ - -/* SPORTx_RCR2 Masks */ -#define SLEN 0x001F /* RX Word Length */ -#define RXSE 0x0100 /* RX Secondary Enable */ -#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ -#define RRFST 0x0400 /* Right-First Data Order */ - -/* SPORTx_STAT Masks */ -#define RXNE 0x0001 /* RX FIFO Not Empty Status */ -#define RUVF 0x0002 /* RX Underflow Status */ -#define ROVF 0x0004 /* RX Overflow Status */ -#define TXF 0x0008 /* TX FIFO Full Status */ -#define TUVF 0x0010 /* TX Underflow Status */ -#define TOVF 0x0020 /* TX Overflow Status */ -#define TXHRE 0x0040 /* TX Hold Register Empty */ - -/* SPORTx_MCMC1 Masks */ -#define WSIZE 0x0000F000 /* Multichannel Window Size Field */ -#define WOFF 0x000003FF /* /Multichannel Window Offset Field */ - -/* SPORTx_MCMC2 Masks */ -#define MCCRM 0x00000003 /* Multichannel Clock Recovery Mode */ -#define MCDTXPE 0x00000004 /* Multichannel DMA Transmit Packing */ -#define MCDRXPE 0x00000008 /* Multichannel DMA Receive Packing */ -#define MCMEN 0x00000010 /* Multichannel Frame Mode Enable */ -#define FSDR 0x00000080 /* Multichannel Frame Sync to Data Relationship */ -#define MFD 0x0000F000 /* Multichannel Frame Delay */ - -/* - * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS - */ - -/* PPI_CONTROL Masks */ -#define PORT_EN 0x00000001 /* PPI Port Enable */ -#define PORT_DIR 0x00000002 /* PPI Port Direction */ -#define XFR_TYPE 0x0000000C /* PPI Transfer Type */ -#define PORT_CFG 0x00000030 /* PPI Port Configuration */ -#define FLD_SEL 0x00000040 /* PPI Active Field Select */ -#define PACK_EN 0x00000080 /* PPI Packing Mode */ -#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ -#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ -#define DLENGTH 0x00003800 /* PPI Data Length */ -#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ -#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ -#define POL 0x0000C000 /* PPI Signal Polarities */ - -/* PPI_STATUS Masks */ -#define FLD 0x00000400 /* Field Indicator */ -#define FT_ERR 0x00000800 /* Frame Track Error */ -#define OVR 0x00001000 /* FIFO Overflow Error */ -#define UNDR 0x00002000 /* FIFO Underrun Error */ -#define ERR_DET 0x00004000 /* Error Detected Indicator */ -#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ - -/* - * DMA CONTROLLER MASKS - */ - -/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ -#define DMAEN 0x00000001 /* Channel Enable */ -#define WNR 0x00000002 /* Channel Direction (W/R*) */ -#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ -#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ -#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ -#define DMA2D 0x00000010 /* 2D/1D* Mode */ -#define RESTART 0x00000020 /* Restart */ -#define DI_SEL 0x00000040 /* Data Interrupt Select */ -#define DI_EN 0x00000080 /* Data Interrupt Enable */ -#define NDSIZE 0x00000900 /* Next Descriptor Size */ -#define FLOW 0x00007000 /* Flow Control */ - -#define DMAEN_P 0 /* Channel Enable */ -#define WNR_P 1 /* Channel Direction (W/R*) */ -#define DMA2D_P 4 /* 2D/1D* Mode */ -#define RESTART_P 5 /* Restart */ -#define DI_SEL_P 6 /* Data Interrupt Select */ -#define DI_EN_P 7 /* Data Interrupt Enable */ - -/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ -#define DMA_DONE 0x00000001 /* DMA Done Indicator */ -#define DMA_ERR 0x00000002 /* DMA Error Indicator */ -#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ -#define DMA_RUN 0x00000008 /* DMA Running Indicator */ - -#define DMA_DONE_P 0 /* DMA Done Indicator */ -#define DMA_ERR_P 1 /* DMA Error Indicator */ -#define DFETCH_P 2 /* Descriptor Fetch Indicator */ -#define DMA_RUN_P 3 /* DMA Running Indicator */ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ -#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ -#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ -#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ -#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ -#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ -#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ -#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ -#define PMAP 0x00007000 /* DMA Peripheral Map Field */ - -/* - * GENERAL PURPOSE TIMER MASKS - */ - -/* PWM Timer bit definitions */ - -/* TIMER_ENABLE Register */ -#define TIMEN0 0x0001 -#define TIMEN1 0x0002 -#define TIMEN2 0x0004 - -#define TIMEN0_P 0x00 -#define TIMEN1_P 0x01 -#define TIMEN2_P 0x02 - -/* TIMER_DISABLE Register */ -#define TIMDIS0 0x0001 -#define TIMDIS1 0x0002 -#define TIMDIS2 0x0004 - -#define TIMDIS0_P 0x00 -#define TIMDIS1_P 0x01 -#define TIMDIS2_P 0x02 - -/* TIMER_STATUS Register */ -#define TIMIL0 0x0001 -#define TIMIL1 0x0002 -#define TIMIL2 0x0004 -#define TOVL_ERR0 0x0010 -#define TOVL_ERR1 0x0020 -#define TOVL_ERR2 0x0040 -#define TRUN0 0x1000 -#define TRUN1 0x2000 -#define TRUN2 0x4000 - -#define TIMIL0_P 0x00 -#define TIMIL1_P 0x01 -#define TIMIL2_P 0x02 -#define TOVL_ERR0_P 0x04 -#define TOVL_ERR1_P 0x05 -#define TOVL_ERR2_P 0x06 -#define TRUN0_P 0x0C -#define TRUN1_P 0x0D -#define TRUN2_P 0x0E - -/* TIMERx_CONFIG Registers */ -#define PWM_OUT 0x0001 -#define WDTH_CAP 0x0002 -#define EXT_CLK 0x0003 -#define PULSE_HI 0x0004 -#define PERIOD_CNT 0x0008 -#define IRQ_ENA 0x0010 -#define TIN_SEL 0x0020 -#define OUT_DIS 0x0040 -#define CLK_SEL 0x0080 -#define TOGGLE_HI 0x0100 -#define EMU_RUN 0x0200 -#define ERR_TYP(x) ((x & 0x03) << 14) - -#define TMODE_P0 0x00 -#define TMODE_P1 0x01 -#define PULSE_HI_P 0x02 -#define PERIOD_CNT_P 0x03 -#define IRQ_ENA_P 0x04 -#define TIN_SEL_P 0x05 -#define OUT_DIS_P 0x06 -#define CLK_SEL_P 0x07 -#define TOGGLE_HI_P 0x08 -#define EMU_RUN_P 0x09 -#define ERR_TYP_P0 0x0E -#define ERR_TYP_P1 0x0F - -/* - * PROGRAMMABLE FLAG MASKS - */ - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ -#define PF0_P 0 -#define PF1_P 1 -#define PF2_P 2 -#define PF3_P 3 -#define PF4_P 4 -#define PF5_P 5 -#define PF6_P 6 -#define PF7_P 7 -#define PF8_P 8 -#define PF9_P 9 -#define PF10_P 10 -#define PF11_P 11 -#define PF12_P 12 -#define PF13_P 13 -#define PF14_P 14 -#define PF15_P 15 - -/* - * SERIAL PERIPHERAL INTERFACE (SPI) MASKS - */ - -/* SPI_CTL Masks */ -#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ -#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ -#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ -#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ -#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ -#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ -#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ -#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ -#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ -#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ -#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ -#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ - -/* SPI_FLG Masks */ -#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_FLG Bit Positions */ -#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_STAT Masks */ -#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ -#define MODF 0x00000002 /* Set(=1)in a master device when some other device tries to become master */ -#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ -#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ -#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ -#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ -#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ - -/* - * ASYNCHRONOUS MEMORY CONTROLLER MASKS - */ - -/* AMGCTL Masks */ -#define AMCKEN 0x00000001 /* Enable CLKOUT */ -#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */ -#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ - -/* AMGCTL Bit Positions */ -#define AMCKEN_P 0x00000000 /* Enable CLKOUT */ -#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ -#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ -#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ - -/* AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ -#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ -#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ -#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ -#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ -#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ -#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ -#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ -#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ -#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ -#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ -#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ -#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ -#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ -#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ -#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ -#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ -#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ -#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ -#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ -#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ -#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ - -/* AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ -#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ -#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ -#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ -#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ -#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ -#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ -#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ -#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ -#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ -#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ -#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ -#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ -#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ - -/* - * SDRAM CONTROLLER MASKS - */ - -/* SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ -#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ -#define PFE 0x00000010 /* Enable SDRAM prefetch */ -#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /* Power-up start delay */ -#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ -#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ -#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ -#define EBUFE 0x02000000 /* Enable external buffering timing */ -#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ -#define EMREN 0x10000000 /* Extended mode register enable */ -#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ -#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ - -/* EBIU_SDBCTL Masks */ -#define EBE 0x00000001 /* Enable SDRAM external bank */ -#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ -#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ -#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ -#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ -#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ -#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ -#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ -#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x00000001 /* SDRAM controller is idle */ -#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ -#define SDPUA 0x00000004 /* SDRAM power up active */ -#define SDRS 0x00000008 /* SDRAM is in reset state */ -#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ -#define BGSTAT 0x00000020 /* Bus granted */ - -#endif /* _DEF_BF532_H */ diff --git a/include/asm-blackfin/cpu/defBF533.h b/include/asm-blackfin/cpu/defBF533.h deleted file mode 100644 index 90e50afa7f..0000000000 --- a/include/asm-blackfin/cpu/defBF533.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * defBF533.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _DEFBF533_H -#define _DEFBF533_H - -#include <asm/cpu/defBF532.h> - -#endif /* _DEFBF533_H */ diff --git a/include/asm-blackfin/cpu/defBF533_extn.h b/include/asm-blackfin/cpu/defBF533_extn.h deleted file mode 100644 index a9a1c7ccbd..0000000000 --- a/include/asm-blackfin/cpu/defBF533_extn.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * defBF533_extn.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _DEF_BF533_EXTN_H -#define _DEF_BF533_EXTN_H - -#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */ -/* Delay inserted for PLL transition */ -#define DELAY 0x1000 - -#define L1_ISRAM 0xFFA00000 -#define L1_ISRAM_END 0xFFA10000 -#define DATA_BANKA_SRAM 0xFF800000 -#define DATA_BANKA_SRAM_END 0xFF808000 -#define DATA_BANKB_SRAM 0xFF900000 -#define DATA_BANKB_SRAM_END 0xFF908000 -#define SYSMMR_BASE 0xFFC00000 -#define WDSIZE16 0x00000004 - -/* Event Vector Table Address */ -#define EVT_EMULATION_ADDR 0xffe02000 -#define EVT_RESET_ADDR 0xffe02004 -#define EVT_NMI_ADDR 0xffe02008 -#define EVT_EXCEPTION_ADDR 0xffe0200c -#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 -#define EVT_HARDWARE_ERROR_ADDR 0xffe02014 -#define EVT_TIMER_ADDR 0xffe02018 -#define EVT_IVG7_ADDR 0xffe0201c -#define EVT_IVG8_ADDR 0xffe02020 -#define EVT_IVG9_ADDR 0xffe02024 -#define EVT_IVG10_ADDR 0xffe02028 -#define EVT_IVG11_ADDR 0xffe0202c -#define EVT_IVG12_ADDR 0xffe02030 -#define EVT_IVG13_ADDR 0xffe02034 -#define EVT_IVG14_ADDR 0xffe02038 -#define EVT_IVG15_ADDR 0xffe0203c -#define EVT_OVERRIDE_ADDR 0xffe02100 - -/* IMASK Bit values */ -#define IVG15_POS 0x00008000 -#define IVG14_POS 0x00004000 -#define IVG13_POS 0x00002000 -#define IVG12_POS 0x00001000 -#define IVG11_POS 0x00000800 -#define IVG10_POS 0x00000400 -#define IVG9_POS 0x00000200 -#define IVG8_POS 0x00000100 -#define IVG7_POS 0x00000080 -#define IVGTMR_POS 0x00000040 -#define IVGHW_POS 0x00000020 - -#define WDOG_TMR_DISABLE (0xAD << 4) -#define ICTL_RST 0x00000000 -#define ICTL_NMI 0x00000002 -#define ICTL_GP 0x00000004 -#define ICTL_DISABLE 0x00000003 - -/* Watch Dog timer values setup */ -#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE - -#endif /* _DEF_BF533_EXTN_H */ diff --git a/include/asm-blackfin/cpu/defBF561.h b/include/asm-blackfin/cpu/defBF561.h deleted file mode 100644 index 11de2beb62..0000000000 --- a/include/asm-blackfin/cpu/defBF561.h +++ /dev/null @@ -1,3057 +0,0 @@ -/************************************************************************ - * - * defBF561.h - * - * (c) Copyright 2001-2003 Analog Devices, Inc. All rights reserved. - * - ************************************************************************/ - -/* SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */ - -#ifndef _DEF_BF561_H -#define _DEF_BF561_H - -/* - * #if !defined(__ADSPBF561__) - * #warning defBF561.h should only be included for BF561 chip. - * #endif - */ - -// include all Core registers and bit definitions -#include <asm/cpu/def_LPBlackfin.h> - -//***************************************************************************** -// System MMR Register Map -//***************************************************************************** - -//// Clock and System Control (0xFFC00000 - 0xFFC000FF) -#define PLL_CTL 0xFFC00000 // PLL Control register (16-bit) -#define PLL_DIV 0xFFC00004 // PLL Divide Register (16-bit) -#define VR_CTL 0xFFC00008 // Voltage Regulator - // Control Register (16-bit) -#define PLL_STAT 0xFFC0000C // PLL Status register (16-bit) -#define PLL_LOCKCNT 0xFFC00010 // PLL Lock Count register - // (16-bit) - -// System Reset and Interrupt Controller registers for -// core A (0xFFC0 0100-0xFFC0 01FF) -#define SICA_SWRST 0xFFC00100 // Software Reset register -#define SICA_SYSCR 0xFFC00104 // System Reset Configuration - // register -#define SICA_RVECT 0xFFC00108 // SIC Reset Vector Address - // Register -#define SICA_IMASK 0xFFC0010C // SIC Interrupt Mask - // register 0 - hack to fix - // old tests -#define SICA_IMASK0 0xFFC0010C // SIC Interrupt Mask - // register 0 -#define SICA_IMASK1 0xFFC00110 // SIC Interrupt Mask - // register 1 -#define SICA_IAR0 0xFFC00124 // SIC Interrupt Assignment - // Register 0 -#define SICA_IAR1 0xFFC00128 // SIC Interrupt Assignment - // Register 1 -#define SICA_IAR2 0xFFC0012C // SIC Interrupt Assignment - // Register 2 -#define SICA_IAR3 0xFFC00130 // SIC Interrupt Assignment - // Register 3 -#define SICA_IAR4 0xFFC00134 // SIC Interrupt Assignment - // Register 4 -#define SICA_IAR5 0xFFC00138 // SIC Interrupt Assignment - // Register 5 -#define SICA_IAR6 0xFFC0013C // SIC Interrupt Assignment - // Register 6 -#define SICA_IAR7 0xFFC00140 // SIC Interrupt Assignment - // Register 7 -#define SICA_ISR0 0xFFC00114 // SIC Interrupt Status - // register 0 -#define SICA_ISR1 0xFFC00118 // SIC Interrupt Status - // register 1 -#define SICA_IWR0 0xFFC0011C // SIC Interrupt - // Wakeup-Enable register 0 -#define SICA_IWR1 0xFFC00120 // SIC Interrupt - // Wakeup-Enable register 1 - -// System Reset and Interrupt Controller registers for -// Core B (0xFFC0 1100-0xFFC0 11FF) -#define SICB_SWRST 0xFFC01100 // reserved -#define SICB_SYSCR 0xFFC01104 // reserved -#define SICB_RVECT 0xFFC01108 // SIC Reset Vector Address - // Register -#define SICB_IMASK0 0xFFC0110C // SIC Interrupt Mask - // register 0 -#define SICB_IMASK1 0xFFC01110 // SIC Interrupt Mask - // register 1 -#define SICB_IAR0 0xFFC01124 // SIC Interrupt Assignment - // Register 0 -#define SICB_IAR1 0xFFC01128 // SIC Interrupt Assignment - // Register 1 -#define SICB_IAR2 0xFFC0112C // SIC Interrupt Assignment - // Register 2 -#define SICB_IAR3 0xFFC01130 // SIC Interrupt Assignment - // Register 3 -#define SICB_IAR4 0xFFC01134 // SIC Interrupt Assignment - // Register 4 -#define SICB_IAR5 0xFFC01138 // SIC Interrupt Assignment - // Register 5 -#define SICB_IAR6 0xFFC0113C // SIC Interrupt Assignment - // Register 6 -#define SICB_IAR7 0xFFC01140 // SIC Interrupt Assignment - // Register 7 -#define SICB_ISR0 0xFFC01114 // SIC Interrupt Status - // register 0 -#define SICB_ISR1 0xFFC01118 // SIC Interrupt Status - // register 1 -#define SICB_IWR0 0xFFC0111C // SIC Interrupt - // Wakeup-Enable register 0 -#define SICB_IWR1 0xFFC01120 // SIC Interrupt - // Wakeup-Enable register 1 - -// Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) -#define WDOGA_CTL 0xFFC00200 // Watchdog Control register -#define WDOGA_CNT 0xFFC00204 // Watchdog Count register -#define WDOGA_STAT 0xFFC00208 // Watchdog Status register - -// Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) -#define WDOGB_CTL 0xFFC01200 // Watchdog Control register -#define WDOGB_CNT 0xFFC01204 // Watchdog Count register -#define WDOGB_STAT 0xFFC01208 // Watchdog Status register - -// UART Controller (0xFFC00400 - 0xFFC004FF) -#define UART_THR 0xFFC00400 // Transmit Holding register -#define UART_RBR 0xFFC00400 // Receive Buffer register -#define UART_DLL 0xFFC00400 // Divisor Latch (Low-Byte) -#define UART_IER 0xFFC00404 // Interrupt Enable Register -#define UART_DLH 0xFFC00404 // Divisor Latch (High-Byte) -#define UART_IIR 0xFFC00408 // Interrupt Identification - // Register -#define UART_LCR 0xFFC0040C // Line Control Register -#define UART_MCR 0xFFC00410 // Modem Control Register -#define UART_LSR 0xFFC00414 // Line Status Register -#define UART_MSR 0xFFC00418 // Modem Status Register -#define UART_SCR 0xFFC0041C // SCR Scratch Register -#define UART_GCTL 0xFFC00424 // Global Control Register - -// SPI Controller (0xFFC00500 - 0xFFC005FF) -#define SPI_CTL 0xFFC00500 // SPI Control Register -#define SPI_FLG 0xFFC00504 // SPI Flag register -#define SPI_STAT 0xFFC00508 // SPI Status register -#define SPI_TDBR 0xFFC0050C // SPI Transmit Data - // Buffer Register -#define SPI_RDBR 0xFFC00510 // SPI Receive Data - // Buffer Register -#define SPI_BAUD 0xFFC00514 // SPI Baud rate - // Register -#define SPI_SHADOW 0xFFC00518 // SPI_RDBR Shadow - // Register - -// Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) -#define TIMER0_CONFIG 0xFFC00600 // Timer0 Configuration - // register -#define TIMER0_COUNTER 0xFFC00604 // Timer0 Counter register -#define TIMER0_PERIOD 0xFFC00608 // Timer0 Period register -#define TIMER0_WIDTH 0xFFC0060C // Timer0 Width register -#define TIMER1_CONFIG 0xFFC00610 // Timer1 Configuration - // register -#define TIMER1_COUNTER 0xFFC00614 // Timer1 Counter register -#define TIMER1_PERIOD 0xFFC00618 // Timer1 Period register -#define TIMER1_WIDTH 0xFFC0061C // Timer1 Width register -#define TIMER2_CONFIG 0xFFC00620 // Timer2 Configuration - // register -#define TIMER2_COUNTER 0xFFC00624 // Timer2 Counter register -#define TIMER2_PERIOD 0xFFC00628 // Timer2 Period register -#define TIMER2_WIDTH 0xFFC0062C // Timer2 Width register -#define TIMER3_CONFIG 0xFFC00630 // Timer3 Configuration - // register -#define TIMER3_COUNTER 0xFFC00634 // Timer3 Counter register -#define TIMER3_PERIOD 0xFFC00638 // Timer3 Period register -#define TIMER3_WIDTH 0xFFC0063C // Timer3 Width register -#define TIMER4_CONFIG 0xFFC00640 // Timer4 Configuration - // register -#define TIMER4_COUNTER 0xFFC00644 // Timer4 Counter register -#define TIMER4_PERIOD 0xFFC00648 // Timer4 Period register -#define TIMER4_WIDTH 0xFFC0064C // Timer4 Width register -#define TIMER5_CONFIG 0xFFC00650 // Timer5 Configuration - // register -#define TIMER5_COUNTER 0xFFC00654 // Timer5 Counter register -#define TIMER5_PERIOD 0xFFC00658 // Timer5 Period register -#define TIMER5_WIDTH 0xFFC0065C // Timer5 Width register -#define TIMER6_CONFIG 0xFFC00660 // Timer6 Configuration - // register -#define TIMER6_COUNTER 0xFFC00664 // Timer6 Counter register -#define TIMER6_PERIOD 0xFFC00668 // Timer6 Period register -#define TIMER6_WIDTH 0xFFC0066C // Timer6 Width register -#define TIMER7_CONFIG 0xFFC00670 // Timer7 Configuration - // register -#define TIMER7_COUNTER 0xFFC00674 // Timer7 Counter register -#define TIMER7_PERIOD 0xFFC00678 // Timer7 Period register -#define TIMER7_WIDTH 0xFFC0067C // Timer7 Width register - -#define TMRS8_ENABLE 0xFFC00680 // Timer Enable Register -#define TMRS8_DISABLE 0xFFC00684 // Timer Disable register -#define TMRS8_STATUS 0xFFC00688 // Timer Status register - -// Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) -#define TIMER8_CONFIG 0xFFC01600 // Timer8 Configuration - // register -#define TIMER8_COUNTER 0xFFC01604 // Timer8 Counter register -#define TIMER8_PERIOD 0xFFC01608 // Timer8 Period register -#define TIMER8_WIDTH 0xFFC0160C // Timer8 Width register -#define TIMER9_CONFIG 0xFFC01610 // Timer9 Configuration - // register -#define TIMER9_COUNTER 0xFFC01614 // Timer9 Counter register -#define TIMER9_PERIOD 0xFFC01618 // Timer9 Period register -#define TIMER9_WIDTH 0xFFC0161C // Timer9 Width register -#define TIMER10_CONFIG 0xFFC01620 // Timer10 Configuration - // register -#define TIMER10_COUNTER 0xFFC01624 // Timer10 Counter register -#define TIMER10_PERIOD 0xFFC01628 // Timer10 Period register -#define TIMER10_WIDTH 0xFFC0162C // Timer10 Width register -#define TIMER11_CONFIG 0xFFC01630 // Timer11 Configuration - // register -#define TIMER11_COUNTER 0xFFC01634 // Timer11 Counter register -#define TIMER11_PERIOD 0xFFC01638 // Timer11 Period register -#define TIMER11_WIDTH 0xFFC0163C // Timer11 Width register - -#define TMRS4_ENABLE 0xFFC01640 // Timer Enable Register -#define TMRS4_DISABLE 0xFFC01644 // Timer Disable register -#define TMRS4_STATUS 0xFFC01648 // Timer Status register - -// Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) -#define FIO0_FLAG_D 0xFFC00700 // Flag Data register -#define FIO0_FLAG_C 0xFFC00704 // Flag Clear register -#define FIO0_FLAG_S 0xFFC00708 // Flag Set register -#define FIO0_FLAG_T 0xFFC0070C // Flag Toggle register -#define FIO0_MASKA_D 0xFFC00710 // Flag Mask Interrupt A Data - // register -#define FIO0_MASKA_C 0xFFC00714 // Flag Mask Interrupt A Clear - // register -#define FIO0_MASKA_S 0xFFC00718 // Flag Mask Interrupt A Set - // register -#define FIO0_MASKA_T 0xFFC0071C // Flag Mask Interrupt A Toggle - // register -#define FIO0_MASKB_D 0xFFC00720 // Flag Mask Interrupt B Data - // register -#define FIO0_MASKB_C 0xFFC00724 // Flag Mask Interrupt B Clear - // register -#define FIO0_MASKB_S 0xFFC00728 // Flag Mask Interrupt B Set - // register -#define FIO0_MASKB_T 0xFFC0072C // Flag Mask Interrupt B Toggle - // register -#define FIO0_DIR 0xFFC00730 // Flag Direction register -#define FIO0_POLAR 0xFFC00734 // Flag Polarity register -#define FIO0_EDGE 0xFFC00738 // Flag Interrupt Sensitivity - // register -#define FIO0_BOTH 0xFFC0073C // Flag Set on Both Edges - // register -#define FIO0_INEN 0xFFC00740 // Flag Input Enable register - -// Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) -#define FIO1_FLAG_D 0xFFC01500 // Flag Data register -#define FIO1_FLAG_C 0xFFC01504 // Flag Clear register -#define FIO1_FLAG_S 0xFFC01508 // Flag Set register -#define FIO1_FLAG_T 0xFFC0150C // Flag Toggle register -#define FIO1_MASKA_D 0xFFC01510 // Flag Mask Interrupt A Data - // register -#define FIO1_MASKA_C 0xFFC01514 // Flag Mask Interrupt A Clear - // register -#define FIO1_MASKA_S 0xFFC01518 // Flag Mask Interrupt A Set - // register -#define FIO1_MASKA_T 0xFFC0151C // Flag Mask Interrupt A Toggle - // register -#define FIO1_MASKB_D 0xFFC01520 // Flag Mask Interrupt B Data - // register -#define FIO1_MASKB_C 0xFFC01524 // Flag Mask Interrupt B Clear - // register -#define FIO1_MASKB_S 0xFFC01528 // Flag Mask Interrupt B Set - // register -#define FIO1_MASKB_T 0xFFC0152C // Flag Mask Interrupt B Toggle - // register -#define FIO1_DIR 0xFFC01530 // Flag Direction register -#define FIO1_POLAR 0xFFC01534 // Flag Polarity register -#define FIO1_EDGE 0xFFC01538 // Flag Interrupt Sensitivity - // register -#define FIO1_BOTH 0xFFC0153C // Flag Set on Both Edges - // register -#define FIO1_INEN 0xFFC01540 // Flag Input Enable register - -// Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) -#define FIO2_FLAG_D 0xFFC01700 // Flag Data register -#define FIO2_FLAG_C 0xFFC01704 // Flag Clear register -#define FIO2_FLAG_S 0xFFC01708 // Flag Set register -#define FIO2_FLAG_T 0xFFC0170C // Flag Toggle register -#define FIO2_MASKA_D 0xFFC01710 // Flag Mask Interrupt A Data - // register -#define FIO2_MASKA_C 0xFFC01714 // Flag Mask Interrupt A Clear - // register -#define FIO2_MASKA_S 0xFFC01718 // Flag Mask Interrupt A Set - // register -#define FIO2_MASKA_T 0xFFC0171C // Flag Mask Interrupt A Toggle - // register -#define FIO2_MASKB_D 0xFFC01720 // Flag Mask Interrupt B Data - // register -#define FIO2_MASKB_C 0xFFC01724 // Flag Mask Interrupt B Clear - // register -#define FIO2_MASKB_S 0xFFC01728 // Flag Mask Interrupt B Set - // register -#define FIO2_MASKB_T 0xFFC0172C // Flag Mask Interrupt B Toggle - // register -#define FIO2_DIR 0xFFC01730 // Flag Direction register -#define FIO2_POLAR 0xFFC01734 // Flag Polarity register -#define FIO2_EDGE 0xFFC01738 // Flag Interrupt Sensitivity - // register -#define FIO2_BOTH 0xFFC0173C // Flag Set on Both Edges - // register -#define FIO2_INEN 0xFFC01740 // Flag Input Enable register - -//// SPORT0 Controller (0xFFC00800 - 0xFFC008FF) -#define SPORT0_TCR1 0xFFC00800 // SPORT0 Transmit - // Configuration 1 Register -#define SPORT0_TCR2 0xFFC00804 // SPORT0 Transmit - // Configuration 2 Register -#define SPORT0_TCLKDIV 0xFFC00808 // SPORT0 Transmit Clock Divider -#define SPORT0_TFSDIV 0xFFC0080C // SPORT0 Transmit - // Frame Sync Divider -#define SPORT0_TX 0xFFC00810 // SPORT0 TX Data Register -#define SPORT0_RX 0xFFC00818 // SPORT0 RX Data Register -#define SPORT0_RCR1 0xFFC00820 // SPORT0 Transmit - // Configuration 1 Register -#define SPORT0_RCR2 0xFFC00824 // SPORT0 Transmit - // Configuration 2 Register -#define SPORT0_RCLKDIV 0xFFC00828 // SPORT0 Receive Clock Divider -#define SPORT0_RFSDIV 0xFFC0082C // SPORT0 Receive - // Frame Sync Divider -#define SPORT0_STAT 0xFFC00830 // SPORT0 Status Register -#define SPORT0_CHNL 0xFFC00834 // SPORT0 Current - // Channel Register -#define SPORT0_MCMC1 0xFFC00838 // SPORT0 Multi-Channel - // Configuration Register 1 -#define SPORT0_MCMC2 0xFFC0083C // SPORT0 Multi-Channel - // Configuration Register 2 -#define SPORT0_MTCS0 0xFFC00840 // SPORT0 Multi-Channel - // Transmit Select Register 0 -#define SPORT0_MTCS1 0xFFC00844 // SPORT0 Multi-Channel - // Transmit Select Register 1 -#define SPORT0_MTCS2 0xFFC00848 // SPORT0 Multi-Channel - // Transmit Select Register 2 -#define SPORT0_MTCS3 0xFFC0084C // SPORT0 Multi-Channel - // Transmit Select Register 3 -#define SPORT0_MRCS0 0xFFC00850 // SPORT0 Multi-Channel - // Receive Select Register 0 -#define SPORT0_MRCS1 0xFFC00854 // SPORT0 Multi-Channel - // Receive Select Register 1 -#define SPORT0_MRCS2 0xFFC00858 // SPORT0 Multi-Channel - // Receive Select Register 2 -#define SPORT0_MRCS3 0xFFC0085C // SPORT0 Multi-Channel - // Receive Select Register 3 - -//// SPORT1 Controller (0xFFC00900 - 0xFFC009FF) -#define SPORT1_TCR1 0xFFC00900 // SPORT1 Transmit - // Configuration 1 Register -#define SPORT1_TCR2 0xFFC00904 // SPORT1 Transmit - // Configuration 2 Register -#define SPORT1_TCLKDIV 0xFFC00908 // SPORT1 Transmit Clock Divider -#define SPORT1_TFSDIV 0xFFC0090C // SPORT1 Transmit - // Frame Sync Divider -#define SPORT1_TX 0xFFC00910 // SPORT1 TX Data Register -#define SPORT1_RX 0xFFC00918 // SPORT1 RX Data Register -#define SPORT1_RCR1 0xFFC00920 // SPORT1 Transmit - // Configuration 1 Register -#define SPORT1_RCR2 0xFFC00924 // SPORT1 Transmit - // Configuration 2 Register -#define SPORT1_RCLKDIV 0xFFC00928 // SPORT1 Receive Clock Divider -#define SPORT1_RFSDIV 0xFFC0092C // SPORT1 Receive - // Frame Sync Divider -#define SPORT1_STAT 0xFFC00930 // SPORT1 Status Register -#define SPORT1_CHNL 0xFFC00934 // SPORT1 Current - // Channel Register -#define SPORT1_MCMC1 0xFFC00938 // SPORT1 Multi-Channel - // Configuration Register 1 -#define SPORT1_MCMC2 0xFFC0093C // SPORT1 Multi-Channel - // Configuration Register 2 -#define SPORT1_MTCS0 0xFFC00940 // SPORT1 Multi-Channel - // Transmit Select Register 0 -#define SPORT1_MTCS1 0xFFC00944 // SPORT1 Multi-Channel - // Transmit Select Register 1 -#define SPORT1_MTCS2 0xFFC00948 // SPORT1 Multi-Channel - // Transmit Select Register 2 -#define SPORT1_MTCS3 0xFFC0094C // SPORT1 Multi-Channel - // Transmit Select Register 3 -#define SPORT1_MRCS0 0xFFC00950 // SPORT1 Multi-Channel - // Receive Select Register 0 -#define SPORT1_MRCS1 0xFFC00954 // SPORT1 Multi-Channel - // Receive Select Register 1 -#define SPORT1_MRCS2 0xFFC00958 // SPORT1 Multi-Channel - // Receive Select Register 2 -#define SPORT1_MRCS3 0xFFC0095C // SPORT1 Multi-Channel - // Receive Select Register 3 - -// Asynchronous Memory Controller - External Bus Interface Unit -#define EBIU_AMGCTL 0xFFC00A00 // Asynchronous Memory - // Global Control Register -#define EBIU_AMBCTL0 0xFFC00A04 // Asynchronous Memory - // Bank Control Register 0 -#define EBIU_AMBCTL1 0xFFC00A08 // Asynchronous Memory - // Bank Control Register 1 - -// SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) -#define EBIU_SDGCTL 0xFFC00A10 // SDRAM Global Control - // Register -#define EBIU_SDBCTL 0xFFC00A14 // SDRAM Bank Control Register -#define EBIU_SDRRC 0xFFC00A18 // SDRAM Refresh Rate Control - // Register -#define EBIU_SDSTAT 0xFFC00A1C // SDRAM Status Register - -// Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) -#define PPI0_CONTROL 0xFFC01000 // PPI0 Control register -#define PPI0_STATUS 0xFFC01004 // PPI0 Status register -#define PPI0_COUNT 0xFFC01008 // PPI0 Transfer Count register -#define PPI0_DELAY 0xFFC0100C // PPI0 Delay Count register -#define PPI0_FRAME 0xFFC01010 // PPI0 Frame Length register - -//Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) -#define PPI1_CONTROL 0xFFC01300 // PPI1 Control register -#define PPI1_STATUS 0xFFC01304 // PPI1 Status register -#define PPI1_COUNT 0xFFC01308 // PPI1 Transfer Count register -#define PPI1_DELAY 0xFFC0130C // PPI1 Delay Count register -#define PPI1_FRAME 0xFFC01310 // PPI1 Frame Length register - -// DMA Traffic controls -#define DMA_TCPER 0xFFC00B0C // Traffic Control Periods - // Register -#define DMA_TCCNT 0xFFC00B10 // Traffic Control Current - // Counts Register -#define DMA_TC_PER 0xFFC00B0C // Traffic Control Periods - // Register -#define DMA_TC_CNT 0xFFC00B10 // Traffic Control Current - // Counts Register - -// DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) -#define DMA1_0_CONFIG 0xFFC01C08 // DMA1 Channel 0 Configuration - // register -#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 // DMA1 Channel 0 Next - // Descripter Ptr Reg -#define DMA1_0_START_ADDR 0xFFC01C04 // DMA1 Channel 0 Start Address -#define DMA1_0_X_COUNT 0xFFC01C10 // DMA1 Channel 0 Inner Loop - // Count -#define DMA1_0_Y_COUNT 0xFFC01C18 // DMA1 Channel 0 Outer Loop - // Count -#define DMA1_0_X_MODIFY 0xFFC01C14 // DMA1 Channel 0 Inner Loop - // Addr Increment -#define DMA1_0_Y_MODIFY 0xFFC01C1C // DMA1 Channel 0 Outer Loop - // Addr Increment -#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 // DMA1 Channel 0 Current - // Descriptor Pointer -#define DMA1_0_CURR_ADDR 0xFFC01C24 // DMA1 Channel 0 Current - // Address Pointer -#define DMA1_0_CURR_X_COUNT 0xFFC01C30 // DMA1 Channel 0 Current Inner - // Loop Count -#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 // DMA1 Channel 0 Current Outer - // Loop Count -#define DMA1_0_IRQ_STATUS 0xFFC01C28 // DMA1 Channel 0 Interrupt - // Status Register -#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C // DMA1 Channel 0 Peripheral - // Map Register - -#define DMA1_1_CONFIG 0xFFC01C48 // DMA1 Channel 1 Configuration - // register -#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 // DMA1 Channel 1 Next - // Descripter Ptr Reg -#define DMA1_1_START_ADDR 0xFFC01C44 // DMA1 Channel 1 Start Address -#define DMA1_1_X_COUNT 0xFFC01C50 // DMA1 Channel 1 Inner Loop - // Count -#define DMA1_1_Y_COUNT 0xFFC01C58 // DMA1 Channel 1 Outer Loop - // Count -#define DMA1_1_X_MODIFY 0xFFC01C54 // DMA1 Channel 1 Inner Loop - // Addr Increment -#define DMA1_1_Y_MODIFY 0xFFC01C5C // DMA1 Channel 1 Outer Loop - // Addr Increment -#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 // DMA1 Channel 1 Current - // Descriptor Pointer -#define DMA1_1_CURR_ADDR 0xFFC01C64 // DMA1 Channel 1 Current - // Address Pointer -#define DMA1_1_CURR_X_COUNT 0xFFC01C70 // DMA1 Channel 1 Current Inner - // Loop Count -#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 // DMA1 Channel 1 Current Outer - // Loop Count -#define DMA1_1_IRQ_STATUS 0xFFC01C68 // DMA1 Channel 1 Interrupt - // Status Register -#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C // DMA1 Channel 1 Peripheral - // Map Register - -#define DMA1_2_CONFIG 0xFFC01C88 // DMA1 Channel 2 Configuration - // register -#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 // DMA1 Channel 2 Next - // Descripter Ptr Reg -#define DMA1_2_START_ADDR 0xFFC01C84 // DMA1 Channel 2 Start Address -#define DMA1_2_X_COUNT 0xFFC01C90 // DMA1 Channel 2 Inner Loop - // Count -#define DMA1_2_Y_COUNT 0xFFC01C98 // DMA1 Channel 2 Outer Loop - // Count -#define DMA1_2_X_MODIFY 0xFFC01C94 // DMA1 Channel 2 Inner Loop - // Addr Increment -#define DMA1_2_Y_MODIFY 0xFFC01C9C // DMA1 Channel 2 Outer Loop - // Addr Increment -#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 // DMA1 Channel 2 Current - // Descriptor Pointer -#define DMA1_2_CURR_ADDR 0xFFC01CA4 // DMA1 Channel 2 Current - // Address Pointer -#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 // DMA1 Channel 2 Current Inner - // Loop Count -#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 // DMA1 Channel 2 Current Outer - // Loop Count -#define DMA1_2_IRQ_STATUS 0xFFC01CA8 // DMA1 Channel 2 Interrupt - // Status Register -#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC // DMA1 Channel 2 Peripheral - // Map Register - -#define DMA1_3_CONFIG 0xFFC01CC8 // DMA1 Channel 3 Configuration - // register -#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 // DMA1 Channel 3 Next - // Descripter Ptr Reg -#define DMA1_3_START_ADDR 0xFFC01CC4 // DMA1 Channel 3 Start Address -#define DMA1_3_X_COUNT 0xFFC01CD0 // DMA1 Channel 3 Inner Loop - // Count -#define DMA1_3_Y_COUNT 0xFFC01CD8 // DMA1 Channel 3 Outer Loop - // Count -#define DMA1_3_X_MODIFY 0xFFC01CD4 // DMA1 Channel 3 Inner Loop - // Addr Increment -#define DMA1_3_Y_MODIFY 0xFFC01CDC // DMA1 Channel 3 Outer Loop - // Addr Increment -#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 // DMA1 Channel 3 Current - // Descriptor Pointer -#define DMA1_3_CURR_ADDR 0xFFC01CE4 // DMA1 Channel 3 Current - // Address Pointer -#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 // DMA1 Channel 3 Current Inner - // Loop Count -#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 // DMA1 Channel 3 Current Outer - // Loop Count -#define DMA1_3_IRQ_STATUS 0xFFC01CE8 // DMA1 Channel 3 Interrupt - // Status Register -#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC // DMA1 Channel 3 Peripheral - // Map Register - -#define DMA1_4_CONFIG 0xFFC01D08 // DMA1 Channel 4 Configuration - // register -#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 // DMA1 Channel 4 Next - // Descripter Ptr Reg -#define DMA1_4_START_ADDR 0xFFC01D04 // DMA1 Channel 4 Start Address -#define DMA1_4_X_COUNT 0xFFC01D10 // DMA1 Channel 4 Inner Loop - // Count -#define DMA1_4_Y_COUNT 0xFFC01D18 // DMA1 Channel 4 Outer Loop - // Count -#define DMA1_4_X_MODIFY 0xFFC01D14 // DMA1 Channel 4 Inner Loop - // Addr Increment -#define DMA1_4_Y_MODIFY 0xFFC01D1C // DMA1 Channel 4 Outer Loop - // Addr Increment -#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 // DMA1 Channel 4 Current - // Descriptor Pointer -#define DMA1_4_CURR_ADDR 0xFFC01D24 // DMA1 Channel 4 Current - // Address Pointer -#define DMA1_4_CURR_X_COUNT 0xFFC01D30 // DMA1 Channel 4 Current Inner - // Loop Count -#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 // DMA1 Channel 4 Current Outer - // Loop Count -#define DMA1_4_IRQ_STATUS 0xFFC01D28 // DMA1 Channel 4 Interrupt - // Status Register -#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C // DMA1 Channel 4 Peripheral - // Map Register - -#define DMA1_5_CONFIG 0xFFC01D48 // DMA1 Channel 5 Configuration - // register -#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 // DMA1 Channel 5 Next - // Descripter Ptr Reg -#define DMA1_5_START_ADDR 0xFFC01D44 // DMA1 Channel 5 Start Address -#define DMA1_5_X_COUNT 0xFFC01D50 // DMA1 Channel 5 Inner Loop - // Count -#define DMA1_5_Y_COUNT 0xFFC01D58 // DMA1 Channel 5 Outer Loop - // Count -#define DMA1_5_X_MODIFY 0xFFC01D54 // DMA1 Channel 5 Inner Loop - // Addr Increment -#define DMA1_5_Y_MODIFY 0xFFC01D5C // DMA1 Channel 5 Outer Loop - // Addr Increment -#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 // DMA1 Channel 5 Current - // Descriptor Pointer -#define DMA1_5_CURR_ADDR 0xFFC01D64 // DMA1 Channel 5 Current - // Address Pointer -#define DMA1_5_CURR_X_COUNT 0xFFC01D70 // DMA1 Channel 5 Current Inner - // Loop Count -#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 // DMA1 Channel 5 Current Outer - // Loop Count -#define DMA1_5_IRQ_STATUS 0xFFC01D68 // DMA1 Channel 5 Interrupt - // Status Register -#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C // DMA1 Channel 5 Peripheral - // Map Register - -#define DMA1_6_CONFIG 0xFFC01D88 // DMA1 Channel 6 Configuration - // register -#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 // DMA1 Channel 6 Next - // Descripter Ptr Reg -#define DMA1_6_START_ADDR 0xFFC01D84 // DMA1 Channel 6 Start Address -#define DMA1_6_X_COUNT 0xFFC01D90 // DMA1 Channel 6 Inner Loop - // Count -#define DMA1_6_Y_COUNT 0xFFC01D98 // DMA1 Channel 6 Outer Loop - // Count -#define DMA1_6_X_MODIFY 0xFFC01D94 // DMA1 Channel 6 Inner Loop - // Addr Increment -#define DMA1_6_Y_MODIFY 0xFFC01D9C // DMA1 Channel 6 Outer Loop - // Addr Increment -#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 // DMA1 Channel 6 Current - // Descriptor Pointer -#define DMA1_6_CURR_ADDR 0xFFC01DA4 // DMA1 Channel 6 Current - // Address Pointer -#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 // DMA1 Channel 6 Current Inner - // Loop Count -#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 // DMA1 Channel 6 Current Outer - // Loop Count -#define DMA1_6_IRQ_STATUS 0xFFC01DA8 // DMA1 Channel 6 Interrupt - // /Status Register -#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC // DMA1 Channel 6 Peripheral - // Map Register - -#define DMA1_7_CONFIG 0xFFC01DC8 // DMA1 Channel 7 Configuration - // register -#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 // DMA1 Channel 7 Next - // Descripter Ptr Reg -#define DMA1_7_START_ADDR 0xFFC01DC4 // DMA1 Channel 7 Start Address -#define DMA1_7_X_COUNT 0xFFC01DD0 // DMA1 Channel 7 Inner Loop - // Count -#define DMA1_7_Y_COUNT 0xFFC01DD8 // DMA1 Channel 7 Outer Loop - // Count -#define DMA1_7_X_MODIFY 0xFFC01DD4 // DMA1 Channel 7 Inner Loop - // Addr Increment -#define DMA1_7_Y_MODIFY 0xFFC01DDC // DMA1 Channel 7 Outer Loop - // Addr Increment -#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 // DMA1 Channel 7 Current - // Descriptor Pointer -#define DMA1_7_CURR_ADDR 0xFFC01DE4 // DMA1 Channel 7 Current - // Address Pointer -#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 // DMA1 Channel 7 Current Inner - // Loop Count -#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 // DMA1 Channel 7 Current Outer - // Loop Count -#define DMA1_7_IRQ_STATUS 0xFFC01DE8 // DMA1 Channel 7 Interrupt - // /Status Register -#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC // DMA1 Channel 7 Peripheral - // Map Register - -#define DMA1_8_CONFIG 0xFFC01E08 // DMA1 Channel 8 Configuration - // register -#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 // DMA1 Channel 8 Next - // Descripter Ptr Reg -#define DMA1_8_START_ADDR 0xFFC01E04 // DMA1 Channel 8 Start Address -#define DMA1_8_X_COUNT 0xFFC01E10 // DMA1 Channel 8 Inner Loop - // Count -#define DMA1_8_Y_COUNT 0xFFC01E18 // DMA1 Channel 8 Outer Loop - // Count -#define DMA1_8_X_MODIFY 0xFFC01E14 // DMA1 Channel 8 Inner Loop - // Addr Increment -#define DMA1_8_Y_MODIFY 0xFFC01E1C // DMA1 Channel 8 Outer Loop - // Addr Increment -#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 // DMA1 Channel 8 Current - // Descriptor Pointer -#define DMA1_8_CURR_ADDR 0xFFC01E24 // DMA1 Channel 8 Current - // Address Pointer -#define DMA1_8_CURR_X_COUNT 0xFFC01E30 // DMA1 Channel 8 Current Inner - // Loop Count -#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 // DMA1 Channel 8 Current Outer - // Loop Count -#define DMA1_8_IRQ_STATUS 0xFFC01E28 // DMA1 Channel 8 Interrupt - // /Status Register -#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C // DMA1 Channel 8 Peripheral - // Map Register - -#define DMA1_9_CONFIG 0xFFC01E48 // DMA1 Channel 9 Configuration - // register -#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 // DMA1 Channel 9 Next - // Descripter Ptr Reg -#define DMA1_9_START_ADDR 0xFFC01E44 // DMA1 Channel 9 Start Address -#define DMA1_9_X_COUNT 0xFFC01E50 // DMA1 Channel 9 Inner Loop - // Count -#define DMA1_9_Y_COUNT 0xFFC01E58 // DMA1 Channel 9 Outer Loop - // Count -#define DMA1_9_X_MODIFY 0xFFC01E54 // DMA1 Channel 9 Inner Loop - // Addr Increment -#define DMA1_9_Y_MODIFY 0xFFC01E5C // DMA1 Channel 9 Outer Loop - // Addr Increment -#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 // DMA1 Channel 9 Current - // Descriptor Pointer -#define DMA1_9_CURR_ADDR 0xFFC01E64 // DMA1 Channel 9 Current - // Address Pointer -#define DMA1_9_CURR_X_COUNT 0xFFC01E70 // DMA1 Channel 9 Current Inner - // Loop Count -#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 // DMA1 Channel 9 Current Outer - // Loop Count -#define DMA1_9_IRQ_STATUS 0xFFC01E68 // DMA1 Channel 9 Interrupt - // /Status Register -#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C // DMA1 Channel 9 Peripheral - // Map Register - -#define DMA1_10_CONFIG 0xFFC01E88 // DMA1 Channel 10 Configuration - // register -#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 // DMA1 Channel 10 Next - // Descripter Ptr Reg -#define DMA1_10_START_ADDR 0xFFC01E84 // DMA1 Channel 10 Start Address -#define DMA1_10_X_COUNT 0xFFC01E90 // DMA1 Channel 10 Inner Loop - // Count -#define DMA1_10_Y_COUNT 0xFFC01E98 // DMA1 Channel 10 Outer Loop - // Count -#define DMA1_10_X_MODIFY 0xFFC01E94 // DMA1 Channel 10 Inner Loop - // Addr Increment -#define DMA1_10_Y_MODIFY 0xFFC01E9C // DMA1 Channel 10 Outer Loop - // Addr Increment -#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 // DMA1 Channel 10 Current - // Descriptor Pointer -#define DMA1_10_CURR_ADDR 0xFFC01EA4 // DMA1 Channel 10 Current - // Address Pointer -#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 // DMA1 Channel 10 Current Inner - // Loop Count -#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 // DMA1 Channel 10 Current Outer - // Loop Count -#define DMA1_10_IRQ_STATUS 0xFFC01EA8 // DMA1 Channel 10 Interrupt - // /Status Register -#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC // DMA1 Channel 10 Peripheral - // Map Register - -#define DMA1_11_CONFIG 0xFFC01EC8 // DMA1 Channel 11 Configuration - // register -#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 // DMA1 Channel 11 Next - // Descripter Ptr Reg -#define DMA1_11_START_ADDR 0xFFC01EC4 // DMA1 Channel 11 Start Address -#define DMA1_11_X_COUNT 0xFFC01ED0 // DMA1 Channel 11 Inner Loop - // Count -#define DMA1_11_Y_COUNT 0xFFC01ED8 // DMA1 Channel 11 Outer Loop - // Count -#define DMA1_11_X_MODIFY 0xFFC01ED4 // DMA1 Channel 11 Inner Loop - // Addr Increment -#define DMA1_11_Y_MODIFY 0xFFC01EDC // DMA1 Channel 11 Outer Loop - // Addr Increment -#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 // DMA1 Channel 11 Current - // Descriptor Pointer -#define DMA1_11_CURR_ADDR 0xFFC01EE4 // DMA1 Channel 11 Current - // Address Pointer -#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 // DMA1 Channel 11 Current Inner - // Loop Count -#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 // DMA1 Channel 11 Current Outer - // Loop Count -#define DMA1_11_IRQ_STATUS 0xFFC01EE8 // DMA1 Channel 11 Interrupt - // /Status Register -#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC // DMA1 Channel 11 Peripheral - // Map Register - -// Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) -#define MDMA1_D0_CONFIG 0xFFC01F08 // MemDMA1 Stream 0 Destination - // Configuration -#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 // MemDMA1 Stream 0 - // Destination Next - // Descriptor Ptr Reg -#define MDMA1_D0_START_ADDR 0xFFC01F04 // MemDMA1 Stream 0 Destination - // Start Address -#define MDMA1_D0_X_COUNT 0xFFC01F10 // MemDMA1 Stream 0 Destination - // Inner-Loop Count -#define MDMA1_D0_Y_COUNT 0xFFC01F18 // MemDMA1 Stream 0 Destination - // Outer-Loop Count -#define MDMA1_D0_X_MODIFY 0xFFC01F14 // MemDMA1 Stream 0 Dest - // Inner-Loop Address-Increment -#define MDMA1_D0_Y_MODIFY 0xFFC01F1C // MemDMA1 Stream 0 Dest - // Outer-Loop Address-Increment -#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 // MemDMA1 Stream 0 Dest - // Current Descriptor Ptr reg -#define MDMA1_D0_CURR_ADDR 0xFFC01F24 // MemDMA1 Stream 0 Destination - // Current Address -#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 // MemDMA1 Stream 0 Dest - // Current Inner-Loop Count -#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 // MemDMA1 Stream 0 Dest - // Current Outer-Loop Count -#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 // MemDMA1 Stream 0 Destination - // Interrupt/Status -#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C // MemDMA1 Stream 0 - // Destination Peripheral Map - -#define MDMA1_S0_CONFIG 0xFFC01F48 // MemDMA1 Stream 0 Source - // Configuration -#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 // MemDMA1 Stream 0 Source - // Next Descriptor Ptr Reg -#define MDMA1_S0_START_ADDR 0xFFC01F44 // MemDMA1 Stream 0 Source - // Start Address -#define MDMA1_S0_X_COUNT 0xFFC01F50 // MemDMA1 Stream 0 Source - // Inner-Loop Count -#define MDMA1_S0_Y_COUNT 0xFFC01F58 // MemDMA1 Stream 0 Source - // Outer-Loop Count -#define MDMA1_S0_X_MODIFY 0xFFC01F54 // MemDMA1 Stream 0 Source - // Inner-Loop Address-Increment -#define MDMA1_S0_Y_MODIFY 0xFFC01F5C // MemDMA1 Stream 0 Source - // Outer-Loop Address-Increment -#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 // MemDMA1 Stream 0 Source - // Current Descriptor Ptr reg -#define MDMA1_S0_CURR_ADDR 0xFFC01F64 // MemDMA1 Stream 0 Source - // Current Address -#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 // MemDMA1 Stream 0 Source - // Current Inner-Loop Count -#define MDMA1_S0_CURR_Y_COUNT ` 0xFFC01F78 // MemDMA1 Stream 0 Source - // Current Outer-Loop Count -#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 // MemDMA1 Stream 0 Source - // Interrupt/Status -#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C // MemDMA1 Stream 0 Source - // Peripheral Map - -#define MDMA1_D1_CONFIG 0xFFC01F88 // MemDMA1 Stream 1 Destination - // Configuration -#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 // MemDMA1 Stream 1 - // Destination Next - // Descriptor Ptr Reg -#define MDMA1_D1_START_ADDR 0xFFC01F84 // MemDMA1 Stream 1 Destination - // Start Address -#define MDMA1_D1_X_COUNT 0xFFC01F90 // MemDMA1 Stream 1 Destination - // Inner-Loop Count -#define MDMA1_D1_Y_COUNT 0xFFC01F98 // MemDMA1 Stream 1 Destination - // Outer-Loop Count -#define MDMA1_D1_X_MODIFY 0xFFC01F94 // MemDMA1 Stream 1 Dest - // Inner-Loop Address-Increment -#define MDMA1_D1_Y_MODIFY 0xFFC01F9C // MemDMA1 Stream 1 Dest - // Outer-Loop Address-Increment -#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 // MemDMA1 Stream 1 Dest - // Current Descriptor Ptr reg -#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 // MemDMA1 Stream 1 Dest - // Current Address -#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 // MemDMA1 Stream 1 Dest - // Current Inner-Loop Count -#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 // MemDMA1 Stream 1 Dest - // Current Outer-Loop Count -#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 // MemDMA1 Stream 1 Dest - // Interrupt/Status -#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC // MemDMA1 Stream 1 Dest - // Peripheral Map - -#define MDMA1_S1_CONFIG 0xFFC01FC8 // MemDMA1 Stream 1 Source - // Configuration -#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 // MemDMA1 Stream 1 Source - // Next Descriptor Ptr Reg -#define MDMA1_S1_START_ADDR 0xFFC01FC4 // MemDMA1 Stream 1 Source - // Start Address -#define MDMA1_S1_X_COUNT 0xFFC01FD0 // MemDMA1 Stream 1 Source - // Inner-Loop Count -#define MDMA1_S1_Y_COUNT 0xFFC01FD8 // MemDMA1 Stream 1 Source - // Outer-Loop Count -#define MDMA1_S1_X_MODIFY 0xFFC01FD4 // MemDMA1 Stream 1 Source - // Inner-Loop Address-Increment -#define MDMA1_S1_Y_MODIFY 0xFFC01FDC // MemDMA1 Stream 1 Source - // Outer-Loop Address-Increment -#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 // MemDMA1 Stream 1 Source - // Current Descriptor Ptr reg -#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 // MemDMA1 Stream 1 Source - // Current Address -#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 // MemDMA1 Stream 1 Source - // Current Inner-Loop Count -#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 // MemDMA1 Stream 1 Source - // Current Outer-Loop Count -#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 // MemDMA1 Stream 1 Source - // Interrupt/Status -#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC // MemDMA1 Stream 1 Source - // Peripheral Map - -// DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) -#define DMA2_0_CONFIG 0xFFC00C08 // DMA2 Channel 0 Configuration - // register -#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 // DMA2 Channel 0 Next - // Descripter Ptr Reg -#define DMA2_0_START_ADDR 0xFFC00C04 // DMA2 Channel 0 Start Address -#define DMA2_0_X_COUNT 0xFFC00C10 // DMA2 Channel 0 Inner Loop - // Count -#define DMA2_0_Y_COUNT 0xFFC00C18 // DMA2 Channel 0 Outer Loop - // Count -#define DMA2_0_X_MODIFY 0xFFC00C14 // DMA2 Channel 0 Inner Loop - // Addr Increment -#define DMA2_0_Y_MODIFY 0xFFC00C1C // DMA2 Channel 0 Outer Loop - // Addr Increment -#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 // DMA2 Channel 0 Current - // Descriptor Pointer -#define DMA2_0_CURR_ADDR 0xFFC00C24 // DMA2 Channel 0 Current - // Address Pointer -#define DMA2_0_CURR_X_COUNT 0xFFC00C30 // DMA2 Channel 0 Current Inner - // Loop Count -#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 // DMA2 Channel 0 Current Outer - // Loop Count -#define DMA2_0_IRQ_STATUS 0xFFC00C28 // DMA2 Channel 0 Interrupt - // /Status Register -#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C // DMA2 Channel 0 Peripheral - // Map Register - -#define DMA2_1_CONFIG 0xFFC00C48 // DMA2 Channel 1 Configuration - // register -#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 // DMA2 Channel 1 Next - // Descripter Ptr Reg -#define DMA2_1_START_ADDR 0xFFC00C44 // DMA2 Channel 1 Start Address -#define DMA2_1_X_COUNT 0xFFC00C50 // DMA2 Channel 1 Inner Loop - // Count -#define DMA2_1_Y_COUNT 0xFFC00C58 // DMA2 Channel 1 Outer Loop - // Count -#define DMA2_1_X_MODIFY 0xFFC00C54 // DMA2 Channel 1 Inner Loop - // Addr Increment -#define DMA2_1_Y_MODIFY 0xFFC00C5C // DMA2 Channel 1 Outer Loop - // Addr Increment -#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 // DMA2 Channel 1 Current - // Descriptor Pointer -#define DMA2_1_CURR_ADDR 0xFFC00C64 // DMA2 Channel 1 Current - // Address Pointer -#define DMA2_1_CURR_X_COUNT 0xFFC00C70 // DMA2 Channel 1 Current - // Inner Loop Count -#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 // DMA2 Channel 1 Current - // Outer Loop Count -#define DMA2_1_IRQ_STATUS 0xFFC00C68 // DMA2 Channel 1 Interrupt - // /Status Register -#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C // DMA2 Channel 1 Peripheral - // Map Register - -#define DMA2_2_CONFIG 0xFFC00C88 // DMA2 Channel 2 Configuration - // register -#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 // DMA2 Channel 2 Next - // Descripter Ptr Reg -#define DMA2_2_START_ADDR 0xFFC00C84 // DMA2 Channel 2 Start Address -#define DMA2_2_X_COUNT 0xFFC00C90 // DMA2 Channel 2 Inner Loop - // Count -#define DMA2_2_Y_COUNT 0xFFC00C98 // DMA2 Channel 2 Outer Loop - // Count -#define DMA2_2_X_MODIFY 0xFFC00C94 // DMA2 Channel 2 Inner Loop - // Addr Increment -#define DMA2_2_Y_MODIFY 0xFFC00C9C // DMA2 Channel 2 Outer Loop - // Addr Increment -#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 // DMA2 Channel 2 Current - // Descriptor Pointer -#define DMA2_2_CURR_ADDR 0xFFC00CA4 // DMA2 Channel 2 Current - // Address Pointer -#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 // DMA2 Channel 2 Current Inner - // Loop Count -#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 // DMA2 Channel 2 Current Outer - // Loop Count -#define DMA2_2_IRQ_STATUS 0xFFC00CA8 // DMA2 Channel 2 Interrupt - // /Status Register -#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC // DMA2 Channel 2 Peripheral - // Map Register - -#define DMA2_3_CONFIG 0xFFC00CC8 // DMA2 Channel 3 Configuration - // register -#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 // DMA2 Channel 3 Next - // Descripter Ptr Reg -#define DMA2_3_START_ADDR 0xFFC00CC4 // DMA2 Channel 3 Start Address -#define DMA2_3_X_COUNT 0xFFC00CD0 // DMA2 Channel 3 Inner Loop - // Count -#define DMA2_3_Y_COUNT 0xFFC00CD8 // DMA2 Channel 3 Outer Loop - // Count -#define DMA2_3_X_MODIFY 0xFFC00CD4 // DMA2 Channel 3 Inner Loop - // Addr Increment -#define DMA2_3_Y_MODIFY 0xFFC00CDC // DMA2 Channel 3 Outer Loop - // Addr Increment -#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 // DMA2 Channel 3 Current - // Descriptor Pointer -#define DMA2_3_CURR_ADDR 0xFFC00CE4 // DMA2 Channel 3 Current - // Address Pointer -#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 // DMA2 Channel 3 Current Inner - // Loop Count -#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 // DMA2 Channel 3 Current Outer - // Loop Count -#define DMA2_3_IRQ_STATUS 0xFFC00CE8 // DMA2 Channel 3 Interrupt - // /Status Register -#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC // DMA2 Channel 3 Peripheral - // Map Register - -#define DMA2_4_CONFIG 0xFFC00D08 // DMA2 Channel 4 Configuration - // register -#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 // DMA2 Channel 4 Next - // Descripter Ptr Reg -#define DMA2_4_START_ADDR 0xFFC00D04 // DMA2 Channel 4 Start Address -#define DMA2_4_X_COUNT 0xFFC00D10 // DMA2 Channel 4 Inner Loop - // Count -#define DMA2_4_Y_COUNT 0xFFC00D18 // DMA2 Channel 4 Outer Loop - // Count -#define DMA2_4_X_MODIFY 0xFFC00D14 // DMA2 Channel 4 Inner Loop - // Addr Increment -#define DMA2_4_Y_MODIFY 0xFFC00D1C // DMA2 Channel 4 Outer Loop - // Addr Increment -#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 // DMA2 Channel 4 Current - // Descriptor Pointer -#define DMA2_4_CURR_ADDR 0xFFC00D24 // DMA2 Channel 4 Current - // Address Pointer -#define DMA2_4_CURR_X_COUNT 0xFFC00D30 // DMA2 Channel 4 Current Inner - // Loop Count -#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 // DMA2 Channel 4 Current Outer - // Loop Count -#define DMA2_4_IRQ_STATUS 0xFFC00D28 // DMA2 Channel 4 Interrupt - // /Status Register -#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C // DMA2 Channel 4 Peripheral - // Map Register - -#define DMA2_5_CONFIG 0xFFC00D48 // DMA2 Channel 5 Configuration - // register -#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 // DMA2 Channel 5 Next - // Descripter Ptr Reg -#define DMA2_5_START_ADDR 0xFFC00D44 // DMA2 Channel 5 Start Address -#define DMA2_5_X_COUNT 0xFFC00D50 // DMA2 Channel 5 Inner Loop - // Count -#define DMA2_5_Y_COUNT 0xFFC00D58 // DMA2 Channel 5 Outer Loop - // Count -#define DMA2_5_X_MODIFY 0xFFC00D54 // DMA2 Channel 5 Inner Loop - // Addr Increment -#define DMA2_5_Y_MODIFY 0xFFC00D5C // DMA2 Channel 5 Outer Loop - // Addr Increment -#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 // DMA2 Channel 5 Current - // Descriptor Pointer -#define DMA2_5_CURR_ADDR 0xFFC00D64 // DMA2 Channel 5 Current - // Address Pointer -#define DMA2_5_CURR_X_COUNT 0xFFC00D70 // DMA2 Channel 5 Current Inner - // Loop Count -#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 // DMA2 Channel 5 Current Outer - // Loop Count -#define DMA2_5_IRQ_STATUS 0xFFC00D68 // DMA2 Channel 5 Interrupt - // /Status Register -#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C // DMA2 Channel 5 Peripheral - // Map Register - -#define DMA2_6_CONFIG 0xFFC00D88 // DMA2 Channel 6 Configuration - // register -#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 // DMA2 Channel 6 Next - // Descripter Ptr Reg -#define DMA2_6_START_ADDR 0xFFC00D84 // DMA2 Channel 6 Start Address -#define DMA2_6_X_COUNT 0xFFC00D90 // DMA2 Channel 6 Inner Loop - // Count -#define DMA2_6_Y_COUNT 0xFFC00D98 // DMA2 Channel 6 Outer Loop - // Count -#define DMA2_6_X_MODIFY 0xFFC00D94 // DMA2 Channel 6 Inner Loop - // Addr Increment -#define DMA2_6_Y_MODIFY 0xFFC00D9C // DMA2 Channel 6 Outer Loop - // Addr Increment -#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 // DMA2 Channel 6 Current - // Descriptor Pointer -#define DMA2_6_CURR_ADDR 0xFFC00DA4 // DMA2 Channel 6 Current - // Address Pointer -#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 // DMA2 Channel 6 Current Inner - // Loop Count -#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 // DMA2 Channel 6 Current Outer - // Loop Count -#define DMA2_6_IRQ_STATUS 0xFFC00DA8 // DMA2 Channel 6 Interrupt - // /Status Register -#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC // DMA2 Channel 6 Peripheral - // Map Register - -#define DMA2_7_CONFIG 0xFFC00DC8 // DMA2 Channel 7 Configuration - // register -#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 // DMA2 Channel 7 Next - // Descripter Ptr Reg -#define DMA2_7_START_ADDR 0xFFC00DC4 // DMA2 Channel 7 Start Address -#define DMA2_7_X_COUNT 0xFFC00DD0 // DMA2 Channel 7 Inner Loop - // Count -#define DMA2_7_Y_COUNT 0xFFC00DD8 // DMA2 Channel 7 Outer Loop - // Count -#define DMA2_7_X_MODIFY 0xFFC00DD4 // DMA2 Channel 7 Inner Loop - // Addr Increment -#define DMA2_7_Y_MODIFY 0xFFC00DDC // DMA2 Channel 7 Outer Loop - // Addr Increment -#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 // DMA2 Channel 7 Current - // Descriptor Pointer -#define DMA2_7_CURR_ADDR 0xFFC00DE4 // DMA2 Channel 7 Current - // Address Pointer -#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 // DMA2 Channel 7 Current Inner - // Loop Count -#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 // DMA2 Channel 7 Current Outer - // Loop Count -#define DMA2_7_IRQ_STATUS 0xFFC00DE8 // DMA2 Channel 7 Interrupt - // /Status Register -#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC // DMA2 Channel 7 Peripheral - // Map Register - -#define DMA2_8_CONFIG 0xFFC00E08 // DMA2 Channel 8 Configuration - // register -#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 // DMA2 Channel 8 Next - // Descripter Ptr Reg -#define DMA2_8_START_ADDR 0xFFC00E04 // DMA2 Channel 8 Start Address -#define DMA2_8_X_COUNT 0xFFC00E10 // DMA2 Channel 8 Inner Loop - // Count -#define DMA2_8_Y_COUNT 0xFFC00E18 // DMA2 Channel 8 Outer Loop - // Count -#define DMA2_8_X_MODIFY 0xFFC00E14 // DMA2 Channel 8 Inner Loop - // Addr Increment -#define DMA2_8_Y_MODIFY 0xFFC00E1C // DMA2 Channel 8 Outer Loop - // Addr Increment -#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 // DMA2 Channel 8 Current - // Descriptor Pointer -#define DMA2_8_CURR_ADDR 0xFFC00E24 // DMA2 Channel 8 Current - // Address Pointer -#define DMA2_8_CURR_X_COUNT 0xFFC00E30 // DMA2 Channel 8 Current Inner - // Loop Count -#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 // DMA2 Channel 8 Current Outer - // Loop Count -#define DMA2_8_IRQ_STATUS 0xFFC00E28 // DMA2 Channel 8 Interrupt - // /Status Register -#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C // DMA2 Channel 8 Peripheral - // Map Register - -#define DMA2_9_CONFIG 0xFFC00E48 // DMA2 Channel 9 Configuration - // register -#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 // DMA2 Channel 9 Next - // Descripter Ptr Reg -#define DMA2_9_START_ADDR 0xFFC00E44 // DMA2 Channel 9 Start Address -#define DMA2_9_X_COUNT 0xFFC00E50 // DMA2 Channel 9 Inner Loop - // Count -#define DMA2_9_Y_COUNT 0xFFC00E58 // DMA2 Channel 9 Outer Loop - // Count -#define DMA2_9_X_MODIFY 0xFFC00E54 // DMA2 Channel 9 Inner Loop - // Addr Increment -#define DMA2_9_Y_MODIFY 0xFFC00E5C // DMA2 Channel 9 Outer Loop - // Addr Increment -#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 // DMA2 Channel 9 Current - // Descriptor Pointer -#define DMA2_9_CURR_ADDR 0xFFC00E64 // DMA2 Channel 9 Current - // Address Pointer -#define DMA2_9_CURR_X_COUNT 0xFFC00E70 // DMA2 Channel 9 Current Inner - // Loop Count -#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 // DMA2 Channel 9 Current Outer - // Loop Count -#define DMA2_9_IRQ_STATUS 0xFFC00E68 // DMA2 Channel 9 Interrupt - // /Status Register -#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C // DMA2 Channel 9 Peripheral - // Map Register - -#define DMA2_10_CONFIG 0xFFC00E88 // DMA2 Channel 10 Configuration - // register -#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 // DMA2 Channel 10 Next - // Descripter Ptr Reg -#define DMA2_10_START_ADDR 0xFFC00E84 // DMA2 Channel 10 Start Address -#define DMA2_10_X_COUNT 0xFFC00E90 // DMA2 Channel 10 Inner Loop - // Count -#define DMA2_10_Y_COUNT 0xFFC00E98 // DMA2 Channel 10 Outer Loop - // Count -#define DMA2_10_X_MODIFY 0xFFC00E94 // DMA2 Channel 10 Inner Loop - // Addr Increment -#define DMA2_10_Y_MODIFY 0xFFC00E9C // DMA2 Channel 10 Outer Loop - // Addr Increment -#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 // DMA2 Channel 10 Current - // Descriptor Pointer -#define DMA2_10_CURR_ADDR 0xFFC00EA4 // DMA2 Channel 10 Current - // Address Pointer -#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 // DMA2 Channel 10 Current Inner - // Loop Count -#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 // DMA2 Channel 10 Current Outer - // Loop Count -#define DMA2_10_IRQ_STATUS 0xFFC00EA8 // DMA2 Channel 10 Interrupt - // /Status Register -#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC // DMA2 Channel 10 Peripheral - // Map Register - -#define DMA2_11_CONFIG 0xFFC00EC8 // DMA2 Channel 11 Configuration - // register -#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 // DMA2 Channel 11 Next - // Descripter Ptr Reg -#define DMA2_11_START_ADDR 0xFFC00EC4 // DMA2 Channel 11 Start Address -#define DMA2_11_X_COUNT 0xFFC00ED0 // DMA2 Channel 11 Inner Loop - // Count -#define DMA2_11_Y_COUNT 0xFFC00ED8 // DMA2 Channel 11 Outer Loop - // Count -#define DMA2_11_X_MODIFY 0xFFC00ED4 // DMA2 Channel 11 Inner Loop - // Addr Increment -#define DMA2_11_Y_MODIFY 0xFFC00EDC // DMA2 Channel 11 Outer Loop - // Addr Increment -#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 // DMA2 Channel 11 Current - // Descriptor Pointer -#define DMA2_11_CURR_ADDR 0xFFC00EE4 // DMA2 Channel 11 Current - // Address Pointer -#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 // DMA2 Channel 11 Current Inner - // Loop Count -#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 // DMA2 Channel 11 Current Outer - // Loop Count -#define DMA2_11_IRQ_STATUS 0xFFC00EE8 // DMA2 Channel 11 Interrupt - // /Status Register -#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC // DMA2 Channel 11 Peripheral - // Map Register - -// Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) -#define MDMA2_D0_CONFIG 0xFFC00F08 // MemDMA2 Stream 0 Destination - // Configuration register -#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 // MemDMA2 Stream 0 - // Destination Next - // Descriptor Ptr Reg -#define MDMA2_D0_START_ADDR 0xFFC00F04 // MemDMA2 Stream 0 Destination - // Start Address -#define MDMA2_D0_X_COUNT 0xFFC00F10 // MemDMA2 Stream 0 Dest - // Inner-Loop Count register -#define MDMA2_D0_Y_COUNT 0xFFC00F18 // MemDMA2 Stream 0 Dest - // Outer-Loop Count register -#define MDMA2_D0_X_MODIFY 0xFFC00F14 // MemDMA2 Stream 0 Dest - // Inner-Loop Address-Increment -#define MDMA2_D0_Y_MODIFY 0xFFC00F1C // MemDMA2 Stream 0 Dest - // Outer-Loop Address-Increment -#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 // MemDMA2 Stream 0 Dest - // Current Descriptor Ptr reg -#define MDMA2_D0_CURR_ADDR 0xFFC00F24 // MemDMA2 Stream 0 Destination - // Current Address -#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 // MemDMA2 Stream 0 Dest - // Current Inner-Loop Count reg -#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 // MemDMA2 Stream 0 Dest - // Current Outer-Loop Count reg -#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 // MemDMA2 Stream 0 Dest - // Interrupt/Status Register -#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C // MemDMA2 Stream 0 - // Destination Peripheral Map - // register - -#define MDMA2_S0_CONFIG 0xFFC00F48 // MemDMA2 Stream 0 Source - // Configuration register -#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 // MemDMA2 Stream 0 Source - // Next Descriptor Ptr Reg -#define MDMA2_S0_START_ADDR 0xFFC00F44 // MemDMA2 Stream 0 Source - // Start Address -#define MDMA2_S0_X_COUNT 0xFFC00F50 // MemDMA2 Stream 0 Source - // Inner-Loop Count register -#define MDMA2_S0_Y_COUNT 0xFFC00F58 // MemDMA2 Stream 0 Source - // Outer-Loop Count register -#define MDMA2_S0_X_MODIFY 0xFFC00F54 // MemDMA2 Stream 0 Src - // Inner-Loop Addr-Increment reg -#define MDMA2_S0_Y_MODIFY 0xFFC00F5C // MemDMA2 Stream 0 Src - // Outer-Loop Addr-Increment reg -#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 // MemDMA2 Stream 0 Source - // Current Descriptor Ptr reg -#define MDMA2_S0_CURR_ADDR 0xFFC00F64 // MemDMA2 Stream 0 Source - // Current Address -#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 // MemDMA2 Stream 0 Src - // Current Inner-Loop Count reg -#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 // MemDMA2 Stream 0 Src - // Current Outer-Loop Count reg -#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 // MemDMA2 Stream 0 Source - // Interrupt/Status Register -#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C // MemDMA2 Stream 0 Source - // Peripheral Map register - -#define MDMA2_D1_CONFIG 0xFFC00F88 // MemDMA2 Stream 1 Destination - // Configuration register -#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 // MemDMA2 Stream 1 - // Destination Next - // Descriptor Ptr Reg -#define MDMA2_D1_START_ADDR 0xFFC00F84 // MemDMA2 Stream 1 Destination - // Start Address -#define MDMA2_D1_X_COUNT 0xFFC00F90 // MemDMA2 Stream 1 Dest - // Inner-Loop Count register -#define MDMA2_D1_Y_COUNT 0xFFC00F98 // MemDMA2 Stream 1 Dest - // Outer-Loop Count register -#define MDMA2_D1_X_MODIFY 0xFFC00F94 // MemDMA2 Stream 1 Dest - // Inner-Loop Address-Increment -#define MDMA2_D1_Y_MODIFY 0xFFC00F9C // MemDMA2 Stream 1 Dest - // Outer-Loop Address-Increment -#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 // MemDMA2 Stream 1 - // Destination Current - // Descriptor Ptr -#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 // MemDMA2 Stream 1 Destination - // Current Address reg -#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 // MemDMA2 Stream 1 Dest - // Current Inner-Loop Count reg -#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 // MemDMA2 Stream 1 Dest - // Current Outer-Loop Count reg -#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 // MemDMA2 Stream 1 Destination - // Interrupt/Status Reg -#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC // MemDMA2 Stream 1 - // Destination Peripheral Map - // register - -#define MDMA2_S1_CONFIG 0xFFC00FC8 // MemDMA2 Stream 1 Source - // Configuration register -#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 // MemDMA2 Stream 1 Source - // Next Descriptor Ptr Reg -#define MDMA2_S1_START_ADDR 0xFFC00FC4 // MemDMA2 Stream 1 Source - // Start Address -#define MDMA2_S1_X_COUNT 0xFFC00FD0 // MemDMA2 Stream 1 Source - // Inner-Loop Count register -#define MDMA2_S1_Y_COUNT 0xFFC00FD8 // MemDMA2 Stream 1 Source - // Outer-Loop Count register -#define MDMA2_S1_X_MODIFY 0xFFC00FD4 // MemDMA2 Stream 1 Src - // Inner-Loop Address-Increment -#define MDMA2_S1_Y_MODIFY 0xFFC00FDC // MemDMA2 Stream 1 Source - // Outer-Loop Address-Increment -#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 // MemDMA2 Stream 1 Source - // Current Descriptor Ptr reg -#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 // MemDMA2 Stream 1 Source - // Current Address -#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 // MemDMA2 Stream 1 Source - // Current Inner-Loop Count -#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 // MemDMA2 Stream 1 Source - // Current Outer-Loop Count -#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 // MemDMA2 Stream 1 Source - // Interrupt/Status Register -#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC // MemDMA2 Stream 1 Source - // Peripheral Map register - -// Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) -#define IMDMA_D0_CONFIG 0xFFC01808 // IMDMA Stream 0 Destination - // Configuration -#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 // IMDMA Stream 0 Destination - // Next Descriptor Ptr Reg -#define IMDMA_D0_START_ADDR 0xFFC01804 // IMDMA Stream 0 Destination - // Start Address -#define IMDMA_D0_X_COUNT 0xFFC01810 // IMDMA Stream 0 Destination - // Inner-Loop Count -#define IMDMA_D0_Y_COUNT 0xFFC01818 // IMDMA Stream 0 Destination - // Outer-Loop Count -#define IMDMA_D0_X_MODIFY 0xFFC01814 // IMDMA Stream 0 Dest - // Inner-Loop Address-Increment -#define IMDMA_D0_Y_MODIFY 0xFFC0181C // IMDMA Stream 0 Dest - // Outer-Loop Address-Increment -#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 // IMDMA Stream 0 Destination - // Current Descriptor Ptr -#define IMDMA_D0_CURR_ADDR 0xFFC01824 // IMDMA Stream 0 Destination - // Current Address -#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 // IMDMA Stream 0 Destination - // Current Inner-Loop Count -#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 // IMDMA Stream 0 Destination - // Current Outer-Loop Count -#define IMDMA_D0_IRQ_STATUS 0xFFC01828 // IMDMA Stream 0 Destination - // Interrupt/Status - -#define IMDMA_S0_CONFIG 0xFFC01848 // IMDMA Stream 0 Source - // Configuration -#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 // IMDMA Stream 0 Source Next - // Descriptor Ptr Reg -#define IMDMA_S0_START_ADDR 0xFFC01844 // IMDMA Stream 0 Source Start - // Address -#define IMDMA_S0_X_COUNT 0xFFC01850 // IMDMA Stream 0 Source - // Inner-Loop Count -#define IMDMA_S0_Y_COUNT 0xFFC01858 // IMDMA Stream 0 Source - // Outer-Loop Count -#define IMDMA_S0_X_MODIFY 0xFFC01854 // IMDMA Stream 0 Source - // Inner-Loop Address-Increment -#define IMDMA_S0_Y_MODIFY 0xFFC0185C // IMDMA Stream 0 Source - // Outer-Loop Address-Increment -#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 // IMDMA Stream 0 Source - // Current Descriptor Ptr reg -#define IMDMA_S0_CURR_ADDR 0xFFC01864 // IMDMA Stream 0 Source Current - // Address -#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 // IMDMA Stream 0 Source - // Current Inner-Loop Count -#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 // IMDMA Stream 0 Source - // Current Outer-Loop Count -#define IMDMA_S0_IRQ_STATUS 0xFFC01868 // IMDMA Stream 0 Source - // Interrupt/Status - -#define IMDMA_D1_CONFIG 0xFFC01888 // IMDMA Stream 1 Destination - // Configuration -#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 // IMDMA Stream 1 Destination - // Next Descriptor Ptr Reg -#define IMDMA_D1_START_ADDR 0xFFC01884 // IMDMA Stream 1 Destination - // Start Address -#define IMDMA_D1_X_COUNT 0xFFC01890 // IMDMA Stream 1 Destination - // Inner-Loop Count -#define IMDMA_D1_Y_COUNT 0xFFC01898 // IMDMA Stream 1 Destination - // Outer-Loop Count -#define IMDMA_D1_X_MODIFY 0xFFC01894 // IMDMA Stream 1 Dest - // Inner-Loop Address-Increment -#define IMDMA_D1_Y_MODIFY 0xFFC0189C // IMDMA Stream 1 Dest - // Outer-Loop Address-Increment -#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 // IMDMA Stream 1 Destination - // Current Descriptor Ptr -#define IMDMA_D1_CURR_ADDR 0xFFC018A4 // IMDMA Stream 1 Destination - // Current Address -#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 // IMDMA Stream 1 Destination - // Current Inner-Loop Count -#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 // IMDMA Stream 1 Destination - // Current Outer-Loop Count -#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 // IMDMA Stream 1 Destination - // Interrupt/Status - -#define IMDMA_S1_CONFIG 0xFFC018C8 // IMDMA Stream 1 Source - // Configuration -#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 // IMDMA Stream 1 Source Next - // Descriptor Ptr Reg -#define IMDMA_S1_START_ADDR 0xFFC018C4 // IMDMA Stream 1 Source Start - // Address -#define IMDMA_S1_X_COUNT 0xFFC018D0 // IMDMA Stream 1 Source - // Inner-Loop Count -#define IMDMA_S1_Y_COUNT 0xFFC018D8 // IMDMA Stream 1 Source - // Outer-Loop Count -#define IMDMA_S1_X_MODIFY 0xFFC018D4 // IMDMA Stream 1 Source - // Inner-Loop Address-Increment -#define IMDMA_S1_Y_MODIFY 0xFFC018DC // IMDMA Stream 1 Source - // Outer-Loop Address-Increment -#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 // IMDMA Stream 1 Source - // Current Descriptor Ptr reg -#define IMDMA_S1_CURR_ADDR 0xFFC018E4 // IMDMA Stream 1 Source Current - // Address -#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 // IMDMA Stream 1 Source - // Current Inner-Loop Count -#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 // IMDMA Stream 1 Source - // Current Outer-Loop Count -#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 // IMDMA Stream 1 Source - // Interrupt/Status - -//**************************************************************************** -// System MMR Register Bits -//**************************************************************************** - -// ********************* PLL AND RESET MASKS ************************ - -//// PLL_CTL Masks -#define PLL_CLKIN 0x00000000 // Pass CLKIN to PLL -#define PLL_CLKIN_DIV2 0x00000001 // Pass CLKIN/2 to PLL -#define PLL_OFF 0x00000002 // Shut off PLL clocks -#define STOPCK_OFF 0x00000008 // Core clock off -#define PDWN 0x00000020 // Put the PLL in a Deep - // Sleep state -#define BYPASS 0x00000100 // Bypass the PLL - -//// PLL_DIV Masks - -#define SCLK_DIV(x) (x) // SCLK = VCO / x - -#define CCLK_DIV1 0x00000000 // CCLK = VCO / 1 -#define CCLK_DIV2 0x00000010 // CCLK = VCO / 2 -#define CCLK_DIV4 0x00000020 // CCLK = VCO / 4 -#define CCLK_DIV8 0x00000030 // CCLK = VCO / 8 - -// SWRST Mask -#define SYSTEM_RESET 0x00000007 // Initiates a system - // software reset -#define SWRST_DBL_FAULT_B 0x00000800 // SWRST Core B Double Fault -#define SWRST_DBL_FAULT_A 0x00001000 // SWRST Core A Double Fault -#define SWRST_WDT_B 0x00002000 // SWRST Watchdog B -#define SWRST_WDT_A 0x00004000 // SWRST Watchdog A -#define SWRST_OCCURRED 0x00008000 // SWRST Status - -// ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** - -// SICu_IARv Masks -// u = A or B -// v = 0 to 7 -// w = 0 or 1 - -// Per_number = 0 to 63 -// IVG_number = 7 to 15 -// Peripheral #Per_number assigned IVG #IVG_number -// Usage: -// r0.l = lo(Peripheral_IVG(62, 10)); -// r0.h = hi(Peripheral_IVG(62, 10)); -#define Peripheral_IVG(Per_number, IVG_number) \ - ( (IVG_number) -7) << ( ((Per_number)%8) *4) - -// SICx_IMASKw Masks -// masks are 32 bit wide, so two writes reguired for "64 bit" wide registers -#define SIC_UNMASK_ALL 0x00000000 // Unmask all peripheral - // interrupts -#define SIC_MASK_ALL 0xFFFFFFFF // Mask all peripheral - // interrupts -#define SIC_MASK(x) (1 << (x)) // Mask Peripheral #x - // interrupt -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) // Unmask Peripheral #x - // interrupt - -// SIC_IWR Masks -#define IWR_DISABLE_ALL 0x00000000 // Wakeup Disable all - // peripherals -#define IWR_ENABLE_ALL 0xFFFFFFFF // Wakeup Enable all - // peripherals -// x = pos 0 to 31, for 32-63 use value-32 -#define IWR_ENABLE(x) (1 << (x)) // Wakeup Enable Peripheral - // #x -// Wakeup Disable Peripheral #x -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) - -// ********* WATCHDOG TIMER MASKS ********************8 - -// Watchdog Timer WDOG_CTL Register -#define WDOGA_CTL 0xFFC00200 -#define WDOGA_CNT 0xFFC00204 -#define WDOGA_STAT 0xFFC00208 -#define WDOGB_CTL 0xFFC01200 -#define WDOGB_CNT 0xFFC01204 -#define WDOGB_STAT 0xFFC01208 -#define ICTL(x) ((x<<1) & 0x0006) -#define ENABLE_RESET 0x00000000 // Set Watchdog Timer to - // generate reset -#define ENABLE_NMI 0x00000002 // Set Watchdog Timer to - // generate non-maskable - // interrupt -#define ENABLE_GPI 0x00000004 // Set Watchdog Timer to - // generate general-purpose - // interrupt -#define DISABLE_EVT 0x00000006 // Disable Watchdog Timer - // interrupts - -#define TMR_EN 0x0000 -#define TMR_DIS 0x0AD0 -#define TRO 0x8000 - -#define ICTL_P0 0x01 -#define ICTL_P1 0x02 -#define TRO_P 0x0F - -// ***************************** UART CONTROLLER MASKS ********************** - -// UART_LCR Register - -#define DLAB 0x80 -#define SB 0x40 -#define STP 0x20 -#define EPS 0x10 -#define PEN 0x08 -#define STB 0x04 -#define WLS(x) ((x-5) & 0x03) - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -// UART_MCR Register -#define LOOP_ENA 0x10 -#define LOOP_ENA_P 0x04 - -// UART_LSR Register -#define TEMT 0x40 -#define THRE 0x20 -#define BI 0x10 -#define FE 0x08 -#define PE 0x04 -#define OE 0x02 -#define DR 0x01 - -#define TEMP_P 0x06 -#define THRE_P 0x05 -#define BI_P 0x04 -#define FE_P 0x03 -#define PE_P 0x02 -#define OE_P 0x01 -#define DR_P 0x00 - -// UART_IER Register -#define ELSI 0x04 -#define ETBEI 0x02 -#define ERBFI 0x01 - -#define ELSI_P 0x02 -#define ETBEI_P 0x01 -#define ERBFI_P 0x00 - -// UART_IIR Register -#define STATUS(x) ((x << 1) & 0x06) -#define NINT 0x01 -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 -#define NINT_P 0x00 - -// UART_GCTL Register -#define FFE 0x20 -#define FPE 0x10 -#define RPOLC 0x08 -#define TPOLC 0x04 -#define IREN 0x02 -#define UCEN 0x01 - -#define FFE_P 0x05 -#define FPE_P 0x04 -#define RPOLC_P 0x03 -#define TPOLC_P 0x02 -#define IREN_P 0x01 -#define UCEN_P 0x00 - -// ********** SERIAL PORT MASKS ********************** - -// SPORTx_TCR1 Masks -#define TSPEN 0x0001 // TX enable -#define ITCLK 0x0002 // Internal TX Clock Select -#define TDTYPE 0x000C // TX Data Formatting Select -#define TLSBIT 0x0010 // TX Bit Order -#define ITFS 0x0200 // Internal TX Frame Sync Select -#define TFSR 0x0400 // TX Frame Sync Required Select -#define DITFS 0x0800 // Data Independent TX Frame Sync Select -#define LTFS 0x1000 // Low TX Frame Sync Select -#define LATFS 0x2000 // Late TX Frame Sync Select -#define TCKFE 0x4000 // TX Clock Falling Edge Select - -// SPORTx_TCR2 Masks -#define SLEN 0x001F // TX Word Length -#define TXSE 0x0100 // TX Secondary Enable -#define TSFSE 0x0200 // TX Stereo Frame Sync Enable -#define TRFST 0x0400 // TX Right-First Data Order - -// SPORTx_RCR1 Masks -#define RSPEN 0x0001 // RX enable -#define IRCLK 0x0002 // Internal RX Clock Select -#define RDTYPE 0x000C // RX Data Formatting Select -#define RULAW 0x0008 // u-Law enable -#define RALAW 0x000C // A-Law enable -#define RLSBIT 0x0010 // RX Bit Order -#define IRFS 0x0200 // Internal RX Frame Sync Select -#define RFSR 0x0400 // RX Frame Sync Required Select -#define LRFS 0x1000 // Low RX Frame Sync Select -#define LARFS 0x2000 // Late RX Frame Sync Select -#define RCKFE 0x4000 // RX Clock Falling Edge Select - -// SPORTx_RCR2 Masks -#define SLEN 0x001F // RX Word Length -#define RXSE 0x0100 // RX Secondary Enable -#define RSFSE 0x0200 // RX Stereo Frame Sync Enable -#define RRFST 0x0400 // Right-First Data Order - -//SPORTx_STAT Masks -#define RXNE 0x0001 // RX FIFO Not Empty Status -#define RUVF 0x0002 // RX Underflow Status -#define ROVF 0x0004 // RX Overflow Status -#define TXF 0x0008 // TX FIFO Full Status -#define TUVF 0x0010 // TX Underflow Status -#define TOVF 0x0020 // TX Overflow Status -#define TXHRE 0x0040 // TX Hold Register Empty - -//SPORTx_MCMC1 Masks -#define WSIZE 0x0000F000 // Multichannel Window Size Field -#define WOFF 0x000003FF // Multichannel Window Offset Field - -//SPORTx_MCMC2 Masks -#define MCCRM 0x00000003 // Multichannel Clock Recovery Mode -#define MCDTXPE 0x00000004 // Multichannel DMA Transmit Packing -#define MCDRXPE 0x00000008 // Multichannel DMA Receive Packing -#define MCMEN 0x00000010 // Multichannel Frame Mode Enable -#define FSDR 0x00000080 // Multichannel Frame Sync to Data - // Relationship -#define MFD 0x0000F000 // Multichannel Frame Delay - -// ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** - -//// PPI_CONTROL Masks -#define PORT_EN 0x00000001 // PPI Port Enable -#define PORT_DIR 0x00000002 // PPI Port Direction -#define XFR_TYPE 0x0000000C // PPI Transfer Type -#define PORT_CFG 0x00000030 // PPI Port Configuration -#define FLD_SEL 0x00000040 // PPI Active Field Select -#define PACK_EN 0x00000080 // PPI Packing Mode -#define DMA32 0x00000100 // PPI 32-bit DMA Enable -#define SKIP_EN 0x00000200 // PPI Skip Element Enable -#define SKIP_EO 0x00000400 // PPI Skip Even/Odd Elements -#define DLENGTH 0x00003800 // PPI Data Length -#define DLEN_8 0x0 // PPI Data Length mask for DLEN=8 -#define DLEN(x) (((x-9) & 0x07) << 11) // PPI Data Length (only works for - // x=10-->x=16) -#define POL 0x0000C000 // PPI Signal Polarities - -//// PPI_STATUS Masks -#define FLD 0x00000400 // Field Indicator -#define FT_ERR 0x00000800 // Frame Track Error -#define OVR 0x00001000 // FIFO Overflow Error -#define UNDR 0x00002000 // FIFO Underrun Error -#define ERR_DET 0x00004000 // Error Detected Indicator -#define ERR_NCOR 0x00008000 // Error Not Corrected Indicator - -// ********** DMA CONTROLLER MASKS *********************8 - -// DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks -#define DMAEN 0x00000001 // Channel Enable -#define WNR 0x00000002 // Channel Direction (W/R*) -#define WDSIZE_8 0x00000000 // Word Size 8 bits -#define WDSIZE_16 0x00000004 // Word Size 16 bits -#define WDSIZE_32 0x00000008 // Word Size 32 bits -#define DMA2D 0x00000010 // 2D/1D* Mode -#define RESTART 0x00000020 // Restart -#define DI_SEL 0x00000040 // Data Interrupt Select -#define DI_EN 0x00000080 // Data Interrupt Enable -#define NDSIZE 0x00000900 // Next Descriptor Size -#define FLOW 0x00007000 // Flow Control - -#define DMAEN_P 0 // Channel Enable -#define WNR_P 1 // Channel Direction (W/R*) -#define DMA2D_P 4 // 2D/1D* Mode -#define RESTART_P 5 // Restart -#define DI_SEL_P 6 // Data Interrupt Select -#define DI_EN_P 7 // Data Interrupt Enable - -////DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks - -#define DMA_DONE 0x00000001 // DMA Done Indicator -#define DMA_ERR 0x00000002 // DMA Error Indicator -#define DFETCH 0x00000004 // Descriptor Fetch Indicator -#define DMA_RUN 0x00000008 // DMA Running Indicator - -#define DMA_DONE_P 0 // DMA Done Indicator -#define DMA_ERR_P 1 // DMA Error Indicator -#define DFETCH_P 2 // Descriptor Fetch Indicator -#define DMA_RUN_P 3 // DMA Running Indicator - -////DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks - -#define CTYPE 0x00000040 // DMA Channel Type Indicator -#define CTYPE_P 6 // DMA Channel Type Indicator BIT POSITION -#define PCAP8 0x00000080 // DMA 8-bit Operation Indicator -#define PCAP16 0x00000100 // DMA 16-bit Operation Indicator -#define PCAP32 0x00000200 // DMA 32-bit Operation Indicator -#define PCAPWR 0x00000400 // DMA Write Operation Indicator -#define PCAPRD 0x00000800 // DMA Read Operation Indicator -#define PMAP 0x00007000 // DMA Peripheral Map Field - -// ************* GENERAL PURPOSE TIMER MASKS ******************** - -/* PWM Timer bit definitions */ - -// TIMER_ENABLE Register -#define TIMEN0 0x0001 -#define TIMEN1 0x0002 -#define TIMEN2 0x0004 -#define TIMEN3 0x0008 -#define TIMEN4 0x0010 -#define TIMEN5 0x0020 -#define TIMEN6 0x0040 -#define TIMEN7 0x0080 -#define TIMEN8 0x0001 -#define TIMEN9 0x0002 -#define TIMEN10 0x0004 -#define TIMEN11 0x0008 - -#define TIMEN0_P 0x00 -#define TIMEN1_P 0x01 -#define TIMEN2_P 0x02 -#define TIMEN3_P 0x03 -#define TIMEN4_P 0x04 -#define TIMEN5_P 0x05 -#define TIMEN6_P 0x06 -#define TIMEN7_P 0x07 -#define TIMEN8_P 0x00 -#define TIMEN9_P 0x01 -#define TIMEN10_P 0x02 -#define TIMEN11_P 0x03 - -// TIMER_DISABLE Register -#define TIMDIS0 0x0001 -#define TIMDIS1 0x0002 -#define TIMDIS2 0x0004 -#define TIMDIS3 0x0008 -#define TIMDIS4 0x0010 -#define TIMDIS5 0x0020 -#define TIMDIS6 0x0040 -#define TIMDIS7 0x0080 -#define TIMDIS8 0x0001 -#define TIMDIS9 0x0002 -#define TIMDIS10 0x0004 -#define TIMDIS11 0x0008 - -#define TIMDIS0_P 0x00 -#define TIMDIS1_P 0x01 -#define TIMDIS2_P 0x02 -#define TIMDIS3_P 0x03 -#define TIMDIS4_P 0x04 -#define TIMDIS5_P 0x05 -#define TIMDIS6_P 0x06 -#define TIMDIS7_P 0x07 -#define TIMDIS8_P 0x00 -#define TIMDIS9_P 0x01 -#define TIMDIS10_P 0x02 -#define TIMDIS11_P 0x03 - -// TIMER_STATUS Register -#define TIMIL0 0x00000001 -#define TIMIL1 0x00000002 -#define TIMIL2 0x00000004 -#define TIMIL3 0x00000008 -#define TIMIL4 0x00010000 -#define TIMIL5 0x00020000 -#define TIMIL6 0x00040000 -#define TIMIL7 0x00080000 -#define TIMIL8 0x0001 -#define TIMIL9 0x0002 -#define TIMIL10 0x0004 -#define TIMIL11 0x0008 -#define TOVL_ERR0 0x00000010 -#define TOVL_ERR1 0x00000020 -#define TOVL_ERR2 0x00000040 -#define TOVL_ERR3 0x00000080 -#define TOVL_ERR4 0x00100000 -#define TOVL_ERR5 0x00200000 -#define TOVL_ERR6 0x00400000 -#define TOVL_ERR7 0x00800000 -#define TOVL_ERR8 0x0010 -#define TOVL_ERR9 0x0020 -#define TOVL_ERR10 0x0040 -#define TOVL_ERR11 0x0080 -#define TRUN0 0x00001000 -#define TRUN1 0x00002000 -#define TRUN2 0x00004000 -#define TRUN3 0x00008000 -#define TRUN4 0x10000000 -#define TRUN5 0x20000000 -#define TRUN6 0x40000000 -#define TRUN7 0x80000000 -#define TRUN8 0x1000 -#define TRUN9 0x2000 -#define TRUN10 0x4000 -#define TRUN11 0x8000 - -#define TIMIL0_P 0x00 -#define TIMIL1_P 0x01 -#define TIMIL2_P 0x02 -#define TIMIL3_P 0x03 -#define TIMIL4_P 0x10 -#define TIMIL5_P 0x11 -#define TIMIL6_P 0x12 -#define TIMIL7_P 0x13 -#define TIMIL8_P 0x00 -#define TIMIL9_P 0x01 -#define TIMIL10_P 0x02 -#define TIMIL11_P 0x03 -#define TOVL_ERR0_P 0x04 -#define TOVL_ERR1_P 0x05 -#define TOVL_ERR2_P 0x06 -#define TOVL_ERR3_P 0x07 -#define TOVL_ERR4_P 0x14 -#define TOVL_ERR5_P 0x15 -#define TOVL_ERR6_P 0x16 -#define TOVL_ERR7_P 0x17 -#define TOVL_ERR8_P 0x04 -#define TOVL_ERR9_P 0x05 -#define TOVL_ERR10_P 0x06 -#define TOVL_ERR11_P 0x07 -#define TRUN0_P 0x0C -#define TRUN1_P 0x0D -#define TRUN2_P 0x0E -#define TRUN3_P 0x0F -#define TRUN4_P 0x1C -#define TRUN5_P 0x1D -#define TRUN6_P 0x1E -#define TRUN7_P 0x1F -#define TRUN8_P 0x0C -#define TRUN9_P 0x0D -#define TRUN10_P 0x0E -#define TRUN11_P 0x0F - -// TIMERx_CONFIG Registers -#define PWM_OUT 0x0001 -#define WDTH_CAP 0x0002 -#define EXT_CLK 0x0003 -#define PULSE_HI 0x0004 -#define PERIOD_CNT 0x0008 -#define IRQ_ENA 0x0010 -#define TIN_SEL 0x0020 -#define OUT_DIS 0x0040 -#define CLK_SEL 0x0080 -#define TOGGLE_HI 0x0100 -#define EMU_RUN 0x0200 -#define ERR_TYP(x) ((x & 0x03) << 14) - -#define TMODE_P0 0x00 -#define TMODE_P1 0x01 -#define PULSE_HI_P 0x02 -#define PERIOD_CNT_P 0x03 -#define IRQ_ENA_P 0x04 -#define TIN_SEL_P 0x05 -#define OUT_DIS_P 0x06 -#define CLK_SEL_P 0x07 -#define TOGGLE_HI_P 0x08 -#define EMU_RUN_P 0x09 -#define ERR_TYP_P0 0x0E -#define ERR_TYP_P1 0x0F - -/// ****************** PROGRAMMABLE FLAG MASKS ********************* - -// General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -// General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS -#define PF0_P 0 -#define PF1_P 1 -#define PF2_P 2 -#define PF3_P 3 -#define PF4_P 4 -#define PF5_P 5 -#define PF6_P 6 -#define PF7_P 7 -#define PF8_P 8 -#define PF9_P 9 -#define PF10_P 10 -#define PF11_P 11 -#define PF12_P 12 -#define PF13_P 13 -#define PF14_P 14 -#define PF15_P 15 - -// *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** - -//// SPI_CTL Masks -#define TIMOD 0x00000003 // Transfer initiation mode - // and interrupt generation -#define SZ 0x00000004 // Send Zero (=0) or last - // (=1) word when TDBR empty. -#define GM 0x00000008 // When RDBR full, get more - // (=1) data or discard (=0) - // incoming Data -#define PSSE 0x00000010 // Enable (=1) Slave-Select - // input for Master. -#define EMISO 0x00000020 // Enable (=1) MISO pin as an - // output. -#define SIZE 0x00000100 // Word length (0 => 8 bits, - // 1 => 16 bits) -#define LSBF 0x00000200 // Data format (0 => MSB - // sent/received first 1 => - // LSB sent/received first) -#define CPHA 0x00000400 // Clock phase (0 => SPICLK - // starts toggling in middle - // of xfer, 1 => SPICLK - // toggles at the beginning - // of xfer. -#define CPOL 0x00000800 // Clock polarity (0 => - // active-high, 1 => - // active-low) -#define MSTR 0x00001000 // Configures SPI as master - // (=1) or slave (=0) -#define WOM 0x00002000 // Open drain (=1) data - // output enable (for MOSI - // and MISO) -#define SPE 0x00004000 // SPI module enable (=1), - // disable (=0) - -//// SPI_FLG Masks -#define FLS1 0x00000002 // Enables (=1) SPI_FLOUT1 as - // flag output for SPI - // Slave-select -#define FLS2 0x00000004 // Enables (=1) SPI_FLOUT2 as - // flag output for SPI - // Slave-select -#define FLS3 0x00000008 // Enables (=1) SPI_FLOUT3 as - // flag output for SPI - // Slave-select -#define FLS4 0x00000010 // Enables (=1) SPI_FLOUT4 as - // flag output for SPI - // Slave-select -#define FLS5 0x00000020 // Enables (=1) SPI_FLOUT5 as - // flag output for SPI - // Slave-select -#define FLS6 0x00000040 // Enables (=1) SPI_FLOUT6 as - // flag output for SPI - // Slave-select -#define FLS7 0x00000080 // Enables (=1) SPI_FLOUT7 as - // flag output for SPI - // Slave-select -#define FLG1 0x00000200 // Activates (=0) SPI_FLOUT1 - // as flag output for SPI - // Slave-select -#define FLG2 0x00000400 // Activates (=0) SPI_FLOUT2 - // as flag output for SPI - // Slave-select -#define FLG3 0x00000800 // Activates (=0) SPI_FLOUT3 - // as flag output for SPI - // Slave-select -#define FLG4 0x00001000 // Activates (=0) SPI_FLOUT4 - // as flag output for SPI - // Slave-select -#define FLG5 0x00002000 // Activates (=0) SPI_FLOUT5 - // as flag output for SPI - // Slave-select -#define FLG6 0x00004000 // Activates (=0) SPI_FLOUT6 - // as flag output for SPI - // Slave-select -#define FLG7 0x00008000 // Activates (=0) SPI_FLOUT7 - // as flag output for SPI - // Slave-select - -//// SPI_FLG Bit Positions -#define FLS1_P 0x00000001 // Enables (=1) SPI_FLOUT1 as - // flag output for SPI - // Slave-select -#define FLS2_P 0x00000002 // Enables (=1) SPI_FLOUT2 as - // flag output for SPI - // Slave-select -#define FLS3_P 0x00000003 // Enables (=1) SPI_FLOUT3 as - // flag output for SPI - // Slave-select -#define FLS4_P 0x00000004 // Enables (=1) SPI_FLOUT4 as - // flag output for SPI - // Slave-select -#define FLS5_P 0x00000005 // Enables (=1) SPI_FLOUT5 as - // flag output for SPI - // Slave-select -#define FLS6_P 0x00000006 // Enables (=1) SPI_FLOUT6 as - // flag output for SPI - // Slave-select -#define FLS7_P 0x00000007 // Enables (=1) SPI_FLOUT7 as - // flag output for SPI - // Slave-select -#define FLG1_P 0x00000009 // Activates (=0) SPI_FLOUT1 - // as flag output for SPI - // Slave-select -#define FLG2_P 0x0000000A // Activates (=0) SPI_FLOUT2 - // as flag output for SPI - // Slave-select -#define FLG3_P 0x0000000B // Activates (=0) SPI_FLOUT3 - // as flag output for SPI - // Slave-select -#define FLG4_P 0x0000000C // Activates (=0) SPI_FLOUT4 - // as flag output for SPI - // Slave-select -#define FLG5_P 0x0000000D // Activates (=0) SPI_FLOUT5 - // as flag output for SPI - // Slave-select -#define FLG6_P 0x0000000E // Activates (=0) SPI_FLOUT6 - // as flag output for SPI - // Slave-select -#define FLG7_P 0x0000000F // Activates (=0) SPI_FLOUT7 - // as flag output for SPI - // Slave-select - -//// SPI_STAT Masks -#define SPIF 0x00000001 // Set (=1) when SPI - // single-word transfer - // complete -#define MODF 0x00000002 // Set (=1) in a master - // device when some other - // device tries to become - // master -#define TXE 0x00000004 // Set (=1) when transmission - // occurs with no new data in - // SPI_TDBR -#define TXS 0x00000008 // SPI_TDBR Data Buffer - // Status (0=Empty, 1=Full) -#define RBSY 0x00000010 // Set (=1) when data is - // received with RDBR full -#define RXS 0x00000020 // SPI_RDBR Data Buffer - // Status (0=Empty, 1=Full) -#define TXCOL 0x00000040 // When set (=1), corrupt - // data may have been - // transmitted - -// ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* - -// AMGCTL Masks -#define AMCKEN 0x0001 // Enable CLKOUT -#define AMBEN_B0 0x0002 // Enable Asynchronous Memory Bank 0 - // only -#define AMBEN_B0_B1 0x0004 // Enable Asynchronous Memory Banks 0 - // & 1 only -#define AMBEN_B0_B1_B2 0x0006 // Enable Asynchronous Memory Banks 0, - // 1, and 2 -#define AMBEN_ALL 0x0008 // Enable Asynchronous Memory Banks - // (all) 0, 1, 2, and 3 -#define B0_PEN 0x0010 // Enable 16-bit packing Bank 0 -#define B1_PEN 0x0020 // Enable 16-bit packing Bank 1 -#define B2_PEN 0x0040 // Enable 16-bit packing Bank 2 -#define B3_PEN 0x0080 // Enable 16-bit packing Bank 3 - -// AMGCTL Bit Positions -#define AMCKEN_P 0x00000000 // Enable CLKOUT -#define AMBEN_P0 0x00000001 // Asynchronous Memory - // Enable, 000 - banks 0-3 - // disabled, 001 - Bank 0 - // enabled -#define AMBEN_P1 0x00000002 // Asynchronous Memory - // Enable, 010 - banks 0&1 - // enabled, 011 - banks 0-3 - // enabled -#define AMBEN_P2 0x00000003 // Asynchronous Memory - // Enable, 1xx - All banks - // (bank 0, 1, 2, and 3) - // enabled -#define B0_PEN_P 0x004 // Enable 16-bit packing Bank 0 -#define B1_PEN_P 0x005 // Enable 16-bit packing Bank 1 -#define B2_PEN_P 0x006 // Enable 16-bit packing Bank 2 -#define B3_PEN_P 0x007 // Enable 16-bit packing Bank 3 - -// AMBCTL0 Masks -#define B0RDYEN 0x00000001 // Bank 0 RDY Enable, - // 0=disable, 1=enable -#define B0RDYPOL 0x00000002 // Bank 0 RDY Active high, - // 0=active low, 1=active high -#define B0TT_1 0x00000004 // Bank 0 Transition Time from - // Read to Write = 1 cycle -#define B0TT_2 0x00000008 // Bank 0 Transition Time from - // Read to Write = 2 cycles -#define B0TT_3 0x0000000C // Bank 0 Transition Time from - // Read to Write = 3 cycles -#define B0TT_4 0x00000000 // Bank 0 Transition Time from - // Read to Write = 4 cycles -#define B0ST_1 0x00000010 // Bank 0 Setup Time from AOE - // asserted to Read/Write - // asserted=1 cycle -#define B0ST_2 0x00000020 // Bank 0 Setup Time from AOE - // asserted to Read/Write - // asserted=2 cycles -#define B0ST_3 0x00000030 // Bank 0 Setup Time from AOE - // asserted to Read/Write - // asserted=3 cycles -#define B0ST_4 0x00000000 // Bank 0 Setup Time from AOE - // asserted to Read/Write - // asserted=4 cycles -#define B0HT_1 0x00000040 // Bank 0 Hold Time from - // Read/Write deasserted to AOE - // deasserted = 1 cycle -#define B0HT_2 0x00000080 // Bank 0 Hold Time from - // Read/Write deasserted to AOE - // deasserted = 2 cycles -#define B0HT_3 0x000000C0 // Bank 0 Hold Time from - // Read/Write deasserted to AOE - // deasserted = 3 cycles -#define B0HT_0 0x00000000 // Bank 0 Hold Time from - // Read/Write deasserted to AOE - // deasserted = 0 cycles -#define B0RAT_1 0x00000100 // Bank 0 Read Access Time = - // 1 cycle -#define B0RAT_2 0x00000200 // Bank 0 Read Access Time = - // 2 cycles -#define B0RAT_3 0x00000300 // Bank 0 Read Access Time = - // 3 cycles -#define B0RAT_4 0x00000400 // Bank 0 Read Access Time = - // 4 cycles -#define B0RAT_5 0x00000500 // Bank 0 Read Access Time = - // 5 cycles -#define B0RAT_6 0x00000600 // Bank 0 Read Access Time = - // 6 cycles -#define B0RAT_7 0x00000700 // Bank 0 Read Access Time = - // 7 cycles -#define B0RAT_8 0x00000800 // Bank 0 Read Access Time = - // 8 cycles -#define B0RAT_9 0x00000900 // Bank 0 Read Access Time = - // 9 cycles -#define B0RAT_10 0x00000A00 // Bank 0 Read Access Time = - // 10 cycles -#define B0RAT_11 0x00000B00 // Bank 0 Read Access Time = - // 11 cycles -#define B0RAT_12 0x00000C00 // Bank 0 Read Access Time = - // 12 cycles -#define B0RAT_13 0x00000D00 // Bank 0 Read Access Time = - // 13 cycles -#define B0RAT_14 0x00000E00 // Bank 0 Read Access Time = - // 14 cycles -#define B0RAT_15 0x00000F00 // Bank 0 Read Access Time = - // 15 cycles -#define B0WAT_1 0x00001000 // Bank 0 Write Access Time = - // 1 cycle -#define B0WAT_2 0x00002000 // Bank 0 Write Access Time = - // 2 cycles -#define B0WAT_3 0x00003000 // Bank 0 Write Access Time = - // 3 cycles -#define B0WAT_4 0x00004000 // Bank 0 Write Access Time = - // 4 cycles -#define B0WAT_5 0x00005000 // Bank 0 Write Access Time = - // 5 cycles -#define B0WAT_6 0x00006000 // Bank 0 Write Access Time = - // 6 cycles -#define B0WAT_7 0x00007000 // Bank 0 Write Access Time = - // 7 cycles -#define B0WAT_8 0x00008000 // Bank 0 Write Access Time = - // 8 cycles -#define B0WAT_9 0x00009000 // Bank 0 Write Access Time = - // 9 cycles -#define B0WAT_10 0x0000A000 // Bank 0 Write Access Time = - // 10 cycles -#define B0WAT_11 0x0000B000 // Bank 0 Write Access Time = - // 11 cycles -#define B0WAT_12 0x0000C000 // Bank 0 Write Access Time = - // 12 cycles -#define B0WAT_13 0x0000D000 // Bank 0 Write Access Time = - // 13 cycles -#define B0WAT_14 0x0000E000 // Bank 0 Write Access Time = - // 14 cycles -#define B0WAT_15 0x0000F000 // Bank 0 Write Access Time = - // 15 cycles -#define B1RDYEN 0x00010000 // Bank 1 RDY enable, - // 0=disable, 1=enable -#define B1RDYPOL 0x00020000 // Bank 1 RDY Active high, - // 0=active low, 1=active - // high -#define B1TT_1 0x00040000 // Bank 1 Transition Time - // from Read to Write = 1 - // cycle -#define B1TT_2 0x00080000 // Bank 1 Transition Time - // from Read to Write = 2 - // cycles -#define B1TT_3 0x000C0000 // Bank 1 Transition Time - // from Read to Write = 3 - // cycles -#define B1TT_4 0x00000000 // Bank 1 Transition Time - // from Read to Write = 4 - // cycles -#define B1ST_1 0x00100000 // Bank 1 Setup Time from AOE - // asserted to Read or Write - // asserted = 1 cycle -#define B1ST_2 0x00200000 // Bank 1 Setup Time from AOE - // asserted to Read or Write - // asserted = 2 cycles -#define B1ST_3 0x00300000 // Bank 1 Setup Time from AOE - // asserted to Read or Write - // asserted = 3 cycles -#define B1ST_4 0x00000000 // Bank 1 Setup Time from AOE - // asserted to Read or Write - // asserted = 4 cycles -#define B1HT_1 0x00400000 // Bank 1 Hold Time from Read - // or Write deasserted to AOE - // deasserted = 1 cycle -#define B1HT_2 0x00800000 // Bank 1 Hold Time from Read - // or Write deasserted to AOE - // deasserted = 2 cycles -#define B1HT_3 0x00C00000 // Bank 1 Hold Time from Read - // or Write deasserted to AOE - // deasserted = 3 cycles -#define B1HT_0 0x00000000 // Bank 1 Hold Time from Read - // or Write deasserted to AOE - // deasserted = 0 cycles -#define B1RAT_1 0x01000000 // Bank 1 Read Access Time = - // 1 cycle -#define B1RAT_2 0x02000000 // Bank 1 Read Access Time = - // 2 cycles -#define B1RAT_3 0x03000000 // Bank 1 Read Access Time = - // 3 cycles -#define B1RAT_4 0x04000000 // Bank 1 Read Access Time = - // 4 cycles -#define B1RAT_5 0x05000000 // Bank 1 Read Access Time = - // 5 cycles -#define B1RAT_6 0x06000000 // Bank 1 Read Access Time = - // 6 cycles -#define B1RAT_7 0x07000000 // Bank 1 Read Access Time = - // 7 cycles -#define B1RAT_8 0x08000000 // Bank 1 Read Access Time = - // 8 cycles -#define B1RAT_9 0x09000000 // Bank 1 Read Access Time = - // 9 cycles -#define B1RAT_10 0x0A000000 // Bank 1 Read Access Time = - // 10 cycles -#define B1RAT_11 0x0B000000 // Bank 1 Read Access Time = - // 11 cycles -#define B1RAT_12 0x0C000000 // Bank 1 Read Access Time = - // 12 cycles -#define B1RAT_13 0x0D000000 // Bank 1 Read Access Time = - // 13 cycles -#define B1RAT_14 0x0E000000 // Bank 1 Read Access Time = - // 14 cycles -#define B1RAT_15 0x0F000000 // Bank 1 Read Access Time = - // 15 cycles -#define B1WAT_1 0x10000000 // Bank 1 Write Access Time = - // 1 cycle -#define B1WAT_2 0x20000000 // Bank 1 Write Access Time = - // 2 cycles -#define B1WAT_3 0x30000000 // Bank 1 Write Access Time = - // 3 cycles -#define B1WAT_4 0x40000000 // Bank 1 Write Access Time = - // 4 cycles -#define B1WAT_5 0x50000000 // Bank 1 Write Access Time = - // 5 cycles -#define B1WAT_6 0x60000000 // Bank 1 Write Access Time = - // 6 cycles -#define B1WAT_7 0x70000000 // Bank 1 Write Access Time = - // 7 cycles -#define B1WAT_8 0x80000000 // Bank 1 Write Access Time = - // 8 cycles -#define B1WAT_9 0x90000000 // Bank 1 Write Access Time = - // 9 cycles -#define B1WAT_10 0xA0000000 // Bank 1 Write Access Time = - // 10 cycles -#define B1WAT_11 0xB0000000 // Bank 1 Write Access Time = - // 11 cycles -#define B1WAT_12 0xC0000000 // Bank 1 Write Access Time = - // 12 cycles -#define B1WAT_13 0xD0000000 // Bank 1 Write Access Time = - // 13 cycles -#define B1WAT_14 0xE0000000 // Bank 1 Write Access Time = - // 14 cycles -#define B1WAT_15 0xF0000000 // Bank 1 Write Access Time = - // 15 cycles - -// AMBCTL1 Masks -#define B2RDYEN 0x00000001 // Bank 2 RDY Enable, - // 0=disable, 1=enable -#define B2RDYPOL 0x00000002 // Bank 2 RDY Active high, - // 0=active low, 1=active - // high -#define B2TT_1 0x00000004 // Bank 2 Transition Time - // from Read to Write = 1 - // cycle -#define B2TT_2 0x00000008 // Bank 2 Transition Time - // from Read to Write = 2 - // cycles -#define B2TT_3 0x0000000C // Bank 2 Transition Time - // from Read to Write = 3 - // cycles -#define B2TT_4 0x00000000 // Bank 2 Transition Time - // from Read to Write = 4 - // cycles -#define B2ST_1 0x00000010 // Bank 2 Setup Time from AOE - // asserted to Read or Write - // asserted = 1 cycle -#define B2ST_2 0x00000020 // Bank 2 Setup Time from AOE - // asserted to Read or Write - // asserted = 2 cycles -#define B2ST_3 0x00000030 // Bank 2 Setup Time from AOE - // asserted to Read or Write - // asserted = 3 cycles -#define B2ST_4 0x00000000 // Bank 2 Setup Time from AOE - // asserted to Read or Write - // asserted = 4 cycles -#define B2HT_1 0x00000040 // Bank 2 Hold Time from Read - // or Write deasserted to AOE - // deasserted = 1 cycle -#define B2HT_2 0x00000080 // Bank 2 Hold Time from Read - // or Write deasserted to AOE - // deasserted = 2 cycles -#define B2HT_3 0x000000C0 // Bank 2 Hold Time from Read - // or Write deasserted to AOE - // deasserted = 3 cycles -#define B2HT_0 0x00000000 // Bank 2 Hold Time from Read - // or Write deasserted to AOE - // deasserted = 0 cycles -#define B2RAT_1 0x00000100 // Bank 2 Read Access Time = - // 1 cycle -#define B2RAT_2 0x00000200 // Bank 2 Read Access Time = - // 2 cycles -#define B2RAT_3 0x00000300 // Bank 2 Read Access Time = - // 3 cycles -#define B2RAT_4 0x00000400 // Bank 2 Read Access Time = - // 4 cycles -#define B2RAT_5 0x00000500 // Bank 2 Read Access Time = - // 5 cycles -#define B2RAT_6 0x00000600 // Bank 2 Read Access Time = - // 6 cycles -#define B2RAT_7 0x00000700 // Bank 2 Read Access Time = - // 7 cycles -#define B2RAT_8 0x00000800 // Bank 2 Read Access Time = - // 8 cycles -#define B2RAT_9 0x00000900 // Bank 2 Read Access Time = - // 9 cycles -#define B2RAT_10 0x00000A00 // Bank 2 Read Access Time = - // 10 cycles -#define B2RAT_11 0x00000B00 // Bank 2 Read Access Time = - // 11 cycles -#define B2RAT_12 0x00000C00 // Bank 2 Read Access Time = - // 12 cycles -#define B2RAT_13 0x00000D00 // Bank 2 Read Access Time = - // 13 cycles -#define B2RAT_14 0x00000E00 // Bank 2 Read Access Time = - // 14 cycles -#define B2RAT_15 0x00000F00 // Bank 2 Read Access Time = - // 15 cycles -#define B2WAT_1 0x00001000 // Bank 2 Write Access Time = - // 1 cycle -#define B2WAT_2 0x00002000 // Bank 2 Write Access Time = - // 2 cycles -#define B2WAT_3 0x00003000 // Bank 2 Write Access Time = - // 3 cycles -#define B2WAT_4 0x00004000 // Bank 2 Write Access Time = - // 4 cycles -#define B2WAT_5 0x00005000 // Bank 2 Write Access Time = - // 5 cycles -#define B2WAT_6 0x00006000 // Bank 2 Write Access Time = - // 6 cycles -#define B2WAT_7 0x00007000 // Bank 2 Write Access Time = - // 7 cycles -#define B2WAT_8 0x00008000 // Bank 2 Write Access Time = - // 8 cycles -#define B2WAT_9 0x00009000 // Bank 2 Write Access Time = - // 9 cycles -#define B2WAT_10 0x0000A000 // Bank 2 Write Access Time = - // 10 cycles -#define B2WAT_11 0x0000B000 // Bank 2 Write Access Time = - // 11 cycles -#define B2WAT_12 0x0000C000 // Bank 2 Write Access Time = - // 12 cycles -#define B2WAT_13 0x0000D000 // Bank 2 Write Access Time = - // 13 cycles -#define B2WAT_14 0x0000E000 // Bank 2 Write Access Time = - // 14 cycles -#define B2WAT_15 0x0000F000 // Bank 2 Write Access Time = - // 15 cycles -#define B3RDYEN 0x00010000 // Bank 3 RDY enable, - // 0=disable, 1=enable -#define B3RDYPOL 0x00020000 // Bank 3 RDY Active high, - // 0=active low, 1=active - // high -#define B3TT_1 0x00040000 // Bank 3 Transition Time - // from Read to Write = 1 - // cycle -#define B3TT_2 0x00080000 // Bank 3 Transition Time - // from Read to Write = 2 - // cycles -#define B3TT_3 0x000C0000 // Bank 3 Transition Time - // from Read to Write = 3 - // cycles -#define B3TT_4 0x00000000 // Bank 3 Transition Time - // from Read to Write = 4 - // cycles -#define B3ST_1 0x00100000 // Bank 3 Setup Time from AOE - // asserted to Read or Write - // asserted = 1 cycle -#define B3ST_2 0x00200000 // Bank 3 Setup Time from AOE - // asserted to Read or Write - // asserted = 2 cycles -#define B3ST_3 0x00300000 // Bank 3 Setup Time from AOE - // asserted to Read or Write - // asserted = 3 cycles -#define B3ST_4 0x00000000 // Bank 3 Setup Time from AOE - // asserted to Read or Write - // asserted = 4 cycles -#define B3HT_1 0x00400000 // Bank 3 Hold Time from Read - // or Write deasserted to AOE - // deasserted = 1 cycle -#define B3HT_2 0x00800000 // Bank 3 Hold Time from Read - // or Write deasserted to AOE - // deasserted = 2 cycles -#define B3HT_3 0x00C00000 // Bank 3 Hold Time from Read - // or Write deasserted to AOE - // deasserted = 3 cycles -#define B3HT_0 0x00000000 // Bank 3 Hold Time from Read - // or Write deasserted to AOE - // deasserted = 0 cycles -#define B3RAT_1 0x01000000 // Bank 3 Read Access Time = - // 1 cycle -#define B3RAT_2 0x02000000 // Bank 3 Read Access Time = - // 2 cycles -#define B3RAT_3 0x03000000 // Bank 3 Read Access Time = - // 3 cycles -#define B3RAT_4 0x04000000 // Bank 3 Read Access Time = - // 4 cycles -#define B3RAT_5 0x05000000 // Bank 3 Read Access Time = - // 5 cycles -#define B3RAT_6 0x06000000 // Bank 3 Read Access Time = - // 6 cycles -#define B3RAT_7 0x07000000 // Bank 3 Read Access Time = - // 7 cycles -#define B3RAT_8 0x08000000 // Bank 3 Read Access Time = - // 8 cycles -#define B3RAT_9 0x09000000 // Bank 3 Read Access Time = - // 9 cycles -#define B3RAT_10 0x0A000000 // Bank 3 Read Access Time = - // 10 cycles -#define B3RAT_11 0x0B000000 // Bank 3 Read Access Time = - // 11 cycles -#define B3RAT_12 0x0C000000 // Bank 3 Read Access Time = - // 12 cycles -#define B3RAT_13 0x0D000000 // Bank 3 Read Access Time = - // 13 cycles -#define B3RAT_14 0x0E000000 // Bank 3 Read Access Time = - // 14 cycles -#define B3RAT_15 0x0F000000 // Bank 3 Read Access Time = - // 15 cycles -#define B3WAT_1 0x10000000 // Bank 3 Write Access Time = - // 1 cycle -#define B3WAT_2 0x20000000 // Bank 3 Write Access Time = - // 2 cycles -#define B3WAT_3 0x30000000 // Bank 3 Write Access Time = - // 3 cycles -#define B3WAT_4 0x40000000 // Bank 3 Write Access Time = - // 4 cycles -#define B3WAT_5 0x50000000 // Bank 3 Write Access Time = - // 5 cycles -#define B3WAT_6 0x60000000 // Bank 3 Write Access Time = - // 6 cycles -#define B3WAT_7 0x70000000 // Bank 3 Write Access Time = - // 7 cycles -#define B3WAT_8 0x80000000 // Bank 3 Write Access Time = - // 8 cycles -#define B3WAT_9 0x90000000 // Bank 3 Write Access Time = - // 9 cycles -#define B3WAT_10 0xA0000000 // Bank 3 Write Access Time = - // 10 cycles -#define B3WAT_11 0xB0000000 // Bank 3 Write Access Time = - // 11 cycles -#define B3WAT_12 0xC0000000 // Bank 3 Write Access Time = - // 12 cycles -#define B3WAT_13 0xD0000000 // Bank 3 Write Access Time = - // 13 cycles -#define B3WAT_14 0xE0000000 // Bank 3 Write Access Time = - // 14 cycles -#define B3WAT_15 0xF0000000 // Bank 3 Write Access Time = - // 15 cycles - -// ********************** SDRAM CONTROLLER MASKS *************************** - -// EBIU_SDGCTL Masks -#define SCTLE 0x00000001 // Enable SCLK[0], /SRAS, - // /SCAS, /SWE, SDQM[3:0] -#define CL_2 0x00000008 // SDRAM CAS latency = 2 - // cycles -#define CL_3 0x0000000C // SDRAM CAS latency = 3 - // cycles -#define PFE 0x00000010 // Enable SDRAM prefetch -#define PFP 0x00000020 // Prefetch has priority over - // AMC requests -#define TRAS_1 0x00000040 // SDRAM tRAS = 1 cycle -#define TRAS_2 0x00000080 // SDRAM tRAS = 2 cycles -#define TRAS_3 0x000000C0 // SDRAM tRAS = 3 cycles -#define TRAS_4 0x00000100 // SDRAM tRAS = 4 cycles -#define TRAS_5 0x00000140 // SDRAM tRAS = 5 cycles -#define TRAS_6 0x00000180 // SDRAM tRAS = 6 cycles -#define TRAS_7 0x000001C0 // SDRAM tRAS = 7 cycles -#define TRAS_8 0x00000200 // SDRAM tRAS = 8 cycles -#define TRAS_9 0x00000240 // SDRAM tRAS = 9 cycles -#define TRAS_10 0x00000280 // SDRAM tRAS = 10 cycles -#define TRAS_11 0x000002C0 // SDRAM tRAS = 11 cycles -#define TRAS_12 0x00000300 // SDRAM tRAS = 12 cycles -#define TRAS_13 0x00000340 // SDRAM tRAS = 13 cycles -#define TRAS_14 0x00000380 // SDRAM tRAS = 14 cycles -#define TRAS_15 0x000003C0 // SDRAM tRAS = 15 cycles -#define TRP_1 0x00000800 // SDRAM tRP = 1 cycle -#define TRP_2 0x00001000 // SDRAM tRP = 2 cycles -#define TRP_3 0x00001800 // SDRAM tRP = 3 cycles -#define TRP_4 0x00002000 // SDRAM tRP = 4 cycles -#define TRP_5 0x00002800 // SDRAM tRP = 5 cycles -#define TRP_6 0x00003000 // SDRAM tRP = 6 cycles -#define TRP_7 0x00003800 // SDRAM tRP = 7 cycles -#define TRCD_1 0x00008000 // SDRAM tRCD = 1 cycle -#define TRCD_2 0x00010000 // SDRAM tRCD = 2 cycles -#define TRCD_3 0x00018000 // SDRAM tRCD = 3 cycles -#define TRCD_4 0x00020000 // SDRAM tRCD = 4 cycles -#define TRCD_5 0x00028000 // SDRAM tRCD = 5 cycles -#define TRCD_6 0x00030000 // SDRAM tRCD = 6 cycles -#define TRCD_7 0x00038000 // SDRAM tRCD = 7 cycles -#define TWR_1 0x00080000 // SDRAM tWR = 1 cycle -#define TWR_2 0x00100000 // SDRAM tWR = 2 cycles -#define TWR_3 0x00180000 // SDRAM tWR = 3 cycles -#define PUPSD 0x00200000 // Power-up start delay -#define PSM 0x00400000 // SDRAM power-up sequence = - // Precharge, mode register - // set, 8 CBR refresh cycles -#define PSS 0x00800000 // enable SDRAM power-up - // sequence on next SDRAM access -#define SRFS 0x01000000 // Start SDRAM self-refresh - // mode -#define EBUFE 0x02000000 // Enable external buffering - // timing -#define FBBRW 0x04000000 // Fast back-to-back read - // write enable -#define EMREN 0x10000000 // Extended mode register - // enable -#define TCSR 0x20000000 // Temp compensated self - // refresh value 85 deg C -#define CDDBG 0x40000000 // Tristate SDRAM controls - // during bus grant - -// EBIU_SDBCTL Masks -#define EB0_E 0x00000001 // Enable SDRAM - // external bank 0 -#define EB0_SZ_16 0x00000000 // SDRAM external - // bank size = 16MB -#define EB0_SZ_32 0x00000002 // SDRAM external - // bank size = 32MB -#define EB0_SZ_64 0x00000004 // SDRAM external - // bank size = 64MB -#define EB0_SZ_128 0x00000006 // SDRAM external - // bank size = 128MB -#define EB0_CAW_8 0x00000000 // SDRAM external bank column - // address width = 8 bits -#define EB0_CAW_9 0x00000010 // SDRAM external bank column - // address width = 9 bits -#define EB0_CAW_10 0x00000020 // SDRAM external bank column - // address width = 9 bits -#define EB0_CAW_11 0x00000030 // SDRAM external bank column - // address width = 9 bits - -#define EB1_E 0x00000100 // Enable SDRAM - // external bank 1 -#define EB1__SZ_16 0x00000000 // SDRAM external - // bank size = 16MB -#define EB1__SZ_32 0x00000200 // SDRAM external - // bank size = 32MB -#define EB1__SZ_64 0x00000400 // SDRAM external - // bank size = 64MB -#define EB1__SZ_128 0x00000600 // SDRAM external - // bank size = 128MB -#define EB1__CAW_8 0x00000000 // SDRAM external bank column - // address width = 8 bits -#define EB1__CAW_9 0x00001000 // SDRAM external bank column - // address width = 9 bits -#define EB1__CAW_10 0x00002000 // SDRAM external bank column - // address width = 9 bits -#define EB1__CAW_11 0x00003000 // SDRAM external bank column - // address width = 9 bits - -#define EB2__E 0x00010000 // Enable SDRAM - // external bank 2 -#define EB2__SZ_16 0x00000000 // SDRAM external - // bank size = 16MB -#define EB2__SZ_32 0x00020000 // SDRAM external - // bank size = 32MB -#define EB2__SZ_64 0x00040000 // SDRAM external - // bank size = 64MB -#define EB2__SZ_128 0x00060000 // SDRAM external - // bank size = 128MB -#define EB2__CAW_8 0x00000000 // SDRAM external bank column - // address width = 8 bits -#define EB2__CAW_9 0x00100000 // SDRAM external bank column - // address width = 9 bits -#define EB2__CAW_10 0x00200000 // SDRAM external bank column - // address width = 9 bits -#define EB2__CAW_11 0x00300000 // SDRAM external bank column - // address width = 9 bits - -#define EB3__E 0x01000000 // Enable SDRAM external bank 3 -#define EB3__SZ_16 0x00000000 // SDRAM external - // bank size = 16MB -#define EB3__SZ_32 0x02000000 // SDRAM external - // bank size = 32MB -#define EB3__SZ_64 0x04000000 // SDRAM external - // bank size = 64MB -#define EB3__SZ_128 0x06000000 // SDRAM external - // bank size = 128MB -#define EB3__CAW_8 0x00000000 // SDRAM external bank column - // address width = 8 bits -#define EB3__CAW_9 0x10000000 // SDRAM external bank column - // address width = 9 bits -#define EB3__CAW_10 0x20000000 // SDRAM external bank column - // address width = 9 bits -#define EB3__CAW_11 0x30000000 // SDRAM external bank column - // address width = 9 bits - -// EBIU_SDSTAT Masks -#define SDCI 0x00000001 // SDRAM controller is idle -#define SDSRA 0x00000002 // SDRAM SDRAM self refresh - // is active -#define SDPUA 0x00000004 // SDRAM power up active -#define SDRS 0x00000008 // SDRAM is in reset state -#define SDEASE 0x00000010 // SDRAM EAB sticky error - // status - W1C -#define BGSTAT 0x00000020 // Bus granted - - -#if 1 /* comment by mhfan */ -#define COREMMR_BASE 0xFFE00000 // Core MMRs -#define SYSMMR_BASE 0xFFC00000 // System MMRs - -// Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) -#define WDOG_CTL 0xFFC00200 // Watchdog Control register -#define WDOG_CNT 0xFFC00204 // Watchdog Count register -#define WDOG_STAT 0xFFC00208 // Watchdog Status register - -// Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) -#define FIO_FLAG_D 0xFFC00700 // Flag Data register -#define FIO_FLAG_C 0xFFC00704 // Flag Clear register -#define FIO_FLAG_S 0xFFC00708 // Flag Set register -#define FIO_FLAG_T 0xFFC0070C // Flag Toggle register -#define FIO_MASKA_D 0xFFC00710 // Flag Mask Interrupt A Data - // register -#define FIO_MASKA_C 0xFFC00714 // Flag Mask Interrupt A Clear - // register -#define FIO_MASKA_S 0xFFC00718 // Flag Mask Interrupt A Set - // register -#define FIO_MASKA_T 0xFFC0071C // Flag Mask Interrupt A Toggle - // register -#define FIO_MASKB_D 0xFFC00720 // Flag Mask Interrupt B Data - // register -#define FIO_MASKB_C 0xFFC00724 // Flag Mask Interrupt B Clear - // register -#define FIO_MASKB_S 0xFFC00728 // Flag Mask Interrupt B Set - // register -#define FIO_MASKB_T 0xFFC0072C // Flag Mask Interrupt B Toggle - // register -#define FIO_DIR 0xFFC00730 // Flag Direction register -#define FIO_POLAR 0xFFC00734 // Flag Polarity register -#define FIO_EDGE 0xFFC00738 // Flag Interrupt Sensitivity - // register -#define FIO_BOTH 0xFFC0073C // Flag Set on Both Edges - // register -#define FIO_INEN 0xFFC00740 // Flag Input Enable register - -// Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) -#define PPI_CONTROL 0xFFC01000 // PPI0 Control register -#define PPI_STATUS 0xFFC01004 // PPI0 Status register -#define PPI_COUNT 0xFFC01008 // PPI0 Transfer Count register -#define PPI_DELAY 0xFFC0100C // PPI0 Delay Count register -#define PPI_FRAME 0xFFC01010 // PPI0 Frame Length register - -// System Reset and Interrupt Controller registers for -// core A (0xFFC0 0100-0xFFC0 01FF) -#define SWRST 0xFFC00100 // Software Reset register -#define SYSCR 0xFFC00104 // System Reset Configuration - // register -#define RVECT 0xFFC00108 // SIC Reset Vector Address - // Register -#define SIC_SWRST 0xFFC00100 // Software Reset register -#define SIC_SYSCR 0xFFC00104 // System Reset Configuration - // register -#define SIC_RVECT 0xFFC00108 // SIC Reset Vector Address - // Register -#define SIC_IMASK 0xFFC0010C // SIC Interrupt Mask - // register 0 - hack to fix - // old tests -#define SIC_IAR 0xFFC00124 // SIC Interrupt Assignment - // Register 0 -#define SIC_IAR1 0xFFC00128 // SIC Interrupt Assignment - // Register 1 -#define SIC_IAR2 0xFFC0012C // SIC Interrupt Assignment - // Register 2 -#define SIC_ISR 0xFFC00114 // SIC Interrupt Status - // register 0 -#define SIC_IWR 0xFFC0011C // SIC Interrupt - // Wakeup-Enable register 0 - -// EBIU_SDBCTL Masks -#define EB_E 0x00000001 // Enable SDRAM - // external bank 0 -#define EB_SZ_16 0x00000000 // SDRAM external - // bank size = 16MB -#define EB_SZ_32 0x00000002 // SDRAM external - // bank size = 32MB -#define EB_SZ_64 0x00000004 // SDRAM external - // bank size = 64MB -#define EB_SZ_128 0x00000006 // SDRAM external - // bank size = 128MB -#define EB_CAW_8 0x00000000 // SDRAM external bank column - // address width = 8 bits -#define EB_CAW_9 0x00000010 // SDRAM external bank column - // address width = 9 bits -#define EB_CAW_10 0x00000020 // SDRAM external bank column - // address width = 9 bits -#define EB_CAW_11 0x00000030 // SDRAM external bank column - // address width = 9 bits - -// EBIU_SDBCTL Masks -#define EBE 0x00000001 // Enable SDRAM - // external bank 0 -#define EBSZ_16 0x00000000 // SDRAM external - // bank size = 16MB -#define EBSZ_32 0x00000002 // SDRAM external - // bank size = 32MB -#define EBSZ_64 0x00000004 // SDRAM external - // bank size = 64MB -#define EBSZ_128 0x00000006 // SDRAM external - // bank size = 128MB -#define EBCAW_8 0x00000000 // SDRAM external bank column - // address width = 8 bits -#define EBCAW_9 0x00000010 // SDRAM external bank column - // address width = 9 bits -#define EBCAW_10 0x00000020 // SDRAM external bank column - // address width = 9 bits -#define EBCAW_11 0x00000030 // SDRAM external bank column - // address width = 9 bits - -// Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) -#define MDMA_D0_CONFIG 0xFFC01F08 // MemDMA1 Stream 0 Destination - // Configuration -#define MDMA_D0_NEXT_DESC_PTR 0xFFC01F00 // MemDMA1 Stream 0 - // Destination Next - // Descriptor Ptr Reg -#define MDMA_D0_START_ADDR 0xFFC01F04 // MemDMA1 Stream 0 Destination - // Start Address -#define MDMA_D0_X_COUNT 0xFFC01F10 // MemDMA1 Stream 0 Destination - // Inner-Loop Count -#define MDMA_D0_Y_COUNT 0xFFC01F18 // MemDMA1 Stream 0 Destination - // Outer-Loop Count -#define MDMA_D0_X_MODIFY 0xFFC01F14 // MemDMA1 Stream 0 Dest - // Inner-Loop Address-Increment -#define MDMA_D0_Y_MODIFY 0xFFC01F1C // MemDMA1 Stream 0 Dest - // Outer-Loop Address-Increment -#define MDMA_D0_CURR_DESC_PTR 0xFFC01F20 // MemDMA1 Stream 0 Dest - // Current Descriptor Ptr reg -#define MDMA_D0_CURR_ADDR 0xFFC01F24 // MemDMA1 Stream 0 Destination - // Current Address -#define MDMA_D0_CURR_X_COUNT 0xFFC01F30 // MemDMA1 Stream 0 Dest - // Current Inner-Loop Count -#define MDMA_D0_CURR_Y_COUNT 0xFFC01F38 // MemDMA1 Stream 0 Dest - // Current Outer-Loop Count -#define MDMA_D0_IRQ_STATUS 0xFFC01F28 // MemDMA1 Stream 0 Destination - // Interrupt/Status -#define MDMA_D0_PERIPHERAL_MAP 0xFFC01F2C // MemDMA1 Stream 0 - // Destination Peripheral Map - -#define MDMA_S0_CONFIG 0xFFC01F48 // MemDMA1 Stream 0 Source - // Configuration -#define MDMA_S0_NEXT_DESC_PTR 0xFFC01F40 // MemDMA1 Stream 0 Source - // Next Descriptor Ptr Reg -#define MDMA_S0_START_ADDR 0xFFC01F44 // MemDMA1 Stream 0 Source - // Start Address -#define MDMA_S0_X_COUNT 0xFFC01F50 // MemDMA1 Stream 0 Source - // Inner-Loop Count -#define MDMA_S0_Y_COUNT 0xFFC01F58 // MemDMA1 Stream 0 Source - // Outer-Loop Count -#define MDMA_S0_X_MODIFY 0xFFC01F54 // MemDMA1 Stream 0 Source - // Inner-Loop Address-Increment -#define MDMA_S0_Y_MODIFY 0xFFC01F5C // MemDMA1 Stream 0 Source - // Outer-Loop Address-Increment -#define MDMA_S0_CURR_DESC_PTR 0xFFC01F60 // MemDMA1 Stream 0 Source - // Current Descriptor Ptr reg -#define MDMA_S0_CURR_ADDR 0xFFC01F64 // MemDMA1 Stream 0 Source - // Current Address -#define MDMA_S0_CURR_X_COUNT 0xFFC01F70 // MemDMA1 Stream 0 Source - // Current Inner-Loop Count -#define MDMA_S0_CURR_Y_COUNT ` 0xFFC01F78 // MemDMA1 Stream 0 Source - // Current Outer-Loop Count -#define MDMA_S0_IRQ_STATUS 0xFFC01F68 // MemDMA1 Stream 0 Source - // Interrupt/Status -#define MDMA_S0_PERIPHERAL_MAP 0xFFC01F6C // MemDMA1 Stream 0 Source - // Peripheral Map - -#define MDMA_D1_CONFIG 0xFFC01F88 // MemDMA1 Stream 1 Destination - // Configuration -#define MDMA_D1_NEXT_DESC_PTR 0xFFC01F80 // MemDMA1 Stream 1 - // Destination Next - // Descriptor Ptr Reg -#define MDMA_D1_START_ADDR 0xFFC01F84 // MemDMA1 Stream 1 Destination - // Start Address -#define MDMA_D1_X_COUNT 0xFFC01F90 // MemDMA1 Stream 1 Destination - // Inner-Loop Count -#define MDMA_D1_Y_COUNT 0xFFC01F98 // MemDMA1 Stream 1 Destination - // Outer-Loop Count -#define MDMA_D1_X_MODIFY 0xFFC01F94 // MemDMA1 Stream 1 Dest - // Inner-Loop Address-Increment -#define MDMA_D1_Y_MODIFY 0xFFC01F9C // MemDMA1 Stream 1 Dest - // Outer-Loop Address-Increment -#define MDMA_D1_CURR_DESC_PTR 0xFFC01FA0 // MemDMA1 Stream 1 Dest - // Current Descriptor Ptr reg -#define MDMA_D1_CURR_ADDR 0xFFC01FA4 // MemDMA1 Stream 1 Dest - // Current Address -#define MDMA_D1_CURR_X_COUNT 0xFFC01FB0 // MemDMA1 Stream 1 Dest - // Current Inner-Loop Count -#define MDMA_D1_CURR_Y_COUNT 0xFFC01FB8 // MemDMA1 Stream 1 Dest - // Current Outer-Loop Count -#define MDMA_D1_IRQ_STATUS 0xFFC01FA8 // MemDMA1 Stream 1 Dest - // Interrupt/Status -#define MDMA_D1_PERIPHERAL_MAP 0xFFC01FAC // MemDMA1 Stream 1 Dest - // Peripheral Map - -#define MDMA_S1_CONFIG 0xFFC01FC8 // MemDMA1 Stream 1 Source - // Configuration -#define MDMA_S1_NEXT_DESC_PTR 0xFFC01FC0 // MemDMA1 Stream 1 Source - // Next Descriptor Ptr Reg -#define MDMA_S1_START_ADDR 0xFFC01FC4 // MemDMA1 Stream 1 Source - // Start Address -#define MDMA_S1_X_COUNT 0xFFC01FD0 // MemDMA1 Stream 1 Source - // Inner-Loop Count -#define MDMA_S1_Y_COUNT 0xFFC01FD8 // MemDMA1 Stream 1 Source - // Outer-Loop Count -#define MDMA_S1_X_MODIFY 0xFFC01FD4 // MemDMA1 Stream 1 Source - // Inner-Loop Address-Increment -#define MDMA_S1_Y_MODIFY 0xFFC01FDC // MemDMA1 Stream 1 Source - // Outer-Loop Address-Increment -#define MDMA_S1_CURR_DESC_PTR 0xFFC01FE0 // MemDMA1 Stream 1 Source - // Current Descriptor Ptr reg -#define MDMA_S1_CURR_ADDR 0xFFC01FE4 // MemDMA1 Stream 1 Source - // Current Address -#define MDMA_S1_CURR_X_COUNT 0xFFC01FF0 // MemDMA1 Stream 1 Source - // Current Inner-Loop Count -#define MDMA_S1_CURR_Y_COUNT 0xFFC01FF8 // MemDMA1 Stream 1 Source - // Current Outer-Loop Count -#define MDMA_S1_IRQ_STATUS 0xFFC01FE8 // MemDMA1 Stream 1 Source - // Interrupt/Status -#define MDMA_S1_PERIPHERAL_MAP 0xFFC01FEC // MemDMA1 Stream 1 Source - // Peripheral Map - -#define DMA0_CONFIG 0xFFC01C08 // DMA1 Channel 0 Configuration - // register -#define DMA0_NEXT_DESC_PTR 0xFFC01C00 // DMA1 Channel 0 Next - // Descripter Ptr Reg -#define DMA0_START_ADDR 0xFFC01C04 // DMA1 Channel 0 Start Address -#define DMA0_X_COUNT 0xFFC01C10 // DMA1 Channel 0 Inner Loop - // Count -#define DMA0_Y_COUNT 0xFFC01C18 // DMA1 Channel 0 Outer Loop - // Count -#define DMA0_X_MODIFY 0xFFC01C14 // DMA1 Channel 0 Inner Loop - // Addr Increment -#define DMA0_Y_MODIFY 0xFFC01C1C // DMA1 Channel 0 Outer Loop - // Addr Increment -#define DMA0_CURR_DESC_PTR 0xFFC01C20 // DMA1 Channel 0 Current - // Descriptor Pointer -#define DMA0_CURR_ADDR 0xFFC01C24 // DMA1 Channel 0 Current - // Address Pointer -#define DMA0_CURR_X_COUNT 0xFFC01C30 // DMA1 Channel 0 Current Inner - // Loop Count -#define DMA0_CURR_Y_COUNT 0xFFC01C38 // DMA1 Channel 0 Current Outer - // Loop Count -#define DMA0_IRQ_STATUS 0xFFC01C28 // DMA1 Channel 0 Interrupt - // Status Register -#define DMA0_PERIPHERAL_MAP 0xFFC01C2C // DMA1 Channel 0 Peripheral - // Map Register - -#define DMA1_CONFIG 0xFFC00C08 // DMA2 Channel 0 Configuration - // register -#define DMA1_NEXT_DESC_PTR 0xFFC00C00 // DMA2 Channel 0 Next - // Descripter Ptr Reg -#define DMA1_START_ADDR 0xFFC00C04 // DMA2 Channel 0 Start Address -#define DMA1_X_COUNT 0xFFC00C10 // DMA2 Channel 0 Inner Loop - // Count -#define DMA1_Y_COUNT 0xFFC00C18 // DMA2 Channel 0 Outer Loop - // Count -#define DMA1_X_MODIFY 0xFFC00C14 // DMA2 Channel 0 Inner Loop - // Addr Increment -#define DMA1_Y_MODIFY 0xFFC00C1C // DMA2 Channel 0 Outer Loop - // Addr Increment -#define DMA1_CURR_DESC_PTR 0xFFC00C20 // DMA2 Channel 0 Current - // Descriptor Pointer -#define DMA1_CURR_ADDR 0xFFC00C24 // DMA2 Channel 0 Current - // Address Pointer -#define DMA1_CURR_X_COUNT 0xFFC00C30 // DMA2 Channel 0 Current Inner - // Loop Count -#define DMA1_CURR_Y_COUNT 0xFFC00C38 // DMA2 Channel 0 Current Outer - // Loop Count -#define DMA1_IRQ_STATUS 0xFFC00C28 // DMA2 Channel 0 Interrupt - // /Status Register -#define DMA1_PERIPHERAL_MAP 0xFFC00C2C // DMA2 Channel 0 Peripheral - // Map Register - -#define DMA2_CONFIG 0xFFC00C48 // DMA2 Channel 1 Configuration - // register -#define DMA2_NEXT_DESC_PTR 0xFFC00C40 // DMA2 Channel 1 Next - // Descripter Ptr Reg -#define DMA2_START_ADDR 0xFFC00C44 // DMA2 Channel 1 Start Address -#define DMA2_X_COUNT 0xFFC00C50 // DMA2 Channel 1 Inner Loop - // Count -#define DMA2_Y_COUNT 0xFFC00C58 // DMA2 Channel 1 Outer Loop - // Count -#define DMA2_X_MODIFY 0xFFC00C54 // DMA2 Channel 1 Inner Loop - // Addr Increment -#define DMA2_Y_MODIFY 0xFFC00C5C // DMA2 Channel 1 Outer Loop - // Addr Increment -#define DMA2_CURR_DESC_PTR 0xFFC00C60 // DMA2 Channel 1 Current - // Descriptor Pointer -#define DMA2_CURR_ADDR 0xFFC00C64 // DMA2 Channel 1 Current - // Address Pointer -#define DMA2_CURR_X_COUNT 0xFFC00C70 // DMA2 Channel 1 Current - // Inner Loop Count -#define DMA2_CURR_Y_COUNT 0xFFC00C78 // DMA2 Channel 1 Current - // Outer Loop Count -#define DMA2_IRQ_STATUS 0xFFC00C68 // DMA2 Channel 1 Interrupt - // /Status Register -#define DMA2_PERIPHERAL_MAP 0xFFC00C6C // DMA2 Channel 1 Peripheral - // Map Register - -#define DMA3_CONFIG 0xFFC00C88 // DMA2 Channel 2 Configuration - // register -#define DMA3_NEXT_DESC_PTR 0xFFC00C80 // DMA2 Channel 2 Next - // Descripter Ptr Reg -#define DMA3_START_ADDR 0xFFC00C84 // DMA2 Channel 2 Start Address -#define DMA3_X_COUNT 0xFFC00C90 // DMA2 Channel 2 Inner Loop - // Count -#define DMA3_Y_COUNT 0xFFC00C98 // DMA2 Channel 2 Outer Loop - // Count -#define DMA3_X_MODIFY 0xFFC00C94 // DMA2 Channel 2 Inner Loop - // Addr Increment -#define DMA3_Y_MODIFY 0xFFC00C9C // DMA2 Channel 2 Outer Loop - // Addr Increment -#define DMA3_CURR_DESC_PTR 0xFFC00CA0 // DMA2 Channel 2 Current - // Descriptor Pointer -#define DMA3_CURR_ADDR 0xFFC00CA4 // DMA2 Channel 2 Current - // Address Pointer -#define DMA3_CURR_X_COUNT 0xFFC00CB0 // DMA2 Channel 2 Current Inner - // Loop Count -#define DMA3_CURR_Y_COUNT 0xFFC00CB8 // DMA2 Channel 2 Current Outer - // Loop Count -#define DMA3_IRQ_STATUS 0xFFC00CA8 // DMA2 Channel 2 Interrupt - // /Status Register -#define DMA3_PERIPHERAL_MAP 0xFFC00CAC // DMA2 Channel 2 Peripheral - // Map Register - -#define DMA4_CONFIG 0xFFC00CC8 // DMA2 Channel 3 Configuration - // register -#define DMA4_NEXT_DESC_PTR 0xFFC00CC0 // DMA2 Channel 3 Next - // Descripter Ptr Reg -#define DMA4_START_ADDR 0xFFC00CC4 // DMA2 Channel 3 Start Address -#define DMA4_X_COUNT 0xFFC00CD0 // DMA2 Channel 3 Inner Loop - // Count -#define DMA4_Y_COUNT 0xFFC00CD8 // DMA2 Channel 3 Outer Loop - // Count -#define DMA4_X_MODIFY 0xFFC00CD4 // DMA2 Channel 3 Inner Loop - // Addr Increment -#define DMA4_Y_MODIFY 0xFFC00CDC // DMA2 Channel 3 Outer Loop - // Addr Increment -#define DMA4_CURR_DESC_PTR 0xFFC00CE0 // DMA2 Channel 3 Current - // Descriptor Pointer -#define DMA4_CURR_ADDR 0xFFC00CE4 // DMA2 Channel 3 Current - // Address Pointer -#define DMA4_CURR_X_COUNT 0xFFC00CF0 // DMA2 Channel 3 Current Inner - // Loop Count -#define DMA4_CURR_Y_COUNT 0xFFC00CF8 // DMA2 Channel 3 Current Outer - // Loop Count -#define DMA4_IRQ_STATUS 0xFFC00CE8 // DMA2 Channel 3 Interrupt - // /Status Register -#define DMA4_PERIPHERAL_MAP 0xFFC00CEC // DMA2 Channel 3 Peripheral - // Map Register - -#define DMA5_CONFIG 0xFFC00D08 // DMA2 Channel 4 Configuration - // register -#define DMA5_NEXT_DESC_PTR 0xFFC00D00 // DMA2 Channel 4 Next - // Descripter Ptr Reg -#define DMA5_START_ADDR 0xFFC00D04 // DMA2 Channel 4 Start Address -#define DMA5_X_COUNT 0xFFC00D10 // DMA2 Channel 4 Inner Loop - // Count -#define DMA5_Y_COUNT 0xFFC00D18 // DMA2 Channel 4 Outer Loop - // Count -#define DMA5_X_MODIFY 0xFFC00D14 // DMA2 Channel 4 Inner Loop - // Addr Increment -#define DMA5_Y_MODIFY 0xFFC00D1C // DMA2 Channel 4 Outer Loop - // Addr Increment -#define DMA5_CURR_DESC_PTR 0xFFC00D20 // DMA2 Channel 4 Current - // Descriptor Pointer -#define DMA5_CURR_ADDR 0xFFC00D24 // DMA2 Channel 4 Current - // Address Pointer -#define DMA5_CURR_X_COUNT 0xFFC00D30 // DMA2 Channel 4 Current Inner - // Loop Count -#define DMA5_CURR_Y_COUNT 0xFFC00D38 // DMA2 Channel 4 Current Outer - // Loop Count -#define DMA5_IRQ_STATUS 0xFFC00D28 // DMA2 Channel 4 Interrupt - // /Status Register -#define DMA5_PERIPHERAL_MAP 0xFFC00D2C // DMA2 Channel 4 Peripheral - // Map Register - -#define DMA6_CONFIG 0xFFC00D48 // DMA2 Channel 5 Configuration - // register -#define DMA6_NEXT_DESC_PTR 0xFFC00D40 // DMA2 Channel 5 Next - // Descripter Ptr Reg -#define DMA6_START_ADDR 0xFFC00D44 // DMA2 Channel 5 Start Address -#define DMA6_X_COUNT 0xFFC00D50 // DMA2 Channel 5 Inner Loop - // Count -#define DMA6_Y_COUNT 0xFFC00D58 // DMA2 Channel 5 Outer Loop - // Count -#define DMA6_X_MODIFY 0xFFC00D54 // DMA2 Channel 5 Inner Loop - // Addr Increment -#define DMA6_Y_MODIFY 0xFFC00D5C // DMA2 Channel 5 Outer Loop - // Addr Increment -#define DMA6_CURR_DESC_PTR 0xFFC00D60 // DMA2 Channel 5 Current - // Descriptor Pointer -#define DMA6_CURR_ADDR 0xFFC00D64 // DMA2 Channel 5 Current - // Address Pointer -#define DMA6_CURR_X_COUNT 0xFFC00D70 // DMA2 Channel 5 Current Inner - // Loop Count -#define DMA6_CURR_Y_COUNT 0xFFC00D78 // DMA2 Channel 5 Current Outer - // Loop Count -#define DMA6_IRQ_STATUS 0xFFC00D68 // DMA2 Channel 5 Interrupt - // /Status Register -#define DMA6_PERIPHERAL_MAP 0xFFC00D6C // DMA2 Channel 5 Peripheral - // Map Register - -#define DMA7_CONFIG 0xFFC00D88 // DMA2 Channel 6 Configuration - // register -#define DMA7_NEXT_DESC_PTR 0xFFC00D80 // DMA2 Channel 6 Next - // Descripter Ptr Reg -#define DMA7_START_ADDR 0xFFC00D84 // DMA2 Channel 6 Start Address -#define DMA7_X_COUNT 0xFFC00D90 // DMA2 Channel 6 Inner Loop - // Count -#define DMA7_Y_COUNT 0xFFC00D98 // DMA2 Channel 6 Outer Loop - // Count -#define DMA7_X_MODIFY 0xFFC00D94 // DMA2 Channel 6 Inner Loop - // Addr Increment -#define DMA7_Y_MODIFY 0xFFC00D9C // DMA2 Channel 6 Outer Loop - // Addr Increment -#define DMA7_CURR_DESC_PTR 0xFFC00DA0 // DMA2 Channel 6 Current - // Descriptor Pointer -#define DMA7_CURR_ADDR 0xFFC00DA4 // DMA2 Channel 6 Current - // Address Pointer -#define DMA7_CURR_X_COUNT 0xFFC00DB0 // DMA2 Channel 6 Current Inner - // Loop Count -#define DMA7_CURR_Y_COUNT 0xFFC00DB8 // DMA2 Channel 6 Current Outer - // Loop Count -#define DMA7_IRQ_STATUS 0xFFC00DA8 // DMA2 Channel 6 Interrupt - // /Status Register -#define DMA7_PERIPHERAL_MAP 0xFFC00DAC // DMA2 Channel 6 Peripheral - // Map Register - -#define TIMER_ENABLE 0xFFC00680 // Timer Enable Register -#define TIMER_DISABLE 0xFFC00684 // Timer Disable register -#define TIMER_STATUS 0xFFC00688 // Timer Status register - -// DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks -#define WDSIZE8 0x00000000 // Word Size 8 bits -#define WDSIZE16 0x00000004 // Word Size 16 bits -#define WDSIZE32 0x00000008 // Word Size 32 bits -#endif /* comment by mhfan */ - -#endif /* _DEF_BF561_H */ diff --git a/include/asm-blackfin/cpu/defBF561_extn.h b/include/asm-blackfin/cpu/defBF561_extn.h deleted file mode 100644 index 8112c3fe1e..0000000000 --- a/include/asm-blackfin/cpu/defBF561_extn.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * defBF533_extn.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -#ifndef _DEF_BF533_EXTN_H -#define _DEF_BF533_EXTN_H - -#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */ -/* Delay inserted for PLL transition */ -#define PLL_DELAY 0x1000 - -#define L1_ISRAM 0xFFA00000 -#define L1_ISRAM_END 0xFFA10000 -#define DATA_BANKA_SRAM 0xFF800000 -#define DATA_BANKA_SRAM_END 0xFF808000 -#define DATA_BANKB_SRAM 0xFF900000 -#define DATA_BANKB_SRAM_END 0xFF908000 -#define SYSMMR_BASE 0xFFC00000 -#define WDSIZE16 0x00000004 - -/* Event Vector Table Address */ -#define EVT_EMULATION_ADDR 0xffe02000 -#define EVT_RESET_ADDR 0xffe02004 -#define EVT_NMI_ADDR 0xffe02008 -#define EVT_EXCEPTION_ADDR 0xffe0200c -#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 -#define EVT_HARDWARE_ERROR_ADDR 0xffe02014 -#define EVT_TIMER_ADDR 0xffe02018 -#define EVT_IVG7_ADDR 0xffe0201c -#define EVT_IVG8_ADDR 0xffe02020 -#define EVT_IVG9_ADDR 0xffe02024 -#define EVT_IVG10_ADDR 0xffe02028 -#define EVT_IVG11_ADDR 0xffe0202c -#define EVT_IVG12_ADDR 0xffe02030 -#define EVT_IVG13_ADDR 0xffe02034 -#define EVT_IVG14_ADDR 0xffe02038 -#define EVT_IVG15_ADDR 0xffe0203c -#define EVT_OVERRIDE_ADDR 0xffe02100 - -/* IMASK Bit values */ -#define IVG15_POS 0x00008000 -#define IVG14_POS 0x00004000 -#define IVG13_POS 0x00002000 -#define IVG12_POS 0x00001000 -#define IVG11_POS 0x00000800 -#define IVG10_POS 0x00000400 -#define IVG9_POS 0x00000200 -#define IVG8_POS 0x00000100 -#define IVG7_POS 0x00000080 -#define IVGTMR_POS 0x00000040 -#define IVGHW_POS 0x00000020 - -#define WDOG_TMR_DISABLE (0xAD << 4) -#define ICTL_RST 0x00000000 -#define ICTL_NMI 0x00000002 -#define ICTL_GP 0x00000004 -#define ICTL_DISABLE 0x00000003 - -/* Watch Dog timer values setup */ -#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE - -#endif /* _DEF_BF533_EXTN_H */ diff --git a/include/asm-blackfin/cpu/def_LPBlackfin.h b/include/asm-blackfin/cpu/def_LPBlackfin.h deleted file mode 100644 index e183b0299e..0000000000 --- a/include/asm-blackfin/cpu/def_LPBlackfin.h +++ /dev/null @@ -1,445 +0,0 @@ -/* - * def_LPBlackfin.h - * - * This file is subject to the terms and conditions of the GNU Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Non-GPL License also available as part of VisualDSP++ - * - * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html - * - * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved - * - * This file under source code control, please send bugs or changes to: - * dsptools.support@analog.com - * - */ - -/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ - -#ifndef _DEF_LPBLACKFIN_H -#define _DEF_LPBLACKFIN_H - -/* - * #if !defined(__ADSPLPBLACKFIN__) - * #warning def_LPBlackfin.h should only be included for 532 compatible chips. - * #endif - */ - -#define MK_BMSK_( x ) (1<<x) /* Make a bit mask from a bit position */ - -/* - * System Register Bits - */ - -/* - * ASTAT register - */ - -/* definitions of ASTAT bit positions */ -#define ASTAT_AZ_P 0x00000000 /* Result of last ALU0 or shifter operation is zero */ -#define ASTAT_AN_P 0x00000001 /* Result of last ALU0 or shifter operation is negative */ -#define ASTAT_CC_P 0x00000005 /* Condition Code, used for holding comparison results */ -#define ASTAT_AQ_P 0x00000006 /* Quotient Bit */ -#define ASTAT_RND_MOD_P 0x00000008 /* Rounding mode, set for biased, clear for unbiased */ -#define ASTAT_AC0_P 0x0000000C /* Result of last ALU0 operation generated a carry */ -#define ASTAT_AC0_COPY_P 0x00000002 /* Result of last ALU0 operation generated a carry */ -#define ASTAT_AC1_P 0x0000000D /* Result of last ALU1 operation generated a carry */ -#define ASTAT_AV0_P 0x00000010 /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */ -#define ASTAT_AV0S_P 0x00000011 /* Sticky version of ASTAT_AV0 */ -#define ASTAT_AV1_P 0x00000012 /* Result of last MAC1 operation overflowed, sticky for MAC */ -#define ASTAT_AV1S_P 0x00000013 /* Sticky version of ASTAT_AV1 */ -#define ASTAT_V_P 0x00000018 /* Result of last ALU0 or MAC0 operation overflowed */ -#define ASTAT_V_COPY_P 0x00000003 /* Result of last ALU0 or MAC0 operation overflowed */ -#define ASTAT_VS_P 0x00000019 /* Sticky version of ASTAT_V */ - -/* ** Masks */ -#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) /* Result of last ALU0 or shifter operation is zero */ -#define ASTAT_AN MK_BMSK_(ASTAT_AN_P) /* Result of last ALU0 or shifter operation is negative */ -#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) /* Result of last ALU0 operation generated a carry */ -#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) /* Result of last ALU0 operation generated a carry */ -#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) /* Result of last ALU0 operation generated a carry */ -#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */ -#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) /* Result of last MAC1 operation overflowed, sticky for MAC */ -#define ASTAT_CC MK_BMSK_(ASTAT_CC_P) /* Condition Code, used for holding comparison results */ -#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) /* Quotient Bit */ -#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) /* Rounding mode, set for biased, clear for unbiased */ -#define ASTAT_V MK_BMSK_(ASTAT_V_P) /* Overflow Bit */ -#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) /* Overflow Bit */ - -/* - * SEQSTAT register - */ - -/* ** Bit Positions */ -#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */ -#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */ -#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */ -#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */ -#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */ -#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */ -#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, set by IDLE instruction */ -#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last reset was a software reset (=1) */ -#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */ -#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */ -#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */ -#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */ -#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */ -#define SEQSTAT_HWERRCAUSE5_P 0x00000013 /* Last hw error cause bit 5 */ -#define SEQSTAT_HWERRCAUSE6_P 0x00000014 /* Last hw error cause bit 6 */ -#define SEQSTAT_HWERRCAUSE7_P 0x00000015 /* Last hw error cause bit 7 */ - -/* ** Masks */ -/* Exception cause */ -#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \ - MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \ - MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \ - MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \ - MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \ - MK_BMSK_(SEQSTAT_EXCAUSE5_P ) | \ - 0) - -/* Indicates whether the last reset was a software reset (=1) */ -#define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P ) - -/* Last hw error cause */ -#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P ) | \ - MK_BMSK_(SEQSTAT_HWERRCAUSE1_P ) | \ - MK_BMSK_(SEQSTAT_HWERRCAUSE2_P ) | \ - MK_BMSK_(SEQSTAT_HWERRCAUSE3_P ) | \ - MK_BMSK_(SEQSTAT_HWERRCAUSE4_P ) | \ - 0) - -/* - * SYSCFG register - */ - -/* ** Bit Positions */ -#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when set it forces an exception for each instruction executed */ -#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */ -#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */ - -/* ** Masks */ -#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P) /* Supervisor single step, when set it forces an exception for each instruction executed */ -#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P) /* Enable cycle counter (=1) */ -#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P /* Self Nesting Interrupt Enable */ - -/* Backward-compatibility for typos in prior releases */ -#define SYSCFG_SSSSTEP SYSCFG_SSSTEP -#define SYSCFG_CCCEN SYSCFG_CCEN - -/* - * Core MMR Register Map - */ - -/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */ -#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ - -/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */ -#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */ -#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ - -/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */ - -/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ - -/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */ -#define DSPID 0xFFE05000 /* DSP Processor ID Register for MP implementations */ -#define DBGSTAT 0xFFE05008 /* Debug Status Register */ - -/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ - -/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */ -#define WPIACTL 0xFFE07000 /* Watchpoint Instruction Address Control Register */ -#define WPIA0 0xFFE07040 /* Watchpoint Instruction Address Register 0 */ -#define WPIA1 0xFFE07044 /* Watchpoint Instruction Address Register 1 */ -#define WPIA2 0xFFE07048 /* Watchpoint Instruction Address Register 2 */ -#define WPIA3 0xFFE0704C /* Watchpoint Instruction Address Register 3 */ -#define WPIA4 0xFFE07050 /* Watchpoint Instruction Address Register 4 */ -#define WPIA5 0xFFE07054 /* Watchpoint Instruction Address Register 5 */ -#define WPIACNT0 0xFFE07080 /* Watchpoint Instruction Address Count Register 0 */ -#define WPIACNT1 0xFFE07084 /* Watchpoint Instruction Address Count Register 1 */ -#define WPIACNT2 0xFFE07088 /* Watchpoint Instruction Address Count Register 2 */ -#define WPIACNT3 0xFFE0708C /* Watchpoint Instruction Address Count Register 3 */ -#define WPIACNT4 0xFFE07090 /* Watchpoint Instruction Address Count Register 4 */ -#define WPIACNT5 0xFFE07094 /* Watchpoint Instruction Address Count Register 5 */ -#define WPDACTL 0xFFE07100 /* Watchpoint Data Address Control Register */ -#define WPDA0 0xFFE07140 /* Watchpoint Data Address Register 0 */ -#define WPDA1 0xFFE07144 /* Watchpoint Data Address Register 1 */ -#define WPDACNT0 0xFFE07180 /* Watchpoint Data Address Count Value Register 0 */ -#define WPDACNT1 0xFFE07184 /* Watchpoint Data Address Count Value Register 1 */ -#define WPSTAT 0xFFE07200 /* Watchpoint Status Register */ - -/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */ -#define PFCTL 0xFFE08000 /* Performance Monitor Control Register */ -#define PFCNTR0 0xFFE08100 /* Performance Monitor Counter Register 0 */ -#define PFCNTR1 0xFFE08104 /* Performance Monitor Counter Register 1 */ - -/* - * Core MMR Register Bits - */ - -/* - * EVT registers (ILAT, IMASK, and IPEND). - */ - -/* ** Bit Positions */ -#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */ -#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */ -#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */ -#define EVT_EVX_P 0x00000003 /* Exception bit position */ -#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */ -#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */ -#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */ -#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */ -#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */ -#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */ -#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */ -#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */ -#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */ -#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */ -#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */ -#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */ - -/* ** Masks */ -#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */ -#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */ -#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */ -#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */ -#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */ -#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */ -#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */ -#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */ -#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */ -#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */ -#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */ -#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */ -#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */ -#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */ -#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */ -#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */ - -/* - * DMEM_CONTROL Register - */ - -/* ** Bit Positions */ -#define ENDM_P 0x00 /* (doesn't really exist) Enable Data Memory L1 */ -#define DMCTL_ENDM_P 0x00 /* "" (older define) */ -#define DMC0_P 0x01 /* Data Memory Configuration, 00 - A SRAM, B SRAM */ -#define DMCTL_DMC0_P 0x01 /* "" (older define) */ -#define DMC1_P 0x02 /* Data Memory Configuration, 10 - A SRAM, B SRAM */ -#define DMCTL_DMC1_P 0x02 /* "" (older define) */ -#define DMC2_P 0x03 /* Data Memory Configuration, 11 - A CACHE, B CACHE */ -#define DMCTL_DMC2_P 0x03 /* "" (older define) */ -#define DCBS_P 0x04 /* L1 Data Cache Bank Select */ -#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */ -#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */ - -/* ** Masks */ -#define ENDM 0x00000001 /* (doesn't really exist) Enable Data Memory L1 */ -#define ENDCPLB 0x00000002 /* Enable DCPLB */ -#define ASRAM_BSRAM 0x00000000 -#define ACACHE_BSRAM 0x00000008 -#define ACACHE_BCACHE 0x0000000C -#define DCBS 0x00000010 /* L1 Data Cache Bank Select */ -#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */ -#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */ - -/* IMEM_CONTROL Register */ -/* ** Bit Positions */ -#define ENIM_P 0x00 /* Enable L1 Code Memory */ -#define IMCTL_ENIM_P 0x00 /* "" (older define) */ -#define ENICPLB_P 0x01 /* Enable ICPLB */ -#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */ -#define IMC_P 0x02 /* Enable */ -#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as cache (0=SRAM) */ -#define ILOC0_P 0x03 /* Lock Way 0 */ -#define ILOC1_P 0x04 /* Lock Way 1 */ -#define ILOC2_P 0x05 /* Lock Way 2 */ -#define ILOC3_P 0x06 /* Lock Way 3 */ -#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement Priority */ - -/* ** Masks */ -#define ENIM 0x00000001 /* Enable L1 Code Memory */ -#define ENICPLB 0x00000002 /* Enable ICPLB */ -#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */ -#define ILOC0 0x00000008 /* Lock Way 0 */ -#define ILOC1 0x00000010 /* Lock Way 1 */ -#define ILOC2 0x00000020 /* Lock Way 2 */ -#define ILOC3 0x00000040 /* Lock Way 3 */ -#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement Priority */ - -/* TCNTL Masks */ -#define TMPWR 0x00000001 /* Timer Low Power Control, 0=low power mode, 1=active state */ -#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */ -#define TAUTORLD 0x00000004 /* Timer auto reload */ -#define TINT 0x00000008 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */ - -/* TCNTL Bit Positions */ -#define TMPWR_P 0x00000000 /* Timer Low Power Control, 0=low power mode, 1=active state */ -#define TMREN_P 0x00000001 /* Timer enable, 0=disable, 1=enable */ -#define TAUTORLD_P 0x00000002 /* Timer auto reload */ -#define TINT_P 0x00000003 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */ - -/* DCPLB_DATA and ICPLB_DATA Registers */ -/* ** Bit Positions */ -#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ -#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */ -#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */ - -/* ** Masks */ -#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ -#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */ -#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */ -#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ -#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ -#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ -#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ -#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */ -#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ -#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */ - -/* ICPLB_DATA only */ -#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */ - -/* DCPLB_DATA only */ -#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */ -#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */ -#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ -#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes */ - /* 1= allocate cache lines on write-through writes. */ -#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ - -/* ITEST_COMMAND and DTEST_COMMAND Registers */ -/* ** Masks */ -#define TEST_READ 0x00000000 /* Read Access */ -#define TEST_WRITE 0x00000002 /* Write Access */ -#define TEST_TAG 0x00000000 /* Access TAG */ -#define TEST_DATA 0x00000004 /* Access DATA */ -#define TEST_DW0 0x00000000 /* Select Double Word 0 */ -#define TEST_DW1 0x00000008 /* Select Double Word 1 */ -#define TEST_DW2 0x00000010 /* Select Double Word 2 */ -#define TEST_DW3 0x00000018 /* Select Double Word 3 */ -#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */ -#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */ -#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */ -#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */ -#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */ -#define TEST_WAY0 0x00000000 /* Access Way0 */ -#define TEST_WAY1 0x04000000 /* Access Way1 */ - -/* ** ITEST_COMMAND only */ -#define TEST_WAY2 0x08000000 /* Access Way2 */ -#define TEST_WAY3 0x0C000000 /* Access Way3 */ - -/* ** DTEST_COMMAND only */ -#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */ -#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */ - -#endif /* _DEF_LPBLACKFIN_H */ diff --git a/include/asm-blackfin/current.h b/include/asm-blackfin/current.h deleted file mode 100644 index 108c2792a0..0000000000 --- a/include/asm-blackfin/current.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * U-boot - current.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_CURRENT_H -#define _BLACKFIN_CURRENT_H -/* - * current.h - * (C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com> - * - * rather than dedicate a register (as the m68k source does), we - * just keep a global, we should probably just change it all to be - * current and lose _current_task. - */ - -extern struct task_struct *_current_task; -#define get_current() _current_task -#define current _current_task - -#endif diff --git a/include/asm-blackfin/elf.h b/include/asm-blackfin/elf.h deleted file mode 100644 index 1238a826b0..0000000000 --- a/include/asm-blackfin/elf.h +++ /dev/null @@ -1,127 +0,0 @@ -/* Changes made by LG Soft Oct 2004*/ - -#ifndef __ASMBFIN_ELF_H -#define __ASMBFIN_ELF_H - -/* - * ELF register definitions.. - */ - -//#include <asm/ptrace.h> -//#include <asm/user.h> - -/* Processor specific flags for the ELF header e_flags field. */ -#define EF_BFIN_PIC 0x00000001 /* -fpic */ -#define EF_BFIN_FDPIC 0x00000002 /* -mfdpic */ -#define EF_BFIN_CODE_IN_L1 0x00000010 /* --code-in-l1 */ -#define EF_BFIN_DATA_IN_L1 0x00000020 /* --data-in-l1 */ - -typedef unsigned long elf_greg_t; - -//#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) -//typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -typedef struct user_bfinfp_struct elf_fpregset_t; -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) ((x)->e_machine == EM_BLACKFIN) - -#define elf_check_fdpic(x) ((x)->e_flags & EF_BFIN_FDPIC /* && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS) */) -#define elf_check_const_displacement(x) ((x)->e_flags & EF_BFIN_PIC) - -/* EM_BLACKFIN defined in linux/elf.h */ - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 -#define ELF_DATA ELFDATA2LSB -#define ELF_ARCH EM_BLACKFIN - -#define ELF_PLAT_INIT(_r) _r->p1 = 0 - -#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr) \ -do { \ - _regs->r7 = 0; \ - _regs->p0 = _exec_map_addr; \ - _regs->p1 = _interp_map_addr; \ - _regs->p2 = _dynamic_addr; \ -} while(0) - -#define USE_ELF_CORE_DUMP -#define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC -#define ELF_EXEC_PAGESIZE 4096 - -#define R_unused0 0 /* relocation type 0 is not defined */ -#define R_pcrel5m2 1 /*LSETUP part a */ -#define R_unused1 2 /* relocation type 2 is not defined */ -#define R_pcrel10 3 /* type 3, if cc jump <target> */ -#define R_pcrel12_jump 4 /* type 4, jump <target> */ -#define R_rimm16 5 /* type 0x5, rN = <target> */ -#define R_luimm16 6 /* # 0x6, preg.l=<target> Load imm 16 to lower half */ -#define R_huimm16 7 /* # 0x7, preg.h=<target> Load imm 16 to upper half */ -#define R_pcrel12_jump_s 8 /* # 0x8 jump.s <target> */ -#define R_pcrel24_jump_x 9 /* # 0x9 jump.x <target> */ -#define R_pcrel24 10 /* # 0xa call <target> , not expandable */ -#define R_unusedb 11 /* # 0xb not generated */ -#define R_unusedc 12 /* # 0xc not used */ -#define R_pcrel24_jump_l 13 /*0xd jump.l <target> */ -#define R_pcrel24_call_x 14 /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */ -#define R_var_eq_symb 15 /* 0xf, linker should treat it same as 0x12 */ -#define R_byte_data 16 /* 0x10, .byte var = symbol */ -#define R_byte2_data 17 /* 0x11, .byte2 var = symbol */ -#define R_byte4_data 18 /* 0x12, .byte4 var = symbol and .var var=symbol */ -#define R_pcrel11 19 /* 0x13, lsetup part b */ -#define R_unused14 20 /* 0x14, undefined */ -#define R_unused15 21 /* not generated by VDSP 3.5 */ - -/* arithmetic relocations */ -#define R_push 0xE0 -#define R_const 0xE1 -#define R_add 0xE2 -#define R_sub 0xE3 -#define R_mult 0xE4 -#define R_div 0xE5 -#define R_mod 0xE6 -#define R_lshift 0xE7 -#define R_rshift 0xE8 -#define R_and 0xE9 -#define R_or 0xEA -#define R_xor 0xEB -#define R_land 0xEC -#define R_lor 0xED -#define R_len 0xEE -#define R_neg 0xEF -#define R_comp 0xF0 -#define R_page 0xF1 -#define R_hwpage 0xF2 -#define R_addr 0xF3 - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#define ELF_ET_DYN_BASE 0xD0000000UL - -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ - memcpy((char *) &pr_reg, (char *)regs, \ - sizeof(struct pt_regs)); - -/* This yields a mask that user programs can use to figure out what - instruction set this cpu supports. */ - -#define ELF_HWCAP (0) - -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. */ - -#define ELF_PLATFORM (NULL) - -#ifdef __KERNEL__ -#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX) -#endif - -#endif diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h deleted file mode 100644 index f031c86d76..0000000000 --- a/include/asm-blackfin/entry.h +++ /dev/null @@ -1,384 +0,0 @@ -/* - * U-boot - entry.h Routines for context saving and restoring - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __BLACKFIN_ENTRY_H -#define __BLACKFIN_ENTRY_H - -#include <asm/setup.h> -#include <asm/page.h> - -/* - * Stack layout in 'ret_from_exception': - * - */ - -/* - * Register %p2 is now set to the current task throughout - * the whole kernel. - */ - -#ifdef __ASSEMBLY__ - -#define LFLUSH_I_AND_D 0x00000808 -#define LSIGTRAP 5 - -/* process bits for task_struct.flags */ -#define PF_TRACESYS_OFF 3 -#define PF_TRACESYS_BIT 5 -#define PF_PTRACED_OFF 3 -#define PF_PTRACED_BIT 4 -#define PF_DTRACE_OFF 1 -#define PF_DTRACE_BIT 5 - -#define NEW_PT_REGS - -#if defined(NEW_PT_REGS) - -#define SAVE_ALL_INT save_context_no_interrupts -#define SAVE_ALL_SYS save_context_no_interrupts -#define SAVE_CONTEXT save_context_with_interrupts - -#define RESTORE_ALL restore_context_no_interrupts -#define RESTORE_ALL_SYS restore_context_no_interrupts -#define RESTORE_CONTEXT restore_context_with_interrupts - -#else - -#define SAVE_ALL_INT save_all_int -#define SAVE_ALL_SYS save_all_sys -#define SAVE_CONTEXT save_context -#define RESTORE_ALL restore_context -#define RESTORE_CONTEXT restore_context - -#endif - -/* - * Code to save processor context. - * We even save the register which are preserved by a function call - * - r4, r5, r6, r7, p3, p4, p5 - */ -.macro save_context_with_interrupts - [--sp] = R0; - [--sp] = ( R7:0, P5:0 ); - [--sp] = fp; - [--sp] = usp; - - [--sp] = i0; - [--sp] = i1; - [--sp] = i2; - [--sp] = i3; - - [--sp] = m0; - [--sp] = m1; - [--sp] = m2; - [--sp] = m3; - - [--sp] = l0; - [--sp] = l1; - [--sp] = l2; - [--sp] = l3; - - [--sp] = b0; - [--sp] = b1; - [--sp] = b2; - [--sp] = b3; - [--sp] = a0.x; - [--sp] = a0.w; - [--sp] = a1.x; - [--sp] = a1.w; - - [--sp] = LC0; - [--sp] = LC1; - [--sp] = LT0; - [--sp] = LT1; - [--sp] = LB0; - [--sp] = LB1; - - [--sp] = ASTAT; - - [--sp] = r0; /* Skip reserved */ - [--sp] = RETS; - [--sp] = RETI; - [--sp] = RETX; - [--sp] = RETN; - [--sp] = RETE; - [--sp] = SEQSTAT; - [--sp] = SYSCFG; - [--sp] = r0; /* Skip IPEND as well. */ -.endm - -.macro save_context_no_interrupts - [--sp] = R0; - [--sp] = ( R7:0, P5:0 ); - [--sp] = fp; - [--sp] = usp; - - [--sp] = i0; - [--sp] = i1; - [--sp] = i2; - [--sp] = i3; - - [--sp] = m0; - [--sp] = m1; - [--sp] = m2; - [--sp] = m3; - - [--sp] = l0; - [--sp] = l1; - [--sp] = l2; - [--sp] = l3; - - [--sp] = b0; - [--sp] = b1; - [--sp] = b2; - [--sp] = b3; - [--sp] = a0.x; - [--sp] = a0.w; - [--sp] = a1.x; - [--sp] = a1.w; - - [--sp] = LC0; - [--sp] = LC1; - [--sp] = LT0; - [--sp] = LT1; - [--sp] = LB0; - [--sp] = LB1; - - [--sp] = ASTAT; - - [--sp] = r0; /* Skip reserved */ - [--sp] = RETS; - r0 = RETI; - [--sp] = r0; - [--sp] = RETX; - [--sp] = RETN; - [--sp] = RETE; - [--sp] = SEQSTAT; - [--sp] = SYSCFG; - [--sp] = r0; /* Skip IPEND as well. */ -.endm - -.macro restore_context_no_interrupts - sp += 4; - SYSCFG = [sp++]; - SEQSTAT = [sp++]; - RETE = [sp++]; - RETN = [sp++]; - RETX = [sp++]; - r0 = [sp++]; - RETI = r0; - RETS = [sp++]; - - sp += 4; - - ASTAT = [sp++]; - - LB1 = [sp++]; - LB0 = [sp++]; - LT1 = [sp++]; - LT0 = [sp++]; - LC1 = [sp++]; - LC0 = [sp++]; - - a1.w = [sp++]; - a1.x = [sp++]; - a0.w = [sp++]; - a0.x = [sp++]; - b3 = [sp++]; - b2 = [sp++]; - b1 = [sp++]; - b0 = [sp++]; - - l3 = [sp++]; - l2 = [sp++]; - l1 = [sp++]; - l0 = [sp++]; - - m3 = [sp++]; - m2 = [sp++]; - m1 = [sp++]; - m0 = [sp++]; - - i3 = [sp++]; - i2 = [sp++]; - i1 = [sp++]; - i0 = [sp++]; - - sp += 4; - fp = [sp++]; - - ( R7 : 0, P5 : 0) = [ SP ++ ]; - sp += 4; -.endm - -.macro restore_context_with_interrupts - sp += 4; - SYSCFG = [sp++]; - SEQSTAT = [sp++]; - RETE = [sp++]; - RETN = [sp++]; - RETX = [sp++]; - RETI = [sp++]; - RETS = [sp++]; - - sp += 4; - - ASTAT = [sp++]; - - LB1 = [sp++]; - LB0 = [sp++]; - LT1 = [sp++]; - LT0 = [sp++]; - LC1 = [sp++]; - LC0 = [sp++]; - - a1.w = [sp++]; - a1.x = [sp++]; - a0.w = [sp++]; - a0.x = [sp++]; - b3 = [sp++]; - b2 = [sp++]; - b1 = [sp++]; - b0 = [sp++]; - - l3 = [sp++]; - l2 = [sp++]; - l1 = [sp++]; - l0 = [sp++]; - - m3 = [sp++]; - m2 = [sp++]; - m1 = [sp++]; - m0 = [sp++]; - - i3 = [sp++]; - i2 = [sp++]; - i1 = [sp++]; - i0 = [sp++]; - - sp += 4; - fp = [sp++]; - - ( R7 : 0, P5 : 0) = [ SP ++ ]; - sp += 4; -.endm - -#if !defined(NEW_PT_REGS) -/* - * a -1 in the orig_r0 field signifies - * that the stack frame is NOT for syscall - */ -.macro save_all_int -/* reserved and disable the single step of SYSCFG, by Steven Chen 03/07/10 */ - [--sp] = r0; - r0.l = 0x30; /* Errata for BF533 */ - r0.h = 0x0; - syscfg = r0; /* disable single step flag in SYSCFG */ - r0 = [sp++]; - [--sp] = syscfg; /* store SYSCFG */ - - [--sp] = r0; /* Reserved for IPEND */ - [--sp] = fp; - [--sp] = usp; - [--sp] = r0; - - [--sp] = r0; - r0 = [sp + 8]; - [--sp] = a0.x; - [--sp] = a1.x; - [--sp] = a0.w; - [--sp] = a1.w; - [--sp] = rets; - [--sp] = astat; - [--sp] = seqstat; - [--sp] = retx; /* current pc when exception happens */ - [--sp] = ( r7:5, p5:0 ); - [--sp] = r1; - [--sp] = r2; - [--sp] = r4; - [--sp] = r3; -.endm - -.macro save_all_sys - [--sp] = r0; - [--sp] = r0; - [--sp] = a0.x; - [--sp] = a1.x; - [--sp] = a0.w; - [--sp] = a1.w; - [--sp] = rets; - [--sp] = astat; - [--sp] = seqstat; - [--sp] = retx; /* current pc when exception happens */ - [--sp] = ( r7:5, p5:0 ); - [--sp] = r1; - [--sp] = r2; - [--sp] = r4; - [--sp] = r3; -.endm - -.macro restore_all - r3 = [sp++]; - r4 = [sp++]; - r2 = [sp++]; - r1 = [sp++]; - ( r7:5, p5:0 ) = [sp++]; - retx = [sp++]; - seqstat = [sp++]; - astat = [sp++]; - rets = [sp++]; - a1.w = [sp++]; - a0.w = [sp++]; - a1.x = [sp++]; - a0.x = [sp++]; - sp += 4; /* orig r0 */ - r0 = [sp++]; - - sp += 4; - fp = [sp++]; - sp +=4; /* Skip the IPEND */ - - syscfg = [sp++]; - -.endm - -#endif - -#define STR(X) STR1(X) -#define STR1(X) #X - -#if defined(NEW_PT_REGS) - -#define PT_OFF_ORIG_R0 208 -#define PT_OFF_SR 8 - -#else - -#define PT_OFF_ORIG_R0 0x54 -#define PT_OFF_SR 0x38 /* seqstat in pt_regs */ - -#endif -#endif - -#endif diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h deleted file mode 100644 index 690b6f3030..0000000000 --- a/include/asm-blackfin/hw_irq.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * U-boot - hw_irq.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * This file is based on - * linux/arch/$(ARCH)/platform/$(PLATFORM)/hw_irq.h - * BlackFin (ADI) assembler restricted values by Ted Ma <mated@sympatico.ca> - * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) - * Copyright (c) 2002 Lineo, Inc <mattw@lineo.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifdef CONFIG_EZKIT533 -#include <asm/board/bf533_irq.h> -#endif -#ifdef CONFIG_STAMP -#include <asm/board/bf533_irq.h> -#endif diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h deleted file mode 100644 index 0a8551218a..0000000000 --- a/include/asm-blackfin/io.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * U-boot - io.h IO routines - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_IO_H -#define _BLACKFIN_IO_H - -/* function prototypes for CF support */ -extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words); -extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words); -extern unsigned char cf_inb(volatile unsigned char *addr); -extern void cf_outb(unsigned char val, volatile unsigned char* addr); - -/* - * These are for ISA/PCI shared memory _only_ and should never be used - * on any other type of memory, including Zorro memory. They are meant to - * access the bus in the bus byte order which is little-endian!. - * - * readX/writeX() are used to access memory mapped devices. On some - * architectures the memory mapped IO stuff needs to be accessed - * differently. On the m68k architecture, we just read/write the - * memory location directly. - */ - - -#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; }) -#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; }) -#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; }) - -#define writeb(b,addr) {((*(volatile unsigned char *) (addr)) = (b)); asm("ssync;");} -#define writew(b,addr) {((*(volatile unsigned short *) (addr)) = (b)); asm("ssync;");} -#define writel(b,addr) {((*(volatile unsigned int *) (addr)) = (b)); asm("ssync;");} - -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) - -#define inb_p(addr) readb((addr) + BF533_PCIIO_BASE) -#define inb(addr) cf_inb((volatile unsigned char*)(addr)) - -#define outb(x,addr) cf_outb((unsigned char)(x), (volatile unsigned char*)(addr)) -#define outb_p(x,addr) outb(x, (addr) + BF533_PCIIO_BASE) - -#define inw(addr) readw((addr) + BF533_PCIIO_BASE) -#define inl(addr) readl((addr) + BF533_PCIIO_BASE) - -#define outw(x,addr) writew(x, (addr) + BF533_PCIIO_BASE) -#define outl(x,addr) writel(x, (addr) + BF533_PCIIO_BASE) - -#define insb(port, addr, count) memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), count) -#define insw(port, addr, count) cf_insw((unsigned short*)addr, (unsigned short*)(port), (count)) -#define insl(port, addr, count) memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), (4*count)) - -#define outsb(port,addr,count) memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, count) -#define outsw(port,addr,count) cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count)) -#define outsl(port,addr,count) memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, (4*count)) - -#define IO_SPACE_LIMIT 0xffff - -/* Values for nocacheflag and cmode */ -#define IOMAP_FULL_CACHING 0 -#define IOMAP_NOCACHE_SER 1 -#define IOMAP_NOCACHE_NONSER 2 -#define IOMAP_WRITETHROUGH 3 - -extern void *__ioremap(unsigned long physaddr, unsigned long size, - int cacheflag); -extern void __iounmap(void *addr, unsigned long size); - -extern inline void *ioremap(unsigned long physaddr, unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); -} -extern inline void *ioremap_nocache(unsigned long physaddr, - unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); -} -extern inline void *ioremap_writethrough(unsigned long physaddr, - unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); -} -extern inline void *ioremap_fullcache(unsigned long physaddr, - unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_FULL_CACHING); -} - -extern void iounmap(void *addr); - -extern void blkfin_inv_cache_all(void); -#define dma_cache_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) -#define dma_cache_wback(_start,_size) do { } while (0) -#define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) - -#endif diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h deleted file mode 100644 index 27da595425..0000000000 --- a/include/asm-blackfin/irq.h +++ /dev/null @@ -1,8 +0,0 @@ - -#define IRQ_EMU 0 /* Emulation */ -#define IRQ_RST 1 /* reset */ -#define IRQ_NMI 2 /* Non Maskable */ -#define IRQ_EVX 3 /* Exception */ -#define IRQ_UNUSED 4 /* - unused interrupt */ -#define IRQ_HWERR 5 /* Hardware Error */ -#define IRQ_CORETMR 6 /* Core timer */ diff --git a/include/asm-blackfin/linkage.h b/include/asm-blackfin/linkage.h deleted file mode 100644 index 7a3166037c..0000000000 --- a/include/asm-blackfin/linkage.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * U-boot - linkage.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _LINUX_LINKAGE_H -#define _LINUX_LINKAGE_H - -#ifdef __cplusplus -#define CPP_ASMLINKAGE extern "C" -#else -#define CPP_ASMLINKAGE -#endif - -#define asmlinkage CPP_ASMLINKAGE - -#define SYMBOL_NAME_STR(X) #X -#define SYMBOL_NAME(X) X -#ifdef __STDC__ -#define SYMBOL_NAME_LABEL(X) X##: -#else -#define SYMBOL_NAME_LABEL(X) X: -#endif - -#define __ALIGN .align 4 -#define __ALIGN_STR ".align 4" - -#ifdef __ASSEMBLY__ - -#define ALIGN __ALIGN -#define ALIGN_STR __ALIGN_STR - -#define ENTRY(name) \ - .globl SYMBOL_NAME(name); \ - ALIGN; \ - SYMBOL_NAME_LABEL(name) -#endif - -#endif diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h deleted file mode 100644 index 1a13d908e0..0000000000 --- a/include/asm-blackfin/mem_init.h +++ /dev/null @@ -1,287 +0,0 @@ -/* - * U-boot - mem_init.h Header file for memory initialization - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#if ( CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E ) - #if ( CONFIG_SCLK_HZ > 119402985 ) - #define SDRAM_tRP TRP_2 - #define SDRAM_tRP_num 2 - #define SDRAM_tRAS TRAS_7 - #define SDRAM_tRAS_num 7 - #define SDRAM_tRCD TRCD_2 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 ) - #define SDRAM_tRP TRP_2 - #define SDRAM_tRP_num 2 - #define SDRAM_tRAS TRAS_6 - #define SDRAM_tRAS_num 6 - #define SDRAM_tRCD TRCD_2 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ > 89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 ) - #define SDRAM_tRP TRP_2 - #define SDRAM_tRP_num 2 - #define SDRAM_tRAS TRAS_5 - #define SDRAM_tRAS_num 5 - #define SDRAM_tRCD TRCD_2 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ > 74626866 ) && ( CONFIG_SCLK_HZ <= 89552239 ) - #define SDRAM_tRP TRP_2 - #define SDRAM_tRP_num 2 - #define SDRAM_tRAS TRAS_4 - #define SDRAM_tRAS_num 4 - #define SDRAM_tRCD TRCD_2 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ > 66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 ) - #define SDRAM_tRP TRP_2 - #define SDRAM_tRP_num 2 - #define SDRAM_tRAS TRAS_3 - #define SDRAM_tRAS_num 3 - #define SDRAM_tRCD TRCD_2 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 ) - #define SDRAM_tRP TRP_1 - #define SDRAM_tRP_num 1 - #define SDRAM_tRAS TRAS_4 - #define SDRAM_tRAS_num 3 - #define SDRAM_tRCD TRCD_1 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ > 44776119 ) && ( CONFIG_SCLK_HZ <= 59701493 ) - #define SDRAM_tRP TRP_1 - #define SDRAM_tRP_num 1 - #define SDRAM_tRAS TRAS_3 - #define SDRAM_tRAS_num 3 - #define SDRAM_tRCD TRCD_1 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ > 29850746 ) && ( CONFIG_SCLK_HZ <= 44776119 ) - #define SDRAM_tRP TRP_1 - #define SDRAM_tRP_num 1 - #define SDRAM_tRAS TRAS_2 - #define SDRAM_tRAS_num 2 - #define SDRAM_tRCD TRCD_1 - #define SDRAM_tWR TWR_2 - #endif - #if ( CONFIG_SCLK_HZ <= 29850746 ) - #define SDRAM_tRP TRP_1 - #define SDRAM_tRP_num 1 - #define SDRAM_tRAS TRAS_1 - #define SDRAM_tRAS_num 1 - #define SDRAM_tRCD TRCD_1 - #define SDRAM_tWR TWR_2 - #endif -#endif - -#if (CONFIG_MEM_MT48LC16M16A2TG_75) - /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ - #define SDRAM_CL CL_3 -#endif - -#if (CONFIG_MEM_MT48LC64M4A2FB_7E) - /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ - #define SDRAM_CL CL_2 -#endif - -#if ( CONFIG_MEM_SIZE == 128 ) - #define SDRAM_SIZE EBSZ_128 -#endif -#if ( CONFIG_MEM_SIZE == 64 ) - #define SDRAM_SIZE EBSZ_64 -#endif -#if ( CONFIG_MEM_SIZE == 32 ) - #define SDRAM_SIZE EBSZ_32 -#endif -#if ( CONFIG_MEM_SIZE == 16 ) - #define SDRAM_SIZE EBSZ_16 -#endif -#if ( CONFIG_MEM_ADD_WDTH == 11 ) - #define SDRAM_WIDTH EBCAW_11 -#endif -#if ( CONFIG_MEM_ADD_WDTH == 10 ) - #define SDRAM_WIDTH EBCAW_10 -#endif -#if ( CONFIG_MEM_ADD_WDTH == 9 ) - #define SDRAM_WIDTH EBCAW_9 -#endif -#if ( CONFIG_MEM_ADD_WDTH == 8 ) - #define SDRAM_WIDTH EBCAW_8 -#endif - -#define mem_SDBCTL SDRAM_WIDTH | SDRAM_SIZE | EBE - -/* Equation from section 17 (p17-46) of BF533 HRM */ -#define mem_SDRRC ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) - -/* Enable SCLK Out */ -#define mem_SDGCTL ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS ) - -#define flash_EBIU_AMBCTL_WAT ( ( CONFIG_FLASH_SPEED_BWAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 -#define flash_EBIU_AMBCTL_RAT ( ( CONFIG_FLASH_SPEED_BRAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 -#define flash_EBIU_AMBCTL_HT ( ( CONFIG_FLASH_SPEED_BHT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) -#define flash_EBIU_AMBCTL_ST ( ( CONFIG_FLASH_SPEED_BST * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 -#define flash_EBIU_AMBCTL_TT ( ( CONFIG_FLASH_SPEED_BTT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 - -#if (flash_EBIU_AMBCTL_TT > 3 ) - #define flash_EBIU_AMBCTL0_TT B0TT_4 -#endif -#if (flash_EBIU_AMBCTL_TT == 3 ) - #define flash_EBIU_AMBCTL0_TT B0TT_3 -#endif -#if (flash_EBIU_AMBCTL_TT == 2 ) - #define flash_EBIU_AMBCTL0_TT B0TT_2 -#endif -#if (flash_EBIU_AMBCTL_TT < 2 ) - #define flash_EBIU_AMBCTL0_TT B0TT_1 -#endif - -#if (flash_EBIU_AMBCTL_ST > 3 ) - #define flash_EBIU_AMBCTL0_ST B0ST_4 -#endif -#if (flash_EBIU_AMBCTL_ST == 3 ) - #define flash_EBIU_AMBCTL0_ST B0ST_3 -#endif -#if (flash_EBIU_AMBCTL_ST == 2 ) - #define flash_EBIU_AMBCTL0_ST B0ST_2 -#endif -#if (flash_EBIU_AMBCTL_ST < 2 ) - #define flash_EBIU_AMBCTL0_ST B0ST_1 -#endif - -#if (flash_EBIU_AMBCTL_HT > 2 ) - #define flash_EBIU_AMBCTL0_HT B0HT_3 -#endif -#if (flash_EBIU_AMBCTL_HT == 2 ) - #define flash_EBIU_AMBCTL0_HT B0HT_2 -#endif -#if (flash_EBIU_AMBCTL_HT == 1 ) - #define flash_EBIU_AMBCTL0_HT B0HT_1 -#endif -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) - #define flash_EBIU_AMBCTL0_HT B0HT_0 -#endif -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) - #define flash_EBIU_AMBCTL0_HT B0HT_1 -#endif - -#if (flash_EBIU_AMBCTL_WAT > 14) - #define flash_EBIU_AMBCTL0_WAT B0WAT_15 -#endif -#if (flash_EBIU_AMBCTL_WAT == 14) - #define flash_EBIU_AMBCTL0_WAT B0WAT_14 -#endif -#if (flash_EBIU_AMBCTL_WAT == 13) - #define flash_EBIU_AMBCTL0_WAT B0WAT_13 -#endif -#if (flash_EBIU_AMBCTL_WAT == 12) - #define flash_EBIU_AMBCTL0_WAT B0WAT_12 -#endif -#if (flash_EBIU_AMBCTL_WAT == 11) - #define flash_EBIU_AMBCTL0_WAT B0WAT_11 -#endif -#if (flash_EBIU_AMBCTL_WAT == 10) - #define flash_EBIU_AMBCTL0_WAT B0WAT_10 -#endif -#if (flash_EBIU_AMBCTL_WAT == 9) - #define flash_EBIU_AMBCTL0_WAT B0WAT_9 -#endif -#if (flash_EBIU_AMBCTL_WAT == 8) - #define flash_EBIU_AMBCTL0_WAT B0WAT_8 -#endif -#if (flash_EBIU_AMBCTL_WAT == 7) - #define flash_EBIU_AMBCTL0_WAT B0WAT_7 -#endif -#if (flash_EBIU_AMBCTL_WAT == 6) - #define flash_EBIU_AMBCTL0_WAT B0WAT_6 -#endif -#if (flash_EBIU_AMBCTL_WAT == 5) - #define flash_EBIU_AMBCTL0_WAT B0WAT_5 -#endif -#if (flash_EBIU_AMBCTL_WAT == 4) - #define flash_EBIU_AMBCTL0_WAT B0WAT_4 -#endif -#if (flash_EBIU_AMBCTL_WAT == 3) - #define flash_EBIU_AMBCTL0_WAT B0WAT_3 -#endif -#if (flash_EBIU_AMBCTL_WAT == 2) - #define flash_EBIU_AMBCTL0_WAT B0WAT_2 -#endif -#if (flash_EBIU_AMBCTL_WAT == 1) - #define flash_EBIU_AMBCTL0_WAT B0WAT_1 -#endif - -#if (flash_EBIU_AMBCTL_RAT > 14) - #define flash_EBIU_AMBCTL0_RAT B0RAT_15 -#endif -#if (flash_EBIU_AMBCTL_RAT == 14) - #define flash_EBIU_AMBCTL0_RAT B0RAT_14 -#endif -#if (flash_EBIU_AMBCTL_RAT == 13) - #define flash_EBIU_AMBCTL0_RAT B0RAT_13 -#endif -#if (flash_EBIU_AMBCTL_RAT == 12) - #define flash_EBIU_AMBCTL0_RAT B0RAT_12 -#endif -#if (flash_EBIU_AMBCTL_RAT == 11) - #define flash_EBIU_AMBCTL0_RAT B0RAT_11 -#endif -#if (flash_EBIU_AMBCTL_RAT == 10) - #define flash_EBIU_AMBCTL0_RAT B0RAT_10 -#endif -#if (flash_EBIU_AMBCTL_RAT == 9) - #define flash_EBIU_AMBCTL0_RAT B0RAT_9 -#endif -#if (flash_EBIU_AMBCTL_RAT == 8) - #define flash_EBIU_AMBCTL0_RAT B0RAT_8 -#endif -#if (flash_EBIU_AMBCTL_RAT == 7) - #define flash_EBIU_AMBCTL0_RAT B0RAT_7 -#endif -#if (flash_EBIU_AMBCTL_RAT == 6) - #define flash_EBIU_AMBCTL0_RAT B0RAT_6 -#endif -#if (flash_EBIU_AMBCTL_RAT == 5) - #define flash_EBIU_AMBCTL0_RAT B0RAT_5 -#endif -#if (flash_EBIU_AMBCTL_RAT == 4) - #define flash_EBIU_AMBCTL0_RAT B0RAT_4 -#endif -#if (flash_EBIU_AMBCTL_RAT == 3) - #define flash_EBIU_AMBCTL0_RAT B0RAT_3 -#endif -#if (flash_EBIU_AMBCTL_RAT == 2) - #define flash_EBIU_AMBCTL0_RAT B0RAT_2 -#endif -#if (flash_EBIU_AMBCTL_RAT == 1) - #define flash_EBIU_AMBCTL0_RAT B0RAT_1 -#endif - -#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN diff --git a/include/asm-blackfin/module.h b/include/asm-blackfin/module.h deleted file mode 100644 index 99c8848e68..0000000000 --- a/include/asm-blackfin/module.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _ASM_BFIN_MODULE_H -#define _ASM_BFIN_MODULE_H - -#define MODULE_SYMBOL_PREFIX "_" - -#define Elf_Shdr Elf32_Shdr -#define Elf_Sym Elf32_Sym -#define Elf_Ehdr Elf32_Ehdr -#define FLG_CODE_IN_L1 0x10 -#define FLG_DATA_IN_L1 0x20 - -struct mod_arch_specific { -}; -#endif /* _ASM_BFIN_MODULE_H */ diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h deleted file mode 100644 index bf90cd56c6..0000000000 --- a/include/asm-blackfin/page.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * U-boot - page.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_PAGE_H -#define _BLACKFIN_PAGE_H - -/* PAGE_SHIFT determines the page size */ - -#define PAGE_SHIFT (12) -#define PAGE_SIZE (4096) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#ifdef __KERNEL__ - -#include <asm/setup.h> - -#if PAGE_SHIFT < 13 -#define KTHREAD_SIZE (8192) -#else -#define KTHREAD_SIZE PAGE_SIZE -#endif - -#ifndef __ASSEMBLY__ - -#define get_user_page(vaddr) __get_free_page(GFP_KERNEL) -#define free_user_page(page, addr) free_page(addr) - -#define clear_page(page) memset((page), 0, PAGE_SIZE) -#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) - -#define clear_user_page(page, vaddr) clear_page(page) -#define copy_user_page(to, from, vaddr) copy_page(to, from) - -/* - * These are used to make use of C type-checking.. - */ -typedef struct { - unsigned long pte; -} pte_t; -typedef struct { - unsigned long pmd[16]; -} pmd_t; -typedef struct { - unsigned long pgd; -} pgd_t; -typedef struct { - unsigned long pgprot; -} pgprot_t; - -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((&x)->pmd[0]) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -/* to align the pointer to the (next) page boundary */ -#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) - -/* Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size - 1) >> (PAGE_SHIFT - 1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - -#endif /* !__ASSEMBLY__ */ - -#include <asm/page_offset.h> - -#define PAGE_OFFSET (PAGE_OFFSET_RAW) - -#ifndef __ASSEMBLY__ - -#define __pa(vaddr) virt_to_phys((void *)vaddr) -#define __va(paddr) phys_to_virt((unsigned long)paddr) - -#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) -#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) -#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) - -#define PAGE_BUG(page) do { \ - BUG(); \ -} while (0) - -#endif - -#endif - -#endif diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h deleted file mode 100644 index 1b9ee01982..0000000000 --- a/include/asm-blackfin/page_offset.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * U-boot - page_offset.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This handles the memory map.. */ - -#ifdef CONFIG_BLACKFIN -#define PAGE_OFFSET_RAW 0x00000000 -#endif diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h deleted file mode 100644 index f1f2b5ffc2..0000000000 --- a/include/asm-blackfin/posix_types.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * U-boot - posix_types.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ARCH_BLACKFIN_POSIX_TYPES_H -#define __ARCH_BLACKFIN_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char *__kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) - -#undef __FD_CLR -#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) - -#undef __FD_ISSET -#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) - -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ - -#endif diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h deleted file mode 100644 index 7095e95626..0000000000 --- a/include/asm-blackfin/processor.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * U-boot - processor.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * This file is based on - * include/asm-m68k/processor.h - * Changes made by Akbar Hussain Lineo, Inc, May 2001 for BLACKFIN - * Copyright (C) 1995 Hamish Macdonald - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_BLACKFIN_PROCESSOR_H -#define __ASM_BLACKFIN_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -#include <asm/segment.h> -#include <asm/ptrace.h> -#include <asm/current.h> - -extern inline unsigned long rdusp(void) -{ - unsigned long usp; - - __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp)); - return usp; -} - -extern inline void wrusp(unsigned long usp) -{ - __asm__ __volatile__("usp = %0;\n\t"::"da"(usp)); -} - -/* - * User space process size: 3.75GB. This is hardcoded into a few places, - * so don't change it unless you know what you are doing. - */ -#define TASK_SIZE (0xF0000000UL) - -/* - * Bus types - */ -#define EISA_bus 0 -#define MCA_bus 0 - -/* There is no pc register avaliable for BLACKFIN, so we are going to get - * it indirectly - */ - - -/* - * if you change this structure, you must change the code and offsets - * in m68k/machasm.S - */ - -struct thread_struct { - unsigned long ksp; /* kernel stack pointer */ - unsigned long usp; /* user stack pointer */ - unsigned short seqstat; /* saved status register */ - unsigned long esp0; /* points to SR of stack frame pt_regs */ - unsigned long pc; /* instruction pointer */ -}; - -#define INIT_MMAP { &init_mm, 0, 0x40000000, NULL, __pgprot(_PAGE_PRESENT|_PAGE_ACCESSED), VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL } - -#define INIT_THREAD { \ - sizeof(init_stack) + (unsigned long) init_stack, 0, \ - PS_S, 0\ -} - -/* - * Do necessary setup to start up a newly executed thread. - * - * pass the data segment into user programs if it exists, - * it can't hurt anything as far as I can tell - */ -#define start_thread(_regs, _pc, _usp) \ -do { \ - set_fs(USER_DS); /* reads from user space */ \ - (_regs)->pc = (_pc); \ - if (current->mm) \ - (_regs)->r5 = current->mm->start_data; \ - (_regs)->seqstat &= ~0x0c00; \ - wrusp(_usp); \ - /* Adde by HuTao, May 26, 2003 3:39PM */\ - if ((_regs)->ipend & 0x8000) /* check whether system in supper mode - StChen */\ - (_regs)->ipend = 0x0;\ -} while(0) - -/* Forward declaration, a strange C thing */ -struct task_struct; - -/* Free all resources held by a thread. */ -static inline void release_thread(struct task_struct *dead_task) -{ -} - -extern int kernel_thread(int (*fn) (void *), void *arg, - unsigned long flags); - -#define copy_segments(tsk, mm) do { } while (0) -#define release_segments(mm) do { } while (0) -#define forget_segments() do { } while (0) - -/* - * Free current thread data structures etc.. - */ -static inline void exit_thread(void) -{ -} - -/* - * Return saved PC of a blocked thread. - */ -extern inline unsigned long thread_saved_pc(struct thread_struct *t) -{ - extern void scheduling_functions_start_here(void); - extern void scheduling_functions_end_here(void); - return 0; -} - -unsigned long get_wchan(struct task_struct *p); - -#define KSTK_EIP(tsk) \ - ({ \ - unsigned long eip = 0; \ - if ((tsk)->thread.esp0 > PAGE_SIZE && \ - MAP_NR((tsk)->thread.esp0) < max_mapnr) \ - eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \ - eip; }) -#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) -#define THREAD_SIZE (2*PAGE_SIZE) - -/* Allocation and freeing of basic task resources. */ -#define alloc_task_struct() \ - ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) -#define free_task_struct(p) free_pages((unsigned long)(p),1) -#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) - -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) - -#endif diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h deleted file mode 100644 index afd57773ac..0000000000 --- a/include/asm-blackfin/ptrace.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * U-boot - ptrace.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_PTRACE_H -#define _BLACKFIN_PTRACE_H - -#define NEW_PT_REGS - -/* - * GCC defines register number like this: - * ----------------------------- - * 0 - 7 are data registers R0-R7 - * 8 - 15 are address registers P0-P7 - * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3 - * 32 - 33 A registers A0 & A1 - * 34 - status register - * - * We follows above, except: - * 32-33 --- Low 32-bit of A0&1 - * 34-35 --- High 8-bit of A0&1 - */ - -#if defined(NEW_PT_REGS) - -#define PT_IPEND 0 -#define PT_SYSCFG (PT_IPEND+4) -#define PT_SEQSTAT (PT_SYSCFG+4) -#define PT_RETE (PT_SEQSTAT+4) -#define PT_RETN (PT_RETE+4) -#define PT_RETX (PT_RETN+4) -#define PT_RETI (PT_RETX+4) -#define PT_PC PT_RETI -#define PT_RETS (PT_RETI+4) -#define PT_RESERVED (PT_RETS+4) -#define PT_ASTAT (PT_RESERVED+4) -#define PT_LB1 (PT_ASTAT+4) -#define PT_LB0 (PT_LB1+4) -#define PT_LT1 (PT_LB0+4) -#define PT_LT0 (PT_LT1+4) -#define PT_LC1 (PT_LT0+4) -#define PT_LC0 (PT_LC1+4) -#define PT_A1W (PT_LC0+4) -#define PT_A1X (PT_A1W+4) -#define PT_A0W (PT_A1X+4) -#define PT_A0X (PT_A0W+4) -#define PT_B3 (PT_A0X+4) -#define PT_B2 (PT_B3+4) -#define PT_B1 (PT_B2+4) -#define PT_B0 (PT_B1+4) -#define PT_L3 (PT_B0+4) -#define PT_L2 (PT_L3+4) -#define PT_L1 (PT_L2+4) -#define PT_L0 (PT_L1+4) -#define PT_M3 (PT_L0+4) -#define PT_M2 (PT_M3+4) -#define PT_M1 (PT_M2+4) -#define PT_M0 (PT_M1+4) -#define PT_I3 (PT_M0+4) -#define PT_I2 (PT_I3+4) -#define PT_I1 (PT_I2+4) -#define PT_I0 (PT_I1+4) -#define PT_USP (PT_I0+4) -#define PT_FP (PT_USP+4) -#define PT_P5 (PT_FP+4) -#define PT_P4 (PT_P5+4) -#define PT_P3 (PT_P4+4) -#define PT_P2 (PT_P3+4) -#define PT_P1 (PT_P2+4) -#define PT_P0 (PT_P1+4) -#define PT_R7 (PT_P0+4) -#define PT_R6 (PT_R7+4) -#define PT_R5 (PT_R6+4) -#define PT_R4 (PT_R5+4) -#define PT_R3 (PT_R4+4) -#define PT_R2 (PT_R3+4) -#define PT_R1 (PT_R2+4) -#define PT_R0 (PT_R1+4) -#define PT_ORIG_R0 (PT_R0+4) -#define PT_SR PT_SEQSTAT - -#else -/* - * Here utilize blackfin : dpregs = [pregs + imm16s4] - * [pregs + imm16s4] = dpregs - * to access defferent saved reg in stack - */ -#define PT_R3 0 -#define PT_R4 4 -#define PT_R2 8 -#define PT_R1 12 -#define PT_P5 16 -#define PT_P4 20 -#define PT_P3 24 -#define PT_P2 28 -#define PT_P1 32 -#define PT_P0 36 -#define PT_R7 40 -#define PT_R6 44 -#define PT_R5 48 -#define PT_PC 52 -#define PT_SEQSTAT 56 /* so-called SR reg */ -#define PT_SR PT_SEQSTAT -#define PT_ASTAT 60 -#define PT_RETS 64 -#define PT_A1w 68 -#define PT_A0w 72 -#define PT_A1x 76 -#define PT_A0x 80 -#define PT_ORIG_R0 84 -#define PT_R0 88 -#define PT_USP 92 -#define PT_FP 96 -#define PT_SP 100 - -/* Added by HuTao, May26 2003 3:18PM */ -#define PT_IPEND 100 - -/* Add SYSCFG register for single stepping support */ -#define PT_SYSCFG 104 - -#endif - -#ifndef __ASSEMBLY__ - -#if defined(NEW_PT_REGS) -/* this struct defines the way the registers are stored on the - * stack during a system call. - */ -struct pt_regs { - long ipend; - long syscfg; - long seqstat; - long rete; - long retn; - long retx; - long pc; - long rets; - long reserved; - long astat; - long lb1; - long lb0; - long lt1; - long lt0; - long lc1; - long lc0; - long a1w; - long a1x; - long a0w; - long a0x; - long b3; - long b2; - long b1; - long b0; - long l3; - long l2; - long l1; - long l0; - long m3; - long m2; - long m1; - long m0; - long i3; - long i2; - long i1; - long i0; - long usp; - long fp; - long p5; - long p4; - long p3; - long p2; - long p1; - long p0; - long r7; - long r6; - long r5; - long r4; - long r3; - long r2; - long r1; - long r0; - long orig_r0; -}; - -#else -/* now we don't know what regs the system call will use */ -struct pt_regs { - long r3; - long r4; - long r2; - long r1; - long p5; - long p4; - long p3; - long p2; - long p1; - long p0; - long r7; - long r6; - long r5; - unsigned long pc; - unsigned long seqstat; - unsigned long astat; - unsigned long rets; - long a1w; - long a0w; - long a1x; - long a0x; - long orig_r0; - long r0; - long usp; - long fp; -/* - * Added for supervisor/user mode switch. - * - * HuTao May26 03 3:23PM - */ - long ipend; - long syscfg; -}; - -#endif - -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 /* ptrace signal */ - -#ifdef __KERNEL__ - -#ifndef PS_S -#define PS_S (0x0c00) - -/* Bit 11:10 of SEQSTAT defines user/supervisor/debug mode - * 00: user - * 01: supervisor - * 1x: debug - */ - -#define PS_M (0x1000) /* I am not sure why this is required here Akbar */ -#endif - -#define user_mode(regs) (!((regs)->seqstat & PS_S)) -#define instruction_pointer(regs) ((regs)->pc) -extern void show_regs(struct pt_regs *); - -#endif -#endif -#endif diff --git a/include/asm-blackfin/segment.h b/include/asm-blackfin/segment.h deleted file mode 100644 index 9e6d817fc7..0000000000 --- a/include/asm-blackfin/segment.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * U-boot - segment.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_SEGMENT_H -#define _BLACKFIN_SEGMENT_H - -/* define constants */ -typedef unsigned long mm_segment_t; /* domain register */ - -#define KERNEL_CS 0x0 -#define KERNEL_DS 0x0 -#define __KERNEL_CS 0x0 -#define __KERNEL_DS 0x0 - -#define USER_CS 0x1 -#define USER_DS 0x1 -#define __USER_CS 0x1 -#define __USER_DS 0x1 - -#define get_ds() (KERNEL_DS) -#define get_fs() (__USER_DS) -#define segment_eq(a,b) ((a) == (b)) -#define set_fs(val) - -#endif diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h deleted file mode 100644 index 440aaf9d9c..0000000000 --- a/include/asm-blackfin/setup.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * U-boot - setup.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * This file is based on - * asm/setup.h -- Definition of the Linux/Blackfin setup information - * Copyright Lineo, Inc 2001 Tony Kou - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_SETUP_H -#define _BLACKFIN_SETUP_H - -/* - * Linux/Blackfin Architectures - */ - -#define MACH_BFIN 1 - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ -extern unsigned long blackfin_machtype; -#endif - -#if defined(CONFIG_BFIN) -#define MACH_IS_BFIN (blackfin_machtype == MACH_BFIN) -#endif - -#ifndef MACH_TYPE -#define MACH_TYPE (blackfin_machtype) -#endif - -#endif - -/* - * CPU, FPU and MMU types - * - * Note: we don't need now: - * - */ - -#ifndef __ASSEMBLY__ -extern unsigned long blackfin_cputype; -#ifdef CONFIG_VME -extern unsigned long vme_brdtype; -#endif - -/* - * Miscellaneous - */ - -#define NUM_MEMINFO 4 -#define CL_SIZE 256 - -extern int blackfin_num_memory; /* # of memory blocks found (and used) */ -extern int blackfin_realnum_memory; /* real # of memory blocks found */ - -struct mem_info { - unsigned long addr; /* physical address of memory chunk */ - unsigned long size; /* length of memory chunk (in bytes) */ -}; - -extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */ - -#endif - -#endif diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h deleted file mode 100644 index 883009ae0d..0000000000 --- a/include/asm-blackfin/string.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * U-boot - string.h String functions - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Changed by Lineo Inc. May 2001 */ - -#ifndef _BLACKFINNOMMU_STRING_H_ -#define _BLACKFINNOMMU_STRING_H_ - -#endif /* _BLACKFIN_STRING_H_ */ diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h deleted file mode 100644 index d84b6365bc..0000000000 --- a/include/asm-blackfin/system.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * U-boot - system.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_SYSTEM_H -#define _BLACKFIN_SYSTEM_H - -#include <asm/linkage.h> -#include <asm/blackfin.h> -#include <asm/segment.h> -#include <asm/entry.h> - -#define prepare_to_switch() do { } while(0) - -/* - * switch_to(n) should switch tasks to task ptr, first checking that - * ptr isn't the current task, in which case it does nothing. This - * also clears the TS-flag if the task we switched to has used the - * math co-processor latest. - * - * 05/25/01 - Tony Kou (tonyko@lineo.ca) - * - * Adapted for BlackFin (ADI) by Ted Ma, Metrowerks, and Motorola GSG - * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) - * Copyright (c) 2003 Metrowerks (www.metrowerks.com) - */ - -asmlinkage void resume(void); - -#define switch_to(prev,next,last) { \ - void *_last; \ - __asm__ __volatile__( \ - "r0 = %1;\n\t" \ - "r1 = %2;\n\t" \ - "call resume;\n\t" \ - "%0 = r0;\n\t" \ - : "=d" (_last) \ - : "d" (prev), \ - "d" (next) \ - : "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\ - (last) = _last; \ -} - -/* Force kerenl switch to user mode -- Steven Chen */ -#define switch_to_user_mode() { \ - __asm__ __volatile__( \ - "call kernel_to_user_mode;\n\t" \ - :: \ - : "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\ -} - -/* - * Interrupt configuring macros. - */ - -extern int irq_flags; - -#define __sti() { \ - __asm__ __volatile__ ( \ - "r3 = %0;" \ - "sti r3;" \ - ::"m"(irq_flags):"R3"); \ -} - -#define __cli() { \ - __asm__ __volatile__ ( \ - "cli r3;" \ - :::"R3"); \ -} - -#define __save_flags(x) { \ - __asm__ __volatile__ ( \ - "cli r3;" \ - "%0 = r3;" \ - "sti r3;" \ - ::"m"(x):"R3"); \ -} - -#define __save_and_cli(x) { \ - __asm__ __volatile__ ( \ - "cli r3;" \ - "%0 = r3;" \ - ::"m"(x):"R3"); \ -} - -#define __restore_flags(x) { \ - __asm__ __volatile__ ( \ - "r3 = %0;" \ - "sti r3;" \ - ::"m"(x):"R3"); \ -} - -/* For spinlocks etc */ -#define local_irq_save(x) __save_and_cli(x) -#define local_irq_restore(x) __restore_flags(x) -#define local_irq_disable() __cli() -#define local_irq_enable() __sti() - -#define cli() __cli() -#define sti() __sti() -#define save_flags(x) __save_flags(x) -#define restore_flags(x) __restore_flags(x) -#define save_and_cli(x) __save_and_cli(x) - -/* - * Force strict CPU ordering. - */ -#define nop() asm volatile ("nop;\n\t"::) -#define mb() asm volatile ("" : : :"memory") -#define rmb() asm volatile ("" : : :"memory") -#define wmb() asm volatile ("" : : :"memory") -#define set_rmb(var, value) do { xchg(&var, value); } while (0) -#define set_mb(var, value) set_rmb(var, value) -#define set_wmb(var, value) do { var = value; wmb(); } while (0) - -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#else -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#endif - -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) -#define tas(ptr) (xchg((ptr),1)) - -struct __xchg_dummy { - unsigned long a[100]; -}; -#define __xg(x) ((volatile struct __xchg_dummy *)(x)) - -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, - int size) -{ - unsigned long tmp; - unsigned long flags = 0; - - save_and_cli(flags); - - switch (size) { - case 1: - __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory"); - break; - case 2: - __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory"); - break; - case 4: - __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory"); - break; - } - restore_flags(flags); - return tmp; -} - -/* Depend on whether Blackfin has hard reset function */ -/* YES it does, but it is tricky to implement - FIXME later ...MaTed--- */ -#define HARD_RESET_NOW() ({}) - -#endif /* _BLACKFIN_SYSTEM_H */ diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h deleted file mode 100644 index b1dde4aba4..0000000000 --- a/include/asm-blackfin/traps.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * U-boot - traps.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * This file is based on - * linux/include/asm/traps.h - * Copyright (C) 1993 Hamish Macdonald - * Lineo, Inc Jul 2001 Tony Kou - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_TRAPS_H -#define _BLACKFIN_TRAPS_H - -#define VEC_SYS (0) -#define VEC_EXCPT01 (1) -#define VEC_EXCPT02 (2) -#define VEC_EXCPT03 (3) -#define VEC_EXCPT04 (4) -#define VEC_EXCPT05 (5) -#define VEC_EXCPT06 (6) -#define VEC_EXCPT07 (7) -#define VEC_EXCPT08 (8) -#define VEC_EXCPT09 (9) -#define VEC_EXCPT10 (10) -#define VEC_EXCPT11 (11) -#define VEC_EXCPT12 (12) -#define VEC_EXCPT13 (13) -#define VEC_EXCPT14 (14) -#define VEC_EXCPT15 (15) -#define VEC_STEP (16) -#define VEC_OVFLOW (17) -#define VEC_UNDEF_I (33) -#define VEC_ILGAL_I (34) -#define VEC_CPLB_VL (35) -#define VEC_MISALI_D (36) -#define VEC_UNCOV (37) -#define VEC_CPLB_M (38) -#define VEC_CPLB_MHIT (39) -#define VEC_WATCH (40) -#define VEC_ISTRU_VL (41) -#define VEC_MISALI_I (42) -#define VEC_CPLB_I_VL (43) -#define VEC_CPLB_I_M (44) -#define VEC_CPLB_I_MHIT (45) -#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ - -#define VECOFF(vec) ((vec)<<2) - -#ifndef __ASSEMBLY__ - -/* Status register bits */ -#define PS_T (0x8000) -#define PS_S (0x0c00) /* Supervisor mode = 0b01 */ -#define PS_D (0x0c00) /* Debug mode = 0b1x */ -#define PS_M (0x1000) -#define PS_C (0x0001) - -#endif -#endif diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h deleted file mode 100644 index 6058908e25..0000000000 --- a/include/asm-blackfin/types.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * U-boot - types.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_TYPES_H -#define _BLACKFIN_TYPES_H - -/* - * This file is never included by application software unless - * explicitly requested (e.g., via linux/types.h) in which case the - * application is Linux specific so (user-) name space pollution is - * not a major issue. However, for interoperability, libraries still - * need to be careful to avoid a name clashes. - */ -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -/* HK0617 -- Changes to unsigned long temporarily */ -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -#endif - -#endif /* __ASSEMBLY__ */ - -#define BITS_PER_LONG 32 - -#endif diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h deleted file mode 100644 index ec39338039..0000000000 --- a/include/asm-blackfin/u-boot.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * U-boot - u-boot.h Structure declarations for board specific data - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _U_BOOT_H_ -#define _U_BOOT_H_ 1 - -typedef struct bd_info { - int bi_baudrate; /* serial console baudrate */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned char bi_enetaddr[6]; /* Ethernet adress */ - unsigned long bi_arch_number; /* unique id for this board */ - unsigned long bi_boot_params; /* where this board expects params */ - unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ -} bd_t; - -#define bi_env_data bi_env->data -#define bi_env_crc bi_env->crc - -#endif /* _U_BOOT_H_ */ diff --git a/include/asm-generic/u-boot.lds.h b/include/asm-generic/u-boot.lds.h index 4982ce03db..1a5f2f7753 100644 --- a/include/asm-generic/u-boot.lds.h +++ b/include/asm-generic/u-boot.lds.h @@ -1,6 +1,6 @@ #ifdef CONFIG_ARCH_IMX25 -#include <asm/arch/u-boot.lds.h> +#include <mach/u-boot.lds.h> #endif #ifndef PRE_IMAGE diff --git a/include/asm-m68k/arch-mcfv4e/clocks.h b/include/asm-m68k/arch-mcfv4e/clocks.h deleted file mode 100644 index 50124b1948..0000000000 --- a/include/asm-m68k/arch-mcfv4e/clocks.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * This File contains functions to query clock settings for the actual - * board. - */ -#ifndef __ASM_ARCH_CLOCKS_H -#define __ASM_ARCH_CLOCKS_H - -ulong mcfv4e_get_bus_clk(void); - -#endif /* __ASM_ARCH_CLOCKS_H */ diff --git a/include/asm-m68k/arch-mcfv4e/debug_ll.h b/include/asm-m68k/arch-mcfv4e/debug_ll.h deleted file mode 100644 index 064961d925..0000000000 --- a/include/asm-m68k/arch-mcfv4e/debug_ll.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * This File contains declaration for early output support - */ -#ifndef __INCLUDE_ARCH_DEBUG_LL_H__ -#define __INCLUDE_ARCH_DEBUG_LL_H__ - -extern __inline__ void putc( char ch ) -{ - //extern int early_console_putc( char ch); - early_console_putc(NULL,ch); -} - -#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */ diff --git a/include/asm-m68k/arch-mcfv4e/hardware.h b/include/asm-m68k/arch-mcfv4e/hardware.h deleted file mode 100644 index 46dc08897f..0000000000 --- a/include/asm-m68k/arch-mcfv4e/hardware.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * This File contains declaration for early output support - */ -#ifndef __ASM_ARCH_HARDWARE_H__ -#define __ASM_ARCH_HARDWARE_H__ - -#include <sizes.h> - -#ifdef CONFIG_ARCH_MCF54xx -#include "mcf54xx-regs.h" -#endif - -#endif /* __ASM_ARCH_HARDWARE_H__ */ diff --git a/include/asm-m68k/arch-mcfv4e/mcf54xx-regs.h b/include/asm-m68k/arch-mcfv4e/mcf54xx-regs.h deleted file mode 100644 index e1b17d55e4..0000000000 --- a/include/asm-m68k/arch-mcfv4e/mcf54xx-regs.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * This File contains declaration for early output support - */ -#ifndef __MCF54xx_REGS_H__ -#define __MCF54xx_REGS_H__ - -/* System Registers for V4E cores (MCF547x and MCF548x) */ -#include <asm/coldfire/mcf5xxx.h> - -#endif /* __MCF54xx_REGS_H__ */ diff --git a/include/asm-m68k/atomic.h b/include/asm-m68k/atomic.h deleted file mode 100644 index be3fa3f195..0000000000 --- a/include/asm-m68k/atomic.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Declaration for atomic operations - */ - -/* Empty dummy FIXME */ diff --git a/include/asm-m68k/bitops.h b/include/asm-m68k/bitops.h deleted file mode 100644 index bfc3054155..0000000000 --- a/include/asm-m68k/bitops.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Bitops helper functions and defines for M68k - * - * bit 0 is the LSB of addr; bit 32 is the HSB. - * - * Please note that the code in this file should never be included - * from user space. Many of these are not implemented in assembler - * since they would be too costly. Also, they require priviledged - * instructions (which are not available from user mode) to ensure - * that they are atomic. - */ - -#ifndef __ASM_M68K_BITOPS_H -#define __ASM_M68K_BITOPS_H - -/* - * Function prototypes to keep gcc -Wall happy. - */ -extern void set_bit(int nr, volatile void * addr); - -static inline void __set_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7)); -} - -extern void clear_bit(int nr, volatile void * addr); - -static inline void __clear_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7)); -} - -extern void change_bit(int nr, volatile void * addr); - -static inline void __change_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] ^= (1U << (nr & 7)); -} - -extern int test_and_set_bit(int nr, volatile void * addr); - -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; - - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval | mask; - return oldval & mask; -} - -extern int test_and_clear_bit(int nr, volatile void * addr); - -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; - - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval & ~mask; - return oldval & mask; -} - -extern int test_and_change_bit(int nr, volatile void * addr); - -static inline int __test_and_change_bit(int nr, volatile void *addr) -{ - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; - - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval ^ mask; - return oldval & mask; -} - -extern int find_first_zero_bit(void * addr, unsigned size); -extern int find_next_zero_bit(void * addr, int size, int offset); - -/* - * This routine doesn't need to be atomic. - */ -static inline int test_bit(int nr, const void * addr) -{ - return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); -} - -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz(unsigned long word) -{ - int k; - - word = ~word; - k = 31; - if (word & 0x0000ffff) { k -= 16; word <<= 16; } - if (word & 0x00ff0000) { k -= 8; word <<= 8; } - if (word & 0x0f000000) { k -= 4; word <<= 4; } - if (word & 0x30000000) { k -= 2; word <<= 2; } - if (word & 0x40000000) { k -= 1; } - return k; -} - -#include <asm-generic/bitops/ffs.h> -#include <asm-generic/bitops/hweight.h> - -#define ext2_set_bit test_and_set_bit -#define ext2_clear_bit test_and_clear_bit -#define ext2_test_bit test_bit -#define ext2_find_first_zero_bit find_first_zero_bit -#define ext2_find_next_zero_bit find_next_zero_bit - -/* Bitmap functions for the minix filesystem. */ -#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) -#define minix_set_bit(nr,addr) set_bit(nr,addr) -#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) -#define minix_test_bit(nr,addr) test_bit(nr,addr) -#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) - -#endif /* __ASM_M68K_BITOPS_H */ diff --git a/include/asm-m68k/bootinfo.h b/include/asm-m68k/bootinfo.h deleted file mode 100644 index 8b18fda350..0000000000 --- a/include/asm-m68k/bootinfo.h +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Definition of the Linux/m68k boot information structure. - * - * Taken from Linux includes. See there for latest version, and update - * if needed - */ -#ifndef _M68K_BOOTINFO_H -#define _M68K_BOOTINFO_H - - -/* - * Bootinfo definitions - * - * This is an easily parsable and extendable structure containing all - * information to be passed from the bootstrap to the kernel. - * - * This way I hope to keep all future changes back/forewards compatible. - * Thus, keep your fingers crossed... - * - * This structure is copied right after the kernel bss by the bootstrap - * routine. - */ - -#ifndef __ASSEMBLY__ - -struct bi_record { - unsigned short tag; /* tag ID */ - unsigned short size; /* size of record (in bytes) */ - unsigned long data[0]; /* data */ -}; - -#endif /* __ASSEMBLY__ */ - - -/* - * Tag Definitions - * - * Machine independent tags start counting from 0x0000 - * Machine dependent tags start counting from 0x8000 - */ - -#define BI_LAST 0x0000 /* last record (sentinel) */ -#define BI_MACHTYPE 0x0001 /* machine type (u_long) */ -#define BI_CPUTYPE 0x0002 /* cpu type (u_long) */ -#define BI_FPUTYPE 0x0003 /* fpu type (u_long) */ -#define BI_MMUTYPE 0x0004 /* mmu type (u_long) */ -#define BI_MEMCHUNK 0x0005 /* memory chunk address and size */ - /* (struct mem_info) */ -#define BI_RAMDISK 0x0006 /* ramdisk address and size */ - /* (struct mem_info) */ -#define BI_COMMAND_LINE 0x0007 /* kernel command line parameters */ - /* (string) */ - -/* - * Amiga-specific tags - */ - -#define BI_AMIGA_MODEL 0x8000 /* model (u_long) */ -#define BI_AMIGA_AUTOCON 0x8001 /* AutoConfig device */ - /* (struct ConfigDev) */ -#define BI_AMIGA_CHIP_SIZE 0x8002 /* size of Chip RAM (u_long) */ -#define BI_AMIGA_VBLANK 0x8003 /* VBLANK frequency (u_char) */ -#define BI_AMIGA_PSFREQ 0x8004 /* power supply frequency (u_char) */ -#define BI_AMIGA_ECLOCK 0x8005 /* EClock frequency (u_long) */ -#define BI_AMIGA_CHIPSET 0x8006 /* native chipset present (u_long) */ -#define BI_AMIGA_SERPER 0x8007 /* serial port period (u_short) */ - -/* - * Atari-specific tags - */ - -#define BI_ATARI_MCH_COOKIE 0x8000 /* _MCH cookie from TOS (u_long) */ -#define BI_ATARI_MCH_TYPE 0x8001 /* special machine type (u_long) */ - /* (values are ATARI_MACH_* defines */ - -/* mch_cookie values (upper word) */ -#define ATARI_MCH_ST 0 -#define ATARI_MCH_STE 1 -#define ATARI_MCH_TT 2 -#define ATARI_MCH_FALCON 3 - -/* mch_type values */ -#define ATARI_MACH_NORMAL 0 /* no special machine type */ -#define ATARI_MACH_MEDUSA 1 /* Medusa 040 */ -#define ATARI_MACH_HADES 2 /* Hades 040 or 060 */ -#define ATARI_MACH_AB40 3 /* Afterburner040 on Falcon */ - -/* - * VME-specific tags - */ - -#define BI_VME_TYPE 0x8000 /* VME sub-architecture (u_long) */ -#define BI_VME_BRDINFO 0x8001 /* VME board information (struct) */ - -/* BI_VME_TYPE codes */ -#define VME_TYPE_TP34V 0x0034 /* Tadpole TP34V */ -#define VME_TYPE_MVME147 0x0147 /* Motorola MVME147 */ -#define VME_TYPE_MVME162 0x0162 /* Motorola MVME162 */ -#define VME_TYPE_MVME166 0x0166 /* Motorola MVME166 */ -#define VME_TYPE_MVME167 0x0167 /* Motorola MVME167 */ -#define VME_TYPE_MVME172 0x0172 /* Motorola MVME172 */ -#define VME_TYPE_MVME177 0x0177 /* Motorola MVME177 */ -#define VME_TYPE_BVME4000 0x4000 /* BVM Ltd. BVME4000 */ -#define VME_TYPE_BVME6000 0x6000 /* BVM Ltd. BVME6000 */ - -/* BI_VME_BRDINFO is a 32 byte struct as returned by the Bug code on - * Motorola VME boards. Contains board number, Bug version, board - * configuration options, etc. See include/asm/mvme16xhw.h for details. - */ - - -/* - * Macintosh-specific tags (all u_long) - */ - -#define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */ -#define BI_MAC_VADDR 0x8001 /* Mac video base address */ -#define BI_MAC_VDEPTH 0x8002 /* Mac video depth */ -#define BI_MAC_VROW 0x8003 /* Mac video rowbytes */ -#define BI_MAC_VDIM 0x8004 /* Mac video dimensions */ -#define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */ -#define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */ -#define BI_MAC_BTIME 0x8007 /* Mac boot time */ -#define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */ -#define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */ -#define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */ -#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */ - -/* - * Macintosh hardware profile data - unused, see macintosh.h for - * resonable type values - */ - -#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) */ -#define BI_MAC_VIA2BASE 0x8011 /* Mac VIA2 base address (type varies) */ -#define BI_MAC_VIA2TYPE 0x8012 /* Mac VIA2 type (VIA, RBV, OSS) */ -#define BI_MAC_ADBTYPE 0x8013 /* Mac ADB interface type */ -#define BI_MAC_ASCBASE 0x8014 /* Mac Apple Sound Chip base address */ -#define BI_MAC_SCSI5380 0x8015 /* Mac NCR 5380 SCSI (base address, multi) */ -#define BI_MAC_SCSIDMA 0x8016 /* Mac SCSI DMA (base address) */ -#define BI_MAC_SCSI5396 0x8017 /* Mac NCR 53C96 SCSI (base address, multi) */ -#define BI_MAC_IDETYPE 0x8018 /* Mac IDE interface type */ -#define BI_MAC_IDEBASE 0x8019 /* Mac IDE interface base address */ -#define BI_MAC_NUBUS 0x801a /* Mac Nubus type (none, regular, pseudo) */ -#define BI_MAC_SLOTMASK 0x801b /* Mac Nubus slots present */ -#define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */ -#define BI_MAC_ETHTYPE 0x801d /* Mac builtin ethernet type (Sonic, MACE */ -#define BI_MAC_ETHBASE 0x801e /* Mac builtin ethernet base address */ -#define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardware */ -#define BI_MAC_IOP_SWIM 0x8020 /* Mac SWIM floppy IOP */ -#define BI_MAC_IOP_ADB 0x8021 /* Mac ADB IOP */ - -/* - * Mac: compatibility with old booter data format (temporarily) - * Fields unused with the new bootinfo can be deleted now; instead of - * adding new fields the struct might be splitted into a hardware address - * part and a hardware type part - */ - -#ifndef __ASSEMBLY__ - -struct mac_booter_data -{ - unsigned long videoaddr; - unsigned long videorow; - unsigned long videodepth; - unsigned long dimensions; - unsigned long args; - unsigned long boottime; - unsigned long gmtbias; - unsigned long bootver; - unsigned long videological; - unsigned long sccbase; - unsigned long id; - unsigned long memsize; - unsigned long serialmf; - unsigned long serialhsk; - unsigned long serialgpi; - unsigned long printmf; - unsigned long printhsk; - unsigned long printgpi; - unsigned long cpuid; - unsigned long rombase; - unsigned long adbdelay; - unsigned long timedbra; -}; - -extern struct mac_booter_data - mac_bi_data; - -#endif - -/* - * Apollo-specific tags - */ - -#define BI_APOLLO_MODEL 0x8000 /* model (u_long) */ - -/* - * HP300-specific tags - */ - -#define BI_HP300_MODEL 0x8000 /* model (u_long) */ -#define BI_HP300_UART_SCODE 0x8001 /* UART select code (u_long) */ -#define BI_HP300_UART_ADDR 0x8002 /* phys. addr of UART (u_long) */ - -/* - * Stuff for bootinfo interface versioning - * - * At the start of kernel code, a 'struct bootversion' is located. - * bootstrap checks for a matching version of the interface before booting - * a kernel, to avoid user confusion if kernel and bootstrap don't work - * together :-) - * - * If incompatible changes are made to the bootinfo interface, the major - * number below should be stepped (and the minor reset to 0) for the - * appropriate machine. If a change is backward-compatible, the minor - * should be stepped. "Backwards-compatible" means that booting will work, - * but certain features may not. - */ - -#define BOOTINFOV_MAGIC 0x4249561A /* 'BIV^Z' */ -#define MK_BI_VERSION(major,minor) (((major)<<16)+(minor)) -#define BI_VERSION_MAJOR(v) (((v) >> 16) & 0xffff) -#define BI_VERSION_MINOR(v) ((v) & 0xffff) - -#ifndef __ASSEMBLY__ - -struct bootversion { - unsigned short branch; - unsigned long magic; - struct { - unsigned long machtype; - unsigned long version; - } machversions[0]; -}; - -#endif /* __ASSEMBLY__ */ - -#define AMIGA_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) -#define ATARI_BOOTI_VERSION MK_BI_VERSION( 2, 1 ) -#define MAC_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) -#define MVME147_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) -#define MVME16x_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) -#define BVME6000_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) -#define Q40_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) -#define HP300_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) - -#ifdef BOOTINFO_COMPAT_1_0 - -/* - * Backwards compatibility with bootinfo interface version 1.0 - */ - -#define COMPAT_AMIGA_BOOTI_VERSION MK_BI_VERSION( 1, 0 ) -#define COMPAT_ATARI_BOOTI_VERSION MK_BI_VERSION( 1, 0 ) -#define COMPAT_MAC_BOOTI_VERSION MK_BI_VERSION( 1, 0 ) - -#include <linux/zorro.h> - -#define COMPAT_NUM_AUTO 16 - -struct compat_bi_Amiga { - int model; - int num_autocon; - struct ConfigDev autocon[COMPAT_NUM_AUTO]; - unsigned long chip_size; - unsigned char vblank; - unsigned char psfreq; - unsigned long eclock; - unsigned long chipset; - unsigned long hw_present; -}; - -struct compat_bi_Atari { - unsigned long hw_present; - unsigned long mch_cookie; -}; - -#ifndef __ASSEMBLY__ - -struct compat_bi_Macintosh -{ - unsigned long videoaddr; - unsigned long videorow; - unsigned long videodepth; - unsigned long dimensions; - unsigned long args; - unsigned long boottime; - unsigned long gmtbias; - unsigned long bootver; - unsigned long videological; - unsigned long sccbase; - unsigned long id; - unsigned long memsize; - unsigned long serialmf; - unsigned long serialhsk; - unsigned long serialgpi; - unsigned long printmf; - unsigned long printhsk; - unsigned long printgpi; - unsigned long cpuid; - unsigned long rombase; - unsigned long adbdelay; - unsigned long timedbra; -}; - -#endif - -struct compat_mem_info { - unsigned long addr; - unsigned long size; -}; - -#define COMPAT_NUM_MEMINFO 4 - -#define COMPAT_CPUB_68020 0 -#define COMPAT_CPUB_68030 1 -#define COMPAT_CPUB_68040 2 -#define COMPAT_CPUB_68060 3 -#define COMPAT_FPUB_68881 5 -#define COMPAT_FPUB_68882 6 -#define COMPAT_FPUB_68040 7 -#define COMPAT_FPUB_68060 8 - -#define COMPAT_CPU_68020 (1<<COMPAT_CPUB_68020) -#define COMPAT_CPU_68030 (1<<COMPAT_CPUB_68030) -#define COMPAT_CPU_68040 (1<<COMPAT_CPUB_68040) -#define COMPAT_CPU_68060 (1<<COMPAT_CPUB_68060) -#define COMPAT_CPU_MASK (31) -#define COMPAT_FPU_68881 (1<<COMPAT_FPUB_68881) -#define COMPAT_FPU_68882 (1<<COMPAT_FPUB_68882) -#define COMPAT_FPU_68040 (1<<COMPAT_FPUB_68040) -#define COMPAT_FPU_68060 (1<<COMPAT_FPUB_68060) -#define COMPAT_FPU_MASK (0xfe0) - -#define COMPAT_CL_SIZE (256) - -struct compat_bootinfo { - unsigned long machtype; - unsigned long cputype; - struct compat_mem_info memory[COMPAT_NUM_MEMINFO]; - int num_memory; - unsigned long ramdisk_size; - unsigned long ramdisk_addr; - char command_line[COMPAT_CL_SIZE]; - union { - struct compat_bi_Amiga bi_ami; - struct compat_bi_Atari bi_ata; - struct compat_bi_Macintosh bi_mac; - } bi_un; -}; - -#define bi_amiga bi_un.bi_ami -#define bi_atari bi_un.bi_ata -#define bi_mac bi_un.bi_mac - -#endif /* BOOTINFO_COMPAT_1_0 */ - - -#endif /* _M68K_BOOTINFO_H */ diff --git a/include/asm-m68k/byteorder.h b/include/asm-m68k/byteorder.h deleted file mode 100644 index 779fca00f0..0000000000 --- a/include/asm-m68k/byteorder.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Define byte order of target - * - * M68K is always big-endian mode. - * - * When in big endian mode, byte accesses appear as: - * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 - * and word accesses (data or instruction) appear as: - * d0...d31 - */ -#ifndef __ASM_M68K_BYTEORDER_H -#define __ASM_M68K_BYTEORDER_H - - -#include <asm/types.h> - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif -#include <linux/byteorder/big_endian.h> - -#endif diff --git a/include/asm-m68k/coldfire/mcf548x.h b/include/asm-m68k/coldfire/mcf548x.h deleted file mode 100644 index 6b3eff3826..0000000000 --- a/include/asm-m68k/coldfire/mcf548x.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF547X and MCF548X processors - */ -#ifndef __MCF548X_H__ -#define __MCF548X_H__ - -/* - * useful padding structure for register maps - */ -typedef struct -{ - vuint8_t a; - vuint16_t b; -} __attribute ((packed)) vuint24_t; - -/* - * Include all internal hardware register macros and defines for this CPU. - */ -#include "asm/coldfire/mcf548x/mcf548x_fec.h" -#include "asm/coldfire/mcf548x/mcf548x_siu.h" -#include "asm/coldfire/mcf548x/mcf548x_ctm.h" -#include "asm/coldfire/mcf548x/mcf548x_dspi.h" -#include "asm/coldfire/mcf548x/mcf548x_eport.h" -#include "asm/coldfire/mcf548x/mcf548x_fbcs.h" -#include "asm/coldfire/mcf548x/mcf548x_gpio.h" -#include "asm/coldfire/mcf548x/mcf548x_gpt.h" -#include "asm/coldfire/mcf548x/mcf548x_i2c.h" -#include "asm/coldfire/mcf548x/mcf548x_intc.h" -#include "asm/coldfire/mcf548x/mcf548x_sdramc.h" -#include "asm/coldfire/mcf548x/mcf548x_sec.h" -#include "asm/coldfire/mcf548x/mcf548x_slt.h" -#include "asm/coldfire/mcf548x/mcf548x_usb.h" -#include "asm/coldfire/mcf548x/mcf548x_psc.h" -#include "asm/coldfire/mcf548x/mcf548x_uart.h" -#include "asm/coldfire/mcf548x/mcf548x_sram.h" -#include "asm/coldfire/mcf548x/mcf548x_pci.h" -#include "asm/coldfire/mcf548x/mcf548x_pciarb.h" -#include "asm/coldfire/mcf548x/mcf548x_dma.h" -#include "asm/coldfire/mcf548x/mcf548x_dma_ereq.h" -#include "asm/coldfire/mcf548x/mcf548x_can.h" -#include "asm/coldfire/mcf548x/mcf548x_xlbarb.h" - -#endif /* __MCF548X_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_can.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_can.h deleted file mode 100644 index 1956f0d760..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_can.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * CAN controllers - */ -#ifndef __MCF548X_CAN_H__ -#define __MCF548X_CAN_H__ - -/* - * FlexCAN Module (CAN) - */ - -/* Register read/write macros */ -#define MCF_CAN_CANMCR0 (*(vuint32_t*)(&__MBAR[0x00A000])) -#define MCF_CAN_CANCTRL0 (*(vuint32_t*)(&__MBAR[0x00A004])) -#define MCF_CAN_TIMER0 (*(vuint32_t*)(&__MBAR[0x00A008])) -#define MCF_CAN_RXGMASK0 (*(vuint32_t*)(&__MBAR[0x00A010])) -#define MCF_CAN_RX14MASK0 (*(vuint32_t*)(&__MBAR[0x00A014])) -#define MCF_CAN_RX15MASK0 (*(vuint32_t*)(&__MBAR[0x00A018])) -#define MCF_CAN_ERRCNT0 (*(vuint32_t*)(&__MBAR[0x00A01C])) -#define MCF_CAN_ERRSTAT0 (*(vuint32_t*)(&__MBAR[0x00A020])) -#define MCF_CAN_IMASK0 (*(vuint16_t*)(&__MBAR[0x00A02A])) -#define MCF_CAN_IFLAG0 (*(vuint16_t*)(&__MBAR[0x00A032])) -#define MCF_CAN_CANMCR1 (*(vuint32_t*)(&__MBAR[0x00A800])) -#define MCF_CAN_CANCTRL1 (*(vuint32_t*)(&__MBAR[0x00A804])) -#define MCF_CAN_TIMER1 (*(vuint32_t*)(&__MBAR[0x00A808])) -#define MCF_CAN_RXGMASK1 (*(vuint32_t*)(&__MBAR[0x00A810])) -#define MCF_CAN_RX14MASK1 (*(vuint32_t*)(&__MBAR[0x00A814])) -#define MCF_CAN_RX15MASK1 (*(vuint32_t*)(&__MBAR[0x00A818])) -#define MCF_CAN_ERRCNT1 (*(vuint32_t*)(&__MBAR[0x00A81C])) -#define MCF_CAN_ERRSTAT1 (*(vuint32_t*)(&__MBAR[0x00A820])) -#define MCF_CAN_IMASK1 (*(vuint16_t*)(&__MBAR[0x00A82A])) -#define MCF_CAN_IFLAG1 (*(vuint16_t*)(&__MBAR[0x00A832])) -#define MCF_CAN_CANMCR(x) (*(vuint32_t*)(&__MBAR[0x00A000+((x)*0x800)])) -#define MCF_CAN_CANCTRL(x) (*(vuint32_t*)(&__MBAR[0x00A004+((x)*0x800)])) -#define MCF_CAN_TIMER(x) (*(vuint32_t*)(&__MBAR[0x00A008+((x)*0x800)])) -#define MCF_CAN_RXGMASK(x) (*(vuint32_t*)(&__MBAR[0x00A010+((x)*0x800)])) -#define MCF_CAN_RX14MASK(x) (*(vuint32_t*)(&__MBAR[0x00A014+((x)*0x800)])) -#define MCF_CAN_RX15MASK(x) (*(vuint32_t*)(&__MBAR[0x00A018+((x)*0x800)])) -#define MCF_CAN_ERRCNT(x) (*(vuint32_t*)(&__MBAR[0x00A01C+((x)*0x800)])) -#define MCF_CAN_ERRSTAT(x) (*(vuint32_t*)(&__MBAR[0x00A020+((x)*0x800)])) -#define MCF_CAN_IMASK(x) (*(vuint16_t*)(&__MBAR[0x00A02A+((x)*0x800)])) -#define MCF_CAN_IFLAG(x) (*(vuint16_t*)(&__MBAR[0x00A032+((x)*0x800)])) - -/* Bit definitions and macros for MCF_CAN_CANMCR */ -#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) -#define MCF_CAN_CANMCR_SUPV (0x00800000) -#define MCF_CAN_CANMCR_FRZACK (0x01000000) -#define MCF_CAN_CANMCR_SOFTRST (0x02000000) -#define MCF_CAN_CANMCR_HALT (0x10000000) -#define MCF_CAN_CANMCR_FRZ (0x40000000) -#define MCF_CAN_CANMCR_MDIS (0x80000000) - -/* Bit definitions and macros for MCF_CAN_CANCTRL */ -#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) -#define MCF_CAN_CANCTRL_LOM (0x00000008) -#define MCF_CAN_CANCTRL_LBUF (0x00000010) -#define MCF_CAN_CANCTRL_TSYNC (0x00000020) -#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) -#define MCF_CAN_CANCTRL_SAMP (0x00000080) -#define MCF_CAN_CANCTRL_LPB (0x00001000) -#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) -#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) -#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) -#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) -#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) -#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) -#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_CAN_TIMER */ -#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RXGMASK */ -#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX14MASK */ -#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX15MASK */ -#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_ERRCNT */ -#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) -#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for MCF_CAN_ERRSTAT */ -#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) -#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) -#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) -#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) -#define MCF_CAN_ERRSTAT_TXRX (0x00000040) -#define MCF_CAN_ERRSTAT_IDLE (0x00000080) -#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) -#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) -#define MCF_CAN_ERRSTAT_STFERR (0x00000400) -#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) -#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) -#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) -#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) -#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) -#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) -#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) - -/* Bit definitions and macros for MCF_CAN_IMASK */ -#define MCF_CAN_IMASK_BUF0M (0x0001) -#define MCF_CAN_IMASK_BUF1M (0x0002) -#define MCF_CAN_IMASK_BUF2M (0x0004) -#define MCF_CAN_IMASK_BUF3M (0x0008) -#define MCF_CAN_IMASK_BUF4M (0x0010) -#define MCF_CAN_IMASK_BUF5M (0x0020) -#define MCF_CAN_IMASK_BUF6M (0x0040) -#define MCF_CAN_IMASK_BUF7M (0x0080) -#define MCF_CAN_IMASK_BUF8M (0x0100) -#define MCF_CAN_IMASK_BUF9M (0x0200) -#define MCF_CAN_IMASK_BUF10M (0x0400) -#define MCF_CAN_IMASK_BUF11M (0x0800) -#define MCF_CAN_IMASK_BUF12M (0x1000) -#define MCF_CAN_IMASK_BUF13M (0x2000) -#define MCF_CAN_IMASK_BUF14M (0x4000) -#define MCF_CAN_IMASK_BUF15M (0x8000) - -/* Bit definitions and macros for MCF_CAN_IFLAG */ -#define MCF_CAN_IFLAG_BUF0I (0x0001) -#define MCF_CAN_IFLAG_BUF1I (0x0002) -#define MCF_CAN_IFLAG_BUF2I (0x0004) -#define MCF_CAN_IFLAG_BUF3I (0x0008) -#define MCF_CAN_IFLAG_BUF4I (0x0010) -#define MCF_CAN_IFLAG_BUF5I (0x0020) -#define MCF_CAN_IFLAG_BUF6I (0x0040) -#define MCF_CAN_IFLAG_BUF7I (0x0080) -#define MCF_CAN_IFLAG_BUF8I (0x0100) -#define MCF_CAN_IFLAG_BUF9I (0x0200) -#define MCF_CAN_IFLAG_BUF10I (0x0400) -#define MCF_CAN_IFLAG_BUF11I (0x0800) -#define MCF_CAN_IFLAG_BUF12I (0x1000) -#define MCF_CAN_IFLAG_BUF13I (0x2000) -#define MCF_CAN_IFLAG_BUF14I (0x4000) -#define MCF_CAN_IFLAG_BUF15I (0x8000) - -#endif /* __MCF548X_CAN_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_ctm.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_ctm.h deleted file mode 100644 index c4982668c5..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_ctm.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Common Timer Module - */ -#ifndef __MCF548X_CTM_H__ -#define __MCF548X_CTM_H__ - -/* - * Comm Timer Module (CTM) - */ - -/* Register read/write macros */ -#define MCF_CTM_CTCRF0 (*(vuint32_t*)(&__MBAR[0x007F00])) -#define MCF_CTM_CTCRF1 (*(vuint32_t*)(&__MBAR[0x007F04])) -#define MCF_CTM_CTCRF2 (*(vuint32_t*)(&__MBAR[0x007F08])) -#define MCF_CTM_CTCRF3 (*(vuint32_t*)(&__MBAR[0x007F0C])) -#define MCF_CTM_CTCRFn(x) (*(vuint32_t*)(&__MBAR[0x007F00+((x)*0x004)])) -#define MCF_CTM_CTCRV4 (*(vuint32_t*)(&__MBAR[0x007F10])) -#define MCF_CTM_CTCRV5 (*(vuint32_t*)(&__MBAR[0x007F14])) -#define MCF_CTM_CTCRV6 (*(vuint32_t*)(&__MBAR[0x007F18])) -#define MCF_CTM_CTCRV7 (*(vuint32_t*)(&__MBAR[0x007F1C])) -#define MCF_CTM_CTCRVn(x) (*(vuint32_t*)(&__MBAR[0x007F10+((x)*0x004)])) - -/* Bit definitions and macros for MCF_CTM_CTCRFn */ -#define MCF_CTM_CTCRFn_CRV(x) (((x)&0x0000FFFF)<<0) -#define MCF_CTM_CTCRFn_S(x) (((x)&0x0000000F)<<16) -#define MCF_CTM_CTCRFn_PCT(x) (((x)&0x00000007)<<20) -#define MCF_CTM_CTCRFn_M (0x00800000) -#define MCF_CTM_CTCRFn_IM (0x01000000) -#define MCF_CTM_CTCRFn_I (0x80000000) -#define MCF_CTM_CTCRFn_PCT_100 (0x00000000) -#define MCF_CTM_CTCRFn_PCT_50 (0x00100000) -#define MCF_CTM_CTCRFn_PCT_25 (0x00200000) -#define MCF_CTM_CTCRFn_PCT_12p5 (0x00300000) -#define MCF_CTM_CTCRFn_PCT_6p25 (0x00400000) -#define MCF_CTM_CTCRFn_PCT_OFF (0x00500000) -#define MCF_CTM_CTCRFn_S_CLK_1 (0x00000000) -#define MCF_CTM_CTCRFn_S_CLK_2 (0x00010000) -#define MCF_CTM_CTCRFn_S_CLK_4 (0x00020000) -#define MCF_CTM_CTCRFn_S_CLK_8 (0x00030000) -#define MCF_CTM_CTCRFn_S_CLK_16 (0x00040000) -#define MCF_CTM_CTCRFn_S_CLK_32 (0x00050000) -#define MCF_CTM_CTCRFn_S_CLK_64 (0x00060000) -#define MCF_CTM_CTCRFn_S_CLK_128 (0x00070000) -#define MCF_CTM_CTCRFn_S_CLK_256 (0x00080000) - -/* Bit definitions and macros for MCF_CTM_CTCRVn */ -#define MCF_CTM_CTCRVn_CRV(x) (((x)&0x00FFFFFF)<<0) -#define MCF_CTM_CTCRVn_PCT(x) (((x)&0x00000007)<<24) -#define MCF_CTM_CTCRVn_M (0x08000000) -#define MCF_CTM_CTCRVn_S(x) (((x)&0x0000000F)<<28) -#define MCF_CTM_CTCRVn_S_CLK_1 (0x00000000) -#define MCF_CTM_CTCRVn_S_CLK_2 (0x10000000) -#define MCF_CTM_CTCRVn_S_CLK_4 (0x20000000) -#define MCF_CTM_CTCRVn_S_CLK_8 (0x30000000) -#define MCF_CTM_CTCRVn_S_CLK_16 (0x40000000) -#define MCF_CTM_CTCRVn_S_CLK_32 (0x50000000) -#define MCF_CTM_CTCRVn_S_CLK_64 (0x60000000) -#define MCF_CTM_CTCRVn_S_CLK_128 (0x70000000) -#define MCF_CTM_CTCRVn_S_CLK_256 (0x80000000) -#define MCF_CTM_CTCRVn_PCT_100 (0x00000000) -#define MCF_CTM_CTCRVn_PCT_50 (0x01000000) -#define MCF_CTM_CTCRVn_PCT_25 (0x02000000) -#define MCF_CTM_CTCRVn_PCT_12p5 (0x03000000) -#define MCF_CTM_CTCRVn_PCT_6p25 (0x04000000) -#define MCF_CTM_CTCRVn_PCT_OFF (0x05000000) - -#endif /* __MCF548X_CTM_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_dma.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_dma.h deleted file mode 100644 index 73abc07a43..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_dma.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Multichannel DMA - */ -#ifndef __MCF548X_DMA_H__ -#define __MCF548X_DMA_H__ - -/* - * Multi-Channel DMA (DMA) - */ - -/* Register read/write macros */ -#define MCF_DMA_DIPR (*(vuint32_t*)(&__MBAR[0x008014])) -#define MCF_DMA_DIMR (*(vuint32_t*)(&__MBAR[0x008018])) -#define MCF_DMA_IMCR (*(vuint32_t*)(&__MBAR[0x00805C])) - -/* Bit definitions and macros for MCF_DMA_DIPR */ -#define MCF_DMA_DIPR_TASK0 (0x00000001) -#define MCF_DMA_DIPR_TASK1 (0x00000002) -#define MCF_DMA_DIPR_TASK2 (0x00000004) -#define MCF_DMA_DIPR_TASK3 (0x00000008) -#define MCF_DMA_DIPR_TASK4 (0x00000010) -#define MCF_DMA_DIPR_TASK5 (0x00000020) -#define MCF_DMA_DIPR_TASK6 (0x00000040) -#define MCF_DMA_DIPR_TASK7 (0x00000080) -#define MCF_DMA_DIPR_TASK8 (0x00000100) -#define MCF_DMA_DIPR_TASK9 (0x00000200) -#define MCF_DMA_DIPR_TASK10 (0x00000400) -#define MCF_DMA_DIPR_TASK11 (0x00000800) -#define MCF_DMA_DIPR_TASK12 (0x00001000) -#define MCF_DMA_DIPR_TASK13 (0x00002000) -#define MCF_DMA_DIPR_TASK14 (0x00004000) -#define MCF_DMA_DIPR_TASK15 (0x00008000) - -/* Bit definitions and macros for MCF_DMA_DIMR */ -#define MCF_DMA_DIMR_TASK0 (0x00000001) -#define MCF_DMA_DIMR_TASK1 (0x00000002) -#define MCF_DMA_DIMR_TASK2 (0x00000004) -#define MCF_DMA_DIMR_TASK3 (0x00000008) -#define MCF_DMA_DIMR_TASK4 (0x00000010) -#define MCF_DMA_DIMR_TASK5 (0x00000020) -#define MCF_DMA_DIMR_TASK6 (0x00000040) -#define MCF_DMA_DIMR_TASK7 (0x00000080) -#define MCF_DMA_DIMR_TASK8 (0x00000100) -#define MCF_DMA_DIMR_TASK9 (0x00000200) -#define MCF_DMA_DIMR_TASK10 (0x00000400) -#define MCF_DMA_DIMR_TASK11 (0x00000800) -#define MCF_DMA_DIMR_TASK12 (0x00001000) -#define MCF_DMA_DIMR_TASK13 (0x00002000) -#define MCF_DMA_DIMR_TASK14 (0x00004000) -#define MCF_DMA_DIMR_TASK15 (0x00008000) - -/* Bit definitions and macros for MCF_DMA_IMCR */ -#define MCF_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0) -#define MCF_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2) -#define MCF_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4) -#define MCF_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6) -#define MCF_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8) -#define MCF_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10) -#define MCF_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12) -#define MCF_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14) -#define MCF_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16) -#define MCF_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18) -#define MCF_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20) -#define MCF_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22) -#define MCF_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24) -#define MCF_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26) -#define MCF_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28) -#define MCF_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30) -#define MCF_DMA_IMCR_SRC16_FEC0RX (0x00000000) -#define MCF_DMA_IMCR_SRC17_FEC0TX (0x00000000) -#define MCF_DMA_IMCR_SRC18_FEC0RX (0x00000020) -#define MCF_DMA_IMCR_SRC19_FEC0TX (0x00000080) -#define MCF_DMA_IMCR_SRC20_FEC1RX (0x00000100) -#define MCF_DMA_IMCR_SRC21_DREQ1 (0x00000000) -#define MCF_DMA_IMCR_SRC21_FEC1TX (0x00000400) -#define MCF_DMA_IMCR_SRC22_FEC0RX (0x00001000) -#define MCF_DMA_IMCR_SRC23_FEC0TX (0x00004000) -#define MCF_DMA_IMCR_SRC24_CTM0 (0x00010000) -#define MCF_DMA_IMCR_SRC24_FEC1RX (0x00020000) -#define MCF_DMA_IMCR_SRC25_CTM1 (0x00040000) -#define MCF_DMA_IMCR_SRC25_FEC1TX (0x00080000) -#define MCF_DMA_IMCR_SRC26_USBEP4 (0x00000000) -#define MCF_DMA_IMCR_SRC26_CTM2 (0x00200000) -#define MCF_DMA_IMCR_SRC27_USBEP5 (0x00000000) -#define MCF_DMA_IMCR_SRC27_CTM3 (0x00800000) -#define MCF_DMA_IMCR_SRC28_USBEP6 (0x00000000) -#define MCF_DMA_IMCR_SRC28_CTM4 (0x01000000) -#define MCF_DMA_IMCR_SRC28_DREQ1 (0x02000000) -#define MCF_DMA_IMCR_SRC28_PSC2RX (0x03000000) -#define MCF_DMA_IMCR_SRC29_DREQ1 (0x04000000) -#define MCF_DMA_IMCR_SRC29_CTM5 (0x08000000) -#define MCF_DMA_IMCR_SRC29_PSC2TX (0x0C000000) -#define MCF_DMA_IMCR_SRC30_FEC1RX (0x00000000) -#define MCF_DMA_IMCR_SRC30_CTM6 (0x10000000) -#define MCF_DMA_IMCR_SRC30_PSC3RX (0x30000000) -#define MCF_DMA_IMCR_SRC31_FEC1TX (0x00000000) -#define MCF_DMA_IMCR_SRC31_CTM7 (0x80000000) -#define MCF_DMA_IMCR_SRC31_PSC3TX (0xC0000000) - -#endif /* __MCF548X_DMA_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_dma_ereq.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_dma_ereq.h deleted file mode 100644 index 309689f464..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_dma_ereq.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Multi-Channel DMA External Requests (DMA_EREQ) - */ -#ifndef __MCF548X_DMA_EREQ_H__ -#define __MCF548X_DMA_EREQ_H__ - -/* - * Multi-Channel DMA External Requests (DMA_EREQ) - */ - -/* Register read/write macros */ -#define MCF_DMA_EREQ_EREQBAR0 (*(vuint32_t*)(&__MBAR[0x000D00])) -#define MCF_DMA_EREQ_EREQMASK0 (*(vuint32_t*)(&__MBAR[0x000D04])) -#define MCF_DMA_EREQ_EREQCTRL0 (*(vuint32_t*)(&__MBAR[0x000D08])) -#define MCF_DMA_EREQ_EREQBAR1 (*(vuint32_t*)(&__MBAR[0x000D10])) -#define MCF_DMA_EREQ_EREQMASK1 (*(vuint32_t*)(&__MBAR[0x000D14])) -#define MCF_DMA_EREQ_EREQCTRL1 (*(vuint32_t*)(&__MBAR[0x000D18])) -#define MCF_DMA_EREQ_EREQBAR(x) (*(vuint32_t*)(&__MBAR[0x000D00+((x)*0x010)])) -#define MCF_DMA_EREQ_EREQMASK(x) (*(vuint32_t*)(&__MBAR[0x000D04+((x)*0x010)])) -#define MCF_DMA_EREQ_EREQCTRL(x) (*(vuint32_t*)(&__MBAR[0x000D08+((x)*0x010)])) - -/* Bit definitions and macros for MCF_DMA_EREQ_EREQCTRL */ -#define MCF_DMA_EREQ_EREQCTRL_EN (0x00000001) -#define MCF_DMA_EREQ_EREQCTRL_SYNC (0x00000002) -#define MCF_DMA_EREQ_EREQCTRL_DACKWID(x) (((x)&0x00000003)<<2) -#define MCF_DMA_EREQ_EREQCTRL_BSEL(x) (((x)&0x00000003)<<4) -#define MCF_DMA_EREQ_EREQCTRL_MD(x) (((x)&0x00000003)<<6) -#define MCF_DMA_EREQ_EREQCTRL_MD_IDLE (0x00000000) -#define MCF_DMA_EREQ_EREQCTRL_MD_LEVEL (0x00000040) -#define MCF_DMA_EREQ_EREQCTRL_MD_EDGE (0x00000080) -#define MCF_DMA_EREQ_EREQCTRL_MD_PIPED (0x000000C0) -#define MCF_DMA_EREQ_EREQCTRL_BSEL_MEM_WRITE (0x00000000) -#define MCF_DMA_EREQ_EREQCTRL_BSEL_MEM_READ (0x00000010) -#define MCF_DMA_EREQ_EREQCTRL_BSEL_PERIPH_WRITE (0x00000020) -#define MCF_DMA_EREQ_EREQCTRL_BSEL_PERIPH_READ (0x00000030) -#define MCF_DMA_EREQ_EREQCTRL_DACKWID_ONE (0x00000000) -#define MCF_DMA_EREQ_EREQCTRL_DACKWID_TWO (0x00000004) -#define MCF_DMA_EREQ_EREQCTRL_DACKWID_THREE (0x00000008) -#define MCF_DMA_EREQ_EREQCTRL_DACKWID_FOUR (0x0000000C) - -#endif /* __MCF548X_DMA_EREQ_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_dspi.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_dspi.h deleted file mode 100644 index 4d8f33142e..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_dspi.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * DMA Serial Peripheral Interface (DSPI) - */ -#ifndef __MCF548X_DSPI_H__ -#define __MCF548X_DSPI_H__ - -/* - * DMA Serial Peripheral Interface (DSPI) - */ - -/* Register read/write macros */ -#define MCF_DSPI_DMCR (*(vuint32_t*)(&__MBAR[0x008A00])) -#define MCF_DSPI_DTCR (*(vuint32_t*)(&__MBAR[0x008A08])) -#define MCF_DSPI_DCTAR0 (*(vuint32_t*)(&__MBAR[0x008A0C])) -#define MCF_DSPI_DCTAR1 (*(vuint32_t*)(&__MBAR[0x008A10])) -#define MCF_DSPI_DCTAR2 (*(vuint32_t*)(&__MBAR[0x008A14])) -#define MCF_DSPI_DCTAR3 (*(vuint32_t*)(&__MBAR[0x008A18])) -#define MCF_DSPI_DCTAR4 (*(vuint32_t*)(&__MBAR[0x008A1C])) -#define MCF_DSPI_DCTAR5 (*(vuint32_t*)(&__MBAR[0x008A20])) -#define MCF_DSPI_DCTAR6 (*(vuint32_t*)(&__MBAR[0x008A24])) -#define MCF_DSPI_DCTAR7 (*(vuint32_t*)(&__MBAR[0x008A28])) -#define MCF_DSPI_DCTARn(x) (*(vuint32_t*)(&__MBAR[0x008A0C+((x)*0x004)])) -#define MCF_DSPI_DSR (*(vuint32_t*)(&__MBAR[0x008A2C])) -#define MCF_DSPI_DIRSR (*(vuint32_t*)(&__MBAR[0x008A30])) -#define MCF_DSPI_DTFR (*(vuint32_t*)(&__MBAR[0x008A34])) -#define MCF_DSPI_DRFR (*(vuint32_t*)(&__MBAR[0x008A38])) -#define MCF_DSPI_DTFDR0 (*(vuint32_t*)(&__MBAR[0x008A3C])) -#define MCF_DSPI_DTFDR1 (*(vuint32_t*)(&__MBAR[0x008A40])) -#define MCF_DSPI_DTFDR2 (*(vuint32_t*)(&__MBAR[0x008A44])) -#define MCF_DSPI_DTFDR3 (*(vuint32_t*)(&__MBAR[0x008A48])) -#define MCF_DSPI_DTFDRn(x) (*(vuint32_t*)(&__MBAR[0x008A3C+((x)*0x004)])) -#define MCF_DSPI_DRFDR0 (*(vuint32_t*)(&__MBAR[0x008A7C])) -#define MCF_DSPI_DRFDR1 (*(vuint32_t*)(&__MBAR[0x008A80])) -#define MCF_DSPI_DRFDR2 (*(vuint32_t*)(&__MBAR[0x008A84])) -#define MCF_DSPI_DRFDR3 (*(vuint32_t*)(&__MBAR[0x008A88])) -#define MCF_DSPI_DRFDRn(x) (*(vuint32_t*)(&__MBAR[0x008A7C+((x)*0x004)])) - -/* Bit definitions and macros for MCF_DSPI_DMCR */ -#define MCF_DSPI_DMCR_HALT (0x00000001) -#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) -#define MCF_DSPI_DMCR_CRXF (0x00000400) -#define MCF_DSPI_DMCR_CTXF (0x00000800) -#define MCF_DSPI_DMCR_DRXF (0x00001000) -#define MCF_DSPI_DMCR_DTXF (0x00002000) -#define MCF_DSPI_DMCR_CSIS0 (0x00010000) -#define MCF_DSPI_DMCR_CSIS2 (0x00040000) -#define MCF_DSPI_DMCR_CSIS3 (0x00080000) -#define MCF_DSPI_DMCR_CSIS5 (0x00200000) -#define MCF_DSPI_DMCR_ROOE (0x01000000) -#define MCF_DSPI_DMCR_PCSSE (0x02000000) -#define MCF_DSPI_DMCR_MTFE (0x04000000) -#define MCF_DSPI_DMCR_FRZ (0x08000000) -#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) -#define MCF_DSPI_DMCR_CSCK (0x40000000) -#define MCF_DSPI_DMCR_MSTR (0x80000000) - -/* Bit definitions and macros for MCF_DSPI_DTCR */ -#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_DSPI_DCTARn */ -#define MCF_DSPI_DCTARn_BR(x) (((x)&0x0000000F)<<0) -#define MCF_DSPI_DCTARn_DT(x) (((x)&0x0000000F)<<4) -#define MCF_DSPI_DCTARn_ASC(x) (((x)&0x0000000F)<<8) -#define MCF_DSPI_DCTARn_CSSCK(x) (((x)&0x0000000F)<<12) -#define MCF_DSPI_DCTARn_PBR(x) (((x)&0x00000003)<<16) -#define MCF_DSPI_DCTARn_PDT(x) (((x)&0x00000003)<<18) -#define MCF_DSPI_DCTARn_PASC(x) (((x)&0x00000003)<<20) -#define MCF_DSPI_DCTARn_PCSSCK(x) (((x)&0x00000003)<<22) -#define MCF_DSPI_DCTARn_LSBFE (0x01000000) -#define MCF_DSPI_DCTARn_CPHA (0x02000000) -#define MCF_DSPI_DCTARn_CPOL (0x04000000) -#define MCF_DSPI_DCTARn_TRSZ(x) (((x)&0x0000000F)<<27) -#define MCF_DSPI_DCTARn_PCSSCK_1CLK (0x00000000) -#define MCF_DSPI_DCTARn_PCSSCK_3CLK (0x00400000) -#define MCF_DSPI_DCTARn_PCSSCK_5CLK (0x00800000) -#define MCF_DSPI_DCTARn_PCSSCK_7CLK (0x00A00000) -#define MCF_DSPI_DCTARn_PASC_1CLK (0x00000000) -#define MCF_DSPI_DCTARn_PASC_3CLK (0x00100000) -#define MCF_DSPI_DCTARn_PASC_5CLK (0x00200000) -#define MCF_DSPI_DCTARn_PASC_7CLK (0x00300000) -#define MCF_DSPI_DCTARn_PDT_1CLK (0x00000000) -#define MCF_DSPI_DCTARn_PDT_3CLK (0x00040000) -#define MCF_DSPI_DCTARn_PDT_5CLK (0x00080000) -#define MCF_DSPI_DCTARn_PDT_7CLK (0x000A0000) -#define MCF_DSPI_DCTARn_PBR_1CLK (0x00000000) -#define MCF_DSPI_DCTARn_PBR_3CLK (0x00010000) -#define MCF_DSPI_DCTARn_PBR_5CLK (0x00020000) -#define MCF_DSPI_DCTARn_PBR_7CLK (0x00030000) - -/* Bit definitions and macros for MCF_DSPI_DSR */ -#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0) -#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) -#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) -#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) -#define MCF_DSPI_DSR_RFDF (0x00020000) -#define MCF_DSPI_DSR_RFOF (0x00080000) -#define MCF_DSPI_DSR_TFFF (0x02000000) -#define MCF_DSPI_DSR_TFUF (0x08000000) -#define MCF_DSPI_DSR_EOQF (0x10000000) -#define MCF_DSPI_DSR_TXRXS (0x40000000) -#define MCF_DSPI_DSR_TCF (0x80000000) - -/* Bit definitions and macros for MCF_DSPI_DIRSR */ -#define MCF_DSPI_DIRSR_RFDFS (0x00010000) -#define MCF_DSPI_DIRSR_RFDFE (0x00020000) -#define MCF_DSPI_DIRSR_RFOFE (0x00080000) -#define MCF_DSPI_DIRSR_TFFFS (0x01000000) -#define MCF_DSPI_DIRSR_TFFFE (0x02000000) -#define MCF_DSPI_DIRSR_TFUFE (0x08000000) -#define MCF_DSPI_DIRSR_EOQFE (0x10000000) -#define MCF_DSPI_DIRSR_TCFE (0x80000000) - -/* Bit definitions and macros for MCF_DSPI_DTFR */ -#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_DSPI_DTFR_CS0 (0x00010000) -#define MCF_DSPI_DTFR_CS2 (0x00040000) -#define MCF_DSPI_DTFR_CS3 (0x00080000) -#define MCF_DSPI_DTFR_CS5 (0x00200000) -#define MCF_DSPI_DTFR_CTCNT (0x04000000) -#define MCF_DSPI_DTFR_EOQ (0x08000000) -#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) -#define MCF_DSPI_DTFR_CONT (0x80000000) - -/* Bit definitions and macros for MCF_DSPI_DRFR */ -#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_DSPI_DTFDRn */ -#define MCF_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_DSPI_DRFDRn */ -#define MCF_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0) - -#endif /* __MCF548X_DSPI_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_eport.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_eport.h deleted file mode 100644 index bb07f7c3b0..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_eport.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Edge Port Module (EPORT) - */ -#ifndef __MCF548X_EPORT_H__ -#define __MCF548X_EPORT_H__ - -/* - * Edge Port Module (EPORT) - */ - -/* Register read/write macros */ -#define MCF_EPORT_EPPAR (*(vuint16_t*)(&__MBAR[0x000F00])) -#define MCF_EPORT_EPDDR (*(vuint8_t *)(&__MBAR[0x000F04])) -#define MCF_EPORT_EPIER (*(vuint8_t *)(&__MBAR[0x000F05])) -#define MCF_EPORT_EPDR (*(vuint8_t *)(&__MBAR[0x000F08])) -#define MCF_EPORT_EPPDR (*(vuint8_t *)(&__MBAR[0x000F09])) -#define MCF_EPORT_EPFR (*(vuint8_t *)(&__MBAR[0x000F0C])) - -/* Bit definitions and macros for MCF_EPORT_EPPAR */ -#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) -#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) -#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) -#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) -#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) -#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) -#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) -#define MCF_EPORT_EPPAR_EPPAx_LEVEL (0) -#define MCF_EPORT_EPPAR_EPPAx_RISING (1) -#define MCF_EPORT_EPPAR_EPPAx_FALLING (2) -#define MCF_EPORT_EPPAR_EPPAx_BOTH (3) - -/* Bit definitions and macros for MCF_EPORT_EPDDR */ -#define MCF_EPORT_EPDDR_EPDD1 (0x02) -#define MCF_EPORT_EPDDR_EPDD2 (0x04) -#define MCF_EPORT_EPDDR_EPDD3 (0x08) -#define MCF_EPORT_EPDDR_EPDD4 (0x10) -#define MCF_EPORT_EPDDR_EPDD5 (0x20) -#define MCF_EPORT_EPDDR_EPDD6 (0x40) -#define MCF_EPORT_EPDDR_EPDD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPIER */ -#define MCF_EPORT_EPIER_EPIE1 (0x02) -#define MCF_EPORT_EPIER_EPIE2 (0x04) -#define MCF_EPORT_EPIER_EPIE3 (0x08) -#define MCF_EPORT_EPIER_EPIE4 (0x10) -#define MCF_EPORT_EPIER_EPIE5 (0x20) -#define MCF_EPORT_EPIER_EPIE6 (0x40) -#define MCF_EPORT_EPIER_EPIE7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPDR */ -#define MCF_EPORT_EPDR_EPD1 (0x02) -#define MCF_EPORT_EPDR_EPD2 (0x04) -#define MCF_EPORT_EPDR_EPD3 (0x08) -#define MCF_EPORT_EPDR_EPD4 (0x10) -#define MCF_EPORT_EPDR_EPD5 (0x20) -#define MCF_EPORT_EPDR_EPD6 (0x40) -#define MCF_EPORT_EPDR_EPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPPDR */ -#define MCF_EPORT_EPPDR_EPPD1 (0x02) -#define MCF_EPORT_EPPDR_EPPD2 (0x04) -#define MCF_EPORT_EPPDR_EPPD3 (0x08) -#define MCF_EPORT_EPPDR_EPPD4 (0x10) -#define MCF_EPORT_EPPDR_EPPD5 (0x20) -#define MCF_EPORT_EPPDR_EPPD6 (0x40) -#define MCF_EPORT_EPPDR_EPPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPFR */ -#define MCF_EPORT_EPFR_EPF1 (0x02) -#define MCF_EPORT_EPFR_EPF2 (0x04) -#define MCF_EPORT_EPFR_EPF3 (0x08) -#define MCF_EPORT_EPFR_EPF4 (0x10) -#define MCF_EPORT_EPFR_EPF5 (0x20) -#define MCF_EPORT_EPFR_EPF6 (0x40) -#define MCF_EPORT_EPFR_EPF7 (0x80) - -#endif /* __MCF548X_EPORT_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_fbcs.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_fbcs.h deleted file mode 100644 index e7e4712bc6..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_fbcs.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * FlexBus Chip Selects (FBCS) - */ -#ifndef __MCF548X_FBCS_H__ -#define __MCF548X_FBCS_H__ - -/* - * FlexBus Chip Selects (FBCS) - */ - -/* Register read/write macros */ -#define MCF_FBCS_CSAR0 (*(vuint32_t*)(&__MBAR[0x000500])) -#define MCF_FBCS_CSMR0 (*(vuint32_t*)(&__MBAR[0x000504])) -#define MCF_FBCS_CSCR0 (*(vuint32_t*)(&__MBAR[0x000508])) -#define MCF_FBCS_CSAR1 (*(vuint32_t*)(&__MBAR[0x00050C])) -#define MCF_FBCS_CSMR1 (*(vuint32_t*)(&__MBAR[0x000510])) -#define MCF_FBCS_CSCR1 (*(vuint32_t*)(&__MBAR[0x000514])) -#define MCF_FBCS_CSAR2 (*(vuint32_t*)(&__MBAR[0x000518])) -#define MCF_FBCS_CSMR2 (*(vuint32_t*)(&__MBAR[0x00051C])) -#define MCF_FBCS_CSCR2 (*(vuint32_t*)(&__MBAR[0x000520])) -#define MCF_FBCS_CSAR3 (*(vuint32_t*)(&__MBAR[0x000524])) -#define MCF_FBCS_CSMR3 (*(vuint32_t*)(&__MBAR[0x000528])) -#define MCF_FBCS_CSCR3 (*(vuint32_t*)(&__MBAR[0x00052C])) -#define MCF_FBCS_CSAR4 (*(vuint32_t*)(&__MBAR[0x000530])) -#define MCF_FBCS_CSMR4 (*(vuint32_t*)(&__MBAR[0x000534])) -#define MCF_FBCS_CSCR4 (*(vuint32_t*)(&__MBAR[0x000538])) -#define MCF_FBCS_CSAR5 (*(vuint32_t*)(&__MBAR[0x00053C])) -#define MCF_FBCS_CSMR5 (*(vuint32_t*)(&__MBAR[0x000540])) -#define MCF_FBCS_CSCR5 (*(vuint32_t*)(&__MBAR[0x000544])) -#define MCF_FBCS_CSAR(x) (*(vuint32_t*)(&__MBAR[0x000500+((x)*0x00C)])) -#define MCF_FBCS_CSMR(x) (*(vuint32_t*)(&__MBAR[0x000504+((x)*0x00C)])) -#define MCF_FBCS_CSCR(x) (*(vuint32_t*)(&__MBAR[0x000508+((x)*0x00C)])) - -/* Bit definitions and macros for MCF_FBCS_CSAR */ -#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) - -/* Bit definitions and macros for MCF_FBCS_CSMR */ -#define MCF_FBCS_CSMR_V (0x00000001) -#define MCF_FBCS_CSMR_WP (0x00000100) -#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) -#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) -#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) -#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) -#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) -#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) -#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) -#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) -#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) -#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) -#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) -#define MCF_FBCS_CSMR_BAM_8M (0x007F0000) -#define MCF_FBCS_CSMR_BAM_4M (0x003F0000) -#define MCF_FBCS_CSMR_BAM_2M (0x001F0000) -#define MCF_FBCS_CSMR_BAM_1M (0x000F0000) -#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) -#define MCF_FBCS_CSMR_BAM_512K (0x00070000) -#define MCF_FBCS_CSMR_BAM_256K (0x00030000) -#define MCF_FBCS_CSMR_BAM_128K (0x00010000) -#define MCF_FBCS_CSMR_BAM_64K (0x00000000) - -/* Bit definitions and macros for MCF_FBCS_CSCR */ -#define MCF_FBCS_CSCR_BSTW (0x00000008) -#define MCF_FBCS_CSCR_BSTR (0x00000010) -#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) -#define MCF_FBCS_CSCR_AA (0x00000100) -#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) -#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) -#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) -#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) -#define MCF_FBCS_CSCR_SWSEN (0x00800000) -#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) -#define MCF_FBCS_CSCR_PS_8 (0x0040) -#define MCF_FBCS_CSCR_PS_16 (0x0080) -#define MCF_FBCS_CSCR_PS_32 (0x0000) - -#endif /* __MCF548X_FBCS_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_fec.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_fec.h deleted file mode 100644 index 29ac249025..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_fec.h +++ /dev/null @@ -1,623 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Fast Ethernet Controller (FEC) - */ -#ifndef __MCF548X_FEC_H__ -#define __MCF548X_FEC_H__ - -/* - * Fast Ethernet Controller (FEC) - */ - -/* Register read/write macros */ -#define MCF_FEC_EIR0 (*(vuint32_t*)(&__MBAR[0x009004])) -#define MCF_FEC_EIMR0 (*(vuint32_t*)(&__MBAR[0x009008])) -#define MCF_FEC_ECR0 (*(vuint32_t*)(&__MBAR[0x009024])) -#define MCF_FEC_MMFR0 (*(vuint32_t*)(&__MBAR[0x009040])) -#define MCF_FEC_MSCR0 (*(vuint32_t*)(&__MBAR[0x009044])) -#define MCF_FEC_MIBC0 (*(vuint32_t*)(&__MBAR[0x009064])) -#define MCF_FEC_RCR0 (*(vuint32_t*)(&__MBAR[0x009084])) -#define MCF_FEC_R_HASH0 (*(vuint32_t*)(&__MBAR[0x009088])) -#define MCF_FEC_TCR0 (*(vuint32_t*)(&__MBAR[0x0090C4])) -#define MCF_FEC_PALR0 (*(vuint32_t*)(&__MBAR[0x0090E4])) -#define MCF_FEC_PAUR0 (*(vuint32_t*)(&__MBAR[0x0090E8])) -#define MCF_FEC_OPD0 (*(vuint32_t*)(&__MBAR[0x0090EC])) -#define MCF_FEC_IAUR0 (*(vuint32_t*)(&__MBAR[0x009118])) -#define MCF_FEC_IALR0 (*(vuint32_t*)(&__MBAR[0x00911C])) -#define MCF_FEC_GAUR0 (*(vuint32_t*)(&__MBAR[0x009120])) -#define MCF_FEC_GALR0 (*(vuint32_t*)(&__MBAR[0x009124])) -#define MCF_FEC_FECTFWR0 (*(vuint32_t*)(&__MBAR[0x009144])) -#define MCF_FEC_FECRFDR0 (*(vuint32_t*)(&__MBAR[0x009184])) -#define MCF_FEC_FECRFSR0 (*(vuint32_t*)(&__MBAR[0x009188])) -#define MCF_FEC_FECRFCR0 (*(vuint32_t*)(&__MBAR[0x00918C])) -#define MCF_FEC_FECRLRFP0 (*(vuint32_t*)(&__MBAR[0x009190])) -#define MCF_FEC_FECRLWFP0 (*(vuint32_t*)(&__MBAR[0x009194])) -#define MCF_FEC_FECRFAR0 (*(vuint32_t*)(&__MBAR[0x009198])) -#define MCF_FEC_FECRFRP0 (*(vuint32_t*)(&__MBAR[0x00919C])) -#define MCF_FEC_FECRFWP0 (*(vuint32_t*)(&__MBAR[0x0091A0])) -#define MCF_FEC_FECTFDR0 (*(vuint32_t*)(&__MBAR[0x0091A4])) -#define MCF_FEC_FECTFSR0 (*(vuint32_t*)(&__MBAR[0x0091A8])) -#define MCF_FEC_FECTFCR0 (*(vuint32_t*)(&__MBAR[0x0091AC])) -#define MCF_FEC_FECTLRFP0 (*(vuint32_t*)(&__MBAR[0x0091B0])) -#define MCF_FEC_FECTLWFP0 (*(vuint32_t*)(&__MBAR[0x0091B4])) -#define MCF_FEC_FECTFAR0 (*(vuint32_t*)(&__MBAR[0x0091B8])) -#define MCF_FEC_FECTFRP0 (*(vuint32_t*)(&__MBAR[0x0091BC])) -#define MCF_FEC_FECTFWP0 (*(vuint32_t*)(&__MBAR[0x0091C0])) -#define MCF_FEC_FRST0 (*(vuint32_t*)(&__MBAR[0x0091C4])) -#define MCF_FEC_CTCWR0 (*(vuint32_t*)(&__MBAR[0x0091C8])) -#define MCF_FEC_RMON_T_DROP0 (*(vuint32_t*)(&__MBAR[0x009200])) -#define MCF_FEC_RMON_T_PACKETS0 (*(vuint32_t*)(&__MBAR[0x009204])) -#define MCF_FEC_RMON_T_BC_PKT0 (*(vuint32_t*)(&__MBAR[0x009208])) -#define MCF_FEC_RMON_T_MC_PKT0 (*(vuint32_t*)(&__MBAR[0x00920C])) -#define MCF_FEC_RMON_T_CRC_ALIGN0 (*(vuint32_t*)(&__MBAR[0x009210])) -#define MCF_FEC_RMON_T_UNDERSIZE0 (*(vuint32_t*)(&__MBAR[0x009214])) -#define MCF_FEC_RMON_T_OVERSIZE0 (*(vuint32_t*)(&__MBAR[0x009218])) -#define MCF_FEC_RMON_T_FRAG0 (*(vuint32_t*)(&__MBAR[0x00921C])) -#define MCF_FEC_RMON_T_JAB0 (*(vuint32_t*)(&__MBAR[0x009220])) -#define MCF_FEC_RMON_T_COL0 (*(vuint32_t*)(&__MBAR[0x009224])) -#define MCF_FEC_RMON_T_P640 (*(vuint32_t*)(&__MBAR[0x009228])) -#define MCF_FEC_RMON_T_P65TO1270 (*(vuint32_t*)(&__MBAR[0x00922C])) -#define MCF_FEC_RMON_T_P128TO2550 (*(vuint32_t*)(&__MBAR[0x009230])) -#define MCF_FEC_RMON_T_P256TO5110 (*(vuint32_t*)(&__MBAR[0x009234])) -#define MCF_FEC_RMON_T_P512TO10230 (*(vuint32_t*)(&__MBAR[0x009238])) -#define MCF_FEC_RMON_T_P1024TO20470 (*(vuint32_t*)(&__MBAR[0x00923C])) -#define MCF_FEC_RMON_T_P_GTE20480 (*(vuint32_t*)(&__MBAR[0x009240])) -#define MCF_FEC_RMON_T_OCTETS0 (*(vuint32_t*)(&__MBAR[0x009244])) -#define MCF_FEC_IEEE_T_DROP0 (*(vuint32_t*)(&__MBAR[0x009248])) -#define MCF_FEC_IEEE_T_FRAME_OK0 (*(vuint32_t*)(&__MBAR[0x00924C])) -#define MCF_FEC_IEEE_T_1COL0 (*(vuint32_t*)(&__MBAR[0x009250])) -#define MCF_FEC_IEEE_T_MCOL0 (*(vuint32_t*)(&__MBAR[0x009254])) -#define MCF_FEC_IEEE_T_DEF0 (*(vuint32_t*)(&__MBAR[0x009258])) -#define MCF_FEC_IEEE_T_LCOL0 (*(vuint32_t*)(&__MBAR[0x00925C])) -#define MCF_FEC_IEEE_T_EXCOL0 (*(vuint32_t*)(&__MBAR[0x009260])) -#define MCF_FEC_IEEE_T_MACERR0 (*(vuint32_t*)(&__MBAR[0x009264])) -#define MCF_FEC_IEEE_T_CSERR0 (*(vuint32_t*)(&__MBAR[0x009268])) -#define MCF_FEC_IEEE_T_SQE0 (*(vuint32_t*)(&__MBAR[0x00926C])) -#define MCF_FEC_IEEE_T_FDXFC0 (*(vuint32_t*)(&__MBAR[0x009270])) -#define MCF_FEC_IEEE_T_OCTETS_OK0 (*(vuint32_t*)(&__MBAR[0x009274])) -#define MCF_FEC_RMON_R_DROP0 (*(vuint32_t*)(&__MBAR[0x009280])) -#define MCF_FEC_RMON_R_PACKETS0 (*(vuint32_t*)(&__MBAR[0x009284])) -#define MCF_FEC_RMON_R_BC_PKT0 (*(vuint32_t*)(&__MBAR[0x009288])) -#define MCF_FEC_RMON_R_MC_PKT0 (*(vuint32_t*)(&__MBAR[0x00928C])) -#define MCF_FEC_RMON_R_CRC_ALIGN0 (*(vuint32_t*)(&__MBAR[0x009290])) -#define MCF_FEC_RMON_R_UNDERSIZE0 (*(vuint32_t*)(&__MBAR[0x009294])) -#define MCF_FEC_RMON_R_OVERSIZE0 (*(vuint32_t*)(&__MBAR[0x009298])) -#define MCF_FEC_RMON_R_FRAG0 (*(vuint32_t*)(&__MBAR[0x00929C])) -#define MCF_FEC_RMON_R_JAB0 (*(vuint32_t*)(&__MBAR[0x0092A0])) -#define MCF_FEC_RMON_R_RESVD_00 (*(vuint32_t*)(&__MBAR[0x0092A4])) -#define MCF_FEC_RMON_R_P640 (*(vuint32_t*)(&__MBAR[0x0092A8])) -#define MCF_FEC_RMON_R_P65TO1270 (*(vuint32_t*)(&__MBAR[0x0092AC])) -#define MCF_FEC_RMON_R_P128TO2550 (*(vuint32_t*)(&__MBAR[0x0092B0])) -#define MCF_FEC_RMON_R_P256TO5110 (*(vuint32_t*)(&__MBAR[0x0092B4])) -#define MCF_FEC_RMON_R_512TO10230 (*(vuint32_t*)(&__MBAR[0x0092B8])) -#define MCF_FEC_RMON_R_1024TO20470 (*(vuint32_t*)(&__MBAR[0x0092BC])) -#define MCF_FEC_RMON_R_P_GTE20480 (*(vuint32_t*)(&__MBAR[0x0092C0])) -#define MCF_FEC_RMON_R_OCTETS0 (*(vuint32_t*)(&__MBAR[0x0092C4])) -#define MCF_FEC_IEEE_R_DROP0 (*(vuint32_t*)(&__MBAR[0x0092C8])) -#define MCF_FEC_IEEE_R_FRAME_OK0 (*(vuint32_t*)(&__MBAR[0x0092CC])) -#define MCF_FEC_IEEE_R_CRC0 (*(vuint32_t*)(&__MBAR[0x0092D0])) -#define MCF_FEC_IEEE_R_ALIGN0 (*(vuint32_t*)(&__MBAR[0x0092D4])) -#define MCF_FEC_IEEE_R_MACERR0 (*(vuint32_t*)(&__MBAR[0x0092D8])) -#define MCF_FEC_IEEE_R_FDXFC0 (*(vuint32_t*)(&__MBAR[0x0092DC])) -#define MCF_FEC_IEEE_R_OCTETS_OK0 (*(vuint32_t*)(&__MBAR[0x0092E0])) -#define MCF_FEC_EIR1 (*(vuint32_t*)(&__MBAR[0x009804])) -#define MCF_FEC_EIMR1 (*(vuint32_t*)(&__MBAR[0x009808])) -#define MCF_FEC_ECR1 (*(vuint32_t*)(&__MBAR[0x009824])) -#define MCF_FEC_MMFR1 (*(vuint32_t*)(&__MBAR[0x009840])) -#define MCF_FEC_MSCR1 (*(vuint32_t*)(&__MBAR[0x009844])) -#define MCF_FEC_MIBC1 (*(vuint32_t*)(&__MBAR[0x009864])) -#define MCF_FEC_RCR1 (*(vuint32_t*)(&__MBAR[0x009884])) -#define MCF_FEC_R_HASH1 (*(vuint32_t*)(&__MBAR[0x009888])) -#define MCF_FEC_TCR1 (*(vuint32_t*)(&__MBAR[0x0098C4])) -#define MCF_FEC_PALR1 (*(vuint32_t*)(&__MBAR[0x0098E4])) -#define MCF_FEC_PAUR1 (*(vuint32_t*)(&__MBAR[0x0098E8])) -#define MCF_FEC_OPD1 (*(vuint32_t*)(&__MBAR[0x0098EC])) -#define MCF_FEC_IAUR1 (*(vuint32_t*)(&__MBAR[0x009918])) -#define MCF_FEC_IALR1 (*(vuint32_t*)(&__MBAR[0x00991C])) -#define MCF_FEC_GAUR1 (*(vuint32_t*)(&__MBAR[0x009920])) -#define MCF_FEC_GALR1 (*(vuint32_t*)(&__MBAR[0x009924])) -#define MCF_FEC_FECTFWR1 (*(vuint32_t*)(&__MBAR[0x009944])) -#define MCF_FEC_FECRFDR1 (*(vuint32_t*)(&__MBAR[0x009984])) -#define MCF_FEC_FECRFSR1 (*(vuint32_t*)(&__MBAR[0x009988])) -#define MCF_FEC_FECRFCR1 (*(vuint32_t*)(&__MBAR[0x00998C])) -#define MCF_FEC_FECRLRFP1 (*(vuint32_t*)(&__MBAR[0x009990])) -#define MCF_FEC_FECRLWFP1 (*(vuint32_t*)(&__MBAR[0x009994])) -#define MCF_FEC_FECRFAR1 (*(vuint32_t*)(&__MBAR[0x009998])) -#define MCF_FEC_FECRFRP1 (*(vuint32_t*)(&__MBAR[0x00999C])) -#define MCF_FEC_FECRFWP1 (*(vuint32_t*)(&__MBAR[0x0099A0])) -#define MCF_FEC_FECTFDR1 (*(vuint32_t*)(&__MBAR[0x0099A4])) -#define MCF_FEC_FECTFSR1 (*(vuint32_t*)(&__MBAR[0x0099A8])) -#define MCF_FEC_FECTFCR1 (*(vuint32_t*)(&__MBAR[0x0099AC])) -#define MCF_FEC_FECTLRFP1 (*(vuint32_t*)(&__MBAR[0x0099B0])) -#define MCF_FEC_FECTLWFP1 (*(vuint32_t*)(&__MBAR[0x0099B4])) -#define MCF_FEC_FECTFAR1 (*(vuint32_t*)(&__MBAR[0x0099B8])) -#define MCF_FEC_FECTFRP1 (*(vuint32_t*)(&__MBAR[0x0099BC])) -#define MCF_FEC_FECTFWP1 (*(vuint32_t*)(&__MBAR[0x0099C0])) -#define MCF_FEC_FRST1 (*(vuint32_t*)(&__MBAR[0x0099C4])) -#define MCF_FEC_CTCWR1 (*(vuint32_t*)(&__MBAR[0x0099C8])) -#define MCF_FEC_RMON_T_DROP1 (*(vuint32_t*)(&__MBAR[0x009A00])) -#define MCF_FEC_RMON_T_PACKETS1 (*(vuint32_t*)(&__MBAR[0x009A04])) -#define MCF_FEC_RMON_T_BC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A08])) -#define MCF_FEC_RMON_T_MC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A0C])) -#define MCF_FEC_RMON_T_CRC_ALIGN1 (*(vuint32_t*)(&__MBAR[0x009A10])) -#define MCF_FEC_RMON_T_UNDERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A14])) -#define MCF_FEC_RMON_T_OVERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A18])) -#define MCF_FEC_RMON_T_FRAG1 (*(vuint32_t*)(&__MBAR[0x009A1C])) -#define MCF_FEC_RMON_T_JAB1 (*(vuint32_t*)(&__MBAR[0x009A20])) -#define MCF_FEC_RMON_T_COL1 (*(vuint32_t*)(&__MBAR[0x009A24])) -#define MCF_FEC_RMON_T_P641 (*(vuint32_t*)(&__MBAR[0x009A28])) -#define MCF_FEC_RMON_T_P65TO1271 (*(vuint32_t*)(&__MBAR[0x009A2C])) -#define MCF_FEC_RMON_T_P128TO2551 (*(vuint32_t*)(&__MBAR[0x009A30])) -#define MCF_FEC_RMON_T_P256TO5111 (*(vuint32_t*)(&__MBAR[0x009A34])) -#define MCF_FEC_RMON_T_P512TO10231 (*(vuint32_t*)(&__MBAR[0x009A38])) -#define MCF_FEC_RMON_T_P1024TO20471 (*(vuint32_t*)(&__MBAR[0x009A3C])) -#define MCF_FEC_RMON_T_P_GTE20481 (*(vuint32_t*)(&__MBAR[0x009A40])) -#define MCF_FEC_RMON_T_OCTETS1 (*(vuint32_t*)(&__MBAR[0x009A44])) -#define MCF_FEC_IEEE_T_DROP1 (*(vuint32_t*)(&__MBAR[0x009A48])) -#define MCF_FEC_IEEE_T_FRAME_OK1 (*(vuint32_t*)(&__MBAR[0x009A4C])) -#define MCF_FEC_IEEE_T_1COL1 (*(vuint32_t*)(&__MBAR[0x009A50])) -#define MCF_FEC_IEEE_T_MCOL1 (*(vuint32_t*)(&__MBAR[0x009A54])) -#define MCF_FEC_IEEE_T_DEF1 (*(vuint32_t*)(&__MBAR[0x009A58])) -#define MCF_FEC_IEEE_T_LCOL1 (*(vuint32_t*)(&__MBAR[0x009A5C])) -#define MCF_FEC_IEEE_T_EXCOL1 (*(vuint32_t*)(&__MBAR[0x009A60])) -#define MCF_FEC_IEEE_T_MACERR1 (*(vuint32_t*)(&__MBAR[0x009A64])) -#define MCF_FEC_IEEE_T_CSERR1 (*(vuint32_t*)(&__MBAR[0x009A68])) -#define MCF_FEC_IEEE_T_SQE1 (*(vuint32_t*)(&__MBAR[0x009A6C])) -#define MCF_FEC_IEEE_T_FDXFC1 (*(vuint32_t*)(&__MBAR[0x009A70])) -#define MCF_FEC_IEEE_T_OCTETS_OK1 (*(vuint32_t*)(&__MBAR[0x009A74])) -#define MCF_FEC_RMON_R_DROP1 (*(vuint32_t*)(&__MBAR[0x009A80])) -#define MCF_FEC_RMON_R_PACKETS1 (*(vuint32_t*)(&__MBAR[0x009A84])) -#define MCF_FEC_RMON_R_BC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A88])) -#define MCF_FEC_RMON_R_MC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A8C])) -#define MCF_FEC_RMON_R_CRC_ALIGN1 (*(vuint32_t*)(&__MBAR[0x009A90])) -#define MCF_FEC_RMON_R_UNDERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A94])) -#define MCF_FEC_RMON_R_OVERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A98])) -#define MCF_FEC_RMON_R_FRAG1 (*(vuint32_t*)(&__MBAR[0x009A9C])) -#define MCF_FEC_RMON_R_JAB1 (*(vuint32_t*)(&__MBAR[0x009AA0])) -#define MCF_FEC_RMON_R_RESVD_01 (*(vuint32_t*)(&__MBAR[0x009AA4])) -#define MCF_FEC_RMON_R_P641 (*(vuint32_t*)(&__MBAR[0x009AA8])) -#define MCF_FEC_RMON_R_P65TO1271 (*(vuint32_t*)(&__MBAR[0x009AAC])) -#define MCF_FEC_RMON_R_P128TO2551 (*(vuint32_t*)(&__MBAR[0x009AB0])) -#define MCF_FEC_RMON_R_P256TO5111 (*(vuint32_t*)(&__MBAR[0x009AB4])) -#define MCF_FEC_RMON_R_512TO10231 (*(vuint32_t*)(&__MBAR[0x009AB8])) -#define MCF_FEC_RMON_R_1024TO20471 (*(vuint32_t*)(&__MBAR[0x009ABC])) -#define MCF_FEC_RMON_R_P_GTE20481 (*(vuint32_t*)(&__MBAR[0x009AC0])) -#define MCF_FEC_RMON_R_OCTETS1 (*(vuint32_t*)(&__MBAR[0x009AC4])) -#define MCF_FEC_IEEE_R_DROP1 (*(vuint32_t*)(&__MBAR[0x009AC8])) -#define MCF_FEC_IEEE_R_FRAME_OK1 (*(vuint32_t*)(&__MBAR[0x009ACC])) -#define MCF_FEC_IEEE_R_CRC1 (*(vuint32_t*)(&__MBAR[0x009AD0])) -#define MCF_FEC_IEEE_R_ALIGN1 (*(vuint32_t*)(&__MBAR[0x009AD4])) -#define MCF_FEC_IEEE_R_MACERR1 (*(vuint32_t*)(&__MBAR[0x009AD8])) -#define MCF_FEC_IEEE_R_FDXFC1 (*(vuint32_t*)(&__MBAR[0x009ADC])) -#define MCF_FEC_IEEE_R_OCTETS_OK1 (*(vuint32_t*)(&__MBAR[0x009AE0])) -#define MCF_FEC_EIR(x) (*(vuint32_t*)(&__MBAR[0x009004+((x)*0x800)])) -#define MCF_FEC_EIMR(x) (*(vuint32_t*)(&__MBAR[0x009008+((x)*0x800)])) -#define MCF_FEC_ECR(x) (*(vuint32_t*)(&__MBAR[0x009024+((x)*0x800)])) -#define MCF_FEC_MMFR(x) (*(vuint32_t*)(&__MBAR[0x009040+((x)*0x800)])) -#define MCF_FEC_MSCR(x) (*(vuint32_t*)(&__MBAR[0x009044+((x)*0x800)])) -#define MCF_FEC_MIBC(x) (*(vuint32_t*)(&__MBAR[0x009064+((x)*0x800)])) -#define MCF_FEC_RCR(x) (*(vuint32_t*)(&__MBAR[0x009084+((x)*0x800)])) -#define MCF_FEC_R_HASH(x) (*(vuint32_t*)(&__MBAR[0x009088+((x)*0x800)])) -#define MCF_FEC_TCR(x) (*(vuint32_t*)(&__MBAR[0x0090C4+((x)*0x800)])) -#define MCF_FEC_PALR(x) (*(vuint32_t*)(&__MBAR[0x0090E4+((x)*0x800)])) -#define MCF_FEC_PAUR(x) (*(vuint32_t*)(&__MBAR[0x0090E8+((x)*0x800)])) -#define MCF_FEC_OPD(x) (*(vuint32_t*)(&__MBAR[0x0090EC+((x)*0x800)])) -#define MCF_FEC_IAUR(x) (*(vuint32_t*)(&__MBAR[0x009118+((x)*0x800)])) -#define MCF_FEC_IALR(x) (*(vuint32_t*)(&__MBAR[0x00911C+((x)*0x800)])) -#define MCF_FEC_GAUR(x) (*(vuint32_t*)(&__MBAR[0x009120+((x)*0x800)])) -#define MCF_FEC_GALR(x) (*(vuint32_t*)(&__MBAR[0x009124+((x)*0x800)])) -#define MCF_FEC_FECTFWR(x) (*(vuint32_t*)(&__MBAR[0x009144+((x)*0x800)])) -#define MCF_FEC_FECRFDR(x) (*(vuint32_t*)(&__MBAR[0x009184+((x)*0x800)])) -#define MCF_FEC_FECRFSR(x) (*(vuint32_t*)(&__MBAR[0x009188+((x)*0x800)])) -#define MCF_FEC_FECRFCR(x) (*(vuint32_t*)(&__MBAR[0x00918C+((x)*0x800)])) -#define MCF_FEC_FECRLRFP(x) (*(vuint32_t*)(&__MBAR[0x009190+((x)*0x800)])) -#define MCF_FEC_FECRLWFP(x) (*(vuint32_t*)(&__MBAR[0x009194+((x)*0x800)])) -#define MCF_FEC_FECRFAR(x) (*(vuint32_t*)(&__MBAR[0x009198+((x)*0x800)])) -#define MCF_FEC_FECRFRP(x) (*(vuint32_t*)(&__MBAR[0x00919C+((x)*0x800)])) -#define MCF_FEC_FECRFWP(x) (*(vuint32_t*)(&__MBAR[0x0091A0+((x)*0x800)])) -#define MCF_FEC_FECTFDR(x) (*(vuint32_t*)(&__MBAR[0x0091A4+((x)*0x800)])) -#define MCF_FEC_FECTFSR(x) (*(vuint32_t*)(&__MBAR[0x0091A8+((x)*0x800)])) -#define MCF_FEC_FECTFCR(x) (*(vuint32_t*)(&__MBAR[0x0091AC+((x)*0x800)])) -#define MCF_FEC_FECTLRFP(x) (*(vuint32_t*)(&__MBAR[0x0091B0+((x)*0x800)])) -#define MCF_FEC_FECTLWFP(x) (*(vuint32_t*)(&__MBAR[0x0091B4+((x)*0x800)])) -#define MCF_FEC_FECTFAR(x) (*(vuint32_t*)(&__MBAR[0x0091B8+((x)*0x800)])) -#define MCF_FEC_FECTFRP(x) (*(vuint32_t*)(&__MBAR[0x0091BC+((x)*0x800)])) -#define MCF_FEC_FECTFWP(x) (*(vuint32_t*)(&__MBAR[0x0091C0+((x)*0x800)])) -#define MCF_FEC_FRST(x) (*(vuint32_t*)(&__MBAR[0x0091C4+((x)*0x800)])) -#define MCF_FEC_CTCWR(x) (*(vuint32_t*)(&__MBAR[0x0091C8+((x)*0x800)])) -#define MCF_FEC_RMON_T_DROP(x) (*(vuint32_t*)(&__MBAR[0x009200+((x)*0x800)])) -#define MCF_FEC_RMON_T_PACKETS(x) (*(vuint32_t*)(&__MBAR[0x009204+((x)*0x800)])) -#define MCF_FEC_RMON_T_BC_PKT(x) (*(vuint32_t*)(&__MBAR[0x009208+((x)*0x800)])) -#define MCF_FEC_RMON_T_MC_PKT(x) (*(vuint32_t*)(&__MBAR[0x00920C+((x)*0x800)])) -#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(vuint32_t*)(&__MBAR[0x009210+((x)*0x800)])) -#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009214+((x)*0x800)])) -#define MCF_FEC_RMON_T_OVERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009218+((x)*0x800)])) -#define MCF_FEC_RMON_T_FRAG(x) (*(vuint32_t*)(&__MBAR[0x00921C+((x)*0x800)])) -#define MCF_FEC_RMON_T_JAB(x) (*(vuint32_t*)(&__MBAR[0x009220+((x)*0x800)])) -#define MCF_FEC_RMON_T_COL(x) (*(vuint32_t*)(&__MBAR[0x009224+((x)*0x800)])) -#define MCF_FEC_RMON_T_P64(x) (*(vuint32_t*)(&__MBAR[0x009228+((x)*0x800)])) -#define MCF_FEC_RMON_T_P65TO127(x) (*(vuint32_t*)(&__MBAR[0x00922C+((x)*0x800)])) -#define MCF_FEC_RMON_T_P128TO255(x) (*(vuint32_t*)(&__MBAR[0x009230+((x)*0x800)])) -#define MCF_FEC_RMON_T_P256TO511(x) (*(vuint32_t*)(&__MBAR[0x009234+((x)*0x800)])) -#define MCF_FEC_RMON_T_P512TO1023(x) (*(vuint32_t*)(&__MBAR[0x009238+((x)*0x800)])) -#define MCF_FEC_RMON_T_P1024TO2047(x) (*(vuint32_t*)(&__MBAR[0x00923C+((x)*0x800)])) -#define MCF_FEC_RMON_T_P_GTE2048(x) (*(vuint32_t*)(&__MBAR[0x009240+((x)*0x800)])) -#define MCF_FEC_RMON_T_OCTETS(x) (*(vuint32_t*)(&__MBAR[0x009244+((x)*0x800)])) -#define MCF_FEC_IEEE_T_DROP(x) (*(vuint32_t*)(&__MBAR[0x009248+((x)*0x800)])) -#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(vuint32_t*)(&__MBAR[0x00924C+((x)*0x800)])) -#define MCF_FEC_IEEE_T_1COL(x) (*(vuint32_t*)(&__MBAR[0x009250+((x)*0x800)])) -#define MCF_FEC_IEEE_T_MCOL(x) (*(vuint32_t*)(&__MBAR[0x009254+((x)*0x800)])) -#define MCF_FEC_IEEE_T_DEF(x) (*(vuint32_t*)(&__MBAR[0x009258+((x)*0x800)])) -#define MCF_FEC_IEEE_T_LCOL(x) (*(vuint32_t*)(&__MBAR[0x00925C+((x)*0x800)])) -#define MCF_FEC_IEEE_T_EXCOL(x) (*(vuint32_t*)(&__MBAR[0x009260+((x)*0x800)])) -#define MCF_FEC_IEEE_T_MACERR(x) (*(vuint32_t*)(&__MBAR[0x009264+((x)*0x800)])) -#define MCF_FEC_IEEE_T_CSERR(x) (*(vuint32_t*)(&__MBAR[0x009268+((x)*0x800)])) -#define MCF_FEC_IEEE_T_SQE(x) (*(vuint32_t*)(&__MBAR[0x00926C+((x)*0x800)])) -#define MCF_FEC_IEEE_T_FDXFC(x) (*(vuint32_t*)(&__MBAR[0x009270+((x)*0x800)])) -#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(vuint32_t*)(&__MBAR[0x009274+((x)*0x800)])) -#define MCF_FEC_RMON_R_DROP(x) (*(vuint32_t*)(&__MBAR[0x009280+((x)*0x800)])) -#define MCF_FEC_RMON_R_PACKETS(x) (*(vuint32_t*)(&__MBAR[0x009284+((x)*0x800)])) -#define MCF_FEC_RMON_R_BC_PKT(x) (*(vuint32_t*)(&__MBAR[0x009288+((x)*0x800)])) -#define MCF_FEC_RMON_R_MC_PKT(x) (*(vuint32_t*)(&__MBAR[0x00928C+((x)*0x800)])) -#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(vuint32_t*)(&__MBAR[0x009290+((x)*0x800)])) -#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009294+((x)*0x800)])) -#define MCF_FEC_RMON_R_OVERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009298+((x)*0x800)])) -#define MCF_FEC_RMON_R_FRAG(x) (*(vuint32_t*)(&__MBAR[0x00929C+((x)*0x800)])) -#define MCF_FEC_RMON_R_JAB(x) (*(vuint32_t*)(&__MBAR[0x0092A0+((x)*0x800)])) -#define MCF_FEC_RMON_R_RESVD_0(x) (*(vuint32_t*)(&__MBAR[0x0092A4+((x)*0x800)])) -#define MCF_FEC_RMON_R_P64(x) (*(vuint32_t*)(&__MBAR[0x0092A8+((x)*0x800)])) -#define MCF_FEC_RMON_R_P65TO127(x) (*(vuint32_t*)(&__MBAR[0x0092AC+((x)*0x800)])) -#define MCF_FEC_RMON_R_P128TO255(x) (*(vuint32_t*)(&__MBAR[0x0092B0+((x)*0x800)])) -#define MCF_FEC_RMON_R_P256TO511(x) (*(vuint32_t*)(&__MBAR[0x0092B4+((x)*0x800)])) -#define MCF_FEC_RMON_R_512TO1023(x) (*(vuint32_t*)(&__MBAR[0x0092B8+((x)*0x800)])) -#define MCF_FEC_RMON_R_1024TO2047(x) (*(vuint32_t*)(&__MBAR[0x0092BC+((x)*0x800)])) -#define MCF_FEC_RMON_R_P_GTE2048(x) (*(vuint32_t*)(&__MBAR[0x0092C0+((x)*0x800)])) -#define MCF_FEC_RMON_R_OCTETS(x) (*(vuint32_t*)(&__MBAR[0x0092C4+((x)*0x800)])) -#define MCF_FEC_IEEE_R_DROP(x) (*(vuint32_t*)(&__MBAR[0x0092C8+((x)*0x800)])) -#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(vuint32_t*)(&__MBAR[0x0092CC+((x)*0x800)])) -#define MCF_FEC_IEEE_R_CRC(x) (*(vuint32_t*)(&__MBAR[0x0092D0+((x)*0x800)])) -#define MCF_FEC_IEEE_R_ALIGN(x) (*(vuint32_t*)(&__MBAR[0x0092D4+((x)*0x800)])) -#define MCF_FEC_IEEE_R_MACERR(x) (*(vuint32_t*)(&__MBAR[0x0092D8+((x)*0x800)])) -#define MCF_FEC_IEEE_R_FDXFC(x) (*(vuint32_t*)(&__MBAR[0x0092DC+((x)*0x800)])) -#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(vuint32_t*)(&__MBAR[0x0092E0+((x)*0x800)])) - -/* Bit definitions and macros for MCF_FEC_EIR */ -#define MCF_FEC_EIR_RFERR (0x00020000) -#define MCF_FEC_EIR_XFERR (0x00040000) -#define MCF_FEC_EIR_XFUN (0x00080000) -#define MCF_FEC_EIR_RL (0x00100000) -#define MCF_FEC_EIR_LC (0x00200000) -#define MCF_FEC_EIR_MII (0x00800000) -#define MCF_FEC_EIR_TXF (0x08000000) -#define MCF_FEC_EIR_GRA (0x10000000) -#define MCF_FEC_EIR_BABT (0x20000000) -#define MCF_FEC_EIR_BABR (0x40000000) -#define MCF_FEC_EIR_HBERR (0x80000000) -#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) - -/* Bit definitions and macros for MCF_FEC_EIMR */ -#define MCF_FEC_EIMR_RFERR (0x00020000) -#define MCF_FEC_EIMR_XFERR (0x00040000) -#define MCF_FEC_EIMR_XFUN (0x00080000) -#define MCF_FEC_EIMR_RL (0x00100000) -#define MCF_FEC_EIMR_LC (0x00200000) -#define MCF_FEC_EIMR_MII (0x00800000) -#define MCF_FEC_EIMR_TXF (0x08000000) -#define MCF_FEC_EIMR_GRA (0x10000000) -#define MCF_FEC_EIMR_BABT (0x20000000) -#define MCF_FEC_EIMR_BABR (0x40000000) -#define MCF_FEC_EIMR_HBERR (0x80000000) -#define MCF_FEC_EIMR_MASK_ALL (0x00000000) -#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) - -/* Bit definitions and macros for MCF_FEC_ECR */ -#define MCF_FEC_ECR_RESET (0x00000001) -#define MCF_FEC_ECR_ETHER_EN (0x00000002) - -/* Bit definitions and macros for MCF_FEC_MMFR */ -#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) -#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) -#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) -#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) -#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) -#define MCF_FEC_MMFR_ST_01 (0x40000000) -#define MCF_FEC_MMFR_OP_READ (0x20000000) -#define MCF_FEC_MMFR_OP_WRITE (0x10000000) -#define MCF_FEC_MMFR_TA_10 (0x00020000) - -/* Bit definitions and macros for MCF_FEC_MSCR */ -#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) -#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) -#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<1) -#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<1) -#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<1) -#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<1) - -/* Bit definitions and macros for MCF_FEC_MIBC */ -#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) -#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) - -/* Bit definitions and macros for MCF_FEC_RCR */ -#define MCF_FEC_RCR_LOOP (0x00000001) -#define MCF_FEC_RCR_DRT (0x00000002) -#define MCF_FEC_RCR_MII_MODE (0x00000004) -#define MCF_FEC_RCR_PROM (0x00000008) -#define MCF_FEC_RCR_BC_REJ (0x00000010) -#define MCF_FEC_RCR_FCE (0x00000020) -#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) - -/* Bit definitions and macros for MCF_FEC_R_HASH */ -#define MCF_FEC_R_HASH_HASH(x) (((x)&0x0000003F)<<24) -#define MCF_FEC_R_HASH_MULTCAST (0x40000000) -#define MCF_FEC_R_HASH_FCE_DC (0x80000000) - -/* Bit definitions and macros for MCF_FEC_TCR */ -#define MCF_FEC_TCR_GTS (0x00000001) -#define MCF_FEC_TCR_HBC (0x00000002) -#define MCF_FEC_TCR_FDEN (0x00000004) -#define MCF_FEC_TCR_TFC_PAUSE (0x00000008) -#define MCF_FEC_TCR_RFC_PAUSE (0x00000010) - -/* Bit definitions and macros for MCF_FEC_PAUR */ -#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_OPD */ -#define MCF_FEC_OPD_OP_PAUSE(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_FECTFWR */ -#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0x0000000F)<<0) -#define MCF_FEC_FECTFWR_X_WMRK_64 (0x00000000) -#define MCF_FEC_FECTFWR_X_WMRK_128 (0x00000001) -#define MCF_FEC_FECTFWR_X_WMRK_192 (0x00000002) -#define MCF_FEC_FECTFWR_X_WMRK_256 (0x00000003) -#define MCF_FEC_FECTFWR_X_WMRK_320 (0x00000004) -#define MCF_FEC_FECTFWR_X_WMRK_384 (0x00000005) -#define MCF_FEC_FECTFWR_X_WMRK_448 (0x00000006) -#define MCF_FEC_FECTFWR_X_WMRK_512 (0x00000007) -#define MCF_FEC_FECTFWR_X_WMRK_576 (0x00000008) -#define MCF_FEC_FECTFWR_X_WMRK_640 (0x00000009) -#define MCF_FEC_FECTFWR_X_WMRK_704 (0x0000000A) -#define MCF_FEC_FECTFWR_X_WMRK_768 (0x0000000B) -#define MCF_FEC_FECTFWR_X_WMRK_832 (0x0000000C) -#define MCF_FEC_FECTFWR_X_WMRK_896 (0x0000000D) -#define MCF_FEC_FECTFWR_X_WMRK_960 (0x0000000E) -#define MCF_FEC_FECTFWR_X_WMRK_1024 (0x0000000F) - -/* Bit definitions and macros for MCF_FEC_FECRFDR */ -#define MCF_FEC_FECRFDR_ADDR0 ((void*)(&__MBAR[0x009184])) -#define MCF_FEC_FECRFDR_ADDR1 ((void*)(&__MBAR[0x009984])) -#define MCF_FEC_FECRFDR_ADDR(x) ((void*)(&__MBAR[0x009184+(0x800*ch)])) - -/* Bit definitions and macros for MCF_FEC_FECRFSR */ -#define MCF_FEC_FECRFSR_EMT (0x00010000) -#define MCF_FEC_FECRFSR_ALARM (0x00020000) -#define MCF_FEC_FECRFSR_FU (0x00040000) -#define MCF_FEC_FECRFSR_FR (0x00080000) -#define MCF_FEC_FECRFSR_OF (0x00100000) -#define MCF_FEC_FECRFSR_UF (0x00200000) -#define MCF_FEC_FECRFSR_RXW (0x00400000) -#define MCF_FEC_FECRFSR_FAE (0x00800000) -#define MCF_FEC_FECRFSR_FRM(x) (((x)&0x0000000F)<<24) -#define MCF_FEC_FECRFSR_IP (0x80000000) - -/* Bit definitions and macros for MCF_FEC_FECRFCR */ -#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_FECRFCR_OF_MSK (0x00080000) -#define MCF_FEC_FECRFCR_UF_MSK (0x00100000) -#define MCF_FEC_FECRFCR_RXW_MSK (0x00200000) -#define MCF_FEC_FECRFCR_FAE_MSK (0x00400000) -#define MCF_FEC_FECRFCR_IP_MSK (0x00800000) -#define MCF_FEC_FECRFCR_GR(x) (((x)&0x00000007)<<24) -#define MCF_FEC_FECRFCR_FRM (0x08000000) -#define MCF_FEC_FECRFCR_TIMER (0x10000000) -#define MCF_FEC_FECRFCR_WFR (0x20000000) -#define MCF_FEC_FECRFCR_WCTL (0x40000000) - -/* Bit definitions and macros for MCF_FEC_FECRLRFP */ -#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECRLWFP */ -#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECRFAR */ -#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECRFRP */ -#define MCF_FEC_FECRFRP_READ(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECRFWP */ -#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECTFDR */ -#define MCF_FEC_FECTFDR_TFCW_TC (0x04000000) -#define MCF_FEC_FECTFDR_TFCW_ABC (0x02000000) -#define MCF_FEC_FECTFDR_ADDR0 ((void*)(&__MBAR[0x0091A4])) -#define MCF_FEC_FECTFDR_ADDR1 ((void*)(&__MBAR[0x0099A4])) -#define MCF_FEC_FECTFDR_ADDR(x) ((void*)(&__MBAR[0x0091A4+(0x800*ch)])) - -/* Bit definitions and macros for MCF_FEC_FECTFSR */ -#define MCF_FEC_FECTFSR_EMT (0x00010000) -#define MCF_FEC_FECTFSR_ALARM (0x00020000) -#define MCF_FEC_FECTFSR_FU (0x00040000) -#define MCF_FEC_FECTFSR_FR (0x00080000) -#define MCF_FEC_FECTFSR_OF (0x00100000) -#define MCF_FEC_FECTFSR_UP (0x00200000) -#define MCF_FEC_FECTFSR_FAE (0x00800000) -#define MCF_FEC_FECTFSR_FRM(x) (((x)&0x0000000F)<<24) -#define MCF_FEC_FECTFSR_TXW (0x40000000) -#define MCF_FEC_FECTFSR_IP (0x80000000) - -/* Bit definitions and macros for MCF_FEC_FECTFCR */ -#define MCF_FEC_FECTFCR_RESERVED (0x00200000) -#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0x0000FFFF)<<0|0x00200000) -#define MCF_FEC_FECTFCR_TXW_MSK (0x00240000) -#define MCF_FEC_FECTFCR_OF_MSK (0x00280000) -#define MCF_FEC_FECTFCR_UF_MSK (0x00300000) -#define MCF_FEC_FECTFCR_FAE_MSK (0x00600000) -#define MCF_FEC_FECTFCR_IP_MSK (0x00A00000) -#define MCF_FEC_FECTFCR_GR(x) (((x)&0x00000007)<<24|0x00200000) -#define MCF_FEC_FECTFCR_FRM (0x08200000) -#define MCF_FEC_FECTFCR_TIMER (0x10200000) -#define MCF_FEC_FECTFCR_WFR (0x20200000) -#define MCF_FEC_FECTFCR_WCTL (0x40200000) - -/* Bit definitions and macros for MCF_FEC_FECTLRFP */ -#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECTLWFP */ -#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECTFAR */ -#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECTFRP */ -#define MCF_FEC_FECTFRP_READ(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECTFWP */ -#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FRST */ -#define MCF_FEC_FRST_RST_CTL (0x01000000) -#define MCF_FEC_FRST_SW_RST (0x02000000) - -/* Bit definitions and macros for MCF_FEC_CTCWR */ -#define MCF_FEC_CTCWR_TFCW (0x01000000) -#define MCF_FEC_CTCWR_CRC (0x02000000) - - -struct mcf54xx_fec -{ - vuint32_t RES0; - vuint32_t eir; // 004 - vuint32_t eimr; // 008 - vuint32_t RES1[6]; - vuint32_t ecr; // 024 - vuint32_t RES2[6]; - vuint32_t mmfr; // 040 - vuint32_t mscr; // 044 - vuint32_t RES3[7]; - vuint32_t mibc; // 064 - vuint32_t RES4[7]; - vuint32_t rcr; // 084 - vuint32_t r_hash; // 088 - vuint32_t RES5[14]; - vuint32_t tcr; // 0c4 - vuint32_t RES6[7]; - vuint32_t palr; // 0e4 - vuint32_t paur; // 0e8 - vuint32_t opd; // 0ec - vuint32_t RES7[10]; - vuint32_t iaur; // 118 - vuint32_t ialr; // 11c - vuint32_t gaur; // 120 - vuint32_t galr; // 124 - vuint32_t RES8[7]; - vuint32_t fectfwr; // 144 - vuint32_t RES8a[15]; - vuint32_t fecrfdr; // 184 - vuint32_t fecrfsr; // 188 - vuint32_t fecrfcr; // 18c - vuint32_t fecrlrfp; // 190 - vuint32_t fecrlwfp; // 194 - vuint32_t fecrfar; // 198 - vuint32_t fecrfrp; // 19c - vuint32_t fecrfwp; // 1a0 - vuint32_t fectfdr; // 1a4 - vuint32_t fectfsr; // 1a8 - vuint32_t fectfcr; // 1ac - vuint32_t fectlrfp; // 1b0 - vuint32_t fectlwfp; // 1b4 - vuint32_t fectfar; // 1b8 - vuint32_t fectfrp; // 1bc - vuint32_t fectfwp; // 1c0 - vuint32_t frst; // 1c4 - vuint32_t ctcwr; // 1c8 - vuint32_t RES9[13]; - - /* MIB Counters Memory Map */ - vuint32_t rmon_t_drop; // 200 - vuint32_t rmon_t_packets; // 204 - vuint32_t rmon_t_bc_pkt; // 208 - vuint32_t rmon_t_mc_pkt; // 20C - vuint32_t rmon_t_crc_align; // 210 - vuint32_t rmon_t_undersize; // 214 - vuint32_t rmon_t_oversize; // 218 - vuint32_t rmon_t_frag; // 21C - vuint32_t rmon_t_jab; // 220 - vuint32_t rmon_t_col; // 224 - vuint32_t rmon_t_p64; // 228 - vuint32_t rmon_t_p65to127; // 22C - vuint32_t rmon_t_p128to255; // 230 - vuint32_t rmon_t_p256to511; // 234 - vuint32_t rmon_t_p512to1023; // 238 - vuint32_t rmon_t_p1024to2047; // 23C - vuint32_t rmon_t_p_gte2048; // 240 - vuint32_t rmon_t_octets; // 244 - vuint32_t ieee_t_drop; // 248 - vuint32_t ieee_t_frame_ok; // 24C - vuint32_t ieee_t_1col; // 250 - vuint32_t ieee_t_mcol; // 254 - vuint32_t ieee_t_def; // 258 - vuint32_t ieee_t_lcol; // 25C - vuint32_t ieee_t_excol; // 260 - vuint32_t ieee_t_macerr; // 264 - vuint32_t ieee_t_cserr; // 268 - vuint32_t ieee_t_sqe; // 26C - vuint32_t ieee_t_fdxfc; // 270 - vuint32_t ieee_t_octets_ok; // 274 - vuint32_t RES10[2]; - - vuint32_t rmon_r_drop; // 280 - vuint32_t rmon_r_packets; // 284 - vuint32_t rmon_r_bc_pkt; // 288 - vuint32_t rmon_r_mc_pkt; // 28C - vuint32_t rmon_r_crc_align; // 290 - vuint32_t rmon_r_undersize; // 294 - vuint32_t rmon_r_oversize; // 298 - vuint32_t rmon_r_frag; // 29C - vuint32_t rmon_r_jab; // 2A0 - vuint32_t rmon_r_resvd_0; // 2A4 - vuint32_t rmon_r_p64; // 2A8 - vuint32_t rmon_r_p65to127; // 2AC - vuint32_t rmon_r_p128to255; // 2B0 - vuint32_t rmon_r_p256to511; // 2B4 - vuint32_t rmon_r_512to1023; // 2B8 - vuint32_t rmon_r_1024to2047; // 2BC - vuint32_t rmon_r_p_gte2048; // 2C0 - vuint32_t rmon_r_octets; // 2C4 - vuint32_t ieee_r_drop; // 2C8 - vuint32_t ieee_r_frame_ok; // 2CC - vuint32_t ieee_r_crc; // 2D0 - vuint32_t ieee_r_align; // 2D4 - vuint32_t ieee_r_macerr; // 2D8 - vuint32_t ieee_r_fdxfc; // 2DC - vuint32_t ieee_r_octets_ok; // 2e0 -}; - -#define MCF_FEC_ADDR(ch) ((void*)(&__MBAR[0x009000+(0x800*ch)])) -#define MCF_FEC_SIZE(ch) ((uint32_t)(0x800)) - -#endif /* __MCF548X_FEC_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_gpio.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_gpio.h deleted file mode 100644 index 5d494a9d49..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_gpio.h +++ /dev/null @@ -1,708 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * General Purpose I/O (GPIO) - */ -#ifndef __MCF548X_GPIO_H__ -#define __MCF548X_GPIO_H__ - -/* - * General Purpose I/O (GPIO) - */ - -/* Register read/write macros */ -#define MCF_GPIO_PODR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A00])) -#define MCF_GPIO_PODR_FBCS (*(vuint8_t *)(&__MBAR[0x000A01])) -#define MCF_GPIO_PODR_DMA (*(vuint8_t *)(&__MBAR[0x000A02])) -#define MCF_GPIO_PODR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A04])) -#define MCF_GPIO_PODR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A05])) -#define MCF_GPIO_PODR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A06])) -#define MCF_GPIO_PODR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A07])) -#define MCF_GPIO_PODR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A08])) -#define MCF_GPIO_PODR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A09])) -#define MCF_GPIO_PODR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A0A])) -#define MCF_GPIO_PODR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A0C])) -#define MCF_GPIO_PODR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A0D])) -#define MCF_GPIO_PODR_DSPI (*(vuint8_t *)(&__MBAR[0x000A0E])) -#define MCF_GPIO_PDDR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A10])) -#define MCF_GPIO_PDDR_FBCS (*(vuint8_t *)(&__MBAR[0x000A11])) -#define MCF_GPIO_PDDR_DMA (*(vuint8_t *)(&__MBAR[0x000A12])) -#define MCF_GPIO_PDDR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A14])) -#define MCF_GPIO_PDDR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A15])) -#define MCF_GPIO_PDDR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A16])) -#define MCF_GPIO_PDDR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A17])) -#define MCF_GPIO_PDDR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A18])) -#define MCF_GPIO_PDDR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A19])) -#define MCF_GPIO_PDDR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A1A])) -#define MCF_GPIO_PDDR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A1C])) -#define MCF_GPIO_PDDR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A1D])) -#define MCF_GPIO_PDDR_DSPI (*(vuint8_t *)(&__MBAR[0x000A1E])) -#define MCF_GPIO_PPDSDR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A20])) -#define MCF_GPIO_PPDSDR_FBCS (*(vuint8_t *)(&__MBAR[0x000A21])) -#define MCF_GPIO_PPDSDR_DMA (*(vuint8_t *)(&__MBAR[0x000A22])) -#define MCF_GPIO_PPDSDR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A24])) -#define MCF_GPIO_PPDSDR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A25])) -#define MCF_GPIO_PPDSDR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A26])) -#define MCF_GPIO_PPDSDR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A27])) -#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A28])) -#define MCF_GPIO_PPDSDR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A29])) -#define MCF_GPIO_PPDSDR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A2A])) -#define MCF_GPIO_PPDSDR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A2C])) -#define MCF_GPIO_PPDSDR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A2D])) -#define MCF_GPIO_PPDSDR_DSPI (*(vuint8_t *)(&__MBAR[0x000A2E])) -#define MCF_GPIO_PCLRR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A30])) -#define MCF_GPIO_PCLRR_FBCS (*(vuint8_t *)(&__MBAR[0x000A31])) -#define MCF_GPIO_PCLRR_DMA (*(vuint8_t *)(&__MBAR[0x000A32])) -#define MCF_GPIO_PCLRR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A34])) -#define MCF_GPIO_PCLRR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A35])) -#define MCF_GPIO_PCLRR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A36])) -#define MCF_GPIO_PCLRR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A37])) -#define MCF_GPIO_PCLRR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A38])) -#define MCF_GPIO_PCLRR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A39])) -#define MCF_GPIO_PCLRR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A3A])) -#define MCF_GPIO_PCLRR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A3C])) -#define MCF_GPIO_PCLRR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A3D])) -#define MCF_GPIO_PCLRR_DSPI (*(vuint8_t *)(&__MBAR[0x000A3E])) -#define MCF_GPIO_PAR_FBCTL (*(vuint16_t*)(&__MBAR[0x000A40])) -#define MCF_GPIO_PAR_FBCS (*(vuint8_t *)(&__MBAR[0x000A42])) -#define MCF_GPIO_PAR_DMA (*(vuint8_t *)(&__MBAR[0x000A43])) -#define MCF_GPIO_PAR_FECI2CIRQ (*(vuint16_t*)(&__MBAR[0x000A44])) -#define MCF_GPIO_PAR_PCIBG (*(vuint16_t*)(&__MBAR[0x000A48])) -#define MCF_GPIO_PAR_PCIBR (*(vuint16_t*)(&__MBAR[0x000A4A])) -#define MCF_GPIO_PAR_PSC3 (*(vuint8_t *)(&__MBAR[0x000A4C])) -#define MCF_GPIO_PAR_PSC2 (*(vuint8_t *)(&__MBAR[0x000A4D])) -#define MCF_GPIO_PAR_PSC1 (*(vuint8_t *)(&__MBAR[0x000A4E])) -#define MCF_GPIO_PAR_PSC0 (*(vuint8_t *)(&__MBAR[0x000A4F])) -#define MCF_GPIO_PAR_DSPI (*(vuint16_t*)(&__MBAR[0x000A50])) -#define MCF_GPIO_PAR_TIMER (*(vuint8_t *)(&__MBAR[0x000A52])) - -/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x01) -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x02) -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x04) -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x08) -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10) -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20) -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40) -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ -#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x02) -#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x04) -#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x08) -#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10) -#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ -#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x01) -#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x02) -#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x04) -#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x01) -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x02) -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x04) -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x08) -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10) -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20) -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40) -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x01) -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x02) -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x04) -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x08) -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10) -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20) -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40) -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x01) -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x02) -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x04) -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x08) -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10) -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20) -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40) -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x01) -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x02) -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x04) -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x08) -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10) -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20) -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40) -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ -#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x01) -#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x02) -#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x04) -#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x08) -#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ -#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x01) -#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x02) -#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x04) -#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x08) -#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC2 */ -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC20 (0x01) -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC21 (0x02) -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC22 (0x04) -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC23 (0x08) -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC24 (0x10) -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC25 (0x20) -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC26 (0x40) -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC0 */ -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC00 (0x01) -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC01 (0x02) -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC02 (0x04) -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC03 (0x08) -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC04 (0x10) -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC05 (0x20) -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC06 (0x40) -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ -#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x01) -#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x02) -#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x04) -#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x08) -#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10) -#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20) -#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x01) -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x02) -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x04) -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x08) -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10) -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20) -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40) -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ -#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x02) -#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x04) -#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x08) -#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10) -#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ -#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x01) -#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x02) -#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x04) -#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x01) -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x02) -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x04) -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x08) -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10) -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20) -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40) -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x01) -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x02) -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x04) -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x08) -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10) -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20) -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40) -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x01) -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x02) -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x04) -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x08) -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10) -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20) -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40) -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x01) -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x02) -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x04) -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x08) -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10) -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20) -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40) -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ -#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x01) -#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x02) -#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x04) -#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x08) -#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ -#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x01) -#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x02) -#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x04) -#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x08) -#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC2 */ -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC20 (0x01) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC21 (0x02) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC22 (0x04) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC23 (0x08) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC26 (0x40) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC0 */ -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC00 (0x01) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC02 (0x04) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC04 (0x10) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC05 (0x20) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC06 (0x40) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ -#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x01) -#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x02) -#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x04) -#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x08) -#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10) -#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20) -#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x01) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x02) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x04) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x08) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ -#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x02) -#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x04) -#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x08) -#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10) -#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ -#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x01) -#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x02) -#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x04) -#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x01) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x02) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x04) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x08) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x01) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x02) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x04) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x08) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x01) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x02) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x04) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x08) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x01) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x02) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x04) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x08) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x01) -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x02) -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x04) -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x08) -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x01) -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x02) -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x04) -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x08) -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC2 */ -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC20 (0x01) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC21 (0x02) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC22 (0x04) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC23 (0x08) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC26 (0x40) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC0 */ -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC00 (0x01) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC02 (0x04) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC04 (0x10) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC05 (0x20) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC06 (0x40) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ -#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x01) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x02) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x04) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x08) -#define MCF_GPIO_PPDSDR_DSPI_PDDR_DSPI4 (0x10) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x01) -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x02) -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x04) -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x08) -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10) -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20) -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40) -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ -#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x02) -#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x04) -#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x08) -#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10) -#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ -#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x01) -#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x02) -#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x04) -#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x01) -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x02) -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x04) -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x08) -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10) -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20) -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40) -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ -#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x01) -#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L1 (0x02) -#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x04) -#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x08) -#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L4 (0x10) -#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L5 (0x20) -#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L6 (0x40) -#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ -#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x01) -#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x02) -#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x04) -#define MCF_GPIO_PCLRR_FEC1H_PODR_FEC1H3 (0x08) -#define MCF_GPIO_PCLRR_FEC1H_PODR_FEC1H4 (0x10) -#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20) -#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40) -#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ -#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x01) -#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x02) -#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x04) -#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x08) -#define MCF_GPIO_PCLRR_FEC1L_PODR_FEC1L4 (0x10) -#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20) -#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40) -#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) -#define MCF_GPIO_PCLRR_FECI2C_PODR_FECI2C2 (0x04) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ -#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG0 (0x01) -#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG1 (0x02) -#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG2 (0x04) -#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x08) -#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ -#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x01) -#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x02) -#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x04) -#define MCF_GPIO_PCLRR_PCIBR_PODR_PCIBR3 (0x08) -#define MCF_GPIO_PCLRR_PCIBR_PODR_PCIBR4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC2 */ -#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC20 (0x01) -#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC21 (0x02) -#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC22 (0x04) -#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC23 (0x08) -#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC24 (0x10) -#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC25 (0x20) -#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC26 (0x40) -#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC0 */ -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC00 (0x01) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC01 (0x02) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC02 (0x04) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC03 (0x08) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC04 (0x10) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC05 (0x20) -#define MCF_GPIO_PCLRR_PSC1PSC0_PODR_PSC1PSC06 (0x40) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ -#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x01) -#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x02) -#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x04) -#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x08) -#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10) -#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20) -#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40) - -/* Bit definitions and macros for MCF_GPIO_PAR_FBCTL */ -#define MCF_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_FBCTL_PAR_TA (0x0004) -#define MCF_GPIO_PAR_FBCTL_PAR_RWB(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_FBCTL_PAR_OE (0x0040) -#define MCF_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100) -#define MCF_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400) -#define MCF_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000) -#define MCF_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000) -#define MCF_GPIO_PAR_FBCTL_PAR_TS_GPIO (0) -#define MCF_GPIO_PAR_FBCTL_PAR_TS_TBST (2) -#define MCF_GPIO_PAR_FBCTL_PAR_TS_TS (3) -#define MCF_GPIO_PAR_FBCTL_PAR_RWB_GPIO (0x0000) -#define MCF_GPIO_PAR_FBCTL_PAR_RWB_TBST (0x0020) -#define MCF_GPIO_PAR_FBCTL_PAR_RWB_RWB (0x0030) - -/* Bit definitions and macros for MCF_GPIO_PAR_FBCS */ -#define MCF_GPIO_PAR_FBCS_PAR_CS1 (0x02) -#define MCF_GPIO_PAR_FBCS_PAR_CS2 (0x04) -#define MCF_GPIO_PAR_FBCS_PAR_CS3 (0x08) -#define MCF_GPIO_PAR_FBCS_PAR_CS4 (0x10) -#define MCF_GPIO_PAR_FBCS_PAR_CS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PAR_DMA */ -#define MCF_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_DMA_PAR_DACKx_GPIO (0) -#define MCF_GPIO_PAR_DMA_PAR_DACKx_TOUT (2) -#define MCF_GPIO_PAR_DMA_PAR_DACKx_DACK (3) -#define MCF_GPIO_PAR_DMA_PAR_DREQx_GPIO (0) -#define MCF_GPIO_PAR_DMA_PAR_DREQx_TIN (2) -#define MCF_GPIO_PAR_DMA_PAR_DREQx_DREQ (3) - -/* Bit definitions and macros for MCF_GPIO_PAR_FECI2CIRQ */ -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0) - -/* Bit definitions and macros for MCF_GPIO_PAR_PCIBG */ -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8) - -/* Bit definitions and macros for MCF_GPIO_PAR_PCIBR */ -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8) - -/* Bit definitions and macros for MCF_GPIO_PAR_PSC3 */ -#define MCF_GPIO_PAR_PSC3_PAR_TXD3 (0x04) -#define MCF_GPIO_PAR_PSC3_PAR_RXD3 (0x08) -#define MCF_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00) -#define MCF_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80) -#define MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0) -#define MCF_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00) -#define MCF_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20) -#define MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30) -#define MCF_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40) - -/* Bit definitions and macros for MCF_GPIO_PAR_PSC2 */ -#define MCF_GPIO_PAR_PSC2_PAR_TXD2 (0x04) -#define MCF_GPIO_PAR_PSC2_PAR_RXD2 (0x08) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00) -#define MCF_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80) -#define MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30) - -/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */ -#define MCF_GPIO_PAR_PSC1_PAR_TXD1 (0x04) -#define MCF_GPIO_PAR_PSC1_PAR_RXD1 (0x08) -#define MCF_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00) -#define MCF_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80) -#define MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0) -#define MCF_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00) -#define MCF_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20) -#define MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30) - -/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */ -#define MCF_GPIO_PAR_PSC0_PAR_TXD0 (0x04) -#define MCF_GPIO_PAR_PSC0_PAR_RXD0 (0x08) -#define MCF_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00) -#define MCF_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80) -#define MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0) -#define MCF_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00) -#define MCF_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20) -#define MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30) - -/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */ -#define MCF_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_DSPI_PAR_CS5 (0x1000) -#define MCF_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400) -#define MCF_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800) -#define MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00) -#define MCF_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100) -#define MCF_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200) -#define MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300) -#define MCF_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040) -#define MCF_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080) -#define MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0) -#define MCF_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010) -#define MCF_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020) -#define MCF_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030) -#define MCF_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008) -#define MCF_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C) -#define MCF_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002) -#define MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003) - -/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ -#define MCF_GPIO_PAR_TIMER_PAR_TOUT2 (0x01) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1) -#define MCF_GPIO_PAR_TIMER_PAR_TOUT3 (0x08) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06) - -#endif /* __MCF548X_GPIO_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_gpt.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_gpt.h deleted file mode 100644 index b7fcfced99..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_gpt.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * General Purpose Timers (GPT) - */ -#ifndef __MCF548X_GPT_H__ -#define __MCF548X_GPT_H__ - -/* - * General Purpose Timers (GPT) - */ - -/* Register read/write macros */ -#define MCF_GPT_GMS0 (*(vuint32_t*)(&__MBAR[0x000800])) -#define MCF_GPT_GCIR0 (*(vuint32_t*)(&__MBAR[0x000804])) -#define MCF_GPT_GPWM0 (*(vuint32_t*)(&__MBAR[0x000808])) -#define MCF_GPT_GSR0 (*(vuint32_t*)(&__MBAR[0x00080C])) -#define MCF_GPT_GMS1 (*(vuint32_t*)(&__MBAR[0x000810])) -#define MCF_GPT_GCIR1 (*(vuint32_t*)(&__MBAR[0x000814])) -#define MCF_GPT_GPWM1 (*(vuint32_t*)(&__MBAR[0x000818])) -#define MCF_GPT_GSR1 (*(vuint32_t*)(&__MBAR[0x00081C])) -#define MCF_GPT_GMS2 (*(vuint32_t*)(&__MBAR[0x000820])) -#define MCF_GPT_GCIR2 (*(vuint32_t*)(&__MBAR[0x000824])) -#define MCF_GPT_GPWM2 (*(vuint32_t*)(&__MBAR[0x000828])) -#define MCF_GPT_GSR2 (*(vuint32_t*)(&__MBAR[0x00082C])) -#define MCF_GPT_GMS3 (*(vuint32_t*)(&__MBAR[0x000830])) -#define MCF_GPT_GCIR3 (*(vuint32_t*)(&__MBAR[0x000834])) -#define MCF_GPT_GPWM3 (*(vuint32_t*)(&__MBAR[0x000838])) -#define MCF_GPT_GSR3 (*(vuint32_t*)(&__MBAR[0x00083C])) -#define MCF_GPT_GMS(x) (*(vuint32_t*)(&__MBAR[0x000800+((x)*0x010)])) -#define MCF_GPT_GCIR(x) (*(vuint32_t*)(&__MBAR[0x000804+((x)*0x010)])) -#define MCF_GPT_GPWM(x) (*(vuint32_t*)(&__MBAR[0x000808+((x)*0x010)])) -#define MCF_GPT_GSR(x) (*(vuint32_t*)(&__MBAR[0x00080C+((x)*0x010)])) - -/* Bit definitions and macros for MCF_GPT_GMS */ -#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) -#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) -#define MCF_GPT_GMS_IEN (0x00000100) -#define MCF_GPT_GMS_OD (0x00000200) -#define MCF_GPT_GMS_SC (0x00000400) -#define MCF_GPT_GMS_CE (0x00001000) -#define MCF_GPT_GMS_WDEN (0x00008000) -#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) -#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) -#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) -#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000) -#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000) -#define MCF_GPT_GMS_OCT_PULSELO (0x00200000) -#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000) -#define MCF_GPT_GMS_ICT_ANY (0x00000000) -#define MCF_GPT_GMS_ICT_RISE (0x00010000) -#define MCF_GPT_GMS_ICT_FALL (0x00020000) -#define MCF_GPT_GMS_ICT_PULSE (0x00030000) -#define MCF_GPT_GMS_GPIO_INPUT (0x00000000) -#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020) -#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030) -#define MCF_GPT_GMS_TMS_DISABLE (0x00000000) -#define MCF_GPT_GMS_TMS_INCAPT (0x00000001) -#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002) -#define MCF_GPT_GMS_TMS_PWM (0x00000003) -#define MCF_GPT_GMS_TMS_GPIO (0x00000004) - -/* Bit definitions and macros for MCF_GPT_GCIR */ -#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) -#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_GPT_GPWM */ -#define MCF_GPT_GPWM_LOAD (0x00000001) -#define MCF_GPT_GPWM_PWMOP (0x00000100) -#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_GPT_GSR */ -#define MCF_GPT_GSR_CAPT (0x00000001) -#define MCF_GPT_GSR_COMP (0x00000002) -#define MCF_GPT_GSR_PWMP (0x00000004) -#define MCF_GPT_GSR_TEXP (0x00000008) -#define MCF_GPT_GSR_PIN (0x00000100) -#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) -#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) - -#endif /* __MCF548X_GPT_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_i2c.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_i2c.h deleted file mode 100644 index 3879c0dbb4..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_i2c.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * I2C Module (I2C) - */ -#ifndef __MCF548X_I2C_H__ -#define __MCF548X_I2C_H__ - -/* - * I2C Module (I2C) - */ - -/* Register read/write macros */ -#define MCF_I2C_I2AR (*(vuint8_t *)(&__MBAR[0x008F00])) -#define MCF_I2C_I2FDR (*(vuint8_t *)(&__MBAR[0x008F04])) -#define MCF_I2C_I2CR (*(vuint8_t *)(&__MBAR[0x008F08])) -#define MCF_I2C_I2SR (*(vuint8_t *)(&__MBAR[0x008F0C])) -#define MCF_I2C_I2DR (*(vuint8_t *)(&__MBAR[0x008F10])) -#define MCF_I2C_I2ICR (*(vuint8_t *)(&__MBAR[0x008F20])) - -/* Bit definitions and macros for MCF_I2C_I2AR */ -#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_I2C_I2FDR */ -#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) - -/* Bit definitions and macros for MCF_I2C_I2CR */ -#define MCF_I2C_I2CR_RSTA (0x04) -#define MCF_I2C_I2CR_TXAK (0x08) -#define MCF_I2C_I2CR_MTX (0x10) -#define MCF_I2C_I2CR_MSTA (0x20) -#define MCF_I2C_I2CR_IIEN (0x40) -#define MCF_I2C_I2CR_IEN (0x80) - -/* Bit definitions and macros for MCF_I2C_I2SR */ -#define MCF_I2C_I2SR_RXAK (0x01) -#define MCF_I2C_I2SR_IIF (0x02) -#define MCF_I2C_I2SR_SRW (0x04) -#define MCF_I2C_I2SR_IAL (0x10) -#define MCF_I2C_I2SR_IBB (0x20) -#define MCF_I2C_I2SR_IAAS (0x40) -#define MCF_I2C_I2SR_ICF (0x80) - -/* Bit definitions and macros for MCF_I2C_I2ICR */ -#define MCF_I2C_I2ICR_IE (0x01) -#define MCF_I2C_I2ICR_RE (0x02) -#define MCF_I2C_I2ICR_TE (0x04) -#define MCF_I2C_I2ICR_BNBE (0x08) - -#endif /* __MCF548X_I2C_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_intc.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_intc.h deleted file mode 100644 index 52bf7452fa..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_intc.h +++ /dev/null @@ -1,329 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Interrupt Controller (INTC) - */ -#ifndef __MCF548X_INTC_H__ -#define __MCF548X_INTC_H__ - -/* - * Interrupt Controller (INTC) - */ - -/* Register read/write macros */ -#define MCF_INTC_IPRH (*(vuint32_t*)(&__MBAR[0x000700])) -#define MCF_INTC_IPRL (*(vuint32_t*)(&__MBAR[0x000704])) -#define MCF_INTC_IMRH (*(vuint32_t*)(&__MBAR[0x000708])) -#define MCF_INTC_IMRL (*(vuint32_t*)(&__MBAR[0x00070C])) -#define MCF_INTC_INTFRCH (*(vuint32_t*)(&__MBAR[0x000710])) -#define MCF_INTC_INTFRCL (*(vuint32_t*)(&__MBAR[0x000714])) -#define MCF_INTC_IRLR (*(vuint8_t *)(&__MBAR[0x000718])) -#define MCF_INTC_IACKLPR (*(vuint8_t *)(&__MBAR[0x000719])) -#define MCF_INTC_ICR0 (*(vuint8_t *)(&__MBAR[0x000740])) -#define MCF_INTC_ICR1 (*(vuint8_t *)(&__MBAR[0x000741])) -#define MCF_INTC_ICR2 (*(vuint8_t *)(&__MBAR[0x000742])) -#define MCF_INTC_ICR3 (*(vuint8_t *)(&__MBAR[0x000743])) -#define MCF_INTC_ICR4 (*(vuint8_t *)(&__MBAR[0x000744])) -#define MCF_INTC_ICR5 (*(vuint8_t *)(&__MBAR[0x000745])) -#define MCF_INTC_ICR6 (*(vuint8_t *)(&__MBAR[0x000746])) -#define MCF_INTC_ICR7 (*(vuint8_t *)(&__MBAR[0x000747])) -#define MCF_INTC_ICR8 (*(vuint8_t *)(&__MBAR[0x000748])) -#define MCF_INTC_ICR9 (*(vuint8_t *)(&__MBAR[0x000749])) -#define MCF_INTC_ICR10 (*(vuint8_t *)(&__MBAR[0x00074A])) -#define MCF_INTC_ICR11 (*(vuint8_t *)(&__MBAR[0x00074B])) -#define MCF_INTC_ICR12 (*(vuint8_t *)(&__MBAR[0x00074C])) -#define MCF_INTC_ICR13 (*(vuint8_t *)(&__MBAR[0x00074D])) -#define MCF_INTC_ICR14 (*(vuint8_t *)(&__MBAR[0x00074E])) -#define MCF_INTC_ICR15 (*(vuint8_t *)(&__MBAR[0x00074F])) -#define MCF_INTC_ICR16 (*(vuint8_t *)(&__MBAR[0x000750])) -#define MCF_INTC_ICR17 (*(vuint8_t *)(&__MBAR[0x000751])) -#define MCF_INTC_ICR18 (*(vuint8_t *)(&__MBAR[0x000752])) -#define MCF_INTC_ICR19 (*(vuint8_t *)(&__MBAR[0x000753])) -#define MCF_INTC_ICR20 (*(vuint8_t *)(&__MBAR[0x000754])) -#define MCF_INTC_ICR21 (*(vuint8_t *)(&__MBAR[0x000755])) -#define MCF_INTC_ICR22 (*(vuint8_t *)(&__MBAR[0x000756])) -#define MCF_INTC_ICR23 (*(vuint8_t *)(&__MBAR[0x000757])) -#define MCF_INTC_ICR24 (*(vuint8_t *)(&__MBAR[0x000758])) -#define MCF_INTC_ICR25 (*(vuint8_t *)(&__MBAR[0x000759])) -#define MCF_INTC_ICR26 (*(vuint8_t *)(&__MBAR[0x00075A])) -#define MCF_INTC_ICR27 (*(vuint8_t *)(&__MBAR[0x00075B])) -#define MCF_INTC_ICR28 (*(vuint8_t *)(&__MBAR[0x00075C])) -#define MCF_INTC_ICR29 (*(vuint8_t *)(&__MBAR[0x00075D])) -#define MCF_INTC_ICR30 (*(vuint8_t *)(&__MBAR[0x00075E])) -#define MCF_INTC_ICR31 (*(vuint8_t *)(&__MBAR[0x00075F])) -#define MCF_INTC_ICR32 (*(vuint8_t *)(&__MBAR[0x000760])) -#define MCF_INTC_ICR33 (*(vuint8_t *)(&__MBAR[0x000761])) -#define MCF_INTC_ICR34 (*(vuint8_t *)(&__MBAR[0x000762])) -#define MCF_INTC_ICR35 (*(vuint8_t *)(&__MBAR[0x000763])) -#define MCF_INTC_ICR36 (*(vuint8_t *)(&__MBAR[0x000764])) -#define MCF_INTC_ICR37 (*(vuint8_t *)(&__MBAR[0x000765])) -#define MCF_INTC_ICR38 (*(vuint8_t *)(&__MBAR[0x000766])) -#define MCF_INTC_ICR39 (*(vuint8_t *)(&__MBAR[0x000767])) -#define MCF_INTC_ICR40 (*(vuint8_t *)(&__MBAR[0x000768])) -#define MCF_INTC_ICR41 (*(vuint8_t *)(&__MBAR[0x000769])) -#define MCF_INTC_ICR42 (*(vuint8_t *)(&__MBAR[0x00076A])) -#define MCF_INTC_ICR43 (*(vuint8_t *)(&__MBAR[0x00076B])) -#define MCF_INTC_ICR44 (*(vuint8_t *)(&__MBAR[0x00076C])) -#define MCF_INTC_ICR45 (*(vuint8_t *)(&__MBAR[0x00076D])) -#define MCF_INTC_ICR46 (*(vuint8_t *)(&__MBAR[0x00076E])) -#define MCF_INTC_ICR47 (*(vuint8_t *)(&__MBAR[0x00076F])) -#define MCF_INTC_ICR48 (*(vuint8_t *)(&__MBAR[0x000770])) -#define MCF_INTC_ICR49 (*(vuint8_t *)(&__MBAR[0x000771])) -#define MCF_INTC_ICR50 (*(vuint8_t *)(&__MBAR[0x000772])) -#define MCF_INTC_ICR51 (*(vuint8_t *)(&__MBAR[0x000773])) -#define MCF_INTC_ICR52 (*(vuint8_t *)(&__MBAR[0x000774])) -#define MCF_INTC_ICR53 (*(vuint8_t *)(&__MBAR[0x000775])) -#define MCF_INTC_ICR54 (*(vuint8_t *)(&__MBAR[0x000776])) -#define MCF_INTC_ICR55 (*(vuint8_t *)(&__MBAR[0x000777])) -#define MCF_INTC_ICR56 (*(vuint8_t *)(&__MBAR[0x000778])) -#define MCF_INTC_ICR57 (*(vuint8_t *)(&__MBAR[0x000779])) -#define MCF_INTC_ICR58 (*(vuint8_t *)(&__MBAR[0x00077A])) -#define MCF_INTC_ICR59 (*(vuint8_t *)(&__MBAR[0x00077B])) -#define MCF_INTC_ICR60 (*(vuint8_t *)(&__MBAR[0x00077C])) -#define MCF_INTC_ICR61 (*(vuint8_t *)(&__MBAR[0x00077D])) -#define MCF_INTC_ICR62 (*(vuint8_t *)(&__MBAR[0x00077E])) -#define MCF_INTC_ICR63 (*(vuint8_t *)(&__MBAR[0x00077F])) -#define MCF_INTC_ICRn(x) (*(vuint8_t *)(&__MBAR[0x000740+((x)*0x001)])) -#define MCF_INTC_SWIACK (*(vuint8_t *)(&__MBAR[0x0007E0])) -#define MCF_INTC_L1IACK (*(vuint8_t *)(&__MBAR[0x0007E4])) -#define MCF_INTC_L2IACK (*(vuint8_t *)(&__MBAR[0x0007E8])) -#define MCF_INTC_L3IACK (*(vuint8_t *)(&__MBAR[0x0007EC])) -#define MCF_INTC_L4IACK (*(vuint8_t *)(&__MBAR[0x0007F0])) -#define MCF_INTC_L5IACK (*(vuint8_t *)(&__MBAR[0x0007F4])) -#define MCF_INTC_L6IACK (*(vuint8_t *)(&__MBAR[0x0007F8])) -#define MCF_INTC_L7IACK (*(vuint8_t *)(&__MBAR[0x0007FC])) -#define MCF_INTC_LnIACK(x) (*(vuint8_t *)(&__MBAR[0x0007E4+((x)*0x004)])) - -/* Bit definitions and macros for MCF_INTC_IPRH */ -#define MCF_INTC_IPRH_INT32 (0x00000001) -#define MCF_INTC_IPRH_INT33 (0x00000002) -#define MCF_INTC_IPRH_INT34 (0x00000004) -#define MCF_INTC_IPRH_INT35 (0x00000008) -#define MCF_INTC_IPRH_INT36 (0x00000010) -#define MCF_INTC_IPRH_INT37 (0x00000020) -#define MCF_INTC_IPRH_INT38 (0x00000040) -#define MCF_INTC_IPRH_INT39 (0x00000080) -#define MCF_INTC_IPRH_INT40 (0x00000100) -#define MCF_INTC_IPRH_INT41 (0x00000200) -#define MCF_INTC_IPRH_INT42 (0x00000400) -#define MCF_INTC_IPRH_INT43 (0x00000800) -#define MCF_INTC_IPRH_INT44 (0x00001000) -#define MCF_INTC_IPRH_INT45 (0x00002000) -#define MCF_INTC_IPRH_INT46 (0x00004000) -#define MCF_INTC_IPRH_INT47 (0x00008000) -#define MCF_INTC_IPRH_INT48 (0x00010000) -#define MCF_INTC_IPRH_INT49 (0x00020000) -#define MCF_INTC_IPRH_INT50 (0x00040000) -#define MCF_INTC_IPRH_INT51 (0x00080000) -#define MCF_INTC_IPRH_INT52 (0x00100000) -#define MCF_INTC_IPRH_INT53 (0x00200000) -#define MCF_INTC_IPRH_INT54 (0x00400000) -#define MCF_INTC_IPRH_INT55 (0x00800000) -#define MCF_INTC_IPRH_INT56 (0x01000000) -#define MCF_INTC_IPRH_INT57 (0x02000000) -#define MCF_INTC_IPRH_INT58 (0x04000000) -#define MCF_INTC_IPRH_INT59 (0x08000000) -#define MCF_INTC_IPRH_INT60 (0x10000000) -#define MCF_INTC_IPRH_INT61 (0x20000000) -#define MCF_INTC_IPRH_INT62 (0x40000000) -#define MCF_INTC_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IPRL */ -#define MCF_INTC_IPRL_INT1 (0x00000002) -#define MCF_INTC_IPRL_INT2 (0x00000004) -#define MCF_INTC_IPRL_INT3 (0x00000008) -#define MCF_INTC_IPRL_INT4 (0x00000010) -#define MCF_INTC_IPRL_INT5 (0x00000020) -#define MCF_INTC_IPRL_INT6 (0x00000040) -#define MCF_INTC_IPRL_INT7 (0x00000080) -#define MCF_INTC_IPRL_INT8 (0x00000100) -#define MCF_INTC_IPRL_INT9 (0x00000200) -#define MCF_INTC_IPRL_INT10 (0x00000400) -#define MCF_INTC_IPRL_INT11 (0x00000800) -#define MCF_INTC_IPRL_INT12 (0x00001000) -#define MCF_INTC_IPRL_INT13 (0x00002000) -#define MCF_INTC_IPRL_INT14 (0x00004000) -#define MCF_INTC_IPRL_INT15 (0x00008000) -#define MCF_INTC_IPRL_INT16 (0x00010000) -#define MCF_INTC_IPRL_INT17 (0x00020000) -#define MCF_INTC_IPRL_INT18 (0x00040000) -#define MCF_INTC_IPRL_INT19 (0x00080000) -#define MCF_INTC_IPRL_INT20 (0x00100000) -#define MCF_INTC_IPRL_INT21 (0x00200000) -#define MCF_INTC_IPRL_INT22 (0x00400000) -#define MCF_INTC_IPRL_INT23 (0x00800000) -#define MCF_INTC_IPRL_INT24 (0x01000000) -#define MCF_INTC_IPRL_INT25 (0x02000000) -#define MCF_INTC_IPRL_INT26 (0x04000000) -#define MCF_INTC_IPRL_INT27 (0x08000000) -#define MCF_INTC_IPRL_INT28 (0x10000000) -#define MCF_INTC_IPRL_INT29 (0x20000000) -#define MCF_INTC_IPRL_INT30 (0x40000000) -#define MCF_INTC_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IMRH */ -#define MCF_INTC_IMRH_INT_MASK32 (0x00000001) -#define MCF_INTC_IMRH_INT_MASK33 (0x00000002) -#define MCF_INTC_IMRH_INT_MASK34 (0x00000004) -#define MCF_INTC_IMRH_INT_MASK35 (0x00000008) -#define MCF_INTC_IMRH_INT_MASK36 (0x00000010) -#define MCF_INTC_IMRH_INT_MASK37 (0x00000020) -#define MCF_INTC_IMRH_INT_MASK38 (0x00000040) -#define MCF_INTC_IMRH_INT_MASK39 (0x00000080) -#define MCF_INTC_IMRH_INT_MASK40 (0x00000100) -#define MCF_INTC_IMRH_INT_MASK41 (0x00000200) -#define MCF_INTC_IMRH_INT_MASK42 (0x00000400) -#define MCF_INTC_IMRH_INT_MASK43 (0x00000800) -#define MCF_INTC_IMRH_INT_MASK44 (0x00001000) -#define MCF_INTC_IMRH_INT_MASK45 (0x00002000) -#define MCF_INTC_IMRH_INT_MASK46 (0x00004000) -#define MCF_INTC_IMRH_INT_MASK47 (0x00008000) -#define MCF_INTC_IMRH_INT_MASK48 (0x00010000) -#define MCF_INTC_IMRH_INT_MASK49 (0x00020000) -#define MCF_INTC_IMRH_INT_MASK50 (0x00040000) -#define MCF_INTC_IMRH_INT_MASK51 (0x00080000) -#define MCF_INTC_IMRH_INT_MASK52 (0x00100000) -#define MCF_INTC_IMRH_INT_MASK53 (0x00200000) -#define MCF_INTC_IMRH_INT_MASK54 (0x00400000) -#define MCF_INTC_IMRH_INT_MASK55 (0x00800000) -#define MCF_INTC_IMRH_INT_MASK56 (0x01000000) -#define MCF_INTC_IMRH_INT_MASK57 (0x02000000) -#define MCF_INTC_IMRH_INT_MASK58 (0x04000000) -#define MCF_INTC_IMRH_INT_MASK59 (0x08000000) -#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) -#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) -#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) -#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IMRL */ -#define MCF_INTC_IMRL_MASKALL (0x00000001) -#define MCF_INTC_IMRL_INT_MASK1 (0x00000002) -#define MCF_INTC_IMRL_INT_MASK2 (0x00000004) -#define MCF_INTC_IMRL_INT_MASK3 (0x00000008) -#define MCF_INTC_IMRL_INT_MASK4 (0x00000010) -#define MCF_INTC_IMRL_INT_MASK5 (0x00000020) -#define MCF_INTC_IMRL_INT_MASK6 (0x00000040) -#define MCF_INTC_IMRL_INT_MASK7 (0x00000080) -#define MCF_INTC_IMRL_INT_MASK8 (0x00000100) -#define MCF_INTC_IMRL_INT_MASK9 (0x00000200) -#define MCF_INTC_IMRL_INT_MASK10 (0x00000400) -#define MCF_INTC_IMRL_INT_MASK11 (0x00000800) -#define MCF_INTC_IMRL_INT_MASK12 (0x00001000) -#define MCF_INTC_IMRL_INT_MASK13 (0x00002000) -#define MCF_INTC_IMRL_INT_MASK14 (0x00004000) -#define MCF_INTC_IMRL_INT_MASK15 (0x00008000) -#define MCF_INTC_IMRL_INT_MASK16 (0x00010000) -#define MCF_INTC_IMRL_INT_MASK17 (0x00020000) -#define MCF_INTC_IMRL_INT_MASK18 (0x00040000) -#define MCF_INTC_IMRL_INT_MASK19 (0x00080000) -#define MCF_INTC_IMRL_INT_MASK20 (0x00100000) -#define MCF_INTC_IMRL_INT_MASK21 (0x00200000) -#define MCF_INTC_IMRL_INT_MASK22 (0x00400000) -#define MCF_INTC_IMRL_INT_MASK23 (0x00800000) -#define MCF_INTC_IMRL_INT_MASK24 (0x01000000) -#define MCF_INTC_IMRL_INT_MASK25 (0x02000000) -#define MCF_INTC_IMRL_INT_MASK26 (0x04000000) -#define MCF_INTC_IMRL_INT_MASK27 (0x08000000) -#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) -#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) -#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) -#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_INTFRCH */ -#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_INTFRCL */ -#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC_INTFRCL_INT6 (0x00000040) -#define MCF_INTC_INTFRCL_INT7 (0x00000080) -#define MCF_INTC_INTFRCL_INT8 (0x00000100) -#define MCF_INTC_INTFRCL_INT9 (0x00000200) -#define MCF_INTC_INTFRCL_INT10 (0x00000400) -#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC_INTFRCL_INT15 (0x00008000) -#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IRLR */ -#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_INTC_IACKLPR */ -#define MCF_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_INTC_ICRn */ -#define MCF_INTC_ICRn_IP(x) (((x)&0x07)<<0) -#define MCF_INTC_ICRn_IL(x) (((x)&0x07)<<3) - -#endif /* __MCF548X_INTC_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_pci.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_pci.h deleted file mode 100644 index 031e50945e..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_pci.h +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * PCI Bus Controller (PCI) - */ -#ifndef __MCF548X_PCI_H__ -#define __MCF548X_PCI_H__ - -/* - * PCI Bus Controller (PCI) - */ -#define MCF_PCI_HDR_BASE (&__MBAR[0x000B00]) - -/* Register read/write macros */ - -/* type 0 header */ -#define MCF_PCI_PCIIDR (*(vuint32_t*)(&__MBAR[0x000B00])) -#define MCF_PCI_PCISCR (*(vuint32_t*)(&__MBAR[0x000B04])) -#define MCF_PCI_PCICCRIR (*(vuint32_t*)(&__MBAR[0x000B08])) -#define MCF_PCI_PCICR1 (*(vuint32_t*)(&__MBAR[0x000B0C])) -#define MCF_PCI_PCIBAR0 (*(vuint32_t*)(&__MBAR[0x000B10])) -#define MCF_PCI_PCIBAR1 (*(vuint32_t*)(&__MBAR[0x000B14])) -#define MCF_PCI_PCISID (*(vuint32_t*)(&__MBAR[0x000B2c])) -#define MCF_PCI_PCICR2 (*(vuint32_t*)(&__MBAR[0x000B3C])) - -/* Target Controls */ -#define MCF_PCI_PCIGSCR (*(vuint32_t*)(&__MBAR[0x000B60])) -#define MCF_PCI_PCITBATR0 (*(vuint32_t*)(&__MBAR[0x000B64])) -#define MCF_PCI_PCITBATR1 (*(vuint32_t*)(&__MBAR[0x000B68])) -#define MCF_PCI_PCITCR (*(vuint32_t*)(&__MBAR[0x000B6C])) -#define MCF_PCI_PCIIW0BTAR (*(vuint32_t*)(&__MBAR[0x000B70])) -#define MCF_PCI_PCIIW1BTAR (*(vuint32_t*)(&__MBAR[0x000B74])) -#define MCF_PCI_PCIIW2BTAR (*(vuint32_t*)(&__MBAR[0x000B78])) -#define MCF_PCI_PCIIWCR (*(vuint32_t*)(&__MBAR[0x000B80])) -#define MCF_PCI_PCIICR (*(vuint32_t*)(&__MBAR[0x000B84])) -#define MCF_PCI_PCIISR (*(vuint32_t*)(&__MBAR[0x000B88])) -#define MCF_PCI_PCICAR (*(vuint32_t*)(&__MBAR[0x000BF8])) -#define MCF_PCI_PCITPSR (*(vuint32_t*)(&__MBAR[0x008400])) -#define MCF_PCI_PCITSAR (*(vuint32_t*)(&__MBAR[0x008404])) -#define MCF_PCI_PCITTCR (*(vuint32_t*)(&__MBAR[0x008408])) -#define MCF_PCI_PCITER (*(vuint32_t*)(&__MBAR[0x00840C])) -#define MCF_PCI_PCITNAR (*(vuint32_t*)(&__MBAR[0x008410])) -#define MCF_PCI_PCITLWR (*(vuint32_t*)(&__MBAR[0x008414])) -#define MCF_PCI_PCITDCR (*(vuint32_t*)(&__MBAR[0x008418])) -#define MCF_PCI_PCITSR (*(vuint32_t*)(&__MBAR[0x00841C])) -#define MCF_PCI_PCITFDR (*(vuint32_t*)(&__MBAR[0x008440])) -#define MCF_PCI_PCITFSR (*(vuint32_t*)(&__MBAR[0x008444])) -#define MCF_PCI_PCITFCR (*(vuint32_t*)(&__MBAR[0x008448])) -#define MCF_PCI_PCITFAR (*(vuint32_t*)(&__MBAR[0x00844C])) -#define MCF_PCI_PCITFRPR (*(vuint32_t*)(&__MBAR[0x008450])) -#define MCF_PCI_PCITFWPR (*(vuint32_t*)(&__MBAR[0x008454])) -#define MCF_PCI_PCIRPSR (*(vuint32_t*)(&__MBAR[0x008480])) -#define MCF_PCI_PCIRSAR (*(vuint32_t*)(&__MBAR[0x008484])) -#define MCF_PCI_PCIRTCR (*(vuint32_t*)(&__MBAR[0x008488])) -#define MCF_PCI_PCIRER (*(vuint32_t*)(&__MBAR[0x00848C])) -#define MCF_PCI_PCIRNAR (*(vuint32_t*)(&__MBAR[0x008490])) -#define MCF_PCI_PCIRDCR (*(vuint32_t*)(&__MBAR[0x008498])) -#define MCF_PCI_PCIRSR (*(vuint32_t*)(&__MBAR[0x00849C])) -#define MCF_PCI_PCIRFDR (*(vuint32_t*)(&__MBAR[0x0084C0])) -#define MCF_PCI_PCIRFSR (*(vuint32_t*)(&__MBAR[0x0084C4])) -#define MCF_PCI_PCIRFCR (*(vuint32_t*)(&__MBAR[0x0084C8])) -#define MCF_PCI_PCIRFAR (*(vuint32_t*)(&__MBAR[0x0084CC])) -#define MCF_PCI_PCIRFRPR (*(vuint32_t*)(&__MBAR[0x0084D0])) -#define MCF_PCI_PCIRFWPR (*(vuint32_t*)(&__MBAR[0x0084D4])) - - -/* - * Type 0 Config Header Regs - */ - -/* Bit definitions and macros for MCF_PCI_PCIIDR */ -#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0) -#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCI_PCISCR */ -#define MCF_PCI_PCISCR_M (0x00000002) -#define MCF_PCI_PCISCR_B (0x00000004) -#define MCF_PCI_PCISCR_SP (0x00000008) -#define MCF_PCI_PCISCR_MW (0x00000010) -#define MCF_PCI_PCISCR_PER (0x00000040) -#define MCF_PCI_PCISCR_S (0x00000100) -#define MCF_PCI_PCISCR_F (0x00000200) -#define MCF_PCI_PCISCR_C (0x00100000) -#define MCF_PCI_PCISCR_66M (0x00200000) -#define MCF_PCI_PCISCR_R (0x00400000) -#define MCF_PCI_PCISCR_FC (0x00800000) -#define MCF_PCI_PCISCR_DP (0x01000000) -#define MCF_PCI_PCISCR_DT(x) (((x)&0x00000003)<<25) -#define MCF_PCI_PCISCR_TS (0x08000000) -#define MCF_PCI_PCISCR_TR (0x10000000) -#define MCF_PCI_PCISCR_MA (0x20000000) -#define MCF_PCI_PCISCR_SE (0x40000000) -#define MCF_PCI_PCISCR_PE (0x80000000) - -/* Bit definitions and macros for MCF_PCI_PCICCRIR */ -#define MCF_PCI_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0) -#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8) - -/* Bit definitions and macros for MCF_PCI_PCICR1 */ -#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0) -#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8) -#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCICR1_BIST(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCI_PCIBAR0 */ -#define MCF_PCI_PCIBAR0_IO (0x00000001) -#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x00000003)<<1) -#define MCF_PCI_PCIBAR0_PREF (0x00000008) -#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_PCI_PCIBAR1 */ -#define MCF_PCI_PCIBAR1_IO (0x00000001) -#define MCF_PCI_PCIBAR1_PREF (0x00000008) -#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x00000003)<<30) - -/* Bit definitions and macros for MCF_PCI_PCICR2 */ -#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0) -#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8) -#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCI_PCIGSCR */ -#define MCF_PCI_PCIGSCR_PR (0x00000001) -#define MCF_PCI_PCIGSCR_SEE (0x00001000) -#define MCF_PCI_PCIGSCR_PEE (0x00002000) -#define MCF_PCI_PCIGSCR_SE (0x10000000) -#define MCF_PCI_PCIGSCR_PE (0x20000000) - -/* - * Target device controls - */ - -/* Bit definitions and macros for MCF_PCI_PCITBATR0 */ -#define MCF_PCI_PCITBATR0_EN (0x00000001) -#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_PCI_PCITBATR1 */ -#define MCF_PCI_PCITBATR1_EN (0x00000001) -#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30) - -/* Bit definitions and macros for MCF_PCI_PCITCR */ -#define MCF_PCI_PCITCR_P (0x00010000) -#define MCF_PCI_PCITCR_LD (0x01000000) - -/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */ -#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8) -#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */ -#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8) -#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */ -#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8) -#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCI_PCIIWCR */ -#define MCF_PCI_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8) -#define MCF_PCI_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16) -#define MCF_PCI_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24) -#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x01000000) -#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000) -#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000) -#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x09000000) -#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x00010000) -#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000) -#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000) -#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x00090000) -#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x00000100) -#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300) -#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500) -#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x00000900) - -/* Bit definitions and macros for MCF_PCI_PCIICR */ -#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0) -#define MCF_PCI_PCIICR_TAE (0x01000000) -#define MCF_PCI_PCIICR_IAE (0x02000000) -#define MCF_PCI_PCIICR_REE (0x04000000) - -/* Bit definitions and macros for MCF_PCI_PCIISR */ -#define MCF_PCI_PCIISR_TA (0x01000000) -#define MCF_PCI_PCIISR_IA (0x02000000) -#define MCF_PCI_PCIISR_RE (0x04000000) - -/* Bit definitions and macros for MCF_PCI_PCICAR */ -#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x0000003F)<<2) -#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8) -#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11) -#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCICAR_E (0x80000000) - - -/* - * PCI Fifos - */ - -/* Bit definitions and macros for MCF_PCI_PCITPSR */ -#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCI_PCITTCR */ -#define MCF_PCI_PCITTCR_DI (0x00000001) -#define MCF_PCI_PCITTCR_W (0x00000010) -#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8) -#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_PCI_PCITER */ -#define MCF_PCI_PCITER_NE (0x00010000) -#define MCF_PCI_PCITER_IAE (0x00020000) -#define MCF_PCI_PCITER_TAE (0x00040000) -#define MCF_PCI_PCITER_RE (0x00080000) -#define MCF_PCI_PCITER_SE (0x00100000) -#define MCF_PCI_PCITER_FEE (0x00200000) -#define MCF_PCI_PCITER_ME (0x01000000) -#define MCF_PCI_PCITER_BE (0x08000000) -#define MCF_PCI_PCITER_CM (0x10000000) -#define MCF_PCI_PCITER_RF (0x40000000) -#define MCF_PCI_PCITER_RC (0x80000000) - -/* Bit definitions and macros for MCF_PCI_PCITDCR */ -#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) -#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCI_PCITSR */ -#define MCF_PCI_PCITSR_IA (0x00010000) -#define MCF_PCI_PCITSR_TA (0x00020000) -#define MCF_PCI_PCITSR_RE (0x00040000) -#define MCF_PCI_PCITSR_SE (0x00080000) -#define MCF_PCI_PCITSR_FE (0x00100000) -#define MCF_PCI_PCITSR_BE1 (0x00200000) -#define MCF_PCI_PCITSR_BE2 (0x00400000) -#define MCF_PCI_PCITSR_BE3 (0x00800000) -#define MCF_PCI_PCITSR_NT (0x01000000) - -/* Bit definitions and macros for MCF_PCI_PCITFSR */ -#define MCF_PCI_PCITFSR_EMT (0x00010000) -#define MCF_PCI_PCITFSR_ALARM (0x00020000) -#define MCF_PCI_PCITFSR_FU (0x00040000) -#define MCF_PCI_PCITFSR_FR (0x00080000) -#define MCF_PCI_PCITFSR_OF (0x00100000) -#define MCF_PCI_PCITFSR_UF (0x00200000) -#define MCF_PCI_PCITFSR_RXW (0x00400000) - -/* Bit definitions and macros for MCF_PCI_PCITFCR */ -#define MCF_PCI_PCITFCR_OF_MSK (0x00080000) -#define MCF_PCI_PCITFCR_UF_MSK (0x00100000) -#define MCF_PCI_PCITFCR_RXW_MSK (0x00200000) -#define MCF_PCI_PCITFCR_FAE_MSK (0x00400000) -#define MCF_PCI_PCITFCR_IP_MSK (0x00800000) -#define MCF_PCI_PCITFCR_GR(x) (((x)&0x00000007)<<24) - -/* Bit definitions and macros for MCF_PCI_PCITFAR */ -#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0) - -/* Bit definitions and macros for MCF_PCI_PCITFRPR */ -#define MCF_PCI_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_PCI_PCITFWPR */ -#define MCF_PCI_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_PCI_PCIRPSR */ -#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCI_PCIRTCR */ -#define MCF_PCI_PCIRTCR_DI (0x00000001) -#define MCF_PCI_PCIRTCR_W (0x00000010) -#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8) -#define MCF_PCI_PCIRTCR_FB (0x00001000) -#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_PCI_PCIRER */ -#define MCF_PCI_PCIRER_NE (0x00010000) -#define MCF_PCI_PCIRER_IAE (0x00020000) -#define MCF_PCI_PCIRER_TAE (0x00040000) -#define MCF_PCI_PCIRER_RE (0x00080000) -#define MCF_PCI_PCIRER_SE (0x00100000) -#define MCF_PCI_PCIRER_FEE (0x00200000) -#define MCF_PCI_PCIRER_ME (0x01000000) -#define MCF_PCI_PCIRER_BE (0x08000000) -#define MCF_PCI_PCIRER_CM (0x10000000) -#define MCF_PCI_PCIRER_FE (0x20000000) -#define MCF_PCI_PCIRER_RF (0x40000000) -#define MCF_PCI_PCIRER_RC (0x80000000) - -/* Bit definitions and macros for MCF_PCI_PCIRDCR */ -#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) -#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCI_PCIRSR */ -#define MCF_PCI_PCIRSR_IA (0x00010000) -#define MCF_PCI_PCIRSR_TA (0x00020000) -#define MCF_PCI_PCIRSR_RE (0x00040000) -#define MCF_PCI_PCIRSR_SE (0x00080000) -#define MCF_PCI_PCIRSR_FE (0x00100000) -#define MCF_PCI_PCIRSR_BE1 (0x00200000) -#define MCF_PCI_PCIRSR_BE2 (0x00400000) -#define MCF_PCI_PCIRSR_BE3 (0x00800000) -#define MCF_PCI_PCIRSR_NT (0x01000000) - -/* Bit definitions and macros for MCF_PCI_PCIRFSR */ -#define MCF_PCI_PCIRFSR_EMT (0x00010000) -#define MCF_PCI_PCIRFSR_ALARM (0x00020000) -#define MCF_PCI_PCIRFSR_FU (0x00040000) -#define MCF_PCI_PCIRFSR_FR (0x00080000) -#define MCF_PCI_PCIRFSR_OF (0x00100000) -#define MCF_PCI_PCIRFSR_UF (0x00200000) -#define MCF_PCI_PCIRFSR_RXW (0x00400000) - -/* Bit definitions and macros for MCF_PCI_PCIRFCR */ -#define MCF_PCI_PCIRFCR_OF_MSK (0x00080000) -#define MCF_PCI_PCIRFCR_UF_MSK (0x00100000) -#define MCF_PCI_PCIRFCR_RXW_MSK (0x00200000) -#define MCF_PCI_PCIRFCR_FAE_MSK (0x00400000) -#define MCF_PCI_PCIRFCR_IP_MSK (0x00800000) -#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x00000007)<<24) - -/* Bit definitions and macros for MCF_PCI_PCIRFAR */ -#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0) - -/* Bit definitions and macros for MCF_PCI_PCIRFRPR */ -#define MCF_PCI_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_PCI_PCIRFWPR */ -#define MCF_PCI_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0) - -#endif /* __MCF548X_PCI_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_pciarb.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_pciarb.h deleted file mode 100644 index a15554384a..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_pciarb.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * PCI Arbiter Module (PCIARB) - */ -#ifndef __MCF548X_PCIARB_H__ -#define __MCF548X_PCIARB_H__ - -/* - * PCI Arbiter Module (PCIARB) - */ - -/* Register read/write macros */ -#define MCF_PCIARB_PACR (*(vuint32_t*)(&__MBAR[0x000C00])) -#define MCF_PCIARB_PASR (*(vuint32_t*)(&__MBAR[0x000C04])) - -/* Bit definitions and macros for MCF_PCIARB_PACR */ -#define MCF_PCIARB_PACR_INTMPRI (0x00000001) -#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1) -#define MCF_PCIARB_PACR_INTMINTEN (0x00010000) -#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17) -/* Not documented! - * #define MCF_PCIARB_PACR_PKMD (0x40000000) - */ -#define MCF_PCIARB_PACR_DS (0x80000000) - -/* Bit definitions and macros for MCF_PCIARB_PASR */ -#define MCF_PCIARB_PASR_ITLMBK (0x00010000) -#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17) - -#endif /* __MCF548X_PCIARB_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_psc.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_psc.h deleted file mode 100644 index 44f920bcbe..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_psc.h +++ /dev/null @@ -1,486 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Programmable Serial Controller (PSC) - */ -#ifndef __MCF548X_PSC_H__ -#define __MCF548X_PSC_H__ - -/* - * Programmable Serial Controller (PSC) - */ - -/* Register read/write macros */ -#define MCF_PSC_MR0 (*(vuint8_t *)(&__MBAR[0x008600])) -#define MCF_PSC_SR0 (*(vuint16_t*)(&__MBAR[0x008604])) -#define MCF_PSC_CSR0 (*(vuint8_t *)(&__MBAR[0x008604])) -#define MCF_PSC_CR0 (*(vuint8_t *)(&__MBAR[0x008608])) -#define MCF_PSC_RB0 (*(vuint32_t*)(&__MBAR[0x00860C])) -#define MCF_PSC_TB0 (*(vuint32_t*)(&__MBAR[0x00860C])) -#define MCF_PSC_TB_8BIT0 (*(vuint32_t*)(&__MBAR[0x00860C])) -#define MCF_PSC_TB_16BIT0 (*(vuint32_t*)(&__MBAR[0x00860C])) -#define MCF_PSC_TB_AC970 (*(vuint32_t*)(&__MBAR[0x00860C])) -#define MCF_PSC_IPCR0 (*(vuint8_t *)(&__MBAR[0x008610])) -#define MCF_PSC_ACR0 (*(vuint8_t *)(&__MBAR[0x008610])) -#define MCF_PSC_ISR0 (*(vuint16_t*)(&__MBAR[0x008614])) -#define MCF_PSC_IMR0 (*(vuint16_t*)(&__MBAR[0x008614])) -#define MCF_PSC_CTUR0 (*(vuint8_t *)(&__MBAR[0x008618])) -#define MCF_PSC_CTLR0 (*(vuint8_t *)(&__MBAR[0x00861C])) -#define MCF_PSC_IP0 (*(vuint8_t *)(&__MBAR[0x008634])) -#define MCF_PSC_OPSET0 (*(vuint8_t *)(&__MBAR[0x008638])) -#define MCF_PSC_OPRESET0 (*(vuint8_t *)(&__MBAR[0x00863C])) -#define MCF_PSC_SICR0 (*(vuint8_t *)(&__MBAR[0x008640])) -#define MCF_PSC_IRCR10 (*(vuint8_t *)(&__MBAR[0x008644])) -#define MCF_PSC_IRCR20 (*(vuint8_t *)(&__MBAR[0x008648])) -#define MCF_PSC_IRSDR0 (*(vuint8_t *)(&__MBAR[0x00864C])) -#define MCF_PSC_IRMDR0 (*(vuint8_t *)(&__MBAR[0x008650])) -#define MCF_PSC_IRFDR0 (*(vuint8_t *)(&__MBAR[0x008654])) -#define MCF_PSC_RFCNT0 (*(vuint16_t*)(&__MBAR[0x008658])) -#define MCF_PSC_TFCNT0 (*(vuint16_t*)(&__MBAR[0x00865C])) -#define MCF_PSC_RFSR0 (*(vuint16_t*)(&__MBAR[0x008664])) -#define MCF_PSC_TFSR0 (*(vuint16_t*)(&__MBAR[0x008684])) -#define MCF_PSC_RFCR0 (*(vuint32_t*)(&__MBAR[0x008668])) -#define MCF_PSC_TFCR0 (*(vuint32_t*)(&__MBAR[0x008688])) -#define MCF_PSC_RFAR0 (*(vuint16_t*)(&__MBAR[0x00866E])) -#define MCF_PSC_TFAR0 (*(vuint16_t*)(&__MBAR[0x00868E])) -#define MCF_PSC_RFRP0 (*(vuint16_t*)(&__MBAR[0x008672])) -#define MCF_PSC_TFRP0 (*(vuint16_t*)(&__MBAR[0x008692])) -#define MCF_PSC_RFWP0 (*(vuint16_t*)(&__MBAR[0x008676])) -#define MCF_PSC_TFWP0 (*(vuint16_t*)(&__MBAR[0x008696])) -#define MCF_PSC_RLRFP0 (*(vuint16_t*)(&__MBAR[0x00867A])) -#define MCF_PSC_TLRFP0 (*(vuint16_t*)(&__MBAR[0x00869A])) -#define MCF_PSC_RLWFP0 (*(vuint16_t*)(&__MBAR[0x00867E])) -#define MCF_PSC_TLWFP0 (*(vuint16_t*)(&__MBAR[0x00869E])) -#define MCF_PSC_MR1 (*(vuint8_t *)(&__MBAR[0x008700])) -#define MCF_PSC_SR1 (*(vuint16_t*)(&__MBAR[0x008704])) -#define MCF_PSC_CSR1 (*(vuint8_t *)(&__MBAR[0x008704])) -#define MCF_PSC_CR1 (*(vuint8_t *)(&__MBAR[0x008708])) -#define MCF_PSC_RB1 (*(vuint32_t*)(&__MBAR[0x00870C])) -#define MCF_PSC_TB1 (*(vuint32_t*)(&__MBAR[0x00870C])) -#define MCF_PSC_TB_8BIT1 (*(vuint32_t*)(&__MBAR[0x00870C])) -#define MCF_PSC_TB_16BIT1 (*(vuint32_t*)(&__MBAR[0x00870C])) -#define MCF_PSC_TB_AC971 (*(vuint32_t*)(&__MBAR[0x00870C])) -#define MCF_PSC_IPCR1 (*(vuint8_t *)(&__MBAR[0x008710])) -#define MCF_PSC_ACR1 (*(vuint8_t *)(&__MBAR[0x008710])) -#define MCF_PSC_ISR1 (*(vuint16_t*)(&__MBAR[0x008714])) -#define MCF_PSC_IMR1 (*(vuint16_t*)(&__MBAR[0x008714])) -#define MCF_PSC_CTUR1 (*(vuint8_t *)(&__MBAR[0x008718])) -#define MCF_PSC_CTLR1 (*(vuint8_t *)(&__MBAR[0x00871C])) -#define MCF_PSC_IP1 (*(vuint8_t *)(&__MBAR[0x008734])) -#define MCF_PSC_OPSET1 (*(vuint8_t *)(&__MBAR[0x008738])) -#define MCF_PSC_OPRESET1 (*(vuint8_t *)(&__MBAR[0x00873C])) -#define MCF_PSC_SICR1 (*(vuint8_t *)(&__MBAR[0x008740])) -#define MCF_PSC_IRCR11 (*(vuint8_t *)(&__MBAR[0x008744])) -#define MCF_PSC_IRCR21 (*(vuint8_t *)(&__MBAR[0x008748])) -#define MCF_PSC_IRSDR1 (*(vuint8_t *)(&__MBAR[0x00874C])) -#define MCF_PSC_IRMDR1 (*(vuint8_t *)(&__MBAR[0x008750])) -#define MCF_PSC_IRFDR1 (*(vuint8_t *)(&__MBAR[0x008754])) -#define MCF_PSC_RFCNT1 (*(vuint16_t*)(&__MBAR[0x008758])) -#define MCF_PSC_TFCNT1 (*(vuint16_t*)(&__MBAR[0x00875C])) -#define MCF_PSC_RFSR1 (*(vuint16_t*)(&__MBAR[0x008764])) -#define MCF_PSC_TFSR1 (*(vuint16_t*)(&__MBAR[0x008784])) -#define MCF_PSC_RFCR1 (*(vuint32_t*)(&__MBAR[0x008768])) -#define MCF_PSC_TFCR1 (*(vuint32_t*)(&__MBAR[0x008788])) -#define MCF_PSC_RFAR1 (*(vuint16_t*)(&__MBAR[0x00876E])) -#define MCF_PSC_TFAR1 (*(vuint16_t*)(&__MBAR[0x00878E])) -#define MCF_PSC_RFRP1 (*(vuint16_t*)(&__MBAR[0x008772])) -#define MCF_PSC_TFRP1 (*(vuint16_t*)(&__MBAR[0x008792])) -#define MCF_PSC_RFWP1 (*(vuint16_t*)(&__MBAR[0x008776])) -#define MCF_PSC_TFWP1 (*(vuint16_t*)(&__MBAR[0x008796])) -#define MCF_PSC_RLRFP1 (*(vuint16_t*)(&__MBAR[0x00877A])) -#define MCF_PSC_TLRFP1 (*(vuint16_t*)(&__MBAR[0x00879A])) -#define MCF_PSC_RLWFP1 (*(vuint16_t*)(&__MBAR[0x00877E])) -#define MCF_PSC_TLWFP1 (*(vuint16_t*)(&__MBAR[0x00879E])) -#define MCF_PSC_MR2 (*(vuint8_t *)(&__MBAR[0x008800])) -#define MCF_PSC_SR2 (*(vuint16_t*)(&__MBAR[0x008804])) -#define MCF_PSC_CSR2 (*(vuint8_t *)(&__MBAR[0x008804])) -#define MCF_PSC_CR2 (*(vuint8_t *)(&__MBAR[0x008808])) -#define MCF_PSC_RB2 (*(vuint32_t*)(&__MBAR[0x00880C])) -#define MCF_PSC_TB2 (*(vuint32_t*)(&__MBAR[0x00880C])) -#define MCF_PSC_TB_8BIT2 (*(vuint32_t*)(&__MBAR[0x00880C])) -#define MCF_PSC_TB_16BIT2 (*(vuint32_t*)(&__MBAR[0x00880C])) -#define MCF_PSC_TB_AC972 (*(vuint32_t*)(&__MBAR[0x00880C])) -#define MCF_PSC_IPCR2 (*(vuint8_t *)(&__MBAR[0x008810])) -#define MCF_PSC_ACR2 (*(vuint8_t *)(&__MBAR[0x008810])) -#define MCF_PSC_ISR2 (*(vuint16_t*)(&__MBAR[0x008814])) -#define MCF_PSC_IMR2 (*(vuint16_t*)(&__MBAR[0x008814])) -#define MCF_PSC_CTUR2 (*(vuint8_t *)(&__MBAR[0x008818])) -#define MCF_PSC_CTLR2 (*(vuint8_t *)(&__MBAR[0x00881C])) -#define MCF_PSC_IP2 (*(vuint8_t *)(&__MBAR[0x008834])) -#define MCF_PSC_OPSET2 (*(vuint8_t *)(&__MBAR[0x008838])) -#define MCF_PSC_OPRESET2 (*(vuint8_t *)(&__MBAR[0x00883C])) -#define MCF_PSC_SICR2 (*(vuint8_t *)(&__MBAR[0x008840])) -#define MCF_PSC_IRCR12 (*(vuint8_t *)(&__MBAR[0x008844])) -#define MCF_PSC_IRCR22 (*(vuint8_t *)(&__MBAR[0x008848])) -#define MCF_PSC_IRSDR2 (*(vuint8_t *)(&__MBAR[0x00884C])) -#define MCF_PSC_IRMDR2 (*(vuint8_t *)(&__MBAR[0x008850])) -#define MCF_PSC_IRFDR2 (*(vuint8_t *)(&__MBAR[0x008854])) -#define MCF_PSC_RFCNT2 (*(vuint16_t*)(&__MBAR[0x008858])) -#define MCF_PSC_TFCNT2 (*(vuint16_t*)(&__MBAR[0x00885C])) -#define MCF_PSC_RFSR2 (*(vuint16_t*)(&__MBAR[0x008864])) -#define MCF_PSC_TFSR2 (*(vuint16_t*)(&__MBAR[0x008884])) -#define MCF_PSC_RFCR2 (*(vuint32_t*)(&__MBAR[0x008868])) -#define MCF_PSC_TFCR2 (*(vuint32_t*)(&__MBAR[0x008888])) -#define MCF_PSC_RFAR2 (*(vuint16_t*)(&__MBAR[0x00886E])) -#define MCF_PSC_TFAR2 (*(vuint16_t*)(&__MBAR[0x00888E])) -#define MCF_PSC_RFRP2 (*(vuint16_t*)(&__MBAR[0x008872])) -#define MCF_PSC_TFRP2 (*(vuint16_t*)(&__MBAR[0x008892])) -#define MCF_PSC_RFWP2 (*(vuint16_t*)(&__MBAR[0x008876])) -#define MCF_PSC_TFWP2 (*(vuint16_t*)(&__MBAR[0x008896])) -#define MCF_PSC_RLRFP2 (*(vuint16_t*)(&__MBAR[0x00887A])) -#define MCF_PSC_TLRFP2 (*(vuint16_t*)(&__MBAR[0x00889A])) -#define MCF_PSC_RLWFP2 (*(vuint16_t*)(&__MBAR[0x00887E])) -#define MCF_PSC_TLWFP2 (*(vuint16_t*)(&__MBAR[0x00889E])) -#define MCF_PSC_MR3 (*(vuint8_t *)(&__MBAR[0x008900])) -#define MCF_PSC_SR3 (*(vuint16_t*)(&__MBAR[0x008904])) -#define MCF_PSC_CSR3 (*(vuint8_t *)(&__MBAR[0x008904])) -#define MCF_PSC_CR3 (*(vuint8_t *)(&__MBAR[0x008908])) -#define MCF_PSC_RB3 (*(vuint32_t*)(&__MBAR[0x00890C])) -#define MCF_PSC_TB3 (*(vuint32_t*)(&__MBAR[0x00890C])) -#define MCF_PSC_TB_8BIT3 (*(vuint32_t*)(&__MBAR[0x00890C])) -#define MCF_PSC_TB_16BIT3 (*(vuint32_t*)(&__MBAR[0x00890C])) -#define MCF_PSC_TB_AC973 (*(vuint32_t*)(&__MBAR[0x00890C])) -#define MCF_PSC_IPCR3 (*(vuint8_t *)(&__MBAR[0x008910])) -#define MCF_PSC_ACR3 (*(vuint8_t *)(&__MBAR[0x008910])) -#define MCF_PSC_ISR3 (*(vuint16_t*)(&__MBAR[0x008914])) -#define MCF_PSC_IMR3 (*(vuint16_t*)(&__MBAR[0x008914])) -#define MCF_PSC_CTUR3 (*(vuint8_t *)(&__MBAR[0x008918])) -#define MCF_PSC_CTLR3 (*(vuint8_t *)(&__MBAR[0x00891C])) -#define MCF_PSC_IP3 (*(vuint8_t *)(&__MBAR[0x008934])) -#define MCF_PSC_OPSET3 (*(vuint8_t *)(&__MBAR[0x008938])) -#define MCF_PSC_OPRESET3 (*(vuint8_t *)(&__MBAR[0x00893C])) -#define MCF_PSC_SICR3 (*(vuint8_t *)(&__MBAR[0x008940])) -#define MCF_PSC_IRCR13 (*(vuint8_t *)(&__MBAR[0x008944])) -#define MCF_PSC_IRCR23 (*(vuint8_t *)(&__MBAR[0x008948])) -#define MCF_PSC_IRSDR3 (*(vuint8_t *)(&__MBAR[0x00894C])) -#define MCF_PSC_IRMDR3 (*(vuint8_t *)(&__MBAR[0x008950])) -#define MCF_PSC_IRFDR3 (*(vuint8_t *)(&__MBAR[0x008954])) -#define MCF_PSC_RFCNT3 (*(vuint16_t*)(&__MBAR[0x008958])) -#define MCF_PSC_TFCNT3 (*(vuint16_t*)(&__MBAR[0x00895C])) -#define MCF_PSC_RFSR3 (*(vuint16_t*)(&__MBAR[0x008964])) -#define MCF_PSC_TFSR3 (*(vuint16_t*)(&__MBAR[0x008984])) -#define MCF_PSC_RFCR3 (*(vuint32_t*)(&__MBAR[0x008968])) -#define MCF_PSC_TFCR3 (*(vuint32_t*)(&__MBAR[0x008988])) -#define MCF_PSC_RFAR3 (*(vuint16_t*)(&__MBAR[0x00896E])) -#define MCF_PSC_TFAR3 (*(vuint16_t*)(&__MBAR[0x00898E])) -#define MCF_PSC_RFRP3 (*(vuint16_t*)(&__MBAR[0x008972])) -#define MCF_PSC_TFRP3 (*(vuint16_t*)(&__MBAR[0x008992])) -#define MCF_PSC_RFWP3 (*(vuint16_t*)(&__MBAR[0x008976])) -#define MCF_PSC_TFWP3 (*(vuint16_t*)(&__MBAR[0x008996])) -#define MCF_PSC_RLRFP3 (*(vuint16_t*)(&__MBAR[0x00897A])) -#define MCF_PSC_TLRFP3 (*(vuint16_t*)(&__MBAR[0x00899A])) -#define MCF_PSC_RLWFP3 (*(vuint16_t*)(&__MBAR[0x00897E])) -#define MCF_PSC_TLWFP3 (*(vuint16_t*)(&__MBAR[0x00899E])) -#define MCF_PSC_MR(x) (*(vuint8_t *)(&__MBAR[0x008600+((x)*0x100)])) -#define MCF_PSC_SR(x) (*(vuint16_t*)(&__MBAR[0x008604+((x)*0x100)])) -#define MCF_PSC_CSR(x) (*(vuint8_t *)(&__MBAR[0x008604+((x)*0x100)])) -#define MCF_PSC_CR(x) (*(vuint8_t *)(&__MBAR[0x008608+((x)*0x100)])) -#define MCF_PSC_RB(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) -#define MCF_PSC_TB(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) -#define MCF_PSC_TB_8BIT(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) -#define MCF_PSC_TB_16BIT(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) -#define MCF_PSC_TB_AC97(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) -#define MCF_PSC_IPCR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)])) -#define MCF_PSC_ACR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)])) -#define MCF_PSC_ISR(x) (*(vuint16_t*)(&__MBAR[0x008614+((x)*0x100)])) -#define MCF_PSC_IMR(x) (*(vuint16_t*)(&__MBAR[0x008614+((x)*0x100)])) -#define MCF_PSC_CTUR(x) (*(vuint8_t *)(&__MBAR[0x008618+((x)*0x100)])) -#define MCF_PSC_CTLR(x) (*(vuint8_t *)(&__MBAR[0x00861C+((x)*0x100)])) -#define MCF_PSC_IP(x) (*(vuint8_t *)(&__MBAR[0x008634+((x)*0x100)])) -#define MCF_PSC_OPSET(x) (*(vuint8_t *)(&__MBAR[0x008638+((x)*0x100)])) -#define MCF_PSC_OPRESET(x) (*(vuint8_t *)(&__MBAR[0x00863C+((x)*0x100)])) -#define MCF_PSC_SICR(x) (*(vuint8_t *)(&__MBAR[0x008640+((x)*0x100)])) -#define MCF_PSC_IRCR1(x) (*(vuint8_t *)(&__MBAR[0x008644+((x)*0x100)])) -#define MCF_PSC_IRCR2(x) (*(vuint8_t *)(&__MBAR[0x008648+((x)*0x100)])) -#define MCF_PSC_IRSDR(x) (*(vuint8_t *)(&__MBAR[0x00864C+((x)*0x100)])) -#define MCF_PSC_IRMDR(x) (*(vuint8_t *)(&__MBAR[0x008650+((x)*0x100)])) -#define MCF_PSC_IRFDR(x) (*(vuint8_t *)(&__MBAR[0x008654+((x)*0x100)])) -#define MCF_PSC_RFCNT(x) (*(vuint16_t*)(&__MBAR[0x008658+((x)*0x100)])) -#define MCF_PSC_TFCNT(x) (*(vuint16_t*)(&__MBAR[0x00865C+((x)*0x100)])) -#define MCF_PSC_RFSR(x) (*(vuint16_t*)(&__MBAR[0x008664+((x)*0x100)])) -#define MCF_PSC_TFSR(x) (*(vuint16_t*)(&__MBAR[0x008684+((x)*0x100)])) -#define MCF_PSC_RFCR(x) (*(vuint32_t*)(&__MBAR[0x008668+((x)*0x100)])) -#define MCF_PSC_TFCR(x) (*(vuint32_t*)(&__MBAR[0x008688+((x)*0x100)])) -#define MCF_PSC_RFAR(x) (*(vuint16_t*)(&__MBAR[0x00866E+((x)*0x100)])) -#define MCF_PSC_TFAR(x) (*(vuint16_t*)(&__MBAR[0x00868E+((x)*0x100)])) -#define MCF_PSC_RFRP(x) (*(vuint16_t*)(&__MBAR[0x008672+((x)*0x100)])) -#define MCF_PSC_TFRP(x) (*(vuint16_t*)(&__MBAR[0x008692+((x)*0x100)])) -#define MCF_PSC_RFWP(x) (*(vuint16_t*)(&__MBAR[0x008676+((x)*0x100)])) -#define MCF_PSC_TFWP(x) (*(vuint16_t*)(&__MBAR[0x008696+((x)*0x100)])) -#define MCF_PSC_RLRFP(x) (*(vuint16_t*)(&__MBAR[0x00867A+((x)*0x100)])) -#define MCF_PSC_TLRFP(x) (*(vuint16_t*)(&__MBAR[0x00869A+((x)*0x100)])) -#define MCF_PSC_RLWFP(x) (*(vuint16_t*)(&__MBAR[0x00867E+((x)*0x100)])) -#define MCF_PSC_TLWFP(x) (*(vuint16_t*)(&__MBAR[0x00869E+((x)*0x100)])) - -/* Bit definitions and macros for MCF_PSC_MR */ -#define MCF_PSC_MR_BC(x) (((x)&0x03)<<0) -#define MCF_PSC_MR_PT (0x04) -#define MCF_PSC_MR_PM(x) (((x)&0x03)<<3) -#define MCF_PSC_MR_ERR (0x20) -#define MCF_PSC_MR_RXIRQ (0x40) -#define MCF_PSC_MR_RXRTS (0x80) -#define MCF_PSC_MR_SB(x) (((x)&0x0F)<<0) -#define MCF_PSC_MR_TXCTS (0x10) -#define MCF_PSC_MR_TXRTS (0x20) -#define MCF_PSC_MR_CM(x) (((x)&0x03)<<6) -#define MCF_PSC_MR_PM_MULTI_ADDR (0x1C) -#define MCF_PSC_MR_PM_MULTI_DATA (0x18) -#define MCF_PSC_MR_PM_NONE (0x10) -#define MCF_PSC_MR_PM_FORCE_HI (0x0C) -#define MCF_PSC_MR_PM_FORCE_LO (0x08) -#define MCF_PSC_MR_PM_ODD (0x04) -#define MCF_PSC_MR_PM_EVEN (0x00) -#define MCF_PSC_MR_BC_5 (0x00) -#define MCF_PSC_MR_BC_6 (0x01) -#define MCF_PSC_MR_BC_7 (0x02) -#define MCF_PSC_MR_BC_8 (0x03) -#define MCF_PSC_MR_CM_NORMAL (0x00) -#define MCF_PSC_MR_CM_ECHO (0x40) -#define MCF_PSC_MR_CM_LOCAL_LOOP (0x80) -#define MCF_PSC_MR_CM_REMOTE_LOOP (0xC0) -#define MCF_PSC_MR_SB_STOP_BITS_1 (0x07) -#define MCF_PSC_MR_SB_STOP_BITS_15 (0x08) -#define MCF_PSC_MR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for MCF_PSC_SR */ -#define MCF_PSC_SR_ERR (0x0040) -#define MCF_PSC_SR_CDE_DEOF (0x0080) -#define MCF_PSC_SR_RXRDY (0x0100) -#define MCF_PSC_SR_FU (0x0200) -#define MCF_PSC_SR_TXRDY (0x0400) -#define MCF_PSC_SR_TXEMP_URERR (0x0800) -#define MCF_PSC_SR_OE (0x1000) -#define MCF_PSC_SR_PE_CRCERR (0x2000) -#define MCF_PSC_SR_FE_PHYERR (0x4000) -#define MCF_PSC_SR_RB_NEOF (0x8000) - -/* Bit definitions and macros for MCF_PSC_CSR */ -#define MCF_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0) -#define MCF_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4) -#define MCF_PSC_CSR_RCSEL_SYS_CLK (0xD0) -#define MCF_PSC_CSR_RCSEL_CTM16 (0xE0) -#define MCF_PSC_CSR_RCSEL_CTM (0xF0) -#define MCF_PSC_CSR_TCSEL_SYS_CLK (0x0D) -#define MCF_PSC_CSR_TCSEL_CTM16 (0x0E) -#define MCF_PSC_CSR_TCSEL_CTM (0x0F) - -/* Bit definitions and macros for MCF_PSC_CR */ -#define MCF_PSC_CR_RXC(x) (((x)&0x03)<<0) -#define MCF_PSC_CR_TXC(x) (((x)&0x03)<<2) -#define MCF_PSC_CR_MISC(x) (((x)&0x07)<<4) -#define MCF_PSC_CR_NONE (0x00) -#define MCF_PSC_CR_STOP_BREAK (0x70) -#define MCF_PSC_CR_START_BREAK (0x60) -#define MCF_PSC_CR_BKCHGINT (0x50) -#define MCF_PSC_CR_RESET_ERROR (0x40) -#define MCF_PSC_CR_RESET_TX (0x30) -#define MCF_PSC_CR_RESET_RX (0x20) -#define MCF_PSC_CR_RESET_MR (0x10) -#define MCF_PSC_CR_TX_DISABLED (0x08) -#define MCF_PSC_CR_TX_ENABLED (0x04) -#define MCF_PSC_CR_RX_DISABLED (0x02) -#define MCF_PSC_CR_RX_ENABLED (0x01) - -/* Bit definitions and macros for MCF_PSC_TB_8BIT */ -#define MCF_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0) -#define MCF_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8) -#define MCF_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16) -#define MCF_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PSC_TB_16BIT */ -#define MCF_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0) -#define MCF_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PSC_TB_AC97 */ -#define MCF_PSC_TB_AC97_SOF (0x00000800) -#define MCF_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12) - -/* Bit definitions and macros for MCF_PSC_IPCR */ -#define MCF_PSC_IPCR_RESERVED (0x0C) -#define MCF_PSC_IPCR_CTS (0x0D) -#define MCF_PSC_IPCR_D_CTS (0x1C) -#define MCF_PSC_IPCR_SYNC (0x8C) - -/* Bit definitions and macros for MCF_PSC_ACR */ -#define MCF_PSC_ACR_IEC0 (0x01) -#define MCF_PSC_ACR_CTMS(x) (((x)&0x07)<<4) -#define MCF_PSC_ACR_BRG (0x80) - -/* Bit definitions and macros for MCF_PSC_ISR */ -#define MCF_PSC_ISR_ERR (0x0040) -#define MCF_PSC_ISR_DEOF (0x0080) -#define MCF_PSC_ISR_TXRDY (0x0100) -#define MCF_PSC_ISR_RXRDY_FU (0x0200) -#define MCF_PSC_ISR_DB (0x0400) -#define MCF_PSC_ISR_IPC (0x8000) - -/* Bit definitions and macros for MCF_PSC_IMR */ -#define MCF_PSC_IMR_ERR (0x0040) -#define MCF_PSC_IMR_DEOF (0x0080) -#define MCF_PSC_IMR_TXRDY (0x0100) -#define MCF_PSC_IMR_RXRDY_FU (0x0200) -#define MCF_PSC_IMR_DB (0x0400) -#define MCF_PSC_IMR_IPC (0x8000) - -/* Bit definitions and macros for MCF_PSC_IP */ -#define MCF_PSC_IP_CTS (0x01) -#define MCF_PSC_IP_TGL (0x40) -#define MCF_PSC_IP_LWPR_B (0x80) - -/* Bit definitions and macros for MCF_PSC_OPSET */ -#define MCF_PSC_OPSET_RTS (0x01) - -/* Bit definitions and macros for MCF_PSC_OPRESET */ -#define MCF_PSC_OPRESET_RTS (0x01) - -/* Bit definitions and macros for MCF_PSC_SICR */ -#define MCF_PSC_SICR_SIM(x) (((x)&0x07)<<0) -#define MCF_PSC_SICR_SHDIR (0x10) -#define MCF_PSC_SICR_DTS (0x20) -#define MCF_PSC_SICR_AWR (0x40) -#define MCF_PSC_SICR_ACRB (0x80) -#define MCF_PSC_SICR_SIM_UART (0x00) -#define MCF_PSC_SICR_SIM_MODEM8 (0x01) -#define MCF_PSC_SICR_SIM_MODEM16 (0x02) -#define MCF_PSC_SICR_SIM_AC97 (0x03) -#define MCF_PSC_SICR_SIM_SIR (0x04) -#define MCF_PSC_SICR_SIM_MIR (0x05) -#define MCF_PSC_SICR_SIM_FIR (0x06) - -/* Bit definitions and macros for MCF_PSC_IRCR1 */ -#define MCF_PSC_IRCR1_SPUL (0x01) -#define MCF_PSC_IRCR1_SIPEN (0x02) -#define MCF_PSC_IRCR1_FD (0x04) - -/* Bit definitions and macros for MCF_PSC_IRCR2 */ -#define MCF_PSC_IRCR2_NXTEOF (0x01) -#define MCF_PSC_IRCR2_ABORT (0x02) -#define MCF_PSC_IRCR2_SIPREQ (0x04) - -/* Bit definitions and macros for MCF_PSC_IRMDR */ -#define MCF_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0) -#define MCF_PSC_IRMDR_FREQ (0x80) - -/* Bit definitions and macros for MCF_PSC_IRFDR */ -#define MCF_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_PSC_RFCNT */ -#define MCF_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TFCNT */ -#define MCF_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RFSR */ -#define MCF_PSC_RFSR_EMT (0x0001) -#define MCF_PSC_RFSR_ALARM (0x0002) -#define MCF_PSC_RFSR_FU (0x0004) -#define MCF_PSC_RFSR_FRMRY (0x0008) -#define MCF_PSC_RFSR_OF (0x0010) -#define MCF_PSC_RFSR_UF (0x0020) -#define MCF_PSC_RFSR_RXW (0x0040) -#define MCF_PSC_RFSR_FAE (0x0080) -#define MCF_PSC_RFSR_FRM(x) (((x)&0x000F)<<8) -#define MCF_PSC_RFSR_TAG (0x1000) -#define MCF_PSC_RFSR_TXW (0x4000) -#define MCF_PSC_RFSR_IP (0x8000) -#define MCF_PSC_RFSR_FRM_BYTE0 (0x0800) -#define MCF_PSC_RFSR_FRM_BYTE1 (0x0400) -#define MCF_PSC_RFSR_FRM_BYTE2 (0x0200) -#define MCF_PSC_RFSR_FRM_BYTE3 (0x0100) - -/* Bit definitions and macros for MCF_PSC_TFSR */ -#define MCF_PSC_TFSR_EMT (0x0001) -#define MCF_PSC_TFSR_ALARM (0x0002) -#define MCF_PSC_TFSR_FU (0x0004) -#define MCF_PSC_TFSR_FRMRY (0x0008) -#define MCF_PSC_TFSR_OF (0x0010) -#define MCF_PSC_TFSR_UF (0x0020) -#define MCF_PSC_TFSR_RXW (0x0040) -#define MCF_PSC_TFSR_FAE (0x0080) -#define MCF_PSC_TFSR_FRM(x) (((x)&0x000F)<<8) -#define MCF_PSC_TFSR_TAG (0x1000) -#define MCF_PSC_TFSR_TXW (0x4000) -#define MCF_PSC_TFSR_IP (0x8000) -#define MCF_PSC_TFSR_FRM_BYTE0 (0x0800) -#define MCF_PSC_TFSR_FRM_BYTE1 (0x0400) -#define MCF_PSC_TFSR_FRM_BYTE2 (0x0200) -#define MCF_PSC_TFSR_FRM_BYTE3 (0x0100) - -/* Bit definitions and macros for MCF_PSC_RFCR */ -#define MCF_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0) -#define MCF_PSC_RFCR_TXW_MSK (0x00040000) -#define MCF_PSC_RFCR_OF_MSK (0x00080000) -#define MCF_PSC_RFCR_UF_MSK (0x00100000) -#define MCF_PSC_RFCR_RXW_MSK (0x00200000) -#define MCF_PSC_RFCR_FAE_MSK (0x00400000) -#define MCF_PSC_RFCR_IP_MSK (0x00800000) -#define MCF_PSC_RFCR_GR(x) (((x)&0x00000007)<<24) -#define MCF_PSC_RFCR_FRMEN (0x08000000) -#define MCF_PSC_RFCR_TIMER (0x10000000) -#define MCF_PSC_RFCR_WRITETAG (0x20000000) -#define MCF_PSC_RFCR_SHADOW (0x80000000) - -/* Bit definitions and macros for MCF_PSC_TFCR */ -#define MCF_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0) -#define MCF_PSC_TFCR_TXW_MSK (0x00040000) -#define MCF_PSC_TFCR_OF_MSK (0x00080000) -#define MCF_PSC_TFCR_UF_MSK (0x00100000) -#define MCF_PSC_TFCR_RXW_MSK (0x00200000) -#define MCF_PSC_TFCR_FAE_MSK (0x00400000) -#define MCF_PSC_TFCR_IP_MSK (0x00800000) -#define MCF_PSC_TFCR_GR(x) (((x)&0x00000007)<<24) -#define MCF_PSC_TFCR_FRMEN (0x08000000) -#define MCF_PSC_TFCR_TIMER (0x10000000) -#define MCF_PSC_TFCR_WRITETAG (0x20000000) -#define MCF_PSC_TFCR_SHADOW (0x80000000) - -/* Bit definitions and macros for MCF_PSC_RFAR */ -#define MCF_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TFAR */ -#define MCF_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RFRP */ -#define MCF_PSC_RFRP_READ(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TFRP */ -#define MCF_PSC_TFRP_READ(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RFWP */ -#define MCF_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TFWP */ -#define MCF_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RLRFP */ -#define MCF_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TLRFP */ -#define MCF_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RLWFP */ -#define MCF_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TLWFP */ -#define MCF_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0) - -#endif /* __MCF548X_PSC_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_sdramc.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_sdramc.h deleted file mode 100644 index 1f41f32310..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_sdramc.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * SDRAM Controller (SDRAMC) - */ -#ifndef __MCF548X_SDRAMC_H__ -#define __MCF548X_SDRAMC_H__ - -/* - * SDRAM Controller (SDRAMC) - */ - -/* Register read/write macros */ -#define MCF_SDRAMC_SDRAMDS (*(vuint32_t*)(&__MBAR[0x000004])) -#define MCF_SDRAMC_CS0CFG (*(vuint32_t*)(&__MBAR[0x000020])) -#define MCF_SDRAMC_CS1CFG (*(vuint32_t*)(&__MBAR[0x000024])) -#define MCF_SDRAMC_CS2CFG (*(vuint32_t*)(&__MBAR[0x000028])) -#define MCF_SDRAMC_CS3CFG (*(vuint32_t*)(&__MBAR[0x00002C])) -#define MCF_SDRAMC_CSnCFG(x) (*(vuint32_t*)(&__MBAR[0x000020+((x)*0x004)])) -#define MCF_SDRAMC_SDMR (*(vuint32_t*)(&__MBAR[0x000100])) -#define MCF_SDRAMC_SDCR (*(vuint32_t*)(&__MBAR[0x000104])) -#define MCF_SDRAMC_SDCFG1 (*(vuint32_t*)(&__MBAR[0x000108])) -#define MCF_SDRAMC_SDCFG2 (*(vuint32_t*)(&__MBAR[0x00010C])) - -/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */ -#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x00000003)<<0) -#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x00000003)<<2) -#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x00000003)<<4) -#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x00000003)<<6) -#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x00000003)<<8) -#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x02) -#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x01) -#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0x00) -#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x03) - -/* Bit definitions and macros for MCF_SDRAMC_CSnCFG */ -#define MCF_SDRAMC_CSnCFG_CSSZ(x) (((x)&0x0000001F)<<0) -#define MCF_SDRAMC_CSnCFG_CSBA(x) (((x)&0x00000FFF)<<20) -#define MCF_SDRAMC_CSnCFG_CSSZ_DIABLE (0x00000000) -#define MCF_SDRAMC_CSnCFG_CSSZ_1MBYTE (0x00000013) -#define MCF_SDRAMC_CSnCFG_CSSZ_2MBYTE (0x00000014) -#define MCF_SDRAMC_CSnCFG_CSSZ_4MBYTE (0x00000015) -#define MCF_SDRAMC_CSnCFG_CSSZ_8MBYTE (0x00000016) -#define MCF_SDRAMC_CSnCFG_CSSZ_16MBYTE (0x00000017) -#define MCF_SDRAMC_CSnCFG_CSSZ_32MBYTE (0x00000018) -#define MCF_SDRAMC_CSnCFG_CSSZ_64MBYTE (0x00000019) -#define MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE (0x0000001A) -#define MCF_SDRAMC_CSnCFG_CSSZ_256MBYTE (0x0000001B) -#define MCF_SDRAMC_CSnCFG_CSSZ_512MBYTE (0x0000001C) -#define MCF_SDRAMC_CSnCFG_CSSZ_1GBYTE (0x0000001D) -#define MCF_SDRAMC_CSnCFG_CSSZ_2GBYTE (0x0000001E) -#define MCF_SDRAMC_CSnCFG_CSSZ_4GBYTE (0x0000001F) - -/* Bit definitions and macros for MCF_SDRAMC_SDMR */ -#define MCF_SDRAMC_SDMR_CMD (0x00010000) -#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) -#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) -#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) -#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) - -/* Bit definitions and macros for MCF_SDRAMC_SDCR */ -#define MCF_SDRAMC_SDCR_IPALL (0x00000002) -#define MCF_SDRAMC_SDCR_IREF (0x00000004) -#define MCF_SDRAMC_SDCR_BUFF (0x00000010) -#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) -#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) -#define MCF_SDRAMC_SDCR_DRIVE (0x00400000) -#define MCF_SDRAMC_SDCR_AP (0x00800000) -#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) -#define MCF_SDRAMC_SDCR_REF (0x10000000) -#define MCF_SDRAMC_SDCR_DDR (0x20000000) -#define MCF_SDRAMC_SDCR_CKE (0x40000000) -#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) - -/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ -#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) -#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) -#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) -#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) -#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) -#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) -#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ -#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) -#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) -#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) -#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) - -#endif /* __MCF548X_SDRAMC_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_sec.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_sec.h deleted file mode 100644 index f4a65320c4..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_sec.h +++ /dev/null @@ -1,389 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Integrated Security Engine (SEC) - */ -#ifndef __MCF548X_SEC_H__ -#define __MCF548X_SEC_H__ - -/* - * Integrated Security Engine (SEC) - */ - -/* Register read/write macros */ -#define MCF_SEC_EUACRH (*(vuint32_t*)(&__MBAR[0x021000])) -#define MCF_SEC_EUACRL (*(vuint32_t*)(&__MBAR[0x021004])) -#define MCF_SEC_EUASRH (*(vuint32_t*)(&__MBAR[0x021028])) -#define MCF_SEC_EUASRL (*(vuint32_t*)(&__MBAR[0x02102C])) -#define MCF_SEC_SIMRH (*(vuint32_t*)(&__MBAR[0x021008])) -#define MCF_SEC_SIMRL (*(vuint32_t*)(&__MBAR[0x02100C])) -#define MCF_SEC_SISRH (*(vuint32_t*)(&__MBAR[0x021010])) -#define MCF_SEC_SISRL (*(vuint32_t*)(&__MBAR[0x021014])) -#define MCF_SEC_SICRH (*(vuint32_t*)(&__MBAR[0x021018])) -#define MCF_SEC_SICRL (*(vuint32_t*)(&__MBAR[0x02101C])) -#define MCF_SEC_SIDR (*(vuint32_t*)(&__MBAR[0x021020])) -#define MCF_SEC_SMCR (*(vuint32_t*)(&__MBAR[0x021030])) -#define MCF_SEC_MEAR (*(vuint32_t*)(&__MBAR[0x021038])) -#define MCF_SEC_CCCR0 (*(vuint32_t*)(&__MBAR[0x02200C])) -#define MCF_SEC_CCCR1 (*(vuint32_t*)(&__MBAR[0x02300C])) -#define MCF_SEC_CCPSRH0 (*(vuint32_t*)(&__MBAR[0x022010])) -#define MCF_SEC_CCPSRH1 (*(vuint32_t*)(&__MBAR[0x023010])) -#define MCF_SEC_CCPSRL0 (*(vuint32_t*)(&__MBAR[0x022014])) -#define MCF_SEC_CCPSRL1 (*(vuint32_t*)(&__MBAR[0x023014])) -#define MCF_SEC_CDPR0 (*(vuint32_t*)(&__MBAR[0x022044])) -#define MCF_SEC_CDPR1 (*(vuint32_t*)(&__MBAR[0x023044])) -#define MCF_SEC_FR0 (*(vuint32_t*)(&__MBAR[0x02204C])) -#define MCF_SEC_FR1 (*(vuint32_t*)(&__MBAR[0x02304C])) -#define MCF_SEC_AFRCR (*(vuint32_t*)(&__MBAR[0x028018])) -#define MCF_SEC_AFSR (*(vuint32_t*)(&__MBAR[0x028028])) -#define MCF_SEC_AFISR (*(vuint32_t*)(&__MBAR[0x028030])) -#define MCF_SEC_AFIMR (*(vuint32_t*)(&__MBAR[0x028038])) -#define MCF_SEC_DRCR (*(vuint32_t*)(&__MBAR[0x02A018])) -#define MCF_SEC_DSR (*(vuint32_t*)(&__MBAR[0x02A028])) -#define MCF_SEC_DISR (*(vuint32_t*)(&__MBAR[0x02A030])) -#define MCF_SEC_DIMR (*(vuint32_t*)(&__MBAR[0x02A038])) -#define MCF_SEC_MDRCR (*(vuint32_t*)(&__MBAR[0x02C018])) -#define MCF_SEC_MDSR (*(vuint32_t*)(&__MBAR[0x02C028])) -#define MCF_SEC_MDISR (*(vuint32_t*)(&__MBAR[0x02C030])) -#define MCF_SEC_MDIMR (*(vuint32_t*)(&__MBAR[0x02C038])) -#define MCF_SEC_RNGRCR (*(vuint32_t*)(&__MBAR[0x02E018])) -#define MCF_SEC_RNGSR (*(vuint32_t*)(&__MBAR[0x02E028])) -#define MCF_SEC_RNGISR (*(vuint32_t*)(&__MBAR[0x02E030])) -#define MCF_SEC_RNGIMR (*(vuint32_t*)(&__MBAR[0x02E038])) -#define MCF_SEC_AESRCR (*(vuint32_t*)(&__MBAR[0x032018])) -#define MCF_SEC_AESSR (*(vuint32_t*)(&__MBAR[0x032028])) -#define MCF_SEC_AESISR (*(vuint32_t*)(&__MBAR[0x032030])) -#define MCF_SEC_AESIMR (*(vuint32_t*)(&__MBAR[0x032038])) - -/* Bit definitions and macros for MCF_SEC_EUACRH */ -#define MCF_SEC_EUACRH_AFEU(x) (((x)&0x0000000F)<<0) -#define MCF_SEC_EUACRH_MDEU(x) (((x)&0x0000000F)<<8) -#define MCF_SEC_EUACRH_RNG(x) (((x)&0x0000000F)<<24) -#define MCF_SEC_EUACRH_RNG_NOASSIGN (0x00000000) -#define MCF_SEC_EUACRH_RNG_CHA0 (0x01000000) -#define MCF_SEC_EUACRH_RNG_CHA1 (0x02000000) -#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0x00000000) -#define MCF_SEC_EUACRH_MDEU_CHA0 (0x00000100) -#define MCF_SEC_EUACRH_MDEU_CHA1 (0x00000200) -#define MCF_SEC_EUACRH_AFEU_NOASSIGN (0x00000000) -#define MCF_SEC_EUACRH_AFEU_CHA0 (0x00000001) -#define MCF_SEC_EUACRH_AFEU_CHA1 (0x00000002) - -/* Bit definitions and macros for MCF_SEC_EUACRL */ -#define MCF_SEC_EUACRL_AESU(x) (((x)&0x0000000F)<<16) -#define MCF_SEC_EUACRL_DEU(x) (((x)&0x0000000F)<<24) -#define MCF_SEC_EUACRL_DEU_NOASSIGN (0x00000000) -#define MCF_SEC_EUACRL_DEU_CHA0 (0x01000000) -#define MCF_SEC_EUACRL_DEU_CHA1 (0x02000000) -#define MCF_SEC_EUACRL_AESU_NOASSIGN (0x00000000) -#define MCF_SEC_EUACRL_AESU_CHA0 (0x00010000) -#define MCF_SEC_EUACRL_AESU_CHA1 (0x00020000) - -/* Bit definitions and macros for MCF_SEC_EUASRH */ -#define MCF_SEC_EUASRH_AFEU(x) (((x)&0x0000000F)<<0) -#define MCF_SEC_EUASRH_MDEU(x) (((x)&0x0000000F)<<8) -#define MCF_SEC_EUASRH_RNG(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_SEC_EUASRL */ -#define MCF_SEC_EUASRL_AESU(x) (((x)&0x0000000F)<<16) -#define MCF_SEC_EUASRL_DEU(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_SEC_SIMRH */ -#define MCF_SEC_SIMRH_AERR (0x08000000) -#define MCF_SEC_SIMRH_CHA0DN (0x10000000) -#define MCF_SEC_SIMRH_CHA0ERR (0x20000000) -#define MCF_SEC_SIMRH_CHA1DN (0x40000000) -#define MCF_SEC_SIMRH_CHA1ERR (0x80000000) - -/* Bit definitions and macros for MCF_SEC_SIMRL */ -#define MCF_SEC_SIMRL_TEA (0x00000040) -#define MCF_SEC_SIMRL_DEUDN (0x00000100) -#define MCF_SEC_SIMRL_DEUERR (0x00000200) -#define MCF_SEC_SIMRL_AESUDN (0x00001000) -#define MCF_SEC_SIMRL_AESUERR (0x00002000) -#define MCF_SEC_SIMRL_MDEUDN (0x00010000) -#define MCF_SEC_SIMRL_MDEUERR (0x00020000) -#define MCF_SEC_SIMRL_AFEUDN (0x00100000) -#define MCF_SEC_SIMRL_AFEUERR (0x00200000) -#define MCF_SEC_SIMRL_RNGDN (0x01000000) -#define MCF_SEC_SIMRL_RNGERR (0x02000000) - -/* Bit definitions and macros for MCF_SEC_SISRH */ -#define MCF_SEC_SISRH_AERR (0x08000000) -#define MCF_SEC_SISRH_CHA0DN (0x10000000) -#define MCF_SEC_SISRH_CHA0ERR (0x20000000) -#define MCF_SEC_SISRH_CHA1DN (0x40000000) -#define MCF_SEC_SISRH_CHA1ERR (0x80000000) - -/* Bit definitions and macros for MCF_SEC_SISRL */ -#define MCF_SEC_SISRL_TEA (0x00000040) -#define MCF_SEC_SISRL_DEUDN (0x00000100) -#define MCF_SEC_SISRL_DEUERR (0x00000200) -#define MCF_SEC_SISRL_AESUDN (0x00001000) -#define MCF_SEC_SISRL_AESUERR (0x00002000) -#define MCF_SEC_SISRL_MDEUDN (0x00010000) -#define MCF_SEC_SISRL_MDEUERR (0x00020000) -#define MCF_SEC_SISRL_AFEUDN (0x00100000) -#define MCF_SEC_SISRL_AFEUERR (0x00200000) -#define MCF_SEC_SISRL_RNGDN (0x01000000) -#define MCF_SEC_SISRL_RNGERR (0x02000000) - -/* Bit definitions and macros for MCF_SEC_SICRH */ -#define MCF_SEC_SICRH_AERR (0x08000000) -#define MCF_SEC_SICRH_CHA0DN (0x10000000) -#define MCF_SEC_SICRH_CHA0ERR (0x20000000) -#define MCF_SEC_SICRH_CHA1DN (0x40000000) -#define MCF_SEC_SICRH_CHA1ERR (0x80000000) - -/* Bit definitions and macros for MCF_SEC_SICRL */ -#define MCF_SEC_SICRL_TEA (0x00000040) -#define MCF_SEC_SICRL_DEUDN (0x00000100) -#define MCF_SEC_SICRL_DEUERR (0x00000200) -#define MCF_SEC_SICRL_AESUDN (0x00001000) -#define MCF_SEC_SICRL_AESUERR (0x00002000) -#define MCF_SEC_SICRL_MDEUDN (0x00010000) -#define MCF_SEC_SICRL_MDEUERR (0x00020000) -#define MCF_SEC_SICRL_AFEUDN (0x00100000) -#define MCF_SEC_SICRL_AFEUERR (0x00200000) -#define MCF_SEC_SICRL_RNGDN (0x01000000) -#define MCF_SEC_SICRL_RNGERR (0x02000000) - -/* Bit definitions and macros for MCF_SEC_SMCR */ -#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0x0000000F)<<4) -#define MCF_SEC_SMCR_SWR (0x01000000) -#define MCF_SEC_SMCR_CURR_CHAN_1 (0x00000010) -#define MCF_SEC_SMCR_CURR_CHAN_2 (0x00000020) - -/* Bit definitions and macros for MCF_SEC_CCCRn */ -#define MCF_SEC_CCCRn_RST (0x00000001) -#define MCF_SEC_CCCRn_CDIE (0x00000002) -#define MCF_SEC_CCCRn_NT (0x00000004) -#define MCF_SEC_CCCRn_NE (0x00000008) -#define MCF_SEC_CCCRn_WE (0x00000010) -#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x00000007)<<8) -#define MCF_SEC_CCCRn_BURST_SIZE_2 (0x00000000) -#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x00000100) -#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x00000200) -#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x00000300) -#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x00000400) -#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x00000500) -#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x00000600) -#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x00000700) - -/* Bit definitions and macros for MCF_SEC_CCPSRHn */ -#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0x000000FF)<<0) - -/* Bit definitions and macros for MCF_SEC_CCPSRLn */ -#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0x000000FF)<<0) -#define MCF_SEC_CCPSRLn_EUERR (0x00000100) -#define MCF_SEC_CCPSRLn_SERR (0x00000200) -#define MCF_SEC_CCPSRLn_DERR (0x00000400) -#define MCF_SEC_CCPSRLn_PERR (0x00001000) -#define MCF_SEC_CCPSRLn_TEA (0x00002000) -#define MCF_SEC_CCPSRLn_SD (0x00010000) -#define MCF_SEC_CCPSRLn_PD (0x00020000) -#define MCF_SEC_CCPSRLn_SRD (0x00040000) -#define MCF_SEC_CCPSRLn_PRD (0x00080000) -#define MCF_SEC_CCPSRLn_SG (0x00100000) -#define MCF_SEC_CCPSRLn_PG (0x00200000) -#define MCF_SEC_CCPSRLn_SR (0x00400000) -#define MCF_SEC_CCPSRLn_PR (0x00800000) -#define MCF_SEC_CCPSRLn_MO (0x01000000) -#define MCF_SEC_CCPSRLn_MI (0x02000000) -#define MCF_SEC_CCPSRLn_STAT (0x04000000) - -/* Bit definitions and macros for MCF_SEC_AFRCR */ -#define MCF_SEC_AFRCR_SR (0x01000000) -#define MCF_SEC_AFRCR_MI (0x02000000) -#define MCF_SEC_AFRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF_SEC_AFSR */ -#define MCF_SEC_AFSR_RD (0x01000000) -#define MCF_SEC_AFSR_ID (0x02000000) -#define MCF_SEC_AFSR_IE (0x04000000) -#define MCF_SEC_AFSR_OFE (0x08000000) -#define MCF_SEC_AFSR_IFW (0x10000000) -#define MCF_SEC_AFSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF_SEC_AFISR */ -#define MCF_SEC_AFISR_DSE (0x00010000) -#define MCF_SEC_AFISR_KSE (0x00020000) -#define MCF_SEC_AFISR_CE (0x00040000) -#define MCF_SEC_AFISR_ERE (0x00080000) -#define MCF_SEC_AFISR_IE (0x00100000) -#define MCF_SEC_AFISR_OFU (0x02000000) -#define MCF_SEC_AFISR_IFO (0x04000000) -#define MCF_SEC_AFISR_IFE (0x10000000) -#define MCF_SEC_AFISR_OFE (0x20000000) -#define MCF_SEC_AFISR_AE (0x40000000) -#define MCF_SEC_AFISR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_AFIMR */ -#define MCF_SEC_AFIMR_DSE (0x00010000) -#define MCF_SEC_AFIMR_KSE (0x00020000) -#define MCF_SEC_AFIMR_CE (0x00040000) -#define MCF_SEC_AFIMR_ERE (0x00080000) -#define MCF_SEC_AFIMR_IE (0x00100000) -#define MCF_SEC_AFIMR_OFU (0x02000000) -#define MCF_SEC_AFIMR_IFO (0x04000000) -#define MCF_SEC_AFIMR_IFE (0x10000000) -#define MCF_SEC_AFIMR_OFE (0x20000000) -#define MCF_SEC_AFIMR_AE (0x40000000) -#define MCF_SEC_AFIMR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_DRCR */ -#define MCF_SEC_DRCR_SR (0x01000000) -#define MCF_SEC_DRCR_MI (0x02000000) -#define MCF_SEC_DRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF_SEC_DSR */ -#define MCF_SEC_DSR_RD (0x01000000) -#define MCF_SEC_DSR_ID (0x02000000) -#define MCF_SEC_DSR_IE (0x04000000) -#define MCF_SEC_DSR_OFR (0x08000000) -#define MCF_SEC_DSR_IFW (0x10000000) -#define MCF_SEC_DSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF_SEC_DISR */ -#define MCF_SEC_DISR_DSE (0x00010000) -#define MCF_SEC_DISR_KSE (0x00020000) -#define MCF_SEC_DISR_CE (0x00040000) -#define MCF_SEC_DISR_ERE (0x00080000) -#define MCF_SEC_DISR_IE (0x00100000) -#define MCF_SEC_DISR_KPE (0x00200000) -#define MCF_SEC_DISR_OFU (0x02000000) -#define MCF_SEC_DISR_IFO (0x04000000) -#define MCF_SEC_DISR_IFE (0x10000000) -#define MCF_SEC_DISR_OFE (0x20000000) -#define MCF_SEC_DISR_AE (0x40000000) -#define MCF_SEC_DISR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_DIMR */ -#define MCF_SEC_DIMR_DSE (0x00010000) -#define MCF_SEC_DIMR_KSE (0x00020000) -#define MCF_SEC_DIMR_CE (0x00040000) -#define MCF_SEC_DIMR_ERE (0x00080000) -#define MCF_SEC_DIMR_IE (0x00100000) -#define MCF_SEC_DIMR_KPE (0x00200000) -#define MCF_SEC_DIMR_OFU (0x02000000) -#define MCF_SEC_DIMR_IFO (0x04000000) -#define MCF_SEC_DIMR_IFE (0x10000000) -#define MCF_SEC_DIMR_OFE (0x20000000) -#define MCF_SEC_DIMR_AE (0x40000000) -#define MCF_SEC_DIMR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_MDRCR */ -#define MCF_SEC_MDRCR_SR (0x01000000) -#define MCF_SEC_MDRCR_MI (0x02000000) -#define MCF_SEC_MDRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF_SEC_MDSR */ -#define MCF_SEC_MDSR_RD (0x01000000) -#define MCF_SEC_MDSR_ID (0x02000000) -#define MCF_SEC_MDSR_IE (0x04000000) -#define MCF_SEC_MDSR_IFW (0x10000000) -#define MCF_SEC_MDSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF_SEC_MDISR */ -#define MCF_SEC_MDISR_DSE (0x00010000) -#define MCF_SEC_MDISR_KSE (0x00020000) -#define MCF_SEC_MDISR_CE (0x00040000) -#define MCF_SEC_MDISR_ERE (0x00080000) -#define MCF_SEC_MDISR_IE (0x00100000) -#define MCF_SEC_MDISR_IFO (0x04000000) -#define MCF_SEC_MDISR_AE (0x40000000) -#define MCF_SEC_MDISR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_MDIMR */ -#define MCF_SEC_MDIMR_DSE (0x00010000) -#define MCF_SEC_MDIMR_KSE (0x00020000) -#define MCF_SEC_MDIMR_CE (0x00040000) -#define MCF_SEC_MDIMR_ERE (0x00080000) -#define MCF_SEC_MDIMR_IE (0x00100000) -#define MCF_SEC_MDIMR_IFO (0x04000000) -#define MCF_SEC_MDIMR_AE (0x40000000) -#define MCF_SEC_MDIMR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_RNGRCR */ -#define MCF_SEC_RNGRCR_SR (0x01000000) -#define MCF_SEC_RNGRCR_MI (0x02000000) -#define MCF_SEC_RNGRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF_SEC_RNGSR */ -#define MCF_SEC_RNGSR_RD (0x01000000) -#define MCF_SEC_RNGSR_O (0x02000000) -#define MCF_SEC_RNGSR_IE (0x04000000) -#define MCF_SEC_RNGSR_OFR (0x08000000) -#define MCF_SEC_RNGSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF_SEC_RNGISR */ -#define MCF_SEC_RNGISR_IE (0x00100000) -#define MCF_SEC_RNGISR_OFU (0x02000000) -#define MCF_SEC_RNGISR_AE (0x40000000) -#define MCF_SEC_RNGISR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_RNGIMR */ -#define MCF_SEC_RNGIMR_IE (0x00100000) -#define MCF_SEC_RNGIMR_OFU (0x02000000) -#define MCF_SEC_RNGIMR_AE (0x40000000) -#define MCF_SEC_RNGIMR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_AESRCR */ -#define MCF_SEC_AESRCR_SR (0x01000000) -#define MCF_SEC_AESRCR_MI (0x02000000) -#define MCF_SEC_AESRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF_SEC_AESSR */ -#define MCF_SEC_AESSR_RD (0x01000000) -#define MCF_SEC_AESSR_ID (0x02000000) -#define MCF_SEC_AESSR_IE (0x04000000) -#define MCF_SEC_AESSR_OFR (0x08000000) -#define MCF_SEC_AESSR_IFW (0x10000000) -#define MCF_SEC_AESSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF_SEC_AESISR */ -#define MCF_SEC_AESISR_DSE (0x00010000) -#define MCF_SEC_AESISR_KSE (0x00020000) -#define MCF_SEC_AESISR_CE (0x00040000) -#define MCF_SEC_AESISR_ERE (0x00080000) -#define MCF_SEC_AESISR_IE (0x00100000) -#define MCF_SEC_AESISR_OFU (0x02000000) -#define MCF_SEC_AESISR_IFO (0x04000000) -#define MCF_SEC_AESISR_IFE (0x10000000) -#define MCF_SEC_AESISR_OFE (0x20000000) -#define MCF_SEC_AESISR_AE (0x40000000) -#define MCF_SEC_AESISR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_AESIMR */ -#define MCF_SEC_AESIMR_DSE (0x00010000) -#define MCF_SEC_AESIMR_KSE (0x00020000) -#define MCF_SEC_AESIMR_CE (0x00040000) -#define MCF_SEC_AESIMR_ERE (0x00080000) -#define MCF_SEC_AESIMR_IE (0x00100000) -#define MCF_SEC_AESIMR_OFU (0x02000000) -#define MCF_SEC_AESIMR_IFO (0x04000000) -#define MCF_SEC_AESIMR_IFE (0x10000000) -#define MCF_SEC_AESIMR_OFE (0x20000000) -#define MCF_SEC_AESIMR_AE (0x40000000) -#define MCF_SEC_AESIMR_ME (0x80000000) - -#endif /* __MCF548X_SEC_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_siu.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_siu.h deleted file mode 100644 index e663ec726f..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_siu.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * DMA Serial Peripheral Interface (DSPI) - */ -#ifndef __MCF548X_SIU_H__ -#define __MCF548X_SIU_H__ - -/* - * System Integration Unit (SIU) - */ - -/* Register read/write macros */ -#define MCF_SIU_SBCR (*(vuint32_t*)(&__MBAR[0x000010])) -#define MCF_SIU_SECSACR (*(vuint32_t*)(&__MBAR[0x000038])) -#define MCF_SIU_RSR (*(vuint32_t*)(&__MBAR[0x000044])) -#define MCF_SIU_JTAGID (*(vuint32_t*)(&__MBAR[0x000050])) - -/* Bit definitions and macros for MCF_SIU_SBCR */ -#define MCF_SIU_SBCR_PIN2DSPI (0x08000000) -#define MCF_SIU_SBCR_DMA2CPU (0x10000000) -#define MCF_SIU_SBCR_CPU2DMA (0x20000000) -#define MCF_SIU_SBCR_PIN2DMA (0x40000000) -#define MCF_SIU_SBCR_PIN2CPU (0x80000000) - -/* Bit definitions and macros for MCF_SIU_SECSACR */ -#define MCF_SIU_SECSACR_SEQEN (0x00000001) - -/* Bit definitions and macros for MCF_SIU_RSR */ -#define MCF_SIU_RSR_RST (0x00000001) -#define MCF_SIU_RSR_RSTWD (0x00000002) -#define MCF_SIU_RSR_RSTJTG (0x00000008) - -/* Bit definitions and macros for MCF_SIU_JTAGID */ -#define MCF_SIU_JTAGID_REV (0xF0000000) -#define MCF_SIU_JTAGID_PROCESSOR (0x0FFFFFFF) -#define MCF_SIU_JTAGID_MCF5485 (0x0800C01D) -#define MCF_SIU_JTAGID_MCF5484 (0x0800D01D) -#define MCF_SIU_JTAGID_MCF5483 (0x0800E01D) -#define MCF_SIU_JTAGID_MCF5482 (0x0800F01D) -#define MCF_SIU_JTAGID_MCF5481 (0x0801001D) -#define MCF_SIU_JTAGID_MCF5480 (0x0801101D) -#define MCF_SIU_JTAGID_MCF5475 (0x0801201D) -#define MCF_SIU_JTAGID_MCF5474 (0x0801301D) -#define MCF_SIU_JTAGID_MCF5473 (0x0801401D) -#define MCF_SIU_JTAGID_MCF5472 (0x0801501D) -#define MCF_SIU_JTAGID_MCF5471 (0x0801601D) -#define MCF_SIU_JTAGID_MCF5470 (0x0801701D) - -#endif /* __MCF548X_SIU_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_slt.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_slt.h deleted file mode 100644 index 6e472f2288..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_slt.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Slice Timers (SLT) - */ -#ifndef __MCF548X_SLT_H__ -#define __MCF548X_SLT_H__ - -/* - * Slice Timers (SLT) - */ - -/* Register read/write macros */ -#define MCF_SLT_SLTCNT0 (*(vuint32_t*)(&__MBAR[0x000900])) -#define MCF_SLT_SCR0 (*(vuint32_t*)(&__MBAR[0x000904])) -#define MCF_SLT_SCNT0 (*(vuint32_t*)(&__MBAR[0x000908])) -#define MCF_SLT_SSR0 (*(vuint32_t*)(&__MBAR[0x00090C])) - -#define MCF_SLT_SLTCNT1 (*(vuint32_t*)(&__MBAR[0x000910])) -#define MCF_SLT_SCR1 (*(vuint32_t*)(&__MBAR[0x000914])) -#define MCF_SLT_SCNT1 (*(vuint32_t*)(&__MBAR[0x000918])) -#define MCF_SLT_SSR1 (*(vuint32_t*)(&__MBAR[0x00091C])) - -#define MCF_SLT_SLTCNT(x) (*(vuint32_t*)(&__MBAR[0x000900+((x)*0x010)])) -#define MCF_SLT_SCR(x) (*(vuint32_t*)(&__MBAR[0x000904+((x)*0x010)])) -#define MCF_SLT_SCNT(x) (*(vuint32_t*)(&__MBAR[0x000908+((x)*0x010)])) -#define MCF_SLT_SSR(x) (*(vuint32_t*)(&__MBAR[0x00090C+((x)*0x010)])) - -/* Bit definitions and macros for MCF_SLT_SCR */ -#define MCF_SLT_SCR_TEN (0x01000000) -#define MCF_SLT_SCR_IEN (0x02000000) -#define MCF_SLT_SCR_RUN (0x04000000) - -/* Bit definitions and macros for MCF_SLT_SSR */ -#define MCF_SLT_SSR_ST (0x01000000) -#define MCF_SLT_SSR_BE (0x02000000) - - -#ifndef __ASSEMBLY__ - -#define MCF_SLT_Address(x) ((struct mcf5xxx_slt*)(void*)(&__MBAR[0x000900+((x)*0x010)])) - -struct mcf5xxx_slt { - vuint32_t STCNT; /* Slice Terminal Count */ - vuint32_t SCR; /* Slice Timer Control Register */ - vuint32_t SCNT; /* Slice Count Value */ - vuint32_t SSR; /* Slice Timer Status Register */ -}; - -#endif - -#endif /* __MCF548X_SLT_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_sram.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_sram.h deleted file mode 100644 index d5eb4642c3..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_sram.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * 32KByte System SRAM (SRAM) - */ -#ifndef __MCF548X_SRAM_H__ -#define __MCF548X_SRAM_H__ - -/* - * 32KByte System SRAM (SRAM) - */ - -/* Register read/write macros */ -#define MCF_SRAM_SSCR (*(vuint32_t*)(&__MBAR[0x01FFC0])) -#define MCF_SRAM_TCCR (*(vuint32_t*)(&__MBAR[0x01FFC4])) -#define MCF_SRAM_TCCRDR (*(vuint32_t*)(&__MBAR[0x01FFC8])) -#define MCF_SRAM_TCCRDW (*(vuint32_t*)(&__MBAR[0x01FFCC])) -#define MCF_SRAM_TCCRSEC (*(vuint32_t*)(&__MBAR[0x01FFD0])) - -/* Bit definitions and macros for MCF_SRAM_SSCR */ -#define MCF_SRAM_SSCR_INLV (0x00010000) - -/* Bit definitions and macros for MCF_SRAM_TCCR */ -#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0x0000000F)<<0) -#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0x0000000F)<<8) -#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0x0000000F)<<16) -#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_SRAM_TCCRDR */ -#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0x0000000F)<<0) -#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0x0000000F)<<8) -#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0x0000000F)<<16) -#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_SRAM_TCCRDW */ -#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0x0000000F)<<0) -#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0x0000000F)<<8) -#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0x0000000F)<<16) -#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_SRAM_TCCRSEC */ -#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0x0000000F)<<0) -#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0x0000000F)<<8) -#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0x0000000F)<<16) -#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0x0000000F)<<24) - -#endif /* __MCF548X_SRAM_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_uart.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_uart.h deleted file mode 100644 index 8f46f1c3ec..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_uart.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Programmable Serial Controller (UART Compatible Definitions) (UART) - */ -#ifndef __MCF548X_UART_H__ -#define __MCF548X_UART_H__ - -/* - * Programmable Serial Controller (UART Compatible Definitions) (UART) - */ - -/* Register read/write macros */ -#define MCF_UART_UMR0 (*(vuint8_t *)(&__MBAR[0x008600])) -#define MCF_UART_USR0 (*(vuint8_t *)(&__MBAR[0x008604])) -#define MCF_UART_UCSR0 (*(vuint8_t *)(&__MBAR[0x008604])) -#define MCF_UART_UCR0 (*(vuint8_t *)(&__MBAR[0x008608])) -#define MCF_UART_URB0 (*(vuint8_t *)(&__MBAR[0x00860C])) -#define MCF_UART_UTB0 (*(vuint8_t *)(&__MBAR[0x00860C])) -#define MCF_UART_UIPCR0 (*(vuint8_t *)(&__MBAR[0x008610])) -#define MCF_UART_UACR0 (*(vuint8_t *)(&__MBAR[0x008610])) -#define MCF_UART_UISR0 (*(vuint8_t *)(&__MBAR[0x008614])) -#define MCF_UART_UIMR0 (*(vuint8_t *)(&__MBAR[0x008614])) -#define MCF_UART_UBG10 (*(vuint8_t *)(&__MBAR[0x008618])) -#define MCF_UART_UBG20 (*(vuint8_t *)(&__MBAR[0x00861C])) -#define MCF_UART_UIP0 (*(vuint8_t *)(&__MBAR[0x008634])) -#define MCF_UART_UOP10 (*(vuint8_t *)(&__MBAR[0x008638])) -#define MCF_UART_UOP00 (*(vuint8_t *)(&__MBAR[0x00863C])) - -#define MCF_UART_UMR1 (*(vuint8_t *)(&__MBAR[0x008700])) -#define MCF_UART_USR1 (*(vuint8_t *)(&__MBAR[0x008704])) -#define MCF_UART_UCSR1 (*(vuint8_t *)(&__MBAR[0x008704])) -#define MCF_UART_UCR1 (*(vuint8_t *)(&__MBAR[0x008708])) -#define MCF_UART_URB1 (*(vuint8_t *)(&__MBAR[0x00870C])) -#define MCF_UART_UTB1 (*(vuint8_t *)(&__MBAR[0x00870C])) -#define MCF_UART_UIPCR1 (*(vuint8_t *)(&__MBAR[0x008710])) -#define MCF_UART_UACR1 (*(vuint8_t *)(&__MBAR[0x008710])) -#define MCF_UART_UISR1 (*(vuint8_t *)(&__MBAR[0x008714])) -#define MCF_UART_UIMR1 (*(vuint8_t *)(&__MBAR[0x008714])) -#define MCF_UART_UBG11 (*(vuint8_t *)(&__MBAR[0x008718])) -#define MCF_UART_UBG21 (*(vuint8_t *)(&__MBAR[0x00871C])) -#define MCF_UART_UIP1 (*(vuint8_t *)(&__MBAR[0x008734])) -#define MCF_UART_UOP11 (*(vuint8_t *)(&__MBAR[0x008738])) -#define MCF_UART_UOP01 (*(vuint8_t *)(&__MBAR[0x00873C])) - -#define MCF_UART_UMR2 (*(vuint8_t *)(&__MBAR[0x008800])) -#define MCF_UART_USR2 (*(vuint8_t *)(&__MBAR[0x008804])) -#define MCF_UART_UCSR2 (*(vuint8_t *)(&__MBAR[0x008804])) -#define MCF_UART_UCR2 (*(vuint8_t *)(&__MBAR[0x008808])) -#define MCF_UART_URB2 (*(vuint8_t *)(&__MBAR[0x00880C])) -#define MCF_UART_UTB2 (*(vuint8_t *)(&__MBAR[0x00880C])) -#define MCF_UART_UIPCR2 (*(vuint8_t *)(&__MBAR[0x008810])) -#define MCF_UART_UACR2 (*(vuint8_t *)(&__MBAR[0x008810])) -#define MCF_UART_UISR2 (*(vuint8_t *)(&__MBAR[0x008814])) -#define MCF_UART_UIMR2 (*(vuint8_t *)(&__MBAR[0x008814])) -#define MCF_UART_UBG12 (*(vuint8_t *)(&__MBAR[0x008818])) -#define MCF_UART_UBG22 (*(vuint8_t *)(&__MBAR[0x00881C])) -#define MCF_UART_UIP2 (*(vuint8_t *)(&__MBAR[0x008834])) -#define MCF_UART_UOP12 (*(vuint8_t *)(&__MBAR[0x008838])) -#define MCF_UART_UOP02 (*(vuint8_t *)(&__MBAR[0x00883C])) - -#define MCF_UART_UMR3 (*(vuint8_t *)(&__MBAR[0x008900])) -#define MCF_UART_USR3 (*(vuint8_t *)(&__MBAR[0x008904])) -#define MCF_UART_UCSR3 (*(vuint8_t *)(&__MBAR[0x008904])) -#define MCF_UART_UCR3 (*(vuint8_t *)(&__MBAR[0x008908])) -#define MCF_UART_URB3 (*(vuint8_t *)(&__MBAR[0x00890C])) -#define MCF_UART_UTB3 (*(vuint8_t *)(&__MBAR[0x00890C])) -#define MCF_UART_UIPCR3 (*(vuint8_t *)(&__MBAR[0x008910])) -#define MCF_UART_UACR3 (*(vuint8_t *)(&__MBAR[0x008910])) -#define MCF_UART_UISR3 (*(vuint8_t *)(&__MBAR[0x008914])) -#define MCF_UART_UIMR3 (*(vuint8_t *)(&__MBAR[0x008914])) -#define MCF_UART_UBG13 (*(vuint8_t *)(&__MBAR[0x008918])) -#define MCF_UART_UBG23 (*(vuint8_t *)(&__MBAR[0x00891C])) -#define MCF_UART_UIP3 (*(vuint8_t *)(&__MBAR[0x008934])) -#define MCF_UART_UOP13 (*(vuint8_t *)(&__MBAR[0x008938])) -#define MCF_UART_UOP03 (*(vuint8_t *)(&__MBAR[0x00893C])) - - -#define MCF_UART_UMR(x) (*(vuint8_t *)(&__MBAR[0x008600+((x)*0x100)])) -#define MCF_UART_USR(x) (*(vuint8_t *)(&__MBAR[0x008604+((x)*0x100)])) -#define MCF_UART_UCSR(x) (*(vuint8_t *)(&__MBAR[0x008604+((x)*0x100)])) -#define MCF_UART_UCR(x) (*(vuint8_t *)(&__MBAR[0x008608+((x)*0x100)])) -#define MCF_UART_URB(x) (*(vuint8_t *)(&__MBAR[0x00860C+((x)*0x100)])) -#define MCF_UART_UTB(x) (*(vuint8_t *)(&__MBAR[0x00860C+((x)*0x100)])) -#define MCF_UART_UIPCR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)])) -#define MCF_UART_UACR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)])) -#define MCF_UART_UISR(x) (*(vuint8_t *)(&__MBAR[0x008614+((x)*0x100)])) -#define MCF_UART_UIMR(x) (*(vuint8_t *)(&__MBAR[0x008614+((x)*0x100)])) -#define MCF_UART_UBG1(x) (*(vuint8_t *)(&__MBAR[0x008618+((x)*0x100)])) -#define MCF_UART_UBG2(x) (*(vuint8_t *)(&__MBAR[0x00861C+((x)*0x100)])) -#define MCF_UART_UIP(x) (*(vuint8_t *)(&__MBAR[0x008634+((x)*0x100)])) -#define MCF_UART_UOP1(x) (*(vuint8_t *)(&__MBAR[0x008638+((x)*0x100)])) -#define MCF_UART_UOP0(x) (*(vuint8_t *)(&__MBAR[0x00863C+((x)*0x100)])) - -/* Bit definitions and macros for MCF_UART_UMR */ -#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) -#define MCF_UART_UMR_PT (0x04) -#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) -#define MCF_UART_UMR_ERR (0x20) -#define MCF_UART_UMR_RXIRQ (0x40) -#define MCF_UART_UMR_RXRTS (0x80) -#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) -#define MCF_UART_UMR_TXCTS (0x10) -#define MCF_UART_UMR_TXRTS (0x20) -#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) -#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) -#define MCF_UART_UMR_PM_MULTI_DATA (0x18) -#define MCF_UART_UMR_PM_NONE (0x10) -#define MCF_UART_UMR_PM_FORCE_HI (0x0C) -#define MCF_UART_UMR_PM_FORCE_LO (0x08) -#define MCF_UART_UMR_PM_ODD (0x04) -#define MCF_UART_UMR_PM_EVEN (0x00) -#define MCF_UART_UMR_BC_5 (0x00) -#define MCF_UART_UMR_BC_6 (0x01) -#define MCF_UART_UMR_BC_7 (0x02) -#define MCF_UART_UMR_BC_8 (0x03) -#define MCF_UART_UMR_CM_NORMAL (0x00) -#define MCF_UART_UMR_CM_ECHO (0x40) -#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) -#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) -#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) -#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) -#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for MCF_UART_USR */ -#define MCF_UART_USR_RXRDY (0x01) -#define MCF_UART_USR_FFULL (0x02) -#define MCF_UART_USR_TXRDY (0x04) -#define MCF_UART_USR_TXEMP (0x08) -#define MCF_UART_USR_OE (0x10) -#define MCF_UART_USR_PE (0x20) -#define MCF_UART_USR_FE (0x40) -#define MCF_UART_USR_RB (0x80) - -/* Bit definitions and macros for MCF_UART_UCSR */ -#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) -#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) -#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) -#define MCF_UART_UCSR_RCS_CTM16 (0xE0) -#define MCF_UART_UCSR_RCS_CTM (0xF0) -#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) -#define MCF_UART_UCSR_TCS_CTM16 (0x0E) -#define MCF_UART_UCSR_TCS_CTM (0x0F) - -/* Bit definitions and macros for MCF_UART_UCR */ -#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) -#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) -#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) -#define MCF_UART_UCR_NONE (0x00) -#define MCF_UART_UCR_STOP_BREAK (0x70) -#define MCF_UART_UCR_START_BREAK (0x60) -#define MCF_UART_UCR_BKCHGINT (0x50) -#define MCF_UART_UCR_RESET_ERROR (0x40) -#define MCF_UART_UCR_RESET_TX (0x30) -#define MCF_UART_UCR_RESET_RX (0x20) -#define MCF_UART_UCR_RESET_MR (0x10) -#define MCF_UART_UCR_TX_DISABLED (0x08) -#define MCF_UART_UCR_TX_ENABLED (0x04) -#define MCF_UART_UCR_RX_DISABLED (0x02) -#define MCF_UART_UCR_RX_ENABLED (0x01) - -/* Bit definitions and macros for MCF_UART_UIPCR */ -#define MCF_UART_UIPCR_CTS (0x01) -#define MCF_UART_UIPCR_COS (0x10) - -/* Bit definitions and macros for MCF_UART_UACR */ -#define MCF_UART_UACR_IEC (0x01) - -/* Bit definitions and macros for MCF_UART_UISR */ -#define MCF_UART_UISR_TXRDY (0x01) -#define MCF_UART_UISR_RXRDY_FU (0x02) -#define MCF_UART_UISR_DB (0x04) -#define MCF_UART_UISR_RXFTO (0x08) -#define MCF_UART_UISR_TXFIFO (0x10) -#define MCF_UART_UISR_RXFIFO (0x20) -#define MCF_UART_UISR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIMR */ -#define MCF_UART_UIMR_TXRDY (0x01) -#define MCF_UART_UIMR_RXRDY_FU (0x02) -#define MCF_UART_UIMR_DB (0x04) -#define MCF_UART_UIMR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIP */ -#define MCF_UART_UIP_CTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP1 */ -#define MCF_UART_UOP1_RTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP0 */ -#define MCF_UART_UOP0_RTS (0x01) - -/* The UART registers for mem mapped access */ -struct m5407uart -{ - vuint8_t umr; vuint24_t reserved0; - vuint8_t usr; vuint24_t reserved1; /* ucsr */ - vuint8_t ucr; vuint24_t reserved2; - vuint8_t urb; vuint24_t reserved3; /* utb */ - vuint8_t uipcr; vuint24_t reserved4; /* uacr */ - vuint8_t uisr; vuint24_t reserved5; /* uimr */ - vuint8_t udu; vuint24_t reserved6; - vuint8_t ubg1; vuint24_t reserved7; - vuint8_t ubg2; vuint24_t reserved8; - const uint8_t uip; vuint24_t reserved9; - vuint8_t uop1; vuint24_t reserved10; - vuint8_t uop0; vuint24_t reserved11; -} __attribute((packed)); - -#define MCF_UART(x) (*(struct m5407uart *)(&__MBAR[0x008600+((x)*0x100)])) - - -#endif /* __MCF548X_UART_H__ */ - diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_usb.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_usb.h deleted file mode 100644 index 0c8e92cdad..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_usb.h +++ /dev/null @@ -1,509 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Universal Serial Bus (USB) - * - * @note According to FreeScale errata sheet, the USB controller - * isn't really usable on MCF54xx V4E CPUs. - * Check V4M cores or wait for errata fixed - * Last update: 25.02.2008 10:55:00 - */ -#ifndef __MCF548X_USB_H__ -#define __MCF548X_USB_H__ - -/* - * Universal Serial Bus (USB) - */ - -/* Register read/write macros */ -#define MCF_USB_USBAISR (*(vuint8_t *)(&__MBAR[0x00B000])) -#define MCF_USB_USBAIMR (*(vuint8_t *)(&__MBAR[0x00B001])) -#define MCF_USB_EPINFO (*(vuint8_t *)(&__MBAR[0x00B003])) -#define MCF_USB_CFGR (*(vuint8_t *)(&__MBAR[0x00B004])) -#define MCF_USB_CFGAR (*(vuint8_t *)(&__MBAR[0x00B005])) -#define MCF_USB_SPEEDR (*(vuint8_t *)(&__MBAR[0x00B006])) -#define MCF_USB_FRMNUMR (*(vuint16_t*)(&__MBAR[0x00B00E])) -#define MCF_USB_EPTNR (*(vuint16_t*)(&__MBAR[0x00B010])) -#define MCF_USB_IFUR (*(vuint16_t*)(&__MBAR[0x00B014])) -#define MCF_USB_IFR0 (*(vuint16_t*)(&__MBAR[0x00B040])) -#define MCF_USB_IFR1 (*(vuint16_t*)(&__MBAR[0x00B042])) -#define MCF_USB_IFR2 (*(vuint16_t*)(&__MBAR[0x00B044])) -#define MCF_USB_IFR3 (*(vuint16_t*)(&__MBAR[0x00B046])) -#define MCF_USB_IFR4 (*(vuint16_t*)(&__MBAR[0x00B048])) -#define MCF_USB_IFR5 (*(vuint16_t*)(&__MBAR[0x00B04A])) -#define MCF_USB_IFR6 (*(vuint16_t*)(&__MBAR[0x00B04C])) -#define MCF_USB_IFR7 (*(vuint16_t*)(&__MBAR[0x00B04E])) -#define MCF_USB_IFR8 (*(vuint16_t*)(&__MBAR[0x00B050])) -#define MCF_USB_IFR9 (*(vuint16_t*)(&__MBAR[0x00B052])) -#define MCF_USB_IFR10 (*(vuint16_t*)(&__MBAR[0x00B054])) -#define MCF_USB_IFR11 (*(vuint16_t*)(&__MBAR[0x00B056])) -#define MCF_USB_IFR12 (*(vuint16_t*)(&__MBAR[0x00B058])) -#define MCF_USB_IFR13 (*(vuint16_t*)(&__MBAR[0x00B05A])) -#define MCF_USB_IFR14 (*(vuint16_t*)(&__MBAR[0x00B05C])) -#define MCF_USB_IFR15 (*(vuint16_t*)(&__MBAR[0x00B05E])) -#define MCF_USB_IFR16 (*(vuint16_t*)(&__MBAR[0x00B060])) -#define MCF_USB_IFR17 (*(vuint16_t*)(&__MBAR[0x00B062])) -#define MCF_USB_IFR18 (*(vuint16_t*)(&__MBAR[0x00B064])) -#define MCF_USB_IFR19 (*(vuint16_t*)(&__MBAR[0x00B066])) -#define MCF_USB_IFR20 (*(vuint16_t*)(&__MBAR[0x00B068])) -#define MCF_USB_IFR21 (*(vuint16_t*)(&__MBAR[0x00B06A])) -#define MCF_USB_IFR22 (*(vuint16_t*)(&__MBAR[0x00B06C])) -#define MCF_USB_IFR23 (*(vuint16_t*)(&__MBAR[0x00B06E])) -#define MCF_USB_IFR24 (*(vuint16_t*)(&__MBAR[0x00B070])) -#define MCF_USB_IFR25 (*(vuint16_t*)(&__MBAR[0x00B072])) -#define MCF_USB_IFR26 (*(vuint16_t*)(&__MBAR[0x00B074])) -#define MCF_USB_IFR27 (*(vuint16_t*)(&__MBAR[0x00B076])) -#define MCF_USB_IFR28 (*(vuint16_t*)(&__MBAR[0x00B078])) -#define MCF_USB_IFR29 (*(vuint16_t*)(&__MBAR[0x00B07A])) -#define MCF_USB_IFR30 (*(vuint16_t*)(&__MBAR[0x00B07C])) -#define MCF_USB_IFR31 (*(vuint16_t*)(&__MBAR[0x00B07E])) -#define MCF_USB_IFRn(x) (*(vuint16_t*)(&__MBAR[0x00B040+((x)*0x002)])) -#define MCF_USB_PPCNT (*(vuint16_t*)(&__MBAR[0x00B080])) -#define MCF_USB_DPCNT (*(vuint16_t*)(&__MBAR[0x00B082])) -#define MCF_USB_CRCECNT (*(vuint16_t*)(&__MBAR[0x00B084])) -#define MCF_USB_BSECNT (*(vuint16_t*)(&__MBAR[0x00B086])) -#define MCF_USB_PIDECNT (*(vuint16_t*)(&__MBAR[0x00B088])) -#define MCF_USB_FRMECNT (*(vuint16_t*)(&__MBAR[0x00B08A])) -#define MCF_USB_TXPCNT (*(vuint16_t*)(&__MBAR[0x00B08C])) -#define MCF_USB_CNTOVR (*(vuint8_t *)(&__MBAR[0x00B08E])) -#define MCF_USB_EP0ACR (*(vuint8_t *)(&__MBAR[0x00B101])) -#define MCF_USB_EP0MPSR (*(vuint16_t*)(&__MBAR[0x00B102])) -#define MCF_USB_EP0IFR (*(vuint8_t *)(&__MBAR[0x00B104])) -#define MCF_USB_EP0SR (*(vuint8_t *)(&__MBAR[0x00B105])) -#define MCF_USB_BMRTR (*(vuint8_t *)(&__MBAR[0x00B106])) -#define MCF_USB_BRTR (*(vuint8_t *)(&__MBAR[0x00B107])) -#define MCF_USB_WVALUER (*(vuint16_t*)(&__MBAR[0x00B108])) -#define MCF_USB_WINDEXR (*(vuint16_t*)(&__MBAR[0x00B10A])) -#define MCF_USB_WLENGTH (*(vuint16_t*)(&__MBAR[0x00B10C])) -#define MCF_USB_EP1OUTACR (*(vuint8_t *)(&__MBAR[0x00B131])) -#define MCF_USB_EP2OUTACR (*(vuint8_t *)(&__MBAR[0x00B161])) -#define MCF_USB_EP3OUTACR (*(vuint8_t *)(&__MBAR[0x00B191])) -#define MCF_USB_EP4OUTACR (*(vuint8_t *)(&__MBAR[0x00B1C1])) -#define MCF_USB_EP5OUTACR (*(vuint8_t *)(&__MBAR[0x00B1F1])) -#define MCF_USB_EP6OUTACR (*(vuint8_t *)(&__MBAR[0x00B221])) -#define MCF_USB_EPnOUTACR(x) (*(vuint8_t *)(&__MBAR[0x00B131+((x)*0x030)])) -#define MCF_USB_EP1OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B132])) -#define MCF_USB_EP2OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B162])) -#define MCF_USB_EP3OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B192])) -#define MCF_USB_EP4OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B1C2])) -#define MCF_USB_EP5OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B1F2])) -#define MCF_USB_EP6OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B222])) -#define MCF_USB_EPnOUTMPSR(x) (*(vuint16_t*)(&__MBAR[0x00B132+((x)*0x030)])) -#define MCF_USB_EP1OUTIFR (*(vuint8_t *)(&__MBAR[0x00B134])) -#define MCF_USB_EP2OUTIFR (*(vuint8_t *)(&__MBAR[0x00B164])) -#define MCF_USB_EP3OUTIFR (*(vuint8_t *)(&__MBAR[0x00B194])) -#define MCF_USB_EP4OUTIFR (*(vuint8_t *)(&__MBAR[0x00B1C4])) -#define MCF_USB_EP5OUTIFR (*(vuint8_t *)(&__MBAR[0x00B1F4])) -#define MCF_USB_EP6OUTIFR (*(vuint8_t *)(&__MBAR[0x00B224])) -#define MCF_USB_EPnOUTIFR(x) (*(vuint8_t *)(&__MBAR[0x00B134+((x)*0x030)])) -#define MCF_USB_EP1OUTSR (*(vuint8_t *)(&__MBAR[0x00B135])) -#define MCF_USB_EP2OUTSR (*(vuint8_t *)(&__MBAR[0x00B165])) -#define MCF_USB_EP3OUTSR (*(vuint8_t *)(&__MBAR[0x00B195])) -#define MCF_USB_EP4OUTSR (*(vuint8_t *)(&__MBAR[0x00B1C5])) -#define MCF_USB_EP5OUTSR (*(vuint8_t *)(&__MBAR[0x00B1F5])) -#define MCF_USB_EP6OUTSR (*(vuint8_t *)(&__MBAR[0x00B225])) -#define MCF_USB_EPnOUTSR(x) (*(vuint8_t *)(&__MBAR[0x00B135+((x)*0x030)])) -#define MCF_USB_EP1OUTSFR (*(vuint16_t*)(&__MBAR[0x00B13E])) -#define MCF_USB_EP2OUTSFR (*(vuint16_t*)(&__MBAR[0x00B16E])) -#define MCF_USB_EP3OUTSFR (*(vuint16_t*)(&__MBAR[0x00B19E])) -#define MCF_USB_EP4OUTSFR (*(vuint16_t*)(&__MBAR[0x00B1CE])) -#define MCF_USB_EP5OUTSFR (*(vuint16_t*)(&__MBAR[0x00B1FE])) -#define MCF_USB_EP6OUTSFR (*(vuint16_t*)(&__MBAR[0x00B22E])) -#define MCF_USB_EPnOUTSFR(x) (*(vuint16_t*)(&__MBAR[0x00B13E+((x)*0x030)])) -#define MCF_USB_EP1INACR (*(vuint8_t *)(&__MBAR[0x00B149])) -#define MCF_USB_EP2INACR (*(vuint8_t *)(&__MBAR[0x00B179])) -#define MCF_USB_EP3INACR (*(vuint8_t *)(&__MBAR[0x00B1A9])) -#define MCF_USB_EP4INACR (*(vuint8_t *)(&__MBAR[0x00B1D9])) -#define MCF_USB_EP5INACR (*(vuint8_t *)(&__MBAR[0x00B209])) -#define MCF_USB_EP6INACR (*(vuint8_t *)(&__MBAR[0x00B239])) -#define MCF_USB_EPnINACR(x) (*(vuint8_t *)(&__MBAR[0x00B149+((x)*0x030)])) -#define MCF_USB_EP1INMPSR (*(vuint16_t*)(&__MBAR[0x00B14A])) -#define MCF_USB_EP2INMPSR (*(vuint16_t*)(&__MBAR[0x00B17A])) -#define MCF_USB_EP3INMPSR (*(vuint16_t*)(&__MBAR[0x00B1AA])) -#define MCF_USB_EP4INMPSR (*(vuint16_t*)(&__MBAR[0x00B1DA])) -#define MCF_USB_EP5INMPSR (*(vuint16_t*)(&__MBAR[0x00B20A])) -#define MCF_USB_EP6INMPSR (*(vuint16_t*)(&__MBAR[0x00B23A])) -#define MCF_USB_EPnINMPSR(x) (*(vuint16_t*)(&__MBAR[0x00B14A+((x)*0x030)])) -#define MCF_USB_EP1INIFR (*(vuint8_t *)(&__MBAR[0x00B14C])) -#define MCF_USB_EP2INIFR (*(vuint8_t *)(&__MBAR[0x00B17C])) -#define MCF_USB_EP3INIFR (*(vuint8_t *)(&__MBAR[0x00B1AC])) -#define MCF_USB_EP4INIFR (*(vuint8_t *)(&__MBAR[0x00B1DC])) -#define MCF_USB_EP5INIFR (*(vuint8_t *)(&__MBAR[0x00B20C])) -#define MCF_USB_EP6INIFR (*(vuint8_t *)(&__MBAR[0x00B23C])) -#define MCF_USB_EPnINIFR(x) (*(vuint8_t *)(&__MBAR[0x00B14C+((x)*0x030)])) -#define MCF_USB_EP1INSR (*(vuint8_t *)(&__MBAR[0x00B14D])) -#define MCF_USB_EP2INSR (*(vuint8_t *)(&__MBAR[0x00B17D])) -#define MCF_USB_EP3INSR (*(vuint8_t *)(&__MBAR[0x00B1AD])) -#define MCF_USB_EP4INSR (*(vuint8_t *)(&__MBAR[0x00B1DD])) -#define MCF_USB_EP5INSR (*(vuint8_t *)(&__MBAR[0x00B20D])) -#define MCF_USB_EP6INSR (*(vuint8_t *)(&__MBAR[0x00B23D])) -#define MCF_USB_EPnINSR(x) (*(vuint8_t *)(&__MBAR[0x00B14D+((x)*0x030)])) -#define MCF_USB_EP1INSFR (*(vuint16_t*)(&__MBAR[0x00B15A])) -#define MCF_USB_EP2INSFR (*(vuint16_t*)(&__MBAR[0x00B18A])) -#define MCF_USB_EP3INSFR (*(vuint16_t*)(&__MBAR[0x00B1BA])) -#define MCF_USB_EP4INSFR (*(vuint16_t*)(&__MBAR[0x00B1EA])) -#define MCF_USB_EP5INSFR (*(vuint16_t*)(&__MBAR[0x00B21A])) -#define MCF_USB_EP6INSFR (*(vuint16_t*)(&__MBAR[0x00B24A])) -#define MCF_USB_EPnINSFR(x) (*(vuint16_t*)(&__MBAR[0x00B15A+((x)*0x030)])) -#define MCF_USB_USBSR (*(vuint32_t*)(&__MBAR[0x00B400])) -#define MCF_USB_USBCR (*(vuint32_t*)(&__MBAR[0x00B404])) -#define MCF_USB_DRAMCR (*(vuint32_t*)(&__MBAR[0x00B408])) -#define MCF_USB_DRAMDR (*(vuint32_t*)(&__MBAR[0x00B40C])) -#define MCF_USB_USBISR (*(vuint32_t*)(&__MBAR[0x00B410])) -#define MCF_USB_USBIMR (*(vuint32_t*)(&__MBAR[0x00B414])) -#define MCF_USB_EP0STAT (*(vuint32_t*)(&__MBAR[0x00B440])) -#define MCF_USB_EP1STAT (*(vuint32_t*)(&__MBAR[0x00B470])) -#define MCF_USB_EP2STAT (*(vuint32_t*)(&__MBAR[0x00B4A0])) -#define MCF_USB_EP3STAT (*(vuint32_t*)(&__MBAR[0x00B4D0])) -#define MCF_USB_EP4STAT (*(vuint32_t*)(&__MBAR[0x00B500])) -#define MCF_USB_EP5STAT (*(vuint32_t*)(&__MBAR[0x00B530])) -#define MCF_USB_EP6STAT (*(vuint32_t*)(&__MBAR[0x00B560])) -#define MCF_USB_EPnSTAT(x) (*(vuint32_t*)(&__MBAR[0x00B440+((x)*0x030)])) -#define MCF_USB_EP0ISR (*(vuint32_t*)(&__MBAR[0x00B444])) -#define MCF_USB_EP1ISR (*(vuint32_t*)(&__MBAR[0x00B474])) -#define MCF_USB_EP2ISR (*(vuint32_t*)(&__MBAR[0x00B4A4])) -#define MCF_USB_EP3ISR (*(vuint32_t*)(&__MBAR[0x00B4D4])) -#define MCF_USB_EP4ISR (*(vuint32_t*)(&__MBAR[0x00B504])) -#define MCF_USB_EP5ISR (*(vuint32_t*)(&__MBAR[0x00B534])) -#define MCF_USB_EP6ISR (*(vuint32_t*)(&__MBAR[0x00B564])) -#define MCF_USB_EPnISR(x) (*(vuint32_t*)(&__MBAR[0x00B444+((x)*0x030)])) -#define MCF_USB_EP0IMR (*(vuint32_t*)(&__MBAR[0x00B448])) -#define MCF_USB_EP1IMR (*(vuint32_t*)(&__MBAR[0x00B478])) -#define MCF_USB_EP2IMR (*(vuint32_t*)(&__MBAR[0x00B4A8])) -#define MCF_USB_EP3IMR (*(vuint32_t*)(&__MBAR[0x00B4D8])) -#define MCF_USB_EP4IMR (*(vuint32_t*)(&__MBAR[0x00B508])) -#define MCF_USB_EP5IMR (*(vuint32_t*)(&__MBAR[0x00B538])) -#define MCF_USB_EP6IMR (*(vuint32_t*)(&__MBAR[0x00B568])) -#define MCF_USB_EPnIMR(x) (*(vuint32_t*)(&__MBAR[0x00B448+((x)*0x030)])) -#define MCF_USB_EP0FRCFGR (*(vuint32_t*)(&__MBAR[0x00B44C])) -#define MCF_USB_EP1FRCFGR (*(vuint32_t*)(&__MBAR[0x00B47C])) -#define MCF_USB_EP2FRCFGR (*(vuint32_t*)(&__MBAR[0x00B4AC])) -#define MCF_USB_EP3FRCFGR (*(vuint32_t*)(&__MBAR[0x00B4DC])) -#define MCF_USB_EP4FRCFGR (*(vuint32_t*)(&__MBAR[0x00B50C])) -#define MCF_USB_EP5FRCFGR (*(vuint32_t*)(&__MBAR[0x00B53C])) -#define MCF_USB_EP6FRCFGR (*(vuint32_t*)(&__MBAR[0x00B56C])) -#define MCF_USB_EPnFRCFGR(x) (*(vuint32_t*)(&__MBAR[0x00B44C+((x)*0x030)])) -#define MCF_USB_EP0FDR (*(vuint32_t*)(&__MBAR[0x00B450])) -#define MCF_USB_EP1FDR (*(vuint32_t*)(&__MBAR[0x00B480])) -#define MCF_USB_EP2FDR (*(vuint32_t*)(&__MBAR[0x00B4B0])) -#define MCF_USB_EP3FDR (*(vuint32_t*)(&__MBAR[0x00B4E0])) -#define MCF_USB_EP4FDR (*(vuint32_t*)(&__MBAR[0x00B510])) -#define MCF_USB_EP5FDR (*(vuint32_t*)(&__MBAR[0x00B540])) -#define MCF_USB_EP6FDR (*(vuint32_t*)(&__MBAR[0x00B570])) -#define MCF_USB_EPnFDR(x) (*(vuint32_t*)(&__MBAR[0x00B450+((x)*0x030)])) -#define MCF_USB_EP0FSR (*(vuint32_t*)(&__MBAR[0x00B454])) -#define MCF_USB_EP1FSR (*(vuint32_t*)(&__MBAR[0x00B484])) -#define MCF_USB_EP2FSR (*(vuint32_t*)(&__MBAR[0x00B4B4])) -#define MCF_USB_EP3FSR (*(vuint32_t*)(&__MBAR[0x00B4E4])) -#define MCF_USB_EP4FSR (*(vuint32_t*)(&__MBAR[0x00B514])) -#define MCF_USB_EP5FSR (*(vuint32_t*)(&__MBAR[0x00B544])) -#define MCF_USB_EP6FSR (*(vuint32_t*)(&__MBAR[0x00B574])) -#define MCF_USB_EPnFSR(x) (*(vuint32_t*)(&__MBAR[0x00B454+((x)*0x030)])) -#define MCF_USB_EP0FCR (*(vuint32_t*)(&__MBAR[0x00B458])) -#define MCF_USB_EP1FCR (*(vuint32_t*)(&__MBAR[0x00B488])) -#define MCF_USB_EP2FCR (*(vuint32_t*)(&__MBAR[0x00B4B8])) -#define MCF_USB_EP3FCR (*(vuint32_t*)(&__MBAR[0x00B4E8])) -#define MCF_USB_EP4FCR (*(vuint32_t*)(&__MBAR[0x00B518])) -#define MCF_USB_EP5FCR (*(vuint32_t*)(&__MBAR[0x00B548])) -#define MCF_USB_EP6FCR (*(vuint32_t*)(&__MBAR[0x00B578])) -#define MCF_USB_EPnFCR(x) (*(vuint32_t*)(&__MBAR[0x00B458+((x)*0x030)])) -#define MCF_USB_EP0FAR (*(vuint32_t*)(&__MBAR[0x00B45C])) -#define MCF_USB_EP1FAR (*(vuint32_t*)(&__MBAR[0x00B48C])) -#define MCF_USB_EP2FAR (*(vuint32_t*)(&__MBAR[0x00B4BC])) -#define MCF_USB_EP3FAR (*(vuint32_t*)(&__MBAR[0x00B4EC])) -#define MCF_USB_EP4FAR (*(vuint32_t*)(&__MBAR[0x00B51C])) -#define MCF_USB_EP5FAR (*(vuint32_t*)(&__MBAR[0x00B54C])) -#define MCF_USB_EP6FAR (*(vuint32_t*)(&__MBAR[0x00B57C])) -#define MCF_USB_EPnFAR(x) (*(vuint32_t*)(&__MBAR[0x00B45C+((x)*0x030)])) -#define MCF_USB_EP0FRP (*(vuint32_t*)(&__MBAR[0x00B460])) -#define MCF_USB_EP1FRP (*(vuint32_t*)(&__MBAR[0x00B490])) -#define MCF_USB_EP2FRP (*(vuint32_t*)(&__MBAR[0x00B4C0])) -#define MCF_USB_EP3FRP (*(vuint32_t*)(&__MBAR[0x00B4F0])) -#define MCF_USB_EP4FRP (*(vuint32_t*)(&__MBAR[0x00B520])) -#define MCF_USB_EP5FRP (*(vuint32_t*)(&__MBAR[0x00B550])) -#define MCF_USB_EP6FRP (*(vuint32_t*)(&__MBAR[0x00B580])) -#define MCF_USB_EPnFRP(x) (*(vuint32_t*)(&__MBAR[0x00B460+((x)*0x030)])) -#define MCF_USB_EP0FWP (*(vuint32_t*)(&__MBAR[0x00B464])) -#define MCF_USB_EP1FWP (*(vuint32_t*)(&__MBAR[0x00B494])) -#define MCF_USB_EP2FWP (*(vuint32_t*)(&__MBAR[0x00B4C4])) -#define MCF_USB_EP3FWP (*(vuint32_t*)(&__MBAR[0x00B4F4])) -#define MCF_USB_EP4FWP (*(vuint32_t*)(&__MBAR[0x00B524])) -#define MCF_USB_EP5FWP (*(vuint32_t*)(&__MBAR[0x00B554])) -#define MCF_USB_EP6FWP (*(vuint32_t*)(&__MBAR[0x00B584])) -#define MCF_USB_EPnFWP(x) (*(vuint32_t*)(&__MBAR[0x00B464+((x)*0x030)])) -#define MCF_USB_EP0LRFP (*(vuint32_t*)(&__MBAR[0x00B468])) -#define MCF_USB_EP1LRFP (*(vuint32_t*)(&__MBAR[0x00B498])) -#define MCF_USB_EP2LRFP (*(vuint32_t*)(&__MBAR[0x00B4C8])) -#define MCF_USB_EP3LRFP (*(vuint32_t*)(&__MBAR[0x00B4F8])) -#define MCF_USB_EP4LRFP (*(vuint32_t*)(&__MBAR[0x00B528])) -#define MCF_USB_EP5LRFP (*(vuint32_t*)(&__MBAR[0x00B558])) -#define MCF_USB_EP6LRFP (*(vuint32_t*)(&__MBAR[0x00B588])) -#define MCF_USB_EPnLRFP(x) (*(vuint32_t*)(&__MBAR[0x00B468+((x)*0x030)])) -#define MCF_USB_EP0LWFP (*(vuint32_t*)(&__MBAR[0x00B46C])) -#define MCF_USB_EP1LWFP (*(vuint32_t*)(&__MBAR[0x00B49C])) -#define MCF_USB_EP2LWFP (*(vuint32_t*)(&__MBAR[0x00B4CC])) -#define MCF_USB_EP3LWFP (*(vuint32_t*)(&__MBAR[0x00B4FC])) -#define MCF_USB_EP4LWFP (*(vuint32_t*)(&__MBAR[0x00B52C])) -#define MCF_USB_EP5LWFP (*(vuint32_t*)(&__MBAR[0x00B55C])) -#define MCF_USB_EP6LWFP (*(vuint32_t*)(&__MBAR[0x00B58C])) -#define MCF_USB_EPnLWFP(x) (*(vuint32_t*)(&__MBAR[0x00B46C+((x)*0x030)])) - -/* Bit definitions and macros for MCF_USB_USBAISR */ -#define MCF_USB_USBAISR_SETUP (0x01) -#define MCF_USB_USBAISR_IN (0x02) -#define MCF_USB_USBAISR_OUT (0x04) -#define MCF_USB_USBAISR_EPHALT (0x08) -#define MCF_USB_USBAISR_TRANSERR (0x10) -#define MCF_USB_USBAISR_ACK (0x20) -#define MCF_USB_USBAISR_CTROVFL (0x40) -#define MCF_USB_USBAISR_EPSTALL (0x80) - -/* Bit definitions and macros for MCF_USB_USBAIMR */ -#define MCF_USB_USBAIMR_SETUPEN (0x01) -#define MCF_USB_USBAIMR_INEN (0x02) -#define MCF_USB_USBAIMR_OUTEN (0x04) -#define MCF_USB_USBAIMR_EPHALTEN (0x08) -#define MCF_USB_USBAIMR_TRANSERREN (0x10) -#define MCF_USB_USBAIMR_ACKEN (0x20) -#define MCF_USB_USBAIMR_CTROVFLEN (0x40) -#define MCF_USB_USBAIMR_EPSTALLEN (0x80) - -/* Bit definitions and macros for MCF_USB_EPINFO */ -#define MCF_USB_EPINFO_EPDIR (0x01) -#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x07)<<1) - -/* Bit definitions and macros for MCF_USB_CFGAR */ -#define MCF_USB_CFGAR_RESERVED (0xA0) -#define MCF_USB_CFGAR_RMTWKEUP (0xE0) - -/* Bit definitions and macros for MCF_USB_SPEEDR */ -#define MCF_USB_SPEEDR_HS (0x01) -#define MCF_USB_SPEEDR_FS (0x02) - -/* Bit definitions and macros for MCF_USB_FRMNUMR */ -#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0x0FFF)<<0) - -/* Bit definitions and macros for MCF_USB_EPTNR */ -#define MCF_USB_EPTNR_EP1T(x) (((x)&0x0003)<<0) -#define MCF_USB_EPTNR_EP2T(x) (((x)&0x0003)<<2) -#define MCF_USB_EPTNR_EP3T(x) (((x)&0x0003)<<4) -#define MCF_USB_EPTNR_EP4T(x) (((x)&0x0003)<<6) -#define MCF_USB_EPTNR_EP5T(x) (((x)&0x0003)<<8) -#define MCF_USB_EPTNR_EP6T(x) (((x)&0x0003)<<10) -#define MCF_USB_EPTNR_EPnT1 (0) -#define MCF_USB_EPTNR_EPnT2 (1) -#define MCF_USB_EPTNR_EPnT3 (2) - -/* Bit definitions and macros for MCF_USB_IFUR */ -#define MCF_USB_IFUR_ALTSET(x) (((x)&0x00FF)<<0) -#define MCF_USB_IFUR_IFNUM(x) (((x)&0x00FF)<<8) - -/* Bit definitions and macros for MCF_USB_IFRn */ -#define MCF_USB_IFRn_ALTSET(x) (((x)&0x00FF)<<0) -#define MCF_USB_IFRn_IFNUM(x) (((x)&0x00FF)<<8) - -/* Bit definitions and macros for MCF_USB_CNTOVR */ -#define MCF_USB_CNTOVR_PPCNT (0x01) -#define MCF_USB_CNTOVR_DPCNT (0x02) -#define MCF_USB_CNTOVR_CRCECNT (0x04) -#define MCF_USB_CNTOVR_BSECNT (0x08) -#define MCF_USB_CNTOVR_PIDECNT (0x10) -#define MCF_USB_CNTOVR_FRMECNT (0x20) -#define MCF_USB_CNTOVR_TXPCNT (0x40) - -/* Bit definitions and macros for MCF_USB_EP0ACR */ -#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x03)<<0) -#define MCF_USB_EP0ACR_TTYPE_CTRL (0) -#define MCF_USB_EP0ACR_TTYPE_ISOC (1) -#define MCF_USB_EP0ACR_TTYPE_BULK (2) -#define MCF_USB_EP0ACR_TTYPE_INT (3) - -/* Bit definitions and macros for MCF_USB_EP0MPSR */ -#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) -#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x0003)<<11) - -/* Bit definitions and macros for MCF_USB_EP0SR */ -#define MCF_USB_EP0SR_HALT (0x01) -#define MCF_USB_EP0SR_ACTIVE (0x02) -#define MCF_USB_EP0SR_PSTALL (0x04) -#define MCF_USB_EP0SR_CCOMP (0x08) -#define MCF_USB_EP0SR_TXZERO (0x20) -#define MCF_USB_EP0SR_INT (0x80) - -/* Bit definitions and macros for MCF_USB_BMRTR */ -#define MCF_USB_BMRTR_DIR (0x80) -#define MCF_USB_BMRTR_TYPE_STANDARD (0x00) -#define MCF_USB_BMRTR_TYPE_CLASS (0x20) -#define MCF_USB_BMRTR_TYPE_VENDOR (0x40) -#define MCF_USB_BMRTR_REC_DEVICE (0x00) -#define MCF_USB_BMRTR_REC_INTERFACE (0x01) -#define MCF_USB_BMRTR_REC_ENDPOINT (0x02) -#define MCF_USB_BMRTR_REC_OTHER (0x03) - -/* Bit definitions and macros for MCF_USB_EPnOUTACR */ -#define MCF_USB_EPnOUTACR_TTYPE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_USB_EPnOUTMPSR */ -#define MCF_USB_EPnOUTMPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) -#define MCF_USB_EPnOUTMPSR_ADDTRANS(x) (((x)&0x0003)<<11) - -/* Bit definitions and macros for MCF_USB_EPnOUTSR */ -#define MCF_USB_EPnOUTSR_HALT (0x01) -#define MCF_USB_EPnOUTSR_ACTIVE (0x02) -#define MCF_USB_EPnOUTSR_PSTALL (0x04) -#define MCF_USB_EPnOUTSR_CCOMP (0x08) -#define MCF_USB_EPnOUTSR_TXZERO (0x20) -#define MCF_USB_EPnOUTSR_INT (0x80) - -/* Bit definitions and macros for MCF_USB_EPnOUTSFR */ -#define MCF_USB_EPnOUTSFR_FRMNUM(x) (((x)&0x07FF)<<0) - -/* Bit definitions and macros for MCF_USB_EPnINACR */ -#define MCF_USB_EPnINACR_TTYPE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_USB_EPnINMPSR */ -#define MCF_USB_EPnINMPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) -#define MCF_USB_EPnINMPSR_ADDTRANS(x) (((x)&0x0003)<<11) - -/* Bit definitions and macros for MCF_USB_EPnINSR */ -#define MCF_USB_EPnINSR_HALT (0x01) -#define MCF_USB_EPnINSR_ACTIVE (0x02) -#define MCF_USB_EPnINSR_PSTALL (0x04) -#define MCF_USB_EPnINSR_CCOMP (0x08) -#define MCF_USB_EPnINSR_TXZERO (0x20) -#define MCF_USB_EPnINSR_INT (0x80) - -/* Bit definitions and macros for MCF_USB_EPnINSFR */ -#define MCF_USB_EPnINSFR_FRMNUM(x) (((x)&0x07FF)<<0) - -/* Bit definitions and macros for MCF_USB_USBSR */ -#define MCF_USB_USBSR_SUSP (0x00000080) -#define MCF_USB_USBSR_ISOERREP (0x0000000F) - -/* Bit definitions and macros for MCF_USB_USBCR */ -#define MCF_USB_USBCR_RESUME (0x00000001) -#define MCF_USB_USBCR_APPLOCK (0x00000002) -#define MCF_USB_USBCR_RST (0x00000004) -#define MCF_USB_USBCR_RAMEN (0x00000008) -#define MCF_USB_USBCR_RAMSPLIT (0x00000020) - -/* Bit definitions and macros for MCF_USB_DRAMCR */ -#define MCF_USB_DRAMCR_DADR(x) (((x)&0x000003FF)<<0) -#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x000007FF)<<16) -#define MCF_USB_DRAMCR_BSY (0x40000000) -#define MCF_USB_DRAMCR_START (0x80000000) - -/* Bit definitions and macros for MCF_USB_DRAMDR */ -#define MCF_USB_DRAMDR_DDAT(x) (((x)&0x000000FF)<<0) - -/* Bit definitions and macros for MCF_USB_USBISR */ -#define MCF_USB_USBISR_ISOERR (0x00000001) -#define MCF_USB_USBISR_FTUNLCK (0x00000002) -#define MCF_USB_USBISR_SUSP (0x00000004) -#define MCF_USB_USBISR_RES (0x00000008) -#define MCF_USB_USBISR_UPDSOF (0x00000010) -#define MCF_USB_USBISR_RSTSTOP (0x00000020) -#define MCF_USB_USBISR_SOF (0x00000040) -#define MCF_USB_USBISR_MSOF (0x00000080) - -/* Bit definitions and macros for MCF_USB_USBIMR */ -#define MCF_USB_USBIMR_ISOERR (0x00000001) -#define MCF_USB_USBIMR_FTUNLCK (0x00000002) -#define MCF_USB_USBIMR_SUSP (0x00000004) -#define MCF_USB_USBIMR_RES (0x00000008) -#define MCF_USB_USBIMR_UPDSOF (0x00000010) -#define MCF_USB_USBIMR_RSTSTOP (0x00000020) -#define MCF_USB_USBIMR_SOF (0x00000040) -#define MCF_USB_USBIMR_MSOF (0x00000080) - -/* Bit definitions and macros for MCF_USB_EPnSTAT */ -#define MCF_USB_EPnSTAT_RST (0x00000001) -#define MCF_USB_EPnSTAT_FLUSH (0x00000002) -#define MCF_USB_EPnSTAT_DIR (0x00000080) -#define MCF_USB_EPnSTAT_BYTECNT(x) (((x)&0x00000FFF)<<16) - -/* Bit definitions and macros for MCF_USB_EPnISR */ -#define MCF_USB_EPnISR_EOF (0x00000001) -#define MCF_USB_EPnISR_EOT (0x00000004) -#define MCF_USB_EPnISR_FIFOLO (0x00000010) -#define MCF_USB_EPnISR_FIFOHI (0x00000020) -#define MCF_USB_EPnISR_ERR (0x00000040) -#define MCF_USB_EPnISR_EMT (0x00000080) -#define MCF_USB_EPnISR_FU (0x00000100) - -/* Bit definitions and macros for MCF_USB_EPnIMR */ -#define MCF_USB_EPnIMR_EOF (0x00000001) -#define MCF_USB_EPnIMR_EOT (0x00000004) -#define MCF_USB_EPnIMR_FIFOLO (0x00000010) -#define MCF_USB_EPnIMR_FIFOHI (0x00000020) -#define MCF_USB_EPnIMR_ERR (0x00000040) -#define MCF_USB_EPnIMR_EMT (0x00000080) -#define MCF_USB_EPnIMR_FU (0x00000100) - -/* Bit definitions and macros for MCF_USB_EPnFRCFGR */ -#define MCF_USB_EPnFRCFGR_DEPTH(x) (((x)&0x00001FFF)<<0) -#define MCF_USB_EPnFRCFGR_BASE(x) (((x)&0x00000FFF)<<16) - -/* Bit definitions and macros for MCF_USB_EPnFSR */ -#define MCF_USB_EPnFSR_EMT (0x00010000) -#define MCF_USB_EPnFSR_ALRM (0x00020000) -#define MCF_USB_EPnFSR_FR (0x00040000) -#define MCF_USB_EPnFSR_FU (0x00080000) -#define MCF_USB_EPnFSR_OF (0x00100000) -#define MCF_USB_EPnFSR_UF (0x00200000) -#define MCF_USB_EPnFSR_RXW (0x00400000) -#define MCF_USB_EPnFSR_FAE (0x00800000) -#define MCF_USB_EPnFSR_FRM(x) (((x)&0x0000000F)<<24) -#define MCF_USB_EPnFSR_TXW (0x40000000) -#define MCF_USB_EPnFSR_IP (0x80000000) - -/* Bit definitions and macros for MCF_USB_EPnFCR */ -#define MCF_USB_EPnFCR_COUNTER(x) (((x)&0x0000FFFF)<<0) -#define MCF_USB_EPnFCR_TXWMSK (0x00040000) -#define MCF_USB_EPnFCR_OFMSK (0x00080000) -#define MCF_USB_EPnFCR_UFMSK (0x00100000) -#define MCF_USB_EPnFCR_RXWMSK (0x00200000) -#define MCF_USB_EPnFCR_FAEMSK (0x00400000) -#define MCF_USB_EPnFCR_IPMSK (0x00800000) -#define MCF_USB_EPnFCR_GR(x) (((x)&0x00000007)<<24) -#define MCF_USB_EPnFCR_FRM (0x08000000) -#define MCF_USB_EPnFCR_TMR (0x10000000) -#define MCF_USB_EPnFCR_WFR (0x20000000) -#define MCF_USB_EPnFCR_SHAD (0x80000000) - -/* Bit definitions and macros for MCF_USB_EPnFAR */ -#define MCF_USB_EPnFAR_ALRMP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_USB_EPnFRP */ -#define MCF_USB_EPnFRP_RP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_USB_EPnFWP */ -#define MCF_USB_EPnFWP_WP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_USB_EPnLRFP */ -#define MCF_USB_EPnLRFP_LRFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_USB_EPnLWFP */ -#define MCF_USB_EPnLWFP_LWFP(x) (((x)&0x00000FFF)<<0) - - -#endif /* __MCF548X_USB_H__ */ diff --git a/include/asm-m68k/coldfire/mcf548x/mcf548x_xlbarb.h b/include/asm-m68k/coldfire/mcf548x/mcf548x_xlbarb.h deleted file mode 100644 index 08c83765f5..0000000000 --- a/include/asm-m68k/coldfire/mcf548x/mcf548x_xlbarb.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * XLB bus arbiter - */ -#ifndef __MCF548X_XLBARB_H__ -#define __MCF548X_XLBARB_H__ - -/* - * XLB arbiter register - */ -#define MCF_XLBARB_ACFG (*(vuint32*)(&__MBAR[0x000240])) -#define MCF_XLBARB_VER (*(vuint32*)(&__MBAR[0x000244])) -#define MCF_XLBARB_STA (*(vuint32*)(&__MBAR[0x000248])) -#define MCF_XLBARB_INTEN (*(vuint32*)(&__MBAR[0x00024C])) -#define MCF_XLBARB_ADRCAP (*(vuint32*)(&__MBAR[0x000250])) -#define MCF_XLBARB_SIGCAP (*(vuint32*)(&__MBAR[0x000254])) -#define MCF_XLBARB_ADRTO (*(vuint32*)(&__MBAR[0x000258])) -#define MCF_XLBARB_DATTO (*(vuint32*)(&__MBAR[0x00025C])) -#define MCF_XLBARB_BUSTO (*(vuint32*)(&__MBAR[0x000260])) -#define MCF_XLBARB_PRIEN (*(vuint32*)(&__MBAR[0x000264])) -#define MCF_XLBARB_PRI (*(vuint32*)(&__MBAR[0x000268])) -#define MCF_XLBARB_BAR (*(vuint32*)(&__MBAR[0x00026C])) - - -#endif /* __MCF548X_XLBARB_H__ */ diff --git a/include/asm-m68k/coldfire/mcf5xxx.h b/include/asm-m68k/coldfire/mcf5xxx.h deleted file mode 100644 index 4e239a31d3..0000000000 --- a/include/asm-m68k/coldfire/mcf5xxx.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Definitions common across all ColdFire processors - */ -#ifndef __MCF5XXX__H -#define __MCF5XXX__H - -/* - * Common M68K & ColdFire definitions - */ -#define ADDRESS uint32_t -#define INSTRUCTION uint16_t -#define ILLEGAL 0x4AFC -#define CPU_WORD_SIZE 16 - -/* - * Definitions for CPU status register (SR) - */ -#define MCF5XXX_SR_T (0x8000) -#define MCF5XXX_SR_S (0x2000) -#define MCF5XXX_SR_M (0x1000) -#define MCF5XXX_SR_IPL (0x0700) -#define MCF5XXX_SR_IPL_0 (0x0000) -#define MCF5XXX_SR_IPL_1 (0x0100) -#define MCF5XXX_SR_IPL_2 (0x0200) -#define MCF5XXX_SR_IPL_3 (0x0300) -#define MCF5XXX_SR_IPL_4 (0x0400) -#define MCF5XXX_SR_IPL_5 (0x0500) -#define MCF5XXX_SR_IPL_6 (0x0600) -#define MCF5XXX_SR_IPL_7 (0x0700) -#define MCF5XXX_SR_X (0x0010) -#define MCF5XXX_SR_N (0x0008) -#define MCF5XXX_SR_Z (0x0004) -#define MCF5XXX_SR_V (0x0002) -#define MCF5XXX_SR_C (0x0001) - -/* - * Definitions for CPU cache control register - */ -#define MCF5XXX_CACR_CENB (0x80000000) -#define MCF5XXX_CACR_DEC (0x80000000) -#define MCF5XXX_CACR_DW (0x40000000) -#define MCF5XXX_CACR_DESB (0x20000000) -#define MCF5XXX_CACR_CPDI (0x10000000) -#define MCF5XXX_CACR_DDPI (0x10000000) -#define MCF5XXX_CACR_CPD (0x10000000) -#define MCF5XXX_CACR_CFRZ (0x08000000) -#define MCF5XXX_CACR_DHLCK (0x08000000) -#define MCF5XXX_CACR_DDCM_WT (0x00000000) -#define MCF5XXX_CACR_DDCM_CB (0x02000000) -#define MCF5XXX_CACR_DDCM_IP (0x04000000) -#define MCF5XXX_CACR_DDCM_II (0x06000000) -#define MCF5XXX_CACR_CINV (0x01000000) -#define MCF5XXX_CACR_DCINVA (0x01000000) -#define MCF5XXX_CACR_DIDI (0x00800000) -#define MCF5XXX_CACR_DDSP (0x00800000) -#define MCF5XXX_CACR_DISD (0x00400000) -#define MCF5XXX_CACR_INVI (0x00200000) -#define MCF5XXX_CACR_INVD (0x00100000) -#define MCF5XXX_CACR_BEC (0x00080000) -#define MCF5XXX_CACR_BCINVA (0x00040000) -#define MCF5XXX_CACR_IEC (0x00008000) -#define MCF5XXX_CACR_DNFB (0x00002000) -#define MCF5XXX_CACR_IDPI (0x00001000) -#define MCF5XXX_CACR_IHLCK (0x00000800) -#define MCF5XXX_CACR_CEIB (0x00000400) -#define MCF5XXX_CACR_IDCM (0x00000400) -#define MCF5XXX_CACR_DCM_WR (0x00000000) -#define MCF5XXX_CACR_DCM_CB (0x00000100) -#define MCF5XXX_CACR_DCM_IP (0x00000200) -#define MCF5XXX_CACR_DCM (0x00000200) -#define MCF5XXX_CACR_DCM_II (0x00000300) -#define MCF5XXX_CACR_DBWE (0x00000100) -#define MCF5XXX_CACR_ICINVA (0x00000100) -#define MCF5XXX_CACR_IDSP (0x00000080) -#define MCF5XXX_CACR_DWP (0x00000020) -#define MCF5XXX_CACR_EUSP (0x00000020) -#define MCF5XXX_CACR_EUST (0x00000020) -#define MCF5XXX_CACR_DF (0x00000010) -#define MCF5XXX_CACR_CLNF_00 (0x00000000) -#define MCF5XXX_CACR_CLNF_01 (0x00000002) -#define MCF5XXX_CACR_CLNF_10 (0x00000004) -#define MCF5XXX_CACR_CLNF_11 (0x00000006) - -/* - * Definition for CPU access control register - */ -#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) -#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) -#define MCF5XXX_ACR_EN (0x00008000) -#define MCF5XXX_ACR_SM_USER (0x00000000) -#define MCF5XXX_ACR_SM_SUPER (0x00002000) -#define MCF5XXX_ACR_SM_IGNORE (0x00006000) -#define MCF5XXX_ACR_ENIB (0x00000080) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_DCM_WR (0x00000000) -#define MCF5XXX_ACR_DCM_CB (0x00000020) -#define MCF5XXX_ACR_DCM_IP (0x00000040) -#define MCF5XXX_ACR_DCM_II (0x00000060) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_BWE (0x00000020) -#define MCF5XXX_ACR_WP (0x00000004) - -/* - * Definitions for CPU core sram control registers - */ -#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) -#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) -#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) -#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) -#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) -#define MCF5XXX_RAMBAR_WP (0x00000100) -#define MCF5XXX_RAMBAR_CI (0x00000020) -#define MCF5XXX_RAMBAR_SC (0x00000010) -#define MCF5XXX_RAMBAR_SD (0x00000008) -#define MCF5XXX_RAMBAR_UC (0x00000004) -#define MCF5XXX_RAMBAR_UD (0x00000002) -#define MCF5XXX_RAMBAR_V (0x00000001) - - -#ifndef __ASSEMBLY__ - -extern char __MBAR[]; - - -/* - * Extention to thhe basic POSIX data types - */ -typedef volatile uint8_t vuint8_t; /* 8 bits */ -typedef volatile uint16_t vuint16_t; /* 16 bits */ -typedef volatile uint32_t vuint32_t; /* 32 bits */ - -/* - * Routines and macros for accessing Input/Output devices - */ - -#define mcf_iord_8(ADDR) *((vuint8_t *)(ADDR)) -#define mcf_iord_16(ADDR) *((vuint16_t *)(ADDR)) -#define mcf_iord_32(ADDR) *((vuint32_t *)(ADDR)) - -#define mcf_iowr_8(ADDR,DATA) *((vuint8_t *)(ADDR)) = (DATA) -#define mcf_iowr_16(ADDR,DATA) *((vuint16_t *)(ADDR)) = (DATA) -#define mcf_iowr_32(ADDR,DATA) *((vuint32_t *)(ADDR)) = (DATA) - -/* - * The ColdFire family of processors has a simplified exception stack - * frame that looks like the following: - * - * 3322222222221111 111111 - * 1098765432109876 5432109876543210 - * 8 +----------------+----------------+ - * | Program Counter | - * 4 +----------------+----------------+ - * |FS/Fmt/Vector/FS| SR | - * SP --> 0 +----------------+----------------+ - * - * The stack self-aligns to a 4-byte boundary at an exception, with - * the FS/Fmt/Vector/FS field indicating the size of the adjustment - * (SP += 0,1,2,3 bytes). - */ -#define MCF5XXX_RD_SF_FORMAT(PTR) \ - ((*((uint16_t *)(PTR)) >> 12) & 0x00FF) - -#define MCF5XXX_RD_SF_VECTOR(PTR) \ - ((*((uint16_t *)(PTR)) >> 2) & 0x00FF) - -#define MCF5XXX_RD_SF_FS(PTR) \ - ( ((*((uint16_t *)(PTR)) & 0x0C00) >> 8) | (*((uint16_t *)(PTR)) & 0x0003) ) - -#define MCF5XXX_SF_SR(PTR) *((uint16_t *)(PTR)+1) -#define MCF5XXX_SF_PC(PTR) *((uint32_t *)(PTR)+1) - -/* - * Functions provided as inline code to access supervisor mode - * registers from C. - * - * Note: Most registers are write-only. So you must use shadow registers in - * RAM to track the state of each register! - */ -static __inline__ uint16_t mcf5xxx_rd_sr(void) { uint16_t rc; __asm__ __volatile__( "move.w %%sr,%0\n" : "=r" (rc) ); return rc; } -static __inline__ void mcf5xxx_wr_sr(uint16_t value) { __asm__ __volatile__( "move.w %0,%%sr\n" : : "r" (value) ); } - -static __inline__ int asm_set_ipl(uint32_t value) -{ - uint32_t oldipl,newipl; - value = (value & 0x7) << 8U; - oldipl = mcf5xxx_rd_sr(); - newipl = oldipl & ~0x0700U; - newipl |= value; - mcf5xxx_wr_sr(newipl); - oldipl = (oldipl & 0x0700U) >> 8U; - return oldipl; -} - -static __inline__ void mcf5xxx_cpushl_bc(uint32_t* value) { __asm__ __volatile__( " move.l %0,%%a0 \n .word 0xF4E8\n nop\n" : : "a" (value) : "a0"); } - // cpushl bc,%%a0@ ??? - -static __inline__ void mcf5xxx_wr_cacr(uint32_t value) { __asm__ __volatile__( "movec %0,%%cacr\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_asid(uint32_t value) { __asm__ __volatile__( "movec %0,%%asid\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acr0(uint32_t value) { __asm__ __volatile__( "movec %0,#4\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acr1(uint32_t value) { __asm__ __volatile__( "movec %0,#5\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acr2(uint32_t value) { __asm__ __volatile__( "movec %0,#6\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acr3(uint32_t value) { __asm__ __volatile__( "movec %0,#7\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_mmubar(uint32_t value) { __asm__ __volatile__( "movec %0,%%mmubar\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_other_a7(uint32_t value) { __asm__ __volatile__( "movec %0,%%other_sp\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_vbr(uint32_t value) { __asm__ __volatile__( "movec %0,%%vbr\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_macsr(uint32_t value) { __asm__ __volatile__( "movec %0,%%macsr\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_mask(uint32_t value) { __asm__ __volatile__( "movec %0,%%mask\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acc0(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc0\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_accext01(uint32_t value) { __asm__ __volatile__( "movec %0,%%accext01\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_accext23(uint32_t value) { __asm__ __volatile__( "movec %0,%%accext23\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acc1(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc1\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acc2(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc2\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acc3(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc3\n nop\n" : : "r" (value) ); } -//static __inline__ void mcf5xxx_wr_sr(uint32_t value) { __asm__ __volatile__( "movec %0,%%sr\n nop\n" : : "r" (value) ); } -//static __inline__ void mcf5xxx_wr_pc(uint32_t value) { __asm__ __volatile__( "movec %0,#0x080F\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_rombar0(uint32_t value) { __asm__ __volatile__( "movec %0,%%rombar0\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_rombar1(uint32_t value) { __asm__ __volatile__( "movec %0,%%rombar1\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_rambar0(uint32_t value) { __asm__ __volatile__( "movec %0,%%rambar0\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_rambar1(uint32_t value) { __asm__ __volatile__( "movec %0,%%rambar1\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_mpcr(uint32_t value) { __asm__ __volatile__( "movec %0,%%mpcr\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_secmbar(uint32_t value) { __asm__ __volatile__( "movec %0,%%mbar1\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_mbar(uint32_t value) { __asm__ __volatile__( "movec %0,%%mbar0\n nop\n" : : "r" (value) ); } - -#endif - -/* - * Now do specific ColdFire processor - */ - -#if (defined(CONFIG_ARCH_MCF54xx)) -#include "asm/coldfire/mcf548x.h" - -#else -#error "Error: Yet unsupported ColdFire processor." -#endif - - -#endif /* __MCF5XXX__H */ diff --git a/include/asm-m68k/common.h b/include/asm-m68k/common.h deleted file mode 100644 index 4cd02ad752..0000000000 --- a/include/asm-m68k/common.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Common include file wrapper for m68k architecture - */ - -/* nothing */ diff --git a/include/asm-m68k/elf.h b/include/asm-m68k/elf.h deleted file mode 100644 index 310179d71d..0000000000 --- a/include/asm-m68k/elf.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Defines for M68k ELF Files - */ -#ifndef __ASMm68k_ELF_H -#define __ASMm68k_ELF_H - -/* - * ELF register definitions.. - */ - -//#include <linux/config.h> -#include <asm/ptrace.h> -//#include <asm/user.h> - -/* - * 68k ELF relocation types - */ -#define R_68K_NONE 0 -#define R_68K_32 1 -#define R_68K_16 2 -#define R_68K_8 3 -#define R_68K_PC32 4 -#define R_68K_PC16 5 -#define R_68K_PC8 6 -#define R_68K_GOT32 7 -#define R_68K_GOT16 8 -#define R_68K_GOT8 9 -#define R_68K_GOT32O 10 -#define R_68K_GOT16O 11 -#define R_68K_GOT8O 12 -#define R_68K_PLT32 13 -#define R_68K_PLT16 14 -#define R_68K_PLT8 15 -#define R_68K_PLT32O 16 -#define R_68K_PLT16O 17 -#define R_68K_PLT8O 18 -#define R_68K_COPY 19 -#define R_68K_GLOB_DAT 20 -#define R_68K_JMP_SLOT 21 -#define R_68K_RELATIVE 22 - -typedef unsigned long elf_greg_t; - -//#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) -#define ELF_NGREG 20 -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -typedef struct user_m68kfp_struct elf_fpregset_t; - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) ((x)->e_machine == EM_68K) - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 -#define ELF_DATA ELFDATA2MSB -#define ELF_ARCH EM_68K - -/* For SVR4/m68k the function pointer to be registered with `atexit' is - passed in %a1. Although my copy of the ABI has no such statement, it - is actually used on ASV. */ -#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0 - -#define USE_ELF_CORE_DUMP -#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) -#define ELF_EXEC_PAGESIZE 4096 -#else -#define ELF_EXEC_PAGESIZE 8192 -#endif - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#ifndef CONFIG_SUN3 -#define ELF_ET_DYN_BASE 0xD0000000UL -#else -#define ELF_ET_DYN_BASE 0x0D800000UL -#endif - -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ - /* Bleech. */ \ - pr_reg[0] = regs->d1; \ - pr_reg[1] = regs->d2; \ - pr_reg[2] = regs->d3; \ - pr_reg[3] = regs->d4; \ - pr_reg[4] = regs->d5; \ - pr_reg[7] = regs->a0; \ - pr_reg[8] = regs->a1; \ - pr_reg[9] = regs->a2; \ - pr_reg[14] = regs->d0; \ - pr_reg[15] = rdusp(); \ - pr_reg[16] = regs->orig_d0; \ - pr_reg[17] = regs->sr; \ - pr_reg[18] = regs->pc; \ - pr_reg[19] = (regs->format << 12) | regs->vector; \ - { \ - struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \ - pr_reg[5] = sw->d6; \ - pr_reg[6] = sw->d7; \ - pr_reg[10] = sw->a3; \ - pr_reg[11] = sw->a4; \ - pr_reg[12] = sw->a5; \ - pr_reg[13] = sw->a6; \ - } - -/* This yields a mask that user programs can use to figure out what - instruction set this cpu supports. */ - -#define ELF_HWCAP (0) - -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. */ - -#define ELF_PLATFORM (NULL) - -#ifdef __KERNEL__ -#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX) -#endif - -#endif diff --git a/include/asm-m68k/hardware.h b/include/asm-m68k/hardware.h deleted file mode 100644 index 54cec0ee20..0000000000 --- a/include/asm-m68k/hardware.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Common hardware definitions - */ - -#ifndef __M68K_HARDWARE_H -#define __M68K_HARDWARE_H - -#include <asm/arch/hardware.h> - -#endif diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h deleted file mode 100644 index 7bbd2fe0f9..0000000000 --- a/include/asm-m68k/io.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ -#ifndef __ASM_M68K_IO_H -#define __ASM_M68K_IO_H - -#ifdef __KERNEL__ - -#include <linux/types.h> -#include <asm/byteorder.h> -#include <asm/memory.h> - -/* - */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); -extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); -extern void __raw_writesl(unsigned int addr, const void *data, int longlen); - -extern void __raw_readsb(unsigned int addr, void *data, int bytelen); -extern void __raw_readsw(unsigned int addr, void *data, int wordlen); -extern void __raw_readsl(unsigned int addr, void *data, int longlen); - -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -#define writeb(v,a) __arch_putb(v,a) -#define writew(v,a) __arch_putw(v,a) -#define writel(v,a) __arch_putl(v,a) - -#define readb(a) __arch_getb(a) -#define readw(a) __arch_getw(a) -#define readl(a) __arch_getl(a) - -/* - * The compiler seems to be incapable of optimising constants - * properly. Spell it out to the compiler in some cases. - * These are only valid for small values of "off" (< 1<<12) - */ -#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) -#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) -#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) - -#define __raw_base_readb(base,off) __arch_base_getb(base,off) -#define __raw_base_readw(base,off) __arch_base_getw(base,off) -#define __raw_base_readl(base,off) __arch_base_getl(base,off) - -/* - * Now, pick up the machine-defined IO definitions - */ - -/* - * IO port access primitives - * ------------------------- - * - * The M68k doesn't have special IO access instructions; all IO is memory - * mapped. Note that these are defined to perform little endian accesses - * only. Their primary purpose is to access PCI and ISA peripherals. - * - * Note that for a big endian machine, this implies that the following - * big endian mode connectivity is in place, as described by numerious - * ARM documents: - * - * PCI: D0-D7 D8-D15 D16-D23 D24-D31 - * ARM: D24-D31 D16-D23 D8-D15 D0-D7 - * - * The machine specific io.h include defines __io to translate an "IO" - * address to a memory address. - * - * Note that we prevent GCC re-ordering or caching values in expressions - * by introducing sequence points into the in*() definitions. Note that - * __raw_* do not guarantee this behaviour. - * - * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. - */ -#ifdef __io -#define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) -#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) - -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) -#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) - -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) -#define outsl(p,d,l) __raw_writesl(__io(p),d,l) - -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -#define insl(p,d,l) __raw_readsl(__io(p),d,l) -#endif - -#define outb_p(val,port) outb((val),(port)) -#define outw_p(val,port) outw((val),(port)) -#define outl_p(val,port) outl((val),(port)) -#define inb_p(port) inb((port)) -#define inw_p(port) inw((port)) -#define inl_p(port) inl((port)) - -#define outsb_p(port,from,len) outsb(port,from,len) -#define outsw_p(port,from,len) outsw(port,from,len) -#define outsl_p(port,from,len) outsl(port,from,len) -#define insb_p(port,to,len) insb(port,to,len) -#define insw_p(port,to,len) insw(port,to,len) -#define insl_p(port,to,len) insl(port,to,len) - -/* - * ioremap and friends. - * - * ioremap takes a PCI memory address, as specified in - * linux/Documentation/IO-mapping.txt. If you want a - * physical address, use __ioremap instead. - */ -extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); -extern void __iounmap(void *addr); - -/* - * Generic ioremap support. - * - * Define: - * iomem_valid_addr(off,size) - * iomem_to_phys(off) - */ -#ifdef iomem_valid_addr -#define __arch_ioremap(off,sz,nocache) \ - ({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off),_size,0); \ - _ret; \ - }) - -#define __arch_iounmap __iounmap -#endif - -#define ioremap(off,sz) __arch_ioremap((off),(sz),0) -#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) -#define iounmap(_addr) __arch_iounmap(_addr) - -/* - * DMA-consistent mapping functions. These allocate/free a region of - * uncached, unwrite-buffered mapped memory space for use with DMA - * devices. This is the "generic" version. The PCI specific version - * is in pci.h - */ -extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); -extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); -extern void consistent_sync(void *vaddr, size_t size, int rw); - -/* - * String version of IO memory access ops: - */ -extern void _memcpy_fromio(void *, unsigned long, size_t); -extern void _memcpy_toio(unsigned long, const void *, size_t); -extern void _memset_io(unsigned long, int, size_t); - -extern void __readwrite_bug(const char *fn); - -/* - * If this architecture has PCI memory IO, then define the read/write - * macros. These should only be used with the cookie passed from - * ioremap. - */ -#ifdef __mem_pci - -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) - -#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) -#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) -#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) - -#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) -#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) -#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) - -#define eth_io_copy_and_sum(s,c,l,b) \ - eth_copy_and_sum((s),__mem_pci(c),(l),(b)) - -static inline int -check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#elif !defined(readb) - -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") - -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") - -#define check_signature(io,sig,len) (0) - -#endif /* __mem_pci */ - -/* - * If this architecture has ISA IO, then define the isa_read/isa_write - * macros. - */ -#ifdef __mem_isa - -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) -#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) -#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) -#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) -#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - eth_copy_and_sum((a),__mem_isa(b),(c),(d)) - -static inline int -isa_check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (isa_readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#else /* __mem_isa */ - -#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) -#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) -#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) -#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") -#define isa_writew(val,addr) __readwrite_bug("isa_writew") -#define isa_writel(val,addr) __readwrite_bug("isa_writel") -#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") -#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") -#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - __readwrite_bug("isa_eth_io_copy_and_sum") - -#define isa_check_signature(io,sig,len) (0) - -#endif /* __mem_isa */ -#endif /* __KERNEL__ */ -#endif /* __ASM_M68K_IO_H */ diff --git a/include/asm-m68k/mach-types.h b/include/asm-m68k/mach-types.h deleted file mode 100644 index d221fcc892..0000000000 --- a/include/asm-m68k/mach-types.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This was automagically generated from arch/m68k/tools/mach-types! - * Do NOT edit - */ - -#ifndef __ASM_M68K_MACH_TYPE_H -#define __ASM_M68K_MACH_TYPE_H - -#ifndef __ASSEMBLY__ -/* The type of machine we're running on */ -extern unsigned int __machine_arch_type; -#endif - -/* see arch/m68k/kernel/arch.c for a description of these */ -#define MACH_TYPE_GENERIC 0 -#define MACH_TYPE_MCF54xx 1 -#define MACH_TYPE_MCF5445x 2 - -#ifdef CONFIG_ARCH_MCF54xx -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MCF54xx -# endif -# define machine_is_mcf54xx() (machine_arch_type == MACH_TYPE_MCF54xx) -#else -# define machine_is_mcf54xx() (0) -#endif - -#ifdef CONFIG_ARCH_MCF5445x -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MCF5445x -# endif -# define machine_is_mcf5445x() (machine_arch_type == MACH_TYPE_MCF5445x) -#else -# define machine_is_mcf5445x() (0) -#endif - - -#ifndef machine_arch_type -#define machine_arch_type __machine_arch_type -#endif - -#endif diff --git a/include/asm-m68k/memory.h b/include/asm-m68k/memory.h deleted file mode 100644 index cb60515a71..0000000000 --- a/include/asm-m68k/memory.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Note: this file should not be included by non-asm/.h files - */ -#ifndef __ASM_M68K_MEMORY_H -#define __ASM_M68K_MEMORY_H - - -#endif /* __ASM_M68K_MEMORY_H */ diff --git a/include/asm-m68k/module.h b/include/asm-m68k/module.h deleted file mode 100644 index 7036a4e12e..0000000000 --- a/include/asm-m68k/module.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Defines for the ELF module loader - */ -#ifndef _ASM_M68K_MODULE_H -#define _ASM_M68K_MODULE_H - -struct mod_arch_specific -{ - int foo; -}; - -#define Elf_Shdr Elf32_Shdr -#define Elf_Sym Elf32_Sym -#define Elf_Ehdr Elf32_Ehdr - -#endif /* _ASM_M68K_MODULE_H */ diff --git a/include/asm-m68k/posix_types.h b/include/asm-m68k/posix_types.h deleted file mode 100644 index 2e85033384..0000000000 --- a/include/asm-m68k/posix_types.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ -#ifndef __ARCH_M68K_POSIX_TYPES_H -#define __ARCH_M68K_POSIX_TYPES_H - - -typedef unsigned short __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -#define __FD_SET(fd, fdsetp) \ - (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) - -#undef __FD_CLR -#define __FD_CLR(fd, fdsetp) \ - (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) - -#undef __FD_ISSET -#define __FD_ISSET(fd, fdsetp) \ - ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) \ - (memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp))) - -#endif - -#endif diff --git a/include/asm-m68k/proc-mcfv4e/dma_utils.h b/include/asm-m68k/proc-mcfv4e/dma_utils.h deleted file mode 100644 index 4ebdd558c1..0000000000 --- a/include/asm-m68k/proc-mcfv4e/dma_utils.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Declaration of support function used with the MultiChannel DMA - */ -#ifndef _DMA_UTILS_H_ -#define _DMA_UTILS_H_ - - -void dma_irq_enable(uint8_t, uint8_t); -void dma_irq_disable(void); -int dma_set_initiator(int); -uint32_t dma_get_initiator(int); -void dma_free_initiator(int); -int dma_set_channel(int, void (*)(void)); -int dma_get_channel(int); -void dma_free_channel(int); -int dma_interrupt_handler(void *, void *); - -/* - * Create identifiers for each initiator/requestor - */ -#define DMA_ALWAYS (0) -#define DMA_DSPI_RX (1) -#define DMA_DSPI_TX (2) -#define DMA_DREQ0 (3) -#define DMA_PSC0_RX (4) -#define DMA_PSC0_TX (5) -#define DMA_USBEP0 (6) -#define DMA_USBEP1 (7) -#define DMA_USBEP2 (8) -#define DMA_USBEP3 (9) -#define DMA_PCI_TX (10) -#define DMA_PCI_RX (11) -#define DMA_PSC1_RX (12) -#define DMA_PSC1_TX (13) -#define DMA_I2C_RX (14) -#define DMA_I2C_TX (15) -#define DMA_FEC0_RX (16) -#define DMA_FEC0_TX (17) -#define DMA_FEC1_RX (18) -#define DMA_FEC1_TX (19) -#define DMA_DREQ1 (20) -#define DMA_CTM0 (21) -#define DMA_CTM1 (22) -#define DMA_CTM2 (23) -#define DMA_CTM3 (24) -#define DMA_CTM4 (25) -#define DMA_CTM5 (26) -#define DMA_CTM6 (27) -#define DMA_CTM7 (28) -#define DMA_USBEP4 (29) -#define DMA_USBEP5 (30) -#define DMA_USBEP6 (31) -#define DMA_PSC2_RX (32) -#define DMA_PSC2_TX (33) -#define DMA_PSC3_RX (34) -#define DMA_PSC3_TX (35) -#define DMA_FEC_RX(x) ((x == 0) ? DMA_FEC0_RX : DMA_FEC1_RX) -#define DMA_FEC_TX(x) ((x == 0) ? DMA_FEC0_TX : DMA_FEC1_TX) - -#endif /* _DMA_UTILS_H_ */ diff --git a/include/asm-m68k/proc-mcfv4e/fec.h b/include/asm-m68k/proc-mcfv4e/fec.h deleted file mode 100644 index 4c94774381..0000000000 --- a/include/asm-m68k/proc-mcfv4e/fec.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Declaration for the Fast Ethernet Controller (FEC) - */ -#ifndef _FEC_H_ -#define _FEC_H_ - -// FIXME -#define NIF void - -/********************************************************************/ -/* MII Speed Settings */ -#define FEC_MII_10BASE_T 0 -#define FEC_MII_100BASE_TX 1 - -/* MII Duplex Settings */ -#define FEC_MII_HALF_DUPLEX 0 -#define FEC_MII_FULL_DUPLEX 1 - -/* Timeout for MII communications */ -#define FEC_MII_TIMEOUT 0x10000 - -/* External Interface Modes */ -#define FEC_MODE_7WIRE 0 -#define FEC_MODE_MII 1 -#define FEC_MODE_LOOPBACK 2 /* Internal Loopback */ - -/* - * FEC Event Log - */ -typedef struct { - int total; /* total count of errors */ - int hberr; /* heartbeat error */ - int babr; /* babbling receiver */ - int babt; /* babbling transmitter */ - int gra; /* graceful stop complete */ - int txf; /* transmit frame */ - int mii; /* MII */ - int lc; /* late collision */ - int rl; /* collision retry limit */ - int xfun; /* transmit FIFO underrrun */ - int xferr; /* transmit FIFO error */ - int rferr; /* receive FIFO error */ - int dtxf; /* DMA transmit frame */ - int drxf; /* DMA receive frame */ - int rfsw_inv; /* Invalid bit in RFSW */ - int rfsw_l; /* RFSW Last in Frame */ - int rfsw_m; /* RFSW Miss */ - int rfsw_bc; /* RFSW Broadcast */ - int rfsw_mc; /* RFSW Multicast */ - int rfsw_lg; /* RFSW Length Violation */ - int rfsw_no; /* RFSW Non-octet */ - int rfsw_cr; /* RFSW Bad CRC */ - int rfsw_ov; /* RFSW Overflow */ - int rfsw_tr; /* RFSW Truncated */ -} FEC_EVENT_LOG; - - -int fec_mii_write(uint8_t , uint8_t , uint8_t , uint16_t ); -int fec_mii_read(uint8_t , uint8_t , uint8_t , uint16_t *x); -void fec_mii_init(uint8_t, uint32_t); - -void fec_mib_init(uint8_t); -void fec_mib_dump(uint8_t); - -void fec_log_init(uint8_t); -void fec_log_dump(uint8_t); - -void fec_debug_dump(uint8_t); -void fec_duplex (uint8_t, uint8_t); - -uint8_t fec_hash_address(const uint8_t *); -void fec_set_address (uint8_t ch, const uint8_t *); - -void fec_reset (uint8_t); -void fec_init (uint8_t, uint8_t, const uint8_t *); - -void fec_rx_start(uint8_t, int8_t *); -void fec_rx_restart(uint8_t); -void fec_rx_stop (uint8_t); - -NBUF * fec_rx_frame(uint8_t ch, NIF *nif); - -void fec0_rx_frame(void); -void fec1_rx_frame(void); - -void fec_tx_start(uint8_t, int8_t *); -void fec_tx_restart(uint8_t); -void fec_tx_stop (uint8_t); - -void fec0_tx_frame(void); -void fec1_tx_frame(void); - -int fec_send(uint8_t, NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); -int fec0_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); -int fec1_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); - -void fec_irq_enable(uint8_t, uint8_t, uint8_t); -void fec_irq_disable(uint8_t); - -void fec_interrupt_handler(uint8_t); -int fec0_interrupt_handler(void *, void *); -int fec1_interrupt_handler(void *, void *); - -void fec_eth_setup(uint8_t, uint8_t, uint8_t, uint8_t, const uint8_t *); - -void fec_eth_reset(uint8_t); - -void fec_eth_stop(uint8_t); - -#endif /* _FEC_H_ */ diff --git a/include/asm-m68k/proc-mcfv4e/fecbd.h b/include/asm-m68k/proc-mcfv4e/fecbd.h deleted file mode 100644 index 92195490c8..0000000000 --- a/include/asm-m68k/proc-mcfv4e/fecbd.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Provide a simple buffer management driver - */ - -#ifndef _FECBD_H_ -#define _FECBD_H_ - -/********************************************************************/ - -#define Rx 1 -#define Tx 0 - -/* - * Buffer sizes in bytes - */ -#ifndef RX_BUF_SZ -#define RX_BUF_SZ NBUF_SZ -#endif -#ifndef TX_BUF_SZ -#define TX_BUF_SZ NBUF_SZ -#endif - -/* - * Number of Rx and Tx Buffers and Buffer Descriptors - */ -#ifndef NRXBD -#define NRXBD 10 -#endif -#ifndef NTXBD -#define NTXBD 4 -#endif - -/* - * Buffer Descriptor Format - */ -typedef struct -{ - uint16_t status; /* control and status */ - uint16_t length; /* transfer length */ - uint8_t *data; /* buffer address */ -} FECBD; - -/* - * Bit level definitions for status field of buffer descriptors - */ -#define TX_BD_R 0x8000 -#define TX_BD_TO1 0x4000 -#define TX_BD_W 0x2000 -#define TX_BD_TO2 0x1000 -#define TX_BD_INTERRUPT 0x1000 /* MCF547x/8x Only */ -#define TX_BD_L 0x0800 -#define TX_BD_TC 0x0400 -#define TX_BD_DEF 0x0200 /* MCF5272 Only */ -#define TX_BD_ABC 0x0200 -#define TX_BD_HB 0x0100 /* MCF5272 Only */ -#define TX_BD_LC 0x0080 /* MCF5272 Only */ -#define TX_BD_RL 0x0040 /* MCF5272 Only */ -#define TX_BD_UN 0x0002 /* MCF5272 Only */ -#define TX_BD_CSL 0x0001 /* MCF5272 Only */ - -#define RX_BD_E 0x8000 -#define RX_BD_R01 0x4000 -#define RX_BD_W 0x2000 -#define RX_BD_R02 0x1000 -#define RX_BD_INTERRUPT 0x1000 /* MCF547x/8x Only */ -#define RX_BD_L 0x0800 -#define RX_BD_M 0x0100 -#define RX_BD_BC 0x0080 -#define RX_BD_MC 0x0040 -#define RX_BD_LG 0x0020 -#define RX_BD_NO 0x0010 -#define RX_BD_CR 0x0004 -#define RX_BD_OV 0x0002 -#define RX_BD_TR 0x0001 -#define RX_BD_ERROR (RX_BD_NO | RX_BD_CR | RX_BD_OV | RX_BD_TR) - -/* - * Functions provided in fec_bd.c - */ -void -fecbd_init(uint8_t); - -uint32_t -fecbd_get_start(uint8_t, uint8_t); - -FECBD * -fecbd_rx_alloc(uint8_t); - -FECBD * -fecbd_tx_alloc(uint8_t); - -FECBD * -fecbd_tx_free(uint8_t); - -#endif /* _FECBD_H_ */ diff --git a/include/asm-m68k/proc-mcfv4e/mcdapi/MCD_dma.h b/include/asm-m68k/proc-mcfv4e/mcdapi/MCD_dma.h deleted file mode 100644 index 09adf8272a..0000000000 --- a/include/asm-m68k/proc-mcfv4e/mcdapi/MCD_dma.h +++ /dev/null @@ -1,379 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Main header file for multi-channel DMA API. - */ -#ifndef _MCD_API_H -#define _MCD_API_H - -/* - * Turn Execution Unit tasks ON (#define) or OFF (#undef) - */ -#undef MCD_INCLUDE_EU - -/* - * Number of DMA channels - */ -#define NCHANNELS 16 - -/* - * Total number of variants - */ -#ifdef MCD_INCLUDE_EU -#define NUMOFVARIANTS 6 -#else -#define NUMOFVARIANTS 4 -#endif - -/* - * Define sizes of the various tables - */ -#define TASK_TABLE_SIZE (NCHANNELS*32) -#define VAR_TAB_SIZE (128) -#define CONTEXT_SAVE_SIZE (128) -#define FUNCDESC_TAB_SIZE (256) - -#ifdef MCD_INCLUDE_EU -#define FUNCDESC_TAB_NUM 16 -#else -#define FUNCDESC_TAB_NUM 1 -#endif - - -#ifndef DEFINESONLY - -/* - * Portability typedefs - */ -//typedef signed int s32; -//typedef unsigned int u32; -//typedef signed short s16; -//typedef unsigned short u16; -//typedef signed char s8; -//typedef unsigned char u8; -// -/* - * These structures represent the internal registers of the - * multi-channel DMA - */ -struct dmaRegs_s { - u32 taskbar; /* task table base address register */ - u32 currPtr; - u32 endPtr; - u32 varTablePtr; - u16 dma_rsvd0; - u16 ptdControl; /* ptd control */ - u32 intPending; /* interrupt pending register */ - u32 intMask; /* interrupt mask register */ - u16 taskControl[16]; /* task control registers */ - u8 priority[32]; /* priority registers */ - u32 initiatorMux; /* initiator mux control */ - u32 taskSize0; /* task size control register 0. */ - u32 taskSize1; /* task size control register 1. */ - u32 dma_rsvd1; /* reserved */ - u32 dma_rsvd2; /* reserved */ - u32 debugComp1; /* debug comparator 1 */ - u32 debugComp2; /* debug comparator 2 */ - u32 debugControl; /* debug control */ - u32 debugStatus; /* debug status */ - u32 ptdDebug; /* priority task decode debug */ - u32 dma_rsvd3[31]; /* reserved */ -}; -typedef volatile struct dmaRegs_s dmaRegs; - -#endif - -/* - * PTD contrl reg bits - */ -#define PTD_CTL_TSK_PRI 0x8000 -#define PTD_CTL_COMM_PREFETCH 0x0001 - -/* - * Task Control reg bits and field masks - */ -#define TASK_CTL_EN 0x8000 -#define TASK_CTL_VALID 0x4000 -#define TASK_CTL_ALWAYS 0x2000 -#define TASK_CTL_INIT_MASK 0x1f00 -#define TASK_CTL_ASTRT 0x0080 -#define TASK_CTL_HIPRITSKEN 0x0040 -#define TASK_CTL_HLDINITNUM 0x0020 -#define TASK_CTL_ASTSKNUM_MASK 0x000f - -/* - * Priority reg bits and field masks - */ -#define PRIORITY_HLD 0x80 -#define PRIORITY_PRI_MASK 0x07 - -/* - * Debug Control reg bits and field masks - */ -#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000 -#define DBG_CTL_AUTO_ARM 0x00008000 -#define DBG_CTL_BREAK 0x00004000 -#define DBG_CTL_COMP1_TYP_MASK 0x00003800 -#define DBG_CTL_COMP2_TYP_MASK 0x00000070 -#define DBG_CTL_EXT_BREAK 0x00000004 -#define DBG_CTL_INT_BREAK 0x00000002 - -/* - * PTD Debug reg selector addresses - * This reg must be written with a value to show the contents of - * one of the desired internal register. - */ -#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */ -#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and - have initiators asserted */ - - -/* - * General return values - */ -#define MCD_OK 0 -#define MCD_ERROR -1 -#define MCD_TABLE_UNALIGNED -2 -#define MCD_CHANNEL_INVALID -3 - -/* - * MCD_initDma input flags - */ -#define MCD_RELOC_TASKS 0x00000001 -#define MCD_NO_RELOC_TASKS 0x00000000 -#define MCD_COMM_PREFETCH_EN 0x00000002 /* Commbus Prefetching - MCF547x/548x ONLY */ - -/* - * MCD_dmaStatus Status Values for each channel - */ -#define MCD_NO_DMA 1 /* No DMA has been requested since reset */ -#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */ -#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */ -#define MCD_PAUSED 4 /* DMA active but it is currently paused */ -#define MCD_HALTED 5 /* the most recent DMA has been killed with MCD_killTask() */ -#define MCD_DONE 6 /* the most recent DMA has completed. */ - - -/* - * MCD_startDma parameter defines - */ - -/* - * Constants for the funcDesc parameter - */ -/* Byte swapping: */ -#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */ -#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */ -#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of - each 32-bit data value being DMAed.*/ -#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each - 16-bit half of each 32-bit data value DMAed */ -#define MCD_NO_BIT_REV 0x00000000 /* do not reverse the bits of each byte DMAed. */ -#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */ -/* CRCing: */ -#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */ -#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */ -#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */ -#define MCD_CSUMINET 0xc0400000 /* to perform internet checksums on DMAed data.*/ -#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */ - -#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM) -#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM) - -/* - * Constants for the flags parameter - */ -#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */ -#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */ -#define MCD_TT_FLAGS_SP 0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY */ -#define MCD_TT_FLAGS_MASK 0x000000ff -#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW) - -#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */ -#define MCD_CHAIN_DMA /* TBD */ -#define MCD_EU_DMA /* TBD */ -#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */ -#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */ - - -/* these flags are valid for MCD_startDma and the chained buffer descriptors */ -#define MCD_BUF_READY 0x80000000 /* indicates that this buffer is now under the DMA's control */ -#define MCD_WRAP 0x20000000 /* to tell the FEC Dmas to wrap to the first BD */ -#define MCD_INTERRUPT 0x10000000 /* to generate an interrupt after completion of the DMA. */ -#define MCD_END_FRAME 0x08000000 /* tell the DMA to end the frame when transferring - last byte of data in buffer */ -#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum - prior to performing the DMA. */ - -/* Defines for the FEC buffer descriptor control/status word*/ -#define MCD_FEC_BUF_READY 0x8000 -#define MCD_FEC_WRAP 0x2000 -#define MCD_FEC_INTERRUPT 0x1000 -#define MCD_FEC_END_FRAME 0x0800 - - -/* - * Defines for general intuitiveness - */ - -#define MCD_TRUE 1 -#define MCD_FALSE 0 - -/* - * Three different cases for destination and source. - */ -#define MINUS1 -1 -#define ZERO 0 -#define PLUS1 1 - -#ifndef DEFINESONLY - -/* Task Table Entry struct*/ -typedef struct { - u32 TDTstart; /* task descriptor table start */ - u32 TDTend; /* task descriptor table end */ - u32 varTab; /* variable table start */ - u32 FDTandFlags; /* function descriptor table start and flags */ - volatile u32 descAddrAndStatus; - volatile u32 modifiedVarTab; - u32 contextSaveSpace; /* context save space start */ - u32 literalBases; -} TaskTableEntry; - - -/* Chained buffer descriptor */ -typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; -struct MCD_bufDesc_struct { - u32 flags; /* flags describing the DMA */ - u32 csumResult; /* checksum from checksumming performed since last checksum reset */ - s8 *srcAddr; /* the address to move data from */ - s8 *destAddr; /* the address to move data to */ - s8 *lastDestAddr; /* the last address written to */ - u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */ - MCD_bufDesc *next; /* next buffer descriptor in chain */ - u32 info; /* private information about this descriptor; DMA does not affect it */ -}; - -/* Progress Query struct */ -typedef volatile struct MCD_XferProg_struct { - s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */ - s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */ - u32 dmaSize; /* the amount of data transferred for the current buffer */ - MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */ -} MCD_XferProg; - - -/* FEC buffer descriptor */ -typedef volatile struct MCD_bufDescFec_struct { - u16 statCtrl; - u16 length; - u32 dataPointer; -} MCD_bufDescFec; - - -/*************************************************************************/ -/* - * API function Prototypes - see MCD_dmaApi.c for further notes - */ - -/* - * MCD_startDma starts a particular kind of DMA . - */ -int MCD_startDma ( - int channel, /* the channel on which to run the DMA */ - s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */ - s16 srcIncr, /* the amount to increment the source address per transfer */ - s8 *destAddr, /* the address to move data to */ - s16 destIncr, /* the amount to increment the destination address per transfer */ - u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */ - u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ - u32 initiator, /* what device initiates the DMA */ - int priority, /* priority of the DMA */ - u32 flags, /* flags describing the DMA */ - u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ -); - -/* - * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA - * registers, relocating and creating the appropriate task structures, and - * setting up some global settings - */ -int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags); - -/* - * MCD_dmaStatus() returns the status of the DMA on the requested channel. - */ -int MCD_dmaStatus (int channel); - -/* - * MCD_XferProgrQuery() returns progress of DMA on requested channel - */ -int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep); - -/* - * MCD_killDma() halts the DMA on the requested channel, without any - * intention of resuming the DMA. - */ -int MCD_killDma (int channel); - -/* - * MCD_continDma() continues a DMA which as stopped due to encountering an - * unready buffer descriptor. - */ -int MCD_continDma (int channel); - -/* - * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is - * running on that channel). - */ -int MCD_pauseDma (int channel); - -/* - * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is - * running on that channel). - */ -int MCD_resumeDma (int channel); - -/* - * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA - */ -int MCD_csumQuery (int channel, u32 *csum); - -/* - * MCD_getCodeSize provides the packed size required by the microcoded task - * and structures. - */ -int MCD_getCodeSize(void); - -/* - * MCD_getVersion provides a pointer to a version string and returns a - * version number. - */ -int MCD_getVersion(char **longVersion); - -/* macro for setting a location in the variable table */ -#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value - /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, - so I'm avoiding surrounding it with "do {} while(0)" */ - -#endif /* DEFINESONLY */ - -#endif /* _MCD_API_H */ diff --git a/include/asm-m68k/proc-mcfv4e/mcdapi/MCD_progCheck.h b/include/asm-m68k/proc-mcfv4e/mcdapi/MCD_progCheck.h deleted file mode 100644 index f90600c7cd..0000000000 --- a/include/asm-m68k/proc-mcfv4e/mcdapi/MCD_progCheck.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * This file is autogenerated. Do not change . - */ -#define CURRBD 4 -#define DCOUNT 6 -#define DESTPTR 5 -#define SRCPTR 7 diff --git a/include/asm-m68k/proc-mcfv4e/mcdapi/MCD_tasksInit.h b/include/asm-m68k/proc-mcfv4e/mcdapi/MCD_tasksInit.h deleted file mode 100644 index bc6ec91f98..0000000000 --- a/include/asm-m68k/proc-mcfv4e/mcdapi/MCD_tasksInit.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Declaration for the MCD tasks. Do not edit. - */ -#ifndef MCD_TSK_INIT_H -#define MCD_TSK_INIT_H 1 - -/* - * Do not edit! - */ - -/* - * Task 0 - */ -void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 1 - */ -void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 2 - */ -void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 3 - */ -void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 4 - */ -void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 5 - */ -void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel); - -#endif /* MCD_TSK_INIT_H */ diff --git a/include/asm-m68k/proc-mcfv4e/net/eth.h b/include/asm-m68k/proc-mcfv4e/net/eth.h deleted file mode 100644 index 5240c0c945..0000000000 --- a/include/asm-m68k/proc-mcfv4e/net/eth.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Declaration for for Ethernet Frames. - */ - -#ifndef _ETH_H -#define _ETH_H - - -/* Ethernet standard lengths in bytes*/ -#define ETH_ADDR_LEN (6) -#define ETH_TYPE_LEN (2) -#define ETH_CRC_LEN (4) -#define ETH_MAX_DATA (1500) -#define ETH_MIN_DATA (46) -#define ETH_HDR_LEN (ETH_ADDR_LEN * 2 + ETH_TYPE_LEN) - -/* Defined Ethernet Frame Types */ -#define ETH_FRM_IP (0x0800) -#define ETH_FRM_ARP (0x0806) -#define ETH_FRM_RARP (0x8035) -#define ETH_FRM_TEST (0xA5A5) - -/* Maximum and Minimum Ethernet Frame Sizes */ -#define ETH_MAX_FRM (ETH_HDR_LEN + ETH_MAX_DATA + ETH_CRC_LEN) -#define ETH_MIN_FRM (ETH_HDR_LEN + ETH_MIN_DATA + ETH_CRC_LEN) -#define ETH_MTU (ETH_HDR_LEN + ETH_MAX_DATA) - -/* Ethernet Addresses */ -typedef uint8_t ETH_ADDR[ETH_ADDR_LEN]; - -/* 16-bit Ethernet Frame Type, ie. Protocol */ -typedef uint16_t ETH_FRM_TYPE; - -/* Ethernet Frame Header definition */ -typedef struct -{ - ETH_ADDR dest; - ETH_ADDR src; - ETH_FRM_TYPE type; -} ETH_HDR; - -/* Ethernet Frame definition */ -typedef struct -{ - ETH_HDR head; - uint8_t* data; -} ETH_FRAME; - - -#endif /* _ETH_H */ diff --git a/include/asm-m68k/proc-mcfv4e/net/nbuf.h b/include/asm-m68k/proc-mcfv4e/net/nbuf.h deleted file mode 100644 index bc3a7a6924..0000000000 --- a/include/asm-m68k/proc-mcfv4e/net/nbuf.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Definitions for network buffer management - */ - -#ifndef _MCFV4E_NBUF_H_ -#define _MCFV4E_NBUF_H_ - -/* - * Include the Queue structure definitions - */ -#include "queue.h" - -/* - * Number of network buffers to use - */ -#define NBUF_MAX 30 - -/* - * Size of each buffer in bytes - */ -#ifndef NBUF_SZ -#define NBUF_SZ 1520 -#endif - -/* - * Defines to identify all the buffer queues - * - FREE must always be defined as 0 - */ -#define NBUF_FREE 0 /* available buffers */ -#define NBUF_TX_RING 1 /* buffers in the Tx BD ring */ -#define NBUF_RX_RING 2 /* buffers in the Rx BD ring */ -#define NBUF_SCRATCH 3 /* misc */ -#define NBUF_MAXQ 4 /* total number of queueus */ - -/* - * Buffer Descriptor Format - * - * Fields: - * next Pointer to next node in the queue - * data Pointer to the data buffer - * offset Index into buffer - * length Remaining bytes in buffer from (data + offset) - */ -typedef struct -{ - QNODE node; - uint8_t *data; - uint16_t offset; - uint16_t length; -} NBUF; - -/* - * Functions to manipulate the network buffers. - */ -int nbuf_init(void); -void nbuf_flush(void); - -NBUF * nbuf_alloc (void); -void nbuf_free(NBUF *); - -NBUF *nbuf_remove(int); -void nbuf_add(int, NBUF *); - -void nbuf_reset(void); -void nbuf_debug_dump(void); - - -#endif /* _MCFV4E_NBUF_H_ */ diff --git a/include/asm-m68k/proc-mcfv4e/net/net.h b/include/asm-m68k/proc-mcfv4e/net/net.h deleted file mode 100644 index a2ccd76510..0000000000 --- a/include/asm-m68k/proc-mcfv4e/net/net.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Network definitions and prototypes for dBUG. - */ - -#ifndef _MCFV4E_NET_H -#define _MCFV4E_NET_H - -/* - * Include information and prototypes for all protocols - */ -#include "eth.h" -#include "nbuf.h" - -int netif_init(int channel); -int netif_setup(int channel); -int netif_done(int channel); - -#endif /* _MCFV4E_NET_H */ - diff --git a/include/asm-m68k/proc-mcfv4e/net/queue.h b/include/asm-m68k/proc-mcfv4e/net/queue.h deleted file mode 100644 index c9da1c83a5..0000000000 --- a/include/asm-m68k/proc-mcfv4e/net/queue.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Implement a first in, first out linked list - */ -#ifndef _QUEUE_H_ -#define _QUEUE_H_ - -/* - * Individual queue node - */ -typedef struct NODE -{ - struct NODE *next; -} QNODE; - -/* - * Queue Struture - linked list of qentry items - */ -typedef struct -{ - QNODE *head; - QNODE *tail; -} QUEUE; - -/* - * Functions provided by queue.c - */ -void queue_init(QUEUE *); -int queue_isempty(QUEUE *); -void queue_add(QUEUE *, QNODE *); -QNODE* queue_remove(QUEUE *); -QNODE* queue_peek(QUEUE *); -void queue_move(QUEUE *, QUEUE *); - -#endif /* _QUEUE_H_ */ diff --git a/include/asm-m68k/proc-mcfv4e/processor.h b/include/asm-m68k/proc-mcfv4e/processor.h deleted file mode 100644 index f49b65d97b..0000000000 --- a/include/asm-m68k/proc-mcfv4e/processor.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Coldfire V4e processor specific defines - */ - -/* Empty dummy FIXME */ - -/* interrupt management */ - -void mcf_interrupts_initialize (void); -int mcf_interrupts_register_handler (int vector, int (*handler)(void *, void *), void *hdev, void *harg); -void mcf_interrupts_remove_handler (int (*handler)(void *, void *)); -int mcf_execute_irq_handler (struct pt_regs *pt_regs,int); - diff --git a/include/asm-m68k/proc-mcfv4e/ptrace.h b/include/asm-m68k/proc-mcfv4e/ptrace.h deleted file mode 100644 index dd124291d6..0000000000 --- a/include/asm-m68k/proc-mcfv4e/ptrace.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Declaration and defines for M68k register frames - */ -#ifndef __ASM_PROC_PTRACE_H -#define __ASM_PROC_PTRACE_H - -#define TRACE_FLAG 0x8000 -#define SVR_MODE 0x2000 -#define MODE_MASK 0x2000 -#define MASTER_FLAG 0x1000 -#define IRQ_MASK 0x0700 -#define CC_MASK 0x00FF - -#define CC_X_BIT 0x0010 -#define CC_N_BIT 0x0008 -#define CC_Z_BIT 0x0004 -#define CC_V_BIT 0x0002 -#define CC_C_BIT 0x0001 - -#define PCMASK 0x0 - -#ifndef __ASSEMBLY__ - -/* this struct defines the way the registers are stored on the - stack during a system call. */ - -struct pt_regs { - long uregs[37]; -}; -#define M68K_sp uregs[37] -#define M68K_sr uregs[36] -#define M68K_pc uregs[35] -#define M68K_fpiar uregs[34] -#define M68K_fpsr uregs[33] -#define M68K_fpcr uregs[32] - -#define M68K_fp7 uregs[30] -#define M68K_fp6 uregs[28] -#define M68K_fp5 uregs[26] -#define M68K_fp4 uregs[24] -#define M68K_fp3 uregs[22] -#define M68K_fp2 uregs[20] -#define M68K_fp1 uregs[18] -#define M68K_fp0 uregs[16] - -#define M68K_a7 uregs[15] -#define M68K_a6 uregs[14] -#define M68K_a5 uregs[13] -#define M68K_a4 uregs[12] -#define M68K_a3 uregs[11] -#define M68K_a2 uregs[10] -#define M68K_a1 uregs[ 9] -#define M68K_a0 uregs[ 8] -#define M68K_d7 uregs[ 7] -#define M68K_d6 uregs[ 6] -#define M68K_d5 uregs[ 5] -#define M68K_d4 uregs[ 4] -#define M68K_d3 uregs[ 3] -#define M68K_d2 uregs[ 2] -#define M68K_d1 uregs[ 1] -#define M68K_d0 uregs[ 0] - - -#ifdef __KERNEL__ - -#define user_mode(regs) \ - (((regs)->M68K_sr & SVR_MODE) == 0) - -#define processor_mode(regs) \ - ((regs)->M68K_sr & SVR_MODE) - -#define interrupts_enabled(regs) \ - (!((regs)->M68K_sr & IRQ_MASK)) - -#define condition_codes(regs) \ - ((regs)->M68K_sr & CC_MASK) - -/* Are the current registers suitable for user mode? - * (used to maintain security in signal handlers) - */ -static inline int valid_user_regs(struct pt_regs *regs) -{ - if ((regs->M68K_sr & SVR_MODE) == 0 && - (regs->M68K_sr & IRQ_MASK) == 7) - return 1; - - /* - * Force SR to something logical... - */ - regs->M68K_sr &= ~(CC_MASK); - - return 0; -} - -#endif /* __KERNEL__ */ - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-m68k/processor.h b/include/asm-m68k/processor.h deleted file mode 100644 index 75086d5409..0000000000 --- a/include/asm-m68k/processor.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * General processor specific definitions - */ -#ifndef __ASM_M68K_PROCESSOR_H -#define __ASM_M68K_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -static inline unsigned long rdusp(void) -{ - unsigned long usp; - - __asm__ __volatile__("movel %/usp,%0" : "=a" (usp)); - return usp; -} - -static inline void wrusp(unsigned long usp) -{ - __asm__ __volatile__("movel %0,%/usp" : : "a" (usp)); -} - -#endif /* __ASM_M68K_PROCESSOR_H */ diff --git a/include/asm-m68k/ptrace.h b/include/asm-m68k/ptrace.h deleted file mode 100644 index fb0f3314d8..0000000000 --- a/include/asm-m68k/ptrace.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Remains of the pthread stuff... - * @todo Rework these headers.... - */ -#ifndef __ASM_M68K_PTRACE_H -#define __ASM_M68K_PTRACE_H - -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 - -#define PTRACE_SETOPTIONS 21 - - -#include <asm/proc/ptrace.h> - -#ifndef __ASSEMBLY__ - -#ifndef PS_S -#define PS_S (0x2000) -#define PS_M (0x1000) -#endif - -//#define user_mode(regs) (!((regs)->sr & PS_S)) -#define instruction_pointer(regs) ((regs)->M68K_pc) -#define profile_pc(regs) instruction_pointer(regs) - -#ifdef __KERNEL__ -extern void show_regs(struct pt_regs *); -#endif - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-m68k/setup.h b/include/asm-m68k/setup.h deleted file mode 100644 index 8fad34434f..0000000000 --- a/include/asm-m68k/setup.h +++ /dev/null @@ -1,412 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Arch dependant U-Boot defines about linux mach types - */ -#ifndef _M68K_SETUP_H -#define _M68K_SETUP_H - -#include <config.h> - - -/* - * Linux/m68k Architectures - */ - -#define MACH_AMIGA 1 -#define MACH_ATARI 2 -#define MACH_MAC 3 -#define MACH_APOLLO 4 -#define MACH_SUN3 5 -#define MACH_MVME147 6 -#define MACH_MVME16x 7 -#define MACH_BVME6000 8 -#define MACH_HP300 9 -#define MACH_Q40 10 -#define MACH_SUN3X 11 - /* ColdFire boards */ -#define MACH_FIRE_ENGINE 12 - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ -extern unsigned long m68k_machtype; -#endif /* !__ASSEMBLY__ */ - -#if !defined(CONFIG_AMIGA) -# define MACH_IS_AMIGA (0) -#elif defined(CONFIG_ATARI) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \ - || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ - || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_AMIGA (m68k_machtype == MACH_AMIGA) -#else -# define MACH_AMIGA_ONLY -# define MACH_IS_AMIGA (1) -# define MACH_TYPE (MACH_AMIGA) -#endif - -#if !defined(CONFIG_ATARI) -# define MACH_IS_ATARI (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \ - || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ - || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_ATARI (m68k_machtype == MACH_ATARI) -#else -# define MACH_ATARI_ONLY -# define MACH_IS_ATARI (1) -# define MACH_TYPE (MACH_ATARI) -#endif - -#if !defined(CONFIG_MAC) -# define MACH_IS_MAC (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_ATARI) || defined(CONFIG_APOLLO) \ - || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ - || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_MAC (m68k_machtype == MACH_MAC) -#else -# define MACH_MAC_ONLY -# define MACH_IS_MAC (1) -# define MACH_TYPE (MACH_MAC) -#endif - -#if defined(CONFIG_SUN3) -#define MACH_IS_SUN3 (1) -#define MACH_SUN3_ONLY (1) -#define MACH_TYPE (MACH_SUN3) -#else -#define MACH_IS_SUN3 (0) -#endif - -#if !defined (CONFIG_APOLLO) -# define MACH_IS_APOLLO (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ - || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ - || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_APOLLO (m68k_machtype == MACH_APOLLO) -#else -# define MACH_APOLLO_ONLY -# define MACH_IS_APOLLO (1) -# define MACH_TYPE (MACH_APOLLO) -#endif - -#if !defined (CONFIG_MVME147) -# define MACH_IS_MVME147 (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ - || defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \ - || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME16x) -# define MACH_IS_MVME147 (m68k_machtype == MACH_MVME147) -#else -# define MACH_MVME147_ONLY -# define MACH_IS_MVME147 (1) -# define MACH_TYPE (MACH_MVME147) -#endif - -#if !defined (CONFIG_MVME16x) -# define MACH_IS_MVME16x (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ - || defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \ - || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_MVME16x (m68k_machtype == MACH_MVME16x) -#else -# define MACH_MVME16x_ONLY -# define MACH_IS_MVME16x (1) -# define MACH_TYPE (MACH_MVME16x) -#endif - -#if !defined (CONFIG_BVME6000) -# define MACH_IS_BVME6000 (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ - || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ - || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_BVME6000 (m68k_machtype == MACH_BVME6000) -#else -# define MACH_BVME6000_ONLY -# define MACH_IS_BVME6000 (1) -# define MACH_TYPE (MACH_BVME6000) -#endif - -#if !defined (CONFIG_HP300) -# define MACH_IS_HP300 (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ - || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ - || defined(CONFIG_BVME6000) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_HP300 (m68k_machtype == MACH_HP300) -#else -# define MACH_HP300_ONLY -# define MACH_IS_HP300 (1) -# define MACH_TYPE (MACH_HP300) -#endif - -#if !defined (CONFIG_Q40) -# define MACH_IS_Q40 (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ - || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ - || defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_Q40 (m68k_machtype == MACH_Q40) -#else -# define MACH_Q40_ONLY -# define MACH_IS_Q40 (1) -# define MACH_TYPE (MACH_Q40) -#endif - -#if !defined (CONFIG_SUN3X) -# define MACH_IS_SUN3X (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ - || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ - || defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \ - || defined(CONFIG_Q40) || defined(CONFIG_MVME147) -# define MACH_IS_SUN3X (m68k_machtype == MACH_SUN3X) -#else -# define CONFIG_SUN3X_ONLY -# define MACH_IS_SUN3X (1) -# define MACH_TYPE (MACH_SUN3X) -#endif - -/* - * We only support one ColdFire board for the moment, so we don't do the - * kind of complicated configuration this file does for the other 68k CPUs. --NL - */ -#if !defined (CONFIG_COLDFIRE) -# define MACH_IS_COLDFIRE (0) -#else -# define CONFIG_COLDFIRE_ONLY -# define MACH_IS_COLDFIRE (1) -# define MACH_TYPE (MACH_COLDFIRE) -#endif - -#ifndef MACH_TYPE -# define MACH_TYPE (m68k_machtype) -#endif - -#endif /* __KERNEL__ */ - - - /* - * CPU, FPU and MMU types - * - * Note: we may rely on the following equalities: - * - * CPU_68020 == MMU_68851 - * CPU_68030 == MMU_68030 - * CPU_68040 == FPU_68040 == MMU_68040 - * CPU_68060 == FPU_68060 == MMU_68060 - */ - -#define CPUB_68020 0 -#define CPUB_68030 1 -#define CPUB_68040 2 -#define CPUB_68060 3 -#define CPUB_CFV4E 4 - -#define CPU_68020 (1<<CPUB_68020) -#define CPU_68030 (1<<CPUB_68030) -#define CPU_68040 (1<<CPUB_68040) -#define CPU_68060 (1<<CPUB_68060) -#define CPU_CFV4E (1<<CPUB_CFV4E) - -#define FPUB_68881 0 -#define FPUB_68882 1 -#define FPUB_68040 2 /* Internal FPU */ -#define FPUB_68060 3 /* Internal FPU */ -#define FPUB_SUNFPA 4 /* Sun-3 FPA */ -#define FPUB_CFV4E 5 - -#define FPU_68881 (1<<FPUB_68881) -#define FPU_68882 (1<<FPUB_68882) -#define FPU_68040 (1<<FPUB_68040) -#define FPU_68060 (1<<FPUB_68060) -#define FPU_SUNFPA (1<<FPUB_SUNFPA) -#define FPU_CFV4E (1<<FPUB_CFV4E) - -#define MMUB_68851 0 -#define MMUB_68030 1 /* Internal MMU */ -#define MMUB_68040 2 /* Internal MMU */ -#define MMUB_68060 3 /* Internal MMU */ -#define MMUB_APOLLO 4 /* Custom Apollo */ -#define MMUB_SUN3 5 /* Custom Sun-3 */ -#define MMUB_CFV4E 6 - -#define MMU_68851 (1<<MMUB_68851) -#define MMU_68030 (1<<MMUB_68030) -#define MMU_68040 (1<<MMUB_68040) -#define MMU_68060 (1<<MMUB_68060) -#define MMU_SUN3 (1<<MMUB_SUN3) -#define MMU_APOLLO (1<<MMUB_APOLLO) -#define MMU_CFV4E (1<<MMUB_CFV4E) - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ -extern unsigned long m68k_cputype; -extern unsigned long m68k_fputype; -extern unsigned long m68k_mmutype; /* Not really used yet */ -#ifdef CONFIG_VME -extern unsigned long vme_brdtype; -#endif - - /* - * m68k_is040or060 is != 0 for a '040 or higher; - * used numbers are 4 for 68040 and 6 for 68060. - */ - -extern int m68k_is040or060; -#endif /* !__ASSEMBLY__ */ - -#if !defined(CONFIG_M68020) -# define CPU_IS_020 (0) -# define MMU_IS_851 (0) -# define MMU_IS_SUN3 (0) -#elif defined(CONFIG_M68030) || defined(CONFIG_M68040) || defined(CONFIG_M68060) -# define CPU_IS_020 (m68k_cputype & CPU_68020) -# define MMU_IS_851 (m68k_mmutype & MMU_68851) -# define MMU_IS_SUN3 (0) /* Sun3 not supported with other CPU enabled */ -#else -# define CPU_M68020_ONLY -# define CPU_IS_020 (1) -#ifdef MACH_SUN3_ONLY -# define MMU_IS_SUN3 (1) -# define MMU_IS_851 (0) -#else -# define MMU_IS_SUN3 (0) -# define MMU_IS_851 (1) -#endif -#endif - -#if !defined(CONFIG_M68030) -# define CPU_IS_030 (0) -# define MMU_IS_030 (0) -#elif defined(CONFIG_M68020) || defined(CONFIG_M68040) || defined(CONFIG_M68060) -# define CPU_IS_030 (m68k_cputype & CPU_68030) -# define MMU_IS_030 (m68k_mmutype & MMU_68030) -#else -# define CPU_M68030_ONLY -# define CPU_IS_030 (1) -# define MMU_IS_030 (1) -#endif - -#if !defined(CONFIG_M68040) -# define CPU_IS_040 (0) -# define MMU_IS_040 (0) -#elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68060) -# define CPU_IS_040 (m68k_cputype & CPU_68040) -# define MMU_IS_040 (m68k_mmutype & MMU_68040) -#else -# define CPU_M68040_ONLY -# define CPU_IS_040 (1) -# define MMU_IS_040 (1) -#endif - -#if !defined(CONFIG_M68060) -# define CPU_IS_060 (0) -# define MMU_IS_060 (0) -#elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68040) -# define CPU_IS_060 (m68k_cputype & CPU_68060) -# define MMU_IS_060 (m68k_mmutype & MMU_68060) -#else -# define CPU_M68060_ONLY -# define CPU_IS_060 (1) -# define MMU_IS_060 (1) -#endif - -#if !defined(CONFIG_M68020) && !defined(CONFIG_M68030) -# define CPU_IS_020_OR_030 (0) -#else -# define CPU_M68020_OR_M68030 -# if defined(CONFIG_M68040) || defined(CONFIG_M68060) -# define CPU_IS_020_OR_030 (!m68k_is040or060) -# else -# define CPU_M68020_OR_M68030_ONLY -# define CPU_IS_020_OR_030 (1) -# endif -#endif - -#if !defined(CONFIG_M68040) && !defined(CONFIG_M68060) -# define CPU_IS_040_OR_060 (0) -#else -# define CPU_M68040_OR_M68060 -# if defined(CONFIG_M68020) || defined(CONFIG_M68030) -# define CPU_IS_040_OR_060 (m68k_is040or060) -# else -# define CPU_M68040_OR_M68060_ONLY -# define CPU_IS_040_OR_060 (1) -# endif -#endif - -#if !defined(CONFIG_CFV4E) -# define CPU_IS_COLDFIRE (0) -#else -# define CPU_IS_COLDFIRE (1) -# define CPU_IS_CFV4E (1) -# define MMU_IS_CFV4E (1) -#endif - -#define CPU_TYPE (m68k_cputype) - -#ifdef CONFIG_M68KFPU_EMU -# ifdef CONFIG_M68KFPU_EMU_ONLY -# define FPU_IS_EMU (1) -# else -# define FPU_IS_EMU (!m68k_fputype) -# endif -#else -# define FPU_IS_EMU (0) -#endif - - -/* - * Miscellaneous - */ - -#define NUM_MEMINFO 4 -#define CL_SIZE 256 -#define COMMAND_LINE_SIZE CL_SIZE - -#ifndef __ASSEMBLY__ -struct mem_info { - unsigned long addr; /* physical address of memory chunk */ - unsigned long size; /* length of memory chunk (in bytes) */ -}; -extern int m68k_num_memory; /* # of memory blocks found (and used) */ -extern int m68k_realnum_memory; /* real # of memory blocks found */ -extern struct mem_info m68k_memory[NUM_MEMINFO];/* memory description */ - -#endif - -#ifdef CONFIG_COLDFIRE -#define QCHIP_RESTORE_DIRECTIVE ".chip 547x" -#define CHIP_RESTORE_DIRECTIVE .chip 547x -#else -#define QCHIP_RESTORE_DIRECTIVE ".chip 68k" -#define CHIP_RESTORE_DIRECTIVE .chip 68k -#endif - -#endif /* __KERNEL__ */ - -#endif /* _M68K_SETUP_H */ diff --git a/include/asm-m68k/string.h b/include/asm-m68k/string.h deleted file mode 100644 index 193ec54a1a..0000000000 --- a/include/asm-m68k/string.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Arch dependant configuration of std libc string and memory functions. - */ -#ifndef __ASM_M68K_STRING_H -#define __ASM_M68K_STRING_H - -/* - * We don't do inline string functions, since the - * optimised inline asm versions are not small. - */ - -#endif diff --git a/include/asm-m68k/types.h b/include/asm-m68k/types.h deleted file mode 100644 index 7ce94a176b..0000000000 --- a/include/asm-m68k/types.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Arch dependant types definitions - */ -#ifndef __ASM_M68K_TYPES_H -#define __ASM_M68K_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG 32 - -#ifndef __ASSEMBLY__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; -typedef u32 dma64_addr_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-m68k/u-boot-m68k.h b/include/asm-m68k/u-boot-m68k.h deleted file mode 100644 index 51cacae6e2..0000000000 --- a/include/asm-m68k/u-boot-m68k.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Arch dependant U-Boot defines - */ -#ifndef _U_BOOT_M68K_H_ -#define _U_BOOT_M68K_H_ 1 - -/* for the following variables, see start.S */ -//extern ulong _armboot_start; /* code start */ -//extern ulong _bss_start; /* code + data end == BSS start */ -//extern ulong _bss_end; /* BSS end */ -//extern ulong IRQ_STACK_START; /* top of IRQ stack */ - -/* cpu/.../cpu.c */ -int cleanup_before_linux(void); - -/* board/.../... */ -//int board_init(void); -//int dram_init (void); - -#endif /* _U_BOOT_M68K_H_ */ diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h deleted file mode 100644 index 34deaf10d0..0000000000 --- a/include/asm-m68k/u-boot.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of U-Boot V2. - * - * U-Boot V2 is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * U-Boot V2 is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with U-Boot V2. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * @note This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - */ - -#ifndef _U_BOOT_H_ -#define _U_BOOT_H_ 1 - -//typedef struct bd_info {} bd_t; - -#endif /* _U_BOOT_H_ */ diff --git a/include/asm-ppc/.gitignore b/include/asm-ppc/.gitignore deleted file mode 100644 index aca8da44fb..0000000000 --- a/include/asm-ppc/.gitignore +++ /dev/null @@ -1 +0,0 @@ -arch
\ No newline at end of file diff --git a/include/asm-ppc/arch-mpc5200/clocks.h b/include/asm-ppc/arch-mpc5200/clocks.h deleted file mode 100644 index 4e1a903e79..0000000000 --- a/include/asm-ppc/arch-mpc5200/clocks.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __ASM_ARCH_CLOCKS_H -#define __ASM_ARCH_CLOCKS_H - -unsigned long get_bus_clock(void); -unsigned long get_cpu_clock(void); -unsigned long get_ipb_clock(void); -unsigned long get_pci_clock(void); -unsigned long get_timebase_clock(void); - -#endif /* __ASM_ARCH_CLOCKS_H */ diff --git a/include/asm-ppc/arch-mpc5200/fec.h b/include/asm-ppc/arch-mpc5200/fec.h deleted file mode 100644 index a3e04b4e9d..0000000000 --- a/include/asm-ppc/arch-mpc5200/fec.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef __INCLUDE_ASM_ARCH_FEC_H -#define __INCLUDE_ASM_ARCH_FEC_H - -struct mpc5xxx_fec_platform_data { - ulong xcv_type; -}; - -typedef enum { - SEVENWIRE, /* 7-wire */ - MII10, /* MII 10Mbps */ - MII100 /* MII 100Mbps */ -} xceiver_type; - -#endif /* __INCLUDE_ASM_ARCH_FEC_H */ diff --git a/include/asm-ppc/arch-mpc5200/mpc5xxx.h b/include/asm-ppc/arch-mpc5200/mpc5xxx.h deleted file mode 100644 index 0638df157c..0000000000 --- a/include/asm-ppc/arch-mpc5200/mpc5xxx.h +++ /dev/null @@ -1,784 +0,0 @@ -/* - * include/asm-ppc/mpc5xxx.h - * - * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx - * embedded cpu chips - * - * 2003 (c) MontaVista, Software, Inc. - * Author: Dale Farnsworth <dfarnsworth@mvista.com> - * - * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASMPPC_MPC5XXX_H -#define __ASMPPC_MPC5XXX_H - -/* Processor name */ -#if defined(CONFIG_MPC5200) -#define CPU_ID_STR "MPC5200" -#elif defined(CONFIG_MGT5100) -#define CPU_ID_STR "MGT5100" -#endif - -/* Exception offsets (PowerPC standard) */ -#define EXC_OFF_SYS_RESET 0x0100 - -/* useful macros for manipulating CSx_START/STOP */ -#if defined(CONFIG_MGT5100) -#define START_REG(start) ((start) >> 15) -#define STOP_REG(start, size) (((start) + (size) - 1) >> 15) -#elif defined(CONFIG_MPC5200) -#define START_REG(start) ((start) >> 16) -#define STOP_REG(start, size) (((start) + (size) - 1) >> 16) -#endif - -/* Internal memory map */ - -#define MPC5XXX_CS0_START (CFG_MBAR + 0x0004) -#define MPC5XXX_CS0_STOP (CFG_MBAR + 0x0008) -#define MPC5XXX_CS1_START (CFG_MBAR + 0x000c) -#define MPC5XXX_CS1_STOP (CFG_MBAR + 0x0010) -#define MPC5XXX_CS2_START (CFG_MBAR + 0x0014) -#define MPC5XXX_CS2_STOP (CFG_MBAR + 0x0018) -#define MPC5XXX_CS3_START (CFG_MBAR + 0x001c) -#define MPC5XXX_CS3_STOP (CFG_MBAR + 0x0020) -#define MPC5XXX_CS4_START (CFG_MBAR + 0x0024) -#define MPC5XXX_CS4_STOP (CFG_MBAR + 0x0028) -#define MPC5XXX_CS5_START (CFG_MBAR + 0x002c) -#define MPC5XXX_CS5_STOP (CFG_MBAR + 0x0030) -#define MPC5XXX_BOOTCS_START (CFG_MBAR + 0x004c) -#define MPC5XXX_BOOTCS_STOP (CFG_MBAR + 0x0050) -#define MPC5XXX_ADDECR (CFG_MBAR + 0x0054) - -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SDRAM_START (CFG_MBAR + 0x0034) -#define MPC5XXX_SDRAM_STOP (CFG_MBAR + 0x0038) -#define MPC5XXX_PCI1_START (CFG_MBAR + 0x003c) -#define MPC5XXX_PCI1_STOP (CFG_MBAR + 0x0040) -#define MPC5XXX_PCI2_START (CFG_MBAR + 0x0044) -#define MPC5XXX_PCI2_STOP (CFG_MBAR + 0x0048) -#elif defined(CONFIG_MPC5200) -#define MPC5XXX_CS6_START (CFG_MBAR + 0x0058) -#define MPC5XXX_CS6_STOP (CFG_MBAR + 0x005c) -#define MPC5XXX_CS7_START (CFG_MBAR + 0x0060) -#define MPC5XXX_CS7_STOP (CFG_MBAR + 0x0064) -#define MPC5XXX_SDRAM_CS0CFG (CFG_MBAR + 0x0034) -#define MPC5XXX_SDRAM_CS1CFG (CFG_MBAR + 0x0038) -#endif - -#define MPC5XXX_SDRAM (CFG_MBAR + 0x0100) -#define MPC5XXX_CDM (CFG_MBAR + 0x0200) -#define MPC5XXX_LPB (CFG_MBAR + 0x0300) -#define MPC5XXX_ICTL (CFG_MBAR + 0x0500) -#define MPC5XXX_GPT (CFG_MBAR + 0x0600) -#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00) -#define MPC5XXX_WU_GPIO (CFG_MBAR + 0x0c00) -#define MPC5XXX_PCI (CFG_MBAR + 0x0d00) -#define MPC5XXX_SPI (CFG_MBAR + 0x0f00) -#define MPC5XXX_USB (CFG_MBAR + 0x1000) -#define MPC5XXX_SDMA (CFG_MBAR + 0x1200) -#define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00) - -#if defined(CONFIG_MGT5100) -#define MPC5XXX_PSC1 (CFG_MBAR + 0x2000) -#define MPC5XXX_PSC2 (CFG_MBAR + 0x2400) -#define MPC5XXX_PSC3 (CFG_MBAR + 0x2800) -#elif defined(CONFIG_MPC5200) -#define MPC5XXX_PSC1 (CFG_MBAR + 0x2000) -#define MPC5XXX_PSC2 (CFG_MBAR + 0x2200) -#define MPC5XXX_PSC3 (CFG_MBAR + 0x2400) -#define MPC5XXX_PSC4 (CFG_MBAR + 0x2600) -#define MPC5XXX_PSC5 (CFG_MBAR + 0x2800) -#define MPC5XXX_PSC6 (CFG_MBAR + 0x2c00) -#endif - -#define MPC5XXX_FEC (CFG_MBAR + 0x3000) -#define MPC5XXX_ATA (CFG_MBAR + 0x3A00) - -#define MPC5XXX_I2C1 (CFG_MBAR + 0x3D00) -#define MPC5XXX_I2C2 (CFG_MBAR + 0x3D40) - -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SRAM (CFG_MBAR + 0x4000) -#define MPC5XXX_SRAM_SIZE (8*1024) -#elif defined(CONFIG_MPC5200) -#define MPC5XXX_SRAM (CFG_MBAR + 0x8000) -#define MPC5XXX_SRAM_SIZE (16*1024) -#endif - -/* SDRAM Controller */ -#define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000) -#define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004) -#define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008) -#define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010) -#endif -#define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090) - -/* Clock Distribution Module */ -#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000) -#define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004) -#define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c) -#define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010) -#define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020) - -/* Local Plus Bus interface */ -#define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000) -#define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004) -#define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008) -#define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c) -#define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010) -#define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014) -#define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG -#define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018) -#define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c) -#if defined(CONFIG_MPC5200) -#define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020) -#define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024) -#define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028) -#define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c) -#endif - -#if defined(CONFIG_MPC5200) -/* XLB Arbiter registers */ -#define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40) -#define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64) -#define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68) -#endif - -/* GPIO registers */ -#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000) - -/* Standard GPIO registers (simple, output only and simple interrupt */ -#define MPC5XXX_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) -#define MPC5XXX_GPIO_ODE (MPC5XXX_GPIO + 0x0008) -#define MPC5XXX_GPIO_DIR (MPC5XXX_GPIO + 0x000c) -#define MPC5XXX_GPIO_DATA_O (MPC5XXX_GPIO + 0x0010) -#define MPC5XXX_GPIO_DATA_I (MPC5XXX_GPIO + 0x0014) -#define MPC5XXX_GPIO_OO_ENABLE (MPC5XXX_GPIO + 0x0018) -#define MPC5XXX_GPIO_OO_DATA (MPC5XXX_GPIO + 0x001C) -#define MPC5XXX_GPIO_SI_ENABLE (MPC5XXX_GPIO + 0x0020) -#define MPC5XXX_GPIO_SI_ODE (MPC5XXX_GPIO + 0x0024) -#define MPC5XXX_GPIO_SI_DIR (MPC5XXX_GPIO + 0x0028) -#define MPC5XXX_GPIO_SI_DATA (MPC5XXX_GPIO + 0x002C) -#define MPC5XXX_GPIO_SI_IEN (MPC5XXX_GPIO + 0x0030) -#define MPC5XXX_GPIO_SI_ITYPE (MPC5XXX_GPIO + 0x0034) -#define MPC5XXX_GPIO_SI_MEN (MPC5XXX_GPIO + 0x0038) -#define MPC5XXX_GPIO_SI_STATUS (MPC5XXX_GPIO + 0x003C) - -/* WakeUp GPIO registers */ -#define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000) -#define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004) -#define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008) -#define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c) -#define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020) - -/* GPIO pins */ -#define GPIO_WKUP_7 0x80000000UL -#define GPIO_PSC6_0 0x10000000UL -#define GPIO_PSC3_9 0x04000000UL -#define GPIO_PSC1_4 0x01000000UL - -/* PCI registers */ -#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04) -#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c) -#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10) -#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68) -#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c) -#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70) -#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74) -#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78) -#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c) -#elif defined(CONFIG_MPC5200) -#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60) -#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64) -#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68) -#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c) -#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70) -#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74) -#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78) -#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80) -#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84) -#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88) -#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c) -#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8) -#endif - -/* Interrupt Controller registers */ -#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000) -#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004) -#define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008) -#define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c) -#define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010) -#define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014) -#define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018) -#define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c) -#define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024) -#define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028) -#define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c) -#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030) -#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038) - -#define NR_IRQS 64 - -/* IRQ mapping - these are our logical IRQ numbers */ -#define MPC5XXX_CRIT_IRQ_NUM 4 -#define MPC5XXX_MAIN_IRQ_NUM 17 -#define MPC5XXX_SDMA_IRQ_NUM 17 -#define MPC5XXX_PERP_IRQ_NUM 23 - -#define MPC5XXX_CRIT_IRQ_BASE 1 -#define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM) -#define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM) -#define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM) - -#define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0) -#define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1) -#define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2) -#define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3) - -#define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1) -#define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2) -#define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3) -#define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5) -#define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6) -#define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7) -#define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8) -#define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9) -#define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10) -#define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11) -#define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12) -#define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13) -#define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14) -#define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15) -#define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16) - -#define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0) -#define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1) -#define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2) -#define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3) -#define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4) -#define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4) -#define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5) -#define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6) -#define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7) -#define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8) -#define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9) -#define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10) -#define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11) -#define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12) -#define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13) -#define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14) -#define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15) -#define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16) -#define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17) -#define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18) -#define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19) -#define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20) -#define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21) -#define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22) - -/* General Purpose Timers registers */ -#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0) -#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4) -#define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C) -#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10) -#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14) -#define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C) -#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20) -#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24) -#define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C) -#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30) -#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34) -#define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C) -#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40) -#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44) -#define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C) -#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50) -#define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C) -#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54) -#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60) -#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64) -#define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C) -#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70) -#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74) -#define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C) - -#define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8) - -#define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78) - -/* ATA registers */ -#define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000) -#define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008) -#define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C) -#define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C) - -/* I2Cn control register bits */ -#define I2C_EN 0x80 -#define I2C_IEN 0x40 -#define I2C_STA 0x20 -#define I2C_TX 0x10 -#define I2C_TXAK 0x08 -#define I2C_RSTA 0x04 -#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) - -/* I2Cn status register bits */ -#define I2C_CF 0x80 -#define I2C_AAS 0x40 -#define I2C_BB 0x20 -#define I2C_AL 0x10 -#define I2C_SRW 0x04 -#define I2C_IF 0x02 -#define I2C_RXAK 0x01 - -/* Programmable Serial Controller (PSC) status register bits */ -#define PSC_SR_CDE 0x0080 -#define PSC_SR_RXRDY 0x0100 -#define PSC_SR_RXFULL 0x0200 -#define PSC_SR_TXRDY 0x0400 -#define PSC_SR_TXEMP 0x0800 -#define PSC_SR_OE 0x1000 -#define PSC_SR_PE 0x2000 -#define PSC_SR_FE 0x4000 -#define PSC_SR_RB 0x8000 - -/* PSC Command values */ -#define PSC_RX_ENABLE 0x0001 -#define PSC_RX_DISABLE 0x0002 -#define PSC_TX_ENABLE 0x0004 -#define PSC_TX_DISABLE 0x0008 -#define PSC_SEL_MODE_REG_1 0x0010 -#define PSC_RST_RX 0x0020 -#define PSC_RST_TX 0x0030 -#define PSC_RST_ERR_STAT 0x0040 -#define PSC_RST_BRK_CHG_INT 0x0050 -#define PSC_START_BRK 0x0060 -#define PSC_STOP_BRK 0x0070 - -/* PSC Rx FIFO status bits */ -#define PSC_RX_FIFO_ERR 0x0040 -#define PSC_RX_FIFO_UF 0x0020 -#define PSC_RX_FIFO_OF 0x0010 -#define PSC_RX_FIFO_FR 0x0008 -#define PSC_RX_FIFO_FULL 0x0004 -#define PSC_RX_FIFO_ALARM 0x0002 -#define PSC_RX_FIFO_EMPTY 0x0001 - -/* PSC interrupt mask bits */ -#define PSC_IMR_TXRDY 0x0100 -#define PSC_IMR_RXRDY 0x0200 -#define PSC_IMR_DB 0x0400 -#define PSC_IMR_IPC 0x8000 - -/* PSC input port change bits */ -#define PSC_IPCR_CTS 0x01 -#define PSC_IPCR_DCD 0x02 - -/* PSC mode fields */ -#define PSC_MODE_5_BITS 0x00 -#define PSC_MODE_6_BITS 0x01 -#define PSC_MODE_7_BITS 0x02 -#define PSC_MODE_8_BITS 0x03 -#define PSC_MODE_PAREVEN 0x00 -#define PSC_MODE_PARODD 0x04 -#define PSC_MODE_PARFORCE 0x08 -#define PSC_MODE_PARNONE 0x10 -#define PSC_MODE_ERR 0x20 -#define PSC_MODE_FFULL 0x40 -#define PSC_MODE_RXRTS 0x80 - -#define PSC_MODE_ONE_STOP_5_BITS 0x00 -#define PSC_MODE_ONE_STOP 0x07 -#define PSC_MODE_TWO_STOP 0x0f - -/* ATA config fields */ -#define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine - reset */ -#define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */ -#define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt - in PIO */ -#define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports - IORDY protocol */ - -#ifndef __ASSEMBLY__ - -#include <linux/types.h> - -struct mpc5xxx_psc { - volatile u8 mode; /* PSC + 0x00 */ - volatile u8 reserved0[3]; - union { /* PSC + 0x04 */ - volatile u16 status; - volatile u16 clock_select; - } sr_csr; -#define psc_status sr_csr.status -#define psc_clock_select sr_csr.clock_select - volatile u16 reserved1; - volatile u8 command; /* PSC + 0x08 */ - volatile u8 reserved2[3]; - union { /* PSC + 0x0c */ - volatile u8 buffer_8; - volatile u16 buffer_16; - volatile u32 buffer_32; - } buffer; -#define psc_buffer_8 buffer.buffer_8 -#define psc_buffer_16 buffer.buffer_16 -#define psc_buffer_32 buffer.buffer_32 - union { /* PSC + 0x10 */ - volatile u8 ipcr; - volatile u8 acr; - } ipcr_acr; -#define psc_ipcr ipcr_acr.ipcr -#define psc_acr ipcr_acr.acr - volatile u8 reserved3[3]; - union { /* PSC + 0x14 */ - volatile u16 isr; - volatile u16 imr; - } isr_imr; -#define psc_isr isr_imr.isr -#define psc_imr isr_imr.imr - volatile u16 reserved4; - volatile u8 ctur; /* PSC + 0x18 */ - volatile u8 reserved5[3]; - volatile u8 ctlr; /* PSC + 0x1c */ - volatile u8 reserved6[3]; - volatile u16 ccr; /* PSC + 0x20 */ - volatile u8 reserved7[14]; - volatile u8 ivr; /* PSC + 0x30 */ - volatile u8 reserved8[3]; - volatile u8 ip; /* PSC + 0x34 */ - volatile u8 reserved9[3]; - volatile u8 op1; /* PSC + 0x38 */ - volatile u8 reserved10[3]; - volatile u8 op0; /* PSC + 0x3c */ - volatile u8 reserved11[3]; - volatile u32 sicr; /* PSC + 0x40 */ - volatile u8 ircr1; /* PSC + 0x44 */ - volatile u8 reserved12[3]; - volatile u8 ircr2; /* PSC + 0x44 */ - volatile u8 reserved13[3]; - volatile u8 irsdr; /* PSC + 0x4c */ - volatile u8 reserved14[3]; - volatile u8 irmdr; /* PSC + 0x50 */ - volatile u8 reserved15[3]; - volatile u8 irfdr; /* PSC + 0x54 */ - volatile u8 reserved16[3]; - volatile u16 rfnum; /* PSC + 0x58 */ - volatile u16 reserved17; - volatile u16 tfnum; /* PSC + 0x5c */ - volatile u16 reserved18; - volatile u32 rfdata; /* PSC + 0x60 */ - volatile u16 rfstat; /* PSC + 0x64 */ - volatile u16 reserved20; - volatile u8 rfcntl; /* PSC + 0x68 */ - volatile u8 reserved21[5]; - volatile u16 rfalarm; /* PSC + 0x6e */ - volatile u16 reserved22; - volatile u16 rfrptr; /* PSC + 0x72 */ - volatile u16 reserved23; - volatile u16 rfwptr; /* PSC + 0x76 */ - volatile u16 reserved24; - volatile u16 rflrfptr; /* PSC + 0x7a */ - volatile u16 reserved25; - volatile u16 rflwfptr; /* PSC + 0x7e */ - volatile u32 tfdata; /* PSC + 0x80 */ - volatile u16 tfstat; /* PSC + 0x84 */ - volatile u16 reserved26; - volatile u8 tfcntl; /* PSC + 0x88 */ - volatile u8 reserved27[5]; - volatile u16 tfalarm; /* PSC + 0x8e */ - volatile u16 reserved28; - volatile u16 tfrptr; /* PSC + 0x92 */ - volatile u16 reserved29; - volatile u16 tfwptr; /* PSC + 0x96 */ - volatile u16 reserved30; - volatile u16 tflrfptr; /* PSC + 0x9a */ - volatile u16 reserved31; - volatile u16 tflwfptr; /* PSC + 0x9e */ -}; - -struct mpc5xxx_intr { - volatile u32 per_mask; /* INTR + 0x00 */ - volatile u32 per_pri1; /* INTR + 0x04 */ - volatile u32 per_pri2; /* INTR + 0x08 */ - volatile u32 per_pri3; /* INTR + 0x0c */ - volatile u32 ctrl; /* INTR + 0x10 */ - volatile u32 main_mask; /* INTR + 0x14 */ - volatile u32 main_pri1; /* INTR + 0x18 */ - volatile u32 main_pri2; /* INTR + 0x1c */ - volatile u32 reserved1; /* INTR + 0x20 */ - volatile u32 enc_status; /* INTR + 0x24 */ - volatile u32 crit_status; /* INTR + 0x28 */ - volatile u32 main_status; /* INTR + 0x2c */ - volatile u32 per_status; /* INTR + 0x30 */ - volatile u32 reserved2; /* INTR + 0x34 */ - volatile u32 per_error; /* INTR + 0x38 */ -}; - -struct mpc5xxx_gpio { - volatile u32 port_config; /* GPIO + 0x00 */ - volatile u32 simple_gpioe; /* GPIO + 0x04 */ - volatile u32 simple_ode; /* GPIO + 0x08 */ - volatile u32 simple_ddr; /* GPIO + 0x0c */ - volatile u32 simple_dvo; /* GPIO + 0x10 */ - volatile u32 simple_ival; /* GPIO + 0x14 */ - volatile u8 outo_gpioe; /* GPIO + 0x18 */ - volatile u8 reserved1[3]; /* GPIO + 0x19 */ - volatile u8 outo_dvo; /* GPIO + 0x1c */ - volatile u8 reserved2[3]; /* GPIO + 0x1d */ - volatile u8 sint_gpioe; /* GPIO + 0x20 */ - volatile u8 reserved3[3]; /* GPIO + 0x21 */ - volatile u8 sint_ode; /* GPIO + 0x24 */ - volatile u8 reserved4[3]; /* GPIO + 0x25 */ - volatile u8 sint_ddr; /* GPIO + 0x28 */ - volatile u8 reserved5[3]; /* GPIO + 0x29 */ - volatile u8 sint_dvo; /* GPIO + 0x2c */ - volatile u8 reserved6[3]; /* GPIO + 0x2d */ - volatile u8 sint_inten; /* GPIO + 0x30 */ - volatile u8 reserved7[3]; /* GPIO + 0x31 */ - volatile u16 sint_itype; /* GPIO + 0x34 */ - volatile u16 reserved8; /* GPIO + 0x36 */ - volatile u8 gpio_control; /* GPIO + 0x38 */ - volatile u8 reserved9[3]; /* GPIO + 0x39 */ - volatile u8 sint_istat; /* GPIO + 0x3c */ - volatile u8 sint_ival; /* GPIO + 0x3d */ - volatile u8 bus_errs; /* GPIO + 0x3e */ - volatile u8 reserved10; /* GPIO + 0x3f */ -}; - -struct mpc5xxx_sdma { - volatile u32 taskBar; /* SDMA + 0x00 */ - volatile u32 currentPointer; /* SDMA + 0x04 */ - volatile u32 endPointer; /* SDMA + 0x08 */ - volatile u32 variablePointer; /* SDMA + 0x0c */ - - volatile u8 IntVect1; /* SDMA + 0x10 */ - volatile u8 IntVect2; /* SDMA + 0x11 */ - volatile u16 PtdCntrl; /* SDMA + 0x12 */ - - volatile u32 IntPend; /* SDMA + 0x14 */ - volatile u32 IntMask; /* SDMA + 0x18 */ - - volatile u16 tcr_0; /* SDMA + 0x1c */ - volatile u16 tcr_1; /* SDMA + 0x1e */ - volatile u16 tcr_2; /* SDMA + 0x20 */ - volatile u16 tcr_3; /* SDMA + 0x22 */ - volatile u16 tcr_4; /* SDMA + 0x24 */ - volatile u16 tcr_5; /* SDMA + 0x26 */ - volatile u16 tcr_6; /* SDMA + 0x28 */ - volatile u16 tcr_7; /* SDMA + 0x2a */ - volatile u16 tcr_8; /* SDMA + 0x2c */ - volatile u16 tcr_9; /* SDMA + 0x2e */ - volatile u16 tcr_a; /* SDMA + 0x30 */ - volatile u16 tcr_b; /* SDMA + 0x32 */ - volatile u16 tcr_c; /* SDMA + 0x34 */ - volatile u16 tcr_d; /* SDMA + 0x36 */ - volatile u16 tcr_e; /* SDMA + 0x38 */ - volatile u16 tcr_f; /* SDMA + 0x3a */ - - volatile u8 IPR0; /* SDMA + 0x3c */ - volatile u8 IPR1; /* SDMA + 0x3d */ - volatile u8 IPR2; /* SDMA + 0x3e */ - volatile u8 IPR3; /* SDMA + 0x3f */ - volatile u8 IPR4; /* SDMA + 0x40 */ - volatile u8 IPR5; /* SDMA + 0x41 */ - volatile u8 IPR6; /* SDMA + 0x42 */ - volatile u8 IPR7; /* SDMA + 0x43 */ - volatile u8 IPR8; /* SDMA + 0x44 */ - volatile u8 IPR9; /* SDMA + 0x45 */ - volatile u8 IPR10; /* SDMA + 0x46 */ - volatile u8 IPR11; /* SDMA + 0x47 */ - volatile u8 IPR12; /* SDMA + 0x48 */ - volatile u8 IPR13; /* SDMA + 0x49 */ - volatile u8 IPR14; /* SDMA + 0x4a */ - volatile u8 IPR15; /* SDMA + 0x4b */ - volatile u8 IPR16; /* SDMA + 0x4c */ - volatile u8 IPR17; /* SDMA + 0x4d */ - volatile u8 IPR18; /* SDMA + 0x4e */ - volatile u8 IPR19; /* SDMA + 0x4f */ - volatile u8 IPR20; /* SDMA + 0x50 */ - volatile u8 IPR21; /* SDMA + 0x51 */ - volatile u8 IPR22; /* SDMA + 0x52 */ - volatile u8 IPR23; /* SDMA + 0x53 */ - volatile u8 IPR24; /* SDMA + 0x54 */ - volatile u8 IPR25; /* SDMA + 0x55 */ - volatile u8 IPR26; /* SDMA + 0x56 */ - volatile u8 IPR27; /* SDMA + 0x57 */ - volatile u8 IPR28; /* SDMA + 0x58 */ - volatile u8 IPR29; /* SDMA + 0x59 */ - volatile u8 IPR30; /* SDMA + 0x5a */ - volatile u8 IPR31; /* SDMA + 0x5b */ - - volatile u32 res1; /* SDMA + 0x5c */ - volatile u32 res2; /* SDMA + 0x60 */ - volatile u32 res3; /* SDMA + 0x64 */ - volatile u32 MDEDebug; /* SDMA + 0x68 */ - volatile u32 ADSDebug; /* SDMA + 0x6c */ - volatile u32 Value1; /* SDMA + 0x70 */ - volatile u32 Value2; /* SDMA + 0x74 */ - volatile u32 Control; /* SDMA + 0x78 */ - volatile u32 Status; /* SDMA + 0x7c */ - volatile u32 EU00; /* SDMA + 0x80 */ - volatile u32 EU01; /* SDMA + 0x84 */ - volatile u32 EU02; /* SDMA + 0x88 */ - volatile u32 EU03; /* SDMA + 0x8c */ - volatile u32 EU04; /* SDMA + 0x90 */ - volatile u32 EU05; /* SDMA + 0x94 */ - volatile u32 EU06; /* SDMA + 0x98 */ - volatile u32 EU07; /* SDMA + 0x9c */ - volatile u32 EU10; /* SDMA + 0xa0 */ - volatile u32 EU11; /* SDMA + 0xa4 */ - volatile u32 EU12; /* SDMA + 0xa8 */ - volatile u32 EU13; /* SDMA + 0xac */ - volatile u32 EU14; /* SDMA + 0xb0 */ - volatile u32 EU15; /* SDMA + 0xb4 */ - volatile u32 EU16; /* SDMA + 0xb8 */ - volatile u32 EU17; /* SDMA + 0xbc */ - volatile u32 EU20; /* SDMA + 0xc0 */ - volatile u32 EU21; /* SDMA + 0xc4 */ - volatile u32 EU22; /* SDMA + 0xc8 */ - volatile u32 EU23; /* SDMA + 0xcc */ - volatile u32 EU24; /* SDMA + 0xd0 */ - volatile u32 EU25; /* SDMA + 0xd4 */ - volatile u32 EU26; /* SDMA + 0xd8 */ - volatile u32 EU27; /* SDMA + 0xdc */ - volatile u32 EU30; /* SDMA + 0xe0 */ - volatile u32 EU31; /* SDMA + 0xe4 */ - volatile u32 EU32; /* SDMA + 0xe8 */ - volatile u32 EU33; /* SDMA + 0xec */ - volatile u32 EU34; /* SDMA + 0xf0 */ - volatile u32 EU35; /* SDMA + 0xf4 */ - volatile u32 EU36; /* SDMA + 0xf8 */ - volatile u32 EU37; /* SDMA + 0xfc */ -}; - -struct mpc5xxx_i2c { - volatile u32 madr; /* I2Cn + 0x00 */ - volatile u32 mfdr; /* I2Cn + 0x04 */ - volatile u32 mcr; /* I2Cn + 0x08 */ - volatile u32 msr; /* I2Cn + 0x0C */ - volatile u32 mdr; /* I2Cn + 0x10 */ -}; - -struct mpc5xxx_spi { - volatile u8 cr1; /* SPI + 0x0F00 */ - volatile u8 cr2; /* SPI + 0x0F01 */ - volatile u8 reserved1[2]; - volatile u8 brr; /* SPI + 0x0F04 */ - volatile u8 sr; /* SPI + 0x0F05 */ - volatile u8 reserved2[3]; - volatile u8 dr; /* SPI + 0x0F09 */ - volatile u8 reserved3[3]; - volatile u8 pdr; /* SPI + 0x0F0D */ - volatile u8 reserved4[2]; - volatile u8 ddr; /* SPI + 0x0F10 */ -}; - - -struct mpc5xxx_gpt { - volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */ - volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */ - volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */ - volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */ -}; - -struct mpc5xxx_gpt_0_7 { - struct mpc5xxx_gpt gpt0; - struct mpc5xxx_gpt gpt1; - struct mpc5xxx_gpt gpt2; - struct mpc5xxx_gpt gpt3; - struct mpc5xxx_gpt gpt4; - struct mpc5xxx_gpt gpt5; - struct mpc5xxx_gpt gpt6; - struct mpc5xxx_gpt gpt7; -}; - -struct mscan_buffer { - volatile u8 idr[0x8]; /* 0x00 */ - volatile u8 dsr[0x10]; /* 0x08 */ - volatile u8 dlr; /* 0x18 */ - volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */ - volatile u16 rsrv1; /* 0x1A */ - volatile u8 tsrh; /* 0x1C */ - volatile u8 tsrl; /* 0x1D */ - volatile u16 rsrv2; /* 0x1E */ -}; - -struct mpc5xxx_mscan { - volatile u8 canctl0; /* MSCAN + 0x00 */ - volatile u8 canctl1; /* MSCAN + 0x01 */ - volatile u16 rsrv1; /* MSCAN + 0x02 */ - volatile u8 canbtr0; /* MSCAN + 0x04 */ - volatile u8 canbtr1; /* MSCAN + 0x05 */ - volatile u16 rsrv2; /* MSCAN + 0x06 */ - volatile u8 canrflg; /* MSCAN + 0x08 */ - volatile u8 canrier; /* MSCAN + 0x09 */ - volatile u16 rsrv3; /* MSCAN + 0x0A */ - volatile u8 cantflg; /* MSCAN + 0x0C */ - volatile u8 cantier; /* MSCAN + 0x0D */ - volatile u16 rsrv4; /* MSCAN + 0x0E */ - volatile u8 cantarq; /* MSCAN + 0x10 */ - volatile u8 cantaak; /* MSCAN + 0x11 */ - volatile u16 rsrv5; /* MSCAN + 0x12 */ - volatile u8 cantbsel; /* MSCAN + 0x14 */ - volatile u8 canidac; /* MSCAN + 0x15 */ - volatile u16 rsrv6[3]; /* MSCAN + 0x16 */ - volatile u8 canrxerr; /* MSCAN + 0x1C */ - volatile u8 cantxerr; /* MSCAN + 0x1D */ - volatile u16 rsrv7; /* MSCAN + 0x1E */ - volatile u8 canidar0; /* MSCAN + 0x20 */ - volatile u8 canidar1; /* MSCAN + 0x21 */ - volatile u16 rsrv8; /* MSCAN + 0x22 */ - volatile u8 canidar2; /* MSCAN + 0x24 */ - volatile u8 canidar3; /* MSCAN + 0x25 */ - volatile u16 rsrv9; /* MSCAN + 0x26 */ - volatile u8 canidmr0; /* MSCAN + 0x28 */ - volatile u8 canidmr1; /* MSCAN + 0x29 */ - volatile u16 rsrv10; /* MSCAN + 0x2A */ - volatile u8 canidmr2; /* MSCAN + 0x2C */ - volatile u8 canidmr3; /* MSCAN + 0x2D */ - volatile u16 rsrv11; /* MSCAN + 0x2E */ - volatile u8 canidar4; /* MSCAN + 0x30 */ - volatile u8 canidar5; /* MSCAN + 0x31 */ - volatile u16 rsrv12; /* MSCAN + 0x32 */ - volatile u8 canidar6; /* MSCAN + 0x34 */ - volatile u8 canidar7; /* MSCAN + 0x35 */ - volatile u16 rsrv13; /* MSCAN + 0x36 */ - volatile u8 canidmr4; /* MSCAN + 0x38 */ - volatile u8 canidmr5; /* MSCAN + 0x39 */ - volatile u16 rsrv14; /* MSCAN + 0x3A */ - volatile u8 canidmr6; /* MSCAN + 0x3C */ - volatile u8 canidmr7; /* MSCAN + 0x3D */ - volatile u16 rsrv15; /* MSCAN + 0x3E */ - - struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */ - struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */ - }; - -/* function prototypes */ -void loadtask(int basetask, int tasks); - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASMPPC_MPC5XXX_H */ diff --git a/include/asm-ppc/arch-mpc5200/sdma.h b/include/asm-ppc/arch-mpc5200/sdma.h deleted file mode 100644 index 17f22f0add..0000000000 --- a/include/asm-ppc/arch-mpc5200/sdma.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on code - * (C) Copyright Motorola, Inc., 2000 - * - * odin smartdma header file - */ - -#ifndef __MPC5XXX_SDMA_H -#define __MPC5XXX_SDMA_H - -#include <common.h> -#include <asm/arch/mpc5xxx.h> - -/* Task number assignment */ -#define FEC_RECV_TASK_NO 0 -#define FEC_XMIT_TASK_NO 1 - -/*---------------------------------------------------------------------*/ - -/* Stuff for Ethernet Tx/Rx tasks */ - -/*---------------------------------------------------------------------*/ - -/* Layout of Ethernet controller Parameter SRAM area: ----------------------------------------------------------------- -0x00: TBD_BASE, base address of TX BD ring -0x04: TBD_NEXT, address of next TX BD to be processed -0x08: RBD_BASE, base address of RX BD ring -0x0C: RBD_NEXT, address of next RX BD to be processed ---------------------------------------------------------------- -ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH). -*/ - -/* base address of SRAM area to store parameters used by Ethernet tasks */ -#define FEC_PARAM_BASE (MPC5XXX_SRAM + 0x0800) - -/* base address of SRAM area for buffer descriptors */ -#define FEC_BD_BASE (MPC5XXX_SRAM + 0x0820) - -/*---------------------------------------------------------------------*/ - -/* common shortcuts used by driver C code */ - -/*---------------------------------------------------------------------*/ - -/* Disable SmartDMA task */ -#define SDMA_TASK_DISABLE(tasknum) \ -{ \ - volatile ushort *tcr = (ushort *)(MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \ - *tcr = (*tcr) & (~0x8000); \ -} - -/* Enable SmartDMA task */ -#define SDMA_TASK_ENABLE(tasknum) \ -{ \ - volatile ushort *tcr = (ushort *) (MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \ - *tcr = (*tcr) | 0x8000; \ -} - -/* Enable interrupt */ -#define SDMA_INT_ENABLE(tasknum) \ -{ \ - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ - sdma->IntMask &= ~(1 << tasknum); \ -} - -/* Disable interrupt */ -#define SDMA_INT_DISABLE(tasknum) \ -{ \ - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ - sdma->IntMask |= (1 << tasknum); \ -} - - -/* Clear interrupt pending bits */ -#define SDMA_CLEAR_IEVENT(tasknum) \ -{ \ - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ - sdma->IntPend = (1 << tasknum); \ -} - -/* get interupt pending bit of a task */ -#define SDMA_GET_PENDINGBIT(tasknum) \ - ((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum))) - -/* get interupt mask bit of a task */ -#define SDMA_GET_MASKBIT(tasknum) \ - ((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum))) - -#endif /* __MPC5XXX_SDMA_H */ diff --git a/include/asm-ppc/atomic.h b/include/asm-ppc/atomic.h deleted file mode 100644 index 23f22df1b7..0000000000 --- a/include/asm-ppc/atomic.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * PowerPC atomic operations - */ - -#ifndef _ASM_PPC_ATOMIC_H_ -#define _ASM_PPC_ATOMIC_H_ - -#include <linux/config.h> - -#ifdef CONFIG_SMP -typedef struct { volatile int counter; } atomic_t; -#else -typedef struct { int counter; } atomic_t; -#endif - -#define ATOMIC_INIT(i) { (i) } - -#define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) - -extern void atomic_clear_mask(unsigned long mask, unsigned long *addr); -extern void atomic_set_mask(unsigned long mask, unsigned long *addr); - -extern __inline__ int atomic_add_return(int a, atomic_t *v) -{ - int t; - - __asm__ __volatile__("\n\ -1: lwarx %0,0,%3\n\ - add %0,%2,%0\n\ - stwcx. %0,0,%3\n\ - bne- 1b" - : "=&r" (t), "=m" (*v) - : "r" (a), "r" (v), "m" (*v) - : "cc"); - - return t; -} - -extern __inline__ int atomic_sub_return(int a, atomic_t *v) -{ - int t; - - __asm__ __volatile__("\n\ -1: lwarx %0,0,%3\n\ - subf %0,%2,%0\n\ - stwcx. %0,0,%3\n\ - bne- 1b" - : "=&r" (t), "=m" (*v) - : "r" (a), "r" (v), "m" (*v) - : "cc"); - - return t; -} - -extern __inline__ int atomic_inc_return(atomic_t *v) -{ - int t; - - __asm__ __volatile__("\n\ -1: lwarx %0,0,%2\n\ - addic %0,%0,1\n\ - stwcx. %0,0,%2\n\ - bne- 1b" - : "=&r" (t), "=m" (*v) - : "r" (v), "m" (*v) - : "cc"); - - return t; -} - -extern __inline__ int atomic_dec_return(atomic_t *v) -{ - int t; - - __asm__ __volatile__("\n\ -1: lwarx %0,0,%2\n\ - addic %0,%0,-1\n\ - stwcx. %0,0,%2\n\ - bne 1b" - : "=&r" (t), "=m" (*v) - : "r" (v), "m" (*v) - : "cc"); - - return t; -} - -#define atomic_add(a, v) ((void) atomic_add_return((a), (v))) -#define atomic_sub(a, v) ((void) atomic_sub_return((a), (v))) -#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0) -#define atomic_inc(v) ((void) atomic_inc_return((v))) -#define atomic_dec(v) ((void) atomic_dec_return((v))) -#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0) - -#endif /* _ASM_PPC_ATOMIC_H_ */ diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h deleted file mode 100644 index e83f0e90d2..0000000000 --- a/include/asm-ppc/bitops.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - * bitops.h: Bit string operations on the ppc - */ - -#ifndef _PPC_BITOPS_H -#define _PPC_BITOPS_H - -#include <asm/byteorder.h> - -extern void set_bit(int nr, volatile void *addr); -extern void clear_bit(int nr, volatile void *addr); -extern void change_bit(int nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void *addr); -extern int test_and_clear_bit(int nr, volatile void *addr); -extern int test_and_change_bit(int nr, volatile void *addr); - -/* - * Arguably these bit operations don't imply any memory barrier or - * SMP ordering, but in fact a lot of drivers expect them to imply - * both, since they do on x86 cpus. - */ -#ifdef CONFIG_SMP -#define SMP_WMB "eieio\n" -#define SMP_MB "\nsync" -#else -#define SMP_WMB -#define SMP_MB -#endif /* CONFIG_SMP */ - -#define __INLINE_BITOPS 1 - -#if __INLINE_BITOPS -/* - * These used to be if'd out here because using : "cc" as a constraint - * resulted in errors from egcs. Things may be OK with gcc-2.95. - */ -extern __inline__ void set_bit(int nr, volatile void * addr) -{ - unsigned long old; - unsigned long mask = 1 << (nr & 0x1f); - unsigned long *p = ((unsigned long *)addr) + (nr >> 5); - - __asm__ __volatile__(SMP_WMB "\ -1: lwarx %0,0,%3\n\ - or %0,%0,%2\n\ - stwcx. %0,0,%3\n\ - bne 1b" - SMP_MB - : "=&r" (old), "=m" (*p) - : "r" (mask), "r" (p), "m" (*p) - : "cc" ); -} - -extern __inline__ void clear_bit(int nr, volatile void *addr) -{ - unsigned long old; - unsigned long mask = 1 << (nr & 0x1f); - unsigned long *p = ((unsigned long *)addr) + (nr >> 5); - - __asm__ __volatile__(SMP_WMB "\ -1: lwarx %0,0,%3\n\ - andc %0,%0,%2\n\ - stwcx. %0,0,%3\n\ - bne 1b" - SMP_MB - : "=&r" (old), "=m" (*p) - : "r" (mask), "r" (p), "m" (*p) - : "cc"); -} - -extern __inline__ void change_bit(int nr, volatile void *addr) -{ - unsigned long old; - unsigned long mask = 1 << (nr & 0x1f); - unsigned long *p = ((unsigned long *)addr) + (nr >> 5); - - __asm__ __volatile__(SMP_WMB "\ -1: lwarx %0,0,%3\n\ - xor %0,%0,%2\n\ - stwcx. %0,0,%3\n\ - bne 1b" - SMP_MB - : "=&r" (old), "=m" (*p) - : "r" (mask), "r" (p), "m" (*p) - : "cc"); -} - -extern __inline__ int test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int old, t; - unsigned int mask = 1 << (nr & 0x1f); - volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); - - __asm__ __volatile__(SMP_WMB "\ -1: lwarx %0,0,%4\n\ - or %1,%0,%3\n\ - stwcx. %1,0,%4\n\ - bne 1b" - SMP_MB - : "=&r" (old), "=&r" (t), "=m" (*p) - : "r" (mask), "r" (p), "m" (*p) - : "cc"); - - return (old & mask) != 0; -} - -extern __inline__ int test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int old, t; - unsigned int mask = 1 << (nr & 0x1f); - volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); - - __asm__ __volatile__(SMP_WMB "\ -1: lwarx %0,0,%4\n\ - andc %1,%0,%3\n\ - stwcx. %1,0,%4\n\ - bne 1b" - SMP_MB - : "=&r" (old), "=&r" (t), "=m" (*p) - : "r" (mask), "r" (p), "m" (*p) - : "cc"); - - return (old & mask) != 0; -} - -extern __inline__ int test_and_change_bit(int nr, volatile void *addr) -{ - unsigned int old, t; - unsigned int mask = 1 << (nr & 0x1f); - volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); - - __asm__ __volatile__(SMP_WMB "\ -1: lwarx %0,0,%4\n\ - xor %1,%0,%3\n\ - stwcx. %1,0,%4\n\ - bne 1b" - SMP_MB - : "=&r" (old), "=&r" (t), "=m" (*p) - : "r" (mask), "r" (p), "m" (*p) - : "cc"); - - return (old & mask) != 0; -} -#endif /* __INLINE_BITOPS */ - -extern __inline__ int test_bit(int nr, __const__ volatile void *addr) -{ - __const__ unsigned int *p = (__const__ unsigned int *) addr; - - return ((p[nr >> 5] >> (nr & 0x1f)) & 1) != 0; -} - -/* Return the bit position of the most significant 1 bit in a word */ -extern __inline__ int __ilog2(unsigned int x) -{ - int lz; - - asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x)); - return 31 - lz; -} - -extern __inline__ int ffz(unsigned int x) -{ - if ((x = ~x) == 0) - return 32; - return __ilog2(x & -x); -} - -#ifdef __KERNEL__ - -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ -extern __inline__ int ffs(int x) -{ - return __ilog2(x & -x) + 1; -} - -#include <asm-generic/bitops/hweight.h> - -#endif /* __KERNEL__ */ - -/* - * This implementation of find_{first,next}_zero_bit was stolen from - * Linus' asm-alpha/bitops.h. - */ -#define find_first_zero_bit(addr, size) \ - find_next_zero_bit((addr), (size), 0) - -extern __inline__ unsigned long find_next_zero_bit(void * addr, - unsigned long size, unsigned long offset) -{ - unsigned int * p = ((unsigned int *) addr) + (offset >> 5); - unsigned int result = offset & ~31UL; - unsigned int tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = *p++; - tmp |= ~0UL >> (32-offset); - if (size < 32) - goto found_first; - if (tmp != ~0U) - goto found_middle; - size -= 32; - result += 32; - } - while (size >= 32) { - if ((tmp = *p++) != ~0U) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = *p; -found_first: - tmp |= ~0UL << size; -found_middle: - return result + ffz(tmp); -} - - -#define _EXT2_HAVE_ASM_BITOPS_ - -#ifdef __KERNEL__ -/* - * test_and_{set,clear}_bit guarantee atomicity without - * disabling interrupts. - */ -#define ext2_set_bit(nr, addr) test_and_set_bit((nr) ^ 0x18, addr) -#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr) ^ 0x18, addr) - -#else -extern __inline__ int ext2_set_bit(int nr, void * addr) -{ - int mask; - unsigned char *ADDR = (unsigned char *) addr; - int oldbit; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - oldbit = (*ADDR & mask) ? 1 : 0; - *ADDR |= mask; - return oldbit; -} - -extern __inline__ int ext2_clear_bit(int nr, void * addr) -{ - int mask; - unsigned char *ADDR = (unsigned char *) addr; - int oldbit; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - oldbit = (*ADDR & mask) ? 1 : 0; - *ADDR = *ADDR & ~mask; - return oldbit; -} -#endif /* __KERNEL__ */ - -extern __inline__ int ext2_test_bit(int nr, __const__ void * addr) -{ - __const__ unsigned char *ADDR = (__const__ unsigned char *) addr; - - return (ADDR[nr >> 3] >> (nr & 7)) & 1; -} - -/* - * This implementation of ext2_find_{first,next}_zero_bit was stolen from - * Linus' asm-alpha/bitops.h and modified for a big-endian machine. - */ - -#define ext2_find_first_zero_bit(addr, size) \ - ext2_find_next_zero_bit((addr), (size), 0) - -extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, - unsigned long size, unsigned long offset) -{ - unsigned int *p = ((unsigned int *) addr) + (offset >> 5); - unsigned int result = offset & ~31UL; - unsigned int tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = cpu_to_le32p(p++); - tmp |= ~0UL >> (32-offset); - if (size < 32) - goto found_first; - if (tmp != ~0U) - goto found_middle; - size -= 32; - result += 32; - } - while (size >= 32) { - if ((tmp = cpu_to_le32p(p++)) != ~0U) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = cpu_to_le32p(p); -found_first: - tmp |= ~0U << size; -found_middle: - return result + ffz(tmp); -} - -/* Bitmap functions for the minix filesystem. */ -#define minix_test_and_set_bit(nr,addr) ext2_set_bit(nr,addr) -#define minix_set_bit(nr,addr) ((void)ext2_set_bit(nr,addr)) -#define minix_test_and_clear_bit(nr,addr) ext2_clear_bit(nr,addr) -#define minix_test_bit(nr,addr) ext2_test_bit(nr,addr) -#define minix_find_first_zero_bit(addr,size) ext2_find_first_zero_bit(addr,size) - -#endif /* _PPC_BITOPS_H */ diff --git a/include/asm-ppc/byteorder.h b/include/asm-ppc/byteorder.h deleted file mode 100644 index d3e719b8a5..0000000000 --- a/include/asm-ppc/byteorder.h +++ /dev/null @@ -1,79 +0,0 @@ -#ifndef _PPC_BYTEORDER_H -#define _PPC_BYTEORDER_H - -#include <asm/types.h> - -#ifdef __GNUC__ - -extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) -{ - unsigned val; - - __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); - return val; -} - -extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val) -{ - __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); -} - -extern __inline__ unsigned ld_le32(const volatile unsigned *addr) -{ - unsigned val; - - __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); - return val; -} - -extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) -{ - __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); -} - -/* alas, egcs sounds like it has a bug in this code that doesn't use the - inline asm correctly, and can cause file corruption. Until I hear that - it's fixed, I can live without the extra speed. I hope. */ -#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90) -static __inline__ __attribute__((const)) __u16 ___arch__swab16(__u16 value) -{ - __u16 result; - - __asm__("rlwimi %0,%1,8,16,23" - : "=r" (result) - : "r" (value), "0" (value >> 8)); - return result; -} - -static __inline__ __attribute__((const)) __u32 ___arch__swab32(__u32 value) -{ - __u32 result; - - __asm__("rlwimi %0,%1,24,16,23\n\t" - "rlwimi %0,%1,8,8,15\n\t" - "rlwimi %0,%1,24,0,7" - : "=r" (result) - : "r" (value), "0" (value >> 24)); - return result; -} -#define __arch__swab32(x) ___arch__swab32(x) -#define __arch__swab16(x) ___arch__swab16(x) - -#endif - -/* The same, but returns converted value from the location pointer by addr. */ -#define __arch__swab16p(addr) ld_le16(addr) -#define __arch__swab32p(addr) ld_le32(addr) - -/* The same, but do the conversion in situ, ie. put the value back to addr. */ -#define __arch__swab16s(addr) st_le16(addr,*addr) -#define __arch__swab32s(addr) st_le32(addr,*addr) - -#endif /* __GNUC__ */ - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -#define __BYTEORDER_HAS_U64__ -#endif -#include <linux/byteorder/big_endian.h> - -#endif /* _PPC_BYTEORDER_H */ diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h deleted file mode 100644 index f37af97c07..0000000000 --- a/include/asm-ppc/cache.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * include/asm-ppc/cache.h - */ -#ifndef __ARCH_PPC_CACHE_H -#define __ARCH_PPC_CACHE_H - -#include <asm/processor.h> - -/* bytes per L1 cache line */ -#if !defined(CONFIG_8xx) || defined(CONFIG_8260) -#if defined(CONFIG_PPC64BRIDGE) -#define L1_CACHE_BYTES 128 -#else -#define L1_CACHE_BYTES 32 -#endif /* PPC64 */ -#else -#define L1_CACHE_BYTES 16 -#endif /* !8xx || 8260 */ - -#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) -#define L1_CACHE_PAGES 8 - -#define SMP_CACHE_BYTES L1_CACHE_BYTES - -#ifdef MODULE -#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) -#else -#define __cacheline_aligned \ - __attribute__((__aligned__(L1_CACHE_BYTES), \ - __section__(".data.cacheline_aligned"))) -#endif - -#if defined(__KERNEL__) && !defined(__ASSEMBLY__) -extern void flush_dcache_range(unsigned long start, unsigned long stop); -extern void clean_dcache_range(unsigned long start, unsigned long stop); -extern void invalidate_dcache_range(unsigned long start, unsigned long stop); -#ifdef CFG_INIT_RAM_LOCK -extern void unlock_ram_in_cache(void); -#endif /* CFG_INIT_RAM_LOCK */ -#endif /* __ASSEMBLY__ */ - -/* prep registers for L2 */ -#define CACHECRBA 0x80000823 /* Cache configuration register address */ -#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ -#define L2CACHE_512KB 0x00 /* 512KB */ -#define L2CACHE_256KB 0x01 /* 256KB */ -#define L2CACHE_1MB 0x02 /* 1MB */ -#define L2CACHE_NONE 0x03 /* NONE */ -#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */ - -#ifdef CONFIG_8xx -/* Cache control on the MPC8xx is provided through some additional - * special purpose registers. - */ -#define IC_CST 560 /* Instruction cache control/status */ -#define IC_ADR 561 /* Address needed for some commands */ -#define IC_DAT 562 /* Read-only data register */ -#define DC_CST 568 /* Data cache control/status */ -#define DC_ADR 569 /* Address needed for some commands */ -#define DC_DAT 570 /* Read-only data register */ - -/* Commands. Only the first few are available to the instruction cache. -*/ -#define IDC_ENABLE 0x02000000 /* Cache enable */ -#define IDC_DISABLE 0x04000000 /* Cache disable */ -#define IDC_LDLCK 0x06000000 /* Load and lock */ -#define IDC_UNLINE 0x08000000 /* Unlock line */ -#define IDC_UNALL 0x0a000000 /* Unlock all */ -#define IDC_INVALL 0x0c000000 /* Invalidate all */ - -#define DC_FLINE 0x0e000000 /* Flush data cache line */ -#define DC_SFWT 0x01000000 /* Set forced writethrough mode */ -#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ -#define DC_SLES 0x05000000 /* Set little endian swap mode */ -#define DC_CLES 0x07000000 /* Clear little endian swap mode */ - -/* Status. -*/ -#define IDC_ENABLED 0x80000000 /* Cache is enabled */ -#define IDC_CERR1 0x00200000 /* Cache error 1 */ -#define IDC_CERR2 0x00100000 /* Cache error 2 */ -#define IDC_CERR3 0x00080000 /* Cache error 3 */ - -#define DC_DFWT 0x40000000 /* Data cache is forced write through */ -#define DC_LES 0x20000000 /* Caches are little endian mode */ -#endif /* CONFIG_8xx */ - -#endif diff --git a/include/asm-ppc/common.h b/include/asm-ppc/common.h deleted file mode 100644 index 843bcf71ed..0000000000 --- a/include/asm-ppc/common.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef __ASM_COMMON_H -#define __ASM_COMMON_H - -#include <asm/u-boot.h> - -void upmconfig (unsigned int, unsigned int *, unsigned int); -ulong get_tbclk (void); - -unsigned long long get_ticks(void); - -int get_clocks (void); -ulong get_bus_freq (ulong); - -int cpu_init (void); - -uint get_pvr (void); -uint get_svr (void); - -void trap_init (ulong); - -int cpu_init_board_data(bd_t *bd); -int init_board_data(bd_t *bd); - -#endif /* __ASM_COMMON_H */ diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h deleted file mode 100644 index 79dcae416f..0000000000 --- a/include/asm-ppc/e300.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor, Inc. - * Liberty Eran (liberty@freescale.com) - */ - -#ifndef __E300_H__ -#define __E300_H__ - -/* - * e300 Processor Version & Revision Numbers - */ -#define PVR_83xx 0x80830000 -#define PVR_8349_REV10 (PVR_83xx | 0x0010) -#define PVR_8349_REV11 (PVR_83xx | 0x0011) -#define PVR_8360_REV10 (PVR_83xx | 0x0020) -#define PVR_8360_REV11 (PVR_83xx | 0x0020) - -/* - * Hardware Implementation-Dependent Register 0 (HID0) - */ - -/* #define HID0 1008 already defined in processor.h */ -#define HID0_MASK_MACHINE_CHECK 0x00000000 -#define HID0_ENABLE_MACHINE_CHECK 0x80000000 - -#define HID0_DISABLE_CACHE_PARITY 0x00000000 -#define HID0_ENABLE_CACHE_PARITY 0x40000000 - -#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */ -#define HID0_ENABLE_ADDRESS_PARITY 0x20000000 - -#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */ -#define HID0_ENABLE_DATE_PARITY 0x10000000 - -#define HID0_CORE_CLK_OUT 0x00000000 -#define HID0_CORE_CLK_OUT_DIV_2 0x08000000 - -#define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */ -#define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000 - -#define HID0_DISABLE_DOSE_MODE 0x00000000 -#define HID0_ENABLE_DOSE_MODE 0x00800000 - -#define HID0_DISABLE_NAP_MODE 0x00000000 -#define HID0_ENABLE_NAP_MODE 0x00400000 - -#define HID0_DISABLE_SLEEP_MODE 0x00000000 -#define HID0_ENABLE_SLEEP_MODE 0x00200000 - -#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000 -#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000 - -#define HID0_SOFT_RESET 0x00010000 - -#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000 -#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000 - -#define HID0_DISABLE_DATA_CACHE 0x00000000 -#define HID0_ENABLE_DATA_CACHE 0x00004000 - -#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000 - -#define HID0_LOCK_DATA_CACHE 0x00001000 - -#define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800 - -#define HID0_INVALIDATE_DATA_CACHE 0x00000400 - -#define HID0_DISABLE_M_BIT 0x00000000 -#define HID0_ENABLE_M_BIT 0x00000080 - -#define HID0_FBIOB 0x00000010 - -#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000 -#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008 - -#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000 -#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001 - -/* - * Hardware Implementation-Dependent Register 2 (HID2) - */ -#define HID2 1011 - -#define HID2_LET 0x08000000 -#define HID2_HBE 0x00040000 -#define HID2_IWLCK_000 0x00000000 /* no ways locked */ -#define HID2_IWLCK_001 0x00002000 /* way 0 locked */ -#define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */ -#define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */ -#define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */ -#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */ -#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */ - - -/* BAT (block address translation */ -#define BATU_BEPI_MSK 0xfffe0000 -#define BATU_BL_MSK 0x00001ffc - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 - -#define BATL_BRPN_MSK 0xfffe0000 -#define BATL_WIMG_MSK 0x00000078 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - -#endif /* __E300_H__ */ diff --git a/include/asm-ppc/elf.h b/include/asm-ppc/elf.h deleted file mode 100644 index 2fb48ecbcf..0000000000 --- a/include/asm-ppc/elf.h +++ /dev/null @@ -1,412 +0,0 @@ -#ifndef _ASM_POWERPC_ELF_H -#define _ASM_POWERPC_ELF_H - -#include <asm/types.h> -#include <asm/ptrace.h> -#include <asm/string.h> - -/* PowerPC relocations defined by the ABIs */ -#define R_PPC_NONE 0 -#define R_PPC_ADDR32 1 /* 32bit absolute address */ -#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ -#define R_PPC_ADDR16 3 /* 16bit absolute address */ -#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ -#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ -#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ -#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ -#define R_PPC_ADDR14_BRTAKEN 8 -#define R_PPC_ADDR14_BRNTAKEN 9 -#define R_PPC_REL24 10 /* PC relative 26 bit */ -#define R_PPC_REL14 11 /* PC relative 16 bit */ -#define R_PPC_REL14_BRTAKEN 12 -#define R_PPC_REL14_BRNTAKEN 13 -#define R_PPC_GOT16 14 -#define R_PPC_GOT16_LO 15 -#define R_PPC_GOT16_HI 16 -#define R_PPC_GOT16_HA 17 -#define R_PPC_PLTREL24 18 -#define R_PPC_COPY 19 -#define R_PPC_GLOB_DAT 20 -#define R_PPC_JMP_SLOT 21 -#define R_PPC_RELATIVE 22 -#define R_PPC_LOCAL24PC 23 -#define R_PPC_UADDR32 24 -#define R_PPC_UADDR16 25 -#define R_PPC_REL32 26 -#define R_PPC_PLT32 27 -#define R_PPC_PLTREL32 28 -#define R_PPC_PLT16_LO 29 -#define R_PPC_PLT16_HI 30 -#define R_PPC_PLT16_HA 31 -#define R_PPC_SDAREL16 32 -#define R_PPC_SECTOFF 33 -#define R_PPC_SECTOFF_LO 34 -#define R_PPC_SECTOFF_HI 35 -#define R_PPC_SECTOFF_HA 36 - -/* PowerPC relocations defined for the TLS access ABI. */ -#define R_PPC_TLS 67 /* none (sym+add)@tls */ -#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ -#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ -#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ -#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ -#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ -#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ -#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ -#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ -#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ -#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ -#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ -#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ -#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ -#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ -#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ -#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ -#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ -#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ -#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ -#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ -#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ -#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ -#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ -#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ -#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ -#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ -#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ - -/* keep this the last entry. */ -#define R_PPC_NUM 95 - -/* - * ELF register definitions.. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */ -#define ELF_NFPREG 33 /* includes fpscr */ - -typedef unsigned long elf_greg_t64; -typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG]; - -typedef unsigned int elf_greg_t32; -typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG]; - -/* - * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps. - */ -#ifdef __powerpc64__ -# define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */ -# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */ -# define ELF_GREG_TYPE elf_greg_t64 -#else -# define ELF_NEVRREG 34 /* includes acc (as 2) */ -# define ELF_NVRREG 33 /* includes vscr */ -# define ELF_GREG_TYPE elf_greg_t32 -# define ELF_ARCH EM_PPC -# define ELF_CLASS ELFCLASS32 -# define ELF_DATA ELFDATA2MSB -#endif /* __powerpc64__ */ - -#ifndef ELF_ARCH -# define ELF_ARCH EM_PPC64 -# define ELF_CLASS ELFCLASS64 -# define ELF_DATA ELFDATA2MSB - typedef elf_greg_t64 elf_greg_t; - typedef elf_gregset_t64 elf_gregset_t; -#else - /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */ - typedef elf_greg_t32 elf_greg_t; - typedef elf_gregset_t32 elf_gregset_t; -#endif /* ELF_ARCH */ - -/* Floating point registers */ -typedef double elf_fpreg_t; -typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; - -/* Altivec registers */ -/* - * The entries with indexes 0-31 contain the corresponding vector registers. - * The entry with index 32 contains the vscr as the last word (offset 12) - * within the quadword. This allows the vscr to be stored as either a - * quadword (since it must be copied via a vector register to/from storage) - * or as a word. - * - * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first - * word (offset 0) within the quadword. - * - * This definition of the VMX state is compatible with the current PPC32 - * ptrace interface. This allows signal handling and ptrace to use the same - * structures. This also simplifies the implementation of a bi-arch - * (combined (32- and 64-bit) gdb. - * - * Note that it's _not_ compatible with 32 bits ucontext which stuffs the - * vrsave along with vscr and so only uses 33 vectors for the register set - */ -#if 0 -typedef __vector128 elf_vrreg_t; -typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG]; -#ifdef __powerpc64__ -typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32]; -#endif -#endif - -#ifdef __KERNEL__ -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) - -#define USE_ELF_CORE_DUMP -#define ELF_EXEC_PAGESIZE PAGE_SIZE - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#define ELF_ET_DYN_BASE (0x20000000) - -extern void * memset(void *, int, __kernel_size_t); - -/* Common routine for both 32-bit and 64-bit processes */ -static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs, - struct pt_regs *regs) -{ - int i, nregs; - - memset((void *)elf_regs, 0, sizeof(elf_gregset_t)); - - /* Our registers are always unsigned longs, whether we're a 32 bit - * process or 64 bit, on either a 64 bit or 32 bit kernel. - * Don't use ELF_GREG_TYPE here. */ - nregs = sizeof(struct pt_regs) / sizeof(unsigned long); - if (nregs > ELF_NGREG) - nregs = ELF_NGREG; - - for (i = 0; i < nregs; i++) { - /* This will correctly truncate 64 bit registers to 32 bits - * for a 32 bit process on a 64 bit kernel. */ - elf_regs[i] = (elf_greg_t)((ELF_GREG_TYPE *)regs)[i]; - } -} -#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs); - -#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs) - -#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs) - -#endif /* __KERNEL__ */ - -/* ELF_HWCAP yields a mask that user programs can use to figure out what - instruction set this cpu supports. This could be done in userspace, - but it's not easy, and we've already done it here. */ -# define ELF_HWCAP (cur_cpu_spec->cpu_user_features) - -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. */ - -#define ELF_PLATFORM (cur_cpu_spec->platform) - -#ifdef __powerpc64__ -# define ELF_PLAT_INIT(_r, load_addr) do { \ - _r->gpr[2] = load_addr; \ -} while (0) -#endif /* __powerpc64__ */ - -#ifdef __KERNEL__ - -#ifdef __powerpc64__ -# define SET_PERSONALITY(ex, ibcs2) \ -do { \ - unsigned long new_flags = 0; \ - if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ - new_flags = _TIF_32BIT; \ - if ((current_thread_info()->flags & _TIF_32BIT) \ - != new_flags) \ - set_thread_flag(TIF_ABI_PENDING); \ - else \ - clear_thread_flag(TIF_ABI_PENDING); \ - if (personality(current->personality) != PER_LINUX32) \ - set_personality(PER_LINUX); \ -} while (0) -/* - * An executable for which elf_read_implies_exec() returns TRUE will - * have the READ_IMPLIES_EXEC personality flag set automatically. This - * is only required to work around bugs in old 32bit toolchains. Since - * the 64bit ABI has never had these issues dont enable the workaround - * even if we have an executable stack. - */ -# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \ - (exec_stk != EXSTACK_DISABLE_X) : 0) -#else -# define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX) -#endif /* __powerpc64__ */ - -#endif /* __KERNEL__ */ - -extern int dcache_bsize; -extern int icache_bsize; -extern int ucache_bsize; - -/* vDSO has arch_setup_additional_pages */ -#define ARCH_HAS_SETUP_ADDITIONAL_PAGES -struct linux_binprm; -extern int arch_setup_additional_pages(struct linux_binprm *bprm, - int executable_stack); -#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b); - -/* - * The requirements here are: - * - keep the final alignment of sp (sp & 0xf) - * - make sure the 32-bit value at the first 16 byte aligned position of - * AUXV is greater than 16 for glibc compatibility. - * AT_IGNOREPPC is used for that. - * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC, - * even if DLINFO_ARCH_ITEMS goes to zero or is undefined. - */ -#define ARCH_DLINFO \ -do { \ - /* Handle glibc compatibility. */ \ - NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \ - NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \ - /* Cache size items */ \ - NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \ - NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \ - NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \ - VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->mm->context.vdso_base) \ -} while (0) - -/* PowerPC64 relocations defined by the ABIs */ -#define R_PPC64_NONE R_PPC_NONE -#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */ -#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */ -#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */ -#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */ -#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */ -#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ -#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */ -#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN -#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN -#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */ -#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */ -#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN -#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN -#define R_PPC64_GOT16 R_PPC_GOT16 -#define R_PPC64_GOT16_LO R_PPC_GOT16_LO -#define R_PPC64_GOT16_HI R_PPC_GOT16_HI -#define R_PPC64_GOT16_HA R_PPC_GOT16_HA - -#define R_PPC64_COPY R_PPC_COPY -#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT -#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT -#define R_PPC64_RELATIVE R_PPC_RELATIVE - -#define R_PPC64_UADDR32 R_PPC_UADDR32 -#define R_PPC64_UADDR16 R_PPC_UADDR16 -#define R_PPC64_REL32 R_PPC_REL32 -#define R_PPC64_PLT32 R_PPC_PLT32 -#define R_PPC64_PLTREL32 R_PPC_PLTREL32 -#define R_PPC64_PLT16_LO R_PPC_PLT16_LO -#define R_PPC64_PLT16_HI R_PPC_PLT16_HI -#define R_PPC64_PLT16_HA R_PPC_PLT16_HA - -#define R_PPC64_SECTOFF R_PPC_SECTOFF -#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO -#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI -#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA -#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */ -#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */ -#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */ -#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */ -#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */ -#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */ -#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */ -#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */ -#define R_PPC64_PLT64 45 /* doubleword64 L + A. */ -#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */ -#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */ -#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */ -#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */ -#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */ -#define R_PPC64_TOC 51 /* doubleword64 .TOC. */ -#define R_PPC64_PLTGOT16 52 /* half16* M + A. */ -#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */ -#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */ -#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */ - -#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */ -#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */ -#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */ -#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */ -#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */ -#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */ -#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */ -#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */ -#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */ -#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */ -#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */ - -/* PowerPC64 relocations defined for the TLS access ABI. */ -#define R_PPC64_TLS 67 /* none (sym+add)@tls */ -#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ -#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ -#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ -#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ -#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ -#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ -#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ -#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ -#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ -#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ -#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ -#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ -#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ -#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ -#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ -#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ -#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ -#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ -#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ -#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ -#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ -#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ -#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ -#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ -#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ -#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ -#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ -#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ -#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ -#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ -#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ -#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ -#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ -#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ -#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ -#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ -#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ -#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ -#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ - -/* Keep this the last entry. */ -#define R_PPC64_NUM 107 - -#ifdef CONFIG_SPU_BASE -/* Notes used in ET_CORE. Note name is "SPU/<fd>/<filename>". */ -#define NT_SPU 1 - -extern int arch_notes_size(void); -extern void arch_write_notes(struct file *file); - -#define ELF_CORE_EXTRA_NOTES_SIZE arch_notes_size() -#define ELF_CORE_WRITE_EXTRA_NOTES arch_write_notes(file) - -#define ARCH_HAVE_EXTRA_ELF_NOTES -#endif /* CONFIG_PPC_CELL */ - -#endif /* _ASM_POWERPC_ELF_H */ diff --git a/include/asm-ppc/fsl_i2c.h b/include/asm-ppc/fsl_i2c.h deleted file mode 100644 index 4f71341327..0000000000 --- a/include/asm-ppc/fsl_i2c.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Freescale I2C Controller - * - * Copyright 2006 Freescale Semiconductor, Inc. - * - * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>, - * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com), - * and Jeff Brown. - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_FSL_I2C_H_ -#define _ASM_FSL_I2C_H_ - -#include <asm/types.h> - -typedef struct fsl_i2c { - - u8 adr; /* I2C slave address */ - u8 res0[3]; -#define I2C_ADR 0xFE -#define I2C_ADR_SHIFT 1 -#define I2C_ADR_RES ~(I2C_ADR) - - u8 fdr; /* I2C frequency divider register */ - u8 res1[3]; -#define IC2_FDR 0x3F -#define IC2_FDR_SHIFT 0 -#define IC2_FDR_RES ~(IC2_FDR) - - u8 cr; /* I2C control redister */ - u8 res2[3]; -#define I2C_CR_MEN 0x80 -#define I2C_CR_MIEN 0x40 -#define I2C_CR_MSTA 0x20 -#define I2C_CR_MTX 0x10 -#define I2C_CR_TXAK 0x08 -#define I2C_CR_RSTA 0x04 -#define I2C_CR_BCST 0x01 - - u8 sr; /* I2C status register */ - u8 res3[3]; -#define I2C_SR_MCF 0x80 -#define I2C_SR_MAAS 0x40 -#define I2C_SR_MBB 0x20 -#define I2C_SR_MAL 0x10 -#define I2C_SR_BCSTM 0x08 -#define I2C_SR_SRW 0x04 -#define I2C_SR_MIF 0x02 -#define I2C_SR_RXAK 0x01 - - u8 dr; /* I2C data register */ - u8 res4[3]; -#define I2C_DR 0xFF -#define I2C_DR_SHIFT 0 -#define I2C_DR_RES ~(I2C_DR) - - u8 dfsrr; /* I2C digital filter sampling rate register */ - u8 res5[3]; -#define I2C_DFSRR 0x3F -#define I2C_DFSRR_SHIFT 0 -#define I2C_DFSRR_RES ~(I2C_DR) - - /* Fill out the reserved block */ - u8 res6[0xE8]; -} fsl_i2c_t; - -#endif /* _ASM_I2C_H_ */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h deleted file mode 100644 index 482c100d89..0000000000 --- a/include/asm-ppc/global_data.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H - -#include "asm/types.h" - -/* - * The following data structure is placed in some memory wich is - * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or - * some locked parts of the data cache) to allow for a minimum set of - * global variables during system initialization (until we have set - * up the memory controller so that we can use RAM). - * - * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) - */ - -typedef struct global_data { - bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long cpu_clk; /* CPU clock in Hz! */ - unsigned long bus_clk; -#if defined(CONFIG_CPM2) - /* There are many clocks on the MPC8260 - see page 9-5 */ - unsigned long vco_out; - unsigned long cpm_clk; - unsigned long scc_clk; - unsigned long brg_clk; -#endif -#if defined(CONFIG_MPC83XX) - /* There are other clocks in the MPC83XX */ - u32 csb_clk; -#if defined (CONFIG_MPC8349) - u32 tsec1_clk; - u32 tsec2_clk; - u32 usbmph_clk; - u32 usbdr_clk; -#endif /* CONFIG_MPC8349 */ - u32 core_clk; - u32 i2c1_clk; - u32 i2c2_clk; - u32 enc_clk; - u32 lbiu_clk; - u32 lclk_clk; - u32 ddr_clk; - u32 pci_clk; -#if defined(CONFIG_QE) - u32 qe_clk; - u32 brg_clk; - uint mp_alloc_base; - uint mp_alloc_top; -#endif /* CONFIG_QE */ -#if defined (CONFIG_MPC8360) - u32 ddr_sec_clk; -#endif /* CONFIG_MPC8360 */ -#endif -#if defined(CONFIG_MPC5xxx) - unsigned long ipb_clk; - unsigned long pci_clk; -#endif -#if defined(CONFIG_MPC8220) - unsigned long bExtUart; - unsigned long inp_clk; - unsigned long pci_clk; - unsigned long vco_clk; - unsigned long pev_clk; - unsigned long flb_clk; -#endif -// unsigned long ram_size; /* RAM size */ - unsigned long reloc_off; /* Relocation Offset */ - unsigned long reset_status; /* reset status register at boot */ - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid? */ - unsigned long have_console; /* serial_init() was called */ -#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_CPM2) - unsigned int dp_alloc_base; - unsigned int dp_alloc_top; -#endif -#if defined(CFG_GT_6426x) - unsigned int mirror_hack[16]; -#endif -#if defined(CONFIG_A3000) || \ - defined(CONFIG_HIDDEN_DRAGON) || \ - defined(CONFIG_MUSENKI) || \ - defined(CONFIG_SANDPOINT) - void * console_addr; -#endif -#ifdef CONFIG_AMIGAONEG3SE - unsigned long relocaddr; /* Start address of U-Boot in RAM */ -#endif -#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) - unsigned long fb_base; /* Base address of framebuffer memory */ -#endif -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - unsigned long post_log_word; /* Record POST activities */ - unsigned long post_init_f_time; /* When post_init_f started */ -#endif -#ifdef CONFIG_BOARD_TYPES - unsigned long board_type; -#endif -#ifdef CONFIG_MODEM_SUPPORT - unsigned long do_mdm_init; - unsigned long be_quiet; -#endif -#ifdef CONFIG_LWMON - unsigned long kbd_status; -#endif - void **jt; /* jump table */ -} gd_t; - -/* - * Global Data Flags - */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ - -#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h deleted file mode 100644 index 052ae152e9..0000000000 --- a/include/asm-ppc/io.h +++ /dev/null @@ -1,195 +0,0 @@ -/* originally from linux source. - * removed the dependencies on CONFIG_ values - * removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__) - * Modified By Rob Taylor, Flying Pig Systems, 2000 - */ - -#ifndef _PPC_IO_H -#define _PPC_IO_H - -#include <asm/byteorder.h> - -#define SIO_CONFIG_RA 0x398 -#define SIO_CONFIG_RD 0x399 - - -#define readb(addr) in_8((volatile u8 *)(addr)) -#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) -#if !defined(__BIG_ENDIAN) -#define readw(addr) (*(volatile u16 *) (addr)) -#define readl(addr) (*(volatile u32 *) (addr)) -#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) -#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) -#else -#define readw(addr) in_le16((volatile u16 *)(addr)) -#define readl(addr) in_le32((volatile u32 *)(addr)) -#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) -#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) -#endif - -/* - * The insw/outsw/insl/outsl macros don't do byte-swapping. - * They are only used in practice for transferring buffers which - * are arrays of bytes, and byte-swapping is not appropriate in - * that case. - paulus - */ -#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) - -#define inb(port) in_8((u8 *)((port)+_IO_BASE)) -#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) -#if !defined(__BIG_ENDIAN) -#define inw(port) in_be16((u16 *)((port)+_IO_BASE)) -#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) -#define inl(port) in_be32((u32 *)((port)+_IO_BASE)) -#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) -#else -#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) -#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) -#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) -#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) -#endif - -#define inb_p(port) in_8((u8 *)((port)+_IO_BASE)) -#define outb_p(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) -#define inw_p(port) in_le16((u16 *)((port)+_IO_BASE)) -#define outw_p(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) -#define inl_p(port) in_le32((u32 *)((port)+_IO_BASE)) -#define outl_p(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) - -extern void _insb(volatile u8 *port, void *buf, int ns); -extern void _outsb(volatile u8 *port, const void *buf, int ns); -extern void _insw(volatile u16 *port, void *buf, int ns); -extern void _outsw(volatile u16 *port, const void *buf, int ns); -extern void _insl(volatile u32 *port, void *buf, int nl); -extern void _outsl(volatile u32 *port, const void *buf, int nl); -extern void _insw_ns(volatile u16 *port, void *buf, int ns); -extern void _outsw_ns(volatile u16 *port, const void *buf, int ns); -extern void _insl_ns(volatile u32 *port, void *buf, int nl); -extern void _outsl_ns(volatile u32 *port, const void *buf, int nl); - -/* - * The *_ns versions below don't do byte-swapping. - * Neither do the standard versions now, these are just here - * for older code. - */ -#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) - - -#define IO_SPACE_LIMIT ~0 - -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) - -/* - * Enforce In-order Execution of I/O: - * Acts as a barrier to ensure all previous I/O accesses have - * completed before any further ones are issued. - */ -#define eieio() __asm__ __volatile__ ("eieio" : : : "memory"); -#define sync() __asm__ __volatile__ ("sync" : : : "memory"); - -/* Enforce in-order execution of data I/O. - * No distinction between read/write on PPC; use eieio for all three. - */ -#define iobarrier_rw() eieio() -#define iobarrier_r() eieio() -#define iobarrier_w() eieio() - -/* - * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. - */ -extern inline int in_8(volatile u8 *addr) -{ - int ret; - - __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_8(volatile u8 *addr, int val) -{ - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} - -extern inline int in_le16(volatile u16 *addr) -{ - int ret; - - __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} - -extern inline int in_be16(volatile u16 *addr) -{ - int ret; - - __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_le16(volatile u16 *addr, int val) -{ - __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : - "r" (val), "r" (addr)); -} - -extern inline void out_be16(volatile u16 *addr, int val) -{ - __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} - -extern inline unsigned in_le32(volatile u32 *addr) -{ - unsigned ret; - - __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} - -extern inline unsigned in_be32(volatile u32 *addr) -{ - unsigned ret; - - __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_le32(volatile unsigned *addr, int val) -{ - __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : - "r" (val), "r" (addr)); -} - -extern inline void out_be32(volatile unsigned *addr, int val) -{ - __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} - -/* these ones were originally in config.h */ -unsigned char in8(unsigned int); -void out8(unsigned int, unsigned char); -unsigned short in16(unsigned int); -unsigned short in16r(unsigned int); -void out16(unsigned int, unsigned short value); -void out16r(unsigned int, unsigned short value); -unsigned long in32(unsigned int); -unsigned long in32r(unsigned int); -void out32(unsigned int, unsigned long value); -void out32r(unsigned int, unsigned long value); -void ppcDcbf(unsigned long value); -void ppcDcbi(unsigned long value); -void ppcSync(void); -void ppcDcbz(unsigned long value); - -#endif diff --git a/include/asm-ppc/mc146818rtc.h b/include/asm-ppc/mc146818rtc.h deleted file mode 100644 index 5f806c4ec2..0000000000 --- a/include/asm-ppc/mc146818rtc.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Machine dependent access functions for RTC registers. - */ -#ifndef __ASM_PPC_MC146818RTC_H -#define __ASM_PPC_MC146818RTC_H - -#include <asm/io.h> - -#ifndef RTC_PORT -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ -#endif - -/* - * The yet supported machines all access the RTC index register via - * an ISA port access but the way to access the date register differs ... - */ -#define CMOS_READ(addr) ({ \ -outb_p((addr),RTC_PORT(0)); \ -inb_p(RTC_PORT(1)); \ -}) -#define CMOS_WRITE(val, addr) ({ \ -outb_p((addr),RTC_PORT(0)); \ -outb_p((val),RTC_PORT(1)); \ -}) - -#endif /* __ASM_PPC_MC146818RTC_H */ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h deleted file mode 100644 index 1667041a8c..0000000000 --- a/include/asm-ppc/mmu.h +++ /dev/null @@ -1,524 +0,0 @@ -/* - * PowerPC memory management structures - */ - -#ifndef _PPC_MMU_H_ -#define _PPC_MMU_H_ - -#ifndef __ASSEMBLY__ -/* Hardware Page Table Entry */ -typedef struct _PTE { -#ifdef CONFIG_PPC64BRIDGE - unsigned long long vsid:52; - unsigned long api:5; - unsigned long :5; - unsigned long h:1; - unsigned long v:1; - unsigned long long rpn:52; -#else /* CONFIG_PPC64BRIDGE */ - unsigned long v:1; /* Entry is valid */ - unsigned long vsid:24; /* Virtual segment identifier */ - unsigned long h:1; /* Hash algorithm indicator */ - unsigned long api:6; /* Abbreviated page index */ - unsigned long rpn:20; /* Real (physical) page number */ -#endif /* CONFIG_PPC64BRIDGE */ - unsigned long :3; /* Unused */ - unsigned long r:1; /* Referenced */ - unsigned long c:1; /* Changed */ - unsigned long w:1; /* Write-thru cache mode */ - unsigned long i:1; /* Cache inhibited */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page protection */ -} PTE; - -/* Values for PP (assumes Ks=0, Kp=1) */ -#define PP_RWXX 0 /* Supervisor read/write, User none */ -#define PP_RWRX 1 /* Supervisor read/write, User read */ -#define PP_RWRW 2 /* Supervisor read/write, User read/write */ -#define PP_RXRX 3 /* Supervisor read, User read */ - -/* Segment Register */ -typedef struct _SEGREG { - unsigned long t:1; /* Normal or I/O type */ - unsigned long ks:1; /* Supervisor 'key' (normally 0) */ - unsigned long kp:1; /* User 'key' (normally 1) */ - unsigned long n:1; /* No-execute */ - unsigned long :4; /* Unused */ - unsigned long vsid:24; /* Virtual Segment Identifier */ -} SEGREG; - -/* Block Address Translation (BAT) Registers */ -typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ - unsigned long bepi:15; /* Effective page index (virtual address) */ - unsigned long :8; /* unused */ - unsigned long w:1; - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long ks:1; /* Supervisor key (normally 0) */ - unsigned long kp:1; /* User key (normally 1) */ - unsigned long pp:2; /* Page access protections */ -} P601_BATU; - -typedef struct _BATU { /* Upper part of BAT (all except 601) */ -#ifdef CONFIG_PPC64BRIDGE - unsigned long long bepi:47; -#else /* CONFIG_PPC64BRIDGE */ - unsigned long bepi:15; /* Effective page index (virtual address) */ -#endif /* CONFIG_PPC64BRIDGE */ - unsigned long :4; /* Unused */ - unsigned long bl:11; /* Block size mask */ - unsigned long vs:1; /* Supervisor valid */ - unsigned long vp:1; /* User valid */ -} BATU; - -typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ - unsigned long brpn:15; /* Real page index (physical address) */ - unsigned long :10; /* Unused */ - unsigned long v:1; /* Valid bit */ - unsigned long bl:6; /* Block size mask */ -} P601_BATL; - -typedef struct _BATL { /* Lower part of BAT (all except 601) */ -#ifdef CONFIG_PPC64BRIDGE - unsigned long long brpn:47; -#else /* CONFIG_PPC64BRIDGE */ - unsigned long brpn:15; /* Real page index (physical address) */ -#endif /* CONFIG_PPC64BRIDGE */ - unsigned long :10; /* Unused */ - unsigned long w:1; /* Write-thru cache */ - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded (MBZ in IBAT) */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page access protections */ -} BATL; - -typedef struct _BAT { - BATU batu; /* Upper register */ - BATL batl; /* Lower register */ -} BAT; - -typedef struct _P601_BAT { - P601_BATU batu; /* Upper register */ - P601_BATL batl; /* Lower register */ -} P601_BAT; - -/* - * Simulated two-level MMU. This structure is used by the kernel - * to keep track of MMU mappings and is used to update/maintain - * the hardware HASH table which is really a cache of mappings. - * - * The simulated structures mimic the hardware available on other - * platforms, notably the 80x86 and 680x0. - */ - -typedef struct _pte { - unsigned long page_num:20; - unsigned long flags:12; /* Page flags (some unused bits) */ -} pte; - -#define PD_SHIFT (10+12) /* Page directory */ -#define PD_MASK 0x02FF -#define PT_SHIFT (12) /* Page Table */ -#define PT_MASK 0x02FF -#define PG_SHIFT (12) /* Page Entry */ - - -/* MMU context */ - -typedef struct _MMU_context { - SEGREG segs[16]; /* Segment registers */ - pte **pmap; /* Two-level page-map structure */ -} MMU_context; - -extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ -extern void _tlbia(void); /* invalidate all TLB entries */ - -typedef enum { - IBAT0 = 0, IBAT1, IBAT2, IBAT3, - DBAT0, DBAT1, DBAT2, DBAT3 -} ppc_bat_t; - -extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower); -extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); - -#endif /* __ASSEMBLY__ */ - -/* Block size masks */ -#define BL_128K 0x000 -#define BL_256K 0x001 -#define BL_512K 0x003 -#define BL_1M 0x007 -#define BL_2M 0x00F -#define BL_4M 0x01F -#define BL_8M 0x03F -#define BL_16M 0x07F -#define BL_32M 0x0FF -#define BL_64M 0x1FF -#define BL_128M 0x3FF -#define BL_256M 0x7FF - -/* BAT Access Protection */ -#define BPP_XX 0x00 /* No access */ -#define BPP_RX 0x01 /* Read only */ -#define BPP_RW 0x02 /* Read/write */ - -/* Used to set up SDR1 register */ -#define HASH_TABLE_SIZE_64K 0x00010000 -#define HASH_TABLE_SIZE_128K 0x00020000 -#define HASH_TABLE_SIZE_256K 0x00040000 -#define HASH_TABLE_SIZE_512K 0x00080000 -#define HASH_TABLE_SIZE_1M 0x00100000 -#define HASH_TABLE_SIZE_2M 0x00200000 -#define HASH_TABLE_SIZE_4M 0x00400000 -#define HASH_TABLE_MASK_64K 0x000 -#define HASH_TABLE_MASK_128K 0x001 -#define HASH_TABLE_MASK_256K 0x003 -#define HASH_TABLE_MASK_512K 0x007 -#define HASH_TABLE_MASK_1M 0x00F -#define HASH_TABLE_MASK_2M 0x01F -#define HASH_TABLE_MASK_4M 0x03F - -/* Control/status registers for the MPC8xx. - * A write operation to these registers causes serialized access. - * During software tablewalk, the registers used perform mask/shift-add - * operations when written/read. A TLB entry is created when the Mx_RPN - * is written, and the contents of several registers are used to - * create the entry. - */ -#define MI_CTR 784 /* Instruction TLB control register */ -#define MI_GPM 0x80000000 /* Set domain manager mode */ -#define MI_PPM 0x40000000 /* Set subpage protection */ -#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ -#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ -#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ -#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ -#define MI_RESETVAL 0x00000000 /* Value of register at reset */ - -/* These are the Ks and Kp from the PowerPC books. For proper operation, - * Ks = 0, Kp = 1. - */ -#define MI_AP 786 -#define MI_Ks 0x80000000 /* Should not be set */ -#define MI_Kp 0x40000000 /* Should always be set */ - -/* The effective page number register. When read, contains the information - * about the last instruction TLB miss. When MI_RPN is written, bits in - * this register are used to create the TLB entry. - */ -#define MI_EPN 787 -#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ -#define MI_EVALID 0x00000200 /* Entry is valid */ -#define MI_ASIDMASK 0x0000000f /* ASID match value */ - /* Reset value is undefined */ - -/* A "level 1" or "segment" or whatever you want to call it register. - * For the instruction TLB, it contains bits that get loaded into the - * TLB entry when the MI_RPN is written. - */ -#define MI_TWC 789 -#define MI_APG 0x000001e0 /* Access protection group (0) */ -#define MI_GUARDED 0x00000010 /* Guarded storage */ -#define MI_PSMASK 0x0000000c /* Mask of page size bits */ -#define MI_PS8MEG 0x0000000c /* 8M page size */ -#define MI_PS512K 0x00000004 /* 512K page size */ -#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ -#define MI_SVALID 0x00000001 /* Segment entry is valid */ - /* Reset value is undefined */ - -/* Real page number. Defined by the pte. Writing this register - * causes a TLB entry to be created for the instruction TLB, using - * additional information from the MI_EPN, and MI_TWC registers. - */ -#define MI_RPN 790 - -/* Define an RPN value for mapping kernel memory to large virtual - * pages for boot initialization. This has real page number of 0, - * large page size, shared page, cache enabled, and valid. - * Also mark all subpages valid and write access. - */ -#define MI_BOOTINIT 0x000001fd - -#define MD_CTR 792 /* Data TLB control register */ -#define MD_GPM 0x80000000 /* Set domain manager mode */ -#define MD_PPM 0x40000000 /* Set subpage protection */ -#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ -#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ -#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ -#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ -#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ -#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ -#define MD_RESETVAL 0x04000000 /* Value of register at reset */ - -#define M_CASID 793 /* Address space ID (context) to match */ -#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ - - -/* These are the Ks and Kp from the PowerPC books. For proper operation, - * Ks = 0, Kp = 1. - */ -#define MD_AP 794 -#define MD_Ks 0x80000000 /* Should not be set */ -#define MD_Kp 0x40000000 /* Should always be set */ - -/* The effective page number register. When read, contains the information - * about the last instruction TLB miss. When MD_RPN is written, bits in - * this register are used to create the TLB entry. - */ -#define MD_EPN 795 -#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ -#define MD_EVALID 0x00000200 /* Entry is valid */ -#define MD_ASIDMASK 0x0000000f /* ASID match value */ - /* Reset value is undefined */ - -/* The pointer to the base address of the first level page table. - * During a software tablewalk, reading this register provides the address - * of the entry associated with MD_EPN. - */ -#define M_TWB 796 -#define M_L1TB 0xfffff000 /* Level 1 table base address */ -#define M_L1INDX 0x00000ffc /* Level 1 index, when read */ - /* Reset value is undefined */ - -/* A "level 1" or "segment" or whatever you want to call it register. - * For the data TLB, it contains bits that get loaded into the TLB entry - * when the MD_RPN is written. It is also provides the hardware assist - * for finding the PTE address during software tablewalk. - */ -#define MD_TWC 797 -#define MD_L2TB 0xfffff000 /* Level 2 table base address */ -#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ -#define MD_APG 0x000001e0 /* Access protection group (0) */ -#define MD_GUARDED 0x00000010 /* Guarded storage */ -#define MD_PSMASK 0x0000000c /* Mask of page size bits */ -#define MD_PS8MEG 0x0000000c /* 8M page size */ -#define MD_PS512K 0x00000004 /* 512K page size */ -#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ -#define MD_WT 0x00000002 /* Use writethrough page attribute */ -#define MD_SVALID 0x00000001 /* Segment entry is valid */ - /* Reset value is undefined */ - - -/* Real page number. Defined by the pte. Writing this register - * causes a TLB entry to be created for the data TLB, using - * additional information from the MD_EPN, and MD_TWC registers. - */ -#define MD_RPN 798 - -/* This is a temporary storage register that could be used to save - * a processor working register during a tablewalk. - */ -#define M_TW 799 - -/* - * At present, all PowerPC 400-class processors share a similar TLB - * architecture. The instruction and data sides share a unified, - * 64-entry, fully-associative TLB which is maintained totally under - * software control. In addition, the instruction side has a - * hardware-managed, 4-entry, fully- associative TLB which serves as a - * first level to the shared TLB. These two TLBs are known as the UTLB - * and ITLB, respectively. - */ - -#define PPC4XX_TLB_SIZE 64 - -/* - * TLB entries are defined by a "high" tag portion and a "low" data - * portion. On all architectures, the data portion is 32-bits. - * - * TLB entries are managed entirely under software control by reading, - * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx - * instructions. - */ - -#define TLB_LO 1 -#define TLB_HI 0 - -#define TLB_DATA TLB_LO -#define TLB_TAG TLB_HI - -/* Tag portion */ - -#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ -#define TLB_PAGESZ_MASK 0x00000380 -#define TLB_PAGESZ(x) (((x) & 0x7) << 7) -#define PAGESZ_1K 0 -#define PAGESZ_4K 1 -#define PAGESZ_16K 2 -#define PAGESZ_64K 3 -#define PAGESZ_256K 4 -#define PAGESZ_1M 5 -#define PAGESZ_4M 6 -#define PAGESZ_16M 7 -#define TLB_VALID 0x00000040 /* Entry is valid */ - -/* Data portion */ - -#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ -#define TLB_PERM_MASK 0x00000300 -#define TLB_EX 0x00000200 /* Instruction execution allowed */ -#define TLB_WR 0x00000100 /* Writes permitted */ -#define TLB_ZSEL_MASK 0x000000F0 -#define TLB_ZSEL(x) (((x) & 0xF) << 4) -#define TLB_ATTR_MASK 0x0000000F -#define TLB_W 0x00000008 /* Caching is write-through */ -#define TLB_I 0x00000004 /* Caching is inhibited */ -#define TLB_M 0x00000002 /* Memory is coherent */ -#define TLB_G 0x00000001 /* Memory is guarded from prefetch */ - -/* - * e500 support - */ - -#define MAS0_TLBSEL 0x10000000 -#define MAS0_ESEL 0x000F0000 -#define MAS0_NV 0x00000001 - -#define MAS1_VALID 0x80000000 -#define MAS1_IPROT 0x40000000 -#define MAS1_TID 0x00FF0000 -#define MAS1_TS 0x00001000 -#define MAS1_TSIZE 0x00000F00 - -#define MAS2_EPN 0xFFFFF000 -#define MAS2_SHAREN 0x00000200 -#define MAS2_X0 0x00000040 -#define MAS2_X1 0x00000020 -#define MAS2_W 0x00000010 -#define MAS2_I 0x00000008 -#define MAS2_M 0x00000004 -#define MAS2_G 0x00000002 -#define MAS2_E 0x00000001 - -#define MAS3_RPN 0xFFFFF000 -#define MAS3_U0 0x00000200 -#define MAS3_U1 0x00000100 -#define MAS3_U2 0x00000080 -#define MAS3_U3 0x00000040 -#define MAS3_UX 0x00000020 -#define MAS3_SX 0x00000010 -#define MAS3_UW 0x00000008 -#define MAS3_SW 0x00000004 -#define MAS3_UR 0x00000002 -#define MAS3_SR 0x00000001 - -#define MAS4_TLBSELD 0x10000000 -#define MAS4_TIDDSEL 0x00030000 -#define MAS4_DSHAREN 0x00001000 -#define MAS4_TSIZED(x) (x << 8) -#define MAS4_X0D 0x00000040 -#define MAS4_X1D 0x00000020 -#define MAS4_WD 0x00000010 -#define MAS4_ID 0x00000008 -#define MAS4_MD 0x00000004 -#define MAS4_GD 0x00000002 -#define MAS4_ED 0x00000001 - -#define MAS6_SPID 0x00FF0000 -#define MAS6_SAS 0x00000001 - -#define BOOKE_PAGESZ_1K 0 -#define BOOKE_PAGESZ_4K 1 -#define BOOKE_PAGESZ_16K 2 -#define BOOKE_PAGESZ_64K 3 -#define BOOKE_PAGESZ_256K 4 -#define BOOKE_PAGESZ_1M 5 -#define BOOKE_PAGESZ_4M 6 -#define BOOKE_PAGESZ_16M 7 -#define BOOKE_PAGESZ_64M 8 -#define BOOKE_PAGESZ_256M 9 -#define BOOKE_PAGESZ_1GB 10 -#define BOOKE_PAGESZ_4GB 11 - -#if defined(CONFIG_MPC86xx) -#define LAWBAR_BASE_ADDR 0x00FFFFFF -#define LAWAR_TRGT_IF 0x01F00000 -#else -#define LAWBAR_BASE_ADDR 0x000FFFFF -#define LAWAR_TRGT_IF 0x00F00000 -#endif -#define LAWAR_EN 0x80000000 -#define LAWAR_SIZE 0x0000003F - -#define LAWAR_TRGT_IF_PCI 0x00000000 -#define LAWAR_TRGT_IF_PCI1 0x00000000 -#define LAWAR_TRGT_IF_PCIX 0x00000000 -#define LAWAR_TRGT_IF_PCI2 0x00100000 -#define LAWAR_TRGT_IF_LBC 0x00400000 -#define LAWAR_TRGT_IF_CCSR 0x00800000 -#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 -#define LAWAR_TRGT_IF_RIO 0x00c00000 -#define LAWAR_TRGT_IF_DDR 0x00f00000 -#define LAWAR_TRGT_IF_DDR1 0x00f00000 -#define LAWAR_TRGT_IF_DDR2 0x01600000 - -#define LAWAR_SIZE_BASE 0xa -#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) -#define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2) -#define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3) -#define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4) -#define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5) -#define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6) -#define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7) -#define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8) -#define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9) -#define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10) -#define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11) -#define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12) -#define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13) -#define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14) -#define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15) -#define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16) -#define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17) -#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) -#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) -#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) -#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) -#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) -#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) -#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) - -#ifdef CONFIG_440SPE -/*----------------------------------------------------------------------------+ -| Following instructions are not available in Book E mode of the GNU assembler. -+----------------------------------------------------------------------------*/ -#define DCCCI(ra,rb) .long 0x7c000000|\ - (ra<<16)|(rb<<11)|(454<<1) - -#define ICCCI(ra,rb) .long 0x7c000000|\ - (ra<<16)|(rb<<11)|(966<<1) - -#define DCREAD(rt,ra,rb) .long 0x7c000000|\ - (rt<<21)|(ra<<16)|(rb<<11)|(486<<1) - -#define ICREAD(ra,rb) .long 0x7c000000|\ - (ra<<16)|(rb<<11)|(998<<1) - -#define TLBSX(rt,ra,rb) .long 0x7c000000|\ - (rt<<21)|(ra<<16)|(rb<<11)|(914<<1) - -#define TLBWE(rs,ra,ws) .long 0x7c000000|\ - (rs<<21)|(ra<<16)|(ws<<11)|(978<<1) - -#define TLBRE(rt,ra,ws) .long 0x7c000000|\ - (rt<<21)|(ra<<16)|(ws<<11)|(946<<1) - -#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\ - (rt<<21)|(ra<<16)|(rb<<11)|(914<<1) - -#define MSYNC .long 0x7c000000|\ - (598<<1) - -#define MBAR_INST .long 0x7c000000|\ - (854<<1) - -/*----------------------------------------------------------------------------+ -| Following instruction is not available in PPC405 mode of the GNU assembler. -+----------------------------------------------------------------------------*/ -#define TLBRE(rt,ra,ws) .long 0x7c000000|\ - (rt<<21)|(ra<<16)|(ws<<11)|(946<<1) - -#endif -#endif /* _PPC_MMU_H_ */ diff --git a/include/asm-ppc/module.h b/include/asm-ppc/module.h deleted file mode 100644 index 09c04402c5..0000000000 --- a/include/asm-ppc/module.h +++ /dev/null @@ -1,16 +0,0 @@ - -/**/ -struct mod_arch_specific { - /* Indices of PLT sections within module. */ - unsigned int core_plt_section; - unsigned int init_plt_section; -}; - -#define Elf_Shdr Elf32_Shdr -#define Elf_Sym Elf32_Sym -#define Elf_Ehdr Elf32_Ehdr - -struct ppc_plt_entry { - /* 16 byte jump instruction sequence (4 instructions) */ - unsigned int jump[4]; -}; diff --git a/include/asm-ppc/pci_io.h b/include/asm-ppc/pci_io.h deleted file mode 100644 index 9b738c383f..0000000000 --- a/include/asm-ppc/pci_io.h +++ /dev/null @@ -1,43 +0,0 @@ -/* originally from linux source (asm-ppc/io.h). - * Sanity added by Rob Taylor, Flying Pig Systems, 2000 - */ -#ifndef _PCI_IO_H_ -#define _PCI_IO_H_ - -#include "io.h" - - -#define pci_read_le16(addr, dest) \ - __asm__ __volatile__("lhbrx %0,0,%1" : "=r" (dest) : \ - "r" (addr), "m" (*addr)); - -#define pci_write_le16(addr, val) \ - __asm__ __volatile__("sthbrx %1,0,%2" : "=m" (*addr) : \ - "r" (val), "r" (addr)); - - -#define pci_read_le32(addr, dest) \ - __asm__ __volatile__("lwbrx %0,0,%1" : "=r" (dest) : \ - "r" (addr), "m" (*addr)); - -#define pci_write_le32(addr, val) \ -__asm__ __volatile__("stwbrx %1,0,%2" : "=m" (*addr) : \ - "r" (val), "r" (addr)); - -#define pci_readb(addr,b) ((b) = *(volatile u8 *) (addr)) -#define pci_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b)) - -#if !defined(__BIG_ENDIAN) -#define pci_readw(addr,b) ((b) = *(volatile u16 *) (addr)) -#define pci_readl(addr,b) ((b) = *(volatile u32 *) (addr)) -#define pci_writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) -#define pci_writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) -#else -#define pci_readw(addr,b) pci_read_le16((volatile u16 *)(addr),(b)) -#define pci_readl(addr,b) pci_read_le32((volatile u32 *)(addr),(b)) -#define pci_writew(b,addr) pci_write_le16((volatile u16 *)(addr),(b)) -#define pci_writel(b,addr) pci_write_le32((volatile u32 *)(addr),(b)) -#endif - - -#endif /* _PCI_IO_H_ */ diff --git a/include/asm-ppc/posix_types.h b/include/asm-ppc/posix_types.h deleted file mode 100644 index 9170728117..0000000000 --- a/include/asm-ppc/posix_types.h +++ /dev/null @@ -1,109 +0,0 @@ -#ifndef _PPC_POSIX_TYPES_H -#define _PPC_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned int __kernel_dev_t; -typedef unsigned int __kernel_ino_t; -typedef unsigned int __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned int __kernel_uid_t; -typedef unsigned int __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef long __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned int __kernel_old_uid_t; -typedef unsigned int __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { - int val[2]; -} __kernel_fsid_t; - -#ifndef __GNUC__ - -#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) -#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) -#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) -#define __FD_ZERO(set) \ - ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set))) - -#else /* __GNUC__ */ - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \ - || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0) -/* With GNU C, use inline functions instead so args are evaluated only once: */ - -#undef __FD_SET -static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp) -{ - unsigned long _tmp = fd / __NFDBITS; - unsigned long _rem = fd % __NFDBITS; - fdsetp->fds_bits[_tmp] |= (1UL<<_rem); -} - -#undef __FD_CLR -static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp) -{ - unsigned long _tmp = fd / __NFDBITS; - unsigned long _rem = fd % __NFDBITS; - fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem); -} - -#undef __FD_ISSET -static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p) -{ - unsigned long _tmp = fd / __NFDBITS; - unsigned long _rem = fd % __NFDBITS; - return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0; -} - -/* - * This will unroll the loop for the normal constant case (8 ints, - * for a 256-bit fd_set) - */ -#undef __FD_ZERO -static __inline__ void __FD_ZERO(__kernel_fd_set *p) -{ - unsigned int *tmp = (unsigned int *)p->fds_bits; - int i; - - if (__builtin_constant_p(__FDSET_LONGS)) { - switch (__FDSET_LONGS) { - case 8: - tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0; - tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0; - return; - } - } - i = __FDSET_LONGS; - while (i) { - i--; - *tmp = 0; - tmp++; - } -} - -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ -#endif /* __GNUC__ */ -#endif /* _PPC_POSIX_TYPES_H */ diff --git a/include/asm-ppc/ppc_asm.tmpl b/include/asm-ppc/ppc_asm.tmpl deleted file mode 100644 index 3e47e82aba..0000000000 --- a/include/asm-ppc/ppc_asm.tmpl +++ /dev/null @@ -1,322 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file contains all the macros and symbols which define - * a PowerPC assembly language environment. - */ -#ifndef __PPC_ASM_TMPL__ -#define __PPC_ASM_TMPL__ - -/*************************************************************************** - * - * These definitions simplify the ugly declarations necessary for GOT - * definitions. - * - * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es - * - * Uses r14 to access the GOT - */ - -#define START_GOT \ - .section ".got2","aw"; \ -.LCTOC1 = .+32768 - -#define END_GOT \ - .text - -#define GET_GOT \ - bl 1f ; \ - .text 2 ; \ -0: .long .LCTOC1-1f ; \ - .text ; \ -1: mflr r14 ; \ - lwz r0,0b-1b(r14) ; \ - add r14,r0,r14 ; - -#define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME - -#define GOT(NAME) .L_ ## NAME (r14) - - -/*************************************************************************** - * Register names - */ -#define r0 0 -#define r1 1 -#define r2 2 -#define r3 3 -#define r4 4 -#define r5 5 -#define r6 6 -#define r7 7 -#define r8 8 -#define r9 9 -#define r10 10 -#define r11 11 -#define r12 12 -#define r13 13 -#define r14 14 -#define r15 15 -#define r16 16 -#define r17 17 -#define r18 18 -#define r19 19 -#define r20 20 -#define r21 21 -#define r22 22 -#define r23 23 -#define r24 24 -#define r25 25 -#define r26 26 -#define r27 27 -#define r28 28 -#define r29 29 -#define r30 30 -#define r31 31 - - -#if defined(CONFIG_8xx) || defined(CONFIG_MPC824X) - -/* Some special registers */ - -#define ICR 148 /* Interrupt Cause Register (37-44) */ -#define DER 149 -#define COUNTA 150 /* Breakpoint Counter (37-44) */ -#define COUNTB 151 /* Breakpoint Counter (37-44) */ -#define LCTRL1 156 /* Load/Store Support (37-40) */ -#define LCTRL2 157 /* Load/Store Support (37-41) */ -#define ICTRL 158 - -#endif /* CONFIG_8xx, CONFIG_MPC824X */ - - -#if defined(CONFIG_5xx) -/* Some special purpose registers */ -#define DER 149 /* Debug Enable Register */ -#define COUNTA 150 /* Breakpoint Counter */ -#define COUNTB 151 /* Breakpoint Counter */ -#define LCTRL1 156 /* Load/Store Support */ -#define LCTRL2 157 /* Load/Store Support */ -#define ICTRL 158 /* I-Bus Support Control Register */ -#define EID 81 -#endif /* CONFIG_5xx */ - -#if defined(CONFIG_8xx) - -/* Registers in the processor's internal memory map that we use. -*/ -#define SYPCR 0x00000004 -#define BR0 0x00000100 -#define OR0 0x00000104 -#define BR1 0x00000108 -#define OR1 0x0000010c -#define BR2 0x00000110 -#define OR2 0x00000114 -#define BR3 0x00000118 -#define OR3 0x0000011c -#define BR4 0x00000120 -#define OR4 0x00000124 - -#define MAR 0x00000164 -#define MCR 0x00000168 -#define MAMR 0x00000170 -#define MBMR 0x00000174 -#define MSTAT 0x00000178 -#define MPTPR 0x0000017a -#define MDR 0x0000017c - -#define TBSCR 0x00000200 -#define TBREFF0 0x00000204 - -#define PLPRCR 0x00000284 - -#elif defined(CONFIG_8260) - -#define HID2 1011 - -#define HID0_IFEM (1<<7) - -#define HID0_ICE_BITPOS 16 -#define HID0_DCE_BITPOS 17 - -#define IM_REGBASE 0x10000 -#define IM_SYPCR (IM_REGBASE+0x0004) -#define IM_SWSR (IM_REGBASE+0x000e) -#define IM_BR0 (IM_REGBASE+0x0100) -#define IM_OR0 (IM_REGBASE+0x0104) -#define IM_BR1 (IM_REGBASE+0x0108) -#define IM_OR1 (IM_REGBASE+0x010c) -#define IM_BR2 (IM_REGBASE+0x0110) -#define IM_OR2 (IM_REGBASE+0x0114) -#define IM_MPTPR (IM_REGBASE+0x0184) -#define IM_PSDMR (IM_REGBASE+0x0190) -#define IM_PSRT (IM_REGBASE+0x019c) -#define IM_IMMR (IM_REGBASE+0x01a8) -#define IM_SCCR (IM_REGBASE+0x0c80) - -#elif defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8220) - -#define HID0_ICE_BITPOS 16 -#define HID0_DCE_BITPOS 17 - -#endif - -#define curptr r2 - -#define SYNC \ - sync; \ - isync - -/* - * Macros for storing registers into and loading registers from - * exception frames. - */ -#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) -#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) -#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) -#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) -#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) -#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) -#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) -#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) -#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) -#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) - -/* - * GCC sometimes accesses words at negative offsets from the stack - * pointer, although the SysV ABI says it shouldn't. To cope with - * this, we leave this much untouched space on the stack on exception - * entry. - */ -#define STACK_UNDERHEAD 64 - -/* - * Exception entry code. This code runs with address translation - * turned off, i.e. using physical addresses. - * We assume sprg3 has the physical address of the current - * task's thread_struct. - */ -#define EXCEPTION_PROLOG \ - mtspr SPRG0,r20; \ - mtspr SPRG1,r21; \ - mfcr r20; \ - subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\ - stw r20,_CCR(r21); /* save registers */ \ - stw r22,GPR22(r21); \ - stw r23,GPR23(r21); \ - mfspr r20,SPRG0; \ - stw r20,GPR20(r21); \ - mfspr r22,SPRG1; \ - stw r22,GPR21(r21); \ - mflr r20; \ - stw r20,_LINK(r21); \ - mfctr r22; \ - stw r22,_CTR(r21); \ - mfspr r20,XER; \ - stw r20,_XER(r21); \ - mfspr r22,SRR0; \ - mfspr r23,SRR1; \ - stw r0,GPR0(r21); \ - stw r1,GPR1(r21); \ - stw r2,GPR2(r21); \ - stw r1,0(r21); \ - mr r1,r21; /* set new kernel sp */ \ - SAVE_4GPRS(3, r21); -/* - * Note: code which follows this uses cr0.eq (set if from kernel), - * r21, r22 (SRR0), and r23 (SRR1). - */ - -/* - * Critical exception entry code. This is just like the other exception - * code except that it uses SRR2 and SRR3 instead of SRR0 and SRR1. - */ -#define CRITICAL_EXCEPTION_PROLOG \ - mtspr SPRG0,r20; \ - mtspr SPRG1,r21; \ - mfcr r20; \ - subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\ - stw r20,_CCR(r21); /* save registers */ \ - stw r22,GPR22(r21); \ - stw r23,GPR23(r21); \ - mfspr r20,SPRG0; \ - stw r20,GPR20(r21); \ - mfspr r22,SPRG1; \ - stw r22,GPR21(r21); \ - mflr r20; \ - stw r20,_LINK(r21); \ - mfctr r22; \ - stw r22,_CTR(r21); \ - mfspr r20,XER; \ - stw r20,_XER(r21); \ - mfspr r22,990; /* SRR2 */ \ - mfspr r23,991; /* SRR3 */ \ - stw r0,GPR0(r21); \ - stw r1,GPR1(r21); \ - stw r2,GPR2(r21); \ - stw r1,0(r21); \ - mr r1,r21; /* set new kernel sp */ \ - SAVE_4GPRS(3, r21); -/* - * Note: code which follows this uses cr0.eq (set if from kernel), - * r21, r22 (SRR2), and r23 (SRR3). - */ - -/* - * Exception vectors. - * - * The data words for `hdlr' and `int_return' are initialized with - * OFFSET values only; they must be relocated first before they can - * be used! - */ -#define STD_EXCEPTION(n, label, hdlr) \ - . = n; \ -label: \ - EXCEPTION_PROLOG; \ - lwz r3,GOT(transfer_to_handler); \ - mtlr r3; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - li r20,MSR_KERNEL; \ - rlwimi r20,r23,0,25,25; \ - blrl ; \ -.L_ ## label : \ - .long hdlr - _start + EXC_OFF_SYS_RESET; \ - .long int_return - _start + EXC_OFF_SYS_RESET - - -#define CRIT_EXCEPTION(n, label, hdlr) \ - . = n; \ -label: \ - CRITICAL_EXCEPTION_PROLOG; \ - lwz r3,GOT(transfer_to_handler); \ - mtlr r3; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \ - rlwimi r20,r23,0,25,25; \ - blrl ; \ -.L_ ## label : \ - .long hdlr - _start + EXC_OFF_SYS_RESET; \ - .long crit_return - _start + EXC_OFF_SYS_RESET - -#endif /* __PPC_ASM_TMPL__ */ diff --git a/include/asm-ppc/ppc_defs.h b/include/asm-ppc/ppc_defs.h deleted file mode 100644 index 8b2b3b5fd7..0000000000 --- a/include/asm-ppc/ppc_defs.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * WARNING! This file is automatically generated - DO NOT EDIT! - */ -#define KERNELBASE -1073741824 -#define STATE 0 -#define NEXT_TASK 64 -#define COUNTER 52 -#define PROCESSOR 916 -#define SIGPENDING 8 -#define TSS 576 -#define MM 880 -#define TASK_STRUCT_SIZE 928 -#define KSP 0 -#define PG_TABLES 4 -#define PGD 8 -#define LAST_SYSCALL 20 -#define PT_REGS 12 -#define PF_TRACESYS 32 -#define TASK_FLAGS 4 -#define TSS_FPR0 24 -#define TSS_FPSCR 284 -#define TSS_SMP_FORK_RET 288 -#define TASK_UNION_SIZE 8192 -#define STACK_FRAME_OVERHEAD 16 -#define INT_FRAME_SIZE 192 -#define GPR0 16 -#define GPR1 20 -#define GPR2 24 -#define GPR3 28 -#define GPR4 32 -#define GPR5 36 -#define GPR6 40 -#define GPR7 44 -#define GPR8 48 -#define GPR9 52 -#define GPR10 56 -#define GPR11 60 -#define GPR12 64 -#define GPR13 68 -#define GPR14 72 -#define GPR15 76 -#define GPR16 80 -#define GPR17 84 -#define GPR18 88 -#define GPR19 92 -#define GPR20 96 -#define GPR21 100 -#define GPR22 104 -#define GPR23 108 -#define GPR24 112 -#define GPR25 116 -#define GPR26 120 -#define GPR27 124 -#define GPR28 128 -#define GPR29 132 -#define GPR30 136 -#define GPR31 140 -#define _NIP 144 -#define _MSR 148 -#define _CTR 156 -#define _LINK 160 -#define _CCR 168 -#define _XER 164 -#define _DAR 180 -#define _DSISR 184 -#define ORIG_GPR3 152 -#define RESULT 188 -#define TRAP 176 diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h deleted file mode 100644 index b336f48b78..0000000000 --- a/include/asm-ppc/processor.h +++ /dev/null @@ -1,1086 +0,0 @@ -#ifndef __ASM_PPC_PROCESSOR_H -#define __ASM_PPC_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -#include <asm/ptrace.h> -#include <asm/types.h> - -/* Machine State Register (MSR) Fields */ - -#ifdef CONFIG_PPC64BRIDGE -#define MSR_SF (1<<63) -#define MSR_ISF (1<<61) -#endif /* CONFIG_PPC64BRIDGE */ -#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ -#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ -#define MSR_SPE (1<<25) /* Enable SPE(e500) */ -#define MSR_POW (1<<18) /* Enable Power Management */ -#define MSR_WE (1<<18) /* Wait State Enable */ -#define MSR_TGPR (1<<17) /* TLB Update registers in use */ -#define MSR_CE (1<<17) /* Critical Interrupt Enable */ -#define MSR_ILE (1<<16) /* Interrupt Little Endian */ -#define MSR_EE (1<<15) /* External Interrupt Enable */ -#define MSR_PR (1<<14) /* Problem State / Privilege Level */ -#define MSR_FP (1<<13) /* Floating Point enable */ -#define MSR_ME (1<<12) /* Machine Check Enable */ -#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ -#define MSR_SE (1<<10) /* Single Step */ -#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ -#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ -#define MSR_BE (1<<9) /* Branch Trace */ -#define MSR_DE (1<<9) /* Debug Exception Enable */ -#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ -#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ -#define MSR_IR (1<<5) /* Instruction Relocate */ -#define MSR_IS (1<<5) /* Book E Instruction space */ -#define MSR_DR (1<<4) /* Data Relocate */ -#define MSR_DS (1<<4) /* Book E Data space */ -#define MSR_PE (1<<3) /* Protection Enable */ -#define MSR_PX (1<<2) /* Protection Exclusive Mode */ -#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ -#define MSR_RI (1<<1) /* Recoverable Exception */ -#define MSR_LE (1<<0) /* Little Endian */ - -#ifdef CONFIG_APUS_FAST_EXCEPT -#define MSR_ MSR_ME|MSR_IP|MSR_RI -#else -#define MSR_ MSR_ME|MSR_RI -#endif -#ifndef CONFIG_E500 -#define MSR_KERNEL MSR_|MSR_IR|MSR_DR -#else -#define MSR_KERNEL MSR_ME -#endif -#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE - -/* Floating Point Status and Control Register (FPSCR) Fields */ - -#define FPSCR_FX 0x80000000 /* FPU exception summary */ -#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ -#define FPSCR_VX 0x20000000 /* Invalid operation summary */ -#define FPSCR_OX 0x10000000 /* Overflow exception summary */ -#define FPSCR_UX 0x08000000 /* Underflow exception summary */ -#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ -#define FPSCR_XX 0x02000000 /* Inexact exception summary */ -#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ -#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ -#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ -#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ -#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ -#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ -#define FPSCR_FR 0x00040000 /* Fraction rounded */ -#define FPSCR_FI 0x00020000 /* Fraction inexact */ -#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ -#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ -#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ -#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ -#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ -#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ -#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ -#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ -#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ -#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ -#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ -#define FPSCR_RN 0x00000003 /* FPU rounding control */ - -/* Special Purpose Registers (SPRNs)*/ - -#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ -#define SPRN_CTR 0x009 /* Count Register */ -#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ -#ifndef CONFIG_BOOKE -#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ -#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ -#else -#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ -#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ -#endif /* CONFIG_BOOKE */ -#define SPRN_DAR 0x013 /* Data Address Register */ -#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ -#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ -#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ -#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ -#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ -#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ -#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ -#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ -#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ -#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ -#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ -#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ -#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ -#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ -#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ -#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ -#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ -#define DBCR_EDM 0x80000000 -#define DBCR_IDM 0x40000000 -#define DBCR_RST(x) (((x) & 0x3) << 28) -#define DBCR_RST_NONE 0 -#define DBCR_RST_CORE 1 -#define DBCR_RST_CHIP 2 -#define DBCR_RST_SYSTEM 3 -#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ -#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ -#define DBCR_EDE 0x02000000 /* Exception Debug Event */ -#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ -#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ -#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ -#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ -#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ -#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ -#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ -#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ -#define DAC_BYTE 0 -#define DAC_HALF 1 -#define DAC_WORD 2 -#define DAC_QUAD 3 -#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ -#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ -#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ -#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ -#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ -#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ -#define DBCR_SIA 0x00000008 /* Second IAC Enable */ -#define DBCR_SDA 0x00000004 /* Second DAC Enable */ -#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ -#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ -#ifndef CONFIG_BOOKE -#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ -#else -#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ -#endif /* CONFIG_BOOKE */ -#ifndef CONFIG_BOOKE -#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ -#define SPRN_DBSR 0x3F0 /* Debug Status Register */ -#else -#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ -#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ -#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ -#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ -#endif /* CONFIG_BOOKE */ -#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ -#define DCCR_NOCACHE 0 /* Noncacheable */ -#define DCCR_CACHE 1 /* Cacheable */ -#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ -#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ -#define DCWR_COPY 0 /* Copy-back */ -#define DCWR_WRITE 1 /* Write-through */ -#ifndef CONFIG_BOOKE -#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ -#else -#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ -#endif /* CONFIG_BOOKE */ -#define SPRN_DEC 0x016 /* Decrement Register */ -#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ -#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ -#define SPRN_EAR 0x11A /* External Address Register */ -#ifndef CONFIG_BOOKE -#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ -#else -#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ -#endif /* CONFIG_BOOKE */ -#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ -#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ -#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ -#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ -#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ -#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ -#define ESR_PTR 0x02000000 /* Program Exception - Trap */ -#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ -#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ -#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ -#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ -#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ -#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ - -#define HID0_ICE_SHIFT 15 -#define HID0_DCE_SHIFT 14 -#define HID0_DLOCK_SHIFT 12 - -#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ -#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ -#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ -#define HID0_SBCLK (1<<27) -#define HID0_EICE (1<<26) -#define HID0_ECLK (1<<25) -#define HID0_PAR (1<<24) -#define HID0_DOZE (1<<23) -#define HID0_NAP (1<<22) -#define HID0_SLEEP (1<<21) -#define HID0_DPM (1<<20) -#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */ -#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */ -#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ -#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */ -#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ -#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ -#define HID0_DCI HID0_DCFI -#define HID0_SPD (1<<9) /* Speculative disable */ -#define HID0_SGE (1<<7) /* Store Gathering Enable */ -#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ -#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ -#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ -#define HID0_ABE (1<<3) /* Address Broadcast Enable */ -#define HID0_BHTE (1<<2) /* Branch History Table Enable */ -#define HID0_BTCD (1<<1) /* Branch target cache disable */ -#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ -#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ -#ifndef CONFIG_BOOKE -#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ -#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ -#else -#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */ -#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */ -#endif /* CONFIG_BOOKE */ -#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ -#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ -#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ -#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ -#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ -#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ -#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ -#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ -#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ -#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ -#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ -#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ -#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ -#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ -#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ -#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ -#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ -#define ICCR_NOCACHE 0 /* Noncacheable */ -#define ICCR_CACHE 1 /* Cacheable */ -#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ -#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ -#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ -#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ -#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ -#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ -#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ -#define SPRN_LR 0x008 /* Link Register */ -#define SPRN_MBAR 0x137 /* System memory base address */ -#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ -#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ -#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ -#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ -#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ -#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ -#ifndef CONFIG_BOOKE -#define SPRN_PID 0x3B1 /* Process ID */ -#define SPRN_PIR 0x3FF /* Processor Identification Register */ -#else -#define SPRN_PID 0x030 /* Book E Process ID */ -#define SPRN_PIR 0x11E /* Book E Processor Identification Register */ -#endif /* CONFIG_BOOKE */ -#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ -#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ -#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ -#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ -#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ -#define SPRN_PVR 0x11F /* Processor Version Register */ -#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ -#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ -#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ -#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ -#define SGR_NORMAL 0 -#define SGR_GUARDED 1 -#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ -#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ -#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ -#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ -#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ -#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ -#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ -#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ -#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ -#ifdef CONFIG_BOOKE -#define SPRN_SVR 0x3FF /* System Version Register */ -#else -#define SPRN_SVR 0x11E /* System Version Register */ -#endif -#define SPRN_TBHI 0x3DC /* Time Base High */ -#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ -#define SPRN_TBLO 0x3DD /* Time Base Low */ -#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ -#define SPRN_TBRL 0x10C /* Time Base Read Lower Register */ -#define SPRN_TBRU 0x10D /* Time Base Read Upper Register */ -#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */ -#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */ -#ifndef CONFIG_BOOKE -#define SPRN_TCR 0x3DA /* Timer Control Register */ -#else -#define SPRN_TCR 0x154 /* Book E Timer Control Register */ -#endif /* CONFIG_BOOKE */ -#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ -#define WP_2_17 0 /* 2^17 clocks */ -#define WP_2_21 1 /* 2^21 clocks */ -#define WP_2_25 2 /* 2^25 clocks */ -#define WP_2_29 3 /* 2^29 clocks */ -#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ -#define WRC_NONE 0 /* No reset will occur */ -#define WRC_CORE 1 /* Core reset will occur */ -#define WRC_CHIP 2 /* Chip reset will occur */ -#define WRC_SYSTEM 3 /* System reset will occur */ -#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ -#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ -#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ -#define FP_2_9 0 /* 2^9 clocks */ -#define FP_2_13 1 /* 2^13 clocks */ -#define FP_2_17 2 /* 2^17 clocks */ -#define FP_2_21 3 /* 2^21 clocks */ -#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ -#define TCR_ARE 0x00400000 /* Auto Reload Enable */ -#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ -#define THRM1_TIN (1<<0) -#define THRM1_TIV (1<<1) -#define THRM1_THRES (0x7f<<2) -#define THRM1_TID (1<<29) -#define THRM1_TIE (1<<30) -#define THRM1_V (1<<31) -#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ -#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ -#define THRM3_E (1<<31) -#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ -#ifndef CONFIG_BOOKE -#define SPRN_TSR 0x3D8 /* Timer Status Register */ -#else -#define SPRN_TSR 0x150 /* Book E Timer Status Register */ -#endif /* CONFIG_BOOKE */ -#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ -#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ -#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ -#define WRS_NONE 0 /* No WDT reset occurred */ -#define WRS_CORE 1 /* WDT forced core reset */ -#define WRS_CHIP 2 /* WDT forced chip reset */ -#define WRS_SYSTEM 3 /* WDT forced system reset */ -#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ -#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ -#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ -#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ -#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ -#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ -#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ -#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ -#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ -#define SPRN_XER 0x001 /* Fixed Point Exception Register */ -#define SPRN_ZPR 0x3B0 /* Zone Protection Register */ - -/* Book E definitions */ -#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ -#define SPRN_CSRR0 0x03A /* Critical SRR0 */ -#define SPRN_CSRR1 0x03B /* Critical SRR0 */ -#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ -#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ -#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ -#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ -#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ -#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ -#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ -#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ -#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ -#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ -#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ -#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ -#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ -#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ -#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ -#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ -#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ -#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ -#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ -#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ -#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ -#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ -#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ -#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ -#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ -#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */ -#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */ -#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */ -#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */ -#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */ -#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ - -/* e500 definitions */ -#define SPRN_L1CSR0 0x3f2 /* L1 Cache Control and Status Register 0 */ -#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ -#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ -#define SPRN_L1CSR1 0x3f3 /* L1 Cache Control and Status Register 1 */ -#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ -#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ - -#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ -#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ -#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ -#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ -#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ -#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ -#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ -#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ -#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ - -#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ -#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ -#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ -#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ -#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ - -#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ -#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ -#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ -#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ -#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ -#define SPRN_PID1 0x279 /* Process ID Register 1 */ -#define SPRN_PID2 0x27a /* Process ID Register 2 */ -#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ -#define ESR_ST 0x00800000 /* Store Operation */ - -#if defined(CONFIG_MPC86xx) -#define SPRN_MSSCRO 0x3f6 -#endif - - -/* Short-hand versions for a number of the above SPRNs */ - -#define CTR SPRN_CTR /* Counter Register */ -#define DAR SPRN_DAR /* Data Address Register */ -#define DABR SPRN_DABR /* Data Address Breakpoint Register */ -#define DAC1 SPRN_DAC1 /* Data Address Register 1 */ -#define DAC2 SPRN_DAC2 /* Data Address Register 2 */ -#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */ -#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */ -#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */ -#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */ -#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */ -#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ -#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ -#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ -#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */ -#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */ -#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */ -#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */ -#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */ -#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */ -#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */ -#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ -#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ -#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ -#define DBSR SPRN_DBSR /* Debug Status Register */ -#define DCMP SPRN_DCMP /* Data TLB Compare Register */ -#define DEC SPRN_DEC /* Decrement Register */ -#define DMISS SPRN_DMISS /* Data TLB Miss Register */ -#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ -#define EAR SPRN_EAR /* External Address Register */ -#define ESR SPRN_ESR /* Exception Syndrome Register */ -#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ -#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ -#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ -#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ -#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ -#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ -#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ -#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ -#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */ -#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */ -#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */ -#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */ -#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */ -#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */ -#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */ -#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */ -#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */ -#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */ -#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ -#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ -#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ -#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ -#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ -#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ -#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ -#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ -#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ -#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ -#define LR SPRN_LR -#define MBAR SPRN_MBAR /* System memory base address */ -#if defined(CONFIG_MPC86xx) -#define MSSCR0 SPRN_MSSCRO -#endif -#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) -#define PIR SPRN_PIR -#endif -#define SVR SPRN_SVR /* System-On-Chip Version Register */ -#define PVR SPRN_PVR /* Processor Version */ -#define RPA SPRN_RPA /* Required Physical Address Register */ -#define SDR1 SPRN_SDR1 /* MMU hash base register */ -#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ -#define SPR1 SPRN_SPRG1 -#define SPR2 SPRN_SPRG2 -#define SPR3 SPRN_SPRG3 -#define SPRG0 SPRN_SPRG0 -#define SPRG1 SPRN_SPRG1 -#define SPRG2 SPRN_SPRG2 -#define SPRG3 SPRN_SPRG3 -#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ -#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ -#define SVR SPRN_SVR /* System Version Register */ -#define TBRL SPRN_TBRL /* Time Base Read Lower Register */ -#define TBRU SPRN_TBRU /* Time Base Read Upper Register */ -#define TBWL SPRN_TBWL /* Time Base Write Lower Register */ -#define TBWU SPRN_TBWU /* Time Base Write Upper Register */ -#define TCR SPRN_TCR /* Timer Control Register */ -#define TSR SPRN_TSR /* Timer Status Register */ -#define ICTC 1019 -#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */ -#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */ -#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */ -#define XER SPRN_XER - -#define DECAR SPRN_DECAR -#define CSRR0 SPRN_CSRR0 -#define CSRR1 SPRN_CSRR1 -#define IVPR SPRN_IVPR -#define USPRG0 SPRN_USPRG -#define SPRG4R SPRN_SPRG4R -#define SPRG5R SPRN_SPRG5R -#define SPRG6R SPRN_SPRG6R -#define SPRG7R SPRN_SPRG7R -#define SPRG4W SPRN_SPRG4W -#define SPRG5W SPRN_SPRG5W -#define SPRG6W SPRN_SPRG6W -#define SPRG7W SPRN_SPRG7W -#define DEAR SPRN_DEAR -#define DBCR2 SPRN_DBCR2 -#define IAC3 SPRN_IAC3 -#define IAC4 SPRN_IAC4 -#define DVC1 SPRN_DVC1 -#define DVC2 SPRN_DVC2 -#define IVOR0 SPRN_IVOR0 -#define IVOR1 SPRN_IVOR1 -#define IVOR2 SPRN_IVOR2 -#define IVOR3 SPRN_IVOR3 -#define IVOR4 SPRN_IVOR4 -#define IVOR5 SPRN_IVOR5 -#define IVOR6 SPRN_IVOR6 -#define IVOR7 SPRN_IVOR7 -#define IVOR8 SPRN_IVOR8 -#define IVOR9 SPRN_IVOR9 -#define IVOR10 SPRN_IVOR10 -#define IVOR11 SPRN_IVOR11 -#define IVOR12 SPRN_IVOR12 -#define IVOR13 SPRN_IVOR13 -#define IVOR14 SPRN_IVOR14 -#define IVOR15 SPRN_IVOR15 -#define IVOR32 SPRN_IVOR32 -#define IVOR33 SPRN_IVOR33 -#define IVOR34 SPRN_IVOR34 -#define IVOR35 SPRN_IVOR35 -#define MCSRR0 SPRN_MCSRR0 -#define MCSRR1 SPRN_MCSRR1 -#define L1CSR0 SPRN_L1CSR0 -#define L1CSR1 SPRN_L1CSR1 -#define MCSR SPRN_MCSR -#define MMUCSR0 SPRN_MMUCSR0 -#define BUCSR SPRN_BUCSR -#define PID0 SPRN_PID -#define PID1 SPRN_PID1 -#define PID2 SPRN_PID2 -#define MAS0 SPRN_MAS0 -#define MAS1 SPRN_MAS1 -#define MAS2 SPRN_MAS2 -#define MAS3 SPRN_MAS3 -#define MAS4 SPRN_MAS4 -#define MAS5 SPRN_MAS5 -#define MAS6 SPRN_MAS6 -#define MAS7 SPRN_MAS7 - -/* Device Control Registers */ - -#define DCRN_BEAR 0x090 /* Bus Error Address Register */ -#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ -#define BESR_DMES 0x40000000 /* DMA Error Status */ -#define BESR_RWS 0x20000000 /* Read/Write Status */ -#define BESR_ETMASK 0x1C000000 /* Error Type */ -#define ET_PROT 0 -#define ET_PARITY 1 -#define ET_NCFG 2 -#define ET_BUSERR 4 -#define ET_BUSTO 6 -#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ -#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ -#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ -#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ -#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ -#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ -#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ -#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ -#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ -#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ -#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ -#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ -#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ -#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ -#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ -#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ -#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ -#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ -#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ -#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ -#define DCRN_DMASR 0x0E0 /* DMA Status Register */ -#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ -#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ -#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ -#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ -#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ -#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ -#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ -#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ -#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ -#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ -#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ -#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ -#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ -#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ -#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ -#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ -#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ -#define IOCR_E0TE 0x80000000 -#define IOCR_E0LP 0x40000000 -#define IOCR_E1TE 0x20000000 -#define IOCR_E1LP 0x10000000 -#define IOCR_E2TE 0x08000000 -#define IOCR_E2LP 0x04000000 -#define IOCR_E3TE 0x02000000 -#define IOCR_E3LP 0x01000000 -#define IOCR_E4TE 0x00800000 -#define IOCR_E4LP 0x00400000 -#define IOCR_EDT 0x00080000 -#define IOCR_SOR 0x00040000 -#define IOCR_EDO 0x00008000 -#define IOCR_2XC 0x00004000 -#define IOCR_ATC 0x00002000 -#define IOCR_SPD 0x00001000 -#define IOCR_BEM 0x00000800 -#define IOCR_PTD 0x00000400 -#define IOCR_ARE 0x00000080 -#define IOCR_DRC 0x00000020 -#define IOCR_RDM(x) (((x) & 0x3) << 3) -#define IOCR_TCS 0x00000004 -#define IOCR_SCS 0x00000002 -#define IOCR_SPC 0x00000001 - -/* System-On-Chip Version Register */ - -/* System-On-Chip Version Register (SVR) field extraction */ - -#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ -#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ - -#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ -#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ -#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ -#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ -#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ -#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ -#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ - -/* System-On-Chip Version Numbers (version field only) */ -#define SVR_MPC5200 0x8011 - -/* Processor Version Register */ - -/* Processor Version Register (PVR) field extraction */ - -#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ -#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ - -/* - * AMCC has further subdivided the standard PowerPC 16-bit version and - * revision subfields of the PVR for the PowerPC 403s into the following: - */ - -#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ -#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ -#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ -#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ -#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ -#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ - -/* Processor Version Numbers */ - -#define PVR_403GA 0x00200000 -#define PVR_403GB 0x00200100 -#define PVR_403GC 0x00200200 -#define PVR_403GCX 0x00201400 -#define PVR_405GP 0x40110000 -#define PVR_405GP_RB 0x40110040 -#define PVR_405GP_RC 0x40110082 -#define PVR_405GP_RD 0x401100C4 -#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ -#define PVR_405CR_RA 0x40110041 -#define PVR_405CR_RB 0x401100C5 -#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ -#define PVR_405EP_RA 0x51210950 -#define PVR_405GPR_RB 0x50910951 -#define PVR_440GP_RB 0x40120440 -#define PVR_440GP_RC 0x40120481 -#define PVR_440EP_RA 0x42221850 -#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ -#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ -#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ -#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ -#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ -#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ -#define PVR_440GRX1_RA 0x216218D8 /* 440GRX rev A with Security / Kasumi */ -#define PVR_440GRX2_RA 0x216218DC /* 440GRX rev A without Security / Kasumi */ -#define PVR_440GX_RA 0x51B21850 -#define PVR_440GX_RB 0x51B21851 -#define PVR_440GX_RC 0x51B21892 -#define PVR_440GX_RF 0x51B21894 -#define PVR_405EP_RB 0x51210950 -#define PVR_440SP_RA 0x53221850 -#define PVR_440SP_RB 0x53221891 -#define PVR_440SP_RC 0x53221892 -#define PVR_440SPe_RA 0x53421890 -#define PVR_440SPe_RB 0x53421891 -#define PVR_601 0x00010000 -#define PVR_602 0x00050000 -#define PVR_603 0x00030000 -#define PVR_603e 0x00060000 -#define PVR_603ev 0x00070000 -#define PVR_603r 0x00071000 -#define PVR_604 0x00040000 -#define PVR_604e 0x00090000 -#define PVR_604r 0x000A0000 -#define PVR_620 0x00140000 -#define PVR_740 0x00080000 -#define PVR_750 PVR_740 -#define PVR_740P 0x10080000 -#define PVR_750P PVR_740P -#define PVR_7400 0x000C0000 -#define PVR_7410 0x800C0000 -#define PVR_7450 0x80000000 - -#define PVR_85xx 0x80200000 -#define PVR_85xx_REV1 (PVR_85xx | 0x0010) -#define PVR_85xx_REV2 (PVR_85xx | 0x0020) - -#define PVR_86xx 0x80040000 -#define PVR_86xx_REV1 (PVR_86xx | 0x0010) - -/* - * For the 8xx processors, all of them report the same PVR family for - * the PowerPC core. The various versions of these processors must be - * differentiated by the version number in the Communication Processor - * Module (CPM). - */ -#define PVR_821 0x00500000 -#define PVR_823 PVR_821 -#define PVR_850 PVR_821 -#define PVR_860 PVR_821 -#define PVR_7400 0x000C0000 -#define PVR_8240 0x00810100 - -/* - * PowerQUICC II family processors report different PVR values depending - * on silicon process (HiP3, HiP4, HiP7, etc.) - */ -#define PVR_8260 PVR_8240 -#define PVR_8260_HIP3 0x00810101 -#define PVR_8260_HIP4 0x80811014 -#define PVR_8260_HIP7 0x80822011 -#define PVR_8260_HIP7R1 0x80822013 -#define PVR_8260_HIP7RA 0x80822014 - - -/* - * System Version Register - */ - -/* System Version Register (SVR) field extraction */ - -#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ -#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ - -#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ - -#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ -#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ - -#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ -#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ - - -/* - * SVR_VER() Version Values - */ - -#define SVR_8540 0x8030 -#define SVR_8560 0x8070 -#define SVR_8555 0x8079 -#define SVR_8541 0x807A -#define SVR_8548 0x8031 -#define SVR_8548_E 0x8039 -#define SVR_8641 0x8090 - - -/* I am just adding a single entry for 8260 boards. I think we may be - * able to combine mbx, fads, rpxlite, bseip, and classic into a single - * generic 8xx as well. The boards containing these processors are either - * identical at the processor level (due to the high integration) or so - * wildly different that testing _machine at run time is best replaced by - * conditional compilation by board type (found in their respective .h file). - * -- Dan - */ -#define _MACH_prep 0x00000001 -#define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */ -#define _MACH_chrp 0x00000004 /* chrp machine */ -#define _MACH_mbx 0x00000008 /* Motorola MBX board */ -#define _MACH_apus 0x00000010 /* amiga with phase5 powerup */ -#define _MACH_fads 0x00000020 /* Motorola FADS board */ -#define _MACH_rpxlite 0x00000040 /* RPCG RPX-Lite 8xx board */ -#define _MACH_bseip 0x00000080 /* Bright Star Engineering ip-Engine */ -#define _MACH_yk 0x00000100 /* Motorola Yellowknife */ -#define _MACH_gemini 0x00000200 /* Synergy Microsystems gemini board */ -#define _MACH_classic 0x00000400 /* RPCG RPX-Classic 8xx board */ -#define _MACH_oak 0x00000800 /* IBM "Oak" 403 eval. board */ -#define _MACH_walnut 0x00001000 /* AMCC "Walnut" 405GP eval. board */ -#define _MACH_8260 0x00002000 /* Generic 8260 */ -#define _MACH_sandpoint 0x00004000 /* Motorola SPS Processor eval board */ -#define _MACH_tqm860 0x00008000 /* TQM860/L */ -#define _MACH_tqm8xxL 0x00010000 /* TQM8xxL */ -#define _MACH_hidden_dragon 0x00020000 /* Motorola Hidden Dragon eval board */ - - -/* see residual.h for these */ -#define _PREP_Motorola 0x01 /* motorola prep */ -#define _PREP_Firm 0x02 /* firmworks prep */ -#define _PREP_IBM 0x00 /* ibm prep */ -#define _PREP_Bull 0x03 /* bull prep */ -#define _PREP_Radstone 0x04 /* Radstone Technology PLC prep */ - -/* - * Radstone board types - */ -#define RS_SYS_TYPE_PPC1 0 -#define RS_SYS_TYPE_PPC2 1 -#define RS_SYS_TYPE_PPC1a 2 -#define RS_SYS_TYPE_PPC2a 3 -#define RS_SYS_TYPE_PPC4 4 -#define RS_SYS_TYPE_PPC4a 5 -#define RS_SYS_TYPE_PPC2ep 6 - -/* these are arbitrary */ -#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ -#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ - -#define _GLOBAL(n)\ - .globl n;\ -n: - -/* Macros for setting and retrieving special purpose registers */ - -#define stringify(s) tostring(s) -#define tostring(s) #s - -#define mfdcr(rn) ({unsigned int rval; \ - asm volatile("mfdcr %0," stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) - -#define mfmsr() ({unsigned int rval; \ - asm volatile("mfmsr %0" : "=r" (rval)); rval;}) -#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) - -#define mfspr(rn) ({unsigned int rval; \ - asm volatile("mfspr %0," stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) - -#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) - -/* Segment Registers */ - -#define SR0 0 -#define SR1 1 -#define SR2 2 -#define SR3 3 -#define SR4 4 -#define SR5 5 -#define SR6 6 -#define SR7 7 -#define SR8 8 -#define SR9 9 -#define SR10 10 -#define SR11 11 -#define SR12 12 -#define SR13 13 -#define SR14 14 -#define SR15 15 - -#ifndef __ASSEMBLY__ -#ifndef CONFIG_MACH_SPECIFIC -extern int _machine; -extern int have_of; -#endif /* CONFIG_MACH_SPECIFIC */ - -/* what kind of prep workstation we are */ -extern int _prep_type; -/* - * This is used to identify the board type from a given PReP board - * vendor. Board revision is also made available. - */ -extern unsigned char ucSystemType; -extern unsigned char ucBoardRev; -extern unsigned char ucBoardRevMaj, ucBoardRevMin; - -struct task_struct; -void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp); -void release_thread(struct task_struct *); - -/* - * Create a new kernel thread. - */ -extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); - -/* - * Bus types - */ -#define EISA_bus 0 -#define EISA_bus__is_a_macro /* for versions in ksyms.c */ -#define MCA_bus 0 -#define MCA_bus__is_a_macro /* for versions in ksyms.c */ - -/* Lazy FPU handling on uni-processor */ -extern struct task_struct *last_task_used_math; -extern struct task_struct *last_task_used_altivec; - -/* - * this is the minimum allowable io space due to the location - * of the io areas on prep (first one at 0x80000000) but - * as soon as I get around to remapping the io areas with the BATs - * to match the mac we can raise this. -- Cort - */ -#define TASK_SIZE (0x80000000UL) - -/* This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) - -typedef struct { - unsigned long seg; -} mm_segment_t; - -struct thread_struct { - unsigned long ksp; /* Kernel stack pointer */ - unsigned long wchan; /* Event task is sleeping on */ - struct pt_regs *regs; /* Pointer to saved register state */ - mm_segment_t fs; /* for get_fs() validation */ - void *pgdir; /* root of page-table tree */ - signed long last_syscall; - double fpr[32]; /* Complete floating point set */ - unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ - unsigned long fpscr; /* Floating point status */ -#ifdef CONFIG_ALTIVEC - vector128 vr[32]; /* Complete AltiVec set */ - vector128 vscr; /* AltiVec status */ - unsigned long vrsave; -#endif /* CONFIG_ALTIVEC */ -}; - -#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) - -#define INIT_THREAD { \ - INIT_SP, /* ksp */ \ - 0, /* wchan */ \ - (struct pt_regs *)INIT_SP - 1, /* regs */ \ - KERNEL_DS, /*fs*/ \ - swapper_pg_dir, /* pgdir */ \ - 0, /* last_syscall */ \ - {0}, 0, 0 \ -} - -/* - * Note: the vm_start and vm_end fields here should *not* - * be in kernel space. (Could vm_end == vm_start perhaps?) - */ -#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ - PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ - 1, NULL, NULL } - -/* - * Return saved PC of a blocked thread. For now, this is the "user" PC - */ -static inline unsigned long thread_saved_pc(struct thread_struct *t) -{ - return (t->regs) ? t->regs->nip : 0; -} - -#define copy_segments(tsk, mm) do { } while (0) -#define release_segments(mm) do { } while (0) -#define forget_segments() do { } while (0) - -unsigned long get_wchan(struct task_struct *p); - -#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip) -#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1]) - -/* - * NOTE! The task struct and the stack go together - */ -#define THREAD_SIZE (2*PAGE_SIZE) -#define alloc_task_struct() \ - ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) -#define free_task_struct(p) free_pages((unsigned long)(p),1) -#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) - -/* in process.c - for early bootup debug -- Cort */ -int ll_printk(const char *, ...); -void ll_puts(const char *); - -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) - -/* In misc.c */ -void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); - -#endif /* ndef ASSEMBLY*/ - -#ifdef CONFIG_MACH_SPECIFIC -#if defined(CONFIG_8xx) -#define _machine _MACH_8xx -#define have_of 0 -#elif defined(CONFIG_OAK) -#define _machine _MACH_oak -#define have_of 0 -#elif defined(CONFIG_WALNUT) -#define _machine _MACH_walnut -#define have_of 0 -#elif defined(CONFIG_APUS) -#define _machine _MACH_apus -#define have_of 0 -#elif defined(CONFIG_GEMINI) -#define _machine _MACH_gemini -#define have_of 0 -#elif defined(CONFIG_8260) -#define _machine _MACH_8260 -#define have_of 0 -#elif defined(CONFIG_SANDPOINT) -#define _machine _MACH_sandpoint -#elif defined(CONFIG_HIDDEN_DRAGON) -#define _machine _MACH_hidden_dragon -#define have_of 0 -#else -#error "Machine not defined correctly" -#endif -#endif /* CONFIG_MACH_SPECIFIC */ - -#endif /* __ASM_PPC_PROCESSOR_H */ diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h deleted file mode 100644 index b4d599f43b..0000000000 --- a/include/asm-ppc/ptrace.h +++ /dev/null @@ -1,106 +0,0 @@ -#ifndef _PPC_PTRACE_H -#define _PPC_PTRACE_H - -/* - * This struct defines the way the registers are stored on the - * kernel stack during a system call or other kernel entry. - * - * this should only contain volatile regs - * since we can keep non-volatile in the thread_struct - * should set this up when only volatiles are saved - * by intr code. - * - * Since this is going on the stack, *CARE MUST BE TAKEN* to insure - * that the overall structure is a multiple of 16 bytes in length. - * - * Note that the offsets of the fields in this struct correspond with - * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c. - */ - - -#ifndef __ASSEMBLY__ -#ifdef CONFIG_PPC64BRIDGE -#define PPC_REG unsigned long /*long*/ -#else -#define PPC_REG unsigned long -#endif -struct pt_regs { - PPC_REG gpr[32]; - PPC_REG nip; - PPC_REG msr; - PPC_REG orig_gpr3; /* Used for restarting system calls */ - PPC_REG ctr; - PPC_REG link; - PPC_REG xer; - PPC_REG ccr; - PPC_REG mq; /* 601 only (not used at present) */ - /* Used on APUS to hold IPL value. */ - PPC_REG trap; /* Reason for being here */ - PPC_REG dar; /* Fault registers */ - PPC_REG dsisr; - PPC_REG result; /* Result of a system call */ -}; -#endif - -#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ - -/* Size of stack frame allocated when calling signal handler. */ -#define __SIGNAL_FRAMESIZE 64 - -#define instruction_pointer(regs) ((regs)->nip) -#define user_mode(regs) (((regs)->msr & MSR_PR) != 0) - -/* - * Offsets used by 'ptrace' system call interface. - * These can't be changed without breaking binary compatibility - * with MkLinux, etc. - */ -#define PT_R0 0 -#define PT_R1 1 -#define PT_R2 2 -#define PT_R3 3 -#define PT_R4 4 -#define PT_R5 5 -#define PT_R6 6 -#define PT_R7 7 -#define PT_R8 8 -#define PT_R9 9 -#define PT_R10 10 -#define PT_R11 11 -#define PT_R12 12 -#define PT_R13 13 -#define PT_R14 14 -#define PT_R15 15 -#define PT_R16 16 -#define PT_R17 17 -#define PT_R18 18 -#define PT_R19 19 -#define PT_R20 20 -#define PT_R21 21 -#define PT_R22 22 -#define PT_R23 23 -#define PT_R24 24 -#define PT_R25 25 -#define PT_R26 26 -#define PT_R27 27 -#define PT_R28 28 -#define PT_R29 29 -#define PT_R30 30 -#define PT_R31 31 - -#define PT_NIP 32 -#define PT_MSR 33 -#ifdef __KERNEL__ -#define PT_ORIG_R3 34 -#endif -#define PT_CTR 35 -#define PT_LNK 36 -#define PT_XER 37 -#define PT_CCR 38 -#define PT_MQ 39 - -#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ -#define PT_FPR31 (PT_FPR0 + 2*31) -#define PT_FPSCR (PT_FPR0 + 2*32 + 1) - -#endif diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h deleted file mode 100644 index 4bd66a707d..0000000000 --- a/include/asm-ppc/sigcontext.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _ASM_PPC_SIGCONTEXT_H -#define _ASM_PPC_SIGCONTEXT_H - -#include <asm/ptrace.h> - - -struct sigcontext_struct { - unsigned long _unused[4]; - int signal; - unsigned long handler; - unsigned long oldmask; - struct pt_regs *regs; -}; - -#endif diff --git a/include/asm-ppc/signal.h b/include/asm-ppc/signal.h deleted file mode 100644 index b11a28efd1..0000000000 --- a/include/asm-ppc/signal.h +++ /dev/null @@ -1,154 +0,0 @@ -#ifndef _ASMPPC_SIGNAL_H -#define _ASMPPC_SIGNAL_H - -#include <linux/types.h> - -/* Avoid too many header ordering problems. */ -struct siginfo; - -/* Most things should be clean enough to redefine this at will, if care - is taken to make libc match. */ - -#define _NSIG 64 -#define _NSIG_BPW 32 -#define _NSIG_WORDS (_NSIG / _NSIG_BPW) - -typedef unsigned long old_sigset_t; /* at least 32 bits */ - -typedef struct { - unsigned long sig[_NSIG_WORDS]; -} sigset_t; - -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGABRT 6 -#define SIGIOT 6 -#define SIGBUS 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGUSR1 10 -#define SIGSEGV 11 -#define SIGUSR2 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGSTKFLT 16 -#define SIGCHLD 17 -#define SIGCONT 18 -#define SIGSTOP 19 -#define SIGTSTP 20 -#define SIGTTIN 21 -#define SIGTTOU 22 -#define SIGURG 23 -#define SIGXCPU 24 -#define SIGXFSZ 25 -#define SIGVTALRM 26 -#define SIGPROF 27 -#define SIGWINCH 28 -#define SIGIO 29 -#define SIGPOLL SIGIO -/* -#define SIGLOST 29 -*/ -#define SIGPWR 30 -#define SIGSYS 31 -#define SIGUNUSED 31 - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) - -/* - * SA_FLAGS values: - * - * SA_ONSTACK is not currently supported, but will allow sigaltstack(2). - * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001 -#define SA_NOCLDWAIT 0x00000002 /* not supported yet */ -#define SA_SIGINFO 0x00000004 -#define SA_ONSTACK 0x08000000 -#define SA_RESTART 0x10000000 -#define SA_NODEFER 0x40000000 -#define SA_RESETHAND 0x80000000 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND -#define SA_INTERRUPT 0x20000000 /* dummy -- ignored */ - -#define SA_RESTORER 0x04000000 - -/* - * sigaltstack controls - */ -#define SS_ONSTACK 1 -#define SS_DISABLE 2 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 -#ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void (*__sighandler_t)(int); - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ - -struct old_sigaction { - __sighandler_t sa_handler; - old_sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -struct sigaction { - __sighandler_t sa_handler; - unsigned long sa_flags; - void (*sa_restorer)(void); - sigset_t sa_mask; /* mask last for extensibility */ -}; - -struct k_sigaction { - struct sigaction sa; -}; - -typedef struct sigaltstack { - void *ss_sp; - int ss_flags; - size_t ss_size; -} stack_t; - -#ifdef __KERNEL__ -#include <asm/sigcontext.h> - -#endif - -#endif diff --git a/include/asm-ppc/status_led.h b/include/asm-ppc/status_led.h deleted file mode 100644 index eb81f371c9..0000000000 --- a/include/asm-ppc/status_led.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * asm/status_led.h - * - * MPC8xx/MPC8260/MPC5xx based status led support functions - */ - -#ifndef __ASM_STATUS_LED_H__ -#define __ASM_STATUS_LED_H__ - -/* if not overriden */ -#ifndef CONFIG_BOARD_SPECIFIC_LED -# if defined(CONFIG_8xx) -# include <mpc8xx.h> -# elif defined(CONFIG_8260) -# include <mpc8260.h> -# elif defined(CONFIG_5xx) -# include <mpc5xx.h> -# else -# error CPU specific Status LED header file missing. -#endif - -/* led_id_t is unsigned long mask */ -typedef unsigned long led_id_t; - -static inline void __led_init (led_id_t mask, int state) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - -#ifdef STATUS_LED_PAR - immr->STATUS_LED_PAR &= ~mask; -#endif -#ifdef STATUS_LED_ODR - immr->STATUS_LED_ODR &= ~mask; -#endif - -#if (STATUS_LED_ACTIVE == 0) - if (state == STATUS_LED_ON) - immr->STATUS_LED_DAT &= ~mask; - else - immr->STATUS_LED_DAT |= mask; -#else - if (state == STATUS_LED_ON) - immr->STATUS_LED_DAT |= mask; - else - immr->STATUS_LED_DAT &= ~mask; -#endif -#ifdef STATUS_LED_DIR - immr->STATUS_LED_DIR |= mask; -#endif -} - -static inline void __led_toggle (led_id_t mask) -{ - ((immap_t *) CFG_IMMR)->STATUS_LED_DAT ^= mask; -} - -static inline void __led_set (led_id_t mask, int state) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - -#if (STATUS_LED_ACTIVE == 0) - if (state == STATUS_LED_ON) - immr->STATUS_LED_DAT &= ~mask; - else - immr->STATUS_LED_DAT |= mask; -#else - if (state == STATUS_LED_ON) - immr->STATUS_LED_DAT |= mask; - else - immr->STATUS_LED_DAT &= ~mask; -#endif - -} - -#endif - -#endif /* __ASM_STATUS_LED_H__ */ diff --git a/include/asm-ppc/string.h b/include/asm-ppc/string.h deleted file mode 100644 index d912a6b5fe..0000000000 --- a/include/asm-ppc/string.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef _PPC_STRING_H_ -#define _PPC_STRING_H_ - -#define __HAVE_ARCH_STRCPY -#define __HAVE_ARCH_STRNCPY -#define __HAVE_ARCH_STRLEN -#define __HAVE_ARCH_STRCMP -#define __HAVE_ARCH_STRCAT -#define __HAVE_ARCH_MEMSET -#define __HAVE_ARCH_BCOPY -#define __HAVE_ARCH_MEMCPY -#define __HAVE_ARCH_MEMMOVE -#define __HAVE_ARCH_MEMCMP -#define __HAVE_ARCH_MEMCHR - -extern int strcasecmp(const char *, const char *); -extern int strncasecmp(const char *, const char *, int); -extern char * strcpy(char *,const char *); -extern char * strncpy(char *,const char *, __kernel_size_t); -extern __kernel_size_t strlen(const char *); -extern int strcmp(const char *,const char *); -extern char * strcat(char *, const char *); -extern void * memset(void *,int,__kernel_size_t); -extern void * memcpy(void *,const void *,__kernel_size_t); -extern void * memmove(void *,const void *,__kernel_size_t); -extern int memcmp(const void *,const void *,__kernel_size_t); -extern void * memchr(const void *,int,__kernel_size_t); - -#endif diff --git a/include/asm-ppc/types.h b/include/asm-ppc/types.h deleted file mode 100644 index 4ebbb9e028..0000000000 --- a/include/asm-ppc/types.h +++ /dev/null @@ -1,50 +0,0 @@ -#ifndef _PPC_TYPES_H -#define _PPC_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -typedef struct { - __u32 u[4]; -} __attribute((aligned(16))) vector128; - -#ifdef __KERNEL__ -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* DMA addresses are 32-bits wide */ -typedef u32 dma_addr_t; - -#endif /* __KERNEL__ */ -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h deleted file mode 100644 index 30b44e3d22..0000000000 --- a/include/asm-ppc/u-boot.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2000 - 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef __U_BOOT_H__ -#define __U_BOOT_H__ - -/* - * Board information passed to Linux kernel from U-Boot - * - * include/asm-ppc/u-boot.h - */ - -#ifndef __ASSEMBLY__ - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ - || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) - unsigned long bi_immr_base; /* base of IMMR register */ -#endif -#if defined(CONFIG_MPC5xxx) - unsigned long bi_mbar_base; /* base of internal registers */ -#endif -#if defined(CONFIG_MPC83XX) - unsigned long bi_immrbar; -#endif -#if defined(CONFIG_MPC8220) - unsigned long bi_mbar_base; /* base of internal registers */ - unsigned long bi_inpfreq; /* Input Freq, In MHz */ - unsigned long bi_pcifreq; /* PCI Freq, in MHz */ - unsigned long bi_pevfreq; /* PEV Freq, in MHz */ - unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */ - unsigned long bi_vcofreq; /* VCO Freq, in MHz */ -#endif - unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned char bi_enetaddr[6]; /* Ethernet adress */ - unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ - unsigned long bi_intfreq; /* Internal Freq, in MHz */ - unsigned long bi_busfreq; /* Bus Freq, in MHz */ -#if defined(CONFIG_CPM2) - unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ - unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ - unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ - unsigned long bi_vco; /* VCO Out from PLL, in MHz */ -#endif -#if defined(CONFIG_MPC5xxx) - unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ - unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ -#endif - unsigned long bi_baudrate; /* Console Baudrate */ -#if defined(CONFIG_405) || \ - defined(CONFIG_405GP) || \ - defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || \ - defined(CONFIG_440) - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ - unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ - unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ - unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ - unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ -#endif -#if defined(CONFIG_HYMOD) - hymod_conf_t bi_hymod_conf; /* hymod configuration information */ -#endif - -#ifdef CONFIG_HAS_ETH1 - /* second onboard ethernet port */ - unsigned char bi_enet1addr[6]; -#endif -#ifdef CONFIG_HAS_ETH2 - /* third onboard ethernet port */ - unsigned char bi_enet2addr[6]; -#endif -#ifdef CONFIG_HAS_ETH3 - unsigned char bi_enet3addr[6]; -#endif - -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - unsigned int bi_opbfreq; /* OPB clock in Hz */ - int bi_iic_fast[2]; /* Use fast i2c mode */ -#endif -#if defined(CONFIG_NX823) - unsigned char bi_sernum[8]; -#endif -#if defined(CONFIG_4xx) -#if defined(CONFIG_440GX) - int bi_phynum[4]; /* Determines phy mapping */ - int bi_phymode[4]; /* Determines phy mode */ -#elif defined(CONFIG_405EP) || defined(CONFIG_440) - int bi_phynum[2]; /* Determines phy mapping */ - int bi_phymode[2]; /* Determines phy mode */ -#else - int bi_phynum[1]; /* Determines phy mapping */ - int bi_phymode[1]; /* Determines phy mode */ -#endif -#endif /* defined(CONFIG_4xx) */ -} bd_t; - -#endif /* __ASSEMBLY__ */ -#endif /* __U_BOOT_H__ */ diff --git a/include/asm-sandbox/arch-sandbox/hostfile.h b/include/asm-sandbox/arch-sandbox/hostfile.h deleted file mode 100644 index 30f9499c03..0000000000 --- a/include/asm-sandbox/arch-sandbox/hostfile.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef __ASM_ARCH_HOSTFILE_H -#define __ASM_ARCH_HOSTFILE_H - -struct hf_platform_data { - int fd; - size_t size; - unsigned long map_base; - char *filename; - char *name; -}; - -int u_boot_register_filedev(struct hf_platform_data *hf); - -#endif /* __ASM_ARCH_HOSTFILE_H */ - diff --git a/include/asm-sandbox/arch-sandbox/linux.h b/include/asm-sandbox/arch-sandbox/linux.h deleted file mode 100644 index 09376413e9..0000000000 --- a/include/asm-sandbox/arch-sandbox/linux.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __ASM_ARCH_LINUX_H -#define __ASM_ARCH_LINUX_H - -int linux_register_device(const char *name, void *start, void *end); -int tap_alloc(char *dev); -uint64_t linux_get_time(void); -int linux_read(int fd, void *buf, size_t count); -int linux_read_nonblock(int fd, void *buf, size_t count); -ssize_t linux_write(int fd, const void *buf, size_t count); -off_t linux_lseek(int fildes, off_t offset); -int linux_getc (void); -void linux_putc (const char c); -int linux_tstc(int fd); - -int u_boot_register_console(char *name_template, int stdinfd, int stdoutfd); - -struct linux_console_data { - int stdinfd; - int stdoutfd; - unsigned int flags; -}; - -#endif /* __ASM_ARCH_LINUX_H */ diff --git a/include/asm-sandbox/bitops.h b/include/asm-sandbox/bitops.h deleted file mode 100644 index 94646d4d0d..0000000000 --- a/include/asm-sandbox/bitops.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _SANDBOX_BITOPS_H -#define _SANDBOX_BITOPS_H - -/* nothing but the defaults.. */ -#include <asm-generic/bitops/__ffs.h> -#include <asm-generic/bitops/__fls.h> -#include <asm-generic/bitops/ffs.h> -#include <asm-generic/bitops/fls.h> -#include <asm-generic/bitops/ffz.h> -#include <asm-generic/bitops/find.h> -#include <asm-generic/bitops/fls64.h> -#include <asm-generic/bitops/hweight.h> -#include <asm-generic/bitops/ops.h> - -#endif diff --git a/include/asm-sandbox/byteorder.h b/include/asm-sandbox/byteorder.h deleted file mode 100644 index 37316f2371..0000000000 --- a/include/asm-sandbox/byteorder.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _I386_BYTEORDER_H -#define _I386_BYTEORDER_H - -#include <asm/types.h> - -#include <linux/byteorder/little_endian.h> - -#endif /* _I386_BYTEORDER_H */ diff --git a/include/asm-sandbox/common.h b/include/asm-sandbox/common.h deleted file mode 100644 index 9b8bd2d94c..0000000000 --- a/include/asm-sandbox/common.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef ASM_COMMON_H -#define ASM_COMMON_H - -#define ARCH_HAS_CTRLC - -#endif /* ASM_COMMON_H */ diff --git a/include/asm-sandbox/elf.h b/include/asm-sandbox/elf.h deleted file mode 100644 index b60d24890c..0000000000 --- a/include/asm-sandbox/elf.h +++ /dev/null @@ -1,2 +0,0 @@ - -/* nothing yet */ diff --git a/include/asm-sandbox/global_data.h b/include/asm-sandbox/global_data.h deleted file mode 100644 index 51d9405d65..0000000000 --- a/include/asm-sandbox/global_data.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H -typedef struct global_data gd_t; - -#define DECLARE_GLOBAL_DATA_PTR - -#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-sandbox/posix_types.h b/include/asm-sandbox/posix_types.h deleted file mode 100644 index 5dcc842ab7..0000000000 --- a/include/asm-sandbox/posix_types.h +++ /dev/null @@ -1,80 +0,0 @@ -#ifndef __ARCH_I386_POSIX_TYPES_H -#define __ARCH_I386_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned long __kernel_size_t; -typedef long __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -#define __FD_SET(fd,fdsetp) \ - __asm__ __volatile__("btsl %1,%0": \ - "=m" (*(__kernel_fd_set *) (fdsetp)):"r" ((int) (fd))) - -#undef __FD_CLR -#define __FD_CLR(fd,fdsetp) \ - __asm__ __volatile__("btrl %1,%0": \ - "=m" (*(__kernel_fd_set *) (fdsetp)):"r" ((int) (fd))) - -#undef __FD_ISSET -#define __FD_ISSET(fd,fdsetp) (__extension__ ({ \ - unsigned char __result; \ - __asm__ __volatile__("btl %1,%2 ; setb %0" \ - :"=q" (__result) :"r" ((int) (fd)), \ - "m" (*(__kernel_fd_set *) (fdsetp))); \ - __result; })) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) \ -do { \ - int __d0, __d1; \ - __asm__ __volatile__("cld ; rep ; stosl" \ - :"=m" (*(__kernel_fd_set *) (fdsetp)), \ - "=&c" (__d0), "=&D" (__d1) \ - :"a" (0), "1" (__FDSET_LONGS), \ - "2" ((__kernel_fd_set *) (fdsetp)) : "memory"); \ -} while (0) - -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ - -#endif diff --git a/include/asm-sandbox/processor.h b/include/asm-sandbox/processor.h deleted file mode 100644 index 5dedba82ca..0000000000 --- a/include/asm-sandbox/processor.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_PROCESSOR_H_ -#define __ASM_PROCESSOR_H_ 1 -/* Currently this header is unused in the i386 port - * but some generic files #include <asm/processor.h> - * so this file is a placeholder. */ -#endif diff --git a/include/asm-sandbox/ptrace.h b/include/asm-sandbox/ptrace.h deleted file mode 100644 index 2997587d82..0000000000 --- a/include/asm-sandbox/ptrace.h +++ /dev/null @@ -1 +0,0 @@ -/* dummy */ diff --git a/include/asm-sandbox/string.h b/include/asm-sandbox/string.h deleted file mode 100644 index 2997587d82..0000000000 --- a/include/asm-sandbox/string.h +++ /dev/null @@ -1 +0,0 @@ -/* dummy */ diff --git a/include/asm-sandbox/types.h b/include/asm-sandbox/types.h deleted file mode 100644 index a9872194d9..0000000000 --- a/include/asm-sandbox/types.h +++ /dev/null @@ -1,58 +0,0 @@ -#ifndef __ASM_I386_TYPES_H -#define __ASM_I386_TYPES_H - -#ifdef __x86_64__ -/* - * This is used in dlmalloc. On X86_64 we need it to be - * 64 bit - */ -#define INTERNAL_SIZE_T unsigned long -#endif - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-sandbox/u-boot.h b/include/asm-sandbox/u-boot.h deleted file mode 100644 index 2997587d82..0000000000 --- a/include/asm-sandbox/u-boot.h +++ /dev/null @@ -1 +0,0 @@ -/* dummy */ diff --git a/include/debug_ll.h b/include/debug_ll.h index f06fa6e57a..e99ae7d207 100644 --- a/include/debug_ll.h +++ b/include/debug_ll.h @@ -26,7 +26,7 @@ #define __INCLUDE_DEBUG_LL_H__ #if defined (CONFIG_DEBUG_LL) -# include <asm/arch/debug_ll.h> +# include <mach/debug_ll.h> #define PUTC_LL(x) putc(x) # define PUTHEX_LL(value) ({ unsigned long v = (unsigned long) (value); \ |