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author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-10-07 08:51:10 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-10-07 08:51:10 +0200 |
commit | c89e912efc4702e01bdf3bde140b5adc371d56b5 (patch) | |
tree | a188642f48be6a5baad56819a431112d0c36b34f /include | |
parent | 2da73f26645be6033840beec5611acfe241784b6 (diff) | |
parent | 35d4cf996034badd45b80c9fcd61e53036786421 (diff) | |
download | barebox-c89e912efc4702e01bdf3bde140b5adc371d56b5.tar.gz barebox-c89e912efc4702e01bdf3bde140b5adc371d56b5.tar.xz |
Merge branch 'for-next/imx'
Diffstat (limited to 'include')
-rw-r--r-- | include/soc/fsl/fsl_udc.h | 11 | ||||
-rw-r--r-- | include/soc/imx8m/ddr.h | 22 |
2 files changed, 32 insertions, 1 deletions
diff --git a/include/soc/fsl/fsl_udc.h b/include/soc/fsl/fsl_udc.h index b983f714c5..0b409a9f6b 100644 --- a/include/soc/fsl/fsl_udc.h +++ b/include/soc/fsl/fsl_udc.h @@ -1,6 +1,9 @@ #ifndef __FSL_UDC_H #define __FSL_UDC_H +#include <linux/types.h> +#include <io.h> + /* USB DR device mode registers (Little Endian) */ struct usb_dr_device { /* Capability register */ @@ -380,4 +383,12 @@ int imx_barebox_start_usb(void __iomem *dr, void *dest); int imx8mm_barebox_load_usb(void *dest); int imx8mm_barebox_start_usb(void *dest); +static inline bool is_chipidea_udc_running(void __iomem *dr) +{ + struct usb_dr_device __iomem *dr_regs = dr; + + return (readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_DEVICE) + && (readl(&dr_regs->usbcmd) & USB_CMD_RUN_STOP); +} + #endif /* __FSL_UDC_H */ diff --git a/include/soc/imx8m/ddr.h b/include/soc/imx8m/ddr.h index 78b15f1d46..9ae7cb8776 100644 --- a/include/soc/imx8m/ddr.h +++ b/include/soc/imx8m/ddr.h @@ -329,6 +329,11 @@ enum fw_type { FW_2D_IMAGE, }; +enum dram_type { + DRAM_TYPE_LPDDR4, + DRAM_TYPE_DDR4, +}; + struct dram_cfg_param { unsigned int reg; unsigned int val; @@ -342,6 +347,7 @@ struct dram_fsp_msg { }; struct dram_timing_info { + enum dram_type dram_type; /* umctl2 config */ struct dram_cfg_param *ddrc_cfg; unsigned int ddrc_cfg_num; @@ -365,11 +371,13 @@ extern struct dram_timing_info dram_timing; enum ddrc_type { DDRC_TYPE_MM, + DDRC_TYPE_MN, DDRC_TYPE_MQ, DDRC_TYPE_MP, }; int imx8mm_ddr_init(struct dram_timing_info *timing_info); +int imx8mn_ddr_init(struct dram_timing_info *timing_info); int imx8mq_ddr_init(struct dram_timing_info *timing_info); int imx8mp_ddr_init(struct dram_timing_info *timing_info); int ddr_cfg_phy(struct dram_timing_info *timing_info, enum ddrc_type type); @@ -407,12 +415,24 @@ enum ddrc_phy_firmware_offset { DDRC_PHY_DMEM = 0x00054000U, }; -void ddr_load_train_code(enum fw_type type); +void ddr_load_train_code(enum dram_type dram_type, enum fw_type type); void ddrc_phy_load_firmware(void __iomem *, enum ddrc_phy_firmware_offset, const u16 *, size_t); +static inline bool dram_is_lpddr4(enum dram_type type) +{ + return IS_ENABLED(CONFIG_FIRMWARE_IMX_LPDDR4_PMU_TRAIN) && + type == DRAM_TYPE_LPDDR4; +} + +static inline bool dram_is_ddr4(enum dram_type type) +{ + return IS_ENABLED(CONFIG_FIRMWARE_IMX_DDR4_PMU_TRAIN) && + type == DRAM_TYPE_DDR4; +} + #define DDRC_PHY_REG(x) ((x) * 4) #endif |