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| author | Enrico Jorns <ejo@pengutronix.de> | 2016-08-09 09:00:28 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-08-18 08:19:45 +0200 |
| commit | 5679e3296f75de1d0dcac7d374d5169309c3f70a (patch) | |
| tree | 953d552bfc85da8231c8035b981527a3153c3f86 /scripts/socfpga_mkimage.c | |
| parent | a308f2eb318a862c1974ade82f1d0c399b313e9a (diff) | |
| download | barebox-5679e3296f75de1d0dcac7d374d5169309c3f70a.tar.gz barebox-5679e3296f75de1d0dcac7d374d5169309c3f70a.tar.xz | |
clk: socfpga: add divider registers to the main pll outputs
This patch is based on kernel patch 0691bb1b5a1865b3bbc9b7ce6e26eff546abb1cf
by Dinh Nguyen <dinguyen@altera.com>.
The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main
PLL go through a pre-divider before coming into the system. These registers
were hidden for the CycloneV platform, but are now used for the ArriaV
platform.
This patch updates the clock driver to read the div-reg property for the
socfpga-periph-clk clocks.
Note: The registers used for the div-reg property are not documented but
set by the preloader.
Signed-off-by: Enrico Jorns <ejo@pengutronix.de>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'scripts/socfpga_mkimage.c')
0 files changed, 0 insertions, 0 deletions