diff options
| -rw-r--r-- | arch/arm/mach-at91/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/mach-at91/at91sam9_sdramc_ll.c | 71 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9_sdramc.h | 12 |
3 files changed, 84 insertions, 1 deletions
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index bfdc89f680..12e64291ba 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y += setup.o aic.o -lwl-y += at91_pmc_ll.o ddramc_ll.o matrix.o +lwl-y += at91_pmc_ll.o ddramc_ll.o at91sam9_sdramc_ll.o matrix.o lwl-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += early_udelay.o ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),) diff --git a/arch/arm/mach-at91/at91sam9_sdramc_ll.c b/arch/arm/mach-at91/at91sam9_sdramc_ll.c new file mode 100644 index 0000000000..805cfbbe43 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9_sdramc_ll.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: BSD-1-Clause +/* + * Copyright (c) 2006, Atmel Corporation + */ + +#include <mach/at91sam9_sdramc.h> +#include <mach/early_udelay.h> + +static inline void sdramc_wr(const struct at91sam9_sdramc_config *config, + unsigned int offset, + const unsigned int value) +{ + writel(value, config->sdramc + offset); +} + +int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config, + unsigned int sdram_address) +{ + unsigned int i; + + /* Step#1 SDRAM feature must be in the configuration register */ + sdramc_wr(config, AT91_SDRAMC_CR, config->cr); + + /* Step#2 For mobile SDRAM, temperature-compensated self refresh(TCSR),... */ + + /* Step#3 The SDRAM memory type must be set in the Memory Device Register */ + sdramc_wr(config, AT91_SDRAMC_MDR, config->mdr); + + /* Step#4 The minimum pause of 200 us is provided to precede any single toggle */ + early_udelay(200); + + /* Step#5 A NOP command is issued to the SDRAM devices */ + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NOP); + writel(0x00000000, sdram_address); + + /* Step#6 An All Banks Precharge command is issued to the SDRAM devices */ + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE); + writel(0x00000000, sdram_address); + + /* Pause cycles */ + early_udelay(2000); + + /* Step#7 Eight auto-refresh cycles are provided */ + for (i = 0; i < 8; i++) { + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH); + writel(0x00000001 + i, sdram_address + 4 + 4 * i); + } + + /* Pause cycles */ + early_udelay(200); + + /* Step#8 A Mode Register set (MRS) cycle is issued to program (TCSR, PASR, DS) */ + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR); + writel(0xcafedede, sdram_address + 0x24); + + /* Pause cycles */ + early_udelay(200); + + /* Step#9 For mobile SDRAM initialization, an Extended Mode Register set ... */ + + /* Step#10 The application must go into Normal Mode, setting Mode to 0 + * and perform a write access at any location in the SDRAM. + */ + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL); // Set mode + writel(0x00000000, sdram_address); // Perform mode + + /* Step#11 Write the refresh rate into the count field in the Refresh Register. */ + sdramc_wr(config, AT91_SDRAMC_TR, config->tr); + + return 0; +} diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h index 3cda101654..c5271af827 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h @@ -85,6 +85,18 @@ #include <mach/at91sam9261.h> #include <mach/at91sam9263.h> +struct at91sam9_sdramc_config { + void __iomem *sdramc; + unsigned int mr; + unsigned int tr; + unsigned int cr; + unsigned int lpr; + unsigned int mdr; +}; + +int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config, + unsigned int sdram_address); + static inline u32 at91_get_sdram_size(void *base) { u32 val; |