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-rw-r--r--arch/arm/Kconfig3
-rw-r--r--board/pcm038/pcm038.c170
2 files changed, 69 insertions, 104 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ca429ca414..873627fbda 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -104,6 +104,9 @@ config MACH_PCM038
select HAS_CFI
select ARCH_IMX27
select MACH_HAS_LOWLEVEL_INIT
+ select SPI
+ select DRIVER_SPI_IMX
+ select DRIVER_SPI_MC13783
help
Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped
with a Freescale i.MX27 Processor
diff --git a/board/pcm038/pcm038.c b/board/pcm038/pcm038.c
index 626a73568e..20d6352255 100644
--- a/board/pcm038/pcm038.c
+++ b/board/pcm038/pcm038.c
@@ -25,6 +25,7 @@
#include <environment.h>
#include <asm/arch/imx-regs.h>
#include <fec.h>
+#include <notifier.h>
#include <asm/arch/gpio.h>
#include <asm/armlinux.h>
#include <asm/mach-types.h>
@@ -110,9 +111,6 @@ static struct device_d nand_dev = {
static int pcm038_devices_init(void)
{
int i;
- struct device_d *nand, *dev;
- char *envdev = "no";
-
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
@@ -164,49 +162,12 @@ static int pcm038_devices_init(void)
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
- register_device(&cfi_dev);
- register_device(&nand_dev);
- register_device(&sdram_dev);
-#if 0
- register_device(&sram_dev);
-#endif
PCCR0 |= PCCR0_CSPI1_EN;
PCCR1 |= PCCR1_PERCLK2_EN;
spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
register_device(&spi_dev);
- switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
- case GPCR_BOOT_8BIT_NAND_2k:
- case GPCR_BOOT_16BIT_NAND_2k:
- case GPCR_BOOT_16BIT_NAND_512:
- case GPCR_BOOT_8BIT_NAND_512:
- nand = get_device_by_path("/dev/nand0");
- if (!nand)
- break;
- dev = dev_add_partition(nand, 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
- if (!dev)
- break;
- dev_add_bb_dev(dev, "self0");
-
- dev = dev_add_partition(nand, 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
- if (!dev)
- break;
- dev_add_bb_dev(dev, "env0");
- envdev = "NAND";
- break;
- default:
- dev_add_partition(&cfi_dev, 0x00000, 0x40000, PARTITION_FIXED, "self");
- dev_add_partition(&cfi_dev, 0x40000, 0x20000, PARTITION_FIXED, "env");
- dev_protect(&cfi_dev, 0x40000, 0, 1);
- envdev = "NOR";
- }
-
- printf("Using environment in %s Flash\n", envdev);
-
- armlinux_set_bootparams((void *)0xa0000100);
- armlinux_set_architecture(MACH_TYPE_PCM038);
-
return 0;
}
@@ -220,17 +181,10 @@ static struct device_d pcm038_serial_device = {
.type = DEVICE_TYPE_CONSOLE,
};
-static int pcm038_console_init(void)
-{
- register_device(&pcm038_serial_device);
- return 0;
-}
-
-console_initcall(pcm038_console_init);
-
static int pcm038_power_init(void)
{
-#ifdef CONFIG_DRIVER_SPI_MC13783
+ struct device_d *nand, *dev;
+ char *envdev = "no";
int i = 0;
int ret;
@@ -238,51 +192,8 @@ static int pcm038_power_init(void)
if (ret)
goto out;
- CSCR |= CSCR_UPDATE_DIS;
-
- MPCTL0 = IMX_PLL_PD(0) |
- IMX_PLL_MFD(51) |
- IMX_PLL_MFI(7) |
- IMX_PLL_MFN(35);
-
/* wait for good power level */
- while (i++ < 128) {
- while (CCSR & CCSR_32K_SR);
- while (!(CCSR & CCSR_32K_SR));
- }
- i = 0;
-
- CSCR |= CSCR_MPLL_RESTART;
-
- while (!(MPCTL1 & MPCTL1_LF));
-
- PCDR1 = 0x09030911;
-
-out:
-#else
-#warning no pmic support enabled. your pcm038 will run on low speed
-#endif
-
- /* Register the fec device after the PLL re-initialisation
- * as the fec depends on the (now higher) ipg clock
- */
- register_device(&fec_dev);
-
- return 0;
-}
-
-late_initcall(pcm038_power_init);
-
-#ifdef CONFIG_NAND_IMX_BOOT
-void __bare_init nand_boot(void)
-{
- imx_nand_load_image((void *)TEXT_BASE, 256 * 1024, 512, 16384);
-}
-#endif
-
-static int pll_init(void)
-{
- int i = 0;
+ udelay(1000);
#define CSCR_VAL CSCR_USB_DIV(3) | \
CSCR_SD_CNT(3) | \
@@ -291,19 +202,19 @@ static int pll_init(void)
CSCR_SSI1_SEL | \
CSCR_SSI2_SEL | \
CSCR_MCU_SEL | \
- CSCR_SP_SEL | \
CSCR_ARM_SRC_MPLL | \
+ CSCR_SP_SEL | \
CSCR_ARM_DIV(0) | \
CSCR_FPM_EN | \
CSCR_SPEN | \
CSCR_MPEN
- CSCR = CSCR_VAL | CSCR_AHB_DIV(3);
+ CSCR &= ~CSCR_MCU_SEL;
/*
* pll clock initialization - see section 3.4.3 of the i.MX27 manual
*/
- MPCTL0 = IMX_PLL_PD(1) |
+ MPCTL0 = IMX_PLL_PD(0) |
IMX_PLL_MFD(51) |
IMX_PLL_MFI(7) |
IMX_PLL_MFN(35); /* MPLL = 2 * 26 * 3.83654 MHz = 199.5 MHz */
@@ -321,20 +232,71 @@ static int pll_init(void)
CSCR = CSCR_VAL | CSCR_AHB_DIV(1) | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART;
- while (i++ < 1000) {
- while (CCSR & CCSR_32K_SR);
- while (!(CCSR & CCSR_32K_SR));
- }
+ udelay(1000);
/* clock gating enable */
GPCR = 0x00050f08;
- /* peripheral clock divider */
- PCDR0 = 0x130410c3; /* FIXME */
- PCDR1 = 0x09030908; /* PERDIV1=08 @133 MHz */
+ PCDR0 = 0x130410c3;
+ PCDR1 = 0x09030911;
+
+ /* Clocks have changed. Notify clients */
+ clock_notifier_call_chain();
+
+out:
+ register_device(&pcm038_serial_device);
+ register_device(&cfi_dev);
+ register_device(&nand_dev);
+ register_device(&sdram_dev);
+#if 0
+ register_device(&sram_dev);
+#endif
+
+ /* Register the fec device after the PLL re-initialisation
+ * as the fec depends on the (now higher) ipg clock
+ */
+ register_device(&fec_dev);
+
+ switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
+ case GPCR_BOOT_8BIT_NAND_2k:
+ case GPCR_BOOT_16BIT_NAND_2k:
+ case GPCR_BOOT_16BIT_NAND_512:
+ case GPCR_BOOT_8BIT_NAND_512:
+ nand = get_device_by_path("/dev/nand0");
+ if (!nand)
+ break;
+ dev = dev_add_partition(nand, 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+ if (!dev)
+ break;
+ dev_add_bb_dev(dev, "self0");
+
+ dev = dev_add_partition(nand, 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
+ if (!dev)
+ break;
+ dev_add_bb_dev(dev, "env0");
+ envdev = "NAND";
+ break;
+ default:
+ dev_add_partition(&cfi_dev, 0x00000, 0x40000, PARTITION_FIXED, "self");
+ dev_add_partition(&cfi_dev, 0x40000, 0x20000, PARTITION_FIXED, "env");
+ dev_protect(&cfi_dev, 0x40000, 0, 1);
+ envdev = "NOR";
+ }
+
+ printf("Using environment in %s Flash\n", envdev);
+
+ armlinux_set_bootparams((void *)0xa0000100);
+ armlinux_set_architecture(MACH_TYPE_PCM038);
return 0;
}
-core_initcall(pll_init);
+late_initcall(pcm038_power_init);
+
+#ifdef CONFIG_NAND_IMX_BOOT
+void __bare_init nand_boot(void)
+{
+ imx_nand_load_image((void *)TEXT_BASE, 256 * 1024, 512, 16384);
+}
+#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-28 18:34:18 +0000