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-rw-r--r--arch/arm/mach-imx/clocksource.c8
-rw-r--r--include/asm-arm/arch-imx/imx1-regs.h3
-rw-r--r--include/asm-arm/arch-imx/imx27-regs.h3
3 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c
index b7eba06e1b..e8894a3301 100644
--- a/arch/arm/mach-imx/clocksource.c
+++ b/arch/arm/mach-imx/clocksource.c
@@ -90,13 +90,7 @@ void reset_cpu (ulong ignored)
WSR = 0x0000AAAA;
/* Enable watchdog */
-#ifdef CONFIG_ARCH_IMX1
- WCR = 0x00000001;
-#elif defined CONFIG_ARCH_IMX27
- WCR = 1 << 2;
-#else
-#error unknown i.MX soc
-#endif
+ WCR = WCR_WDE;
while (1);
/*NOTREACHED*/
diff --git a/include/asm-arm/arch-imx/imx1-regs.h b/include/asm-arm/arch-imx/imx1-regs.h
index 224f7d8ee5..1488304db8 100644
--- a/include/asm-arm/arch-imx/imx1-regs.h
+++ b/include/asm-arm/arch-imx/imx1-regs.h
@@ -45,6 +45,9 @@
#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */
#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */
+/* important definition of some bits of WCR */
+#define WCR_WDE 0x01
+
/* SYSCTRL Registers */
#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */
#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
diff --git a/include/asm-arm/arch-imx/imx27-regs.h b/include/asm-arm/arch-imx/imx27-regs.h
index db4d071c82..962b22ee63 100644
--- a/include/asm-arm/arch-imx/imx27-regs.h
+++ b/include/asm-arm/arch-imx/imx27-regs.h
@@ -71,6 +71,9 @@
#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */
#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */
+/* important definition of some bits of WCR */
+#define WCR_WDE 0x04
+
/* PLL registers */
#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */
#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */