diff options
43 files changed, 2890 insertions, 100 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index f9daa08a38..a85de760f7 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_MACH_HIGHBANK) += highbank/ obj-$(CONFIG_MACH_IMX21ADS) += freescale-mx21-ads/ obj-$(CONFIG_MACH_IMX233_OLINUXINO) += imx233-olinuxino/ obj-$(CONFIG_MACH_IMX27ADS) += freescale-mx27-ads/ +obj-$(CONFIG_MACH_LUBBOCK) += lubbock/ obj-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += marvell-armada-xp-gp/ obj-$(CONFIG_MACH_MB7707) += module-mb7707/ obj-$(CONFIG_MACH_MIOA701) += mioa701/ @@ -126,4 +127,5 @@ obj-$(CONFIG_MACH_VERSATILEPB) += versatile/ obj-$(CONFIG_MACH_VEXPRESS) += vexpress/ obj-$(CONFIG_MACH_VIRT2REAL) += virt2real/ obj-$(CONFIG_MACH_ZEDBOARD) += avnet-zedboard/ +obj-$(CONFIG_MACH_ZYLONITE) += zylonite/ obj-$(CONFIG_MACH_VARISCITE_MX6) += variscite-mx6/ diff --git a/arch/arm/boards/lubbock/Makefile b/arch/arm/boards/lubbock/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/lubbock/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/lubbock/board.c b/arch/arm/boards/lubbock/board.c new file mode 100644 index 0000000000..6f517d8926 --- /dev/null +++ b/arch/arm/boards/lubbock/board.c @@ -0,0 +1,134 @@ +/* + * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <driver.h> +#include <environment.h> +#include <fs.h> +#include <init.h> +#include <partition.h> +#include <led.h> +#include <gpio.h> +#include <pwm.h> +#include <linux/sizes.h> + +#include <mach/devices.h> +#include <mach/mfp-pxa27x.h> +#include <mach/pxa-regs.h> +#include <mach/udc_pxa2xx.h> +#include <mach/mci_pxa2xx.h> + +#include <net/smc91111.h> +#include <asm/armlinux.h> +#include <asm/io.h> +#include <asm/mmu.h> + +#include <generated/mach-types.h> + +#define ECOR 0x8000 +#define ECOR_RESET 0x80 +#define ECOR_LEVEL_IRQ 0x40 +#define ECOR_WR_ATTRIB 0x04 +#define ECOR_ENABLE 0x01 + +#define ECSR 0x8002 +#define ECSR_IOIS8 0x20 +#define ECSR_PWRDWN 0x04 +#define ECSR_INT 0x02 + +static struct smc91c111_pdata smsc91x_pdata = { + .control_setup = 0x0800, + .config_setup = 0x10b2, + .bus_width = 16, + .addr_shift = 2, +}; + +static unsigned long lubbock_pin_config[] = { + GPIO15_nCS_1, /* CS1 - Flash */ + GPIO78_nCS_2, /* CS2 - Baseboard FGPA + SRAM */ + GPIO79_nCS_3, /* CS3 - SMC ethernet */ + GPIO80_nCS_4, /* CS4 - SA1111 */ + + /* LCD - 16bpp DSTN */ + GPIOxx_LCD_DSTN_16BPP, + + /* FFUART */ + GPIO34_FFUART_RXD, + GPIO35_FFUART_CTS, + GPIO36_FFUART_DCD, + GPIO37_FFUART_DSR, + GPIO38_FFUART_RI, + GPIO39_FFUART_TXD, + GPIO40_FFUART_DTR, + GPIO41_FFUART_RTS, +}; + +static int lubbock_devices_init(void) +{ + void *nor0_iospace; + + armlinux_set_architecture(MACH_TYPE_LUBBOCK); + + pxa_add_uart((void *)0x40100000, 0); + pxa_add_pwm((void *)0x40b00000, 0); + + nor0_iospace = map_io_sections(0x0, (void *)0xe0000000, SZ_64M); + add_cfi_flash_device(0, (ulong)nor0_iospace, SZ_64M, 0); + add_cfi_flash_device(1, 0x04000000, SZ_64M, 0); + devfs_add_partition("nor0", SZ_2M, SZ_256K, DEVFS_PARTITION_FIXED, + "env0"); + add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, + 0x0c000300, 0xff4000, IORESOURCE_MEM, + &smsc91x_pdata); + return 0; +} + +device_initcall(lubbock_devices_init); + +static void smc_init(void) +{ + /* SMC91c96 */ + void __iomem *attaddr = (void __iomem *)0x0e000000; + + writel(ECOR_RESET, attaddr + (ECOR << 2)); + mdelay(100); + writel(0, attaddr + (ECOR << 2)); + writel(ECOR_ENABLE, attaddr + (ECOR << 2)); + + /* force 16-bit mode */ + writel(0, attaddr + (ECSR << 2)); + mdelay(100); +} + +static int lubbock_coredevice_init(void) +{ + barebox_set_model("Lubbock PXA25x"); + barebox_set_hostname("lubbock"); + pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config)); + smc_init(); + return 0; +} +coredevice_initcall(lubbock_coredevice_init); + +static int lubbock_mem_init(void) +{ + arm_add_mem_device("ram0", 0xa0000000, SZ_64M); + add_mem_device("sram0", 0x0a000000, SZ_1M, IORESOURCE_MEM_WRITEABLE); + return 0; +} +mem_initcall(lubbock_mem_init); diff --git a/arch/arm/boards/lubbock/env/boot/nor-ubi b/arch/arm/boards/lubbock/env/boot/nor-ubi new file mode 100644 index 0000000000..533605e86a --- /dev/null +++ b/arch/arm/boards/lubbock/env/boot/nor-ubi @@ -0,0 +1,5 @@ +#!/bin/sh + +global.bootm.image="/dev/nor0.kernel" +#global.bootm.oftree="/env/oftree" +global.linux.bootargs.dyn.root="root=ubi0:linux_root ubi.mtd=nor0.root rootfstype=ubifs" diff --git a/arch/arm/boards/lubbock/env/init/mtdparts-nor b/arch/arm/boards/lubbock/env/init/mtdparts-nor new file mode 100644 index 0000000000..3307596467 --- /dev/null +++ b/arch/arm/boards/lubbock/env/init/mtdparts-nor @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NOR partitions" + exit +fi + +mtdparts="2048k@0(nor0.barebox)ro,256k(nor0.barebox-env),256k(nor0.barebox-logo),256k(nor0.barebox-logo2),5120k(nor0.kernel),-(nor0.root)" +kernelname="application-flash" + +mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/lubbock/env/nv/linux.bootargs.base b/arch/arm/boards/lubbock/env/nv/linux.bootargs.base new file mode 100644 index 0000000000..476b1fbe49 --- /dev/null +++ b/arch/arm/boards/lubbock/env/nv/linux.bootargs.base @@ -0,0 +1 @@ +console=ttyS0,115200 diff --git a/arch/arm/boards/lubbock/lowlevel.c b/arch/arm/boards/lubbock/lowlevel.c new file mode 100644 index 0000000000..3c8ae76e03 --- /dev/null +++ b/arch/arm/boards/lubbock/lowlevel.c @@ -0,0 +1,192 @@ +#include <common.h> +#include <init.h> +#include <io.h> + +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <linux/sizes.h> +#include <mach/pxa-regs.h> +#include <mach/regs-ost.h> + +/* + * Memory settings + */ +#define DEFAULT_MSC0_VAL 0x23d223d2 +#define DEFAULT_MSC1_VAL 0x3ff1a441 +#define DEFAULT_MSC2_VAL 0x7ff17ff1 +#define DEFAULT_MDCNFG_VAL 0x00001ac9 +#define DEFAULT_MDREFR_VAL 0x00018018 +#define DEFAULT_MDMRS_VAL 0x00000000 + +#define DEFAULT_FLYCNFG_VAL 0x00000000 +#define DEFAULT_SXCNFG_VAL 0x00000000 + +/* + * PCMCIA and CF Interfaces + */ +#define DEFAULT_MECR_VAL 0x00000000 +#define DEFAULT_MCMEM0_VAL 0x00010504 +#define DEFAULT_MCMEM1_VAL 0x00010504 +#define DEFAULT_MCATT0_VAL 0x00010504 +#define DEFAULT_MCATT1_VAL 0x00010504 +#define DEFAULT_MCIO0_VAL 0x00004715 +#define DEFAULT_MCIO1_VAL 0x00004715 + +static inline void writelrb(uint32_t val, volatile u32 __iomem *addr) +{ + writel(val, addr); + barrier(); + readl(addr); + barrier(); +} + +static inline void pxa_wait_ticks(int ticks) +{ + writel(0, &OSCR); + while (readl(&OSCR) < ticks) + barrier(); +} + +static inline void pxa2xx_dram_init(void) +{ + uint32_t tmp; + int i; + /* + * 1) Initialize Asynchronous static memory controller + */ + + writelrb(DEFAULT_MSC0_VAL, &MSC0); + writelrb(DEFAULT_MSC1_VAL, &MSC1); + writelrb(DEFAULT_MSC2_VAL, &MSC2); + /* + * 2) Initialize Card Interface + */ + + /* MECR: Memory Expansion Card Register */ + writelrb(DEFAULT_MECR_VAL, &MECR); + /* MCMEM0: Card Interface slot 0 timing */ + writelrb(DEFAULT_MCMEM0_VAL, &MCMEM0); + /* MCMEM1: Card Interface slot 1 timing */ + writelrb(DEFAULT_MCMEM1_VAL, &MCMEM1); + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + writelrb(DEFAULT_MCATT0_VAL, &MCATT0); + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + writelrb(DEFAULT_MCATT1_VAL, &MCATT1); + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + writelrb(DEFAULT_MCIO0_VAL, &MCIO0); + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + writelrb(DEFAULT_MCIO1_VAL, &MCIO1); + + /* + * 3) Configure Fly-By DMA register + */ + + writelrb(DEFAULT_FLYCNFG_VAL, &FLYCNFG); + + /* + * 4) Initialize Timing for Sync Memory (SDCLK0) + */ + + /* + * Before accessing MDREFR we need a valid DRI field, so we set + * this to power on defaults + DRI field. + */ + + /* Read current MDREFR config and zero out DRI */ + tmp = readl(&MDREFR) & ~0xfff; + /* Add user-specified DRI */ + tmp |= DEFAULT_MDREFR_VAL & 0xfff; + /* Configure important bits */ + tmp |= MDREFR_K0RUN | MDREFR_SLFRSH; + tmp &= ~(MDREFR_APD | MDREFR_E1PIN); + + /* Write MDREFR back */ + writelrb(tmp, &MDREFR); + + /* + * 5) Initialize Synchronous Static Memory (Flash/Peripherals) + */ + + /* Initialize SXCNFG register. Assert the enable bits. + * + * Write SXMRS to cause an MRS command to all enabled banks of + * synchronous static memory. Note that SXLCR need not be written + * at this time. + */ + writelrb(DEFAULT_SXCNFG_VAL, &SXCNFG); + + /* + * 6) Initialize SDRAM + */ + + writelrb(DEFAULT_MDREFR_VAL & ~MDREFR_SLFRSH, &MDREFR); + writelrb(DEFAULT_MDREFR_VAL | MDREFR_E1PIN, &MDREFR); + + /* + * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure + * but not enable each SDRAM partition pair. + */ + + writelrb(DEFAULT_MDCNFG_VAL & + ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), &MDCNFG); + /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */ + pxa_wait_ticks(0x300); + + /* + * 8) Trigger a number (usually 8) refresh cycles by attempting + * non-burst read or write accesses to disabled SDRAM, as commonly + * specified in the power up sequence documented in SDRAM data + * sheets. The address(es) used for this purpose must not be + * cacheable. + */ + for (i = 9; i >= 0; i--) { + writel(i, 0xa0000000); + barrier(); + } + /* + * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). + */ + + tmp = DEFAULT_MDCNFG_VAL & + (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3); + tmp |= readl(&MDCNFG); + writelrb(tmp, &MDCNFG); + + /* + * 10) Write MDMRS. + */ + + writelrb(DEFAULT_MDMRS_VAL, &MDMRS); + + /* + * 11) Enable APD + */ + + if (DEFAULT_MDREFR_VAL & MDREFR_APD) { + tmp = readl(&MDREFR); + tmp |= MDREFR_APD; + writelrb(tmp, &MDREFR); + } +} + +void __bare_init __naked barebox_arm_reset_vector(void) +{ + unsigned long pssr = PSSR; + unsigned long pc = get_pc(); + + arm_cpu_lowlevel_init(); + CKEN |= CKEN_OSTIMER | CKEN_MEMC | CKEN_FFUART; + + /* + * When not running from SDRAM, get it out of self refresh, and/or + * initialize it. + */ + if (!(pc >= 0xa0000000 && pc < 0xb0000000)) + pxa2xx_dram_init(); + + if ((pssr >= 0xa0000000 && pssr < 0xb0000000) || + (pssr >= 0x04000000 && pssr < 0x10000000)) + asm("mov pc, %0" : : "r"(pssr) : ); + + barebox_arm_entry(0xa0000000, SZ_64M, 0); +} diff --git a/arch/arm/boards/zylonite/Makefile b/arch/arm/boards/zylonite/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/zylonite/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/zylonite/board.c b/arch/arm/boards/zylonite/board.c new file mode 100644 index 0000000000..dabc6ffb0b --- /dev/null +++ b/arch/arm/boards/zylonite/board.c @@ -0,0 +1,101 @@ +/* + * (C) 2014 Robert Jarzmik <robert.jarzmik@free.fr> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> + +#include <driver.h> +#include <environment.h> +#include <fs.h> +#include <gpio.h> +#include <init.h> +#include <partition.h> +#include <led.h> +#include <net/smc91111.h> +#include <platform_data/mtd-nand-mrvl.h> +#include <pwm.h> + +#include <mach/devices.h> +#include <mach/mfp-pxa3xx.h> +#include <mach/pxa-regs.h> + +#include <asm/armlinux.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <generated/mach-types.h> + +#include "zylonite.h" + +static struct smc91c111_pdata smsc91x_pdata; +static struct mrvl_nand_platform_data nand_pdata = { + .keep_config = 0, + .flash_bbt = 1, +}; + +static mfp_cfg_t pxa310_mfp_cfg[] = { + /* FFUART */ + MFP_CFG_LPM(GPIO99, AF1, FLOAT), /* GPIO99_UART1_RXD */ + MFP_CFG_LPM(GPIO100, AF1, FLOAT), /* GPIO100_UART1_RXD */ + MFP_CFG_LPM(GPIO101, AF1, FLOAT), /* GPIO101_UART1_CTS */ + MFP_CFG_LPM(GPIO106, AF1, FLOAT), /* GPIO106_UART1_CTS */ + + /* Ethernet */ + MFP_CFG(GPIO2, AF1), /* GPIO2_nCS3 */ +}; + +static int zylonite_devices_init(void) +{ + armlinux_set_architecture(MACH_TYPE_ZYLONITE); + pxa_add_uart((void *)0x40100000, 0); + add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, + 0x14000300, 0x100000, IORESOURCE_MEM, + &smsc91x_pdata); + add_generic_device("mrvl_nand", DEVICE_ID_DYNAMIC, NULL, + 0x43100000, 0x1000, IORESOURCE_MEM, &nand_pdata); + return 0; +} +device_initcall(zylonite_devices_init); + +static int zylonite_coredevice_init(void) +{ + barebox_set_model("Zylonite"); + barebox_set_hostname("zylonite"); + + mfp_init(); + if (cpu_is_pxa310()) + pxa3xx_mfp_config(pxa310_mfp_cfg, ARRAY_SIZE(pxa310_mfp_cfg)); + CKENA |= CKEN_NAND | CKEN_SMC | CKEN_FFUART | CKEN_GPIO; + /* + * Configure Ethernet controller : + * MCS1: setup VLIO on nCS3, with 15 DF_SCLK cycles (max) for hold, + * setup and assertion times + * CSADRCFG3: DFI AA/D multiplexing VLIO, addr split at bit <16>, full + * latched mode, 7 DF_SCLK cycles (max) for nLUA and nLLA. + */ + MSC1 = 0x7ffc0000 | (MSC1 & 0x0000ffff); + CSADRCFG3 = 0x003e080b; + + return 0; +} +coredevice_initcall(zylonite_coredevice_init); + +static int zylonite_mem_init(void) +{ + arm_add_mem_device("ram0", 0x80000000, 64 * 1024 * 1024); + return 0; +} +mem_initcall(zylonite_mem_init); diff --git a/arch/arm/boards/zylonite/env/bin/init b/arch/arm/boards/zylonite/env/bin/init new file mode 100644 index 0000000000..a6bc087b22 --- /dev/null +++ b/arch/arm/boards/zylonite/env/bin/init @@ -0,0 +1,25 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +addpart /dev/nand0 $mtdparts +usbserial -s "Zylonite usb gadget" + +# Phase1: check for MTD override +mtd_env_override +if [ $? = 0 ]; then + echo "Switching to custom environment" + /env/init + exit +fi + +# Phase2: initiate network +dhcp -H zylonite + +# Phase3: activate netconsole, broadcast everywhere +netconsole.ip=255.255.255.255 +netconsole.active=ioe +netconsole.port=6666 + diff --git a/arch/arm/boards/zylonite/env/bin/mtd_env_override b/arch/arm/boards/zylonite/env/bin/mtd_env_override new file mode 100644 index 0000000000..6ea253a4f0 --- /dev/null +++ b/arch/arm/boards/zylonite/env/bin/mtd_env_override @@ -0,0 +1,4 @@ +#!/bin/sh + +loadenv /dev/nand0.barebox-env +exit $? diff --git a/arch/arm/boards/zylonite/env/config b/arch/arm/boards/zylonite/env/config new file mode 100644 index 0000000000..ee66e37cc3 --- /dev/null +++ b/arch/arm/boards/zylonite/env/config @@ -0,0 +1,6 @@ +#!/bin/sh + +autoboot_timeout=3 + +mtdparts="128k@0(TIMH)ro,128k@128k(OBMI)ro,768k@256k(barebox),256k@1024k(barebox-env),12M@1280k(kernel),38016k@13568k(root)" +bootargs="$bootargs mtdparts=pxa3xx_nand-0:$mtdparts ubi.mtd=5 rootfstype=ubifs root=ubi0:root ro ram=64M console=ttyS0,115200" diff --git a/arch/arm/boards/zylonite/lowlevel.c b/arch/arm/boards/zylonite/lowlevel.c new file mode 100644 index 0000000000..9f1aa6641c --- /dev/null +++ b/arch/arm/boards/zylonite/lowlevel.c @@ -0,0 +1,10 @@ +#include <common.h> +#include <linux/sizes.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> + +void __naked barebox_arm_reset_vector(void) +{ + arm_cpu_lowlevel_init(); + barebox_arm_entry(0x80000000, SZ_64M, NULL); +} diff --git a/arch/arm/boards/zylonite/zylonite.h b/arch/arm/boards/zylonite/zylonite.h new file mode 100644 index 0000000000..d39ab72d3d --- /dev/null +++ b/arch/arm/boards/zylonite/zylonite.h @@ -0,0 +1,22 @@ +/* + * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef _ZYLONITE_H_ +#define _ZYLONITE_H_ + + +#endif /* _ZYLONITE_H */ diff --git a/arch/arm/configs/lubbock_defconfig b/arch/arm/configs/lubbock_defconfig new file mode 100644 index 0000000000..bf04fa3b18 --- /dev/null +++ b/arch/arm/configs/lubbock_defconfig @@ -0,0 +1,106 @@ +CONFIG_ARCH_PXA=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000 +CONFIG_AEABI=y +CONFIG_ARM_BOARD_APPEND_ATAG=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +# CONFIG_BANNER is not set +CONFIG_MMU=y +CONFIG_TEXT_BASE=0xa3d00000 +CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x80000 +CONFIG_MALLOC_SIZE=0x1000000 +CONFIG_EXPERIMENTAL=y +CONFIG_MODULES=y +CONFIG_KALLSYMS=y +CONFIG_PROMPT="lubbock-barebox:" +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_CONSOLE_ACTIVATE_ALL=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/lubbock/env" +CONFIG_RESET_SOURCE=y +CONFIG_DEBUG_INFO=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_RESET=y +CONFIG_CMD_SAVES=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_UBIFORMAT=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_HOST=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_LED=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_LSMOD=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y +CONFIG_NET_NETCONSOLE=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_SERIAL_PXA=y +CONFIG_DRIVER_NET_SMC91111=y +# CONFIG_SPI is not set +CONFIG_MTD=y +CONFIG_DRIVER_CFI=y +# CONFIG_DRIVER_CFI_AMD is not set +CONFIG_CFI_BUFFER_WRITE=y +CONFIG_MTD_UBI=y +CONFIG_MCI=y +CONFIG_MCI_PXA=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_GENERIC_PHY=y +CONFIG_FS_CRAMFS=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_FS_UBIFS=y +CONFIG_FS_UBIFS_COMPRESSION_LZO=y +CONFIG_FS_UBIFS_COMPRESSION_ZLIB=y +CONFIG_BZLIB=y +CONFIG_BMP=y +CONFIG_PNG=y diff --git a/arch/arm/configs/mioa701_defconfig b/arch/arm/configs/mioa701_defconfig index 20f71e9374..d405edf01b 100644 --- a/arch/arm/configs/mioa701_defconfig +++ b/arch/arm/configs/mioa701_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_PXA=y CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000 +CONFIG_ARCH_PXA27X=y CONFIG_AEABI=y CONFIG_ARM_BOARD_APPEND_ATAG=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y diff --git a/arch/arm/configs/phytec-phycore-pxa270_defconfig b/arch/arm/configs/phytec-phycore-pxa270_defconfig index b7bf190df2..57eaff09ec 100644 --- a/arch/arm/configs/phytec-phycore-pxa270_defconfig +++ b/arch/arm/configs/phytec-phycore-pxa270_defconfig @@ -1,4 +1,5 @@ CONFIG_ARCH_PXA=y +CONFIG_ARCH_PXA27X=y CONFIG_MACH_PCM027=y CONFIG_AEABI=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y diff --git a/arch/arm/configs/zylonite310_defconfig b/arch/arm/configs/zylonite310_defconfig new file mode 100644 index 0000000000..77e4f84ff1 --- /dev/null +++ b/arch/arm/configs/zylonite310_defconfig @@ -0,0 +1,117 @@ +CONFIG_ARCH_PXA=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000 +CONFIG_ARCH_PXA3XX=y +CONFIG_AEABI=y +CONFIG_ARM_BOARD_APPEND_ATAG=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +# CONFIG_BANNER is not set +CONFIG_MMU=y +CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x80000 +CONFIG_MALLOC_SIZE=0x1000000 +CONFIG_EXPERIMENTAL=y +CONFIG_MODULES=y +CONFIG_KALLSYMS=y +CONFIG_PROMPT="zylonite-barebox:" +CONFIG_GLOB=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_CONSOLE_ACTIVATE_ALL=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/zylonite/env" +CONFIG_RESET_SOURCE=y +CONFIG_DEFAULT_LOGLEVEL=8 +CONFIG_DEBUG_INFO=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MEMINFO=y +CONFIG_FLEXIBLE_BOOTARGS=y +CONFIG_CMD_BOOT=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_RESET=y +CONFIG_CMD_SAVES=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_AUTOMOUNT=y +CONFIG_CMD_UBIFORMAT=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_GLOBAL=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_BASENAME=y +CONFIG_CMD_CMP=y +CONFIG_CMD_DIRNAME=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_READLINK=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_HOST=y +CONFIG_NET_CMD_IFUP=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_LOGIN=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_PASSWD=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_2048=y +CONFIG_CMD_LSMOD=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y +CONFIG_NET_NETCONSOLE=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_SERIAL_PXA=y +CONFIG_DRIVER_NET_SMC91111=y +# CONFIG_SPI is not set +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MRVL_NFC=y +CONFIG_MTD_UBI=y +CONFIG_MCI=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_PWM=y +# CONFIG_PINCTRL is not set +CONFIG_FS_CRAMFS=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_FS_UBIFS=y +CONFIG_FS_UBIFS_COMPRESSION_LZO=y +CONFIG_FS_UBIFS_COMPRESSION_ZLIB=y +CONFIG_BZLIB=y +CONFIG_BMP=y +CONFIG_PNG=y +CONFIG_SHA256=y diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig index 8934df0074..4f5d9b6e16 100644 --- a/arch/arm/cpu/Kconfig +++ b/arch/arm/cpu/Kconfig @@ -69,6 +69,12 @@ config CPU_V7 bool select CPU_32v7 +config CPU_XSC3 + bool + select CPU_32v4T + help + Select code specific to PXA3xx variants + # Xscale PXA25x, PXA27x config CPU_XSCALE bool diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index cdec1b7e5d..a45e01a702 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -4,6 +4,7 @@ config ARCH_TEXT_BASE hex default 0xa0000000 if MACH_MIOA701 default 0xa3f00000 if MACH_PCM027 + default 0x83f00000 if MACH_ZYLONITE # ---------------------------------------------------------- @@ -11,17 +12,48 @@ config ARCH_PXA2XX bool select CPU_XSCALE +config ARCH_PXA3XX + bool + select CPU_XSC3 + +config ARCH_PXA310 + bool + choice prompt "Intel/Marvell PXA Processor" +config ARCH_PXA25X + bool "PXA25x" + select ARCH_PXA2XX + config ARCH_PXA27X bool "PXA27x" select ARCH_PXA2XX +config ARCH_PXA3XX + bool "PXA3xx" + endchoice # ---------------------------------------------------------- +if ARCH_PXA25X + +choice + prompt "PXA25x Board Type" + bool + +config MACH_LUBBOCK + bool "Lubbock board" + select PWM + help + Say Y here if you are using a Lubbock board +endchoice + +endif + +# ---------------------------------------------------------- + if ARCH_PXA27X choice @@ -55,4 +87,26 @@ endif # ---------------------------------------------------------- +if ARCH_PXA3XX + +config MACH_ZYLONITE + bool + +choice + prompt "PXA3xx Board Type" + +config MACH_ZYLONITE_PXA310 + bool "Zylonite board based on a PXA310 pxa SoC" + help + Say Y here if you are using a Zylonite board, based + on a PXA31x SoC. + select ARCH_PXA310 + select MACH_ZYLONITE + +endchoice + +endif + +# ---------------------------------------------------------- + endif diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 6ddb6e58e5..0c3219807b 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -4,6 +4,7 @@ obj-y += gpio.o obj-y += devices.o obj-y += sleep.o -obj-$(CONFIG_ARCH_PXA2XX) += mfp-pxa2xx.o +obj-$(CONFIG_ARCH_PXA2XX) += mfp-pxa2xx.o pxa2xx.o +obj-$(CONFIG_ARCH_PXA25X) += speed-pxa25x.o obj-$(CONFIG_ARCH_PXA27X) += speed-pxa27x.o -obj-$(CONFIG_RESET_SOURCE) += reset_source.o +obj-$(CONFIG_ARCH_PXA3XX) += speed-pxa3xx.o mfp-pxa3xx.o pxa3xx.o diff --git a/arch/arm/mach-pxa/common.c b/arch/arm/mach-pxa/common.c index 0c114ed58e..2c27d812fc 100644 --- a/arch/arm/mach-pxa/common.c +++ b/arch/arm/mach-pxa/common.c @@ -27,12 +27,12 @@ #define OWER_WME (1 << 0) /* Watch-dog Match Enable */ #define OSSR_M3 (1 << 3) /* Match status channel 3 */ -extern void pxa_suspend(int mode); +extern void pxa_clear_reset_source(void); void reset_cpu(ulong addr) { /* Clear last reset source */ - RCSR = RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR; + pxa_clear_reset_source(); /* Initialize the watchdog and let it fire */ writel(OWER_WME, OWER); @@ -41,14 +41,3 @@ void reset_cpu(ulong addr) while (1); } - -void __noreturn poweroff() -{ - shutdown_barebox(); - - /* Clear last reset source */ - RCSR = RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR; - - pxa_suspend(PWRMODE_DEEPSLEEP); - unreachable(); -} diff --git a/arch/arm/mach-pxa/include/mach/clock.h b/arch/arm/mach-pxa/include/mach/clock.h index f86152f7af..40f6223cd9 100644 --- a/arch/arm/mach-pxa/include/mach/clock.h +++ b/arch/arm/mach-pxa/include/mach/clock.h @@ -14,6 +14,7 @@ unsigned long pxa_get_uartclk(void); unsigned long pxa_get_mmcclk(void); unsigned long pxa_get_lcdclk(void); +unsigned long pxa_get_nandclk(void); unsigned long pxa_get_pwmclk(void); #endif /* !__MACH_CLOCK_H */ diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index c5f40d7c08..902d11ddfc 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -13,7 +13,7 @@ #ifdef CONFIG_ARCH_PXA2XX #define cpu_is_pxa2xx() (1) #else -#define cpi_is_pxa2xx() (0) +#define cpu_is_pxa2xx() (0) #endif #ifdef CONFIG_ARCH_PXA25X @@ -28,6 +28,22 @@ #define cpu_is_pxa27x() (0) #endif +#ifdef CONFIG_ARCH_PXA3XX +#define cpu_is_pxa3xx() (1) +# ifdef CONFIG_ARCH_PXA320 +# define cpu_is_pxa320() (1) +# else +# define cpu_is_pxa320() (0) +# endif +# ifdef CONFIG_ARCH_PXA310 +# define cpu_is_pxa310() (1) +# else +# define cpu_is_pxa310() (0) +# endif +#else +#define cpu_is_pxa3xx() (0) +#endif + #ifdef __ASSEMBLY__ #define __REG(x) (x) #endif diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h new file mode 100644 index 0000000000..7bdd44db13 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h @@ -0,0 +1,25 @@ +#ifndef __ASM_ARCH_MFP_PXA3XX_H +#define __ASM_ARCH_MFP_PXA3XX_H + +#include <plat/mfp.h> + +#define MFPR_BASE (0x40e10000) + +/* NOTE: usage of these two functions is not recommended, + * use pxa3xx_mfp_config() instead. + */ +static inline unsigned long pxa3xx_mfp_read(int mfp) +{ + return mfp_read(mfp); +} + +static inline void pxa3xx_mfp_write(int mfp, unsigned long val) +{ + mfp_write(mfp, val); +} + +static inline void pxa3xx_mfp_config(unsigned long *mfp_cfg, int num) +{ + mfp_config(mfp_cfg, num); +} +#endif /* __ASM_ARCH_MFP_PXA3XX_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h index c32d2ae704..9bcb5efb7f 100644 --- a/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h @@ -24,8 +24,12 @@ # include <mach/pxa2xx-regs.h> #endif -#ifdef CONFIG_ARCH_PXA27X +#if defined(CONFIG_ARCH_PXA27X) # include <mach/pxa27x-regs.h> +#elif defined(CONFIG_ARCH_PXA3XX) +# include <mach/pxa3xx-regs.h> +#elif defined(CONFIG_ARCH_PXA25X) +# include <mach/pxa25x-regs.h> #else # error "unknown PXA soc type" #endif diff --git a/arch/arm/mach-pxa/include/mach/pxa25x-regs.h b/arch/arm/mach-pxa/include/mach/pxa25x-regs.h new file mode 100644 index 0000000000..a7f16bd418 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa25x-regs.h @@ -0,0 +1,6 @@ +#ifndef __MACH_PXA25X_REGS +#define __MACH_PXA25X_REGS + +/* this file intentionally left blank */ + +#endif /* !__MACH_PXA25X_REGS */ diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index b43648e3c4..dc7704eda2 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h @@ -53,6 +53,7 @@ #define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ #define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ #define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ +#define FLYCNFG __REG(0x48000020) /* Flycnfg Register */ #define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ #define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ #define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h new file mode 100644 index 0000000000..373711d92f --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h @@ -0,0 +1,224 @@ +/* + * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h + * + * PXA3xx specific register definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_PXA3XX_REGS +#define __MACH_PXA3XX_REGS + +#include <mach/hardware.h> + +/* + * Oscillator Configuration Register (OSCC) + */ +#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ + +#define OSCC_PEN (1 << 11) /* 13MHz POUT */ + + +/* + * Service Power Management Unit (MPMU) + */ +#define PMCR __REG(0x40F50000) /* Power Manager Control Register */ +#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ +#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ +#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ +#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ +#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ +#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ +#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ +#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ +#define PCMD(x) __REG(0x40F50110 + ((x) << 2)) + +/* + * Slave Power Management Unit + */ +#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */ +#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ +#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */ +#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */ +#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */ +#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */ +#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */ +#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */ +#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */ +#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */ +#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */ +#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */ +#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */ +#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */ + +/* + * Application Subsystem Configuration bits. + */ +#define ASCR_RDH (1 << 31) +#define ASCR_D1S (1 << 2) +#define ASCR_D2S (1 << 1) +#define ASCR_D3S (1 << 0) + +/* + * Application Reset Status bits. + */ +#define ARSR_GPR (1 << 3) +#define ARSR_LPMR (1 << 2) +#define ARSR_WDT (1 << 1) +#define ARSR_HWR (1 << 0) + +/* + * Application Subsystem Wake-Up bits. + */ +#define ADXER_WRTC (1 << 31) /* RTC */ +#define ADXER_WOST (1 << 30) /* OS Timer */ +#define ADXER_WTSI (1 << 29) /* Touchscreen */ +#define ADXER_WUSBH (1 << 28) /* USB host */ +#define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */ +#define ADXER_WMSL0 (1 << 24) /* MSL port 0*/ +#define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */ +#define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */ +#define ADXER_WKP (1 << 21) /* Keypad */ +#define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */ +#define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */ +#define ADXER_WOTG (1 << 16) /* USBOTG input */ +#define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */ +#define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */ +#define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */ +#define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */ +#define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */ +#define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */ +#define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */ +#define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */ +#define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */ +#define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */ +#define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */ +#define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */ +#define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */ +#define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */ +#define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */ +#define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */ + +/* + * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320. + */ +#define ADXR_L2 (1 << 8) +#define ADXR_R5 (1 << 5) +#define ADXR_R4 (1 << 4) +#define ADXR_R3 (1 << 3) +#define ADXR_R2 (1 << 2) +#define ADXR_R1 (1 << 1) +#define ADXR_R0 (1 << 0) + +/* + * Values for PWRMODE CP15 register + */ +#define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */ +#define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */ +#define PXA3xx_PM_S0D2C2 0x03 /* aka standby */ +#define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */ +#define PXA3xx_PM_S0D0C1 0x01 + +/* + * Application Subsystem Clock + */ +#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ +#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ +#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ +#define CKENA __REG(0x4134000C) /* A Clock Enable Register */ +#define CKENB __REG(0x41340010) /* B Clock Enable Register */ +#define CKENC __REG(0x41340024) /* C Clock Enable Register */ +#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ + +#define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ +#define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */ +#define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */ +#define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */ +#define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */ + +#define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */ +#define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */ +#define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */ +#define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */ +#define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */ +#define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */ +#define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */ + +#define ACCR_SMCFS(x) (((x) & 0x7) << 23) +#define ACCR_SFLFS(x) (((x) & 0x3) << 18) +#define ACCR_XSPCLK(x) (((x) & 0x3) << 16) +#define ACCR_HSS(x) (((x) & 0x3) << 14) +#define ACCR_DMCFS(x) (((x) & 0x3) << 12) +#define ACCR_XN(x) (((x) & 0x7) << 8) +#define ACCR_XL(x) ((x) & 0x1f) + +/* + * Clock Enable Bit + */ +#define CKEN_LCD 1 /* < LCD Clock Enable */ +#define CKEN_USBH 2 /* < USB host clock enable */ +#define CKEN_CAMERA 3 /* < Camera interface clock enable */ +#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ +#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ +#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ +#define CKEN_SMC 9 /* < Static Memory Controller clock enable */ +#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ +#define CKEN_BOOT 11 /* < Boot rom clock enable */ +#define CKEN_MMC1 12 /* < MMC1 Clock enable */ +#define CKEN_MMC2 13 /* < MMC2 clock enable */ +#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ +#define CKEN_CIR 15 /* < Consumer IR Clock Enable */ +#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ +#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ +#define CKEN_TPM 19 /* < TPM clock enable */ +#define CKEN_UDC 20 /* < UDC clock enable */ +#define CKEN_BTUART 21 /* < BTUART clock enable */ +#define CKEN_FFUART 22 /* < FFUART clock enable */ +#define CKEN_STUART 23 /* < STUART clock enable */ +#define CKEN_AC97 24 /* < AC97 clock enable */ +#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ +#define CKEN_SSP1 26 /* < SSP1 clock enable */ +#define CKEN_SSP2 27 /* < SSP2 clock enable */ +#define CKEN_SSP3 28 /* < SSP3 clock enable */ +#define CKEN_SSP4 29 /* < SSP4 clock enable */ +#define CKEN_MSL0 30 /* < MSL0 clock enable */ +#define CKEN_PWM0 32 /* < PWM[0] clock enable */ +#define CKEN_PWM1 33 /* < PWM[1] clock enable */ +#define CKEN_I2C 36 /* < I2C clock enable */ +#define CKEN_INTC 38 /* < Interrupt controller clock enable */ +#define CKEN_GPIO 39 /* < GPIO clock enable */ +#define CKEN_1WIRE 40 /* < 1-wire clock enable */ +#define CKEN_HSIO2 41 /* < HSIO2 clock enable */ +#define CKEN_MINI_IM 48 /* < Mini-IM */ +#define CKEN_MINI_LCD 49 /* < Mini LCD */ + +#define CKEN_MMC3 5 /* < MMC3 Clock Enable */ +#define CKEN_MVED 43 /* < MVED clock enable */ + +/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ +#define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */ +#define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */ + +/* + * Static Memory Controller + */ +#define MSC0 __REG(0x4a000008) /* Static Memory Control 0 */ +#define MSC1 __REG(0x4a00000c) /* Static Memory Control 1 */ +#define MECR __REG(0x4a000014) /* Expansion Memory Configuration */ +#define SXCNFG __REG(0x4a00001c) /* Synchronous Static Memory Control */ +#define MCMEM0 __REG(0x4a000028) /* Expansion Memory Timing */ +#define MCATT0 __REG(0x4a000030) /* Expansion Memory Timing */ +#define MCIO0 __REG(0x4a000038) /* Expansion Memory Timing */ +#define MEMCLKCFG __REG(0x4a000068) /* Clock configuration */ +#define CSADRCFG0 __REG(0x4a000080) /* CS0 address configuration */ +#define CSADRCFG1 __REG(0x4a000084) /* CS1 address configuration */ +#define CSADRCFG2 __REG(0x4a000088) /* CS2 address configuration */ +#define CSADRCFG3 __REG(0x4a00008c) /* CS3 address configuration */ +#define CSADRCFGP __REG(0x4a000090) /* CSP address configuration */ +#define CSMSADRCFG __REG(0x4a0000a0) /* CSP address configuration */ + +#endif /* !__MACH_PXA3XX_REGS */ diff --git a/arch/arm/mach-pxa/include/plat/mfp.h b/arch/arm/mach-pxa/include/plat/mfp.h index 755b02062b..aedb956cd3 100644 --- a/arch/arm/mach-pxa/include/plat/mfp.h +++ b/arch/arm/mach-pxa/include/plat/mfp.h @@ -416,7 +416,7 @@ typedef unsigned long mfp_cfg_t; ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\ (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm)) -#if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP) +#if defined(CONFIG_ARCH_PXA3XX) /* * each MFP pin will have a MFPR register, since the offset of the * register varies between processors, the processor specific code @@ -449,7 +449,7 @@ struct mfp_addr_map { #define MFP_ADDR_END { MFP_PIN_INVALID, 0 } -void __init mfp_init_base(unsigned long mfpr_base); +void __init mfp_init_base(void __iomem *mfpr_base); void __init mfp_init_addr(struct mfp_addr_map *map); /* @@ -463,6 +463,7 @@ void mfp_write(int mfp, unsigned long mfpr_val); void mfp_config(unsigned long *mfp_cfgs, int num); void mfp_config_run(void); void mfp_config_lpm(void); -#endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */ +void mfp_init(void); +#endif /* CONFIG_ARCH_PXA3XX */ #endif /* __ASM_PLAT_MFP_H */ diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index 4f393c4d47..2456cef936 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -169,8 +169,10 @@ static int __init pxa2xx_mfp_init(void) if (!cpu_is_pxa2xx()) return 0; - if (cpu_is_pxa25x()) + if (cpu_is_pxa25x()) { + pxa_init_gpio(0, 84); pxa25x_mfp_init(); + } if (cpu_is_pxa27x()) { pxa_init_gpio(2, 120); diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c new file mode 100644 index 0000000000..df4922453d --- /dev/null +++ b/arch/arm/mach-pxa/mfp-pxa3xx.c @@ -0,0 +1,338 @@ +/* + * linux/arch/arm/plat-pxa/mfp.c + * + * Multi-Function Pin Support + * + * Copyright (C) 2007 Marvell Internation Ltd. + * + * 2007-08-21: eric miao <eric.miao@marvell.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <mach/hardware.h> +#include <mach/mfp-pxa3xx.h> +#include <plat/mfp.h> + +#define MFPR_SIZE (PAGE_SIZE) + +/* MFPR register bit definitions */ +#define MFPR_PULL_SEL (0x1 << 15) +#define MFPR_PULLUP_EN (0x1 << 14) +#define MFPR_PULLDOWN_EN (0x1 << 13) +#define MFPR_SLEEP_SEL (0x1 << 9) +#define MFPR_SLEEP_OE_N (0x1 << 7) +#define MFPR_EDGE_CLEAR (0x1 << 6) +#define MFPR_EDGE_FALL_EN (0x1 << 5) +#define MFPR_EDGE_RISE_EN (0x1 << 4) + +#define MFPR_SLEEP_DATA(x) ((x) << 8) +#define MFPR_DRIVE(x) (((x) & 0x7) << 10) +#define MFPR_AF_SEL(x) (((x) & 0x7) << 0) + +#define MFPR_EDGE_NONE (0) +#define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN) +#define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN) +#define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL) + +/* + * Table that determines the low power modes outputs, with actual settings + * used in parentheses for don't-care values. Except for the float output, + * the configured driven and pulled levels match, so if there is a need for + * non-LPM pulled output, the same configuration could probably be used. + * + * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel + * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) + * + * Input 0 X(0) X(0) X(0) 0 + * Drive 0 0 0 0 X(1) 0 + * Drive 1 0 1 X(1) 0 0 + * Pull hi (1) 1 X(1) 1 0 0 + * Pull lo (0) 1 X(0) 0 1 0 + * Z (float) 1 X(0) 0 0 0 + */ +#define MFPR_LPM_INPUT (0) +#define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN) +#define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN) +#define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N) +#define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N) +#define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N) +#define MFPR_LPM_MASK (0xe080) + +/* + * The pullup and pulldown state of the MFP pin at run mode is by default + * determined by the selected alternate function. In case that some buggy + * devices need to override this default behavior, the definitions below + * indicates the setting of corresponding MFPR bits + * + * Definition pull_sel pullup_en pulldown_en + * MFPR_PULL_NONE 0 0 0 + * MFPR_PULL_LOW 1 0 1 + * MFPR_PULL_HIGH 1 1 0 + * MFPR_PULL_BOTH 1 1 1 + * MFPR_PULL_FLOAT 1 0 0 + */ +#define MFPR_PULL_NONE (0) +#define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN) +#define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN) +#define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN) +#define MFPR_PULL_FLOAT (MFPR_PULL_SEL) + +/* mfp_spin_lock is used to ensure that MFP register configuration + * (most likely a read-modify-write operation) is atomic, and that + * mfp_table[] is consistent + */ +static void __iomem *mfpr_mmio_base; + +struct mfp_pin { + unsigned long config; /* -1 for not configured */ + unsigned long mfpr_off; /* MFPRxx Register offset */ + unsigned long mfpr_run; /* Run-Mode Register Value */ + unsigned long mfpr_lpm; /* Low Power Mode Register Value */ +}; + +static struct mfp_pin mfp_table[MFP_PIN_MAX]; + +/* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */ +static const unsigned long mfpr_lpm[] = { + MFPR_LPM_INPUT, + MFPR_LPM_DRIVE_LOW, + MFPR_LPM_DRIVE_HIGH, + MFPR_LPM_PULL_LOW, + MFPR_LPM_PULL_HIGH, + MFPR_LPM_FLOAT, + MFPR_LPM_INPUT, +}; + +/* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */ +static const unsigned long mfpr_pull[] = { + MFPR_PULL_NONE, + MFPR_PULL_LOW, + MFPR_PULL_HIGH, + MFPR_PULL_BOTH, + MFPR_PULL_FLOAT, +}; + +/* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */ +static const unsigned long mfpr_edge[] = { + MFPR_EDGE_NONE, + MFPR_EDGE_RISE, + MFPR_EDGE_FALL, + MFPR_EDGE_BOTH, +}; + +#define mfpr_readl(off) \ + __raw_readl(mfpr_mmio_base + (off)) + +#define mfpr_writel(off, val) \ + __raw_writel(val, mfpr_mmio_base + (off)) + +#define mfp_configured(p) ((p)->config != -1) + +/* + * perform a read-back of any valid MFPR register to make sure the + * previous writings are finished + */ +static unsigned long mfpr_off_readback; +#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + mfpr_off_readback) + +static inline void __mfp_config_run(struct mfp_pin *p) +{ + if (mfp_configured(p)) + mfpr_writel(p->mfpr_off, p->mfpr_run); +} + +static inline void __mfp_config_lpm(struct mfp_pin *p) +{ + if (mfp_configured(p)) { + unsigned long mfpr_clr = + (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR; + + if (mfpr_clr != p->mfpr_run) + mfpr_writel(p->mfpr_off, mfpr_clr); + if (p->mfpr_lpm != mfpr_clr) + mfpr_writel(p->mfpr_off, p->mfpr_lpm); + } +} + +void mfp_config(unsigned long *mfp_cfgs, int num) +{ + int i; + + for (i = 0; i < num; i++, mfp_cfgs++) { + unsigned long tmp, c = *mfp_cfgs; + struct mfp_pin *p; + int pin, af, drv, lpm, edge, pull; + + pin = MFP_PIN(c); + BUG_ON(pin >= MFP_PIN_MAX); + p = &mfp_table[pin]; + + af = MFP_AF(c); + drv = MFP_DS(c); + lpm = MFP_LPM_STATE(c); + edge = MFP_LPM_EDGE(c); + pull = MFP_PULL(c); + + /* run-mode pull settings will conflict with MFPR bits of + * low power mode state, calculate mfpr_run and mfpr_lpm + * individually if pull != MFP_PULL_NONE + */ + tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv); + + if (likely(pull == MFP_PULL_NONE)) { + p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge]; + p->mfpr_lpm = p->mfpr_run; + } else { + p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge]; + p->mfpr_run = tmp | mfpr_pull[pull]; + } + + p->config = c; __mfp_config_run(p); + } + + mfpr_sync(); +} + +unsigned long mfp_read(int mfp) +{ + unsigned long val; + + BUG_ON(mfp < 0 || mfp >= MFP_PIN_MAX); + + val = mfpr_readl(mfp_table[mfp].mfpr_off); + return val; +} + +void mfp_write(int mfp, unsigned long val) +{ + BUG_ON(mfp < 0 || mfp >= MFP_PIN_MAX); + + mfpr_writel(mfp_table[mfp].mfpr_off, val); + mfpr_sync(); +} + +void __init mfp_init_base(void __iomem *mfpr_base) +{ + int i; + + /* initialize the table with default - unconfigured */ + for (i = 0; i < ARRAY_SIZE(mfp_table); i++) + mfp_table[i].config = -1; + + mfpr_mmio_base = mfpr_base; +} + +void __init mfp_init_addr(struct mfp_addr_map *map) +{ + struct mfp_addr_map *p; + unsigned long offset; + int i; + + /* mfp offset for readback */ + mfpr_off_readback = map[0].offset; + + for (p = map; p->start != MFP_PIN_INVALID; p++) { + offset = p->offset; + i = p->start; + + do { + mfp_table[i].mfpr_off = offset; + mfp_table[i].mfpr_run = 0; + mfp_table[i].mfpr_lpm = 0; + offset += 4; i++; + } while ((i <= p->end) && (p->end != -1)); + } +} + +void mfp_config_lpm(void) +{ + struct mfp_pin *p = &mfp_table[0]; + int pin; + + for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++) + __mfp_config_lpm(p); +} + +void mfp_config_run(void) +{ + struct mfp_pin *p = &mfp_table[0]; + int pin; + + for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++) + __mfp_config_run(p); +} + +static struct mfp_addr_map pxa300_mfp_addr_map[] __initdata = { + + MFP_ADDR_X(GPIO0, GPIO2, 0x00b4), + MFP_ADDR_X(GPIO3, GPIO26, 0x027c), + MFP_ADDR_X(GPIO27, GPIO98, 0x0400), + MFP_ADDR_X(GPIO99, GPIO127, 0x0600), + MFP_ADDR_X(GPIO0_2, GPIO1_2, 0x0674), + MFP_ADDR_X(GPIO2_2, GPIO6_2, 0x02dc), + + MFP_ADDR(nBE0, 0x0204), + MFP_ADDR(nBE1, 0x0208), + + MFP_ADDR(nLUA, 0x0244), + MFP_ADDR(nLLA, 0x0254), + + MFP_ADDR(DF_CLE_nOE, 0x0240), + MFP_ADDR(DF_nRE_nOE, 0x0200), + MFP_ADDR(DF_ALE_nWE, 0x020C), + MFP_ADDR(DF_INT_RnB, 0x00C8), + MFP_ADDR(DF_nCS0, 0x0248), + MFP_ADDR(DF_nCS1, 0x0278), + MFP_ADDR(DF_nWE, 0x00CC), + + MFP_ADDR(DF_ADDR0, 0x0210), + MFP_ADDR(DF_ADDR1, 0x0214), + MFP_ADDR(DF_ADDR2, 0x0218), + MFP_ADDR(DF_ADDR3, 0x021C), + + MFP_ADDR(DF_IO0, 0x0220), + MFP_ADDR(DF_IO1, 0x0228), + MFP_ADDR(DF_IO2, 0x0230), + MFP_ADDR(DF_IO3, 0x0238), + MFP_ADDR(DF_IO4, 0x0258), + MFP_ADDR(DF_IO5, 0x0260), + MFP_ADDR(DF_IO6, 0x0268), + MFP_ADDR(DF_IO7, 0x0270), + MFP_ADDR(DF_IO8, 0x0224), + MFP_ADDR(DF_IO9, 0x022C), + MFP_ADDR(DF_IO10, 0x0234), + MFP_ADDR(DF_IO11, 0x023C), + MFP_ADDR(DF_IO12, 0x025C), + MFP_ADDR(DF_IO13, 0x0264), + MFP_ADDR(DF_IO14, 0x026C), + MFP_ADDR(DF_IO15, 0x0274), + + MFP_ADDR_END, +}; + +/* override pxa300 MFP register addresses */ +static struct mfp_addr_map pxa310_mfp_addr_map[] __initdata = { + MFP_ADDR_X(GPIO30, GPIO98, 0x0418), + MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C), + + MFP_ADDR(ULPI_STP, 0x040C), + MFP_ADDR(ULPI_NXT, 0x0410), + MFP_ADDR(ULPI_DIR, 0x0414), + + MFP_ADDR_END, +}; + +void mfp_init(void) +{ + mfp_init_base((void __iomem *)MFPR_BASE); + mfp_init_addr(pxa300_mfp_addr_map); + if (cpu_is_pxa310()) + mfp_init_addr(pxa310_mfp_addr_map); +} diff --git a/arch/arm/mach-pxa/reset_source.c b/arch/arm/mach-pxa/pxa2xx.c index a90584b1a6..b712b388c8 100644 --- a/arch/arm/mach-pxa/reset_source.c +++ b/arch/arm/mach-pxa/pxa2xx.c @@ -15,8 +15,11 @@ #include <common.h> #include <init.h> #include <reset_source.h> +#include <mach/hardware.h> #include <mach/pxa-regs.h> +extern void pxa_suspend(int mode); + static int pxa_detect_reset_source(void) { u32 reg = RCSR; @@ -38,4 +41,19 @@ static int pxa_detect_reset_source(void) return 0; } +void pxa_clear_reset_source(void) +{ + RCSR = RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR; +} + device_initcall(pxa_detect_reset_source); + +void __noreturn poweroff(void) +{ + shutdown_barebox(); + + /* Clear last reset source */ + pxa_clear_reset_source(); + pxa_suspend(PWRMODE_DEEPSLEEP); + unreachable(); +} diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c new file mode 100644 index 0000000000..86ca63b160 --- /dev/null +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2015 Robert Jarzmik <robert.jarzmik@free.fr> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <init.h> +#include <reset_source.h> +#include <mach/hardware.h> +#include <mach/pxa-regs.h> + +extern void pxa3xx_suspend(int mode); + +static int pxa_detect_reset_source(void) +{ + u32 reg = ARSR; + + /* + * Order is important, as many bits can be set together + */ + if (reg & ARSR_GPR) + reset_source_set(RESET_RST); + else if (reg & ARSR_WDT) + reset_source_set(RESET_WDG); + else if (reg & ARSR_HWR) + reset_source_set(RESET_POR); + else if (reg & ARSR_LPMR) + reset_source_set(RESET_WKE); + else + reset_source_set(RESET_UKWN); + + return 0; +} + +void pxa_clear_reset_source(void) +{ + ARSR = ARSR_GPR | ARSR_LPMR | ARSR_WDT | ARSR_HWR; +} + +device_initcall(pxa_detect_reset_source); + +void __noreturn poweroff(void) +{ + shutdown_barebox(); + + /* Clear last reset source */ + pxa_clear_reset_source(); + pxa3xx_suspend(PXA3xx_PM_S3D4C4); + unreachable(); +} diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index 881033da21..1c678158c9 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S @@ -21,7 +21,7 @@ #define UNCACHED_PHYS_0 0 .text -#ifdef CONFIG_ARCH_PXA27X +#if (defined CONFIG_ARCH_PXA27X || defined CONFIG_ARCH_PXA25X) /* * pxa27x_finish_suspend() * @@ -79,3 +79,10 @@ pxa_cpu_do_suspend: @ enter sleep mode mcr p14, 0, r1, c7, c0, 0 @ PWRMODE 20: b 20b @ loop waiting for sleep + + /* + * pxa3xx_finish_suspend() - forces CPU into sleep state + */ +ENTRY(pxa3xx_suspend) + mcr p14, 0, r0, c7, c0, 0 @ enter sleep +20: b 20b @ waiting for sleep diff --git a/arch/arm/mach-pxa/speed-pxa25x.c b/arch/arm/mach-pxa/speed-pxa25x.c new file mode 100644 index 0000000000..69143431e4 --- /dev/null +++ b/arch/arm/mach-pxa/speed-pxa25x.c @@ -0,0 +1,54 @@ +/* + * clock.h - implementation of the PXA clock functions + * + * Copyright (C) 2014 Robert Jarzmik <robert.jarzmik@free.fr> + * + * This file is released under the GPLv2 + * + */ + +#include <common.h> +#include <mach/clock.h> +#include <mach/pxa-regs.h> + +/* Crystal clock: 13MHz */ +#define BASE_CLK 13000000 + +unsigned long pxa_get_uartclk(void) +{ + return 14857000; +} + +unsigned long pxa_get_mmcclk(void) +{ + return 19500000; +} + +/* + * Return the current LCD clock frequency in units of 10kHz as + */ +static unsigned int pxa_get_lcdclk_10khz(void) +{ + unsigned long ccsr; + unsigned int l, L, k, K; + + ccsr = CCSR; + + l = ccsr & 0x1f; + k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4; + + L = l * BASE_CLK; + K = L / k; + + return (K / 10000); +} + +unsigned long pxa_get_lcdclk(void) +{ + return pxa_get_lcdclk_10khz() * 10000; +} + +unsigned long pxa_get_pwmclk(void) +{ + return BASE_CLK; +} diff --git a/arch/arm/mach-pxa/speed-pxa3xx.c b/arch/arm/mach-pxa/speed-pxa3xx.c new file mode 100644 index 0000000000..6a08ea78f0 --- /dev/null +++ b/arch/arm/mach-pxa/speed-pxa3xx.c @@ -0,0 +1,33 @@ +/* + * clock.h - implementation of the PXA clock functions + * + * Copyright (C) 2014 by Robert Jarzmik <robert.jarzmik@free.fr> + * + * This file is released under the GPLv2 + * + */ + +#include <common.h> +#include <mach/clock.h> +#include <mach/pxa-regs.h> + +/* Crystal clock: 13MHz */ +#define BASE_CLK 13000000 + +unsigned long pxa_get_uartclk(void) +{ + return 14857000; +} + +unsigned long pxa_get_pwmclk(void) +{ + return BASE_CLK; +} + +unsigned long pxa_get_nandclk(void) +{ + if (cpu_is_pxa320()) + return 104000000; + else + return 156000000; +} diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index c345847d8f..a75540b4ec 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -97,6 +97,13 @@ config NAND_ORION help Support for the Orion NAND controller, present in Kirkwood SoCs. +config NAND_MRVL_NFC + bool + prompt "Marvell NAND driver" + depends on ARCH_PXA3XX + help + Support for the PXA3xx NAND controller, present in pxa3xx SoCs. + config NAND_ATMEL bool prompt "Atmel (AT91SAM9xxx) NAND driver" diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 02dacde962..a0b31989ff 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_NAND_IMX) += nand_imx.o obj-$(CONFIG_NAND_IMX_BBM) += nand_imx_bbm.o obj-$(CONFIG_NAND_OMAP_GPMC) += nand_omap_gpmc.o nand_omap_bch_decoder.o obj-$(CONFIG_NAND_ORION) += nand_orion.o +obj-$(CONFIG_NAND_MRVL_NFC) += nand_mrvl_nfc.o obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o obj-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o pbl-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c new file mode 100644 index 0000000000..258ff75953 --- /dev/null +++ b/drivers/mtd/nand/nand_mrvl_nfc.c @@ -0,0 +1,1020 @@ +/* + * drivers/mtd/nand/mrvl_nand.c + * + * Copyright © 2005 Intel Corporation + * Copyright © 2006 Marvell International Ltd. + * Copyright (C) 2014 Robert Jarzmik + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * See Documentation/mtd/nand/pxa3xx-nand.txt for more details. + */ +#include <common.h> + +#include <driver.h> +#include <dma/apbh-dma.h> +#include <errno.h> +#include <clock.h> +#include <init.h> +#include <io.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/types.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <mach/clock.h> +#include <malloc.h> +#include <of_mtd.h> +#include <stmp-device.h> + +#include <platform_data/mtd-nand-mrvl.h> + +#define CHIP_DELAY_TIMEOUT_US 500000 +#define PAGE_CHUNK_SIZE (2048) + +/* + * Define a buffer size for the initial command that detects the flash device: + * STATUS, READID and PARAM. The largest of these is the PARAM command, + * needing 256 bytes. + */ +#define INIT_BUFFER_SIZE 256 + +/* registers and bit definitions */ +#define NDCR (0x00) /* Control register */ +#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */ +#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */ +#define NDSR (0x14) /* Status Register */ +#define NDPCR (0x18) /* Page Count Register */ +#define NDBDR0 (0x1C) /* Bad Block Register 0 */ +#define NDBDR1 (0x20) /* Bad Block Register 1 */ +#define NDECCCTRL (0x28) /* ECC control */ +#define NDDB (0x40) /* Data Buffer */ +#define NDCB0 (0x48) /* Command Buffer0 */ +#define NDCB1 (0x4C) /* Command Buffer1 */ +#define NDCB2 (0x50) /* Command Buffer2 */ + +#define NDCR_SPARE_EN (0x1 << 31) +#define NDCR_ECC_EN (0x1 << 30) +#define NDCR_DMA_EN (0x1 << 29) +#define NDCR_ND_RUN (0x1 << 28) +#define NDCR_DWIDTH_C (0x1 << 27) +#define NDCR_DWIDTH_M (0x1 << 26) +#define NDCR_PAGE_SZ (0x1 << 24) +#define NDCR_NCSX (0x1 << 23) +#define NDCR_ND_MODE (0x3 << 21) +#define NDCR_NAND_MODE (0x0) +#define NDCR_CLR_PG_CNT (0x1 << 20) +#define NDCR_STOP_ON_UNCOR (0x1 << 19) +#define NDCR_RD_ID_CNT_MASK (0x7 << 16) +#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK) + +#define NDCR_RA_START (0x1 << 15) +#define NDCR_PG_PER_BLK (0x1 << 14) +#define NDCR_ND_ARB_EN (0x1 << 12) +#define NDCR_INT_MASK (0xFFF) + +#define NDSR_MASK (0xfff) +#define NDSR_ERR_CNT_OFF (16) +#define NDSR_ERR_CNT_MASK (0x1f) +#define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK) +#define NDSR_RDY (0x1 << 12) +#define NDSR_FLASH_RDY (0x1 << 11) +#define NDSR_CS0_PAGED (0x1 << 10) +#define NDSR_CS1_PAGED (0x1 << 9) +#define NDSR_CS0_CMDD (0x1 << 8) +#define NDSR_CS1_CMDD (0x1 << 7) +#define NDSR_CS0_BBD (0x1 << 6) +#define NDSR_CS1_BBD (0x1 << 5) +#define NDSR_UNCORERR (0x1 << 4) +#define NDSR_CORERR (0x1 << 3) +#define NDSR_WRDREQ (0x1 << 2) +#define NDSR_RDDREQ (0x1 << 1) +#define NDSR_WRCMDREQ (0x1) + +#define NDCB0_LEN_OVRD (0x1 << 28) +#define NDCB0_ST_ROW_EN (0x1 << 26) +#define NDCB0_AUTO_RS (0x1 << 25) +#define NDCB0_CSEL (0x1 << 24) +#define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29) +#define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK) +#define NDCB0_CMD_TYPE_MASK (0x7 << 21) +#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK) +#define NDCB0_NC (0x1 << 20) +#define NDCB0_DBC (0x1 << 19) +#define NDCB0_ADDR_CYC_MASK (0x7 << 16) +#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK) +#define NDCB0_CMD2_MASK (0xff << 8) +#define NDCB0_CMD1_MASK (0xff) +#define NDCB0_ADDR_CYC_SHIFT (16) + +#define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */ +#define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */ +#define EXT_CMD_TYPE_READ 4 /* Read */ +#define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */ +#define EXT_CMD_TYPE_FINAL 3 /* Final command */ +#define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */ +#define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */ + +/* macros for registers read/write */ +#define nand_writel(host, off, val) \ + _nand_writel(__func__, __LINE__, (host), (off), (val)) + +#define nand_writesl(host, off, buf, nbbytes) \ + writesl((host)->mmio_base + (off), buf, nbbytes) + +#define nand_readl(host, off) \ + _nand_readl(__func__, __LINE__, (host), (off)) + +#define nand_readsl(host, off, buf, nbbytes) \ + readsl((host)->mmio_base + (off), buf, nbbytes) + +struct mrvl_nand_host { + struct mtd_info mtd; + struct nand_chip chip; + struct mtd_partition *parts; + struct device_d *dev; + + /* calculated from mrvl_nand_flash data */ + unsigned int col_addr_cycles; + unsigned int row_addr_cycles; + size_t read_id_bytes; + + void __iomem *mmio_base; + + unsigned int buf_start; + unsigned int buf_count; + unsigned int buf_size; + + unsigned char *data_buff; + + int keep_config; + int ecc_strength; + int ecc_step; + + int cs; /* selected chip 0/1 */ + int use_ecc; /* use HW ECC ? */ + int use_spare; /* use spare ? */ + int flash_bbt; + + unsigned int data_size; /* data to be read from FIFO */ + unsigned int chunk_size; /* split commands chunk size */ + unsigned int oob_size; + unsigned int spare_size; + unsigned int ecc_size; + unsigned int max_bitflips; + int cmd_ongoing; + + /* cached register value */ + uint32_t reg_ndcr; + uint32_t ndtr0cs0_chip0; + uint32_t ndtr1cs0_chip0; + uint32_t ndtr0cs0_chip1; + uint32_t ndtr1cs0_chip1; + + /* generated NDCBx register values */ + uint32_t ndcb0; + uint32_t ndcb1; + uint32_t ndcb2; + uint32_t ndcb3; +}; + +static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' }; +static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION, + .offs = 8, + .len = 6, + .veroffs = 14, + .maxblocks = 8, /* Last 8 blocks in each chip */ + .pattern = bbt_pattern, +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION, + .offs = 8, + .len = 6, + .veroffs = 14, + .maxblocks = 8, /* Last 8 blocks in each chip */ + .pattern = bbt_mirror_pattern, +}; + +static struct nand_ecclayout ecc_layout_512B_hwecc = { + .eccbytes = 6, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15 }, + .oobfree = { {0, 8} } +}; + +static struct nand_ecclayout ecc_layout_2KB_hwecc = { + .eccbytes = 24, + .eccpos = { + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63 }, + .oobfree = { {0, 40} } +}; + +#define NDTR0_tCH(c) (min((c), 7) << 19) +#define NDTR0_tCS(c) (min((c), 7) << 16) +#define NDTR0_tWH(c) (min((c), 7) << 11) +#define NDTR0_tWP(c) (min((c), 7) << 8) +#define NDTR0_tRH(c) (min((c), 7) << 3) +#define NDTR0_tRP(c) (min((c), 7) << 0) + +#define NDTR1_tR(c) (min((c), 65535) << 16) +#define NDTR1_tWHR(c) (min((c), 15) << 4) +#define NDTR1_tAR(c) (min((c), 15) << 0) + +#define mtd_info_to_host(mtd) ((struct mrvl_nand_host *) \ + (((struct nand_chip *)((mtd)->priv))->priv)) + +static struct of_device_id mrvl_nand_dt_ids[] = { + { + .compatible = "marvell,pxa3xx-nand", + }, + {} +}; + +/* convert nano-seconds to nand flash controller clock cycles */ +static int ns2cycle(int ns, unsigned long clk_rate) +{ + int clk_mhz = clk_rate / 1000000; + + return roundup(ns * clk_mhz, 1000) / 1000; +} + +static volatile u32 _nand_readl(const char *func, const int line, + struct mrvl_nand_host *host, int off) +{ + volatile u32 val = readl((host)->mmio_base + (off)); + + dev_vdbg(host->dev, "\treadl %s:%d reg=0x%08x => 0x%08x\n", + func, line, off, val); + return val; +} + +static void _nand_writel(const char *func, const int line, + struct mrvl_nand_host *host, int off, u32 val) +{ + dev_vdbg(host->dev, "\twritel %s:%d reg=0x%08x val=0x%08x\n", + func, line, off, val); + writel(val, (host)->mmio_base + off); +} + +static struct mrvl_nand_timing timings[] = { + { 0x46ec, 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, + { 0xdaec, 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, + { 0xd7ec, 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, + { 0xa12c, 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, + { 0xb12c, 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, + { 0xdc2c, 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, + { 0xcc2c, 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, + { 0xba20, 10, 35, 15, 25, 15, 25, 25000, 60, 10, }, + { 0x0000, 40, 80, 60, 100, 80, 100, 90000, 400, 40, }, +}; + +static void mrvl_nand_set_timing(struct mrvl_nand_host *host, bool use_default) +{ + struct mtd_info *mtd = &host->mtd; + struct mrvl_nand_timing *t; + uint32_t ndtr0, ndtr1; + u16 id; + unsigned long nand_clk = pxa_get_nandclk(); + + if (use_default) { + id = 0; + } else { + host->chip.cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + host->chip.read_buf(mtd, (unsigned char *)&id, sizeof(id)); + } + for (t = &timings[0]; t->id; t++) + if (t->id == id) + break; + ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) | + NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) | + NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) | + NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) | + NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) | + NDTR0_tRP(ns2cycle(t->tRP, nand_clk)); + + ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | + NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) | + NDTR1_tAR(ns2cycle(t->tAR, nand_clk)); + nand_writel(host, NDTR0CS0, ndtr0); + nand_writel(host, NDTR1CS0, ndtr1); +} + +static int mrvl_nand_ready(struct mtd_info *mtd) +{ + struct mrvl_nand_host *host = mtd_info_to_host(mtd); + u32 ndcr; + + ndcr = nand_readl(host, NDSR); + if (host->cs == 0) + return ndcr & NDSR_FLASH_RDY; + if (host->cs == 1) + return ndcr & NDSR_RDY; + return 0; +} + +/* + * Claims all blocks are good. + * + * In principle, this function is *only* called when the NAND Flash MTD system + * isn't allowed to keep an in-memory bad block table, so it is forced to ask + * the driver for bad block information. + * + * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so + * this function is *only* called when we take it away. + * + * Thus, this function is only called when we want *all* blocks to look good, + * so it *always* return success. + */ +static int mrvl_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) +{ + return 0; +} + +static void mrvl_nand_select_chip(struct mtd_info *mtd, int chipnr) +{ + struct mrvl_nand_host *host = mtd_info_to_host(mtd); + + if (chipnr <= 0 || chipnr >= 3 || chipnr == host->cs) + return; + host->cs = chipnr - 1; +} + +/* + * Set the data and OOB size, depending on the selected + * spare and ECC configuration. + * Only applicable to READ0, READOOB and PAGEPROG commands. + */ +static unsigned int mrvl_datasize(struct mrvl_nand_host *host) +{ + unsigned int datasize; + + datasize = host->mtd.writesize; + if (host->use_spare) { + datasize += host->spare_size; + if (!host->use_ecc) + datasize += host->ecc_size; + } + return datasize; +} + +/** + * NOTE: it is a must to set ND_RUN firstly, then write + * command buffer, otherwise, it does not work. + * We enable all the interrupt at the same time, and + * let mrvl_nand_irq to handle all logic. + */ +static void mrvl_nand_start(struct mrvl_nand_host *host) +{ + uint32_t ndcr; + + ndcr = host->reg_ndcr; + if (host->use_ecc) + ndcr |= NDCR_ECC_EN; + else + ndcr &= ~NDCR_ECC_EN; + + ndcr &= ~NDCR_DMA_EN; + + if (host->use_spare) + ndcr |= NDCR_SPARE_EN; + else + ndcr &= ~NDCR_SPARE_EN; + + ndcr &= ~NDCR_ND_RUN; + ndcr |= NDCR_INT_MASK; + + /* clear status bits and run */ + nand_writel(host, NDCR, ndcr); + nand_writel(host, NDSR, NDSR_MASK); + nand_writel(host, NDCR, ndcr | NDCR_ND_RUN); + + if (wait_on_timeout(host->chip.chip_delay * USECOND, + nand_readl(host, NDSR) & NDSR_WRCMDREQ)) { + dev_err(host->dev, "Waiting for command request failed\n"); + } else { + /* + * Writing 12 bytes to NDBC0 sets NDBC0, NDBC1 and NDBC2 ! + */ + nand_writel(host, NDSR, NDSR_WRCMDREQ); + nand_writel(host, NDCB0, host->ndcb0); + nand_writel(host, NDCB0, host->ndcb1); + nand_writel(host, NDCB0, host->ndcb2); + } +} + +static void disable_int(struct mrvl_nand_host *host, uint32_t int_mask) +{ + uint32_t ndcr; + + ndcr = nand_readl(host, NDCR); + nand_writel(host, NDCR, ndcr | int_mask); +} + +static inline int is_buf_blank(uint8_t *buf, size_t len) +{ + for (; len > 0; len--) + if (*buf++ != 0xff) + return 0; + return 1; +} + +static void set_command_address(struct mrvl_nand_host *host, + unsigned int page_size, uint16_t column, int page_addr) +{ + /* small page addr setting */ + if (page_size < PAGE_CHUNK_SIZE) { + host->ndcb1 = ((page_addr & 0xFFFFFF) << 8) + | (column & 0xFF); + + host->ndcb2 = 0; + } else { + host->ndcb1 = ((page_addr & 0xFFFF) << 16) + | (column & 0xFFFF); + + if (page_addr & 0xFF0000) + host->ndcb2 = (page_addr & 0xFF0000) >> 16; + else + host->ndcb2 = 0; + } +} + +static void prepare_start_command(struct mrvl_nand_host *host, int command) +{ + /* reset data and oob column point to handle data */ + host->buf_start = 0; + host->buf_count = 0; + host->oob_size = 0; + host->use_ecc = 0; + host->use_spare = 1; + host->ndcb3 = 0; + host->cmd_ongoing = command; + + switch (command) { + case NAND_CMD_SEQIN: + /* + * This command is a no-op, as merged with PROGPAGE. + */ + break; + case NAND_CMD_READOOB: + host->data_size = mrvl_datasize(host); + break; + case NAND_CMD_READ0: + host->use_ecc = 1; + host->data_size = mrvl_datasize(host); + break; + case NAND_CMD_PAGEPROG: + host->use_ecc = 1; + host->data_size = mrvl_datasize(host); + break; + case NAND_CMD_PARAM: + host->use_spare = 0; + break; + default: + host->ndcb1 = 0; + host->ndcb2 = 0; + break; + } + + /* + * If we are about to issue a read command, or about to set + * the write address, then clean the data buffer. + */ + if (command == NAND_CMD_READ0 || + command == NAND_CMD_READOOB || + command == NAND_CMD_SEQIN) { + host->buf_count = host->mtd.writesize + host->mtd.oobsize; + memset(host->data_buff, 0xFF, host->buf_count); + } + +} + +/** + * prepare_set_command - Prepare a NAND command + * + * Prepare data for a NAND command. If the command will not be executed, but + * instead merged into a "bi-command", returns 0. + * + * Returns if the command should be launched on the NFC + */ +static int prepare_set_command(struct mrvl_nand_host *host, int command, + int ext_cmd_type, uint16_t column, int page_addr) +{ + int addr_cycle, exec_cmd; + struct mtd_info *mtd; + + mtd = &host->mtd; + exec_cmd = 1; + + if (host->cs != 0) + host->ndcb0 = NDCB0_CSEL; + else + host->ndcb0 = 0; + + addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles + + host->col_addr_cycles); + switch (command) { + case NAND_CMD_READOOB: + case NAND_CMD_READ0: + host->ndcb0 |= NDCB0_CMD_TYPE(0) + | addr_cycle + | NAND_CMD_READ0; + + if (command == NAND_CMD_READOOB) + host->buf_start = column + mtd->writesize; + else + host->buf_start = column; + + /* + * Multiple page read needs an 'extended command type' field, + * which is either naked-read or last-read according to the + * state. + */ + if (mtd->writesize == PAGE_CHUNK_SIZE) { + host->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8); + } else if (mtd->writesize > PAGE_CHUNK_SIZE) { + host->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) + | NDCB0_LEN_OVRD + | NDCB0_EXT_CMD_TYPE(ext_cmd_type); + host->ndcb3 = host->chunk_size + + host->oob_size; + } + + set_command_address(host, mtd->writesize, column, page_addr); + break; + + case NAND_CMD_SEQIN: + host->buf_start = column; + set_command_address(host, mtd->writesize, 0, page_addr); + /* Data transfer will occur in write_page */ + host->data_size = 0; + exec_cmd = 0; + break; + + case NAND_CMD_PAGEPROG: + host->ndcb0 |= NDCB0_CMD_TYPE(0x1) + | NDCB0_DBC + | (NAND_CMD_PAGEPROG << 8) + | NAND_CMD_SEQIN + | addr_cycle; + break; + + case NAND_CMD_PARAM: + host->buf_count = 256; + host->ndcb0 |= NDCB0_CMD_TYPE(0) + | NDCB0_ADDR_CYC(1) + | NDCB0_LEN_OVRD + | command; + host->ndcb1 = (column & 0xFF); + host->ndcb3 = 256; + host->data_size = 256; + break; + + case NAND_CMD_READID: + host->buf_count = host->read_id_bytes; + host->ndcb0 |= NDCB0_CMD_TYPE(3) + | NDCB0_ADDR_CYC(1) + | command; + host->ndcb1 = (column & 0xFF); + + host->data_size = 8; + break; + case NAND_CMD_STATUS: + host->buf_count = 1; + host->ndcb0 |= NDCB0_CMD_TYPE(4) + | NDCB0_ADDR_CYC(1) + | command; + + host->data_size = 8; + break; + + case NAND_CMD_ERASE1: + host->ndcb0 |= NDCB0_CMD_TYPE(2) + | NDCB0_ADDR_CYC(3) + | NDCB0_DBC + | (NAND_CMD_ERASE2 << 8) + | NAND_CMD_ERASE1; + host->ndcb1 = page_addr; + host->ndcb2 = 0; + + break; + case NAND_CMD_RESET: + host->ndcb0 |= NDCB0_CMD_TYPE(5) + | command; + break; + + case NAND_CMD_ERASE2: + exec_cmd = 0; + break; + + default: + exec_cmd = 0; + dev_err(host->dev, "non-supported command %x\n", + command); + break; + } + + return exec_cmd; +} + +static void mrvl_data_stage(struct mrvl_nand_host *host) +{ + unsigned int i, mask = NDSR_RDDREQ | NDSR_WRDREQ; + u32 *src, ndsr; + + dev_dbg(host->dev, "%s() ndsr=0x%08x\n", __func__, + nand_readl(host, NDSR)); + if (!host->data_size) + return; + + wait_on_timeout(host->chip.chip_delay * USECOND, + nand_readl(host, NDSR) & mask); + if (!(nand_readl(host, NDSR) & mask)) { + dev_err(host->dev, "Timeout waiting for data ndsr=0x%08x\n", + nand_readl(host, NDSR)); + return; + } + + ndsr = nand_readl(host, NDSR); + mask &= ndsr; + src = (u32 *)host->data_buff; + + for (i = 0; i < host->data_size; i += 4) { + if (ndsr & NDSR_RDDREQ) + *src++ = nand_readl(host, NDDB); + if (ndsr & NDSR_WRDREQ) + nand_writel(host, NDDB, *src++); + } + + host->data_size = 0; + nand_writel(host, NDSR, mask); +} + +static void mrvl_nand_wait_cmd_done(struct mrvl_nand_host *host, + unsigned command) +{ + unsigned int mask; + static unsigned int nb_done; + + if (host->cs == 0) + mask = NDSR_CS0_CMDD; + else + mask = NDSR_CS1_CMDD; + wait_on_timeout(host->chip.chip_delay * USECOND, + (nand_readl(host, NDSR) & mask) == mask); + if ((nand_readl(host, NDSR) & mask) != mask) { + dev_err(host->dev, "Waiting end of command %dth %d timeout, ndsr=0x%08x ndcr=0x%08x\n", + nb_done++, command, nand_readl(host, NDSR), + nand_readl(host, NDCR)); + } +} + +static void mrvl_nand_cmdfunc(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + struct mrvl_nand_host *host = mtd_info_to_host(mtd); + + /* + * if this is a x16 device ,then convert the input + * "byte" address into a "word" address appropriate + * for indexing a word-oriented device + */ + dev_dbg(host->dev, "%s(cmd=%d, col=%d, page=%d)\n", __func__, + command, column, page_addr); + if ((host->reg_ndcr & NDCR_DWIDTH_M) && (command != NAND_CMD_READID)) + column /= 2; + + prepare_start_command(host, command); + if (prepare_set_command(host, command, 0, column, page_addr)) { + mrvl_nand_start(host); + mrvl_data_stage(host); + mrvl_nand_wait_cmd_done(host, command); + } +} + +/** + * mrvl_nand_write_page_hwecc - prepare page for write + * + * Fills in the host->data_buff. The actual write will be done by the PAGEPROG + * command, which will trigger a mrvl_data_stage(). + * + * Returns 0 + */ +static int mrvl_nand_write_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf, int oob_required) +{ + struct mrvl_nand_host *host = mtd_info_to_host(mtd); + + memcpy(host->data_buff, buf, mtd->writesize); + if (oob_required) + memcpy(host->data_buff + mtd->writesize, chip->oob_poi, + mtd->oobsize); + else + memset(host->data_buff + mtd->writesize, 0, mtd->oobsize); + dev_dbg(host->dev, "%s(buf=%p, oob_required=%d) => 0\n", + __func__, buf, oob_required); + return 0; +} + +static int mrvl_nand_read_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, int oob_required, + int page) +{ + struct mrvl_nand_host *host = mtd_info_to_host(mtd); + u32 ndsr; + int ret = 0; + + chip->read_buf(mtd, buf, mtd->writesize); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + ndsr = nand_readl(host, NDSR); + + if (ndsr & NDSR_UNCORERR) { + if (is_buf_blank(buf, mtd->writesize)) + ret = 0; + else + ret = -EBADMSG; + } + if (ndsr & NDSR_CORERR) + ret = 1; + dev_dbg(host->dev, "%s(buf=%p, page=%d, oob_required=%d) => %d\n", + __func__, buf, page, oob_required, ret); + return ret; +} + +static void mrvl_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct mrvl_nand_host *host = mtd_info_to_host(mtd); + int xfer; + + xfer = min_t(int, len, host->buf_count); + memcpy(buf, host->data_buff + host->buf_start, xfer); + host->buf_start += xfer; + host->buf_count -= xfer; +} + +static uint8_t mrvl_nand_read_byte(struct mtd_info *mtd) +{ + uint8_t ret; + + mrvl_nand_read_buf(mtd, (uint8_t *)&ret, sizeof(ret)); + return ret; +} + +static u16 mrvl_nand_read_word(struct mtd_info *mtd) +{ + u16 ret; + + mrvl_nand_read_buf(mtd, (uint8_t *)&ret, sizeof(ret)); + return ret; +} + +static void mrvl_nand_write_buf(struct mtd_info *mtd, + const uint8_t *buf, int len) +{ + struct mrvl_nand_host *host = mtd_info_to_host(mtd); + + memcpy(host->data_buff + host->buf_start, buf, len); + host->buf_start += len; + host->buf_count -= len; +} + +static void mrvl_nand_config_flash(struct mrvl_nand_host *host) +{ + struct nand_chip *chip = &host->chip; + struct mtd_info *mtd = &host->mtd; + uint32_t ndcr = host->reg_ndcr; + + /* calculate flash information */ + host->read_id_bytes = (mtd->writesize == 2048) ? 4 : 2; + + /* calculate addressing information */ + host->col_addr_cycles = (mtd->writesize == 2048) ? 2 : 1; + if ((mtd->size >> chip->page_shift) > 65536) + host->row_addr_cycles = 3; + else + host->row_addr_cycles = 2; + + ndcr |= NDCR_ND_ARB_EN; + ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0; + ndcr |= ((mtd->erasesize / mtd->writesize) == 64) ? NDCR_PG_PER_BLK : 0; + ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0; + + ndcr &= ~NDCR_RD_ID_CNT_MASK; + ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes); + ndcr |= NDCR_SPARE_EN; /* enable spare by default */ + ndcr &= ~NDCR_DMA_EN; + + if (chip->options & NAND_BUSWIDTH_16) + ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; + else + ndcr &= ~(NDCR_DWIDTH_M | NDCR_DWIDTH_C); + + host->reg_ndcr = ndcr; +} + +static int pxa_ecc_init(struct mrvl_nand_host *host, + struct nand_ecc_ctrl *ecc, + int strength, int ecc_stepsize, int page_size) +{ + if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) { + host->chunk_size = 2048; + host->spare_size = 40; + host->ecc_size = 24; + ecc->mode = NAND_ECC_HW; + ecc->size = 512; + ecc->strength = 1; + ecc->layout = &ecc_layout_2KB_hwecc; + + } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) { + host->chunk_size = 512; + host->spare_size = 8; + host->ecc_size = 8; + ecc->mode = NAND_ECC_HW; + ecc->size = 512; + ecc->layout = &ecc_layout_512B_hwecc; + ecc->strength = 1; + } else { + dev_err(host->dev, + "ECC strength %d at page size %d is not supported\n", + strength, page_size); + return -ENODEV; + } + + dev_info(host->dev, "ECC strength %d, ECC step size %d\n", + ecc->strength, ecc->size); + return 0; +} + +static int mrvl_nand_scan(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct mrvl_nand_host *host = chip->priv; + int ret; + unsigned int ndcr; + uint16_t ecc_strength = host->ecc_strength; + uint16_t ecc_step = host->ecc_step; + + host->read_id_bytes = 4; + ndcr = NDCR_ND_ARB_EN | NDCR_SPARE_EN; + ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes); + host->reg_ndcr = ndcr; + + mrvl_nand_set_timing(host, true); + if (nand_scan_ident(mtd, 1, NULL)) { + host->reg_ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; + if (nand_scan_ident(mtd, 1, NULL)) + return -ENODEV; + } + mrvl_nand_config_flash(host); + mrvl_nand_set_timing(host, false); + if (host->flash_bbt) { + /* + * We'll use a bad block table stored in-flash and don't + * allow writing the bad block marker to the flash. + */ + chip->bbt_options |= NAND_BBT_USE_FLASH | + NAND_BBT_NO_OOB_BBM; + chip->bbt_td = &bbt_main_descr; + chip->bbt_md = &bbt_mirror_descr; + } + + /* + * If the page size is bigger than the FIFO size, let's check + * we are given the right variant and then switch to the extended + * (aka split) command handling, + */ + if (mtd->writesize > PAGE_CHUNK_SIZE) { + dev_err(host->dev, + "unsupported page size on this variant\n"); + return -ENODEV; + } + + /* Set default ECC strength requirements on non-ONFI devices */ + if (ecc_strength < 1 && ecc_step < 1) { + ecc_strength = 1; + ecc_step = 512; + } + + ret = pxa_ecc_init(host, &chip->ecc, ecc_strength, + ecc_step, mtd->writesize); + if (ret) + return ret; + mtd->oobsize = host->spare_size + host->ecc_size; + + /* allocate the real data + oob buffer */ + host->buf_size = mtd->writesize + mtd->oobsize; + host->data_buff = xmalloc(host->buf_size); + + return nand_scan_tail(mtd); +} + +static struct mrvl_nand_host *alloc_nand_resource(struct device_d *dev) +{ + struct mrvl_nand_platform_data *pdata; + struct mrvl_nand_host *host; + struct nand_chip *chip = NULL; + struct mtd_info *mtd; + + pdata = dev->platform_data; + host = xzalloc(sizeof(*host)); + host->cs = 0; + mtd = &host->mtd; + mtd->priv = &host->chip; + mtd->parent = dev; + mtd->name = "mrvl_nand"; + + chip = &host->chip; + chip->read_byte = mrvl_nand_read_byte; + chip->read_word = mrvl_nand_read_word; + chip->ecc.read_page = mrvl_nand_read_page_hwecc; + chip->ecc.write_page = mrvl_nand_write_page_hwecc; + chip->dev_ready = mrvl_nand_ready; + chip->select_chip = mrvl_nand_select_chip; + chip->block_bad = mrvl_nand_block_bad; + chip->read_buf = mrvl_nand_read_buf; + chip->write_buf = mrvl_nand_write_buf; + chip->options |= NAND_NO_SUBPAGE_WRITE; + chip->cmdfunc = mrvl_nand_cmdfunc; + chip->priv = host; + chip->chip_delay = CHIP_DELAY_TIMEOUT_US; + + host->dev = dev; + host->mmio_base = dev_request_mem_region(dev, 0); + if (IS_ERR(host->mmio_base)) { + free(host); + return host->mmio_base; + } + if (pdata) { + host->keep_config = pdata->keep_config; + host->flash_bbt = pdata->flash_bbt; + host->ecc_strength = pdata->ecc_strength; + host->ecc_step = pdata->ecc_step_size; + } + + /* Allocate a buffer to allow flash detection */ + host->buf_size = INIT_BUFFER_SIZE; + host->data_buff = xmalloc(host->buf_size); + + /* initialize all interrupts to be disabled */ + disable_int(host, NDSR_MASK); + return host; +} + +static int mrvl_nand_probe_dt(struct mrvl_nand_host *host) +{ + struct device_node *np = host->dev->device_node; + + if (of_get_property(np, "marvell,nand-keep-config", NULL)) + host->keep_config = 1; + of_property_read_u32(np, "num-cs", &host->cs); + if (of_get_nand_on_flash_bbt(np)) + host->flash_bbt = 1; + + return 0; +} + +static int mrvl_nand_probe(struct device_d *dev) +{ + struct mrvl_nand_host *host; + int ret; + + host = alloc_nand_resource(dev); + if (IS_ERR(host)) { + dev_err(dev, "alloc nand resource failed\n"); + return PTR_ERR(host); + } + + ret = mrvl_nand_probe_dt(host); + if (ret) + return ret; + + host->chip.controller = &host->chip.hwcontrol; + ret = mrvl_nand_scan(&host->mtd); + if (ret) { + dev_warn(dev, "failed to scan nand at cs %d\n", + host->cs); + return -ENODEV; + } + + ret = add_mtd_nand_device(&host->mtd, "nand"); + return ret; +} + +static struct driver_d mrvl_nand_driver = { + .name = "mrvl_nand", + .probe = mrvl_nand_probe, + .of_compatible = DRV_OF_COMPAT(mrvl_nand_dt_ids), +}; +device_platform_driver(mrvl_nand_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Marvell NAND controller driver"); diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c index 100688ccf8..698c74add1 100644 --- a/drivers/net/smc91111.c +++ b/drivers/net/smc91111.c @@ -435,14 +435,14 @@ #define MEMORY_WAIT_TIME 16 struct accessors { - void (*ob)(unsigned, void __iomem *); - void (*ow)(unsigned, void __iomem *); - void (*ol)(unsigned long, void __iomem *); - void (*osl)(void __iomem *, const void *, int); - unsigned (*ib)(void __iomem *); - unsigned (*iw)(void __iomem *); - unsigned long (*il)(void __iomem *); - void (*isl)(void __iomem *, void*, int); + void (*ob)(unsigned, void __iomem *, unsigned, unsigned); + void (*ow)(unsigned, void __iomem *, unsigned, unsigned); + void (*ol)(unsigned long, void __iomem *, unsigned, unsigned); + void (*osl)(void __iomem *, unsigned, const void *, int, unsigned); + unsigned (*ib)(void __iomem *, unsigned, unsigned); + unsigned (*iw)(void __iomem *, unsigned, unsigned); + unsigned long (*il)(void __iomem *, unsigned, unsigned); + void (*isl)(void __iomem *, unsigned, void*, int, unsigned); }; struct smc91c111_priv { @@ -450,6 +450,11 @@ struct smc91c111_priv { struct accessors a; void __iomem *base; int qemu_fixup; + unsigned shift; + int version; + int revision; + unsigned int control_setup; + unsigned int config_setup; }; #if (SMC_DEBUG > 2 ) @@ -479,109 +484,176 @@ struct smc91c111_priv { #define ETH_ZLEN 60 -static void a_outb(unsigned value, void __iomem *offset) +static void a8_outb(unsigned value, void __iomem *base, unsigned int offset, + unsigned shift) { - writeb(value, offset); + writeb(value, base + (offset << shift)); } -static void a_outw(unsigned value, void __iomem *offset) +static void a16_outw(unsigned value, void __iomem *base, unsigned int offset, + unsigned shift) { - writew(value, offset); + writew(value, base + (offset << shift)); } -static void a_outl(unsigned long value, void __iomem *offset) +static void a32_outl(unsigned long value, void __iomem *base, + unsigned int offset, unsigned shift) { - writel(value, offset); + writel(value, base + (offset << shift)); } -static void a_outsl(void __iomem *offset, const void *data, int count) +static void a16_outsl(void __iomem *base, unsigned int offset, + const void *data, int count, unsigned shift) { - writesl(offset, data, count); + writesw(base + (offset << shift), data, count * 2); } -static unsigned a_inb(void __iomem *offset) +static void a16_outl(unsigned long value, void __iomem *base, + unsigned int offset, unsigned shift) { - return readb(offset); + writew(value & 0xffff, base + (offset << shift)); + writew(value >> 16, base + ((offset + 2) << shift)); } -static unsigned a_inw(void __iomem *offset) +static void a32_outsl(void __iomem *base, unsigned int offset, + const void *data, int count, unsigned shift) { - return readw(offset); + writesw(base + (offset << shift), data, count * 2); } -static unsigned long a_inl(void __iomem *offset) +static unsigned a8_inb(void __iomem *base, unsigned int offset, unsigned shift) { - return readl(offset); + return readb(base + (offset << shift)); } -static inline void a_insl(void __iomem *offset, void *data, int count) +static unsigned a16_inw(void __iomem *base, unsigned int offset, unsigned shift) { - readsl(offset, data, count); + return readw(base + (offset << shift)); } -/* access happens via a 32 bit bus */ -static const struct accessors access_via_32bit = { - .ob = a_outb, - .ow = a_outw, - .ol = a_outl, - .osl = a_outsl, - .ib = a_inb, - .iw = a_inw, - .il = a_inl, - .isl = a_insl, -}; - -/* ------------------------------------------------------------------------ */ - -static inline void SMC_outb(struct smc91c111_priv *p, unsigned value, - unsigned offset) +static unsigned long a16_inl(void __iomem *base, unsigned int offset, + unsigned shift) { - (p->a.ob)(value, p->base + offset); -} + u32 value; -static inline void SMC_outw(struct smc91c111_priv *p, unsigned value, - unsigned offset) -{ - (p->a.ow)(value, p->base + offset); -} + value = readw(base + (offset << shift)); + value |= readw(base + (offset << shift)) << 16; -static inline void SMC_outl(struct smc91c111_priv *p, unsigned long value, - unsigned offset) -{ - (p->a.ol)(value, p->base + offset); + return value; } -static inline void SMC_outsl(struct smc91c111_priv *p, unsigned offset, - const void *data, int count) +static inline void a16_insl(void __iomem *base, unsigned int offset, void *data, + int count, unsigned shift) { - (p->a.osl)(p->base + offset, data, count); + readsw(base + (offset << shift), data, count * 2); } -static inline unsigned SMC_inb(struct smc91c111_priv *p, unsigned offset) +static unsigned long a32_inl(void __iomem *base, unsigned int offset, + unsigned shift) { - return (p->a.ib)(p->base + offset); + return readl(base + (offset << shift)); } -static inline unsigned SMC_inw(struct smc91c111_priv *p, unsigned offset) +static inline void a32_insl(void __iomem *base, unsigned int offset, void *data, + int count, unsigned shift) { - return (p->a.iw)(p->base + offset); + readsl(base + (offset << shift), data, count); } -static inline unsigned long SMC_inl(struct smc91c111_priv *p, unsigned offset) -{ - return (p->a.il)(p->base + offset); -} +static const struct accessors access_via_16bit = { + .ob = a8_outb, + .ow = a16_outw, + .ol = a16_outl, + .osl = a16_outsl, + .ib = a8_inb, + .iw = a16_inw, + .il = a16_inl, + .isl = a16_insl, +}; -static inline void SMC_insl(struct smc91c111_priv *p, unsigned offset, - void *data, int count) -{ - (p->a.isl)(p->base + offset, data, count); -} +/* access happens via a 32 bit bus */ +static const struct accessors access_via_32bit = { + .ob = a8_outb, + .ow = a16_outw, + .ol = a32_outl, + .osl = a32_outsl, + .ib = a8_inb, + .iw = a16_inw, + .il = a32_inl, + .isl = a32_insl, +}; -static inline void SMC_SELECT_BANK(struct smc91c111_priv *p, int bank) -{ - SMC_outw(p, bank, BANK_SELECT); -} +/* ------------------------------------------------------------------------ */ + +static unsigned last_bank; +#define SMC_outb(p, value, offset) \ + do { \ + PRINTK3("\t%s:%d outb: %s[%1d:0x%04x] = 0x%02x\n", \ + __func__, __LINE__, #offset, last_bank, \ + (offset), (value)); \ + ((p)->a.ob)((value), (p)->base, (offset), (p)->shift); \ + } while (0) + +#define SMC_outw(p, value, offset) \ + do { \ + PRINTK3("\t%s:%d outw: %s[%1d:0x%04x] = 0x%04x\n", \ + __func__, __LINE__, #offset, last_bank, \ + (offset), (value)); \ + ((p)->a.ow)((value), (p)->base, (offset), (p)->shift); \ + } while (0) + +#define SMC_outl(p, value, offset) \ + do { \ + PRINTK3("\t%s:%d outl: %s[%1d:0x%04x] = 0x%08lx\n", \ + __func__, __LINE__, #offset, last_bank, \ + (offset), (unsigned long)(value)); \ + ((p)->a.ol)((value), (p)->base, (offset), (p)->shift); \ + } while (0) + +#define SMC_outsl(p, offset, data, count)\ + do { \ + PRINTK3("\t%s:%d outsl: %5d@%p -> [%1d:0x%04x]\n", \ + __func__, __LINE__, (count) * 4, data, \ + last_bank, (offset)); \ + ((p)->a.osl)((p)->base, (offset), data, (count), \ + (p)->shift); \ + } while (0) + +#define SMC_inb(p, offset) \ + ({ \ + unsigned _v = ((p)->a.ib)((p)->base, (offset), \ + (p)->shift); \ + PRINTK3("\t%s:%d inb: %s[%1d:0x%04x] -> 0x%02x\n", \ + __func__, __LINE__, #offset, last_bank, \ + (offset), _v); \ + _v; }) + +#define SMC_inw(p, offset) \ + ({ \ + unsigned _v = ((p)->a.iw)((p)->base, (offset), \ + (p)->shift); \ + PRINTK3("\t%s:%d inw: %s[%1d:0x%04x] -> 0x%04x\n", \ + __func__, __LINE__, #offset, last_bank, \ + (offset), _v); \ + _v; }) + +#define SMC_inl(p, offset) \ + ({ \ + unsigned long _v = ((p)->a.il)((p)->base, (offset), \ + (p)->shift); \ + PRINTK3("\t%s:%d inl: %s[%1d:0x%04x] -> 0x%08lx\n", \ + __func__, __LINE__, #offset, last_bank, \ + (offset), _v); \ + _v; }) + +#define SMC_insl(p, offset, data, count) \ + ((p)->a.isl)((p)->base, (offset), data, (count), (p)->shift) + +#define SMC_SELECT_BANK(p, bank) \ + do { \ + SMC_outw(p, bank & 0xf, BANK_SELECT); \ + last_bank = bank & 0xf; \ + } while (0) #if SMC_DEBUG > 2 static void print_packet( unsigned char * buf, int length ) @@ -863,6 +935,7 @@ static int smc91c111_phy_read(struct mii_bus *bus, int phyaddr, int phyreg) static void smc91c111_reset(struct eth_device *edev) { struct smc91c111_priv *priv = (struct smc91c111_priv *)edev->priv; + int rev_vers; /* This resets the registers mostly to defaults, but doesn't affect EEPROM. That seems unnecessary */ @@ -878,8 +951,11 @@ static void smc91c111_reset(struct eth_device *edev) /* Release from possible power-down state */ /* Configuration register is not affected by Soft Reset */ - SMC_outw(priv, SMC_inw(priv, CONFIG_REG) | CONFIG_EPH_POWER_EN, - CONFIG_REG); + if (priv->config_setup) + SMC_outw(priv, priv->config_setup, CONFIG_REG); + else + SMC_outw(priv, SMC_inw(priv, CONFIG_REG) | CONFIG_EPH_POWER_EN, + CONFIG_REG); SMC_SELECT_BANK(priv, 0); @@ -892,7 +968,10 @@ static void smc91c111_reset(struct eth_device *edev) /* set the control register */ SMC_SELECT_BANK(priv, 1); - SMC_outw(priv, CTL_DEFAULT, CTL_REG); + if (priv->control_setup) + SMC_outw(priv, priv->control_setup, CTL_REG); + else + SMC_outw(priv, CTL_DEFAULT, CTL_REG); /* Reset the MMU */ SMC_SELECT_BANK(priv, 2); @@ -908,6 +987,14 @@ static void smc91c111_reset(struct eth_device *edev) /* Disable all interrupts */ SMC_outb(priv, 0, IM_REG); + + /* Check chip revision (91c94, 91c96, 91c100, ...) */ + SMC_SELECT_BANK(priv, 3); + rev_vers = SMC_inb(priv, REV_REG); + priv->revision = (rev_vers >> 4) & 0xf; + priv->version = rev_vers & 0xf; + dev_info(edev->parent, "chip is revision=%2d, version=%2d\n", + priv->revision, priv->version); } static void smc91c111_enable(struct eth_device *edev) @@ -927,10 +1014,16 @@ static int smc91c111_eth_open(struct eth_device *edev) /* Configure the Receive/Phy Control register */ SMC_SELECT_BANK(priv, 0); - SMC_outw(priv, RPC_DEFAULT, RPC_REG); + if (priv->revision > 4) + SMC_outw(priv, RPC_DEFAULT, RPC_REG); smc91c111_enable(edev); + if (priv->revision <= 4) { + dev_info(edev->parent, "force link at 10Mpbs on internal phy\n"); + return 0; + } + ret = phy_device_connect(edev, &priv->miibus, 0, NULL, 0, PHY_INTERFACE_MODE_NA); @@ -1333,15 +1426,19 @@ static int smc91c111_probe(struct device_d *dev) edev->priv = (struct smc91c111_priv *)(edev + 1); priv = edev->priv; + priv->a = access_via_32bit; if (dev->platform_data) { struct smc91c111_pdata *pdata = dev->platform_data; priv->qemu_fixup = pdata->qemu_fixup; + priv->shift = pdata->addr_shift; + if (pdata->bus_width == 16) + priv->a = access_via_16bit; + pdata->config_setup = pdata->config_setup; + pdata->control_setup = pdata->control_setup; } - priv->a = access_via_32bit; - edev->init = smc91c111_init_dev; edev->open = smc91c111_eth_open; edev->send = smc91c111_eth_send; @@ -1361,7 +1458,8 @@ static int smc91c111_probe(struct device_d *dev) smc91c111_reset(edev); - mdiobus_register(&priv->miibus); + if (priv->revision > 4) + mdiobus_register(&priv->miibus); eth_register(edev); return 0; diff --git a/include/net/smc91111.h b/include/net/smc91111.h index 0b2d49bb19..ba9da0b8dd 100644 --- a/include/net/smc91111.h +++ b/include/net/smc91111.h @@ -9,6 +9,10 @@ struct smc91c111_pdata { int qemu_fixup; + int addr_shift; + int bus_width; + int config_setup; + int control_setup; }; #endif /* __SMC91111_H__ */ diff --git a/include/platform_data/mtd-nand-mrvl.h b/include/platform_data/mtd-nand-mrvl.h new file mode 100644 index 0000000000..c8ef6a1eea --- /dev/null +++ b/include/platform_data/mtd-nand-mrvl.h @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2014 Robert Jarzmik + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Taken from linux kernel mostly. + */ +#ifndef __MRVL_NAND_H +#define __MRVL_NAND_H + +struct mrvl_nand_timing { + uint16_t id; /* NAND id code (READID) */ + unsigned int tCH; /* Enable signal hold time */ + unsigned int tCS; /* Enable signal setup time */ + unsigned int tWH; /* ND_nWE high duration */ + unsigned int tWP; /* ND_nWE pulse time */ + unsigned int tRH; /* ND_nRE high duration */ + unsigned int tRP; /* ND_nRE pulse width */ + unsigned int tR; /* ND_nWE high to ND_nRE low for read */ + unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */ + unsigned int tAR; /* ND_ALE low to ND_nRE low delay */ +}; + +struct mrvl_nand_flash { + char *name; + uint32_t chip_id; + unsigned int page_per_block; /* Pages per block (PG_PER_BLK) */ + unsigned int page_size; /* Page size in bytes (PAGE_SZ) */ + unsigned int flash_width; /* Flash memory width (DWIDTH_M) */ + unsigned int dfc_width; /* Flash controller width (DWIDTH_C) */ + unsigned int num_blocks; /* Number of physical blocks in Flash */ + + struct mrvl_nand_timing *timing; /* NAND Flash timing */ +}; + +/* + * Current pxa3xx_nand controller has two chip select which + * both be workable. + * + * Notice should be taken that: + * When you want to use this feature, you should not enable the + * keep configuration feature, for two chip select could be + * attached with different nand chip. The different page size + * and timing requirement make the keep configuration impossible. + */ + +/* The max num of chip select current support */ +#define NUM_CHIP_SELECT (2) +struct mrvl_nand_platform_data { + /* the data flash bus is shared between the Static Memory + * Controller and the Data Flash Controller, the arbiter + * controls the ownership of the bus + */ + int dwidth_c; + int dwidth_m; + + /* allow platform code to keep OBM/bootloader defined NFC config */ + int keep_config; + + /* indicate how many chip selects will be used */ + int num_cs; + + /* use an flash-based bad block table */ + bool flash_bbt; + + /* requested ECC strength and ECC step size */ + int ecc_strength, ecc_step_size; + + const struct mtd_partition *parts[NUM_CHIP_SELECT]; + unsigned int nr_parts[NUM_CHIP_SELECT]; + + const struct mrvl_nand_flash *flash; + size_t num_flash; +}; + +extern void mrvl_set_nand_info(struct mrvl_nand_platform_data *info); +#endif /* __MRVL_NAND_H */ |