diff options
26 files changed, 949 insertions, 84 deletions
diff --git a/arch/arm/boards/freescale-mx51-pdk/env/config b/arch/arm/boards/freescale-mx51-pdk/env/config deleted file mode 100644 index 7a2841e606..0000000000 --- a/arch/arm/boards/freescale-mx51-pdk/env/config +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/sh - -hostname=babbage -eth0.serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-$hostname.$rootfs_type - -kernelimage=zImage-$hostname -#kernelimage=uImage-$hostname -#kernelimage=Image-$hostname -#kernelimage=Image-$hostname.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttymxc0,115200" - -disk_parts="256k(barebox)ro,128k(bareboxenv),4M(kernel),-(root)" - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " - diff --git a/arch/arm/boards/freescale-mx51-pdk/env/init/bootargs-base b/arch/arm/boards/freescale-mx51-pdk/env/init/bootargs-base new file mode 100644 index 0000000000..d86975406e --- /dev/null +++ b/arch/arm/boards/freescale-mx51-pdk/env/init/bootargs-base @@ -0,0 +1,8 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "Base bootargs" + exit +fi + +global.linux.bootargs.base="console=ttymxc0,115200" diff --git a/arch/arm/boards/freescale-mx51-pdk/env/init/hostname b/arch/arm/boards/freescale-mx51-pdk/env/init/hostname new file mode 100644 index 0000000000..4c78902a17 --- /dev/null +++ b/arch/arm/boards/freescale-mx51-pdk/env/init/hostname @@ -0,0 +1,8 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "hostname" + exit +fi + +global.hostname=babbage diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c index cd80677fc5..ca10afb8ca 100644 --- a/arch/arm/boards/pcm038/pcm970.c +++ b/arch/arm/boards/pcm038/pcm970.c @@ -18,11 +18,17 @@ #include <common.h> #include <io.h> #include <init.h> +#include <sizes.h> +#include <platform_ide.h> #include <mach/imx-regs.h> #include <mach/iomux-mx27.h> #include <mach/gpio.h> #include <usb/ulpi.h> +#define GPIO_IDE_POWER (GPIO_PORTE + 18) +#define GPIO_IDE_PCOE (GPIO_PORTF + 7) +#define GPIO_IDE_RESET (GPIO_PORTF + 10) + #ifdef CONFIG_USB static void pcm970_usbh2_init(void) { @@ -45,6 +51,103 @@ static void pcm970_usbh2_init(void) } #endif +#ifdef CONFIG_DISK_INTF_PLATFORM_IDE +static struct resource pcm970_ide_resources[] = { + { + .start = IMX_PCMCIA_MEM_BASE, + .size = SZ_1K, + .flags = IORESOURCE_MEM, + }, +}; + +static void pcm970_ide_reset(int state) +{ + /* Switch reset line to low/high state */ + gpio_set_value(GPIO_IDE_RESET, !!state); +} + +static struct ide_port_info pcm970_ide_pdata = { + .ioport_shift = 0, + .reset = &pcm970_ide_reset, +}; + +static struct device_d pcm970_ide_device = { + .id = -1, + .name = "ide_intf", + .num_resources = ARRAY_SIZE(pcm970_ide_resources), + .resource = pcm970_ide_resources, + .platform_data = &pcm970_ide_pdata, +}; + +static void pcm970_ide_init(void) +{ + uint32_t i; + unsigned int mode[] = { + /* PCMCIA */ + PF20_PF_PC_CD1, + PF19_PF_PC_CD2, + PF18_PF_PC_WAIT, + PF17_PF_PC_READY, + PF16_PF_PC_PWRON, + PF14_PF_PC_VS1, + PF13_PF_PC_VS2, + PF12_PF_PC_BVD1, + PF11_PF_PC_BVD2, + PF9_PF_PC_IOIS16, + PF8_PF_PC_RW, + GPIO_IDE_PCOE | GPIO_GPIO | GPIO_OUT, /* PCOE */ + GPIO_IDE_RESET | GPIO_GPIO | GPIO_OUT, /* Reset */ + GPIO_IDE_POWER | GPIO_GPIO | GPIO_OUT, /* Power */ + }; + + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i] | GPIO_PUEN); + + /* Always set PCOE signal to low */ + gpio_set_value(GPIO_IDE_PCOE, 0); + + /* Assert RESET line */ + gpio_set_value(GPIO_IDE_RESET, 0); + + /* Power up CF-card (Also switched on User-LED) */ + gpio_set_value(GPIO_IDE_POWER, 1); + mdelay(10); + + /* Reset PCMCIA Status Change Register */ + writel(0x00000fff, PCMCIA_PSCR); + mdelay(10); + + /* Check PCMCIA Input Pins Register for Card Detect & Power */ + if ((readl(PCMCIA_PIPR) & ((1 << 8) | (3 << 3))) != (1 << 8)) { + printf("CompactFlash card not found. Driver not enabled.\n"); + return; + } + + /* Disable all interrupts */ + writel(0, PCMCIA_PER); + + /* Disable all PCMCIA banks */ + for (i = 0; i < 5; i++) + writel(0, PCMCIA_POR(i)); + + /* Not use internal PCOE */ + writel(0, PCMCIA_PGCR); + + /* Setup PCMCIA bank0 for Common memory mode */ + writel(0, PCMCIA_PBR(0)); + writel(0, PCMCIA_POFR(0)); + writel((0 << 25) | (17 << 17) | (4 << 11) | (3 << 5) | 0xf, PCMCIA_POR(0)); + + /* Clear PCMCIA General Status Register */ + writel(0x0000001f, PCMCIA_PGSR); + + /* Make PCMCIA bank0 valid */ + writel(readl(PCMCIA_POR(0)) | (1 << 29), PCMCIA_POR(0)); + + register_device(&pcm970_ide_device); +} +#endif + static int pcm970_init(void) { int i; @@ -74,6 +177,10 @@ static int pcm970_init(void) pcm970_usbh2_init(); #endif +#ifdef CONFIG_DISK_INTF_PLATFORM_IDE + pcm970_ide_init(); +#endif + return 0; } diff --git a/arch/arm/configs/freescale_mx51_babbage_defconfig b/arch/arm/configs/freescale_mx51_babbage_defconfig index c4f7aeff78..22ef163a4b 100644 --- a/arch/arm/configs/freescale_mx51_babbage_defconfig +++ b/arch/arm/configs/freescale_mx51_babbage_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_IMX51=y CONFIG_IMX_IIM=y CONFIG_IMX_IIM_FUSE_BLOW=y CONFIG_AEABI=y +CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y CONFIG_MMU=y @@ -11,23 +12,26 @@ CONFIG_MALLOC_SIZE=0x2000000 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y CONFIG_LONGHELP=y -CONFIG_GLOB=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_MENU=y +CONFIG_DEFAULT_ENVIRONMENT_COMPRESSED_LZO=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx51-pdk/env/" CONFIG_CMD_EDIT=y CONFIG_CMD_SLEEP=y CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y CONFIG_CMD_EXPORT=y CONFIG_CMD_PRINTENV=y CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y CONFIG_CMD_TIME=y CONFIG_CMD_ECHO_E=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_IOMEM=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y CONFIG_CMD_FLASH=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y @@ -47,10 +51,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_UNCOMPRESS=y CONFIG_NET=y CONFIG_NET_DHCP=y -CONFIG_NET_NFS=y CONFIG_NET_PING=y -CONFIG_NET_TFTP=y -CONFIG_NET_TFTP_PUSH=y +CONFIG_NET_RESOLV=y CONFIG_DRIVER_NET_FEC_IMX=y CONFIG_DRIVER_SPI_IMX=y CONFIG_DRIVER_CFI=y @@ -59,6 +61,8 @@ CONFIG_MCI=y CONFIG_MCI_STARTUP=y CONFIG_MCI_IMX_ESDHC=y CONFIG_MFD_MC13XXX=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S index fc53653c34..6d03565c58 100644 --- a/arch/arm/cpu/cache-armv4.S +++ b/arch/arm/cpu/cache-armv4.S @@ -42,7 +42,6 @@ ENTRY(__mmu_cache_off) mov pc, lr ENDPROC(__mmu_cache_off) -__BARE_INIT ENTRY(__mmu_cache_flush) mrc p15, 0, r6, c0, c0 @ get processor ID mov r2, #64*1024 @ default: 32K dcache size (*2) diff --git a/arch/arm/cpu/cache-armv5.S b/arch/arm/cpu/cache-armv5.S index d870e6b80f..a1193a6a66 100644 --- a/arch/arm/cpu/cache-armv5.S +++ b/arch/arm/cpu/cache-armv5.S @@ -42,7 +42,6 @@ ENTRY(__mmu_cache_off) mov pc, lr ENDPROC(__mmu_cache_off) -__BARE_INIT ENTRY(__mmu_cache_flush) 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache bne 1b diff --git a/arch/arm/cpu/cache-armv6.S b/arch/arm/cpu/cache-armv6.S index 9de76da452..335bac2a45 100644 --- a/arch/arm/cpu/cache-armv6.S +++ b/arch/arm/cpu/cache-armv6.S @@ -44,7 +44,6 @@ ENTRY(__mmu_cache_off) #endif mov pc, lr -__BARE_INIT ENTRY(__mmu_cache_flush) mov r1, #0 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S index 416498d329..28a6315522 100644 --- a/arch/arm/cpu/cache-armv7.S +++ b/arch/arm/cpu/cache-armv7.S @@ -50,7 +50,6 @@ ENTRY(__mmu_cache_off) mov pc, r12 ENDPROC(__mmu_cache_off) -__BARE_INIT ENTRY(__mmu_cache_flush) mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 tst r10, #0xf << 16 @ hierarchical cache (ARMv7) diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c index c7462f6e2e..3c282ee791 100644 --- a/arch/arm/cpu/start.c +++ b/arch/arm/cpu/start.c @@ -75,12 +75,6 @@ void __naked __bare_init reset(void) #ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT arch_init_lowlevel(); #endif - __asm__ __volatile__ ( - "bl __mmu_cache_flush;" - : - : - : "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory" - ); /* disable MMU stuff and caches */ r = get_cr(); @@ -135,6 +129,9 @@ void __naked __section(.text_ll_return) board_init_lowlevel_return(void) /* clear bss */ memset(__bss_start, 0, __bss_stop - __bss_start); + /* flush I-cache before jumping to the copied binary */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); + /* call start_barebox with its absolute address */ r = (unsigned int)&start_barebox; __asm__ __volatile__("mov pc, %0" : : "r"(r)); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 7905027b1c..564e2fe92d 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -391,6 +391,7 @@ choice prompt "i.MX51 Board Type" config MACH_FREESCALE_MX51_PDK + select DEFAULT_ENVIRONMENT_GENERIC_NEW bool "Freescale i.MX51 PDK" config MACH_EUKREA_CPUIMX51SD diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h index 437cc7d302..19dcad9e9b 100644 --- a/arch/arm/mach-imx/include/mach/imx27-regs.h +++ b/arch/arm/mach-imx/include/mach/imx27-regs.h @@ -41,6 +41,17 @@ #define IMX_NFC_BASE (0xd8000000) #define IMX_ESD_BASE (0xd8001000) #define IMX_WEIM_BASE (0xd8002000) +#define IMX_M3IF_BASE (0xd8003000) +#define IMX_PCMCIA_CTL_BASE (0xd8004000) + +#define PCMCIA_PIPR (IMX_PCMCIA_CTL_BASE + 0x00) +#define PCMCIA_PSCR (IMX_PCMCIA_CTL_BASE + 0x04) +#define PCMCIA_PER (IMX_PCMCIA_CTL_BASE + 0x08) +#define PCMCIA_PBR(x) (IMX_PCMCIA_CTL_BASE + 0x0c + ((x) << 2)) +#define PCMCIA_POR(x) (IMX_PCMCIA_CTL_BASE + 0x28 + ((x) << 2)) +#define PCMCIA_POFR(x) (IMX_PCMCIA_CTL_BASE + 0x44 + ((x) << 2)) +#define PCMCIA_PGCR (IMX_PCMCIA_CTL_BASE + 0x60) +#define PCMCIA_PGSR (IMX_PCMCIA_CTL_BASE + 0x64) /* AIPI */ #define AIPI1_PSR0 __REG(IMX_AIPI1_BASE + 0x00) @@ -240,6 +251,8 @@ #define IMX_CS4_BASE 0xD4000000 #define IMX_CS5_BASE 0xD6000000 +#define IMX_PCMCIA_MEM_BASE (0xdc000000) + #ifndef __ASSEMBLY__ static inline void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned addional) { diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile index f9151d28a1..d6d28ce652 100644 --- a/arch/mips/boot/Makefile +++ b/arch/mips/boot/Makefile @@ -1 +1,2 @@ obj-y += start.o +obj-y += main_entry.o diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c new file mode 100644 index 0000000000..8f5f6fc00e --- /dev/null +++ b/arch/mips/boot/main_entry.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2012 Antony Pavlov <antonynpavlov@gmail.com> + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <string.h> +#include <asm/sections.h> +#include <asm/cpu-features.h> + +extern void start_barebox(void); + +void main_entry(void); + +/** + * Called plainly from assembler code + * + * @note The C environment isn't initialized yet + */ +void main_entry(void) +{ + /* clear the BSS first */ + memset(__bss_start, 0x00, __bss_stop - __bss_start); + + cpu_probe(); + + if (cpu_has_4k_cache) { + extern void r4k_cache_init(void); + + r4k_cache_init(); + } + + start_barebox(); +} diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S index e8868e1dc0..dd302fcd35 100644 --- a/arch/mips/boot/start.S +++ b/arch/mips/boot/start.S @@ -79,7 +79,7 @@ __start: la a1, _start /* link (RAM) _start address */ - beq a0, a1, clear_bss + beq a0, a1, stack_setup nop la t0, _start @@ -105,16 +105,6 @@ copy_loop: blez t3, copy_loop addi a1, LONGSIZE * 4 -clear_bss: - la t0, __bss_start - sw zero, (t0) - la t1, _end - 4 -1: - addiu t0, LONGSIZE - sw zero, (t0) - bne t0, t1, 1b - nop - /* * Dominic Sweetman, See MIPS Run, Morgan Kaufmann, 2nd edition, 2006 * @@ -144,7 +134,7 @@ stack_setup: /* reserve four 32-bit argument slots */ addiu sp, -16 - la v0, start_barebox + la v0, main_entry jal v0 nop diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 36d34b62a3..001ebf2e72 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -27,6 +27,6 @@ #ifndef _ASM_MIPS_BITOPS_H_ #define _ASM_MIPS_BITOPS_H_ -/* nothing special yet */ +#include <asm-generic/bitops/__ffs.h> #endif /* _ASM_MIPS_BITOPS_H_ */ diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h new file mode 100644 index 0000000000..168d854454 --- /dev/null +++ b/arch/mips/include/asm/cpu-features.h @@ -0,0 +1,254 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + */ +#ifndef __ASM_CPU_FEATURES_H +#define __ASM_CPU_FEATURES_H + +#include <asm/cpu.h> +#include <asm/cpu-info.h> + +#ifndef current_cpu_type +#define current_cpu_type() current_cpu_data.cputype +#endif + +/* + * SMP assumption: Options of CPU 0 are a superset of all processors. + * This is true for all known MIPS systems. + */ +#ifndef cpu_has_tlb +#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) +#endif +#ifndef cpu_has_4kex +#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) +#endif +#ifndef cpu_has_3k_cache +#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) +#endif +#define cpu_has_6k_cache 0 +#define cpu_has_8k_cache 0 +#ifndef cpu_has_4k_cache +#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) +#endif +#ifndef cpu_has_tx39_cache +#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) +#endif +#ifndef cpu_has_octeon_cache +#define cpu_has_octeon_cache 0 +#endif +#ifndef cpu_has_fpu +#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) +#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) +#else +#define raw_cpu_has_fpu cpu_has_fpu +#endif +#ifndef cpu_has_32fpr +#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) +#endif +#ifndef cpu_has_counter +#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) +#endif +#ifndef cpu_has_watch +#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) +#endif +#ifndef cpu_has_divec +#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) +#endif +#ifndef cpu_has_vce +#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) +#endif +#ifndef cpu_has_cache_cdex_p +#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) +#endif +#ifndef cpu_has_cache_cdex_s +#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) +#endif +#ifndef cpu_has_prefetch +#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) +#endif +#ifndef cpu_has_mcheck +#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) +#endif +#ifndef cpu_has_ejtag +#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) +#endif +#ifndef cpu_has_llsc +#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) +#endif +#ifndef kernel_uses_llsc +#define kernel_uses_llsc cpu_has_llsc +#endif +#ifndef cpu_has_mips16 +#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) +#endif +#ifndef cpu_has_mdmx +#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) +#endif +#ifndef cpu_has_mips3d +#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) +#endif +#ifndef cpu_has_smartmips +#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) +#endif +#ifndef kernel_uses_smartmips_rixi +#define kernel_uses_smartmips_rixi 0 +#endif +#ifndef cpu_has_vtag_icache +#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) +#endif +#ifndef cpu_has_dc_aliases +#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) +#endif +#ifndef cpu_has_ic_fills_f_dc +#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) +#endif +#ifndef cpu_has_pindexed_dcache +#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) +#endif + +/* + * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors + * such as the R10000 have I-Caches that snoop local stores; the embedded ones + * don't. For maintaining I-cache coherency this means we need to flush the + * D-cache all the way back to whever the I-cache does refills from, so the + * I-cache has a chance to see the new data at all. Then we have to flush the + * I-cache also. + * Note we may have been rescheduled and may no longer be running on the CPU + * that did the store so we can't optimize this into only doing the flush on + * the local CPU. + */ +#ifndef cpu_icache_snoops_remote_store +#ifdef CONFIG_SMP +#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) +#else +#define cpu_icache_snoops_remote_store 1 +#endif +#endif + +# ifndef cpu_has_mips32r1 +# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) +# endif +# ifndef cpu_has_mips32r2 +# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) +# endif +# ifndef cpu_has_mips64r1 +# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) +# endif +# ifndef cpu_has_mips64r2 +# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) +# endif + +/* + * Shortcuts ... + */ +#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) +#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) +#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) +#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) +#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ + cpu_has_mips64r1 | cpu_has_mips64r2) + +#ifndef cpu_has_mips_r2_exec_hazard +#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2 +#endif + +/* + * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other + * pre-MIPS32/MIPS53 processors have CLO, CLZ. The IDT RC64574 is 64-bit and + * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels + * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. + */ +# ifndef cpu_has_clo_clz +# define cpu_has_clo_clz cpu_has_mips_r +# endif + +#ifndef cpu_has_dsp +#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) +#endif + +#ifndef cpu_has_mipsmt +#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) +#endif + +#ifndef cpu_has_userlocal +#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) +#endif + +#ifdef CONFIG_32BIT +# ifndef cpu_has_nofpuex +# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) +# endif +# ifndef cpu_has_64bits +# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) +# endif +# ifndef cpu_has_64bit_zero_reg +# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) +# endif +# ifndef cpu_has_64bit_gp_regs +# define cpu_has_64bit_gp_regs 0 +# endif +# ifndef cpu_has_64bit_addresses +# define cpu_has_64bit_addresses 0 +# endif +# ifndef cpu_vmbits +# define cpu_vmbits 31 +# endif +#endif + +#ifdef CONFIG_64BIT +# ifndef cpu_has_nofpuex +# define cpu_has_nofpuex 0 +# endif +# ifndef cpu_has_64bits +# define cpu_has_64bits 1 +# endif +# ifndef cpu_has_64bit_zero_reg +# define cpu_has_64bit_zero_reg 1 +# endif +# ifndef cpu_has_64bit_gp_regs +# define cpu_has_64bit_gp_regs 1 +# endif +# ifndef cpu_has_64bit_addresses +# define cpu_has_64bit_addresses 1 +# endif +# ifndef cpu_vmbits +# define cpu_vmbits cpu_data[0].vmbits +# define __NEED_VMBITS_PROBE +# endif +#endif + +#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) +# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) +#elif !defined(cpu_has_vint) +# define cpu_has_vint 0 +#endif + +#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) +# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) +#elif !defined(cpu_has_veic) +# define cpu_has_veic 0 +#endif + +#ifndef cpu_has_inclusive_pcaches +#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES) +#endif + +#ifndef cpu_dcache_line_size +#define cpu_dcache_line_size() cpu_data[0].dcache.linesz +#endif +#ifndef cpu_icache_line_size +#define cpu_icache_line_size() cpu_data[0].icache.linesz +#endif +#ifndef cpu_scache_line_size +#define cpu_scache_line_size() cpu_data[0].scache.linesz +#endif + +#ifndef cpu_hwrena_impl_bits +#define cpu_hwrena_impl_bits 0 +#endif + +#endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h new file mode 100644 index 0000000000..6701730465 --- /dev/null +++ b/arch/mips/include/asm/cpu-info.h @@ -0,0 +1,71 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 Waldorf GMBH + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle + * Copyright (C) 1996 Paul M. Antoine + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2004 Maciej W. Rozycki + */ +#ifndef __ASM_CPU_INFO_H +#define __ASM_CPU_INFO_H + +#include <linux/types.h> + +/* + * Descriptor for a cache + */ +struct cache_desc { + unsigned int waysize; /* Bytes per way */ + unsigned short sets; /* Number of lines per set */ + unsigned char ways; /* Number of ways */ + unsigned char linesz; /* Size of line in bytes */ + unsigned char waybit; /* Bits to select in a cache set */ + unsigned char flags; /* Flags describing cache properties */ +}; + +/* + * Flag definitions + */ +#define MIPS_CACHE_NOT_PRESENT 0x00000001 +#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */ +#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */ +#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */ +#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */ +#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ + +struct cpuinfo_mips { + unsigned int udelay_val; + unsigned int asid_cache; + + /* + * Capability and feature descriptor structure for MIPS CPU + */ + unsigned long options; + unsigned long ases; + unsigned int processor_id; + unsigned int fpu_id; + unsigned int cputype; + int isa_level; + int tlbsize; + struct cache_desc icache; /* Primary I-cache */ + struct cache_desc dcache; /* Primary D or combined I/D cache */ + struct cache_desc scache; /* Secondary cache */ + struct cache_desc tcache; /* Tertiary/split secondary cache */ + int srsets; /* Shadow register sets */ + int core; /* physical core number */ +#ifdef CONFIG_64BIT + int vmbits; /* Virtual memory size in bits */ +#endif +}; + +extern struct cpuinfo_mips cpu_data[]; +#define current_cpu_data cpu_data[0] + +extern void cpu_probe(void); + +extern const char *__cpu_name; + +#endif /* __ASM_CPU_INFO_H */ diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h new file mode 100644 index 0000000000..e63f847f2b --- /dev/null +++ b/arch/mips/include/asm/cpu.h @@ -0,0 +1,143 @@ +/* + * cpu.h: Values of the PRId register used to match up + * various MIPS cpu types. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 2004 Maciej W. Rozycki + */ +#ifndef _ASM_CPU_H +#define _ASM_CPU_H + +/* Assigned Company values for bits 23:16 of the PRId Register + (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from + MTI, the PRId register is defined in this (backwards compatible) + way: + + +----------------+----------------+----------------+----------------+ + | Company Options| Company ID | Processor ID | Revision | + +----------------+----------------+----------------+----------------+ + 31 24 23 16 15 8 7 + + I don't have docs for all the previous processors, but my impression is + that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 + spec. +*/ + +#define PRID_COMP_LEGACY 0x000000 +#define PRID_COMP_MIPS 0x010000 +#define PRID_COMP_BROADCOM 0x020000 +#define PRID_COMP_INGENIC 0xd00000 + +#define PRID_IMP_UNKNOWN 0xff00 + +/* + * These are the PRID's for when 23:16 == PRID_COMP_MIPS + */ + +#define PRID_IMP_24K 0x9300 +#define PRID_IMP_24KE 0x9600 + +/* + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM + */ + +#define PRID_IMP_BMIPS3300 0x9000 + +/* + * These are the PRID's for when 23:16 == PRID_COMP_INGENIC + */ + +#define PRID_IMP_JZRISC 0x0200 + +/* + * Older processors used to encode processor version and revision in two + * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores + * have switched to use the 8-bits as 3:3:2 bitfield with the last field as + * the patch number. *ARGH* + */ +#define PRID_REV_ENCODE_44(ver, rev) \ + ((ver) << 4 | (rev)) +#define PRID_REV_ENCODE_332(ver, rev, patch) \ + ((ver) << 5 | (rev) << 2 | (patch)) + +/* + * FPU implementation/revision register (CP1 control register 0). + * + * +---------------------------------+----------------+----------------+ + * | 0 | Implementation | Revision | + * +---------------------------------+----------------+----------------+ + * 31 16 15 8 7 0 + */ + +#define FPIR_IMP_NONE 0x0000 + +enum cpu_type_enum { + CPU_UNKNOWN, + + /* + * MIPS32 class processors + */ + CPU_24K, + CPU_BMIPS3300, + CPU_JZRISC, + + CPU_LAST +}; + +/* + * ISA Level encodings + * + */ +#define MIPS_CPU_ISA_I 0x00000001 +#define MIPS_CPU_ISA_II 0x00000002 +#define MIPS_CPU_ISA_III 0x00000004 +#define MIPS_CPU_ISA_IV 0x00000008 +#define MIPS_CPU_ISA_V 0x00000010 +#define MIPS_CPU_ISA_M32R1 0x00000020 +#define MIPS_CPU_ISA_M32R2 0x00000040 +#define MIPS_CPU_ISA_M64R1 0x00000080 +#define MIPS_CPU_ISA_M64R2 0x00000100 + +#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ + MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 ) +#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ + MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) + +/* + * CPU Option encodings + */ +#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ +#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */ +#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ +#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ +#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ +#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */ +#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */ +#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */ +#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */ +#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ +#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ +#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ +#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ +#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ +#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ +#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ +#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ +#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */ +#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ +#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ +#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ +#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ +#define MIPS_CPU_CP2 0x00400000 /* CPU has CP2 */ + +/* + * CPU ASE encodings + */ +#define MIPS_ASE_MIPS16 0x00000001 /* code compression */ +#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ +#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ +#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ +#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ +#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ + +#endif /* _ASM_CPU_H */ diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 85aa19418d..b99bb71837 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -4,6 +4,10 @@ obj-y += lshrdi3.o obj-y += ashldi3.o obj-y += ashrdi3.o obj-y += memory.o +obj-y += cpu-probe.o + +obj-$(CONFIG_CPU_MIPS32) += c-r4k.o +obj-$(CONFIG_CPU_MIPS64) += c-r4k.o obj-$(CONFIG_CMD_MIPS_CPUINFO) += cpuinfo.o obj-$(CONFIG_CMD_BOOTM) += bootm.o diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c new file mode 100644 index 0000000000..01b8665193 --- /dev/null +++ b/arch/mips/lib/c-r4k.c @@ -0,0 +1,97 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 David S. Miller (davem@davemloft.net) + * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + */ +#include <common.h> +#include <asm/io.h> +#include <asm/mipsregs.h> +#include <asm/cpu.h> +#include <asm/cpu-info.h> +#include <asm/bitops.h> + +void r4k_cache_init(void); + +static void probe_pcache(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int icache_size, dcache_size; + unsigned int config = read_c0_config(); + unsigned long config1; + unsigned int lsize; + + switch (c->cputype) { + + default: + /* + * So we seem to be a MIPS32 or MIPS64 CPU + * So let's probe the I-cache ... + */ + config1 = read_c0_config1(); + + if ((lsize = ((config1 >> 19) & 7))) + c->icache.linesz = 2 << lsize; + else + c->icache.linesz = lsize; + c->icache.sets = 64 << ((config1 >> 22) & 7); + c->icache.ways = 1 + ((config1 >> 16) & 7); + + icache_size = c->icache.sets * + c->icache.ways * + c->icache.linesz; + c->icache.waybit = __ffs(icache_size/c->icache.ways); + + if (config & 0x8) /* VI bit */ + c->icache.flags |= MIPS_CACHE_VTAG; + + /* + * Now probe the MIPS32 / MIPS64 data cache. + */ + c->dcache.flags = 0; + + if ((lsize = ((config1 >> 10) & 7))) + c->dcache.linesz = 2 << lsize; + else + c->dcache.linesz= lsize; + c->dcache.sets = 64 << ((config1 >> 13) & 7); + c->dcache.ways = 1 + ((config1 >> 7) & 7); + + dcache_size = c->dcache.sets * + c->dcache.ways * + c->dcache.linesz; + c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); + + c->options |= MIPS_CPU_PREFETCH; + break; + } + + /* compute a couple of other cache variables */ + c->icache.waysize = icache_size / c->icache.ways; + c->dcache.waysize = dcache_size / c->dcache.ways; + + c->icache.sets = c->icache.linesz ? + icache_size / (c->icache.linesz * c->icache.ways) : 0; + c->dcache.sets = c->dcache.linesz ? + dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; + + /* + * R10000 and R12000 P-caches are odd in a positive way. They're 32kB + * 2-way virtually indexed so normally would suffer from aliases. So + * normally they'd suffer from aliases but magic in the hardware deals + * with that for us so we don't need to take care ourselves. + */ + switch (c->cputype) { + default: + if (c->dcache.waysize > PAGE_SIZE) + c->dcache.flags |= MIPS_CACHE_ALIASES; + } +} + +void r4k_cache_init(void) +{ + probe_pcache(); +} diff --git a/arch/mips/lib/cpu-probe.c b/arch/mips/lib/cpu-probe.c new file mode 100644 index 0000000000..de45421df7 --- /dev/null +++ b/arch/mips/lib/cpu-probe.c @@ -0,0 +1,143 @@ +/* + * Processor capabilities determination functions. + * + * Copyright (C) xxxx the Anonymous + * Copyright (C) 1994 - 2006 Ralf Baechle + * Copyright (C) 2003, 2004 Maciej W. Rozycki + * Copyright (C) 2001, 2004 MIPS Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include <common.h> +#include <asm/mipsregs.h> +#include <asm/cpu-info.h> +#include <asm/cpu.h> + +const char *__cpu_name; +struct cpuinfo_mips cpu_data[1]; + +static char unknown_isa[] = KERN_ERR \ + "Unsupported ISA type, c0.config0: %d."; + +static inline unsigned int decode_config0(struct cpuinfo_mips *c) +{ + unsigned int config0; + int isa; + + config0 = read_c0_config(); + + if (((config0 & MIPS_CONF_MT) >> 7) == 1) + c->options |= MIPS_CPU_TLB; + isa = (config0 & MIPS_CONF_AT) >> 13; + switch (isa) { + case 0: + switch ((config0 & MIPS_CONF_AR) >> 10) { + case 0: + c->isa_level = MIPS_CPU_ISA_M32R1; + break; + case 1: + c->isa_level = MIPS_CPU_ISA_M32R2; + break; + default: + goto unknown; + } + break; + case 2: + switch ((config0 & MIPS_CONF_AR) >> 10) { + case 0: + c->isa_level = MIPS_CPU_ISA_M64R1; + break; + case 1: + c->isa_level = MIPS_CPU_ISA_M64R2; + break; + default: + goto unknown; + } + break; + default: + goto unknown; + } + + return config0 & MIPS_CONF_M; + +unknown: + panic(unknown_isa, config0); +} + +static void decode_configs(struct cpuinfo_mips *c) +{ + int ok; + + /* MIPS32 or MIPS64 compliant CPU. */ + c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | + MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; + + c->scache.flags = MIPS_CACHE_NOT_PRESENT; + + ok = decode_config0(c); /* Read Config registers. */ + BUG_ON(!ok); /* Arch spec violation! */ +} + +static inline void cpu_probe_mips(struct cpuinfo_mips *c) +{ + decode_configs(c); + switch (c->processor_id & 0xff00) { + case PRID_IMP_24K: + case PRID_IMP_24KE: + c->cputype = CPU_24K; + __cpu_name = "MIPS 24Kc"; + break; + } +} + +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c) +{ + decode_configs(c); + switch (c->processor_id & 0xff00) { + case PRID_IMP_BMIPS3300: + c->cputype = CPU_BMIPS3300; + __cpu_name = "Broadcom BMIPS3300"; + break; + } +} + +static inline void cpu_probe_ingenic(struct cpuinfo_mips *c) +{ + decode_configs(c); + /* JZRISC does not implement the CP0 counter. */ + c->options &= ~MIPS_CPU_COUNTER; + switch (c->processor_id & 0xff00) { + case PRID_IMP_JZRISC: + c->cputype = CPU_JZRISC; + __cpu_name = "Ingenic JZRISC"; + break; + default: + panic("Unknown Ingenic Processor ID!"); + break; + } +} + +void cpu_probe(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + + c->processor_id = PRID_IMP_UNKNOWN; + c->fpu_id = FPIR_IMP_NONE; + c->cputype = CPU_UNKNOWN; + + c->processor_id = read_c0_prid(); + switch (c->processor_id & 0xff0000) { + case PRID_COMP_MIPS: + cpu_probe_mips(c); + break; + case PRID_COMP_BROADCOM: + cpu_probe_broadcom(c); + break; + case PRID_COMP_INGENIC: + cpu_probe_ingenic(c); + break; + } +} diff --git a/arch/mips/lib/cpuinfo.c b/arch/mips/lib/cpuinfo.c index fc8fb00f0f..c0bb87a5fe 100644 --- a/arch/mips/lib/cpuinfo.c +++ b/arch/mips/lib/cpuinfo.c @@ -23,11 +23,34 @@ #include <common.h> #include <command.h> #include <asm/mipsregs.h> +#include <asm/cpu-info.h> + +static char *way_string[] = { NULL, "direct mapped", "2-way", + "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" +}; static int do_cpuinfo(int argc, char *argv[]) { - printf("CP0_PRID = 0x%08x\n", read_c0_prid()); - printf("CP0_CONFIG = 0x%08x\n", read_c0_config()); + unsigned int icache_size, dcache_size; + struct cpuinfo_mips *c = ¤t_cpu_data; + + printk(KERN_INFO "CPU revision is: %08x (%s)\n", + current_cpu_data.processor_id, __cpu_name); + + icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; + dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; + + printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", + icache_size >> 10, + c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", + way_string[c->icache.ways], c->icache.linesz); + + printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", + dcache_size >> 10, way_string[c->dcache.ways], + (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", + (c->dcache.flags & MIPS_CACHE_ALIASES) ? + "cache aliases" : "no aliases", + c->dcache.linesz); return 0; } diff --git a/defaultenv-2/base/init/automount b/defaultenv-2/base/init/automount index e02922217a..63099f9c38 100644 --- a/defaultenv-2/base/init/automount +++ b/defaultenv-2/base/init/automount @@ -8,20 +8,20 @@ fi # automount server returned from dhcp server mkdir -p /mnt/tftp-dhcp -automount /mnt/tftp-dhcp 'ifup eth0; mount $eth0.serverip tftp /mnt/tftp-dhcp' +automount /mnt/tftp-dhcp 'ifup eth0 && mount $eth0.serverip tftp /mnt/tftp-dhcp' # automount nfs server example #nfshost=somehost #mkdir -p /mnt/${nfshost} -#automount /mnt/$nfshost "ifup eth0; mount ${nfshost}:/tftpboot nfs /mnt/${nfshost}" +#automount /mnt/$nfshost "ifup eth0 && mount ${nfshost}:/tftpboot nfs /mnt/${nfshost}" # static tftp server example #mkdir -p /mnt/tftp -#automount -d /mnt/tftp 'ifup eth0; mount $serverip tftp /mnt/tftp' +#automount -d /mnt/tftp 'ifup eth0 && mount $serverip tftp /mnt/tftp' # FAT on usb disk example #mkdir -p /mnt/fat -#automount -d /mnt/fat 'usb; mount /dev/usbdisk0.0 fat $automount_path' +#automount -d /mnt/fat 'usb && [ -e /dev/disk0.0 ] && mount /dev/disk0.0 fat /mnt/fat' diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index ae2b41ed53..a2473a9141 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -858,7 +858,7 @@ static int ehci_probe(struct device_d *dev) uint32_t reg; struct ehci_platform_data *pdata = dev->platform_data; - ehci = xmalloc(sizeof(struct ehci_priv)); + ehci = xzalloc(sizeof(struct ehci_priv)); host = &ehci->host; dev->priv = ehci; diff --git a/drivers/usb/storage/usb.c b/drivers/usb/storage/usb.c index fa3691af15..2adc2ef508 100644 --- a/drivers/usb/storage/usb.c +++ b/drivers/usb/storage/usb.c @@ -613,7 +613,7 @@ static struct usb_device_id usb_storage_usb_ids[] = { ***********************************************************************/ static struct usb_driver usb_storage_driver = { - .driver.name = "usb-storage", + .name = "usb-storage", .id_table = usb_storage_usb_ids, .probe = usb_stor_probe, .disconnect = usb_stor_disconnect, |