diff options
| -rw-r--r-- | arch/arm/boards/scb9328/lowlevel_init.S | 51 |
1 files changed, 0 insertions, 51 deletions
diff --git a/arch/arm/boards/scb9328/lowlevel_init.S b/arch/arm/boards/scb9328/lowlevel_init.S index d7afa21b23..4250c95dfb 100644 --- a/arch/arm/boards/scb9328/lowlevel_init.S +++ b/arch/arm/boards/scb9328/lowlevel_init.S @@ -15,61 +15,10 @@ #include <mach/imx1-regs.h> #include <asm/barebox-arm-head.h> -#define CPU200 - -#ifdef CPU200 #define CFG_MPCTL0_VAL 0x00321431 -#else -#define CFG_MPCTL0_VAL 0x040e200e -#endif - -#define BUS72 - -#ifdef BUS72 #define CFG_SPCTL0_VAL 0x04002400 -#endif - -#ifdef BUS96 -#define CFG_SPCTL0_VAL 0x04001800 -#endif - -#ifdef BUS64 -#define CFG_SPCTL0_VAL 0x08001800 -#endif - -/* Das ist der BCLK Divider, der aus der System PLL - BCLK und HCLK erzeugt: - 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0 - 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2 - 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2 - 0x2f001003 : 192MHz/5=38,4MHz - 0x2f000003 : 64MHz/1 - Bit 22: SPLL Restart - Bit 21: MPLL Restart */ - -#ifdef BUS64 -#define CFG_CSCR_VAL 0x2f030003 -#endif - -#ifdef BUS72 #define CFG_CSCR_VAL 0x2f030403 -#endif -/* Bit[0:3] contain PERCLK1DIV for UART 1 - 0x000b00b ->b<- -> 192MHz/12=16MHz - 0x000b00b ->8<- -> 144MHz/09=16MHz - 0x000b00b ->3<- -> 64MHz/4=16MHz */ - -#ifdef BUS96 -#define CFG_PCDR_VAL 0x000b00b5 -#endif - -#ifdef BUS64 -#define CFG_PCDR_VAL 0x000b00b3 -#endif - -#ifdef BUS72 #define CFG_PCDR_VAL 0x000b00b8 -#endif #define writel(val, reg) \ ldr r0, =reg; \ |