diff options
| -rw-r--r-- | arch/arm/Kconfig | 11 | ||||
| -rw-r--r-- | arch/arm/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/configs/mx21ads_defconfig | 203 | ||||
| -rw-r--r-- | arch/arm/mach-imx/Kconfig | 7 | ||||
| -rw-r--r-- | arch/arm/mach-imx/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/mach-imx/clocksource.c | 9 | ||||
| -rw-r--r-- | arch/arm/mach-imx/imx21.c | 27 | ||||
| -rw-r--r-- | arch/arm/mach-imx/speed-imx21.c | 169 | ||||
| -rw-r--r-- | drivers/nand/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/serial/serial_imx.c | 2 | ||||
| -rw-r--r-- | include/asm-arm/arch-imx/imx-regs.h | 2 | ||||
| -rw-r--r-- | include/asm-arm/arch-imx/imx21-regs.h | 150 |
12 files changed, 578 insertions, 6 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a5e34c51ee..5fd843ab18 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -8,6 +8,7 @@ config ARCH_TEXT_BASE default 0x81f00000 if MACH_NXDB500 default 0x21e00000 if MACH_ECO920 default 0xa0000000 if MACH_PCM038 + default 0xc0000000 if MACH_IMX21ADS default 0xa0000000 if MACH_IMX27ADS default 0x87f00000 if MACH_PCM037 default 0x23f00000 if MACH_AT91SAM9260_EK @@ -19,6 +20,7 @@ config BOARDINFO default "Synertronixx scb9328" if MACH_SCB9328 default "Hilscher Netx nxdb500" if MACH_NXDB500 default "Phytec phyCORE-i.MX27" if MACH_PCM038 + default "Freescale i.MX21 ADS" if MACH_IMX21ADS default "Freescale i.MX27 ADS" if MACH_IMX27ADS default "Phytec phyCORE-i.MX31" if MACH_PCM037 default "Atmel 91SAM9260-EK" if MACH_AT91SAM9260_EK @@ -104,6 +106,15 @@ config MACH_PCM038 Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped with a Freescale i.MX27 Processor +config MACH_IMX21ADS + bool "Freescale i.MX21ADS" + select HAS_CFI + select ARCH_IMX21 + select MACH_HAS_LOWLEVEL_INIT + help + Say Y here if you are using the Freescale i.MX21ads board equipped + with a Freescale i.MX21 Processor + config MACH_IMX27ADS bool "Freescale i.MX27ADS" select HAS_CFI diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5f85a3f142..1dcf5f7ecf 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -11,6 +11,7 @@ board-$(CONFIG_MACH_MX1ADS) := mx1ads board-$(CONFIG_MACH_ECO920) := eco920 board-$(CONFIG_MACH_SCB9328) := scb9328 board-$(CONFIG_MACH_PCM038) := pcm038 +board-$(CONFIG_MACH_IMX21ADS) := imx21ads board-$(CONFIG_MACH_IMX27ADS) := imx27ads board-$(CONFIG_MACH_NXDB500) := netx board-$(CONFIG_MACH_PCM037) := pcm037 diff --git a/arch/arm/configs/mx21ads_defconfig b/arch/arm/configs/mx21ads_defconfig new file mode 100644 index 0000000000..077778577c --- /dev/null +++ b/arch/arm/configs/mx21ads_defconfig @@ -0,0 +1,203 @@ +# +# Automatically generated make config: don't edit +# U-Boot version: 2.0.0-rc7 +# Thu Apr 2 15:40:41 2009 +# +CONFIG_ARCH_TEXT_BASE=0xc0000000 +CONFIG_BOARDINFO="Freescale i.MX21 ADS" +# CONFIG_BOARD_LINKER_SCRIPT is not set +CONFIG_GENERIC_LINKER_SCRIPT=y +CONFIG_ARM=y +CONFIG_ARM926EJS=y +CONFIG_ARCH_IMX=y +CONFIG_ARCH_IMX21=y +# CONFIG_MACH_MX1ADS is not set +# CONFIG_MACH_SCB9328 is not set +# CONFIG_MACH_PCM038 is not set +CONFIG_MACH_IMX21ADS=y +# CONFIG_MACH_IMX27ADS is not set +# CONFIG_MACH_PCM043 is not set +# CONFIG_MACH_FREESCALE_MX35_3STACK is not set +# CONFIG_MACH_ECO920 is not set +# CONFIG_MACH_NXDB500 is not set +# CONFIG_MACH_PCM037 is not set +# CONFIG_MACH_OMAP is not set +# CONFIG_MACH_AT91SAM9260_EK is not set +# CONFIG_MACH_PM9263 is not set + +# +# Board specific settings +# + +# +# i.MX specific settings +# +CONFIG_IMX_CLKO=y + +# +# Arm specific settings +# +CONFIG_CMD_ARM_CPUINFO=y +CONFIG_CMDLINE_TAG=y +CONFIG_SETUP_MEMORY_TAGS=y +# CONFIG_INITRD_TAG is not set +CONFIG_GREGORIAN_CALENDER=y +CONFIG_HAS_KALLSYMS=y +CONFIG_HAS_MODULES=y +CONFIG_CMD_MEMORY=y +CONFIG_ENV_HANDLING=y + +# +# General Settings +# +CONFIG_LOCALVERSION_AUTO=y + +# +# memory layout +# +CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y +CONFIG_TEXT_BASE=0xc1000000 +CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y +CONFIG_MEMORY_LAYOUT_DEFAULT=y +# CONFIG_MEMORY_LAYOUT_FIXED is not set +CONFIG_STACK_SIZE=0x8000 +CONFIG_MALLOC_SIZE=0x400000 +# CONFIG_BROKEN is not set +# CONFIG_EXPERIMENTAL is not set +CONFIG_MACH_HAS_LOWLEVEL_INIT=y +CONFIG_MACH_DO_LOWLEVEL_INIT=y +CONFIG_PROMPT="uboot:" +CONFIG_BAUDRATE=115200 +CONFIG_LONGHELP=y +CONFIG_CBSIZE=1024 +CONFIG_MAXARGS=16 +CONFIG_SHELL_HUSH=y +# CONFIG_SHELL_SIMPLE is not set +# CONFIG_GLOB is not set +CONFIG_PROMPT_HUSH_PS2="> " +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_DYNAMIC_CRC_TABLE=y +CONFIG_ERRNO_MESSAGES=y +CONFIG_TIMESTAMP=y +CONFIG_CONSOLE_FULL=y +CONFIG_CONSOLE_ACTIVATE_FIRST=y +# CONFIG_OF_FLAT_TREE is not set +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="board/imx21ads/env" + +# +# Debugging +# +# CONFIG_DEBUG_INFO is not set +# CONFIG_ENABLE_FLASH_NOISE is not set +# CONFIG_ENABLE_PARTITION_NOISE is not set +# CONFIG_ENABLE_DEVICE_NOISE is not set + +# +# Commands +# + +# +# scripting +# +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TRUE=y +CONFIG_CMD_FALSE=y + +# +# file commands +# +CONFIG_CMD_LS=y +CONFIG_CMD_RM=y +CONFIG_CMD_CAT=y +CONFIG_CMD_MKDIR=y +CONFIG_CMD_RMDIR=y +CONFIG_CMD_CP=y +CONFIG_CMD_PWD=y +CONFIG_CMD_CD=y +CONFIG_CMD_MOUNT=y +CONFIG_CMD_UMOUNT=y + +# +# console +# +CONFIG_CMD_CLEAR=y +CONFIG_CMD_ECHO=y + +# +# memory +# +# CONFIG_CMD_LOADB is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_CRC=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y + +# +# flash +# +CONFIG_CMD_FLASH=y + +# +# booting +# +CONFIG_CMD_BOOTM=y +# CONFIG_CMD_BOOTM_ZLIB is not set +# CONFIG_CMD_BOOTM_BZLIB is not set +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_TEST=y +CONFIG_CMD_VERSION=y +CONFIG_CMD_HELP=y +CONFIG_CMD_DEVINFO=y +# CONFIG_NET is not set + +# +# Drivers +# + +# +# serial drivers +# +CONFIG_DRIVER_SERIAL_IMX=y +# CONFIG_DRIVER_SERIAL_NS16550 is not set + +# +# SPI drivers +# +# CONFIG_SPI is not set + +# +# flash drivers +# +CONFIG_HAS_CFI=y +CONFIG_DRIVER_CFI=y +CONFIG_DRIVER_CFI_NEW=y +# CONFIG_DRIVER_CFI_INTEL is not set +CONFIG_DRIVER_CFI_AMD=y +CONFIG_DRIVER_CFI_BANK_WIDTH_1=y +CONFIG_DRIVER_CFI_BANK_WIDTH_2=y +CONFIG_DRIVER_CFI_BANK_WIDTH_4=y +# CONFIG_DRIVER_CFI_BANK_WIDTH_8 is not set +CONFIG_CFI_BUFFER_WRITE=y +# CONFIG_NAND is not set + +# +# Filesystem support +# +# CONFIG_FS_CRAMFS is not set +CONFIG_FS_RAMFS=y +CONFIG_FS_DEVFS=y +CONFIG_CRC32=y +# CONFIG_GENERIC_FIND_NEXT_BIT is not set diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index a713c205ed..efa608b216 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -12,6 +12,11 @@ config ARCH_IMX1 select ARCH_IMX select ARM920T +config ARCH_IMX21 + bool + select ARCH_IMX + select ARM926EJS + config ARCH_IMX27 bool select ARCH_IMX @@ -52,7 +57,7 @@ endmenu menu "i.MX specific settings " config IMX_CLKO bool "clko command" - depends on ARCH_IMX27 || ARCH_IMX35 + depends on ARCH_IMX21 || ARCH_IMX27 || ARCH_IMX35 help The i.MX SoCs have a Pin which can output different reference frequencies. Say y here if you want to have the clko command which lets you select the diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 1a062704d7..c9bc8434bb 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -1,5 +1,6 @@ obj-y += clocksource.o obj-$(CONFIG_ARCH_IMX1) += speed-imx1.o gpio.o +obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o gpio.o imx21.o obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o gpio.o imx27.o obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o iomux-v2.o obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o gpio-imx35.o diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c index a0fd61e39e..1abe65ebde 100644 --- a/arch/arm/mach-imx/clocksource.c +++ b/arch/arm/mach-imx/clocksource.c @@ -54,6 +54,9 @@ static int clocksource_init (void) /* setup GP Timer 1 */ GPT(GPT_TCTL) = TCTL_SWR; +#ifdef CONFIG_ARCH_IMX21 + PCCR1 |= PCCR1_GPT1_EN; +#endif #ifdef CONFIG_ARCH_IMX27 PCCR0 |= PCCR0_GPT1_EN; PCCR1 |= PCCR1_PERCLK1_EN; @@ -82,11 +85,11 @@ core_initcall(clocksource_init); void reset_cpu (ulong ignored) { /* Disable watchdog and set Time-Out field to 0 */ - WCR = 0x00000000; + WCR = 0x0000; /* Write Service Sequence */ - WSR = 0x00005555; - WSR = 0x0000AAAA; + WSR = 0x5555; + WSR = 0xAAAA; /* Enable watchdog */ WCR = WCR_WDE; diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c new file mode 100644 index 0000000000..90b1eef99c --- /dev/null +++ b/arch/arm/mach-imx/imx21.c @@ -0,0 +1,27 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/imx-regs.h> + +int imx_silicon_revision(void) +{ + // Known values: + // 0x101D101D : mask set ID 0M55B + // 0x201D101D : mask set ID 1M55B or M55B + return CID; +} diff --git a/arch/arm/mach-imx/speed-imx21.c b/arch/arm/mach-imx/speed-imx21.c new file mode 100644 index 0000000000..ff5278a3a1 --- /dev/null +++ b/arch/arm/mach-imx/speed-imx21.c @@ -0,0 +1,169 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/generic.h> +#include <asm/arch/clock.h> +#include <init.h> + +#ifndef CLK32 +#define CLK32 32768 +#endif + +static ulong clk_in_32k(void) +{ + return 512 * CLK32; +} + +static ulong clk_in_26m(void) +{ + if (CSCR & CSCR_OSC26M_DIV1P5) { + /* divide by 1.5 */ + return 173333333; + } else { + /* divide by 1 */ + return 26000000; + } +} + +ulong imx_get_mpllclk(void) +{ + ulong cscr = CSCR; + ulong fref; + + if (cscr & CSCR_MCU_SEL) + fref = clk_in_26m(); + else + fref = clk_in_32k(); + + return imx_decode_pll(MPCTL0, fref); +} + +ulong imx_get_armclk(void) +{ + ulong cscr = CSCR; + ulong fref = imx_get_mpllclk(); + ulong div; + + div = ((cscr >> 10) & 0x7) + 1; + + return fref / div; +} + +ulong imx_get_spllclk(void) +{ + ulong cscr = CSCR; + ulong spctl0; + ulong fref; + + if (cscr & CSCR_SP_SEL) + fref = clk_in_26m(); + else + fref = clk_in_32k(); + + spctl0 = SPCTL0; + SPCTL0 = spctl0; + return imx_decode_pll(spctl0, fref); +} + +static ulong imx_decode_perclk(ulong div) +{ + return imx_get_mpllclk() / div; +} + +ulong imx_get_perclk1(void) +{ + return imx_decode_perclk((PCDR1 & 0x3f) + 1); +} + +ulong imx_get_perclk2(void) +{ + return imx_decode_perclk(((PCDR1 >> 8) & 0x3f) + 1); +} + +ulong imx_get_perclk3(void) +{ + return imx_decode_perclk(((PCDR1 >> 16) & 0x3f) + 1); +} + +ulong imx_get_perclk4(void) +{ + return imx_decode_perclk(((PCDR1 >> 24) & 0x3f) + 1); +} + +ulong imx_get_uartclk(void) +{ + return imx_get_perclk1(); +} + +ulong imx_get_gptclk(void) +{ + return imx_decode_perclk((PCDR1 & 0x3f) + 1); +} + +int imx_dump_clocks(void) +{ + uint32_t cid = CID; + + printf("chip id: [%08x]\n", cid); + printf("mpll: %10d Hz\n", imx_get_mpllclk()); + printf("spll: %10d Hz\n", imx_get_spllclk()); + printf("arm: %10d Hz\n", imx_get_armclk()); + printf("perclk1: %10d Hz\n", imx_get_perclk1()); + printf("perclk2: %10d Hz\n", imx_get_perclk2()); + printf("perclk3: %10d Hz\n", imx_get_perclk3()); + printf("perclk4: %10d Hz\n", imx_get_perclk4()); + printf("clkin26: %10d Hz\n", clk_in_26m()); + return 0; +} + +late_initcall(imx_dump_clocks); + +/* + * Set the divider of the CLKO pin (when CLK48DIV_CLKO is chosen). + * Returns the new divider (which may be smaller + * than the desired one) + */ +int imx_clko_set_div(int div) +{ + ulong pcdr; + div--; + div &= 0x7; + + pcdr = PCDR0 & ~(7 << 5); + pcdr |= div << 5; + PCDR0 = pcdr; + + return div + 1; +} + +/* + * Set the clock source for the CLKO pin + */ +void imx_clko_set_src(int src) +{ + unsigned long ccsr; + + if (src < 0) { + return; + } + + ccsr = CCSR & ~0x1f; + ccsr |= src & 0x1f; + CCSR = ccsr; +} diff --git a/drivers/nand/Kconfig b/drivers/nand/Kconfig index 2b93b0cf11..4f238dfa6b 100644 --- a/drivers/nand/Kconfig +++ b/drivers/nand/Kconfig @@ -11,7 +11,7 @@ if NAND config NAND_IMX bool prompt "i.MX NAND driver" - depends on ARCH_IMX27 || ARCH_IMX31 + depends on ARCH_IMX21 || ARCH_IMX27 || ARCH_IMX31 config NAND_IMX_BOOT bool diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c index 35f18700bd..94ca027d06 100644 --- a/drivers/serial/serial_imx.c +++ b/drivers/serial/serial_imx.c @@ -153,7 +153,7 @@ # define UCR3_VAL 0 # define UCR4_VAL (UCR4_CTSTL_32 | UCR4_REF16) #endif -#ifdef CONFIG_ARCH_IMX27 +#if defined CONFIG_ARCH_IMX21 || defined CONFIG_ARCH_IMX27 # define UCR1_VAL (UCR1_UARTCLKEN) # define UCR3_VAL (0x700 | UCR3_RXDMUXSEL) # define UCR4_VAL UCR4_CTSTL_32 diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h index 7149fa88a0..9e530dcdff 100644 --- a/include/asm-arm/arch-imx/imx-regs.h +++ b/include/asm-arm/arch-imx/imx-regs.h @@ -41,6 +41,8 @@ #ifdef CONFIG_ARCH_IMX1 # include <asm/arch/imx1-regs.h> +#elif defined CONFIG_ARCH_IMX21 +# include <asm/arch/imx21-regs.h> #elif defined CONFIG_ARCH_IMX27 # include <asm/arch/imx27-regs.h> #elif defined CONFIG_ARCH_IMX31 diff --git a/include/asm-arm/arch-imx/imx21-regs.h b/include/asm-arm/arch-imx/imx21-regs.h new file mode 100644 index 0000000000..b8cb06075f --- /dev/null +++ b/include/asm-arm/arch-imx/imx21-regs.h @@ -0,0 +1,150 @@ +#ifndef _IMX21_REGS_H +#define _IMX21_REGS_H + +#ifndef _IMX_REGS_H +#error "Please do not include directly" +#endif + +#define IMX_IO_BASE 0x10000000 + +#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) +#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) +#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) +#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) +#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) +#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) +#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) +#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) +#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) +#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) +#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) +#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) +#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) + +#define IMX_SDRAM_BASE (0xdf000000) +#define IMX_EIM_BASE (0xdf001000) +#define IMX_NFC_BASE (0xdf003000) + +/* AIPI */ +#define AIPI1_PSR0 __REG(IMX_AIPI1_BASE + 0x00) +#define AIPI1_PSR1 __REG(IMX_AIPI1_BASE + 0x04) +#define AIPI2_PSR0 __REG(IMX_AIPI2_BASE + 0x00) +#define AIPI2_PSR1 __REG(IMX_AIPI2_BASE + 0x04) + +/* System Control */ +#define SUID0 __REG(IMX_SYSTEM_CTL_BASE + 0x4) /* Silicon ID Register (12 bytes) */ +#define SUID1 __REG(IMX_SYSTEM_CTL_BASE + 0x8) /* Silicon ID Register (12 bytes) */ +#define CID __REG(IMX_SYSTEM_CTL_BASE + 0xC) /* Silicon ID Register (12 bytes) */ +#define FMCR __REG(IMX_SYSTEM_CTL_BASE + 0x14) /* Function Multeplexing Control Register */ +#define GPCR __REG(IMX_SYSTEM_CTL_BASE + 0x18) /* Global Peripheral Control Register */ +#define WBCR __REG(IMX_SYSTEM_CTL_BASE + 0x1C) /* Well Bias Control Register */ +#define DSCR(x) __REG(IMX_SYSTEM_CTL_BASE + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ + +#define GPCR_BOOT_SHIFT 16 +#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT) +#define GPCR_BOOT_UART_USB 0 +#define GPCR_BOOT_8BIT_NAND_2k 2 +#define GPCR_BOOT_16BIT_NAND_2k 3 +#define GPCR_BOOT_16BIT_NAND_512 4 +#define GPCR_BOOT_16BIT_CS0 5 +#define GPCR_BOOT_32BIT_CS0 6 +#define GPCR_BOOT_8BIT_NAND_512 7 + +/* SDRAM Controller registers bitfields */ +#define SDCTL0 __REG(IMX_SDRAM_BASE + 0x00) /* SDRAM 0 Control Register */ +#define SDCTL1 __REG(IMX_SDRAM_BASE + 0x04) /* SDRAM 0 Control Register */ +#define SDRST __REG(IMX_SDRAM_BASE + 0x18) /* SDRAM Reset Register */ +#define SDMISC __REG(IMX_SDRAM_BASE + 0x14) /* SDRAM Miscellaneous Register */ + + +/* Chip Select Registers */ +#define CS0U __REG(IMX_EIM_BASE + 0x00) /* Chip Select 0 Upper Register */ +#define CS0L __REG(IMX_EIM_BASE + 0x04) /* Chip Select 0 Lower Register */ +#define CS1U __REG(IMX_EIM_BASE + 0x08) /* Chip Select 1 Upper Register */ +#define CS1L __REG(IMX_EIM_BASE + 0x0C) /* Chip Select 1 Lower Register */ +#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */ +#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */ +#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */ +#define CS3L __REG(IMX_EIM_BASE + 0x1C) /* Chip Select 3 Lower Register */ +#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */ +#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */ +#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */ +#define CS5L __REG(IMX_EIM_BASE + 0x2C) /* Chip Select 5 Lower Register */ +#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */ + +/* Watchdog Registers*/ +#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ +#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ +#define WRSR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Reset Status Register */ + +/* important definition of some bits of WCR */ +#define WCR_WDE 0x04 + +/* PLL registers */ +#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */ +#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */ +#define MPCTL1 __REG(IMX_PLL_BASE + 0x08) /* MCU PLL Control Register 1 */ +#define SPCTL0 __REG(IMX_PLL_BASE + 0x0c) /* System PLL Control Register 0 */ +#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ +#define OSC26MCTL __REG(IMX_PLL_BASE + 0x14) /* Oscillator 26M Register */ +#define PCDR0 __REG(IMX_PLL_BASE + 0x18) /* Peripheral Clock Divider Register 0 */ +#define PCDR1 __REG(IMX_PLL_BASE + 0x1c) /* Peripheral Clock Divider Register 1 */ +#define PCCR0 __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Control Register 0 */ +#define PCCR1 __REG(IMX_PLL_BASE + 0x24) /* Peripheral Clock Control Register 1 */ +#define CCSR __REG(IMX_PLL_BASE + 0x28) /* Clock Control Status Register */ + +#define CSCR_MPEN (1 << 0) +#define CSCR_SPEN (1 << 1) +#define CSCR_FPM_EN (1 << 2) +#define CSCR_OSC26M_DIS (1 << 3) +#define CSCR_OSC26M_DIV1P5 (1 << 4) +#define CSCR_MCU_SEL (1 << 16) +#define CSCR_SP_SEL (1 << 17) +#define CSCR_SD_CNT(d) (((d) & 0x3) << 24) +#define CSCR_USB_DIV(d) (((d) & 0x7) << 26) +#define CSCR_PRESC(d) (((d) & 0x7) << 29) + +#define MPCTL1_BRMO (1 << 6) +#define MPCTL1_LF (1 << 15) + +#define PCCR1_GPT1_EN (1 << 25) + +#define CCSR_32K_SR (1 << 15) + +#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) +#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) +#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) +#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) + +/* + * Definitions for the clocksource driver + */ +/* Part 1: Registers */ +# define GPT_TCTL 0x00 +# define GPT_TPRER 0x04 +# define GPT_TCMP 0x08 +# define GPT_TCR 0x0c +# define GPT_TCN 0x10 +# define GPT_TSTAT 0x14 + +/* Part 2: Bitfields */ +#define TCTL_SWR (1<<15) /* Software reset */ +#define TCTL_CC (1<<10) /* counter clear */ +#define TCTL_FRR (1<<8) /* Freerun / restart */ +#define TCTL_CAP (3<<6) /* Capture Edge */ +#define TCTL_CAPEN (1<<5) /* compare interrupt enable */ +#define TCTL_COMPEN (1<<4) /* compare interrupt enable */ +#define TCTL_CLKSOURCE (1) /* Clock source bit position */ +#define TCTL_TEN (1) /* Timer enable */ +#define TPRER_PRES (0xff) /* Prescale */ +#define TSTAT_CAPT (1<<1) /* Capture event */ +#define TSTAT_COMP (1) /* Compare event */ + +#define IMX_CS0_BASE 0xC8000000 +#define IMX_CS1_BASE 0xCC000000 +#define IMX_CS2_BASE 0xD0000000 +#define IMX_CS3_BASE 0xD1000000 +#define IMX_CS4_BASE 0xD2000000 +#define IMX_CS5_BASE 0xD3000000 + +#endif /* _IMX21_REGS_H */ |