diff options
188 files changed, 8273 insertions, 811 deletions
diff --git a/Documentation/boards/imx/Garz-Fricke-Vincell.rst b/Documentation/boards/imx/Garz-Fricke-Vincell.rst index 2eb5f65c64..58ab0ab42f 100644 --- a/Documentation/boards/imx/Garz-Fricke-Vincell.rst +++ b/Documentation/boards/imx/Garz-Fricke-Vincell.rst @@ -7,7 +7,7 @@ This CPU card is based on a Freescale i.MX53 CPU. The card is shipped with: * 512MiB synchronous dynamic RAM * microSD slot -see http://www.garz-fricke.com/vincell-lt-core_de.html for more information +see http://www.garz-fricke.com/en/products/embedded-systems/single-board-computer/ia-0086r/ for more information Bootstrapping barebox diff --git a/Documentation/boards/imx/amazon-kindle-mx50.rst b/Documentation/boards/imx/amazon-kindle-mx50.rst new file mode 100644 index 0000000000..1e71cd26ba --- /dev/null +++ b/Documentation/boards/imx/amazon-kindle-mx50.rst @@ -0,0 +1,58 @@ +Amazon Kindle 4/5 Model No. D01100, D01200 and EY21 +=================================================== + +The Kindle Model No. D01100 (Kindle Wi-Fi), D01200 (Kindle Touch) +and EY21 (Paperwhite) are refered as the Kindle 4th and 5th generation. +Those e-book readers share a common set of hardware: + +* a Freescale i.MX50 SOC +* 2 or 4GiB eMMC +* a MC13892 PMIC + +The older readers D01100 and D01200 use 256MiB of LPDDR1, +while the newer EY21 uses 256MiB of LPDDR2. + +The devices boot up in internal boot mode from an eMMC boot partition and +are shipped with a vendor modified u-boot imximage based on u-boot v2009.08. + +To upload and run a new bootloader the older devices can be put into +USB-downloader mode by the SOC microcode when a specific key is pressed during +startup: +* the fiveway down button on the model D01100 +* the home button on model D01200 +A new USB device "NS Blank CODEX" should appear, barebox may be uploaded using +$ scripts/imx/imx-usb-loader barebox-kindle-d01100.img +$ scripts/imx/imx-usb-loader barebox-kindle-d01200.img +Hint: keep the select button pressed down to get the barebox USB console. + +Barebox may be used as drop-in replacement for the shipped bootloader, when +the imximg fits into 258048 bytes. When installing the barebox imximg on +the eMMC take care not to overwrite the vendor supplied serial numbers stored +on the eMMC. +e.g. for the D01100 just write the imx-header and the application section: +loady -t usbserial +memcpy -b -s barebox-kindle-d01100.img -d /dev/disk0.boot0.imx_header 1024 0 2048 +memcpy -b -s barebox-kindle-d01100.img -d /dev/disk0.boot0.self 4096 0 253952 + +Note: a USB serial ACM console will be launched by a barebox init script +when +* the cursor select key is pressed during startup of model D01100 +* the home button is pressed within a second after startup of model D01200. + If you press the home button during startup, you will enter USB boot mode. +* the EY21 has no keys to press, a USB console will be launched for 10s. + +This device is battery-powered and there is no way to switch the device off. +When the device is inactive, the kindle software will first reduce the +power consumption to a few milliamps of battery power, after some minutes +the power consumption is further reduced to about 550 microamps. Switching +on iomux pullups may significantly reduce your standby-time. + +Hints to reduce the build image size. +Note that a drop-in replacement barebox imximage must not exceed 258048 bytes +since the space behind it is in use. Hence, don't build in drivers and FS +that are not required, e.g.: + NET, DISK_AHCI, DISK_INTF_PLATFORM_IDE, DISK_ATA, VIDEO, PWM, LED, + USB_STORAGE, USB_ULPI, NAND, MTD_UBI, FS_UBIFS, MFD_MC34704, MFD_MC9SDZ60, + MFD_STMPE, EEPROM_AT25, EEPROM_AT24, KEYBOARD_GPIO, PARTITION_DISK_EFI +Also unselect support for other boards to get rid of their dependencies. +Further select IMAGE_COMPRESSION_XZKERN @@ -1,5 +1,5 @@ VERSION = 2017 -PATCHLEVEL = 04 +PATCHLEVEL = 05 SUBLEVEL = 0 EXTRAVERSION = NAME = None diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2583e9dd1b..e7edc2ad44 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -169,7 +169,7 @@ config ARCH_ROCKCHIP select ARCH_HAS_L2X0 config ARCH_SOCFPGA - bool "Altera SOCFPGA cyclone5" + bool "Altera SOCFPGA" select HAS_DEBUG_LL select ARM_SMP_TWD select CPU_V7 @@ -177,8 +177,8 @@ config ARCH_SOCFPGA select CLKDEV_LOOKUP select GPIOLIB select HAVE_PBL_MULTI_IMAGES - select OFDEVICE if !ARCH_SOCFPGA_XLOAD - select OFTREE if !ARCH_SOCFPGA_XLOAD + select OFDEVICE if !(ARCH_SOCFPGA_XLOAD && ARCH_SOCFPGA_CYCLONE5) + select OFTREE if !(ARCH_SOCFPGA_XLOAD && ARCH_SOCFPGA_CYCLONE5) config ARCH_S3C24xx bool "Samsung S3C2410, S3C2440" diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 250ccb8889..0ecfb3e4b3 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -110,6 +110,7 @@ obj-$(CONFIG_MACH_SAMA5D4EK) += sama5d4ek/ obj-$(CONFIG_MACH_SCB9328) += scb9328/ obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += altera-socdk/ obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/ +obj-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += reflex-achilles/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox/ @@ -118,6 +119,7 @@ obj-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += technexion-wandboard/ obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/ obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/ obj-$(CONFIG_MACH_TNY_A9G20) += tny-a926x/ +obj-$(CONFIG_MACH_KINDLE_MX50) += kindle-mx50/ obj-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += toradex-colibri-t20/ obj-$(CONFIG_MACH_TOSHIBA_AC100) += toshiba-ac100/ obj-$(CONFIG_MACH_TQMA53) += tqma53/ diff --git a/arch/arm/boards/altera-socdk/board.c b/arch/arm/boards/altera-socdk/board.c index d7fb923a04..f4b1dcd324 100644 --- a/arch/arm/boards/altera-socdk/board.c +++ b/arch/arm/boards/altera-socdk/board.c @@ -8,7 +8,7 @@ #include <linux/sizes.h> #include <fcntl.h> #include <fs.h> -#include <mach/socfpga-regs.h> +#include <mach/cyclone5-regs.h> static int ksz9021rn_phy_fixup(struct phy_device *dev) { diff --git a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c index 07a4485f1f..9777d15dfe 100644 --- a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c +++ b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c @@ -27,7 +27,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include <mach/scan-manager.h> +#include <mach/cyclone5-scan-manager.h> static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { diff --git a/arch/arm/boards/altera-socdk/lowlevel.c b/arch/arm/boards/altera-socdk/lowlevel.c index 02c995fe45..8cfe839159 100644 --- a/arch/arm/boards/altera-socdk/lowlevel.c +++ b/arch/arm/boards/altera-socdk/lowlevel.c @@ -7,13 +7,13 @@ #include <debug_ll.h> #include <asm/cache.h> #include "sdram_config.h" -#include <mach/sdram_config.h> +#include <mach/cyclone5-sdram-config.h> #include "pinmux_config.c" #include "pll_config.h" #include <mach/pll_config.h> #include "sequencer_defines.h" #include "sequencer_auto.h" -#include <mach/sequencer.c> +#include <mach/cyclone5-sequencer.c> #include "sequencer_auto_inst_init.c" #include "sequencer_auto_ac_init.c" #include "iocsr_config_cyclone5.c" diff --git a/arch/arm/boards/at91sam9m10ihd/hw_version.c b/arch/arm/boards/at91sam9m10ihd/hw_version.c index 96fb02d801..cab26b0ac4 100644 --- a/arch/arm/boards/at91sam9m10ihd/hw_version.c +++ b/arch/arm/boards/at91sam9m10ihd/hw_version.c @@ -195,8 +195,8 @@ static void at91sam9m10ihd_devices_detect_one(const char *name) dev_add_param_fixed(dev, "board", info.board_name); sprintf(str, "%.2s", info.vendor_country); dev_add_param_fixed(dev, "country", str); - dev_add_param_int_ro(dev, "year", info.year, "%d"); - dev_add_param_int_ro(dev, "week", info.week, "%d"); + dev_add_param_uint32_fixed(dev, "year", info.year, "%u"); + dev_add_param_uint32_fixed(dev, "week", info.week, "%u"); sprintf(str, "%c", info.revision_code); dev_add_param_fixed(dev, "revision_code", str); sprintf(str, "%c", info.revision_id); diff --git a/arch/arm/boards/at91sam9x5ek/hw_version.c b/arch/arm/boards/at91sam9x5ek/hw_version.c index d1ca036fe9..10563cf98b 100644 --- a/arch/arm/boards/at91sam9x5ek/hw_version.c +++ b/arch/arm/boards/at91sam9x5ek/hw_version.c @@ -221,8 +221,8 @@ static void at91sam9x5ek_devices_detect_one(const char *name) dev_add_param_fixed(dev, "board", info.board_name); sprintf(str, "%.2s", info.vendor_country); dev_add_param_fixed(dev, "country", str); - dev_add_param_int_ro(dev, "year", info.year, "%d"); - dev_add_param_int_ro(dev, "week", info.week, "%d"); + dev_add_param_uint32_fixed(dev, "year", info.year, "%u"); + dev_add_param_uint32_fixed(dev, "week", info.week, "%u"); sprintf(str, "%c", info.revision_code); dev_add_param_fixed(dev, "revision_code", str); sprintf(str, "%c", info.revision_id); diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c index 5717c45020..18a9a10a86 100644 --- a/arch/arm/boards/beaglebone/board.c +++ b/arch/arm/boards/beaglebone/board.c @@ -87,7 +87,7 @@ static int beaglebone_devices_init(void) defaultenv_append_directory(defaultenv_beaglebone); - globalvar_add_simple("board.variant", black ? "boneblack" : "bone"); + globalvar_add_simple_string_fixed("board.variant", black ? "boneblack" : "bone"); printf("detected 'BeagleBone %s'\n", black ? "Black" : "White"); diff --git a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c index c94cb355e2..d0907c11f0 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c +++ b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c @@ -105,7 +105,7 @@ void cfa10036_detect_hw(void) return; } - globalvar_add_simple("board.variant", board_name); + globalvar_add_simple_string_fixed("board.variant", board_name); pr_info("Booting on a CFA10036 with %s\n", board_name); } diff --git a/arch/arm/boards/ebv-socrates/board.c b/arch/arm/boards/ebv-socrates/board.c index f3207b88ef..965150f9a3 100644 --- a/arch/arm/boards/ebv-socrates/board.c +++ b/arch/arm/boards/ebv-socrates/board.c @@ -11,7 +11,7 @@ #include <linux/sizes.h> #include <fcntl.h> #include <fs.h> -#include <mach/socfpga-regs.h> +#include <mach/cyclone5-regs.h> static int phy_fixup(struct phy_device *dev) { diff --git a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c index ab6733f92b..9a814cba79 100644 --- a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c +++ b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c @@ -27,7 +27,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include <mach/scan-manager.h> +#include <mach/cyclone5-scan-manager.h> static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, diff --git a/arch/arm/boards/ebv-socrates/lowlevel.c b/arch/arm/boards/ebv-socrates/lowlevel.c index ea4e1d746a..9643269f8e 100644 --- a/arch/arm/boards/ebv-socrates/lowlevel.c +++ b/arch/arm/boards/ebv-socrates/lowlevel.c @@ -7,13 +7,13 @@ #include <mach/generic.h> #include <debug_ll.h> #include "sdram_config.h" -#include <mach/sdram_config.h> +#include <mach/cyclone5-sdram-config.h> #include "pinmux_config.c" #include "pll_config.h" #include <mach/pll_config.h> #include "sequencer_defines.h" #include "sequencer_auto.h" -#include <mach/sequencer.c> +#include <mach/cyclone5-sequencer.c> #include "sequencer_auto_inst_init.c" #include "sequencer_auto_ac_init.c" #include "iocsr_config_cyclone5.c" diff --git a/arch/arm/boards/kindle-mx50/Makefile b/arch/arm/boards/kindle-mx50/Makefile new file mode 100644 index 0000000000..76ad17a1c2 --- /dev/null +++ b/arch/arm/boards/kindle-mx50/Makefile @@ -0,0 +1,4 @@ +obj-y += board.o flash-header-kindle-lpddr1.dcd.o flash-header-kindle-lpddr2.dcd.o +extra-y += flash-header-kindle-lpddr1.dcd.S flash-header-kindle-lpddr1.dcd flash-header-kindle-lpddr2.dcd.S flash-header-kindle-lpddr2.dcd +lwl-y += lowlevel.o +bbenv-y += defaultenv-kindle-mx50 diff --git a/arch/arm/boards/kindle-mx50/board.c b/arch/arm/boards/kindle-mx50/board.c new file mode 100644 index 0000000000..fa4beb7f3c --- /dev/null +++ b/arch/arm/boards/kindle-mx50/board.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * Copyright (C) 2017 Alexander Kurz <akurz@blala.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <envfs.h> +#include <environment.h> +#include <init.h> +#include <io.h> +#include <driver.h> +#include <param.h> +#include <magicvar.h> +#include <partition.h> +#include <libfile.h> +#include <globalvar.h> +#include <asm/armlinux.h> +#include <generated/mach-types.h> +#include <linux/sizes.h> +#include <usb/fsl_usb2.h> +#include <mach/generic.h> +#include <mach/imx50-regs.h> +#include <mach/imx5.h> +#include <mach/revision.h> + +/* 16 byte id for serial number */ +#define ATAG_SERIAL16 0x5441000a +/* 16 byte id for a board revision */ +#define ATAG_REVISION16 0x5441000b + +struct char16_tag { + char data[16]; +}; + +static struct tag *setup_16char_tag(struct tag *params, uint32_t tag, + const char *value) +{ + struct char16_tag *target; + target = ((void *) params) + sizeof(struct tag_header); + params->hdr.tag = tag; + params->hdr.size = tag_size(char16_tag); + memcpy(target->data, value, sizeof target->data); + return tag_next(params); +} + +static const char *get_env_16char_tag(const char *tag) +{ + static const char *default16 = "0000000000000000"; + const char *value; + value = getenv(tag); + if (!value) { + pr_err("env var %s not found, using default\n", tag); + return default16; + } + if (strlen(value) != 16) { + pr_err("env var %s: expecting 16 characters, using default\n", + tag); + return default16; + } + pr_info("%s: %s\n", tag, value); + return value; +} + +BAREBOX_MAGICVAR_NAMED(global_atags_serial16, global.board.serial16, + "Pass the kindle Serial as vendor-specific ATAG to linux"); +BAREBOX_MAGICVAR_NAMED(global_atags_revision16, global.board.revision16, + "Pass the kindle BoardId as vendor-specific ATAG to linux"); + +/* The Kindle Kernel expects two custom ATAGs, ATAG_REVISION16 describing + * the board and ATAG_SERIAL16 to identify the individual device. + */ +struct tag *kindle_mx50_append_atags(struct tag *params) +{ + params = setup_16char_tag(params, ATAG_SERIAL16, + get_env_16char_tag("global.board.serial16")); + params = setup_16char_tag(params, ATAG_REVISION16, + get_env_16char_tag("global.board.revision16")); + return params; +} + +static char *serial16; +static char *revision16; +static char *mac; + +static void kindle_rev_init(void) +{ + int ret; + size_t size; + void *buf; + const char userdata[] = "/dev/disk0.boot0.userdata"; + ret = read_file_2(userdata, &size, &buf, 128); + if (ret && ret != -EFBIG) { + pr_err("Could not read board info from %s\n", userdata); + return; + } + + serial16 = xzalloc(17); + revision16 = xzalloc(17); + mac = xzalloc(17); + + memcpy(serial16, buf, 16); + memcpy(revision16, buf + 96, 16); + memcpy(mac, buf + 48, 16); + + globalvar_add_simple_string("board.serial16", &serial16); + globalvar_add_simple_string("board.revision16", &revision16); + globalvar_add_simple_string("board.mac", &mac); + + free(buf); +} + +static int kindle_mx50_late_init(void) +{ + armlinux_set_revision(0x50000 | imx_silicon_revision()); + /* Compatibility ATAGs for original kernel */ + armlinux_set_atag_appender(kindle_mx50_append_atags); + + kindle_rev_init(); + + return 0; +} +late_initcall(kindle_mx50_late_init); + +static int kindle_mx50_mem_init(void) +{ + arm_add_mem_device("ram0", MX50_CSD0_BASE_ADDR, SZ_256M); + return 0; +} +mem_initcall(kindle_mx50_mem_init); + +static int kindle_mx50_devices_init(void) +{ + struct device_d *dev; + /* Probe the eMMC to allow reading the board serial and revision */ + dev = get_device_by_name("mci0"); + if (dev) + dev_set_param(dev, "probe", "1"); + + defaultenv_append_directory(defaultenv_kindle_mx50); + + return 0; +} +device_initcall(kindle_mx50_devices_init); + +static int kindle_mx50_postcore_init(void) +{ + imx50_init_lowlevel(800); + + return 0; +} +postcore_initcall(kindle_mx50_postcore_init); diff --git a/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/boot/mmc_kernel b/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/boot/mmc_kernel new file mode 100644 index 0000000000..a43ee0cc92 --- /dev/null +++ b/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/boot/mmc_kernel @@ -0,0 +1,15 @@ +#!/bin/sh +# Boot the Amazon factory-shipped kernel uimage stored on +# the eMMC at CONFIG_MMC_BOOTFLASH_ADDR 0x41000 + +# Purge the OF tree to enable passing of ATAGs +oftree -f + +# The same machine type introduced with freescale ENGR00124359 +armlinux_architecture=2955 + +armlinux_system_serial="$global.board.ocotp_serial" + +global linux.bootargs.dyn.root="root=/dev/mmcblk0p1 rootwait ro" + +bootm -c /dev/disk0.kernel diff --git a/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/init/usbconsole b/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/init/usbconsole new file mode 100644 index 0000000000..4fe12113cc --- /dev/null +++ b/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/init/usbconsole @@ -0,0 +1,21 @@ +#!/bin/sh + +if test "$global.model" = "Amazon Kindle D01100"; then + if gpio_get_value 18; then; else + usbserial + global.autoboot_timeout=60 + fi +fi + +if test "$global.model" = "Amazon Kindle D01200"; then + sleep 5 + if gpio_get_value 0; then + usbserial + global.autoboot_timeout=60 + fi +fi + +if test "$global.model" = "Amazon Kindle EY21"; then + usbserial + global.autoboot_timeout=10 +fi diff --git a/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/nv/autoboot_timeout b/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/nv/autoboot_timeout new file mode 100644 index 0000000000..00750edc07 --- /dev/null +++ b/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/nv/autoboot_timeout @@ -0,0 +1 @@ +3 diff --git a/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/nv/boot.default b/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/nv/boot.default new file mode 100644 index 0000000000..3118b7af45 --- /dev/null +++ b/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/nv/boot.default @@ -0,0 +1 @@ +mmc_kernel diff --git a/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/nv/linux.bootargs.consoleblank b/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/nv/linux.bootargs.consoleblank new file mode 100644 index 0000000000..efc4ee63d4 --- /dev/null +++ b/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/nv/linux.bootargs.consoleblank @@ -0,0 +1 @@ +consoleblank=0 diff --git a/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/nv/linux.bootargs.eink b/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/nv/linux.bootargs.eink new file mode 100644 index 0000000000..2ff3618376 --- /dev/null +++ b/arch/arm/boards/kindle-mx50/defaultenv-kindle-mx50/nv/linux.bootargs.eink @@ -0,0 +1 @@ +fslepdc video=mxcepdcfb:E60,bpp=8 diff --git a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg new file mode 100644 index 0000000000..e6b6098973 --- /dev/null +++ b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg @@ -0,0 +1,166 @@ +# DCD i.MX50 SoC setup using 256MiB LPDDR1 +# Copyright (C) 2017 Alexander Kurz <akurz@blala.de> +# +# Initial DCD setup according to Freescale ENGR00124359 +# with adaption for LPDDR1 ENGR00025557 +# Copyright (C) 2010 Freescale Semiconductor, Inc. + +soc imx50 +loadaddr 0x70020000 +dcdofs 0x400 + +# Switch pll1_sw_clk to step_clk +wm 32 0x53fd400c 0x00000004 +# Setup PLL1 to 800MHz +wm 32 0x63f80000 0x00001232 +wm 32 0x63f80004 0x00000002 +wm 32 0x63f80008 0x00000080 +wm 32 0x63f8000c 0x00000002 +wm 32 0x63f80010 0x00000001 +wm 32 0x63f8001c 0x00000080 +wm 32 0x63f80020 0x00000002 +wm 32 0x63f80024 0x00000001 +wm 32 0x63f80000 0x00001232 +check 8 while_any_bit_clear 0x63f80000 0x01 +# Switch pll1_sw_clk to pll1 +wm 32 0x53fd400c 0x00000000 + +# CGR +wm 32 0x53fd4068 0xffffffff +wm 32 0x53fd406c 0xffffffff +wm 32 0x53fd4070 0xffffffff +wm 32 0x53fd4074 0xffffffff +wm 32 0x53fd4078 0xffffffff +wm 32 0x53fd407c 0xffffffff +wm 32 0x53fd4080 0xffffffff +wm 32 0x53fd4084 0xffffffff +wm 32 0x53FD4098 0x80000004 + +# CCM DDR div 4 / 200MHz +wm 32 0x53fd4098 0x80000004 +check 32 while_all_bits_set 0x53fd408c 0x00000004 + +# IOMUX +wm 32 0x53fa8490 0x00180000 +wm 32 0x53fa8494 0x00180000 +wm 32 0x53fa86ac 0x00000000 +wm 32 0x53fa8668 0x00180000 +wm 32 0x53fa866c 0x00000000 +wm 32 0x53fa8670 0x00000000 +wm 32 0x53fa868c 0x00000000 +wm 32 0x53fa8698 0x00180000 +wm 32 0x53fa86a0 0x00180000 +wm 32 0x53fa86a4 0x00180000 +wm 32 0x53fa86a8 0x00180000 +wm 32 0x53fa86b4 0x00180000 + +# set SW_PAD_CTL_GRP_NANDF to Low output voltage +wm 32 0x53fa86c0 0x2000 + +wm 32 0x53fa8498 0x00180200 +wm 32 0x53fa849c 0x00180200 +wm 32 0x53fa84c8 0x00180000 +wm 32 0x53fa84cc 0x00180080 +wm 32 0x53fa84f0 0x00180000 +wm 32 0x53fa84f4 0x00180080 +wm 32 0x53fa84fc 0x00180080 +wm 32 0x53fa8500 0x00180000 +wm 32 0x53fa8524 0x00180080 +wm 32 0x53fa8528 0x00180000 + +# ZQ Load +wm 32 0x1400012C 0x00000817 +wm 32 0x14000128 0x09180000 +wm 32 0x14000124 0x00310000 +wm 32 0x14000124 0x00200000 +wm 32 0x14000128 0x09180010 +wm 32 0x14000124 0x00310000 +wm 32 0x14000124 0x00200000 + +# DRAM_CTL +wm 32 0x14000000 0x00000100 +wm 32 0x14000008 0x00009c40 +wm 32 0x14000014 0x02000000 +wm 32 0x14000018 0x01010006 +wm 32 0x1400001c 0x080b0201 +wm 32 0x14000020 0x02000303 +wm 32 0x14000024 0x0036b002 +wm 32 0x14000028 0x00000606 +wm 32 0x1400002c 0x06030400 +wm 32 0x14000030 0x01000000 +wm 32 0x14000034 0x00000a02 +wm 32 0x14000038 0x00000003 +wm 32 0x1400003c 0x00001801 +wm 32 0x14000040 0x00050612 +wm 32 0x14000044 0x00000200 +wm 32 0x14000048 0x001c001c +wm 32 0x1400004c 0x00010000 +wm 32 0x1400005c 0x01000000 +wm 32 0x14000060 0x00000001 +wm 32 0x14000064 0x00000000 +wm 32 0x14000068 0x00320000 +wm 32 0x1400006c 0x00000000 +wm 32 0x14000070 0x00000000 +wm 32 0x14000074 0x00320000 +wm 32 0x14000080 0x02000000 +wm 32 0x14000084 0x00000100 +wm 32 0x14000088 0x02400040 +wm 32 0x1400008c 0x01000000 +wm 32 0x14000090 0x0a000100 +wm 32 0x14000094 0x01011f1f +wm 32 0x14000098 0x01010101 +wm 32 0x1400009c 0x00030101 +wm 32 0x140000a4 0x00010000 +wm 32 0x140000a8 0x00000000 +wm 32 0x140000ac 0x0000ffff +wm 32 0x140000c8 0x02020101 +wm 32 0x140000cc 0x00000000 +wm 32 0x140000d0 0x01000202 +wm 32 0x140000d4 0x00000200 +wm 32 0x140000d8 0x00000001 +wm 32 0x140000dc 0x0000ffff +wm 32 0x140000e0 0x00000000 +wm 32 0x140000e4 0x02020000 +wm 32 0x140000e8 0x02020202 +wm 32 0x140000ec 0x00000202 +wm 32 0x140000f0 0x01010064 +wm 32 0x140000f4 0x01010101 +wm 32 0x140000f8 0x00010101 +wm 32 0x140000fc 0x00000064 +wm 32 0x14000104 0x02000602 +wm 32 0x14000108 0x06120000 +wm 32 0x1400010c 0x06120612 +wm 32 0x14000110 0x06120612 +wm 32 0x14000114 0x01030612 +wm 32 0x14000118 0x00010002 +wm 32 0x1400011c 0x00001000 + +# DDR PHY +wm 32 0x14000200 0x00000000 +wm 32 0x14000204 0x00000000 +wm 32 0x14000208 0x35002725 +wm 32 0x14000210 0x35002725 +wm 32 0x14000218 0x35002725 +wm 32 0x14000220 0x35002725 +wm 32 0x14000228 0x35002725 +wm 32 0x1400020c 0x380002d0 +wm 32 0x14000214 0x380002d0 +wm 32 0x1400021c 0x380002d0 +wm 32 0x14000224 0x380002d0 +wm 32 0x1400022c 0x380002d0 +wm 32 0x14000230 0x00000000 +wm 32 0x14000234 0x00800006 +wm 32 0x14000238 0x60101414 +wm 32 0x14000240 0x60101414 +wm 32 0x14000248 0x60101414 +wm 32 0x14000250 0x60101414 +wm 32 0x14000258 0x60101414 +wm 32 0x1400023c 0x00101001 +wm 32 0x14000244 0x00101001 +wm 32 0x1400024c 0x00101001 +wm 32 0x14000254 0x00101001 +wm 32 0x1400025c 0x00102201 + +# start DDR +wm 32 0x14000000 0x00000101 +check 32 while_any_bit_clear 0x140000a8 0x00000010 diff --git a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg new file mode 100644 index 0000000000..ffceac34b5 --- /dev/null +++ b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg @@ -0,0 +1,176 @@ +# DCD i.MX50 SoC setup using 256MiB LPDDR2 +# Copyright (C) 2017 Alexander Kurz <akurz@blala.de> +# +# Initial DCD setup according to Freescale ENGR00124359 with adaption from +# Kindle_src_5.6.1.1_2634130033 uboot_2009.08 imx50_yoshi flash_header. +# Copyright (C) 2010 Freescale Semiconductor, Inc. + +soc imx50 +loadaddr 0x70020000 + +dcdofs 0x400 + +# Switch pll1_sw_clk to step_clk +wm 32 0x53fd400c 0x00000004 +# Setup PLL1 to 800MHz +wm 32 0x63f80000 0x00001236 +wm 32 0x63f80004 0x00000002 +wm 32 0x63f80008 0x00000080 +wm 32 0x63f8000c 0x000000b3 +wm 32 0x63f80010 0x000000b4 +wm 32 0x63f8001c 0x00000080 +wm 32 0x63f80020 0x000000b3 +wm 32 0x63f80024 0x000000b4 +wm 32 0x63f80000 0x00001236 +check 8 while_any_bit_clear 0x63f80000 0x01 +# Switch pll1_sw_clk to pll1 +wm 32 0x53fd400c 0x00000000 + +# CGR +wm 32 0x53fd4068 0xffffffff +wm 32 0x53fd406c 0xffffffff +wm 32 0x53fd4070 0xffffffff +wm 32 0x53fd4074 0xffffffff +wm 32 0x53fd4078 0xffffffff +wm 32 0x53fd407c 0xffffffff +wm 32 0x53fd4080 0xffffffff +wm 32 0x53fd4084 0xffffffff +wm 32 0x53FD4098 0x80000004 + +# CCM DDR div 3 / 266MHz +wm 32 0x53fd4098 0x80000003 +check 32 while_all_bits_set 0x53fd408c 0x00000004 + +# IOMUX +wm 32 0x53fa86ac 0x04000000 +wm 32 0x53fa8668 0x00200000 +wm 32 0x53fa866c 0x00000200 +wm 32 0x53fa8670 0x00000000 +wm 32 0x53fa868c 0x00000000 +wm 32 0x53fa8698 0x00200000 +wm 32 0x53fa86a0 0x00200000 +wm 32 0x53fa86a4 0x00200000 +wm 32 0x53fa86a8 0x00200000 +wm 32 0x53fa86b4 0x00200000 + +# set SW_PAD_CTL_GRP_NANDF to Low output voltage +wm 32 0x53fa86c0 0x2000 + +wm 32 0x53fa8490 0x00200000 +wm 32 0x53fa8494 0x00200000 +wm 32 0x53fa8498 0x00200000 +wm 32 0x53fa849c 0x00200000 +wm 32 0x53fa84c8 0x00200000 +wm 32 0x53fa84cc 0x00200000 +wm 32 0x53fa84f0 0x00200000 +wm 32 0x53fa84f4 0x00200000 +wm 32 0x53fa84fc 0x00200000 +wm 32 0x53fa8500 0x00200000 +wm 32 0x53fa8524 0x00200000 +wm 32 0x53fa8528 0x00200000 + +# ZQ Load +wm 32 0x1400012C 0x00000817 +wm 32 0x14000128 0x09180000 +wm 32 0x14000124 0x00310000 +wm 32 0x14000124 0x00200000 +wm 32 0x14000128 0x09180010 +wm 32 0x14000124 0x00310000 +wm 32 0x14000124 0x00200000 + +# DRAM_CTL +wm 32 0x14000000 0x00000500 +wm 32 0x14000008 0x0000001b +wm 32 0x1400000c 0x0000d056 +wm 32 0x14000010 0x0000010b +wm 32 0x14000014 0x00000a6b +wm 32 0x14000018 0x02020d0c +wm 32 0x1400001c 0x0c110302 +wm 32 0x14000020 0x05020503 +wm 32 0x14000024 0x0048eb05 +wm 32 0x14000028 0x00000606 +wm 32 0x1400002c 0x09040501 +wm 32 0x14000030 0x02000000 +wm 32 0x14000034 0x00000e02 +wm 32 0x14000038 0x00000006 +wm 32 0x1400003c 0x00002301 +wm 32 0x14000040 0x00050408 +wm 32 0x14000044 0x00000300 +wm 32 0x14000048 0x00260026 +wm 32 0x1400004c 0x00010000 +wm 32 0x14000050 0x00000000 +wm 32 0x14000054 0x00000000 +wm 32 0x14000058 0x00000000 +wm 32 0x1400005c 0x02000000 +wm 32 0x14000060 0x00000002 +wm 32 0x14000064 0x00000000 +wm 32 0x14000068 0x00000000 +wm 32 0x1400006c 0x00040042 +wm 32 0x14000070 0x00000001 +wm 32 0x14000074 0x00000000 +wm 32 0x14000078 0x00040042 +wm 32 0x1400007c 0x00000001 +wm 32 0x14000080 0x010b0000 +wm 32 0x14000084 0x00000060 +wm 32 0x14000088 0x02400018 +wm 32 0x1400008c 0x01000e00 +wm 32 0x14000090 0x0a010101 +wm 32 0x14000094 0x01011f1f +wm 32 0x14000098 0x01010101 +wm 32 0x1400009c 0x00030101 +wm 32 0x140000a0 0x00010000 +wm 32 0x140000a4 0x00010000 +wm 32 0x140000a8 0x00000000 +wm 32 0x140000ac 0x0000ffff +wm 32 0x140000c8 0x02020101 +wm 32 0x140000cc 0x01000000 +wm 32 0x140000d0 0x01000201 +wm 32 0x140000d4 0x00000200 +wm 32 0x140000d8 0x00000102 +wm 32 0x140000dc 0x0000ffff +wm 32 0x140000e0 0x0000ff00 +wm 32 0x140000e4 0x02020000 +wm 32 0x140000e8 0x02020202 +wm 32 0x140000ec 0x00000202 +wm 32 0x140000f0 0x01010064 +wm 32 0x140000f4 0x01010101 +wm 32 0x140000f8 0x00010101 +wm 32 0x140000fc 0x00000064 +wm 32 0x14000100 0x00000000 +wm 32 0x14000104 0x02000802 +wm 32 0x14000108 0x04080000 +wm 32 0x1400010c 0x04080408 +wm 32 0x14000110 0x04080408 +wm 32 0x14000114 0x03060408 +wm 32 0x14000118 0x00010002 +wm 32 0x1400011c 0x00001000 + +# DDR PHY +wm 32 0x14000200 0x00000000 +wm 32 0x14000204 0x00000000 +wm 32 0x14000208 0x35003a27 +wm 32 0x14000210 0x35003a27 +wm 32 0x14000218 0x35003a27 +wm 32 0x14000220 0x35003a27 +wm 32 0x14000228 0x35003a27 +wm 32 0x1400020c 0x380002e1 +wm 32 0x14000214 0x380002e1 +wm 32 0x1400021c 0x380002e1 +wm 32 0x14000224 0x380002e1 +wm 32 0x1400022c 0x380002e1 +wm 32 0x14000230 0x00000000 +wm 32 0x14000234 0x00810006 +wm 32 0x14000238 0x60101014 +wm 32 0x14000240 0x60101014 +wm 32 0x14000248 0x60101014 +wm 32 0x14000250 0x60101014 +wm 32 0x14000258 0x60101014 +wm 32 0x1400023c 0x00100b01 +wm 32 0x14000244 0x00100b01 +wm 32 0x1400024c 0x00100b01 +wm 32 0x14000254 0x00100b01 +wm 32 0x1400025c 0x00100b01 + +# start DDR +wm 32 0x14000000 0x00000501 +check 32 while_any_bit_clear 0x140000a8 0x00000010 diff --git a/arch/arm/boards/kindle-mx50/lowlevel.c b/arch/arm/boards/kindle-mx50/lowlevel.c new file mode 100644 index 0000000000..dc321b533b --- /dev/null +++ b/arch/arm/boards/kindle-mx50/lowlevel.c @@ -0,0 +1,50 @@ +#include <common.h> +#include <linux/sizes.h> +#include <io.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <asm/sections.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <mach/imx50-regs.h> +#include <mach/generic.h> + +extern char __dtb_imx50_kindle_d01100_start[]; +extern char __dtb_imx50_kindle_d01200_start[]; +extern char __dtb_imx50_kindle_ey21_start[]; + +ENTRY_FUNCTION(start_imx50_kindle_d01100, r0, r1, r2) +{ + void *fdt; + + imx5_cpu_lowlevel_init(); + arm_setup_stack(MX50_IRAM_BASE_ADDR + MX50_IRAM_SIZE - 8); + + fdt = __dtb_imx50_kindle_d01100_start - get_runtime_offset(); + + barebox_arm_entry(MX50_CSD0_BASE_ADDR, SZ_256M, fdt); +} + +ENTRY_FUNCTION(start_imx50_kindle_d01200, r0, r1, r2) +{ + void *fdt; + + imx5_cpu_lowlevel_init(); + arm_setup_stack(MX50_IRAM_BASE_ADDR + MX50_IRAM_SIZE - 8); + + fdt = __dtb_imx50_kindle_d01200_start - get_runtime_offset(); + + barebox_arm_entry(MX50_CSD0_BASE_ADDR, SZ_256M, fdt); +} + +ENTRY_FUNCTION(start_imx50_kindle_ey21, r0, r1, r2) +{ + void *fdt; + + imx5_cpu_lowlevel_init(); + arm_setup_stack(MX50_IRAM_BASE_ADDR + MX50_IRAM_SIZE - 8); + + fdt = __dtb_imx50_kindle_ey21_start - get_runtime_offset(); + + barebox_arm_entry(MX50_CSD0_BASE_ADDR, SZ_256M, fdt); +} diff --git a/arch/arm/boards/phytec-som-am335x/board.c b/arch/arm/boards/phytec-som-am335x/board.c index 7f62453d93..dc3b84a806 100644 --- a/arch/arm/boards/phytec-som-am335x/board.c +++ b/arch/arm/boards/phytec-som-am335x/board.c @@ -112,6 +112,7 @@ static int physom_devices_init(void) xloadslots, ARRAY_SIZE(xloadslots)); am33xx_bbu_nand_slots_register_handler("nand", nandslots, ARRAY_SIZE(nandslots)); + am33xx_bbu_emmc_mlo_register_handler("MLO.emmc", "/dev/mmc1"); if (IS_ENABLED(CONFIG_SHELL_NONE)) return am33xx_of_register_bootdevice(); diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c index ed9453bdda..31b2761024 100644 --- a/arch/arm/boards/phytec-som-imx6/board.c +++ b/arch/arm/boards/phytec-som-imx6/board.c @@ -152,7 +152,7 @@ static int physom_imx6_devices_init(void) phyflex_err006282_workaround(); pfla02_module_revision = get_module_rev(); - globalvar_add_simple_int("board.revision", &pfla02_module_revision, "%u"); + globalvar_add_simple_uint32_fixed("board.revision", pfla02_module_revision, "%u"); pr_info("Module Revision: %u\n", pfla02_module_revision); barebox_set_hostname("phyFLEX-i.MX6"); diff --git a/arch/arm/boards/reflex-achilles/Makefile b/arch/arm/boards/reflex-achilles/Makefile new file mode 100644 index 0000000000..6b42141153 --- /dev/null +++ b/arch/arm/boards/reflex-achilles/Makefile @@ -0,0 +1,2 @@ +obj-y += lowlevel.o +pbl-y += lowlevel.o diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c new file mode 100644 index 0000000000..12994177cc --- /dev/null +++ b/arch/arm/boards/reflex-achilles/lowlevel.c @@ -0,0 +1,48 @@ +#include <common.h> +#include <linux/sizes.h> +#include <io.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <asm/cache.h> +#include <debug_ll.h> +#include <mach/arria10-sdram.h> +#include <mach/arria10-regs.h> +#include <mach/arria10-reset-manager.h> +#include <mach/arria10-clock-manager.h> +#include <mach/arria10-pinmux.h> +#include "pll-config-arria10.c" +#include "pinmux-config-arria10.c" +#include <mach/generic.h> + +extern char __dtb_socfpga_arria10_achilles_start[]; + +static noinline void achilles_entry(void) +{ + void *fdt; + + arm_early_mmu_cache_invalidate(); + + relocate_to_current_adr(); + setup_c(); + + arria10_init(&mainpll_cfg, &perpll_cfg, pinmux); + + puts_ll("lowlevel init done\n"); + + arria10_ddr_calibration_sequence(); + + puts_ll("SDRAM setup done\n"); + + fdt = __dtb_socfpga_arria10_achilles_start - get_runtime_offset(); + + barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt); +} + +ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + + arm_setup_stack(0xffe00000 + SZ_256K - SZ_32K - SZ_4K - 16); + + achilles_entry(); +} diff --git a/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c b/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c new file mode 100644 index 0000000000..246838a228 --- /dev/null +++ b/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c @@ -0,0 +1,102 @@ +#include <mach/arria10-pinmux.h> + +static uint32_t pinmux[] = { +[arria10_pinmux_shared_io_q4_12] = 8, +[arria10_pinmux_shared_io_q4_11] = 8, +[arria10_pinmux_shared_io_q4_10] = 8, +[arria10_pinmux_shared_io_q4_9] = 8, +[arria10_pinmux_shared_io_q4_8] = 8, +[arria10_pinmux_shared_io_q4_6] = 8, +[arria10_pinmux_shared_io_q4_7] = 8, +[arria10_pinmux_shared_io_q4_5] = 8, +[arria10_pinmux_shared_io_q4_4] = 8, +[arria10_pinmux_shared_io_q4_3] = 8, +[arria10_pinmux_shared_io_q4_2] = 8, +[arria10_pinmux_shared_io_q4_1] = 8, +[arria10_pinmux_shared_io_q3_12] = 8, +[arria10_pinmux_shared_io_q3_11] = 8, +[arria10_pinmux_shared_io_q3_10] = 8, +[arria10_pinmux_shared_io_q3_8] = 8, +[arria10_pinmux_shared_io_q3_9] = 8, +[arria10_pinmux_shared_io_q3_7] = 8, +[arria10_pinmux_shared_io_q3_6] = 8, +[arria10_pinmux_shared_io_q3_5] = 8, +[arria10_pinmux_shared_io_q3_4] = 8, +[arria10_pinmux_shared_io_q3_3] = 8, +[arria10_pinmux_shared_io_q3_2] = 8, +[arria10_pinmux_shared_io_q3_1] = 8, +[arria10_pinmux_shared_io_q2_12] = 8, +[arria10_pinmux_shared_io_q2_10] = 8, +[arria10_pinmux_shared_io_q2_11] = 8, +[arria10_pinmux_shared_io_q2_9] = 8, +[arria10_pinmux_shared_io_q2_8] = 8, +[arria10_pinmux_shared_io_q2_7] = 8, +[arria10_pinmux_shared_io_q2_6] = 8, +[arria10_pinmux_shared_io_q2_5] = 8, +[arria10_pinmux_shared_io_q2_4] = 8, +[arria10_pinmux_shared_io_q2_3] = 8, +[arria10_pinmux_shared_io_q2_2] = 8, +[arria10_pinmux_shared_io_q2_1] = 8, +[arria10_pinmux_shared_io_q1_12] = 10, +[arria10_pinmux_shared_io_q1_11] = 10, +[arria10_pinmux_shared_io_q1_10] = 1, +[arria10_pinmux_shared_io_q1_9] = 1, +[arria10_pinmux_shared_io_q1_8] = 1, +[arria10_pinmux_shared_io_q1_7] = 1, +[arria10_pinmux_shared_io_q1_6] = 0, +[arria10_pinmux_shared_io_q1_5] = 0, +[arria10_pinmux_shared_io_q1_4] = 13, +[arria10_pinmux_shared_io_q1_3] = 13, +[arria10_pinmux_shared_io_q1_2] = 13, +[arria10_pinmux_shared_io_q1_1] = 13, +[arria10_pinmux_dedicated_io_4] = 8, +[arria10_pinmux_dedicated_io_5] = 8, +[arria10_pinmux_dedicated_io_6] = 8, +[arria10_pinmux_dedicated_io_7] = 8, +[arria10_pinmux_dedicated_io_8] = 8, +[arria10_pinmux_dedicated_io_9] = 8, +[arria10_pinmux_dedicated_io_10] = 10, +[arria10_pinmux_dedicated_io_11] = 10, +[arria10_pinmux_dedicated_io_12] = 8, +[arria10_pinmux_dedicated_io_13] = 8, +[arria10_pinmux_dedicated_io_14] = 8, +[arria10_pinmux_dedicated_io_15] = 8, +[arria10_pinmux_dedicated_io_16] = 15, +[arria10_pinmux_dedicated_io_17] = 15, +[arria10_pincfg_dedicated_io_bank] = 0x101, +[arria10_pincfg_dedicated_io_1] = 0xb080a, +[arria10_pincfg_dedicated_io_2] = 0xb080a, +[arria10_pincfg_dedicated_io_3] = 0xb080a, +[arria10_pincfg_dedicated_io_4] = 0xa282a, +[arria10_pincfg_dedicated_io_5] = 0xa282a, +[arria10_pincfg_dedicated_io_6] = 0xa282a, +[arria10_pincfg_dedicated_io_7] = 0xa282a, +[arria10_pincfg_dedicated_io_8] = 0xa282a, +[arria10_pincfg_dedicated_io_9] = 0xa282a, +[arria10_pincfg_dedicated_io_10] = 0x90000, +[arria10_pincfg_dedicated_io_11] = 0x90000, +[arria10_pincfg_dedicated_io_12] = 0xa282a, +[arria10_pincfg_dedicated_io_13] = 0xa282a, +[arria10_pincfg_dedicated_io_14] = 0xa282a, +[arria10_pincfg_dedicated_io_15] = 0xa282a, +[arria10_pincfg_dedicated_io_16] = 0xa282a, +[arria10_pincfg_dedicated_io_17] = 0xa282a, +[arria10_pinmux_rgmii0_usefpga] = 0, +[arria10_pinmux_rgmii1_usefpga] = 0, +[arria10_pinmux_rgmii2_usefpga] = 0, +[arria10_pinmux_nand_usefpga] = 0, +[arria10_pinmux_qspi_usefpga] = 0, +[arria10_pinmux_sdmmc_usefpga] = 0, +[arria10_pinmux_spim0_usefpga] = 1, +[arria10_pinmux_spim1_usefpga] = 0, +[arria10_pinmux_spis0_usefpga] = 0, +[arria10_pinmux_spis1_usefpga] = 0, +[arria10_pinmux_uart0_usefpga] = 0, +[arria10_pinmux_uart1_usefpga] = 0, +[arria10_pinmux_i2c0_usefpga] = 0, +[arria10_pinmux_i2c1_usefpga] = 0, +[arria10_pinmux_i2cemac0_usefpga] = 0, +[arria10_pinmux_i2cemac1_usefpga] = 0, +[arria10_pinmux_i2cemac2_usefpga] = 0, +}; + diff --git a/arch/arm/boards/reflex-achilles/pll-config-arria10.c b/arch/arm/boards/reflex-achilles/pll-config-arria10.c new file mode 100644 index 0000000000..94d596606e --- /dev/null +++ b/arch/arm/boards/reflex-achilles/pll-config-arria10.c @@ -0,0 +1,54 @@ +#include <mach/arria10-clock-manager.h> + +static struct arria10_mainpll_cfg mainpll_cfg = { + .cntr15clk_cnt = 900, + .cntr2clk_cnt = 900, + .cntr3clk_cnt = 900, + .cntr4clk_cnt = 900, + .cntr5clk_cnt = 900, + .cntr6clk_cnt = 7, + .cntr7clk_cnt = 900, + .cntr7clk_src = 0, + .cntr8clk_cnt = 900, + .cntr9clk_cnt = 900, + .cntr9clk_src = 0, + .mpuclk_cnt = 0, + .mpuclk_src = 0, + .nocclk_cnt = 0, + .nocclk_src = 0, + .nocdiv_csatclk = 2, + .nocdiv_cspdbgclk = 0, + .nocdiv_cstraceclk = 0, + .nocdiv_l4mainclk = 2, + .nocdiv_l4mpclk = 2, + .nocdiv_l4spclk = 2, + .vco0_psrc = 0, + .vco1_denom = 1, + .vco1_numer = 127, + .mpuclk = 0x3840001, + .nocclk = 0x3840003, +}; + +static struct arria10_perpll_cfg perpll_cfg = { + .cntr2clk_cnt = 5, + .cntr2clk_src = 1, + .cntr3clk_cnt = 900, + .cntr3clk_src = 1, + .cntr4clk_cnt = 14, + .cntr4clk_src = 1, + .cntr5clk_cnt = 374, + .cntr5clk_src = 1, + .cntr6clk_cnt = 900, + .cntr6clk_src = 0, + .cntr7clk_cnt = 900, + .cntr8clk_cnt = 900, + .cntr8clk_src = 0, + .cntr9clk_cnt = 900, + .emacctl_emac0sel = 0, + .emacctl_emac1sel = 0, + .emacctl_emac2sel = 0, + .gpiodiv_gpiodbclk = 32000, + .vco0_psrc = 0, + .vco1_denom = 1, + .vco1_numer = 119, +}; diff --git a/arch/arm/boards/sama5d3xek/hw_version.c b/arch/arm/boards/sama5d3xek/hw_version.c index c809c37742..e5077854e3 100644 --- a/arch/arm/boards/sama5d3xek/hw_version.c +++ b/arch/arm/boards/sama5d3xek/hw_version.c @@ -227,8 +227,8 @@ static void at91sama5d3xek_devices_detect_one(const char *name) dev_add_param_fixed(dev, "board", bname); sprintf(str, "%.2s", info.vendor_country); dev_add_param_fixed(dev, "country", str); - dev_add_param_int_ro(dev, "year", info.year, "%d"); - dev_add_param_int_ro(dev, "week", info.week, "%d"); + dev_add_param_uint32_fixed(dev, "year", info.year, "%u"); + dev_add_param_uint32_fixed(dev, "week", info.week, "%u"); sprintf(str, "%c", info.revision_board); dev_add_param_fixed(dev, "revision_board", str); sprintf(str, "%c", info.revision_schema); diff --git a/arch/arm/boards/solidrun-microsom/board.c b/arch/arm/boards/solidrun-microsom/board.c index b9041687e4..155199ff78 100644 --- a/arch/arm/boards/solidrun-microsom/board.c +++ b/arch/arm/boards/solidrun-microsom/board.c @@ -78,7 +78,9 @@ static void microsom_eth_init(void) static int hummingboard_device_init(void) { if (!of_machine_is_compatible("solidrun,hummingboard/dl") && - !of_machine_is_compatible("solidrun,hummingboard/q")) + !of_machine_is_compatible("solidrun,hummingboard/q") && + !of_machine_is_compatible("solidrun,hummingboard2/dl") && + !of_machine_is_compatible("solidrun,hummingboard2/q")) return 0; microsom_eth_init(); @@ -108,13 +110,26 @@ device_initcall(h100_device_init); static int hummingboard_late_init(void) { + bool emmc_present = false; + if (!of_machine_is_compatible("solidrun,hummingboard/dl") && !of_machine_is_compatible("solidrun,hummingboard/q") && + !of_machine_is_compatible("solidrun,hummingboard2/dl") && + !of_machine_is_compatible("solidrun,hummingboard2/q") && !of_machine_is_compatible("auvidea,h100")) return 0; + if (of_machine_is_compatible("solidrun,hummingboard2/dl") || + of_machine_is_compatible("solidrun,hummingboard2/q")) + emmc_present = true; + imx6_bbu_internal_mmc_register_handler("sdcard", "/dev/mmc1.barebox", - BBU_HANDLER_FLAG_DEFAULT); + emmc_present ? 0 : BBU_HANDLER_FLAG_DEFAULT); + + if (emmc_present) { + imx6_bbu_internal_mmc_register_handler("emmc", + "/dev/mmc2.barebox", BBU_HANDLER_FLAG_DEFAULT); + } return 0; } diff --git a/arch/arm/boards/solidrun-microsom/lowlevel.c b/arch/arm/boards/solidrun-microsom/lowlevel.c index 7b97f2e947..cc15958d64 100644 --- a/arch/arm/boards/solidrun-microsom/lowlevel.c +++ b/arch/arm/boards/solidrun-microsom/lowlevel.c @@ -5,6 +5,8 @@ extern char __dtb_imx6dl_hummingboard_start[]; extern char __dtb_imx6q_hummingboard_start[]; +extern char __dtb_imx6dl_hummingboard2_start[]; +extern char __dtb_imx6q_hummingboard2_start[]; extern char __dtb_imx6q_h100_start[]; ENTRY_FUNCTION(start_hummingboard_microsom_i1, r0, r1, r2) @@ -47,6 +49,46 @@ ENTRY_FUNCTION(start_hummingboard_microsom_i4, r0, r1, r2) imx6q_barebox_entry(fdt); } +ENTRY_FUNCTION(start_hummingboard2_microsom_i1, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_imx6dl_hummingboard2_start - get_runtime_offset(); + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_hummingboard2_microsom_i2, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_imx6dl_hummingboard2_start - get_runtime_offset(); + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_hummingboard2_microsom_i2ex, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_imx6q_hummingboard2_start - get_runtime_offset(); + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_hummingboard2_microsom_i4, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_imx6q_hummingboard2_start - get_runtime_offset(); + imx6q_barebox_entry(fdt); +} + ENTRY_FUNCTION(start_h100_microsom_i2ex, r0, r1, r2) { void *fdt; diff --git a/arch/arm/boards/terasic-de0-nano-soc/board.c b/arch/arm/boards/terasic-de0-nano-soc/board.c index 919bfc8c54..8e69319d17 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/board.c +++ b/arch/arm/boards/terasic-de0-nano-soc/board.c @@ -8,7 +8,7 @@ #include <linux/sizes.h> #include <fcntl.h> #include <fs.h> -#include <mach/socfpga-regs.h> +#include <mach/cyclone5-regs.h> static int phy_fixup(struct phy_device *dev) { diff --git a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c index 4e9ac7fb77..d5098055ff 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c +++ b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c @@ -27,7 +27,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include <mach/scan-manager.h> +#include <mach/cyclone5-scan-manager.h> static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, diff --git a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c index 6d937abda5..1d5ea6b12a 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c +++ b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c @@ -7,13 +7,13 @@ #include <debug_ll.h> #include <asm/cache.h> #include "sdram_config.h" -#include <mach/sdram_config.h> +#include <mach/cyclone5-sdram-config.h> #include "pinmux_config.c" #include "pll_config.h" #include <mach/pll_config.h> #include "sequencer_defines.h" #include "sequencer_auto.h" -#include <mach/sequencer.c> +#include <mach/cyclone5-sequencer.c> #include "sequencer_auto_inst_init.c" #include "sequencer_auto_ac_init.c" #include "iocsr_config_cyclone5.c" diff --git a/arch/arm/boards/terasic-sockit/board.c b/arch/arm/boards/terasic-sockit/board.c index 53cd36834f..ec68315998 100644 --- a/arch/arm/boards/terasic-sockit/board.c +++ b/arch/arm/boards/terasic-sockit/board.c @@ -8,7 +8,6 @@ #include <linux/sizes.h> #include <fcntl.h> #include <fs.h> -#include <mach/socfpga-regs.h> static int phy_fixup(struct phy_device *dev) { diff --git a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c index 117d7f4ebc..9367b0d110 100644 --- a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c +++ b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c @@ -27,7 +27,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include <mach/scan-manager.h> +#include <mach/cyclone5-scan-manager.h> static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, diff --git a/arch/arm/boards/terasic-sockit/lowlevel.c b/arch/arm/boards/terasic-sockit/lowlevel.c index 8012783df3..0a6eb21365 100644 --- a/arch/arm/boards/terasic-sockit/lowlevel.c +++ b/arch/arm/boards/terasic-sockit/lowlevel.c @@ -7,13 +7,13 @@ #include <debug_ll.h> #include <asm/cache.h> #include "sdram_config.h" -#include <mach/sdram_config.h> +#include <mach/cyclone5-sdram-config.h> #include "pinmux_config.c" #include "pll_config.h" #include <mach/pll_config.h> #include "sequencer_defines.h" #include "sequencer_auto.h" -#include <mach/sequencer.c> +#include <mach/cyclone5-sequencer.c> #include "sequencer_auto_inst_init.c" #include "sequencer_auto_ac_init.c" #include "iocsr_config_cyclone5.c" diff --git a/arch/arm/boards/vscom-baltos/board.c b/arch/arm/boards/vscom-baltos/board.c index 39f40a6061..1a4dc30936 100644 --- a/arch/arm/boards/vscom-baltos/board.c +++ b/arch/arm/boards/vscom-baltos/board.c @@ -64,7 +64,7 @@ static int baltos_read_eeprom(void) { struct bsp_vs_hwparam hw_param; size_t size; - char *buf, var_buf[32]; + char *buf; int rc; unsigned char mac_addr[6]; @@ -107,8 +107,7 @@ static int baltos_read_eeprom(void) hw_param.SystemId = 0; } - sprintf(var_buf, "%d", hw_param.SystemId); - globalvar_add_simple("board.id", var_buf); + globalvar_add_simple_uint32_fixed("board.id", hw_param.SystemId, "%u"); /* enable mPCIe slot */ gpio_direction_output(100, 1); @@ -131,7 +130,7 @@ static int baltos_devices_init(void) if (!of_machine_is_compatible("vscom,onrisc")) return 0; - globalvar_add_simple("board.variant", "baltos"); + globalvar_add_simple_string_fixed("board.variant", "baltos"); if (bootsource_get() == BOOTSOURCE_MMC) omap_set_bootmmc_devname("mmc0"); diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index df67cd0a92..ab837cc55f 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -1,6 +1,7 @@ CONFIG_ARCH_IMX=y CONFIG_IMX_MULTI_BOARDS=y CONFIG_MACH_EFIKA_MX_SMARTBOOK=y +CONFIG_MACH_KINDLE_MX50=y CONFIG_MACH_EMBEDSKY_E9=y CONFIG_MACH_FREESCALE_MX51_PDK=y CONFIG_MACH_CCMX53=y diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index dab3d7a45e..cfbccb5a14 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -112,6 +112,7 @@ CONFIG_USB_STORAGE=y CONFIG_MCI=y CONFIG_MCI_STARTUP=y CONFIG_MCI_MMC_BOOT_PARTITIONS=y +CONFIG_MCI_DOVE=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_LED_GPIO_OF=y diff --git a/arch/arm/configs/socfpga-arria10_defconfig b/arch/arm/configs/socfpga-arria10_defconfig new file mode 100644 index 0000000000..e661895d6e --- /dev/null +++ b/arch/arm/configs/socfpga-arria10_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARCH_SOCFPGA=y +CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES=y +CONFIG_THUMB2_BAREBOX=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_RELOCATABLE=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +# CONFIG_TIMESTAMP is not set +CONFIG_BOOTM_SHOW_TYPE=y +CONFIG_BOOTM_VERBOSE=y +CONFIG_BOOTM_INITRD=y +CONFIG_BOOTM_OFTREE=y +CONFIG_PBL_CONSOLE=y +CONFIG_DEFAULT_COMPRESSION_LZO=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_POLLER=y +CONFIG_STATE=y +CONFIG_DEBUG_INFO=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_ARM_MMUINFO=y +CONFIG_CMD_GO=y +CONFIG_CMD_RESET=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA256SUM=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_FIRMWARELOAD=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_STATE=y +CONFIG_NET=y +CONFIG_NET_NETCONSOLE=y +CONFIG_NET_RESOLV=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_OF_BAREBOX_ENV_IN_FS=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_NET_DESIGNWARE=y +CONFIG_MICREL_PHY=y +# CONFIG_SPI is not set +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_MMC_BOOT_PARTITIONS=y +CONFIG_MCI_DW=y +# CONFIG_PINCTRL is not set +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_ZLIB=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DIGEST_SHA256_ARM=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e8ad43bfd8..2342d35a4b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -12,6 +12,7 @@ pbl-dtb-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am pbl-dtb-$(CONFIG_MACH_CM_FX6) += imx6dl-cm-fx6.dtb.o imx6q-cm-fx6.dtb.o imx6q-utilite.dtb.o pbl-dtb-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o pbl-dtb-$(CONFIG_MACH_DUCKBILL) += imx28-duckbill.dtb.o +pbl-dtb-$(CONFIG_MACH_KINDLE_MX50) += imx50-kindle-d01100.dtb.o imx50-kindle-d01200.dtb.o imx50-kindle-ey21.dtb.o pbl-dtb-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o pbl-dtb-$(CONFIG_MACH_ELTEC_HIPERCAM) += imx6dl-eltec-hipercam.dtb.o pbl-dtb-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o @@ -65,10 +66,13 @@ pbl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o pbl-dtb-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o pbl-dtb-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o +pbl-dtb-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += socfpga_arria10_achilles.dtb.o pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o pbl-dtb-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o -pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o imx6q-h100.dtb.o +pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o \ + imx6dl-hummingboard2.dtb.o imx6q-hummingboard2.dtb.o \ + imx6q-h100.dtb.o pbl-dtb-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o pbl-dtb-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o pbl-dtb-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o diff --git a/arch/arm/dts/imx50-kindle-common.dtsi b/arch/arm/dts/imx50-kindle-common.dtsi new file mode 100644 index 0000000000..a6ea504f6c --- /dev/null +++ b/arch/arm/dts/imx50-kindle-common.dtsi @@ -0,0 +1,322 @@ +/* + * Copyright 2017 Alexander Kurz <akurz@blala.de> + * Copyright 2013 Greg Ungerer <gerg@uclinux.org> + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx50.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + /* this is a dummy fixed-voltage "regulator", mainly to satisfy + * the esdhc implementation requiring vmmc-supply and vqmmc-supply + */ + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&iomuxc { + imx50-kindle { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX50_PAD_UART1_TXD__UART1_TXD_MUX 0xe4 + MX50_PAD_UART1_RXD__UART1_RXD_MUX 0xe4 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x84 + MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x84 + MX50_PAD_ECSPI2_MISO__ECSPI2_MISO 0x84 + MX50_PAD_ECSPI2_SS0__GPIO4_19 0x84 + >; + }; + + pinctrl_cspi: cspigrp { + fsl,pins = < + MX50_PAD_CSPI_SCLK__CSPI_SCLK 0xc4 + MX50_PAD_CSPI_MISO__CSPI_MISO 0xc4 + MX50_PAD_CSPI_MOSI__CSPI_MOSI 0xc4 + MX50_PAD_CSPI_SS0__GPIO4_11 0xe4 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX50_PAD_UART1_CTS__GPIO6_8 0x84 + MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 0x84 + >; + }; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX50_PAD_SD3_CMD__ESDHC3_CMD 0xd4 + MX50_PAD_SD3_CLK__ESDHC3_CLK 0x00 + MX50_PAD_SD3_D0__ESDHC3_DAT0 0xd4 + MX50_PAD_SD3_D1__ESDHC3_DAT1 0xd4 + MX50_PAD_SD3_D2__ESDHC3_DAT2 0xd4 + MX50_PAD_SD3_D3__ESDHC3_DAT3 0xd4 + MX50_PAD_SD3_D4__ESDHC3_DAT4 0xd4 + MX50_PAD_SD3_D5__ESDHC3_DAT5 0xd4 + MX50_PAD_SD3_D6__ESDHC3_DAT6 0xd4 + MX50_PAD_SD3_D7__ESDHC3_DAT7 0xd4 + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX50_PAD_SD2_CMD__ESDHC2_CMD 0x84 + MX50_PAD_SD2_CLK__ESDHC2_CLK 0x84 + MX50_PAD_SD2_D0__ESDHC2_DAT0 0x84 + MX50_PAD_SD2_D1__ESDHC2_DAT1 0x84 + MX50_PAD_SD2_D2__ESDHC2_DAT2 0x84 + MX50_PAD_SD2_D3__ESDHC2_DAT3 0x84 + + MX50_PAD_EIM_DA5__GPIO1_5 0xe4 /* wake-on-lan */ + MX50_PAD_SD3_WP__GPIO5_28 0x84 /* power */ + MX50_PAD_DISP_RS__GPIO2_17 0xe4 /* ? */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX50_PAD_I2C1_SCL__I2C1_SCL 0x4000002c + MX50_PAD_I2C1_SDA__I2C1_SDA 0x4000002c + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX50_PAD_I2C2_SCL__I2C2_SCL 0x4000002c + MX50_PAD_I2C2_SDA__I2C2_SDA 0x4000002c + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX50_PAD_I2C3_SCL__I2C3_SCL 0x4000002c + MX50_PAD_I2C3_SDA__I2C3_SDA 0x4000002c + >; + }; + + pinctrl_charger_detect: chargerdetectgrp { + fsl,pins = < + MX50_PAD_OWIRE__GPIO6_26 0x84 + >; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3>; + non-removable; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + kernel: kernel@0x41000 { + label = "kernel"; + reg = <0x41000 0xe00000>; + }; + + diags_kernel: diags_kernel@0xe41000 { + label = "diags_kernel"; + reg = <0xe41000 0xe00000>; + }; + }; + + boot0-partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + imx_header: imx_header@0x400 { + label = "imx_header"; + reg = <0x400 0x800>; + }; + + self: self@0x1000 { + label = "self"; + reg = <0x1000 0x3e000>; + }; + + userdata: userdata@0x3f000 { + label = "userdata"; + reg = <0x3f000 0x1400>; + }; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 19 0>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <1000000>; + reg = <0>; + }; +}; + +&cspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 11 0>; + status = "okay"; + + pmic: mc13892@0 { + compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + spi-max-frequency = <1000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio6>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-rtc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0 0xff8 0 0>; + ledg { + reg = <2>; + label = "pmic_ledsg"; + linux,default-trigger = "heartbeat"; + }; + }; + }; +}; + +&usbotg { + phy_type = "utmi"; + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/dts/imx50-kindle-d01100.dts b/arch/arm/dts/imx50-kindle-d01100.dts new file mode 100644 index 0000000000..edbc929120 --- /dev/null +++ b/arch/arm/dts/imx50-kindle-d01100.dts @@ -0,0 +1,71 @@ +/* + * Copyright 2017 Alexander Kurz <akurz@blala.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx50-kindle-common.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Amazon Kindle D01100"; + compatible = "fsl,imx50"; + + chosen { + linux,stdout-path = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0x70000000 0x10000000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx50-kindle-d01100 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX50_PAD_EIM_EB1__GPIO1_20 0xc0 + MX50_PAD_EIM_EB0__GPIO1_19 0xc0 + MX50_PAD_EIM_CS2__GPIO1_16 0xc0 + MX50_PAD_EIM_CS1__GPIO1_17 0xc0 + MX50_PAD_EIM_CS0__GPIO1_18 0xc0 + MX50_PAD_SSI_RXC__GPIO6_5 0x84 + >; + }; + }; +}; + +&i2c2 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + max14656@35 { + compatible = "maxim,max14656"; + reg = <0x35>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_charger_detect>; + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; + }; + + smart-battery@55 { + compatible = "ti,bq27210"; + reg = <0x55>; + ti,i2c-retry-count = <2>; + ti,poll-retry-count = <10>; + }; +}; diff --git a/arch/arm/dts/imx50-kindle-d01200.dts b/arch/arm/dts/imx50-kindle-d01200.dts new file mode 100644 index 0000000000..8f93c1b520 --- /dev/null +++ b/arch/arm/dts/imx50-kindle-d01200.dts @@ -0,0 +1,86 @@ +/* + * Copyright 2017 Alexander Kurz <akurz@blala.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx50-kindle-common.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Amazon Kindle D01200"; + compatible = "fsl,imx50"; + + chosen { + linux,stdout-path = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0x70000000 0x10000000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx50-kindle-d01200 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX50_PAD_EIM_DA0__GPIO1_0 0xc0 + MX50_PAD_SSI_RXC__GPIO6_5 0x84 + >; + }; + }; +}; + +&i2c1 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + mma8453: mma8453@1c { + compatible = "fsl,mma8453"; + reg = <0x1c>; + }; +}; + +&i2c2 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + max14656@35 { + compatible = "maxim,max14656"; + reg = <0x35>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_charger_detect>; + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; + }; + + smart-battery@55 { + compatible = "ti,bq27210"; + reg = <0x55>; + ti,i2c-retry-count = <2>; + ti,poll-retry-count = <10>; + }; +}; + +&i2c3 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx50-kindle-ey21.dts b/arch/arm/dts/imx50-kindle-ey21.dts new file mode 100644 index 0000000000..1b8f2ad89a --- /dev/null +++ b/arch/arm/dts/imx50-kindle-ey21.dts @@ -0,0 +1,66 @@ +/* + * Copyright 2017 Alexander Kurz <akurz@blala.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx50-kindle-common.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Amazon Kindle EY21"; + compatible = "fsl,imx50"; + + memory { + device_type = "memory"; + reg = <0x70000000 0x10000000>; + }; +}; + +&iomuxc { + imx50-kindle-ey21 { + pinctrl_gpiokey: gpiokeygrp { + fsl,pins = < + MX50_PAD_EIM_EB1__GPIO1_20 0x40 + >; + }; + }; +}; + +&i2c2 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + max14656@35 { + compatible = "maxim,max14656"; + reg = <0x35>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_charger_detect>; + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; + }; + + smart-battery@55 { + compatible = "ti,bq27210"; + reg = <0x55>; + ti,i2c-retry-count = <2>; + ti,poll-retry-count = <10>; + }; +}; + +&i2c3 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx50.dtsi b/arch/arm/dts/imx50.dtsi new file mode 100644 index 0000000000..8737d4f33f --- /dev/null +++ b/arch/arm/dts/imx50.dtsi @@ -0,0 +1,40 @@ +#include <arm/imx50.dtsi> + +/ { + soc { + aips@50000000 { /* AIPS1 */ + usbphy0: usbphy@0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; + clock-names = "main_clk"; + status = "okay"; + }; + + usbphy1: usbphy@1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; + clock-names = "main_clk"; + status = "okay"; + }; + + usbmisc: usbmisc@53f80800 { + #index-cells = <1>; + compatible = "fsl,imx53-usbmisc"; + reg = <0x53f80800 0x200>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + }; + }; + }; +}; + +&usbotg { + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; +}; + +&usbh1 { + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; +}; diff --git a/arch/arm/dts/imx6dl-hummingboard2.dts b/arch/arm/dts/imx6dl-hummingboard2.dts new file mode 100644 index 0000000000..40ef174411 --- /dev/null +++ b/arch/arm/dts/imx6dl-hummingboard2.dts @@ -0,0 +1,71 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com> + * Based on work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include <arm/imx6dl.dtsi> +#include "imx6qdl-hummingboard2.dtsi" + +/ { + model = "SolidRun HummingBoard2 Solo/DualLite"; + compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; +}; + +&ocotp { + barebox,provide-mac-address = <&fec 0x620>; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; diff --git a/arch/arm/dts/imx6q-hummingboard2.dts b/arch/arm/dts/imx6q-hummingboard2.dts new file mode 100644 index 0000000000..89065581b8 --- /dev/null +++ b/arch/arm/dts/imx6q-hummingboard2.dts @@ -0,0 +1,87 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com> + * Based on work by Russell King + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; + +#include <arm/imx6q.dtsi> +#include "imx6qdl-hummingboard2.dtsi" +#include "imx6q.dtsi" + +/ { + model = "SolidRun HummingBoard2 Dual/Quad"; + compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; + + chosen { + environment@0 { + compatible = "barebox,environment"; + device-path = &usdhc3, "partname:barebox-environment"; + }; + }; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; +}; + +&ocotp { + barebox,provide-mac-address = <&fec 0x620>; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; diff --git a/arch/arm/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/dts/imx6qdl-hummingboard2.dtsi new file mode 100644 index 0000000000..2a5f389378 --- /dev/null +++ b/arch/arm/dts/imx6qdl-hummingboard2.dtsi @@ -0,0 +1,536 @@ +/* + * Device Tree file for SolidRun HummingBoard2 + * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include <arm/imx6qdl-microsom.dtsi> +#include <arm/imx6qdl-microsom-ar8035.dtsi> + +/ { + chosen { + stdout-path = &uart1; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_gpio7_9>; + linux,rc-map-name = "rc-rc6-mce"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_usbh2_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbh1_vbus>; + regulator-name = "V_USB2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbotg_vbus>; + regulator-name = "V_USB1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh3_vbus: regulator-usb-h2-vbus { + compatible = "regulator-fixed"; + enable-active-high; + enable-gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbh2_vbus>; + regulator-name = "V_USB3"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usbh4_vbus: regulator-usb-h3-vbus { + compatible = "regulator-fixed"; + enable-active-high; + enable-gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbh3_vbus>; + regulator-name = "V_USB4"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usdhc2_vmmc: reg-usdhc2-vmmc { + compatible = "regulator-fixed"; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_vmmc>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "V_SD"; + startup-delay-us = <1000>; + }; + + sound-sgtl5000 { + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + compatible = "fsl,imx-audio-sgtl5000"; + model = "On-board Codec"; + mux-ext-port = <5>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; +}; + +&audmux { + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>; + cs-gpios = <&gpio2 26 0>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_i2c1>; + status = "okay"; + + pcf8523: rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + + sgtl5000: codec@0a { + clocks = <&clks IMX6QDL_CLK_CKO>; + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_sgtl5000>; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p8v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hummingboard2 { + pinctrl_hog: hoggrp { + fsl,pins = < + /* + * 36 pin headers GPIO description. The pins + * numbering as following - + * + * 3.2v 5v 74 75 + * 73 72 71 70 + * 69 68 67 66 + * + * 77 78 79 76 + * 65 64 61 60 + * 53 52 51 50 + * 49 48 166 132 + * 95 94 90 91 + * GND 54 24 204 + * + * The GPIO numbers can be extracted using + * signal name from below. + * Example - + * MX6QDL_PAD_EIM_DA10__GPIO3_IO10 is + * GPIO(3,10) which is (3-1)*32+10 = gpio 74 + * + * i.e. The mapping of GPIO(X,Y) to Linux gpio + * number is : gpio number = (X-1) * 32 + Y + */ + /* DI1_PIN15 */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x400130b1 + /* DI1_PIN02 */ + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x400130b1 + /* DISP1_DATA00 */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 + /* DISP1_DATA01 */ + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 + /* DISP1_DATA02 */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 + /* DISP1_DATA03 */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 + /* DISP1_DATA04 */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x400130b1 + /* DISP1_DATA05 */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x400130b1 + /* DISP1_DATA06 */ + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 + /* DISP1_DATA07 */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x400130b1 + /* DI1_D0_CS */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x400130b1 + /* DI1_D1_CS */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x400130b1 + /* DI1_PIN01 */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x400130b1 + /* DI1_PIN03 */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x400130b1 + /* DISP1_DATA08 */ + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x400130b1 + /* DISP1_DATA09 */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x400130b1 + /* DISP1_DATA10 */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x400130b1 + /* DISP1_DATA11 */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x400130b1 + /* DISP1_DATA12 */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x400130b1 + /* DISP1_DATA13 */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x400130b1 + /* DISP1_DATA14 */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x400130b1 + /* DISP1_DATA15 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x400130b1 + /* DISP1_DATA16 */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x400130b1 + /* DISP1_DATA17 */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x400130b1 + /* DISP1_DATA18 */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x400130b1 + /* DISP1_DATA19 */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x400130b1 + /* DISP1_DATA20 */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x400130b1 + /* DISP1_DATA21 */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x400130b1 + /* DISP1_DATA22 */ + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x400130b1 + /* DISP1_DATA23 */ + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400130b1 + /* DI1_DISP_CLK */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x400130b1 + /* SPDIF_IN */ + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x400130b1 + /* SPDIF_OUT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x400130b1 + + /* MikroBUS GPIO pin number 10 */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 + >; + }; + + pinctrl_hummingboard2_ecspi2: hummingboard2-ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 /* CS */ + >; + }; + + pinctrl_hummingboard2_gpio7_9: hummingboard2-gpio7_9 { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x80000000 + >; + }; + + pinctrl_hummingboard2_hdmi: hummingboard2-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hummingboard2_i2c1: hummingboard2-i2c1 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard2_i2c2: hummingboard2-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard2_i2c3: hummingboard2-i2c3 { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard2_mipi: hummingboard2_mipi { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x4001b8b1 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x4001b8b1 + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 + >; + }; + + pinctrl_hummingboard2_pcie_reset: hummingboard2-pcie-reset { + fsl,pins = < + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b1 + >; + }; + + pinctrl_hummingboard2_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_hummingboard2_sgtl5000: hummingboard2-sgtl5000 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_hummingboard2_usbh1_vbus: hummingboard2-usbh1-vbus { + fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>; + }; + + pinctrl_hummingboard2_usbh2_vbus: hummingboard2-usbh2-vbus { + fsl,pins = <MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0>; + }; + + pinctrl_hummingboard2_usbh3_vbus: hummingboard2-usbh3-vbus { + fsl,pins = <MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x1b0b0>; + }; + + pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id { + /* + * Similar to pinctrl_usbotg_2, but we want it + * pulled down for a fixed host connection. + */ + fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>; + }; + + pinctrl_hummingboard2_usbotg_vbus: hummingboard2-usbotg-vbus { + fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>; + }; + + pinctrl_hummingboard2_usdhc2_aux: hummingboard2-usdhc2-aux { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 + >; + }; + + pinctrl_hummingboard2_usdhc2: hummingboard2-usdhc2 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 + >; + }; + + pinctrl_hummingboard2_usdhc2_100mhz: hummingboard2-usdhc2-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 + >; + }; + + pinctrl_hummingboard2_usdhc2_200mhz: hummingboard2-usdhc2-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 + >; + }; + + pinctrl_hummingboard2_vmmc: hummingboard2-vmmc { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_hummingboard2_usdhc3: hummingboard2-usdhc3 { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 + >; + }; + + pinctrl_hummingboard2_uart3: hummingboard2-uart3 { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x40013000 + >; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_pcie_reset>; + reset-gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_pwm1>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbotg { + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usbotg_id>; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = < + &pinctrl_hummingboard2_usdhc2_aux + &pinctrl_hummingboard2_usdhc2 + >; + pinctrl-1 = < + &pinctrl_hummingboard2_usdhc2_aux + &pinctrl_hummingboard2_usdhc2_100mhz + >; + pinctrl-2 = < + &pinctrl_hummingboard2_usdhc2_aux + &pinctrl_hummingboard2_usdhc2_200mhz + >; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_usdhc3>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard2_uart3>; + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 274c491804..b3a7f69ffe 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -10,22 +10,6 @@ aliases { mmc0 = &mmc; }; - - soc { - qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; - interrupts = <0 151 4>; - ext-decoder = <0>; /* external decoder */ - fifo-depth = <128>; - clocks = <&qspi_clk>; - clock-names = "qspi_clk"; - status = "disabled"; - }; - }; }; &osc2 { clock-frequency = <0>; diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts b/arch/arm/dts/socfpga_arria10_achilles.dts new file mode 100644 index 0000000000..dd991318e2 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_achilles.dts @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2015 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +/dts-v1/; +#include <arm/socfpga_arria10.dtsi> + +/ { + model = "Reflex SOCFPGA Arria 10 Achilles"; + compatible = "reflex,achilles", "altr,socfpga-arria10", "altr,socfpga"; + + aliases { + serial0 = &uart0; + }; + + chosen { + linux,stdout-path = &uart0; + + environment@0 { + compatible = "barebox,environment"; + device-path = &mmc, "partname:1"; + file-path = "barebox.env"; + }; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0xc0000000>; + }; + + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + + cb_intosc_hs_div2_clk { + clock-frequency = <0>; + }; + cb_intosc_ls_clk { + clock-frequency = <60000000>; + }; + f2s_free_clk { + clock-frequency = <200000000>; + }; + }; + }; + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + phy-addr = <0x00fffff0>; /* probe for phy addr */ + + /* + * These skews assume the user's FPGA design is adding 600ps of delay + * for TX_CLK on Arria 10. + * + * All skews are offset since hardware skew values for the ksz9031 + * range from a negative skew to a positive skew. + * See the micrel-ksz90x1.txt Documentation file for details. + */ + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + max-frame-size = <3800>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + tempsensor: ti,tmp102@0x48 { + compatible = "ti,tmp102"; + reg = <0x48>; + }; + + rtc: nxp,pcf8563@0x51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + eeprom: at24@0x54 { + compatible = "at24"; + reg = <0x54>; + bytelen = <256>; + pagesize = <16>; + }; +}; + +&mmc { + supports-highspeed; + broken-cd; + bus-width = <1>; + status = "okay"; +}; + +&uart0 { + reg-io-width = <4>; + status = "okay"; +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 9c03a5935e..80f53ce124 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -212,6 +212,20 @@ config MACH_PCM038 Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped with a Freescale i.MX27 Processor +config MACH_KINDLE_MX50 + bool "i.MX50 based Amazon Kindle 4 and 5" + select ARCH_IMX50 + select SPI + select DRIVER_SPI_IMX + select I2C + select I2C_IMX + select MFD_MC13XXX + select ARM_BOARD_APPEND_ATAG + help + Say Y here if you are using the fourth or fifth generation Amazon + Kindle Model No. D01100 (Kindle Wi-Fi), D01200 (Kindle Touch) or + EY21 (Kindle Paperwhite). + config MACH_EFIKA_MX_SMARTBOOK bool "Efika MX smartbook" select ARCH_IMX51 diff --git a/arch/arm/mach-omap/am33xx_bbu_emmc.c b/arch/arm/mach-omap/am33xx_bbu_emmc.c index 3220575cd4..d3adb3744c 100644 --- a/arch/arm/mach-omap/am33xx_bbu_emmc.c +++ b/arch/arm/mach-omap/am33xx_bbu_emmc.c @@ -39,7 +39,7 @@ static int emmc_mlo_handler(struct bbu_handler *handler, struct bbu_data *data) if (ret != 0) return ret; - fd = open(handler->devicefile, O_WRONLY); + fd = open(handler->devicefile, O_RDWR); if (fd < 0) { pr_err("could not open %s: %s\n", handler->devicefile, errno_str()); diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 04b5416b64..caff566bdc 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -12,16 +12,40 @@ config ARCH_TEXT_BASE hex default 0x00100000 if MACH_SOCFPGA_CYCLONE5 +comment "Altera SoCFPGA System-on-Chip" + +config ARCH_SOCFPGA_CYCLONE5 + bool + select CPU_V7 + +config ARCH_SOCFPGA_ARRIA10 + bool + select CPU_V7 + select HAVE_MACH_ARM_HEAD + config MACH_SOCFPGA_ALTERA_SOCDK + select HAVE_DEFAULT_ENVIRONMENT_NEW + select ARCH_SOCFPGA_CYCLONE5 bool "Altera SoCFPGA Development Kit" config MACH_SOCFPGA_EBV_SOCRATES + select HAVE_DEFAULT_ENVIRONMENT_NEW + select ARCH_SOCFPGA_CYCLONE5 bool "EBV Socrates" +config MACH_SOCFPGA_REFLEX_ACHILLES + select HAVE_DEFAULT_ENVIRONMENT_NEW + select ARCH_SOCFPGA_ARRIA10 + bool "Reflex Achilles" + config MACH_SOCFPGA_TERASIC_DE0_NANO_SOC + select HAVE_DEFAULT_ENVIRONMENT_NEW + select ARCH_SOCFPGA_CYCLONE5 bool "Terasic DE0-NANO-SoC aka Atlas" config MACH_SOCFPGA_TERASIC_SOCKIT + select HAVE_DEFAULT_ENVIRONMENT_NEW + select ARCH_SOCFPGA_CYCLONE5 bool "Terasic SoCKit" endif diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index dea0e075d1..cbb47fa206 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -1,4 +1,8 @@ -obj-y += generic.o nic301.o bootsource.o reset-manager.o -pbl-y += init.o freeze-controller.o scan-manager.o system-manager.o -pbl-y += clock-manager.o +pbl-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-init.o cyclone5-freeze-controller.o cyclone5-scan-manager.o cyclone5-system-manager.o +pbl-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-clock-manager.o +obj-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-generic.o nic301.o cyclone5-bootsource.o cyclone5-reset-manager.o + +pbl-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += arria10-init.o arria10-clock-manager.o arria10-sdram.o arria10-reset-manager.o arria10-bootsource.o +obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += arria10-bootsource.o arria10-generic.o arria10-reset-manager.o + obj-$(CONFIG_ARCH_SOCFPGA_XLOAD) += xload.o diff --git a/arch/arm/mach-socfpga/bootsource.c b/arch/arm/mach-socfpga/arria10-bootsource.c index 739f0b5c0e..26af64a1a4 100644 --- a/arch/arm/mach-socfpga/bootsource.c +++ b/arch/arm/mach-socfpga/arria10-bootsource.c @@ -13,22 +13,18 @@ #include <common.h> #include <bootsource.h> -#include <environment.h> #include <init.h> #include <io.h> -#include <mach/socfpga-regs.h> -#include <mach/system-manager.h> +#include <mach/arria10-system-manager.h> -#define SYSMGR_BOOTINFO 0x14 - -static int socfpga_boot_save_loc(void) +static int arria10_boot_save_loc(void) { enum bootsource src = BOOTSOURCE_UNKNOWN; uint32_t val; - val = readl(CYCLONE5_SYSMGR_ADDRESS + SYSMGR_BOOTINFO); + val = readl(ARRIA10_SYSMGR_BOOTINFO); - switch (val & 0x7) { + switch ((val & 0x7000) >> 12) { case 0: /* reserved */ break; @@ -54,4 +50,4 @@ static int socfpga_boot_save_loc(void) return 0; } -core_initcall(socfpga_boot_save_loc); +core_initcall(arria10_boot_save_loc); diff --git a/arch/arm/mach-socfpga/arria10-clock-manager.c b/arch/arm/mach-socfpga/arria10-clock-manager.c new file mode 100644 index 0000000000..8052afe2d8 --- /dev/null +++ b/arch/arm/mach-socfpga/arria10-clock-manager.c @@ -0,0 +1,815 @@ +/* + * Copyright (C) 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/generic.h> +#include <mach/arria10-regs.h> +#include <mach/arria10-clock-manager.h> + +static const struct arria10_clock_manager *arria10_clkmgr_base = + (void *)ARRIA10_CLKMGR_ADDR; + +static uint32_t eosc1_hz; +static uint32_t cb_intosc_hz; +static uint32_t f2s_free_hz; +#define LOCKED_MASK (ARRIA10_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \ + ARRIA10_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK) + +static inline void arria10_cm_wait_for_lock(uint32_t mask) +{ + register uint32_t inter_val; + + do { + inter_val = readl(&arria10_clkmgr_base->stat) & mask; + } while (inter_val != mask); +} + +/* function to poll in the fsm busy bit */ +static inline void arria10_cm_wait4fsm(void) +{ + register uint32_t inter_val; + + do { + inter_val = readl(&arria10_clkmgr_base->stat) & + ARRIA10_CLKMGR_CLKMGR_STAT_BUSY_SET_MSK; + } while (inter_val); +} + +static uint32_t arria10_cm_get_main_vco(void) +{ + uint32_t vco1, src_hz, numer, denom, vco; + uint32_t clk_src = readl(&arria10_clkmgr_base->main_pll_vco0); + + clk_src = (clk_src >> ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_LSB) & + ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_MSK; + + switch (clk_src) { + case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_EOSC: + src_hz = eosc1_hz; + break; + case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: + src_hz = cb_intosc_hz; + break; + case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_F2S: + src_hz = f2s_free_hz; + break; + default: + pr_err("arria10_cm_get_main_vco invalid clk_src %d\n", clk_src); + return 0; + } + + vco1 = readl(&arria10_clkmgr_base->main_pll_vco1); + numer = vco1 & ARRIA10_CLKMGR_MAINPLL_VCO1_NUMER_MSK; + denom = (vco1 >> ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) & + ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_MSK; + vco = src_hz * (1 + numer); + vco /= 1 + denom; + + return vco; +} + +static uint32_t arria10_cm_get_peri_vco(void) +{ + uint32_t vco1, src_hz, numer, denom, vco; + uint32_t clk_src = readl(&arria10_clkmgr_base->per_pll_vco0); + + clk_src = (clk_src >> ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_LSB) & + ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MSK; + + switch (clk_src) { + case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_EOSC: + src_hz = eosc1_hz; + break; + case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: + src_hz = cb_intosc_hz; + break; + case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_F2S: + src_hz = f2s_free_hz; + break; + case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MAIN: + src_hz = arria10_cm_get_main_vco(); + src_hz /= (readl(&arria10_clkmgr_base->main_pll_cntr15clk) & + ARRIA10_CLKMGR_MAINPLL_CNTRCLK_MSK) + 1; + break; + default: + pr_err("arria10_cm_get_peri_vco invalid clk_src %d\n", clk_src); + return 0; + } + + vco1 = readl(&arria10_clkmgr_base->per_pll_vco1); + numer = vco1 & ARRIA10_CLKMGR_PERPLL_VCO1_NUMER_MSK; + denom = (vco1 >> ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) & + ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_MSK; + vco = src_hz * (1 + numer); + vco /= 1 + denom; + + return vco; +} + +unsigned int arria10_cm_get_mmc_controller_clk_hz(void) +{ + uint32_t clk_hz = 0; + uint32_t clk_input = readl(&arria10_clkmgr_base->per_pll_cntr6clk); + clk_input = (clk_input >> ARRIA10_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB) & + ARRIA10_CLKMGR_PERPLLGRP_SRC_MSK; + + switch (clk_input) { + case ARRIA10_CLKMGR_PERPLLGRP_SRC_MAIN: + clk_hz = arria10_cm_get_main_vco(); + clk_hz /= 1 + (readl(&arria10_clkmgr_base->main_pll_cntr6clk) & + ARRIA10_CLKMGR_MAINPLL_CNTRCLK_MSK); + break; + + case ARRIA10_CLKMGR_PERPLLGRP_SRC_PERI: + clk_hz = arria10_cm_get_peri_vco(); + clk_hz /= 1 + (readl(&arria10_clkmgr_base->per_pll_cntr6clk) & + ARRIA10_CLKMGR_PERPLL_CNTRCLK_MSK); + break; + + case ARRIA10_CLKMGR_PERPLLGRP_SRC_OSC1: + clk_hz = eosc1_hz; + break; + + case ARRIA10_CLKMGR_PERPLLGRP_SRC_INTOSC: + clk_hz = cb_intosc_hz; + break; + + case ARRIA10_CLKMGR_PERPLLGRP_SRC_FPGA: + clk_hz = f2s_free_hz; + break; + } + + return clk_hz/4; +} + +/* calculate the intended main VCO frequency based on handoff */ +static uint32_t arria10_cm_calc_handoff_main_vco_clk_hz(struct arria10_mainpll_cfg *main_cfg) +{ + uint32_t clk_hz; + + /* Check main VCO clock source: eosc, intosc or f2s? */ + switch (main_cfg->vco0_psrc) { + case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_EOSC: + clk_hz = eosc1_hz; + break; + case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: + clk_hz = cb_intosc_hz; + break; + case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_F2S: + clk_hz = f2s_free_hz; + break; + default: + return 0; + } + + /* calculate the VCO frequency */ + clk_hz *= 1 + main_cfg->vco1_numer; + clk_hz /= 1 + main_cfg->vco1_denom; + + return clk_hz; +} + +/* calculate the intended periph VCO frequency based on handoff */ +static uint32_t arria10_cm_calc_handoff_periph_vco_clk_hz(struct arria10_mainpll_cfg *main_cfg, + struct arria10_perpll_cfg *per_cfg) +{ + uint32_t clk_hz; + + /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */ + switch (per_cfg->vco0_psrc) { + case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_EOSC: + clk_hz = eosc1_hz; + break; + case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: + clk_hz = cb_intosc_hz; + break; + case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_F2S: + clk_hz = f2s_free_hz; + break; + case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MAIN: + clk_hz = arria10_cm_calc_handoff_main_vco_clk_hz(main_cfg); + clk_hz /= main_cfg->cntr15clk_cnt; + break; + default: + return 0; + } + + /* calculate the VCO frequency */ + clk_hz *= 1 + per_cfg->vco1_numer; + clk_hz /= 1 + per_cfg->vco1_denom; + + return clk_hz; +} + +/* calculate the intended MPU clock frequency based on handoff */ +static uint32_t arria10_cm_calc_handoff_mpu_clk_hz(struct arria10_mainpll_cfg *main_cfg, + struct arria10_perpll_cfg *per_cfg) +{ + uint32_t clk_hz; + + /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ + switch (main_cfg->mpuclk_src) { + case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN: + clk_hz = arria10_cm_calc_handoff_main_vco_clk_hz(main_cfg); + clk_hz /= ((main_cfg->mpuclk & ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + + 1); + break; + case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI: + clk_hz = arria10_cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); + clk_hz /= (((main_cfg->mpuclk >> + ARRIA10_CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & + ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1); + break; + case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_OSC1: + clk_hz = eosc1_hz; + break; + case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC: + clk_hz = cb_intosc_hz; + break; + case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_FPGA: + clk_hz = f2s_free_hz; + break; + default: + return 0; + } + + clk_hz /= (main_cfg->mpuclk_cnt + 1); + + return clk_hz; +} + +/* calculate the intended NOC clock frequency based on handoff */ +static uint32_t arria10_cm_calc_handoff_noc_clk_hz(struct arria10_mainpll_cfg *main_cfg, + struct arria10_perpll_cfg *per_cfg) +{ + uint32_t clk_hz; + + /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ + switch (main_cfg->nocclk_src) { + case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN: + clk_hz = arria10_cm_calc_handoff_main_vco_clk_hz(main_cfg); + clk_hz /= ((main_cfg->nocclk & ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + + 1); + break; + case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI: + clk_hz = arria10_cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); + clk_hz /= (((main_cfg->nocclk >> + ARRIA10_CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & + ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1); + break; + case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_OSC1: + clk_hz = eosc1_hz; + break; + case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC: + clk_hz = cb_intosc_hz; + break; + case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_FPGA: + clk_hz = f2s_free_hz; + break; + default: + return 0; + } + + clk_hz /= (main_cfg->nocclk_cnt + 1); + + return clk_hz; +} + +/* return 1 if PLL ramp is required */ +static int arria10_cm_is_pll_ramp_required(int main0periph1, + struct arria10_mainpll_cfg *main_cfg, + struct arria10_perpll_cfg *per_cfg) +{ + + /* Check for main PLL */ + if (main0periph1 == 0) { + /* + * PLL ramp is not required if both MPU clock and NOC clock are + * not sourced from main PLL + */ + if (main_cfg->mpuclk_src != ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && + main_cfg->nocclk_src != ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) + return 0; + + /* + * PLL ramp is required if MPU clock is sourced from main PLL + * and MPU clock is over 900MHz (as advised by HW team) + */ + if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && + (arria10_cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > + ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) + return 1; + + /* + * PLL ramp is required if NOC clock is sourced from main PLL + * and NOC clock is over 300MHz (as advised by HW team) + */ + if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN && + (arria10_cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > + ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) + return 1; + + } else if (main0periph1 == 1) { + /* + * PLL ramp is not required if both MPU clock and NOC clock are + * not sourced from periph PLL + */ + if (main_cfg->mpuclk_src != ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI && + main_cfg->nocclk_src != ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI) + return 0; + + /* + * PLL ramp is required if MPU clock are source from periph PLL + * and MPU clock is over 900MHz (as advised by HW team) + */ + if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI && + (arria10_cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > + ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) + return 1; + + /* + * PLL ramp is required if NOC clock are source from periph PLL + * and NOC clock is over 300MHz (as advised by HW team) + */ + if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI && + (arria10_cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > + ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) + return 1; + } + + return 0; +} + +/* + * Calculate the new PLL numerator which is based on existing DTS hand off and + * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the + * numerator while maintaining denominator as denominator will influence the + * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final + * value for numerator is minus with 1 to cater our register value + * representation. + */ +static uint32_t arria10_cm_calc_safe_pll_numer(int main0periph1, + struct arria10_mainpll_cfg *main_cfg, + struct arria10_perpll_cfg *per_cfg, + uint32_t safe_hz) +{ + uint32_t clk_hz = 0; + + /* Check for main PLL */ + if (main0periph1 == 0) { + /* Check main VCO clock source: eosc, intosc or f2s? */ + switch (main_cfg->vco0_psrc) { + case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_EOSC: + clk_hz = eosc1_hz; + break; + case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: + clk_hz = cb_intosc_hz; + break; + case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_F2S: + clk_hz = f2s_free_hz; + break; + default: + return 0; + } + + /* Applicable if MPU clock is from main PLL */ + if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { + /* calculate the safe numer value */ + clk_hz = (safe_hz / clk_hz) * + (main_cfg->mpuclk_cnt + 1) * + ((main_cfg->mpuclk & + ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1) * + (1 + main_cfg->vco1_denom) - 1; + } + /* Reach here if MPU clk not from main PLL but NOC clk is */ + else if (main_cfg->nocclk_src == + ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { + /* calculate the safe numer value */ + clk_hz = (safe_hz / clk_hz) * + (main_cfg->nocclk_cnt + 1) * + ((main_cfg->nocclk & + ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1) * + (1 + main_cfg->vco1_denom) - 1; + } else { + clk_hz = 0; + } + + } else if (main0periph1 == 1) { + /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */ + switch (per_cfg->vco0_psrc) { + case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_EOSC: + clk_hz = eosc1_hz; + break; + case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: + clk_hz = cb_intosc_hz; + break; + case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_F2S: + clk_hz = f2s_free_hz; + break; + case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MAIN: + clk_hz = arria10_cm_calc_handoff_main_vco_clk_hz( + main_cfg); + clk_hz /= main_cfg->cntr15clk_cnt; + break; + default: + return 0; + } + /* Applicable if MPU clock is from periph PLL */ + if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { + /* calculate the safe numer value */ + clk_hz = (safe_hz / clk_hz) * + (main_cfg->mpuclk_cnt + 1) * + (((main_cfg->mpuclk >> + ARRIA10_CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & + ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1) * + (1 + per_cfg->vco1_denom) - 1; + } + /* Reach here if MPU clk not from periph PLL but NOC clk is */ + else if (main_cfg->nocclk_src == + ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { + /* calculate the safe numer value */ + clk_hz = (safe_hz / clk_hz) * + (main_cfg->nocclk_cnt + 1) * + (((main_cfg->nocclk >> + ARRIA10_CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & + ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1) * + (1 + per_cfg->vco1_denom) - 1; + } else { + clk_hz = 0; + } + } + + return clk_hz; +} + +/* ramping the main PLL to final value */ +static void arria10_cm_pll_ramp_main(struct arria10_mainpll_cfg *main_cfg, + struct arria10_perpll_cfg *per_cfg, + uint32_t pll_ramp_main_hz) +{ + uint32_t clk_hz = 0; + uint32_t clk_incr_hz = 0; + uint32_t clk_final_hz = 0; + + /* find out the increment value */ + if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { + clk_incr_hz = ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; + clk_final_hz = arria10_cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); + } else if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { + clk_incr_hz = ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; + clk_final_hz = arria10_cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); + } + + /* execute the ramping here */ + for (clk_hz = pll_ramp_main_hz + clk_incr_hz; + clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { + writel((main_cfg->vco1_denom << ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) | + arria10_cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz), + &arria10_clkmgr_base->main_pll_vco1); + __udelay(1000); + arria10_cm_wait_for_lock(LOCKED_MASK); + } + + writel((main_cfg->vco1_denom << ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) | + main_cfg->vco1_numer, &arria10_clkmgr_base->main_pll_vco1); + + __udelay(1000); + arria10_cm_wait_for_lock(LOCKED_MASK); +} + +/* ramping the periph PLL to final value */ +static void arria10_cm_pll_ramp_periph(struct arria10_mainpll_cfg *main_cfg, + struct arria10_perpll_cfg *per_cfg, + uint32_t pll_ramp_periph_hz) +{ + uint32_t clk_hz = 0; + uint32_t clk_incr_hz = 0; + uint32_t clk_final_hz = 0; + + /* find out the increment value */ + if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { + clk_incr_hz = ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; + clk_final_hz = arria10_cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); + } else if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { + clk_incr_hz = ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; + clk_final_hz = arria10_cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); + } + + /* execute the ramping here */ + for (clk_hz = pll_ramp_periph_hz + clk_incr_hz; + clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { + writel((per_cfg->vco1_denom << ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) | + arria10_cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz), + &arria10_clkmgr_base->per_pll_vco1); + __udelay(1000); + arria10_cm_wait_for_lock(LOCKED_MASK); + } + + writel((per_cfg->vco1_denom << ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) | + per_cfg->vco1_numer, &arria10_clkmgr_base->per_pll_vco1); + __udelay(1000); + arria10_cm_wait_for_lock(LOCKED_MASK); +} + +/* + * Setup clocks while making no assumptions of the + * previous state of the clocks. + * + * - Start by being paranoid and gate all sw managed clocks + * - Put all plls in bypass + * - Put all plls VCO registers back to reset value (bgpwr dwn). + * - Put peripheral and main pll src to reset value to avoid glitch. + * - Delay 5 us. + * - Deassert bg pwr dn and set numerator and denominator + * - Start 7 us timer. + * - set internal dividers + * - Wait for 7 us timer. + * - Enable plls + * - Set external dividers while plls are locking + * - Wait for pll lock + * - Assert/deassert outreset all. + * - Take all pll's out of bypass + * - Clear safe mode + * - set source main and peripheral clocks + * - Ungate clocks + */ +static int arria10_cm_full_cfg(struct arria10_mainpll_cfg *main_cfg, + struct arria10_perpll_cfg *per_cfg) +{ + uint32_t pll_ramp_main_hz = 0; + uint32_t pll_ramp_periph_hz = 0; + + /* gate off all mainpll clock excpet HW managed clock */ + writel(ARRIA10_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | + ARRIA10_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, + &arria10_clkmgr_base->main_pll_enr); + + /* now we can gate off the rest of the peripheral clocks */ + writel(0, &arria10_clkmgr_base->per_pll_en); + + /* Put all plls in external bypass */ + writel(ARRIA10_CLKMGR_MAINPLL_BYPASS_RESET, + &arria10_clkmgr_base->main_pll_bypasss); + writel(ARRIA10_CLKMGR_PERPLL_BYPASS_RESET, + &arria10_clkmgr_base->per_pll_bypasss); + + /* + * Put all plls VCO registers back to reset value. + * Some code might have messed with them. At same time set the + * desired clock source + */ + writel(ARRIA10_CLKMGR_MAINPLL_VCO0_RESET | + ARRIA10_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK | + (main_cfg->vco0_psrc << ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_LSB), + &arria10_clkmgr_base->main_pll_vco0); + + writel(ARRIA10_CLKMGR_PERPLL_VCO0_RESET | + ARRIA10_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK | + (per_cfg->vco0_psrc << ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_LSB), + &arria10_clkmgr_base->per_pll_vco0); + + writel(ARRIA10_CLKMGR_MAINPLL_VCO1_RESET, + &arria10_clkmgr_base->main_pll_vco1); + writel(ARRIA10_CLKMGR_PERPLL_VCO1_RESET, + &arria10_clkmgr_base->per_pll_vco1); + + /* clear the interrupt register status register */ + writel(ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | + ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | + ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | + ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | + ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | + ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK | + ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK | + ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK, + &arria10_clkmgr_base->intr); + + /* Program VCO “Numerator” and “Denominator” for main PLL */ + if (arria10_cm_is_pll_ramp_required(0, main_cfg, per_cfg)) { + /* set main PLL to safe starting threshold frequency */ + if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) + pll_ramp_main_hz = ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; + else if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) + pll_ramp_main_hz = ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; + + writel((main_cfg->vco1_denom << ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) | + arria10_cm_calc_safe_pll_numer(0, main_cfg, per_cfg, + pll_ramp_main_hz), + &arria10_clkmgr_base->main_pll_vco1); + } else { + writel((main_cfg->vco1_denom << ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) | + main_cfg->vco1_numer, + &arria10_clkmgr_base->main_pll_vco1); + } + + /* Program VCO “Numerator” and “Denominator” for periph PLL */ + if (arria10_cm_is_pll_ramp_required(1, main_cfg, per_cfg)) { + /* set periph PLL to safe starting threshold frequency */ + if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI) + pll_ramp_periph_hz = ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; + else if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI) + pll_ramp_periph_hz = ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; + + writel((per_cfg->vco1_denom << ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) | + arria10_cm_calc_safe_pll_numer(1, main_cfg, per_cfg, + pll_ramp_periph_hz), + &arria10_clkmgr_base->per_pll_vco1); + } else { + writel((per_cfg->vco1_denom << ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) | + per_cfg->vco1_numer, &arria10_clkmgr_base->per_pll_vco1); + } + + /* Wait for at least 5 us */ + __udelay(5); + + /* Now deassert BGPWRDN and PWRDN */ + clrbits_le32(&arria10_clkmgr_base->main_pll_vco0, + ARRIA10_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK | + ARRIA10_CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK); + clrbits_le32(&arria10_clkmgr_base->per_pll_vco0, + ARRIA10_CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK | + ARRIA10_CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK); + + /* Wait for at least 7 us */ + __udelay(7); + + /* enable the VCO and disable the external regulator to PLL */ + writel((readl(&arria10_clkmgr_base->main_pll_vco0) & + ~ARRIA10_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) | + ARRIA10_CLKMGR_MAINPLL_VCO0_EN_SET_MSK, + &arria10_clkmgr_base->main_pll_vco0); + writel((readl(&arria10_clkmgr_base->per_pll_vco0) & + ~ARRIA10_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) | + ARRIA10_CLKMGR_PERPLL_VCO0_EN_SET_MSK, + &arria10_clkmgr_base->per_pll_vco0); + + /* setup all the main PLL counter and clock source */ + writel(main_cfg->nocclk, + ARRIA10_CLKMGR_ADDR + ARRIA10_CLKMGR_MAINPLL_NOC_CLK_OFFSET); + writel(main_cfg->mpuclk, + ARRIA10_CLKMGR_ADDR + ARRIA10_CLKMGR_ALTERAGRP_MPU_CLK_OFFSET); + + /* main_emaca_clk divider */ + writel(main_cfg->cntr2clk_cnt, &arria10_clkmgr_base->main_pll_cntr2clk); + /* main_emacb_clk divider */ + writel(main_cfg->cntr3clk_cnt, &arria10_clkmgr_base->main_pll_cntr3clk); + /* main_emac_ptp_clk divider */ + writel(main_cfg->cntr4clk_cnt, &arria10_clkmgr_base->main_pll_cntr4clk); + /* main_gpio_db_clk divider */ + writel(main_cfg->cntr5clk_cnt, &arria10_clkmgr_base->main_pll_cntr5clk); + /* main_sdmmc_clk divider */ + writel(main_cfg->cntr6clk_cnt, &arria10_clkmgr_base->main_pll_cntr6clk); + /* main_s2f_user0_clk divider */ + writel(main_cfg->cntr7clk_cnt | + (main_cfg->cntr7clk_src << ARRIA10_CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB), + &arria10_clkmgr_base->main_pll_cntr7clk); + /* main_s2f_user1_clk divider */ + writel(main_cfg->cntr8clk_cnt, &arria10_clkmgr_base->main_pll_cntr8clk); + /* main_hmc_pll_clk divider */ + writel(main_cfg->cntr9clk_cnt | + (main_cfg->cntr9clk_src << ARRIA10_CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB), + &arria10_clkmgr_base->main_pll_cntr9clk); + /* main_periph_ref_clk divider */ + writel(main_cfg->cntr15clk_cnt, &arria10_clkmgr_base->main_pll_cntr15clk); + + /* setup all the peripheral PLL counter and clock source */ + /* peri_emaca_clk divider */ + writel(per_cfg->cntr2clk_cnt | + (per_cfg->cntr2clk_src << ARRIA10_CLKMGR_PERPLL_CNTR2CLK_SRC_LSB), + &arria10_clkmgr_base->per_pll_cntr2clk); + /* peri_emacb_clk divider */ + writel(per_cfg->cntr3clk_cnt | + (per_cfg->cntr3clk_src << ARRIA10_CLKMGR_PERPLL_CNTR3CLK_SRC_LSB), + &arria10_clkmgr_base->per_pll_cntr3clk); + /* peri_emac_ptp_clk divider */ + writel(per_cfg->cntr4clk_cnt | + (per_cfg->cntr4clk_src << ARRIA10_CLKMGR_PERPLL_CNTR4CLK_SRC_LSB), + &arria10_clkmgr_base->per_pll_cntr4clk); + /* peri_gpio_db_clk divider */ + writel(per_cfg->cntr5clk_cnt | + (per_cfg->cntr5clk_src << ARRIA10_CLKMGR_PERPLL_CNTR5CLK_SRC_LSB), + &arria10_clkmgr_base->per_pll_cntr5clk); + /* peri_sdmmc_clk divider */ + writel(per_cfg->cntr6clk_cnt | + (per_cfg->cntr6clk_src << ARRIA10_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB), + &arria10_clkmgr_base->per_pll_cntr6clk); + /* peri_s2f_user0_clk divider */ + writel(per_cfg->cntr7clk_cnt, &arria10_clkmgr_base->per_pll_cntr7clk); + /* peri_s2f_user1_clk divider */ + writel(per_cfg->cntr8clk_cnt | + (per_cfg->cntr8clk_src << ARRIA10_CLKMGR_PERPLL_CNTR8CLK_SRC_LSB), + &arria10_clkmgr_base->per_pll_cntr8clk); + /* peri_hmc_pll_clk divider */ + writel(per_cfg->cntr9clk_cnt, &arria10_clkmgr_base->per_pll_cntr9clk); + + /* setup all the external PLL counter */ + /* mpu wrapper / external divider */ + writel(main_cfg->mpuclk_cnt | + (main_cfg->mpuclk_src << ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_LSB), + &arria10_clkmgr_base->main_pll_mpuclk); + /* NOC wrapper / external divider */ + writel(main_cfg->nocclk_cnt | + (main_cfg->nocclk_src << ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_LSB), + &arria10_clkmgr_base->main_pll_nocclk); + /* NOC subclock divider such as l4 */ + writel(main_cfg->nocdiv_l4mainclk | + (main_cfg->nocdiv_l4mpclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) | + (main_cfg->nocdiv_l4spclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) | + (main_cfg->nocdiv_csatclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) | + (main_cfg->nocdiv_cstraceclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) | + (main_cfg->nocdiv_cspdbgclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB), + &arria10_clkmgr_base->main_pll_nocdiv); + /* gpio_db external divider */ + writel(per_cfg->gpiodiv_gpiodbclk, &arria10_clkmgr_base->per_pll_gpiodiv); + + /* setup the EMAC clock mux select */ + writel((per_cfg->emacctl_emac0sel < ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) | + (per_cfg->emacctl_emac1sel << ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) | + (per_cfg->emacctl_emac2sel << ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB), + &arria10_clkmgr_base->per_pll_emacctl); + + /* at this stage, check for PLL lock status */ + arria10_cm_wait_for_lock(LOCKED_MASK); + + /* + * after locking, but before taking out of bypass, + * assert/deassert outresetall + */ + + /* assert mainpll outresetall */ + setbits_le32(&arria10_clkmgr_base->main_pll_vco0, + ARRIA10_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); + /* assert perpll outresetall */ + setbits_le32(&arria10_clkmgr_base->per_pll_vco0, + ARRIA10_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); + /* de-assert mainpll outresetall */ + clrbits_le32(&arria10_clkmgr_base->main_pll_vco0, + ARRIA10_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); + /* de-assert perpll outresetall */ + clrbits_le32(&arria10_clkmgr_base->per_pll_vco0, + ARRIA10_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); + + /* + * Take all PLLs out of bypass when boot mode is cleared. + * release mainpll from bypass + */ + writel(ARRIA10_CLKMGR_MAINPLL_BYPASS_RESET, + &arria10_clkmgr_base->main_pll_bypassr); + /* wait till Clock Manager is not busy */ + arria10_cm_wait4fsm(); + + /* release perpll from bypass */ + writel(ARRIA10_CLKMGR_PERPLL_BYPASS_RESET, + &arria10_clkmgr_base->per_pll_bypassr); + /* wait till Clock Manager is not busy */ + arria10_cm_wait4fsm(); + + /* clear boot mode */ + clrbits_le32(&arria10_clkmgr_base->ctrl, + ARRIA10_CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK); + /* wait till Clock Manager is not busy */ + arria10_cm_wait4fsm(); + + /* At here, we need to ramp to final value if needed */ + if (pll_ramp_main_hz != 0) + arria10_cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz); + if (pll_ramp_periph_hz != 0) + arria10_cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz); + + /* Now ungate non-hw-managed clocks */ + writel(ARRIA10_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | + ARRIA10_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, + &arria10_clkmgr_base->main_pll_ens); + writel(ARRIA10_CLKMGR_PERPLL_EN_RESET, + &arria10_clkmgr_base->per_pll_ens); + + /* + * Clear the loss lock and slip bits as they might set during + * clock reconfiguration + */ + writel(ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | + ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | + ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | + ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | + ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | + ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK, + &arria10_clkmgr_base->intr); + + return 0; +} + +int arria10_cm_basic_init(struct arria10_mainpll_cfg *mainpll, + struct arria10_perpll_cfg *perpll) +{ + return arria10_cm_full_cfg(mainpll, perpll); +} + +void arria10_cm_use_intosc(void) +{ + setbits_le32(&arria10_clkmgr_base->ctrl, + ARRIA10_CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK); +} diff --git a/arch/arm/mach-socfpga/arria10-generic.c b/arch/arm/mach-socfpga/arria10-generic.c new file mode 100644 index 0000000000..b8129eaf23 --- /dev/null +++ b/arch/arm/mach-socfpga/arria10-generic.c @@ -0,0 +1,85 @@ +#include <common.h> +#include <io.h> +#include <init.h> +#include <restart.h> +#include <mach/generic.h> +#include <mach/arria10-reset-manager.h> +#include <mach/arria10-system-manager.h> +#include <mach/arria10-regs.h> + +/* Some initialization for the EMAC */ +static void arria10_init_emac(void) +{ + uint32_t rst, val; + + /* No need for this without network support, e.g. xloader build */ + if (!IS_ENABLED(CONFIG_NET)) + return; + + rst = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST); + rst |= ARRIA10_RSTMGR_PER0MODRST_EMAC0 | + ARRIA10_RSTMGR_PER0MODRST_EMAC1 | + ARRIA10_RSTMGR_PER0MODRST_EMAC2; + + writel(rst, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST); + val = readl(ARRIA10_SYSMGR_EMAC0); + val &= ~(ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK); + val |= ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + writel(val, ARRIA10_SYSMGR_EMAC0); + + val = readl(ARRIA10_SYSMGR_EMAC1); + val &= ~(ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK); + val |= ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + writel(val, ARRIA10_SYSMGR_EMAC1); + + val = readl(ARRIA10_SYSMGR_EMAC2); + val &= ~(ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK); + val |= ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + writel(val, ARRIA10_SYSMGR_EMAC2); + + val = readl(ARRIA10_SYSMGR_FPGAINTF_EN_3); + val &= ~(ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0 | + ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0_SW | + ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1 | + ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1_SW | + ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2 | + ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2_SW); + + rst = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST); + rst &= ~(ARRIA10_RSTMGR_PER0MODRST_EMAC0 | + ARRIA10_RSTMGR_PER0MODRST_EMAC1 | + ARRIA10_RSTMGR_PER0MODRST_EMAC2); + writel(rst, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST); +} + +/* Write the reset manager register to cause reset */ +static void __noreturn arria10_restart_soc(struct restart_handler *rst) +{ + /* request a warm reset */ + writel(ARRIA10_RSTMGR_CTL_SWWARMRSTREQ, + ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_CTRL); + /* + * infinite loop here as watchdog will trigger and reset + * the processor + */ + hang(); +} + +static int arria10_generic_init(void) +{ + barebox_set_model("SoCFPGA Arria10"); + + pr_debug("Setting SDMMC phase shifts for Arria10\n"); + writel(ARRIA10_SYSMGR_SDMMC_DRVSEL(3) | + ARRIA10_SYSMGR_SDMMC_SMPLSEL(0), + ARRIA10_SYSMGR_SDMMC); + + pr_debug("Initialize EMACs\n"); + arria10_init_emac(); + + pr_debug("Register restart handler\n"); + restart_handler_register_fn(arria10_restart_soc); + + return 0; +} +postcore_initcall(arria10_generic_init); diff --git a/arch/arm/mach-socfpga/arria10-init.c b/arch/arm/mach-socfpga/arria10-init.c new file mode 100644 index 0000000000..07256da1db --- /dev/null +++ b/arch/arm/mach-socfpga/arria10-init.c @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <debug_ll.h> +#include <mach/arria10-regs.h> +#include <mach/arria10-clock-manager.h> +#include <mach/arria10-pinmux.h> +#include <mach/arria10-reset-manager.h> +#include <mach/arria10-system-manager.h> +#include <mach/generic.h> +#include <asm/io.h> +#include <asm/cache-l2x0.h> +#include <asm/system.h> + +#define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */ +#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26) +#define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */ + +static inline void set_auxcr(unsigned int val) +{ + asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR" + : : "r" (val)); + isb(); +} + +static inline unsigned int get_auxcr(void) +{ + unsigned int val; + + asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val)); + return val; +} + +static void l2c310_disable(void __iomem *base) +{ + u32 aux; + int ways = 8; + + aux = readl(base + L2X0_AUX_CTRL); + + /* + * If full-line-of-zeros is enabled, we must first disable it in the + * Cortex-A9 auxiliary control register before disabling the L2 cache. + */ + if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) + set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1))); + + /* flush all ways */ + writel((1 << ways) - 1, base + L2X0_INV_WAY); + + while (readl(base + L2X0_INV_WAY) & ways) + ; + + /* sync */ + writel(0, base + L2X0_CACHE_SYNC); + + /* disable */ + writel(0, base + L2X0_CTRL); + dsb(); +} + +static void arria10_initialize_security_policies(void) +{ + void __iomem *l2x0_base = (void __iomem *) 0xfffff000; + + /* BootROM leaves the L2X0 in a weird state. Always disable L2X0 for now. */ + l2c310_disable(l2x0_base); + + /* Put OCRAM in non-secure */ + writel(0x003f0000, ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION0); + writel(0x1, ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN); + + /* Put DDR in non-secure */ + writel(0xffff0000, ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION0); + writel(0x1, ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN); + + /* Enable priviledge and non priviledge access to L4 peripherals */ + writel(0xffffffff, ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV); + + /* Enable secure and non secure transaction to bridges */ + writel(0xffffffff, ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_LWSOC2FPGA); + writel(0xffffffff, ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_SOC2FPGA); + + /* allow non-secure and secure transaction from/to all peripherals */ + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_NAND_REG); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_NAND_DATA); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_QSPI_DATA); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_USB0_REG); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_USB1_REG); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPIM0); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPIM1); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPIS0); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPIS1); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_EMAC0); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_EMAC1); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_EMAC2); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_EMAC3); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_QSPI); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SDMMC); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_GPIO0); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_GPIO1); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_GPIO2); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C0); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C1); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C2); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C3); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C4); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER0); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER1); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_UART0); + writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_UART1); + + /* Return error instead of random data */ + writel(0x1, ARRIA10_NOC_FW_DDR_L3_DDR_SCR_GLOBAL); +} + +static void arria10_mask_ecc_errors(void) +{ + writel(0x0007FFFF, ARRIA10_SYSMGR_ADDR + 0x94); +} + +/* + * First C function to initialize the critical hardware early + */ +void arria10_init(struct arria10_mainpll_cfg *mainpll, + struct arria10_perpll_cfg *perpll, + uint32_t *pinmux) +{ + int i; + + arria10_cm_use_intosc(); + + arria10_initialize_security_policies(); + + arria10_mask_ecc_errors(); + + /* + * Configure the L2 controller to make SDRAM start at 0. + * Set address filtering start to 0x0 (Bits [31:20]), + * Enable address filtering (Bit[0]) + */ + writel(0x00000001, ARRIA10_MPUL2_ADRFLTR_START); + writel(0x00000002, ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE); + + arria10_reset_peripherals(); + + /* timer init */ + writel(0xffffffff, ARRIA10_OSC1TIMER0_ADDR); + writel(0xffffffff, ARRIA10_OSC1TIMER0_ADDR + 0x4); + writel(0x00000003, ARRIA10_OSC1TIMER0_ADDR + 0x8); + + /* configuring the clock based on handoff */ + arria10_cm_basic_init(mainpll, perpll); + + /* dedicated pins */ + for (i = arria10_pinmux_dedicated_io_4; + i <= arria10_pinmux_dedicated_io_17; i++) + writel(pinmux[i], ARRIA10_PINMUX_DEDICATED_IO_4_ADDR + + (i - arria10_pinmux_dedicated_io_4) * sizeof(uint32_t)); + + for (i = arria10_pincfg_dedicated_io_bank; + i <= arria10_pincfg_dedicated_io_17; i++) + writel(pinmux[i], ARRIA10_PINCFG_DEDICATED_IO_BANK_ADDR + + (i - arria10_pincfg_dedicated_io_bank) * sizeof(uint32_t)); + + /* deassert peripheral resets */ + arria10_reset_deassert_dedicated_peripherals(); + + /* wait for fpga_usermode */ + while ((readl(0xffd03080) & 0x6) == 0); + + /* shared pins */ + for (i = arria10_pinmux_shared_io_q1_1; + i <= arria10_pinmux_shared_io_q4_12; i++) + writel(pinmux[i], ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + + (i - arria10_pinmux_shared_io_q1_1) * sizeof(uint32_t)); + + arria10_reset_deassert_shared_peripherals(); + + /* usefpga: select source for signals: hps or fpga */ + for (i = arria10_pinmux_rgmii0_usefpga; + i < arria10_pinmux_max; i++) + writel(pinmux[i], ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + + (i - arria10_pinmux_rgmii0_usefpga) * sizeof(uint32_t)); + + arria10_reset_deassert_fpga_peripherals(); + + INIT_LL(); +} diff --git a/arch/arm/mach-socfpga/arria10-reset-manager.c b/arch/arm/mach-socfpga/arria10-reset-manager.c new file mode 100644 index 0000000000..a7e4bd603e --- /dev/null +++ b/arch/arm/mach-socfpga/arria10-reset-manager.c @@ -0,0 +1,398 @@ +/* + * Copyright (C) 2014-2016 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <errno.h> +#include <io.h> +#include <mach/arria10-pinmux.h> +#include <mach/arria10-regs.h> +#include <mach/arria10-reset-manager.h> +#include <mach/arria10-system-manager.h> + +void arria10_reset_peripherals(void) +{ + unsigned mask_ecc_ocp = ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP | + ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP | + ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP | + ARRIA10_RSTMGR_PER0MODRST_USB0OCP | + ARRIA10_RSTMGR_PER0MODRST_USB1OCP | + ARRIA10_RSTMGR_PER0MODRST_NANDOCP | + ARRIA10_RSTMGR_PER0MODRST_QSPIOCP | + ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP; + + /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */ + writel(0xffffffff, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST); + setbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, + ~mask_ecc_ocp); + + /* Finally disable the ECC_OCP */ + setbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, + mask_ecc_ocp); +} + +void arria10_reset_deassert_dedicated_peripherals(void) +{ + uint32_t mask; + + mask = ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP | + ARRIA10_RSTMGR_PER0MODRST_QSPIOCP | + ARRIA10_RSTMGR_PER0MODRST_NANDOCP | + ARRIA10_RSTMGR_PER0MODRST_DMAOCP; + + /* enable ECC OCP first */ + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask); + + mask = ARRIA10_RSTMGR_PER0MODRST_SDMMC | + ARRIA10_RSTMGR_PER0MODRST_QSPI | + ARRIA10_RSTMGR_PER0MODRST_NAND | + ARRIA10_RSTMGR_PER0MODRST_DMA; + + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask); + + mask = ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER0 | + ARRIA10_RSTMGR_PER1MODRST_UART1 | + ARRIA10_RSTMGR_PER1MODRST_UART0; + + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask); + + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, + ARRIA10_RSTMGR_OCP_MASK); + mask = ARRIA10_RSTMGR_PER0MODRST_EMAC1 | + ARRIA10_RSTMGR_PER0MODRST_EMAC2 | + ARRIA10_RSTMGR_PER0MODRST_EMAC0 | + ARRIA10_RSTMGR_PER0MODRST_SPIS0 | + ARRIA10_RSTMGR_PER0MODRST_SPIM0; + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask); + + mask = ARRIA10_RSTMGR_PER1MODRST_I2C3 | + ARRIA10_RSTMGR_PER1MODRST_I2C4 | + ARRIA10_RSTMGR_PER1MODRST_I2C2 | + ARRIA10_RSTMGR_PER1MODRST_UART1 | + ARRIA10_RSTMGR_PER1MODRST_GPIO2; + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask); +} + +static const uint32_t per0fpgamasks[] = { + ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP | ARRIA10_RSTMGR_PER0MODRST_EMAC0, + ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP | ARRIA10_RSTMGR_PER0MODRST_EMAC1, + ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP | ARRIA10_RSTMGR_PER0MODRST_EMAC2, + 0, /* i2c0 per0mod */ + 0, /* i2c1 per0mod */ + 0, /* i2c0_emac */ + 0, /* i2c1_emac */ + 0, /* i2c2_emac */ + ARRIA10_RSTMGR_PER0MODRST_NANDOCP | ARRIA10_RSTMGR_PER0MODRST_NAND, + ARRIA10_RSTMGR_PER0MODRST_QSPIOCP | ARRIA10_RSTMGR_PER0MODRST_QSPI, + ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP | ARRIA10_RSTMGR_PER0MODRST_SDMMC, + ARRIA10_RSTMGR_PER0MODRST_SPIM0, + ARRIA10_RSTMGR_PER0MODRST_SPIM1, + ARRIA10_RSTMGR_PER0MODRST_SPIS0, + ARRIA10_RSTMGR_PER0MODRST_SPIS1, + 0, /* uart0 per0mod */ + 0, /* uart1 per0mod */ +}; + +static const uint32_t per1fpgamasks[] = { + 0, /* emac0 per0mod */ + 0, /* emac1 per0mod */ + 0, /* emac2 per0mod */ + ARRIA10_RSTMGR_PER1MODRST_I2C0, + ARRIA10_RSTMGR_PER1MODRST_I2C1, + ARRIA10_RSTMGR_PER1MODRST_I2C2, + ARRIA10_RSTMGR_PER1MODRST_I2C3, + ARRIA10_RSTMGR_PER1MODRST_I2C4, + 0, /* nand per0mod */ + 0, /* qspi per0mod */ + 0, /* sdmmc per0mod */ + 0, /* spim0 per0mod */ + 0, /* spim1 per0mod */ + 0, /* spis0 per0mod */ + 0, /* spis1 per0mod */ + ARRIA10_RSTMGR_PER1MODRST_UART0, + ARRIA10_RSTMGR_PER1MODRST_UART1, +}; + +void arria10_reset_deassert_fpga_peripherals(void) +{ + uint32_t mask0 = 0; + uint32_t mask1 = 0; + uint32_t fpga_pinux_addr = ARRIA10_PINMUX_FPGA_INTERFACE_ADDR; + int i; + + for (i = 0; i < ARRAY_SIZE(per1fpgamasks); i++) { + if (readl(fpga_pinux_addr)) { + mask0 |= per0fpgamasks[i]; + mask1 |= per1fpgamasks[i]; + } + fpga_pinux_addr += sizeof(uint32_t); + } + + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, + mask0 & ARRIA10_RSTMGR_OCP_MASK); + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask0); + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask1); +} + +void arria10_reset_deassert_shared_peripherals_q1(uint32_t *mask0, + uint32_t *mask1) +{ + uint32_t pinmux_addr = ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR; + int q1; + + for (q1 = 1; q1 <= 12; q1++, pinmux_addr += sizeof(uint32_t)) { + switch (readl(pinmux_addr)) { + case ARRIA10_PINMUX_SHARED_IO_Q1_GPIO: + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_GPIO0; + break; + case ARRIA10_PINMUX_SHARED_IO_Q1_NAND: + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_NANDOCP| + ARRIA10_RSTMGR_PER0MODRST_NAND; + break; + case ARRIA10_PINMUX_SHARED_IO_Q1_UART: + if ((q1 >= 1) && (q1 <= 4)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART0; + else if ((q1 >= 5) && (q1 <= 8)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART1; + break; + case ARRIA10_PINMUX_SHARED_IO_Q1_QSPI: + if ((q1 >= 5) && (q1 <= 6)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_QSPIOCP | + ARRIA10_RSTMGR_PER0MODRST_QSPI; + break; + case ARRIA10_PINMUX_SHARED_IO_Q1_USB: + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_USB0OCP | + ARRIA10_RSTMGR_PER0MODRST_USB0; + break; + case ARRIA10_PINMUX_SHARED_IO_Q1_SDMMC: + if ((q1 >= 1) && (q1 <= 10)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP | + ARRIA10_RSTMGR_PER0MODRST_SDMMC; + break; + case ARRIA10_PINMUX_SHARED_IO_Q1_SPIM: + if ((q1 == 1) || ((q1 >= 5) && (q1 <= 8))) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM0; + else if ((q1 == 2) || ((q1 >= 9) && (q1 <= 12))) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM1; + break; + case ARRIA10_PINMUX_SHARED_IO_Q1_SPIS: + if ((q1 >= 1) && (q1 <= 4)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS0; + else if ((q1 >= 9) && (q1 <= 12)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS1; + break; + case ARRIA10_PINMUX_SHARED_IO_Q1_EMAC: + if ((q1 == 7) || (q1 == 8)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP | + ARRIA10_RSTMGR_PER0MODRST_EMAC2; + else if ((q1 == 9) || (q1 == 10)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP | + ARRIA10_RSTMGR_PER0MODRST_EMAC1; + else if ((q1 == 11) || (1 == 12)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP | + ARRIA10_RSTMGR_PER0MODRST_EMAC0; + break; + case ARRIA10_PINMUX_SHARED_IO_Q1_I2C: + if ((q1 == 3) || (q1 == 4)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C1; + else if ((q1 == 5) || (q1 == 6)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C0; + else if ((q1 == 7) || (q1 == 8)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C4; + else if ((q1 == 9) || (q1 == 10)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C3; + else if ((q1 == 11) || (q1 == 12)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C2; + break; + } + } +} + +void arria10_reset_deassert_shared_peripherals_q2(uint32_t *mask0, + uint32_t *mask1) +{ + uint32_t pinmux_addr = ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR; + int q2; + + for (q2 = 1; q2 <= 12; q2++, pinmux_addr += sizeof(uint32_t)) { + switch (readl(pinmux_addr)) { + case ARRIA10_PINMUX_SHARED_IO_Q2_GPIO: + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_GPIO0; + break; + case ARRIA10_PINMUX_SHARED_IO_Q2_NAND: + if ((q2 != 4) && (q2 != 5)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_NANDOCP | + ARRIA10_RSTMGR_PER0MODRST_NAND; + break; + case ARRIA10_PINMUX_SHARED_IO_Q2_UART: + if ((q2 >= 9) && (q2 <= 12)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART0; + break; + case ARRIA10_PINMUX_SHARED_IO_Q2_USB: + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_USB1OCP | + ARRIA10_RSTMGR_PER0MODRST_USB1; + break; + case ARRIA10_PINMUX_SHARED_IO_Q2_EMAC: + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP | + ARRIA10_RSTMGR_PER0MODRST_EMAC0; + break; + case ARRIA10_PINMUX_SHARED_IO_Q2_SPIM: + if ((q2 >= 8) && (q2 <= 12)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM1; + break; + case ARRIA10_PINMUX_SHARED_IO_Q2_SPIS: + if ((q2 >= 9) && (q2 <= 12)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS0; + break; + case ARRIA10_PINMUX_SHARED_IO_Q2_I2C: + if ((q2 == 9) || (q2 == 10)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C1; + else if ((q2 == 11) || (q2 == 12)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C0; + break; + } + } +} + +void arria10_reset_deassert_shared_peripherals_q3(uint32_t *mask0, + uint32_t *mask1) +{ + uint32_t pinmux_addr = ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR; + int q3; + + for (q3 = 1; q3 <= 12; q3++, pinmux_addr += sizeof(uint32_t)) { + switch (readl(pinmux_addr)) { + case ARRIA10_PINMUX_SHARED_IO_Q3_GPIO: + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_GPIO1; + break; + case ARRIA10_PINMUX_SHARED_IO_Q3_NAND: + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_NANDOCP | + ARRIA10_RSTMGR_PER0MODRST_NAND; + break; + case ARRIA10_PINMUX_SHARED_IO_Q3_UART: + if ((q3 >= 1) && (q3 <= 4)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART0; + else if ((q3 >= 5) && (q3 <= 8)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART1; + break; + case ARRIA10_PINMUX_SHARED_IO_Q3_EMAC1: + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP | + ARRIA10_RSTMGR_PER0MODRST_EMAC1; + break; + case ARRIA10_PINMUX_SHARED_IO_Q3_SPIM: + if ((q3 >= 1) && (q3 <= 5)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM1; + break; + case ARRIA10_PINMUX_SHARED_IO_Q3_SPIS: + if ((q3 >= 5) && (q3 <= 8)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS1; + else if ((q3 >= 9) && (q3 <= 12)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS0; + break; + case ARRIA10_PINMUX_SHARED_IO_Q3_EMAC0: + if ((q3 == 9) || (q3 == 10)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP | + ARRIA10_RSTMGR_PER0MODRST_EMAC2; + else if ((q3 == 11) || (q3 == 12)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP | + ARRIA10_RSTMGR_PER0MODRST_EMAC0; + break; + case ARRIA10_PINMUX_SHARED_IO_Q3_I2C: + if ((q3 == 7) || (q3 == 8)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C1; + else if ((q3 == 3) || (q3 == 4)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C0; + else if ((q3 == 9) || (q3 == 10)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C4; + else if ((q3 == 11) || (q3 == 12)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C2; + break; + } + } +} + +void arria10_reset_deassert_shared_peripherals_q4(uint32_t *mask0, uint32_t *mask1) +{ + uint32_t pinmux_addr = ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR; + int q4; + + for (q4 = 1; q4 <= 12; q4++, pinmux_addr += sizeof(uint32_t)) { + switch (readl(pinmux_addr)) { + case ARRIA10_PINMUX_SHARED_IO_Q4_GPIO: + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_GPIO1; + break; + case ARRIA10_PINMUX_SHARED_IO_Q4_NAND: + if (q4 != 4) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_NANDOCP | + ARRIA10_RSTMGR_PER0MODRST_NAND; + break; + case ARRIA10_PINMUX_SHARED_IO_Q4_UART: + if ((q4 >= 3) && (q4 <= 6)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART1; + break; + case ARRIA10_PINMUX_SHARED_IO_Q4_QSPI: + if ((q4 == 5) || (q4 == 6)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_QSPIOCP | + ARRIA10_RSTMGR_PER0MODRST_QSPI; + break; + case ARRIA10_PINMUX_SHARED_IO_Q4_EMAC1: + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP | + ARRIA10_RSTMGR_PER0MODRST_EMAC2; + break; + case ARRIA10_PINMUX_SHARED_IO_Q4_SDMMC: + if ((q4 >= 1) && (q4 <= 6)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP | + ARRIA10_RSTMGR_PER0MODRST_SDMMC; + break; + case ARRIA10_PINMUX_SHARED_IO_Q4_SPIM: + if ((q4 >= 6) && (q4 <= 12)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM0; + break; + case ARRIA10_PINMUX_SHARED_IO_Q4_SPIS: + if ((q4 >= 9) && (q4 <= 12)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS1; + break; + case ARRIA10_PINMUX_SHARED_IO_Q4_EMAC0: + if ((q4 == 7) || (q4 == 8)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP | + ARRIA10_RSTMGR_PER0MODRST_EMAC1; + else if ((q4 == 11) || (q4 == 12)) + *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP | + ARRIA10_RSTMGR_PER0MODRST_EMAC0; + break; + case ARRIA10_PINMUX_SHARED_IO_Q4_I2C: + if ((q4 == 1) || (q4 == 2)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C1; + else if ((q4 == 7) || (q4 == 8)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C3; + else if ((q4 == 9) || (q4 == 10)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C4; + else if ((q4 == 11) || (q4 == 12)) + *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C2; + break; + } + } +} + +void arria10_reset_deassert_shared_peripherals(void) +{ + uint32_t mask0 = 0; + uint32_t mask1 = 0; + + arria10_reset_deassert_shared_peripherals_q1(&mask0, &mask1); + arria10_reset_deassert_shared_peripherals_q2(&mask0, &mask1); + arria10_reset_deassert_shared_peripherals_q3(&mask0, &mask1); + arria10_reset_deassert_shared_peripherals_q4(&mask0, &mask1); + + mask1 |= ARRIA10_RSTMGR_PER1MODRST_WATCHDOG1 | + ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER1 | + ARRIA10_RSTMGR_PER1MODRST_SPTIMER0 | + ARRIA10_RSTMGR_PER1MODRST_SPTIMER1; + + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, + mask0 & ARRIA10_RSTMGR_OCP_MASK); + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask1); + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask0); +} diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c new file mode 100644 index 0000000000..08de0e32cd --- /dev/null +++ b/arch/arm/mach-socfpga/arria10-sdram.c @@ -0,0 +1,535 @@ +/* + * Copyright (C) 2014-2016 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <io.h> +#include <debug_ll.h> +#include <mach/generic.h> +#include <mach/arria10-sdram.h> +#include <mach/arria10-regs.h> +#include <mach/arria10-reset-manager.h> + + +/* FAWBANK - Number of Bank of a given device involved in the FAW period. */ +#define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1) + +#define ARRIA10_EMIF_RST BIT(31) +#define ARRIA10_OCT_CAL_REQ BIT(30) +#define ARRIA10_OCT_CAL_ACK 31 + +#define ARRIA10_NIOS_OCT_DONE BIT(7) +#define ARRIA10_NIOS_OCT_ACK 7 + +/* Engineering sample silicon */ +#define ARRIA10_ES_SILICON_VER 0x00010001 + +#define DDR_REG_SEQ2CORE 0xFFD0507C +#define DDR_REG_CORE2SEQ 0xFFD05078 +#define DDR_REG_GPOUT 0xFFD03010 +#define DDR_REG_GPIN 0xFFD03014 +#define DDR_MAX_TRIES 0x00100000 +#define IO48_MMR_DRAMSTS 0xFFCFA0EC +#define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110 +#define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114 +#define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118 + +#define SEQ2CORE_MASK 0xF +#define CORE2SEQ_INT_REQ 0xF +#define SEQ2CORE_INT_RESP_BIT 3 + +#define DDR_ECC_DMA_SIZE 1500 +#define DDR_READ_LATENCY_DELAY 40 + +#define ARRIA_DDR_CONFIG(A, B, C, R) ((A<<24)|(B<<16)|(C<<8)|R) +/* The followring are the supported configurations */ +uint32_t ddr_config[] = { + /* Chip - Row - Bank - Column Style */ + /* All Types */ + ARRIA_DDR_CONFIG(0, 3, 10, 12), + ARRIA_DDR_CONFIG(0, 3, 10, 13), + ARRIA_DDR_CONFIG(0, 3, 10, 14), + ARRIA_DDR_CONFIG(0, 3, 10, 15), + ARRIA_DDR_CONFIG(0, 3, 10, 16), + ARRIA_DDR_CONFIG(0, 3, 10, 17), + /* LPDDR x16 */ + ARRIA_DDR_CONFIG(0, 3, 11, 14), + ARRIA_DDR_CONFIG(0, 3, 11, 15), + ARRIA_DDR_CONFIG(0, 3, 11, 16), + ARRIA_DDR_CONFIG(0, 3, 12, 15), + /* DDR4 Only */ + ARRIA_DDR_CONFIG(0, 4, 10, 14), + ARRIA_DDR_CONFIG(0, 4, 10, 15), + ARRIA_DDR_CONFIG(0, 4, 10, 16), + ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */ + /* Chip - Bank - Row - Column Style */ + ARRIA_DDR_CONFIG(1, 3, 10, 12), + ARRIA_DDR_CONFIG(1, 3, 10, 13), + ARRIA_DDR_CONFIG(1, 3, 10, 14), + ARRIA_DDR_CONFIG(1, 3, 10, 15), + ARRIA_DDR_CONFIG(1, 3, 10, 16), + ARRIA_DDR_CONFIG(1, 3, 10, 17), + ARRIA_DDR_CONFIG(1, 3, 11, 14), + ARRIA_DDR_CONFIG(1, 3, 11, 15), + ARRIA_DDR_CONFIG(1, 3, 11, 16), + ARRIA_DDR_CONFIG(1, 3, 12, 15), + /* DDR4 Only */ + ARRIA_DDR_CONFIG(1, 4, 10, 14), + ARRIA_DDR_CONFIG(1, 4, 10, 15), + ARRIA_DDR_CONFIG(1, 4, 10, 16), + ARRIA_DDR_CONFIG(1, 4, 10, 17), +}; +#define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config) + +static int match_ddr_conf(uint32_t ddr_conf) +{ + int i; + + for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) { + if (ddr_conf == ddr_config[i]) + return i; + } + return 0; +} + +/* Check whether SDRAM is successfully Calibrated */ +static int is_sdram_cal_success(void) +{ + return readl(ARRIA10_ECC_HMC_OCP_DDRCALSTAT); +} + +static unsigned char ddr_get_bit(uint32_t ereg, unsigned char bit) +{ + unsigned int reg = readl(ereg); + + return (reg & (1 << bit)) ? 1 : 0; +} + +static unsigned char ddr_wait_bit(uint32_t ereg, uint32_t bit, + uint32_t expected, uint32_t timeout_usec) +{ + unsigned int tmr; + + for (tmr = 0; tmr < timeout_usec; tmr += 100) { + __udelay(100); + if (ddr_get_bit(ereg, bit) == expected) + return 0; + } + + return 1; +} + +static void ddr_delay(uint32_t delay) +{ + int tmr; + + for (tmr = 0; tmr < delay; tmr++) + __udelay(1000); +} + +/* + * Diagram of OCT Workaround: + * + * EMIF Core HPS Processor OCT FSM + * ================================================================= + * + * seq2core ==============> + * [0x?????????] OCT Request [0xFFD0507C] + * + * core2seq + * [0x?????????] <============== + * OCT Ready [0xFFD05078] + * + * [0xFFD03010] ============> Request + * OCT Request + * + * [0xFFD03014] <============ Ready + * OCT Ready + * Signal definitions: + * + * seq2core[7] - OCT calibration request (act-high) + * core2seq[7] - Signals OCT FSM is ready (active high) + * gpout[31] - EMIF Reset override (active low) + * gpout[30] - OCT calibration request (act-high) + * gpin[31] - OCT calibration ready (act-high) + */ + +static int ddr_calibration_es_workaround(void) +{ + ddr_delay(500); + /* Step 1 - Initiating Reset Sequence */ + clrbits_le32(DDR_REG_GPOUT, ARRIA10_EMIF_RST); + ddr_delay(10); + + /* Step 2 - Clearing registers to EMIF core */ + writel(0, DDR_REG_CORE2SEQ); /*Clear the HPS->NIOS COM reg.*/ + + /* Step 3 - Clearing registers to OCT core */ + clrbits_le32(DDR_REG_GPOUT, ARRIA10_OCT_CAL_REQ); + ddr_delay(5); + + /* Step 4 - Taking EMIF out of reset */ + setbits_le32(DDR_REG_GPOUT, ARRIA10_EMIF_RST); + ddr_delay(10); + + /* Step 5 - Waiting for OCT circuitry to come out of reset */ + if (ddr_wait_bit(DDR_REG_GPIN, ARRIA10_OCT_CAL_ACK, 1, 1000000)) + return -1; + + /* Step 6 - Allowing EMIF to proceed with OCT calibration */ + setbits_le32(DDR_REG_CORE2SEQ, ARRIA10_NIOS_OCT_DONE); + + /* Step 7 - Waiting for EMIF request */ + if (ddr_wait_bit(DDR_REG_SEQ2CORE, ARRIA10_NIOS_OCT_ACK, 1, 2000000)) + return -2; + + /* Step 8 - Acknowledging EMIF OCT request */ + clrbits_le32(DDR_REG_CORE2SEQ, ARRIA10_NIOS_OCT_DONE); + + /* Step 9 - Waiting for EMIF response */ + if (ddr_wait_bit(DDR_REG_SEQ2CORE, ARRIA10_NIOS_OCT_ACK, 0, 2000000)) + return -3; + + /* Step 10 - Triggering OCT Calibration */ + setbits_le32(DDR_REG_GPOUT, ARRIA10_OCT_CAL_REQ); + + /* Step 11 - Waiting for OCT response */ + if (ddr_wait_bit(DDR_REG_GPIN, ARRIA10_OCT_CAL_ACK, 0, 1000)) + return -4; + + /* Step 12 - Clearing OCT Request bit */ + clrbits_le32(DDR_REG_GPOUT, ARRIA10_OCT_CAL_REQ); + + /* Step 13 - Waiting for OCT Engine */ + if (ddr_wait_bit(DDR_REG_GPIN, ARRIA10_OCT_CAL_ACK, 1, 200000)) + return -5; + + /* Step 14 - Proceeding with EMIF calibration */ + setbits_le32(DDR_REG_CORE2SEQ, ARRIA10_NIOS_OCT_DONE); + + ddr_delay(100); + + return 0; +} + +static int emif_clear(void) +{ + uint32_t s2c; + uint32_t i = DDR_MAX_TRIES; + + writel(0, DDR_REG_CORE2SEQ); + do { + ddr_delay(50); + s2c = readl(DDR_REG_SEQ2CORE); + } while ((s2c & SEQ2CORE_MASK) && (--i > 0)); + + return !i; +} +static int emif_reset(void) +{ + uint32_t c2s, s2c; + + c2s = readl(DDR_REG_CORE2SEQ); + s2c = readl(DDR_REG_SEQ2CORE); + + pr_debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", + c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0), + readl(IO48_MMR_NIOS2_RESERVE1), + readl(IO48_MMR_NIOS2_RESERVE2), + readl(IO48_MMR_DRAMSTS)); + + if ((s2c & SEQ2CORE_MASK) && emif_clear()) { + printf("failed emif_clear()\n"); + return -1; + } + + writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ); + + if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) { + printf("emif_reset failed to see interrupt acknowledge\n"); + return -2; + } else { + printf("emif_reset interrupt acknowledged\n"); + } + + if (emif_clear()) { + printf("emif_clear() failed\n"); + return -3; + } + pr_debug("emif_reset interrupt cleared\n"); + + pr_debug("nr0=%08x nr1=%08x nr2=%08x\n", + readl(IO48_MMR_NIOS2_RESERVE0), + readl(IO48_MMR_NIOS2_RESERVE1), + readl(IO48_MMR_NIOS2_RESERVE2)); + + return 0; +} + +static int arria10_ddr_setup(void) +{ + int i, j, retcode, ddr_setup_complete = 0; + int chip_version = readl(ARRIA10_SYSMGR_SILICONID1); + + /* Try 3 times to do a calibration */ + for (i = 0; (i < 3) && !ddr_setup_complete; i++) { + /* Only engineering sample needs calibration workaround */ + if (ARRIA10_ES_SILICON_VER == chip_version) { + retcode = ddr_calibration_es_workaround(); + if (retcode) { + printf("DDRCAL: Failure: %d\n", retcode); + continue; + } + } + + /* A delay to wait for calibration bit to set */ + for (j = 0; (j < 10) && !ddr_setup_complete; j++) { + ddr_delay(500); + ddr_setup_complete = is_sdram_cal_success(); + } + + if (!ddr_setup_complete && + (ARRIA10_ES_SILICON_VER != chip_version)) { + emif_reset(); + } + } + + if (!ddr_setup_complete) { + puts_ll("Error: Could Not Calibrate SDRAM\n"); + return -1; + } + + return 0; +} + +/* Function to startup the SDRAM*/ +static int arria10_sdram_startup(void) +{ + uint32_t val; + + /* Release NOC ddr scheduler from reset */ + val = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST); + val &= ~ARRIA10_RSTMGR_BRGMODRST_DDRSCH; + writel(val, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST); + + /* Bringup the DDR (calibration and configuration) */ + return arria10_ddr_setup(); +} + +/* Function to initialize SDRAM MMR and NOC DDR scheduler*/ +static void arria10_sdram_mmr_init(void) +{ + uint32_t update_value, io48_value; + union ctrlcfg0_reg ctrlcfg0 = + (union ctrlcfg0_reg)readl(ARRIA10_IO48_HMC_MMR_CTRLCFG0); + union ctrlcfg1_reg ctrlcfg1 = + (union ctrlcfg1_reg)readl(ARRIA10_IO48_HMC_MMR_CTRLCFG1); + union dramaddrw_reg dramaddrw = + (union dramaddrw_reg)readl(ARRIA10_IO48_HMC_MMR_DRAMADDRW); + union caltiming0_reg caltim0 = + (union caltiming0_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING0); + union caltiming1_reg caltim1 = + (union caltiming1_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING1); + union caltiming2_reg caltim2 = + (union caltiming2_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING2); + union caltiming3_reg caltim3 = + (union caltiming3_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING3); + union caltiming4_reg caltim4 = + (union caltiming4_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING4); + union caltiming9_reg caltim9 = + (union caltiming9_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING9); + uint32_t ddrioctl; + + /* + * Configure the DDR IO size [0xFFCFB008] + * niosreserve0: Used to indicate DDR width & + * bit[7:0] = Number of data bits (0x20 for 32bit) + * bit[8] = 1 if user-mode OCT is present + * bit[9] = 1 if warm reset compiled into EMIF Cal Code + * bit[10] = 1 if warm reset is on during generation in EMIF Cal + * niosreserve1: IP ADCDS version encoded as 16 bit value + * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta, + * 3=EAP, 4-6 are reserved) + * bit[5:3] = Service Pack # (e.g. 1) + * bit[9:6] = Minor Release # + * bit[14:10] = Major Release # + */ + if ((readl(ARRIA10_IO48_HMC_MMR_NIOSRESERVE1) >> 6) & 0x1FF) { + update_value = readl(ARRIA10_IO48_HMC_MMR_NIOSRESERVE0); + writel(((update_value & 0xFF) >> 5), + ARRIA10_ECC_HMC_OCP_DDRIOCTRL); + } + + ddrioctl = readl(ARRIA10_ECC_HMC_OCP_DDRIOCTRL); + + /* Set the DDR Configuration [0xFFD12400] */ + io48_value = ARRIA_DDR_CONFIG(ctrlcfg1.cfg_addr_order, + (dramaddrw.cfg_bank_addr_width + + dramaddrw.cfg_bank_group_addr_width), + dramaddrw.cfg_col_addr_width, + dramaddrw.cfg_row_addr_width); + + update_value = match_ddr_conf(io48_value); + if (update_value) + writel(update_value, ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRCONF); + + /* + * Configure DDR timing [0xFFD1240C] + * RDTOMISS = tRTP + tRP + tRCD - BL/2 + * WRTOMISS = WL + tWR + tRP + tRCD and + * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so... + * First part of equation is in memory clock units so divide by 2 + * for HMC clock units. 1066MHz is close to 1ns so use 15 directly. + * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD + */ + update_value = (caltim2.cfg_rd_to_pch + caltim4.cfg_pch_to_valid + + caltim0.cfg_act_to_rdwr - + (ctrlcfg0.cfg_ctrl_burst_len >> 2)); + io48_value = ((((readl(ARRIA10_IO48_HMC_MMR_DRAMTIMING0) & + ARRIA10_IO48_DRAMTIME_MEM_READ_LATENCY) + 2 + 15 + + (ctrlcfg0.cfg_ctrl_burst_len >> 1)) >> 1) - + /* Up to here was in memory cycles so divide by 2 */ + caltim1.cfg_rd_to_wr + caltim0.cfg_act_to_rdwr + + caltim4.cfg_pch_to_valid); + + writel(((caltim0.cfg_act_to_act << + ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) | + (update_value << + ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) | + (io48_value << + ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) | + ((ctrlcfg0.cfg_ctrl_burst_len >> 2) << + ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) | + (caltim1.cfg_rd_to_wr << + ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) | + (caltim3.cfg_wr_to_rd << + ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) | + (((ddrioctl == 1) ? 1 : 0) << + ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)), + ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRTIMING); + + /* Configure DDR mode [0xFFD12410] [precharge = 0] */ + writel(((ddrioctl ? 0 : 1) << + ARRIA10_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB), + ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRMODE); + + /* Configure the read latency [0xFFD12414] */ + writel(((readl(ARRIA10_IO48_HMC_MMR_DRAMTIMING0) & + ARRIA10_IO48_DRAMTIME_MEM_READ_LATENCY) >> 1) + + DDR_READ_LATENCY_DELAY, + ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_READLATENCY); + + /* + * Configuring timing values concerning activate commands + * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR] + */ + writel(((caltim0.cfg_act_to_act_db << + ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) | + (caltim9.cfg_4_act_to_act << + ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) | + (ARRIA10_SDR_ACTIVATE_FAWBANK << + ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)), + ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ACTIVATE); + + /* + * Configuring timing values concerning device to device data bus + * ownership change [0xFFD1243C] + */ + writel(((caltim1.cfg_rd_to_rd_dc << + ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) | + (caltim1.cfg_rd_to_wr_dc << + ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) | + (caltim3.cfg_wr_to_rd_dc << + ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)), + ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DEVTODEV); + + /* Enable or disable the SDRAM ECC */ + if (ctrlcfg1.cfg_ctrl_enable_ecc) { + setbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL1, + (ARRIA10_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST | + ARRIA10_ECC_HMC_OCP_ECCCTL_CNT_RST | + ARRIA10_ECC_HMC_OCP_ECCCTL_ECC_EN)); + clrbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL1, + (ARRIA10_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST | + ARRIA10_ECC_HMC_OCP_ECCCTL_CNT_RST)); + setbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL2, + (ARRIA10_ECC_HMC_OCP_ECCCTL2_RMW_EN | + ARRIA10_ECC_HMC_OCP_ECCCTL2_AWB_EN)); + } else { + clrbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL1, + (ARRIA10_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST | + ARRIA10_ECC_HMC_OCP_ECCCTL_CNT_RST | + ARRIA10_ECC_HMC_OCP_ECCCTL_ECC_EN)); + clrbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL2, + (ARRIA10_ECC_HMC_OCP_ECCCTL2_RMW_EN | + ARRIA10_ECC_HMC_OCP_ECCCTL2_AWB_EN)); + } +} + +static int arria10_sdram_firewall_setup(void) +{ + uint32_t mpu_en = 0; + + /* set to default state */ + writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_EN); + writel(0x00000000, ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x00); + + writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION0ADDR); + + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG0EN; + + writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); + writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION1ADDR); + writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION2ADDR); + writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR); + writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR); + + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN; + writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); + + writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR); + writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION2ADDR); + writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR); + writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR); + + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN; + writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); + + writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR); + writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION2ADDR); + writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR); + writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR); + + mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN; + writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN); + + writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR); + writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION2ADDR); + writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION3ADDR); + + writel(0xffff0000, ARRIA10_NOC_FW_DDR_L3_HPSREGION0ADDR); + writel(ARRIA10_NOC_FW_DDR_L3_HPSREG0EN, ARRIA10_NOC_FW_DDR_L3_EN); + + return 0; +} + +int arria10_ddr_calibration_sequence(void) +{ + /* Check to see if SDRAM cal was success */ + if (arria10_sdram_startup()) { + puts_ll("DDRCAL: Failed\n"); + return -1; + } + + puts_ll("DDRCAL: Success\n"); + + /* initialize the MMR register */ + arria10_sdram_mmr_init(); + + if (arria10_sdram_firewall_setup()) + puts_ll("FW: Error Configuring Firewall\n"); + + return 0; +} diff --git a/arch/arm/mach-socfpga/cyclone5-bootsource.c b/arch/arm/mach-socfpga/cyclone5-bootsource.c new file mode 100644 index 0000000000..717a003425 --- /dev/null +++ b/arch/arm/mach-socfpga/cyclone5-bootsource.c @@ -0,0 +1,100 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <bootsource.h> +#include <environment.h> +#include <init.h> +#include <io.h> +#include <mach/cyclone5-system-manager.h> +#include <mach/cyclone5-regs.h> +#include <mach/arria10-system-manager.h> + +#define CYCLONE5_SYSMGR_BOOTINFO 0x14 + +static int cyclone5_boot_save_loc(void) +{ + enum bootsource src = BOOTSOURCE_UNKNOWN; + uint32_t val; + + val = readl(CYCLONE5_SYSMGR_ADDRESS + CYCLONE5_SYSMGR_BOOTINFO); + + switch (val & 0x7) { + case 0: + /* reserved */ + break; + case 1: + /* FPGA, currently not decoded */ + break; + case 2: + case 3: + src = BOOTSOURCE_NAND; + break; + case 4: + case 5: + src = BOOTSOURCE_MMC; + break; + case 6: + case 7: + src = BOOTSOURCE_SPI; + break; + } + + bootsource_set(src); + bootsource_set_instance(0); + + return 0; +} + +static int arria10_boot_save_loc(void) +{ + enum bootsource src = BOOTSOURCE_UNKNOWN; + uint32_t val; + + val = readl(ARRIA10_SYSMGR_BOOTINFO); + + switch ((val & 0x7000) >> 12) { + case 0: + /* reserved */ + break; + case 1: + /* FPGA, currently not decoded */ + break; + case 2: + case 3: + src = BOOTSOURCE_NAND; + break; + case 4: + case 5: + src = BOOTSOURCE_MMC; + break; + case 6: + case 7: + src = BOOTSOURCE_SPI; + break; + } + + bootsource_set(src); + bootsource_set_instance(0); + + return 0; +} + +static int socfpga_boot_save_loc(void) +{ + if (IS_ENABLED(CONFIG_ARCH_SOCFPGA_ARRIA10)) + return arria10_boot_save_loc(); + else + return cyclone5_boot_save_loc(); +} +core_initcall(socfpga_boot_save_loc); diff --git a/arch/arm/mach-socfpga/clock-manager.c b/arch/arm/mach-socfpga/cyclone5-clock-manager.c index f17371365f..79c8b6bf28 100644 --- a/arch/arm/mach-socfpga/clock-manager.c +++ b/arch/arm/mach-socfpga/cyclone5-clock-manager.c @@ -17,8 +17,8 @@ #include <common.h> #include <io.h> -#include <mach/clock-manager.h> -#include <mach/socfpga-regs.h> +#include <mach/cyclone5-clock-manager.h> +#include <mach/cyclone5-regs.h> #include <mach/generic.h> static inline void cm_wait_for_lock(void __iomem *cm, uint32_t mask) diff --git a/arch/arm/mach-socfpga/freeze-controller.c b/arch/arm/mach-socfpga/cyclone5-freeze-controller.c index 570bdeb735..87160161b0 100644 --- a/arch/arm/mach-socfpga/freeze-controller.c +++ b/arch/arm/mach-socfpga/cyclone5-freeze-controller.c @@ -18,7 +18,7 @@ #include <common.h> #include <io.h> #include <mach/generic.h> -#include <mach/freeze-controller.h> +#include <mach/cyclone5-freeze-controller.h> #define SYSMGR_FRZCTRL_LOOP_PARAM (1000) #define SYSMGR_FRZCTRL_DELAY_LOOP_PARAM (10) diff --git a/arch/arm/mach-socfpga/cyclone5-generic.c b/arch/arm/mach-socfpga/cyclone5-generic.c new file mode 100644 index 0000000000..3f49a9a542 --- /dev/null +++ b/arch/arm/mach-socfpga/cyclone5-generic.c @@ -0,0 +1,210 @@ +#include <common.h> +#include <malloc.h> +#include <envfs.h> +#include <init.h> +#include <io.h> +#include <fs.h> +#include <mci.h> +#include <linux/clkdev.h> +#include <linux/clk.h> +#include <linux/stat.h> +#include <linux/sizes.h> +#include <asm/memory.h> +#include <mach/cyclone5-system-manager.h> +#include <mach/cyclone5-reset-manager.h> +#include <mach/cyclone5-regs.h> +#include <mach/generic.h> +#include <mach/nic301.h> +#include <platform_data/dw_mmc.h> +#include <platform_data/serial-ns16550.h> +#include <platform_data/cadence_qspi.h> + +#define SYSMGR_SDMMCGRP_CTRL_REG (CYCLONE5_SYSMGR_ADDRESS + 0x108) +#define SYSMGR_SDMMC_CTRL_SMPLSEL(smplsel) (((smplsel) & 0x7) << 3) +#define SYSMGR_SDMMC_CTRL_DRVSEL(drvsel) ((drvsel) & 0x7) + +enum socfpga_clks { + timer, mmc, qspi_clk, uart, clk_max +}; + +static struct clk *clks[clk_max]; + +#if defined(CONFIG_MCI_DW) +static struct dw_mmc_platform_data mmc_pdata = { + .bus_width_caps = MMC_CAP_4_BIT_DATA, + .ciu_div = 3, +}; + +void socfpga_cyclone5_mmc_init(void) +{ + clks[mmc] = clk_fixed("mmc", 400000000); + clkdev_add_physbase(clks[mmc], CYCLONE5_SDMMC_ADDRESS, NULL); + add_generic_device("dw_mmc", 0, NULL, CYCLONE5_SDMMC_ADDRESS, SZ_4K, + IORESOURCE_MEM, &mmc_pdata); +} +#else +void socfpga_cyclone5_mmc_init(void) +{ + pr_debug("%s: MMC support not compiled in!\n", __func__); + + return; +} +#endif + +#if defined(CONFIG_SPI_CADENCE_QUADSPI) +static struct cadence_qspi_platform_data qspi_pdata = { + .ext_decoder = 0, + .fifo_depth = 128, +}; + +static void add_cadence_qspi_device(int id, resource_size_t ctrl, + resource_size_t data, void *pdata) +{ + struct device_d *dev; + struct resource *res; + + res = xzalloc(sizeof(struct resource) * 2); + res[0].start = ctrl; + res[0].end = ctrl + 0x100 - 1; + res[0].flags = IORESOURCE_MEM; + res[1].start = data; + res[1].end = data + 0x100 - 1; + res[1].flags = IORESOURCE_MEM; + + dev = add_generic_device_res("cadence_qspi", id, res, 2, pdata); + + dev_dbg(dev, "added resource\n"); +} + +void socfpga_cyclone5_qspi_init(void) +{ + clks[qspi_clk] = clk_fixed("qspi_clk", 370000000); + clkdev_add_physbase(clks[qspi_clk], CYCLONE5_QSPI_CTRL_ADDRESS, NULL); + clkdev_add_physbase(clks[qspi_clk], CYCLONE5_QSPI_DATA_ADDRESS, NULL); + add_cadence_qspi_device(0, CYCLONE5_QSPI_CTRL_ADDRESS, + CYCLONE5_QSPI_DATA_ADDRESS, &qspi_pdata); +} +#else +void socfpga_cyclone5_qspi_init(void) +{ + pr_debug("%s: QSPI support not compiled in!\n", __func__); + + return; +} +#endif + +static struct NS16550_plat uart_pdata = { + .clock = 100000000, + .shift = 2, +}; + +void socfpga_cyclone5_uart_init(void) +{ + struct device_d *dev; + + clks[uart] = clk_fixed("uart", 100000000); + clkdev_add_physbase(clks[uart], CYCLONE5_UART0_ADDRESS, NULL); + clkdev_add_physbase(clks[uart], CYCLONE5_UART1_ADDRESS, NULL); + dev = add_ns16550_device(0, 0xffc02000, 1024, IORESOURCE_MEM | + IORESOURCE_MEM_8BIT, &uart_pdata); + + dev_dbg(dev, "initialized\n"); +} + +void socfpga_cyclone5_timer_init(void) +{ + struct device_d *dev; + + clks[timer] = clk_fixed("timer", 200000000); + clkdev_add_physbase(clks[timer], CYCLONE5_SMP_TWD_ADDRESS, NULL); + dev = add_generic_device("smp_twd", 0, NULL, CYCLONE5_SMP_TWD_ADDRESS, 0x100, + IORESOURCE_MEM, NULL); + + dev_dbg(dev, "added smp_twd\n"); +} + +static int socfpga_detect_sdram(void) +{ + void __iomem *base = (void *)CYCLONE5_SDR_ADDRESS; + uint32_t dramaddrw, ctrlwidth, memsize; + int colbits, rowbits, bankbits; + int width_bytes; + + dramaddrw = readl(base + 0x5000 + 0x2c); + + colbits = dramaddrw & 0x1f; + rowbits = (dramaddrw >> 5) & 0x1f; + bankbits = (dramaddrw >> 10) & 0x7; + + ctrlwidth = readl(base + 0x5000 + 0x60); + + switch (ctrlwidth & 0x3) { + default: + case 0: + width_bytes = 1; + break; + case 1: + width_bytes = 2; + break; + case 2: + width_bytes = 4; + break; + } + + memsize = (1 << colbits) * (1 << rowbits) * (1 << bankbits) * width_bytes; + + pr_debug("%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08x\n", + __func__, colbits, rowbits, bankbits, width_bytes, memsize); + + arm_add_mem_device("ram0", 0x0, memsize); + + return 0; +} + +/* Some initialization for the EMAC */ +static void socfpga_init_emac(void) +{ + uint32_t rst, val; + + /* No need for this without network support, e.g. xloader build */ + if (!IS_ENABLED(CONFIG_NET)) + return; + + /* According to Cyclone V datasheet, 17-60 "EMAC HPS Interface + * Initialization", changing PHYSEL should be done with EMAC in reset + * via permodrst. */ + + /* Everything, except L4WD0/1, is out of reset via socfpga_lowlevel_init() */ + rst = readl(CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS); + rst |= RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1; + writel(rst, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS); + + /* Set emac0/1 PHY interface select to RGMII. We could read phy-mode + * from the device tree, if it was desired to support interfaces other + * than RGMII. */ + val = readl(CONFIG_SYSMGR_EMAC_CTRL); + val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB); + val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB); + val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; + val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; + writel(val, CONFIG_SYSMGR_EMAC_CTRL); + + /* Take emac0 and emac1 out of reset */ + rst &= ~(RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1); + writel(rst, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS); +} + +static int socfpga_init(void) +{ + socfpga_init_emac(); + + writel(SYSMGR_SDMMC_CTRL_DRVSEL(3) | SYSMGR_SDMMC_CTRL_SMPLSEL(0), + SYSMGR_SDMMCGRP_CTRL_REG); + + nic301_slave_ns(); + + socfpga_detect_sdram(); + + return 0; +} +core_initcall(socfpga_init); diff --git a/arch/arm/mach-socfpga/init.c b/arch/arm/mach-socfpga/cyclone5-init.c index 0c679e3d2d..412808b841 100644 --- a/arch/arm/mach-socfpga/init.c +++ b/arch/arm/mach-socfpga/cyclone5-init.c @@ -2,11 +2,11 @@ #include <common.h> #include <init.h> #include <io.h> -#include <mach/freeze-controller.h> -#include <mach/system-manager.h> -#include <mach/clock-manager.h> -#include <mach/reset-manager.h> -#include <mach/scan-manager.h> +#include <mach/cyclone5-freeze-controller.h> +#include <mach/cyclone5-system-manager.h> +#include <mach/cyclone5-clock-manager.h> +#include <mach/cyclone5-reset-manager.h> +#include <mach/cyclone5-scan-manager.h> #include <mach/generic.h> void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config, diff --git a/arch/arm/mach-socfpga/reset-manager.c b/arch/arm/mach-socfpga/cyclone5-reset-manager.c index 04522da4d1..4bbe1a8101 100644 --- a/arch/arm/mach-socfpga/reset-manager.c +++ b/arch/arm/mach-socfpga/cyclone5-reset-manager.c @@ -19,8 +19,8 @@ #include <io.h> #include <init.h> #include <restart.h> -#include <mach/socfpga-regs.h> -#include <mach/reset-manager.h> +#include <mach/cyclone5-regs.h> +#include <mach/cyclone5-reset-manager.h> /* Disable the watchdog (toggle reset to watchdog) */ void watchdog_disable(void) diff --git a/arch/arm/mach-socfpga/scan-manager.c b/arch/arm/mach-socfpga/cyclone5-scan-manager.c index 57979b90a2..cf076c3885 100644 --- a/arch/arm/mach-socfpga/scan-manager.c +++ b/arch/arm/mach-socfpga/cyclone5-scan-manager.c @@ -17,8 +17,8 @@ #include <common.h> #include <io.h> -#include <mach/freeze-controller.h> -#include <mach/scan-manager.h> +#include <mach/cyclone5-freeze-controller.h> +#include <mach/cyclone5-scan-manager.h> /* * @fn scan_mgr_io_scan_chain_engine_is_idle diff --git a/arch/arm/mach-socfpga/system-manager.c b/arch/arm/mach-socfpga/cyclone5-system-manager.c index 45db921f1a..7e86692c39 100644 --- a/arch/arm/mach-socfpga/system-manager.c +++ b/arch/arm/mach-socfpga/cyclone5-system-manager.c @@ -17,8 +17,8 @@ #include <common.h> #include <io.h> -#include <mach/system-manager.h> -#include <mach/socfpga-regs.h> +#include <mach/cyclone5-system-manager.h> +#include <mach/cyclone5-regs.h> void socfpga_sysmgr_pinmux_init(unsigned long *sys_mgr_init_table, int num) { diff --git a/arch/arm/mach-socfpga/generic.c b/arch/arm/mach-socfpga/generic.c deleted file mode 100644 index c920bd658f..0000000000 --- a/arch/arm/mach-socfpga/generic.c +++ /dev/null @@ -1,104 +0,0 @@ -#include <common.h> -#include <malloc.h> -#include <envfs.h> -#include <init.h> -#include <io.h> -#include <fs.h> -#include <linux/clkdev.h> -#include <linux/clk.h> -#include <linux/stat.h> -#include <asm/memory.h> -#include <mach/system-manager.h> -#include <mach/reset-manager.h> -#include <mach/socfpga-regs.h> -#include <mach/nic301.h> - -#define SYSMGR_SDMMCGRP_CTRL_REG (CYCLONE5_SYSMGR_ADDRESS + 0x108) -#define SYSMGR_SDMMC_CTRL_SMPLSEL(smplsel) (((smplsel) & 0x7) << 3) -#define SYSMGR_SDMMC_CTRL_DRVSEL(drvsel) ((drvsel) & 0x7) - -static int socfpga_detect_sdram(void) -{ - void __iomem *base = (void *)CYCLONE5_SDR_ADDRESS; - uint32_t dramaddrw, ctrlwidth, memsize; - int colbits, rowbits, bankbits; - int width_bytes; - - dramaddrw = readl(base + 0x5000 + 0x2c); - - colbits = dramaddrw & 0x1f; - rowbits = (dramaddrw >> 5) & 0x1f; - bankbits = (dramaddrw >> 10) & 0x7; - - ctrlwidth = readl(base + 0x5000 + 0x60); - - switch (ctrlwidth & 0x3) { - default: - case 0: - width_bytes = 1; - break; - case 1: - width_bytes = 2; - break; - case 2: - width_bytes = 4; - break; - } - - memsize = (1 << colbits) * (1 << rowbits) * (1 << bankbits) * width_bytes; - - pr_debug("%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08x\n", - __func__, colbits, rowbits, bankbits, width_bytes, memsize); - - arm_add_mem_device("ram0", 0x0, memsize); - - return 0; -} - -/* Some initialization for the EMAC */ -static void socfpga_init_emac(void) -{ - uint32_t rst, val; - - /* No need for this without network support, e.g. xloader build */ - if (!IS_ENABLED(CONFIG_NET)) - return; - - /* According to Cyclone V datasheet, 17-60 "EMAC HPS Interface - * Initialization", changing PHYSEL should be done with EMAC in reset - * via permodrst. */ - - /* Everything, except L4WD0/1, is out of reset via socfpga_lowlevel_init() */ - rst = readl(CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS); - rst |= RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1; - writel(rst, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS); - - /* Set emac0/1 PHY interface select to RGMII. We could read phy-mode - * from the device tree, if it was desired to support interfaces other - * than RGMII. */ - val = readl(CONFIG_SYSMGR_EMAC_CTRL); - val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB); - val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB); - val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; - val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; - writel(val, CONFIG_SYSMGR_EMAC_CTRL); - - /* Take emac0 and emac1 out of reset */ - rst &= ~(RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1); - writel(rst, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS); -} - -static int socfpga_init(void) -{ - socfpga_init_emac(); - - writel(SYSMGR_SDMMC_CTRL_DRVSEL(3) | SYSMGR_SDMMC_CTRL_SMPLSEL(0), - SYSMGR_SDMMCGRP_CTRL_REG); - - nic301_slave_ns(); - - socfpga_detect_sdram(); - - return 0; -} -core_initcall(socfpga_init); diff --git a/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h new file mode 100644 index 0000000000..ee2b9b3c5e --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h @@ -0,0 +1,249 @@ +/* + * Copyright (C) 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ARRIA10_CLOCK_MANAGER_H_ +#define _ARRIA10_CLOCK_MANAGER_H_ + +struct arria10_clock_manager { + /* clkmgr */ + volatile uint32_t ctrl; + volatile uint32_t intr; + volatile uint32_t intrs; + volatile uint32_t intrr; + volatile uint32_t intren; + volatile uint32_t intrens; + volatile uint32_t intrenr; + volatile uint32_t stat; + volatile uint32_t testioctrl; + volatile uint32_t _pad_0x24_0x40[7]; + + /* mainpllgrp*/ + volatile uint32_t main_pll_vco0; + volatile uint32_t main_pll_vco1; + volatile uint32_t main_pll_en; + volatile uint32_t main_pll_ens; + volatile uint32_t main_pll_enr; + volatile uint32_t main_pll_bypass; + volatile uint32_t main_pll_bypasss; + volatile uint32_t main_pll_bypassr; + volatile uint32_t main_pll_mpuclk; + volatile uint32_t main_pll_nocclk; + volatile uint32_t main_pll_cntr2clk; + volatile uint32_t main_pll_cntr3clk; + volatile uint32_t main_pll_cntr4clk; + volatile uint32_t main_pll_cntr5clk; + volatile uint32_t main_pll_cntr6clk; + volatile uint32_t main_pll_cntr7clk; + volatile uint32_t main_pll_cntr8clk; + volatile uint32_t main_pll_cntr9clk; + volatile uint32_t main_pll__pad_0x48_0x5b[5]; + volatile uint32_t main_pll_cntr15clk; + volatile uint32_t main_pll_outrst; + volatile uint32_t main_pll_outrststat; + volatile uint32_t main_pll_nocdiv; + volatile uint32_t main_pll__pad_0x6c_0x80[5]; + + /* perpllgrp*/ + volatile uint32_t per_pll_vco0; + volatile uint32_t per_pll_vco1; + volatile uint32_t per_pll_en; + volatile uint32_t per_pll_ens; + volatile uint32_t per_pll_enr; + volatile uint32_t per_pll_bypass; + volatile uint32_t per_pll_bypasss; + volatile uint32_t per_pll_bypassr; + volatile uint32_t per_pll__pad_0x20_0x27[2]; + volatile uint32_t per_pll_cntr2clk; + volatile uint32_t per_pll_cntr3clk; + volatile uint32_t per_pll_cntr4clk; + volatile uint32_t per_pll_cntr5clk; + volatile uint32_t per_pll_cntr6clk; + volatile uint32_t per_pll_cntr7clk; + volatile uint32_t per_pll_cntr8clk; + volatile uint32_t per_pll_cntr9clk; + volatile uint32_t per_pll__pad_0x48_0x5f[6]; + volatile uint32_t per_pll_outrst; + volatile uint32_t per_pll_outrststat; + volatile uint32_t per_pll_emacctl; + volatile uint32_t per_pll_gpiodiv; + volatile uint32_t per_pll__pad_0x70_0x80[4]; +}; + +struct arria10_mainpll_cfg { + uint32_t vco0_psrc; + uint32_t vco1_denom; + uint32_t vco1_numer; + uint32_t mpuclk; + uint32_t mpuclk_cnt; + uint32_t mpuclk_src; + uint32_t nocclk; + uint32_t nocclk_cnt; + uint32_t nocclk_src; + uint32_t cntr2clk_cnt; + uint32_t cntr3clk_cnt; + uint32_t cntr4clk_cnt; + uint32_t cntr5clk_cnt; + uint32_t cntr6clk_cnt; + uint32_t cntr7clk_cnt; + uint32_t cntr7clk_src; + uint32_t cntr8clk_cnt; + uint32_t cntr9clk_cnt; + uint32_t cntr9clk_src; + uint32_t cntr15clk_cnt; + uint32_t nocdiv_l4mainclk; + uint32_t nocdiv_l4mpclk; + uint32_t nocdiv_l4spclk; + uint32_t nocdiv_csatclk; + uint32_t nocdiv_cstraceclk; + uint32_t nocdiv_cspdbgclk; +}; + +struct arria10_perpll_cfg { + uint32_t vco0_psrc; + uint32_t vco1_denom; + uint32_t vco1_numer; + uint32_t cntr2clk_cnt; + uint32_t cntr2clk_src; + uint32_t cntr3clk_cnt; + uint32_t cntr3clk_src; + uint32_t cntr4clk_cnt; + uint32_t cntr4clk_src; + uint32_t cntr5clk_cnt; + uint32_t cntr5clk_src; + uint32_t cntr6clk_cnt; + uint32_t cntr6clk_src; + uint32_t cntr7clk_cnt; + uint32_t cntr8clk_cnt; + uint32_t cntr8clk_src; + uint32_t cntr9clk_cnt; + uint32_t cntr9clk_src; + uint32_t emacctl_emac0sel; + uint32_t emacctl_emac1sel; + uint32_t emacctl_emac2sel; + uint32_t gpiodiv_gpiodbclk; +}; + +extern int arria10_cm_basic_init(struct arria10_mainpll_cfg *mainpll_cfg, + struct arria10_perpll_cfg *perpll_cfg); +extern unsigned int cm_get_mmc_controller_clk_hz(void); +extern void arria10_cm_use_intosc(void); +extern uint32_t cm_l4_main_clk_hz; +extern uint32_t cm_l4_sp_clk_hz; +extern uint32_t cm_l4_mp_clk_hz; +extern uint32_t cm_l4_sys_free_clk_hz; + +#define ARRIA10_CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140 +#define ARRIA10_CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144 + +/* value */ +#define ARRIA10_CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f +#define ARRIA10_CLKMGR_MAINPLL_VCO0_RESET 0x00010053 +#define ARRIA10_CLKMGR_MAINPLL_VCO1_RESET 0x00010001 +#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0 +#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1 +#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_F2S 0x2 +#define ARRIA10_CLKMGR_PERPLL_BYPASS_RESET 0x000000ff +#define ARRIA10_CLKMGR_PERPLL_VCO0_RESET 0x00010053 +#define ARRIA10_CLKMGR_PERPLL_VCO1_RESET 0x00010001 +#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_EOSC 0x0 +#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC 0x1 +#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_F2S 0x2 +#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MAIN 0x3 + +/* mask */ +#define ARRIA10_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK 0x00000040 +#define ARRIA10_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK 0x00000080 +#define ARRIA10_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK 0x00000001 +#define ARRIA10_CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK 0x00000002 +#define ARRIA10_CLKMGR_MAINPLL_VCO0_EN_SET_MSK 0x00000004 +#define ARRIA10_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008 +#define ARRIA10_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010 +#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_MSK 0x00000003 +#define ARRIA10_CLKMGR_MAINPLL_VCO1_NUMER_MSK 0x00001fff +#define ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_MSK 0x0000003f +#define ARRIA10_CLKMGR_MAINPLL_CNTRCLK_MSK 0x000003ff +#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK 0x000003ff +#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN 0 +#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI 1 +#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_OSC1 2 +#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC 3 +#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_FPGA 4 +#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_MSK 0x00000003 +#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK 0x000003ff +#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MSK 0x00000007 +#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN 0 +#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI 1 +#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_OSC1 2 +#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC 3 +#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_FPGA 4 +#define ARRIA10_CLKMGR_CLKMGR_STAT_BUSY_SET_MSK 0x00000001 +#define ARRIA10_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK 0x00000100 +#define ARRIA10_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK 0x00000200 +#define ARRIA10_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK 0x00020000 +#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK 0x00000800 +#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK 0x00000400 +#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK 0x00000200 +#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK 0x00000100 +#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK 0x00000008 +#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK 0x00000004 +#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK 0x00000001 +#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK 0x00000002 +#define ARRIA10_CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK 0x00000001 +#define ARRIA10_CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK 0x00000300 +#define ARRIA10_CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK 0x00000001 +#define ARRIA10_CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK 0x00000002 +#define ARRIA10_CLKMGR_PERPLL_VCO0_EN_SET_MSK 0x00000004 +#define ARRIA10_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008 +#define ARRIA10_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010 +#define ARRIA10_CLKMGR_PERPLL_EN_RESET 0x00000f7f +#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MSK 0x00000003 +#define ARRIA10_CLKMGR_PERPLL_VCO1_NUMER_MSK 0x00001fff +#define ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_MSK 0x0000003f +#define ARRIA10_CLKMGR_PERPLL_CNTRCLK_MSK 0x000003ff + +#define ARRIA10_CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020 +#define ARRIA10_CLKMGR_PERPLLGRP_SRC_MSK 0x00000007 +#define ARRIA10_CLKMGR_PERPLLGRP_SRC_MAIN 0 +#define ARRIA10_CLKMGR_PERPLLGRP_SRC_PERI 1 +#define ARRIA10_CLKMGR_PERPLLGRP_SRC_OSC1 2 +#define ARRIA10_CLKMGR_PERPLLGRP_SRC_INTOSC 3 +#define ARRIA10_CLKMGR_PERPLLGRP_SRC_FPGA 4 + +/* bit shifting macro */ +#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_LSB 8 +#define ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB 16 +#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB 16 +#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16 +#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0 +#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8 +#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16 +#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24 +#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26 +#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28 +#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16 +#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB 16 +#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16 +#define ARRIA10_CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16 +#define ARRIA10_CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16 +#define ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB 16 +#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_LSB 8 +#define ARRIA10_CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16 +#define ARRIA10_CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16 +#define ARRIA10_CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16 +#define ARRIA10_CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16 +#define ARRIA10_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16 +#define ARRIA10_CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16 +#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26 +#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27 +#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28 + +/* PLL ramping work around */ +#define ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ 900000000 +#define ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ 300000000 +#define ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ 100000000 +#define ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ 33000000 + +#endif /* _ARRIA10_CLOCK_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h b/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h new file mode 100644 index 0000000000..979e4769db --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h @@ -0,0 +1,250 @@ +/* + * Copyright (C) 2017 Pengutronix, Steffen Trumtrar <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _ARRIA10_PINMUX_H_ +#define _ARRIA10_PINMUX_H_ + +#include <mach/arria10-regs.h> + +#define ARRIA10_PINMUX_SHARED_IO_Q1_1_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x00 +#define ARRIA10_PINMUX_SHARED_IO_Q1_2_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x04 +#define ARRIA10_PINMUX_SHARED_IO_Q1_3_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x08 +#define ARRIA10_PINMUX_SHARED_IO_Q1_4_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x0c +#define ARRIA10_PINMUX_SHARED_IO_Q1_5_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x10 +#define ARRIA10_PINMUX_SHARED_IO_Q1_6_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x14 +#define ARRIA10_PINMUX_SHARED_IO_Q1_7_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x18 +#define ARRIA10_PINMUX_SHARED_IO_Q1_8_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x1c +#define ARRIA10_PINMUX_SHARED_IO_Q1_9_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x20 +#define ARRIA10_PINMUX_SHARED_IO_Q1_10_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x24 +#define ARRIA10_PINMUX_SHARED_IO_Q1_11_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x28 +#define ARRIA10_PINMUX_SHARED_IO_Q1_12_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x2c +#define ARRIA10_PINMUX_SHARED_IO_Q2_1_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x30 +#define ARRIA10_PINMUX_SHARED_IO_Q2_2_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x34 +#define ARRIA10_PINMUX_SHARED_IO_Q2_3_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x38 +#define ARRIA10_PINMUX_SHARED_IO_Q2_4_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x3c +#define ARRIA10_PINMUX_SHARED_IO_Q2_5_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x40 +#define ARRIA10_PINMUX_SHARED_IO_Q2_6_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x44 +#define ARRIA10_PINMUX_SHARED_IO_Q2_7_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x48 +#define ARRIA10_PINMUX_SHARED_IO_Q2_8_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x4c +#define ARRIA10_PINMUX_SHARED_IO_Q2_9_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x50 +#define ARRIA10_PINMUX_SHARED_IO_Q2_10_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x54 +#define ARRIA10_PINMUX_SHARED_IO_Q2_11_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x58 +#define ARRIA10_PINMUX_SHARED_IO_Q2_12_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x5c +#define ARRIA10_PINMUX_SHARED_IO_Q3_1_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x60 +#define ARRIA10_PINMUX_SHARED_IO_Q3_2_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x64 +#define ARRIA10_PINMUX_SHARED_IO_Q3_3_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x68 +#define ARRIA10_PINMUX_SHARED_IO_Q3_4_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x6c +#define ARRIA10_PINMUX_SHARED_IO_Q3_5_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x70 +#define ARRIA10_PINMUX_SHARED_IO_Q3_6_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x74 +#define ARRIA10_PINMUX_SHARED_IO_Q3_7_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x78 +#define ARRIA10_PINMUX_SHARED_IO_Q3_8_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x7c +#define ARRIA10_PINMUX_SHARED_IO_Q3_9_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x80 +#define ARRIA10_PINMUX_SHARED_IO_Q3_10_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x84 +#define ARRIA10_PINMUX_SHARED_IO_Q3_11_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x88 +#define ARRIA10_PINMUX_SHARED_IO_Q3_12_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x8c +#define ARRIA10_PINMUX_SHARED_IO_Q4_1_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x90 +#define ARRIA10_PINMUX_SHARED_IO_Q4_2_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x94 +#define ARRIA10_PINMUX_SHARED_IO_Q4_3_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x98 +#define ARRIA10_PINMUX_SHARED_IO_Q4_4_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0x9c +#define ARRIA10_PINMUX_SHARED_IO_Q4_5_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xa0 +#define ARRIA10_PINMUX_SHARED_IO_Q4_6_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xa4 +#define ARRIA10_PINMUX_SHARED_IO_Q4_7_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xa8 +#define ARRIA10_PINMUX_SHARED_IO_Q4_8_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xac +#define ARRIA10_PINMUX_SHARED_IO_Q4_9_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xb0 +#define ARRIA10_PINMUX_SHARED_IO_Q4_10_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xb4 +#define ARRIA10_PINMUX_SHARED_IO_Q4_11_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xb8 +#define ARRIA10_PINMUX_SHARED_IO_Q4_12_ADDR ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR + 0xbc + +#define ARRIA10_PINMUX_SHARED_IO_Q1_I2C 0 +#define ARRIA10_PINMUX_SHARED_IO_Q1_EMAC 1 +#define ARRIA10_PINMUX_SHARED_IO_Q1_SPIS 2 +#define ARRIA10_PINMUX_SHARED_IO_Q1_SPIM 3 +#define ARRIA10_PINMUX_SHARED_IO_Q1_SDMMC 4 +#define ARRIA10_PINMUX_SHARED_IO_Q1_USB 8 +#define ARRIA10_PINMUX_SHARED_IO_Q1_QSPI 12 +#define ARRIA10_PINMUX_SHARED_IO_Q1_UART 13 +#define ARRIA10_PINMUX_SHARED_IO_Q1_NAND 14 +#define ARRIA10_PINMUX_SHARED_IO_Q1_GPIO 15 + +#define ARRIA10_PINMUX_SHARED_IO_Q2_I2C 0 +#define ARRIA10_PINMUX_SHARED_IO_Q2_SPIS 2 +#define ARRIA10_PINMUX_SHARED_IO_Q2_SPIM 3 +#define ARRIA10_PINMUX_SHARED_IO_Q2_EMAC 4 +#define ARRIA10_PINMUX_SHARED_IO_Q2_USB 8 +#define ARRIA10_PINMUX_SHARED_IO_Q2_UART 13 +#define ARRIA10_PINMUX_SHARED_IO_Q2_NAND 14 +#define ARRIA10_PINMUX_SHARED_IO_Q2_GPIO 15 + +#define ARRIA10_PINMUX_SHARED_IO_Q3_I2C 0 +#define ARRIA10_PINMUX_SHARED_IO_Q3_EMAC0 1 +#define ARRIA10_PINMUX_SHARED_IO_Q3_SPIS 2 +#define ARRIA10_PINMUX_SHARED_IO_Q3_SPIM 3 +#define ARRIA10_PINMUX_SHARED_IO_Q3_EMAC1 8 +#define ARRIA10_PINMUX_SHARED_IO_Q3_UART 13 +#define ARRIA10_PINMUX_SHARED_IO_Q3_NAND 14 +#define ARRIA10_PINMUX_SHARED_IO_Q3_GPIO 15 + +#define ARRIA10_PINMUX_SHARED_IO_Q4_I2C 0 +#define ARRIA10_PINMUX_SHARED_IO_Q4_EMAC0 1 +#define ARRIA10_PINMUX_SHARED_IO_Q4_SPIS 2 +#define ARRIA10_PINMUX_SHARED_IO_Q4_SPIM 3 +#define ARRIA10_PINMUX_SHARED_IO_Q4_SDMMC 4 +#define ARRIA10_PINMUX_SHARED_IO_Q4_EMAC1 8 +#define ARRIA10_PINMUX_SHARED_IO_Q4_QSPI 12 +#define ARRIA10_PINMUX_SHARED_IO_Q4_UART 13 +#define ARRIA10_PINMUX_SHARED_IO_Q4_NAND 14 +#define ARRIA10_PINMUX_SHARED_IO_Q4_GPIO 15 + +#define ARRIA10_PINMUX_DEDICATED_IO_1_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x00 +#define ARRIA10_PINMUX_DEDICATED_IO_2_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x04 +#define ARRIA10_PINMUX_DEDICATED_IO_3_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x08 +#define ARRIA10_PINMUX_DEDICATED_IO_4_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x0c +#define ARRIA10_PINMUX_DEDICATED_IO_5_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x10 +#define ARRIA10_PINMUX_DEDICATED_IO_6_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x14 +#define ARRIA10_PINMUX_DEDICATED_IO_7_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x18 +#define ARRIA10_PINMUX_DEDICATED_IO_8_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x1c +#define ARRIA10_PINMUX_DEDICATED_IO_9_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x20 +#define ARRIA10_PINMUX_DEDICATED_IO_10_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x24 +#define ARRIA10_PINMUX_DEDICATED_IO_11_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x28 +#define ARRIA10_PINMUX_DEDICATED_IO_12_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x2c +#define ARRIA10_PINMUX_DEDICATED_IO_13_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x30 +#define ARRIA10_PINMUX_DEDICATED_IO_14_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x34 +#define ARRIA10_PINMUX_DEDICATED_IO_15_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x38 +#define ARRIA10_PINMUX_DEDICATED_IO_16_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x3c +#define ARRIA10_PINMUX_DEDICATED_IO_17_ADDR ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR + 0x40 + +#define ARRIA10_PINCFG_DEDICATED_IO_BANK_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x00 +#define ARRIA10_PINCFG_DEDICATED_IO_1_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x04 +#define ARRIA10_PINCFG_DEDICATED_IO_2_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x08 +#define ARRIA10_PINCFG_DEDICATED_IO_3_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x0c +#define ARRIA10_PINCFG_DEDICATED_IO_4_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x10 +#define ARRIA10_PINCFG_DEDICATED_IO_5_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x14 +#define ARRIA10_PINCFG_DEDICATED_IO_6_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x18 +#define ARRIA10_PINCFG_DEDICATED_IO_7_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x1c +#define ARRIA10_PINCFG_DEDICATED_IO_8_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x20 +#define ARRIA10_PINCFG_DEDICATED_IO_9_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x24 +#define ARRIA10_PINCFG_DEDICATED_IO_10_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x28 +#define ARRIA10_PINCFG_DEDICATED_IO_11_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x2c +#define ARRIA10_PINCFG_DEDICATED_IO_12_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x30 +#define ARRIA10_PINCFG_DEDICATED_IO_13_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x34 +#define ARRIA10_PINCFG_DEDICATED_IO_14_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x38 +#define ARRIA10_PINCFG_DEDICATED_IO_15_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x3c +#define ARRIA10_PINCFG_DEDICATED_IO_16_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x40 +#define ARRIA10_PINCFG_DEDICATED_IO_17_ADDR ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR + 0x44 + +enum arria10_pinmux_io_addr { + arria10_pinmux_shared_io_q1_1, + arria10_pinmux_shared_io_q1_2, + arria10_pinmux_shared_io_q1_3, + arria10_pinmux_shared_io_q1_4, + arria10_pinmux_shared_io_q1_5, + arria10_pinmux_shared_io_q1_6, + arria10_pinmux_shared_io_q1_7, + arria10_pinmux_shared_io_q1_8, + arria10_pinmux_shared_io_q1_9, + arria10_pinmux_shared_io_q1_10, + arria10_pinmux_shared_io_q1_11, + arria10_pinmux_shared_io_q1_12, + arria10_pinmux_shared_io_q2_1, + arria10_pinmux_shared_io_q2_2, + arria10_pinmux_shared_io_q2_3, + arria10_pinmux_shared_io_q2_4, + arria10_pinmux_shared_io_q2_5, + arria10_pinmux_shared_io_q2_6, + arria10_pinmux_shared_io_q2_7, + arria10_pinmux_shared_io_q2_8, + arria10_pinmux_shared_io_q2_9, + arria10_pinmux_shared_io_q2_10, + arria10_pinmux_shared_io_q2_11, + arria10_pinmux_shared_io_q2_12, + arria10_pinmux_shared_io_q3_1, + arria10_pinmux_shared_io_q3_2, + arria10_pinmux_shared_io_q3_3, + arria10_pinmux_shared_io_q3_4, + arria10_pinmux_shared_io_q3_5, + arria10_pinmux_shared_io_q3_6, + arria10_pinmux_shared_io_q3_7, + arria10_pinmux_shared_io_q3_8, + arria10_pinmux_shared_io_q3_9, + arria10_pinmux_shared_io_q3_10, + arria10_pinmux_shared_io_q3_11, + arria10_pinmux_shared_io_q3_12, + arria10_pinmux_shared_io_q4_1, + arria10_pinmux_shared_io_q4_2, + arria10_pinmux_shared_io_q4_3, + arria10_pinmux_shared_io_q4_4, + arria10_pinmux_shared_io_q4_5, + arria10_pinmux_shared_io_q4_6, + arria10_pinmux_shared_io_q4_7, + arria10_pinmux_shared_io_q4_8, + arria10_pinmux_shared_io_q4_9, + arria10_pinmux_shared_io_q4_10, + arria10_pinmux_shared_io_q4_11, + arria10_pinmux_shared_io_q4_12, + arria10_pinmux_dedicated_io_1, + arria10_pinmux_dedicated_io_2, + arria10_pinmux_dedicated_io_3, + arria10_pinmux_dedicated_io_4, + arria10_pinmux_dedicated_io_5, + arria10_pinmux_dedicated_io_6, + arria10_pinmux_dedicated_io_7, + arria10_pinmux_dedicated_io_8, + arria10_pinmux_dedicated_io_9, + arria10_pinmux_dedicated_io_10, + arria10_pinmux_dedicated_io_11, + arria10_pinmux_dedicated_io_12, + arria10_pinmux_dedicated_io_13, + arria10_pinmux_dedicated_io_14, + arria10_pinmux_dedicated_io_15, + arria10_pinmux_dedicated_io_16, + arria10_pinmux_dedicated_io_17, + arria10_pincfg_dedicated_io_bank, + arria10_pincfg_dedicated_io_1, + arria10_pincfg_dedicated_io_2, + arria10_pincfg_dedicated_io_3, + arria10_pincfg_dedicated_io_4, + arria10_pincfg_dedicated_io_5, + arria10_pincfg_dedicated_io_6, + arria10_pincfg_dedicated_io_7, + arria10_pincfg_dedicated_io_8, + arria10_pincfg_dedicated_io_9, + arria10_pincfg_dedicated_io_10, + arria10_pincfg_dedicated_io_11, + arria10_pincfg_dedicated_io_12, + arria10_pincfg_dedicated_io_13, + arria10_pincfg_dedicated_io_14, + arria10_pincfg_dedicated_io_15, + arria10_pincfg_dedicated_io_16, + arria10_pincfg_dedicated_io_17, + arria10_pinmux_rgmii0_usefpga, + arria10_pinmux_rgmii1_usefpga, + arria10_pinmux_rgmii2_usefpga, + arria10_pinmux_i2c0_usefpga, + arria10_pinmux_i2c1_usefpga, + arria10_pinmux_i2cemac0_usefpga, + arria10_pinmux_i2cemac1_usefpga, + arria10_pinmux_i2cemac2_usefpga, + arria10_pinmux_nand_usefpga, + arria10_pinmux_qspi_usefpga, + arria10_pinmux_sdmmc_usefpga, + arria10_pinmux_spim0_usefpga, + arria10_pinmux_spim1_usefpga, + arria10_pinmux_spis0_usefpga, + arria10_pinmux_spis1_usefpga, + arria10_pinmux_uart0_usefpga, + arria10_pinmux_uart1_usefpga, + arria10_pinmux_max +}; +#endif diff --git a/arch/arm/mach-socfpga/include/mach/arria10-regs.h b/arch/arm/mach-socfpga/include/mach/arria10-regs.h new file mode 100644 index 0000000000..5569574e15 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/arria10-regs.h @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ARRIA10_HARDWARE_H_ +#define _ARRIA10_HARDWARE_H_ + +#define ARRIA10_EMAC0_ADDR (0xff800000) +#define ARRIA10_EMAC1_ADDR (0xff802000) +#define ARRIA10_EMAC2_ADDR (0xff804000) +#define ARRIA10_SDMMC_ADDR (0xff808000) +#define ARRIA10_QSPIREGS_ADDR (0xff809000) +#define ARRIA10_ECC_OCRAM_ADDR (0xff8c3000) +#define ARRIA10_QSPIDATA_ADDR (0xffa00000) +#define ARRIA10_UART0_ADDR (0xffc02000) +#define ARRIA10_UART1_ADDR (0xffc02100) +#define ARRIA10_I2C0_ADDR (0xffc02200) +#define ARRIA10_I2C1_ADDR (0xffc02300) +#define ARRIA10_GPIO0_ADDR (0xffc02900) +#define ARRIA10_GPIO1_ADDR (0xffc02a00) +#define ARRIA10_GPIO2_ADDR (0xffc02b00) +#define ARRIA10_HMC_MMR_IO48_ADDR (0xffcfa000) +#define ARRIA10_SDR_ADDR (0xffcfb000) +#define ARRIA10_FPGAMGRDATA_ADDR (0xffcfe400) +#define ARRIA10_OSC1TIMER0_ADDR (0xffd00000) +#define ARRIA10_L4WD0_ADDR (0xffd00200) +#define ARRIA10_FPGAMGRREGS_ADDR (0xffd03000) +#define ARRIA10_CLKMGR_ADDR (0xffd04000) +#define ARRIA10_RSTMGR_ADDR (0xffd05000) +#define ARRIA10_SYSMGR_ADDR (0xffd06000) +#define ARRIA10_PINMUX_SHARED_3V_IO_GRP_ADDR (0xffd07000) +#define ARRIA10_PINMUX_DEDICATED_IO_GRP_ADDR (0xffd07200) +#define ARRIA10_PINMUX_CFG_DEDICATED_IO_GRP_ADDR (0xffd07300) +#define ARRIA10_PINMUX_FPGA_INTERFACE_ADDR (0xffd07400) +#define ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR (0xffd11000) +#define ARRIA10_SDR_SCHEDULER_ADDR (0xffd12400) +#define ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR (0xffd13000) +#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR (0xffd13200) +#define ARRIA10_SDR_FW_MPU_FPGA_ADDR (0xffd13300) +#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR (0xffd13400) +#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR (0xffd13500) +#define ARRIA10_DMANONSECURE_ADDR (0xffda0000) +#define ARRIA10_DMASECURE_ADDR (0xffda1000) +#define ARRIA10_MPUSCU_ADDR (0xffffc000) +#define ARRIA10_MPUL2_ADDR (0xfffff000) + +/* L2 cache controller */ +#define ARRIA10_MPUL2_ADRFLTR_START (ARRIA10_MPUL2_ADDR + 0xC00) + +/* NOC L4 Priv */ +#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV (ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x00) +#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV_SET (ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x04) +#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV_CLR (ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x08) + +/* NOC L4 Permissions */ +#define ARRIA10_NOC_FW_L4_PER_SCR_NAND_REG (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x00) +#define ARRIA10_NOC_FW_L4_PER_SCR_NAND_DATA (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x04) +#define ARRIA10_NOC_FW_L4_PER_SCR_QSPI_DATA (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x08) +#define ARRIA10_NOC_FW_L4_PER_SCR_USB0_REG (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x0c) +#define ARRIA10_NOC_FW_L4_PER_SCR_USB1_REG (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x10) +#define ARRIA10_NOC_FW_L4_PER_SCR_DMA_NONSECURE (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x14) +#define ARRIA10_NOC_FW_L4_PER_SCR_DMA_SECURE (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x18) +#define ARRIA10_NOC_FW_L4_PER_SCR_SPIM0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x1c) +#define ARRIA10_NOC_FW_L4_PER_SCR_SPIM1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x20) +#define ARRIA10_NOC_FW_L4_PER_SCR_SPIS0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x24) +#define ARRIA10_NOC_FW_L4_PER_SCR_SPIS1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x28) +#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x2c) +#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x30) +#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC2 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x34) +#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC3 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x38) +#define ARRIA10_NOC_FW_L4_PER_SCR_QSPI (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x3c) +#define ARRIA10_NOC_FW_L4_PER_SCR_SDMMC (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x40) +#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x44) +#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x48) +#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO2 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x4c) +#define ARRIA10_NOC_FW_L4_PER_SCR_I2C0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x50) +#define ARRIA10_NOC_FW_L4_PER_SCR_I2C1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x54) +#define ARRIA10_NOC_FW_L4_PER_SCR_I2C2 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x58) +#define ARRIA10_NOC_FW_L4_PER_SCR_I2C3 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x5c) +#define ARRIA10_NOC_FW_L4_PER_SCR_I2C4 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x60) +#define ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x64) +#define ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x68) +#define ARRIA10_NOC_FW_L4_PER_SCR_UART0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x6c) +#define ARRIA10_NOC_FW_L4_PER_SCR_UART1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x70) + +#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x00) +#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN_SET (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x04) +#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN_CLR (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x08) +#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION0 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x0c) +#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION1 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x10) +#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION2 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x14) +#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION3 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x18) +#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION4 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x1c) +#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION5 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x20) + +#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x00) +#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN_SET (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x04) +#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN_CLR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x08) +#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION0 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x0c) +#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION1 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x10) +#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION2 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x14) +#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION3 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x18) +#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION4 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x1c) +#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION5 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x20) +#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION6 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x24) +#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION7 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x28) +#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_GLOBAL (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x2c) + +#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_LWSOC2FPGA (ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR + 0x00) +#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_SOC2FPGA (ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR + 0x04) + +#endif diff --git a/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h new file mode 100644 index 0000000000..ebd2043426 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2014-2016 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ARRIA10_RESET_MANAGER_H_ +#define _ARRIA10_RESET_MANAGER_H_ + +#define ARRIA10_RSTMGR_STATUS 0x0 +#define ARRIA10_RSTMGR_RAMSTAT 0x4 +#define ARRIA10_RSTMGR_MISCSTAT 0x8 +#define ARRIA10_RSTMGR_CTRL 0xc +#define ARRIA10_RSTMGR_HDSKEN 0x10 +#define ARRIA10_RSTMGR_HDSKREQ 0x14 +#define ARRIA10_RSTMGR_HDSKACK 0x18 +#define ARRIA10_RSTMGR_COUNTS 0x1c +#define ARRIA10_RSTMGR_MPUMODRST 0x20 +#define ARRIA10_RSTMGR_PER0MODRST 0x24 +#define ARRIA10_RSTMGR_PER1MODRST 0x28 +#define ARRIA10_RSTMGR_BRGMODRST 0x2c +#define ARRIA10_RSTMGR_SYSMODRST 0x30 +#define ARRIA10_RSTMGR_COLDMODRST 0x34 +#define ARRIA10_RSTMGR_NRSTMODRST 0x38 +#define ARRIA10_RSTMGR_DBGMODRST 0x3c +#define ARRIA10_RSTMGR_MPUWARMMASK 0x40 +#define ARRIA10_RSTMGR_PER0WARMMASK 0x44 +#define ARRIA10_RSTMGR_PER1WARMMASK 0x48 +#define ARRIA10_RSTMGR_BRGWARMMASK 0x4c +#define ARRIA10_RSTMGR_SYSWARMMASK 0x50 +#define ARRIA10_RSTMGR_NRSTWARMMASK 0x54 +#define ARRIA10_RSTMGR_L3WARMMASK 0x58 +#define ARRIA10_RSTMGR_TSTSTA 0x5c +#define ARRIA10_RSTMGR_TSTSCRATCH 0x60 +#define ARRIA10_RSTMGR_HDSKTIMEOUT 0x64 +#define ARRIA10_RSTMGR_HMCINTR 0x68 +#define ARRIA10_RSTMGR_HMCINTREN 0x6c +#define ARRIA10_RSTMGR_HMCINTRENS 0x70 +#define ARRIA10_RSTMGR_HMCINTRENR 0x74 +#define ARRIA10_RSTMGR_HMCGPOUT 0x78 +#define ARRIA10_RSTMGR_HMCGPIN 0x7c + +#define ARRIA10_RSTMGR_CTL_SWWARMRSTREQ BIT(1) +#define ARRIA10_RSTMGR_PER0MODRST_EMAC0 BIT(0) +#define ARRIA10_RSTMGR_PER0MODRST_EMAC1 BIT(1) +#define ARRIA10_RSTMGR_PER0MODRST_EMAC2 BIT(2) +#define ARRIA10_RSTMGR_PER0MODRST_USB0 BIT(3) +#define ARRIA10_RSTMGR_PER0MODRST_USB1 BIT(4) +#define ARRIA10_RSTMGR_PER0MODRST_NAND BIT(5) +#define ARRIA10_RSTMGR_PER0MODRST_QSPI BIT(6) +#define ARRIA10_RSTMGR_PER0MODRST_SDMMC BIT(7) +#define ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP BIT(8) +#define ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP BIT(9) +#define ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP BIT(10) +#define ARRIA10_RSTMGR_PER0MODRST_USB0OCP BIT(11) +#define ARRIA10_RSTMGR_PER0MODRST_USB1OCP BIT(12) +#define ARRIA10_RSTMGR_PER0MODRST_NANDOCP BIT(13) +#define ARRIA10_RSTMGR_PER0MODRST_QSPIOCP BIT(14) +#define ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP BIT(15) +#define ARRIA10_RSTMGR_PER0MODRST_DMA BIT(16) +#define ARRIA10_RSTMGR_PER0MODRST_SPIM0 BIT(17) +#define ARRIA10_RSTMGR_PER0MODRST_SPIM1 BIT(18) +#define ARRIA10_RSTMGR_PER0MODRST_SPIS0 BIT(19) +#define ARRIA10_RSTMGR_PER0MODRST_SPIS1 BIT(20) +#define ARRIA10_RSTMGR_PER0MODRST_DMAOCP BIT(21) +#define ARRIA10_RSTMGR_PER0MODRST_EMACPTP BIT(22) +#define ARRIA10_RSTMGR_PER0MODRST_DMAIF0 BIT(24) +#define ARRIA10_RSTMGR_PER0MODRST_DMAIF1 BIT(25) +#define ARRIA10_RSTMGR_PER0MODRST_DMAIF2 BIT(26) +#define ARRIA10_RSTMGR_PER0MODRST_DMAIF3 BIT(27) +#define ARRIA10_RSTMGR_PER0MODRST_DMAIF4 BIT(28) +#define ARRIA10_RSTMGR_PER0MODRST_DMAIF5 BIT(29) +#define ARRIA10_RSTMGR_PER0MODRST_DMAIF6 BIT(30) +#define ARRIA10_RSTMGR_PER0MODRST_DMAIF7 BIT(31) + +#define ARRIA10_RSTMGR_PER1MODRST_WATCHDOG0 BIT(0) +#define ARRIA10_RSTMGR_PER1MODRST_WATCHDOG1 BIT(1) +#define ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER0 BIT(2) +#define ARRIA10_RSTMGR_PER1MODRST_L4SYSTIMER1 BIT(3) +#define ARRIA10_RSTMGR_PER1MODRST_SPTIMER0 BIT(4) +#define ARRIA10_RSTMGR_PER1MODRST_SPTIMER1 BIT(5) +#define ARRIA10_RSTMGR_PER1MODRST_I2C0 BIT(8) +#define ARRIA10_RSTMGR_PER1MODRST_I2C1 BIT(9) +#define ARRIA10_RSTMGR_PER1MODRST_I2C2 BIT(10) +#define ARRIA10_RSTMGR_PER1MODRST_I2C3 BIT(11) +#define ARRIA10_RSTMGR_PER1MODRST_I2C4 BIT(12) +#define ARRIA10_RSTMGR_PER1MODRST_UART0 BIT(16) +#define ARRIA10_RSTMGR_PER1MODRST_UART1 BIT(17) +#define ARRIA10_RSTMGR_PER1MODRST_GPIO0 BIT(24) +#define ARRIA10_RSTMGR_PER1MODRST_GPIO1 BIT(25) +#define ARRIA10_RSTMGR_PER1MODRST_GPIO2 BIT(26) + +#define ARRIA10_RSTMGR_BRGMODRST_HPS2FPGA BIT(0) +#define ARRIA10_RSTMGR_BRGMODRST_LWHPS2FPGA BIT(1) +#define ARRIA10_RSTMGR_BRGMODRST_FPGA2HPS BIT(2) +#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM0 BIT(3) +#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM1 BIT(4) +#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM2 BIT(5) +#define ARRIA10_RSTMGR_BRGMODRST_DDRSCH BIT(6) + +#define ARRIA10_RSTMGR_OCP_MASK (ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP | \ + ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP | \ + ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP | \ + ARRIA10_RSTMGR_PER0MODRST_NANDOCP | \ + ARRIA10_RSTMGR_PER0MODRST_QSPIOCP | \ + ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP) + +void arria10_reset_peripherals(void); +void arria10_reset_deassert_dedicated_peripherals(void); +void arria10_reset_deassert_shared_peripherals(void); +void arria10_reset_deassert_fpga_peripherals(void); + +#endif + diff --git a/arch/arm/mach-socfpga/include/mach/arria10-sdram.h b/arch/arm/mach-socfpga/include/mach/arria10-sdram.h new file mode 100644 index 0000000000..07e4dd0130 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/arria10-sdram.h @@ -0,0 +1,353 @@ +/* + * Copyright (C) 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <mach/arria10-system-manager.h> + +#ifndef _ARRIA10_SDRAM_H_ +#define _ARRIA10_SDRAM_H_ + +#define ARRIA10_ECC_HMC_OCP_IP_REV_ID (ARRIA10_SDR_ADDR + 0x00) +#define ARRIA10_ECC_HMC_OCP_DDRIOCTRL (ARRIA10_SDR_ADDR + 0x08) +#define ARRIA10_ECC_HMC_OCP_DDRCALSTAT (ARRIA10_SDR_ADDR + 0x0c) +#define ARRIA10_ECC_HMC_OCP_MPR_OBEAT1 (ARRIA10_SDR_ADDR + 0x10) +#define ARRIA10_ECC_HMC_OCP_MPR_1BEAT1 (ARRIA10_SDR_ADDR + 0x14) +#define ARRIA10_ECC_HMC_OCP_MPR_2BEAT1 (ARRIA10_SDR_ADDR + 0x18) +#define ARRIA10_ECC_HMC_OCP_MPR_3BEAT1 (ARRIA10_SDR_ADDR + 0x1c) +#define ARRIA10_ECC_HMC_OCP_MPR_4BEAT1 (ARRIA10_SDR_ADDR + 0x20) +#define ARRIA10_ECC_HMC_OCP_MPR_5BEAT1 (ARRIA10_SDR_ADDR + 0x24) +#define ARRIA10_ECC_HMC_OCP_MPR_6BEAT1 (ARRIA10_SDR_ADDR + 0x28) +#define ARRIA10_ECC_HMC_OCP_MPR_7BEAT1 (ARRIA10_SDR_ADDR + 0x2c) +#define ARRIA10_ECC_HMC_OCP_MPR_8BEAT1 (ARRIA10_SDR_ADDR + 0x30) +#define ARRIA10_ECC_HMC_OCP_MPR_OBEAT2 (ARRIA10_SDR_ADDR + 0x34) +#define ARRIA10_ECC_HMC_OCP_MPR_1BEAT2 (ARRIA10_SDR_ADDR + 0x38) +#define ARRIA10_ECC_HMC_OCP_MPR_2BEAT2 (ARRIA10_SDR_ADDR + 0x3c) +#define ARRIA10_ECC_HMC_OCP_MPR_3BEAT2 (ARRIA10_SDR_ADDR + 0x40) +#define ARRIA10_ECC_HMC_OCP_MPR_4BEAT2 (ARRIA10_SDR_ADDR + 0x44) +#define ARRIA10_ECC_HMC_OCP_MPR_5BEAT2 (ARRIA10_SDR_ADDR + 0x48) +#define ARRIA10_ECC_HMC_OCP_MPR_6BEAT2 (ARRIA10_SDR_ADDR + 0x4c) +#define ARRIA10_ECC_HMC_OCP_MPR_7BEAT2 (ARRIA10_SDR_ADDR + 0x50) +#define ARRIA10_ECC_HMC_OCP_MPR_8BEAT2 (ARRIA10_SDR_ADDR + 0x54) +#define ARRIA10_ECC_HMC_OCP_MPR_AUTO_PRECHARGE (ARRIA10_SDR_ADDR + 0x60) +#define ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL1 (ARRIA10_SDR_ADDR + 0x100) +#define ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL2 (ARRIA10_SDR_ADDR + 0x104) +#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTEN (ARRIA10_SDR_ADDR + 0x110) +#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTENS (ARRIA10_SDR_ADDR + 0x114) +#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTENR (ARRIA10_SDR_ADDR + 0x118) +#define ARRIA10_ECC_HMC_OCP_MPR_INTMODE (ARRIA10_SDR_ADDR + 0x11c) +#define ARRIA10_ECC_HMC_OCP_MPR_INTSTAT (ARRIA10_SDR_ADDR + 0x120) +#define ARRIA10_ECC_HMC_OCP_MPR_DIAGINTTEST (ARRIA10_SDR_ADDR + 0x124) +#define ARRIA10_ECC_HMC_OCP_MPR_MODSTAT (ARRIA10_SDR_ADDR + 0x128) +#define ARRIA10_ECC_HMC_OCP_MPR_DERRADDRA (ARRIA10_SDR_ADDR + 0x12c) +#define ARRIA10_ECC_HMC_OCP_MPR_SERRADDRA (ARRIA10_SDR_ADDR + 0x130) +#define ARRIA10_ECC_HMC_OCP_MPR_AUTOWB_CORRADDR (ARRIA10_SDR_ADDR + 0x138) +#define ARRIA10_ECC_HMC_OCP_MPR_SERRCNTREG (ARRIA10_SDR_ADDR + 0x13c) +#define ARRIA10_ECC_HMC_OCP_MPR_AUTOWB_DROP_CNTREG (ARRIA10_SDR_ADDR + 0x140) +#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2WRECCDATABUS (ARRIA10_SDR_ADDR + 0x144) +#define ARRIA10_ECC_HMC_OCP_MPR_ECC_RDECCDATA2REGBUS (ARRIA10_SDR_ADDR + 0x148) +#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDECCDATABUS (ARRIA10_SDR_ADDR + 0x14c) +#define ARRIA10_ECC_HMC_OCP_MPR_ECC_DIAGON (ARRIA10_SDR_ADDR + 0x150) +#define ARRIA10_ECC_HMC_OCP_MPR_ECC_DECSTAT (ARRIA10_SDR_ADDR + 0x154) +#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_0 (ARRIA10_SDR_ADDR + 0x160) +#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_1 (ARRIA10_SDR_ADDR + 0x164) +#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_2 (ARRIA10_SDR_ADDR + 0x168) +#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_3 (ARRIA10_SDR_ADDR + 0x16c) +#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT0 (ARRIA10_SDR_ADDR + 0x170) +#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT1 (ARRIA10_SDR_ADDR + 0x174) +#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT2 (ARRIA10_SDR_ADDR + 0x178) +#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT3 (ARRIA10_SDR_ADDR + 0x17c) + +#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ID_COREID (ARRIA10_SDR_SCHEDULER_ADDR + 0x00) +#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ID_REVISIONID (ARRIA10_SDR_SCHEDULER_ADDR + 0x04) +#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRCONF (ARRIA10_SDR_SCHEDULER_ADDR + 0x08) +#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRTIMING (ARRIA10_SDR_SCHEDULER_ADDR + 0x0c) +#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRMODE (ARRIA10_SDR_SCHEDULER_ADDR + 0x10) +#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_READLATENCY (ARRIA10_SDR_SCHEDULER_ADDR + 0x14) +#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ACTIVATE (ARRIA10_SDR_SCHEDULER_ADDR + 0x38) +#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DEVTODEV (ARRIA10_SDR_SCHEDULER_ADDR + 0x3c) + +#define ARRIA10_IO48_HMC_MMR_DBGCFG0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x00) +#define ARRIA10_IO48_HMC_MMR_DBGCFG1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x04) +#define ARRIA10_IO48_HMC_MMR_DBGCFG2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x08) +#define ARRIA10_IO48_HMC_MMR_DBGCFG3 (ARRIA10_HMC_MMR_IO48_ADDR + 0x0c) +#define ARRIA10_IO48_HMC_MMR_DBGCFG4 (ARRIA10_HMC_MMR_IO48_ADDR + 0x10) +#define ARRIA10_IO48_HMC_MMR_DBGCFG5 (ARRIA10_HMC_MMR_IO48_ADDR + 0x14) +#define ARRIA10_IO48_HMC_MMR_DBGCFG6 (ARRIA10_HMC_MMR_IO48_ADDR + 0x18) +#define ARRIA10_IO48_HMC_MMR_RESERVE0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x1c) +#define ARRIA10_IO48_HMC_MMR_RESERVE1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x20) +#define ARRIA10_IO48_HMC_MMR_RESERVE2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x24) +#define ARRIA10_IO48_HMC_MMR_CTRLCFG0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x28) +#define ARRIA10_IO48_HMC_MMR_CTRLCFG1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x2c) +#define ARRIA10_IO48_HMC_MMR_CTRLCFG2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x30) +#define ARRIA10_IO48_HMC_MMR_CTRLCFG3 (ARRIA10_HMC_MMR_IO48_ADDR + 0x34) +#define ARRIA10_IO48_HMC_MMR_CTRLCFG4 (ARRIA10_HMC_MMR_IO48_ADDR + 0x38) +#define ARRIA10_IO48_HMC_MMR_CTRLCFG5 (ARRIA10_HMC_MMR_IO48_ADDR + 0x3c) +#define ARRIA10_IO48_HMC_MMR_CTRLCFG6 (ARRIA10_HMC_MMR_IO48_ADDR + 0x40) +#define ARRIA10_IO48_HMC_MMR_CTRLCFG7 (ARRIA10_HMC_MMR_IO48_ADDR + 0x44) +#define ARRIA10_IO48_HMC_MMR_CTRLCFG8 (ARRIA10_HMC_MMR_IO48_ADDR + 0x48) +#define ARRIA10_IO48_HMC_MMR_CTRLCFG9 (ARRIA10_HMC_MMR_IO48_ADDR + 0x4c) +#define ARRIA10_IO48_HMC_MMR_DRAMTIMING0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x50) +#define ARRIA10_IO48_HMC_MMR_DRAMODT0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x54) +#define ARRIA10_IO48_HMC_MMR_DRAMODT1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x58) +#define ARRIA10_IO48_HMC_MMR_SBCFG0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x5c) +#define ARRIA10_IO48_HMC_MMR_SBCFG1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x60) +#define ARRIA10_IO48_HMC_MMR_SBCFG2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x64) +#define ARRIA10_IO48_HMC_MMR_SBCFG3 (ARRIA10_HMC_MMR_IO48_ADDR + 0x68) +#define ARRIA10_IO48_HMC_MMR_SBCFG4 (ARRIA10_HMC_MMR_IO48_ADDR + 0x6c) +#define ARRIA10_IO48_HMC_MMR_SBCFG5 (ARRIA10_HMC_MMR_IO48_ADDR + 0x70) +#define ARRIA10_IO48_HMC_MMR_SBCFG6 (ARRIA10_HMC_MMR_IO48_ADDR + 0x74) +#define ARRIA10_IO48_HMC_MMR_SBCFG7 (ARRIA10_HMC_MMR_IO48_ADDR + 0x78) +#define ARRIA10_IO48_HMC_MMR_CALTIMING0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x7c) +#define ARRIA10_IO48_HMC_MMR_CALTIMING1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x80) +#define ARRIA10_IO48_HMC_MMR_CALTIMING2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x84) +#define ARRIA10_IO48_HMC_MMR_CALTIMING3 (ARRIA10_HMC_MMR_IO48_ADDR + 0x88) +#define ARRIA10_IO48_HMC_MMR_CALTIMING4 (ARRIA10_HMC_MMR_IO48_ADDR + 0x8c) +#define ARRIA10_IO48_HMC_MMR_CALTIMING5 (ARRIA10_HMC_MMR_IO48_ADDR + 0x90) +#define ARRIA10_IO48_HMC_MMR_CALTIMING6 (ARRIA10_HMC_MMR_IO48_ADDR + 0x94) +#define ARRIA10_IO48_HMC_MMR_CALTIMING7 (ARRIA10_HMC_MMR_IO48_ADDR + 0x98) +#define ARRIA10_IO48_HMC_MMR_CALTIMING8 (ARRIA10_HMC_MMR_IO48_ADDR + 0x9c) +#define ARRIA10_IO48_HMC_MMR_CALTIMING9 (ARRIA10_HMC_MMR_IO48_ADDR + 0xa0) +#define ARRIA10_IO48_HMC_MMR_CALTIMING10 (ARRIA10_HMC_MMR_IO48_ADDR + 0xa4) +#define ARRIA10_IO48_HMC_MMR_DRAMADDRW (ARRIA10_HMC_MMR_IO48_ADDR + 0xa8) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND0 (ARRIA10_HMC_MMR_IO48_ADDR + 0xac) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND1 (ARRIA10_HMC_MMR_IO48_ADDR + 0xb0) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND2 (ARRIA10_HMC_MMR_IO48_ADDR + 0xb4) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND3 (ARRIA10_HMC_MMR_IO48_ADDR + 0xb8) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND4 (ARRIA10_HMC_MMR_IO48_ADDR + 0xbc) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND5 (ARRIA10_HMC_MMR_IO48_ADDR + 0xc0) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND6 (ARRIA10_HMC_MMR_IO48_ADDR + 0xc4) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND7 (ARRIA10_HMC_MMR_IO48_ADDR + 0xc8) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND8 (ARRIA10_HMC_MMR_IO48_ADDR + 0xcc) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND9 (ARRIA10_HMC_MMR_IO48_ADDR + 0xd0) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND10 (ARRIA10_HMC_MMR_IO48_ADDR + 0xd4) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND11 (ARRIA10_HMC_MMR_IO48_ADDR + 0xd8) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND12 (ARRIA10_HMC_MMR_IO48_ADDR + 0xdc) +#define ARRIA10_IO48_HMC_MMR_SIDEBANB13 (ARRIA10_HMC_MMR_IO48_ADDR + 0xe0) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND14 (ARRIA10_HMC_MMR_IO48_ADDR + 0xe4) +#define ARRIA10_IO48_HMC_MMR_SIDEBAND15 (ARRIA10_HMC_MMR_IO48_ADDR + 0xe8) +#define ARRIA10_IO48_HMC_MMR_DRAMSTS (ARRIA10_HMC_MMR_IO48_ADDR + 0xec) +#define ARRIA10_IO48_HMC_MMR_DBGDONE (ARRIA10_HMC_MMR_IO48_ADDR + 0xf0) +#define ARRIA10_IO48_HMC_MMR_DBGSIGNALS (ARRIA10_HMC_MMR_IO48_ADDR + 0xf4) +#define ARRIA10_IO48_HMC_MMR_DBGRESET (ARRIA10_HMC_MMR_IO48_ADDR + 0xf8) +#define ARRIA10_IO48_HMC_MMR_DBGMATCH (ARRIA10_HMC_MMR_IO48_ADDR + 0xfc) +#define ARRIA10_IO48_HMC_MMR_COUNTER0MASK (ARRIA10_HMC_MMR_IO48_ADDR + 0x100) +#define ARRIA10_IO48_HMC_MMR_COUNTER1MASK (ARRIA10_HMC_MMR_IO48_ADDR + 0x104) +#define ARRIA10_IO48_HMC_MMR_COUNTER0MATCH (ARRIA10_HMC_MMR_IO48_ADDR + 0x108) +#define ARRIA10_IO48_HMC_MMR_COUNTER1MATCH (ARRIA10_HMC_MMR_IO48_ADDR + 0x10c) +#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x110) +#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x114) +#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x118) + +union dramaddrw_reg { + struct { + u32 cfg_col_addr_width:5; + u32 cfg_row_addr_width:5; + u32 cfg_bank_addr_width:4; + u32 cfg_bank_group_addr_width:2; + u32 cfg_cs_addr_width:3; + u32 reserved:13; + }; + u32 word; +}; + +union ctrlcfg0_reg { + struct { + u32 cfg_mem_type:4; + u32 cfg_dimm_type:3; + u32 cfg_ac_pos:2; + u32 cfg_ctrl_burst_len:5; + u32 reserved:18; /* Other fields unused */ + }; + u32 word; +}; + +union ctrlcfg1_reg { + struct { + u32 cfg_dbc3_burst_len:5; + u32 cfg_addr_order:2; + u32 cfg_ctrl_enable_ecc:1; + u32 reserved:24; /* Other fields unused */ + }; + u32 word; +}; + +union caltiming0_reg { + struct { + u32 cfg_act_to_rdwr:6; + u32 cfg_act_to_pch:6; + u32 cfg_act_to_act:6; + u32 cfg_act_to_act_db:6; + u32 reserved:8; /* Other fields unused */ + }; + u32 word; +}; + +union caltiming1_reg { + struct { + u32 cfg_rd_to_rd:6; + u32 cfg_rd_to_rd_dc:6; + u32 cfg_rd_to_rd_db:6; + u32 cfg_rd_to_wr:6; + u32 cfg_rd_to_wr_dc:6; + u32 reserved:2; + }; + u32 word; +}; + +union caltiming2_reg { + struct { + u32 cfg_rd_to_wr_db:6; + u32 cfg_rd_to_pch:6; + u32 cfg_rd_ap_to_valid:6; + u32 cfg_wr_to_wr:6; + u32 cfg_wr_to_wr_dc:6; + u32 reserved:2; + }; + u32 word; +}; + +union caltiming3_reg { + struct { + u32 cfg_wr_to_wr_db:6; + u32 cfg_wr_to_rd:6; + u32 cfg_wr_to_rd_dc:6; + u32 cfg_wr_to_rd_db:6; + u32 cfg_wr_to_pch:6; + u32 reserved:2; + }; + u32 word; +}; + +union caltiming4_reg { + struct { + u32 cfg_wr_ap_to_valid:6; + u32 cfg_pch_to_valid:6; + u32 cfg_pch_all_to_valid:6; + u32 cfg_arf_to_valid:8; + u32 cfg_pdn_to_valid:6; + }; + u32 word; +}; + +union caltiming9_reg { + struct { + u32 cfg_4_act_to_act:8; + u32 reserved:24; + }; + u32 word; +}; + +#define IRQ_ECC_SERR 34 +#define IRQ_ECC_DERR 32 + +#define ARRIA10_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE 0x00000001 + +#define ARRIA10_ECC_HMC_OCP_INTSTAT_SERRPENA 0x00000001 +#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERRPENA 0x00000002 +#define ARRIA10_ECC_HMC_OCP_ERRINTEN_SERRINTEN 0x00000001 +#define ARRIA10_ECC_HMC_OCP_ERRINTEN_DERRINTEN 0x00000002 +#define ARRIA10_ECC_HMC_OCP_INTMOD_INTONCMP 0x00010000 +#define ARRIA10_ECC_HMC_OCP_INTMOD_SERR 0x00000001 +#define ARRIA10_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY 0x00000100 +#define ARRIA10_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST 0x00010000 +#define ARRIA10_ECC_HMC_OCP_ECCCTL_CNT_RST 0x00000100 +#define ARRIA10_ECC_HMC_OCP_ECCCTL_ECC_EN 0x00000000 +#define ARRIA10_ECC_HMC_OCP_ECCCTL2_RMW_EN 0x00000100 +#define ARRIA10_ECC_HMC_OCP_ECCCTL2_AWB_EN 0x00000001 +#define ARRIA10_ECC_HMC_OCP_ERRINTEN_SERR 0x00000001 +#define ARRIA10_ECC_HMC_OCP_ERRINTEN_DERR 0x00000002 +#define ARRIA10_ECC_HMC_OCP_ERRINTEN_HMI 0x00000004 +#define ARRIA10_ECC_HMC_OCP_INTSTAT_SERR 0x00000001 +#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERR 0x00000002 +#define ARRIA10_ECC_HMC_OCP_INTSTAT_HMI 0x00000004 +#define ARRIA10_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG 0x00010000 +#define ARRIA10_ECC_HMC_OCP_INTSTAT_ADDRPARFLG 0x00020000 +#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERRBUSFLG 0x00040000 + +#define ARRIA10_ECC_HMC_OCP_SERRCNTREG_VALUE 8 + +#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 22 +#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB 0 +#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB 0 +#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB 2 +#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB 6 +#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB 15 +#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB 0 + +#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB 0 +#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB 0 + +#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB 4 +#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB 13 +#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB 4 + +#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB 4 +#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB 6 +#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB 6 + +#define ARRIA10_SDR_FW_MPU_FPGA_EN (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x00) +#define ARRIA10_SDR_FW_MPU_FPGA_EN_SET (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x04) +#define ARRIA10_SDR_FW_MPU_FPGA_EN_CLR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x08) +#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION0ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x10) +#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION1ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x14) +#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION2ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x18) +#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x1c) +#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x20) +#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x24) +#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION2ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x28) +#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x2c) +#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x30) +#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x34) +#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION2ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x38) +#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x3c) +#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x40) +#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x44) +#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION2ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x48) +#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION3ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x4c) + +#define ARRIA10_NOC_FW_DDR_MPU_MPUREG0EN BIT(0) +#define ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN BIT(1) +#define ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN BIT(2) +#define ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN BIT(3) +#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG0EN BIT(4) +#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG1EN BIT(5) +#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG2EN BIT(6) +#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG3EN BIT(7) +#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG0EN BIT(8) +#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG1EN BIT(9) +#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG2EN BIT(10) +#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG3EN BIT(11) +#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG0EN BIT(12) +#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG1EN BIT(13) +#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG2EN BIT(14) +#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG3EN BIT(15) + +#define ARRIA10_NOC_FW_DDR_L3_EN (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x00) +#define ARRIA10_NOC_FW_DDR_L3_EN_SET (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x04) +#define ARRIA10_NOC_FW_DDR_L3_EN_CLR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x08) +#define ARRIA10_NOC_FW_DDR_L3_HPSREGION0ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x0c) +#define ARRIA10_NOC_FW_DDR_L3_HPSREGION1ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x10) +#define ARRIA10_NOC_FW_DDR_L3_HPSREGION2ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x14) +#define ARRIA10_NOC_FW_DDR_L3_HPSREGION3ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x18) +#define ARRIA10_NOC_FW_DDR_L3_HPSREGION4ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x1c) +#define ARRIA10_NOC_FW_DDR_L3_HPSREGION5ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x20) +#define ARRIA10_NOC_FW_DDR_L3_HPSREGION6ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x24) +#define ARRIA10_NOC_FW_DDR_L3_HPSREGION7ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x28) +#define ARRIA10_NOC_FW_DDR_L3_GLOBAL (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x2c) + +#define ARRIA10_NOC_FW_DDR_L3_HPSREG0EN BIT(0) +#define ARRIA10_NOC_FW_DDR_L3_HPSREG1EN BIT(1) +#define ARRIA10_NOC_FW_DDR_L3_HPSREG2EN BIT(2) +#define ARRIA10_NOC_FW_DDR_L3_HPSREG3EN BIT(3) +#define ARRIA10_NOC_FW_DDR_L3_HPSREG4EN BIT(4) +#define ARRIA10_NOC_FW_DDR_L3_HPSREG5EN BIT(5) +#define ARRIA10_NOC_FW_DDR_L3_HPSREG6EN BIT(6) +#define ARRIA10_NOC_FW_DDR_L3_HPSREG7EN BIT(7) + +#define ARRIA10_IO48_DRAMTIME_MEM_READ_LATENCY 0x0000003f + +int arria10_ddr_calibration_sequence(void); + +#endif diff --git a/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h new file mode 100644 index 0000000000..f98cc36c76 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2014-2016 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ARRIA10_SYSTEM_MANAGER_H_ +#define _ARRIA10_SYSTEM_MANAGER_H_ + +#include <mach/arria10-regs.h> + +#define ARRIA10_SYSMGR_SILICONID1 (ARRIA10_SYSMGR_ADDR + 0x00) +#define ARRIA10_SYSMGR_SILICONID2 (ARRIA10_SYSMGR_ADDR + 0x04) +#define ARRIA10_SYSMGR_WDDBG (ARRIA10_SYSMGR_ADDR + 0x08) +#define ARRIA10_SYSMGR_BOOTINFO (ARRIA10_SYSMGR_ADDR + 0x0c) +#define ARRIA10_SYSMGR_MPU_CTRL_L2_ECC (ARRIA10_SYSMGR_ADDR + 0x10) +#define ARRIA10_SYSMGR_DMA (ARRIA10_SYSMGR_ADDR + 0x20) +#define ARRIA10_SYSMGR_DMA_PERIPH (ARRIA10_SYSMGR_ADDR + 0x24) +#define ARRIA10_SYSMGR_SDMMC (ARRIA10_SYSMGR_ADDR + 0x28) +#define ARRIA10_SYSMGR_SDMMC_L3MASTER (ARRIA10_SYSMGR_ADDR + 0x2c) +#define ARRIA10_SYSMGR_NAND_BOOTSTRAP (ARRIA10_SYSMGR_ADDR + 0x30) +#define ARRIA10_SYSMGR_NAND_L3MASTER (ARRIA10_SYSMGR_ADDR + 0x34) +#define ARRIA10_SYSMGR_USB0_L3MASTER (ARRIA10_SYSMGR_ADDR + 0x38) +#define ARRIA10_SYSMGR_USB1_L3MASTER (ARRIA10_SYSMGR_ADDR + 0x3c) +#define ARRIA10_SYSMGR_EMAC_GLOBAL (ARRIA10_SYSMGR_ADDR + 0x40) +#define ARRIA10_SYSMGR_EMAC0 (ARRIA10_SYSMGR_ADDR + 0x44) +#define ARRIA10_SYSMGR_EMAC1 (ARRIA10_SYSMGR_ADDR + 0x48) +#define ARRIA10_SYSMGR_EMAC2 (ARRIA10_SYSMGR_ADDR + 0x4c) +#define ARRIA10_SYSMGR_FPGAINTF_GLOBAL (ARRIA10_SYSMGR_ADDR + 0x60) +#define ARRIA10_SYSMGR_FPGAINTF_EN_0 (ARRIA10_SYSMGR_ADDR + 0x64) +#define ARRIA10_SYSMGR_FPGAINTF_EN_1 (ARRIA10_SYSMGR_ADDR + 0x68) +#define ARRIA10_SYSMGR_FPGAINTF_EN_2 (ARRIA10_SYSMGR_ADDR + 0x6c) +#define ARRIA10_SYSMGR_FPGAINTF_EN_3 (ARRIA10_SYSMGR_ADDR + 0x70) +#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE (ARRIA10_SYSMGR_ADDR + 0x80) +#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_SET (ARRIA10_SYSMGR_ADDR + 0x84) +#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_CLEAR (ARRIA10_SYSMGR_ADDR + 0x88) +#define ARRIA10_SYSMGR_ECC_INTMASK_VALUE (ARRIA10_SYSMGR_ADDR + 0x90) +#define ARRIA10_SYSMGR_ECC_INTMASK_SET (ARRIA10_SYSMGR_ADDR + 0x94) +#define ARRIA10_SYSMGR_ECC_INTMASK_CLR (ARRIA10_SYSMGR_ADDR + 0x98) +#define ARRIA10_SYSMGR_ECC_INTSTATUS_SERR (ARRIA10_SYSMGR_ADDR + 0x9c) +#define ARRIA10_SYSMGR_ECC_INTSTATUS_DERR (ARRIA10_SYSMGR_ADDR + 0xa0) +#define ARRIA10_SYSMGR_MPU_STATUS_L2_ECC (ARRIA10_SYSMGR_ADDR + 0xa4) +#define ARRIA10_SYSMGR_MPU_CLEAR_L2_ECC (ARRIA10_SYSMGR_ADDR + 0xa8) +#define ARRIA10_SYSMGR_MPU_STATUS_L1_PARITY (ARRIA10_SYSMGR_ADDR + 0xac) +#define ARRIA10_SYSMGR_MPU_CLEAR_L1_PARITY (ARRIA10_SYSMGR_ADDR + 0xb0) +#define ARRIA10_SYSMGR_MPU_SET_L1_PARITY (ARRIA10_SYSMGR_ADDR + 0xb4) +#define ARRIA10_SYSMGR_NOC_TIMEOUT (ARRIA10_SYSMGR_ADDR + 0xc0) +#define ARRIA10_SYSMGR_NOC_IDLEREQ_SET (ARRIA10_SYSMGR_ADDR + 0xc4) +#define ARRIA10_SYSMGR_NOC_IDLEREQ_CLR (ARRIA10_SYSMGR_ADDR + 0xc8) +#define ARRIA10_SYSMGR_NOC_IDLEREQ_VALUE (ARRIA10_SYSMGR_ADDR + 0xcc) +#define ARRIA10_SYSMGR_NOC_IDLEACK (ARRIA10_SYSMGR_ADDR + 0xd0) +#define ARRIA10_SYSMGR_NOC_IDLESTATUS (ARRIA10_SYSMGR_ADDR + 0xd4) +#define ARRIA10_SYSMGR_FPGA2SOC_CTRL (ARRIA10_SYSMGR_ADDR + 0xd8) + +/* pin mux */ +#define ARRIA10_SYSMGR_PINMUXGRP (ARRIA10_SYSMGR_ADDR + 0x400) +#define ARRIA10_SYSMGR_PINMUXGRP_NANDUSEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x2F0) +#define ARRIA10_SYSMGR_PINMUXGRP_EMAC1USEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x2F8) +#define ARRIA10_SYSMGR_PINMUXGRP_SDMMCUSEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x308) +#define ARRIA10_SYSMGR_PINMUXGRP_EMAC0USEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x314) +#define ARRIA10_SYSMGR_PINMUXGRP_SPIM1USEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x330) +#define ARRIA10_SYSMGR_PINMUXGRP_SPIM0USEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x338) + +/* bit fields */ +#define ARRIA10_SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) +#define ARRIA10_SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) +#define ARRIA10_SYSMGR_ECC_OCRAM_EN BIT(0) +#define ARRIA10_SYSMGR_ECC_OCRAM_SERR BIT(3) +#define ARRIA10_SYSMGR_ECC_OCRAM_DERR BIT(4) +#define ARRIA10_SYSMGR_FPGAINTF_USEFPGA BIT(1) +#define ARRIA10_SYSMGR_FPGAINTF_SPIM0 BIT(0) +#define ARRIA10_SYSMGR_FPGAINTF_SPIM1 BIT(1) +#define ARRIA10_SYSMGR_FPGAINTF_EMAC0 BIT(2) +#define ARRIA10_SYSMGR_FPGAINTF_EMAC1 BIT(3) +#define ARRIA10_SYSMGR_FPGAINTF_NAND BIT(4) +#define ARRIA10_SYSMGR_FPGAINTF_SDMMC BIT(5) + +#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 +#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_LSB 0 +#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003 + +#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0 BIT(0) +#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0_SW BIT(4) +#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1 BIT(8) +#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1_SW BIT(12) +#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2 BIT(16) +#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2_SW BIT(20) + +#define ARRIA10_SYSMGR_SDMMC_SMPLSEL(smplsel) (((smplsel) & 0x7) << 4) +#define ARRIA10_SYSMGR_SDMMC_DRVSEL(drvsel) ((drvsel) & 0x7) + +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((drvsel << 0) & 0x7) | ((smplsel << 4) & 0x70) + +#endif diff --git a/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h b/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h new file mode 100644 index 0000000000..28fb1c92fc --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/barebox-arm-head.h @@ -0,0 +1,42 @@ +static inline void __barebox_arm_head(void) +{ + __asm__ __volatile__ ( +#ifdef CONFIG_THUMB2_BAREBOX + ".arm\n" + "adr r9, 1f + 1\n" + "bx r9\n" + ".thumb\n" + "1:\n" + "bl 2f\n" + ".rept 10\n" + "1: b 1b\n" + ".endr\n" +#else + "b 2f\n" + "1: b 1b\n" + "1: b 1b\n" + "1: b 1b\n" + "1: b 1b\n" + "1: b 1b\n" + "1: b 1b\n" + "1: b 1b\n" +#endif + ".asciz \"barebox\"\n" + ".word _text\n" /* text base. If copied there, + * barebox can skip relocation + */ + ".word _barebox_image_size\n" /* image size to copy */ + + ".rept 10\n" + ".word 0x55555555\n" + ".endr\n" + "2:\n" + ); +} +static inline void barebox_arm_head(void) +{ + __barebox_arm_head(); + __asm__ __volatile__ ( + "b barebox_arm_reset_vector\n" + ); +} diff --git a/arch/arm/mach-socfpga/include/mach/clock-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-clock-manager.h index 45800de79a..797aa5d3cf 100644 --- a/arch/arm/mach-socfpga/include/mach/clock-manager.h +++ b/arch/arm/mach-socfpga/include/mach/cyclone5-clock-manager.h @@ -15,8 +15,8 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef _CLOCK_MANAGER_H_ -#define _CLOCK_MANAGER_H_ +#ifndef _CLOCK_MANAGER_CYCLONE5_H_ +#define _CLOCK_MANAGER_CYCLONE5_H_ struct socfpga_cm_config { /* main group */ @@ -197,4 +197,4 @@ void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg); CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \ CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) -#endif /* _CLOCK_MANAGER_H_ */ +#endif diff --git a/arch/arm/mach-socfpga/include/mach/freeze-controller.h b/arch/arm/mach-socfpga/include/mach/cyclone5-freeze-controller.h index 4253f5b38f..93ce5152ed 100644 --- a/arch/arm/mach-socfpga/include/mach/freeze-controller.h +++ b/arch/arm/mach-socfpga/include/mach/cyclone5-freeze-controller.h @@ -15,10 +15,10 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef _FREEZE_CONTROLLER_H_ -#define _FREEZE_CONTROLLER_H_ +#ifndef _CYCLONE5_FREEZE_CONTROLLER_H_ +#define _CYCLONE5_FREEZE_CONTROLLER_H_ -#include <mach/socfpga-regs.h> +#include <mach/cyclone5-regs.h> #define SYSMGR_FRZCTRL_ADDRESS 0x40 #define SYSMGR_FRZCTRL_VIOCTRL_ADDRESS 0x40 diff --git a/arch/arm/mach-socfpga/include/mach/socfpga-regs.h b/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h index e88daf7189..e88daf7189 100644 --- a/arch/arm/mach-socfpga/include/mach/socfpga-regs.h +++ b/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h diff --git a/arch/arm/mach-socfpga/include/mach/reset-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-reset-manager.h index 899401ce3c..899401ce3c 100644 --- a/arch/arm/mach-socfpga/include/mach/reset-manager.h +++ b/arch/arm/mach-socfpga/include/mach/cyclone5-reset-manager.h diff --git a/arch/arm/mach-socfpga/include/mach/scan-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-scan-manager.h index 568bedfde1..df720a7e08 100644 --- a/arch/arm/mach-socfpga/include/mach/scan-manager.h +++ b/arch/arm/mach-socfpga/include/mach/cyclone5-scan-manager.h @@ -19,7 +19,7 @@ #define _SCAN_MANAGER_H_ #include <io.h> -#include <mach/socfpga-regs.h> +#include <mach/cyclone5-regs.h> /*********************************************************** * * diff --git a/arch/arm/mach-socfpga/include/mach/sdram_config.h b/arch/arm/mach-socfpga/include/mach/cyclone5-sdram-config.h index 2af797a920..a19a837994 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_config.h +++ b/arch/arm/mach-socfpga/include/mach/cyclone5-sdram-config.h @@ -1,9 +1,9 @@ #ifndef __MACH_SDRAM_CONFIG_H #define __MACH_SDRAM_CONFIG_H -#include <mach/sdram.h> -#include <mach/socfpga-regs.h> -#include <mach/system-manager.h> +#include <mach/cyclone5-sdram.h> +#include <mach/cyclone5-regs.h> +#include <mach/cyclone5-system-manager.h> static inline void sdram_write(unsigned register_offset, unsigned val) { diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/cyclone5-sdram.h index ebd331e83e..ebd331e83e 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram.h +++ b/arch/arm/mach-socfpga/include/mach/cyclone5-sdram.h diff --git a/arch/arm/mach-socfpga/include/mach/sequencer.c b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c index d2338e6406..e5ecb0f1b8 100644 --- a/arch/arm/mach-socfpga/include/mach/sequencer.c +++ b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c @@ -26,11 +26,9 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "sequencer_defines.h" - #include "system.h" #include "sdram_io.h" -#include "sequencer.h" +#include "cyclone5-sequencer.h" #include "tclrpt.h" /****************************************************************************** @@ -57,7 +55,7 @@ asm(".global __alt_stack_pointer"); asm("__alt_stack_pointer = " STRINGIFY(STACK_POINTER)); #endif -#include <mach/sdram.h> +#include <mach/cyclone5-sdram.h> #define NEWVERSION_RDDESKEW 1 #define NEWVERSION_WRDESKEW 1 diff --git a/arch/arm/mach-socfpga/include/mach/sequencer.h b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.h index dd0378af34..d2da21d13f 100644 --- a/arch/arm/mach-socfpga/include/mach/sequencer.h +++ b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.h @@ -369,7 +369,7 @@ static const uint32_t ac_rom_init[]; /* parameter variable holder */ -typedef struct param_type { +typedef struct sequencer_param_type { t_btfld dm_correct_mask; t_btfld read_correct_mask; t_btfld read_correct_mask_vg; diff --git a/arch/arm/mach-socfpga/include/mach/system-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h index 9efc37a4dc..9efc37a4dc 100644 --- a/arch/arm/mach-socfpga/include/mach/system-manager.h +++ b/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h diff --git a/arch/arm/mach-socfpga/include/mach/debug_ll.h b/arch/arm/mach-socfpga/include/mach/debug_ll.h index f378435970..f41258c504 100644 --- a/arch/arm/mach-socfpga/include/mach/debug_ll.h +++ b/arch/arm/mach-socfpga/include/mach/debug_ll.h @@ -2,24 +2,33 @@ #define __MACH_DEBUG_LL_H__ #include <io.h> +#include <errno.h> -#define UART_BASE 0xffc02000 +#ifdef CONFIG_DEBUG_LL +#define UART_BASE CONFIG_DEBUG_SOCFPGA_UART_PHYS_ADDR +#endif #define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LSR (5 << 2) -#define THR (0 << 2) +#define LSR_TEMT 0x40 #define LCR_BKSE 0x80 /* Bank select enable */ -#define LSR (5 << 2) -#define THR (0 << 2) -#define DLL (0 << 2) -#define IER (1 << 2) -#define DLM (1 << 2) -#define FCR (2 << 2) -#define LCR (3 << 2) -#define MCR (4 << 2) -#define MDR (8 << 2) +#define LCRVAL 0x3 +#define MCRVAL 0x3 +#define FCRVAL 0xc1 + +#define RBR 0x0 +#define DLL 0x0 +#define IER 0x4 +#define DLM 0x4 +#define FCR 0x8 +#define LCR 0xc +#define MCR 0x10 +#define LSR 0x14 +#define MSR 0x18 +#define SCR 0x1c +#define THR 0x30 +#ifdef CONFIG_DEBUG_LL static inline unsigned int ns16550_calc_divisor(unsigned int clk, unsigned int baudrate) { @@ -28,21 +37,33 @@ static inline unsigned int ns16550_calc_divisor(unsigned int clk, static inline void INIT_LL(void) { - unsigned int clk = 100000000; - unsigned int divisor = clk / 16 / 115200; - - writeb(0x00, UART_BASE + LCR); - writeb(0x00, UART_BASE + IER); - writeb(0x07, UART_BASE + MDR); - writeb(LCR_BKSE, UART_BASE + LCR); - writeb(divisor & 0xff, UART_BASE + DLL); - writeb(divisor >> 8, UART_BASE + DLM); - writeb(0x03, UART_BASE + LCR); - writeb(0x03, UART_BASE + MCR); - writeb(0x07, UART_BASE + FCR); - writeb(0x00, UART_BASE + MDR); + unsigned int div = ns16550_calc_divisor(CONFIG_DEBUG_SOCFPGA_UART_CLOCK, + 115200); + + while ((readl(UART_BASE + LSR) & LSR_TEMT) == 0); + + writel(0x00, UART_BASE + IER); + + writel(LCR_BKSE, UART_BASE + LCR); + writel(div & 0xff, UART_BASE + DLL); + writel((div >> 8) & 0xff, UART_BASE + DLM); + writel(LCRVAL, UART_BASE + LCR); + + writel(MCRVAL, UART_BASE + MCR); + writel(FCRVAL, UART_BASE + FCR); } +#ifdef CONFIG_ARCH_SOCFPGA_ARRIA10 +static inline void PUTC_LL(char c) +{ + /* Wait until there is space in the FIFO */ + while ((readl(UART_BASE + LSR) & LSR_THRE) == 0); + /* Send the character */ + writel(c, UART_BASE + THR); + /* Wait to make sure it hits the line, in case we die too soon. */ + while ((readl(UART_BASE + LSR) & LSR_THRE) == 0); +} +#else static inline void PUTC_LL(char c) { /* Wait until there is space in the FIFO */ @@ -53,3 +74,13 @@ static inline void PUTC_LL(char c) while ((readb(UART_BASE + LSR) & LSR_THRE) == 0); } #endif + +#else +static inline unsigned int ns16550_calc_divisor(unsigned int clk, + unsigned int baudrate) { + return -ENOSYS; +} +static inline void INIT_LL(void) {} +static inline void PUTC_LL(char c) {} +#endif +#endif diff --git a/arch/arm/mach-socfpga/include/mach/generic.h b/arch/arm/mach-socfpga/include/mach/generic.h index 2a7e0ea499..9d6dd1f26c 100644 --- a/arch/arm/mach-socfpga/include/mach/generic.h +++ b/arch/arm/mach-socfpga/include/mach/generic.h @@ -1,13 +1,49 @@ #ifndef __MACH_SOCFPGA_GENERIC_H #define __MACH_SOCFPGA_GENERIC_H +#include <linux/types.h> + struct socfpga_cm_config; struct socfpga_io_config; +struct arria10_mainpll_cfg; +struct arria10_perpll_cfg; +struct arria10_pinmux_cfg; + +void arria10_init(struct arria10_mainpll_cfg *mainpll, + struct arria10_perpll_cfg *perpll, uint32_t *pinmux); + void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config, struct socfpga_io_config *io_config); +#if defined(CONFIG_ARCH_SOCFPGA_CYCLONE5) +void socfpga_cyclone5_mmc_init(void); +void socfpga_cyclone5_uart_init(void); +void socfpga_cyclone5_timer_init(void); +void socfpga_cyclone5_qspi_init(void); +#else +static inline void socfpga_cyclone5_mmc_init(void) +{ + return; +} + +static inline void socfpga_cyclone5_uart_init(void) +{ + return; +} + +static inline void socfpga_cyclone5_timer_init(void) +{ + return; +} + +static inline void socfpga_cyclone5_qspi_init(void) +{ + return; +} +#endif + static inline void __udelay(unsigned us) { volatile unsigned int i; diff --git a/arch/arm/mach-socfpga/include/mach/pll_config.h b/arch/arm/mach-socfpga/include/mach/pll_config.h index bb491d82f1..1a7e851eda 100644 --- a/arch/arm/mach-socfpga/include/mach/pll_config.h +++ b/arch/arm/mach-socfpga/include/mach/pll_config.h @@ -1,5 +1,5 @@ -#include <mach/clock-manager.h> +#include <mach/cyclone5-clock-manager.h> static struct socfpga_cm_config cm_default_cfg = { /* main group */ diff --git a/arch/arm/mach-socfpga/include/mach/sdram_io.h b/arch/arm/mach-socfpga/include/mach/sdram_io.h index 62698000f6..ef87bdaf63 100755..100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_io.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_io.h @@ -26,7 +26,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include <mach/sdram.h> +#include <mach/cyclone5-sdram.h> #define MGR_SELECT_MASK 0xf8000 diff --git a/arch/arm/mach-socfpga/include/mach/sequencer_defines.h b/arch/arm/mach-socfpga/include/mach/sequencer_defines.h deleted file mode 100644 index 5059844106..0000000000 --- a/arch/arm/mach-socfpga/include/mach/sequencer_defines.h +++ /dev/null @@ -1,6 +0,0 @@ -#define TINIT_CNTR1_VAL 32 -#define TINIT_CNTR2_VAL 32 -#define TINIT_CNTR0_VAL 99 -#define TRESET_CNTR1_VAL 99 -#define TRESET_CNTR2_VAL 10 -#define TRESET_CNTR0_VAL 99 diff --git a/arch/arm/mach-socfpga/include/mach/system.h b/arch/arm/mach-socfpga/include/mach/system.h index 89527b2c2b..89527b2c2b 100755..100644 --- a/arch/arm/mach-socfpga/include/mach/system.h +++ b/arch/arm/mach-socfpga/include/mach/system.h diff --git a/arch/arm/mach-socfpga/include/mach/tclrpt.h b/arch/arm/mach-socfpga/include/mach/tclrpt.h index 4345b23ba6..6b332c8754 100755..100644 --- a/arch/arm/mach-socfpga/include/mach/tclrpt.h +++ b/arch/arm/mach-socfpga/include/mach/tclrpt.h @@ -28,7 +28,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "sequencer.h" +#include "cyclone5-sequencer.h" #define TCLRPT_SET(item, value) diff --git a/arch/arm/mach-socfpga/nic301.c b/arch/arm/mach-socfpga/nic301.c index 206dd48ff9..7069c6e5b9 100644 --- a/arch/arm/mach-socfpga/nic301.c +++ b/arch/arm/mach-socfpga/nic301.c @@ -18,7 +18,7 @@ #include <common.h> #include <io.h> #include <mach/nic301.h> -#include <mach/socfpga-regs.h> +#include <mach/cyclone5-regs.h> /* * Convert all slave from secure to non secure diff --git a/arch/arm/mach-socfpga/xload.c b/arch/arm/mach-socfpga/xload.c index d24944bbb8..ee7d194427 100644 --- a/arch/arm/mach-socfpga/xload.c +++ b/arch/arm/mach-socfpga/xload.c @@ -1,8 +1,5 @@ -#include <platform_data/cadence_qspi.h> -#include <platform_data/dw_mmc.h> #include <bootsource.h> #include <bootstrap.h> -#include <platform_data/serial-ns16550.h> #include <common.h> #include <malloc.h> #include <init.h> @@ -10,15 +7,14 @@ #include <linux/sizes.h> #include <fs.h> #include <io.h> -#include <mci.h> #include <linux/clkdev.h> #include <linux/stat.h> #include <linux/clk.h> #include <mach/generic.h> -#include <mach/system-manager.h> -#include <mach/socfpga-regs.h> +#include <mach/cyclone5-system-manager.h> +#include <mach/cyclone5-regs.h> static struct socfpga_barebox_part default_parts[] = { { @@ -30,84 +26,6 @@ static struct socfpga_barebox_part default_parts[] = { }; const struct socfpga_barebox_part *barebox_parts = default_parts; -enum socfpga_clks { - timer, mmc, qspi_clk, uart, clk_max -}; - -static struct clk *clks[clk_max]; - -static struct dw_mmc_platform_data mmc_pdata = { - .bus_width_caps = MMC_CAP_4_BIT_DATA, - .ciu_div = 3, -}; - -static void socfpga_mmc_init(void) -{ - clks[mmc] = clk_fixed("mmc", 400000000); - clkdev_add_physbase(clks[mmc], CYCLONE5_SDMMC_ADDRESS, NULL); - add_generic_device("dw_mmc", 0, NULL, CYCLONE5_SDMMC_ADDRESS, SZ_4K, - IORESOURCE_MEM, &mmc_pdata); -} - -#if defined(CONFIG_SPI_CADENCE_QUADSPI) -static struct cadence_qspi_platform_data qspi_pdata = { - .ext_decoder = 0, - .fifo_depth = 128, -}; - -static __maybe_unused void add_cadence_qspi_device(int id, resource_size_t ctrl, - resource_size_t data, void *pdata) -{ - struct resource *res; - - res = xzalloc(sizeof(struct resource) * 2); - res[0].start = ctrl; - res[0].end = ctrl + 0x100 - 1; - res[0].flags = IORESOURCE_MEM; - res[1].start = data; - res[1].end = data + 0x100 - 1; - res[1].flags = IORESOURCE_MEM; - - add_generic_device_res("cadence_qspi", id, res, 2, pdata); -} - -static __maybe_unused void socfpga_qspi_init(void) -{ - clks[qspi_clk] = clk_fixed("qspi_clk", 370000000); - clkdev_add_physbase(clks[qspi_clk], CYCLONE5_QSPI_CTRL_ADDRESS, NULL); - clkdev_add_physbase(clks[qspi_clk], CYCLONE5_QSPI_DATA_ADDRESS, NULL); - add_cadence_qspi_device(0, CYCLONE5_QSPI_CTRL_ADDRESS, - CYCLONE5_QSPI_DATA_ADDRESS, &qspi_pdata); -} -#else -static void socfpga_qspi_init(void) -{ - return; -} -#endif - -static struct NS16550_plat uart_pdata = { - .clock = 100000000, - .shift = 2, -}; - -static void socfpga_uart_init(void) -{ - clks[uart] = clk_fixed("uart", 100000000); - clkdev_add_physbase(clks[uart], CYCLONE5_UART0_ADDRESS, NULL); - clkdev_add_physbase(clks[uart], CYCLONE5_UART1_ADDRESS, NULL); - add_ns16550_device(0, 0xffc02000, 1024, IORESOURCE_MEM | - IORESOURCE_MEM_8BIT, &uart_pdata); -} - -static void socfpga_timer_init(void) -{ - clks[timer] = clk_fixed("timer", 200000000); - clkdev_add_physbase(clks[timer], CYCLONE5_SMP_TWD_ADDRESS, NULL); - add_generic_device("smp_twd", 0, NULL, CYCLONE5_SMP_TWD_ADDRESS, 0x100, - IORESOURCE_MEM, NULL); -} - static __noreturn int socfpga_xload(void) { enum bootsource bootsource = bootsource_get(); @@ -116,7 +34,7 @@ static __noreturn int socfpga_xload(void) switch (bootsource) { case BOOTSOURCE_MMC: - socfpga_mmc_init(); + socfpga_cyclone5_mmc_init(); for (part = barebox_parts; part->mmc_disk; part++) { buf = bootstrap_read_disk(barebox_parts->mmc_disk, "fat"); @@ -132,8 +50,7 @@ static __noreturn int socfpga_xload(void) } break; case BOOTSOURCE_SPI: - socfpga_qspi_init(); - + socfpga_cyclone5_qspi_init(); for (part = barebox_parts; part->nor_size; part++) { buf = bootstrap_read_devfs("mtd0", false, part->nor_offset, part->nor_size, SZ_1M); @@ -142,7 +59,6 @@ static __noreturn int socfpga_xload(void) part->nor_offset); continue; } - break; } @@ -167,8 +83,8 @@ static __noreturn int socfpga_xload(void) static int socfpga_devices_init(void) { barebox_set_model("SoCFPGA"); - socfpga_timer_init(); - socfpga_uart_init(); + socfpga_cyclone5_timer_init(); + socfpga_cyclone5_uart_init(); barebox_main = socfpga_xload; diff --git a/arch/ppc/boards/pcm030/eeprom.c b/arch/ppc/boards/pcm030/eeprom.c index aa00f361cd..34bce85b94 100644 --- a/arch/ppc/boards/pcm030/eeprom.c +++ b/arch/ppc/boards/pcm030/eeprom.c @@ -53,7 +53,7 @@ static void pcm030_read_factory_data(const struct pcm030_eeprom *buf) continue; board = xstrndup(&buf->product[u], l); u += l + 1; - globalvar_add_simple("model.type", board); + globalvar_add_simple_string_fixed("model.type", board); free(board); } @@ -62,7 +62,7 @@ static void pcm030_read_factory_data(const struct pcm030_eeprom *buf) continue; serial = xstrndup(&buf->product[u], l); u += l + 1; - globalvar_add_simple("model.serial", serial); + globalvar_add_simple_string_fixed("model.serial", serial); free(serial); } diff --git a/commands/basename.c b/commands/basename.c index 028b0e0f24..c1a28e9e1d 100644 --- a/commands/basename.c +++ b/commands/basename.c @@ -27,7 +27,7 @@ static int do_basename(int argc, char *argv[]) if (argc != 3) return COMMAND_ERROR_USAGE; - setenv(argv[2], basename(argv[1])); + setenv(argv[2], posix_basename(argv[1])); return 0; } diff --git a/commands/cp.c b/commands/cp.c index 4f1c068dd6..54934dd64f 100644 --- a/commands/cp.c +++ b/commands/cp.c @@ -76,7 +76,8 @@ static int do_cp(int argc, char *argv[]) for (i = optind; i < argc - 1; i++) { char *dst; - dst = concat_path_file(argv[argc - 1], basename(argv[i])); + + dst = concat_path_file(argv[argc - 1], posix_basename(argv[i])); if (recursive) ret = copy_recursive(argv[i], dst); diff --git a/commands/devinfo.c b/commands/devinfo.c index 9d5e8b86eb..cd69d2e5f8 100644 --- a/commands/devinfo.c +++ b/commands/devinfo.c @@ -103,7 +103,8 @@ static int do_devinfo(int argc, char *argv[]) printf("Parameters:\n"); first = false; } - printf(" %s: %s", param->name, dev_get_param(dev, param->name)); + printf(" %s: %s (type: %s)", param->name, dev_get_param(dev, param->name), + get_param_type(param)); if (param->info) { param->info(param); } diff --git a/commands/spd_decode.c b/commands/spd_decode.c index 2bedcf05c5..08b9589622 100644 --- a/commands/spd_decode.c +++ b/commands/spd_decode.c @@ -59,5 +59,6 @@ BAREBOX_CMD_START(spd_decode) .cmd = do_spd_decode, BAREBOX_CMD_DESC("Decode SPD EEPROM") BAREBOX_CMD_OPTS("FILE") + BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP) BAREBOX_CMD_HELP(cmd_spd_decode_help) BAREBOX_CMD_END diff --git a/common/Kconfig b/common/Kconfig index 8dd40db2c0..bc7cb0fe76 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -101,6 +101,7 @@ config BAREBOX_UPDATE_IMX_NAND_FCB depends on BAREBOX_UPDATE depends on MTD_WRITE depends on NAND_MXS + select BCH if ARCH_IMX6 default y config UBIFORMAT @@ -1122,6 +1123,21 @@ config DEBUG_ROCKCHIP_UART Say Y here if you want kernel low-level debugging support on RK3XXX. +config DEBUG_SOCFPGA_UART0 + bool "Use SOCFPGA UART0 for low-level debug" + depends on ARCH_SOCFPGA + help + Say Y here if you want kernel low-level debugging support + on SOCFPGA(Cyclone 5 and Arria 5) based platforms. + +config DEBUG_SOCFPGA_UART1 + bool "Use SOCFPGA UART1 for low-level debug" + depends on ARCH_SOCFPGA + help + Say Y here if you want kernel low-level debugging support + on SOCFPGA(Arria 10) based platforms. + + endchoice config DEBUG_IMX_UART_PORT @@ -1164,6 +1180,20 @@ config DEBUG_ROCKCHIP_UART_PORT Choose UART port on which kernel low-level debug messages should be output. +config DEBUG_SOCFPGA_UART_PHYS_ADDR + hex "Physical base address of debug UART" if DEBUG_LL + default 0xffc02000 if DEBUG_SOCFPGA_UART0 + default 0xffc02100 if DEBUG_SOCFPGA_UART1 + depends on ARCH_SOCFPGA + +config DEBUG_SOCFPGA_UART_CLOCK + int "SoCFPGA UART debug clock" if DEBUG_LL + default 100000000 if ARCH_SOCFPGA_CYCLONE5 + default 50000000 if ARCH_SOCFPGA_ARRIA10 + depends on ARCH_SOCFPGA + help + Choose UART root clock. + config DEBUG_INITCALLS bool "Trace initcalls" help diff --git a/common/boot.c b/common/boot.c index cef3d5e514..a2d27d1593 100644 --- a/common/boot.c +++ b/common/boot.c @@ -123,7 +123,7 @@ void boot_set_watchdog_timeout(unsigned int timeout) static int init_boot_watchdog_timeout(void) { - return globalvar_add_simple_int("boot.watchdog_timeout", + return globalvar_add_simple_uint32("boot.watchdog_timeout", &boot_watchdog_timeout, "%u"); } late_initcall(init_boot_watchdog_timeout); diff --git a/common/bootchooser.c b/common/bootchooser.c index 455f290fa2..f6d99d130b 100644 --- a/common/bootchooser.c +++ b/common/bootchooser.c @@ -907,8 +907,8 @@ static int bootchooser_init(void) globalvar_add_simple_bool("bootchooser.retry", &retry); globalvar_add_simple_string("bootchooser.targets", &available_targets); globalvar_add_simple_string("bootchooser.state_prefix", &state_prefix); - globalvar_add_simple_int("bootchooser.default_attempts", &global_default_attempts, "%u"); - globalvar_add_simple_int("bootchooser.default_priority", &global_default_priority, "%u"); + globalvar_add_simple_uint32("bootchooser.default_attempts", &global_default_attempts, "%u"); + globalvar_add_simple_uint32("bootchooser.default_priority", &global_default_priority, "%u"); globalvar_add_simple_bitmask("bootchooser.reset_attempts", &reset_attempts, reset_attempts_names, ARRAY_SIZE(reset_attempts_names)); globalvar_add_simple_bitmask("bootchooser.reset_priorities", &reset_priorities, diff --git a/common/bootm.c b/common/bootm.c index 81625d9157..92cfeb6c32 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -668,7 +668,7 @@ static int bootm_init(void) if (IS_ENABLED(CONFIG_BOOTM_FORCE_SIGNED_IMAGES)) bootm_verify_mode = BOOTM_VERIFY_SIGNATURE; - globalvar_add_simple_int("bootm.verbose", &bootm_verbosity, "%u"); + globalvar_add_simple_uint32("bootm.verbose", &bootm_verbosity, "%u"); globalvar_add_simple_enum("bootm.verify", (unsigned int *)&bootm_verify_mode, bootm_verify_names, ARRAY_SIZE(bootm_verify_names)); diff --git a/common/console.c b/common/console.c index 74fb684b2c..f4c799fa54 100644 --- a/common/console.c +++ b/common/console.c @@ -94,7 +94,7 @@ int console_close(struct console_device *cdev) int console_set_active(struct console_device *cdev, unsigned flag) { - int ret, i; + int ret; if (!cdev->getc) flag &= ~CONSOLE_STDIN; @@ -119,18 +119,6 @@ int console_set_active(struct console_device *cdev, unsigned flag) cdev->f_active = flag; - if (IS_ENABLED(CONFIG_PARAMETER)) { - i = 0; - - if (flag & CONSOLE_STDIN) - cdev->active[i++] = 'i'; - if (flag & CONSOLE_STDOUT) - cdev->active[i++] = 'o'; - if (flag & CONSOLE_STDERR) - cdev->active[i++] = 'e'; - cdev->active[i] = 0; - } - if (initialized < CONSOLE_INIT_FULL) { char ch; initialized = CONSOLE_INIT_FULL; @@ -150,30 +138,39 @@ unsigned console_get_active(struct console_device *cdev) return cdev->f_active; } -static int console_active_set(struct device_d *dev, struct param_d *param, - const char *val) +static int console_active_set(struct param_d *param, void *priv) { - struct console_device *cdev = to_console_dev(dev); + struct console_device *cdev = priv; unsigned int flag = 0; + int ret; - if (val) { - if (strchr(val, 'i')) + if (cdev->active_string) { + if (strchr(cdev->active_string, 'i')) flag |= CONSOLE_STDIN; - if (strchr(val, 'o')) + if (strchr(cdev->active_string, 'o')) flag |= CONSOLE_STDOUT; - if (strchr(val, 'e')) + if (strchr(cdev->active_string, 'e')) flag |= CONSOLE_STDERR; } - return console_set_active(cdev, flag); + ret = console_set_active(cdev, flag); + if (ret) + return ret; + + return 0; } -static const char *console_active_get(struct device_d *dev, - struct param_d *param) +static int console_active_get(struct param_d *param, void *priv) { - struct console_device *cdev = to_console_dev(dev); + struct console_device *cdev = priv; + unsigned int flag = cdev->f_active; - return cdev->active; + free(cdev->active_string); + cdev->active_string = basprintf("%s%s%s", + flag & CONSOLE_STDIN ? "i" : "", + flag & CONSOLE_STDOUT ? "o" : "", + flag & CONSOLE_STDERR ? "e" : ""); + return 0; } int console_set_baudrate(struct console_device *cdev, unsigned baudrate) @@ -331,7 +328,7 @@ int console_register(struct console_device *newcdev) if (ret) return ret; newcdev->baudrate_param = newcdev->baudrate = CONFIG_BAUDRATE; - dev_add_param_int(dev, "baudrate", console_baudrate_set, + dev_add_param_uint32(dev, "baudrate", console_baudrate_set, NULL, &newcdev->baudrate_param, "%u", newcdev); } @@ -340,7 +337,8 @@ int console_register(struct console_device *newcdev) newcdev->open_count = 0; - dev_add_param(dev, "active", console_active_set, console_active_get, 0); + dev_add_param_string(dev, "active", console_active_set, console_active_get, + &newcdev->active_string, newcdev); if (IS_ENABLED(CONFIG_CONSOLE_ACTIVATE_FIRST)) { if (list_empty(&console_list)) diff --git a/common/console_common.c b/common/console_common.c index d051458de4..b36b3ff083 100644 --- a/common/console_common.c +++ b/common/console_common.c @@ -148,10 +148,10 @@ int dev_printf(int level, const struct device_d *dev, const char *format, ...) static int loglevel_init(void) { if (IS_ENABLED(CONFIG_LOGBUF)) - globalvar_add_simple_int("log_max_messages", - &barebox_log_max_messages, "%d"); + globalvar_add_simple_uint32("log_max_messages", + &barebox_log_max_messages, "%u"); - return globalvar_add_simple_int("loglevel", &barebox_loglevel, "%d"); + return globalvar_add_simple_uint32("loglevel", &barebox_loglevel, "%u"); } device_initcall(loglevel_init); diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 499ec93c28..9c33cc2c95 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1753,7 +1753,6 @@ void *calloc(size_t n, size_t elem_size) /* Utility to update current_mallinfo for malloc_stats and mallinfo() */ -#ifdef CONFIG_CMD_MEMINFO static void malloc_update_mallinfo(void) { int i; @@ -1821,8 +1820,6 @@ void malloc_stats(void) #endif } -#endif /* CONFIG_CMD_MEMINFO */ - /* History: diff --git a/common/dummy_malloc.c b/common/dummy_malloc.c index dd36a5b156..641baa125a 100644 --- a/common/dummy_malloc.c +++ b/common/dummy_malloc.c @@ -24,6 +24,10 @@ #include <common.h> #include <malloc.h> +void malloc_stats(void) +{ +} + void *memalign(size_t alignment, size_t bytes) { unsigned long mem = (unsigned long)sbrk(bytes + alignment); diff --git a/common/globalvar.c b/common/globalvar.c index 1ecf5134af..1385559fd7 100644 --- a/common/globalvar.c +++ b/common/globalvar.c @@ -19,7 +19,7 @@ struct device_d global_device = { .id = DEVICE_ID_SINGLE, }; -struct device_d nv_device = { +static struct device_d nv_device = { .name = "nv", .id = DEVICE_ID_SINGLE, }; @@ -166,7 +166,7 @@ static int nvvar_device_dispatch(const char *name, struct device_d **dev, return 1; } -static int nv_set(struct device_d *dev, struct param_d *p, const char *val) +static int nv_set(struct param_d *p, const char *val) { struct param_d *g; int ret; @@ -187,16 +187,16 @@ static int nv_set(struct device_d *dev, struct param_d *p, const char *val) return 0; } -static const char *nv_param_get(struct device_d *dev, struct param_d *p) +static const char *nv_param_get(struct param_d *p) { return p->value ? p->value : ""; } -static int nv_param_set(struct device_d *dev, struct param_d *p, const char *val) +static int nv_param_set(struct param_d *p, const char *val) { int ret; - ret = nv_set(dev, p, val); + ret = nv_set(p, val); if (ret) return ret; @@ -219,7 +219,7 @@ static int __nvvar_add(const char *name, const char *value) } if (value) - return nv_set(&nv_device, p, value); + return nv_set(p, value); value = dev_get_param(&global_device, name); if (value) { @@ -373,7 +373,7 @@ void globalvar_set_match(const char *match, const char *val) } } -static int globalvar_simple_set(struct device_d *dev, struct param_d *p, const char *val) +static int globalvar_simple_set(struct param_d *p, const char *val) { struct device_d *rdev; const char *pname = NULL; @@ -391,7 +391,7 @@ static int globalvar_simple_set(struct device_d *dev, struct param_d *p, const c } /* Pass to the generic function we have overwritten */ - return dev_param_set_generic(dev, p, val); + return dev_param_set_generic(p, val); } static void globalvar_nv_sync(const char *name) @@ -430,7 +430,7 @@ int globalvar_add_simple(const char *name, const char *value) return 0; } -int globalvar_add_simple_string(const char *name, char **value) +int __globalvar_add_simple_string(const char *name, char **value) { struct param_d *p; @@ -445,28 +445,14 @@ int globalvar_add_simple_string(const char *name, char **value) return 0; } -int globalvar_add_simple_int(const char *name, int *value, - const char *format) +int __globalvar_add_simple_int(const char *name, void *value, + enum param_type type, + const char *format) { struct param_d *p; - p = dev_add_param_int(&global_device, name, NULL, NULL, - value, format, NULL); - - if (IS_ERR(p)) - return PTR_ERR(p); - - globalvar_nv_sync(name); - - return 0; -} - -int globalvar_add_simple_bool(const char *name, int *value) -{ - struct param_d *p; - - p = dev_add_param_bool(&global_device, name, NULL, NULL, - value, NULL); + p = __dev_add_param_int(&global_device, name, NULL, NULL, + value, type, format, NULL); if (IS_ERR(p)) return PTR_ERR(p); @@ -528,7 +514,7 @@ static int globalvar_init(void) if (IS_ENABLED(CONFIG_NVVAR)) register_device(&nv_device); - globalvar_add_simple("version", UTS_RELEASE); + globalvar_add_simple_string_fixed("version", UTS_RELEASE); return 0; } diff --git a/common/imx-bbu-nand-fcb.c b/common/imx-bbu-nand-fcb.c index 34a5f83230..5d3d3f7e93 100644 --- a/common/imx-bbu-nand-fcb.c +++ b/common/imx-bbu-nand-fcb.c @@ -33,9 +33,12 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/stat.h> +#include <linux/bch.h> +#include <linux/bitops.h> #include <io.h> #include <crc.h> #include <mach/generic.h> +#include <mach/imx6.h> #include <mtd/mtd-peb.h> struct dbbt_block { @@ -129,6 +132,132 @@ static uint8_t calculate_parity_13_8(uint8_t d) return p; } +static uint8_t reverse_bit(uint8_t b) +{ + b = (b & 0xf0) >> 4 | (b & 0x0f) << 4; + b = (b & 0xcc) >> 2 | (b & 0x33) << 2; + b = (b & 0xaa) >> 1 | (b & 0x55) << 1; + + return b; +} + +static void encode_bch_ecc(void *buf, struct fcb_block *fcb, int eccbits) +{ + int i, j, m = 13; + int blocksize = 128; + int numblocks = 8; + int ecc_buf_size = (m * eccbits + 7) / 8; + struct bch_control *bch = init_bch(m, eccbits, 0); + uint8_t *ecc_buf = xmalloc(ecc_buf_size); + uint8_t *tmp_buf = xzalloc(blocksize * numblocks); + uint8_t *psrc, *pdst; + + /* + * The blocks here are bit aligned. If eccbits is a multiple of 8, + * we just can copy bytes. Otherwiese we must move the blocks to + * the next free bit position. + */ + BUG_ON(eccbits % 8); + + memcpy(tmp_buf, fcb, sizeof(*fcb)); + + for (i = 0; i < numblocks; i++) { + memset(ecc_buf, 0, ecc_buf_size); + psrc = tmp_buf + i * blocksize; + pdst = buf + i * (blocksize + ecc_buf_size); + + /* copy data byte aligned to destination buf */ + memcpy(pdst, psrc, blocksize); + + /* + * imx-kobs use a modified encode_bch which reverse the + * bit order of the data before calculating bch. + * Do this in the buffer and use the bch lib here. + */ + for (j = 0; j < blocksize; j++) + psrc[j] = reverse_bit(psrc[j]); + + encode_bch(bch, psrc, blocksize, ecc_buf); + + /* reverse ecc bit */ + for (j = 0; j < ecc_buf_size; j++) + ecc_buf[j] = reverse_bit(ecc_buf[j]); + + /* Here eccbuf is byte aligned and we can just copy it */ + memcpy(pdst + blocksize, ecc_buf, ecc_buf_size); + } + + free(ecc_buf); + free(tmp_buf); + free_bch(bch); +} + +struct fcb_block *read_fcb_bch(void *rawpage, int eccbits) +{ + int i, j, ret, errbit, m = 13; + int blocksize = 128; + int numblocks = 8; + int ecc_buf_size = (m * eccbits + 7) / 8; + struct bch_control *bch = init_bch(m, eccbits, 0); + uint8_t *fcb = xmalloc(numblocks * blocksize); + uint8_t *ecc_buf = xmalloc(ecc_buf_size); + uint8_t *data_buf = xmalloc(blocksize); + unsigned int *errloc = xmalloc(eccbits * sizeof(*errloc)); + uint8_t *psrc, *pdst; + + /* see encode_bch_ecc */ + BUG_ON(eccbits % 8); + + for (i = 0; i < numblocks; i++) { + psrc = rawpage + 32 + i * (blocksize + ecc_buf_size); + pdst = fcb + i * blocksize; + + /* reverse data bit */ + for (j = 0; j < blocksize; j++) + data_buf[j] = reverse_bit(psrc[j]); + + /* reverse ecc bit */ + for (j = 0; j < ecc_buf_size; j++) + ecc_buf[j] = reverse_bit(psrc[j + blocksize]); + + ret = decode_bch(bch, data_buf, blocksize, ecc_buf, + NULL, NULL, errloc); + + if (ret < 0) { + pr_err("Uncorrectable error at block %d\n", i); + free(fcb); + fcb = ERR_PTR(ret); + goto out; + } + if (ret > 0) + pr_info("Found %d correctable errors in block %d\n", + ret, i); + + for (j = 0; j < ret; j++) { + /* + * calculate the reverse position + * pos - (pos % 8) -> byte offset + * 7 - (pos % 8) -> reverse bit position + */ + errbit = errloc[j] - 2 * (errloc[j] % 8) + 7; + pr_debug("Found error: bit %d in block %d\n", + errbit, i); + if (errbit < blocksize * 8) + change_bit(errbit, psrc); + /* else error in ecc, ignore it */ + } + memcpy(pdst, psrc, blocksize); + } + +out: + free(data_buf); + free(ecc_buf); + free(errloc); + free_bch(bch); + + return (struct fcb_block *)fcb; +} + static void encode_hamming_13_8(void *_src, void *_ecc, size_t size) { int i; @@ -312,7 +441,11 @@ static int read_fcb(struct mtd_info *mtd, int num, struct fcb_block **retfcb) goto err; } - fcb = read_fcb_hamming_13_8(rawpage); + if (cpu_is_mx6ul()) + fcb = read_fcb_bch(rawpage, 40); + else + fcb = read_fcb_hamming_13_8(rawpage); + if (IS_ERR(fcb)) { pr_err("Cannot read fcb\n"); ret = PTR_ERR(fcb); @@ -766,8 +899,14 @@ static int imx_bbu_write_fcbs_dbbts(struct mtd_info *mtd, struct fcb_block *fcb) fcb_raw_page = xzalloc(mtd->writesize + mtd->oobsize); - memcpy(fcb_raw_page + 12, fcb, sizeof(struct fcb_block)); - encode_hamming_13_8(fcb_raw_page + 12, fcb_raw_page + 12 + 512, 512); + if (cpu_is_mx6ul()) { + /* 40 bit BCH, for i.MX6UL */ + encode_bch_ecc(fcb_raw_page + 32, fcb, 40); + } else { + memcpy(fcb_raw_page + 12, fcb, sizeof(struct fcb_block)); + encode_hamming_13_8(fcb_raw_page + 12, + fcb_raw_page + 12 + 512, 512); + } dbbt = dbbt_data_create(mtd); diff --git a/common/partitions/dos.c b/common/partitions/dos.c index 5f08e253ee..91b5399079 100644 --- a/common/partitions/dos.c +++ b/common/partitions/dos.c @@ -251,7 +251,7 @@ static void dos_partition(void *buf, struct block_device *blk, * signature and pp is a zero-filled hex representation of the 1-based * partition number. */ - dev_add_param_int(blk->dev, "nt_signature", + dev_add_param_uint32(blk->dev, "nt_signature", dos_set_disk_signature, dos_get_disk_signature, &dsp->signature, "%08x", dsp); } diff --git a/common/password.c b/common/password.c index 74d328f4b2..5e6bfc53e7 100644 --- a/common/password.c +++ b/common/password.c @@ -443,7 +443,7 @@ static int login_global_init(void) { login_fail_command = xstrdup("boot"); - globalvar_add_simple_int("login.timeout", &login_timeout, "%d"); + globalvar_add_simple_uint32("login.timeout", &login_timeout, "%u"); globalvar_add_simple_string("login.fail_command", &login_fail_command); return 0; diff --git a/common/reset_source.c b/common/reset_source.c index 06e2ca85f5..e18bf6db68 100644 --- a/common/reset_source.c +++ b/common/reset_source.c @@ -54,7 +54,7 @@ EXPORT_SYMBOL(reset_source_set_priority); static int reset_source_init(void) { - globalvar_add_simple_enum("system.reset", (unsigned int *)&reset_source, + globalvar_add_simple_enum_ro("system.reset", (unsigned int *)&reset_source, reset_src_names, ARRAY_SIZE(reset_src_names)); return 0; diff --git a/common/state/backend_bucket_circular.c b/common/state/backend_bucket_circular.c index 832f44e599..7c81cdfaff 100644 --- a/common/state/backend_bucket_circular.c +++ b/common/state/backend_bucket_circular.c @@ -72,7 +72,6 @@ struct __attribute__((__packed__)) state_backend_storage_bucket_circular_meta { }; static const uint32_t circular_magic = 0x14fa2d02; -static const uint8_t free_pattern = 0xff; static inline struct state_backend_storage_bucket_circular *get_bucket_circular(struct state_backend_storage_bucket *bucket) diff --git a/common/state/state_variables.c b/common/state/state_variables.c index 5b8e6284d9..56bcd9590a 100644 --- a/common/state/state_variables.c +++ b/common/state/state_variables.c @@ -108,7 +108,7 @@ static struct state_variable *state_uint8_create(struct state *state, su32 = xzalloc(sizeof(*su32)); - param = dev_add_param_int(&state->dev, name, state_uint8_set, + param = dev_add_param_uint32(&state->dev, name, state_uint8_set, NULL, &su32->value, "%u", &su32->var); if (IS_ERR(param)) { free(su32); @@ -136,7 +136,7 @@ static struct state_variable *state_uint32_create(struct state *state, su32 = xzalloc(sizeof(*su32)); - param = dev_add_param_int(&state->dev, name, state_set_dirty, + param = dev_add_param_uint32(&state->dev, name, state_set_dirty, NULL, &su32->value, "%u", &su32->var); if (IS_ERR(param)) { free(su32); diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index ddd9661806..ae5df13c96 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -155,7 +155,7 @@ int amba_device_add(struct amba_device *dev) if (ret) goto err_release; - dev_add_param_int_ro(&dev->dev, "periphid", dev->periphid, "0x%08x"); + dev_add_param_uint32_fixed(&dev->dev, "periphid", dev->periphid, "0x%08x"); return ret; err_release: diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index d75b954a4e..b5abe1cdf5 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -8,7 +8,7 @@ obj-$(CONFIG_ARCH_MVEBU) += mvebu/ obj-$(CONFIG_ARCH_MXS) += mxs/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ -obj-$(CONFIG_CLK_SOCFPGA) += socfpga.o +obj-$(CONFIG_CLK_SOCFPGA) += socfpga/ obj-$(CONFIG_MACH_MIPS_ATH79) += clk-ar933x.o obj-$(CONFIG_ARCH_IMX) += imx/ obj-$(CONFIG_COMMON_CLK_AT91) += at91/ diff --git a/drivers/clk/imx/clk-imx5.c b/drivers/clk/imx/clk-imx5.c index c4c47a6d87..edebd25a38 100644 --- a/drivers/clk/imx/clk-imx5.c +++ b/drivers/clk/imx/clk-imx5.c @@ -313,6 +313,7 @@ int __init mx50_clocks_init(struct device_d *dev, void __iomem *regs) clkdev_add_physbase(clks[IMX5_CLK_ESDHC_D_SEL], MX50_ESDHC4_BASE_ADDR, NULL); clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX50_PWM1_BASE_ADDR, "per"); clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX50_PWM2_BASE_ADDR, "per"); + clkdev_add_physbase(clks[IMX5_CLK_AHB], MX50_OTG_BASE_ADDR, NULL); return 0; } diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile new file mode 100644 index 0000000000..341e6433e5 --- /dev/null +++ b/drivers/clk/socfpga/Makefile @@ -0,0 +1,3 @@ +obj-y += clk.o + +obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += clk-gate-a10.o clk-periph-a10.o clk-pll-a10.o diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c new file mode 100644 index 0000000000..07f6026c2e --- /dev/null +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2015 Altera Corporation. All rights reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <io.h> +#include <malloc.h> +#include <regmap.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <mach/arria10-regs.h> +#include <mach/arria10-system-manager.h> + +#include "clk.h" + +#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, clk) + +/* SDMMC Group for System Manager defines */ +#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x28 + +static unsigned long socfpga_gate_clk_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(clk); + u32 div = 1, val; + + if (socfpgaclk->fixed_div) + div = socfpgaclk->fixed_div; + else if (socfpgaclk->div_reg) { + val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; + val &= GENMASK(socfpgaclk->width - 1, 0); + div = (1 << val); + } + + return parent_rate / div; +} + +static int socfpga_clk_prepare(struct clk *clk) +{ + struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(clk); + int i; + u32 hs_timing; + u32 clk_phase[2]; + + if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { + for (i = 0; i < ARRAY_SIZE(clk_phase); i++) { + switch (socfpgaclk->clk_phase[i]) { + case 0: + clk_phase[i] = 0; + break; + case 45: + clk_phase[i] = 1; + break; + case 90: + clk_phase[i] = 2; + break; + case 135: + clk_phase[i] = 3; + break; + case 180: + clk_phase[i] = 4; + break; + case 225: + clk_phase[i] = 5; + break; + case 270: + clk_phase[i] = 6; + break; + case 315: + clk_phase[i] = 7; + break; + default: + clk_phase[i] = 0; + break; + } + } + + hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); + writel(hs_timing, ARRIA10_SYSMGR_SDMMC); + } + return 0; +} + +static int clk_socfpga_enable(struct clk *clk) +{ + struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(clk); + u32 val; + + socfpga_clk_prepare(clk); + + val = readl(socfpga_clk->reg); + val |= 1 << socfpga_clk->bit_idx; + writel(val, socfpga_clk->reg); + + return 0; +} + +static void clk_socfpga_disable(struct clk *clk) +{ + struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(clk); + u32 val; + + val = readl(socfpga_clk->reg); + val &= ~(1 << socfpga_clk->shift); + writel(val, socfpga_clk->reg); +} + +static struct clk_ops gateclk_ops = { + .recalc_rate = socfpga_gate_clk_recalc_rate, +}; + +static struct clk *__socfpga_gate_init(struct device_node *node, + const struct clk_ops *ops) +{ + u32 clk_gate[2]; + u32 div_reg[3]; + u32 clk_phase[2]; + u32 fixed_div; + struct socfpga_gate_clk *socfpga_clk; + const char *clk_name = node->name; + int rc; + int i; + + socfpga_clk = xzalloc(sizeof(*socfpga_clk)); + + rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); + if (rc) + clk_gate[0] = 0; + + if (clk_gate[0]) { + socfpga_clk->reg = clk_mgr_base_addr + clk_gate[0]; + socfpga_clk->bit_idx = clk_gate[1]; + + gateclk_ops.enable = clk_socfpga_enable; + gateclk_ops.disable = clk_socfpga_disable; + } + + rc = of_property_read_u32(node, "fixed-divider", &fixed_div); + if (rc) + socfpga_clk->fixed_div = 0; + else + socfpga_clk->fixed_div = fixed_div; + + rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); + if (!rc) { + socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; + socfpga_clk->shift = div_reg[1]; + socfpga_clk->width = div_reg[2]; + } else { + socfpga_clk->div_reg = NULL; + } + + rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); + if (!rc) { + socfpga_clk->clk_phase[0] = clk_phase[0]; + socfpga_clk->clk_phase[1] = clk_phase[1]; + } + + of_property_read_string(node, "clock-output-names", &clk_name); + + socfpga_clk->clk.name = xstrdup(clk_name); + socfpga_clk->clk.ops = ops; + + for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) { + socfpga_clk->parent_names[i] = of_clk_get_parent_name(node, i); + if (!socfpga_clk->parent_names[i]) + break; + } + + socfpga_clk->clk.num_parents = i; + socfpga_clk->clk.parent_names = socfpga_clk->parent_names; + + rc = clk_register(&socfpga_clk->clk); + if (rc) { + free(socfpga_clk); + return ERR_PTR(rc); + } + + return &socfpga_clk->clk; +} + +struct clk *socfpga_a10_gate_init(struct device_node *node) +{ + return __socfpga_gate_init(node, &gateclk_ops); +} diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c new file mode 100644 index 0000000000..9dd7fc9c25 --- /dev/null +++ b/drivers/clk/socfpga/clk-periph-a10.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2015 Altera Corporation. All rights reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <io.h> +#include <malloc.h> +#include <linux/clk.h> +#include <linux/clkdev.h> + +#include "clk.h" + +#define CLK_MGR_FREE_SHIFT 16 +#define CLK_MGR_FREE_MASK 0x7 + +#define SOCFPGA_MPU_FREE_CLK "mpu_free_clk" +#define SOCFPGA_NOC_FREE_CLK "noc_free_clk" +#define SOCFPGA_SDMMC_FREE_CLK "sdmmc_free_clk" +#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, clk) + +static unsigned long clk_periclk_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(clk); + u32 div; + + if (socfpgaclk->fixed_div) { + div = socfpgaclk->fixed_div; + } else if (socfpgaclk->div_reg) { + div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; + div &= GENMASK(socfpgaclk->width - 1, 0); + div += 1; + } else { + div = ((readl(socfpgaclk->reg) & 0x7ff) + 1); + } + + return parent_rate / div; +} + +static int clk_periclk_get_parent(struct clk *clk) +{ + struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(clk); + u32 clk_src; + + clk_src = readl(socfpgaclk->reg); + if (streq(clk->name, SOCFPGA_MPU_FREE_CLK) || + streq(clk->name, SOCFPGA_NOC_FREE_CLK) || + streq(clk->name, SOCFPGA_SDMMC_FREE_CLK)) + return (clk_src >> CLK_MGR_FREE_SHIFT) & + CLK_MGR_FREE_MASK; + else + return 0; +} + +static const struct clk_ops periclk_ops = { + .recalc_rate = clk_periclk_recalc_rate, + .get_parent = clk_periclk_get_parent, +}; + +static struct clk *__socfpga_periph_init(struct device_node *node, + const struct clk_ops *ops) +{ + u32 reg; + struct socfpga_periph_clk *periph_clk; + const char *clk_name = node->name; + int rc; + u32 fixed_div; + u32 div_reg[3]; + int i; + + of_property_read_u32(node, "reg", ®); + + periph_clk = xzalloc(sizeof(*periph_clk)); + + periph_clk->reg = clk_mgr_base_addr + reg; + + rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); + if (!rc) { + periph_clk->div_reg = clk_mgr_base_addr + div_reg[0]; + periph_clk->shift = div_reg[1]; + periph_clk->width = div_reg[2]; + } else { + periph_clk->div_reg = NULL; + } + + rc = of_property_read_u32(node, "fixed-divider", &fixed_div); + if (rc) + periph_clk->fixed_div = 0; + else + periph_clk->fixed_div = fixed_div; + + of_property_read_string(node, "clock-output-names", &clk_name); + + for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) { + periph_clk->parent_names[i] = of_clk_get_parent_name(node, i); + if (!periph_clk->parent_names[i]) + break; + } + + periph_clk->clk.num_parents = i; + periph_clk->clk.parent_names = periph_clk->parent_names; + + periph_clk->clk.name = xstrdup(clk_name); + periph_clk->clk.ops = ops; + + rc = clk_register(&periph_clk->clk); + if (rc) { + free(periph_clk); + return ERR_PTR(rc); + } + + return &periph_clk->clk; +} + +struct clk *socfpga_a10_periph_init(struct device_node *node) +{ + return __socfpga_periph_init(node, &periclk_ops); +} diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c new file mode 100644 index 0000000000..4dae3e537b --- /dev/null +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2015 Altera Corporation. All rights reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ +#include <common.h> +#include <io.h> +#include <malloc.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <asm-generic/div64.h> + +#include "clk.h" + +/* Clock Manager offsets */ +#define CLK_MGR_PLL_CLK_SRC_SHIFT 8 +#define CLK_MGR_PLL_CLK_SRC_MASK 0x3 + +/* Clock bypass bits */ +#define SOCFPGA_PLL_BG_PWRDWN 0 +#define SOCFPGA_PLL_PWR_DOWN 1 +#define SOCFPGA_PLL_EXT_ENA 2 +#define SOCFPGA_PLL_DIVF_MASK 0x00001FFF +#define SOCFPGA_PLL_DIVF_SHIFT 0 +#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000 +#define SOCFPGA_PLL_DIVQ_SHIFT 16 +#define SOCFGPA_MAX_PARENTS 5 + +#define SOCFPGA_MAIN_PLL_CLK "main_pll" +#define SOCFPGA_PERIP_PLL_CLK "periph_pll" + +#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, clk) + +static unsigned long clk_pll_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct socfpga_pll *socfpgaclk = to_socfpga_clk(clk); + unsigned long divf, divq, reg; + unsigned long long vco_freq; + + /* read VCO1 reg for numerator and denominator */ + reg = readl(socfpgaclk->reg + 0x4); + divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; + divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; + vco_freq = (unsigned long long)parent_rate * (divf + 1); + do_div(vco_freq, (1 + divq)); + return (unsigned long)vco_freq; +} + +static int clk_pll_get_parent(struct clk *clk) +{ + struct socfpga_pll *socfpgaclk = to_socfpga_clk(clk); + u32 pll_src; + + pll_src = readl(socfpgaclk->reg); + + return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) & + CLK_MGR_PLL_CLK_SRC_MASK; +} + +static int clk_socfpga_enable(struct clk *clk) +{ + struct socfpga_pll *socfpga_clk = to_socfpga_clk(clk); + u32 val; + + val = readl(socfpga_clk->reg); + val |= 1 << socfpga_clk->bit_idx; + writel(val, socfpga_clk->reg); + + return 0; +} + +static void clk_socfpga_disable(struct clk *clk) +{ + struct socfpga_pll *socfpga_clk = to_socfpga_clk(clk); + u32 val; + + val = readl(socfpga_clk->reg); + val &= ~(1 << socfpga_clk->bit_idx); + writel(val, socfpga_clk->reg); +} + +static struct clk_ops clk_pll_ops = { + .recalc_rate = clk_pll_recalc_rate, + .get_parent = clk_pll_get_parent, +}; + +static struct clk *__socfpga_pll_init(struct device_node *node, + const struct clk_ops *ops) +{ + u32 reg; + struct socfpga_pll *pll_clk; + const char *clk_name = node->name; + int rc; + int i; + + of_property_read_u32(node, "reg", ®); + + pll_clk = xzalloc(sizeof(*pll_clk)); + + pll_clk->reg = clk_mgr_base_addr + reg; + + of_property_read_string(node, "clock-output-names", &clk_name); + + pll_clk->clk.name = xstrdup(clk_name); + pll_clk->clk.ops = ops; + + for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) { + pll_clk->parent_names[i] = of_clk_get_parent_name(node, i); + if (!pll_clk->parent_names[i]) + break; + } + + pll_clk->bit_idx = SOCFPGA_PLL_EXT_ENA; + pll_clk->clk.num_parents = i; + pll_clk->clk.parent_names = pll_clk->parent_names; + + clk_pll_ops.enable = clk_socfpga_enable; + clk_pll_ops.disable = clk_socfpga_disable; + + rc = clk_register(&pll_clk->clk); + if (rc) { + free(pll_clk); + return NULL; + } + + return &pll_clk->clk; +} + +struct clk *socfpga_a10_pll_init(struct device_node *node) +{ + return __socfpga_pll_init(node, &clk_pll_ops); +} diff --git a/drivers/clk/socfpga.c b/drivers/clk/socfpga/clk.c index 6af0632caf..ade608ffe3 100644 --- a/drivers/clk/socfpga.c +++ b/drivers/clk/socfpga/clk.c @@ -12,6 +12,7 @@ */ #include <common.h> +#include <debug_ll.h> #include <init.h> #include <driver.h> #include <linux/clk.h> @@ -20,6 +21,8 @@ #include <linux/clkdev.h> #include <linux/err.h> +#include "clk.h" + /* Clock Manager offsets */ #define CLKMGR_CTRL 0x0 #define CLKMGR_BYPASS 0x4 @@ -52,7 +55,7 @@ #define div_mask(width) ((1 << (width)) - 1) #define streq(a, b) (strcmp((a), (b)) == 0) -static void __iomem *clk_mgr_base_addr; +void __iomem *clk_mgr_base_addr; struct clk_pll { struct clk clk; @@ -385,6 +388,12 @@ static void socfpga_register_clocks(struct device_d *dev, struct device_node *no clk = socfpga_periph_clk(node); else if (of_device_is_compatible(node, "altr,socfpga-gate-clk")) clk = socfpga_gate_clk(node); + else if (of_device_is_compatible(node, "altr,socfpga-a10-pll-clock")) + clk = socfpga_a10_pll_init(node); + else if (of_device_is_compatible(node, "altr,socfpga-a10-perip-clk")) + clk = socfpga_a10_periph_init(node); + else if (of_device_is_compatible(node, "altr,socfpga-a10-gate-clk")) + clk = socfpga_a10_gate_init(node); else return; diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h new file mode 100644 index 0000000000..6d6c28344d --- /dev/null +++ b/drivers/clk/socfpga/clk.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * based on drivers/clk/tegra/clk.h + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __SOCFPGA_CLK_H +#define __SOCFPGA_CLK_H + +#include <linux/clk.h> + +/* Clock Manager offsets */ +#define CLKMGR_CTRL 0x0 +#define CLKMGR_BYPASS 0x4 +#define CLKMGR_DBCTRL 0x10 +#define CLKMGR_L4SRC 0x70 +#define CLKMGR_PERPLL_SRC 0xAC + +#define SOCFPGA_MAX_PARENTS 5 + +#define streq(a, b) (strcmp((a), (b)) == 0) + +extern void __iomem *clk_mgr_base_addr; + +void __init socfpga_pll_init(struct device_node *node); +void __init socfpga_periph_init(struct device_node *node); +void __init socfpga_gate_init(struct device_node *node); + +#ifdef CONFIG_ARCH_SOCFPGA_ARRIA10 +struct clk *socfpga_a10_pll_init(struct device_node *node); +struct clk *socfpga_a10_periph_init(struct device_node *node); +struct clk *socfpga_a10_gate_init(struct device_node *node); +#else +struct clk *socfpga_a10_pll_init(struct device_node *node) +{ + return ERR_PTR(-ENOSYS); +} +struct clk *socfpga_a10_periph_init(struct device_node *node) +{ + return ERR_PTR(-ENOSYS); +} +struct clk *socfpga_a10_gate_init(struct device_node *node) +{ + return ERR_PTR(-ENOSYS); +} +#endif + +struct socfpga_pll { + struct clk clk; + void __iomem *reg; + u32 bit_idx; + const char *parent_names[SOCFPGA_MAX_PARENTS]; +}; + +struct socfpga_gate_clk { + struct clk clk; + char *parent_name; + u32 fixed_div; + void __iomem *div_reg; + struct regmap *sys_mgr_base_addr; + u32 width; /* only valid if div_reg != 0 */ + u32 shift; /* only valid if div_reg != 0 */ + u32 bit_idx; + void __iomem *reg; + u32 clk_phase[2]; + const char *parent_names[SOCFPGA_MAX_PARENTS]; +}; + +struct socfpga_periph_clk { + struct clk clk; + void __iomem *reg; + char *parent_name; + u32 fixed_div; + void __iomem *div_reg; + u32 width; /* only valid if div_reg != 0 */ + u32 shift; /* only valid if div_reg != 0 */ + const char *parent_names[SOCFPGA_MAX_PARENTS]; +}; + +#endif /* SOCFPGA_CLK_H */ diff --git a/drivers/eeprom/at24.c b/drivers/eeprom/at24.c index 1227286fbe..050a35aed8 100644 --- a/drivers/eeprom/at24.c +++ b/drivers/eeprom/at24.c @@ -454,6 +454,10 @@ static int at24_probe(struct device_d *dev) at24->cdev.size = chip.byte_len; writable = !(chip.flags & AT24_FLAG_READONLY); + + if (of_get_property(dev->device_node, "read-only", NULL)) + writable = 0; + if (writable) { unsigned write_max = chip.page_size; diff --git a/drivers/eeprom/at25.c b/drivers/eeprom/at25.c index 1caaebd371..9f16f964a8 100644 --- a/drivers/eeprom/at25.c +++ b/drivers/eeprom/at25.c @@ -290,7 +290,7 @@ static int at25_np_to_chip(struct device_d *dev, val); return -ENODEV; } - if (of_find_property(np, "read-only", NULL)) + if (of_property_read_bool(np, "read-only")) chip->flags |= EE_READONLY; } return 0; diff --git a/drivers/efi/efi-device.c b/drivers/efi/efi-device.c index e9b03cb02a..9975aea6f7 100644 --- a/drivers/efi/efi-device.c +++ b/drivers/efi/efi-device.c @@ -404,12 +404,12 @@ static int efi_init_devices(void) dev_add_param_fixed(efi_bus.dev, "fw_vendor", fw_vendor); free(fw_vendor); - dev_add_param_int_ro(efi_bus.dev, "major", sys_major, "%u"); - dev_add_param_int_ro(efi_bus.dev, "minor", sys_minor, "%u"); - dev_add_param_int_ro(efi_bus.dev, "fw_revision", efi_sys_table->fw_revision, "%u"); - dev_add_param_int_ro(efi_bus.dev, "secure_boot", secure_boot, "%d"); - dev_add_param_int_ro(efi_bus.dev, "secure_mode", - secure_boot & setup_mode, "%u"); + dev_add_param_uint32_fixed(efi_bus.dev, "major", sys_major, "%u"); + dev_add_param_uint32_fixed(efi_bus.dev, "minor", sys_minor, "%u"); + dev_add_param_uint32_fixed(efi_bus.dev, "fw_revision", efi_sys_table->fw_revision, "%u"); + dev_add_param_bool_fixed(efi_bus.dev, "secure_boot", secure_boot); + dev_add_param_bool_fixed(efi_bus.dev, "secure_mode", + secure_boot & setup_mode); efi_bus.dev->info = efi_businfo; diff --git a/drivers/firmware/socfpga.c b/drivers/firmware/socfpga.c index a0cd2011cb..c1eae98acc 100644 --- a/drivers/firmware/socfpga.c +++ b/drivers/firmware/socfpga.c @@ -34,10 +34,10 @@ #include <fcntl.h> #include <init.h> #include <io.h> -#include <mach/system-manager.h> -#include <mach/reset-manager.h> -#include <mach/socfpga-regs.h> -#include <mach/sdram.h> +#include <mach/cyclone5-system-manager.h> +#include <mach/cyclone5-reset-manager.h> +#include <mach/cyclone5-regs.h> +#include <mach/cyclone5-sdram.h> #define FPGAMGRREGS_STAT 0x0 #define FPGAMGRREGS_CTRL 0x4 diff --git a/drivers/input/qt1070.c b/drivers/input/qt1070.c index 1ee868dfdd..d81a8fa401 100644 --- a/drivers/input/qt1070.c +++ b/drivers/input/qt1070.c @@ -238,8 +238,8 @@ static int qt1070_probe(struct device_d *dev) goto err; } - dev_add_param_int_ro(dev, "fw_version", fw_version, "0x%x"); - dev_add_param_int_ro(dev, "chip_ip", chip_id, "0x%x"); + dev_add_param_uint32_fixed(dev, "fw_version", fw_version, "0x%x"); + dev_add_param_uint32_fixed(dev, "chip_ip", chip_id, "0x%x"); memcpy(data->code, default_code, sizeof(int) * ARRAY_SIZE(default_code)); diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig index 0f3504c735..954f957bc7 100644 --- a/drivers/mci/Kconfig +++ b/drivers/mci/Kconfig @@ -66,6 +66,13 @@ config MCI_BCM283X bool "MCI support for BCM283X" depends on ARCH_BCM283X +config MCI_DOVE + bool "Marvell Dove SDHCI" + depends on ARCH_DOVE + help + Enable this entry to add support to read and write SD cards on a + Marvell Dove SoC based system. + config MCI_IMX bool "i.MX" depends on ARCH_IMX27 || ARCH_IMX31 diff --git a/drivers/mci/Makefile b/drivers/mci/Makefile index 88ec456aa3..fe2c8adbac 100644 --- a/drivers/mci/Makefile +++ b/drivers/mci/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_MCI) += mci-core.o obj-$(CONFIG_MCI_ATMEL) += atmel_mci.o obj-$(CONFIG_MCI_BCM283X) += mci-bcm2835.o +obj-$(CONFIG_MCI_DOVE) += dove-sdhci.o obj-$(CONFIG_MCI_IMX) += imx.o obj-$(CONFIG_MCI_IMX_ESDHC) += imx-esdhc.o obj-$(CONFIG_MCI_MXS) += mxs.o diff --git a/drivers/mci/dove-sdhci.c b/drivers/mci/dove-sdhci.c new file mode 100644 index 0000000000..caee4107eb --- /dev/null +++ b/drivers/mci/dove-sdhci.c @@ -0,0 +1,392 @@ +/* + * Marvell Dove SDHCI MCI driver + * + * Pengutronix, Michael Grzeschik <mgr@pengutronix.de> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <clock.h> +#include <common.h> +#include <init.h> +#include <io.h> +#include <dma.h> +#include <malloc.h> +#include <mci.h> +#include <linux/err.h> + +#include "sdhci.h" + +struct dove_sdhci { + struct mci_host mci; + void __iomem *base; +}; + +#define priv_from_mci_host(h) \ + container_of(h, struct dove_sdhci, mci); + +static inline void dove_sdhci_writel(struct dove_sdhci *p, int reg, u32 val) +{ + writel(val, p->base + reg); +} + +static inline void dove_sdhci_writew(struct dove_sdhci *p, int reg, u16 val) +{ + writew(val, p->base + reg); +} + +static inline void dove_sdhci_writeb(struct dove_sdhci *p, int reg, u8 val) +{ + writeb(val, p->base + reg); +} + +static inline u32 dove_sdhci_readl(struct dove_sdhci *p, int reg) +{ + return readl(p->base + reg); +} + +static inline u16 dove_sdhci_readw(struct dove_sdhci *p, int reg) +{ + return readw(p->base + reg); +} + +static inline u8 dove_sdhci_readb(struct dove_sdhci *p, int reg) +{ + return readb(p->base + reg); +} + +static int dove_sdhci_wait_for_done(struct dove_sdhci *host, u16 mask) +{ + u16 status; + u64 start; + + start = get_time_ns(); + while (1) { + status = dove_sdhci_readw(host, SDHCI_INT_NORMAL_STATUS); + if (status & SDHCI_INT_ERROR) + return -EPERM; + /* this special quirk is necessary, as the dma + * engine stops on dma boundary and will only + * restart after acknowledging it this way. + */ + if (status & SDHCI_INT_DMA) { + u32 addr = dove_sdhci_readl(host, SDHCI_DMA_ADDRESS); + dove_sdhci_writel(host, SDHCI_DMA_ADDRESS, addr); + } + if (status & mask) + break; + if (is_timeout(start, 1000 * MSECOND)) { + dev_err(host->mci.hw_dev, "SDHCI timeout while waiting for done\n"); + return -ETIMEDOUT; + } + } + return 0; +} + +static int dove_sdhci_mci_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, + struct mci_data *data) +{ + u16 val; + u64 start; + int ret; + unsigned int num_bytes = data->blocks * data->blocksize; + struct dove_sdhci *host = priv_from_mci_host(mci); + + dove_sdhci_writel(host, SDHCI_INT_STATUS, ~0); + + /* Do not wait for CMD_INHIBIT_DAT on stop commands */ + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + val = SDHCI_CMD_INHIBIT_CMD; + else + val = SDHCI_CMD_INHIBIT_CMD | SDHCI_CMD_INHIBIT_DATA; + + /* Wait for bus idle */ + start = get_time_ns(); + while (1) { + if (!(dove_sdhci_readw(host, SDHCI_PRESENT_STATE) & val)) + break; + if (is_timeout(start, 10 * MSECOND)) { + dev_err(host->mci.hw_dev, "SDHCI timeout while waiting for idle\n"); + return -ETIMEDOUT; + } + } + + /* setup transfer data */ + if (data) { + if (data->flags & MMC_DATA_READ) + dove_sdhci_writel(host, SDHCI_DMA_ADDRESS, (u32)data->dest); + else + dove_sdhci_writel(host, SDHCI_DMA_ADDRESS, (u32)data->src); + dove_sdhci_writew(host, SDHCI_BLOCK_SIZE, SDHCI_DMA_BOUNDARY_512K | + SDHCI_TRANSFER_BLOCK_SIZE(data->blocksize)); + dove_sdhci_writew(host, SDHCI_BLOCK_COUNT, data->blocks); + dove_sdhci_writeb(host, SDHCI_TIMEOUT_CONTROL, 0xe); + + + if (data->flags & MMC_DATA_WRITE) + dma_sync_single_for_device((unsigned long)data->src, + num_bytes, DMA_TO_DEVICE); + else + dma_sync_single_for_device((unsigned long)data->dest, + num_bytes, DMA_FROM_DEVICE); + } + + /* setup transfer mode */ + val = 0; + if (data) { + val |= SDHCI_DMA_EN | SDHCI_BLOCK_COUNT_EN; + if (data->blocks > 1) + val |= SDHCI_MULTIPLE_BLOCKS; + if (data->flags & MMC_DATA_READ) + val |= SDHCI_DATA_TO_HOST; + } + dove_sdhci_writew(host, SDHCI_TRANSFER_MODE, val); + + dove_sdhci_writel(host, SDHCI_ARGUMENT, cmd->cmdarg); + + if (!(cmd->resp_type & MMC_RSP_PRESENT)) + val = SDHCI_RESP_NONE; + else if (cmd->resp_type & MMC_RSP_136) + val = SDHCI_RESP_TYPE_136; + else if (cmd->resp_type & MMC_RSP_BUSY) + val = SDHCI_RESP_TYPE_48_BUSY; + else + val = SDHCI_RESP_TYPE_48; + + if (cmd->resp_type & MMC_RSP_CRC) + val |= SDHCI_CMD_CRC_CHECK_EN; + if (cmd->resp_type & MMC_RSP_OPCODE) + val |= SDHCI_CMD_INDEX_CHECK_EN; + if (data) + val |= SDHCI_DATA_PRESENT; + val |= SDHCI_CMD_INDEX(cmd->cmdidx); + + dove_sdhci_writew(host, SDHCI_COMMAND, val); + + ret = dove_sdhci_wait_for_done(host, SDHCI_INT_CMD_COMPLETE); + if (ret) { + dev_err(host->mci.hw_dev, "error on command %d\n", cmd->cmdidx); + dev_err(host->mci.hw_dev, "state = %04x %04x, interrupt = %04x %04x\n", + dove_sdhci_readw(host, SDHCI_PRESENT_STATE), + dove_sdhci_readw(host, SDHCI_PRESENT_STATE1), + dove_sdhci_readw(host, SDHCI_INT_NORMAL_STATUS), + dove_sdhci_readw(host, SDHCI_INT_ERROR_STATUS)); + goto cmd_error; + } + + /* CRC is stripped so we need to do some shifting. */ + if (cmd->resp_type & MMC_RSP_136) { + int i; + for (i = 0; i < 4; i++) { + cmd->response[i] = dove_sdhci_readl(host, + SDHCI_RESPONSE_0 + 4*(3-i)) << 8; + if (i != 3) + cmd->response[i] |= dove_sdhci_readb(host, + SDHCI_RESPONSE_0 + 4*(3-i) - 1); + } + } else + cmd->response[0] = dove_sdhci_readl(host, SDHCI_RESPONSE_0); + + if (data->flags & MMC_DATA_WRITE) + dma_sync_single_for_cpu((unsigned long)data->src, + num_bytes, DMA_TO_DEVICE); + else + dma_sync_single_for_cpu((unsigned long)data->dest, + num_bytes, DMA_FROM_DEVICE); + + if (data) { + ret = dove_sdhci_wait_for_done(host, SDHCI_INT_XFER_COMPLETE); + if (ret) { + dev_err(host->mci.hw_dev, "error while transfering data for command %d\n", + cmd->cmdidx); + dev_err(host->mci.hw_dev, "state = %04x %04x, interrupt = %04x %04x\n", + dove_sdhci_readw(host, SDHCI_PRESENT_STATE), + dove_sdhci_readw(host, SDHCI_PRESENT_STATE1), + dove_sdhci_readw(host, SDHCI_INT_NORMAL_STATUS), + dove_sdhci_readw(host, SDHCI_INT_ERROR_STATUS)); + goto cmd_error; + } + } + +cmd_error: + dove_sdhci_writel(host, SDHCI_INT_STATUS, ~0); + return ret; +} + +static u16 dove_sdhci_get_clock_divider(struct dove_sdhci *host, u32 reqclk) +{ + u16 div; + + for (div = 1; div < SDHCI_SPEC_200_MAX_CLK_DIVIDER; div *= 2) + if ((host->mci.f_max / div) <= reqclk) + break; + div /= 2; + + return div; +} + +static void dove_sdhci_mci_set_ios(struct mci_host *mci, struct mci_ios *ios) +{ + u16 val; + u64 start; + struct dove_sdhci *host = priv_from_mci_host(mci); + + debug("%s: clock = %u, bus-width = %d, timing = %02x\n", __func__, ios->clock, ios->bus_width, ios->timing); + + /* disable on zero clock */ + if (!ios->clock) + return; + + /* enable bus power */ + val = SDHCI_BUS_VOLTAGE_330; + dove_sdhci_writeb(host, SDHCI_POWER_CONTROL, val | SDHCI_BUS_POWER_EN); + udelay(400); + + /* set bus width */ + val = dove_sdhci_readb(host, SDHCI_HOST_CONTROL) & + ~(SDHCI_DATA_WIDTH_4BIT | SDHCI_DATA_WIDTH_8BIT); + switch (ios->bus_width) { + case MMC_BUS_WIDTH_8: + val |= SDHCI_DATA_WIDTH_8BIT; + break; + case MMC_BUS_WIDTH_4: + val |= SDHCI_DATA_WIDTH_4BIT; + break; + } + + if (ios->clock > 26000000) + val |= SDHCI_HIGHSPEED_EN; + else + val &= ~SDHCI_HIGHSPEED_EN; + + dove_sdhci_writeb(host, SDHCI_HOST_CONTROL, val); + + /* set bus clock */ + dove_sdhci_writew(host, SDHCI_CLOCK_CONTROL, 0); + val = dove_sdhci_get_clock_divider(host, ios->clock); + val = SDHCI_INTCLOCK_EN | SDHCI_FREQ_SEL(val); + dove_sdhci_writew(host, SDHCI_CLOCK_CONTROL, val); + + /* wait for internal clock stable */ + start = get_time_ns(); + while (!(dove_sdhci_readw(host, SDHCI_CLOCK_CONTROL) & + SDHCI_INTCLOCK_STABLE)) { + if (is_timeout(start, 20 * MSECOND)) { + dev_err(host->mci.hw_dev, "SDHCI clock stable timeout\n"); + return; + } + } + + /* enable bus clock */ + dove_sdhci_writew(host, SDHCI_CLOCK_CONTROL, val | SDHCI_SDCLOCK_EN); +} + +static int dove_sdhci_mci_init(struct mci_host *mci, struct device_d *dev) +{ + u64 start; + struct dove_sdhci *host = priv_from_mci_host(mci); + + /* reset sdhci controller */ + dove_sdhci_writeb(host, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL); + + /* wait for reset completion */ + start = get_time_ns(); + while (1) { + if ((dove_sdhci_readb(host, SDHCI_SOFTWARE_RESET) & + SDHCI_RESET_ALL) == 0) + break; + if (is_timeout(start, 100 * MSECOND)) { + dev_err(dev, "SDHCI reset timeout\n"); + return -ETIMEDOUT; + } + } + + dove_sdhci_writel(host, SDHCI_INT_STATUS, ~0); + dove_sdhci_writel(host, SDHCI_INT_ENABLE, ~0); + dove_sdhci_writel(host, SDHCI_SIGNAL_ENABLE, ~0); + + return 0; +} + +static void dove_sdhci_set_mci_caps(struct dove_sdhci *host) +{ + u16 caps[2]; + + caps[0] = dove_sdhci_readw(host, SDHCI_CAPABILITIES); + caps[1] = dove_sdhci_readw(host, SDHCI_CAPABILITIES_1); + + if (caps[1] & SDHCI_HOSTCAP_VOLTAGE_180) + host->mci.voltages |= MMC_VDD_165_195; + if (caps[1] & SDHCI_HOSTCAP_VOLTAGE_300) + host->mci.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; + if (caps[1] & SDHCI_HOSTCAP_VOLTAGE_330) + host->mci.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; + + if (caps[1] & SDHCI_HOSTCAP_HIGHSPEED) + host->mci.host_caps |= (MMC_CAP_MMC_HIGHSPEED_52MHZ | + MMC_CAP_MMC_HIGHSPEED | + MMC_CAP_SD_HIGHSPEED); + + /* parse board supported bus width capabilities */ + mci_of_parse(&host->mci); + + /* limit bus widths to controller capabilities */ + if ((caps[1] & SDHCI_HOSTCAP_8BIT) == 0) + host->mci.host_caps &= ~MMC_CAP_8_BIT_DATA; +} + +static int dove_sdhci_detect(struct device_d *dev) +{ + struct dove_sdhci *host = dev->priv; + return mci_detect_card(&host->mci); +} + +static int dove_sdhci_probe(struct device_d *dev) +{ + struct dove_sdhci *host; + int ret; + + host = xzalloc(sizeof(*host)); + host->base = dev_request_mem_region(dev, 0); + host->mci.max_req_size = 0x8000; + host->mci.hw_dev = dev; + host->mci.send_cmd = dove_sdhci_mci_send_cmd; + host->mci.set_ios = dove_sdhci_mci_set_ios; + host->mci.init = dove_sdhci_mci_init; + host->mci.f_max = 50000000; + host->mci.f_min = host->mci.f_max / 256; + dev->priv = host; + dev->detect = dove_sdhci_detect; + + dove_sdhci_set_mci_caps(host); + + ret = mci_register(&host->mci); + if (ret) + free(host); + return ret; +} + +static struct of_device_id dove_sdhci_dt_ids[] = { + { .compatible = "marvell,dove-sdhci", }, + { } +}; + +static struct driver_d dove_sdhci_driver = { + .name = "dove-sdhci", + .probe = dove_sdhci_probe, + .of_compatible = DRV_OF_COMPAT(dove_sdhci_dt_ids), +}; +device_platform_driver(dove_sdhci_driver); diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c index b173a173b1..3da1c261a9 100644 --- a/drivers/mci/mci-core.c +++ b/drivers/mci/mci-core.c @@ -984,7 +984,7 @@ static int mci_startup_sd(struct mci *mci) mci_setup_cmd(&cmd, SD_CMD_APP_SET_BUS_WIDTH, 2, MMC_RSP_R1); err = mci_send_cmd(mci, &cmd, NULL); if (err) { - dev_dbg(&mci->dev, "Changing SD bus width failed: %d\n", err); + dev_warn(&mci->dev, "Changing SD bus width failed: %d\n", err); /* TODO continue with 1 bit? */ return err; } @@ -1041,8 +1041,11 @@ static int mci_startup_mmc(struct mci *mci) err = mci_switch(mci, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, ext_csd_bits[idx]); - if (err) + if (err) { + if (idx == 0) + dev_warn(&mci->dev, "Changing MMC bus width failed: %d\n", err); continue; + } mci_set_bus_width(mci, bus_widths[idx]); @@ -1051,7 +1054,7 @@ static int mci_startup_mmc(struct mci *mci) break; } - return 0; + return err; } /** @@ -1693,7 +1696,7 @@ static int mci_card_probe(struct mci *mci) rc = mci_startup(mci); if (rc) { - dev_dbg(&mci->dev, "Card's startup fails with %d\n", rc); + dev_warn(&mci->dev, "Card's startup fails with %d\n", rc); goto on_error; } diff --git a/drivers/mci/sdhci.h b/drivers/mci/sdhci.h index 82a692e732..90595e6433 100644 --- a/drivers/mci/sdhci.h +++ b/drivers/mci/sdhci.h @@ -3,21 +3,80 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_BLOCK_SIZE__BLOCK_COUNT 0x04 +#define SDHCI_BLOCK_SIZE 0x04 +#define SDHCI_DMA_BOUNDARY_512K SDHCI_DMA_BOUNDARY(7) +#define SDHCI_DMA_BOUNDARY_256K SDHCI_DMA_BOUNDARY(6) +#define SDHCI_DMA_BOUNDARY_128K SDHCI_DMA_BOUNDARY(5) +#define SDHCI_DMA_BOUNDARY_64K SDHCI_DMA_BOUNDARY(4) +#define SDHCI_DMA_BOUNDARY_32K SDHCI_DMA_BOUNDARY(3) +#define SDHCI_DMA_BOUNDARY_16K SDHCI_DMA_BOUNDARY(2) +#define SDHCI_DMA_BOUNDARY_8K SDHCI_DMA_BOUNDARY(1) +#define SDHCI_DMA_BOUNDARY_4K SDHCI_DMA_BOUNDARY(0) +#define SDHCI_DMA_BOUNDARY(x) (((x) & 0x7) << 12) +#define SDHCI_TRANSFER_BLOCK_SIZE(x) ((x) & 0xfff) +#define SDHCI_BLOCK_COUNT 0x06 #define SDHCI_ARGUMENT 0x08 #define SDHCI_TRANSFER_MODE__COMMAND 0x0c +#define SDHCI_TRANSFER_MODE 0x0c +#define SDHCI_MULTIPLE_BLOCKS BIT(5) +#define SDHCI_DATA_TO_HOST BIT(4) +#define SDHCI_BLOCK_COUNT_EN BIT(1) +#define SDHCI_DMA_EN BIT(0) +#define SDHCI_COMMAND 0x0e +#define SDHCI_CMD_INDEX(c) (((c) & 0x3f) << 8) +#define SDHCI_DATA_PRESENT BIT(5) +#define SDHCI_CMD_INDEX_CHECK_EN BIT(4) +#define SDHCI_CMD_CRC_CHECK_EN BIT(3) +#define SDHCI_RESP_TYPE_48_BUSY 3 +#define SDHCI_RESP_TYPE_48 2 +#define SDHCI_RESP_TYPE_136 1 +#define SDHCI_RESP_NONE 0 #define SDHCI_RESPONSE_0 0x10 #define SDHCI_RESPONSE_1 0x14 #define SDHCI_RESPONSE_2 0x18 #define SDHCI_RESPONSE_3 0x1c #define SDHCI_BUFFER 0x20 #define SDHCI_PRESENT_STATE 0x24 +#define SDHCI_CMD_INHIBIT_DATA BIT(1) +#define SDHCI_CMD_INHIBIT_CMD BIT(0) +#define SDHCI_PRESENT_STATE1 0x26 #define SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL 0x28 +#define SDHCI_HOST_CONTROL 0x28 +#define SDHCI_DATA_WIDTH_8BIT BIT(5) +#define SDHCI_HIGHSPEED_EN BIT(2) +#define SDHCI_DATA_WIDTH_4BIT BIT(1) +#define SDHCI_POWER_CONTROL 0x29 +#define SDHCI_BUS_VOLTAGE_330 SDHCI_BUS_VOLTAGE(7) +#define SDHCI_BUS_VOLTAGE(v) ((v) << 1) +#define SDHCI_BUS_POWER_EN BIT(0) #define SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET 0x2c +#define SDHCI_CLOCK_CONTROL 0x2c +#define SDHCI_FREQ_SEL(x) (((x) & 0xff) << 8) +#define SDHCI_SDCLOCK_EN BIT(2) +#define SDHCI_INTCLOCK_STABLE BIT(1) +#define SDHCI_INTCLOCK_EN BIT(0) +#define SDHCI_TIMEOUT_CONTROL 0x2e +#define SDHCI_SOFTWARE_RESET 0x2f +#define SDHCI_RESET_ALL BIT(0) #define SDHCI_INT_STATUS 0x30 +#define SDHCI_INT_NORMAL_STATUS 0x30 +#define SDHCI_INT_ERROR BIT(15) +#define SDHCI_INT_DMA BIT(3) +#define SDHCI_INT_XFER_COMPLETE BIT(1) +#define SDHCI_INT_CMD_COMPLETE BIT(0) +#define SDHCI_INT_ERROR_STATUS 0x32 #define SDHCI_INT_ENABLE 0x34 #define SDHCI_SIGNAL_ENABLE 0x38 #define SDHCI_ACMD12_ERR__HOST_CONTROL2 0x3C #define SDHCI_CAPABILITIES 0x40 +#define SDHCI_CAPABILITIES_1 0x42 +#define SDHCI_HOSTCAP_VOLTAGE_180 BIT(10) +#define SDHCI_HOSTCAP_VOLTAGE_300 BIT(9) +#define SDHCI_HOSTCAP_VOLTAGE_330 BIT(8) +#define SDHCI_HOSTCAP_HIGHSPEED BIT(5) +#define SDHCI_HOSTCAP_8BIT BIT(2) + +#define SDHCI_SPEC_200_MAX_CLK_DIVIDER 256 #define SDHCI_MMC_BOOT 0xC4 #define COMMAND_CMD(x) ((x & 0x3f) << 24) diff --git a/drivers/mtd/core.c b/drivers/mtd/core.c index 1eb8dd36d8..1950ee87ee 100644 --- a/drivers/mtd/core.c +++ b/drivers/mtd/core.c @@ -449,13 +449,13 @@ static struct file_operations mtd_ops = { .lseek = dev_lseek_default, }; -static int mtd_partition_set(struct device_d *dev, struct param_d *p, const char *val) +static int mtd_partition_set(struct param_d *p, void *priv) { - struct mtd_info *mtd = container_of(dev, struct mtd_info, class_dev); + struct mtd_info *mtd = priv; struct mtd_info *mtdpart, *tmp; int ret; - if (!val) + if (!mtd->partition_string) return -EINVAL; list_for_each_entry_safe(mtdpart, tmp, &mtd->partitions, partitions_entry) { @@ -464,7 +464,7 @@ static int mtd_partition_set(struct device_d *dev, struct param_d *p, const char return ret; } - return cmdlinepart_do_parse(mtd->cdev.name, val, mtd->size, CMDLINEPART_ADD_DEVNAME); + return cmdlinepart_do_parse(mtd->cdev.name, mtd->partition_string, mtd->size, CMDLINEPART_ADD_DEVNAME); } static char *print_size(uint64_t s) @@ -530,18 +530,18 @@ static int print_parts(char *buf, int bufsize, struct mtd_info *mtd) return ret; } -static const char *mtd_partition_get(struct device_d *dev, struct param_d *p) +static int mtd_partition_get(struct param_d *p, void *priv) { - struct mtd_info *mtd = container_of(dev, struct mtd_info, class_dev); + struct mtd_info *mtd = priv; int len = 0; - free(p->value); + free(mtd->partition_string); len = print_parts(NULL, 0, mtd); - p->value = xzalloc(len + 1); - print_parts(p->value, len + 1, mtd); + mtd->partition_string = xzalloc(len + 1); + print_parts(mtd->partition_string, len + 1, mtd); - return p->value; + return 0; } static int mtd_part_compare(struct list_head *a, struct list_head *b) @@ -637,10 +637,10 @@ int add_mtd_device(struct mtd_info *mtd, const char *devname, int device_id) mtd->cdev.mtd = mtd; if (IS_ENABLED(CONFIG_PARAMETER)) { - dev_add_param_llint_ro(&mtd->class_dev, "size", mtd->size, "%llu"); - dev_add_param_int_ro(&mtd->class_dev, "erasesize", mtd->erasesize, "%u"); - dev_add_param_int_ro(&mtd->class_dev, "writesize", mtd->writesize, "%u"); - dev_add_param_int_ro(&mtd->class_dev, "oobsize", mtd->oobsize, "%u"); + dev_add_param_uint64_ro(&mtd->class_dev, "size", &mtd->size, "%llu"); + dev_add_param_uint32_ro(&mtd->class_dev, "erasesize", &mtd->erasesize, "%u"); + dev_add_param_uint32_ro(&mtd->class_dev, "writesize", &mtd->writesize, "%u"); + dev_add_param_uint32_ro(&mtd->class_dev, "oobsize", &mtd->oobsize, "%u"); } ret = devfs_create(&mtd->cdev); @@ -667,7 +667,7 @@ int add_mtd_device(struct mtd_info *mtd, const char *devname, int device_id) mtd->cdev_bb = mtd_add_bb(mtd, NULL); if (mtd->parent && !mtd->master) { - dev_add_param(&mtd->class_dev, "partitions", mtd_partition_set, mtd_partition_get, 0); + dev_add_param_string(&mtd->class_dev, "partitions", mtd_partition_set, mtd_partition_get, &mtd->partition_string, mtd); of_parse_partitions(&mtd->cdev, mtd->parent->device_node); if (IS_ENABLED(CONFIG_OFDEVICE) && mtd->parent->device_node) { mtd->of_path = xstrdup(mtd->parent->device_node->full_name); diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ceb2bb7215..d9f79474cd 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -3853,25 +3853,40 @@ static int mtd_set_erasebad(struct param_d *param, void *priv) return 0; } -static const char *mtd_get_bbt_type(struct device_d *dev, struct param_d *p) +enum bbt_type { + BBT_TYPE_NONE = 0, + BBT_TYPE_FLASHBASED, + BBT_TYPE_MEMORYBASED, +}; + +static const char *bbt_type_strings[] = { + [BBT_TYPE_NONE] = "none", + [BBT_TYPE_FLASHBASED] = "flashbased", + [BBT_TYPE_MEMORYBASED] = "memorybased", +}; + +static int mtd_get_bbt_type(struct param_d *p, void *priv) { - struct mtd_info *mtd = container_of(dev, struct mtd_info, class_dev); + struct mtd_info *mtd = priv; struct nand_chip *chip = mtd->priv; - const char *str; + enum bbt_type type; if (!chip->bbt) - str = "none"; + type = BBT_TYPE_NONE; else if ((chip->bbt_td && chip->bbt_td->pages[0] != -1) || (chip->bbt_md && chip->bbt_md->pages[0] != -1)) - str = "flashbased"; + type = BBT_TYPE_FLASHBASED; else - str = "memorybased"; + type = BBT_TYPE_MEMORYBASED; + + chip->bbt_type = type; - return str; + return 0; } int add_mtd_nand_device(struct mtd_info *mtd, char *devname) { + struct nand_chip *chip = mtd->priv; int ret; ret = add_mtd_device(mtd, devname, DEVICE_ID_DYNAMIC); @@ -3882,7 +3897,10 @@ int add_mtd_nand_device(struct mtd_info *mtd, char *devname) dev_add_param_bool(&mtd->class_dev, "erasebad", mtd_set_erasebad, NULL, &mtd->p_allow_erasebad, mtd); - dev_add_param(&mtd->class_dev, "bbt", NULL, mtd_get_bbt_type, 0); + dev_add_param_enum(&mtd->class_dev, "bbt", NULL, mtd_get_bbt_type, + &chip->bbt_type, bbt_type_strings, + ARRAY_SIZE(bbt_type_strings), + mtd); return ret; } diff --git a/drivers/mtd/peb.c b/drivers/mtd/peb.c index c35b63f2fd..0e64fe1671 100644 --- a/drivers/mtd/peb.c +++ b/drivers/mtd/peb.c @@ -76,11 +76,11 @@ static int mtd_peb_emulate_erase_failure(void) #ifdef CONFIG_MTD_PEB_DEBUG static int mtd_peb_debug_init(void) { - globalvar_add_simple_int("mtd_peb.mtd_peb_emulate_bitflip", + globalvar_add_simple_uint32("mtd_peb.mtd_peb_emulate_bitflip", &__mtd_peb_emulate_bitflip, "%u"); - globalvar_add_simple_int("mtd_peb.mtd_peb_emulate_write_failure", + globalvar_add_simple_uint32("mtd_peb.mtd_peb_emulate_write_failure", &__mtd_peb_emulate_write_failure, "%u"); - globalvar_add_simple_int("mtd_peb.mtd_peb_emulate_erase_failures", + globalvar_add_simple_uint32("mtd_peb.mtd_peb_emulate_erase_failures", &__mtd_peb_emulate_erase_failures, "%u"); globalvar_add_simple_bool("mtd_peb.mtd_peb_chk_io", &__mtd_peb_chk_io); diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index 680f30f707..6269668187 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -58,7 +58,7 @@ struct cqspi_st { unsigned int irq_mask; int current_cs; unsigned int master_ref_clk_hz; - unsigned int ext_decoder; + unsigned int is_decoded_cs; unsigned int fifo_depth; struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; bool no_reconfig; @@ -903,7 +903,7 @@ static void cqspi_switch_cs(struct cqspi_st *cqspi, unsigned int cs) writel(reg, reg_base + CQSPI_REG_SIZE); /* configure the chip select */ - cqspi_chipselect(cqspi, cs, cqspi->ext_decoder); + cqspi_chipselect(cqspi, cs, cqspi->is_decoded_cs); cqspi_controller_enable(cqspi); } @@ -1020,12 +1020,9 @@ static int cqspi_parse_dt(struct cqspi_st *cqspi) struct device_node *np = cqspi->dev->device_node; struct device_d *dev = cqspi->dev; - if (of_property_read_u32(np, "ext-decoder", &cqspi->ext_decoder)) { - dev_err(dev, "couldn't determine ext-decoder\n"); - return -ENXIO; - } + cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); - if (of_property_read_u32(np, "fifo-depth", &cqspi->fifo_depth)) { + if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { dev_err(dev, "couldn't determine fifo-depth\n"); return -ENXIO; } @@ -1123,7 +1120,7 @@ static int cqspi_probe(struct device_d *dev) dev->priv = cqspi; if (pdata) { - cqspi->ext_decoder = pdata->ext_decoder; + cqspi->is_decoded_cs = pdata->is_decoded_cs; cqspi->fifo_depth = pdata->fifo_depth; } else { ret = cqspi_parse_dt(cqspi); @@ -1133,7 +1130,7 @@ static int cqspi_probe(struct device_d *dev) } } - cqspi->qspi_clk = clk_get(dev, "qspi_clk"); + cqspi->qspi_clk = clk_get(dev, NULL); if (IS_ERR(cqspi->qspi_clk)) { dev_err(dev, "cannot get qspi clk\n"); ret = PTR_ERR(cqspi->qspi_clk); diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 2ea66ed067..40fa890c9e 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -656,17 +656,17 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, ubi_msg(ubi, "available PEBs: %d, total reserved PEBs: %d, PEBs reserved for bad PEB handling: %d", ubi->avail_pebs, ubi->rsvd_pebs, ubi->beb_rsvd_pebs); - dev_add_param_int_ro(&ubi->dev, "peb_size", ubi->peb_size, "%d"); - dev_add_param_int_ro(&ubi->dev, "leb_size", ubi->leb_size, "%d"); - dev_add_param_int_ro(&ubi->dev, "vid_header_offset", ubi->vid_hdr_offset, "%d"); - dev_add_param_int_ro(&ubi->dev, "min_io_size", ubi->min_io_size, "%d"); - dev_add_param_int_ro(&ubi->dev, "sub_page_size", ubi->hdrs_min_io_size, "%d"); - dev_add_param_int_ro(&ubi->dev, "good_peb_count", ubi->good_peb_count, "%d"); - dev_add_param_int_ro(&ubi->dev, "bad_peb_count", ubi->bad_peb_count, "%d"); - dev_add_param_int_ro(&ubi->dev, "max_erase_counter", ubi->max_ec, "%d"); - dev_add_param_int_ro(&ubi->dev, "mean_erase_counter", ubi->mean_ec, "%d"); - dev_add_param_int_ro(&ubi->dev, "available_pebs", ubi->avail_pebs, "%d"); - dev_add_param_int_ro(&ubi->dev, "reserved_pebs", ubi->rsvd_pebs, "%d"); + dev_add_param_uint32_ro(&ubi->dev, "peb_size", &ubi->peb_size, "%u"); + dev_add_param_uint32_ro(&ubi->dev, "leb_size", &ubi->leb_size, "%u"); + dev_add_param_uint32_ro(&ubi->dev, "vid_header_offset", &ubi->vid_hdr_offset, "%u"); + dev_add_param_uint32_ro(&ubi->dev, "min_io_size", &ubi->min_io_size, "%u"); + dev_add_param_uint32_ro(&ubi->dev, "sub_page_size", &ubi->hdrs_min_io_size, "%u"); + dev_add_param_uint32_ro(&ubi->dev, "good_peb_count", &ubi->good_peb_count, "%u"); + dev_add_param_uint32_ro(&ubi->dev, "bad_peb_count", &ubi->bad_peb_count, "%u"); + dev_add_param_uint32_ro(&ubi->dev, "max_erase_counter", &ubi->max_ec, "%u"); + dev_add_param_uint32_ro(&ubi->dev, "mean_erase_counter", &ubi->mean_ec, "%u"); + dev_add_param_uint32_ro(&ubi->dev, "available_pebs", &ubi->avail_pebs, "%u"); + dev_add_param_uint32_ro(&ubi->dev, "reserved_pebs", &ubi->rsvd_pebs, "%u"); ubi_devices[ubi_num] = ubi; diff --git a/drivers/net/designware.c b/drivers/net/designware.c index bd20a8793a..1d3a68384e 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -520,6 +520,9 @@ static __maybe_unused struct of_device_id dwc_ether_compatible[] = { .compatible = "snps,dwmac-3.70a", .data = &dwmac_370a_drvdata, }, { + .compatible = "snps,dwmac-3.72a", + .data = &dwmac_370a_drvdata, + }, { /* sentinel */ } }; diff --git a/drivers/net/dm9k.c b/drivers/net/dm9k.c index 25f08602f6..c99d188ded 100644 --- a/drivers/net/dm9k.c +++ b/drivers/net/dm9k.c @@ -737,7 +737,7 @@ static int dm9000_parse_dt(struct device_d *dev, struct dm9k *priv) if (!IS_ENABLED(CONFIG_OFDEVICE) || !np) return -ENODEV; - if (of_find_property(np, "davicom,no-eeprom", NULL)) { + if (of_property_read_bool(np, "davicom,no-eeprom")) { priv->srom = 0; } else { priv->srom = 1; diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c index 41bf018141..012b90e834 100644 --- a/drivers/net/phy/mdio_bus.c +++ b/drivers/net/phy/mdio_bus.c @@ -330,8 +330,8 @@ static int mdio_bus_probe(struct device_d *_dev) of_set_phy_supported(dev); dev->advertising = dev->supported; - dev_add_param_int_ro(&dev->dev, "phy_addr", dev->addr, "%d"); - dev_add_param_int_ro(&dev->dev, "phy_id", dev->phy_id, "0x%08x"); + dev_add_param_uint32_ro(&dev->dev, "phy_addr", &dev->addr, "%u"); + dev_add_param_uint32_ro(&dev->dev, "phy_id", &dev->phy_id, "0x%08x"); dev->cdev.name = xasprintf("mdio%d-phy%02x", dev->bus->dev.id, diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index a9eb865358..cfa34a2f2a 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -492,10 +492,6 @@ static int rtl8139_eth_send(struct eth_device *edev, void *packet, return 0; } -static const u16 rtl8139_intr_mask = - PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | - TxErr | TxOK | RxErr | RxOK; - static int rtl8139_eth_rx(struct eth_device *edev) { struct rtl8139_priv *priv = edev->priv; diff --git a/drivers/of/base.c b/drivers/of/base.c index 6632f4d9dd..c9bdd91810 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -1090,19 +1090,14 @@ int of_property_write_u8_array(struct device_node *np, size_t sz) { struct property *prop = of_find_property(np, propname, NULL); - u8 *val; if (prop) of_delete_property(prop); - prop = of_new_property(np, propname, NULL, sizeof(*val) * sz); + prop = of_new_property(np, propname, values, sizeof(*values) * sz); if (!prop) return -ENOMEM; - val = prop->value; - while (sz--) - *val++ = *values++; - return 0; } @@ -1807,12 +1802,7 @@ struct property *of_new_property(struct device_node *node, const char *name, struct property *prop; prop = xzalloc(sizeof(*prop)); - prop->name = strdup(name); - if (!prop->name) { - free(prop); - return NULL; - } - + prop->name = xstrdup(name); prop->length = len; prop->value = xzalloc(len); diff --git a/drivers/of/of_net.c b/drivers/of/of_net.c index 086573fc1a..9b54e44674 100644 --- a/drivers/of/of_net.c +++ b/drivers/of/of_net.c @@ -77,19 +77,15 @@ EXPORT_SYMBOL_GPL(of_get_phy_mode); */ const void *of_get_mac_address(struct device_node *np) { - struct property *pp; + const void *p; + int len, i; + const char *str[] = { "mac-address", "local-mac-address", "address" }; - pp = of_find_property(np, "mac-address", NULL); - if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value)) - return pp->value; - - pp = of_find_property(np, "local-mac-address", NULL); - if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value)) - return pp->value; - - pp = of_find_property(np, "address", NULL); - if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value)) - return pp->value; + for (i = 0; i < ARRAY_SIZE(str); i++) { + p = of_get_property(np, str[i], &len); + if (p && (len == 6) && is_valid_ether_addr(p)) + return p; + } return NULL; } diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index ee65619c4e..80fade0611 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -99,12 +99,12 @@ int pwmchip_add(struct pwm_chip *chip, struct device_d *dev) list_add_tail(&pwm->node, &pwm_list); - p = dev_add_param_int(&pwm->dev, "duty_ns", set_duty_period_ns, + p = dev_add_param_uint32(&pwm->dev, "duty_ns", set_duty_period_ns, NULL, &pwm->chip->duty_ns, "%u", pwm); if (IS_ERR(p)) return PTR_ERR(p); - p = dev_add_param_int(&pwm->dev, "period_ns", set_duty_period_ns, + p = dev_add_param_uint32(&pwm->dev, "period_ns", set_duty_period_ns, NULL, &pwm->chip->period_ns, "%u", pwm); if (IS_ERR(p)) return PTR_ERR(p); diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 99412b07e2..5650098a0a 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -118,13 +118,13 @@ static void spi_of_register_slaves(struct spi_master *master) chip.name = xstrdup(n->name); chip.bus_num = master->bus_num; /* Mode (clock phase/polarity/etc.) */ - if (of_find_property(n, "spi-cpha", NULL)) + if (of_property_read_bool(n, "spi-cpha")) chip.mode |= SPI_CPHA; - if (of_find_property(n, "spi-cpol", NULL)) + if (of_property_read_bool(n, "spi-cpol")) chip.mode |= SPI_CPOL; - if (of_find_property(n, "spi-cs-high", NULL)) + if (of_property_read_bool(n, "spi-cs-high")) chip.mode |= SPI_CS_HIGH; - if (of_find_property(n, "spi-3wire", NULL)) + if (of_property_read_bool(n, "spi-3wire")) chip.mode |= SPI_3WIRE; of_property_read_u32(n, "spi-max-frequency", &chip.max_speed_hz); diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c index aba2da0ad3..9170ba4d53 100644 --- a/drivers/usb/core/usb.c +++ b/drivers/usb/core/usb.c @@ -447,19 +447,19 @@ int usb_new_device(struct usb_device *dev) goto err_out; } - dev_add_param_int_ro(&dev->dev, "iManufacturer", - dev->descriptor->iManufacturer, "%d"); - dev_add_param_int_ro(&dev->dev, "iProduct", - dev->descriptor->iProduct, "%d"); - dev_add_param_int_ro(&dev->dev, "iSerialNumber", - dev->descriptor->iSerialNumber, "%d"); + dev_add_param_uint32_fixed(&dev->dev, "iManufacturer", + dev->descriptor->iManufacturer, "%u"); + dev_add_param_uint32_fixed(&dev->dev, "iProduct", + dev->descriptor->iProduct, "%u"); + dev_add_param_uint32_fixed(&dev->dev, "iSerialNumber", + dev->descriptor->iSerialNumber, "%u"); dev_add_param_fixed(&dev->dev, "iSerialNumber", str); dev_add_param_fixed(&dev->dev, "Manufacturer", dev->mf); dev_add_param_fixed(&dev->dev, "Product", dev->prod); dev_add_param_fixed(&dev->dev, "SerialNumber", dev->serial); - dev_add_param_int_ro(&dev->dev, "idVendor", + dev_add_param_uint32_fixed(&dev->dev, "idVendor", dev->descriptor->idVendor, "%04x"); - dev_add_param_int_ro(&dev->dev, "idProduct", + dev_add_param_uint32_fixed(&dev->dev, "idProduct", dev->descriptor->idProduct, "%04x"); list_add_tail(&dev->list, &usb_device_list); dev_count++; diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index ef5f7ec6e0..598637619d 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -758,6 +758,9 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req, const char *cmd copy: ret = copy_file(FASTBOOT_TMPFILE, filename, 1); + + unlink(FASTBOOT_TMPFILE); + if (ret) { fastboot_tx_print(f_fb, "FAILwrite partition: %s", strerror(-ret)); return; diff --git a/drivers/usb/gadget/udc-core.c b/drivers/usb/gadget/udc-core.c index 4f001e102f..ed99b53df7 100644 --- a/drivers/usb/gadget/udc-core.c +++ b/drivers/usb/gadget/udc-core.c @@ -187,9 +187,9 @@ int usb_add_gadget_udc_release(struct device_d *parent, struct usb_gadget *gadge if (ret) goto err2; - dev_add_param_int(&gadget->dev, "product", NULL, NULL, + dev_add_param_uint32(&gadget->dev, "product", NULL, NULL, &gadget->product_id, "0x%04x", NULL); - dev_add_param_int(&gadget->dev, "vendor", NULL, NULL, + dev_add_param_uint32(&gadget->dev, "vendor", NULL, NULL, &gadget->vendor_id, "0x%04x", NULL); gadget->manufacturer = xstrdup("barebox"); dev_add_param_string(&gadget->dev, "manufacturer", NULL, NULL, diff --git a/drivers/video/backlight.c b/drivers/video/backlight.c index ddde6f8523..09c0e47af6 100644 --- a/drivers/video/backlight.c +++ b/drivers/video/backlight.c @@ -70,7 +70,7 @@ int backlight_register(struct backlight_device *bl) if (ret) return ret; - dev_add_param_int(&bl->dev, "brightness", backlight_brightness_set, + dev_add_param_uint32(&bl->dev, "brightness", backlight_brightness_set, NULL, &bl->brightness, "%d", bl); list_add_tail(&bl->list, &backlights); diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c index 7c3a800149..9cc7a911ea 100644 --- a/drivers/video/imx-ipu-fb.c +++ b/drivers/video/imx-ipu-fb.c @@ -978,7 +978,7 @@ static int sdc_fb_register_overlay(struct ipu_fb_info *fbi, void *fb) return ret; } - dev_add_param_int(&overlay->dev, "alpha", sdc_alpha_set, + dev_add_param_uint32(&overlay->dev, "alpha", sdc_alpha_set, NULL, &fbi->alpha, "%u", overlay); return 0; diff --git a/drivers/video/imx.c b/drivers/video/imx.c index 78cb5c0ca2..947f8d5349 100644 --- a/drivers/video/imx.c +++ b/drivers/video/imx.c @@ -530,7 +530,7 @@ static int imxfb_register_overlay(struct imxfb_info *fbi, void *fb) return ret; } - dev_add_param_int(&overlay->dev, "alpha", imxfb_alpha_set, + dev_add_param_uint32(&overlay->dev, "alpha", imxfb_alpha_set, NULL, &fbi->alpha, "%u", overlay); return 0; diff --git a/drivers/video/of_display_timing.c b/drivers/video/of_display_timing.c index 6a5bf62a36..20f9354a18 100644 --- a/drivers/video/of_display_timing.c +++ b/drivers/video/of_display_timing.c @@ -188,22 +188,3 @@ entryfail: return NULL; } EXPORT_SYMBOL_GPL(of_get_display_timings); - -/** - * of_display_timings_exist - check if a display-timings node is provided - * @np: device_node with the timing - **/ -int of_display_timings_exist(struct device_node *np) -{ - struct device_node *timings_np; - - if (!np) - return -EINVAL; - - timings_np = of_parse_phandle(np, "display-timings", 0); - if (!timings_np) - return -EINVAL; - - return 1; -} -EXPORT_SYMBOL_GPL(of_display_timings_exist); diff --git a/dts/Bindings/pci/hisilicon-pcie.txt b/dts/Bindings/pci/hisilicon-pcie.txt index b7fa3b9798..a339dbb154 100644 --- a/dts/Bindings/pci/hisilicon-pcie.txt +++ b/dts/Bindings/pci/hisilicon-pcie.txt @@ -44,13 +44,19 @@ Hip05 Example (note that Hip06 is the same except compatible): }; HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description. + +Some BIOSes place the host controller in a mode where it is ECAM +compliant for all devices other than the root complex. In such cases, +the host controller should be described as below. + The properties and their meanings are identical to those described in host-generic-pci.txt except as listed below. Properties of the host controller node that differ from host-generic-pci.txt: -- compatible : Must be "hisilicon,pcie-almost-ecam" +- compatible : Must be "hisilicon,hip06-pcie-ecam", or + "hisilicon,hip07-pcie-ecam" - reg : Two entries: First the ECAM configuration space for any other bus underneath the root bus. Second, the base @@ -59,7 +65,7 @@ host-generic-pci.txt: Example: pcie0: pcie@a0090000 { - compatible = "hisilicon,pcie-almost-ecam"; + compatible = "hisilicon,hip06-pcie-ecam"; reg = <0 0xb0000000 0 0x2000000>, /* ECAM configuration space */ <0 0xa0090000 0 0x10000>; /* host bridge registers */ bus-range = <0 31>; diff --git a/dts/src/arm/am335x-baltos.dtsi b/dts/src/arm/am335x-baltos.dtsi index efb5eae290..d42b98f15e 100644 --- a/dts/src/arm/am335x-baltos.dtsi +++ b/dts/src/arm/am335x-baltos.dtsi @@ -371,6 +371,8 @@ phy1: ethernet-phy@1 { reg = <7>; + eee-broken-100tx; + eee-broken-1000t; }; }; diff --git a/dts/src/arm/am335x-evmsk.dts b/dts/src/arm/am335x-evmsk.dts index 9e43c44373..9ba4b18c0c 100644 --- a/dts/src/arm/am335x-evmsk.dts +++ b/dts/src/arm/am335x-evmsk.dts @@ -672,6 +672,7 @@ ti,non-removable; bus-width = <4>; cap-power-off-card; + keep-power-in-suspend; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; diff --git a/dts/src/arm/dra7.dtsi b/dts/src/arm/dra7.dtsi index 2c9e56f4aa..bbfb9d5a70 100644 --- a/dts/src/arm/dra7.dtsi +++ b/dts/src/arm/dra7.dtsi @@ -283,6 +283,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x20013000 0x13000 0 0xffed000>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; linux,pci-domain = <0>; @@ -319,6 +320,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x30013000 0x13000 0 0xffed000>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; linux,pci-domain = <1>; diff --git a/dts/src/arm/imx6qdl.dtsi b/dts/src/arm/imx6qdl.dtsi index 8e90014705..6d7bf64961 100644 --- a/dts/src/arm/imx6qdl.dtsi +++ b/dts/src/arm/imx6qdl.dtsi @@ -768,12 +768,6 @@ mask = <0x60>; status = "disabled"; }; - - snvs_lpgpr: snvs-lpgpr { - compatible = "fsl,imx6q-snvs-lpgpr"; - regmap = <&snvs>; - offset = <0x68>; - }; }; epit1: epit@020d0000 { /* EPIT1 */ diff --git a/dts/src/arm/imx6sl.dtsi b/dts/src/arm/imx6sl.dtsi index eeafba04cf..cc9572ea28 100644 --- a/dts/src/arm/imx6sl.dtsi +++ b/dts/src/arm/imx6sl.dtsi @@ -655,12 +655,6 @@ mask = <0x60>; status = "disabled"; }; - - snvs_lpgpr: snvs-lpgpr { - compatible = "fsl,imx6sl-snvs-lpgpr"; - regmap = <&snvs>; - offset = <0x68>; - }; }; epit1: epit@020d0000 { diff --git a/dts/src/arm/logicpd-torpedo-som.dtsi b/dts/src/arm/logicpd-torpedo-som.dtsi index 8f9a69ca81..efe53998c9 100644 --- a/dts/src/arm/logicpd-torpedo-som.dtsi +++ b/dts/src/arm/logicpd-torpedo-som.dtsi @@ -121,7 +121,7 @@ &i2c3 { clock-frequency = <400000>; at24@50 { - compatible = "at24,24c02"; + compatible = "atmel,24c64"; readonly; reg = <0x50>; }; diff --git a/dts/src/arm/sun8i-a33.dtsi b/dts/src/arm/sun8i-a33.dtsi index 0467fb365b..306af6cadf 100644 --- a/dts/src/arm/sun8i-a33.dtsi +++ b/dts/src/arm/sun8i-a33.dtsi @@ -66,12 +66,6 @@ opp-microvolt = <1200000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - - opp@1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1320000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; }; cpus { @@ -81,16 +75,22 @@ operating-points-v2 = <&cpu0_opp_table>; }; + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + }; + cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + operating-points-v2 = <&cpu0_opp_table>; }; }; diff --git a/dts/src/arm64/allwinner/sun50i-a64.dtsi b/dts/src/arm64/allwinner/sun50i-a64.dtsi index 1c64ea2d23..0565779e66 100644 --- a/dts/src/arm64/allwinner/sun50i-a64.dtsi +++ b/dts/src/arm64/allwinner/sun50i-a64.dtsi @@ -179,8 +179,10 @@ usbphy: phy@01c19400 { compatible = "allwinner,sun50i-a64-usb-phy"; reg = <0x01c19400 0x14>, + <0x01c1a800 0x4>, <0x01c1b800 0x4>; reg-names = "phy_ctrl", + "pmu0", "pmu1"; clocks = <&ccu CLK_USB_PHY0>, <&ccu CLK_USB_PHY1>; diff --git a/images/Makefile.imx b/images/Makefile.imx index 2563779484..cdad2e0b88 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -49,6 +49,22 @@ pblx-$(CONFIG_MACH_PCM038) += start_phytec_phycore_imx27 FILE_barebox-phytec-phycore-imx27.img = start_phytec_phycore_imx27.pblx image-$(CONFIG_MACH_PCM038) += barebox-phytec-phycore-imx27.img +# ----------------------- i.MX50 based boards --------------------------- +pblx-$(CONFIG_MACH_KINDLE_MX50) += start_imx50_kindle_d01100 +CFG_start_imx50_kindle_d01100.pblx.imximg = $(board)/kindle-mx50/flash-header-kindle-lpddr1.imxcfg +FILE_barebox-kindle-d01100.img = start_imx50_kindle_d01100.pblx.imximg +imx-barebox-$(CONFIG_MACH_KINDLE_MX50) += barebox-kindle-d01100.img + +pblx-$(CONFIG_MACH_KINDLE_MX50) += start_imx50_kindle_d01200 +CFG_start_imx50_kindle_d01200.pblx.imximg = $(board)/kindle-mx50/flash-header-kindle-lpddr1.imxcfg +FILE_barebox-kindle-d01200.img = start_imx50_kindle_d01200.pblx.imximg +imx-barebox-$(CONFIG_MACH_KINDLE_MX50) += barebox-kindle-d01200.img + +pblx-$(CONFIG_MACH_KINDLE_MX50) += start_imx50_kindle_ey21 +CFG_start_imx50_kindle_ey21.pblx.imximg = $(board)/kindle-mx50/flash-header-kindle-lpddr2.imxcfg +FILE_barebox-kindle-ey21.img = start_imx50_kindle_ey21.pblx.imximg +imx-barebox-$(CONFIG_MACH_KINDLE_MX50) += barebox-kindle-ey21.img + # ----------------------- i.MX51 based boards --------------------------- pblx-$(CONFIG_MACH_FREESCALE_MX51_PDK) += start_imx51_babbage CFG_start_imx51_babbage.pblx.imximg = $(board)/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg @@ -249,16 +265,16 @@ CFG_start_imx6sx_sabresdb.pblx.imximg = $(board)/freescale-mx6sx-sabresdb/flash- FILE_barebox-freescale-imx6sx-sabresdb.img = start_imx6sx_sabresdb.pblx.imximg image-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += barebox-freescale-imx6sx-sabresdb.img -pblx-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += start_hummingboard_microsom_i1 -CFG_start_hummingboard_microsom_i1.pblx.imximg = $(board)/solidrun-microsom/flash-header-microsom-i1.imxcfg -FILE_barebox-solidrun-hummingboard-microsom-i1.img = start_hummingboard_microsom_i1.pblx.imximg -image-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += barebox-solidrun-hummingboard-microsom-i1.img - pblx-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += start_imx6_wandboard CFG_start_imx6_wandboard.imx-sram-img = $(board)/technexion-wandboard/flash-header-technexion-wandboard.imxcfg FILE_barebox-imx6-wandboard.img = start_imx6_wandboard.imx-sram-img image-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += barebox-imx6-wandboard.img +pblx-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += start_hummingboard_microsom_i1 +CFG_start_hummingboard_microsom_i1.pblx.imximg = $(board)/solidrun-microsom/flash-header-microsom-i1.imxcfg +FILE_barebox-solidrun-hummingboard-microsom-i1.img = start_hummingboard_microsom_i1.pblx.imximg +image-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += barebox-solidrun-hummingboard-microsom-i1.img + pblx-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += start_hummingboard_microsom_i2 CFG_start_hummingboard_microsom_i2.pblx.imximg = $(board)/solidrun-microsom/flash-header-microsom-i2.imxcfg FILE_barebox-solidrun-hummingboard-microsom-i2.img = start_hummingboard_microsom_i2.pblx.imximg @@ -274,6 +290,26 @@ CFG_start_hummingboard_microsom_i4.pblx.imximg = $(board)/solidrun-microsom/flas FILE_barebox-solidrun-hummingboard-microsom-i4.img = start_hummingboard_microsom_i4.pblx.imximg image-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += barebox-solidrun-hummingboard-microsom-i4.img +pblx-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += start_hummingboard2_microsom_i1 +CFG_start_hummingboard2_microsom_i1.pblx.imximg = $(board)/solidrun-microsom/flash-header-microsom-i1.imxcfg +FILE_barebox-solidrun-hummingboard2-microsom-i1.img = start_hummingboard2_microsom_i1.pblx.imximg +image-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += barebox-solidrun-hummingboard2-microsom-i1.img + +pblx-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += start_hummingboard2_microsom_i2 +CFG_start_hummingboard2_microsom_i2.pblx.imximg = $(board)/solidrun-microsom/flash-header-microsom-i2.imxcfg +FILE_barebox-solidrun-hummingboard2-microsom-i2.img = start_hummingboard2_microsom_i2.pblx.imximg +image-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += barebox-solidrun-hummingboard2-microsom-i2.img + +pblx-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += start_hummingboard2_microsom_i2ex +CFG_start_hummingboard2_microsom_i2ex.pblx.imximg = $(board)/solidrun-microsom/flash-header-microsom-i2eX.imxcfg +FILE_barebox-solidrun-hummingboard2-microsom-i2eX.img = start_hummingboard2_microsom_i2ex.pblx.imximg +image-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += barebox-solidrun-hummingboard2-microsom-i2eX.img + +pblx-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += start_hummingboard2_microsom_i4 +CFG_start_hummingboard2_microsom_i4.pblx.imximg = $(board)/solidrun-microsom/flash-header-microsom-i4.imxcfg +FILE_barebox-solidrun-hummingboard2-microsom-i4.img = start_hummingboard2_microsom_i4.pblx.imximg +image-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += barebox-solidrun-hummingboard2-microsom-i4.img + pblx-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += start_h100_microsom_i2ex CFG_start_h100_microsom_i2ex.pblx.imximg = $(board)/solidrun-microsom/flash-header-microsom-i2eX.imxcfg FILE_barebox-auvidea-h100-microsom-i2eX.img = start_h100_microsom_i2ex.pblx.imximg diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga index 21804d93df..60b98d1ef2 100644 --- a/images/Makefile.socfpga +++ b/images/Makefile.socfpga @@ -4,8 +4,11 @@ # %.socfpgaimg - convert into socfpga image # ---------------------------------------------------------------- +SOCFPGA_IMAGE_ARGS-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += -v1 +SOCFPGA_IMAGE_ARGS-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += -v0 + quiet_cmd_socfpga_image = SOCFPGA-IMG $@ - cmd_socfpga_image = scripts/socfpga_mkimage -o $@ $< + cmd_socfpga_image = scripts/socfpga_mkimage -o $@ $(SOCFPGA_IMAGE_ARGS-y) $< $(obj)/%.socfpgaimg: $(obj)/% FORCE $(call if_changed,socfpga_image) @@ -27,6 +30,10 @@ pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += start_socfpga_de0_nano_soc FILE_barebox-socfpga-de0_nano_soc.img = start_socfpga_de0_nano_soc.pblx socfpga-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += barebox-socfpga-de0_nano_soc.img +pblx-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += start_socfpga_achilles +FILE_barebox-socfpga-achilles.img = start_socfpga_achilles.pblx.socfpgaimg +socfpga-barebox-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += barebox-socfpga-achilles.img + pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += start_socfpga_sockit_xload FILE_barebox-socfpga-sockit-xload.img = start_socfpga_sockit_xload.pblx.socfpgaimg socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit-xload.img diff --git a/include/console.h b/include/console.h index 126c2e8aa3..724168e07c 100644 --- a/include/console.h +++ b/include/console.h @@ -53,7 +53,7 @@ struct console_device { struct list_head list; unsigned char f_active; - char active[4]; + char *active_string; unsigned int open_count; diff --git a/include/globalvar.h b/include/globalvar.h index df43f1fe66..aea43b193d 100644 --- a/include/globalvar.h +++ b/include/globalvar.h @@ -15,10 +15,9 @@ void globalvar_remove(const char *name); char *globalvar_get_match(const char *match, const char *separator); void globalvar_set_match(const char *match, const char *val); -int globalvar_add_simple_string(const char *name, char **value); -int globalvar_add_simple_int(const char *name, int *value, - const char *format); -int globalvar_add_simple_bool(const char *name, int *value); +int __globalvar_add_simple_string(const char *name, char **value); +int __globalvar_add_simple_int(const char *name, void *value, + enum param_type type, const char *format); int globalvar_add_simple_enum(const char *name, int *value, const char * const *names, int max); int globalvar_add_simple_bitmask(const char *name, unsigned long *value, @@ -39,19 +38,13 @@ static inline int globalvar_add_simple(const char *name, const char *value) return 0; } -static inline int globalvar_add_simple_string(const char *name, char **value) +static inline int __globalvar_add_simple_int(const char *name, void *value, + enum param_type type, const char *format) { return 0; } -static inline int globalvar_add_simple_int(const char *name, - int *value, const char *format) -{ - return 0; -} - -static inline int globalvar_add_simple_bool(const char *name, - int *value) +static inline int __globalvar_add_simple_string(const char *name, char **value) { return 0; } @@ -115,6 +108,96 @@ static inline void dev_param_init_from_nv(struct device_d *dev, const char *name #endif +#define DECLARE_GLOBALVAR_INT(intname, inttype, paramtype) \ + static inline int globalvar_add_simple_##intname(const char *name, \ + inttype *value, \ + const char *format) \ + { \ + return __globalvar_add_simple_int(name, value, \ + paramtype, \ + format); \ + } + +DECLARE_GLOBALVAR_INT(uint32, uint32_t, PARAM_TYPE_UINT32) +DECLARE_GLOBALVAR_INT(int32, int32_t, PARAM_TYPE_INT32) +DECLARE_GLOBALVAR_INT(uint64, uint64_t, PARAM_TYPE_UINT64) +DECLARE_GLOBALVAR_INT(int64, int64_t, PARAM_TYPE_INT64) + +static inline int globalvar_add_simple_bool(const char *name, uint32_t *value) +{ + return __globalvar_add_simple_int(name, value, PARAM_TYPE_BOOL, "%u"); +} + +static inline int globalvar_add_simple_string(const char *name, char **value) +{ + return __globalvar_add_simple_string(name, value); +} + +#define DECLARE_GLOBALVAR_INT_RO(intname, inttype, paramtype) \ + static inline int globalvar_add_simple_##intname##_ro(const char *name, \ + inttype *value, \ + const char *format) \ + { \ + return PTR_ERR_OR_ZERO(__dev_add_param_int(&global_device, name,\ + param_set_readonly, \ + NULL, value, \ + paramtype, \ + format, NULL)); \ + } + +DECLARE_GLOBALVAR_INT_RO(uint32, uint32_t, PARAM_TYPE_UINT32) +DECLARE_GLOBALVAR_INT_RO(int32, int32_t, PARAM_TYPE_INT32) +DECLARE_GLOBALVAR_INT_RO(uint64, uint64_t, PARAM_TYPE_UINT64) +DECLARE_GLOBALVAR_INT_RO(int64, int64_t, PARAM_TYPE_INT64) + +static inline int globalvar_add_simple_bool_ro(const char *name, uint32_t *value) +{ + return PTR_ERR_OR_ZERO(__dev_add_param_int(&global_device, name, + param_set_readonly, NULL, + value, PARAM_TYPE_BOOL, "%u", + NULL)); +} + +static inline int globalvar_add_simple_string_ro(const char *name, char **value) +{ + return __globalvar_add_simple_string(name, value); +} + +#define DECLARE_GLOBALVAR_INT_FIXED(intname, inttype, paramtype) \ + static inline int globalvar_add_simple_##intname##_fixed(const char *name, \ + inttype value, \ + const char *format) \ + { \ + return PTR_ERR_OR_ZERO(__dev_add_param_int(&global_device, name, \ + ERR_PTR(-EROFS), NULL, \ + &value, paramtype, \ + format, NULL)); \ + } + +DECLARE_GLOBALVAR_INT_FIXED(uint32, uint32_t, PARAM_TYPE_UINT32) +DECLARE_GLOBALVAR_INT_FIXED(int32, int32_t, PARAM_TYPE_INT32) +DECLARE_GLOBALVAR_INT_FIXED(uint64, uint64_t, PARAM_TYPE_UINT64) +DECLARE_GLOBALVAR_INT_FIXED(int64, int64_t, PARAM_TYPE_INT64) + +static inline int globalvar_add_simple_bool_fixed(const char *name, uint32_t value) +{ + return PTR_ERR_OR_ZERO(__dev_add_param_int(&global_device, name, ERR_PTR(-EROFS), + NULL, &value, PARAM_TYPE_BOOL, "%u", + NULL)); +} + +static inline int globalvar_add_simple_string_fixed(const char *name, char *value) +{ + return PTR_ERR_OR_ZERO(dev_add_param_string_fixed(&global_device, name, value)); +} + +static inline int globalvar_add_simple_enum_ro(const char *name, int *value, + const char * const *names, int max) +{ + return PTR_ERR_OR_ZERO(dev_add_param_enum_ro(&global_device, name, value, names, + max)); +} + void nv_var_set_clean(void); int nvvar_save(void); int nv_global_complete(struct string_list *sl, char *instr); diff --git a/include/libgen.h b/include/libgen.h index cd27fd11e3..71f06eb6f6 100644 --- a/include/libgen.h +++ b/include/libgen.h @@ -2,6 +2,7 @@ #define __LIBGEN_H char *basename (char *path); +char *posix_basename(char *path); char *dirname (char *path); #endif /* __LIBGEN_H */ diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 945e063f02..b4d2f09081 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -92,6 +92,7 @@ void __noreturn panic(const char *fmt, ...); extern unsigned long simple_strtoul(const char *,char **,unsigned int); extern long simple_strtol(const char *,char **,unsigned int); extern unsigned long long simple_strtoull(const char *,char **,unsigned int); +extern long long simple_strtoll(const char *,char **,unsigned int); /* * min()/max()/clamp() macros that also do diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index fa35c7ef39..16725ac4bc 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -226,6 +226,7 @@ struct mtd_info { struct list_head partitions; struct list_head partitions_entry; + char *partition_string; char *of_path; unsigned int of_binding; diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 66c936ee70..27538c3f42 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -540,6 +540,7 @@ struct nand_chip { struct nand_bbt_descr *badblock_pattern; void *priv; + unsigned int bbt_type; }; /* diff --git a/include/param.h b/include/param.h index 23abb52406..9637229838 100644 --- a/include/param.h +++ b/include/param.h @@ -10,9 +10,22 @@ struct device_d; typedef uint32_t IPaddr_t; +enum param_type { + PARAM_TYPE_STRING = 0, + PARAM_TYPE_INT32, + PARAM_TYPE_UINT32, + PARAM_TYPE_INT64, + PARAM_TYPE_UINT64, + PARAM_TYPE_BOOL, + PARAM_TYPE_ENUM, + PARAM_TYPE_BITMASK, + PARAM_TYPE_IPV4, + PARAM_TYPE_MAC, +}; + struct param_d { - const char* (*get)(struct device_d *, struct param_d *param); - int (*set)(struct device_d *, struct param_d *param, const char *val); + const char* (*get)(struct param_d *param); + int (*set)(struct param_d *param, const char *val); void (*info)(struct param_d *param); unsigned int flags; char *name; @@ -20,16 +33,18 @@ struct param_d { struct device_d *dev; void *driver_priv; struct list_head list; + enum param_type type; }; #ifdef CONFIG_PARAMETER +const char *get_param_type(struct param_d *param); const char *dev_get_param(struct device_d *dev, const char *name); int dev_set_param(struct device_d *dev, const char *name, const char *val); struct param_d *get_param_by_name(struct device_d *dev, const char *name); struct param_d *dev_add_param(struct device_d *dev, const char *name, - int (*set)(struct device_d *dev, struct param_d *p, const char *val), - const char *(*get)(struct device_d *, struct param_d *p), + int (*set)(struct param_d *p, const char *val), + const char *(*get)(struct param_d *p), unsigned long flags); struct param_d *dev_add_param_string(struct device_d *dev, const char *name, @@ -37,15 +52,10 @@ struct param_d *dev_add_param_string(struct device_d *dev, const char *name, int (*get)(struct param_d *p, void *priv), char **value, void *priv); -struct param_d *dev_add_param_int(struct device_d *dev, const char *name, - int (*set)(struct param_d *p, void *priv), - int (*get)(struct param_d *p, void *priv), - int *value, const char *format, void *priv); - -struct param_d *dev_add_param_bool(struct device_d *dev, const char *name, +struct param_d *__dev_add_param_int(struct device_d *dev, const char *name, int (*set)(struct param_d *p, void *priv), int (*get)(struct param_d *p, void *priv), - int *value, void *priv); + void *value, enum param_type type, const char *format, void *priv); struct param_d *dev_add_param_enum(struct device_d *dev, const char *name, int (*set)(struct param_d *p, void *priv), @@ -57,12 +67,6 @@ struct param_d *dev_add_param_bitmask(struct device_d *dev, const char *name, int (*get)(struct param_d *p, void *priv), unsigned long *value, const char * const *names, int max, void *priv); -struct param_d *dev_add_param_int_ro(struct device_d *dev, const char *name, - int value, const char *format); - -struct param_d *dev_add_param_llint_ro(struct device_d *dev, const char *name, - long long value, const char *format); - struct param_d *dev_add_param_ip(struct device_d *dev, const char *name, int (*set)(struct param_d *p, void *priv), int (*get)(struct param_d *p, void *priv), @@ -73,14 +77,13 @@ struct param_d *dev_add_param_mac(struct device_d *dev, const char *name, int (*get)(struct param_d *p, void *priv), u8 *mac, void *priv); -int dev_add_param_fixed(struct device_d *dev, const char *name, const char *value); +struct param_d *dev_add_param_fixed(struct device_d *dev, const char *name, const char *value); void dev_remove_param(struct param_d *p); void dev_remove_parameters(struct device_d *dev); -int dev_param_set_generic(struct device_d *dev, struct param_d *p, - const char *val); +int dev_param_set_generic(struct param_d *p, const char *val); #else static inline const char *dev_get_param(struct device_d *dev, const char *name) @@ -114,10 +117,10 @@ static inline struct param_d *dev_add_param_string(struct device_d *dev, const c return ERR_PTR(-ENOSYS); } -static inline struct param_d *dev_add_param_int(struct device_d *dev, const char *name, +static inline struct param_d *__dev_add_param_int(struct device_d *dev, const char *name, int (*set)(struct param_d *p, void *priv), int (*get)(struct param_d *p, void *priv), - int *value, const char *format, void *priv) + void *value, enum param_type type, const char *format, void *priv) { return ERR_PTR(-ENOSYS); } @@ -139,56 +142,162 @@ static inline struct param_d *dev_add_param_bitmask(struct device_d *dev, const return ERR_PTR(-ENOSYS); } -static inline struct param_d *dev_add_param_bool(struct device_d *dev, const char *name, +static inline struct param_d *dev_add_param_ip(struct device_d *dev, const char *name, int (*set)(struct param_d *p, void *priv), int (*get)(struct param_d *p, void *priv), - int *value, void *priv) + IPaddr_t *ip, void *priv) { return ERR_PTR(-ENOSYS); } -static inline struct param_d *dev_add_param_int_ro(struct device_d *dev, const char *name, - int value, const char *format) +static inline struct param_d *dev_add_param_mac(struct device_d *dev, const char *name, + int (*set)(struct param_d *p, void *priv), + int (*get)(struct param_d *p, void *priv), + u8 *mac, void *priv) { return ERR_PTR(-ENOSYS); } -static inline struct param_d *dev_add_param_llint_ro(struct device_d *dev, const char *name, - long long value, const char *format) +static inline struct param_d *dev_add_param_fixed(struct device_d *dev, const char *name, + const char *value) { return ERR_PTR(-ENOSYS); } -static inline struct param_d *dev_add_param_ip(struct device_d *dev, const char *name, +static inline void dev_remove_param(struct param_d *p) {} + +static inline void dev_remove_parameters(struct device_d *dev) {} + +static inline int dev_param_set_generic(struct device_d *dev, struct param_d *p, + const char *val) +{ + return 0; +} +#endif + +int param_set_readonly(struct param_d *p, void *priv); + +/* + * dev_add_param_int + * dev_add_param_int32 + * dev_add_param_uint32 + * dev_add_param_int64 + * dev_add_param_uint64 + */ +#define DECLARE_PARAM_INT(intname, inttype, paramtype) \ + static inline struct param_d *dev_add_param_##intname(struct device_d *dev, const char *name, \ + int (*set)(struct param_d *p, void *priv), \ + int (*get)(struct param_d *p, void *priv), \ + inttype *value, const char *format, void *priv) \ + { \ + return __dev_add_param_int(dev, name, set, get, value, paramtype, format, priv); \ + } + +DECLARE_PARAM_INT(int, int, PARAM_TYPE_INT32) +DECLARE_PARAM_INT(int32, int32_t, PARAM_TYPE_INT32) +DECLARE_PARAM_INT(uint32, uint32_t, PARAM_TYPE_UINT32) +DECLARE_PARAM_INT(int64, int64_t, PARAM_TYPE_INT64) +DECLARE_PARAM_INT(uint64, uint64_t, PARAM_TYPE_UINT64) + +/* + * dev_add_param_int_fixed + * dev_add_param_int32_fixed + * dev_add_param_uint32_fixed + * dev_add_param_int64_fixed + * dev_add_param_uint64_fixed + */ +#define DECLARE_PARAM_INT_FIXED(intname, inttype, paramtype) \ + static inline struct param_d *dev_add_param_##intname##_fixed(struct device_d *dev, const char *name, \ + inttype value, const char *format) \ + { \ + return __dev_add_param_int(dev, name, ERR_PTR(-EROFS), NULL, &value, paramtype, format, NULL); \ + } + +DECLARE_PARAM_INT_FIXED(int, int, PARAM_TYPE_INT32) +DECLARE_PARAM_INT_FIXED(int32, int32_t, PARAM_TYPE_INT32) +DECLARE_PARAM_INT_FIXED(uint32, uint32_t, PARAM_TYPE_UINT32) +DECLARE_PARAM_INT_FIXED(int64, int64_t, PARAM_TYPE_INT64) +DECLARE_PARAM_INT_FIXED(uint64, uint64_t, PARAM_TYPE_UINT64) + +/* + * dev_add_param_int_ro + * dev_add_param_int32_ro + * dev_add_param_uint32_ro + * dev_add_param_int64_ro + * dev_add_param_uint64_ro + */ +#define DECLARE_PARAM_INT_RO(intname, inttype, paramtype) \ + static inline struct param_d *dev_add_param_##intname##_ro(struct device_d *dev, const char *name, \ + inttype *value, const char *format) \ + { \ + return __dev_add_param_int(dev, name, param_set_readonly, NULL, value, paramtype, format, NULL); \ + } + +DECLARE_PARAM_INT_RO(int, int, PARAM_TYPE_INT32) +DECLARE_PARAM_INT_RO(int32, int32_t, PARAM_TYPE_INT32) +DECLARE_PARAM_INT_RO(uint32, uint32_t, PARAM_TYPE_UINT32) +DECLARE_PARAM_INT_RO(int64, int64_t, PARAM_TYPE_INT64) +DECLARE_PARAM_INT_RO(uint64, uint64_t, PARAM_TYPE_UINT64) + +static inline struct param_d *dev_add_param_bool(struct device_d *dev, const char *name, int (*set)(struct param_d *p, void *priv), int (*get)(struct param_d *p, void *priv), - IPaddr_t *ip, void *priv) + uint32_t *value, void *priv) { - return ERR_PTR(-ENOSYS); + return __dev_add_param_int(dev, name, set, get, value, PARAM_TYPE_BOOL, "%u", priv); } -static inline struct param_d *dev_add_param_mac(struct device_d *dev, const char *name, +static inline struct param_d *dev_add_param_bool_fixed(struct device_d *dev, const char *name, + uint32_t value) +{ + return __dev_add_param_int(dev, name, ERR_PTR(-EROFS), NULL, &value, PARAM_TYPE_BOOL, + "%u", NULL); +} + +static inline struct param_d *dev_add_param_bool_ro(struct device_d *dev, const char *name, + uint32_t *value) +{ + return __dev_add_param_int(dev, name, param_set_readonly, NULL, value, PARAM_TYPE_BOOL, + "%u", NULL); +} + +static inline struct param_d *dev_add_param_string_ro(struct device_d *dev, const char *name, int (*set)(struct param_d *p, void *priv), int (*get)(struct param_d *p, void *priv), - u8 *mac, void *priv) + char **value, void *priv) { - return ERR_PTR(-ENOSYS); + return dev_add_param_string(dev, name, param_set_readonly, NULL, value, NULL); } -static inline int dev_add_param_fixed(struct device_d *dev, const char *name, const char *value) +static inline struct param_d *dev_add_param_string_fixed(struct device_d *dev, const char *name, + char *value) { - return 0; + return dev_add_param_fixed(dev, name, value); } -static inline void dev_remove_param(struct param_d *p) {} - -static inline void dev_remove_parameters(struct device_d *dev) {} +static inline struct param_d *dev_add_param_enum_ro(struct device_d *dev, const char *name, + int *value, const char * const *names, int max) +{ + return dev_add_param_enum(dev, name, param_set_readonly, NULL, + value, names, max, NULL); +} -static inline int dev_param_set_generic(struct device_d *dev, struct param_d *p, - const char *val) +static inline struct param_d *dev_add_param_bitmask_ro(struct device_d *dev, const char *name, + int (*set)(struct param_d *p, void *priv), + int (*get)(struct param_d *p, void *priv), + unsigned long *value, const char * const *names, int max, void *priv) { - return 0; + return dev_add_param_bitmask(dev, name, param_set_readonly, NULL, + value, names, max, NULL); } -#endif +/* + * unimplemented: + * dev_add_param_enum_fixed + * dev_add_param_bitmask_fixed + * dev_add_param_ip_ro + * dev_add_param_ip_fixed + * dev_add_param_mac_ro + * dev_add_param_mac_fixed + */ #endif /* PARAM_H */ diff --git a/include/platform_data/cadence_qspi.h b/include/platform_data/cadence_qspi.h index 4930edce50..ad1a680c9f 100644 --- a/include/platform_data/cadence_qspi.h +++ b/include/platform_data/cadence_qspi.h @@ -2,7 +2,7 @@ #define __INCLUDE_PLATFORM_DATA_CADENCE_QSPI_H struct cadence_qspi_platform_data { - unsigned int ext_decoder; + unsigned int is_decoded_cs; unsigned int fifo_depth; }; diff --git a/lib/libgen.c b/lib/libgen.c index 1e43cf3f29..08ef3528af 100644 --- a/lib/libgen.c +++ b/lib/libgen.c @@ -37,6 +37,29 @@ char *basename (char *path) } EXPORT_SYMBOL(basename); +/* + * There are two different versions of basename(): The GNU version implemented + * above and the POSIX version. The GNU version never modifies its argument and + * returns the empty string when path has a trailing slash, and in particular + * also when it is "/". + */ +char *posix_basename(char *path) +{ + char *fname; + + fname = path + strlen(path) - 1; + + while (*fname == '/') { + if (fname == path) + return path; + *fname = '\0'; + fname--; + } + + return basename(path); +} +EXPORT_SYMBOL(posix_basename); + char *dirname (char *path) { char *fname; diff --git a/lib/parameter.c b/lib/parameter.c index 65d6c7c0df..ab36b15591 100644 --- a/lib/parameter.c +++ b/lib/parameter.c @@ -31,6 +31,24 @@ #include <globalvar.h> #include <linux/err.h> +static const char *param_type_string[] = { + [PARAM_TYPE_STRING] = "string", + [PARAM_TYPE_INT32] = "int32", + [PARAM_TYPE_UINT32] = "uint32", + [PARAM_TYPE_INT64] = "int64", + [PARAM_TYPE_UINT64] = "uint64", + [PARAM_TYPE_BOOL] = "bool", + [PARAM_TYPE_ENUM] = "enum", + [PARAM_TYPE_BITMASK] = "bitmask", + [PARAM_TYPE_IPV4] = "ipv4", + [PARAM_TYPE_MAC] = "MAC", +}; + +const char *get_param_type(struct param_d *param) +{ + return param_type_string[param->type]; +} + struct param_d *get_param_by_name(struct device_d *dev, const char *name) { struct param_d *p; @@ -58,7 +76,7 @@ const char *dev_get_param(struct device_d *dev, const char *name) return NULL; } - return param->get(dev, param); + return param->get(param); } /** @@ -89,7 +107,7 @@ int dev_set_param(struct device_d *dev, const char *name, const char *val) return -EACCES; } - ret = param->set(dev, param, val); + ret = param->set(param, val); if (ret) errno = -ret; @@ -107,7 +125,7 @@ int dev_set_param(struct device_d *dev, const char *name, const char *val) * used during deregistration of the parameter to free the alloctated * memory. */ -int dev_param_set_generic(struct device_d *dev, struct param_d *p, +int dev_param_set_generic(struct param_d *p, const char *val) { free(p->value); @@ -119,7 +137,7 @@ int dev_param_set_generic(struct device_d *dev, struct param_d *p, return p->value ? 0 : -ENOMEM; } -static const char *param_get_generic(struct device_d *dev, struct param_d *p) +static const char *param_get_generic(struct param_d *p) { return p->value ? p->value : ""; } @@ -133,8 +151,8 @@ static int compare(struct list_head *a, struct list_head *b) } static int __dev_add_param(struct param_d *param, struct device_d *dev, const char *name, - int (*set)(struct device_d *dev, struct param_d *p, const char *val), - const char *(*get)(struct device_d *dev, struct param_d *p), + int (*set)(struct param_d *p, const char *val), + const char *(*get)(struct param_d *p), unsigned long flags) { if (get_param_by_name(dev, name)) @@ -176,8 +194,8 @@ static int __dev_add_param(struct param_d *param, struct device_d *dev, const ch * not use static arrays when using the generic functions. */ struct param_d *dev_add_param(struct device_d *dev, const char *name, - int (*set)(struct device_d *dev, struct param_d *p, const char *val), - const char *(*get)(struct device_d *dev, struct param_d *param), + int (*set)(struct param_d *p, const char *val), + const char *(*get)(struct param_d *param), unsigned long flags) { struct param_d *param; @@ -200,7 +218,7 @@ struct param_d *dev_add_param(struct device_d *dev, const char *name, * @param name The name of the parameter * @param value The value of the parameter */ -int dev_add_param_fixed(struct device_d *dev, const char *name, const char *value) +struct param_d *dev_add_param_fixed(struct device_d *dev, const char *name, const char *value) { struct param_d *param; int ret; @@ -210,12 +228,12 @@ int dev_add_param_fixed(struct device_d *dev, const char *name, const char *valu ret = __dev_add_param(param, dev, name, NULL, NULL, PARAM_FLAG_RO); if (ret) { free(param); - return ret; + return ERR_PTR(ret); } param->value = strdup(value); - return 0; + return param; } struct param_string { @@ -230,7 +248,7 @@ static inline struct param_string *to_param_string(struct param_d *p) return container_of(p, struct param_string, param); } -static int param_string_set(struct device_d *dev, struct param_d *p, const char *val) +static int param_string_set(struct param_d *p, const char *val) { struct param_string *ps = to_param_string(p); int ret; @@ -255,7 +273,7 @@ static int param_string_set(struct device_d *dev, struct param_d *p, const char return ret; } -static const char *param_string_get(struct device_d *dev, struct param_d *p) +static const char *param_string_get(struct param_d *p) { struct param_string *ps = to_param_string(p); int ret; @@ -284,6 +302,7 @@ struct param_d *dev_add_param_string(struct device_d *dev, const char *name, ps->get = get; p = &ps->param; p->driver_priv = priv; + p->type = PARAM_TYPE_STRING; ret = __dev_add_param(p, dev, name, param_string_set, param_string_get, 0); if (ret) { @@ -296,10 +315,9 @@ struct param_d *dev_add_param_string(struct device_d *dev, const char *name, struct param_int { struct param_d param; - int *value; + void *value; + int dsize; const char *format; -#define PARAM_INT_FLAG_BOOL (1 << 0) - unsigned flags; int (*set)(struct param_d *p, void *priv); int (*get)(struct param_d *p, void *priv); }; @@ -309,21 +327,35 @@ static inline struct param_int *to_param_int(struct param_d *p) return container_of(p, struct param_int, param); } -static int param_int_set(struct device_d *dev, struct param_d *p, const char *val) +static int param_int_set(struct param_d *p, const char *val) { struct param_int *pi = to_param_int(p); - int value_save = *pi->value; + u8 value_save[pi->dsize]; int ret; if (!val) return -EINVAL; - if (pi->flags & PARAM_INT_FLAG_BOOL) { + memcpy(value_save, pi->value, pi->dsize); + + switch (p->type) { + case PARAM_TYPE_BOOL: ret = strtobool(val, pi->value); - if (ret) - return ret; - } else { - *pi->value = simple_strtol(val, NULL, 0); + break; + case PARAM_TYPE_INT32: + *(uint32_t *)pi->value = simple_strtol(val, NULL, 0); + break; + case PARAM_TYPE_UINT32: + *(int32_t *)pi->value = simple_strtoul(val, NULL, 0); + break; + case PARAM_TYPE_INT64: + *(int64_t *)pi->value = simple_strtoll(val, NULL, 0); + break; + case PARAM_TYPE_UINT64: + *(uint64_t *)pi->value = simple_strtoull(val, NULL, 0); + break; + default: + return -EINVAL; } if (!pi->set) @@ -331,12 +363,12 @@ static int param_int_set(struct device_d *dev, struct param_d *p, const char *va ret = pi->set(p, p->driver_priv); if (ret) - *pi->value = value_save; + memcpy(pi->value, value_save, pi->dsize); return ret; } -static const char *param_int_get(struct device_d *dev, struct param_d *p) +static const char *param_int_get(struct param_d *p) { struct param_int *pi = to_param_int(p); int ret; @@ -348,11 +380,28 @@ static const char *param_int_get(struct device_d *dev, struct param_d *p) } free(p->value); - p->value = basprintf(pi->format, *pi->value); + switch (p->type) { + case PARAM_TYPE_BOOL: + case PARAM_TYPE_INT32: + case PARAM_TYPE_UINT32: + p->value = basprintf(pi->format, *(int32_t *)pi->value); + break; + case PARAM_TYPE_INT64: + case PARAM_TYPE_UINT64: + p->value = basprintf(pi->format, *(int64_t *)pi->value); + break; + default: + return NULL; + } return p->value; } +int param_set_readonly(struct param_d *p, void *priv) +{ + return -EROFS; +} + /** * dev_add_param_int - add an integer parameter to a device * @param dev The device @@ -360,6 +409,7 @@ static const char *param_int_get(struct device_d *dev, struct param_d *p) * @param set set function * @param get get function * @param value pointer to the integer containing the value of the parameter + * @param type The variable type * @param format the printf format used to print the value * @param priv user private data, will be passed to get/set * @@ -368,22 +418,51 @@ static const char *param_int_get(struct device_d *dev, struct param_d *p) * The set function can be used as a notifer when the variable is about * to be written. Can also be used to limit the value. */ -struct param_d *dev_add_param_int(struct device_d *dev, const char *name, +struct param_d *__dev_add_param_int(struct device_d *dev, const char *name, int (*set)(struct param_d *p, void *priv), int (*get)(struct param_d *p, void *priv), - int *value, const char *format, void *priv) + void *value, enum param_type type, const char *format, void *priv) { struct param_int *pi; struct param_d *p; - int ret; + int ret, dsize; + + switch (type) { + case PARAM_TYPE_BOOL: + dsize = sizeof(uint32_t); + break; + case PARAM_TYPE_INT32: + dsize = sizeof(int32_t); + break; + case PARAM_TYPE_UINT32: + dsize = sizeof(uint32_t); + break; + case PARAM_TYPE_INT64: + dsize = sizeof(int64_t); + break; + case PARAM_TYPE_UINT64: + dsize = sizeof(uint64_t); + break; + default: + return ERR_PTR(-EINVAL); + } pi = xzalloc(sizeof(*pi)); - pi->value = value; + + if (IS_ERR(set)) { + pi->value = xmemdup(value, dsize); + set = param_set_readonly; + } else { + pi->value = value; + } + + pi->dsize = dsize; pi->format = format; pi->set = set; pi->get = get; p = &pi->param; p->driver_priv = priv; + p->type = type; ret = __dev_add_param(p, dev, name, param_int_set, param_int_get, 0); if (ret) { @@ -408,7 +487,7 @@ static inline struct param_enum *to_param_enum(struct param_d *p) return container_of(p, struct param_enum, param); } -static int param_enum_set(struct device_d *dev, struct param_d *p, const char *val) +static int param_enum_set(struct param_d *p, const char *val) { struct param_enum *pe = to_param_enum(p); int value_save = *pe->value; @@ -436,7 +515,7 @@ static int param_enum_set(struct device_d *dev, struct param_d *p, const char *v return ret; } -static const char *param_enum_get(struct device_d *dev, struct param_d *p) +static const char *param_enum_get(struct param_d *p) { struct param_enum *pe = to_param_enum(p); int ret; @@ -465,7 +544,7 @@ static void param_enum_info(struct param_d *p) if (pe->num_names <= 1) return; - printf(" ("); + printf(" (values: "); for (i = 0; i < pe->num_names; i++) { if (!pe->names[i] || !*pe->names[i]) @@ -493,6 +572,7 @@ struct param_d *dev_add_param_enum(struct device_d *dev, const char *name, pe->num_names = num_names; p = &pe->param; p->driver_priv = priv; + p->type = PARAM_TYPE_ENUM; ret = __dev_add_param(p, dev, name, param_enum_set, param_enum_get, 0); if (ret) { @@ -519,7 +599,7 @@ static inline struct param_bitmask *to_param_bitmask(struct param_d *p) return container_of(p, struct param_bitmask, param); } -static int param_bitmask_set(struct device_d *dev, struct param_d *p, const char *val) +static int param_bitmask_set(struct param_d *p, const char *val) { struct param_bitmask *pb = to_param_bitmask(p); void *value_save; @@ -565,7 +645,7 @@ out: return ret; } -static const char *param_bitmask_get(struct device_d *dev, struct param_d *p) +static const char *param_bitmask_get(struct param_d *p) { struct param_bitmask *pb = to_param_bitmask(p); int ret, bit; @@ -622,6 +702,7 @@ struct param_d *dev_add_param_bitmask(struct device_d *dev, const char *name, pb->num_names = max; p = &pb->param; p->driver_priv = priv; + p->type = PARAM_TYPE_BITMASK; for (i = 0; i < pb->num_names; i++) if (pb->names[i]) @@ -640,95 +721,6 @@ struct param_d *dev_add_param_bitmask(struct device_d *dev, const char *name, return &pb->param; } -/** - * dev_add_param_bool - add an boolean parameter to a device - * @param dev The device - * @param name The name of the parameter - * @param set set function - * @param get get function - * @param value pointer to the integer containing the value of the parameter - * @param priv user private data, will be passed to get/set - * - * The get function can be used as a notifier when the variable is about - * to be read. - * The set function can be used as a notifer when the variable is about - * to be written. Can also be used to limit the value. - */ -struct param_d *dev_add_param_bool(struct device_d *dev, const char *name, - int (*set)(struct param_d *p, void *priv), - int (*get)(struct param_d *p, void *priv), - int *value, void *priv) -{ - struct param_int *pi; - struct param_d *p; - - p = dev_add_param_int(dev, name, set, get, value, "%d", priv); - if (IS_ERR(p)) - return p; - - pi = to_param_int(p); - pi->flags |= PARAM_INT_FLAG_BOOL; - - return p; -} - -struct param_int_ro { - struct param_d param; - char *value; -}; - -/** - * dev_add_param_int_ro - add a read only integer parameter to a device - * @param dev The device - * @param name The name of the parameter - * @param value The value of the parameter - * @param format the printf format used to print the value - */ -struct param_d *dev_add_param_int_ro(struct device_d *dev, const char *name, - int value, const char *format) -{ - struct param_int *piro; - int ret; - - piro = xzalloc(sizeof(*piro)); - - ret = __dev_add_param(&piro->param, dev, name, NULL, NULL, PARAM_FLAG_RO); - if (ret) { - free(piro); - return ERR_PTR(ret); - } - - piro->param.value = basprintf(format, value); - - return &piro->param; -} - -/** - * dev_add_param_llint_ro - add a read only long long parameter to a device - * @param dev The device - * @param name The name of the parameter - * @param value The value of the parameter - * @param format the printf format used to print the value - */ -struct param_d *dev_add_param_llint_ro(struct device_d *dev, const char *name, - long long value, const char *format) -{ - struct param_int *piro; - int ret; - - piro = xzalloc(sizeof(*piro)); - - ret = __dev_add_param(&piro->param, dev, name, NULL, NULL, PARAM_FLAG_RO); - if (ret) { - free(piro); - return ERR_PTR(ret); - } - - piro->param.value = basprintf(format, value); - - return &piro->param; -} - struct param_ip { struct param_d param; IPaddr_t *ip; @@ -742,7 +734,7 @@ static inline struct param_ip *to_param_ip(struct param_d *p) return container_of(p, struct param_ip, param); } -static int param_ip_set(struct device_d *dev, struct param_d *p, const char *val) +static int param_ip_set(struct param_d *p, const char *val) { struct param_ip *pi = to_param_ip(p); IPaddr_t ip_save = *pi->ip; @@ -765,7 +757,7 @@ static int param_ip_set(struct device_d *dev, struct param_d *p, const char *val return ret; } -static const char *param_ip_get(struct device_d *dev, struct param_d *p) +static const char *param_ip_get(struct param_d *p) { struct param_ip *pi = to_param_ip(p); int ret; @@ -795,6 +787,7 @@ struct param_d *dev_add_param_ip(struct device_d *dev, const char *name, pi->set = set; pi->get = get; pi->param.driver_priv = priv; + pi->param.type = PARAM_TYPE_IPV4; ret = __dev_add_param(&pi->param, dev, name, param_ip_set, param_ip_get, 0); @@ -823,7 +816,7 @@ static inline struct param_mac *to_param_mac(struct param_d *p) return container_of(p, struct param_mac, param); } -static int param_mac_set(struct device_d *dev, struct param_d *p, const char *val) +static int param_mac_set(struct param_d *p, const char *val) { struct param_mac *pm = to_param_mac(p); char mac_save[6]; @@ -852,7 +845,7 @@ out: return ret; } -static const char *param_mac_get(struct device_d *dev, struct param_d *p) +static const char *param_mac_get(struct param_d *p) { struct param_mac *pm = to_param_mac(p); int ret; @@ -882,6 +875,7 @@ struct param_d *dev_add_param_mac(struct device_d *dev, const char *name, pm->get = get; pm->param.driver_priv = priv; pm->param.value = pm->mac_str; + pm->param.type = PARAM_TYPE_MAC; ret = __dev_add_param(&pm->param, dev, name, param_mac_set, param_mac_get, 0); @@ -900,7 +894,7 @@ struct param_d *dev_add_param_mac(struct device_d *dev, const char *name, */ void dev_remove_param(struct param_d *p) { - p->set(p->dev, p, NULL); + p->set(p, NULL); list_del(&p->list); free(p->name); free(p); @@ -916,7 +910,7 @@ void dev_remove_parameters(struct device_d *dev) struct param_d *p, *n; list_for_each_entry_safe(p, n, &dev->parameters, list) { - p->set(dev, p, NULL); + p->set(p, NULL); list_del(&p->list); free(p->name); free(p); diff --git a/lib/readline_simple.c b/lib/readline_simple.c index c2960665fb..c4d3d240e5 100644 --- a/lib/readline_simple.c +++ b/lib/readline_simple.c @@ -57,19 +57,6 @@ int readline (const char *prompt, char *line, int len) col = plen; for (;;) { -#ifdef CONFIG_BOOT_RETRY_TIME - while (!tstc()) { /* while no incoming data */ - if (retry_time >= 0 && get_ticks() > endtime) - return (-2); /* timed out */ - } -#endif - -#ifdef CONFIG_SHOW_ACTIVITY - while (!tstc()) { - extern void show_activity(int arg); - show_activity(0); - } -#endif c = getchar(); /* diff --git a/lib/strtox.c b/lib/strtox.c index cfe61240cc..4b601a1b39 100644 --- a/lib/strtox.c +++ b/lib/strtox.c @@ -1,67 +1,84 @@ #include <common.h> #include <linux/ctype.h> -unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base) +unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base) { - unsigned long result = 0,value; + unsigned long result = 0, value; if (*cp == '0') { cp++; + if ((*cp == 'x') && isxdigit(cp[1])) { base = 16; cp++; } - if (!base) { + + if (!base) base = 8; - } } - if (!base) { + + if (!base) base = 10; - } - while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) - ? toupper(*cp) : *cp)-'A'+10) < base) { - result = result*base + value; + + while (isxdigit(*cp) && (value = isdigit(*cp) ? + *cp - '0' : toupper(*cp) - 'A' + 10) < base) { + result = result * base + value; cp++; } + if (endp) *endp = (char *)cp; + return result; } EXPORT_SYMBOL(simple_strtoul); -long simple_strtol(const char *cp,char **endp,unsigned int base) +long simple_strtol(const char *cp, char **endp, unsigned int base) { - if(*cp=='-') - return -simple_strtoul(cp+1,endp,base); - return simple_strtoul(cp,endp,base); + if (*cp == '-') + return -simple_strtoul(cp + 1, endp, base); + + return simple_strtoul(cp, endp, base); } EXPORT_SYMBOL(simple_strtol); -unsigned long long simple_strtoull (const char *cp, char **endp, unsigned int base) +unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base) { unsigned long long result = 0, value; if (*cp == '0') { cp++; - if ((*cp == 'x') && isxdigit (cp[1])) { + + if ((*cp == 'x') && isxdigit(cp[1])) { base = 16; cp++; } - if (!base) { + + if (!base) base = 8; - } } - if (!base) { + + if (!base) base = 10; - } - while (isxdigit (*cp) && (value = isdigit (*cp) - ? *cp - '0' - : (islower (*cp) ? toupper (*cp) : *cp) - 'A' + 10) < base) { + + while (isxdigit(*cp) && (value = isdigit(*cp) ? + *cp - '0' : toupper(*cp) - 'A' + 10) < base) { result = result * base + value; cp++; } + if (endp) - *endp = (char *) cp; + *endp = (char *)cp; + return result; } EXPORT_SYMBOL(simple_strtoull); + +long long simple_strtoll(const char *cp, char **endp, unsigned int base) +{ + if (*cp == '-') + return -simple_strtoull(cp + 1, endp, base); + + return simple_strtoull(cp, endp, base); +} +EXPORT_SYMBOL(simple_strtoll); diff --git a/lib/xfuncs.c b/lib/xfuncs.c index 1dc2ea92d8..1bcaa5e10e 100644 --- a/lib/xfuncs.c +++ b/lib/xfuncs.c @@ -18,18 +18,30 @@ * GNU General Public License for more details. * */ +#define pr_fmt(fmt) "xfuncs: " fmt #include <common.h> #include <malloc.h> #include <module.h> #include <wchar.h> +static void __noreturn enomem_panic(size_t size) +{ + pr_emerg("out of memory\n"); + if (size) + pr_emerg("Unable to allocate %d bytes\n", size); + + malloc_stats(); + + panic("out of memory"); +} + void *xmalloc(size_t size) { void *p = NULL; if (!(p = malloc(size))) - panic("ERROR: out of memory\n"); + enomem_panic(size); return p; } @@ -40,7 +52,7 @@ void *xrealloc(void *ptr, size_t size) void *p = NULL; if (!(p = realloc(ptr, size))) - panic("ERROR: out of memory\n"); + enomem_panic(size); return p; } @@ -63,7 +75,7 @@ char *xstrdup(const char *s) p = strdup(s); if (!p) - panic("ERROR: out of memory\n"); + enomem_panic(strlen(s) + 1); return p; } @@ -95,7 +107,8 @@ void* xmemalign(size_t alignment, size_t bytes) { void *p = memalign(alignment, bytes); if (!p) - panic("ERROR: out of memory\n"); + enomem_panic(bytes); + return p; } EXPORT_SYMBOL(xmemalign); @@ -116,7 +129,7 @@ char *xvasprintf(const char *fmt, va_list ap) p = bvasprintf(fmt, ap); if (!p) - panic("ERROR: out of memory\n"); + enomem_panic(0); return p; } EXPORT_SYMBOL(xvasprintf); @@ -139,7 +152,8 @@ wchar_t *xstrdup_wchar(const wchar_t *s) wchar_t *p = strdup_wchar(s); if (!p) - panic("ERROR: out of memory\n"); + enomem_panic((wcslen(s) + 1) * sizeof(wchar_t)); + return p; } EXPORT_SYMBOL(xstrdup_wchar); @@ -149,7 +163,8 @@ wchar_t *xstrdup_char_to_wchar(const char *s) wchar_t *p = strdup_char_to_wchar(s); if (!p) - panic("ERROR: out of memory\n"); + enomem_panic((strlen(s) + 1) * sizeof(wchar_t)); + return p; } EXPORT_SYMBOL(xstrdup_char_to_wchar); @@ -159,7 +174,8 @@ char *xstrdup_wchar_to_char(const wchar_t *s) char *p = strdup_wchar_to_char(s); if (!p) - panic("ERROR: out of memory\n"); + enomem_panic((wcslen(s) + 1) * sizeof(wchar_t)); + return p; } EXPORT_SYMBOL(xstrdup_wchar_to_char); @@ -573,6 +573,9 @@ static struct device_d net_device = { .id = DEVICE_ID_SINGLE, }; +static char *net_nameserver; +static char *net_domainname; + static int net_init(void) { int i; @@ -581,8 +584,12 @@ static int net_init(void) NetRxPackets[i] = net_alloc_packet(); register_device(&net_device); - dev_add_param(&net_device, "nameserver", NULL, NULL, 0); - dev_add_param(&net_device, "domainname", NULL, NULL, 0); + net_nameserver = xstrdup(""); + dev_add_param_string(&net_device, "nameserver", NULL, NULL, + &net_nameserver, NULL); + net_domainname = xstrdup(""); + dev_add_param_string(&net_device, "domainname", NULL, NULL, + &net_domainname, NULL); return 0; } diff --git a/scripts/mkmakefile b/scripts/mkmakefile index 7f9d544f9b..84af27bf0f 100644..100755 --- a/scripts/mkmakefile +++ b/scripts/mkmakefile @@ -11,7 +11,15 @@ test ! -r $2/Makefile -o -O $2/Makefile || exit 0 -echo " GEN $2/Makefile" +# Only overwrite automatically generated Makefiles +# (so we do not overwrite kernel Makefile) +if test -e $2/Makefile && ! grep -q Automatically $2/Makefile +then + exit 0 +fi +if [ "${quiet}" != "silent_" ]; then + echo " GEN $2/Makefile" +fi cat << EOF > $2/Makefile # Automatically generated by $0: don't edit @@ -19,18 +27,26 @@ cat << EOF > $2/Makefile VERSION = $3 PATCHLEVEL = $4 -KERNELSRC := $1 -KERNELOUTPUT := $2 +lastword = \$(word \$(words \$(1)),\$(1)) +makedir := \$(dir \$(call lastword,\$(MAKEFILE_LIST))) -MAKEFLAGS += --no-print-directory +ifeq ("\$(origin V)", "command line") +VERBOSE := \$(V) +endif +ifneq (\$(VERBOSE),1) +Q := @ +endif + +MAKEARGS := -C $1 +MAKEARGS += O=\$(if \$(patsubst /%,,\$(makedir)),\$(CURDIR)/)\$(patsubst %/,%,\$(makedir)) -.PHONY: all \$(MAKECMDGOALS) +MAKEFLAGS += --no-print-directory -all: - \$(MAKE) -C \$(KERNELSRC) O=\$(KERNELOUTPUT) +.PHONY: __sub-make \$(MAKECMDGOALS) -Makefile:; +__sub-make: + \$(Q)\$(MAKE) \$(MAKEARGS) \$(MAKECMDGOALS) -\$(filter-out all Makefile,\$(MAKECMDGOALS)) %/: - \$(MAKE) -C \$(KERNELSRC) O=\$(KERNELOUTPUT) \$@ +\$(filter-out __sub-make, \$(MAKECMDGOALS)): __sub-make + @: EOF diff --git a/scripts/socfpga_import_preloader b/scripts/socfpga_import_preloader index b08262cb6c..63ff30ec2a 100755 --- a/scripts/socfpga_import_preloader +++ b/scripts/socfpga_import_preloader @@ -46,7 +46,7 @@ copy_source() { echo " Fixing include pathes..." # Fix include pathes - sed -i 's/#include <iocsr_config_cyclone5.h>/#include <mach\/scan-manager.h>/g' $tgt + sed -i 's/#include <iocsr_config_cyclone5.h>/#include <mach\/cyclone5-scan-manager.h>/g' $tgt sed -i 's/#include <pinmux_config.h>/#include <common.h>/g' $tgt sed -i 's/#include "sequencer_auto.h"//g' $tgt sed -i 's/#include "sequencer_defines.h"//g' $tgt diff --git a/scripts/socfpga_xml_to_config.sh b/scripts/socfpga_xml_to_config.sh new file mode 100755 index 0000000000..7e22ebb9e8 --- /dev/null +++ b/scripts/socfpga_xml_to_config.sh @@ -0,0 +1,117 @@ +#!/bin/bash + +## TODO: +## - read in mpuclk and nocclk, must be calculated by hand at the moment +## - read in cfg_dedicated_io_*, must be calculated by hand at the moment + +if [ "$#" -lt "2" ] +then + echo "USAGE: $0 <boarddir> <HPS.xml>" + exit 1 +fi + +dir=$1 +xml=$2 + +pll_config() { + local src + local tgt + src=$1 + tgt=$2 + + MAINPLL=`grep mainpll "$src" | \ + sed -e 's/^.*mainpllgrp\.//g' | \ + sed -e 's/\./_/g' | \ + sed -e "s/' value/ /g" | \ + sed -e "s/'/ /g" | \ + sed -e "s# />#,#g" | \ + sed -e "s/^/\t./g" | + sort` + + # FIXME: Find solution + MAINPLL_FIXME=".mpuclk = FIXME, + .nocclk = FIXME," + + PERPLL=`grep perpll "$src" | \ + sed -e 's/^.*perpllgrp\.//g' | \ + sed -e 's/\./_/g' | \ + sed -e "s/' value/ /g" | \ + sed -e "s/'/ /g" | \ + sed -e "s# />#,#g" | \ + sed -e "s/^/\t./g" | + sort` + + echo "#include <mach/arria10-clock-manager.h>" > $tgt + echo >> $tgt + echo "static struct arria10_mainpll_cfg mainpll_cfg = {" >> $tgt + echo "$MAINPLL" >> $tgt + echo "$MAINPLL_FIXME" >> $tgt + echo "};" >> $tgt + echo >> $tgt + echo "static struct arria10_perpll_cfg perpll_cfg = {" >> $tgt + echo "$PERPLL" >> $tgt + echo "};" >> $tgt + + dos2unix $tgt +} + +pinmux_config() { + local src + local tgt + src=$1 + tgt=$2 + + SHARED=`grep pinmux_shared "$src" | \ + sed -e 's/^.*pinmux_/[arria10_pinmux_/g' | \ + sed -e "s/\.sel' value='/] = /g" | \ + sed -e "s/' \/>/,/g"` + + DEDICATED=`grep pinmux_dedicated "$src" | \ + sed -e 's/^.*pinmux_/[arria10_pinmux_/g' | \ + sed -e "s/\.sel' value='/] = /g" | \ + sed -e "s/' \/>/,/g"` + + # FIXME: Either find solution how to parse these values too or replace + # script with something that goes more in the direction of a programming + # language + DEDICATED_FIXME="[arria10_pincfg_dedicated_io_bank] = FIXME, + [arria10_pincfg_dedicated_io_1] = FIXME, + [arria10_pincfg_dedicated_io_2] = FIXME, + [arria10_pincfg_dedicated_io_3] = FIXME, + [arria10_pincfg_dedicated_io_4] = FIXME, + [arria10_pincfg_dedicated_io_5] = FIXME, + [arria10_pincfg_dedicated_io_6] = FIXME, + [arria10_pincfg_dedicated_io_7] = FIXME, + [arria10_pincfg_dedicated_io_8] = FIXME, + [arria10_pincfg_dedicated_io_9] = FIXME, + [arria10_pincfg_dedicated_io_10] = FIXME, + [arria10_pincfg_dedicated_io_11] = FIXME, + [arria10_pincfg_dedicated_io_12] = FIXME, + [arria10_pincfg_dedicated_io_13] = FIXME, + [arria10_pincfg_dedicated_io_14] = FIXME, + [arria10_pincfg_dedicated_io_15] = FIXME, + [arria10_pincfg_dedicated_io_16] = FIXME, + [arria10_pincfg_dedicated_io_17] = FIXME" + + FPGA=`grep _fpga_interface_grp "$src" | \ + grep -v -e usb -e pll_clock_out | \ + sed -e 's/^.*pinmux_/[arria10_pinmux_/g' | \ + sed -e "s/\.sel' value='/] = /g" | \ + sed -e "s/' \/>/,/g"` + + echo "#include <mach/arria10-pinmux.h>" > $tgt + echo >> $tgt + echo "static uint32_t pinmux[] = {" >> $tgt + echo "$SHARED" >> $tgt + echo "$DEDICATED" >> $tgt + echo "$DEDICATED_FIXME" >> $tgt + echo "$FPGA" >> $tgt + echo "};" >> $tgt + echo >> $tgt + + dos2unix $tgt +} + +pll_config $xml $dir/pll-config-arria10.c + +pinmux_config $xml $dir/pinmux-config-arria10.c |