diff options
221 files changed, 9102 insertions, 1649 deletions
@@ -1,5 +1,5 @@ VERSION = 2020 -PATCHLEVEL = 03 +PATCHLEVEL = 04 SUBLEVEL = 0 EXTRAVERSION = NAME = None @@ -163,6 +163,10 @@ export srctree objtree VPATH # Alternatively CROSS_COMPILE can be set in the environment. # Default value for CROSS_COMPILE is not to prefix executables +ifeq ($(ARCH),arm64) +ARCH = arm +endif + ARCH ?= sandbox CROSS_COMPILE ?= diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/spi b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/spi index 2000a16a12..8fb71f569b 100644 --- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/spi +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/spi @@ -1,5 +1,5 @@ #!/bin/sh -global.bootm.image="/dev/m25p0.kernel" -global.bootm.oftree="/dev/m25p0.oftree" +global.bootm.image="/dev/m25p0.nor.kernel" +global.bootm.oftree="/dev/m25p0.nor.oftree" global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw" diff --git a/arch/arm/cpu/exceptions.S b/arch/arm/cpu/exceptions.S index eda0d6ab8d..55014c8d46 100644 --- a/arch/arm/cpu/exceptions.S +++ b/arch/arm/cpu/exceptions.S @@ -55,26 +55,6 @@ mov r0, sp .endm - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - .macro get_bad_stack ldr r13, =abort_stack str lr, [r13] @ save caller lr / spsr @@ -103,14 +83,6 @@ do_abort_\@: .endm - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - /* * exception handlers */ diff --git a/arch/arm/cpu/interrupts_64.c b/arch/arm/cpu/interrupts_64.c index e8475d2e47..baccf47808 100644 --- a/arch/arm/cpu/interrupts_64.c +++ b/arch/arm/cpu/interrupts_64.c @@ -194,15 +194,22 @@ extern unsigned long vectors; static int aarch64_init_vectors(void) { - unsigned int el; - - el = current_el(); - if (el == 1) - asm volatile("msr vbar_el1, %0" : : "r" (&vectors) : "cc"); - else if (el == 2) - asm volatile("msr vbar_el2, %0" : : "r" (&vectors) : "cc"); - else - asm volatile("msr vbar_el3, %0" : : "r" (&vectors) : "cc"); + unsigned int el; + + el = current_el(); + switch (el) { + case 3: + asm volatile("msr vbar_el3, %0" : : "r" (&vectors) : "cc"); + /* Fall through */ + case 2: + asm volatile("msr vbar_el2, %0" : : "r" (&vectors) : "cc"); + /* Fall through */ + case 1: + asm volatile("msr vbar_el1, %0" : : "r" (&vectors) : "cc"); + /* Fall through */ + default: + break; + } return 0; } diff --git a/arch/arm/cpu/mmu-early_64.c b/arch/arm/cpu/mmu-early_64.c index 94e372637a..a7598f28aa 100644 --- a/arch/arm/cpu/mmu-early_64.c +++ b/arch/arm/cpu/mmu-early_64.c @@ -67,7 +67,8 @@ void mmu_early_enable(unsigned long membase, unsigned long memsize, el = current_el(); set_ttbr_tcr_mair(el, ttb, calc_tcr(el, EARLY_BITS_PER_VA), MEMORY_ATTRIBUTES); - create_sections((void *)ttb, 0, 0, 1UL << (EARLY_BITS_PER_VA - 1), UNCACHED_MEM); + create_sections((void *)ttb, 0, 0, 1UL << (EARLY_BITS_PER_VA - 1), + attrs_uncached_mem()); create_sections((void *)ttb, membase, membase, memsize, CACHED_MEM); tlb_invalidate(); isb(); diff --git a/arch/arm/cpu/mmu.h b/arch/arm/cpu/mmu.h index 6e7a4c0350..c85e0ea050 100644 --- a/arch/arm/cpu/mmu.h +++ b/arch/arm/cpu/mmu.h @@ -39,6 +39,15 @@ static inline void set_ttbr(void *ttb) #define DOMAIN_CLIENT 1 #define DOMAIN_MANAGER 3 +static inline unsigned long get_domain(void) +{ + unsigned long dacr; + + asm volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r"(dacr)); + + return dacr; +} + static inline void set_domain(unsigned val) { /* Set the Domain Access Control Register */ diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c index 98cd4c754e..14d955cd96 100644 --- a/arch/arm/cpu/mmu_64.c +++ b/arch/arm/cpu/mmu_64.c @@ -158,19 +158,21 @@ static void create_sections(uint64_t virt, uint64_t phys, uint64_t size, int arch_remap_range(void *_start, size_t size, unsigned flags) { + unsigned long attrs; + switch (flags) { case MAP_CACHED: - flags = CACHED_MEM; + attrs = CACHED_MEM; break; case MAP_UNCACHED: - flags = UNCACHED_MEM; + attrs = attrs_uncached_mem(); break; default: return -EINVAL; } create_sections((uint64_t)_start, (uint64_t)_start, (uint64_t)size, - flags); + attrs); return 0; } @@ -199,7 +201,7 @@ void __mmu_init(bool mmu_on) pr_debug("ttb: 0x%p\n", ttb); /* create a flat mapping */ - create_sections(0, 0, 1UL << (BITS_PER_VA - 1), UNCACHED_MEM); + create_sections(0, 0, 1UL << (BITS_PER_VA - 1), attrs_uncached_mem()); /* Map sdram cached. */ for_each_memory_bank(bank) diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h index a2a5477569..9bbb62fc6b 100644 --- a/arch/arm/cpu/mmu_64.h +++ b/arch/arm/cpu/mmu_64.h @@ -8,6 +8,23 @@ PTE_BLOCK_OUTER_SHARE | \ PTE_BLOCK_AF) +static inline unsigned long attrs_uncached_mem(void) +{ + unsigned long attrs = UNCACHED_MEM; + + switch (current_el()) { + case 3: + case 2: + attrs |= PTE_BLOCK_UXN; + break; + default: + attrs |= PTE_BLOCK_UXN | PTE_BLOCK_PXN; + break; + } + + return attrs; +} + /* * Do it the simple way for now and invalidate the entire tlb */ diff --git a/arch/arm/cpu/sm.c b/arch/arm/cpu/sm.c index 1f2c236d5a..f5a1edbd4f 100644 --- a/arch/arm/cpu/sm.c +++ b/arch/arm/cpu/sm.c @@ -26,7 +26,7 @@ static unsigned int read_id_pfr1(void) { unsigned int reg; - asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg)); + asm volatile ("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg)); return reg; } @@ -34,18 +34,18 @@ static u32 read_nsacr(void) { unsigned int reg; - asm("mrc p15, 0, %0, c1, c1, 2\n" : "=r"(reg)); + asm volatile ("mrc p15, 0, %0, c1, c1, 2\n" : "=r"(reg)); return reg; } static void write_nsacr(u32 val) { - asm("mcr p15, 0, %0, c1, c1, 2" : : "r"(val)); + asm volatile ("mcr p15, 0, %0, c1, c1, 2" : : "r"(val)); } static void write_mvbar(u32 val) { - asm("mcr p15, 0, %0, c12, c0, 1" : : "r"(val)); + asm volatile ("mcr p15, 0, %0, c12, c0, 1" : : "r"(val)); } static int cpu_is_virt_capable(void) @@ -150,7 +150,7 @@ static bool armv7_have_security_extensions(void) int armv7_secure_monitor_install(void) { int mmuon; - unsigned long ttb, vbar; + unsigned long ttb, vbar, dacr; if (!armv7_have_security_extensions()) { pr_err("Security extensions not implemented.\n"); @@ -164,12 +164,14 @@ int armv7_secure_monitor_install(void) vbar = get_vbar(); ttb = get_ttbr(); + dacr = get_domain(); armv7_init_nonsec(); __armv7_secure_monitor_install(); set_ttbr((void *)ttb); set_vbar(vbar); + set_domain(dacr); if (mmuon) { /* diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h deleted file mode 100644 index d5dbab0ac2..0000000000 --- a/arch/arm/include/asm/processor.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * linux/include/asm-arm/processor.h - * - * Copyright (C) 1995-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARM_PROCESSOR_H -#define __ASM_ARM_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -#define FP_SIZE 35 - -struct fp_hard_struct { - unsigned int save[FP_SIZE]; /* as yet undefined */ -}; - -struct fp_soft_struct { - unsigned int save[FP_SIZE]; /* undefined information */ -}; - -union fp_state { - struct fp_hard_struct hard; - struct fp_soft_struct soft; -}; - -typedef unsigned long mm_segment_t; /* domain register */ - -#ifdef __KERNEL__ - -#define EISA_bus 0 -#define MCA_bus 0 -#define MCA_bus__is_a_macro - -#include <asm/atomic.h> -#include <asm/ptrace.h> -#include <asm/proc/processor.h> -#include <asm/types.h> - -union debug_insn { - u32 arm; - u16 thumb; -}; - -struct debug_entry { - u32 address; - union debug_insn insn; -}; - -struct debug_info { - int nsaved; - struct debug_entry bp[2]; -}; - -struct thread_struct { - atomic_t refcount; - /* fault info */ - unsigned long address; - unsigned long trap_no; - unsigned long error_code; - /* floating point */ - union fp_state fpstate; - /* debugging */ - struct debug_info debug; - /* context info */ - struct context_save_struct *save; - EXTRA_THREAD_STRUCT -}; - -#define INIT_THREAD { \ - refcount: ATOMIC_INIT(1), \ - EXTRA_THREAD_STRUCT_INIT \ -} - -/* - * Return saved PC of a blocked thread. - */ -static inline unsigned long thread_saved_pc(struct thread_struct *t) -{ - return t->save ? pc_pointer(t->save->pc) : 0; -} - -static inline unsigned long thread_saved_fp(struct thread_struct *t) -{ - return t->save ? t->save->fp : 0; -} - -/* Forward declaration, a strange C thing */ -struct task_struct; - -/* Free all resources held by a thread. */ -extern void release_thread(struct task_struct *); - -/* Copy and release all segment info associated with a VM */ -#define copy_segments(tsk, mm) do { } while (0) -#define release_segments(mm) do { } while (0) - -unsigned long get_wchan(struct task_struct *p); - -#define THREAD_SIZE (8192) - -extern struct task_struct *alloc_task_struct(void); -extern void __free_task_struct(struct task_struct *); -#define get_task_struct(p) atomic_inc(&(p)->thread.refcount) -#define free_task_struct(p) \ - do { \ - if (atomic_dec_and_test(&(p)->thread.refcount)) \ - __free_task_struct((p)); \ - } while (0) - -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) - -#define cpu_relax() barrier() - -/* - * Create a new kernel thread - */ -extern int arch_kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); - -#endif - -#endif /* __ASM_ARM_PROCESSOR_H */ diff --git a/arch/arm/lib32/bootm.c b/arch/arm/lib32/bootm.c index d64e705c40..971ebee8ac 100644 --- a/arch/arm/lib32/bootm.c +++ b/arch/arm/lib32/bootm.c @@ -104,11 +104,24 @@ static int get_kernel_addresses(size_t image_size, spacing = SZ_1M; if (*load_address == UIMAGE_INVALID_ADDRESS) { + unsigned long mem_end = mem_start + mem_size - 1; + unsigned long kaddr; + /* * Place the kernel at an address where it does not need to * relocate itself before decompression. */ - *load_address = mem_start + image_decomp_size; + kaddr = mem_start + image_decomp_size; + + /* + * Make sure we do not place the image past the end of the + * available memory. + */ + if (kaddr + image_size + spacing >= mem_end) + kaddr = mem_end - image_size - spacing; + + *load_address = PAGE_ALIGN_DOWN(kaddr); + if (verbose) printf("no OS load address, defaulting to 0x%08lx\n", *load_address); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index eb14cd2c28..77b3e9db64 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -34,6 +34,15 @@ config HAVE_AT91_GENERATED_CLK config HAVE_AT91_BOOTSTRAP bool +config HAVE_AT91_AUDIO_PLL + bool + +config HAVE_AT91_I2S_MUX_CLK + bool + +config HAVE_AT91_SAM9X60_PLL + bool + # Select if board uses the common at91sam926x_board_init config AT91SAM926X_BOARD_INIT bool @@ -71,6 +80,8 @@ config SOC_SAMA5D2 select HAVE_AT91_USB_CLK select HAVE_AT91_GENERATED_CLK select PINCTRL + select HAVE_AT91_AUDIO_PLL + select HAVE_AT91_I2S_MUX_CLK select PINCTRL_AT91PIO4 select HAS_MACB select HAVE_MACH_ARM_HEAD @@ -100,6 +111,14 @@ config SOC_SAMA5D4 select HAS_MACB select HAVE_MACH_ARM_HEAD +config SOC_SAM9X60 + bool + select CPU_ARM926T + select HAVE_AT91_USB_CLK + select HAVE_AT91_GENERATED_CLK + select HAVE_AT91_SAM9X60_PLL + select PINCTRL_AT91 + config ARCH_TEXT_BASE hex default 0x73f00000 if SOC_AT91SAM9G45 diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c index b574a554ab..aec57f4b3f 100644 --- a/arch/arm/mach-layerscape/icid.c +++ b/arch/arm/mach-layerscape/icid.c @@ -495,8 +495,10 @@ static int icid_of_fixup(struct device_node *root, void *context) phandle iommu_handle; iommu = of_find_compatible_node(root, NULL, "arm,mmu-500"); - if (!iommu) - return -ENOENT; + if (!iommu) { + pr_info("No \"arm,mmu-500\" node found, won't fixup\n"); + return 0; + } iommu_handle = of_node_create_phandle(iommu); diff --git a/arch/arm/mach-omap/omap4_rom_usb.c b/arch/arm/mach-omap/omap4_rom_usb.c index 31d93c34ee..0b31240590 100644 --- a/arch/arm/mach-omap/omap4_rom_usb.c +++ b/arch/arm/mach-omap/omap4_rom_usb.c @@ -111,8 +111,7 @@ int omap4_usbboot_wait_read(void) { int ret; while (omap4_usbboot_data.dread.status == STATUS_WAITING) - /* cpu_relax(); */ - barrier(); + cpu_relax(); ret = omap4_usbboot_data.dread.status; omap4_usbboot_data.dread.status = -1; return ret; @@ -153,8 +152,7 @@ int omap4_usbboot_wait_write(void) { int ret; while (omap4_usbboot_data.dwrite.status == STATUS_WAITING) - /* cpu_relax(); */ - barrier(); + cpu_relax(); ret = omap4_usbboot_data.dwrite.status; omap4_usbboot_data.dwrite.status = -1; return ret; diff --git a/arch/kvx/Kconfig b/arch/kvx/Kconfig new file mode 100644 index 0000000000..5463bb4f14 --- /dev/null +++ b/arch/kvx/Kconfig @@ -0,0 +1,55 @@ +config KVX + bool + select 64BIT + select CLKDEV_LOOKUP + select COMMON_CLK + select COMMON_CLK_OF_PROVIDER + select FLEXIBLE_BOOTARGS + select GENERIC_FIND_NEXT_BIT + select LIBFDT + select MFD_SYSCON + select OF_BAREBOX_DRIVERS + select OFDEVICE + select PARTITION + select RESET_SOURCE + default y + +config PHYS_ADDR_T_64BIT + bool + +config 64BIT + bool + select ARCH_DMA_ADDR_T_64BIT + select PHYS_ADDR_T_64BIT + default y + +config ARCH_TEXT_BASE + hex + default 0x110000000 + +menu "Kalray specific" + +config ARCHINFO + string + default "coolidge" +endmenu + +menu "Board configuration" + +config BUILTIN_DTB + bool "link a DTB into the barebox image" + depends on OFTREE + +config BUILTIN_DTB_NAME + string "DTB to build into the barebox image" + depends on BUILTIN_DTB + +choice + prompt "Select your board" + +config BOARD_K200 + bool "K200 Network card" + +endchoice + +endmenu diff --git a/arch/kvx/Makefile b/arch/kvx/Makefile new file mode 100644 index 0000000000..81040f4e69 --- /dev/null +++ b/arch/kvx/Makefile @@ -0,0 +1,37 @@ +KBUILD_DEFCONFIG := generic_defconfig + +CPPFLAGS += -fno-strict-aliasing + +board-$(CONFIG_GENERIC) := generic + +KALLSYMS += --symbol-prefix=_ + +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := kvx-elf- +endif + +DEFAULT_CFLAGS := -nostdlib -fno-builtin -fstrict-align -g +DEFAULT_CFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE) + +LIBGCC_PATH = $(dir $(shell $(CC) $(CFLAGS) --print-libgcc-file-name)) + +CFLAGS += $(DEFAULT_CFLAGS) +AFLAGS += $(DEFAULT_CFLAGS) + +LDFLAGS += -m elf64kvx + +archprepare: maketools + +PHONY += maketools + +common-y += arch/kvx/lib/ +common-y += arch/kvx/cpu/ +common-$(CONFIG_OFTREE) += arch/kvx/dts/ + +lds-y += arch/kvx/cpu/barebox.lds + +cmd_barebox__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_barebox) -o $@ \ + -T $(BAREBOX_LDS) \ + --start-group $(BAREBOX_OBJS) --end-group \ + -L$(LIBGCC_PATH) -lgcc \ + $(filter-out $(BAREBOX_LDS) $(BAREBOX_OBJS) FORCE ,$^) diff --git a/arch/kvx/configs/generic_defconfig b/arch/kvx/configs/generic_defconfig new file mode 100644 index 0000000000..f9ff773a0e --- /dev/null +++ b/arch/kvx/configs/generic_defconfig @@ -0,0 +1,14 @@ +CONFIG_AUTO_COMPLETE=y +CONFIG_BAUDRATE=115200 +# CONFIG_BOOTM is not set +CONFIG_CLOCKSOURCE_KVX=y +CONFIG_CMD_CMP=y +CONFIG_CMD_OF_DUMP=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_RESET=y +CONFIG_CMD_WD=y +CONFIG_CONSOLE_RATP=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_KVX=y diff --git a/arch/kvx/cpu/Makefile b/arch/kvx/cpu/Makefile new file mode 100644 index 0000000000..4a140ffd1b --- /dev/null +++ b/arch/kvx/cpu/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2019 Kalray Inc. +# + +obj-y += start.o cpu.o exception.o reset.o +extra-y += barebox.lds diff --git a/arch/kvx/cpu/barebox.lds.S b/arch/kvx/cpu/barebox.lds.S new file mode 100644 index 0000000000..8d1944afbf --- /dev/null +++ b/arch/kvx/cpu/barebox.lds.S @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <config.h> +#include <asm/common.h> +#include <asm/sys_arch.h> +#include <asm-generic/barebox.lds.h> + +OUTPUT_FORMAT("elf64-kvx") +OUTPUT_ARCH("kvx:kv3-1:64") + +#define DTB_DEFAULT_SIZE (24 * 1024) + +SECTIONS +{ + . = CONFIG_ARCH_TEXT_BASE; + .text ALIGN(4) : { + *(.startup); + _stext = .; + *(.text) + } + + /* Exception vector must be aligned on a huge frontier */ + .exception ALIGN(EXCEPTION_ALIGNMENT) : + { + _exception_start = ABSOLUTE(.); + /** + * First handler is at _exception_start + EXCEPTION_STRIDE + * In order to force getting to the next stride, add at + * least 1 byte of data. The next ALIGN will then be + * forced to get to the next stride. + */ + . += 1; + . = ALIGN(EXCEPTION_STRIDE); + + /* Entry for traps */ + KEEP(*(.exception.trap)); + . += 1; + + /* Entry for interrupts */ + . = ALIGN(EXCEPTION_STRIDE); + KEEP(*(.exception.interrupt)); + . += 1; + + /* Entry for syscall */ + . = ALIGN(EXCEPTION_STRIDE); + KEEP(*(.exception.syscall)); + } + + .rodata ALIGN(8) : { + *(.rodata*) + . = ALIGN(8); + RO_DATA_SECTION + } + + .dtb ALIGN(16): + { + __dtb_start = .; + . += DTB_DEFAULT_SIZE; + __dtb_end = .; + } + + _etext = .; /* End of text and rodata section */ + + .data ALIGN(4): { + sdata = .; + _sdata = .; + *(.data) + . = ALIGN(8); + __stack_end = .; + . += CONFIG_STACK_SIZE; + __stack_start = .; + } + + .gdb_page ALIGN(4 * 1024) : + { + _debug_start = ABSOLUTE(.); + _debug_phy_start = ABSOLUTE(.); + . += 4 * 1024; + } + __debug_phy_end = ABSOLUTE(.); + _edata = .; + + /* We use store quad for bss init so align on 16 bytes */ + .bss ALIGN(16): + { + __bss_start = .; + *(.bss) + . = ALIGN(16); + __bss_stop = .; + } + __end = .; +} diff --git a/arch/kvx/cpu/cpu.c b/arch/kvx/cpu/cpu.c new file mode 100644 index 0000000000..788d3194fe --- /dev/null +++ b/arch/kvx/cpu/cpu.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <common.h> +#include <asm/sfr.h> +#include <asm/sys_arch.h> + +extern char __dtb_start[]; + +/* Default to builtin dtb */ +void *boot_dtb = __dtb_start; + +void kvx_lowlevel_setup(unsigned long r0, void *dtb_ptr) +{ + uint64_t ev_val = (uint64_t) &_exception_start | EXCEPTION_STRIDE; + + if (r0 == FSBL_PARAM_MAGIC) { + boot_dtb = dtb_ptr; + pr_info("Using DTB provided by FSBL\n"); + } + + /* Install exception handlers */ + kvx_sfr_set(EV, ev_val); + + /* Clear exception taken bit now that we setup our handlers */ + kvx_sfr_set_field(PS, ET, 0); + + /* Finally, make sure nobody disabled hardware trap before us */ + kvx_sfr_set_field(PS, HTD, 0); +} diff --git a/arch/kvx/cpu/exception.S b/arch/kvx/cpu/exception.S new file mode 100644 index 0000000000..0017e8ea12 --- /dev/null +++ b/arch/kvx/cpu/exception.S @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <linux/linkage.h> + +/** + * We do not aim at handling exceptions but at least, we want the CPU to + * stop when taking one. + * Note that we can not expect to be able to issue a print since + * it might be the cause of trap... + */ +#define exception_stub(__type) \ +.section .exception.## __type, "ax", @progbits ;\ +ENTRY(kvx_## __type ##_early_handler): ;\ + goto . ;\ + ;; ;\ +ENDPROC(kvx_ ## __type ## _early_handler) + +exception_stub(debug) +exception_stub(trap) +exception_stub(interrupt) +exception_stub(syscall) diff --git a/arch/kvx/cpu/reset.c b/arch/kvx/cpu/reset.c new file mode 100644 index 0000000000..c7f2018e00 --- /dev/null +++ b/arch/kvx/cpu/reset.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2020 Kalray Inc. + */ + +#include <common.h> +#include <reset_source.h> +#include <mfd/syscon.h> +#include <restart.h> +#include <regmap.h> +#include <init.h> + +#include <asm/ftu.h> + +static struct regmap *ftu_regmap; + +static void __noreturn kvx_restart_soc(struct restart_handler *rst) +{ + regmap_write(ftu_regmap, KVX_FTU_SW_RESET_OFFSET, 0x1); + + /* Not reached */ + hang(); +} + + +static int kvx_reset_init(void) +{ + int ret; + u32 rst_cause; + + ftu_regmap = syscon_regmap_lookup_by_compatible("kalray,kvx-syscon"); + if (IS_ERR(ftu_regmap)) + return PTR_ERR(ftu_regmap); + + ret = regmap_read(ftu_regmap, KVX_FTU_RESET_CAUSE_OFFSET, &rst_cause); + if (ret < 0) { + reset_source_set(RESET_UKWN); + return ret; + } + + switch (rst_cause) { + case KVX_FTU_RESET_CAUSE_CODE_DSU: + reset_source_set(RESET_JTAG); + break; + case KVX_FTU_RESET_CAUSE_CODE_SW: + reset_source_set(RESET_RST); + break; + case KVX_FTU_RESET_CAUSE_CODE_MPPA: + reset_source_set(RESET_POR); + break; + case KVX_FTU_RESET_CAUSE_CODE_PCIE: + reset_source_set(RESET_EXT); + break; + case KVX_FTU_RESET_CAUSE_CODE_WDOG_0: + case KVX_FTU_RESET_CAUSE_CODE_WDOG_1: + case KVX_FTU_RESET_CAUSE_CODE_WDOG_2: + case KVX_FTU_RESET_CAUSE_CODE_WDOG_3: + case KVX_FTU_RESET_CAUSE_CODE_WDOG_4: + reset_source_set(RESET_WDG); + break; + } + + restart_handler_register_fn(kvx_restart_soc); + + return 0; +} +device_initcall(kvx_reset_init); diff --git a/arch/kvx/cpu/start.S b/arch/kvx/cpu/start.S new file mode 100644 index 0000000000..a02900fb93 --- /dev/null +++ b/arch/kvx/cpu/start.S @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/privilege.h> +#include <asm/sys_arch.h> + +#define PS_VAL_WFXL(__field, __val) \ + SFR_SET_VAL_WFXL(PS, __field, __val) + +#define PS_WFXL_START_VALUE PS_VAL_WFXL(HLE, 1) | \ + PS_VAL_WFXL(USE, 1) | \ + PS_VAL_WFXL(DCE, 1) | \ + PS_VAL_WFXL(ICE, 1) | \ + PS_VAL_WFXL(V64, 1) | \ + PS_VAL_WFXL(ET, 0) + +#define PCR_VAL_WFXM(__field, __val) \ + SFR_SET_VAL_WFXM(PCR, __field, __val) + +#define PCR_WFXM_START_VALUE PCR_VAL_WFXM(L1CE, 1) + +/* Enable STOP in WS */ +#define WS_ENABLE_WU2 (KVX_SFR_WS_WU2_MASK) + +#define WS_WFXL_VALUE (WS_ENABLE_WU2) + +/* + * This is our entry point. When entering from bootloader, + * the following registers are set: + * $r0 is a magic "KALARGV1" (FSBL_PARAM_MAGIC) indicating parameters are passed + * $r1 Device tree pointer + * + * WARNING WARNING WARNING + * ! DO NOT CLOBBER THEM ! + * WARNING WARNING WARNING + * + * Try to use register above $r20 to ease parameter adding in future + */ +.section .startup, "ax" +ENTRY(kvx_start) + /* (Re)initialize performance counter */ + make $r20 = 0x00000000 + ;; + set $pmc = $r20 + ;; + call asm_init_pl + ;; + /* Setup default processor status */ + make $r25 = PS_WFXL_START_VALUE + ;; + wfxl $ps = $r25 + ;; + make $r25 = PCR_WFXM_START_VALUE + ;; + wfxm $pcr = $r25 + ;; + /* Clear BSS */ + make $r22 = __bss_stop + make $r21 = __bss_start + ;; + sbfd $r22 = $r21, $r22 + make $r24 = 0 + ;; + /* Divide by 16 for hardware loop */ + srld $r22, $r22, 4 + make $r25 = 0 + ;; + /* Clear bss with hardware loop */ + loopdo $r22, clear_bss_done + ;; + sq 0[$r21] = $r24r25 + addd $r21 = $r21, 16 + ;; + clear_bss_done: + /* Setup stack */ + make $sp, __stack_start + ;; + call kvx_lowlevel_setup + ;; + call kvx_start_barebox + ;; + goto kvx_proc_power_off + ;; +ENDPROC(kvx_start) + +#define request_ownership(__pl) ;\ + make $r21 = SYO_WFXL_VALUE_##__pl ;\ + ;; ;\ + wfxl $syow = $r21 ;\ + ;; ;\ + make $r21 = HTO_WFXL_VALUE_##__pl ;\ + ;; ;\ + wfxl $htow = $r21 ;\ + ;; ;\ + make $r21 = MO_WFXL_VALUE_##__pl ;\ + make $r22 = MO_WFXM_VALUE_##__pl ;\ + ;; ;\ + wfxl $mow = $r21 ;\ + ;; ;\ + wfxm $mow = $r22 ;\ + ;; ;\ + make $r21 = ITO_WFXL_VALUE_##__pl ;\ + make $r22 = ITO_WFXM_VALUE_##__pl ;\ + ;; ;\ + wfxl $itow = $r21 ;\ + ;; ;\ + wfxm $itow = $r22 ;\ + ;; ;\ + make $r21 = PSO_WFXL_VALUE_##__pl ;\ + make $r22 = PSO_WFXM_VALUE_##__pl ;\ + ;; ;\ + wfxl $psow = $r21 ;\ + ;; ;\ + wfxm $psow = $r22 ;\ + ;; + +/** + * Initialize privilege level + */ +ENTRY(asm_init_pl) + get $r21 = $ps + ;; + /* Extract privilege level from $ps to check if we need to + * lower our privilege level (we might already be in PL1) + */ + extfz $r20 = $r21, KVX_SFR_END(PS_PL), KVX_SFR_START(PS_PL) + ;; + /* If our privilege level is 0, then we need to lower in execution level + * to ring 1 in order to let the debug routines be inserted at runtime + * by the JTAG. In both case, we will request the resources we need for + * barebox to run. + */ + cb.deqz $r20? delegate_pl + ;; + /* + * When someone is already above us, request the resources we need to + * run barebox . No need to request double exception or ECC traps for + * instance. When doing so, the more privileged level will trap for + * permission and delegate us the required resources. + */ + request_ownership(PL_CUR) + ;; + ret + ;; +delegate_pl: + request_ownership(PL_CUR_PLUS_1) + ;; + /* Copy our $ps into $sps for 1:1 restoration */ + get $r22 = $ps + ;; + /* We will return to $ra after rfe */ + get $r21 = $ra + /* Set privilege level to +1 in $sps (relative level from the + * current one) + */ + addd $r22 = $r22, PL_CUR_PLUS_1 + ;; + set $spc = $r21 + ;; + set $sps = $r22 + ;; + /* When using rfe, $spc and $sps will be restored in $ps and $pc, + * We will then return to the caller ($ra) in current PL + 1 + */ + rfe + ;; +ENDPROC(asm_init_pl) + +ENTRY(kvx_proc_power_off): + dinval + make $r1 = WS_WFXL_VALUE + ;; + /* Enable STOP */ + wfxl $ws, $r1 + ;; +1: stop + ;; + goto 1b + ;; +ENDPROC(kvx_proc_power_off) diff --git a/arch/kvx/dts/Makefile b/arch/kvx/dts/Makefile new file mode 100644 index 0000000000..9d5e94ae10 --- /dev/null +++ b/arch/kvx/dts/Makefile @@ -0,0 +1,13 @@ +# just to build a built-in.o. Otherwise compilation fails when no devicetree is +# created. +obj- += dummy.o + +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) +ifneq ($(BUILTIN_DTB),) +obj-dtb-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o +endif + +obj-dtb-$(CONFIG_BOARD_K200) += k200.dtb.o + +always := $(dtb-y) +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts diff --git a/arch/kvx/dts/k200.dts b/arch/kvx/dts/k200.dts new file mode 100644 index 0000000000..d463ffda50 --- /dev/null +++ b/arch/kvx/dts/k200.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Kalray, Inc. + */ + +/dts-v1/; + +/ { + model = "KONIC 200 (K200)"; + compatible = "kalray,board-k200"; + + #address-cells = <2>; + #size-cells = <2>; + + /* Standard nodes (choosen, cpus, memory, etc) */ + chosen { + bootargs = "earlycon norandmaps console=ttyS0"; + stdout-path = &serial0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "kalray,kvx-pe"; + reg = <0>; + clocks = <&core_clk>; + clock-names = "cpu"; + }; + + }; + + clocks { + ref_clk: ref_clk@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* 100 MHz clock */ + clock-frequency = <100000000>; + }; + + core_clk: core_clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* 1 GHz clock */ + clock-frequency = <1000000000>; + }; + }; + + ddr: memory@100000000 { + device_type = "memory"; + /* Declare 4G of DDR starting at 4G */ + reg = <0x1 0x00000000 0x1 0x00000000>; + }; + + smem: memory@0 { + device_type = "memory"; + /* 4M of SMEM starting at @0 */ + reg = <0x0 0x0 0x0 0x400000>; + }; + + core_timer { + compatible = "kalray,kvx-core-timer"; + clocks = <&core_clk>; + }; + + core_watchdog { + compatible = "kalray,kvx-core-watchdog"; + clocks = <&core_clk>; + }; + + axi { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges; + + ftu: ftu@10181000 { + compatible = "kalray,kvx-syscon", "syscon"; + reg = <0x0 0x10181000 0x0 0x410>; + }; + + pmx_gpio0: pinmux@20230008 { + compatible = "pinctrl-single"; + reg = <0x0 0x20230008 0x0 0x4>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x1>; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,bits = <0x00 0x00000003 0x00000003>; + }; + }; + + serial0: uart0@20210000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20210000 0x0 0x100>; + clocks = <&ref_clk>; + reg-io-width = <4>; + reg-shift = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + }; + }; +}; diff --git a/arch/kvx/include/asm/barrier.h b/arch/kvx/include/asm/barrier.h new file mode 100644 index 0000000000..616b5f90a2 --- /dev/null +++ b/arch/kvx/include/asm/barrier.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_BARRIER_H +#define _ASM_KVX_BARRIER_H + +/* fence is sufficient to guarantee write ordering */ +#define wmb() __builtin_kvx_fence() + +/* no L2 coherency, therefore rmb is D$ invalidation */ +#define rmb() __builtin_kvx_dinval() + +/* general memory barrier */ +#define mb() do { wmb(); rmb(); } while (0) + +#endif /* _ASM_KVX_BARRIER_H */ diff --git a/arch/kvx/include/asm/bitops.h b/arch/kvx/include/asm/bitops.h new file mode 100644 index 0000000000..a78b8a0cea --- /dev/null +++ b/arch/kvx/include/asm/bitops.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_BITOPS_H +#define _ASM_KVX_BITOPS_H + +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit(x, y) __set_bit(x, y) +#define clear_bit(x, y) __clear_bit(x, y) +#define change_bit(x, y) __change_bit(x, y) +#define test_and_set_bit(x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit(x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit(x, y) __test_and_change_bit(x, y) + +#endif /* _ASM_KVX_BITOPS_H */ + diff --git a/arch/kvx/include/asm/bitsperlong.h b/arch/kvx/include/asm/bitsperlong.h new file mode 100644 index 0000000000..9157b3a8e0 --- /dev/null +++ b/arch/kvx/include/asm/bitsperlong.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_BITSPERLONG_H +#define _ASM_KVX_BITSPERLONG_H + +#include <asm-generic/bitsperlong.h> + +#endif /* _ASM_KVX_BITSPERLONG_H */ + diff --git a/arch/kvx/include/asm/byteorder.h b/arch/kvx/include/asm/byteorder.h new file mode 100644 index 0000000000..2dbd079d2a --- /dev/null +++ b/arch/kvx/include/asm/byteorder.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_BYTEORDER_H +#define _ASM_KVX_BYTEORDER_H + +#include <linux/byteorder/little_endian.h> + +#endif /* _ASM_KVX_BYTEORDER_H */ + diff --git a/arch/kvx/include/asm/common.h b/arch/kvx/include/asm/common.h new file mode 100644 index 0000000000..a7e301e53a --- /dev/null +++ b/arch/kvx/include/asm/common.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_COMMON_H +#define _ASM_KVX_COMMON_H + +#ifndef __ASSEMBLY__ + +/* + * Magic value passed in r0 to indicate valid parameters from FSBL when booting + * If $r0 contains this value, then $r1 contains dtb pointer. + */ +#define FSBL_PARAM_MAGIC 0x31564752414C414BULL + +extern char _exception_start; +extern char __end; +extern void *boot_dtb; + +void kvx_start_barebox(void); +void kvx_lowlevel_setup(unsigned long r0, void *dtb_ptr); + +#endif + +#endif /* _ASM_KVX_COMMON_H */ + diff --git a/arch/kvx/include/asm/elf.h b/arch/kvx/include/asm/elf.h new file mode 100644 index 0000000000..7cc09d7bac --- /dev/null +++ b/arch/kvx/include/asm/elf.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_ELF_H +#define _ASM_KVX_ELF_H + +/* + * ELF register definitions.. + */ +#include <linux/types.h> + +#define ELF_CLASS ELFCLASS32 +#define ELF_DATA ELFDATA2MSB + +#endif /* _ASM_KVX_ELF_H */ + diff --git a/arch/kvx/include/asm/ftu.h b/arch/kvx/include/asm/ftu.h new file mode 100644 index 0000000000..4bc935721d --- /dev/null +++ b/arch/kvx/include/asm/ftu.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_FTU_H +#define _ASM_KVX_FTU_H + +/* FTU reset cause register definitions */ +#define KVX_FTU_RESET_CAUSE_OFFSET 0x48 +#define KVX_FTU_RESET_CAUSE_CODE_MPPA 0x0 +#define KVX_FTU_RESET_CAUSE_CODE_DSU 0x1 +#define KVX_FTU_RESET_CAUSE_CODE_SW 0x2 +#define KVX_FTU_RESET_CAUSE_CODE_PCIE 0x3 +#define KVX_FTU_RESET_CAUSE_CODE_WDOG_0 0x8 +#define KVX_FTU_RESET_CAUSE_CODE_WDOG_1 0x9 +#define KVX_FTU_RESET_CAUSE_CODE_WDOG_2 0xA +#define KVX_FTU_RESET_CAUSE_CODE_WDOG_3 0xB +#define KVX_FTU_RESET_CAUSE_CODE_WDOG_4 0xC + +/* FTU reset register definitions */ +#define KVX_FTU_SW_RESET_OFFSET 0x50 + +#endif /* _ASM_KVX_FTU_H */ diff --git a/arch/kvx/include/asm/io.h b/arch/kvx/include/asm/io.h new file mode 100644 index 0000000000..d9993f14b3 --- /dev/null +++ b/arch/kvx/include/asm/io.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_IO_H +#define _ASM_KVX_IO_H + +#define IO_SPACE_LIMIT 0x0 + +#include <asm/byteorder.h> +#include <asm-generic/io.h> + +#endif /* _ASM_KVX_IO_H */ diff --git a/arch/kvx/include/asm/linkage.h b/arch/kvx/include/asm/linkage.h new file mode 100644 index 0000000000..3d2a26508e --- /dev/null +++ b/arch/kvx/include/asm/linkage.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_LINKAGE_H +#define _ASM_KVX_LINKAGE_H + + +#endif /* _ASM_KVX_LINKAGE_H */ diff --git a/arch/kvx/include/asm/posix_types.h b/arch/kvx/include/asm/posix_types.h new file mode 100644 index 0000000000..fc650c326c --- /dev/null +++ b/arch/kvx/include/asm/posix_types.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_POSIX_TYPES_H +#define _ASM_KVX_POSIX_TYPES_H + +#include <asm-generic/posix_types.h> + +#endif /* _ASM_KVX_POSIX_TYPES_H */ + diff --git a/arch/kvx/include/asm/privilege.h b/arch/kvx/include/asm/privilege.h new file mode 100644 index 0000000000..36b9ade494 --- /dev/null +++ b/arch/kvx/include/asm/privilege.h @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_PRIVILEGE_H +#define _ASM_KVX_PRIVILEGE_H + +#include <asm/sys_arch.h> + +/** + * Privilege level stuff + */ + +/* + * When manipulating ring levels, we always use relative values. This means that + * settings a resource owner to value 1 means "Current privilege level + 1. + * Setting it to 0 means "Current privilege level" + */ +#define PL_CUR_PLUS_1 1 +#define PL_CUR 0 + +/** + * Syscall owner configuration + */ +#define SYO_WFXL_OWN(__field, __pl) \ + SFR_SET_VAL_WFXL(SYO, __field, __pl) + +#define SYO_WFXL_VALUE(__pl) (SYO_WFXL_OWN(Q0, __pl) | \ + SYO_WFXL_OWN(Q1, __pl) | \ + SYO_WFXL_OWN(Q2, __pl) | \ + SYO_WFXL_OWN(Q3, __pl)) + +#define SYO_WFXL_VALUE_PL_CUR_PLUS_1 SYO_WFXL_VALUE(PL_CUR_PLUS_1) +#define SYO_WFXL_VALUE_PL_CUR SYO_WFXL_VALUE(PL_CUR) + +/** + * hardware trap owner configuration + */ +#define HTO_WFXL_OWN(__field, __pl) \ + SFR_SET_VAL_WFXL(HTO, __field, __pl) + + +#define HTO_WFXL_VALUE_BASE(__pl) (HTO_WFXL_OWN(OPC, __pl) | \ + HTO_WFXL_OWN(DMIS, __pl) | \ + HTO_WFXL_OWN(PSYS, __pl) | \ + HTO_WFXL_OWN(DSYS, __pl) | \ + HTO_WFXL_OWN(NOMAP, __pl) | \ + HTO_WFXL_OWN(PROT, __pl) | \ + HTO_WFXL_OWN(W2CL, __pl) | \ + HTO_WFXL_OWN(A2CL, __pl) | \ + HTO_WFXL_OWN(VSFR, __pl) | \ + HTO_WFXL_OWN(PLO, __pl)) + +/* + * When alone on the processor, we need to request all traps or the processor + * will die badly without any information at all by jumping to the more + * privilege level even if nobody is there. + */ +#define HTO_WFXL_VALUE_PL_CUR_PLUS_1 (HTO_WFXL_VALUE_BASE(PL_CUR_PLUS_1) | \ + HTO_WFXL_OWN(DECCG, PL_CUR_PLUS_1) | \ + HTO_WFXL_OWN(SECCG, PL_CUR_PLUS_1) | \ + HTO_WFXL_OWN(DE, PL_CUR_PLUS_1)) + +#define HTO_WFXL_VALUE_PL_CUR HTO_WFXL_VALUE_BASE(PL_CUR) + +/** + * Interrupt owner configuration + */ +#define ITO_WFXL_OWN(__field, __pl) \ + SFR_SET_VAL_WFXL(ITO, __field, __pl) + +#define ITO_WFXL_VALUE(__pl) (ITO_WFXL_OWN(IT0, __pl) | \ + ITO_WFXL_OWN(IT1, __pl) | \ + ITO_WFXL_OWN(IT2, __pl) | \ + ITO_WFXL_OWN(IT3, __pl) | \ + ITO_WFXL_OWN(IT4, __pl) | \ + ITO_WFXL_OWN(IT5, __pl) | \ + ITO_WFXL_OWN(IT6, __pl) | \ + ITO_WFXL_OWN(IT7, __pl) | \ + ITO_WFXL_OWN(IT8, __pl) | \ + ITO_WFXL_OWN(IT9, __pl) | \ + ITO_WFXL_OWN(IT10, __pl) | \ + ITO_WFXL_OWN(IT11, __pl) | \ + ITO_WFXL_OWN(IT12, __pl) | \ + ITO_WFXL_OWN(IT13, __pl) | \ + ITO_WFXL_OWN(IT14, __pl) | \ + ITO_WFXL_OWN(IT15, __pl)) + +#define ITO_WFXL_VALUE_PL_CUR_PLUS_1 ITO_WFXL_VALUE(PL_CUR_PLUS_1) +#define ITO_WFXL_VALUE_PL_CUR ITO_WFXL_VALUE(PL_CUR) + +#define ITO_WFXM_OWN(__field, __pl) \ + SFR_SET_VAL_WFXM(ITO, __field, __pl) + +#define ITO_WFXM_VALUE(__pl) (ITO_WFXM_OWN(IT16, __pl) | \ + ITO_WFXM_OWN(IT17, __pl) | \ + ITO_WFXM_OWN(IT18, __pl) | \ + ITO_WFXM_OWN(IT19, __pl) | \ + ITO_WFXM_OWN(IT20, __pl) | \ + ITO_WFXM_OWN(IT21, __pl) | \ + ITO_WFXM_OWN(IT22, __pl) | \ + ITO_WFXM_OWN(IT23, __pl) | \ + ITO_WFXM_OWN(IT24, __pl) | \ + ITO_WFXM_OWN(IT25, __pl) | \ + ITO_WFXM_OWN(IT26, __pl) | \ + ITO_WFXM_OWN(IT27, __pl) | \ + ITO_WFXM_OWN(IT28, __pl) | \ + ITO_WFXM_OWN(IT29, __pl) | \ + ITO_WFXM_OWN(IT30, __pl) | \ + ITO_WFXM_OWN(IT31, __pl)) + +#define ITO_WFXM_VALUE_PL_CUR_PLUS_1 ITO_WFXM_VALUE(PL_CUR_PLUS_1) +#define ITO_WFXM_VALUE_PL_CUR ITO_WFXM_VALUE(PL_CUR) + +/** + * Misc owner configuration + */ +#define MO_WFXL_OWN(__field, __pl) \ + SFR_SET_VAL_WFXL(MO, __field, __pl) + +#define MO_WFXL_VALUE(__pl) (MO_WFXL_OWN(MMI, __pl) | \ + MO_WFXL_OWN(RFE, __pl) | \ + MO_WFXL_OWN(STOP, __pl) | \ + MO_WFXL_OWN(SYNC, __pl) | \ + MO_WFXL_OWN(PCR, __pl) | \ + MO_WFXL_OWN(MSG, __pl) | \ + MO_WFXL_OWN(MEN, __pl) | \ + MO_WFXL_OWN(MES, __pl) | \ + MO_WFXL_OWN(CSIT, __pl) | \ + MO_WFXL_OWN(T0, __pl) | \ + MO_WFXL_OWN(T1, __pl) | \ + MO_WFXL_OWN(WD, __pl) | \ + MO_WFXL_OWN(PM0, __pl) | \ + MO_WFXL_OWN(PM1, __pl) | \ + MO_WFXL_OWN(PM2, __pl) | \ + MO_WFXL_OWN(PM3, __pl)) + +#define MO_WFXL_VALUE_PL_CUR_PLUS_1 MO_WFXL_VALUE(PL_CUR_PLUS_1) +#define MO_WFXL_VALUE_PL_CUR MO_WFXL_VALUE(PL_CUR) + +#define MO_WFXM_OWN(__field, __pl) \ + SFR_SET_VAL_WFXM(MO, __field, __pl) + +#define MO_WFXM_VALUE(__pl) (MO_WFXM_OWN(PMIT, __pl)) + +#define MO_WFXM_VALUE_PL_CUR_PLUS_1 MO_WFXM_VALUE(PL_CUR_PLUS_1) +#define MO_WFXM_VALUE_PL_CUR MO_WFXM_VALUE(PL_CUR) + +/** + * $ps owner configuration + */ +#define PSO_WFXL_OWN(__field, __pl) \ + SFR_SET_VAL_WFXL(PSO, __field, __pl) + +#define PSO_WFXL_BASE_VALUE(__pl) (PSO_WFXL_OWN(PL0, __pl) | \ + PSO_WFXL_OWN(PL1, __pl) | \ + PSO_WFXL_OWN(ET, __pl) | \ + PSO_WFXL_OWN(HTD, __pl) | \ + PSO_WFXL_OWN(IE, __pl) | \ + PSO_WFXL_OWN(HLE, __pl) | \ + PSO_WFXL_OWN(SRE, __pl) | \ + PSO_WFXL_OWN(ICE, __pl) | \ + PSO_WFXL_OWN(USE, __pl) | \ + PSO_WFXL_OWN(DCE, __pl) | \ + PSO_WFXL_OWN(MME, __pl) | \ + PSO_WFXL_OWN(IL0, __pl) | \ + PSO_WFXL_OWN(IL1, __pl) | \ + PSO_WFXL_OWN(VS0, __pl)) +/* Request additionnal VS1 when alone */ +#define PSO_WFXL_VALUE_PL_CUR_PLUS_1 (PSO_WFXL_BASE_VALUE(PL_CUR_PLUS_1) | \ + PSO_WFXL_OWN(VS1, PL_CUR_PLUS_1)) +#define PSO_WFXL_VALUE_PL_CUR PSO_WFXL_BASE_VALUE(PL_CUR) + +#define PSO_WFXM_OWN(__field, __pl) \ + SFR_SET_VAL_WFXM(PSO, __field, __pl) + +#define PSO_WFXM_VALUE(__pl) (PSO_WFXM_OWN(V64, __pl) | \ + PSO_WFXM_OWN(L2E, __pl) | \ + PSO_WFXM_OWN(SME, __pl) | \ + PSO_WFXM_OWN(SMR, __pl) | \ + PSO_WFXM_OWN(PMJ0, __pl) | \ + PSO_WFXM_OWN(PMJ1, __pl) | \ + PSO_WFXM_OWN(PMJ2, __pl) | \ + PSO_WFXM_OWN(PMJ3, __pl) | \ + PSO_WFXM_OWN(MMUP, __pl)) + +/* Request additionnal VS1 */ +#define PSO_WFXM_VALUE_PL_CUR_PLUS_1 PSO_WFXM_VALUE(PL_CUR_PLUS_1) +#define PSO_WFXM_VALUE_PL_CUR PSO_WFXM_VALUE(PL_CUR) + +#endif /* _ASM_KVX_PRIVILEGE_H */ diff --git a/arch/kvx/include/asm/sections.h b/arch/kvx/include/asm/sections.h new file mode 100644 index 0000000000..51376bd99e --- /dev/null +++ b/arch/kvx/include/asm/sections.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_SECTIONS_H +#define _ASM_KVX_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif /* _ASM_KVX_SECTIONS_H */ + diff --git a/arch/kvx/include/asm/sfr.h b/arch/kvx/include/asm/sfr.h new file mode 100644 index 0000000000..5b93cee345 --- /dev/null +++ b/arch/kvx/include/asm/sfr.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_SFR_H +#define _ASM_KVX_SFR_H + +#include <asm/sfr_defs.h> + +#define wfxl(_sfr, _val) __builtin_kvx_wfxl(_sfr, _val) + +#define wfxm(_sfr, _val) __builtin_kvx_wfxm(_sfr, _val) + +static inline uint64_t make_sfr_val(uint64_t mask, uint64_t value) +{ + return ((value & 0xFFFFFFFF) << 32) | (mask & 0xFFFFFFFF); +} + +static inline void +kvx_sfr_set_mask(unsigned char sfr, uint64_t mask, uint64_t value) +{ + uint64_t wf_val; + /* Least significant bits */ + if (mask & 0xFFFFFFFF) { + wf_val = make_sfr_val(mask, value); + wfxl(sfr, wf_val); + } + + /* Most significant bits */ + if (mask & (0xFFFFFFFFULL << 32)) { + value >>= 32; + mask >>= 32; + wf_val = make_sfr_val(mask, value); + wfxm(sfr, wf_val); + } +} + +#define kvx_sfr_set_field(sfr, field, value) \ + kvx_sfr_set_mask(KVX_SFR_ ## sfr, \ + KVX_SFR_ ## sfr ## _ ## field ## _MASK, \ + ((uint64_t) (value) << KVX_SFR_ ## sfr ## _ ## field ## _SHIFT)) + +#define kvx_sfr_set(_sfr, _val) __builtin_kvx_set(KVX_SFR_ ## _sfr, _val) +#define kvx_sfr_get(_sfr) __builtin_kvx_get(KVX_SFR_ ## _sfr) + +#endif /* _ASM_KVX_SFR_DEFS_H */ diff --git a/arch/kvx/include/asm/sfr_defs.h b/arch/kvx/include/asm/sfr_defs.h new file mode 100644 index 0000000000..2b7598e0aa --- /dev/null +++ b/arch/kvx/include/asm/sfr_defs.h @@ -0,0 +1,5029 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_SFR_DEFS_H +#define _ASM_KVX_SFR_DEFS_H + +#include <linux/const.h> + +#define _ULL(X) _AC(X, ULL) + +/* Register file indices */ +#define KVX_SFR_PC 0 /* Program Counter $pc $s0 */ +#define KVX_SFR_PS 1 /* Processor State $ps $s1 */ +#define KVX_SFR_PCR 2 /* Processing Identification $pcr $s2 */ +#define KVX_SFR_RA 3 /* Return Address $ra $s3 */ +#define KVX_SFR_CS 4 /* Compute Status $cs $s4 */ +#define KVX_SFR_CSIT 5 /* Compute Status arithmetic interrupt $csit $s5 */ +#define KVX_SFR_AESPC 6 /* Arithmetic Exception Saved PC $aespc $s6 */ +#define KVX_SFR_LS 7 /* Loop Start Address $ls $s7 */ +#define KVX_SFR_LE 8 /* Loop Exit Address $le $s8 */ +#define KVX_SFR_LC 9 /* Loop Counter $lc $s9 */ +#define KVX_SFR_IPE 10 /* Inter Processor Event $ipe $s10 */ +#define KVX_SFR_MEN 11 /* Misc External Notifications $men $s11 */ +#define KVX_SFR_PMC 12 /* Performance Monitor Control $pmc $s12 */ +#define KVX_SFR_PM0 13 /* Performance Monitor 0 $pm0 $s13 */ +#define KVX_SFR_PM1 14 /* Performance Monitor 1 $pm1 $s14 */ +#define KVX_SFR_PM2 15 /* Performance Monitor 2 $pm2 $s15 */ +#define KVX_SFR_PM3 16 /* Performance Monitor 3 $pm3 $s16 */ +#define KVX_SFR_PMSA 17 /* Performance Monitor Saved Address $pmsa $s17 */ +#define KVX_SFR_TCR 18 /* Timer Control $tcr $s18 */ +#define KVX_SFR_T0V 19 /* Timer 0 value $t0v $s19 */ +#define KVX_SFR_T1V 20 /* Timer 1 value $t1v $s20 */ +#define KVX_SFR_T0R 21 /* Timer 0 reload value $t0r $s21 */ +#define KVX_SFR_T1R 22 /* Timer 1 reload value $t1r $s22 */ +#define KVX_SFR_WDV 23 /* Watchdog Value $wdv $s23 */ +#define KVX_SFR_WDR 24 /* Watchdog Reload $wdr $s24 */ +#define KVX_SFR_ILE 25 /* Interrupt Line Enable $ile $s25 */ +#define KVX_SFR_ILL 26 /* Interrupt Line Level $ill $s26 */ +#define KVX_SFR_ILR 27 /* Interrupt Line Request $ilr $s27 */ +#define KVX_SFR_MMC 28 /* Memory Management Control $mmc $s28 */ +#define KVX_SFR_TEL 29 /* TLB Entry Low $tel $s29 */ +#define KVX_SFR_TEH 30 /* TLB Entry High $teh $s30 */ +#define KVX_SFR_SYO 32 /* Syscall Owners $syo $s32 */ +#define KVX_SFR_HTO 33 /* Hardware Trap Owners $hto $s33 */ +#define KVX_SFR_ITO 34 /* Interrupt Owners $ito $s34 */ +#define KVX_SFR_DO 35 /* Debug Owners $do $s35 */ +#define KVX_SFR_MO 36 /* Miscellaneous Owners $mo $s36 */ +#define KVX_SFR_PSO 37 /* PS register fields Owners $pso $s37 */ +#define KVX_SFR_DC 40 /* OCE (Debug) Control $dc $s40 */ +#define KVX_SFR_DBA0 41 /* Breakpoint Address 0 $dba0 $s41 */ +#define KVX_SFR_DBA1 42 /* Breakpoint Address 1 $dba1 $s42 */ +#define KVX_SFR_DWA0 43 /* Watchpoint Address 0 $dwa0 $s43 */ +#define KVX_SFR_DWA1 44 /* Watchpoint Address 1 $dwa1 $s44 */ +#define KVX_SFR_MES 45 /* Memory Error Status $mes $s45 */ +#define KVX_SFR_WS 46 /* Wake-Up Status $ws $s46 */ +#define KVX_SFR_SPC_PL0 64 /* Shadow PC PL 0 $spc_pl0 $s64 */ +#define KVX_SFR_SPC_PL1 65 /* Shadow PC PL 1 $spc_pl1 $s65 */ +#define KVX_SFR_SPC_PL2 66 /* Shadow PC PL 2 $spc_pl2 $s66 */ +#define KVX_SFR_SPC_PL3 67 /* Shadow PC PL 3 $spc_pl3 $s67 */ +#define KVX_SFR_SPS_PL0 68 /* Shadow PS PL 0 $sps_pl0 $s68 */ +#define KVX_SFR_SPS_PL1 69 /* Shadow PS PL 1 $sps_pl1 $s69 */ +#define KVX_SFR_SPS_PL2 70 /* Shadow PS PL 2 $sps_pl2 $s70 */ +#define KVX_SFR_SPS_PL3 71 /* Shadow PS PL 3 $sps_pl3 $s71 */ +#define KVX_SFR_EA_PL0 72 /* Effective Address PL0 $ea_pl0 $s72 */ +#define KVX_SFR_EA_PL1 73 /* Effective Address PL1 $ea_pl1 $s73 */ +#define KVX_SFR_EA_PL2 74 /* Effective Address PL2 $ea_pl2 $s74 */ +#define KVX_SFR_EA_PL3 75 /* Effective Address PL3 $ea_pl3 $s75 */ +#define KVX_SFR_EV_PL0 76 /* Exception Vector PL 0 $ev_pl0 $s76 */ +#define KVX_SFR_EV_PL1 77 /* Exception Vector PL 1 $ev_pl1 $s77 */ +#define KVX_SFR_EV_PL2 78 /* Exception Vector PL 2 $ev_pl2 $s78 */ +#define KVX_SFR_EV_PL3 79 /* Exception Vector PL 3 $ev_pl3 $s79 */ +#define KVX_SFR_SR_PL0 80 /* System Register PL 0 $sr_pl0 $s80 */ +#define KVX_SFR_SR_PL1 81 /* System Register PL 1 $sr_pl1 $s81 */ +#define KVX_SFR_SR_PL2 82 /* System Register PL 2 $sr_pl2 $s82 */ +#define KVX_SFR_SR_PL3 83 /* System Register PL 3 $sr_pl3 $s83 */ +#define KVX_SFR_ES_PL0 84 /* Exception Syndrome PL 0 $es_pl0 $s84 */ +#define KVX_SFR_ES_PL1 85 /* Exception Syndrome PL 1 $es_pl1 $s85 */ +#define KVX_SFR_ES_PL2 86 /* Exception Syndrome PL 2 $es_pl2 $s86 */ +#define KVX_SFR_ES_PL3 87 /* Exception Syndrome PL 3 $es_pl3 $s87 */ +#define KVX_SFR_SYOW 96 /* Alias to SYO register $syow $s96 */ +#define KVX_SFR_HTOW 97 /* Alias to HTO register $htow $s97 */ +#define KVX_SFR_ITOW 98 /* Alias to ITO register $itow $s98 */ +#define KVX_SFR_DOW 99 /* Alias to DO register $dow $s99 */ +#define KVX_SFR_MOW 100 /* Alias to MO register $mow $s100 */ +#define KVX_SFR_PSOW 101 /* Alias to PSO register $psow $s101 */ +#define KVX_SFR_SPC 128 /* Shadow PC alias on SPC_PL<i> $spc $s128 */ +#define KVX_SFR_SPS 132 /* Shadow PS alias on PS_PL<i> $sps $s132 */ +#define KVX_SFR_EA 136 /* Effective Address alias on EA_PL<i> $ea $s136 */ +#define KVX_SFR_EV 140 /* Exception Vector alias on EV_PL<i> $ev $s140 */ +#define KVX_SFR_SR 144 /* System Register alias on SR_PL<i> $sr $s144 */ +#define KVX_SFR_ES 148 /* Exception Syndrome alias on ES_PL<i> $es $s148 */ +#define KVX_SFR_VSFR0 256 /* Virtual SFR 0 $vsfr0 $s256 */ +#define KVX_SFR_VSFR1 257 /* Virtual SFR 1 $vsfr1 $s257 */ +#define KVX_SFR_VSFR2 258 /* Virtual SFR 2 $vsfr2 $s258 */ +#define KVX_SFR_VSFR3 259 /* Virtual SFR 3 $vsfr3 $s259 */ +#define KVX_SFR_VSFR4 260 /* Virtual SFR 4 $vsfr4 $s260 */ +#define KVX_SFR_VSFR5 261 /* Virtual SFR 5 $vsfr5 $s261 */ +#define KVX_SFR_VSFR6 262 /* Virtual SFR 6 $vsfr6 $s262 */ +#define KVX_SFR_VSFR7 263 /* Virtual SFR 7 $vsfr7 $s263 */ +#define KVX_SFR_VSFR8 264 /* Virtual SFR 8 $vsfr8 $s264 */ +#define KVX_SFR_VSFR9 265 /* Virtual SFR 9 $vsfr9 $s265 */ +#define KVX_SFR_VSFR10 266 /* Virtual SFR 10 $vsfr10 $s266 */ +#define KVX_SFR_VSFR11 267 /* Virtual SFR 11 $vsfr11 $s267 */ +#define KVX_SFR_VSFR12 268 /* Virtual SFR 12 $vsfr12 $s268 */ +#define KVX_SFR_VSFR13 269 /* Virtual SFR 13 $vsfr13 $s269 */ +#define KVX_SFR_VSFR14 270 /* Virtual SFR 14 $vsfr14 $s270 */ +#define KVX_SFR_VSFR15 271 /* Virtual SFR 15 $vsfr15 $s271 */ +#define KVX_SFR_VSFR16 272 /* Virtual SFR 16 $vsfr16 $s272 */ +#define KVX_SFR_VSFR17 273 /* Virtual SFR 17 $vsfr17 $s273 */ +#define KVX_SFR_VSFR18 274 /* Virtual SFR 18 $vsfr18 $s274 */ +#define KVX_SFR_VSFR19 275 /* Virtual SFR 19 $vsfr19 $s275 */ +#define KVX_SFR_VSFR20 276 /* Virtual SFR 20 $vsfr20 $s276 */ +#define KVX_SFR_VSFR21 277 /* Virtual SFR 21 $vsfr21 $s277 */ +#define KVX_SFR_VSFR22 278 /* Virtual SFR 22 $vsfr22 $s278 */ +#define KVX_SFR_VSFR23 279 /* Virtual SFR 23 $vsfr23 $s279 */ +#define KVX_SFR_VSFR24 280 /* Virtual SFR 24 $vsfr24 $s280 */ +#define KVX_SFR_VSFR25 281 /* Virtual SFR 25 $vsfr25 $s281 */ +#define KVX_SFR_VSFR26 282 /* Virtual SFR 26 $vsfr26 $s282 */ +#define KVX_SFR_VSFR27 283 /* Virtual SFR 27 $vsfr27 $s283 */ +#define KVX_SFR_VSFR28 284 /* Virtual SFR 28 $vsfr28 $s284 */ +#define KVX_SFR_VSFR29 285 /* Virtual SFR 29 $vsfr29 $s285 */ +#define KVX_SFR_VSFR30 286 /* Virtual SFR 30 $vsfr30 $s286 */ +#define KVX_SFR_VSFR31 287 /* Virtual SFR 31 $vsfr31 $s287 */ +#define KVX_SFR_VSFR32 288 /* Virtual SFR 32 $vsfr32 $s288 */ +#define KVX_SFR_VSFR33 289 /* Virtual SFR 33 $vsfr33 $s289 */ +#define KVX_SFR_VSFR34 290 /* Virtual SFR 34 $vsfr34 $s290 */ +#define KVX_SFR_VSFR35 291 /* Virtual SFR 35 $vsfr35 $s291 */ +#define KVX_SFR_VSFR36 292 /* Virtual SFR 36 $vsfr36 $s292 */ +#define KVX_SFR_VSFR37 293 /* Virtual SFR 37 $vsfr37 $s293 */ +#define KVX_SFR_VSFR38 294 /* Virtual SFR 38 $vsfr38 $s294 */ +#define KVX_SFR_VSFR39 295 /* Virtual SFR 39 $vsfr39 $s295 */ +#define KVX_SFR_VSFR40 296 /* Virtual SFR 40 $vsfr40 $s296 */ +#define KVX_SFR_VSFR41 297 /* Virtual SFR 41 $vsfr41 $s297 */ +#define KVX_SFR_VSFR42 298 /* Virtual SFR 42 $vsfr42 $s298 */ +#define KVX_SFR_VSFR43 299 /* Virtual SFR 43 $vsfr43 $s299 */ +#define KVX_SFR_VSFR44 300 /* Virtual SFR 44 $vsfr44 $s300 */ +#define KVX_SFR_VSFR45 301 /* Virtual SFR 45 $vsfr45 $s301 */ +#define KVX_SFR_VSFR46 302 /* Virtual SFR 46 $vsfr46 $s302 */ +#define KVX_SFR_VSFR47 303 /* Virtual SFR 47 $vsfr47 $s303 */ +#define KVX_SFR_VSFR48 304 /* Virtual SFR 48 $vsfr48 $s304 */ +#define KVX_SFR_VSFR49 305 /* Virtual SFR 49 $vsfr49 $s305 */ +#define KVX_SFR_VSFR50 306 /* Virtual SFR 50 $vsfr50 $s306 */ +#define KVX_SFR_VSFR51 307 /* Virtual SFR 51 $vsfr51 $s307 */ +#define KVX_SFR_VSFR52 308 /* Virtual SFR 52 $vsfr52 $s308 */ +#define KVX_SFR_VSFR53 309 /* Virtual SFR 53 $vsfr53 $s309 */ +#define KVX_SFR_VSFR54 310 /* Virtual SFR 54 $vsfr54 $s310 */ +#define KVX_SFR_VSFR55 311 /* Virtual SFR 55 $vsfr55 $s311 */ +#define KVX_SFR_VSFR56 312 /* Virtual SFR 56 $vsfr56 $s312 */ +#define KVX_SFR_VSFR57 313 /* Virtual SFR 57 $vsfr57 $s313 */ +#define KVX_SFR_VSFR58 314 /* Virtual SFR 58 $vsfr58 $s314 */ +#define KVX_SFR_VSFR59 315 /* Virtual SFR 59 $vsfr59 $s315 */ +#define KVX_SFR_VSFR60 316 /* Virtual SFR 60 $vsfr60 $s316 */ +#define KVX_SFR_VSFR61 317 /* Virtual SFR 61 $vsfr61 $s317 */ +#define KVX_SFR_VSFR62 318 /* Virtual SFR 62 $vsfr62 $s318 */ +#define KVX_SFR_VSFR63 319 /* Virtual SFR 63 $vsfr63 $s319 */ +#define KVX_SFR_VSFR64 320 /* Virtual SFR 64 $vsfr64 $s320 */ +#define KVX_SFR_VSFR65 321 /* Virtual SFR 65 $vsfr65 $s321 */ +#define KVX_SFR_VSFR66 322 /* Virtual SFR 66 $vsfr66 $s322 */ +#define KVX_SFR_VSFR67 323 /* Virtual SFR 67 $vsfr67 $s323 */ +#define KVX_SFR_VSFR68 324 /* Virtual SFR 68 $vsfr68 $s324 */ +#define KVX_SFR_VSFR69 325 /* Virtual SFR 69 $vsfr69 $s325 */ +#define KVX_SFR_VSFR70 326 /* Virtual SFR 70 $vsfr70 $s326 */ +#define KVX_SFR_VSFR71 327 /* Virtual SFR 71 $vsfr71 $s327 */ +#define KVX_SFR_VSFR72 328 /* Virtual SFR 72 $vsfr72 $s328 */ +#define KVX_SFR_VSFR73 329 /* Virtual SFR 73 $vsfr73 $s329 */ +#define KVX_SFR_VSFR74 330 /* Virtual SFR 74 $vsfr74 $s330 */ +#define KVX_SFR_VSFR75 331 /* Virtual SFR 75 $vsfr75 $s331 */ +#define KVX_SFR_VSFR76 332 /* Virtual SFR 76 $vsfr76 $s332 */ +#define KVX_SFR_VSFR77 333 /* Virtual SFR 77 $vsfr77 $s333 */ +#define KVX_SFR_VSFR78 334 /* Virtual SFR 78 $vsfr78 $s334 */ +#define KVX_SFR_VSFR79 335 /* Virtual SFR 79 $vsfr79 $s335 */ +#define KVX_SFR_VSFR80 336 /* Virtual SFR 80 $vsfr80 $s336 */ +#define KVX_SFR_VSFR81 337 /* Virtual SFR 81 $vsfr81 $s337 */ +#define KVX_SFR_VSFR82 338 /* Virtual SFR 82 $vsfr82 $s338 */ +#define KVX_SFR_VSFR83 339 /* Virtual SFR 83 $vsfr83 $s339 */ +#define KVX_SFR_VSFR84 340 /* Virtual SFR 84 $vsfr84 $s340 */ +#define KVX_SFR_VSFR85 341 /* Virtual SFR 85 $vsfr85 $s341 */ +#define KVX_SFR_VSFR86 342 /* Virtual SFR 86 $vsfr86 $s342 */ +#define KVX_SFR_VSFR87 343 /* Virtual SFR 87 $vsfr87 $s343 */ +#define KVX_SFR_VSFR88 344 /* Virtual SFR 88 $vsfr88 $s344 */ +#define KVX_SFR_VSFR89 345 /* Virtual SFR 89 $vsfr89 $s345 */ +#define KVX_SFR_VSFR90 346 /* Virtual SFR 90 $vsfr90 $s346 */ +#define KVX_SFR_VSFR91 347 /* Virtual SFR 91 $vsfr91 $s347 */ +#define KVX_SFR_VSFR92 348 /* Virtual SFR 92 $vsfr92 $s348 */ +#define KVX_SFR_VSFR93 349 /* Virtual SFR 93 $vsfr93 $s349 */ +#define KVX_SFR_VSFR94 350 /* Virtual SFR 94 $vsfr94 $s350 */ +#define KVX_SFR_VSFR95 351 /* Virtual SFR 95 $vsfr95 $s351 */ +#define KVX_SFR_VSFR96 352 /* Virtual SFR 96 $vsfr96 $s352 */ +#define KVX_SFR_VSFR97 353 /* Virtual SFR 97 $vsfr97 $s353 */ +#define KVX_SFR_VSFR98 354 /* Virtual SFR 98 $vsfr98 $s354 */ +#define KVX_SFR_VSFR99 355 /* Virtual SFR 99 $vsfr99 $s355 */ +#define KVX_SFR_VSFR100 356 /* Virtual SFR 100 $vsfr100 $s356 */ +#define KVX_SFR_VSFR101 357 /* Virtual SFR 101 $vsfr101 $s357 */ +#define KVX_SFR_VSFR102 358 /* Virtual SFR 102 $vsfr102 $s358 */ +#define KVX_SFR_VSFR103 359 /* Virtual SFR 103 $vsfr103 $s359 */ +#define KVX_SFR_VSFR104 360 /* Virtual SFR 104 $vsfr104 $s360 */ +#define KVX_SFR_VSFR105 361 /* Virtual SFR 105 $vsfr105 $s361 */ +#define KVX_SFR_VSFR106 362 /* Virtual SFR 106 $vsfr106 $s362 */ +#define KVX_SFR_VSFR107 363 /* Virtual SFR 107 $vsfr107 $s363 */ +#define KVX_SFR_VSFR108 364 /* Virtual SFR 108 $vsfr108 $s364 */ +#define KVX_SFR_VSFR109 365 /* Virtual SFR 109 $vsfr109 $s365 */ +#define KVX_SFR_VSFR110 366 /* Virtual SFR 110 $vsfr110 $s366 */ +#define KVX_SFR_VSFR111 367 /* Virtual SFR 111 $vsfr111 $s367 */ +#define KVX_SFR_VSFR112 368 /* Virtual SFR 112 $vsfr112 $s368 */ +#define KVX_SFR_VSFR113 369 /* Virtual SFR 113 $vsfr113 $s369 */ +#define KVX_SFR_VSFR114 370 /* Virtual SFR 114 $vsfr114 $s370 */ +#define KVX_SFR_VSFR115 371 /* Virtual SFR 115 $vsfr115 $s371 */ +#define KVX_SFR_VSFR116 372 /* Virtual SFR 116 $vsfr116 $s372 */ +#define KVX_SFR_VSFR117 373 /* Virtual SFR 117 $vsfr117 $s373 */ +#define KVX_SFR_VSFR118 374 /* Virtual SFR 118 $vsfr118 $s374 */ +#define KVX_SFR_VSFR119 375 /* Virtual SFR 119 $vsfr119 $s375 */ +#define KVX_SFR_VSFR120 376 /* Virtual SFR 120 $vsfr120 $s376 */ +#define KVX_SFR_VSFR121 377 /* Virtual SFR 121 $vsfr121 $s377 */ +#define KVX_SFR_VSFR122 378 /* Virtual SFR 122 $vsfr122 $s378 */ +#define KVX_SFR_VSFR123 379 /* Virtual SFR 123 $vsfr123 $s379 */ +#define KVX_SFR_VSFR124 380 /* Virtual SFR 124 $vsfr124 $s380 */ +#define KVX_SFR_VSFR125 381 /* Virtual SFR 125 $vsfr125 $s381 */ +#define KVX_SFR_VSFR126 382 /* Virtual SFR 126 $vsfr126 $s382 */ +#define KVX_SFR_VSFR127 383 /* Virtual SFR 127 $vsfr127 $s383 */ +#define KVX_SFR_VSFR128 384 /* Virtual SFR 128 $vsfr128 $s384 */ +#define KVX_SFR_VSFR129 385 /* Virtual SFR 129 $vsfr129 $s385 */ +#define KVX_SFR_VSFR130 386 /* Virtual SFR 130 $vsfr130 $s386 */ +#define KVX_SFR_VSFR131 387 /* Virtual SFR 131 $vsfr131 $s387 */ +#define KVX_SFR_VSFR132 388 /* Virtual SFR 132 $vsfr132 $s388 */ +#define KVX_SFR_VSFR133 389 /* Virtual SFR 133 $vsfr133 $s389 */ +#define KVX_SFR_VSFR134 390 /* Virtual SFR 134 $vsfr134 $s390 */ +#define KVX_SFR_VSFR135 391 /* Virtual SFR 135 $vsfr135 $s391 */ +#define KVX_SFR_VSFR136 392 /* Virtual SFR 136 $vsfr136 $s392 */ +#define KVX_SFR_VSFR137 393 /* Virtual SFR 137 $vsfr137 $s393 */ +#define KVX_SFR_VSFR138 394 /* Virtual SFR 138 $vsfr138 $s394 */ +#define KVX_SFR_VSFR139 395 /* Virtual SFR 139 $vsfr139 $s395 */ +#define KVX_SFR_VSFR140 396 /* Virtual SFR 140 $vsfr140 $s396 */ +#define KVX_SFR_VSFR141 397 /* Virtual SFR 141 $vsfr141 $s397 */ +#define KVX_SFR_VSFR142 398 /* Virtual SFR 142 $vsfr142 $s398 */ +#define KVX_SFR_VSFR143 399 /* Virtual SFR 143 $vsfr143 $s399 */ +#define KVX_SFR_VSFR144 400 /* Virtual SFR 144 $vsfr144 $s400 */ +#define KVX_SFR_VSFR145 401 /* Virtual SFR 145 $vsfr145 $s401 */ +#define KVX_SFR_VSFR146 402 /* Virtual SFR 146 $vsfr146 $s402 */ +#define KVX_SFR_VSFR147 403 /* Virtual SFR 147 $vsfr147 $s403 */ +#define KVX_SFR_VSFR148 404 /* Virtual SFR 148 $vsfr148 $s404 */ +#define KVX_SFR_VSFR149 405 /* Virtual SFR 149 $vsfr149 $s405 */ +#define KVX_SFR_VSFR150 406 /* Virtual SFR 150 $vsfr150 $s406 */ +#define KVX_SFR_VSFR151 407 /* Virtual SFR 151 $vsfr151 $s407 */ +#define KVX_SFR_VSFR152 408 /* Virtual SFR 152 $vsfr152 $s408 */ +#define KVX_SFR_VSFR153 409 /* Virtual SFR 153 $vsfr153 $s409 */ +#define KVX_SFR_VSFR154 410 /* Virtual SFR 154 $vsfr154 $s410 */ +#define KVX_SFR_VSFR155 411 /* Virtual SFR 155 $vsfr155 $s411 */ +#define KVX_SFR_VSFR156 412 /* Virtual SFR 156 $vsfr156 $s412 */ +#define KVX_SFR_VSFR157 413 /* Virtual SFR 157 $vsfr157 $s413 */ +#define KVX_SFR_VSFR158 414 /* Virtual SFR 158 $vsfr158 $s414 */ +#define KVX_SFR_VSFR159 415 /* Virtual SFR 159 $vsfr159 $s415 */ +#define KVX_SFR_VSFR160 416 /* Virtual SFR 160 $vsfr160 $s416 */ +#define KVX_SFR_VSFR161 417 /* Virtual SFR 161 $vsfr161 $s417 */ +#define KVX_SFR_VSFR162 418 /* Virtual SFR 162 $vsfr162 $s418 */ +#define KVX_SFR_VSFR163 419 /* Virtual SFR 163 $vsfr163 $s419 */ +#define KVX_SFR_VSFR164 420 /* Virtual SFR 164 $vsfr164 $s420 */ +#define KVX_SFR_VSFR165 421 /* Virtual SFR 165 $vsfr165 $s421 */ +#define KVX_SFR_VSFR166 422 /* Virtual SFR 166 $vsfr166 $s422 */ +#define KVX_SFR_VSFR167 423 /* Virtual SFR 167 $vsfr167 $s423 */ +#define KVX_SFR_VSFR168 424 /* Virtual SFR 168 $vsfr168 $s424 */ +#define KVX_SFR_VSFR169 425 /* Virtual SFR 169 $vsfr169 $s425 */ +#define KVX_SFR_VSFR170 426 /* Virtual SFR 170 $vsfr170 $s426 */ +#define KVX_SFR_VSFR171 427 /* Virtual SFR 171 $vsfr171 $s427 */ +#define KVX_SFR_VSFR172 428 /* Virtual SFR 172 $vsfr172 $s428 */ +#define KVX_SFR_VSFR173 429 /* Virtual SFR 173 $vsfr173 $s429 */ +#define KVX_SFR_VSFR174 430 /* Virtual SFR 174 $vsfr174 $s430 */ +#define KVX_SFR_VSFR175 431 /* Virtual SFR 175 $vsfr175 $s431 */ +#define KVX_SFR_VSFR176 432 /* Virtual SFR 176 $vsfr176 $s432 */ +#define KVX_SFR_VSFR177 433 /* Virtual SFR 177 $vsfr177 $s433 */ +#define KVX_SFR_VSFR178 434 /* Virtual SFR 178 $vsfr178 $s434 */ +#define KVX_SFR_VSFR179 435 /* Virtual SFR 179 $vsfr179 $s435 */ +#define KVX_SFR_VSFR180 436 /* Virtual SFR 180 $vsfr180 $s436 */ +#define KVX_SFR_VSFR181 437 /* Virtual SFR 181 $vsfr181 $s437 */ +#define KVX_SFR_VSFR182 438 /* Virtual SFR 182 $vsfr182 $s438 */ +#define KVX_SFR_VSFR183 439 /* Virtual SFR 183 $vsfr183 $s439 */ +#define KVX_SFR_VSFR184 440 /* Virtual SFR 184 $vsfr184 $s440 */ +#define KVX_SFR_VSFR185 441 /* Virtual SFR 185 $vsfr185 $s441 */ +#define KVX_SFR_VSFR186 442 /* Virtual SFR 186 $vsfr186 $s442 */ +#define KVX_SFR_VSFR187 443 /* Virtual SFR 187 $vsfr187 $s443 */ +#define KVX_SFR_VSFR188 444 /* Virtual SFR 188 $vsfr188 $s444 */ +#define KVX_SFR_VSFR189 445 /* Virtual SFR 189 $vsfr189 $s445 */ +#define KVX_SFR_VSFR190 446 /* Virtual SFR 190 $vsfr190 $s446 */ +#define KVX_SFR_VSFR191 447 /* Virtual SFR 191 $vsfr191 $s447 */ +#define KVX_SFR_VSFR192 448 /* Virtual SFR 192 $vsfr192 $s448 */ +#define KVX_SFR_VSFR193 449 /* Virtual SFR 193 $vsfr193 $s449 */ +#define KVX_SFR_VSFR194 450 /* Virtual SFR 194 $vsfr194 $s450 */ +#define KVX_SFR_VSFR195 451 /* Virtual SFR 195 $vsfr195 $s451 */ +#define KVX_SFR_VSFR196 452 /* Virtual SFR 196 $vsfr196 $s452 */ +#define KVX_SFR_VSFR197 453 /* Virtual SFR 197 $vsfr197 $s453 */ +#define KVX_SFR_VSFR198 454 /* Virtual SFR 198 $vsfr198 $s454 */ +#define KVX_SFR_VSFR199 455 /* Virtual SFR 199 $vsfr199 $s455 */ +#define KVX_SFR_VSFR200 456 /* Virtual SFR 200 $vsfr200 $s456 */ +#define KVX_SFR_VSFR201 457 /* Virtual SFR 201 $vsfr201 $s457 */ +#define KVX_SFR_VSFR202 458 /* Virtual SFR 202 $vsfr202 $s458 */ +#define KVX_SFR_VSFR203 459 /* Virtual SFR 203 $vsfr203 $s459 */ +#define KVX_SFR_VSFR204 460 /* Virtual SFR 204 $vsfr204 $s460 */ +#define KVX_SFR_VSFR205 461 /* Virtual SFR 205 $vsfr205 $s461 */ +#define KVX_SFR_VSFR206 462 /* Virtual SFR 206 $vsfr206 $s462 */ +#define KVX_SFR_VSFR207 463 /* Virtual SFR 207 $vsfr207 $s463 */ +#define KVX_SFR_VSFR208 464 /* Virtual SFR 208 $vsfr208 $s464 */ +#define KVX_SFR_VSFR209 465 /* Virtual SFR 209 $vsfr209 $s465 */ +#define KVX_SFR_VSFR210 466 /* Virtual SFR 210 $vsfr210 $s466 */ +#define KVX_SFR_VSFR211 467 /* Virtual SFR 211 $vsfr211 $s467 */ +#define KVX_SFR_VSFR212 468 /* Virtual SFR 212 $vsfr212 $s468 */ +#define KVX_SFR_VSFR213 469 /* Virtual SFR 213 $vsfr213 $s469 */ +#define KVX_SFR_VSFR214 470 /* Virtual SFR 214 $vsfr214 $s470 */ +#define KVX_SFR_VSFR215 471 /* Virtual SFR 215 $vsfr215 $s471 */ +#define KVX_SFR_VSFR216 472 /* Virtual SFR 216 $vsfr216 $s472 */ +#define KVX_SFR_VSFR217 473 /* Virtual SFR 217 $vsfr217 $s473 */ +#define KVX_SFR_VSFR218 474 /* Virtual SFR 218 $vsfr218 $s474 */ +#define KVX_SFR_VSFR219 475 /* Virtual SFR 219 $vsfr219 $s475 */ +#define KVX_SFR_VSFR220 476 /* Virtual SFR 220 $vsfr220 $s476 */ +#define KVX_SFR_VSFR221 477 /* Virtual SFR 221 $vsfr221 $s477 */ +#define KVX_SFR_VSFR222 478 /* Virtual SFR 222 $vsfr222 $s478 */ +#define KVX_SFR_VSFR223 479 /* Virtual SFR 223 $vsfr223 $s479 */ +#define KVX_SFR_VSFR224 480 /* Virtual SFR 224 $vsfr224 $s480 */ +#define KVX_SFR_VSFR225 481 /* Virtual SFR 225 $vsfr225 $s481 */ +#define KVX_SFR_VSFR226 482 /* Virtual SFR 226 $vsfr226 $s482 */ +#define KVX_SFR_VSFR227 483 /* Virtual SFR 227 $vsfr227 $s483 */ +#define KVX_SFR_VSFR228 484 /* Virtual SFR 228 $vsfr228 $s484 */ +#define KVX_SFR_VSFR229 485 /* Virtual SFR 229 $vsfr229 $s485 */ +#define KVX_SFR_VSFR230 486 /* Virtual SFR 230 $vsfr230 $s486 */ +#define KVX_SFR_VSFR231 487 /* Virtual SFR 231 $vsfr231 $s487 */ +#define KVX_SFR_VSFR232 488 /* Virtual SFR 232 $vsfr232 $s488 */ +#define KVX_SFR_VSFR233 489 /* Virtual SFR 233 $vsfr233 $s489 */ +#define KVX_SFR_VSFR234 490 /* Virtual SFR 234 $vsfr234 $s490 */ +#define KVX_SFR_VSFR235 491 /* Virtual SFR 235 $vsfr235 $s491 */ +#define KVX_SFR_VSFR236 492 /* Virtual SFR 236 $vsfr236 $s492 */ +#define KVX_SFR_VSFR237 493 /* Virtual SFR 237 $vsfr237 $s493 */ +#define KVX_SFR_VSFR238 494 /* Virtual SFR 238 $vsfr238 $s494 */ +#define KVX_SFR_VSFR239 495 /* Virtual SFR 239 $vsfr239 $s495 */ +#define KVX_SFR_VSFR240 496 /* Virtual SFR 240 $vsfr240 $s496 */ +#define KVX_SFR_VSFR241 497 /* Virtual SFR 241 $vsfr241 $s497 */ +#define KVX_SFR_VSFR242 498 /* Virtual SFR 242 $vsfr242 $s498 */ +#define KVX_SFR_VSFR243 499 /* Virtual SFR 243 $vsfr243 $s499 */ +#define KVX_SFR_VSFR244 500 /* Virtual SFR 244 $vsfr244 $s500 */ +#define KVX_SFR_VSFR245 501 /* Virtual SFR 245 $vsfr245 $s501 */ +#define KVX_SFR_VSFR246 502 /* Virtual SFR 246 $vsfr246 $s502 */ +#define KVX_SFR_VSFR247 503 /* Virtual SFR 247 $vsfr247 $s503 */ +#define KVX_SFR_VSFR248 504 /* Virtual SFR 248 $vsfr248 $s504 */ +#define KVX_SFR_VSFR249 505 /* Virtual SFR 249 $vsfr249 $s505 */ +#define KVX_SFR_VSFR250 506 /* Virtual SFR 250 $vsfr250 $s506 */ +#define KVX_SFR_VSFR251 507 /* Virtual SFR 251 $vsfr251 $s507 */ +#define KVX_SFR_VSFR252 508 /* Virtual SFR 252 $vsfr252 $s508 */ +#define KVX_SFR_VSFR253 509 /* Virtual SFR 253 $vsfr253 $s509 */ +#define KVX_SFR_VSFR254 510 /* Virtual SFR 254 $vsfr254 $s510 */ +#define KVX_SFR_VSFR255 511 /* Virtual SFR 255 $vsfr255 $s511 */ + +/* Register field masks */ + +#define KVX_SFR_MEN_MEN_MASK _ULL(0xffff) /* Miscellaneous External Notifications */ +#define KVX_SFR_MEN_MEN_SHIFT 0 +#define KVX_SFR_MEN_MEN_WIDTH 16 +#define KVX_SFR_MEN_MEN_WFXL_MASK _ULL(0xffff) +#define KVX_SFR_MEN_MEN_WFXL_CLEAR _ULL(0xffff) +#define KVX_SFR_MEN_MEN_WFXL_SET _ULL(0xffff00000000) + +#define KVX_SFR_SYO_Q0_MASK _ULL(0x3) /* Quarter 0 syscalls 0 to 1023 owner */ +#define KVX_SFR_SYO_Q0_SHIFT 0 +#define KVX_SFR_SYO_Q0_WIDTH 2 +#define KVX_SFR_SYO_Q0_WFXL_MASK _ULL(0x3) +#define KVX_SFR_SYO_Q0_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_SYO_Q0_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_SYO_Q1_MASK _ULL(0xc) /* Quarter 1 syscalls 1024 to 2047 owner */ +#define KVX_SFR_SYO_Q1_SHIFT 2 +#define KVX_SFR_SYO_Q1_WIDTH 2 +#define KVX_SFR_SYO_Q1_WFXL_MASK _ULL(0xc) +#define KVX_SFR_SYO_Q1_WFXL_CLEAR _ULL(0xc) +#define KVX_SFR_SYO_Q1_WFXL_SET _ULL(0xc00000000) + +#define KVX_SFR_SYO_Q2_MASK _ULL(0x30) /* Quarter 2 syscalls 2048 to 3071 owner */ +#define KVX_SFR_SYO_Q2_SHIFT 4 +#define KVX_SFR_SYO_Q2_WIDTH 2 +#define KVX_SFR_SYO_Q2_WFXL_MASK _ULL(0x30) +#define KVX_SFR_SYO_Q2_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_SYO_Q2_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_SYO_Q3_MASK _ULL(0xc0) /* Quarter 3 syscalls 3072 to 4095 owner */ +#define KVX_SFR_SYO_Q3_SHIFT 6 +#define KVX_SFR_SYO_Q3_WIDTH 2 +#define KVX_SFR_SYO_Q3_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_SYO_Q3_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_SYO_Q3_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_SYOW_Q0_MASK _ULL(0x3) /* Quarter 0 syscalls 0 to 1023 owner */ +#define KVX_SFR_SYOW_Q0_SHIFT 0 +#define KVX_SFR_SYOW_Q0_WIDTH 2 +#define KVX_SFR_SYOW_Q0_WFXL_MASK _ULL(0x3) +#define KVX_SFR_SYOW_Q0_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_SYOW_Q0_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_SYOW_Q1_MASK _ULL(0xc) /* Quarter 1 syscalls 1024 to 2047 owner */ +#define KVX_SFR_SYOW_Q1_SHIFT 2 +#define KVX_SFR_SYOW_Q1_WIDTH 2 +#define KVX_SFR_SYOW_Q1_WFXL_MASK _ULL(0xc) +#define KVX_SFR_SYOW_Q1_WFXL_CLEAR _ULL(0xc) +#define KVX_SFR_SYOW_Q1_WFXL_SET _ULL(0xc00000000) + +#define KVX_SFR_SYOW_Q2_MASK _ULL(0x30) /* Quarter 2 syscalls 2048 to 3071 owner */ +#define KVX_SFR_SYOW_Q2_SHIFT 4 +#define KVX_SFR_SYOW_Q2_WIDTH 2 +#define KVX_SFR_SYOW_Q2_WFXL_MASK _ULL(0x30) +#define KVX_SFR_SYOW_Q2_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_SYOW_Q2_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_SYOW_Q3_MASK _ULL(0xc0) /* Quarter 3 syscalls 3072 to 4095 owner */ +#define KVX_SFR_SYOW_Q3_SHIFT 6 +#define KVX_SFR_SYOW_Q3_WIDTH 2 +#define KVX_SFR_SYOW_Q3_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_SYOW_Q3_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_SYOW_Q3_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_HTO_OPC_MASK _ULL(0x3) /* OPCode trap owner */ +#define KVX_SFR_HTO_OPC_SHIFT 0 +#define KVX_SFR_HTO_OPC_WIDTH 2 +#define KVX_SFR_HTO_OPC_WFXL_MASK _ULL(0x3) +#define KVX_SFR_HTO_OPC_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_HTO_OPC_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_HTO_DMIS_MASK _ULL(0xc) /* Data MISalign access trap owner */ +#define KVX_SFR_HTO_DMIS_SHIFT 2 +#define KVX_SFR_HTO_DMIS_WIDTH 2 +#define KVX_SFR_HTO_DMIS_WFXL_MASK _ULL(0xc) +#define KVX_SFR_HTO_DMIS_WFXL_CLEAR _ULL(0xc) +#define KVX_SFR_HTO_DMIS_WFXL_SET _ULL(0xc00000000) + +#define KVX_SFR_HTO_PSYS_MASK _ULL(0x30) /* Program System Error trap owner */ +#define KVX_SFR_HTO_PSYS_SHIFT 4 +#define KVX_SFR_HTO_PSYS_WIDTH 2 +#define KVX_SFR_HTO_PSYS_WFXL_MASK _ULL(0x30) +#define KVX_SFR_HTO_PSYS_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_HTO_PSYS_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_HTO_DSYS_MASK _ULL(0xc0) /* Data System Error trap owner */ +#define KVX_SFR_HTO_DSYS_SHIFT 6 +#define KVX_SFR_HTO_DSYS_WIDTH 2 +#define KVX_SFR_HTO_DSYS_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_HTO_DSYS_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_HTO_DSYS_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_HTO_DECCG_MASK _ULL(0x300) /* Double ECC traps group owner */ +#define KVX_SFR_HTO_DECCG_SHIFT 8 +#define KVX_SFR_HTO_DECCG_WIDTH 2 +#define KVX_SFR_HTO_DECCG_WFXL_MASK _ULL(0x300) +#define KVX_SFR_HTO_DECCG_WFXL_CLEAR _ULL(0x300) +#define KVX_SFR_HTO_DECCG_WFXL_SET _ULL(0x30000000000) + +#define KVX_SFR_HTO_SECCG_MASK _ULL(0xc00) /* Single ECC traps group owner */ +#define KVX_SFR_HTO_SECCG_SHIFT 10 +#define KVX_SFR_HTO_SECCG_WIDTH 2 +#define KVX_SFR_HTO_SECCG_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_HTO_SECCG_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_HTO_SECCG_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_HTO_NOMAP_MASK _ULL(0x3000) /* No mapping trap owner */ +#define KVX_SFR_HTO_NOMAP_SHIFT 12 +#define KVX_SFR_HTO_NOMAP_WIDTH 2 +#define KVX_SFR_HTO_NOMAP_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_HTO_NOMAP_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_HTO_NOMAP_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_HTO_PROT_MASK _ULL(0xc000) /* PROTection trap owner */ +#define KVX_SFR_HTO_PROT_SHIFT 14 +#define KVX_SFR_HTO_PROT_WIDTH 2 +#define KVX_SFR_HTO_PROT_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_HTO_PROT_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_HTO_PROT_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_HTO_W2CL_MASK _ULL(0x30000) /* Write to clean trap owner */ +#define KVX_SFR_HTO_W2CL_SHIFT 16 +#define KVX_SFR_HTO_W2CL_WIDTH 2 +#define KVX_SFR_HTO_W2CL_WFXL_MASK _ULL(0x30000) +#define KVX_SFR_HTO_W2CL_WFXL_CLEAR _ULL(0x30000) +#define KVX_SFR_HTO_W2CL_WFXL_SET _ULL(0x3000000000000) + +#define KVX_SFR_HTO_A2CL_MASK _ULL(0xc0000) /* Atomic to clean trap owner */ +#define KVX_SFR_HTO_A2CL_SHIFT 18 +#define KVX_SFR_HTO_A2CL_WIDTH 2 +#define KVX_SFR_HTO_A2CL_WFXL_MASK _ULL(0xc0000) +#define KVX_SFR_HTO_A2CL_WFXL_CLEAR _ULL(0xc0000) +#define KVX_SFR_HTO_A2CL_WFXL_SET _ULL(0xc000000000000) + +#define KVX_SFR_HTO_DE_MASK _ULL(0x300000) /* Double Exception trap owner */ +#define KVX_SFR_HTO_DE_SHIFT 20 +#define KVX_SFR_HTO_DE_WIDTH 2 +#define KVX_SFR_HTO_DE_WFXL_MASK _ULL(0x300000) +#define KVX_SFR_HTO_DE_WFXL_CLEAR _ULL(0x300000) +#define KVX_SFR_HTO_DE_WFXL_SET _ULL(0x30000000000000) + +#define KVX_SFR_HTO_VSFR_MASK _ULL(0xc00000) /* Virtual SFR trap owner */ +#define KVX_SFR_HTO_VSFR_SHIFT 22 +#define KVX_SFR_HTO_VSFR_WIDTH 2 +#define KVX_SFR_HTO_VSFR_WFXL_MASK _ULL(0xc00000) +#define KVX_SFR_HTO_VSFR_WFXL_CLEAR _ULL(0xc00000) +#define KVX_SFR_HTO_VSFR_WFXL_SET _ULL(0xc0000000000000) + +#define KVX_SFR_HTO_PLO_MASK _ULL(0x3000000) /* Privilege Level Overflow trap owner */ +#define KVX_SFR_HTO_PLO_SHIFT 24 +#define KVX_SFR_HTO_PLO_WIDTH 2 +#define KVX_SFR_HTO_PLO_WFXL_MASK _ULL(0x3000000) +#define KVX_SFR_HTO_PLO_WFXL_CLEAR _ULL(0x3000000) +#define KVX_SFR_HTO_PLO_WFXL_SET _ULL(0x300000000000000) + +#define KVX_SFR_HTOW_OPC_MASK _ULL(0x3) /* OPCode trap owner */ +#define KVX_SFR_HTOW_OPC_SHIFT 0 +#define KVX_SFR_HTOW_OPC_WIDTH 2 +#define KVX_SFR_HTOW_OPC_WFXL_MASK _ULL(0x3) +#define KVX_SFR_HTOW_OPC_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_HTOW_OPC_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_HTOW_DMIS_MASK _ULL(0xc) /* Data MISalign access trap owner */ +#define KVX_SFR_HTOW_DMIS_SHIFT 2 +#define KVX_SFR_HTOW_DMIS_WIDTH 2 +#define KVX_SFR_HTOW_DMIS_WFXL_MASK _ULL(0xc) +#define KVX_SFR_HTOW_DMIS_WFXL_CLEAR _ULL(0xc) +#define KVX_SFR_HTOW_DMIS_WFXL_SET _ULL(0xc00000000) + +#define KVX_SFR_HTOW_PSYS_MASK _ULL(0x30) /* Program System Error trap owner */ +#define KVX_SFR_HTOW_PSYS_SHIFT 4 +#define KVX_SFR_HTOW_PSYS_WIDTH 2 +#define KVX_SFR_HTOW_PSYS_WFXL_MASK _ULL(0x30) +#define KVX_SFR_HTOW_PSYS_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_HTOW_PSYS_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_HTOW_DSYS_MASK _ULL(0xc0) /* Data System Error trap owner */ +#define KVX_SFR_HTOW_DSYS_SHIFT 6 +#define KVX_SFR_HTOW_DSYS_WIDTH 2 +#define KVX_SFR_HTOW_DSYS_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_HTOW_DSYS_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_HTOW_DSYS_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_HTOW_DECCG_MASK _ULL(0x300) /* Double ECC traps group owner */ +#define KVX_SFR_HTOW_DECCG_SHIFT 8 +#define KVX_SFR_HTOW_DECCG_WIDTH 2 +#define KVX_SFR_HTOW_DECCG_WFXL_MASK _ULL(0x300) +#define KVX_SFR_HTOW_DECCG_WFXL_CLEAR _ULL(0x300) +#define KVX_SFR_HTOW_DECCG_WFXL_SET _ULL(0x30000000000) + +#define KVX_SFR_HTOW_SECCG_MASK _ULL(0xc00) /* Single ECC traps group owner */ +#define KVX_SFR_HTOW_SECCG_SHIFT 10 +#define KVX_SFR_HTOW_SECCG_WIDTH 2 +#define KVX_SFR_HTOW_SECCG_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_HTOW_SECCG_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_HTOW_SECCG_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_HTOW_NOMAP_MASK _ULL(0x3000) /* No mapping trap owner */ +#define KVX_SFR_HTOW_NOMAP_SHIFT 12 +#define KVX_SFR_HTOW_NOMAP_WIDTH 2 +#define KVX_SFR_HTOW_NOMAP_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_HTOW_NOMAP_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_HTOW_NOMAP_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_HTOW_PROT_MASK _ULL(0xc000) /* PROTection trap owner */ +#define KVX_SFR_HTOW_PROT_SHIFT 14 +#define KVX_SFR_HTOW_PROT_WIDTH 2 +#define KVX_SFR_HTOW_PROT_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_HTOW_PROT_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_HTOW_PROT_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_HTOW_W2CL_MASK _ULL(0x30000) /* Write to clean trap owner */ +#define KVX_SFR_HTOW_W2CL_SHIFT 16 +#define KVX_SFR_HTOW_W2CL_WIDTH 2 +#define KVX_SFR_HTOW_W2CL_WFXL_MASK _ULL(0x30000) +#define KVX_SFR_HTOW_W2CL_WFXL_CLEAR _ULL(0x30000) +#define KVX_SFR_HTOW_W2CL_WFXL_SET _ULL(0x3000000000000) + +#define KVX_SFR_HTOW_A2CL_MASK _ULL(0xc0000) /* Atomic to clean trap owner */ +#define KVX_SFR_HTOW_A2CL_SHIFT 18 +#define KVX_SFR_HTOW_A2CL_WIDTH 2 +#define KVX_SFR_HTOW_A2CL_WFXL_MASK _ULL(0xc0000) +#define KVX_SFR_HTOW_A2CL_WFXL_CLEAR _ULL(0xc0000) +#define KVX_SFR_HTOW_A2CL_WFXL_SET _ULL(0xc000000000000) + +#define KVX_SFR_HTOW_DE_MASK _ULL(0x300000) /* Double Exception trap owner */ +#define KVX_SFR_HTOW_DE_SHIFT 20 +#define KVX_SFR_HTOW_DE_WIDTH 2 +#define KVX_SFR_HTOW_DE_WFXL_MASK _ULL(0x300000) +#define KVX_SFR_HTOW_DE_WFXL_CLEAR _ULL(0x300000) +#define KVX_SFR_HTOW_DE_WFXL_SET _ULL(0x30000000000000) + +#define KVX_SFR_HTOW_VSFR_MASK _ULL(0xc00000) /* Virtual SFR trap owner */ +#define KVX_SFR_HTOW_VSFR_SHIFT 22 +#define KVX_SFR_HTOW_VSFR_WIDTH 2 +#define KVX_SFR_HTOW_VSFR_WFXL_MASK _ULL(0xc00000) +#define KVX_SFR_HTOW_VSFR_WFXL_CLEAR _ULL(0xc00000) +#define KVX_SFR_HTOW_VSFR_WFXL_SET _ULL(0xc0000000000000) + +#define KVX_SFR_HTOW_PLO_MASK _ULL(0x3000000) /* Privilege Level Overflow trap owner */ +#define KVX_SFR_HTOW_PLO_SHIFT 24 +#define KVX_SFR_HTOW_PLO_WIDTH 2 +#define KVX_SFR_HTOW_PLO_WFXL_MASK _ULL(0x3000000) +#define KVX_SFR_HTOW_PLO_WFXL_CLEAR _ULL(0x3000000) +#define KVX_SFR_HTOW_PLO_WFXL_SET _ULL(0x300000000000000) + +#define KVX_SFR_ITO_IT0_MASK _ULL(0x3) /* Interrupt 0 owner */ +#define KVX_SFR_ITO_IT0_SHIFT 0 +#define KVX_SFR_ITO_IT0_WIDTH 2 +#define KVX_SFR_ITO_IT0_WFXL_MASK _ULL(0x3) +#define KVX_SFR_ITO_IT0_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_ITO_IT0_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_ITO_IT1_MASK _ULL(0xc) /* Interrupt 1 owner */ +#define KVX_SFR_ITO_IT1_SHIFT 2 +#define KVX_SFR_ITO_IT1_WIDTH 2 +#define KVX_SFR_ITO_IT1_WFXL_MASK _ULL(0xc) +#define KVX_SFR_ITO_IT1_WFXL_CLEAR _ULL(0xc) +#define KVX_SFR_ITO_IT1_WFXL_SET _ULL(0xc00000000) + +#define KVX_SFR_ITO_IT2_MASK _ULL(0x30) /* Interrupt 2 owner */ +#define KVX_SFR_ITO_IT2_SHIFT 4 +#define KVX_SFR_ITO_IT2_WIDTH 2 +#define KVX_SFR_ITO_IT2_WFXL_MASK _ULL(0x30) +#define KVX_SFR_ITO_IT2_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_ITO_IT2_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_ITO_IT3_MASK _ULL(0xc0) /* Interrupt 3 owner */ +#define KVX_SFR_ITO_IT3_SHIFT 6 +#define KVX_SFR_ITO_IT3_WIDTH 2 +#define KVX_SFR_ITO_IT3_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_ITO_IT3_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_ITO_IT3_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_ITO_IT4_MASK _ULL(0x300) /* Interrupt 4 owner */ +#define KVX_SFR_ITO_IT4_SHIFT 8 +#define KVX_SFR_ITO_IT4_WIDTH 2 +#define KVX_SFR_ITO_IT4_WFXL_MASK _ULL(0x300) +#define KVX_SFR_ITO_IT4_WFXL_CLEAR _ULL(0x300) +#define KVX_SFR_ITO_IT4_WFXL_SET _ULL(0x30000000000) + +#define KVX_SFR_ITO_IT5_MASK _ULL(0xc00) /* Interrupt 5 owner */ +#define KVX_SFR_ITO_IT5_SHIFT 10 +#define KVX_SFR_ITO_IT5_WIDTH 2 +#define KVX_SFR_ITO_IT5_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_ITO_IT5_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_ITO_IT5_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_ITO_IT6_MASK _ULL(0x3000) /* Interrupt 6 owner */ +#define KVX_SFR_ITO_IT6_SHIFT 12 +#define KVX_SFR_ITO_IT6_WIDTH 2 +#define KVX_SFR_ITO_IT6_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_ITO_IT6_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_ITO_IT6_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_ITO_IT7_MASK _ULL(0xc000) /* Interrupt 7 owner */ +#define KVX_SFR_ITO_IT7_SHIFT 14 +#define KVX_SFR_ITO_IT7_WIDTH 2 +#define KVX_SFR_ITO_IT7_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_ITO_IT7_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_ITO_IT7_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_ITO_IT8_MASK _ULL(0x30000) /* Interrupt 8 owner */ +#define KVX_SFR_ITO_IT8_SHIFT 16 +#define KVX_SFR_ITO_IT8_WIDTH 2 +#define KVX_SFR_ITO_IT8_WFXL_MASK _ULL(0x30000) +#define KVX_SFR_ITO_IT8_WFXL_CLEAR _ULL(0x30000) +#define KVX_SFR_ITO_IT8_WFXL_SET _ULL(0x3000000000000) + +#define KVX_SFR_ITO_IT9_MASK _ULL(0xc0000) /* Interrupt 9 owner */ +#define KVX_SFR_ITO_IT9_SHIFT 18 +#define KVX_SFR_ITO_IT9_WIDTH 2 +#define KVX_SFR_ITO_IT9_WFXL_MASK _ULL(0xc0000) +#define KVX_SFR_ITO_IT9_WFXL_CLEAR _ULL(0xc0000) +#define KVX_SFR_ITO_IT9_WFXL_SET _ULL(0xc000000000000) + +#define KVX_SFR_ITO_IT10_MASK _ULL(0x300000) /* Interrupt 10 owner */ +#define KVX_SFR_ITO_IT10_SHIFT 20 +#define KVX_SFR_ITO_IT10_WIDTH 2 +#define KVX_SFR_ITO_IT10_WFXL_MASK _ULL(0x300000) +#define KVX_SFR_ITO_IT10_WFXL_CLEAR _ULL(0x300000) +#define KVX_SFR_ITO_IT10_WFXL_SET _ULL(0x30000000000000) + +#define KVX_SFR_ITO_IT11_MASK _ULL(0xc00000) /* Interrupt 11 owner */ +#define KVX_SFR_ITO_IT11_SHIFT 22 +#define KVX_SFR_ITO_IT11_WIDTH 2 +#define KVX_SFR_ITO_IT11_WFXL_MASK _ULL(0xc00000) +#define KVX_SFR_ITO_IT11_WFXL_CLEAR _ULL(0xc00000) +#define KVX_SFR_ITO_IT11_WFXL_SET _ULL(0xc0000000000000) + +#define KVX_SFR_ITO_IT12_MASK _ULL(0x3000000) /* Interrupt 12 owner */ +#define KVX_SFR_ITO_IT12_SHIFT 24 +#define KVX_SFR_ITO_IT12_WIDTH 2 +#define KVX_SFR_ITO_IT12_WFXL_MASK _ULL(0x3000000) +#define KVX_SFR_ITO_IT12_WFXL_CLEAR _ULL(0x3000000) +#define KVX_SFR_ITO_IT12_WFXL_SET _ULL(0x300000000000000) + +#define KVX_SFR_ITO_IT13_MASK _ULL(0xc000000) /* Interrupt 13 owner */ +#define KVX_SFR_ITO_IT13_SHIFT 26 +#define KVX_SFR_ITO_IT13_WIDTH 2 +#define KVX_SFR_ITO_IT13_WFXL_MASK _ULL(0xc000000) +#define KVX_SFR_ITO_IT13_WFXL_CLEAR _ULL(0xc000000) +#define KVX_SFR_ITO_IT13_WFXL_SET _ULL(0xc00000000000000) + +#define KVX_SFR_ITO_IT14_MASK _ULL(0x30000000) /* Interrupt 14 owner */ +#define KVX_SFR_ITO_IT14_SHIFT 28 +#define KVX_SFR_ITO_IT14_WIDTH 2 +#define KVX_SFR_ITO_IT14_WFXL_MASK _ULL(0x30000000) +#define KVX_SFR_ITO_IT14_WFXL_CLEAR _ULL(0x30000000) +#define KVX_SFR_ITO_IT14_WFXL_SET _ULL(0x3000000000000000) + +#define KVX_SFR_ITO_IT15_MASK _ULL(0xc0000000) /* Interrupt 15 owner */ +#define KVX_SFR_ITO_IT15_SHIFT 30 +#define KVX_SFR_ITO_IT15_WIDTH 2 +#define KVX_SFR_ITO_IT15_WFXL_MASK _ULL(0xc0000000) +#define KVX_SFR_ITO_IT15_WFXL_CLEAR _ULL(0xc0000000) +#define KVX_SFR_ITO_IT15_WFXL_SET _ULL(0xc000000000000000) + +#define KVX_SFR_ITO_IT16_MASK _ULL(0x300000000) /* Interrupt 16 owner */ +#define KVX_SFR_ITO_IT16_SHIFT 32 +#define KVX_SFR_ITO_IT16_WIDTH 2 +#define KVX_SFR_ITO_IT16_WFXM_MASK _ULL(0x300000000) +#define KVX_SFR_ITO_IT16_WFXM_CLEAR _ULL(0x3) +#define KVX_SFR_ITO_IT16_WFXM_SET _ULL(0x300000000) + +#define KVX_SFR_ITO_IT17_MASK _ULL(0xc00000000) /* Interrupt 17 owner */ +#define KVX_SFR_ITO_IT17_SHIFT 34 +#define KVX_SFR_ITO_IT17_WIDTH 2 +#define KVX_SFR_ITO_IT17_WFXM_MASK _ULL(0xc00000000) +#define KVX_SFR_ITO_IT17_WFXM_CLEAR _ULL(0xc) +#define KVX_SFR_ITO_IT17_WFXM_SET _ULL(0xc00000000) + +#define KVX_SFR_ITO_IT18_MASK _ULL(0x3000000000) /* Interrupt 18 owner */ +#define KVX_SFR_ITO_IT18_SHIFT 36 +#define KVX_SFR_ITO_IT18_WIDTH 2 +#define KVX_SFR_ITO_IT18_WFXM_MASK _ULL(0x3000000000) +#define KVX_SFR_ITO_IT18_WFXM_CLEAR _ULL(0x30) +#define KVX_SFR_ITO_IT18_WFXM_SET _ULL(0x3000000000) + +#define KVX_SFR_ITO_IT19_MASK _ULL(0xc000000000) /* Interrupt 19 owner */ +#define KVX_SFR_ITO_IT19_SHIFT 38 +#define KVX_SFR_ITO_IT19_WIDTH 2 +#define KVX_SFR_ITO_IT19_WFXM_MASK _ULL(0xc000000000) +#define KVX_SFR_ITO_IT19_WFXM_CLEAR _ULL(0xc0) +#define KVX_SFR_ITO_IT19_WFXM_SET _ULL(0xc000000000) + +#define KVX_SFR_ITO_IT20_MASK _ULL(0x30000000000) /* Interrupt 20 owner */ +#define KVX_SFR_ITO_IT20_SHIFT 40 +#define KVX_SFR_ITO_IT20_WIDTH 2 +#define KVX_SFR_ITO_IT20_WFXM_MASK _ULL(0x30000000000) +#define KVX_SFR_ITO_IT20_WFXM_CLEAR _ULL(0x300) +#define KVX_SFR_ITO_IT20_WFXM_SET _ULL(0x30000000000) + +#define KVX_SFR_ITO_IT21_MASK _ULL(0xc0000000000) /* Interrupt 21 owner */ +#define KVX_SFR_ITO_IT21_SHIFT 42 +#define KVX_SFR_ITO_IT21_WIDTH 2 +#define KVX_SFR_ITO_IT21_WFXM_MASK _ULL(0xc0000000000) +#define KVX_SFR_ITO_IT21_WFXM_CLEAR _ULL(0xc00) +#define KVX_SFR_ITO_IT21_WFXM_SET _ULL(0xc0000000000) + +#define KVX_SFR_ITO_IT22_MASK _ULL(0x300000000000) /* Interrupt 22 owner */ +#define KVX_SFR_ITO_IT22_SHIFT 44 +#define KVX_SFR_ITO_IT22_WIDTH 2 +#define KVX_SFR_ITO_IT22_WFXM_MASK _ULL(0x300000000000) +#define KVX_SFR_ITO_IT22_WFXM_CLEAR _ULL(0x3000) +#define KVX_SFR_ITO_IT22_WFXM_SET _ULL(0x300000000000) + +#define KVX_SFR_ITO_IT23_MASK _ULL(0xc00000000000) /* Interrupt 23 owner */ +#define KVX_SFR_ITO_IT23_SHIFT 46 +#define KVX_SFR_ITO_IT23_WIDTH 2 +#define KVX_SFR_ITO_IT23_WFXM_MASK _ULL(0xc00000000000) +#define KVX_SFR_ITO_IT23_WFXM_CLEAR _ULL(0xc000) +#define KVX_SFR_ITO_IT23_WFXM_SET _ULL(0xc00000000000) + +#define KVX_SFR_ITO_IT24_MASK _ULL(0x3000000000000) /* Interrupt 24 owner */ +#define KVX_SFR_ITO_IT24_SHIFT 48 +#define KVX_SFR_ITO_IT24_WIDTH 2 +#define KVX_SFR_ITO_IT24_WFXM_MASK _ULL(0x3000000000000) +#define KVX_SFR_ITO_IT24_WFXM_CLEAR _ULL(0x30000) +#define KVX_SFR_ITO_IT24_WFXM_SET _ULL(0x3000000000000) + +#define KVX_SFR_ITO_IT25_MASK _ULL(0xc000000000000) /* Interrupt 25 owner */ +#define KVX_SFR_ITO_IT25_SHIFT 50 +#define KVX_SFR_ITO_IT25_WIDTH 2 +#define KVX_SFR_ITO_IT25_WFXM_MASK _ULL(0xc000000000000) +#define KVX_SFR_ITO_IT25_WFXM_CLEAR _ULL(0xc0000) +#define KVX_SFR_ITO_IT25_WFXM_SET _ULL(0xc000000000000) + +#define KVX_SFR_ITO_IT26_MASK _ULL(0x30000000000000) /* Interrupt 26 owner */ +#define KVX_SFR_ITO_IT26_SHIFT 52 +#define KVX_SFR_ITO_IT26_WIDTH 2 +#define KVX_SFR_ITO_IT26_WFXM_MASK _ULL(0x30000000000000) +#define KVX_SFR_ITO_IT26_WFXM_CLEAR _ULL(0x300000) +#define KVX_SFR_ITO_IT26_WFXM_SET _ULL(0x30000000000000) + +#define KVX_SFR_ITO_IT27_MASK _ULL(0xc0000000000000) /* Interrupt 27 owner */ +#define KVX_SFR_ITO_IT27_SHIFT 54 +#define KVX_SFR_ITO_IT27_WIDTH 2 +#define KVX_SFR_ITO_IT27_WFXM_MASK _ULL(0xc0000000000000) +#define KVX_SFR_ITO_IT27_WFXM_CLEAR _ULL(0xc00000) +#define KVX_SFR_ITO_IT27_WFXM_SET _ULL(0xc0000000000000) + +#define KVX_SFR_ITO_IT28_MASK _ULL(0x300000000000000) /* Interrupt 28 owner */ +#define KVX_SFR_ITO_IT28_SHIFT 56 +#define KVX_SFR_ITO_IT28_WIDTH 2 +#define KVX_SFR_ITO_IT28_WFXM_MASK _ULL(0x300000000000000) +#define KVX_SFR_ITO_IT28_WFXM_CLEAR _ULL(0x3000000) +#define KVX_SFR_ITO_IT28_WFXM_SET _ULL(0x300000000000000) + +#define KVX_SFR_ITO_IT29_MASK _ULL(0xc00000000000000) /* Interrupt 29 owner */ +#define KVX_SFR_ITO_IT29_SHIFT 58 +#define KVX_SFR_ITO_IT29_WIDTH 2 +#define KVX_SFR_ITO_IT29_WFXM_MASK _ULL(0xc00000000000000) +#define KVX_SFR_ITO_IT29_WFXM_CLEAR _ULL(0xc000000) +#define KVX_SFR_ITO_IT29_WFXM_SET _ULL(0xc00000000000000) + +#define KVX_SFR_ITO_IT30_MASK _ULL(0x3000000000000000) /* Interrupt 30 owner */ +#define KVX_SFR_ITO_IT30_SHIFT 60 +#define KVX_SFR_ITO_IT30_WIDTH 2 +#define KVX_SFR_ITO_IT30_WFXM_MASK _ULL(0x3000000000000000) +#define KVX_SFR_ITO_IT30_WFXM_CLEAR _ULL(0x30000000) +#define KVX_SFR_ITO_IT30_WFXM_SET _ULL(0x3000000000000000) + +#define KVX_SFR_ITO_IT31_MASK _ULL(0xc000000000000000) /* Interrupt 31 owner */ +#define KVX_SFR_ITO_IT31_SHIFT 62 +#define KVX_SFR_ITO_IT31_WIDTH 2 +#define KVX_SFR_ITO_IT31_WFXM_MASK _ULL(0xc000000000000000) +#define KVX_SFR_ITO_IT31_WFXM_CLEAR _ULL(0xc0000000) +#define KVX_SFR_ITO_IT31_WFXM_SET _ULL(0xc000000000000000) + +#define KVX_SFR_ILE_IT0_MASK _ULL(0x1) /* Interrupt 0 owner */ +#define KVX_SFR_ILE_IT0_SHIFT 0 +#define KVX_SFR_ILE_IT0_WIDTH 1 +#define KVX_SFR_ILE_IT0_WFXL_MASK _ULL(0x1) +#define KVX_SFR_ILE_IT0_WFXL_CLEAR _ULL(0x1) +#define KVX_SFR_ILE_IT0_WFXL_SET _ULL(0x100000000) + +#define KVX_SFR_ILE_IT1_MASK _ULL(0x2) /* Interrupt 1 owner */ +#define KVX_SFR_ILE_IT1_SHIFT 1 +#define KVX_SFR_ILE_IT1_WIDTH 1 +#define KVX_SFR_ILE_IT1_WFXL_MASK _ULL(0x2) +#define KVX_SFR_ILE_IT1_WFXL_CLEAR _ULL(0x2) +#define KVX_SFR_ILE_IT1_WFXL_SET _ULL(0x200000000) + +#define KVX_SFR_ILE_IT2_MASK _ULL(0x4) /* Interrupt 2 owner */ +#define KVX_SFR_ILE_IT2_SHIFT 2 +#define KVX_SFR_ILE_IT2_WIDTH 1 +#define KVX_SFR_ILE_IT2_WFXL_MASK _ULL(0x4) +#define KVX_SFR_ILE_IT2_WFXL_CLEAR _ULL(0x4) +#define KVX_SFR_ILE_IT2_WFXL_SET _ULL(0x400000000) + +#define KVX_SFR_ILE_IT3_MASK _ULL(0x8) /* Interrupt 3 owner */ +#define KVX_SFR_ILE_IT3_SHIFT 3 +#define KVX_SFR_ILE_IT3_WIDTH 1 +#define KVX_SFR_ILE_IT3_WFXL_MASK _ULL(0x8) +#define KVX_SFR_ILE_IT3_WFXL_CLEAR _ULL(0x8) +#define KVX_SFR_ILE_IT3_WFXL_SET _ULL(0x800000000) + +#define KVX_SFR_ILE_IT4_MASK _ULL(0x10) /* Interrupt 4 owner */ +#define KVX_SFR_ILE_IT4_SHIFT 4 +#define KVX_SFR_ILE_IT4_WIDTH 1 +#define KVX_SFR_ILE_IT4_WFXL_MASK _ULL(0x10) +#define KVX_SFR_ILE_IT4_WFXL_CLEAR _ULL(0x10) +#define KVX_SFR_ILE_IT4_WFXL_SET _ULL(0x1000000000) + +#define KVX_SFR_ILE_IT5_MASK _ULL(0x20) /* Interrupt 5 owner */ +#define KVX_SFR_ILE_IT5_SHIFT 5 +#define KVX_SFR_ILE_IT5_WIDTH 1 +#define KVX_SFR_ILE_IT5_WFXL_MASK _ULL(0x20) +#define KVX_SFR_ILE_IT5_WFXL_CLEAR _ULL(0x20) +#define KVX_SFR_ILE_IT5_WFXL_SET _ULL(0x2000000000) + +#define KVX_SFR_ILE_IT6_MASK _ULL(0x40) /* Interrupt 6 owner */ +#define KVX_SFR_ILE_IT6_SHIFT 6 +#define KVX_SFR_ILE_IT6_WIDTH 1 +#define KVX_SFR_ILE_IT6_WFXL_MASK _ULL(0x40) +#define KVX_SFR_ILE_IT6_WFXL_CLEAR _ULL(0x40) +#define KVX_SFR_ILE_IT6_WFXL_SET _ULL(0x4000000000) + +#define KVX_SFR_ILE_IT7_MASK _ULL(0x80) /* Interrupt 7 owner */ +#define KVX_SFR_ILE_IT7_SHIFT 7 +#define KVX_SFR_ILE_IT7_WIDTH 1 +#define KVX_SFR_ILE_IT7_WFXL_MASK _ULL(0x80) +#define KVX_SFR_ILE_IT7_WFXL_CLEAR _ULL(0x80) +#define KVX_SFR_ILE_IT7_WFXL_SET _ULL(0x8000000000) + +#define KVX_SFR_ILE_IT8_MASK _ULL(0x100) /* Interrupt 8 owner */ +#define KVX_SFR_ILE_IT8_SHIFT 8 +#define KVX_SFR_ILE_IT8_WIDTH 1 +#define KVX_SFR_ILE_IT8_WFXL_MASK _ULL(0x100) +#define KVX_SFR_ILE_IT8_WFXL_CLEAR _ULL(0x100) +#define KVX_SFR_ILE_IT8_WFXL_SET _ULL(0x10000000000) + +#define KVX_SFR_ILE_IT9_MASK _ULL(0x200) /* Interrupt 9 owner */ +#define KVX_SFR_ILE_IT9_SHIFT 9 +#define KVX_SFR_ILE_IT9_WIDTH 1 +#define KVX_SFR_ILE_IT9_WFXL_MASK _ULL(0x200) +#define KVX_SFR_ILE_IT9_WFXL_CLEAR _ULL(0x200) +#define KVX_SFR_ILE_IT9_WFXL_SET _ULL(0x20000000000) + +#define KVX_SFR_ILE_IT10_MASK _ULL(0x400) /* Interrupt 10 owner */ +#define KVX_SFR_ILE_IT10_SHIFT 10 +#define KVX_SFR_ILE_IT10_WIDTH 1 +#define KVX_SFR_ILE_IT10_WFXL_MASK _ULL(0x400) +#define KVX_SFR_ILE_IT10_WFXL_CLEAR _ULL(0x400) +#define KVX_SFR_ILE_IT10_WFXL_SET _ULL(0x40000000000) + +#define KVX_SFR_ILE_IT11_MASK _ULL(0x800) /* Interrupt 11 owner */ +#define KVX_SFR_ILE_IT11_SHIFT 11 +#define KVX_SFR_ILE_IT11_WIDTH 1 +#define KVX_SFR_ILE_IT11_WFXL_MASK _ULL(0x800) +#define KVX_SFR_ILE_IT11_WFXL_CLEAR _ULL(0x800) +#define KVX_SFR_ILE_IT11_WFXL_SET _ULL(0x80000000000) + +#define KVX_SFR_ILE_IT12_MASK _ULL(0x1000) /* Interrupt 12 owner */ +#define KVX_SFR_ILE_IT12_SHIFT 12 +#define KVX_SFR_ILE_IT12_WIDTH 1 +#define KVX_SFR_ILE_IT12_WFXL_MASK _ULL(0x1000) +#define KVX_SFR_ILE_IT12_WFXL_CLEAR _ULL(0x1000) +#define KVX_SFR_ILE_IT12_WFXL_SET _ULL(0x100000000000) + +#define KVX_SFR_ILE_IT13_MASK _ULL(0x2000) /* Interrupt 13 owner */ +#define KVX_SFR_ILE_IT13_SHIFT 13 +#define KVX_SFR_ILE_IT13_WIDTH 1 +#define KVX_SFR_ILE_IT13_WFXL_MASK _ULL(0x2000) +#define KVX_SFR_ILE_IT13_WFXL_CLEAR _ULL(0x2000) +#define KVX_SFR_ILE_IT13_WFXL_SET _ULL(0x200000000000) + +#define KVX_SFR_ILE_IT14_MASK _ULL(0x4000) /* Interrupt 14 owner */ +#define KVX_SFR_ILE_IT14_SHIFT 14 +#define KVX_SFR_ILE_IT14_WIDTH 1 +#define KVX_SFR_ILE_IT14_WFXL_MASK _ULL(0x4000) +#define KVX_SFR_ILE_IT14_WFXL_CLEAR _ULL(0x4000) +#define KVX_SFR_ILE_IT14_WFXL_SET _ULL(0x400000000000) + +#define KVX_SFR_ILE_IT15_MASK _ULL(0x8000) /* Interrupt 15 owner */ +#define KVX_SFR_ILE_IT15_SHIFT 15 +#define KVX_SFR_ILE_IT15_WIDTH 1 +#define KVX_SFR_ILE_IT15_WFXL_MASK _ULL(0x8000) +#define KVX_SFR_ILE_IT15_WFXL_CLEAR _ULL(0x8000) +#define KVX_SFR_ILE_IT15_WFXL_SET _ULL(0x800000000000) + +#define KVX_SFR_ILE_IT16_MASK _ULL(0x10000) /* Interrupt 16 owner */ +#define KVX_SFR_ILE_IT16_SHIFT 16 +#define KVX_SFR_ILE_IT16_WIDTH 1 +#define KVX_SFR_ILE_IT16_WFXL_MASK _ULL(0x10000) +#define KVX_SFR_ILE_IT16_WFXL_CLEAR _ULL(0x10000) +#define KVX_SFR_ILE_IT16_WFXL_SET _ULL(0x1000000000000) + +#define KVX_SFR_ILE_IT17_MASK _ULL(0x20000) /* Interrupt 17 owner */ +#define KVX_SFR_ILE_IT17_SHIFT 17 +#define KVX_SFR_ILE_IT17_WIDTH 1 +#define KVX_SFR_ILE_IT17_WFXL_MASK _ULL(0x20000) +#define KVX_SFR_ILE_IT17_WFXL_CLEAR _ULL(0x20000) +#define KVX_SFR_ILE_IT17_WFXL_SET _ULL(0x2000000000000) + +#define KVX_SFR_ILE_IT18_MASK _ULL(0x40000) /* Interrupt 18 owner */ +#define KVX_SFR_ILE_IT18_SHIFT 18 +#define KVX_SFR_ILE_IT18_WIDTH 1 +#define KVX_SFR_ILE_IT18_WFXL_MASK _ULL(0x40000) +#define KVX_SFR_ILE_IT18_WFXL_CLEAR _ULL(0x40000) +#define KVX_SFR_ILE_IT18_WFXL_SET _ULL(0x4000000000000) + +#define KVX_SFR_ILE_IT19_MASK _ULL(0x80000) /* Interrupt 19 owner */ +#define KVX_SFR_ILE_IT19_SHIFT 19 +#define KVX_SFR_ILE_IT19_WIDTH 1 +#define KVX_SFR_ILE_IT19_WFXL_MASK _ULL(0x80000) +#define KVX_SFR_ILE_IT19_WFXL_CLEAR _ULL(0x80000) +#define KVX_SFR_ILE_IT19_WFXL_SET _ULL(0x8000000000000) + +#define KVX_SFR_ILE_IT20_MASK _ULL(0x100000) /* Interrupt 20 owner */ +#define KVX_SFR_ILE_IT20_SHIFT 20 +#define KVX_SFR_ILE_IT20_WIDTH 1 +#define KVX_SFR_ILE_IT20_WFXL_MASK _ULL(0x100000) +#define KVX_SFR_ILE_IT20_WFXL_CLEAR _ULL(0x100000) +#define KVX_SFR_ILE_IT20_WFXL_SET _ULL(0x10000000000000) + +#define KVX_SFR_ILE_IT21_MASK _ULL(0x200000) /* Interrupt 21 owner */ +#define KVX_SFR_ILE_IT21_SHIFT 21 +#define KVX_SFR_ILE_IT21_WIDTH 1 +#define KVX_SFR_ILE_IT21_WFXL_MASK _ULL(0x200000) +#define KVX_SFR_ILE_IT21_WFXL_CLEAR _ULL(0x200000) +#define KVX_SFR_ILE_IT21_WFXL_SET _ULL(0x20000000000000) + +#define KVX_SFR_ILE_IT22_MASK _ULL(0x400000) /* Interrupt 22 owner */ +#define KVX_SFR_ILE_IT22_SHIFT 22 +#define KVX_SFR_ILE_IT22_WIDTH 1 +#define KVX_SFR_ILE_IT22_WFXL_MASK _ULL(0x400000) +#define KVX_SFR_ILE_IT22_WFXL_CLEAR _ULL(0x400000) +#define KVX_SFR_ILE_IT22_WFXL_SET _ULL(0x40000000000000) + +#define KVX_SFR_ILE_IT23_MASK _ULL(0x800000) /* Interrupt 23 owner */ +#define KVX_SFR_ILE_IT23_SHIFT 23 +#define KVX_SFR_ILE_IT23_WIDTH 1 +#define KVX_SFR_ILE_IT23_WFXL_MASK _ULL(0x800000) +#define KVX_SFR_ILE_IT23_WFXL_CLEAR _ULL(0x800000) +#define KVX_SFR_ILE_IT23_WFXL_SET _ULL(0x80000000000000) + +#define KVX_SFR_ILE_IT24_MASK _ULL(0x1000000) /* Interrupt 24 owner */ +#define KVX_SFR_ILE_IT24_SHIFT 24 +#define KVX_SFR_ILE_IT24_WIDTH 1 +#define KVX_SFR_ILE_IT24_WFXL_MASK _ULL(0x1000000) +#define KVX_SFR_ILE_IT24_WFXL_CLEAR _ULL(0x1000000) +#define KVX_SFR_ILE_IT24_WFXL_SET _ULL(0x100000000000000) + +#define KVX_SFR_ILE_IT25_MASK _ULL(0x2000000) /* Interrupt 25 owner */ +#define KVX_SFR_ILE_IT25_SHIFT 25 +#define KVX_SFR_ILE_IT25_WIDTH 1 +#define KVX_SFR_ILE_IT25_WFXL_MASK _ULL(0x2000000) +#define KVX_SFR_ILE_IT25_WFXL_CLEAR _ULL(0x2000000) +#define KVX_SFR_ILE_IT25_WFXL_SET _ULL(0x200000000000000) + +#define KVX_SFR_ILE_IT26_MASK _ULL(0x4000000) /* Interrupt 26 owner */ +#define KVX_SFR_ILE_IT26_SHIFT 26 +#define KVX_SFR_ILE_IT26_WIDTH 1 +#define KVX_SFR_ILE_IT26_WFXL_MASK _ULL(0x4000000) +#define KVX_SFR_ILE_IT26_WFXL_CLEAR _ULL(0x4000000) +#define KVX_SFR_ILE_IT26_WFXL_SET _ULL(0x400000000000000) + +#define KVX_SFR_ILE_IT27_MASK _ULL(0x8000000) /* Interrupt 27 owner */ +#define KVX_SFR_ILE_IT27_SHIFT 27 +#define KVX_SFR_ILE_IT27_WIDTH 1 +#define KVX_SFR_ILE_IT27_WFXL_MASK _ULL(0x8000000) +#define KVX_SFR_ILE_IT27_WFXL_CLEAR _ULL(0x8000000) +#define KVX_SFR_ILE_IT27_WFXL_SET _ULL(0x800000000000000) + +#define KVX_SFR_ILE_IT28_MASK _ULL(0x10000000) /* Interrupt 28 owner */ +#define KVX_SFR_ILE_IT28_SHIFT 28 +#define KVX_SFR_ILE_IT28_WIDTH 1 +#define KVX_SFR_ILE_IT28_WFXL_MASK _ULL(0x10000000) +#define KVX_SFR_ILE_IT28_WFXL_CLEAR _ULL(0x10000000) +#define KVX_SFR_ILE_IT28_WFXL_SET _ULL(0x1000000000000000) + +#define KVX_SFR_ILE_IT29_MASK _ULL(0x20000000) /* Interrupt 29 owner */ +#define KVX_SFR_ILE_IT29_SHIFT 29 +#define KVX_SFR_ILE_IT29_WIDTH 1 +#define KVX_SFR_ILE_IT29_WFXL_MASK _ULL(0x20000000) +#define KVX_SFR_ILE_IT29_WFXL_CLEAR _ULL(0x20000000) +#define KVX_SFR_ILE_IT29_WFXL_SET _ULL(0x2000000000000000) + +#define KVX_SFR_ILE_IT30_MASK _ULL(0x40000000) /* Interrupt 30 owner */ +#define KVX_SFR_ILE_IT30_SHIFT 30 +#define KVX_SFR_ILE_IT30_WIDTH 1 +#define KVX_SFR_ILE_IT30_WFXL_MASK _ULL(0x40000000) +#define KVX_SFR_ILE_IT30_WFXL_CLEAR _ULL(0x40000000) +#define KVX_SFR_ILE_IT30_WFXL_SET _ULL(0x4000000000000000) + +#define KVX_SFR_ILE_IT31_MASK _ULL(0x80000000) /* Interrupt 31 owner */ +#define KVX_SFR_ILE_IT31_SHIFT 31 +#define KVX_SFR_ILE_IT31_WIDTH 1 +#define KVX_SFR_ILE_IT31_WFXL_MASK _ULL(0x80000000) +#define KVX_SFR_ILE_IT31_WFXL_CLEAR _ULL(0x80000000) +#define KVX_SFR_ILE_IT31_WFXL_SET _ULL(0x8000000000000000) + +#define KVX_SFR_ILL_IT0_MASK _ULL(0x3) /* Interrupt 0 owner */ +#define KVX_SFR_ILL_IT0_SHIFT 0 +#define KVX_SFR_ILL_IT0_WIDTH 2 +#define KVX_SFR_ILL_IT0_WFXL_MASK _ULL(0x3) +#define KVX_SFR_ILL_IT0_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_ILL_IT0_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_ILL_IT1_MASK _ULL(0xc) /* Interrupt 1 owner */ +#define KVX_SFR_ILL_IT1_SHIFT 2 +#define KVX_SFR_ILL_IT1_WIDTH 2 +#define KVX_SFR_ILL_IT1_WFXL_MASK _ULL(0xc) +#define KVX_SFR_ILL_IT1_WFXL_CLEAR _ULL(0xc) +#define KVX_SFR_ILL_IT1_WFXL_SET _ULL(0xc00000000) + +#define KVX_SFR_ILL_IT2_MASK _ULL(0x30) /* Interrupt 2 owner */ +#define KVX_SFR_ILL_IT2_SHIFT 4 +#define KVX_SFR_ILL_IT2_WIDTH 2 +#define KVX_SFR_ILL_IT2_WFXL_MASK _ULL(0x30) +#define KVX_SFR_ILL_IT2_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_ILL_IT2_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_ILL_IT3_MASK _ULL(0xc0) /* Interrupt 3 owner */ +#define KVX_SFR_ILL_IT3_SHIFT 6 +#define KVX_SFR_ILL_IT3_WIDTH 2 +#define KVX_SFR_ILL_IT3_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_ILL_IT3_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_ILL_IT3_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_ILL_IT4_MASK _ULL(0x300) /* Interrupt 4 owner */ +#define KVX_SFR_ILL_IT4_SHIFT 8 +#define KVX_SFR_ILL_IT4_WIDTH 2 +#define KVX_SFR_ILL_IT4_WFXL_MASK _ULL(0x300) +#define KVX_SFR_ILL_IT4_WFXL_CLEAR _ULL(0x300) +#define KVX_SFR_ILL_IT4_WFXL_SET _ULL(0x30000000000) + +#define KVX_SFR_ILL_IT5_MASK _ULL(0xc00) /* Interrupt 5 owner */ +#define KVX_SFR_ILL_IT5_SHIFT 10 +#define KVX_SFR_ILL_IT5_WIDTH 2 +#define KVX_SFR_ILL_IT5_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_ILL_IT5_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_ILL_IT5_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_ILL_IT6_MASK _ULL(0x3000) /* Interrupt 6 owner */ +#define KVX_SFR_ILL_IT6_SHIFT 12 +#define KVX_SFR_ILL_IT6_WIDTH 2 +#define KVX_SFR_ILL_IT6_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_ILL_IT6_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_ILL_IT6_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_ILL_IT7_MASK _ULL(0xc000) /* Interrupt 7 owner */ +#define KVX_SFR_ILL_IT7_SHIFT 14 +#define KVX_SFR_ILL_IT7_WIDTH 2 +#define KVX_SFR_ILL_IT7_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_ILL_IT7_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_ILL_IT7_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_ILL_IT8_MASK _ULL(0x30000) /* Interrupt 8 owner */ +#define KVX_SFR_ILL_IT8_SHIFT 16 +#define KVX_SFR_ILL_IT8_WIDTH 2 +#define KVX_SFR_ILL_IT8_WFXL_MASK _ULL(0x30000) +#define KVX_SFR_ILL_IT8_WFXL_CLEAR _ULL(0x30000) +#define KVX_SFR_ILL_IT8_WFXL_SET _ULL(0x3000000000000) + +#define KVX_SFR_ILL_IT9_MASK _ULL(0xc0000) /* Interrupt 9 owner */ +#define KVX_SFR_ILL_IT9_SHIFT 18 +#define KVX_SFR_ILL_IT9_WIDTH 2 +#define KVX_SFR_ILL_IT9_WFXL_MASK _ULL(0xc0000) +#define KVX_SFR_ILL_IT9_WFXL_CLEAR _ULL(0xc0000) +#define KVX_SFR_ILL_IT9_WFXL_SET _ULL(0xc000000000000) + +#define KVX_SFR_ILL_IT10_MASK _ULL(0x300000) /* Interrupt 10 owner */ +#define KVX_SFR_ILL_IT10_SHIFT 20 +#define KVX_SFR_ILL_IT10_WIDTH 2 +#define KVX_SFR_ILL_IT10_WFXL_MASK _ULL(0x300000) +#define KVX_SFR_ILL_IT10_WFXL_CLEAR _ULL(0x300000) +#define KVX_SFR_ILL_IT10_WFXL_SET _ULL(0x30000000000000) + +#define KVX_SFR_ILL_IT11_MASK _ULL(0xc00000) /* Interrupt 11 owner */ +#define KVX_SFR_ILL_IT11_SHIFT 22 +#define KVX_SFR_ILL_IT11_WIDTH 2 +#define KVX_SFR_ILL_IT11_WFXL_MASK _ULL(0xc00000) +#define KVX_SFR_ILL_IT11_WFXL_CLEAR _ULL(0xc00000) +#define KVX_SFR_ILL_IT11_WFXL_SET _ULL(0xc0000000000000) + +#define KVX_SFR_ILL_IT12_MASK _ULL(0x3000000) /* Interrupt 12 owner */ +#define KVX_SFR_ILL_IT12_SHIFT 24 +#define KVX_SFR_ILL_IT12_WIDTH 2 +#define KVX_SFR_ILL_IT12_WFXL_MASK _ULL(0x3000000) +#define KVX_SFR_ILL_IT12_WFXL_CLEAR _ULL(0x3000000) +#define KVX_SFR_ILL_IT12_WFXL_SET _ULL(0x300000000000000) + +#define KVX_SFR_ILL_IT13_MASK _ULL(0xc000000) /* Interrupt 13 owner */ +#define KVX_SFR_ILL_IT13_SHIFT 26 +#define KVX_SFR_ILL_IT13_WIDTH 2 +#define KVX_SFR_ILL_IT13_WFXL_MASK _ULL(0xc000000) +#define KVX_SFR_ILL_IT13_WFXL_CLEAR _ULL(0xc000000) +#define KVX_SFR_ILL_IT13_WFXL_SET _ULL(0xc00000000000000) + +#define KVX_SFR_ILL_IT14_MASK _ULL(0x30000000) /* Interrupt 14 owner */ +#define KVX_SFR_ILL_IT14_SHIFT 28 +#define KVX_SFR_ILL_IT14_WIDTH 2 +#define KVX_SFR_ILL_IT14_WFXL_MASK _ULL(0x30000000) +#define KVX_SFR_ILL_IT14_WFXL_CLEAR _ULL(0x30000000) +#define KVX_SFR_ILL_IT14_WFXL_SET _ULL(0x3000000000000000) + +#define KVX_SFR_ILL_IT15_MASK _ULL(0xc0000000) /* Interrupt 15 owner */ +#define KVX_SFR_ILL_IT15_SHIFT 30 +#define KVX_SFR_ILL_IT15_WIDTH 2 +#define KVX_SFR_ILL_IT15_WFXL_MASK _ULL(0xc0000000) +#define KVX_SFR_ILL_IT15_WFXL_CLEAR _ULL(0xc0000000) +#define KVX_SFR_ILL_IT15_WFXL_SET _ULL(0xc000000000000000) + +#define KVX_SFR_ILL_IT16_MASK _ULL(0x300000000) /* Interrupt 16 owner */ +#define KVX_SFR_ILL_IT16_SHIFT 32 +#define KVX_SFR_ILL_IT16_WIDTH 2 +#define KVX_SFR_ILL_IT16_WFXM_MASK _ULL(0x300000000) +#define KVX_SFR_ILL_IT16_WFXM_CLEAR _ULL(0x3) +#define KVX_SFR_ILL_IT16_WFXM_SET _ULL(0x300000000) + +#define KVX_SFR_ILL_IT17_MASK _ULL(0xc00000000) /* Interrupt 17 owner */ +#define KVX_SFR_ILL_IT17_SHIFT 34 +#define KVX_SFR_ILL_IT17_WIDTH 2 +#define KVX_SFR_ILL_IT17_WFXM_MASK _ULL(0xc00000000) +#define KVX_SFR_ILL_IT17_WFXM_CLEAR _ULL(0xc) +#define KVX_SFR_ILL_IT17_WFXM_SET _ULL(0xc00000000) + +#define KVX_SFR_ILL_IT18_MASK _ULL(0x3000000000) /* Interrupt 18 owner */ +#define KVX_SFR_ILL_IT18_SHIFT 36 +#define KVX_SFR_ILL_IT18_WIDTH 2 +#define KVX_SFR_ILL_IT18_WFXM_MASK _ULL(0x3000000000) +#define KVX_SFR_ILL_IT18_WFXM_CLEAR _ULL(0x30) +#define KVX_SFR_ILL_IT18_WFXM_SET _ULL(0x3000000000) + +#define KVX_SFR_ILL_IT19_MASK _ULL(0xc000000000) /* Interrupt 19 owner */ +#define KVX_SFR_ILL_IT19_SHIFT 38 +#define KVX_SFR_ILL_IT19_WIDTH 2 +#define KVX_SFR_ILL_IT19_WFXM_MASK _ULL(0xc000000000) +#define KVX_SFR_ILL_IT19_WFXM_CLEAR _ULL(0xc0) +#define KVX_SFR_ILL_IT19_WFXM_SET _ULL(0xc000000000) + +#define KVX_SFR_ILL_IT20_MASK _ULL(0x30000000000) /* Interrupt 20 owner */ +#define KVX_SFR_ILL_IT20_SHIFT 40 +#define KVX_SFR_ILL_IT20_WIDTH 2 +#define KVX_SFR_ILL_IT20_WFXM_MASK _ULL(0x30000000000) +#define KVX_SFR_ILL_IT20_WFXM_CLEAR _ULL(0x300) +#define KVX_SFR_ILL_IT20_WFXM_SET _ULL(0x30000000000) + +#define KVX_SFR_ILL_IT21_MASK _ULL(0xc0000000000) /* Interrupt 21 owner */ +#define KVX_SFR_ILL_IT21_SHIFT 42 +#define KVX_SFR_ILL_IT21_WIDTH 2 +#define KVX_SFR_ILL_IT21_WFXM_MASK _ULL(0xc0000000000) +#define KVX_SFR_ILL_IT21_WFXM_CLEAR _ULL(0xc00) +#define KVX_SFR_ILL_IT21_WFXM_SET _ULL(0xc0000000000) + +#define KVX_SFR_ILL_IT22_MASK _ULL(0x300000000000) /* Interrupt 22 owner */ +#define KVX_SFR_ILL_IT22_SHIFT 44 +#define KVX_SFR_ILL_IT22_WIDTH 2 +#define KVX_SFR_ILL_IT22_WFXM_MASK _ULL(0x300000000000) +#define KVX_SFR_ILL_IT22_WFXM_CLEAR _ULL(0x3000) +#define KVX_SFR_ILL_IT22_WFXM_SET _ULL(0x300000000000) + +#define KVX_SFR_ILL_IT23_MASK _ULL(0xc00000000000) /* Interrupt 23 owner */ +#define KVX_SFR_ILL_IT23_SHIFT 46 +#define KVX_SFR_ILL_IT23_WIDTH 2 +#define KVX_SFR_ILL_IT23_WFXM_MASK _ULL(0xc00000000000) +#define KVX_SFR_ILL_IT23_WFXM_CLEAR _ULL(0xc000) +#define KVX_SFR_ILL_IT23_WFXM_SET _ULL(0xc00000000000) + +#define KVX_SFR_ILL_IT24_MASK _ULL(0x3000000000000) /* Interrupt 24 owner */ +#define KVX_SFR_ILL_IT24_SHIFT 48 +#define KVX_SFR_ILL_IT24_WIDTH 2 +#define KVX_SFR_ILL_IT24_WFXM_MASK _ULL(0x3000000000000) +#define KVX_SFR_ILL_IT24_WFXM_CLEAR _ULL(0x30000) +#define KVX_SFR_ILL_IT24_WFXM_SET _ULL(0x3000000000000) + +#define KVX_SFR_ILL_IT25_MASK _ULL(0xc000000000000) /* Interrupt 25 owner */ +#define KVX_SFR_ILL_IT25_SHIFT 50 +#define KVX_SFR_ILL_IT25_WIDTH 2 +#define KVX_SFR_ILL_IT25_WFXM_MASK _ULL(0xc000000000000) +#define KVX_SFR_ILL_IT25_WFXM_CLEAR _ULL(0xc0000) +#define KVX_SFR_ILL_IT25_WFXM_SET _ULL(0xc000000000000) + +#define KVX_SFR_ILL_IT26_MASK _ULL(0x30000000000000) /* Interrupt 26 owner */ +#define KVX_SFR_ILL_IT26_SHIFT 52 +#define KVX_SFR_ILL_IT26_WIDTH 2 +#define KVX_SFR_ILL_IT26_WFXM_MASK _ULL(0x30000000000000) +#define KVX_SFR_ILL_IT26_WFXM_CLEAR _ULL(0x300000) +#define KVX_SFR_ILL_IT26_WFXM_SET _ULL(0x30000000000000) + +#define KVX_SFR_ILL_IT27_MASK _ULL(0xc0000000000000) /* Interrupt 27 owner */ +#define KVX_SFR_ILL_IT27_SHIFT 54 +#define KVX_SFR_ILL_IT27_WIDTH 2 +#define KVX_SFR_ILL_IT27_WFXM_MASK _ULL(0xc0000000000000) +#define KVX_SFR_ILL_IT27_WFXM_CLEAR _ULL(0xc00000) +#define KVX_SFR_ILL_IT27_WFXM_SET _ULL(0xc0000000000000) + +#define KVX_SFR_ILL_IT28_MASK _ULL(0x300000000000000) /* Interrupt 28 owner */ +#define KVX_SFR_ILL_IT28_SHIFT 56 +#define KVX_SFR_ILL_IT28_WIDTH 2 +#define KVX_SFR_ILL_IT28_WFXM_MASK _ULL(0x300000000000000) +#define KVX_SFR_ILL_IT28_WFXM_CLEAR _ULL(0x3000000) +#define KVX_SFR_ILL_IT28_WFXM_SET _ULL(0x300000000000000) + +#define KVX_SFR_ILL_IT29_MASK _ULL(0xc00000000000000) /* Interrupt 29 owner */ +#define KVX_SFR_ILL_IT29_SHIFT 58 +#define KVX_SFR_ILL_IT29_WIDTH 2 +#define KVX_SFR_ILL_IT29_WFXM_MASK _ULL(0xc00000000000000) +#define KVX_SFR_ILL_IT29_WFXM_CLEAR _ULL(0xc000000) +#define KVX_SFR_ILL_IT29_WFXM_SET _ULL(0xc00000000000000) + +#define KVX_SFR_ILL_IT30_MASK _ULL(0x3000000000000000) /* Interrupt 30 owner */ +#define KVX_SFR_ILL_IT30_SHIFT 60 +#define KVX_SFR_ILL_IT30_WIDTH 2 +#define KVX_SFR_ILL_IT30_WFXM_MASK _ULL(0x3000000000000000) +#define KVX_SFR_ILL_IT30_WFXM_CLEAR _ULL(0x30000000) +#define KVX_SFR_ILL_IT30_WFXM_SET _ULL(0x3000000000000000) + +#define KVX_SFR_ILL_IT31_MASK _ULL(0xc000000000000000) /* Interrupt 31 owner */ +#define KVX_SFR_ILL_IT31_SHIFT 62 +#define KVX_SFR_ILL_IT31_WIDTH 2 +#define KVX_SFR_ILL_IT31_WFXM_MASK _ULL(0xc000000000000000) +#define KVX_SFR_ILL_IT31_WFXM_CLEAR _ULL(0xc0000000) +#define KVX_SFR_ILL_IT31_WFXM_SET _ULL(0xc000000000000000) + +#define KVX_SFR_ILR_IT0_MASK _ULL(0x1) /* Interrupt 0 owner */ +#define KVX_SFR_ILR_IT0_SHIFT 0 +#define KVX_SFR_ILR_IT0_WIDTH 1 +#define KVX_SFR_ILR_IT0_WFXL_MASK _ULL(0x1) +#define KVX_SFR_ILR_IT0_WFXL_CLEAR _ULL(0x1) +#define KVX_SFR_ILR_IT0_WFXL_SET _ULL(0x100000000) + +#define KVX_SFR_ILR_IT1_MASK _ULL(0x2) /* Interrupt 1 owner */ +#define KVX_SFR_ILR_IT1_SHIFT 1 +#define KVX_SFR_ILR_IT1_WIDTH 1 +#define KVX_SFR_ILR_IT1_WFXL_MASK _ULL(0x2) +#define KVX_SFR_ILR_IT1_WFXL_CLEAR _ULL(0x2) +#define KVX_SFR_ILR_IT1_WFXL_SET _ULL(0x200000000) + +#define KVX_SFR_ILR_IT2_MASK _ULL(0x4) /* Interrupt 2 owner */ +#define KVX_SFR_ILR_IT2_SHIFT 2 +#define KVX_SFR_ILR_IT2_WIDTH 1 +#define KVX_SFR_ILR_IT2_WFXL_MASK _ULL(0x4) +#define KVX_SFR_ILR_IT2_WFXL_CLEAR _ULL(0x4) +#define KVX_SFR_ILR_IT2_WFXL_SET _ULL(0x400000000) + +#define KVX_SFR_ILR_IT3_MASK _ULL(0x8) /* Interrupt 3 owner */ +#define KVX_SFR_ILR_IT3_SHIFT 3 +#define KVX_SFR_ILR_IT3_WIDTH 1 +#define KVX_SFR_ILR_IT3_WFXL_MASK _ULL(0x8) +#define KVX_SFR_ILR_IT3_WFXL_CLEAR _ULL(0x8) +#define KVX_SFR_ILR_IT3_WFXL_SET _ULL(0x800000000) + +#define KVX_SFR_ILR_IT4_MASK _ULL(0x10) /* Interrupt 4 owner */ +#define KVX_SFR_ILR_IT4_SHIFT 4 +#define KVX_SFR_ILR_IT4_WIDTH 1 +#define KVX_SFR_ILR_IT4_WFXL_MASK _ULL(0x10) +#define KVX_SFR_ILR_IT4_WFXL_CLEAR _ULL(0x10) +#define KVX_SFR_ILR_IT4_WFXL_SET _ULL(0x1000000000) + +#define KVX_SFR_ILR_IT5_MASK _ULL(0x20) /* Interrupt 5 owner */ +#define KVX_SFR_ILR_IT5_SHIFT 5 +#define KVX_SFR_ILR_IT5_WIDTH 1 +#define KVX_SFR_ILR_IT5_WFXL_MASK _ULL(0x20) +#define KVX_SFR_ILR_IT5_WFXL_CLEAR _ULL(0x20) +#define KVX_SFR_ILR_IT5_WFXL_SET _ULL(0x2000000000) + +#define KVX_SFR_ILR_IT6_MASK _ULL(0x40) /* Interrupt 6 owner */ +#define KVX_SFR_ILR_IT6_SHIFT 6 +#define KVX_SFR_ILR_IT6_WIDTH 1 +#define KVX_SFR_ILR_IT6_WFXL_MASK _ULL(0x40) +#define KVX_SFR_ILR_IT6_WFXL_CLEAR _ULL(0x40) +#define KVX_SFR_ILR_IT6_WFXL_SET _ULL(0x4000000000) + +#define KVX_SFR_ILR_IT7_MASK _ULL(0x80) /* Interrupt 7 owner */ +#define KVX_SFR_ILR_IT7_SHIFT 7 +#define KVX_SFR_ILR_IT7_WIDTH 1 +#define KVX_SFR_ILR_IT7_WFXL_MASK _ULL(0x80) +#define KVX_SFR_ILR_IT7_WFXL_CLEAR _ULL(0x80) +#define KVX_SFR_ILR_IT7_WFXL_SET _ULL(0x8000000000) + +#define KVX_SFR_ILR_IT8_MASK _ULL(0x100) /* Interrupt 8 owner */ +#define KVX_SFR_ILR_IT8_SHIFT 8 +#define KVX_SFR_ILR_IT8_WIDTH 1 +#define KVX_SFR_ILR_IT8_WFXL_MASK _ULL(0x100) +#define KVX_SFR_ILR_IT8_WFXL_CLEAR _ULL(0x100) +#define KVX_SFR_ILR_IT8_WFXL_SET _ULL(0x10000000000) + +#define KVX_SFR_ILR_IT9_MASK _ULL(0x200) /* Interrupt 9 owner */ +#define KVX_SFR_ILR_IT9_SHIFT 9 +#define KVX_SFR_ILR_IT9_WIDTH 1 +#define KVX_SFR_ILR_IT9_WFXL_MASK _ULL(0x200) +#define KVX_SFR_ILR_IT9_WFXL_CLEAR _ULL(0x200) +#define KVX_SFR_ILR_IT9_WFXL_SET _ULL(0x20000000000) + +#define KVX_SFR_ILR_IT10_MASK _ULL(0x400) /* Interrupt 10 owner */ +#define KVX_SFR_ILR_IT10_SHIFT 10 +#define KVX_SFR_ILR_IT10_WIDTH 1 +#define KVX_SFR_ILR_IT10_WFXL_MASK _ULL(0x400) +#define KVX_SFR_ILR_IT10_WFXL_CLEAR _ULL(0x400) +#define KVX_SFR_ILR_IT10_WFXL_SET _ULL(0x40000000000) + +#define KVX_SFR_ILR_IT11_MASK _ULL(0x800) /* Interrupt 11 owner */ +#define KVX_SFR_ILR_IT11_SHIFT 11 +#define KVX_SFR_ILR_IT11_WIDTH 1 +#define KVX_SFR_ILR_IT11_WFXL_MASK _ULL(0x800) +#define KVX_SFR_ILR_IT11_WFXL_CLEAR _ULL(0x800) +#define KVX_SFR_ILR_IT11_WFXL_SET _ULL(0x80000000000) + +#define KVX_SFR_ILR_IT12_MASK _ULL(0x1000) /* Interrupt 12 owner */ +#define KVX_SFR_ILR_IT12_SHIFT 12 +#define KVX_SFR_ILR_IT12_WIDTH 1 +#define KVX_SFR_ILR_IT12_WFXL_MASK _ULL(0x1000) +#define KVX_SFR_ILR_IT12_WFXL_CLEAR _ULL(0x1000) +#define KVX_SFR_ILR_IT12_WFXL_SET _ULL(0x100000000000) + +#define KVX_SFR_ILR_IT13_MASK _ULL(0x2000) /* Interrupt 13 owner */ +#define KVX_SFR_ILR_IT13_SHIFT 13 +#define KVX_SFR_ILR_IT13_WIDTH 1 +#define KVX_SFR_ILR_IT13_WFXL_MASK _ULL(0x2000) +#define KVX_SFR_ILR_IT13_WFXL_CLEAR _ULL(0x2000) +#define KVX_SFR_ILR_IT13_WFXL_SET _ULL(0x200000000000) + +#define KVX_SFR_ILR_IT14_MASK _ULL(0x4000) /* Interrupt 14 owner */ +#define KVX_SFR_ILR_IT14_SHIFT 14 +#define KVX_SFR_ILR_IT14_WIDTH 1 +#define KVX_SFR_ILR_IT14_WFXL_MASK _ULL(0x4000) +#define KVX_SFR_ILR_IT14_WFXL_CLEAR _ULL(0x4000) +#define KVX_SFR_ILR_IT14_WFXL_SET _ULL(0x400000000000) + +#define KVX_SFR_ILR_IT15_MASK _ULL(0x8000) /* Interrupt 15 owner */ +#define KVX_SFR_ILR_IT15_SHIFT 15 +#define KVX_SFR_ILR_IT15_WIDTH 1 +#define KVX_SFR_ILR_IT15_WFXL_MASK _ULL(0x8000) +#define KVX_SFR_ILR_IT15_WFXL_CLEAR _ULL(0x8000) +#define KVX_SFR_ILR_IT15_WFXL_SET _ULL(0x800000000000) + +#define KVX_SFR_ILR_IT16_MASK _ULL(0x10000) /* Interrupt 16 owner */ +#define KVX_SFR_ILR_IT16_SHIFT 16 +#define KVX_SFR_ILR_IT16_WIDTH 1 +#define KVX_SFR_ILR_IT16_WFXL_MASK _ULL(0x10000) +#define KVX_SFR_ILR_IT16_WFXL_CLEAR _ULL(0x10000) +#define KVX_SFR_ILR_IT16_WFXL_SET _ULL(0x1000000000000) + +#define KVX_SFR_ILR_IT17_MASK _ULL(0x20000) /* Interrupt 17 owner */ +#define KVX_SFR_ILR_IT17_SHIFT 17 +#define KVX_SFR_ILR_IT17_WIDTH 1 +#define KVX_SFR_ILR_IT17_WFXL_MASK _ULL(0x20000) +#define KVX_SFR_ILR_IT17_WFXL_CLEAR _ULL(0x20000) +#define KVX_SFR_ILR_IT17_WFXL_SET _ULL(0x2000000000000) + +#define KVX_SFR_ILR_IT18_MASK _ULL(0x40000) /* Interrupt 18 owner */ +#define KVX_SFR_ILR_IT18_SHIFT 18 +#define KVX_SFR_ILR_IT18_WIDTH 1 +#define KVX_SFR_ILR_IT18_WFXL_MASK _ULL(0x40000) +#define KVX_SFR_ILR_IT18_WFXL_CLEAR _ULL(0x40000) +#define KVX_SFR_ILR_IT18_WFXL_SET _ULL(0x4000000000000) + +#define KVX_SFR_ILR_IT19_MASK _ULL(0x80000) /* Interrupt 19 owner */ +#define KVX_SFR_ILR_IT19_SHIFT 19 +#define KVX_SFR_ILR_IT19_WIDTH 1 +#define KVX_SFR_ILR_IT19_WFXL_MASK _ULL(0x80000) +#define KVX_SFR_ILR_IT19_WFXL_CLEAR _ULL(0x80000) +#define KVX_SFR_ILR_IT19_WFXL_SET _ULL(0x8000000000000) + +#define KVX_SFR_ILR_IT20_MASK _ULL(0x100000) /* Interrupt 20 owner */ +#define KVX_SFR_ILR_IT20_SHIFT 20 +#define KVX_SFR_ILR_IT20_WIDTH 1 +#define KVX_SFR_ILR_IT20_WFXL_MASK _ULL(0x100000) +#define KVX_SFR_ILR_IT20_WFXL_CLEAR _ULL(0x100000) +#define KVX_SFR_ILR_IT20_WFXL_SET _ULL(0x10000000000000) + +#define KVX_SFR_ILR_IT21_MASK _ULL(0x200000) /* Interrupt 21 owner */ +#define KVX_SFR_ILR_IT21_SHIFT 21 +#define KVX_SFR_ILR_IT21_WIDTH 1 +#define KVX_SFR_ILR_IT21_WFXL_MASK _ULL(0x200000) +#define KVX_SFR_ILR_IT21_WFXL_CLEAR _ULL(0x200000) +#define KVX_SFR_ILR_IT21_WFXL_SET _ULL(0x20000000000000) + +#define KVX_SFR_ILR_IT22_MASK _ULL(0x400000) /* Interrupt 22 owner */ +#define KVX_SFR_ILR_IT22_SHIFT 22 +#define KVX_SFR_ILR_IT22_WIDTH 1 +#define KVX_SFR_ILR_IT22_WFXL_MASK _ULL(0x400000) +#define KVX_SFR_ILR_IT22_WFXL_CLEAR _ULL(0x400000) +#define KVX_SFR_ILR_IT22_WFXL_SET _ULL(0x40000000000000) + +#define KVX_SFR_ILR_IT23_MASK _ULL(0x800000) /* Interrupt 23 owner */ +#define KVX_SFR_ILR_IT23_SHIFT 23 +#define KVX_SFR_ILR_IT23_WIDTH 1 +#define KVX_SFR_ILR_IT23_WFXL_MASK _ULL(0x800000) +#define KVX_SFR_ILR_IT23_WFXL_CLEAR _ULL(0x800000) +#define KVX_SFR_ILR_IT23_WFXL_SET _ULL(0x80000000000000) + +#define KVX_SFR_ILR_IT24_MASK _ULL(0x1000000) /* Interrupt 24 owner */ +#define KVX_SFR_ILR_IT24_SHIFT 24 +#define KVX_SFR_ILR_IT24_WIDTH 1 +#define KVX_SFR_ILR_IT24_WFXL_MASK _ULL(0x1000000) +#define KVX_SFR_ILR_IT24_WFXL_CLEAR _ULL(0x1000000) +#define KVX_SFR_ILR_IT24_WFXL_SET _ULL(0x100000000000000) + +#define KVX_SFR_ILR_IT25_MASK _ULL(0x2000000) /* Interrupt 25 owner */ +#define KVX_SFR_ILR_IT25_SHIFT 25 +#define KVX_SFR_ILR_IT25_WIDTH 1 +#define KVX_SFR_ILR_IT25_WFXL_MASK _ULL(0x2000000) +#define KVX_SFR_ILR_IT25_WFXL_CLEAR _ULL(0x2000000) +#define KVX_SFR_ILR_IT25_WFXL_SET _ULL(0x200000000000000) + +#define KVX_SFR_ILR_IT26_MASK _ULL(0x4000000) /* Interrupt 26 owner */ +#define KVX_SFR_ILR_IT26_SHIFT 26 +#define KVX_SFR_ILR_IT26_WIDTH 1 +#define KVX_SFR_ILR_IT26_WFXL_MASK _ULL(0x4000000) +#define KVX_SFR_ILR_IT26_WFXL_CLEAR _ULL(0x4000000) +#define KVX_SFR_ILR_IT26_WFXL_SET _ULL(0x400000000000000) + +#define KVX_SFR_ILR_IT27_MASK _ULL(0x8000000) /* Interrupt 27 owner */ +#define KVX_SFR_ILR_IT27_SHIFT 27 +#define KVX_SFR_ILR_IT27_WIDTH 1 +#define KVX_SFR_ILR_IT27_WFXL_MASK _ULL(0x8000000) +#define KVX_SFR_ILR_IT27_WFXL_CLEAR _ULL(0x8000000) +#define KVX_SFR_ILR_IT27_WFXL_SET _ULL(0x800000000000000) + +#define KVX_SFR_ILR_IT28_MASK _ULL(0x10000000) /* Interrupt 28 owner */ +#define KVX_SFR_ILR_IT28_SHIFT 28 +#define KVX_SFR_ILR_IT28_WIDTH 1 +#define KVX_SFR_ILR_IT28_WFXL_MASK _ULL(0x10000000) +#define KVX_SFR_ILR_IT28_WFXL_CLEAR _ULL(0x10000000) +#define KVX_SFR_ILR_IT28_WFXL_SET _ULL(0x1000000000000000) + +#define KVX_SFR_ILR_IT29_MASK _ULL(0x20000000) /* Interrupt 29 owner */ +#define KVX_SFR_ILR_IT29_SHIFT 29 +#define KVX_SFR_ILR_IT29_WIDTH 1 +#define KVX_SFR_ILR_IT29_WFXL_MASK _ULL(0x20000000) +#define KVX_SFR_ILR_IT29_WFXL_CLEAR _ULL(0x20000000) +#define KVX_SFR_ILR_IT29_WFXL_SET _ULL(0x2000000000000000) + +#define KVX_SFR_ILR_IT30_MASK _ULL(0x40000000) /* Interrupt 30 owner */ +#define KVX_SFR_ILR_IT30_SHIFT 30 +#define KVX_SFR_ILR_IT30_WIDTH 1 +#define KVX_SFR_ILR_IT30_WFXL_MASK _ULL(0x40000000) +#define KVX_SFR_ILR_IT30_WFXL_CLEAR _ULL(0x40000000) +#define KVX_SFR_ILR_IT30_WFXL_SET _ULL(0x4000000000000000) + +#define KVX_SFR_ILR_IT31_MASK _ULL(0x80000000) /* Interrupt 31 owner */ +#define KVX_SFR_ILR_IT31_SHIFT 31 +#define KVX_SFR_ILR_IT31_WIDTH 1 +#define KVX_SFR_ILR_IT31_WFXL_MASK _ULL(0x80000000) +#define KVX_SFR_ILR_IT31_WFXL_CLEAR _ULL(0x80000000) +#define KVX_SFR_ILR_IT31_WFXL_SET _ULL(0x8000000000000000) + +#define KVX_SFR_ITOW_IT0_MASK _ULL(0x3) /* Interrupt 0 owner */ +#define KVX_SFR_ITOW_IT0_SHIFT 0 +#define KVX_SFR_ITOW_IT0_WIDTH 2 +#define KVX_SFR_ITOW_IT0_WFXL_MASK _ULL(0x3) +#define KVX_SFR_ITOW_IT0_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_ITOW_IT0_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_ITOW_IT1_MASK _ULL(0xc) /* Interrupt 1 owner */ +#define KVX_SFR_ITOW_IT1_SHIFT 2 +#define KVX_SFR_ITOW_IT1_WIDTH 2 +#define KVX_SFR_ITOW_IT1_WFXL_MASK _ULL(0xc) +#define KVX_SFR_ITOW_IT1_WFXL_CLEAR _ULL(0xc) +#define KVX_SFR_ITOW_IT1_WFXL_SET _ULL(0xc00000000) + +#define KVX_SFR_ITOW_IT2_MASK _ULL(0x30) /* Interrupt 2 owner */ +#define KVX_SFR_ITOW_IT2_SHIFT 4 +#define KVX_SFR_ITOW_IT2_WIDTH 2 +#define KVX_SFR_ITOW_IT2_WFXL_MASK _ULL(0x30) +#define KVX_SFR_ITOW_IT2_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_ITOW_IT2_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_ITOW_IT3_MASK _ULL(0xc0) /* Interrupt 3 owner */ +#define KVX_SFR_ITOW_IT3_SHIFT 6 +#define KVX_SFR_ITOW_IT3_WIDTH 2 +#define KVX_SFR_ITOW_IT3_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_ITOW_IT3_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_ITOW_IT3_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_ITOW_IT4_MASK _ULL(0x300) /* Interrupt 4 owner */ +#define KVX_SFR_ITOW_IT4_SHIFT 8 +#define KVX_SFR_ITOW_IT4_WIDTH 2 +#define KVX_SFR_ITOW_IT4_WFXL_MASK _ULL(0x300) +#define KVX_SFR_ITOW_IT4_WFXL_CLEAR _ULL(0x300) +#define KVX_SFR_ITOW_IT4_WFXL_SET _ULL(0x30000000000) + +#define KVX_SFR_ITOW_IT5_MASK _ULL(0xc00) /* Interrupt 5 owner */ +#define KVX_SFR_ITOW_IT5_SHIFT 10 +#define KVX_SFR_ITOW_IT5_WIDTH 2 +#define KVX_SFR_ITOW_IT5_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_ITOW_IT5_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_ITOW_IT5_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_ITOW_IT6_MASK _ULL(0x3000) /* Interrupt 6 owner */ +#define KVX_SFR_ITOW_IT6_SHIFT 12 +#define KVX_SFR_ITOW_IT6_WIDTH 2 +#define KVX_SFR_ITOW_IT6_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_ITOW_IT6_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_ITOW_IT6_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_ITOW_IT7_MASK _ULL(0xc000) /* Interrupt 7 owner */ +#define KVX_SFR_ITOW_IT7_SHIFT 14 +#define KVX_SFR_ITOW_IT7_WIDTH 2 +#define KVX_SFR_ITOW_IT7_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_ITOW_IT7_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_ITOW_IT7_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_ITOW_IT8_MASK _ULL(0x30000) /* Interrupt 8 owner */ +#define KVX_SFR_ITOW_IT8_SHIFT 16 +#define KVX_SFR_ITOW_IT8_WIDTH 2 +#define KVX_SFR_ITOW_IT8_WFXL_MASK _ULL(0x30000) +#define KVX_SFR_ITOW_IT8_WFXL_CLEAR _ULL(0x30000) +#define KVX_SFR_ITOW_IT8_WFXL_SET _ULL(0x3000000000000) + +#define KVX_SFR_ITOW_IT9_MASK _ULL(0xc0000) /* Interrupt 9 owner */ +#define KVX_SFR_ITOW_IT9_SHIFT 18 +#define KVX_SFR_ITOW_IT9_WIDTH 2 +#define KVX_SFR_ITOW_IT9_WFXL_MASK _ULL(0xc0000) +#define KVX_SFR_ITOW_IT9_WFXL_CLEAR _ULL(0xc0000) +#define KVX_SFR_ITOW_IT9_WFXL_SET _ULL(0xc000000000000) + +#define KVX_SFR_ITOW_IT10_MASK _ULL(0x300000) /* Interrupt 10 owner */ +#define KVX_SFR_ITOW_IT10_SHIFT 20 +#define KVX_SFR_ITOW_IT10_WIDTH 2 +#define KVX_SFR_ITOW_IT10_WFXL_MASK _ULL(0x300000) +#define KVX_SFR_ITOW_IT10_WFXL_CLEAR _ULL(0x300000) +#define KVX_SFR_ITOW_IT10_WFXL_SET _ULL(0x30000000000000) + +#define KVX_SFR_ITOW_IT11_MASK _ULL(0xc00000) /* Interrupt 11 owner */ +#define KVX_SFR_ITOW_IT11_SHIFT 22 +#define KVX_SFR_ITOW_IT11_WIDTH 2 +#define KVX_SFR_ITOW_IT11_WFXL_MASK _ULL(0xc00000) +#define KVX_SFR_ITOW_IT11_WFXL_CLEAR _ULL(0xc00000) +#define KVX_SFR_ITOW_IT11_WFXL_SET _ULL(0xc0000000000000) + +#define KVX_SFR_ITOW_IT12_MASK _ULL(0x3000000) /* Interrupt 12 owner */ +#define KVX_SFR_ITOW_IT12_SHIFT 24 +#define KVX_SFR_ITOW_IT12_WIDTH 2 +#define KVX_SFR_ITOW_IT12_WFXL_MASK _ULL(0x3000000) +#define KVX_SFR_ITOW_IT12_WFXL_CLEAR _ULL(0x3000000) +#define KVX_SFR_ITOW_IT12_WFXL_SET _ULL(0x300000000000000) + +#define KVX_SFR_ITOW_IT13_MASK _ULL(0xc000000) /* Interrupt 13 owner */ +#define KVX_SFR_ITOW_IT13_SHIFT 26 +#define KVX_SFR_ITOW_IT13_WIDTH 2 +#define KVX_SFR_ITOW_IT13_WFXL_MASK _ULL(0xc000000) +#define KVX_SFR_ITOW_IT13_WFXL_CLEAR _ULL(0xc000000) +#define KVX_SFR_ITOW_IT13_WFXL_SET _ULL(0xc00000000000000) + +#define KVX_SFR_ITOW_IT14_MASK _ULL(0x30000000) /* Interrupt 14 owner */ +#define KVX_SFR_ITOW_IT14_SHIFT 28 +#define KVX_SFR_ITOW_IT14_WIDTH 2 +#define KVX_SFR_ITOW_IT14_WFXL_MASK _ULL(0x30000000) +#define KVX_SFR_ITOW_IT14_WFXL_CLEAR _ULL(0x30000000) +#define KVX_SFR_ITOW_IT14_WFXL_SET _ULL(0x3000000000000000) + +#define KVX_SFR_ITOW_IT15_MASK _ULL(0xc0000000) /* Interrupt 15 owner */ +#define KVX_SFR_ITOW_IT15_SHIFT 30 +#define KVX_SFR_ITOW_IT15_WIDTH 2 +#define KVX_SFR_ITOW_IT15_WFXL_MASK _ULL(0xc0000000) +#define KVX_SFR_ITOW_IT15_WFXL_CLEAR _ULL(0xc0000000) +#define KVX_SFR_ITOW_IT15_WFXL_SET _ULL(0xc000000000000000) + +#define KVX_SFR_ITOW_IT16_MASK _ULL(0x300000000) /* Interrupt 16 owner */ +#define KVX_SFR_ITOW_IT16_SHIFT 32 +#define KVX_SFR_ITOW_IT16_WIDTH 2 +#define KVX_SFR_ITOW_IT16_WFXM_MASK _ULL(0x300000000) +#define KVX_SFR_ITOW_IT16_WFXM_CLEAR _ULL(0x3) +#define KVX_SFR_ITOW_IT16_WFXM_SET _ULL(0x300000000) + +#define KVX_SFR_ITOW_IT17_MASK _ULL(0xc00000000) /* Interrupt 17 owner */ +#define KVX_SFR_ITOW_IT17_SHIFT 34 +#define KVX_SFR_ITOW_IT17_WIDTH 2 +#define KVX_SFR_ITOW_IT17_WFXM_MASK _ULL(0xc00000000) +#define KVX_SFR_ITOW_IT17_WFXM_CLEAR _ULL(0xc) +#define KVX_SFR_ITOW_IT17_WFXM_SET _ULL(0xc00000000) + +#define KVX_SFR_ITOW_IT18_MASK _ULL(0x3000000000) /* Interrupt 18 owner */ +#define KVX_SFR_ITOW_IT18_SHIFT 36 +#define KVX_SFR_ITOW_IT18_WIDTH 2 +#define KVX_SFR_ITOW_IT18_WFXM_MASK _ULL(0x3000000000) +#define KVX_SFR_ITOW_IT18_WFXM_CLEAR _ULL(0x30) +#define KVX_SFR_ITOW_IT18_WFXM_SET _ULL(0x3000000000) + +#define KVX_SFR_ITOW_IT19_MASK _ULL(0xc000000000) /* Interrupt 19 owner */ +#define KVX_SFR_ITOW_IT19_SHIFT 38 +#define KVX_SFR_ITOW_IT19_WIDTH 2 +#define KVX_SFR_ITOW_IT19_WFXM_MASK _ULL(0xc000000000) +#define KVX_SFR_ITOW_IT19_WFXM_CLEAR _ULL(0xc0) +#define KVX_SFR_ITOW_IT19_WFXM_SET _ULL(0xc000000000) + +#define KVX_SFR_ITOW_IT20_MASK _ULL(0x30000000000) /* Interrupt 20 owner */ +#define KVX_SFR_ITOW_IT20_SHIFT 40 +#define KVX_SFR_ITOW_IT20_WIDTH 2 +#define KVX_SFR_ITOW_IT20_WFXM_MASK _ULL(0x30000000000) +#define KVX_SFR_ITOW_IT20_WFXM_CLEAR _ULL(0x300) +#define KVX_SFR_ITOW_IT20_WFXM_SET _ULL(0x30000000000) + +#define KVX_SFR_ITOW_IT21_MASK _ULL(0xc0000000000) /* Interrupt 21 owner */ +#define KVX_SFR_ITOW_IT21_SHIFT 42 +#define KVX_SFR_ITOW_IT21_WIDTH 2 +#define KVX_SFR_ITOW_IT21_WFXM_MASK _ULL(0xc0000000000) +#define KVX_SFR_ITOW_IT21_WFXM_CLEAR _ULL(0xc00) +#define KVX_SFR_ITOW_IT21_WFXM_SET _ULL(0xc0000000000) + +#define KVX_SFR_ITOW_IT22_MASK _ULL(0x300000000000) /* Interrupt 22 owner */ +#define KVX_SFR_ITOW_IT22_SHIFT 44 +#define KVX_SFR_ITOW_IT22_WIDTH 2 +#define KVX_SFR_ITOW_IT22_WFXM_MASK _ULL(0x300000000000) +#define KVX_SFR_ITOW_IT22_WFXM_CLEAR _ULL(0x3000) +#define KVX_SFR_ITOW_IT22_WFXM_SET _ULL(0x300000000000) + +#define KVX_SFR_ITOW_IT23_MASK _ULL(0xc00000000000) /* Interrupt 23 owner */ +#define KVX_SFR_ITOW_IT23_SHIFT 46 +#define KVX_SFR_ITOW_IT23_WIDTH 2 +#define KVX_SFR_ITOW_IT23_WFXM_MASK _ULL(0xc00000000000) +#define KVX_SFR_ITOW_IT23_WFXM_CLEAR _ULL(0xc000) +#define KVX_SFR_ITOW_IT23_WFXM_SET _ULL(0xc00000000000) + +#define KVX_SFR_ITOW_IT24_MASK _ULL(0x3000000000000) /* Interrupt 24 owner */ +#define KVX_SFR_ITOW_IT24_SHIFT 48 +#define KVX_SFR_ITOW_IT24_WIDTH 2 +#define KVX_SFR_ITOW_IT24_WFXM_MASK _ULL(0x3000000000000) +#define KVX_SFR_ITOW_IT24_WFXM_CLEAR _ULL(0x30000) +#define KVX_SFR_ITOW_IT24_WFXM_SET _ULL(0x3000000000000) + +#define KVX_SFR_ITOW_IT25_MASK _ULL(0xc000000000000) /* Interrupt 25 owner */ +#define KVX_SFR_ITOW_IT25_SHIFT 50 +#define KVX_SFR_ITOW_IT25_WIDTH 2 +#define KVX_SFR_ITOW_IT25_WFXM_MASK _ULL(0xc000000000000) +#define KVX_SFR_ITOW_IT25_WFXM_CLEAR _ULL(0xc0000) +#define KVX_SFR_ITOW_IT25_WFXM_SET _ULL(0xc000000000000) + +#define KVX_SFR_ITOW_IT26_MASK _ULL(0x30000000000000) /* Interrupt 26 owner */ +#define KVX_SFR_ITOW_IT26_SHIFT 52 +#define KVX_SFR_ITOW_IT26_WIDTH 2 +#define KVX_SFR_ITOW_IT26_WFXM_MASK _ULL(0x30000000000000) +#define KVX_SFR_ITOW_IT26_WFXM_CLEAR _ULL(0x300000) +#define KVX_SFR_ITOW_IT26_WFXM_SET _ULL(0x30000000000000) + +#define KVX_SFR_ITOW_IT27_MASK _ULL(0xc0000000000000) /* Interrupt 27 owner */ +#define KVX_SFR_ITOW_IT27_SHIFT 54 +#define KVX_SFR_ITOW_IT27_WIDTH 2 +#define KVX_SFR_ITOW_IT27_WFXM_MASK _ULL(0xc0000000000000) +#define KVX_SFR_ITOW_IT27_WFXM_CLEAR _ULL(0xc00000) +#define KVX_SFR_ITOW_IT27_WFXM_SET _ULL(0xc0000000000000) + +#define KVX_SFR_ITOW_IT28_MASK _ULL(0x300000000000000) /* Interrupt 28 owner */ +#define KVX_SFR_ITOW_IT28_SHIFT 56 +#define KVX_SFR_ITOW_IT28_WIDTH 2 +#define KVX_SFR_ITOW_IT28_WFXM_MASK _ULL(0x300000000000000) +#define KVX_SFR_ITOW_IT28_WFXM_CLEAR _ULL(0x3000000) +#define KVX_SFR_ITOW_IT28_WFXM_SET _ULL(0x300000000000000) + +#define KVX_SFR_ITOW_IT29_MASK _ULL(0xc00000000000000) /* Interrupt 29 owner */ +#define KVX_SFR_ITOW_IT29_SHIFT 58 +#define KVX_SFR_ITOW_IT29_WIDTH 2 +#define KVX_SFR_ITOW_IT29_WFXM_MASK _ULL(0xc00000000000000) +#define KVX_SFR_ITOW_IT29_WFXM_CLEAR _ULL(0xc000000) +#define KVX_SFR_ITOW_IT29_WFXM_SET _ULL(0xc00000000000000) + +#define KVX_SFR_ITOW_IT30_MASK _ULL(0x3000000000000000) /* Interrupt 30 owner */ +#define KVX_SFR_ITOW_IT30_SHIFT 60 +#define KVX_SFR_ITOW_IT30_WIDTH 2 +#define KVX_SFR_ITOW_IT30_WFXM_MASK _ULL(0x3000000000000000) +#define KVX_SFR_ITOW_IT30_WFXM_CLEAR _ULL(0x30000000) +#define KVX_SFR_ITOW_IT30_WFXM_SET _ULL(0x3000000000000000) + +#define KVX_SFR_ITOW_IT31_MASK _ULL(0xc000000000000000) /* Interrupt 31 owner */ +#define KVX_SFR_ITOW_IT31_SHIFT 62 +#define KVX_SFR_ITOW_IT31_WIDTH 2 +#define KVX_SFR_ITOW_IT31_WFXM_MASK _ULL(0xc000000000000000) +#define KVX_SFR_ITOW_IT31_WFXM_CLEAR _ULL(0xc0000000) +#define KVX_SFR_ITOW_IT31_WFXM_SET _ULL(0xc000000000000000) + +#define KVX_SFR_DO_B0_MASK _ULL(0x3) /* Breakpoint 0 owner. */ +#define KVX_SFR_DO_B0_SHIFT 0 +#define KVX_SFR_DO_B0_WIDTH 2 +#define KVX_SFR_DO_B0_WFXL_MASK _ULL(0x3) +#define KVX_SFR_DO_B0_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_DO_B0_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_DO_B1_MASK _ULL(0xc) /* Breakpoint 1 owner. */ +#define KVX_SFR_DO_B1_SHIFT 2 +#define KVX_SFR_DO_B1_WIDTH 2 +#define KVX_SFR_DO_B1_WFXL_MASK _ULL(0xc) +#define KVX_SFR_DO_B1_WFXL_CLEAR _ULL(0xc) +#define KVX_SFR_DO_B1_WFXL_SET _ULL(0xc00000000) + +#define KVX_SFR_DO_W0_MASK _ULL(0x30) /* Watchpoint 0 owner. */ +#define KVX_SFR_DO_W0_SHIFT 4 +#define KVX_SFR_DO_W0_WIDTH 2 +#define KVX_SFR_DO_W0_WFXL_MASK _ULL(0x30) +#define KVX_SFR_DO_W0_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_DO_W0_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_DO_W1_MASK _ULL(0xc0) /* Watchpoint 1 owner. */ +#define KVX_SFR_DO_W1_SHIFT 6 +#define KVX_SFR_DO_W1_WIDTH 2 +#define KVX_SFR_DO_W1_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_DO_W1_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_DO_W1_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_DBA0_DBA0_MASK _ULL(0xffffffffffffffff) /* Debug Breakpoint Address 0 */ +#define KVX_SFR_DBA0_DBA0_SHIFT 0 +#define KVX_SFR_DBA0_DBA0_WIDTH 64 +#define KVX_SFR_DBA0_DBA0_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_DBA0_DBA0_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_DBA0_DBA0_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_DBA0_DBA0_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_DBA0_DBA0_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_DBA0_DBA0_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_DBA1_DBA1_MASK _ULL(0xffffffffffffffff) /* Debug Breakpoint Address 1 */ +#define KVX_SFR_DBA1_DBA1_SHIFT 0 +#define KVX_SFR_DBA1_DBA1_WIDTH 64 +#define KVX_SFR_DBA1_DBA1_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_DBA1_DBA1_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_DBA1_DBA1_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_DBA1_DBA1_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_DBA1_DBA1_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_DBA1_DBA1_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_DWA0_DWA0_MASK _ULL(0xffffffffffffffff) /* Debug Breakpoint Address 0 */ +#define KVX_SFR_DWA0_DWA0_SHIFT 0 +#define KVX_SFR_DWA0_DWA0_WIDTH 64 +#define KVX_SFR_DWA0_DWA0_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_DWA0_DWA0_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_DWA0_DWA0_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_DWA0_DWA0_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_DWA0_DWA0_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_DWA0_DWA0_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_DWA1_DWA1_MASK _ULL(0xffffffffffffffff) /* Debug Breakpoint Address 1 */ +#define KVX_SFR_DWA1_DWA1_SHIFT 0 +#define KVX_SFR_DWA1_DWA1_WIDTH 64 +#define KVX_SFR_DWA1_DWA1_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_DWA1_DWA1_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_DWA1_DWA1_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_DWA1_DWA1_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_DWA1_DWA1_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_DWA1_DWA1_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_DOW_B0_MASK _ULL(0x3) /* Breakpoint 0 owner. */ +#define KVX_SFR_DOW_B0_SHIFT 0 +#define KVX_SFR_DOW_B0_WIDTH 2 +#define KVX_SFR_DOW_B0_WFXL_MASK _ULL(0x3) +#define KVX_SFR_DOW_B0_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_DOW_B0_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_DOW_B1_MASK _ULL(0xc) /* Breakpoint 1 owner. */ +#define KVX_SFR_DOW_B1_SHIFT 2 +#define KVX_SFR_DOW_B1_WIDTH 2 +#define KVX_SFR_DOW_B1_WFXL_MASK _ULL(0xc) +#define KVX_SFR_DOW_B1_WFXL_CLEAR _ULL(0xc) +#define KVX_SFR_DOW_B1_WFXL_SET _ULL(0xc00000000) + +#define KVX_SFR_DOW_W0_MASK _ULL(0x30) /* Watchpoint 0 owner. */ +#define KVX_SFR_DOW_W0_SHIFT 4 +#define KVX_SFR_DOW_W0_WIDTH 2 +#define KVX_SFR_DOW_W0_WFXL_MASK _ULL(0x30) +#define KVX_SFR_DOW_W0_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_DOW_W0_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_DOW_W1_MASK _ULL(0xc0) /* Watchpoint 1 owner. */ +#define KVX_SFR_DOW_W1_SHIFT 6 +#define KVX_SFR_DOW_W1_WIDTH 2 +#define KVX_SFR_DOW_W1_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_DOW_W1_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_DOW_W1_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_MO_MMI_MASK _ULL(0x3) /* Memory Management Instructions owner. */ +#define KVX_SFR_MO_MMI_SHIFT 0 +#define KVX_SFR_MO_MMI_WIDTH 2 +#define KVX_SFR_MO_MMI_WFXL_MASK _ULL(0x3) +#define KVX_SFR_MO_MMI_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_MO_MMI_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_MO_RFE_MASK _ULL(0xc) /* RFE instruction owner. */ +#define KVX_SFR_MO_RFE_SHIFT 2 +#define KVX_SFR_MO_RFE_WIDTH 2 +#define KVX_SFR_MO_RFE_WFXL_MASK _ULL(0xc) +#define KVX_SFR_MO_RFE_WFXL_CLEAR _ULL(0xc) +#define KVX_SFR_MO_RFE_WFXL_SET _ULL(0xc00000000) + +#define KVX_SFR_MO_STOP_MASK _ULL(0x30) /* STOP instruction owner. */ +#define KVX_SFR_MO_STOP_SHIFT 4 +#define KVX_SFR_MO_STOP_WIDTH 2 +#define KVX_SFR_MO_STOP_WFXL_MASK _ULL(0x30) +#define KVX_SFR_MO_STOP_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_MO_STOP_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_MO_SYNC_MASK _ULL(0xc0) /* SYNCGROUP instruction owner. */ +#define KVX_SFR_MO_SYNC_SHIFT 6 +#define KVX_SFR_MO_SYNC_WIDTH 2 +#define KVX_SFR_MO_SYNC_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_MO_SYNC_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_MO_SYNC_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_MO_PCR_MASK _ULL(0x300) /* PCR register owner. */ +#define KVX_SFR_MO_PCR_SHIFT 8 +#define KVX_SFR_MO_PCR_WIDTH 2 +#define KVX_SFR_MO_PCR_WFXL_MASK _ULL(0x300) +#define KVX_SFR_MO_PCR_WFXL_CLEAR _ULL(0x300) +#define KVX_SFR_MO_PCR_WFXL_SET _ULL(0x30000000000) + +#define KVX_SFR_MO_MSG_MASK _ULL(0xc00) /* MMU SFR GROUP registers owner. */ +#define KVX_SFR_MO_MSG_SHIFT 10 +#define KVX_SFR_MO_MSG_WIDTH 2 +#define KVX_SFR_MO_MSG_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_MO_MSG_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_MO_MSG_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_MO_MEN_MASK _ULL(0x3000) /* Miscellaneous External Notifications register owner. */ +#define KVX_SFR_MO_MEN_SHIFT 12 +#define KVX_SFR_MO_MEN_WIDTH 2 +#define KVX_SFR_MO_MEN_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_MO_MEN_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_MO_MEN_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_MO_MES_MASK _ULL(0xc000) /* Memory Error Status register owner. */ +#define KVX_SFR_MO_MES_SHIFT 14 +#define KVX_SFR_MO_MES_WIDTH 2 +#define KVX_SFR_MO_MES_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_MO_MES_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_MO_MES_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_MO_CSIT_MASK _ULL(0x30000) /* Compute Status Artithmetic Interrupt register owner. */ +#define KVX_SFR_MO_CSIT_SHIFT 16 +#define KVX_SFR_MO_CSIT_WIDTH 2 +#define KVX_SFR_MO_CSIT_WFXL_MASK _ULL(0x30000) +#define KVX_SFR_MO_CSIT_WFXL_CLEAR _ULL(0x30000) +#define KVX_SFR_MO_CSIT_WFXL_SET _ULL(0x3000000000000) + +#define KVX_SFR_MO_T0_MASK _ULL(0xc0000) /* Timer 0 register group owner */ +#define KVX_SFR_MO_T0_SHIFT 18 +#define KVX_SFR_MO_T0_WIDTH 2 +#define KVX_SFR_MO_T0_WFXL_MASK _ULL(0xc0000) +#define KVX_SFR_MO_T0_WFXL_CLEAR _ULL(0xc0000) +#define KVX_SFR_MO_T0_WFXL_SET _ULL(0xc000000000000) + +#define KVX_SFR_MO_T1_MASK _ULL(0x300000) /* Timer 1 register group owner */ +#define KVX_SFR_MO_T1_SHIFT 20 +#define KVX_SFR_MO_T1_WIDTH 2 +#define KVX_SFR_MO_T1_WFXL_MASK _ULL(0x300000) +#define KVX_SFR_MO_T1_WFXL_CLEAR _ULL(0x300000) +#define KVX_SFR_MO_T1_WFXL_SET _ULL(0x30000000000000) + +#define KVX_SFR_MO_WD_MASK _ULL(0xc00000) /* Watch Dog register group owner. */ +#define KVX_SFR_MO_WD_SHIFT 22 +#define KVX_SFR_MO_WD_WIDTH 2 +#define KVX_SFR_MO_WD_WFXL_MASK _ULL(0xc00000) +#define KVX_SFR_MO_WD_WFXL_CLEAR _ULL(0xc00000) +#define KVX_SFR_MO_WD_WFXL_SET _ULL(0xc0000000000000) + +#define KVX_SFR_MO_PM0_MASK _ULL(0x3000000) /* Performance Monitor 0 register owner. */ +#define KVX_SFR_MO_PM0_SHIFT 24 +#define KVX_SFR_MO_PM0_WIDTH 2 +#define KVX_SFR_MO_PM0_WFXL_MASK _ULL(0x3000000) +#define KVX_SFR_MO_PM0_WFXL_CLEAR _ULL(0x3000000) +#define KVX_SFR_MO_PM0_WFXL_SET _ULL(0x300000000000000) + +#define KVX_SFR_MO_PM1_MASK _ULL(0xc000000) /* Performance Monitor 1 register owner. */ +#define KVX_SFR_MO_PM1_SHIFT 26 +#define KVX_SFR_MO_PM1_WIDTH 2 +#define KVX_SFR_MO_PM1_WFXL_MASK _ULL(0xc000000) +#define KVX_SFR_MO_PM1_WFXL_CLEAR _ULL(0xc000000) +#define KVX_SFR_MO_PM1_WFXL_SET _ULL(0xc00000000000000) + +#define KVX_SFR_MO_PM2_MASK _ULL(0x30000000) /* Performance Monitor 2 register owner. */ +#define KVX_SFR_MO_PM2_SHIFT 28 +#define KVX_SFR_MO_PM2_WIDTH 2 +#define KVX_SFR_MO_PM2_WFXL_MASK _ULL(0x30000000) +#define KVX_SFR_MO_PM2_WFXL_CLEAR _ULL(0x30000000) +#define KVX_SFR_MO_PM2_WFXL_SET _ULL(0x3000000000000000) + +#define KVX_SFR_MO_PM3_MASK _ULL(0xc0000000) /* Performance Monitor 3 register owner. */ +#define KVX_SFR_MO_PM3_SHIFT 30 +#define KVX_SFR_MO_PM3_WIDTH 2 +#define KVX_SFR_MO_PM3_WFXL_MASK _ULL(0xc0000000) +#define KVX_SFR_MO_PM3_WFXL_CLEAR _ULL(0xc0000000) +#define KVX_SFR_MO_PM3_WFXL_SET _ULL(0xc000000000000000) + +#define KVX_SFR_MO_PMIT_MASK _ULL(0x300000000) /* Performance Monitor Interrupt register group owner. */ +#define KVX_SFR_MO_PMIT_SHIFT 32 +#define KVX_SFR_MO_PMIT_WIDTH 2 +#define KVX_SFR_MO_PMIT_WFXM_MASK _ULL(0x300000000) +#define KVX_SFR_MO_PMIT_WFXM_CLEAR _ULL(0x3) +#define KVX_SFR_MO_PMIT_WFXM_SET _ULL(0x300000000) + +#define KVX_SFR_MOW_MMI_MASK _ULL(0x3) /* Memory Management Instructions owner. */ +#define KVX_SFR_MOW_MMI_SHIFT 0 +#define KVX_SFR_MOW_MMI_WIDTH 2 +#define KVX_SFR_MOW_MMI_WFXL_MASK _ULL(0x3) +#define KVX_SFR_MOW_MMI_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_MOW_MMI_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_MOW_RFE_MASK _ULL(0xc) /* RFE instruction owner. */ +#define KVX_SFR_MOW_RFE_SHIFT 2 +#define KVX_SFR_MOW_RFE_WIDTH 2 +#define KVX_SFR_MOW_RFE_WFXL_MASK _ULL(0xc) +#define KVX_SFR_MOW_RFE_WFXL_CLEAR _ULL(0xc) +#define KVX_SFR_MOW_RFE_WFXL_SET _ULL(0xc00000000) + +#define KVX_SFR_MOW_STOP_MASK _ULL(0x30) /* STOP instruction owner. */ +#define KVX_SFR_MOW_STOP_SHIFT 4 +#define KVX_SFR_MOW_STOP_WIDTH 2 +#define KVX_SFR_MOW_STOP_WFXL_MASK _ULL(0x30) +#define KVX_SFR_MOW_STOP_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_MOW_STOP_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_MOW_SYNC_MASK _ULL(0xc0) /* SYNCGROUP instruction owner. */ +#define KVX_SFR_MOW_SYNC_SHIFT 6 +#define KVX_SFR_MOW_SYNC_WIDTH 2 +#define KVX_SFR_MOW_SYNC_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_MOW_SYNC_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_MOW_SYNC_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_MOW_PCR_MASK _ULL(0x300) /* PCR register owner. */ +#define KVX_SFR_MOW_PCR_SHIFT 8 +#define KVX_SFR_MOW_PCR_WIDTH 2 +#define KVX_SFR_MOW_PCR_WFXL_MASK _ULL(0x300) +#define KVX_SFR_MOW_PCR_WFXL_CLEAR _ULL(0x300) +#define KVX_SFR_MOW_PCR_WFXL_SET _ULL(0x30000000000) + +#define KVX_SFR_MOW_MSG_MASK _ULL(0xc00) /* MMU SFR GROUP registers owner. */ +#define KVX_SFR_MOW_MSG_SHIFT 10 +#define KVX_SFR_MOW_MSG_WIDTH 2 +#define KVX_SFR_MOW_MSG_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_MOW_MSG_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_MOW_MSG_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_MOW_MEN_MASK _ULL(0x3000) /* Miscellaneous External Notifications register owner. */ +#define KVX_SFR_MOW_MEN_SHIFT 12 +#define KVX_SFR_MOW_MEN_WIDTH 2 +#define KVX_SFR_MOW_MEN_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_MOW_MEN_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_MOW_MEN_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_MOW_MES_MASK _ULL(0xc000) /* Memory Error Status register owner. */ +#define KVX_SFR_MOW_MES_SHIFT 14 +#define KVX_SFR_MOW_MES_WIDTH 2 +#define KVX_SFR_MOW_MES_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_MOW_MES_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_MOW_MES_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_MOW_CSIT_MASK _ULL(0x30000) /* Compute Status Artithmetic Interrupt register owner. */ +#define KVX_SFR_MOW_CSIT_SHIFT 16 +#define KVX_SFR_MOW_CSIT_WIDTH 2 +#define KVX_SFR_MOW_CSIT_WFXL_MASK _ULL(0x30000) +#define KVX_SFR_MOW_CSIT_WFXL_CLEAR _ULL(0x30000) +#define KVX_SFR_MOW_CSIT_WFXL_SET _ULL(0x3000000000000) + +#define KVX_SFR_MOW_T0_MASK _ULL(0xc0000) /* Timer 0 register group owner */ +#define KVX_SFR_MOW_T0_SHIFT 18 +#define KVX_SFR_MOW_T0_WIDTH 2 +#define KVX_SFR_MOW_T0_WFXL_MASK _ULL(0xc0000) +#define KVX_SFR_MOW_T0_WFXL_CLEAR _ULL(0xc0000) +#define KVX_SFR_MOW_T0_WFXL_SET _ULL(0xc000000000000) + +#define KVX_SFR_MOW_T1_MASK _ULL(0x300000) /* Timer 1 register group owner */ +#define KVX_SFR_MOW_T1_SHIFT 20 +#define KVX_SFR_MOW_T1_WIDTH 2 +#define KVX_SFR_MOW_T1_WFXL_MASK _ULL(0x300000) +#define KVX_SFR_MOW_T1_WFXL_CLEAR _ULL(0x300000) +#define KVX_SFR_MOW_T1_WFXL_SET _ULL(0x30000000000000) + +#define KVX_SFR_MOW_WD_MASK _ULL(0xc00000) /* Watch Dog register group owner. */ +#define KVX_SFR_MOW_WD_SHIFT 22 +#define KVX_SFR_MOW_WD_WIDTH 2 +#define KVX_SFR_MOW_WD_WFXL_MASK _ULL(0xc00000) +#define KVX_SFR_MOW_WD_WFXL_CLEAR _ULL(0xc00000) +#define KVX_SFR_MOW_WD_WFXL_SET _ULL(0xc0000000000000) + +#define KVX_SFR_MOW_PM0_MASK _ULL(0x3000000) /* Performance Monitor 0 register owner. */ +#define KVX_SFR_MOW_PM0_SHIFT 24 +#define KVX_SFR_MOW_PM0_WIDTH 2 +#define KVX_SFR_MOW_PM0_WFXL_MASK _ULL(0x3000000) +#define KVX_SFR_MOW_PM0_WFXL_CLEAR _ULL(0x3000000) +#define KVX_SFR_MOW_PM0_WFXL_SET _ULL(0x300000000000000) + +#define KVX_SFR_MOW_PM1_MASK _ULL(0xc000000) /* Performance Monitor 1 register owner. */ +#define KVX_SFR_MOW_PM1_SHIFT 26 +#define KVX_SFR_MOW_PM1_WIDTH 2 +#define KVX_SFR_MOW_PM1_WFXL_MASK _ULL(0xc000000) +#define KVX_SFR_MOW_PM1_WFXL_CLEAR _ULL(0xc000000) +#define KVX_SFR_MOW_PM1_WFXL_SET _ULL(0xc00000000000000) + +#define KVX_SFR_MOW_PM2_MASK _ULL(0x30000000) /* Performance Monitor 2 register owner. */ +#define KVX_SFR_MOW_PM2_SHIFT 28 +#define KVX_SFR_MOW_PM2_WIDTH 2 +#define KVX_SFR_MOW_PM2_WFXL_MASK _ULL(0x30000000) +#define KVX_SFR_MOW_PM2_WFXL_CLEAR _ULL(0x30000000) +#define KVX_SFR_MOW_PM2_WFXL_SET _ULL(0x3000000000000000) + +#define KVX_SFR_MOW_PM3_MASK _ULL(0xc0000000) /* Performance Monitor 3 register owner. */ +#define KVX_SFR_MOW_PM3_SHIFT 30 +#define KVX_SFR_MOW_PM3_WIDTH 2 +#define KVX_SFR_MOW_PM3_WFXL_MASK _ULL(0xc0000000) +#define KVX_SFR_MOW_PM3_WFXL_CLEAR _ULL(0xc0000000) +#define KVX_SFR_MOW_PM3_WFXL_SET _ULL(0xc000000000000000) + +#define KVX_SFR_MOW_PMIT_MASK _ULL(0x300000000) /* Performance Monitor Interrupt register group owner. */ +#define KVX_SFR_MOW_PMIT_SHIFT 32 +#define KVX_SFR_MOW_PMIT_WIDTH 2 +#define KVX_SFR_MOW_PMIT_WFXM_MASK _ULL(0x300000000) +#define KVX_SFR_MOW_PMIT_WFXM_CLEAR _ULL(0x3) +#define KVX_SFR_MOW_PMIT_WFXM_SET _ULL(0x300000000) + +#define KVX_SFR_PS_PL_MASK _ULL(0x3) /* Current Privilege Level */ +#define KVX_SFR_PS_PL_SHIFT 0 +#define KVX_SFR_PS_PL_WIDTH 2 +#define KVX_SFR_PS_PL_WFXL_MASK _ULL(0x3) +#define KVX_SFR_PS_PL_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_PS_PL_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_PS_ET_MASK _ULL(0x4) /* Exception Taken */ +#define KVX_SFR_PS_ET_SHIFT 2 +#define KVX_SFR_PS_ET_WIDTH 1 +#define KVX_SFR_PS_ET_WFXL_MASK _ULL(0x4) +#define KVX_SFR_PS_ET_WFXL_CLEAR _ULL(0x4) +#define KVX_SFR_PS_ET_WFXL_SET _ULL(0x400000000) + +#define KVX_SFR_PS_HTD_MASK _ULL(0x8) /* Hardware Trap Disable */ +#define KVX_SFR_PS_HTD_SHIFT 3 +#define KVX_SFR_PS_HTD_WIDTH 1 +#define KVX_SFR_PS_HTD_WFXL_MASK _ULL(0x8) +#define KVX_SFR_PS_HTD_WFXL_CLEAR _ULL(0x8) +#define KVX_SFR_PS_HTD_WFXL_SET _ULL(0x800000000) + +#define KVX_SFR_PS_IE_MASK _ULL(0x10) /* Interrupt Enable */ +#define KVX_SFR_PS_IE_SHIFT 4 +#define KVX_SFR_PS_IE_WIDTH 1 +#define KVX_SFR_PS_IE_WFXL_MASK _ULL(0x10) +#define KVX_SFR_PS_IE_WFXL_CLEAR _ULL(0x10) +#define KVX_SFR_PS_IE_WFXL_SET _ULL(0x1000000000) + +#define KVX_SFR_PS_HLE_MASK _ULL(0x20) /* Hardware Loop Enable */ +#define KVX_SFR_PS_HLE_SHIFT 5 +#define KVX_SFR_PS_HLE_WIDTH 1 +#define KVX_SFR_PS_HLE_WFXL_MASK _ULL(0x20) +#define KVX_SFR_PS_HLE_WFXL_CLEAR _ULL(0x20) +#define KVX_SFR_PS_HLE_WFXL_SET _ULL(0x2000000000) + +#define KVX_SFR_PS_SRE_MASK _ULL(0x40) /* Software REserved */ +#define KVX_SFR_PS_SRE_SHIFT 6 +#define KVX_SFR_PS_SRE_WIDTH 1 +#define KVX_SFR_PS_SRE_WFXL_MASK _ULL(0x40) +#define KVX_SFR_PS_SRE_WFXL_CLEAR _ULL(0x40) +#define KVX_SFR_PS_SRE_WFXL_SET _ULL(0x4000000000) + +#define KVX_SFR_PS_DAUS_MASK _ULL(0x80) /* Data Accesses Use SPS settings */ +#define KVX_SFR_PS_DAUS_SHIFT 7 +#define KVX_SFR_PS_DAUS_WIDTH 1 +#define KVX_SFR_PS_DAUS_WFXL_MASK _ULL(0x80) +#define KVX_SFR_PS_DAUS_WFXL_CLEAR _ULL(0x80) +#define KVX_SFR_PS_DAUS_WFXL_SET _ULL(0x8000000000) + +#define KVX_SFR_PS_ICE_MASK _ULL(0x100) /* Instruction Cache Enable */ +#define KVX_SFR_PS_ICE_SHIFT 8 +#define KVX_SFR_PS_ICE_WIDTH 1 +#define KVX_SFR_PS_ICE_WFXL_MASK _ULL(0x100) +#define KVX_SFR_PS_ICE_WFXL_CLEAR _ULL(0x100) +#define KVX_SFR_PS_ICE_WFXL_SET _ULL(0x10000000000) + +#define KVX_SFR_PS_USE_MASK _ULL(0x200) /* Uncached Streaming Enable */ +#define KVX_SFR_PS_USE_SHIFT 9 +#define KVX_SFR_PS_USE_WIDTH 1 +#define KVX_SFR_PS_USE_WFXL_MASK _ULL(0x200) +#define KVX_SFR_PS_USE_WFXL_CLEAR _ULL(0x200) +#define KVX_SFR_PS_USE_WFXL_SET _ULL(0x20000000000) + +#define KVX_SFR_PS_DCE_MASK _ULL(0x400) /* Data Cache Enable */ +#define KVX_SFR_PS_DCE_SHIFT 10 +#define KVX_SFR_PS_DCE_WIDTH 1 +#define KVX_SFR_PS_DCE_WFXL_MASK _ULL(0x400) +#define KVX_SFR_PS_DCE_WFXL_CLEAR _ULL(0x400) +#define KVX_SFR_PS_DCE_WFXL_SET _ULL(0x40000000000) + +#define KVX_SFR_PS_MME_MASK _ULL(0x800) /* Memory Management Enable */ +#define KVX_SFR_PS_MME_SHIFT 11 +#define KVX_SFR_PS_MME_WIDTH 1 +#define KVX_SFR_PS_MME_WFXL_MASK _ULL(0x800) +#define KVX_SFR_PS_MME_WFXL_CLEAR _ULL(0x800) +#define KVX_SFR_PS_MME_WFXL_SET _ULL(0x80000000000) + +#define KVX_SFR_PS_IL_MASK _ULL(0x3000) /* Interrupt Level */ +#define KVX_SFR_PS_IL_SHIFT 12 +#define KVX_SFR_PS_IL_WIDTH 2 +#define KVX_SFR_PS_IL_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_PS_IL_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_PS_IL_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_PS_VS_MASK _ULL(0xc000) /* Virtual Space */ +#define KVX_SFR_PS_VS_SHIFT 14 +#define KVX_SFR_PS_VS_WIDTH 2 +#define KVX_SFR_PS_VS_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_PS_VS_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_PS_VS_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_PS_V64_MASK _ULL(0x10000) /* Virtual 64 bits mode. */ +#define KVX_SFR_PS_V64_SHIFT 16 +#define KVX_SFR_PS_V64_WIDTH 1 +#define KVX_SFR_PS_V64_WFXL_MASK _ULL(0x10000) +#define KVX_SFR_PS_V64_WFXL_CLEAR _ULL(0x10000) +#define KVX_SFR_PS_V64_WFXL_SET _ULL(0x1000000000000) + +#define KVX_SFR_PS_L2E_MASK _ULL(0x20000) /* L2 cache Enable. */ +#define KVX_SFR_PS_L2E_SHIFT 17 +#define KVX_SFR_PS_L2E_WIDTH 1 +#define KVX_SFR_PS_L2E_WFXL_MASK _ULL(0x20000) +#define KVX_SFR_PS_L2E_WFXL_CLEAR _ULL(0x20000) +#define KVX_SFR_PS_L2E_WFXL_SET _ULL(0x2000000000000) + +#define KVX_SFR_PS_SME_MASK _ULL(0x40000) /* Step Mode Enabled */ +#define KVX_SFR_PS_SME_SHIFT 18 +#define KVX_SFR_PS_SME_WIDTH 1 +#define KVX_SFR_PS_SME_WFXL_MASK _ULL(0x40000) +#define KVX_SFR_PS_SME_WFXL_CLEAR _ULL(0x40000) +#define KVX_SFR_PS_SME_WFXL_SET _ULL(0x4000000000000) + +#define KVX_SFR_PS_SMR_MASK _ULL(0x80000) /* Step Mode Ready */ +#define KVX_SFR_PS_SMR_SHIFT 19 +#define KVX_SFR_PS_SMR_WIDTH 1 +#define KVX_SFR_PS_SMR_WFXL_MASK _ULL(0x80000) +#define KVX_SFR_PS_SMR_WFXL_CLEAR _ULL(0x80000) +#define KVX_SFR_PS_SMR_WFXL_SET _ULL(0x8000000000000) + +#define KVX_SFR_PS_PMJ_MASK _ULL(0xf00000) /* Page Mask in JTLB. */ +#define KVX_SFR_PS_PMJ_SHIFT 20 +#define KVX_SFR_PS_PMJ_WIDTH 4 +#define KVX_SFR_PS_PMJ_WFXL_MASK _ULL(0xf00000) +#define KVX_SFR_PS_PMJ_WFXL_CLEAR _ULL(0xf00000) +#define KVX_SFR_PS_PMJ_WFXL_SET _ULL(0xf0000000000000) + +#define KVX_SFR_PS_MMUP_MASK _ULL(0x1000000) /* Privileged on MMU. */ +#define KVX_SFR_PS_MMUP_SHIFT 24 +#define KVX_SFR_PS_MMUP_WIDTH 1 +#define KVX_SFR_PS_MMUP_WFXL_MASK _ULL(0x1000000) +#define KVX_SFR_PS_MMUP_WFXL_CLEAR _ULL(0x1000000) +#define KVX_SFR_PS_MMUP_WFXL_SET _ULL(0x100000000000000) + +#define KVX_SFR_SPS_PL_MASK _ULL(0x3) /* Current Privilege Level */ +#define KVX_SFR_SPS_PL_SHIFT 0 +#define KVX_SFR_SPS_PL_WIDTH 2 +#define KVX_SFR_SPS_PL_WFXL_MASK _ULL(0x3) +#define KVX_SFR_SPS_PL_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_SPS_PL_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_SPS_ET_MASK _ULL(0x4) /* Exception Taken */ +#define KVX_SFR_SPS_ET_SHIFT 2 +#define KVX_SFR_SPS_ET_WIDTH 1 +#define KVX_SFR_SPS_ET_WFXL_MASK _ULL(0x4) +#define KVX_SFR_SPS_ET_WFXL_CLEAR _ULL(0x4) +#define KVX_SFR_SPS_ET_WFXL_SET _ULL(0x400000000) + +#define KVX_SFR_SPS_HTD_MASK _ULL(0x8) /* Hardware Trap Disable */ +#define KVX_SFR_SPS_HTD_SHIFT 3 +#define KVX_SFR_SPS_HTD_WIDTH 1 +#define KVX_SFR_SPS_HTD_WFXL_MASK _ULL(0x8) +#define KVX_SFR_SPS_HTD_WFXL_CLEAR _ULL(0x8) +#define KVX_SFR_SPS_HTD_WFXL_SET _ULL(0x800000000) + +#define KVX_SFR_SPS_IE_MASK _ULL(0x10) /* Interrupt Enable */ +#define KVX_SFR_SPS_IE_SHIFT 4 +#define KVX_SFR_SPS_IE_WIDTH 1 +#define KVX_SFR_SPS_IE_WFXL_MASK _ULL(0x10) +#define KVX_SFR_SPS_IE_WFXL_CLEAR _ULL(0x10) +#define KVX_SFR_SPS_IE_WFXL_SET _ULL(0x1000000000) + +#define KVX_SFR_SPS_HLE_MASK _ULL(0x20) /* Hardware Loop Enable */ +#define KVX_SFR_SPS_HLE_SHIFT 5 +#define KVX_SFR_SPS_HLE_WIDTH 1 +#define KVX_SFR_SPS_HLE_WFXL_MASK _ULL(0x20) +#define KVX_SFR_SPS_HLE_WFXL_CLEAR _ULL(0x20) +#define KVX_SFR_SPS_HLE_WFXL_SET _ULL(0x2000000000) + +#define KVX_SFR_SPS_SRE_MASK _ULL(0x40) /* Software REserved */ +#define KVX_SFR_SPS_SRE_SHIFT 6 +#define KVX_SFR_SPS_SRE_WIDTH 1 +#define KVX_SFR_SPS_SRE_WFXL_MASK _ULL(0x40) +#define KVX_SFR_SPS_SRE_WFXL_CLEAR _ULL(0x40) +#define KVX_SFR_SPS_SRE_WFXL_SET _ULL(0x4000000000) + +#define KVX_SFR_SPS_DAUS_MASK _ULL(0x80) /* Data Accesses Use SPS settings */ +#define KVX_SFR_SPS_DAUS_SHIFT 7 +#define KVX_SFR_SPS_DAUS_WIDTH 1 +#define KVX_SFR_SPS_DAUS_WFXL_MASK _ULL(0x80) +#define KVX_SFR_SPS_DAUS_WFXL_CLEAR _ULL(0x80) +#define KVX_SFR_SPS_DAUS_WFXL_SET _ULL(0x8000000000) + +#define KVX_SFR_SPS_ICE_MASK _ULL(0x100) /* Instruction Cache Enable */ +#define KVX_SFR_SPS_ICE_SHIFT 8 +#define KVX_SFR_SPS_ICE_WIDTH 1 +#define KVX_SFR_SPS_ICE_WFXL_MASK _ULL(0x100) +#define KVX_SFR_SPS_ICE_WFXL_CLEAR _ULL(0x100) +#define KVX_SFR_SPS_ICE_WFXL_SET _ULL(0x10000000000) + +#define KVX_SFR_SPS_USE_MASK _ULL(0x200) /* Uncached Streaming Enable */ +#define KVX_SFR_SPS_USE_SHIFT 9 +#define KVX_SFR_SPS_USE_WIDTH 1 +#define KVX_SFR_SPS_USE_WFXL_MASK _ULL(0x200) +#define KVX_SFR_SPS_USE_WFXL_CLEAR _ULL(0x200) +#define KVX_SFR_SPS_USE_WFXL_SET _ULL(0x20000000000) + +#define KVX_SFR_SPS_DCE_MASK _ULL(0x400) /* Data Cache Enable */ +#define KVX_SFR_SPS_DCE_SHIFT 10 +#define KVX_SFR_SPS_DCE_WIDTH 1 +#define KVX_SFR_SPS_DCE_WFXL_MASK _ULL(0x400) +#define KVX_SFR_SPS_DCE_WFXL_CLEAR _ULL(0x400) +#define KVX_SFR_SPS_DCE_WFXL_SET _ULL(0x40000000000) + +#define KVX_SFR_SPS_MME_MASK _ULL(0x800) /* Memory Management Enable */ +#define KVX_SFR_SPS_MME_SHIFT 11 +#define KVX_SFR_SPS_MME_WIDTH 1 +#define KVX_SFR_SPS_MME_WFXL_MASK _ULL(0x800) +#define KVX_SFR_SPS_MME_WFXL_CLEAR _ULL(0x800) +#define KVX_SFR_SPS_MME_WFXL_SET _ULL(0x80000000000) + +#define KVX_SFR_SPS_IL_MASK _ULL(0x3000) /* Interrupt Level */ +#define KVX_SFR_SPS_IL_SHIFT 12 +#define KVX_SFR_SPS_IL_WIDTH 2 +#define KVX_SFR_SPS_IL_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_SPS_IL_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_SPS_IL_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_SPS_VS_MASK _ULL(0xc000) /* Virtual Space */ +#define KVX_SFR_SPS_VS_SHIFT 14 +#define KVX_SFR_SPS_VS_WIDTH 2 +#define KVX_SFR_SPS_VS_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_SPS_VS_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_SPS_VS_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_SPS_V64_MASK _ULL(0x10000) /* Virtual 64 bits mode. */ +#define KVX_SFR_SPS_V64_SHIFT 16 +#define KVX_SFR_SPS_V64_WIDTH 1 +#define KVX_SFR_SPS_V64_WFXL_MASK _ULL(0x10000) +#define KVX_SFR_SPS_V64_WFXL_CLEAR _ULL(0x10000) +#define KVX_SFR_SPS_V64_WFXL_SET _ULL(0x1000000000000) + +#define KVX_SFR_SPS_L2E_MASK _ULL(0x20000) /* L2 cache Enable. */ +#define KVX_SFR_SPS_L2E_SHIFT 17 +#define KVX_SFR_SPS_L2E_WIDTH 1 +#define KVX_SFR_SPS_L2E_WFXL_MASK _ULL(0x20000) +#define KVX_SFR_SPS_L2E_WFXL_CLEAR _ULL(0x20000) +#define KVX_SFR_SPS_L2E_WFXL_SET _ULL(0x2000000000000) + +#define KVX_SFR_SPS_SME_MASK _ULL(0x40000) /* Step Mode Enabled */ +#define KVX_SFR_SPS_SME_SHIFT 18 +#define KVX_SFR_SPS_SME_WIDTH 1 +#define KVX_SFR_SPS_SME_WFXL_MASK _ULL(0x40000) +#define KVX_SFR_SPS_SME_WFXL_CLEAR _ULL(0x40000) +#define KVX_SFR_SPS_SME_WFXL_SET _ULL(0x4000000000000) + +#define KVX_SFR_SPS_SMR_MASK _ULL(0x80000) /* Step Mode Ready */ +#define KVX_SFR_SPS_SMR_SHIFT 19 +#define KVX_SFR_SPS_SMR_WIDTH 1 +#define KVX_SFR_SPS_SMR_WFXL_MASK _ULL(0x80000) +#define KVX_SFR_SPS_SMR_WFXL_CLEAR _ULL(0x80000) +#define KVX_SFR_SPS_SMR_WFXL_SET _ULL(0x8000000000000) + +#define KVX_SFR_SPS_PMJ_MASK _ULL(0xf00000) /* Page Mask in JTLB. */ +#define KVX_SFR_SPS_PMJ_SHIFT 20 +#define KVX_SFR_SPS_PMJ_WIDTH 4 +#define KVX_SFR_SPS_PMJ_WFXL_MASK _ULL(0xf00000) +#define KVX_SFR_SPS_PMJ_WFXL_CLEAR _ULL(0xf00000) +#define KVX_SFR_SPS_PMJ_WFXL_SET _ULL(0xf0000000000000) + +#define KVX_SFR_SPS_MMUP_MASK _ULL(0x1000000) /* Privileged on MMU. */ +#define KVX_SFR_SPS_MMUP_SHIFT 24 +#define KVX_SFR_SPS_MMUP_WIDTH 1 +#define KVX_SFR_SPS_MMUP_WFXL_MASK _ULL(0x1000000) +#define KVX_SFR_SPS_MMUP_WFXL_CLEAR _ULL(0x1000000) +#define KVX_SFR_SPS_MMUP_WFXL_SET _ULL(0x100000000000000) + +#define KVX_SFR_SPS_PL0_PL_MASK _ULL(0x3) /* Current Privilege Level */ +#define KVX_SFR_SPS_PL0_PL_SHIFT 0 +#define KVX_SFR_SPS_PL0_PL_WIDTH 2 +#define KVX_SFR_SPS_PL0_PL_WFXL_MASK _ULL(0x3) +#define KVX_SFR_SPS_PL0_PL_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_SPS_PL0_PL_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_SPS_PL0_ET_MASK _ULL(0x4) /* Exception Taken */ +#define KVX_SFR_SPS_PL0_ET_SHIFT 2 +#define KVX_SFR_SPS_PL0_ET_WIDTH 1 +#define KVX_SFR_SPS_PL0_ET_WFXL_MASK _ULL(0x4) +#define KVX_SFR_SPS_PL0_ET_WFXL_CLEAR _ULL(0x4) +#define KVX_SFR_SPS_PL0_ET_WFXL_SET _ULL(0x400000000) + +#define KVX_SFR_SPS_PL0_HTD_MASK _ULL(0x8) /* Hardware Trap Disable */ +#define KVX_SFR_SPS_PL0_HTD_SHIFT 3 +#define KVX_SFR_SPS_PL0_HTD_WIDTH 1 +#define KVX_SFR_SPS_PL0_HTD_WFXL_MASK _ULL(0x8) +#define KVX_SFR_SPS_PL0_HTD_WFXL_CLEAR _ULL(0x8) +#define KVX_SFR_SPS_PL0_HTD_WFXL_SET _ULL(0x800000000) + +#define KVX_SFR_SPS_PL0_IE_MASK _ULL(0x10) /* Interrupt Enable */ +#define KVX_SFR_SPS_PL0_IE_SHIFT 4 +#define KVX_SFR_SPS_PL0_IE_WIDTH 1 +#define KVX_SFR_SPS_PL0_IE_WFXL_MASK _ULL(0x10) +#define KVX_SFR_SPS_PL0_IE_WFXL_CLEAR _ULL(0x10) +#define KVX_SFR_SPS_PL0_IE_WFXL_SET _ULL(0x1000000000) + +#define KVX_SFR_SPS_PL0_HLE_MASK _ULL(0x20) /* Hardware Loop Enable */ +#define KVX_SFR_SPS_PL0_HLE_SHIFT 5 +#define KVX_SFR_SPS_PL0_HLE_WIDTH 1 +#define KVX_SFR_SPS_PL0_HLE_WFXL_MASK _ULL(0x20) +#define KVX_SFR_SPS_PL0_HLE_WFXL_CLEAR _ULL(0x20) +#define KVX_SFR_SPS_PL0_HLE_WFXL_SET _ULL(0x2000000000) + +#define KVX_SFR_SPS_PL0_SRE_MASK _ULL(0x40) /* Software REserved */ +#define KVX_SFR_SPS_PL0_SRE_SHIFT 6 +#define KVX_SFR_SPS_PL0_SRE_WIDTH 1 +#define KVX_SFR_SPS_PL0_SRE_WFXL_MASK _ULL(0x40) +#define KVX_SFR_SPS_PL0_SRE_WFXL_CLEAR _ULL(0x40) +#define KVX_SFR_SPS_PL0_SRE_WFXL_SET _ULL(0x4000000000) + +#define KVX_SFR_SPS_PL0_DAUS_MASK _ULL(0x80) /* Data Accesses Use SPS settings */ +#define KVX_SFR_SPS_PL0_DAUS_SHIFT 7 +#define KVX_SFR_SPS_PL0_DAUS_WIDTH 1 +#define KVX_SFR_SPS_PL0_DAUS_WFXL_MASK _ULL(0x80) +#define KVX_SFR_SPS_PL0_DAUS_WFXL_CLEAR _ULL(0x80) +#define KVX_SFR_SPS_PL0_DAUS_WFXL_SET _ULL(0x8000000000) + +#define KVX_SFR_SPS_PL0_ICE_MASK _ULL(0x100) /* Instruction Cache Enable */ +#define KVX_SFR_SPS_PL0_ICE_SHIFT 8 +#define KVX_SFR_SPS_PL0_ICE_WIDTH 1 +#define KVX_SFR_SPS_PL0_ICE_WFXL_MASK _ULL(0x100) +#define KVX_SFR_SPS_PL0_ICE_WFXL_CLEAR _ULL(0x100) +#define KVX_SFR_SPS_PL0_ICE_WFXL_SET _ULL(0x10000000000) + +#define KVX_SFR_SPS_PL0_USE_MASK _ULL(0x200) /* Uncached Streaming Enable */ +#define KVX_SFR_SPS_PL0_USE_SHIFT 9 +#define KVX_SFR_SPS_PL0_USE_WIDTH 1 +#define KVX_SFR_SPS_PL0_USE_WFXL_MASK _ULL(0x200) +#define KVX_SFR_SPS_PL0_USE_WFXL_CLEAR _ULL(0x200) +#define KVX_SFR_SPS_PL0_USE_WFXL_SET _ULL(0x20000000000) + +#define KVX_SFR_SPS_PL0_DCE_MASK _ULL(0x400) /* Data Cache Enable */ +#define KVX_SFR_SPS_PL0_DCE_SHIFT 10 +#define KVX_SFR_SPS_PL0_DCE_WIDTH 1 +#define KVX_SFR_SPS_PL0_DCE_WFXL_MASK _ULL(0x400) +#define KVX_SFR_SPS_PL0_DCE_WFXL_CLEAR _ULL(0x400) +#define KVX_SFR_SPS_PL0_DCE_WFXL_SET _ULL(0x40000000000) + +#define KVX_SFR_SPS_PL0_MME_MASK _ULL(0x800) /* Memory Management Enable */ +#define KVX_SFR_SPS_PL0_MME_SHIFT 11 +#define KVX_SFR_SPS_PL0_MME_WIDTH 1 +#define KVX_SFR_SPS_PL0_MME_WFXL_MASK _ULL(0x800) +#define KVX_SFR_SPS_PL0_MME_WFXL_CLEAR _ULL(0x800) +#define KVX_SFR_SPS_PL0_MME_WFXL_SET _ULL(0x80000000000) + +#define KVX_SFR_SPS_PL0_IL_MASK _ULL(0x3000) /* Interrupt Level */ +#define KVX_SFR_SPS_PL0_IL_SHIFT 12 +#define KVX_SFR_SPS_PL0_IL_WIDTH 2 +#define KVX_SFR_SPS_PL0_IL_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_SPS_PL0_IL_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_SPS_PL0_IL_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_SPS_PL0_VS_MASK _ULL(0xc000) /* Virtual Space */ +#define KVX_SFR_SPS_PL0_VS_SHIFT 14 +#define KVX_SFR_SPS_PL0_VS_WIDTH 2 +#define KVX_SFR_SPS_PL0_VS_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_SPS_PL0_VS_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_SPS_PL0_VS_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_SPS_PL0_V64_MASK _ULL(0x10000) /* Virtual 64 bits mode. */ +#define KVX_SFR_SPS_PL0_V64_SHIFT 16 +#define KVX_SFR_SPS_PL0_V64_WIDTH 1 +#define KVX_SFR_SPS_PL0_V64_WFXL_MASK _ULL(0x10000) +#define KVX_SFR_SPS_PL0_V64_WFXL_CLEAR _ULL(0x10000) +#define KVX_SFR_SPS_PL0_V64_WFXL_SET _ULL(0x1000000000000) + +#define KVX_SFR_SPS_PL0_L2E_MASK _ULL(0x20000) /* L2 cache Enable. */ +#define KVX_SFR_SPS_PL0_L2E_SHIFT 17 +#define KVX_SFR_SPS_PL0_L2E_WIDTH 1 +#define KVX_SFR_SPS_PL0_L2E_WFXL_MASK _ULL(0x20000) +#define KVX_SFR_SPS_PL0_L2E_WFXL_CLEAR _ULL(0x20000) +#define KVX_SFR_SPS_PL0_L2E_WFXL_SET _ULL(0x2000000000000) + +#define KVX_SFR_SPS_PL0_SME_MASK _ULL(0x40000) /* Step Mode Enabled */ +#define KVX_SFR_SPS_PL0_SME_SHIFT 18 +#define KVX_SFR_SPS_PL0_SME_WIDTH 1 +#define KVX_SFR_SPS_PL0_SME_WFXL_MASK _ULL(0x40000) +#define KVX_SFR_SPS_PL0_SME_WFXL_CLEAR _ULL(0x40000) +#define KVX_SFR_SPS_PL0_SME_WFXL_SET _ULL(0x4000000000000) + +#define KVX_SFR_SPS_PL0_SMR_MASK _ULL(0x80000) /* Step Mode Ready */ +#define KVX_SFR_SPS_PL0_SMR_SHIFT 19 +#define KVX_SFR_SPS_PL0_SMR_WIDTH 1 +#define KVX_SFR_SPS_PL0_SMR_WFXL_MASK _ULL(0x80000) +#define KVX_SFR_SPS_PL0_SMR_WFXL_CLEAR _ULL(0x80000) +#define KVX_SFR_SPS_PL0_SMR_WFXL_SET _ULL(0x8000000000000) + +#define KVX_SFR_SPS_PL0_PMJ_MASK _ULL(0xf00000) /* Page Mask in JTLB. */ +#define KVX_SFR_SPS_PL0_PMJ_SHIFT 20 +#define KVX_SFR_SPS_PL0_PMJ_WIDTH 4 +#define KVX_SFR_SPS_PL0_PMJ_WFXL_MASK _ULL(0xf00000) +#define KVX_SFR_SPS_PL0_PMJ_WFXL_CLEAR _ULL(0xf00000) +#define KVX_SFR_SPS_PL0_PMJ_WFXL_SET _ULL(0xf0000000000000) + +#define KVX_SFR_SPS_PL0_MMUP_MASK _ULL(0x1000000) /* Privileged on MMU. */ +#define KVX_SFR_SPS_PL0_MMUP_SHIFT 24 +#define KVX_SFR_SPS_PL0_MMUP_WIDTH 1 +#define KVX_SFR_SPS_PL0_MMUP_WFXL_MASK _ULL(0x1000000) +#define KVX_SFR_SPS_PL0_MMUP_WFXL_CLEAR _ULL(0x1000000) +#define KVX_SFR_SPS_PL0_MMUP_WFXL_SET _ULL(0x100000000000000) + +#define KVX_SFR_SPS_PL1_PL_MASK _ULL(0x3) /* Current Privilege Level */ +#define KVX_SFR_SPS_PL1_PL_SHIFT 0 +#define KVX_SFR_SPS_PL1_PL_WIDTH 2 +#define KVX_SFR_SPS_PL1_PL_WFXL_MASK _ULL(0x3) +#define KVX_SFR_SPS_PL1_PL_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_SPS_PL1_PL_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_SPS_PL1_ET_MASK _ULL(0x4) /* Exception Taken */ +#define KVX_SFR_SPS_PL1_ET_SHIFT 2 +#define KVX_SFR_SPS_PL1_ET_WIDTH 1 +#define KVX_SFR_SPS_PL1_ET_WFXL_MASK _ULL(0x4) +#define KVX_SFR_SPS_PL1_ET_WFXL_CLEAR _ULL(0x4) +#define KVX_SFR_SPS_PL1_ET_WFXL_SET _ULL(0x400000000) + +#define KVX_SFR_SPS_PL1_HTD_MASK _ULL(0x8) /* Hardware Trap Disable */ +#define KVX_SFR_SPS_PL1_HTD_SHIFT 3 +#define KVX_SFR_SPS_PL1_HTD_WIDTH 1 +#define KVX_SFR_SPS_PL1_HTD_WFXL_MASK _ULL(0x8) +#define KVX_SFR_SPS_PL1_HTD_WFXL_CLEAR _ULL(0x8) +#define KVX_SFR_SPS_PL1_HTD_WFXL_SET _ULL(0x800000000) + +#define KVX_SFR_SPS_PL1_IE_MASK _ULL(0x10) /* Interrupt Enable */ +#define KVX_SFR_SPS_PL1_IE_SHIFT 4 +#define KVX_SFR_SPS_PL1_IE_WIDTH 1 +#define KVX_SFR_SPS_PL1_IE_WFXL_MASK _ULL(0x10) +#define KVX_SFR_SPS_PL1_IE_WFXL_CLEAR _ULL(0x10) +#define KVX_SFR_SPS_PL1_IE_WFXL_SET _ULL(0x1000000000) + +#define KVX_SFR_SPS_PL1_HLE_MASK _ULL(0x20) /* Hardware Loop Enable */ +#define KVX_SFR_SPS_PL1_HLE_SHIFT 5 +#define KVX_SFR_SPS_PL1_HLE_WIDTH 1 +#define KVX_SFR_SPS_PL1_HLE_WFXL_MASK _ULL(0x20) +#define KVX_SFR_SPS_PL1_HLE_WFXL_CLEAR _ULL(0x20) +#define KVX_SFR_SPS_PL1_HLE_WFXL_SET _ULL(0x2000000000) + +#define KVX_SFR_SPS_PL1_SRE_MASK _ULL(0x40) /* Software REserved */ +#define KVX_SFR_SPS_PL1_SRE_SHIFT 6 +#define KVX_SFR_SPS_PL1_SRE_WIDTH 1 +#define KVX_SFR_SPS_PL1_SRE_WFXL_MASK _ULL(0x40) +#define KVX_SFR_SPS_PL1_SRE_WFXL_CLEAR _ULL(0x40) +#define KVX_SFR_SPS_PL1_SRE_WFXL_SET _ULL(0x4000000000) + +#define KVX_SFR_SPS_PL1_DAUS_MASK _ULL(0x80) /* Data Accesses Use SPS settings */ +#define KVX_SFR_SPS_PL1_DAUS_SHIFT 7 +#define KVX_SFR_SPS_PL1_DAUS_WIDTH 1 +#define KVX_SFR_SPS_PL1_DAUS_WFXL_MASK _ULL(0x80) +#define KVX_SFR_SPS_PL1_DAUS_WFXL_CLEAR _ULL(0x80) +#define KVX_SFR_SPS_PL1_DAUS_WFXL_SET _ULL(0x8000000000) + +#define KVX_SFR_SPS_PL1_ICE_MASK _ULL(0x100) /* Instruction Cache Enable */ +#define KVX_SFR_SPS_PL1_ICE_SHIFT 8 +#define KVX_SFR_SPS_PL1_ICE_WIDTH 1 +#define KVX_SFR_SPS_PL1_ICE_WFXL_MASK _ULL(0x100) +#define KVX_SFR_SPS_PL1_ICE_WFXL_CLEAR _ULL(0x100) +#define KVX_SFR_SPS_PL1_ICE_WFXL_SET _ULL(0x10000000000) + +#define KVX_SFR_SPS_PL1_USE_MASK _ULL(0x200) /* Uncached Streaming Enable */ +#define KVX_SFR_SPS_PL1_USE_SHIFT 9 +#define KVX_SFR_SPS_PL1_USE_WIDTH 1 +#define KVX_SFR_SPS_PL1_USE_WFXL_MASK _ULL(0x200) +#define KVX_SFR_SPS_PL1_USE_WFXL_CLEAR _ULL(0x200) +#define KVX_SFR_SPS_PL1_USE_WFXL_SET _ULL(0x20000000000) + +#define KVX_SFR_SPS_PL1_DCE_MASK _ULL(0x400) /* Data Cache Enable */ +#define KVX_SFR_SPS_PL1_DCE_SHIFT 10 +#define KVX_SFR_SPS_PL1_DCE_WIDTH 1 +#define KVX_SFR_SPS_PL1_DCE_WFXL_MASK _ULL(0x400) +#define KVX_SFR_SPS_PL1_DCE_WFXL_CLEAR _ULL(0x400) +#define KVX_SFR_SPS_PL1_DCE_WFXL_SET _ULL(0x40000000000) + +#define KVX_SFR_SPS_PL1_MME_MASK _ULL(0x800) /* Memory Management Enable */ +#define KVX_SFR_SPS_PL1_MME_SHIFT 11 +#define KVX_SFR_SPS_PL1_MME_WIDTH 1 +#define KVX_SFR_SPS_PL1_MME_WFXL_MASK _ULL(0x800) +#define KVX_SFR_SPS_PL1_MME_WFXL_CLEAR _ULL(0x800) +#define KVX_SFR_SPS_PL1_MME_WFXL_SET _ULL(0x80000000000) + +#define KVX_SFR_SPS_PL1_IL_MASK _ULL(0x3000) /* Interrupt Level */ +#define KVX_SFR_SPS_PL1_IL_SHIFT 12 +#define KVX_SFR_SPS_PL1_IL_WIDTH 2 +#define KVX_SFR_SPS_PL1_IL_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_SPS_PL1_IL_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_SPS_PL1_IL_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_SPS_PL1_VS_MASK _ULL(0xc000) /* Virtual Space */ +#define KVX_SFR_SPS_PL1_VS_SHIFT 14 +#define KVX_SFR_SPS_PL1_VS_WIDTH 2 +#define KVX_SFR_SPS_PL1_VS_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_SPS_PL1_VS_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_SPS_PL1_VS_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_SPS_PL1_V64_MASK _ULL(0x10000) /* Virtual 64 bits mode. */ +#define KVX_SFR_SPS_PL1_V64_SHIFT 16 +#define KVX_SFR_SPS_PL1_V64_WIDTH 1 +#define KVX_SFR_SPS_PL1_V64_WFXL_MASK _ULL(0x10000) +#define KVX_SFR_SPS_PL1_V64_WFXL_CLEAR _ULL(0x10000) +#define KVX_SFR_SPS_PL1_V64_WFXL_SET _ULL(0x1000000000000) + +#define KVX_SFR_SPS_PL1_L2E_MASK _ULL(0x20000) /* L2 cache Enable. */ +#define KVX_SFR_SPS_PL1_L2E_SHIFT 17 +#define KVX_SFR_SPS_PL1_L2E_WIDTH 1 +#define KVX_SFR_SPS_PL1_L2E_WFXL_MASK _ULL(0x20000) +#define KVX_SFR_SPS_PL1_L2E_WFXL_CLEAR _ULL(0x20000) +#define KVX_SFR_SPS_PL1_L2E_WFXL_SET _ULL(0x2000000000000) + +#define KVX_SFR_SPS_PL1_SME_MASK _ULL(0x40000) /* Step Mode Enabled */ +#define KVX_SFR_SPS_PL1_SME_SHIFT 18 +#define KVX_SFR_SPS_PL1_SME_WIDTH 1 +#define KVX_SFR_SPS_PL1_SME_WFXL_MASK _ULL(0x40000) +#define KVX_SFR_SPS_PL1_SME_WFXL_CLEAR _ULL(0x40000) +#define KVX_SFR_SPS_PL1_SME_WFXL_SET _ULL(0x4000000000000) + +#define KVX_SFR_SPS_PL1_SMR_MASK _ULL(0x80000) /* Step Mode Ready */ +#define KVX_SFR_SPS_PL1_SMR_SHIFT 19 +#define KVX_SFR_SPS_PL1_SMR_WIDTH 1 +#define KVX_SFR_SPS_PL1_SMR_WFXL_MASK _ULL(0x80000) +#define KVX_SFR_SPS_PL1_SMR_WFXL_CLEAR _ULL(0x80000) +#define KVX_SFR_SPS_PL1_SMR_WFXL_SET _ULL(0x8000000000000) + +#define KVX_SFR_SPS_PL1_PMJ_MASK _ULL(0xf00000) /* Page Mask in JTLB. */ +#define KVX_SFR_SPS_PL1_PMJ_SHIFT 20 +#define KVX_SFR_SPS_PL1_PMJ_WIDTH 4 +#define KVX_SFR_SPS_PL1_PMJ_WFXL_MASK _ULL(0xf00000) +#define KVX_SFR_SPS_PL1_PMJ_WFXL_CLEAR _ULL(0xf00000) +#define KVX_SFR_SPS_PL1_PMJ_WFXL_SET _ULL(0xf0000000000000) + +#define KVX_SFR_SPS_PL1_MMUP_MASK _ULL(0x1000000) /* Privileged on MMU. */ +#define KVX_SFR_SPS_PL1_MMUP_SHIFT 24 +#define KVX_SFR_SPS_PL1_MMUP_WIDTH 1 +#define KVX_SFR_SPS_PL1_MMUP_WFXL_MASK _ULL(0x1000000) +#define KVX_SFR_SPS_PL1_MMUP_WFXL_CLEAR _ULL(0x1000000) +#define KVX_SFR_SPS_PL1_MMUP_WFXL_SET _ULL(0x100000000000000) + +#define KVX_SFR_SPS_PL2_PL_MASK _ULL(0x3) /* Current Privilege Level */ +#define KVX_SFR_SPS_PL2_PL_SHIFT 0 +#define KVX_SFR_SPS_PL2_PL_WIDTH 2 +#define KVX_SFR_SPS_PL2_PL_WFXL_MASK _ULL(0x3) +#define KVX_SFR_SPS_PL2_PL_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_SPS_PL2_PL_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_SPS_PL2_ET_MASK _ULL(0x4) /* Exception Taken */ +#define KVX_SFR_SPS_PL2_ET_SHIFT 2 +#define KVX_SFR_SPS_PL2_ET_WIDTH 1 +#define KVX_SFR_SPS_PL2_ET_WFXL_MASK _ULL(0x4) +#define KVX_SFR_SPS_PL2_ET_WFXL_CLEAR _ULL(0x4) +#define KVX_SFR_SPS_PL2_ET_WFXL_SET _ULL(0x400000000) + +#define KVX_SFR_SPS_PL2_HTD_MASK _ULL(0x8) /* Hardware Trap Disable */ +#define KVX_SFR_SPS_PL2_HTD_SHIFT 3 +#define KVX_SFR_SPS_PL2_HTD_WIDTH 1 +#define KVX_SFR_SPS_PL2_HTD_WFXL_MASK _ULL(0x8) +#define KVX_SFR_SPS_PL2_HTD_WFXL_CLEAR _ULL(0x8) +#define KVX_SFR_SPS_PL2_HTD_WFXL_SET _ULL(0x800000000) + +#define KVX_SFR_SPS_PL2_IE_MASK _ULL(0x10) /* Interrupt Enable */ +#define KVX_SFR_SPS_PL2_IE_SHIFT 4 +#define KVX_SFR_SPS_PL2_IE_WIDTH 1 +#define KVX_SFR_SPS_PL2_IE_WFXL_MASK _ULL(0x10) +#define KVX_SFR_SPS_PL2_IE_WFXL_CLEAR _ULL(0x10) +#define KVX_SFR_SPS_PL2_IE_WFXL_SET _ULL(0x1000000000) + +#define KVX_SFR_SPS_PL2_HLE_MASK _ULL(0x20) /* Hardware Loop Enable */ +#define KVX_SFR_SPS_PL2_HLE_SHIFT 5 +#define KVX_SFR_SPS_PL2_HLE_WIDTH 1 +#define KVX_SFR_SPS_PL2_HLE_WFXL_MASK _ULL(0x20) +#define KVX_SFR_SPS_PL2_HLE_WFXL_CLEAR _ULL(0x20) +#define KVX_SFR_SPS_PL2_HLE_WFXL_SET _ULL(0x2000000000) + +#define KVX_SFR_SPS_PL2_SRE_MASK _ULL(0x40) /* Software REserved */ +#define KVX_SFR_SPS_PL2_SRE_SHIFT 6 +#define KVX_SFR_SPS_PL2_SRE_WIDTH 1 +#define KVX_SFR_SPS_PL2_SRE_WFXL_MASK _ULL(0x40) +#define KVX_SFR_SPS_PL2_SRE_WFXL_CLEAR _ULL(0x40) +#define KVX_SFR_SPS_PL2_SRE_WFXL_SET _ULL(0x4000000000) + +#define KVX_SFR_SPS_PL2_DAUS_MASK _ULL(0x80) /* Data Accesses Use SPS settings */ +#define KVX_SFR_SPS_PL2_DAUS_SHIFT 7 +#define KVX_SFR_SPS_PL2_DAUS_WIDTH 1 +#define KVX_SFR_SPS_PL2_DAUS_WFXL_MASK _ULL(0x80) +#define KVX_SFR_SPS_PL2_DAUS_WFXL_CLEAR _ULL(0x80) +#define KVX_SFR_SPS_PL2_DAUS_WFXL_SET _ULL(0x8000000000) + +#define KVX_SFR_SPS_PL2_ICE_MASK _ULL(0x100) /* Instruction Cache Enable */ +#define KVX_SFR_SPS_PL2_ICE_SHIFT 8 +#define KVX_SFR_SPS_PL2_ICE_WIDTH 1 +#define KVX_SFR_SPS_PL2_ICE_WFXL_MASK _ULL(0x100) +#define KVX_SFR_SPS_PL2_ICE_WFXL_CLEAR _ULL(0x100) +#define KVX_SFR_SPS_PL2_ICE_WFXL_SET _ULL(0x10000000000) + +#define KVX_SFR_SPS_PL2_USE_MASK _ULL(0x200) /* Uncached Streaming Enable */ +#define KVX_SFR_SPS_PL2_USE_SHIFT 9 +#define KVX_SFR_SPS_PL2_USE_WIDTH 1 +#define KVX_SFR_SPS_PL2_USE_WFXL_MASK _ULL(0x200) +#define KVX_SFR_SPS_PL2_USE_WFXL_CLEAR _ULL(0x200) +#define KVX_SFR_SPS_PL2_USE_WFXL_SET _ULL(0x20000000000) + +#define KVX_SFR_SPS_PL2_DCE_MASK _ULL(0x400) /* Data Cache Enable */ +#define KVX_SFR_SPS_PL2_DCE_SHIFT 10 +#define KVX_SFR_SPS_PL2_DCE_WIDTH 1 +#define KVX_SFR_SPS_PL2_DCE_WFXL_MASK _ULL(0x400) +#define KVX_SFR_SPS_PL2_DCE_WFXL_CLEAR _ULL(0x400) +#define KVX_SFR_SPS_PL2_DCE_WFXL_SET _ULL(0x40000000000) + +#define KVX_SFR_SPS_PL2_MME_MASK _ULL(0x800) /* Memory Management Enable */ +#define KVX_SFR_SPS_PL2_MME_SHIFT 11 +#define KVX_SFR_SPS_PL2_MME_WIDTH 1 +#define KVX_SFR_SPS_PL2_MME_WFXL_MASK _ULL(0x800) +#define KVX_SFR_SPS_PL2_MME_WFXL_CLEAR _ULL(0x800) +#define KVX_SFR_SPS_PL2_MME_WFXL_SET _ULL(0x80000000000) + +#define KVX_SFR_SPS_PL2_IL_MASK _ULL(0x3000) /* Interrupt Level */ +#define KVX_SFR_SPS_PL2_IL_SHIFT 12 +#define KVX_SFR_SPS_PL2_IL_WIDTH 2 +#define KVX_SFR_SPS_PL2_IL_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_SPS_PL2_IL_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_SPS_PL2_IL_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_SPS_PL2_VS_MASK _ULL(0xc000) /* Virtual Space */ +#define KVX_SFR_SPS_PL2_VS_SHIFT 14 +#define KVX_SFR_SPS_PL2_VS_WIDTH 2 +#define KVX_SFR_SPS_PL2_VS_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_SPS_PL2_VS_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_SPS_PL2_VS_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_SPS_PL2_V64_MASK _ULL(0x10000) /* Virtual 64 bits mode. */ +#define KVX_SFR_SPS_PL2_V64_SHIFT 16 +#define KVX_SFR_SPS_PL2_V64_WIDTH 1 +#define KVX_SFR_SPS_PL2_V64_WFXL_MASK _ULL(0x10000) +#define KVX_SFR_SPS_PL2_V64_WFXL_CLEAR _ULL(0x10000) +#define KVX_SFR_SPS_PL2_V64_WFXL_SET _ULL(0x1000000000000) + +#define KVX_SFR_SPS_PL2_L2E_MASK _ULL(0x20000) /* L2 cache Enable. */ +#define KVX_SFR_SPS_PL2_L2E_SHIFT 17 +#define KVX_SFR_SPS_PL2_L2E_WIDTH 1 +#define KVX_SFR_SPS_PL2_L2E_WFXL_MASK _ULL(0x20000) +#define KVX_SFR_SPS_PL2_L2E_WFXL_CLEAR _ULL(0x20000) +#define KVX_SFR_SPS_PL2_L2E_WFXL_SET _ULL(0x2000000000000) + +#define KVX_SFR_SPS_PL2_SME_MASK _ULL(0x40000) /* Step Mode Enabled */ +#define KVX_SFR_SPS_PL2_SME_SHIFT 18 +#define KVX_SFR_SPS_PL2_SME_WIDTH 1 +#define KVX_SFR_SPS_PL2_SME_WFXL_MASK _ULL(0x40000) +#define KVX_SFR_SPS_PL2_SME_WFXL_CLEAR _ULL(0x40000) +#define KVX_SFR_SPS_PL2_SME_WFXL_SET _ULL(0x4000000000000) + +#define KVX_SFR_SPS_PL2_SMR_MASK _ULL(0x80000) /* Step Mode Ready */ +#define KVX_SFR_SPS_PL2_SMR_SHIFT 19 +#define KVX_SFR_SPS_PL2_SMR_WIDTH 1 +#define KVX_SFR_SPS_PL2_SMR_WFXL_MASK _ULL(0x80000) +#define KVX_SFR_SPS_PL2_SMR_WFXL_CLEAR _ULL(0x80000) +#define KVX_SFR_SPS_PL2_SMR_WFXL_SET _ULL(0x8000000000000) + +#define KVX_SFR_SPS_PL2_PMJ_MASK _ULL(0xf00000) /* Page Mask in JTLB. */ +#define KVX_SFR_SPS_PL2_PMJ_SHIFT 20 +#define KVX_SFR_SPS_PL2_PMJ_WIDTH 4 +#define KVX_SFR_SPS_PL2_PMJ_WFXL_MASK _ULL(0xf00000) +#define KVX_SFR_SPS_PL2_PMJ_WFXL_CLEAR _ULL(0xf00000) +#define KVX_SFR_SPS_PL2_PMJ_WFXL_SET _ULL(0xf0000000000000) + +#define KVX_SFR_SPS_PL2_MMUP_MASK _ULL(0x1000000) /* Privileged on MMU. */ +#define KVX_SFR_SPS_PL2_MMUP_SHIFT 24 +#define KVX_SFR_SPS_PL2_MMUP_WIDTH 1 +#define KVX_SFR_SPS_PL2_MMUP_WFXL_MASK _ULL(0x1000000) +#define KVX_SFR_SPS_PL2_MMUP_WFXL_CLEAR _ULL(0x1000000) +#define KVX_SFR_SPS_PL2_MMUP_WFXL_SET _ULL(0x100000000000000) + +#define KVX_SFR_SPS_PL3_PL_MASK _ULL(0x3) /* Current Privilege Level */ +#define KVX_SFR_SPS_PL3_PL_SHIFT 0 +#define KVX_SFR_SPS_PL3_PL_WIDTH 2 +#define KVX_SFR_SPS_PL3_PL_WFXL_MASK _ULL(0x3) +#define KVX_SFR_SPS_PL3_PL_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_SPS_PL3_PL_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_SPS_PL3_ET_MASK _ULL(0x4) /* Exception Taken */ +#define KVX_SFR_SPS_PL3_ET_SHIFT 2 +#define KVX_SFR_SPS_PL3_ET_WIDTH 1 +#define KVX_SFR_SPS_PL3_ET_WFXL_MASK _ULL(0x4) +#define KVX_SFR_SPS_PL3_ET_WFXL_CLEAR _ULL(0x4) +#define KVX_SFR_SPS_PL3_ET_WFXL_SET _ULL(0x400000000) + +#define KVX_SFR_SPS_PL3_HTD_MASK _ULL(0x8) /* Hardware Trap Disable */ +#define KVX_SFR_SPS_PL3_HTD_SHIFT 3 +#define KVX_SFR_SPS_PL3_HTD_WIDTH 1 +#define KVX_SFR_SPS_PL3_HTD_WFXL_MASK _ULL(0x8) +#define KVX_SFR_SPS_PL3_HTD_WFXL_CLEAR _ULL(0x8) +#define KVX_SFR_SPS_PL3_HTD_WFXL_SET _ULL(0x800000000) + +#define KVX_SFR_SPS_PL3_IE_MASK _ULL(0x10) /* Interrupt Enable */ +#define KVX_SFR_SPS_PL3_IE_SHIFT 4 +#define KVX_SFR_SPS_PL3_IE_WIDTH 1 +#define KVX_SFR_SPS_PL3_IE_WFXL_MASK _ULL(0x10) +#define KVX_SFR_SPS_PL3_IE_WFXL_CLEAR _ULL(0x10) +#define KVX_SFR_SPS_PL3_IE_WFXL_SET _ULL(0x1000000000) + +#define KVX_SFR_SPS_PL3_HLE_MASK _ULL(0x20) /* Hardware Loop Enable */ +#define KVX_SFR_SPS_PL3_HLE_SHIFT 5 +#define KVX_SFR_SPS_PL3_HLE_WIDTH 1 +#define KVX_SFR_SPS_PL3_HLE_WFXL_MASK _ULL(0x20) +#define KVX_SFR_SPS_PL3_HLE_WFXL_CLEAR _ULL(0x20) +#define KVX_SFR_SPS_PL3_HLE_WFXL_SET _ULL(0x2000000000) + +#define KVX_SFR_SPS_PL3_SRE_MASK _ULL(0x40) /* Software REserved */ +#define KVX_SFR_SPS_PL3_SRE_SHIFT 6 +#define KVX_SFR_SPS_PL3_SRE_WIDTH 1 +#define KVX_SFR_SPS_PL3_SRE_WFXL_MASK _ULL(0x40) +#define KVX_SFR_SPS_PL3_SRE_WFXL_CLEAR _ULL(0x40) +#define KVX_SFR_SPS_PL3_SRE_WFXL_SET _ULL(0x4000000000) + +#define KVX_SFR_SPS_PL3_DAUS_MASK _ULL(0x80) /* Data Accesses Use SPS settings */ +#define KVX_SFR_SPS_PL3_DAUS_SHIFT 7 +#define KVX_SFR_SPS_PL3_DAUS_WIDTH 1 +#define KVX_SFR_SPS_PL3_DAUS_WFXL_MASK _ULL(0x80) +#define KVX_SFR_SPS_PL3_DAUS_WFXL_CLEAR _ULL(0x80) +#define KVX_SFR_SPS_PL3_DAUS_WFXL_SET _ULL(0x8000000000) + +#define KVX_SFR_SPS_PL3_ICE_MASK _ULL(0x100) /* Instruction Cache Enable */ +#define KVX_SFR_SPS_PL3_ICE_SHIFT 8 +#define KVX_SFR_SPS_PL3_ICE_WIDTH 1 +#define KVX_SFR_SPS_PL3_ICE_WFXL_MASK _ULL(0x100) +#define KVX_SFR_SPS_PL3_ICE_WFXL_CLEAR _ULL(0x100) +#define KVX_SFR_SPS_PL3_ICE_WFXL_SET _ULL(0x10000000000) + +#define KVX_SFR_SPS_PL3_USE_MASK _ULL(0x200) /* Uncached Streaming Enable */ +#define KVX_SFR_SPS_PL3_USE_SHIFT 9 +#define KVX_SFR_SPS_PL3_USE_WIDTH 1 +#define KVX_SFR_SPS_PL3_USE_WFXL_MASK _ULL(0x200) +#define KVX_SFR_SPS_PL3_USE_WFXL_CLEAR _ULL(0x200) +#define KVX_SFR_SPS_PL3_USE_WFXL_SET _ULL(0x20000000000) + +#define KVX_SFR_SPS_PL3_DCE_MASK _ULL(0x400) /* Data Cache Enable */ +#define KVX_SFR_SPS_PL3_DCE_SHIFT 10 +#define KVX_SFR_SPS_PL3_DCE_WIDTH 1 +#define KVX_SFR_SPS_PL3_DCE_WFXL_MASK _ULL(0x400) +#define KVX_SFR_SPS_PL3_DCE_WFXL_CLEAR _ULL(0x400) +#define KVX_SFR_SPS_PL3_DCE_WFXL_SET _ULL(0x40000000000) + +#define KVX_SFR_SPS_PL3_MME_MASK _ULL(0x800) /* Memory Management Enable */ +#define KVX_SFR_SPS_PL3_MME_SHIFT 11 +#define KVX_SFR_SPS_PL3_MME_WIDTH 1 +#define KVX_SFR_SPS_PL3_MME_WFXL_MASK _ULL(0x800) +#define KVX_SFR_SPS_PL3_MME_WFXL_CLEAR _ULL(0x800) +#define KVX_SFR_SPS_PL3_MME_WFXL_SET _ULL(0x80000000000) + +#define KVX_SFR_SPS_PL3_IL_MASK _ULL(0x3000) /* Interrupt Level */ +#define KVX_SFR_SPS_PL3_IL_SHIFT 12 +#define KVX_SFR_SPS_PL3_IL_WIDTH 2 +#define KVX_SFR_SPS_PL3_IL_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_SPS_PL3_IL_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_SPS_PL3_IL_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_SPS_PL3_VS_MASK _ULL(0xc000) /* Virtual Space */ +#define KVX_SFR_SPS_PL3_VS_SHIFT 14 +#define KVX_SFR_SPS_PL3_VS_WIDTH 2 +#define KVX_SFR_SPS_PL3_VS_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_SPS_PL3_VS_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_SPS_PL3_VS_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_SPS_PL3_V64_MASK _ULL(0x10000) /* Virtual 64 bits mode. */ +#define KVX_SFR_SPS_PL3_V64_SHIFT 16 +#define KVX_SFR_SPS_PL3_V64_WIDTH 1 +#define KVX_SFR_SPS_PL3_V64_WFXL_MASK _ULL(0x10000) +#define KVX_SFR_SPS_PL3_V64_WFXL_CLEAR _ULL(0x10000) +#define KVX_SFR_SPS_PL3_V64_WFXL_SET _ULL(0x1000000000000) + +#define KVX_SFR_SPS_PL3_L2E_MASK _ULL(0x20000) /* L2 cache Enable. */ +#define KVX_SFR_SPS_PL3_L2E_SHIFT 17 +#define KVX_SFR_SPS_PL3_L2E_WIDTH 1 +#define KVX_SFR_SPS_PL3_L2E_WFXL_MASK _ULL(0x20000) +#define KVX_SFR_SPS_PL3_L2E_WFXL_CLEAR _ULL(0x20000) +#define KVX_SFR_SPS_PL3_L2E_WFXL_SET _ULL(0x2000000000000) + +#define KVX_SFR_SPS_PL3_SME_MASK _ULL(0x40000) /* Step Mode Enabled */ +#define KVX_SFR_SPS_PL3_SME_SHIFT 18 +#define KVX_SFR_SPS_PL3_SME_WIDTH 1 +#define KVX_SFR_SPS_PL3_SME_WFXL_MASK _ULL(0x40000) +#define KVX_SFR_SPS_PL3_SME_WFXL_CLEAR _ULL(0x40000) +#define KVX_SFR_SPS_PL3_SME_WFXL_SET _ULL(0x4000000000000) + +#define KVX_SFR_SPS_PL3_SMR_MASK _ULL(0x80000) /* Step Mode Ready */ +#define KVX_SFR_SPS_PL3_SMR_SHIFT 19 +#define KVX_SFR_SPS_PL3_SMR_WIDTH 1 +#define KVX_SFR_SPS_PL3_SMR_WFXL_MASK _ULL(0x80000) +#define KVX_SFR_SPS_PL3_SMR_WFXL_CLEAR _ULL(0x80000) +#define KVX_SFR_SPS_PL3_SMR_WFXL_SET _ULL(0x8000000000000) + +#define KVX_SFR_SPS_PL3_PMJ_MASK _ULL(0xf00000) /* Page Mask in JTLB. */ +#define KVX_SFR_SPS_PL3_PMJ_SHIFT 20 +#define KVX_SFR_SPS_PL3_PMJ_WIDTH 4 +#define KVX_SFR_SPS_PL3_PMJ_WFXL_MASK _ULL(0xf00000) +#define KVX_SFR_SPS_PL3_PMJ_WFXL_CLEAR _ULL(0xf00000) +#define KVX_SFR_SPS_PL3_PMJ_WFXL_SET _ULL(0xf0000000000000) + +#define KVX_SFR_SPS_PL3_MMUP_MASK _ULL(0x1000000) /* Privileged on MMU. */ +#define KVX_SFR_SPS_PL3_MMUP_SHIFT 24 +#define KVX_SFR_SPS_PL3_MMUP_WIDTH 1 +#define KVX_SFR_SPS_PL3_MMUP_WFXL_MASK _ULL(0x1000000) +#define KVX_SFR_SPS_PL3_MMUP_WFXL_CLEAR _ULL(0x1000000) +#define KVX_SFR_SPS_PL3_MMUP_WFXL_SET _ULL(0x100000000000000) + +#define KVX_SFR_PSO_PL0_MASK _ULL(0x3) /* Current Privilege Level bit 0 owner */ +#define KVX_SFR_PSO_PL0_SHIFT 0 +#define KVX_SFR_PSO_PL0_WIDTH 2 +#define KVX_SFR_PSO_PL0_WFXL_MASK _ULL(0x3) +#define KVX_SFR_PSO_PL0_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_PSO_PL0_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_PSO_PL1_MASK _ULL(0xc) /* Current Privilege Level bit 1 owner */ +#define KVX_SFR_PSO_PL1_SHIFT 2 +#define KVX_SFR_PSO_PL1_WIDTH 2 +#define KVX_SFR_PSO_PL1_WFXL_MASK _ULL(0xc) +#define KVX_SFR_PSO_PL1_WFXL_CLEAR _ULL(0xc) +#define KVX_SFR_PSO_PL1_WFXL_SET _ULL(0xc00000000) + +#define KVX_SFR_PSO_ET_MASK _ULL(0x30) /* Exception Taken owner */ +#define KVX_SFR_PSO_ET_SHIFT 4 +#define KVX_SFR_PSO_ET_WIDTH 2 +#define KVX_SFR_PSO_ET_WFXL_MASK _ULL(0x30) +#define KVX_SFR_PSO_ET_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_PSO_ET_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_PSO_HTD_MASK _ULL(0xc0) /* Hardware Trap Disable owner */ +#define KVX_SFR_PSO_HTD_SHIFT 6 +#define KVX_SFR_PSO_HTD_WIDTH 2 +#define KVX_SFR_PSO_HTD_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_PSO_HTD_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_PSO_HTD_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_PSO_IE_MASK _ULL(0x300) /* Interrupt Enable owner */ +#define KVX_SFR_PSO_IE_SHIFT 8 +#define KVX_SFR_PSO_IE_WIDTH 2 +#define KVX_SFR_PSO_IE_WFXL_MASK _ULL(0x300) +#define KVX_SFR_PSO_IE_WFXL_CLEAR _ULL(0x300) +#define KVX_SFR_PSO_IE_WFXL_SET _ULL(0x30000000000) + +#define KVX_SFR_PSO_HLE_MASK _ULL(0xc00) /* Hardware Loop Enable owner */ +#define KVX_SFR_PSO_HLE_SHIFT 10 +#define KVX_SFR_PSO_HLE_WIDTH 2 +#define KVX_SFR_PSO_HLE_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_PSO_HLE_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_PSO_HLE_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_PSO_SRE_MASK _ULL(0x3000) /* Software REserved owner */ +#define KVX_SFR_PSO_SRE_SHIFT 12 +#define KVX_SFR_PSO_SRE_WIDTH 2 +#define KVX_SFR_PSO_SRE_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_PSO_SRE_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_PSO_SRE_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_PSO_DAUS_MASK _ULL(0xc000) /* Data Accesses Use SPS settings owner */ +#define KVX_SFR_PSO_DAUS_SHIFT 14 +#define KVX_SFR_PSO_DAUS_WIDTH 2 +#define KVX_SFR_PSO_DAUS_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_PSO_DAUS_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_PSO_DAUS_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_PSO_ICE_MASK _ULL(0x30000) /* Instruction Cache Enable owner */ +#define KVX_SFR_PSO_ICE_SHIFT 16 +#define KVX_SFR_PSO_ICE_WIDTH 2 +#define KVX_SFR_PSO_ICE_WFXL_MASK _ULL(0x30000) +#define KVX_SFR_PSO_ICE_WFXL_CLEAR _ULL(0x30000) +#define KVX_SFR_PSO_ICE_WFXL_SET _ULL(0x3000000000000) + +#define KVX_SFR_PSO_USE_MASK _ULL(0xc0000) /* Uncached Streaming Enable owner */ +#define KVX_SFR_PSO_USE_SHIFT 18 +#define KVX_SFR_PSO_USE_WIDTH 2 +#define KVX_SFR_PSO_USE_WFXL_MASK _ULL(0xc0000) +#define KVX_SFR_PSO_USE_WFXL_CLEAR _ULL(0xc0000) +#define KVX_SFR_PSO_USE_WFXL_SET _ULL(0xc000000000000) + +#define KVX_SFR_PSO_DCE_MASK _ULL(0x300000) /* Data Cache Enable owner */ +#define KVX_SFR_PSO_DCE_SHIFT 20 +#define KVX_SFR_PSO_DCE_WIDTH 2 +#define KVX_SFR_PSO_DCE_WFXL_MASK _ULL(0x300000) +#define KVX_SFR_PSO_DCE_WFXL_CLEAR _ULL(0x300000) +#define KVX_SFR_PSO_DCE_WFXL_SET _ULL(0x30000000000000) + +#define KVX_SFR_PSO_MME_MASK _ULL(0xc00000) /* Memory Management Enable owner */ +#define KVX_SFR_PSO_MME_SHIFT 22 +#define KVX_SFR_PSO_MME_WIDTH 2 +#define KVX_SFR_PSO_MME_WFXL_MASK _ULL(0xc00000) +#define KVX_SFR_PSO_MME_WFXL_CLEAR _ULL(0xc00000) +#define KVX_SFR_PSO_MME_WFXL_SET _ULL(0xc0000000000000) + +#define KVX_SFR_PSO_IL0_MASK _ULL(0x3000000) /* Interrupt Level bit 0 owner */ +#define KVX_SFR_PSO_IL0_SHIFT 24 +#define KVX_SFR_PSO_IL0_WIDTH 2 +#define KVX_SFR_PSO_IL0_WFXL_MASK _ULL(0x3000000) +#define KVX_SFR_PSO_IL0_WFXL_CLEAR _ULL(0x3000000) +#define KVX_SFR_PSO_IL0_WFXL_SET _ULL(0x300000000000000) + +#define KVX_SFR_PSO_IL1_MASK _ULL(0xc000000) /* Interrupt Level bit 1 owner */ +#define KVX_SFR_PSO_IL1_SHIFT 26 +#define KVX_SFR_PSO_IL1_WIDTH 2 +#define KVX_SFR_PSO_IL1_WFXL_MASK _ULL(0xc000000) +#define KVX_SFR_PSO_IL1_WFXL_CLEAR _ULL(0xc000000) +#define KVX_SFR_PSO_IL1_WFXL_SET _ULL(0xc00000000000000) + +#define KVX_SFR_PSO_VS0_MASK _ULL(0x30000000) /* Virtual Space bit 0 owner */ +#define KVX_SFR_PSO_VS0_SHIFT 28 +#define KVX_SFR_PSO_VS0_WIDTH 2 +#define KVX_SFR_PSO_VS0_WFXL_MASK _ULL(0x30000000) +#define KVX_SFR_PSO_VS0_WFXL_CLEAR _ULL(0x30000000) +#define KVX_SFR_PSO_VS0_WFXL_SET _ULL(0x3000000000000000) + +#define KVX_SFR_PSO_VS1_MASK _ULL(0xc0000000) /* Virtual Space bit 1 owner */ +#define KVX_SFR_PSO_VS1_SHIFT 30 +#define KVX_SFR_PSO_VS1_WIDTH 2 +#define KVX_SFR_PSO_VS1_WFXL_MASK _ULL(0xc0000000) +#define KVX_SFR_PSO_VS1_WFXL_CLEAR _ULL(0xc0000000) +#define KVX_SFR_PSO_VS1_WFXL_SET _ULL(0xc000000000000000) + +#define KVX_SFR_PSO_V64_MASK _ULL(0x300000000) /* Virtual 64 bits mode owner */ +#define KVX_SFR_PSO_V64_SHIFT 32 +#define KVX_SFR_PSO_V64_WIDTH 2 +#define KVX_SFR_PSO_V64_WFXM_MASK _ULL(0x300000000) +#define KVX_SFR_PSO_V64_WFXM_CLEAR _ULL(0x3) +#define KVX_SFR_PSO_V64_WFXM_SET _ULL(0x300000000) + +#define KVX_SFR_PSO_L2E_MASK _ULL(0xc00000000) /* L2 cache Enable owner */ +#define KVX_SFR_PSO_L2E_SHIFT 34 +#define KVX_SFR_PSO_L2E_WIDTH 2 +#define KVX_SFR_PSO_L2E_WFXM_MASK _ULL(0xc00000000) +#define KVX_SFR_PSO_L2E_WFXM_CLEAR _ULL(0xc) +#define KVX_SFR_PSO_L2E_WFXM_SET _ULL(0xc00000000) + +#define KVX_SFR_PSO_SME_MASK _ULL(0x3000000000) /* Step Mode Enabled owner */ +#define KVX_SFR_PSO_SME_SHIFT 36 +#define KVX_SFR_PSO_SME_WIDTH 2 +#define KVX_SFR_PSO_SME_WFXM_MASK _ULL(0x3000000000) +#define KVX_SFR_PSO_SME_WFXM_CLEAR _ULL(0x30) +#define KVX_SFR_PSO_SME_WFXM_SET _ULL(0x3000000000) + +#define KVX_SFR_PSO_SMR_MASK _ULL(0xc000000000) /* Step Mode Ready owner */ +#define KVX_SFR_PSO_SMR_SHIFT 38 +#define KVX_SFR_PSO_SMR_WIDTH 2 +#define KVX_SFR_PSO_SMR_WFXM_MASK _ULL(0xc000000000) +#define KVX_SFR_PSO_SMR_WFXM_CLEAR _ULL(0xc0) +#define KVX_SFR_PSO_SMR_WFXM_SET _ULL(0xc000000000) + +#define KVX_SFR_PSO_PMJ0_MASK _ULL(0x30000000000) /* Page Mask in JTLB bit 0 owner */ +#define KVX_SFR_PSO_PMJ0_SHIFT 40 +#define KVX_SFR_PSO_PMJ0_WIDTH 2 +#define KVX_SFR_PSO_PMJ0_WFXM_MASK _ULL(0x30000000000) +#define KVX_SFR_PSO_PMJ0_WFXM_CLEAR _ULL(0x300) +#define KVX_SFR_PSO_PMJ0_WFXM_SET _ULL(0x30000000000) + +#define KVX_SFR_PSO_PMJ1_MASK _ULL(0xc0000000000) /* Page Mask in JTLB bit 1 owner */ +#define KVX_SFR_PSO_PMJ1_SHIFT 42 +#define KVX_SFR_PSO_PMJ1_WIDTH 2 +#define KVX_SFR_PSO_PMJ1_WFXM_MASK _ULL(0xc0000000000) +#define KVX_SFR_PSO_PMJ1_WFXM_CLEAR _ULL(0xc00) +#define KVX_SFR_PSO_PMJ1_WFXM_SET _ULL(0xc0000000000) + +#define KVX_SFR_PSO_PMJ2_MASK _ULL(0x300000000000) /* Page Mask in JTLB bit 2 owner */ +#define KVX_SFR_PSO_PMJ2_SHIFT 44 +#define KVX_SFR_PSO_PMJ2_WIDTH 2 +#define KVX_SFR_PSO_PMJ2_WFXM_MASK _ULL(0x300000000000) +#define KVX_SFR_PSO_PMJ2_WFXM_CLEAR _ULL(0x3000) +#define KVX_SFR_PSO_PMJ2_WFXM_SET _ULL(0x300000000000) + +#define KVX_SFR_PSO_PMJ3_MASK _ULL(0xc00000000000) /* Page Mask in JTLB bit 3 owner */ +#define KVX_SFR_PSO_PMJ3_SHIFT 46 +#define KVX_SFR_PSO_PMJ3_WIDTH 2 +#define KVX_SFR_PSO_PMJ3_WFXM_MASK _ULL(0xc00000000000) +#define KVX_SFR_PSO_PMJ3_WFXM_CLEAR _ULL(0xc000) +#define KVX_SFR_PSO_PMJ3_WFXM_SET _ULL(0xc00000000000) + +#define KVX_SFR_PSO_MMUP_MASK _ULL(0x3000000000000) /* Privileged on MMU owner. */ +#define KVX_SFR_PSO_MMUP_SHIFT 48 +#define KVX_SFR_PSO_MMUP_WIDTH 2 +#define KVX_SFR_PSO_MMUP_WFXM_MASK _ULL(0x3000000000000) +#define KVX_SFR_PSO_MMUP_WFXM_CLEAR _ULL(0x30000) +#define KVX_SFR_PSO_MMUP_WFXM_SET _ULL(0x3000000000000) + +#define KVX_SFR_PSOW_PL0_MASK _ULL(0x3) /* Current Privilege Level bit 0 owner */ +#define KVX_SFR_PSOW_PL0_SHIFT 0 +#define KVX_SFR_PSOW_PL0_WIDTH 2 +#define KVX_SFR_PSOW_PL0_WFXL_MASK _ULL(0x3) +#define KVX_SFR_PSOW_PL0_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_PSOW_PL0_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_PSOW_PL1_MASK _ULL(0xc) /* Current Privilege Level bit 1 owner */ +#define KVX_SFR_PSOW_PL1_SHIFT 2 +#define KVX_SFR_PSOW_PL1_WIDTH 2 +#define KVX_SFR_PSOW_PL1_WFXL_MASK _ULL(0xc) +#define KVX_SFR_PSOW_PL1_WFXL_CLEAR _ULL(0xc) +#define KVX_SFR_PSOW_PL1_WFXL_SET _ULL(0xc00000000) + +#define KVX_SFR_PSOW_ET_MASK _ULL(0x30) /* Exception Taken owner */ +#define KVX_SFR_PSOW_ET_SHIFT 4 +#define KVX_SFR_PSOW_ET_WIDTH 2 +#define KVX_SFR_PSOW_ET_WFXL_MASK _ULL(0x30) +#define KVX_SFR_PSOW_ET_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_PSOW_ET_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_PSOW_HTD_MASK _ULL(0xc0) /* Hardware Trap Disable owner */ +#define KVX_SFR_PSOW_HTD_SHIFT 6 +#define KVX_SFR_PSOW_HTD_WIDTH 2 +#define KVX_SFR_PSOW_HTD_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_PSOW_HTD_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_PSOW_HTD_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_PSOW_IE_MASK _ULL(0x300) /* Interrupt Enable owner */ +#define KVX_SFR_PSOW_IE_SHIFT 8 +#define KVX_SFR_PSOW_IE_WIDTH 2 +#define KVX_SFR_PSOW_IE_WFXL_MASK _ULL(0x300) +#define KVX_SFR_PSOW_IE_WFXL_CLEAR _ULL(0x300) +#define KVX_SFR_PSOW_IE_WFXL_SET _ULL(0x30000000000) + +#define KVX_SFR_PSOW_HLE_MASK _ULL(0xc00) /* Hardware Loop Enable owner */ +#define KVX_SFR_PSOW_HLE_SHIFT 10 +#define KVX_SFR_PSOW_HLE_WIDTH 2 +#define KVX_SFR_PSOW_HLE_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_PSOW_HLE_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_PSOW_HLE_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_PSOW_SRE_MASK _ULL(0x3000) /* Software REserved owner */ +#define KVX_SFR_PSOW_SRE_SHIFT 12 +#define KVX_SFR_PSOW_SRE_WIDTH 2 +#define KVX_SFR_PSOW_SRE_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_PSOW_SRE_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_PSOW_SRE_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_PSOW_DAUS_MASK _ULL(0xc000) /* Data Accesses Use SPS settings owner */ +#define KVX_SFR_PSOW_DAUS_SHIFT 14 +#define KVX_SFR_PSOW_DAUS_WIDTH 2 +#define KVX_SFR_PSOW_DAUS_WFXL_MASK _ULL(0xc000) +#define KVX_SFR_PSOW_DAUS_WFXL_CLEAR _ULL(0xc000) +#define KVX_SFR_PSOW_DAUS_WFXL_SET _ULL(0xc00000000000) + +#define KVX_SFR_PSOW_ICE_MASK _ULL(0x30000) /* Instruction Cache Enable owner */ +#define KVX_SFR_PSOW_ICE_SHIFT 16 +#define KVX_SFR_PSOW_ICE_WIDTH 2 +#define KVX_SFR_PSOW_ICE_WFXL_MASK _ULL(0x30000) +#define KVX_SFR_PSOW_ICE_WFXL_CLEAR _ULL(0x30000) +#define KVX_SFR_PSOW_ICE_WFXL_SET _ULL(0x3000000000000) + +#define KVX_SFR_PSOW_USE_MASK _ULL(0xc0000) /* Uncached Streaming Enable owner */ +#define KVX_SFR_PSOW_USE_SHIFT 18 +#define KVX_SFR_PSOW_USE_WIDTH 2 +#define KVX_SFR_PSOW_USE_WFXL_MASK _ULL(0xc0000) +#define KVX_SFR_PSOW_USE_WFXL_CLEAR _ULL(0xc0000) +#define KVX_SFR_PSOW_USE_WFXL_SET _ULL(0xc000000000000) + +#define KVX_SFR_PSOW_DCE_MASK _ULL(0x300000) /* Data Cache Enable owner */ +#define KVX_SFR_PSOW_DCE_SHIFT 20 +#define KVX_SFR_PSOW_DCE_WIDTH 2 +#define KVX_SFR_PSOW_DCE_WFXL_MASK _ULL(0x300000) +#define KVX_SFR_PSOW_DCE_WFXL_CLEAR _ULL(0x300000) +#define KVX_SFR_PSOW_DCE_WFXL_SET _ULL(0x30000000000000) + +#define KVX_SFR_PSOW_MME_MASK _ULL(0xc00000) /* Memory Management Enable owner */ +#define KVX_SFR_PSOW_MME_SHIFT 22 +#define KVX_SFR_PSOW_MME_WIDTH 2 +#define KVX_SFR_PSOW_MME_WFXL_MASK _ULL(0xc00000) +#define KVX_SFR_PSOW_MME_WFXL_CLEAR _ULL(0xc00000) +#define KVX_SFR_PSOW_MME_WFXL_SET _ULL(0xc0000000000000) + +#define KVX_SFR_PSOW_IL0_MASK _ULL(0x3000000) /* Interrupt Level bit 0 owner */ +#define KVX_SFR_PSOW_IL0_SHIFT 24 +#define KVX_SFR_PSOW_IL0_WIDTH 2 +#define KVX_SFR_PSOW_IL0_WFXL_MASK _ULL(0x3000000) +#define KVX_SFR_PSOW_IL0_WFXL_CLEAR _ULL(0x3000000) +#define KVX_SFR_PSOW_IL0_WFXL_SET _ULL(0x300000000000000) + +#define KVX_SFR_PSOW_IL1_MASK _ULL(0xc000000) /* Interrupt Level bit 1 owner */ +#define KVX_SFR_PSOW_IL1_SHIFT 26 +#define KVX_SFR_PSOW_IL1_WIDTH 2 +#define KVX_SFR_PSOW_IL1_WFXL_MASK _ULL(0xc000000) +#define KVX_SFR_PSOW_IL1_WFXL_CLEAR _ULL(0xc000000) +#define KVX_SFR_PSOW_IL1_WFXL_SET _ULL(0xc00000000000000) + +#define KVX_SFR_PSOW_VS0_MASK _ULL(0x30000000) /* Virtual Space bit 0 owner */ +#define KVX_SFR_PSOW_VS0_SHIFT 28 +#define KVX_SFR_PSOW_VS0_WIDTH 2 +#define KVX_SFR_PSOW_VS0_WFXL_MASK _ULL(0x30000000) +#define KVX_SFR_PSOW_VS0_WFXL_CLEAR _ULL(0x30000000) +#define KVX_SFR_PSOW_VS0_WFXL_SET _ULL(0x3000000000000000) + +#define KVX_SFR_PSOW_VS1_MASK _ULL(0xc0000000) /* Virtual Space bit 1 owner */ +#define KVX_SFR_PSOW_VS1_SHIFT 30 +#define KVX_SFR_PSOW_VS1_WIDTH 2 +#define KVX_SFR_PSOW_VS1_WFXL_MASK _ULL(0xc0000000) +#define KVX_SFR_PSOW_VS1_WFXL_CLEAR _ULL(0xc0000000) +#define KVX_SFR_PSOW_VS1_WFXL_SET _ULL(0xc000000000000000) + +#define KVX_SFR_PSOW_V64_MASK _ULL(0x300000000) /* Virtual 64 bits mode owner */ +#define KVX_SFR_PSOW_V64_SHIFT 32 +#define KVX_SFR_PSOW_V64_WIDTH 2 +#define KVX_SFR_PSOW_V64_WFXM_MASK _ULL(0x300000000) +#define KVX_SFR_PSOW_V64_WFXM_CLEAR _ULL(0x3) +#define KVX_SFR_PSOW_V64_WFXM_SET _ULL(0x300000000) + +#define KVX_SFR_PSOW_L2E_MASK _ULL(0xc00000000) /* L2 cache Enable owner */ +#define KVX_SFR_PSOW_L2E_SHIFT 34 +#define KVX_SFR_PSOW_L2E_WIDTH 2 +#define KVX_SFR_PSOW_L2E_WFXM_MASK _ULL(0xc00000000) +#define KVX_SFR_PSOW_L2E_WFXM_CLEAR _ULL(0xc) +#define KVX_SFR_PSOW_L2E_WFXM_SET _ULL(0xc00000000) + +#define KVX_SFR_PSOW_SME_MASK _ULL(0x3000000000) /* Step Mode Enabled owner */ +#define KVX_SFR_PSOW_SME_SHIFT 36 +#define KVX_SFR_PSOW_SME_WIDTH 2 +#define KVX_SFR_PSOW_SME_WFXM_MASK _ULL(0x3000000000) +#define KVX_SFR_PSOW_SME_WFXM_CLEAR _ULL(0x30) +#define KVX_SFR_PSOW_SME_WFXM_SET _ULL(0x3000000000) + +#define KVX_SFR_PSOW_SMR_MASK _ULL(0xc000000000) /* Step Mode Ready owner */ +#define KVX_SFR_PSOW_SMR_SHIFT 38 +#define KVX_SFR_PSOW_SMR_WIDTH 2 +#define KVX_SFR_PSOW_SMR_WFXM_MASK _ULL(0xc000000000) +#define KVX_SFR_PSOW_SMR_WFXM_CLEAR _ULL(0xc0) +#define KVX_SFR_PSOW_SMR_WFXM_SET _ULL(0xc000000000) + +#define KVX_SFR_PSOW_PMJ0_MASK _ULL(0x30000000000) /* Page Mask in JTLB bit 0 owner */ +#define KVX_SFR_PSOW_PMJ0_SHIFT 40 +#define KVX_SFR_PSOW_PMJ0_WIDTH 2 +#define KVX_SFR_PSOW_PMJ0_WFXM_MASK _ULL(0x30000000000) +#define KVX_SFR_PSOW_PMJ0_WFXM_CLEAR _ULL(0x300) +#define KVX_SFR_PSOW_PMJ0_WFXM_SET _ULL(0x30000000000) + +#define KVX_SFR_PSOW_PMJ1_MASK _ULL(0xc0000000000) /* Page Mask in JTLB bit 1 owner */ +#define KVX_SFR_PSOW_PMJ1_SHIFT 42 +#define KVX_SFR_PSOW_PMJ1_WIDTH 2 +#define KVX_SFR_PSOW_PMJ1_WFXM_MASK _ULL(0xc0000000000) +#define KVX_SFR_PSOW_PMJ1_WFXM_CLEAR _ULL(0xc00) +#define KVX_SFR_PSOW_PMJ1_WFXM_SET _ULL(0xc0000000000) + +#define KVX_SFR_PSOW_PMJ2_MASK _ULL(0x300000000000) /* Page Mask in JTLB bit 2 owner */ +#define KVX_SFR_PSOW_PMJ2_SHIFT 44 +#define KVX_SFR_PSOW_PMJ2_WIDTH 2 +#define KVX_SFR_PSOW_PMJ2_WFXM_MASK _ULL(0x300000000000) +#define KVX_SFR_PSOW_PMJ2_WFXM_CLEAR _ULL(0x3000) +#define KVX_SFR_PSOW_PMJ2_WFXM_SET _ULL(0x300000000000) + +#define KVX_SFR_PSOW_PMJ3_MASK _ULL(0xc00000000000) /* Page Mask in JTLB bit 3 owner */ +#define KVX_SFR_PSOW_PMJ3_SHIFT 46 +#define KVX_SFR_PSOW_PMJ3_WIDTH 2 +#define KVX_SFR_PSOW_PMJ3_WFXM_MASK _ULL(0xc00000000000) +#define KVX_SFR_PSOW_PMJ3_WFXM_CLEAR _ULL(0xc000) +#define KVX_SFR_PSOW_PMJ3_WFXM_SET _ULL(0xc00000000000) + +#define KVX_SFR_PSOW_MMUP_MASK _ULL(0x3000000000000) /* Privileged on MMU owner. */ +#define KVX_SFR_PSOW_MMUP_SHIFT 48 +#define KVX_SFR_PSOW_MMUP_WIDTH 2 +#define KVX_SFR_PSOW_MMUP_WFXM_MASK _ULL(0x3000000000000) +#define KVX_SFR_PSOW_MMUP_WFXM_CLEAR _ULL(0x30000) +#define KVX_SFR_PSOW_MMUP_WFXM_SET _ULL(0x3000000000000) + +#define KVX_SFR_CS_IC_MASK _ULL(0x1) /* Integer Carry */ +#define KVX_SFR_CS_IC_SHIFT 0 +#define KVX_SFR_CS_IC_WIDTH 1 +#define KVX_SFR_CS_IC_WFXL_MASK _ULL(0x1) +#define KVX_SFR_CS_IC_WFXL_CLEAR _ULL(0x1) +#define KVX_SFR_CS_IC_WFXL_SET _ULL(0x100000000) + +#define KVX_SFR_CS_IO_MASK _ULL(0x2) /* IEEE 754 Invalid Operation */ +#define KVX_SFR_CS_IO_SHIFT 1 +#define KVX_SFR_CS_IO_WIDTH 1 +#define KVX_SFR_CS_IO_WFXL_MASK _ULL(0x2) +#define KVX_SFR_CS_IO_WFXL_CLEAR _ULL(0x2) +#define KVX_SFR_CS_IO_WFXL_SET _ULL(0x200000000) + +#define KVX_SFR_CS_DZ_MASK _ULL(0x4) /* IEEE 754 Divide by Zero */ +#define KVX_SFR_CS_DZ_SHIFT 2 +#define KVX_SFR_CS_DZ_WIDTH 1 +#define KVX_SFR_CS_DZ_WFXL_MASK _ULL(0x4) +#define KVX_SFR_CS_DZ_WFXL_CLEAR _ULL(0x4) +#define KVX_SFR_CS_DZ_WFXL_SET _ULL(0x400000000) + +#define KVX_SFR_CS_OV_MASK _ULL(0x8) /* IEEE 754 Overflow */ +#define KVX_SFR_CS_OV_SHIFT 3 +#define KVX_SFR_CS_OV_WIDTH 1 +#define KVX_SFR_CS_OV_WFXL_MASK _ULL(0x8) +#define KVX_SFR_CS_OV_WFXL_CLEAR _ULL(0x8) +#define KVX_SFR_CS_OV_WFXL_SET _ULL(0x800000000) + +#define KVX_SFR_CS_UN_MASK _ULL(0x10) /* IEEE 754 Underflow */ +#define KVX_SFR_CS_UN_SHIFT 4 +#define KVX_SFR_CS_UN_WIDTH 1 +#define KVX_SFR_CS_UN_WFXL_MASK _ULL(0x10) +#define KVX_SFR_CS_UN_WFXL_CLEAR _ULL(0x10) +#define KVX_SFR_CS_UN_WFXL_SET _ULL(0x1000000000) + +#define KVX_SFR_CS_IN_MASK _ULL(0x20) /* IEEE 754 Inexact */ +#define KVX_SFR_CS_IN_SHIFT 5 +#define KVX_SFR_CS_IN_WIDTH 1 +#define KVX_SFR_CS_IN_WFXL_MASK _ULL(0x20) +#define KVX_SFR_CS_IN_WFXL_CLEAR _ULL(0x20) +#define KVX_SFR_CS_IN_WFXL_SET _ULL(0x2000000000) + +#define KVX_SFR_CS_XIO_MASK _ULL(0x200) /* Extension IEEE 754 Invalid Operation */ +#define KVX_SFR_CS_XIO_SHIFT 9 +#define KVX_SFR_CS_XIO_WIDTH 1 +#define KVX_SFR_CS_XIO_WFXL_MASK _ULL(0x200) +#define KVX_SFR_CS_XIO_WFXL_CLEAR _ULL(0x200) +#define KVX_SFR_CS_XIO_WFXL_SET _ULL(0x20000000000) + +#define KVX_SFR_CS_XDZ_MASK _ULL(0x400) /* Extension IEEE 754 Divide by Zero */ +#define KVX_SFR_CS_XDZ_SHIFT 10 +#define KVX_SFR_CS_XDZ_WIDTH 1 +#define KVX_SFR_CS_XDZ_WFXL_MASK _ULL(0x400) +#define KVX_SFR_CS_XDZ_WFXL_CLEAR _ULL(0x400) +#define KVX_SFR_CS_XDZ_WFXL_SET _ULL(0x40000000000) + +#define KVX_SFR_CS_XOV_MASK _ULL(0x800) /* Extension IEEE 754 Overflow */ +#define KVX_SFR_CS_XOV_SHIFT 11 +#define KVX_SFR_CS_XOV_WIDTH 1 +#define KVX_SFR_CS_XOV_WFXL_MASK _ULL(0x800) +#define KVX_SFR_CS_XOV_WFXL_CLEAR _ULL(0x800) +#define KVX_SFR_CS_XOV_WFXL_SET _ULL(0x80000000000) + +#define KVX_SFR_CS_XUN_MASK _ULL(0x1000) /* Extension IEEE 754 Underflow */ +#define KVX_SFR_CS_XUN_SHIFT 12 +#define KVX_SFR_CS_XUN_WIDTH 1 +#define KVX_SFR_CS_XUN_WFXL_MASK _ULL(0x1000) +#define KVX_SFR_CS_XUN_WFXL_CLEAR _ULL(0x1000) +#define KVX_SFR_CS_XUN_WFXL_SET _ULL(0x100000000000) + +#define KVX_SFR_CS_XIN_MASK _ULL(0x2000) /* Extension IEEE 754 Inexact */ +#define KVX_SFR_CS_XIN_SHIFT 13 +#define KVX_SFR_CS_XIN_WIDTH 1 +#define KVX_SFR_CS_XIN_WFXL_MASK _ULL(0x2000) +#define KVX_SFR_CS_XIN_WFXL_CLEAR _ULL(0x2000) +#define KVX_SFR_CS_XIN_WFXL_SET _ULL(0x200000000000) + +#define KVX_SFR_CS_RM_MASK _ULL(0x30000) /* IEEE 754 Rounding Mode */ +#define KVX_SFR_CS_RM_SHIFT 16 +#define KVX_SFR_CS_RM_WIDTH 2 +#define KVX_SFR_CS_RM_WFXL_MASK _ULL(0x30000) +#define KVX_SFR_CS_RM_WFXL_CLEAR _ULL(0x30000) +#define KVX_SFR_CS_RM_WFXL_SET _ULL(0x3000000000000) + +#define KVX_SFR_CS_XRM_MASK _ULL(0x300000) /* Extension IEEE 754 Rounding Mode */ +#define KVX_SFR_CS_XRM_SHIFT 20 +#define KVX_SFR_CS_XRM_WIDTH 2 +#define KVX_SFR_CS_XRM_WFXL_MASK _ULL(0x300000) +#define KVX_SFR_CS_XRM_WFXL_CLEAR _ULL(0x300000) +#define KVX_SFR_CS_XRM_WFXL_SET _ULL(0x30000000000000) + +#define KVX_SFR_CS_XMF_MASK _ULL(0x1000000) /* eXtension ModiFied */ +#define KVX_SFR_CS_XMF_SHIFT 24 +#define KVX_SFR_CS_XMF_WIDTH 1 +#define KVX_SFR_CS_XMF_WFXL_MASK _ULL(0x1000000) +#define KVX_SFR_CS_XMF_WFXL_CLEAR _ULL(0x1000000) +#define KVX_SFR_CS_XMF_WFXL_SET _ULL(0x100000000000000) + +#define KVX_SFR_CS_CC_MASK _ULL(0xffff00000000) /* Carry Counter */ +#define KVX_SFR_CS_CC_SHIFT 32 +#define KVX_SFR_CS_CC_WIDTH 16 +#define KVX_SFR_CS_CC_WFXM_MASK _ULL(0xffff00000000) +#define KVX_SFR_CS_CC_WFXM_CLEAR _ULL(0xffff) +#define KVX_SFR_CS_CC_WFXM_SET _ULL(0xffff00000000) + +#define KVX_SFR_CS_XDROP_MASK _ULL(0x3f000000000000) /* Extension Conversion Drop Bits */ +#define KVX_SFR_CS_XDROP_SHIFT 48 +#define KVX_SFR_CS_XDROP_WIDTH 6 +#define KVX_SFR_CS_XDROP_WFXM_MASK _ULL(0x3f000000000000) +#define KVX_SFR_CS_XDROP_WFXM_CLEAR _ULL(0x3f0000) +#define KVX_SFR_CS_XDROP_WFXM_SET _ULL(0x3f000000000000) + +#define KVX_SFR_CS_XPOW2_MASK _ULL(0xfc0000000000000) /* Extension FScale Power of Two */ +#define KVX_SFR_CS_XPOW2_SHIFT 54 +#define KVX_SFR_CS_XPOW2_WIDTH 6 +#define KVX_SFR_CS_XPOW2_WFXM_MASK _ULL(0xfc0000000000000) +#define KVX_SFR_CS_XPOW2_WFXM_CLEAR _ULL(0xfc00000) +#define KVX_SFR_CS_XPOW2_WFXM_SET _ULL(0xfc0000000000000) + +#define KVX_SFR_AESPC_AESPC_MASK _ULL(0xffffffffffffffff) /* Arithmetic Exception Saved PC */ +#define KVX_SFR_AESPC_AESPC_SHIFT 0 +#define KVX_SFR_AESPC_AESPC_WIDTH 64 +#define KVX_SFR_AESPC_AESPC_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_AESPC_AESPC_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_AESPC_AESPC_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_AESPC_AESPC_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_AESPC_AESPC_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_AESPC_AESPC_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_CSIT_ICIE_MASK _ULL(0x1) /* Integer Carry Interrupt Enable */ +#define KVX_SFR_CSIT_ICIE_SHIFT 0 +#define KVX_SFR_CSIT_ICIE_WIDTH 1 +#define KVX_SFR_CSIT_ICIE_WFXL_MASK _ULL(0x1) +#define KVX_SFR_CSIT_ICIE_WFXL_CLEAR _ULL(0x1) +#define KVX_SFR_CSIT_ICIE_WFXL_SET _ULL(0x100000000) + +#define KVX_SFR_CSIT_IOIE_MASK _ULL(0x2) /* IEEE 754 Invalid Operation Interrupt Enable */ +#define KVX_SFR_CSIT_IOIE_SHIFT 1 +#define KVX_SFR_CSIT_IOIE_WIDTH 1 +#define KVX_SFR_CSIT_IOIE_WFXL_MASK _ULL(0x2) +#define KVX_SFR_CSIT_IOIE_WFXL_CLEAR _ULL(0x2) +#define KVX_SFR_CSIT_IOIE_WFXL_SET _ULL(0x200000000) + +#define KVX_SFR_CSIT_DZIE_MASK _ULL(0x4) /* IEEE 754 Divide by Zero Interrupt Enable */ +#define KVX_SFR_CSIT_DZIE_SHIFT 2 +#define KVX_SFR_CSIT_DZIE_WIDTH 1 +#define KVX_SFR_CSIT_DZIE_WFXL_MASK _ULL(0x4) +#define KVX_SFR_CSIT_DZIE_WFXL_CLEAR _ULL(0x4) +#define KVX_SFR_CSIT_DZIE_WFXL_SET _ULL(0x400000000) + +#define KVX_SFR_CSIT_OVIE_MASK _ULL(0x8) /* IEEE 754 Overflow Interrupt Enable */ +#define KVX_SFR_CSIT_OVIE_SHIFT 3 +#define KVX_SFR_CSIT_OVIE_WIDTH 1 +#define KVX_SFR_CSIT_OVIE_WFXL_MASK _ULL(0x8) +#define KVX_SFR_CSIT_OVIE_WFXL_CLEAR _ULL(0x8) +#define KVX_SFR_CSIT_OVIE_WFXL_SET _ULL(0x800000000) + +#define KVX_SFR_CSIT_UNIE_MASK _ULL(0x10) /* IEEE 754 Underflow Interrupt Enable */ +#define KVX_SFR_CSIT_UNIE_SHIFT 4 +#define KVX_SFR_CSIT_UNIE_WIDTH 1 +#define KVX_SFR_CSIT_UNIE_WFXL_MASK _ULL(0x10) +#define KVX_SFR_CSIT_UNIE_WFXL_CLEAR _ULL(0x10) +#define KVX_SFR_CSIT_UNIE_WFXL_SET _ULL(0x1000000000) + +#define KVX_SFR_CSIT_INIE_MASK _ULL(0x20) /* IEEE 754 Inexact Interrupt Enable */ +#define KVX_SFR_CSIT_INIE_SHIFT 5 +#define KVX_SFR_CSIT_INIE_WIDTH 1 +#define KVX_SFR_CSIT_INIE_WFXL_MASK _ULL(0x20) +#define KVX_SFR_CSIT_INIE_WFXL_CLEAR _ULL(0x20) +#define KVX_SFR_CSIT_INIE_WFXL_SET _ULL(0x2000000000) + +#define KVX_SFR_CSIT_XIOIE_MASK _ULL(0x200) /* Extension IEEE 754 Invalid Operation Interrupt Enable */ +#define KVX_SFR_CSIT_XIOIE_SHIFT 9 +#define KVX_SFR_CSIT_XIOIE_WIDTH 1 +#define KVX_SFR_CSIT_XIOIE_WFXL_MASK _ULL(0x200) +#define KVX_SFR_CSIT_XIOIE_WFXL_CLEAR _ULL(0x200) +#define KVX_SFR_CSIT_XIOIE_WFXL_SET _ULL(0x20000000000) + +#define KVX_SFR_CSIT_XDZIE_MASK _ULL(0x400) /* Extension IEEE 754 Divide by Zero Interrupt Enable */ +#define KVX_SFR_CSIT_XDZIE_SHIFT 10 +#define KVX_SFR_CSIT_XDZIE_WIDTH 1 +#define KVX_SFR_CSIT_XDZIE_WFXL_MASK _ULL(0x400) +#define KVX_SFR_CSIT_XDZIE_WFXL_CLEAR _ULL(0x400) +#define KVX_SFR_CSIT_XDZIE_WFXL_SET _ULL(0x40000000000) + +#define KVX_SFR_CSIT_XOVIE_MASK _ULL(0x800) /* Extension IEEE 754 Overflow Interrupt Enable */ +#define KVX_SFR_CSIT_XOVIE_SHIFT 11 +#define KVX_SFR_CSIT_XOVIE_WIDTH 1 +#define KVX_SFR_CSIT_XOVIE_WFXL_MASK _ULL(0x800) +#define KVX_SFR_CSIT_XOVIE_WFXL_CLEAR _ULL(0x800) +#define KVX_SFR_CSIT_XOVIE_WFXL_SET _ULL(0x80000000000) + +#define KVX_SFR_CSIT_XUNIE_MASK _ULL(0x1000) /* Extension IEEE 754 Underflow Interrupt Enable */ +#define KVX_SFR_CSIT_XUNIE_SHIFT 12 +#define KVX_SFR_CSIT_XUNIE_WIDTH 1 +#define KVX_SFR_CSIT_XUNIE_WFXL_MASK _ULL(0x1000) +#define KVX_SFR_CSIT_XUNIE_WFXL_CLEAR _ULL(0x1000) +#define KVX_SFR_CSIT_XUNIE_WFXL_SET _ULL(0x100000000000) + +#define KVX_SFR_CSIT_XINIE_MASK _ULL(0x2000) /* Extension IEEE 754 Inexact Interrupt Enable */ +#define KVX_SFR_CSIT_XINIE_SHIFT 13 +#define KVX_SFR_CSIT_XINIE_WIDTH 1 +#define KVX_SFR_CSIT_XINIE_WFXL_MASK _ULL(0x2000) +#define KVX_SFR_CSIT_XINIE_WFXL_CLEAR _ULL(0x2000) +#define KVX_SFR_CSIT_XINIE_WFXL_SET _ULL(0x200000000000) + +#define KVX_SFR_CSIT_AEIR_MASK _ULL(0x10000) /* Arithmetic Exception Interrupt Raised */ +#define KVX_SFR_CSIT_AEIR_SHIFT 16 +#define KVX_SFR_CSIT_AEIR_WIDTH 1 +#define KVX_SFR_CSIT_AEIR_WFXL_MASK _ULL(0x10000) +#define KVX_SFR_CSIT_AEIR_WFXL_CLEAR _ULL(0x10000) +#define KVX_SFR_CSIT_AEIR_WFXL_SET _ULL(0x1000000000000) + +#define KVX_SFR_CSIT_AEC_MASK _ULL(0xe0000) /* Arithmetic Exception Code */ +#define KVX_SFR_CSIT_AEC_SHIFT 17 +#define KVX_SFR_CSIT_AEC_WIDTH 3 +#define KVX_SFR_CSIT_AEC_WFXL_MASK _ULL(0xe0000) +#define KVX_SFR_CSIT_AEC_WFXL_CLEAR _ULL(0xe0000) +#define KVX_SFR_CSIT_AEC_WFXL_SET _ULL(0xe000000000000) + +#define KVX_SFR_CSIT_SPCV_MASK _ULL(0x100000) /* SPC Valid */ +#define KVX_SFR_CSIT_SPCV_SHIFT 20 +#define KVX_SFR_CSIT_SPCV_WIDTH 1 +#define KVX_SFR_CSIT_SPCV_WFXL_MASK _ULL(0x100000) +#define KVX_SFR_CSIT_SPCV_WFXL_CLEAR _ULL(0x100000) +#define KVX_SFR_CSIT_SPCV_WFXL_SET _ULL(0x10000000000000) + +#define KVX_SFR_ES_EC_MASK _ULL(0xf) /* Exception Class */ +#define KVX_SFR_ES_EC_SHIFT 0 +#define KVX_SFR_ES_EC_WIDTH 4 +#define KVX_SFR_ES_EC_WFXL_MASK _ULL(0xf) +#define KVX_SFR_ES_EC_WFXL_CLEAR _ULL(0xf) +#define KVX_SFR_ES_EC_WFXL_SET _ULL(0xf00000000) + +#define KVX_SFR_ES_ED_MASK _ULL(0xfffffffffffffff0) /* Exception Details */ +#define KVX_SFR_ES_ED_SHIFT 4 +#define KVX_SFR_ES_ED_WIDTH 60 +#define KVX_SFR_ES_ED_WFXL_MASK _ULL(0xfffffff0) +#define KVX_SFR_ES_ED_WFXL_CLEAR _ULL(0xfffffff0) +#define KVX_SFR_ES_ED_WFXL_SET _ULL(0xfffffff000000000) +#define KVX_SFR_ES_ED_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_ES_ED_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_ES_ED_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_ES_OAPL_MASK _ULL(0x30) /* Origin Absolute PL */ +#define KVX_SFR_ES_OAPL_SHIFT 4 +#define KVX_SFR_ES_OAPL_WIDTH 2 +#define KVX_SFR_ES_OAPL_WFXL_MASK _ULL(0x30) +#define KVX_SFR_ES_OAPL_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_ES_OAPL_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_ES_ORPL_MASK _ULL(0xc0) /* Origin Relative PL */ +#define KVX_SFR_ES_ORPL_SHIFT 6 +#define KVX_SFR_ES_ORPL_WIDTH 2 +#define KVX_SFR_ES_ORPL_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_ES_ORPL_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_ES_ORPL_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_ES_PTAPL_MASK _ULL(0x300) /* Primary Target Absolute PL */ +#define KVX_SFR_ES_PTAPL_SHIFT 8 +#define KVX_SFR_ES_PTAPL_WIDTH 2 +#define KVX_SFR_ES_PTAPL_WFXL_MASK _ULL(0x300) +#define KVX_SFR_ES_PTAPL_WFXL_CLEAR _ULL(0x300) +#define KVX_SFR_ES_PTAPL_WFXL_SET _ULL(0x30000000000) + +#define KVX_SFR_ES_PTRPL_MASK _ULL(0xc00) /* Primary Target Relative PL */ +#define KVX_SFR_ES_PTRPL_SHIFT 10 +#define KVX_SFR_ES_PTRPL_WIDTH 2 +#define KVX_SFR_ES_PTRPL_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_ES_PTRPL_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_ES_PTRPL_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_ES_ITN_MASK _ULL(0x1f000) /* InTerrupt Number */ +#define KVX_SFR_ES_ITN_SHIFT 12 +#define KVX_SFR_ES_ITN_WIDTH 5 +#define KVX_SFR_ES_ITN_WFXL_MASK _ULL(0x1f000) +#define KVX_SFR_ES_ITN_WFXL_CLEAR _ULL(0x1f000) +#define KVX_SFR_ES_ITN_WFXL_SET _ULL(0x1f00000000000) + +#define KVX_SFR_ES_ITL_MASK _ULL(0x60000) /* InTerrupt Level */ +#define KVX_SFR_ES_ITL_SHIFT 17 +#define KVX_SFR_ES_ITL_WIDTH 2 +#define KVX_SFR_ES_ITL_WFXL_MASK _ULL(0x60000) +#define KVX_SFR_ES_ITL_WFXL_CLEAR _ULL(0x60000) +#define KVX_SFR_ES_ITL_WFXL_SET _ULL(0x6000000000000) + +#define KVX_SFR_ES_ITI_MASK _ULL(0x1ff80000) /* InTerrupt Info */ +#define KVX_SFR_ES_ITI_SHIFT 19 +#define KVX_SFR_ES_ITI_WIDTH 10 +#define KVX_SFR_ES_ITI_WFXL_MASK _ULL(0x1ff80000) +#define KVX_SFR_ES_ITI_WFXL_CLEAR _ULL(0x1ff80000) +#define KVX_SFR_ES_ITI_WFXL_SET _ULL(0x1ff8000000000000) + +#define KVX_SFR_ES_SN_MASK _ULL(0xfff000) /* Syscall Number */ +#define KVX_SFR_ES_SN_SHIFT 12 +#define KVX_SFR_ES_SN_WIDTH 12 +#define KVX_SFR_ES_SN_WFXL_MASK _ULL(0xfff000) +#define KVX_SFR_ES_SN_WFXL_CLEAR _ULL(0xfff000) +#define KVX_SFR_ES_SN_WFXL_SET _ULL(0xfff00000000000) + +#define KVX_SFR_ES_HTC_MASK _ULL(0x1f000) /* Hardware Trap Cause */ +#define KVX_SFR_ES_HTC_SHIFT 12 +#define KVX_SFR_ES_HTC_WIDTH 5 +#define KVX_SFR_ES_HTC_WFXL_MASK _ULL(0x1f000) +#define KVX_SFR_ES_HTC_WFXL_CLEAR _ULL(0x1f000) +#define KVX_SFR_ES_HTC_WFXL_SET _ULL(0x1f00000000000) + +#define KVX_SFR_ES_SFRT_MASK _ULL(0x20000) /* SFR Trap */ +#define KVX_SFR_ES_SFRT_SHIFT 17 +#define KVX_SFR_ES_SFRT_WIDTH 1 +#define KVX_SFR_ES_SFRT_WFXL_MASK _ULL(0x20000) +#define KVX_SFR_ES_SFRT_WFXL_CLEAR _ULL(0x20000) +#define KVX_SFR_ES_SFRT_WFXL_SET _ULL(0x2000000000000) + +#define KVX_SFR_ES_SFRI_MASK _ULL(0x1c0000) /* SFR Instruction */ +#define KVX_SFR_ES_SFRI_SHIFT 18 +#define KVX_SFR_ES_SFRI_WIDTH 3 +#define KVX_SFR_ES_SFRI_WFXL_MASK _ULL(0x1c0000) +#define KVX_SFR_ES_SFRI_WFXL_CLEAR _ULL(0x1c0000) +#define KVX_SFR_ES_SFRI_WFXL_SET _ULL(0x1c000000000000) + +#define KVX_SFR_ES_GPRP_MASK _ULL(0x7e00000) /* GPR Pointer */ +#define KVX_SFR_ES_GPRP_SHIFT 21 +#define KVX_SFR_ES_GPRP_WIDTH 6 +#define KVX_SFR_ES_GPRP_WFXL_MASK _ULL(0x7e00000) +#define KVX_SFR_ES_GPRP_WFXL_CLEAR _ULL(0x7e00000) +#define KVX_SFR_ES_GPRP_WFXL_SET _ULL(0x7e0000000000000) + +#define KVX_SFR_ES_SFRP_MASK _ULL(0xff8000000) /* SFR Pointer */ +#define KVX_SFR_ES_SFRP_SHIFT 27 +#define KVX_SFR_ES_SFRP_WIDTH 9 +#define KVX_SFR_ES_SFRP_WFXL_MASK _ULL(0xf8000000) +#define KVX_SFR_ES_SFRP_WFXL_CLEAR _ULL(0xf8000000) +#define KVX_SFR_ES_SFRP_WFXL_SET _ULL(0xf800000000000000) +#define KVX_SFR_ES_SFRP_WFXM_MASK _ULL(0xf00000000) +#define KVX_SFR_ES_SFRP_WFXM_CLEAR _ULL(0xf) +#define KVX_SFR_ES_SFRP_WFXM_SET _ULL(0xf00000000) + +#define KVX_SFR_ES_DHT_MASK _ULL(0x1000000000) /* Disabled Hardware Trap */ +#define KVX_SFR_ES_DHT_SHIFT 36 +#define KVX_SFR_ES_DHT_WIDTH 1 +#define KVX_SFR_ES_DHT_WFXM_MASK _ULL(0x1000000000) +#define KVX_SFR_ES_DHT_WFXM_CLEAR _ULL(0x10) +#define KVX_SFR_ES_DHT_WFXM_SET _ULL(0x1000000000) + +#define KVX_SFR_ES_RWX_MASK _ULL(0x38000000000) /* Read Write Execute */ +#define KVX_SFR_ES_RWX_SHIFT 39 +#define KVX_SFR_ES_RWX_WIDTH 3 +#define KVX_SFR_ES_RWX_WFXM_MASK _ULL(0x38000000000) +#define KVX_SFR_ES_RWX_WFXM_CLEAR _ULL(0x380) +#define KVX_SFR_ES_RWX_WFXM_SET _ULL(0x38000000000) + +#define KVX_SFR_ES_NTA_MASK _ULL(0x40000000000) /* Non-Trapping Access */ +#define KVX_SFR_ES_NTA_SHIFT 42 +#define KVX_SFR_ES_NTA_WIDTH 1 +#define KVX_SFR_ES_NTA_WFXM_MASK _ULL(0x40000000000) +#define KVX_SFR_ES_NTA_WFXM_CLEAR _ULL(0x400) +#define KVX_SFR_ES_NTA_WFXM_SET _ULL(0x40000000000) + +#define KVX_SFR_ES_UCA_MASK _ULL(0x80000000000) /* Un-Cached Access */ +#define KVX_SFR_ES_UCA_SHIFT 43 +#define KVX_SFR_ES_UCA_WIDTH 1 +#define KVX_SFR_ES_UCA_WFXM_MASK _ULL(0x80000000000) +#define KVX_SFR_ES_UCA_WFXM_CLEAR _ULL(0x800) +#define KVX_SFR_ES_UCA_WFXM_SET _ULL(0x80000000000) + +#define KVX_SFR_ES_AS_MASK _ULL(0x3f00000000000) /* Access Size */ +#define KVX_SFR_ES_AS_SHIFT 44 +#define KVX_SFR_ES_AS_WIDTH 6 +#define KVX_SFR_ES_AS_WFXM_MASK _ULL(0x3f00000000000) +#define KVX_SFR_ES_AS_WFXM_CLEAR _ULL(0x3f000) +#define KVX_SFR_ES_AS_WFXM_SET _ULL(0x3f00000000000) + +#define KVX_SFR_ES_BS_MASK _ULL(0x3c000000000000) /* Bundle Size */ +#define KVX_SFR_ES_BS_SHIFT 50 +#define KVX_SFR_ES_BS_WIDTH 4 +#define KVX_SFR_ES_BS_WFXM_MASK _ULL(0x3c000000000000) +#define KVX_SFR_ES_BS_WFXM_CLEAR _ULL(0x3c0000) +#define KVX_SFR_ES_BS_WFXM_SET _ULL(0x3c000000000000) + +#define KVX_SFR_ES_DRI_MASK _ULL(0xfc0000000000000) /* Data Register Index */ +#define KVX_SFR_ES_DRI_SHIFT 54 +#define KVX_SFR_ES_DRI_WIDTH 6 +#define KVX_SFR_ES_DRI_WFXM_MASK _ULL(0xfc0000000000000) +#define KVX_SFR_ES_DRI_WFXM_CLEAR _ULL(0xfc00000) +#define KVX_SFR_ES_DRI_WFXM_SET _ULL(0xfc0000000000000) + +#define KVX_SFR_ES_PIC_MASK _ULL(0xf000000000000000) /* Privileged Instruction Code */ +#define KVX_SFR_ES_PIC_SHIFT 60 +#define KVX_SFR_ES_PIC_WIDTH 4 +#define KVX_SFR_ES_PIC_WFXM_MASK _ULL(0xf000000000000000) +#define KVX_SFR_ES_PIC_WFXM_CLEAR _ULL(0xf0000000) +#define KVX_SFR_ES_PIC_WFXM_SET _ULL(0xf000000000000000) + +#define KVX_SFR_ES_DC_MASK _ULL(0x3000) /* Debug Cause */ +#define KVX_SFR_ES_DC_SHIFT 12 +#define KVX_SFR_ES_DC_WIDTH 2 +#define KVX_SFR_ES_DC_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_ES_DC_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_ES_DC_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_ES_BN_MASK _ULL(0x4000) /* Breakpoint Number */ +#define KVX_SFR_ES_BN_SHIFT 14 +#define KVX_SFR_ES_BN_WIDTH 1 +#define KVX_SFR_ES_BN_WFXL_MASK _ULL(0x4000) +#define KVX_SFR_ES_BN_WFXL_CLEAR _ULL(0x4000) +#define KVX_SFR_ES_BN_WFXL_SET _ULL(0x400000000000) + +#define KVX_SFR_ES_WN_MASK _ULL(0x8000) /* Watchpoint Number */ +#define KVX_SFR_ES_WN_SHIFT 15 +#define KVX_SFR_ES_WN_WIDTH 1 +#define KVX_SFR_ES_WN_WFXL_MASK _ULL(0x8000) +#define KVX_SFR_ES_WN_WFXL_CLEAR _ULL(0x8000) +#define KVX_SFR_ES_WN_WFXL_SET _ULL(0x800000000000) + +#define KVX_SFR_ES_PL0_EC_MASK _ULL(0xf) /* Exception Class */ +#define KVX_SFR_ES_PL0_EC_SHIFT 0 +#define KVX_SFR_ES_PL0_EC_WIDTH 4 +#define KVX_SFR_ES_PL0_EC_WFXL_MASK _ULL(0xf) +#define KVX_SFR_ES_PL0_EC_WFXL_CLEAR _ULL(0xf) +#define KVX_SFR_ES_PL0_EC_WFXL_SET _ULL(0xf00000000) + +#define KVX_SFR_ES_PL0_ED_MASK _ULL(0xfffffffffffffff0) /* Exception Details */ +#define KVX_SFR_ES_PL0_ED_SHIFT 4 +#define KVX_SFR_ES_PL0_ED_WIDTH 60 +#define KVX_SFR_ES_PL0_ED_WFXL_MASK _ULL(0xfffffff0) +#define KVX_SFR_ES_PL0_ED_WFXL_CLEAR _ULL(0xfffffff0) +#define KVX_SFR_ES_PL0_ED_WFXL_SET _ULL(0xfffffff000000000) +#define KVX_SFR_ES_PL0_ED_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_ES_PL0_ED_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_ES_PL0_ED_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_ES_PL0_OAPL_MASK _ULL(0x30) /* Origin Absolute PL */ +#define KVX_SFR_ES_PL0_OAPL_SHIFT 4 +#define KVX_SFR_ES_PL0_OAPL_WIDTH 2 +#define KVX_SFR_ES_PL0_OAPL_WFXL_MASK _ULL(0x30) +#define KVX_SFR_ES_PL0_OAPL_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_ES_PL0_OAPL_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_ES_PL0_ORPL_MASK _ULL(0xc0) /* Origin Relative PL */ +#define KVX_SFR_ES_PL0_ORPL_SHIFT 6 +#define KVX_SFR_ES_PL0_ORPL_WIDTH 2 +#define KVX_SFR_ES_PL0_ORPL_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_ES_PL0_ORPL_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_ES_PL0_ORPL_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_ES_PL0_PTAPL_MASK _ULL(0x300) /* Target Absolute PL */ +#define KVX_SFR_ES_PL0_PTAPL_SHIFT 8 +#define KVX_SFR_ES_PL0_PTAPL_WIDTH 2 +#define KVX_SFR_ES_PL0_PTAPL_WFXL_MASK _ULL(0x300) +#define KVX_SFR_ES_PL0_PTAPL_WFXL_CLEAR _ULL(0x300) +#define KVX_SFR_ES_PL0_PTAPL_WFXL_SET _ULL(0x30000000000) + +#define KVX_SFR_ES_PL0_PTRPL_MASK _ULL(0xc00) /* Target Relative PL */ +#define KVX_SFR_ES_PL0_PTRPL_SHIFT 10 +#define KVX_SFR_ES_PL0_PTRPL_WIDTH 2 +#define KVX_SFR_ES_PL0_PTRPL_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_ES_PL0_PTRPL_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_ES_PL0_PTRPL_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_ES_PL0_ITN_MASK _ULL(0x1f000) /* InTerrupt Number */ +#define KVX_SFR_ES_PL0_ITN_SHIFT 12 +#define KVX_SFR_ES_PL0_ITN_WIDTH 5 +#define KVX_SFR_ES_PL0_ITN_WFXL_MASK _ULL(0x1f000) +#define KVX_SFR_ES_PL0_ITN_WFXL_CLEAR _ULL(0x1f000) +#define KVX_SFR_ES_PL0_ITN_WFXL_SET _ULL(0x1f00000000000) + +#define KVX_SFR_ES_PL0_ITL_MASK _ULL(0x60000) /* InTerrupt Level */ +#define KVX_SFR_ES_PL0_ITL_SHIFT 17 +#define KVX_SFR_ES_PL0_ITL_WIDTH 2 +#define KVX_SFR_ES_PL0_ITL_WFXL_MASK _ULL(0x60000) +#define KVX_SFR_ES_PL0_ITL_WFXL_CLEAR _ULL(0x60000) +#define KVX_SFR_ES_PL0_ITL_WFXL_SET _ULL(0x6000000000000) + +#define KVX_SFR_ES_PL0_ITI_MASK _ULL(0x1ff80000) /* InTerrupt Info */ +#define KVX_SFR_ES_PL0_ITI_SHIFT 19 +#define KVX_SFR_ES_PL0_ITI_WIDTH 10 +#define KVX_SFR_ES_PL0_ITI_WFXL_MASK _ULL(0x1ff80000) +#define KVX_SFR_ES_PL0_ITI_WFXL_CLEAR _ULL(0x1ff80000) +#define KVX_SFR_ES_PL0_ITI_WFXL_SET _ULL(0x1ff8000000000000) + +#define KVX_SFR_ES_PL0_SN_MASK _ULL(0xfff000) /* Syscall Number */ +#define KVX_SFR_ES_PL0_SN_SHIFT 12 +#define KVX_SFR_ES_PL0_SN_WIDTH 12 +#define KVX_SFR_ES_PL0_SN_WFXL_MASK _ULL(0xfff000) +#define KVX_SFR_ES_PL0_SN_WFXL_CLEAR _ULL(0xfff000) +#define KVX_SFR_ES_PL0_SN_WFXL_SET _ULL(0xfff00000000000) + +#define KVX_SFR_ES_PL0_HTC_MASK _ULL(0x1f000) /* Hardware Trap Cause */ +#define KVX_SFR_ES_PL0_HTC_SHIFT 12 +#define KVX_SFR_ES_PL0_HTC_WIDTH 5 +#define KVX_SFR_ES_PL0_HTC_WFXL_MASK _ULL(0x1f000) +#define KVX_SFR_ES_PL0_HTC_WFXL_CLEAR _ULL(0x1f000) +#define KVX_SFR_ES_PL0_HTC_WFXL_SET _ULL(0x1f00000000000) + +#define KVX_SFR_ES_PL0_SFRT_MASK _ULL(0x20000) /* SFR Trap */ +#define KVX_SFR_ES_PL0_SFRT_SHIFT 17 +#define KVX_SFR_ES_PL0_SFRT_WIDTH 1 +#define KVX_SFR_ES_PL0_SFRT_WFXL_MASK _ULL(0x20000) +#define KVX_SFR_ES_PL0_SFRT_WFXL_CLEAR _ULL(0x20000) +#define KVX_SFR_ES_PL0_SFRT_WFXL_SET _ULL(0x2000000000000) + +#define KVX_SFR_ES_PL0_SFRI_MASK _ULL(0x1c0000) /* SFR Instruction */ +#define KVX_SFR_ES_PL0_SFRI_SHIFT 18 +#define KVX_SFR_ES_PL0_SFRI_WIDTH 3 +#define KVX_SFR_ES_PL0_SFRI_WFXL_MASK _ULL(0x1c0000) +#define KVX_SFR_ES_PL0_SFRI_WFXL_CLEAR _ULL(0x1c0000) +#define KVX_SFR_ES_PL0_SFRI_WFXL_SET _ULL(0x1c000000000000) + +#define KVX_SFR_ES_PL0_GPRP_MASK _ULL(0x7e00000) /* GPR Pointer */ +#define KVX_SFR_ES_PL0_GPRP_SHIFT 21 +#define KVX_SFR_ES_PL0_GPRP_WIDTH 6 +#define KVX_SFR_ES_PL0_GPRP_WFXL_MASK _ULL(0x7e00000) +#define KVX_SFR_ES_PL0_GPRP_WFXL_CLEAR _ULL(0x7e00000) +#define KVX_SFR_ES_PL0_GPRP_WFXL_SET _ULL(0x7e0000000000000) + +#define KVX_SFR_ES_PL0_SFRP_MASK _ULL(0xff8000000) /* SFR Pointer */ +#define KVX_SFR_ES_PL0_SFRP_SHIFT 27 +#define KVX_SFR_ES_PL0_SFRP_WIDTH 9 +#define KVX_SFR_ES_PL0_SFRP_WFXL_MASK _ULL(0xf8000000) +#define KVX_SFR_ES_PL0_SFRP_WFXL_CLEAR _ULL(0xf8000000) +#define KVX_SFR_ES_PL0_SFRP_WFXL_SET _ULL(0xf800000000000000) +#define KVX_SFR_ES_PL0_SFRP_WFXM_MASK _ULL(0xf00000000) +#define KVX_SFR_ES_PL0_SFRP_WFXM_CLEAR _ULL(0xf) +#define KVX_SFR_ES_PL0_SFRP_WFXM_SET _ULL(0xf00000000) + +#define KVX_SFR_ES_PL0_DHT_MASK _ULL(0x1000000000) /* Disabled Hardware Trap */ +#define KVX_SFR_ES_PL0_DHT_SHIFT 36 +#define KVX_SFR_ES_PL0_DHT_WIDTH 1 +#define KVX_SFR_ES_PL0_DHT_WFXM_MASK _ULL(0x1000000000) +#define KVX_SFR_ES_PL0_DHT_WFXM_CLEAR _ULL(0x10) +#define KVX_SFR_ES_PL0_DHT_WFXM_SET _ULL(0x1000000000) + +#define KVX_SFR_ES_PL0_RWX_MASK _ULL(0x38000000000) /* Read Write Execute */ +#define KVX_SFR_ES_PL0_RWX_SHIFT 39 +#define KVX_SFR_ES_PL0_RWX_WIDTH 3 +#define KVX_SFR_ES_PL0_RWX_WFXM_MASK _ULL(0x38000000000) +#define KVX_SFR_ES_PL0_RWX_WFXM_CLEAR _ULL(0x380) +#define KVX_SFR_ES_PL0_RWX_WFXM_SET _ULL(0x38000000000) + +#define KVX_SFR_ES_PL0_NTA_MASK _ULL(0x40000000000) /* Non-Trapping Access */ +#define KVX_SFR_ES_PL0_NTA_SHIFT 42 +#define KVX_SFR_ES_PL0_NTA_WIDTH 1 +#define KVX_SFR_ES_PL0_NTA_WFXM_MASK _ULL(0x40000000000) +#define KVX_SFR_ES_PL0_NTA_WFXM_CLEAR _ULL(0x400) +#define KVX_SFR_ES_PL0_NTA_WFXM_SET _ULL(0x40000000000) + +#define KVX_SFR_ES_PL0_UCA_MASK _ULL(0x80000000000) /* Un-Cached Access */ +#define KVX_SFR_ES_PL0_UCA_SHIFT 43 +#define KVX_SFR_ES_PL0_UCA_WIDTH 1 +#define KVX_SFR_ES_PL0_UCA_WFXM_MASK _ULL(0x80000000000) +#define KVX_SFR_ES_PL0_UCA_WFXM_CLEAR _ULL(0x800) +#define KVX_SFR_ES_PL0_UCA_WFXM_SET _ULL(0x80000000000) + +#define KVX_SFR_ES_PL0_AS_MASK _ULL(0x3f00000000000) /* Access Size */ +#define KVX_SFR_ES_PL0_AS_SHIFT 44 +#define KVX_SFR_ES_PL0_AS_WIDTH 6 +#define KVX_SFR_ES_PL0_AS_WFXM_MASK _ULL(0x3f00000000000) +#define KVX_SFR_ES_PL0_AS_WFXM_CLEAR _ULL(0x3f000) +#define KVX_SFR_ES_PL0_AS_WFXM_SET _ULL(0x3f00000000000) + +#define KVX_SFR_ES_PL0_BS_MASK _ULL(0x3c000000000000) /* Bundle Size */ +#define KVX_SFR_ES_PL0_BS_SHIFT 50 +#define KVX_SFR_ES_PL0_BS_WIDTH 4 +#define KVX_SFR_ES_PL0_BS_WFXM_MASK _ULL(0x3c000000000000) +#define KVX_SFR_ES_PL0_BS_WFXM_CLEAR _ULL(0x3c0000) +#define KVX_SFR_ES_PL0_BS_WFXM_SET _ULL(0x3c000000000000) + +#define KVX_SFR_ES_PL0_DRI_MASK _ULL(0xfc0000000000000) /* Data Register Index */ +#define KVX_SFR_ES_PL0_DRI_SHIFT 54 +#define KVX_SFR_ES_PL0_DRI_WIDTH 6 +#define KVX_SFR_ES_PL0_DRI_WFXM_MASK _ULL(0xfc0000000000000) +#define KVX_SFR_ES_PL0_DRI_WFXM_CLEAR _ULL(0xfc00000) +#define KVX_SFR_ES_PL0_DRI_WFXM_SET _ULL(0xfc0000000000000) + +#define KVX_SFR_ES_PL0_PIC_MASK _ULL(0xf000000000000000) /* Privileged Instruction Code */ +#define KVX_SFR_ES_PL0_PIC_SHIFT 60 +#define KVX_SFR_ES_PL0_PIC_WIDTH 4 +#define KVX_SFR_ES_PL0_PIC_WFXM_MASK _ULL(0xf000000000000000) +#define KVX_SFR_ES_PL0_PIC_WFXM_CLEAR _ULL(0xf0000000) +#define KVX_SFR_ES_PL0_PIC_WFXM_SET _ULL(0xf000000000000000) + +#define KVX_SFR_ES_PL0_DC_MASK _ULL(0x3000) /* Debug Cause */ +#define KVX_SFR_ES_PL0_DC_SHIFT 12 +#define KVX_SFR_ES_PL0_DC_WIDTH 2 +#define KVX_SFR_ES_PL0_DC_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_ES_PL0_DC_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_ES_PL0_DC_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_ES_PL0_BN_MASK _ULL(0x4000) /* Breakpoint Number */ +#define KVX_SFR_ES_PL0_BN_SHIFT 14 +#define KVX_SFR_ES_PL0_BN_WIDTH 1 +#define KVX_SFR_ES_PL0_BN_WFXL_MASK _ULL(0x4000) +#define KVX_SFR_ES_PL0_BN_WFXL_CLEAR _ULL(0x4000) +#define KVX_SFR_ES_PL0_BN_WFXL_SET _ULL(0x400000000000) + +#define KVX_SFR_ES_PL0_WN_MASK _ULL(0x8000) /* Watchpoint Number */ +#define KVX_SFR_ES_PL0_WN_SHIFT 15 +#define KVX_SFR_ES_PL0_WN_WIDTH 1 +#define KVX_SFR_ES_PL0_WN_WFXL_MASK _ULL(0x8000) +#define KVX_SFR_ES_PL0_WN_WFXL_CLEAR _ULL(0x8000) +#define KVX_SFR_ES_PL0_WN_WFXL_SET _ULL(0x800000000000) + +#define KVX_SFR_ES_PL1_EC_MASK _ULL(0xf) /* Exception Class */ +#define KVX_SFR_ES_PL1_EC_SHIFT 0 +#define KVX_SFR_ES_PL1_EC_WIDTH 4 +#define KVX_SFR_ES_PL1_EC_WFXL_MASK _ULL(0xf) +#define KVX_SFR_ES_PL1_EC_WFXL_CLEAR _ULL(0xf) +#define KVX_SFR_ES_PL1_EC_WFXL_SET _ULL(0xf00000000) + +#define KVX_SFR_ES_PL1_ED_MASK _ULL(0xfffffffffffffff0) /* Exception Details */ +#define KVX_SFR_ES_PL1_ED_SHIFT 4 +#define KVX_SFR_ES_PL1_ED_WIDTH 60 +#define KVX_SFR_ES_PL1_ED_WFXL_MASK _ULL(0xfffffff0) +#define KVX_SFR_ES_PL1_ED_WFXL_CLEAR _ULL(0xfffffff0) +#define KVX_SFR_ES_PL1_ED_WFXL_SET _ULL(0xfffffff000000000) +#define KVX_SFR_ES_PL1_ED_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_ES_PL1_ED_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_ES_PL1_ED_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_ES_PL1_OAPL_MASK _ULL(0x30) /* Origin Absolute PL */ +#define KVX_SFR_ES_PL1_OAPL_SHIFT 4 +#define KVX_SFR_ES_PL1_OAPL_WIDTH 2 +#define KVX_SFR_ES_PL1_OAPL_WFXL_MASK _ULL(0x30) +#define KVX_SFR_ES_PL1_OAPL_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_ES_PL1_OAPL_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_ES_PL1_ORPL_MASK _ULL(0xc0) /* Origin Relative PL */ +#define KVX_SFR_ES_PL1_ORPL_SHIFT 6 +#define KVX_SFR_ES_PL1_ORPL_WIDTH 2 +#define KVX_SFR_ES_PL1_ORPL_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_ES_PL1_ORPL_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_ES_PL1_ORPL_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_ES_PL1_PTAPL_MASK _ULL(0x300) /* Target Absolute PL */ +#define KVX_SFR_ES_PL1_PTAPL_SHIFT 8 +#define KVX_SFR_ES_PL1_PTAPL_WIDTH 2 +#define KVX_SFR_ES_PL1_PTAPL_WFXL_MASK _ULL(0x300) +#define KVX_SFR_ES_PL1_PTAPL_WFXL_CLEAR _ULL(0x300) +#define KVX_SFR_ES_PL1_PTAPL_WFXL_SET _ULL(0x30000000000) + +#define KVX_SFR_ES_PL1_PTRPL_MASK _ULL(0xc00) /* Target Relative PL */ +#define KVX_SFR_ES_PL1_PTRPL_SHIFT 10 +#define KVX_SFR_ES_PL1_PTRPL_WIDTH 2 +#define KVX_SFR_ES_PL1_PTRPL_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_ES_PL1_PTRPL_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_ES_PL1_PTRPL_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_ES_PL1_ITN_MASK _ULL(0x1f000) /* InTerrupt Number */ +#define KVX_SFR_ES_PL1_ITN_SHIFT 12 +#define KVX_SFR_ES_PL1_ITN_WIDTH 5 +#define KVX_SFR_ES_PL1_ITN_WFXL_MASK _ULL(0x1f000) +#define KVX_SFR_ES_PL1_ITN_WFXL_CLEAR _ULL(0x1f000) +#define KVX_SFR_ES_PL1_ITN_WFXL_SET _ULL(0x1f00000000000) + +#define KVX_SFR_ES_PL1_ITL_MASK _ULL(0x60000) /* InTerrupt Level */ +#define KVX_SFR_ES_PL1_ITL_SHIFT 17 +#define KVX_SFR_ES_PL1_ITL_WIDTH 2 +#define KVX_SFR_ES_PL1_ITL_WFXL_MASK _ULL(0x60000) +#define KVX_SFR_ES_PL1_ITL_WFXL_CLEAR _ULL(0x60000) +#define KVX_SFR_ES_PL1_ITL_WFXL_SET _ULL(0x6000000000000) + +#define KVX_SFR_ES_PL1_ITI_MASK _ULL(0x1ff80000) /* InTerrupt Info */ +#define KVX_SFR_ES_PL1_ITI_SHIFT 19 +#define KVX_SFR_ES_PL1_ITI_WIDTH 10 +#define KVX_SFR_ES_PL1_ITI_WFXL_MASK _ULL(0x1ff80000) +#define KVX_SFR_ES_PL1_ITI_WFXL_CLEAR _ULL(0x1ff80000) +#define KVX_SFR_ES_PL1_ITI_WFXL_SET _ULL(0x1ff8000000000000) + +#define KVX_SFR_ES_PL1_SN_MASK _ULL(0xfff000) /* Syscall Number */ +#define KVX_SFR_ES_PL1_SN_SHIFT 12 +#define KVX_SFR_ES_PL1_SN_WIDTH 12 +#define KVX_SFR_ES_PL1_SN_WFXL_MASK _ULL(0xfff000) +#define KVX_SFR_ES_PL1_SN_WFXL_CLEAR _ULL(0xfff000) +#define KVX_SFR_ES_PL1_SN_WFXL_SET _ULL(0xfff00000000000) + +#define KVX_SFR_ES_PL1_HTC_MASK _ULL(0x1f000) /* Hardware Trap Cause */ +#define KVX_SFR_ES_PL1_HTC_SHIFT 12 +#define KVX_SFR_ES_PL1_HTC_WIDTH 5 +#define KVX_SFR_ES_PL1_HTC_WFXL_MASK _ULL(0x1f000) +#define KVX_SFR_ES_PL1_HTC_WFXL_CLEAR _ULL(0x1f000) +#define KVX_SFR_ES_PL1_HTC_WFXL_SET _ULL(0x1f00000000000) + +#define KVX_SFR_ES_PL1_SFRT_MASK _ULL(0x20000) /* SFR Trap */ +#define KVX_SFR_ES_PL1_SFRT_SHIFT 17 +#define KVX_SFR_ES_PL1_SFRT_WIDTH 1 +#define KVX_SFR_ES_PL1_SFRT_WFXL_MASK _ULL(0x20000) +#define KVX_SFR_ES_PL1_SFRT_WFXL_CLEAR _ULL(0x20000) +#define KVX_SFR_ES_PL1_SFRT_WFXL_SET _ULL(0x2000000000000) + +#define KVX_SFR_ES_PL1_SFRI_MASK _ULL(0x1c0000) /* SFR Instruction */ +#define KVX_SFR_ES_PL1_SFRI_SHIFT 18 +#define KVX_SFR_ES_PL1_SFRI_WIDTH 3 +#define KVX_SFR_ES_PL1_SFRI_WFXL_MASK _ULL(0x1c0000) +#define KVX_SFR_ES_PL1_SFRI_WFXL_CLEAR _ULL(0x1c0000) +#define KVX_SFR_ES_PL1_SFRI_WFXL_SET _ULL(0x1c000000000000) + +#define KVX_SFR_ES_PL1_GPRP_MASK _ULL(0x7e00000) /* GPR Pointer */ +#define KVX_SFR_ES_PL1_GPRP_SHIFT 21 +#define KVX_SFR_ES_PL1_GPRP_WIDTH 6 +#define KVX_SFR_ES_PL1_GPRP_WFXL_MASK _ULL(0x7e00000) +#define KVX_SFR_ES_PL1_GPRP_WFXL_CLEAR _ULL(0x7e00000) +#define KVX_SFR_ES_PL1_GPRP_WFXL_SET _ULL(0x7e0000000000000) + +#define KVX_SFR_ES_PL1_SFRP_MASK _ULL(0xff8000000) /* SFR Pointer */ +#define KVX_SFR_ES_PL1_SFRP_SHIFT 27 +#define KVX_SFR_ES_PL1_SFRP_WIDTH 9 +#define KVX_SFR_ES_PL1_SFRP_WFXL_MASK _ULL(0xf8000000) +#define KVX_SFR_ES_PL1_SFRP_WFXL_CLEAR _ULL(0xf8000000) +#define KVX_SFR_ES_PL1_SFRP_WFXL_SET _ULL(0xf800000000000000) +#define KVX_SFR_ES_PL1_SFRP_WFXM_MASK _ULL(0xf00000000) +#define KVX_SFR_ES_PL1_SFRP_WFXM_CLEAR _ULL(0xf) +#define KVX_SFR_ES_PL1_SFRP_WFXM_SET _ULL(0xf00000000) + +#define KVX_SFR_ES_PL1_DHT_MASK _ULL(0x1000000000) /* Disabled Hardware Trap */ +#define KVX_SFR_ES_PL1_DHT_SHIFT 36 +#define KVX_SFR_ES_PL1_DHT_WIDTH 1 +#define KVX_SFR_ES_PL1_DHT_WFXM_MASK _ULL(0x1000000000) +#define KVX_SFR_ES_PL1_DHT_WFXM_CLEAR _ULL(0x10) +#define KVX_SFR_ES_PL1_DHT_WFXM_SET _ULL(0x1000000000) + +#define KVX_SFR_ES_PL1_RWX_MASK _ULL(0x38000000000) /* Read Write Execute */ +#define KVX_SFR_ES_PL1_RWX_SHIFT 39 +#define KVX_SFR_ES_PL1_RWX_WIDTH 3 +#define KVX_SFR_ES_PL1_RWX_WFXM_MASK _ULL(0x38000000000) +#define KVX_SFR_ES_PL1_RWX_WFXM_CLEAR _ULL(0x380) +#define KVX_SFR_ES_PL1_RWX_WFXM_SET _ULL(0x38000000000) + +#define KVX_SFR_ES_PL1_NTA_MASK _ULL(0x40000000000) /* Non-Trapping Access */ +#define KVX_SFR_ES_PL1_NTA_SHIFT 42 +#define KVX_SFR_ES_PL1_NTA_WIDTH 1 +#define KVX_SFR_ES_PL1_NTA_WFXM_MASK _ULL(0x40000000000) +#define KVX_SFR_ES_PL1_NTA_WFXM_CLEAR _ULL(0x400) +#define KVX_SFR_ES_PL1_NTA_WFXM_SET _ULL(0x40000000000) + +#define KVX_SFR_ES_PL1_UCA_MASK _ULL(0x80000000000) /* Un-Cached Access */ +#define KVX_SFR_ES_PL1_UCA_SHIFT 43 +#define KVX_SFR_ES_PL1_UCA_WIDTH 1 +#define KVX_SFR_ES_PL1_UCA_WFXM_MASK _ULL(0x80000000000) +#define KVX_SFR_ES_PL1_UCA_WFXM_CLEAR _ULL(0x800) +#define KVX_SFR_ES_PL1_UCA_WFXM_SET _ULL(0x80000000000) + +#define KVX_SFR_ES_PL1_AS_MASK _ULL(0x3f00000000000) /* Access Size */ +#define KVX_SFR_ES_PL1_AS_SHIFT 44 +#define KVX_SFR_ES_PL1_AS_WIDTH 6 +#define KVX_SFR_ES_PL1_AS_WFXM_MASK _ULL(0x3f00000000000) +#define KVX_SFR_ES_PL1_AS_WFXM_CLEAR _ULL(0x3f000) +#define KVX_SFR_ES_PL1_AS_WFXM_SET _ULL(0x3f00000000000) + +#define KVX_SFR_ES_PL1_BS_MASK _ULL(0x3c000000000000) /* Bundle Size */ +#define KVX_SFR_ES_PL1_BS_SHIFT 50 +#define KVX_SFR_ES_PL1_BS_WIDTH 4 +#define KVX_SFR_ES_PL1_BS_WFXM_MASK _ULL(0x3c000000000000) +#define KVX_SFR_ES_PL1_BS_WFXM_CLEAR _ULL(0x3c0000) +#define KVX_SFR_ES_PL1_BS_WFXM_SET _ULL(0x3c000000000000) + +#define KVX_SFR_ES_PL1_DRI_MASK _ULL(0xfc0000000000000) /* Data Register Index */ +#define KVX_SFR_ES_PL1_DRI_SHIFT 54 +#define KVX_SFR_ES_PL1_DRI_WIDTH 6 +#define KVX_SFR_ES_PL1_DRI_WFXM_MASK _ULL(0xfc0000000000000) +#define KVX_SFR_ES_PL1_DRI_WFXM_CLEAR _ULL(0xfc00000) +#define KVX_SFR_ES_PL1_DRI_WFXM_SET _ULL(0xfc0000000000000) + +#define KVX_SFR_ES_PL1_PIC_MASK _ULL(0xf000000000000000) /* Privileged Instruction Code */ +#define KVX_SFR_ES_PL1_PIC_SHIFT 60 +#define KVX_SFR_ES_PL1_PIC_WIDTH 4 +#define KVX_SFR_ES_PL1_PIC_WFXM_MASK _ULL(0xf000000000000000) +#define KVX_SFR_ES_PL1_PIC_WFXM_CLEAR _ULL(0xf0000000) +#define KVX_SFR_ES_PL1_PIC_WFXM_SET _ULL(0xf000000000000000) + +#define KVX_SFR_ES_PL1_DC_MASK _ULL(0x3000) /* Debug Cause */ +#define KVX_SFR_ES_PL1_DC_SHIFT 12 +#define KVX_SFR_ES_PL1_DC_WIDTH 2 +#define KVX_SFR_ES_PL1_DC_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_ES_PL1_DC_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_ES_PL1_DC_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_ES_PL1_BN_MASK _ULL(0x4000) /* Breakpoint Number */ +#define KVX_SFR_ES_PL1_BN_SHIFT 14 +#define KVX_SFR_ES_PL1_BN_WIDTH 1 +#define KVX_SFR_ES_PL1_BN_WFXL_MASK _ULL(0x4000) +#define KVX_SFR_ES_PL1_BN_WFXL_CLEAR _ULL(0x4000) +#define KVX_SFR_ES_PL1_BN_WFXL_SET _ULL(0x400000000000) + +#define KVX_SFR_ES_PL1_WN_MASK _ULL(0x8000) /* Watchpoint Number */ +#define KVX_SFR_ES_PL1_WN_SHIFT 15 +#define KVX_SFR_ES_PL1_WN_WIDTH 1 +#define KVX_SFR_ES_PL1_WN_WFXL_MASK _ULL(0x8000) +#define KVX_SFR_ES_PL1_WN_WFXL_CLEAR _ULL(0x8000) +#define KVX_SFR_ES_PL1_WN_WFXL_SET _ULL(0x800000000000) + +#define KVX_SFR_ES_PL2_EC_MASK _ULL(0xf) /* Exception Class */ +#define KVX_SFR_ES_PL2_EC_SHIFT 0 +#define KVX_SFR_ES_PL2_EC_WIDTH 4 +#define KVX_SFR_ES_PL2_EC_WFXL_MASK _ULL(0xf) +#define KVX_SFR_ES_PL2_EC_WFXL_CLEAR _ULL(0xf) +#define KVX_SFR_ES_PL2_EC_WFXL_SET _ULL(0xf00000000) + +#define KVX_SFR_ES_PL2_ED_MASK _ULL(0xfffffffffffffff0) /* Exception Details */ +#define KVX_SFR_ES_PL2_ED_SHIFT 4 +#define KVX_SFR_ES_PL2_ED_WIDTH 60 +#define KVX_SFR_ES_PL2_ED_WFXL_MASK _ULL(0xfffffff0) +#define KVX_SFR_ES_PL2_ED_WFXL_CLEAR _ULL(0xfffffff0) +#define KVX_SFR_ES_PL2_ED_WFXL_SET _ULL(0xfffffff000000000) +#define KVX_SFR_ES_PL2_ED_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_ES_PL2_ED_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_ES_PL2_ED_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_ES_PL2_OAPL_MASK _ULL(0x30) /* Origin Absolute PL */ +#define KVX_SFR_ES_PL2_OAPL_SHIFT 4 +#define KVX_SFR_ES_PL2_OAPL_WIDTH 2 +#define KVX_SFR_ES_PL2_OAPL_WFXL_MASK _ULL(0x30) +#define KVX_SFR_ES_PL2_OAPL_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_ES_PL2_OAPL_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_ES_PL2_ORPL_MASK _ULL(0xc0) /* Origin Relative PL */ +#define KVX_SFR_ES_PL2_ORPL_SHIFT 6 +#define KVX_SFR_ES_PL2_ORPL_WIDTH 2 +#define KVX_SFR_ES_PL2_ORPL_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_ES_PL2_ORPL_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_ES_PL2_ORPL_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_ES_PL2_PTAPL_MASK _ULL(0x300) /* Target Absolute PL */ +#define KVX_SFR_ES_PL2_PTAPL_SHIFT 8 +#define KVX_SFR_ES_PL2_PTAPL_WIDTH 2 +#define KVX_SFR_ES_PL2_PTAPL_WFXL_MASK _ULL(0x300) +#define KVX_SFR_ES_PL2_PTAPL_WFXL_CLEAR _ULL(0x300) +#define KVX_SFR_ES_PL2_PTAPL_WFXL_SET _ULL(0x30000000000) + +#define KVX_SFR_ES_PL2_PTRPL_MASK _ULL(0xc00) /* Target Relative PL */ +#define KVX_SFR_ES_PL2_PTRPL_SHIFT 10 +#define KVX_SFR_ES_PL2_PTRPL_WIDTH 2 +#define KVX_SFR_ES_PL2_PTRPL_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_ES_PL2_PTRPL_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_ES_PL2_PTRPL_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_ES_PL2_ITN_MASK _ULL(0x1f000) /* InTerrupt Number */ +#define KVX_SFR_ES_PL2_ITN_SHIFT 12 +#define KVX_SFR_ES_PL2_ITN_WIDTH 5 +#define KVX_SFR_ES_PL2_ITN_WFXL_MASK _ULL(0x1f000) +#define KVX_SFR_ES_PL2_ITN_WFXL_CLEAR _ULL(0x1f000) +#define KVX_SFR_ES_PL2_ITN_WFXL_SET _ULL(0x1f00000000000) + +#define KVX_SFR_ES_PL2_ITL_MASK _ULL(0x60000) /* InTerrupt Level */ +#define KVX_SFR_ES_PL2_ITL_SHIFT 17 +#define KVX_SFR_ES_PL2_ITL_WIDTH 2 +#define KVX_SFR_ES_PL2_ITL_WFXL_MASK _ULL(0x60000) +#define KVX_SFR_ES_PL2_ITL_WFXL_CLEAR _ULL(0x60000) +#define KVX_SFR_ES_PL2_ITL_WFXL_SET _ULL(0x6000000000000) + +#define KVX_SFR_ES_PL2_ITI_MASK _ULL(0x1ff80000) /* InTerrupt Info */ +#define KVX_SFR_ES_PL2_ITI_SHIFT 19 +#define KVX_SFR_ES_PL2_ITI_WIDTH 10 +#define KVX_SFR_ES_PL2_ITI_WFXL_MASK _ULL(0x1ff80000) +#define KVX_SFR_ES_PL2_ITI_WFXL_CLEAR _ULL(0x1ff80000) +#define KVX_SFR_ES_PL2_ITI_WFXL_SET _ULL(0x1ff8000000000000) + +#define KVX_SFR_ES_PL2_SN_MASK _ULL(0xfff000) /* Syscall Number */ +#define KVX_SFR_ES_PL2_SN_SHIFT 12 +#define KVX_SFR_ES_PL2_SN_WIDTH 12 +#define KVX_SFR_ES_PL2_SN_WFXL_MASK _ULL(0xfff000) +#define KVX_SFR_ES_PL2_SN_WFXL_CLEAR _ULL(0xfff000) +#define KVX_SFR_ES_PL2_SN_WFXL_SET _ULL(0xfff00000000000) + +#define KVX_SFR_ES_PL2_HTC_MASK _ULL(0x1f000) /* Hardware Trap Cause */ +#define KVX_SFR_ES_PL2_HTC_SHIFT 12 +#define KVX_SFR_ES_PL2_HTC_WIDTH 5 +#define KVX_SFR_ES_PL2_HTC_WFXL_MASK _ULL(0x1f000) +#define KVX_SFR_ES_PL2_HTC_WFXL_CLEAR _ULL(0x1f000) +#define KVX_SFR_ES_PL2_HTC_WFXL_SET _ULL(0x1f00000000000) + +#define KVX_SFR_ES_PL2_SFRT_MASK _ULL(0x20000) /* SFR Trap */ +#define KVX_SFR_ES_PL2_SFRT_SHIFT 17 +#define KVX_SFR_ES_PL2_SFRT_WIDTH 1 +#define KVX_SFR_ES_PL2_SFRT_WFXL_MASK _ULL(0x20000) +#define KVX_SFR_ES_PL2_SFRT_WFXL_CLEAR _ULL(0x20000) +#define KVX_SFR_ES_PL2_SFRT_WFXL_SET _ULL(0x2000000000000) + +#define KVX_SFR_ES_PL2_SFRI_MASK _ULL(0x1c0000) /* SFR Instruction */ +#define KVX_SFR_ES_PL2_SFRI_SHIFT 18 +#define KVX_SFR_ES_PL2_SFRI_WIDTH 3 +#define KVX_SFR_ES_PL2_SFRI_WFXL_MASK _ULL(0x1c0000) +#define KVX_SFR_ES_PL2_SFRI_WFXL_CLEAR _ULL(0x1c0000) +#define KVX_SFR_ES_PL2_SFRI_WFXL_SET _ULL(0x1c000000000000) + +#define KVX_SFR_ES_PL2_GPRP_MASK _ULL(0x7e00000) /* GPR Pointer */ +#define KVX_SFR_ES_PL2_GPRP_SHIFT 21 +#define KVX_SFR_ES_PL2_GPRP_WIDTH 6 +#define KVX_SFR_ES_PL2_GPRP_WFXL_MASK _ULL(0x7e00000) +#define KVX_SFR_ES_PL2_GPRP_WFXL_CLEAR _ULL(0x7e00000) +#define KVX_SFR_ES_PL2_GPRP_WFXL_SET _ULL(0x7e0000000000000) + +#define KVX_SFR_ES_PL2_SFRP_MASK _ULL(0xff8000000) /* SFR Pointer */ +#define KVX_SFR_ES_PL2_SFRP_SHIFT 27 +#define KVX_SFR_ES_PL2_SFRP_WIDTH 9 +#define KVX_SFR_ES_PL2_SFRP_WFXL_MASK _ULL(0xf8000000) +#define KVX_SFR_ES_PL2_SFRP_WFXL_CLEAR _ULL(0xf8000000) +#define KVX_SFR_ES_PL2_SFRP_WFXL_SET _ULL(0xf800000000000000) +#define KVX_SFR_ES_PL2_SFRP_WFXM_MASK _ULL(0xf00000000) +#define KVX_SFR_ES_PL2_SFRP_WFXM_CLEAR _ULL(0xf) +#define KVX_SFR_ES_PL2_SFRP_WFXM_SET _ULL(0xf00000000) + +#define KVX_SFR_ES_PL2_DHT_MASK _ULL(0x1000000000) /* Disabled Hardware Trap */ +#define KVX_SFR_ES_PL2_DHT_SHIFT 36 +#define KVX_SFR_ES_PL2_DHT_WIDTH 1 +#define KVX_SFR_ES_PL2_DHT_WFXM_MASK _ULL(0x1000000000) +#define KVX_SFR_ES_PL2_DHT_WFXM_CLEAR _ULL(0x10) +#define KVX_SFR_ES_PL2_DHT_WFXM_SET _ULL(0x1000000000) + +#define KVX_SFR_ES_PL2_RWX_MASK _ULL(0x38000000000) /* Read Write Execute */ +#define KVX_SFR_ES_PL2_RWX_SHIFT 39 +#define KVX_SFR_ES_PL2_RWX_WIDTH 3 +#define KVX_SFR_ES_PL2_RWX_WFXM_MASK _ULL(0x38000000000) +#define KVX_SFR_ES_PL2_RWX_WFXM_CLEAR _ULL(0x380) +#define KVX_SFR_ES_PL2_RWX_WFXM_SET _ULL(0x38000000000) + +#define KVX_SFR_ES_PL2_NTA_MASK _ULL(0x40000000000) /* Non-Trapping Access */ +#define KVX_SFR_ES_PL2_NTA_SHIFT 42 +#define KVX_SFR_ES_PL2_NTA_WIDTH 1 +#define KVX_SFR_ES_PL2_NTA_WFXM_MASK _ULL(0x40000000000) +#define KVX_SFR_ES_PL2_NTA_WFXM_CLEAR _ULL(0x400) +#define KVX_SFR_ES_PL2_NTA_WFXM_SET _ULL(0x40000000000) + +#define KVX_SFR_ES_PL2_UCA_MASK _ULL(0x80000000000) /* Un-Cached Access */ +#define KVX_SFR_ES_PL2_UCA_SHIFT 43 +#define KVX_SFR_ES_PL2_UCA_WIDTH 1 +#define KVX_SFR_ES_PL2_UCA_WFXM_MASK _ULL(0x80000000000) +#define KVX_SFR_ES_PL2_UCA_WFXM_CLEAR _ULL(0x800) +#define KVX_SFR_ES_PL2_UCA_WFXM_SET _ULL(0x80000000000) + +#define KVX_SFR_ES_PL2_AS_MASK _ULL(0x3f00000000000) /* Access Size */ +#define KVX_SFR_ES_PL2_AS_SHIFT 44 +#define KVX_SFR_ES_PL2_AS_WIDTH 6 +#define KVX_SFR_ES_PL2_AS_WFXM_MASK _ULL(0x3f00000000000) +#define KVX_SFR_ES_PL2_AS_WFXM_CLEAR _ULL(0x3f000) +#define KVX_SFR_ES_PL2_AS_WFXM_SET _ULL(0x3f00000000000) + +#define KVX_SFR_ES_PL2_BS_MASK _ULL(0x3c000000000000) /* Bundle Size */ +#define KVX_SFR_ES_PL2_BS_SHIFT 50 +#define KVX_SFR_ES_PL2_BS_WIDTH 4 +#define KVX_SFR_ES_PL2_BS_WFXM_MASK _ULL(0x3c000000000000) +#define KVX_SFR_ES_PL2_BS_WFXM_CLEAR _ULL(0x3c0000) +#define KVX_SFR_ES_PL2_BS_WFXM_SET _ULL(0x3c000000000000) + +#define KVX_SFR_ES_PL2_DRI_MASK _ULL(0xfc0000000000000) /* Data Register Index */ +#define KVX_SFR_ES_PL2_DRI_SHIFT 54 +#define KVX_SFR_ES_PL2_DRI_WIDTH 6 +#define KVX_SFR_ES_PL2_DRI_WFXM_MASK _ULL(0xfc0000000000000) +#define KVX_SFR_ES_PL2_DRI_WFXM_CLEAR _ULL(0xfc00000) +#define KVX_SFR_ES_PL2_DRI_WFXM_SET _ULL(0xfc0000000000000) + +#define KVX_SFR_ES_PL2_PIC_MASK _ULL(0xf000000000000000) /* Privileged Instruction Code */ +#define KVX_SFR_ES_PL2_PIC_SHIFT 60 +#define KVX_SFR_ES_PL2_PIC_WIDTH 4 +#define KVX_SFR_ES_PL2_PIC_WFXM_MASK _ULL(0xf000000000000000) +#define KVX_SFR_ES_PL2_PIC_WFXM_CLEAR _ULL(0xf0000000) +#define KVX_SFR_ES_PL2_PIC_WFXM_SET _ULL(0xf000000000000000) + +#define KVX_SFR_ES_PL2_DC_MASK _ULL(0x3000) /* Debug Cause */ +#define KVX_SFR_ES_PL2_DC_SHIFT 12 +#define KVX_SFR_ES_PL2_DC_WIDTH 2 +#define KVX_SFR_ES_PL2_DC_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_ES_PL2_DC_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_ES_PL2_DC_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_ES_PL2_BN_MASK _ULL(0x4000) /* Breakpoint Number */ +#define KVX_SFR_ES_PL2_BN_SHIFT 14 +#define KVX_SFR_ES_PL2_BN_WIDTH 1 +#define KVX_SFR_ES_PL2_BN_WFXL_MASK _ULL(0x4000) +#define KVX_SFR_ES_PL2_BN_WFXL_CLEAR _ULL(0x4000) +#define KVX_SFR_ES_PL2_BN_WFXL_SET _ULL(0x400000000000) + +#define KVX_SFR_ES_PL2_WN_MASK _ULL(0x8000) /* Watchpoint Number */ +#define KVX_SFR_ES_PL2_WN_SHIFT 15 +#define KVX_SFR_ES_PL2_WN_WIDTH 1 +#define KVX_SFR_ES_PL2_WN_WFXL_MASK _ULL(0x8000) +#define KVX_SFR_ES_PL2_WN_WFXL_CLEAR _ULL(0x8000) +#define KVX_SFR_ES_PL2_WN_WFXL_SET _ULL(0x800000000000) + +#define KVX_SFR_ES_PL3_EC_MASK _ULL(0xf) /* Exception Class */ +#define KVX_SFR_ES_PL3_EC_SHIFT 0 +#define KVX_SFR_ES_PL3_EC_WIDTH 4 +#define KVX_SFR_ES_PL3_EC_WFXL_MASK _ULL(0xf) +#define KVX_SFR_ES_PL3_EC_WFXL_CLEAR _ULL(0xf) +#define KVX_SFR_ES_PL3_EC_WFXL_SET _ULL(0xf00000000) + +#define KVX_SFR_ES_PL3_ED_MASK _ULL(0xfffffffffffffff0) /* Exception Details */ +#define KVX_SFR_ES_PL3_ED_SHIFT 4 +#define KVX_SFR_ES_PL3_ED_WIDTH 60 +#define KVX_SFR_ES_PL3_ED_WFXL_MASK _ULL(0xfffffff0) +#define KVX_SFR_ES_PL3_ED_WFXL_CLEAR _ULL(0xfffffff0) +#define KVX_SFR_ES_PL3_ED_WFXL_SET _ULL(0xfffffff000000000) +#define KVX_SFR_ES_PL3_ED_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_ES_PL3_ED_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_ES_PL3_ED_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_ES_PL3_OAPL_MASK _ULL(0x30) /* Origin Absolute PL */ +#define KVX_SFR_ES_PL3_OAPL_SHIFT 4 +#define KVX_SFR_ES_PL3_OAPL_WIDTH 2 +#define KVX_SFR_ES_PL3_OAPL_WFXL_MASK _ULL(0x30) +#define KVX_SFR_ES_PL3_OAPL_WFXL_CLEAR _ULL(0x30) +#define KVX_SFR_ES_PL3_OAPL_WFXL_SET _ULL(0x3000000000) + +#define KVX_SFR_ES_PL3_ORPL_MASK _ULL(0xc0) /* Origin Relative PL */ +#define KVX_SFR_ES_PL3_ORPL_SHIFT 6 +#define KVX_SFR_ES_PL3_ORPL_WIDTH 2 +#define KVX_SFR_ES_PL3_ORPL_WFXL_MASK _ULL(0xc0) +#define KVX_SFR_ES_PL3_ORPL_WFXL_CLEAR _ULL(0xc0) +#define KVX_SFR_ES_PL3_ORPL_WFXL_SET _ULL(0xc000000000) + +#define KVX_SFR_ES_PL3_PTAPL_MASK _ULL(0x300) /* Target Absolute PL */ +#define KVX_SFR_ES_PL3_PTAPL_SHIFT 8 +#define KVX_SFR_ES_PL3_PTAPL_WIDTH 2 +#define KVX_SFR_ES_PL3_PTAPL_WFXL_MASK _ULL(0x300) +#define KVX_SFR_ES_PL3_PTAPL_WFXL_CLEAR _ULL(0x300) +#define KVX_SFR_ES_PL3_PTAPL_WFXL_SET _ULL(0x30000000000) + +#define KVX_SFR_ES_PL3_PTRPL_MASK _ULL(0xc00) /* Target Relative PL */ +#define KVX_SFR_ES_PL3_PTRPL_SHIFT 10 +#define KVX_SFR_ES_PL3_PTRPL_WIDTH 2 +#define KVX_SFR_ES_PL3_PTRPL_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_ES_PL3_PTRPL_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_ES_PL3_PTRPL_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_ES_PL3_ITN_MASK _ULL(0x1f000) /* InTerrupt Number */ +#define KVX_SFR_ES_PL3_ITN_SHIFT 12 +#define KVX_SFR_ES_PL3_ITN_WIDTH 5 +#define KVX_SFR_ES_PL3_ITN_WFXL_MASK _ULL(0x1f000) +#define KVX_SFR_ES_PL3_ITN_WFXL_CLEAR _ULL(0x1f000) +#define KVX_SFR_ES_PL3_ITN_WFXL_SET _ULL(0x1f00000000000) + +#define KVX_SFR_ES_PL3_ITL_MASK _ULL(0x60000) /* InTerrupt Level */ +#define KVX_SFR_ES_PL3_ITL_SHIFT 17 +#define KVX_SFR_ES_PL3_ITL_WIDTH 2 +#define KVX_SFR_ES_PL3_ITL_WFXL_MASK _ULL(0x60000) +#define KVX_SFR_ES_PL3_ITL_WFXL_CLEAR _ULL(0x60000) +#define KVX_SFR_ES_PL3_ITL_WFXL_SET _ULL(0x6000000000000) + +#define KVX_SFR_ES_PL3_ITI_MASK _ULL(0x1ff80000) /* InTerrupt Info */ +#define KVX_SFR_ES_PL3_ITI_SHIFT 19 +#define KVX_SFR_ES_PL3_ITI_WIDTH 10 +#define KVX_SFR_ES_PL3_ITI_WFXL_MASK _ULL(0x1ff80000) +#define KVX_SFR_ES_PL3_ITI_WFXL_CLEAR _ULL(0x1ff80000) +#define KVX_SFR_ES_PL3_ITI_WFXL_SET _ULL(0x1ff8000000000000) + +#define KVX_SFR_ES_PL3_SN_MASK _ULL(0xfff000) /* Syscall Number */ +#define KVX_SFR_ES_PL3_SN_SHIFT 12 +#define KVX_SFR_ES_PL3_SN_WIDTH 12 +#define KVX_SFR_ES_PL3_SN_WFXL_MASK _ULL(0xfff000) +#define KVX_SFR_ES_PL3_SN_WFXL_CLEAR _ULL(0xfff000) +#define KVX_SFR_ES_PL3_SN_WFXL_SET _ULL(0xfff00000000000) + +#define KVX_SFR_ES_PL3_HTC_MASK _ULL(0x1f000) /* Hardware Trap Cause */ +#define KVX_SFR_ES_PL3_HTC_SHIFT 12 +#define KVX_SFR_ES_PL3_HTC_WIDTH 5 +#define KVX_SFR_ES_PL3_HTC_WFXL_MASK _ULL(0x1f000) +#define KVX_SFR_ES_PL3_HTC_WFXL_CLEAR _ULL(0x1f000) +#define KVX_SFR_ES_PL3_HTC_WFXL_SET _ULL(0x1f00000000000) + +#define KVX_SFR_ES_PL3_SFRT_MASK _ULL(0x20000) /* SFR Trap */ +#define KVX_SFR_ES_PL3_SFRT_SHIFT 17 +#define KVX_SFR_ES_PL3_SFRT_WIDTH 1 +#define KVX_SFR_ES_PL3_SFRT_WFXL_MASK _ULL(0x20000) +#define KVX_SFR_ES_PL3_SFRT_WFXL_CLEAR _ULL(0x20000) +#define KVX_SFR_ES_PL3_SFRT_WFXL_SET _ULL(0x2000000000000) + +#define KVX_SFR_ES_PL3_SFRI_MASK _ULL(0x1c0000) /* SFR Instruction */ +#define KVX_SFR_ES_PL3_SFRI_SHIFT 18 +#define KVX_SFR_ES_PL3_SFRI_WIDTH 3 +#define KVX_SFR_ES_PL3_SFRI_WFXL_MASK _ULL(0x1c0000) +#define KVX_SFR_ES_PL3_SFRI_WFXL_CLEAR _ULL(0x1c0000) +#define KVX_SFR_ES_PL3_SFRI_WFXL_SET _ULL(0x1c000000000000) + +#define KVX_SFR_ES_PL3_GPRP_MASK _ULL(0x7e00000) /* GPR Pointer */ +#define KVX_SFR_ES_PL3_GPRP_SHIFT 21 +#define KVX_SFR_ES_PL3_GPRP_WIDTH 6 +#define KVX_SFR_ES_PL3_GPRP_WFXL_MASK _ULL(0x7e00000) +#define KVX_SFR_ES_PL3_GPRP_WFXL_CLEAR _ULL(0x7e00000) +#define KVX_SFR_ES_PL3_GPRP_WFXL_SET _ULL(0x7e0000000000000) + +#define KVX_SFR_ES_PL3_SFRP_MASK _ULL(0xff8000000) /* SFR Pointer */ +#define KVX_SFR_ES_PL3_SFRP_SHIFT 27 +#define KVX_SFR_ES_PL3_SFRP_WIDTH 9 +#define KVX_SFR_ES_PL3_SFRP_WFXL_MASK _ULL(0xf8000000) +#define KVX_SFR_ES_PL3_SFRP_WFXL_CLEAR _ULL(0xf8000000) +#define KVX_SFR_ES_PL3_SFRP_WFXL_SET _ULL(0xf800000000000000) +#define KVX_SFR_ES_PL3_SFRP_WFXM_MASK _ULL(0xf00000000) +#define KVX_SFR_ES_PL3_SFRP_WFXM_CLEAR _ULL(0xf) +#define KVX_SFR_ES_PL3_SFRP_WFXM_SET _ULL(0xf00000000) + +#define KVX_SFR_ES_PL3_DHT_MASK _ULL(0x1000000000) /* Disabled Hardware Trap */ +#define KVX_SFR_ES_PL3_DHT_SHIFT 36 +#define KVX_SFR_ES_PL3_DHT_WIDTH 1 +#define KVX_SFR_ES_PL3_DHT_WFXM_MASK _ULL(0x1000000000) +#define KVX_SFR_ES_PL3_DHT_WFXM_CLEAR _ULL(0x10) +#define KVX_SFR_ES_PL3_DHT_WFXM_SET _ULL(0x1000000000) + +#define KVX_SFR_ES_PL3_RWX_MASK _ULL(0x38000000000) /* Read Write Execute */ +#define KVX_SFR_ES_PL3_RWX_SHIFT 39 +#define KVX_SFR_ES_PL3_RWX_WIDTH 3 +#define KVX_SFR_ES_PL3_RWX_WFXM_MASK _ULL(0x38000000000) +#define KVX_SFR_ES_PL3_RWX_WFXM_CLEAR _ULL(0x380) +#define KVX_SFR_ES_PL3_RWX_WFXM_SET _ULL(0x38000000000) + +#define KVX_SFR_ES_PL3_NTA_MASK _ULL(0x40000000000) /* Non-Trapping Access */ +#define KVX_SFR_ES_PL3_NTA_SHIFT 42 +#define KVX_SFR_ES_PL3_NTA_WIDTH 1 +#define KVX_SFR_ES_PL3_NTA_WFXM_MASK _ULL(0x40000000000) +#define KVX_SFR_ES_PL3_NTA_WFXM_CLEAR _ULL(0x400) +#define KVX_SFR_ES_PL3_NTA_WFXM_SET _ULL(0x40000000000) + +#define KVX_SFR_ES_PL3_UCA_MASK _ULL(0x80000000000) /* Un-Cached Access */ +#define KVX_SFR_ES_PL3_UCA_SHIFT 43 +#define KVX_SFR_ES_PL3_UCA_WIDTH 1 +#define KVX_SFR_ES_PL3_UCA_WFXM_MASK _ULL(0x80000000000) +#define KVX_SFR_ES_PL3_UCA_WFXM_CLEAR _ULL(0x800) +#define KVX_SFR_ES_PL3_UCA_WFXM_SET _ULL(0x80000000000) + +#define KVX_SFR_ES_PL3_AS_MASK _ULL(0x3f00000000000) /* Access Size */ +#define KVX_SFR_ES_PL3_AS_SHIFT 44 +#define KVX_SFR_ES_PL3_AS_WIDTH 6 +#define KVX_SFR_ES_PL3_AS_WFXM_MASK _ULL(0x3f00000000000) +#define KVX_SFR_ES_PL3_AS_WFXM_CLEAR _ULL(0x3f000) +#define KVX_SFR_ES_PL3_AS_WFXM_SET _ULL(0x3f00000000000) + +#define KVX_SFR_ES_PL3_BS_MASK _ULL(0x3c000000000000) /* Bundle Size */ +#define KVX_SFR_ES_PL3_BS_SHIFT 50 +#define KVX_SFR_ES_PL3_BS_WIDTH 4 +#define KVX_SFR_ES_PL3_BS_WFXM_MASK _ULL(0x3c000000000000) +#define KVX_SFR_ES_PL3_BS_WFXM_CLEAR _ULL(0x3c0000) +#define KVX_SFR_ES_PL3_BS_WFXM_SET _ULL(0x3c000000000000) + +#define KVX_SFR_ES_PL3_DRI_MASK _ULL(0xfc0000000000000) /* Data Register Index */ +#define KVX_SFR_ES_PL3_DRI_SHIFT 54 +#define KVX_SFR_ES_PL3_DRI_WIDTH 6 +#define KVX_SFR_ES_PL3_DRI_WFXM_MASK _ULL(0xfc0000000000000) +#define KVX_SFR_ES_PL3_DRI_WFXM_CLEAR _ULL(0xfc00000) +#define KVX_SFR_ES_PL3_DRI_WFXM_SET _ULL(0xfc0000000000000) + +#define KVX_SFR_ES_PL3_PIC_MASK _ULL(0xf000000000000000) /* Privileged Instruction Code */ +#define KVX_SFR_ES_PL3_PIC_SHIFT 60 +#define KVX_SFR_ES_PL3_PIC_WIDTH 4 +#define KVX_SFR_ES_PL3_PIC_WFXM_MASK _ULL(0xf000000000000000) +#define KVX_SFR_ES_PL3_PIC_WFXM_CLEAR _ULL(0xf0000000) +#define KVX_SFR_ES_PL3_PIC_WFXM_SET _ULL(0xf000000000000000) + +#define KVX_SFR_ES_PL3_DC_MASK _ULL(0x3000) /* Debug Cause */ +#define KVX_SFR_ES_PL3_DC_SHIFT 12 +#define KVX_SFR_ES_PL3_DC_WIDTH 2 +#define KVX_SFR_ES_PL3_DC_WFXL_MASK _ULL(0x3000) +#define KVX_SFR_ES_PL3_DC_WFXL_CLEAR _ULL(0x3000) +#define KVX_SFR_ES_PL3_DC_WFXL_SET _ULL(0x300000000000) + +#define KVX_SFR_ES_PL3_BN_MASK _ULL(0x4000) /* Breakpoint Number */ +#define KVX_SFR_ES_PL3_BN_SHIFT 14 +#define KVX_SFR_ES_PL3_BN_WIDTH 1 +#define KVX_SFR_ES_PL3_BN_WFXL_MASK _ULL(0x4000) +#define KVX_SFR_ES_PL3_BN_WFXL_CLEAR _ULL(0x4000) +#define KVX_SFR_ES_PL3_BN_WFXL_SET _ULL(0x400000000000) + +#define KVX_SFR_ES_PL3_WN_MASK _ULL(0x8000) /* Watchpoint Number */ +#define KVX_SFR_ES_PL3_WN_SHIFT 15 +#define KVX_SFR_ES_PL3_WN_WIDTH 1 +#define KVX_SFR_ES_PL3_WN_WFXL_MASK _ULL(0x8000) +#define KVX_SFR_ES_PL3_WN_WFXL_CLEAR _ULL(0x8000) +#define KVX_SFR_ES_PL3_WN_WFXL_SET _ULL(0x800000000000) + +#define KVX_SFR_TCR_T0CE_MASK _ULL(0x10000) /* Timer 0 Count Enable */ +#define KVX_SFR_TCR_T0CE_SHIFT 16 +#define KVX_SFR_TCR_T0CE_WIDTH 1 +#define KVX_SFR_TCR_T0CE_WFXL_MASK _ULL(0x10000) +#define KVX_SFR_TCR_T0CE_WFXL_CLEAR _ULL(0x10000) +#define KVX_SFR_TCR_T0CE_WFXL_SET _ULL(0x1000000000000) + +#define KVX_SFR_TCR_T1CE_MASK _ULL(0x20000) /* Timer 1 Count Enable */ +#define KVX_SFR_TCR_T1CE_SHIFT 17 +#define KVX_SFR_TCR_T1CE_WIDTH 1 +#define KVX_SFR_TCR_T1CE_WFXL_MASK _ULL(0x20000) +#define KVX_SFR_TCR_T1CE_WFXL_CLEAR _ULL(0x20000) +#define KVX_SFR_TCR_T1CE_WFXL_SET _ULL(0x2000000000000) + +#define KVX_SFR_TCR_T0IE_MASK _ULL(0x40000) /* Timer 0 Interrupt Enable */ +#define KVX_SFR_TCR_T0IE_SHIFT 18 +#define KVX_SFR_TCR_T0IE_WIDTH 1 +#define KVX_SFR_TCR_T0IE_WFXL_MASK _ULL(0x40000) +#define KVX_SFR_TCR_T0IE_WFXL_CLEAR _ULL(0x40000) +#define KVX_SFR_TCR_T0IE_WFXL_SET _ULL(0x4000000000000) + +#define KVX_SFR_TCR_T1IE_MASK _ULL(0x80000) /* Timer 1 Interrupt Enable */ +#define KVX_SFR_TCR_T1IE_SHIFT 19 +#define KVX_SFR_TCR_T1IE_WIDTH 1 +#define KVX_SFR_TCR_T1IE_WFXL_MASK _ULL(0x80000) +#define KVX_SFR_TCR_T1IE_WFXL_CLEAR _ULL(0x80000) +#define KVX_SFR_TCR_T1IE_WFXL_SET _ULL(0x8000000000000) + +#define KVX_SFR_TCR_T0ST_MASK _ULL(0x100000) /* Timer 0 Status */ +#define KVX_SFR_TCR_T0ST_SHIFT 20 +#define KVX_SFR_TCR_T0ST_WIDTH 1 +#define KVX_SFR_TCR_T0ST_WFXL_MASK _ULL(0x100000) +#define KVX_SFR_TCR_T0ST_WFXL_CLEAR _ULL(0x100000) +#define KVX_SFR_TCR_T0ST_WFXL_SET _ULL(0x10000000000000) + +#define KVX_SFR_TCR_T1ST_MASK _ULL(0x200000) /* Timer 1 Status */ +#define KVX_SFR_TCR_T1ST_SHIFT 21 +#define KVX_SFR_TCR_T1ST_WIDTH 1 +#define KVX_SFR_TCR_T1ST_WFXL_MASK _ULL(0x200000) +#define KVX_SFR_TCR_T1ST_WFXL_CLEAR _ULL(0x200000) +#define KVX_SFR_TCR_T1ST_WFXL_SET _ULL(0x20000000000000) + +#define KVX_SFR_TCR_T0SI_MASK _ULL(0x400000) /* Stop Timer 0 in Idle */ +#define KVX_SFR_TCR_T0SI_SHIFT 22 +#define KVX_SFR_TCR_T0SI_WIDTH 1 +#define KVX_SFR_TCR_T0SI_WFXL_MASK _ULL(0x400000) +#define KVX_SFR_TCR_T0SI_WFXL_CLEAR _ULL(0x400000) +#define KVX_SFR_TCR_T0SI_WFXL_SET _ULL(0x40000000000000) + +#define KVX_SFR_TCR_T1SI_MASK _ULL(0x800000) /* Stop Timer 1 in Idle */ +#define KVX_SFR_TCR_T1SI_SHIFT 23 +#define KVX_SFR_TCR_T1SI_WIDTH 1 +#define KVX_SFR_TCR_T1SI_WFXL_MASK _ULL(0x800000) +#define KVX_SFR_TCR_T1SI_WFXL_CLEAR _ULL(0x800000) +#define KVX_SFR_TCR_T1SI_WFXL_SET _ULL(0x80000000000000) + +#define KVX_SFR_TCR_WCE_MASK _ULL(0x1000000) /* Watchdog Counting Enable */ +#define KVX_SFR_TCR_WCE_SHIFT 24 +#define KVX_SFR_TCR_WCE_WIDTH 1 +#define KVX_SFR_TCR_WCE_WFXL_MASK _ULL(0x1000000) +#define KVX_SFR_TCR_WCE_WFXL_CLEAR _ULL(0x1000000) +#define KVX_SFR_TCR_WCE_WFXL_SET _ULL(0x100000000000000) + +#define KVX_SFR_TCR_WIE_MASK _ULL(0x2000000) /* Watchdog Interrupt Enable */ +#define KVX_SFR_TCR_WIE_SHIFT 25 +#define KVX_SFR_TCR_WIE_WIDTH 1 +#define KVX_SFR_TCR_WIE_WFXL_MASK _ULL(0x2000000) +#define KVX_SFR_TCR_WIE_WFXL_CLEAR _ULL(0x2000000) +#define KVX_SFR_TCR_WIE_WFXL_SET _ULL(0x200000000000000) + +#define KVX_SFR_TCR_WUI_MASK _ULL(0x4000000) /* Watchdog Underflow Inform */ +#define KVX_SFR_TCR_WUI_SHIFT 26 +#define KVX_SFR_TCR_WUI_WIDTH 1 +#define KVX_SFR_TCR_WUI_WFXL_MASK _ULL(0x4000000) +#define KVX_SFR_TCR_WUI_WFXL_CLEAR _ULL(0x4000000) +#define KVX_SFR_TCR_WUI_WFXL_SET _ULL(0x400000000000000) + +#define KVX_SFR_TCR_WUS_MASK _ULL(0x8000000) /* Watchdog Underflow Status */ +#define KVX_SFR_TCR_WUS_SHIFT 27 +#define KVX_SFR_TCR_WUS_WIDTH 1 +#define KVX_SFR_TCR_WUS_WFXL_MASK _ULL(0x8000000) +#define KVX_SFR_TCR_WUS_WFXL_CLEAR _ULL(0x8000000) +#define KVX_SFR_TCR_WUS_WFXL_SET _ULL(0x800000000000000) + +#define KVX_SFR_TCR_WSI_MASK _ULL(0x10000000) /* Watchdog Stop in Idle */ +#define KVX_SFR_TCR_WSI_SHIFT 28 +#define KVX_SFR_TCR_WSI_WIDTH 1 +#define KVX_SFR_TCR_WSI_WFXL_MASK _ULL(0x10000000) +#define KVX_SFR_TCR_WSI_WFXL_CLEAR _ULL(0x10000000) +#define KVX_SFR_TCR_WSI_WFXL_SET _ULL(0x1000000000000000) + +#define KVX_SFR_PM0_PM0_MASK _ULL(0xffffffffffffffff) /* Performance Monitor 0 */ +#define KVX_SFR_PM0_PM0_SHIFT 0 +#define KVX_SFR_PM0_PM0_WIDTH 64 +#define KVX_SFR_PM0_PM0_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_PM0_PM0_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_PM0_PM0_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_PM0_PM0_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_PM0_PM0_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_PM0_PM0_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_PM1_PM1_MASK _ULL(0xffffffffffffffff) /* Performance Monitor 1 */ +#define KVX_SFR_PM1_PM1_SHIFT 0 +#define KVX_SFR_PM1_PM1_WIDTH 64 +#define KVX_SFR_PM1_PM1_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_PM1_PM1_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_PM1_PM1_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_PM1_PM1_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_PM1_PM1_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_PM1_PM1_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_PM2_PM2_MASK _ULL(0xffffffffffffffff) /* Performance Monitor 2 */ +#define KVX_SFR_PM2_PM2_SHIFT 0 +#define KVX_SFR_PM2_PM2_WIDTH 64 +#define KVX_SFR_PM2_PM2_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_PM2_PM2_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_PM2_PM2_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_PM2_PM2_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_PM2_PM2_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_PM2_PM2_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_PM3_PM3_MASK _ULL(0xffffffffffffffff) /* Performance Monitor 3 */ +#define KVX_SFR_PM3_PM3_SHIFT 0 +#define KVX_SFR_PM3_PM3_WIDTH 64 +#define KVX_SFR_PM3_PM3_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_PM3_PM3_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_PM3_PM3_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_PM3_PM3_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_PM3_PM3_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_PM3_PM3_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_PMSA_PMSA_MASK _ULL(0xffffffffffffffff) /* Performance Monitor Saved Address */ +#define KVX_SFR_PMSA_PMSA_SHIFT 0 +#define KVX_SFR_PMSA_PMSA_WIDTH 64 +#define KVX_SFR_PMSA_PMSA_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_PMSA_PMSA_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_PMSA_PMSA_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_PMSA_PMSA_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_PMSA_PMSA_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_PMSA_PMSA_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_T0V_T0V_MASK _ULL(0xffffffffffffffff) /* Timer 0 value */ +#define KVX_SFR_T0V_T0V_SHIFT 0 +#define KVX_SFR_T0V_T0V_WIDTH 64 +#define KVX_SFR_T0V_T0V_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_T0V_T0V_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_T0V_T0V_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_T0V_T0V_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_T0V_T0V_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_T0V_T0V_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_T1V_T1V_MASK _ULL(0xffffffffffffffff) /* Timer 1 value */ +#define KVX_SFR_T1V_T1V_SHIFT 0 +#define KVX_SFR_T1V_T1V_WIDTH 64 +#define KVX_SFR_T1V_T1V_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_T1V_T1V_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_T1V_T1V_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_T1V_T1V_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_T1V_T1V_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_T1V_T1V_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_T0R_T0R_MASK _ULL(0xffffffffffffffff) /* Timer 0 reload value */ +#define KVX_SFR_T0R_T0R_SHIFT 0 +#define KVX_SFR_T0R_T0R_WIDTH 64 +#define KVX_SFR_T0R_T0R_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_T0R_T0R_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_T0R_T0R_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_T0R_T0R_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_T0R_T0R_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_T0R_T0R_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_T1R_T1R_MASK _ULL(0xffffffffffffffff) /* Timer 1 reload value */ +#define KVX_SFR_T1R_T1R_SHIFT 0 +#define KVX_SFR_T1R_T1R_WIDTH 64 +#define KVX_SFR_T1R_T1R_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_T1R_T1R_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_T1R_T1R_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_T1R_T1R_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_T1R_T1R_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_T1R_T1R_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_WDV_WDV_MASK _ULL(0xffffffffffffffff) /* Watchdog Value */ +#define KVX_SFR_WDV_WDV_SHIFT 0 +#define KVX_SFR_WDV_WDV_WIDTH 64 +#define KVX_SFR_WDV_WDV_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_WDV_WDV_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_WDV_WDV_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_WDV_WDV_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_WDV_WDV_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_WDV_WDV_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_WDR_WDR_MASK _ULL(0xffffffffffffffff) /* Watchdog Reload Value */ +#define KVX_SFR_WDR_WDR_SHIFT 0 +#define KVX_SFR_WDR_WDR_WIDTH 64 +#define KVX_SFR_WDR_WDR_WFXL_MASK _ULL(0xffffffff) +#define KVX_SFR_WDR_WDR_WFXL_CLEAR _ULL(0xffffffff) +#define KVX_SFR_WDR_WDR_WFXL_SET _ULL(0xffffffff00000000) +#define KVX_SFR_WDR_WDR_WFXM_MASK _ULL(0xffffffff00000000) +#define KVX_SFR_WDR_WDR_WFXM_CLEAR _ULL(0xffffffff) +#define KVX_SFR_WDR_WDR_WFXM_SET _ULL(0xffffffff00000000) + +#define KVX_SFR_PMC_PM0C_MASK _ULL(0x3f) /* PM0 Configuration */ +#define KVX_SFR_PMC_PM0C_SHIFT 0 +#define KVX_SFR_PMC_PM0C_WIDTH 6 +#define KVX_SFR_PMC_PM0C_WFXL_MASK _ULL(0x3f) +#define KVX_SFR_PMC_PM0C_WFXL_CLEAR _ULL(0x3f) +#define KVX_SFR_PMC_PM0C_WFXL_SET _ULL(0x3f00000000) + +#define KVX_SFR_PMC_PM1C_MASK _ULL(0x1f80) /* PM1 Configuration */ +#define KVX_SFR_PMC_PM1C_SHIFT 7 +#define KVX_SFR_PMC_PM1C_WIDTH 6 +#define KVX_SFR_PMC_PM1C_WFXL_MASK _ULL(0x1f80) +#define KVX_SFR_PMC_PM1C_WFXL_CLEAR _ULL(0x1f80) +#define KVX_SFR_PMC_PM1C_WFXL_SET _ULL(0x1f8000000000) + +#define KVX_SFR_PMC_PM2C_MASK _ULL(0xfc000) /* PM2 Configuration */ +#define KVX_SFR_PMC_PM2C_SHIFT 14 +#define KVX_SFR_PMC_PM2C_WIDTH 6 +#define KVX_SFR_PMC_PM2C_WFXL_MASK _ULL(0xfc000) +#define KVX_SFR_PMC_PM2C_WFXL_CLEAR _ULL(0xfc000) +#define KVX_SFR_PMC_PM2C_WFXL_SET _ULL(0xfc00000000000) + +#define KVX_SFR_PMC_PM3C_MASK _ULL(0x7e00000) /* PM3 Configuration */ +#define KVX_SFR_PMC_PM3C_SHIFT 21 +#define KVX_SFR_PMC_PM3C_WIDTH 6 +#define KVX_SFR_PMC_PM3C_WFXL_MASK _ULL(0x7e00000) +#define KVX_SFR_PMC_PM3C_WFXL_CLEAR _ULL(0x7e00000) +#define KVX_SFR_PMC_PM3C_WFXL_SET _ULL(0x7e0000000000000) + +#define KVX_SFR_PMC_SAV_MASK _ULL(0x40000000) /* Saved Address Valid */ +#define KVX_SFR_PMC_SAV_SHIFT 30 +#define KVX_SFR_PMC_SAV_WIDTH 1 +#define KVX_SFR_PMC_SAV_WFXL_MASK _ULL(0x40000000) +#define KVX_SFR_PMC_SAV_WFXL_CLEAR _ULL(0x40000000) +#define KVX_SFR_PMC_SAV_WFXL_SET _ULL(0x4000000000000000) + +#define KVX_SFR_PMC_PM0IE_MASK _ULL(0x100000000) /* PM0 Interrupt Enable */ +#define KVX_SFR_PMC_PM0IE_SHIFT 32 +#define KVX_SFR_PMC_PM0IE_WIDTH 1 +#define KVX_SFR_PMC_PM0IE_WFXM_MASK _ULL(0x100000000) +#define KVX_SFR_PMC_PM0IE_WFXM_CLEAR _ULL(0x1) +#define KVX_SFR_PMC_PM0IE_WFXM_SET _ULL(0x100000000) + +#define KVX_SFR_PMC_PM1IE_MASK _ULL(0x200000000) /* PM1 Interrupt Enable */ +#define KVX_SFR_PMC_PM1IE_SHIFT 33 +#define KVX_SFR_PMC_PM1IE_WIDTH 1 +#define KVX_SFR_PMC_PM1IE_WFXM_MASK _ULL(0x200000000) +#define KVX_SFR_PMC_PM1IE_WFXM_CLEAR _ULL(0x2) +#define KVX_SFR_PMC_PM1IE_WFXM_SET _ULL(0x200000000) + +#define KVX_SFR_PMC_PM2IE_MASK _ULL(0x400000000) /* PM2 Interrupt Enable */ +#define KVX_SFR_PMC_PM2IE_SHIFT 34 +#define KVX_SFR_PMC_PM2IE_WIDTH 1 +#define KVX_SFR_PMC_PM2IE_WFXM_MASK _ULL(0x400000000) +#define KVX_SFR_PMC_PM2IE_WFXM_CLEAR _ULL(0x4) +#define KVX_SFR_PMC_PM2IE_WFXM_SET _ULL(0x400000000) + +#define KVX_SFR_PMC_PM3IE_MASK _ULL(0x800000000) /* PM3 Interrupt Enable */ +#define KVX_SFR_PMC_PM3IE_SHIFT 35 +#define KVX_SFR_PMC_PM3IE_WIDTH 1 +#define KVX_SFR_PMC_PM3IE_WFXM_MASK _ULL(0x800000000) +#define KVX_SFR_PMC_PM3IE_WFXM_CLEAR _ULL(0x8) +#define KVX_SFR_PMC_PM3IE_WFXM_SET _ULL(0x800000000) + +#define KVX_SFR_PMC_SAT_MASK _ULL(0x3000000000) /* Saved Address Type */ +#define KVX_SFR_PMC_SAT_SHIFT 36 +#define KVX_SFR_PMC_SAT_WIDTH 2 +#define KVX_SFR_PMC_SAT_WFXM_MASK _ULL(0x3000000000) +#define KVX_SFR_PMC_SAT_WFXM_CLEAR _ULL(0x30) +#define KVX_SFR_PMC_SAT_WFXM_SET _ULL(0x3000000000) + +#define KVX_SFR_PCR_PID_MASK _ULL(0xff) /* Processing Identifier in cluster */ +#define KVX_SFR_PCR_PID_SHIFT 0 +#define KVX_SFR_PCR_PID_WIDTH 8 +#define KVX_SFR_PCR_PID_WFXL_MASK _ULL(0xff) +#define KVX_SFR_PCR_PID_WFXL_CLEAR _ULL(0xff) +#define KVX_SFR_PCR_PID_WFXL_SET _ULL(0xff00000000) + +#define KVX_SFR_PCR_CID_MASK _ULL(0xff00) /* Cluster Identifier in system */ +#define KVX_SFR_PCR_CID_SHIFT 8 +#define KVX_SFR_PCR_CID_WIDTH 8 +#define KVX_SFR_PCR_CID_WFXL_MASK _ULL(0xff00) +#define KVX_SFR_PCR_CID_WFXL_CLEAR _ULL(0xff00) +#define KVX_SFR_PCR_CID_WFXL_SET _ULL(0xff0000000000) + +#define KVX_SFR_PCR_MID_MASK _ULL(0xff0000) /* MPPA Identifier */ +#define KVX_SFR_PCR_MID_SHIFT 16 +#define KVX_SFR_PCR_MID_WIDTH 8 +#define KVX_SFR_PCR_MID_WFXL_MASK _ULL(0xff0000) +#define KVX_SFR_PCR_MID_WFXL_CLEAR _ULL(0xff0000) +#define KVX_SFR_PCR_MID_WFXL_SET _ULL(0xff000000000000) + +#define KVX_SFR_PCR_CAR_MASK _ULL(0xf000000) /* Core Architecture Revision ID */ +#define KVX_SFR_PCR_CAR_SHIFT 24 +#define KVX_SFR_PCR_CAR_WIDTH 4 +#define KVX_SFR_PCR_CAR_WFXL_MASK _ULL(0xf000000) +#define KVX_SFR_PCR_CAR_WFXL_CLEAR _ULL(0xf000000) +#define KVX_SFR_PCR_CAR_WFXL_SET _ULL(0xf00000000000000) + +#define KVX_SFR_PCR_CMA_MASK _ULL(0xf0000000) /* Core Micro-Architecture Revision ID */ +#define KVX_SFR_PCR_CMA_SHIFT 28 +#define KVX_SFR_PCR_CMA_WIDTH 4 +#define KVX_SFR_PCR_CMA_WFXL_MASK _ULL(0xf0000000) +#define KVX_SFR_PCR_CMA_WFXL_CLEAR _ULL(0xf0000000) +#define KVX_SFR_PCR_CMA_WFXL_SET _ULL(0xf000000000000000) + +#define KVX_SFR_PCR_SV_MASK _ULL(0xff00000000) /* System-On-Chip Version */ +#define KVX_SFR_PCR_SV_SHIFT 32 +#define KVX_SFR_PCR_SV_WIDTH 8 +#define KVX_SFR_PCR_SV_WFXM_MASK _ULL(0xff00000000) +#define KVX_SFR_PCR_SV_WFXM_CLEAR _ULL(0xff) +#define KVX_SFR_PCR_SV_WFXM_SET _ULL(0xff00000000) + +#define KVX_SFR_PCR_ST_MASK _ULL(0xf0000000000) /* System-On-Chip Type */ +#define KVX_SFR_PCR_ST_SHIFT 40 +#define KVX_SFR_PCR_ST_WIDTH 4 +#define KVX_SFR_PCR_ST_WFXM_MASK _ULL(0xf0000000000) +#define KVX_SFR_PCR_ST_WFXM_CLEAR _ULL(0xf00) +#define KVX_SFR_PCR_ST_WFXM_SET _ULL(0xf0000000000) + +#define KVX_SFR_PCR_BM_MASK _ULL(0xff00000000000) /* Boot Mode */ +#define KVX_SFR_PCR_BM_SHIFT 44 +#define KVX_SFR_PCR_BM_WIDTH 8 +#define KVX_SFR_PCR_BM_WFXM_MASK _ULL(0xff00000000000) +#define KVX_SFR_PCR_BM_WFXM_CLEAR _ULL(0xff000) +#define KVX_SFR_PCR_BM_WFXM_SET _ULL(0xff00000000000) + +#define KVX_SFR_PCR_COE_MASK _ULL(0x10000000000000) /* COprocessor Enable */ +#define KVX_SFR_PCR_COE_SHIFT 52 +#define KVX_SFR_PCR_COE_WIDTH 1 +#define KVX_SFR_PCR_COE_WFXM_MASK _ULL(0x10000000000000) +#define KVX_SFR_PCR_COE_WFXM_CLEAR _ULL(0x100000) +#define KVX_SFR_PCR_COE_WFXM_SET _ULL(0x10000000000000) + +#define KVX_SFR_PCR_L1CE_MASK _ULL(0x20000000000000) /* L1 cache Coherency Enable */ +#define KVX_SFR_PCR_L1CE_SHIFT 53 +#define KVX_SFR_PCR_L1CE_WIDTH 1 +#define KVX_SFR_PCR_L1CE_WFXM_MASK _ULL(0x20000000000000) +#define KVX_SFR_PCR_L1CE_WFXM_CLEAR _ULL(0x200000) +#define KVX_SFR_PCR_L1CE_WFXM_SET _ULL(0x20000000000000) + +#define KVX_SFR_PCR_DSEM_MASK _ULL(0x40000000000000) /* Data Simple Ecc exception Mode */ +#define KVX_SFR_PCR_DSEM_SHIFT 54 +#define KVX_SFR_PCR_DSEM_WIDTH 1 +#define KVX_SFR_PCR_DSEM_WFXM_MASK _ULL(0x40000000000000) +#define KVX_SFR_PCR_DSEM_WFXM_CLEAR _ULL(0x400000) +#define KVX_SFR_PCR_DSEM_WFXM_SET _ULL(0x40000000000000) + +#define KVX_SFR_MMC_ASN_MASK _ULL(0x1ff) /* Address Space Number */ +#define KVX_SFR_MMC_ASN_SHIFT 0 +#define KVX_SFR_MMC_ASN_WIDTH 9 +#define KVX_SFR_MMC_ASN_WFXL_MASK _ULL(0x1ff) +#define KVX_SFR_MMC_ASN_WFXL_CLEAR _ULL(0x1ff) +#define KVX_SFR_MMC_ASN_WFXL_SET _ULL(0x1ff00000000) + +#define KVX_SFR_MMC_S_MASK _ULL(0x200) /* Speculative */ +#define KVX_SFR_MMC_S_SHIFT 9 +#define KVX_SFR_MMC_S_WIDTH 1 +#define KVX_SFR_MMC_S_WFXL_MASK _ULL(0x200) +#define KVX_SFR_MMC_S_WFXL_CLEAR _ULL(0x200) +#define KVX_SFR_MMC_S_WFXL_SET _ULL(0x20000000000) + +#define KVX_SFR_MMC_SNE_MASK _ULL(0x4000) /* Speculative NOMAPPING Enable */ +#define KVX_SFR_MMC_SNE_SHIFT 14 +#define KVX_SFR_MMC_SNE_WIDTH 1 +#define KVX_SFR_MMC_SNE_WFXL_MASK _ULL(0x4000) +#define KVX_SFR_MMC_SNE_WFXL_CLEAR _ULL(0x4000) +#define KVX_SFR_MMC_SNE_WFXL_SET _ULL(0x400000000000) + +#define KVX_SFR_MMC_SPE_MASK _ULL(0x8000) /* Speculative PROTECTION Enable */ +#define KVX_SFR_MMC_SPE_SHIFT 15 +#define KVX_SFR_MMC_SPE_WIDTH 1 +#define KVX_SFR_MMC_SPE_WFXL_MASK _ULL(0x8000) +#define KVX_SFR_MMC_SPE_WFXL_CLEAR _ULL(0x8000) +#define KVX_SFR_MMC_SPE_WFXL_SET _ULL(0x800000000000) + +#define KVX_SFR_MMC_PTC_MASK _ULL(0x30000) /* Protection Trap Cause */ +#define KVX_SFR_MMC_PTC_SHIFT 16 +#define KVX_SFR_MMC_PTC_WIDTH 2 +#define KVX_SFR_MMC_PTC_WFXL_MASK _ULL(0x30000) +#define KVX_SFR_MMC_PTC_WFXL_CLEAR _ULL(0x30000) +#define KVX_SFR_MMC_PTC_WFXL_SET _ULL(0x3000000000000) + +#define KVX_SFR_MMC_SW_MASK _ULL(0x3c0000) /* Select Way */ +#define KVX_SFR_MMC_SW_SHIFT 18 +#define KVX_SFR_MMC_SW_WIDTH 4 +#define KVX_SFR_MMC_SW_WFXL_MASK _ULL(0x3c0000) +#define KVX_SFR_MMC_SW_WFXL_CLEAR _ULL(0x3c0000) +#define KVX_SFR_MMC_SW_WFXL_SET _ULL(0x3c000000000000) + +#define KVX_SFR_MMC_SS_MASK _ULL(0xfc00000) /* Select Set */ +#define KVX_SFR_MMC_SS_SHIFT 22 +#define KVX_SFR_MMC_SS_WIDTH 6 +#define KVX_SFR_MMC_SS_WFXL_MASK _ULL(0xfc00000) +#define KVX_SFR_MMC_SS_WFXL_CLEAR _ULL(0xfc00000) +#define KVX_SFR_MMC_SS_WFXL_SET _ULL(0xfc0000000000000) + +#define KVX_SFR_MMC_SB_MASK _ULL(0x10000000) /* Select Buffer */ +#define KVX_SFR_MMC_SB_SHIFT 28 +#define KVX_SFR_MMC_SB_WIDTH 1 +#define KVX_SFR_MMC_SB_WFXL_MASK _ULL(0x10000000) +#define KVX_SFR_MMC_SB_WFXL_CLEAR _ULL(0x10000000) +#define KVX_SFR_MMC_SB_WFXL_SET _ULL(0x1000000000000000) + +#define KVX_SFR_MMC_PAR_MASK _ULL(0x40000000) /* PARity error flag */ +#define KVX_SFR_MMC_PAR_SHIFT 30 +#define KVX_SFR_MMC_PAR_WIDTH 1 +#define KVX_SFR_MMC_PAR_WFXL_MASK _ULL(0x40000000) +#define KVX_SFR_MMC_PAR_WFXL_CLEAR _ULL(0x40000000) +#define KVX_SFR_MMC_PAR_WFXL_SET _ULL(0x4000000000000000) + +#define KVX_SFR_MMC_E_MASK _ULL(0x80000000) /* Error Flag */ +#define KVX_SFR_MMC_E_SHIFT 31 +#define KVX_SFR_MMC_E_WIDTH 1 +#define KVX_SFR_MMC_E_WFXL_MASK _ULL(0x80000000) +#define KVX_SFR_MMC_E_WFXL_CLEAR _ULL(0x80000000) +#define KVX_SFR_MMC_E_WFXL_SET _ULL(0x8000000000000000) + +#define KVX_SFR_TEL_ES_MASK _ULL(0x3) /* Entry Status */ +#define KVX_SFR_TEL_ES_SHIFT 0 +#define KVX_SFR_TEL_ES_WIDTH 2 +#define KVX_SFR_TEL_ES_WFXL_MASK _ULL(0x3) +#define KVX_SFR_TEL_ES_WFXL_CLEAR _ULL(0x3) +#define KVX_SFR_TEL_ES_WFXL_SET _ULL(0x300000000) + +#define KVX_SFR_TEL_CP_MASK _ULL(0xc) /* Cache Policy */ +#define KVX_SFR_TEL_CP_SHIFT 2 +#define KVX_SFR_TEL_CP_WIDTH 2 +#define KVX_SFR_TEL_CP_WFXL_MASK _ULL(0xc) +#define KVX_SFR_TEL_CP_WFXL_CLEAR _ULL(0xc) +#define KVX_SFR_TEL_CP_WFXL_SET _ULL(0xc00000000) + +#define KVX_SFR_TEL_PA_MASK _ULL(0xf0) /* Protection Attributes */ +#define KVX_SFR_TEL_PA_SHIFT 4 +#define KVX_SFR_TEL_PA_WIDTH 4 +#define KVX_SFR_TEL_PA_WFXL_MASK _ULL(0xf0) +#define KVX_SFR_TEL_PA_WFXL_CLEAR _ULL(0xf0) +#define KVX_SFR_TEL_PA_WFXL_SET _ULL(0xf000000000) + +#define KVX_SFR_TEL_PS_MASK _ULL(0xc00) /* Page Size */ +#define KVX_SFR_TEL_PS_SHIFT 10 +#define KVX_SFR_TEL_PS_WIDTH 2 +#define KVX_SFR_TEL_PS_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_TEL_PS_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_TEL_PS_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_TEL_FN_MASK _ULL(0xfffffff000) /* Frame Number */ +#define KVX_SFR_TEL_FN_SHIFT 12 +#define KVX_SFR_TEL_FN_WIDTH 28 +#define KVX_SFR_TEL_FN_WFXL_MASK _ULL(0xfffff000) +#define KVX_SFR_TEL_FN_WFXL_CLEAR _ULL(0xfffff000) +#define KVX_SFR_TEL_FN_WFXL_SET _ULL(0xfffff00000000000) +#define KVX_SFR_TEL_FN_WFXM_MASK _ULL(0xff00000000) +#define KVX_SFR_TEL_FN_WFXM_CLEAR _ULL(0xff) +#define KVX_SFR_TEL_FN_WFXM_SET _ULL(0xff00000000) + +#define KVX_SFR_TEH_ASN_MASK _ULL(0x1ff) /* Adress Space Number */ +#define KVX_SFR_TEH_ASN_SHIFT 0 +#define KVX_SFR_TEH_ASN_WIDTH 9 +#define KVX_SFR_TEH_ASN_WFXL_MASK _ULL(0x1ff) +#define KVX_SFR_TEH_ASN_WFXL_CLEAR _ULL(0x1ff) +#define KVX_SFR_TEH_ASN_WFXL_SET _ULL(0x1ff00000000) + +#define KVX_SFR_TEH_G_MASK _ULL(0x200) /* Global page indicator */ +#define KVX_SFR_TEH_G_SHIFT 9 +#define KVX_SFR_TEH_G_WIDTH 1 +#define KVX_SFR_TEH_G_WFXL_MASK _ULL(0x200) +#define KVX_SFR_TEH_G_WFXL_CLEAR _ULL(0x200) +#define KVX_SFR_TEH_G_WFXL_SET _ULL(0x20000000000) + +#define KVX_SFR_TEH_VS_MASK _ULL(0xc00) /* Virtual Space */ +#define KVX_SFR_TEH_VS_SHIFT 10 +#define KVX_SFR_TEH_VS_WIDTH 2 +#define KVX_SFR_TEH_VS_WFXL_MASK _ULL(0xc00) +#define KVX_SFR_TEH_VS_WFXL_CLEAR _ULL(0xc00) +#define KVX_SFR_TEH_VS_WFXL_SET _ULL(0xc0000000000) + +#define KVX_SFR_TEH_PN_MASK _ULL(0x1fffffff000) /* Page Number */ +#define KVX_SFR_TEH_PN_SHIFT 12 +#define KVX_SFR_TEH_PN_WIDTH 29 +#define KVX_SFR_TEH_PN_WFXL_MASK _ULL(0xfffff000) +#define KVX_SFR_TEH_PN_WFXL_CLEAR _ULL(0xfffff000) +#define KVX_SFR_TEH_PN_WFXL_SET _ULL(0xfffff00000000000) +#define KVX_SFR_TEH_PN_WFXM_MASK _ULL(0x1ff00000000) +#define KVX_SFR_TEH_PN_WFXM_CLEAR _ULL(0x1ff) +#define KVX_SFR_TEH_PN_WFXM_SET _ULL(0x1ff00000000) + +#define KVX_SFR_DC_BE0_MASK _ULL(0x1) /* Breakpoint 0 Enable */ +#define KVX_SFR_DC_BE0_SHIFT 0 +#define KVX_SFR_DC_BE0_WIDTH 1 +#define KVX_SFR_DC_BE0_WFXL_MASK _ULL(0x1) +#define KVX_SFR_DC_BE0_WFXL_CLEAR _ULL(0x1) +#define KVX_SFR_DC_BE0_WFXL_SET _ULL(0x100000000) + +#define KVX_SFR_DC_BR0_MASK _ULL(0x7e) /* Breakpoint 0 Range */ +#define KVX_SFR_DC_BR0_SHIFT 1 +#define KVX_SFR_DC_BR0_WIDTH 6 +#define KVX_SFR_DC_BR0_WFXL_MASK _ULL(0x7e) +#define KVX_SFR_DC_BR0_WFXL_CLEAR _ULL(0x7e) +#define KVX_SFR_DC_BR0_WFXL_SET _ULL(0x7e00000000) + +#define KVX_SFR_DC_BE1_MASK _ULL(0x80) /* Breakpoint 1 Enable */ +#define KVX_SFR_DC_BE1_SHIFT 7 +#define KVX_SFR_DC_BE1_WIDTH 1 +#define KVX_SFR_DC_BE1_WFXL_MASK _ULL(0x80) +#define KVX_SFR_DC_BE1_WFXL_CLEAR _ULL(0x80) +#define KVX_SFR_DC_BE1_WFXL_SET _ULL(0x8000000000) + +#define KVX_SFR_DC_BR1_MASK _ULL(0x3f00) /* Breakpoint 1 Range */ +#define KVX_SFR_DC_BR1_SHIFT 8 +#define KVX_SFR_DC_BR1_WIDTH 6 +#define KVX_SFR_DC_BR1_WFXL_MASK _ULL(0x3f00) +#define KVX_SFR_DC_BR1_WFXL_CLEAR _ULL(0x3f00) +#define KVX_SFR_DC_BR1_WFXL_SET _ULL(0x3f0000000000) + +#define KVX_SFR_DC_WE0_MASK _ULL(0x4000) /* Watchpoint 0 Enable */ +#define KVX_SFR_DC_WE0_SHIFT 14 +#define KVX_SFR_DC_WE0_WIDTH 1 +#define KVX_SFR_DC_WE0_WFXL_MASK _ULL(0x4000) +#define KVX_SFR_DC_WE0_WFXL_CLEAR _ULL(0x4000) +#define KVX_SFR_DC_WE0_WFXL_SET _ULL(0x400000000000) + +#define KVX_SFR_DC_WR0_MASK _ULL(0x1f8000) /* Watchpoint 0 Range */ +#define KVX_SFR_DC_WR0_SHIFT 15 +#define KVX_SFR_DC_WR0_WIDTH 6 +#define KVX_SFR_DC_WR0_WFXL_MASK _ULL(0x1f8000) +#define KVX_SFR_DC_WR0_WFXL_CLEAR _ULL(0x1f8000) +#define KVX_SFR_DC_WR0_WFXL_SET _ULL(0x1f800000000000) + +#define KVX_SFR_DC_WE1_MASK _ULL(0x200000) /* Watchpoint 1 Enable */ +#define KVX_SFR_DC_WE1_SHIFT 21 +#define KVX_SFR_DC_WE1_WIDTH 1 +#define KVX_SFR_DC_WE1_WFXL_MASK _ULL(0x200000) +#define KVX_SFR_DC_WE1_WFXL_CLEAR _ULL(0x200000) +#define KVX_SFR_DC_WE1_WFXL_SET _ULL(0x20000000000000) + +#define KVX_SFR_DC_WR1_MASK _ULL(0xfc00000) /* Watchpoint 1 Range */ +#define KVX_SFR_DC_WR1_SHIFT 22 +#define KVX_SFR_DC_WR1_WIDTH 6 +#define KVX_SFR_DC_WR1_WFXL_MASK _ULL(0xfc00000) +#define KVX_SFR_DC_WR1_WFXL_CLEAR _ULL(0xfc00000) +#define KVX_SFR_DC_WR1_WFXL_SET _ULL(0xfc0000000000000) + +#define KVX_SFR_MES_PSE_MASK _ULL(0x1) /* Program Simple Ecc */ +#define KVX_SFR_MES_PSE_SHIFT 0 +#define KVX_SFR_MES_PSE_WIDTH 1 +#define KVX_SFR_MES_PSE_WFXL_MASK _ULL(0x1) +#define KVX_SFR_MES_PSE_WFXL_CLEAR _ULL(0x1) +#define KVX_SFR_MES_PSE_WFXL_SET _ULL(0x100000000) + +#define KVX_SFR_MES_PILSY_MASK _ULL(0x2) /* Program cache Invalidated Line following pSYs error. */ +#define KVX_SFR_MES_PILSY_SHIFT 1 +#define KVX_SFR_MES_PILSY_WIDTH 1 +#define KVX_SFR_MES_PILSY_WFXL_MASK _ULL(0x2) +#define KVX_SFR_MES_PILSY_WFXL_CLEAR _ULL(0x2) +#define KVX_SFR_MES_PILSY_WFXL_SET _ULL(0x200000000) + +#define KVX_SFR_MES_PILDE_MASK _ULL(0x4) /* Program cache Invalidated Line following pDEcc error. */ +#define KVX_SFR_MES_PILDE_SHIFT 2 +#define KVX_SFR_MES_PILDE_WIDTH 1 +#define KVX_SFR_MES_PILDE_WFXL_MASK _ULL(0x4) +#define KVX_SFR_MES_PILDE_WFXL_CLEAR _ULL(0x4) +#define KVX_SFR_MES_PILDE_WFXL_SET _ULL(0x400000000) + +#define KVX_SFR_MES_PILPA_MASK _ULL(0x8) /* Program cache Invalidated Line following pPArity error. */ +#define KVX_SFR_MES_PILPA_SHIFT 3 +#define KVX_SFR_MES_PILPA_WIDTH 1 +#define KVX_SFR_MES_PILPA_WFXL_MASK _ULL(0x8) +#define KVX_SFR_MES_PILPA_WFXL_CLEAR _ULL(0x8) +#define KVX_SFR_MES_PILPA_WFXL_SET _ULL(0x800000000) + +#define KVX_SFR_MES_DSE_MASK _ULL(0x10) /* Data Simple Ecc */ +#define KVX_SFR_MES_DSE_SHIFT 4 +#define KVX_SFR_MES_DSE_WIDTH 1 +#define KVX_SFR_MES_DSE_WFXL_MASK _ULL(0x10) +#define KVX_SFR_MES_DSE_WFXL_CLEAR _ULL(0x10) +#define KVX_SFR_MES_DSE_WFXL_SET _ULL(0x1000000000) + +#define KVX_SFR_MES_DILSY_MASK _ULL(0x20) /* Data cache Invalidated Line following dSYs error. */ +#define KVX_SFR_MES_DILSY_SHIFT 5 +#define KVX_SFR_MES_DILSY_WIDTH 1 +#define KVX_SFR_MES_DILSY_WFXL_MASK _ULL(0x20) +#define KVX_SFR_MES_DILSY_WFXL_CLEAR _ULL(0x20) +#define KVX_SFR_MES_DILSY_WFXL_SET _ULL(0x2000000000) + +#define KVX_SFR_MES_DILDE_MASK _ULL(0x40) /* Data cache Invalidated Line following dDEcc error. */ +#define KVX_SFR_MES_DILDE_SHIFT 6 +#define KVX_SFR_MES_DILDE_WIDTH 1 +#define KVX_SFR_MES_DILDE_WFXL_MASK _ULL(0x40) +#define KVX_SFR_MES_DILDE_WFXL_CLEAR _ULL(0x40) +#define KVX_SFR_MES_DILDE_WFXL_SET _ULL(0x4000000000) + +#define KVX_SFR_MES_DILPA_MASK _ULL(0x80) /* Data cache Invalidated Line following dPArity error. */ +#define KVX_SFR_MES_DILPA_SHIFT 7 +#define KVX_SFR_MES_DILPA_WIDTH 1 +#define KVX_SFR_MES_DILPA_WFXL_MASK _ULL(0x80) +#define KVX_SFR_MES_DILPA_WFXL_CLEAR _ULL(0x80) +#define KVX_SFR_MES_DILPA_WFXL_SET _ULL(0x8000000000) + +#define KVX_SFR_MES_DDEE_MASK _ULL(0x100) /* Data DEcc Error. */ +#define KVX_SFR_MES_DDEE_SHIFT 8 +#define KVX_SFR_MES_DDEE_WIDTH 1 +#define KVX_SFR_MES_DDEE_WFXL_MASK _ULL(0x100) +#define KVX_SFR_MES_DDEE_WFXL_CLEAR _ULL(0x100) +#define KVX_SFR_MES_DDEE_WFXL_SET _ULL(0x10000000000) + +#define KVX_SFR_MES_DSYE_MASK _ULL(0x200) /* Data dSYs Error. */ +#define KVX_SFR_MES_DSYE_SHIFT 9 +#define KVX_SFR_MES_DSYE_WIDTH 1 +#define KVX_SFR_MES_DSYE_WFXL_MASK _ULL(0x200) +#define KVX_SFR_MES_DSYE_WFXL_CLEAR _ULL(0x200) +#define KVX_SFR_MES_DSYE_WFXL_SET _ULL(0x20000000000) + +#define KVX_SFR_WS_WU0_MASK _ULL(0x1) /* Wake-Up 0 */ +#define KVX_SFR_WS_WU0_SHIFT 0 +#define KVX_SFR_WS_WU0_WIDTH 1 +#define KVX_SFR_WS_WU0_WFXL_MASK _ULL(0x1) +#define KVX_SFR_WS_WU0_WFXL_CLEAR _ULL(0x1) +#define KVX_SFR_WS_WU0_WFXL_SET _ULL(0x100000000) + +#define KVX_SFR_WS_WU1_MASK _ULL(0x2) /* Wake-Up 1 */ +#define KVX_SFR_WS_WU1_SHIFT 1 +#define KVX_SFR_WS_WU1_WIDTH 1 +#define KVX_SFR_WS_WU1_WFXL_MASK _ULL(0x2) +#define KVX_SFR_WS_WU1_WFXL_CLEAR _ULL(0x2) +#define KVX_SFR_WS_WU1_WFXL_SET _ULL(0x200000000) + +#define KVX_SFR_WS_WU2_MASK _ULL(0x4) /* Wake-Up 2 */ +#define KVX_SFR_WS_WU2_SHIFT 2 +#define KVX_SFR_WS_WU2_WIDTH 1 +#define KVX_SFR_WS_WU2_WFXL_MASK _ULL(0x4) +#define KVX_SFR_WS_WU2_WFXL_CLEAR _ULL(0x4) +#define KVX_SFR_WS_WU2_WFXL_SET _ULL(0x400000000) + +#define KVX_SFR_IPE_FE_MASK _ULL(0xffff) /* Forward Events */ +#define KVX_SFR_IPE_FE_SHIFT 0 +#define KVX_SFR_IPE_FE_WIDTH 16 +#define KVX_SFR_IPE_FE_WFXL_MASK _ULL(0xffff) +#define KVX_SFR_IPE_FE_WFXL_CLEAR _ULL(0xffff) +#define KVX_SFR_IPE_FE_WFXL_SET _ULL(0xffff00000000) + +#define KVX_SFR_IPE_BE_MASK _ULL(0xffff0000) /* Backward Events */ +#define KVX_SFR_IPE_BE_SHIFT 16 +#define KVX_SFR_IPE_BE_WIDTH 16 +#define KVX_SFR_IPE_BE_WFXL_MASK _ULL(0xffff0000) +#define KVX_SFR_IPE_BE_WFXL_CLEAR _ULL(0xffff0000) +#define KVX_SFR_IPE_BE_WFXL_SET _ULL(0xffff000000000000) + +#define KVX_SFR_IPE_FM_MASK _ULL(0xffff00000000) /* Forward Mode */ +#define KVX_SFR_IPE_FM_SHIFT 32 +#define KVX_SFR_IPE_FM_WIDTH 16 +#define KVX_SFR_IPE_FM_WFXM_MASK _ULL(0xffff00000000) +#define KVX_SFR_IPE_FM_WFXM_CLEAR _ULL(0xffff) +#define KVX_SFR_IPE_FM_WFXM_SET _ULL(0xffff00000000) + +#define KVX_SFR_IPE_BM_MASK _ULL(0xffff000000000000) /* Backward Modes */ +#define KVX_SFR_IPE_BM_SHIFT 48 +#define KVX_SFR_IPE_BM_WIDTH 16 +#define KVX_SFR_IPE_BM_WFXM_MASK _ULL(0xffff000000000000) +#define KVX_SFR_IPE_BM_WFXM_CLEAR _ULL(0xffff0000) +#define KVX_SFR_IPE_BM_WFXM_SET _ULL(0xffff000000000000) + +#endif/*_ASM_KVX_SFR_DEFS_H */ diff --git a/arch/kvx/include/asm/string.h b/arch/kvx/include/asm/string.h new file mode 100644 index 0000000000..6e98910c39 --- /dev/null +++ b/arch/kvx/include/asm/string.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_STRING_H +#define _ASM_KVX_STRING_H + +/** + * FIXME AUTO: Implement optimized memcpy and memset for kvx + */ + +#endif /* _ASM_KVX_STRING_H */ + diff --git a/arch/kvx/include/asm/swab.h b/arch/kvx/include/asm/swab.h new file mode 100644 index 0000000000..35ca773059 --- /dev/null +++ b/arch/kvx/include/asm/swab.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_SWAB_H +#define _ASM_KVX_SWAB_H + +/** + * FIXME AUTO: Implement optimized byte swap using sbmm for kvx + */ + +#endif /* _ASM_KVX_SWAB_H */ + diff --git a/arch/kvx/include/asm/sys_arch.h b/arch/kvx/include/asm/sys_arch.h new file mode 100644 index 0000000000..9df32c4e72 --- /dev/null +++ b/arch/kvx/include/asm/sys_arch.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_SYS_ARCH_H +#define _ASM_KVX_SYS_ARCH_H + +#include <asm/sfr_defs.h> + +#define EXCEPTION_STRIDE 0x40 +#define EXCEPTION_ALIGNMENT 0x100 + +#define KVX_SFR_START(__sfr_reg) \ + (KVX_SFR_## __sfr_reg ## _SHIFT) + +#define KVX_SFR_END(__sfr_reg) \ + (KVX_SFR_## __sfr_reg ## _SHIFT + KVX_SFR_## __sfr_reg ## _WIDTH - 1) + +/** + * Get the value to clear a sfr + */ +#define SFR_CLEAR(__sfr, __field, __lm) \ + KVX_SFR_## __sfr ## _ ## __field ## _ ## __lm ## _CLEAR + +#define SFR_CLEAR_WFXL(__sfr, __field) SFR_CLEAR(__sfr, __field, WFXL) +#define SFR_CLEAR_WFXM(__sfr, __field) SFR_CLEAR(__sfr, __field, WFXM) + +/** + * Get the value to set a sfr. + */ +#define SFR_SET_WFXL(__sfr, __field, __val) \ + (__val << (KVX_SFR_ ## __sfr ## _ ## __field ## _SHIFT + 32)) + +#define SFR_SET_WFXM(__sfr, __field, __val) \ + (__val << (KVX_SFR_ ## __sfr ## _ ## __field ## _SHIFT)) + +/** + * Generate the mask to clear and set a value using wfx{m|l}. + */ +#define SFR_SET_VAL_WFXL(__sfr, __field, __val) \ + (SFR_SET_WFXL(__sfr, __field, __val) | SFR_CLEAR_WFXL(__sfr, __field)) +#define SFR_SET_VAL_WFXM(__sfr, __field, __val) \ + (SFR_SET_WFXM(__sfr, __field, __val) | SFR_CLEAR_WFXM(__sfr, __field)) + +#endif /* _ASM_KVX_SYS_ARCH_H */ diff --git a/arch/kvx/include/asm/types.h b/arch/kvx/include/asm/types.h new file mode 100644 index 0000000000..a24f70db55 --- /dev/null +++ b/arch/kvx/include/asm/types.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_TYPES_H +#define _ASM_KVX_TYPES_H + +#include <asm-generic/int-ll64.h> + +typedef unsigned short umode_t; + +#endif /* _ASM_KVX_TYPES_H */ + diff --git a/arch/kvx/include/asm/unaligned.h b/arch/kvx/include/asm/unaligned.h new file mode 100644 index 0000000000..74b3f34c14 --- /dev/null +++ b/arch/kvx/include/asm/unaligned.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#ifndef _ASM_KVX_UNALIGNED_H +#define _ASM_KVX_UNALIGNED_H + +#include <linux/unaligned/le_struct.h> +#include <linux/unaligned/be_byteshift.h> +#include <linux/unaligned/generic.h> + +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le + +#endif /* _ASM_KVX_UNALIGNED_H */ + diff --git a/arch/kvx/lib/Makefile b/arch/kvx/lib/Makefile new file mode 100644 index 0000000000..352e7034a6 --- /dev/null +++ b/arch/kvx/lib/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2019 Kalray Inc. +# + +obj-y += cpuinfo.o board.o dtb.o poweroff.o diff --git a/arch/kvx/lib/asm-offsets.c b/arch/kvx/lib/asm-offsets.c new file mode 100644 index 0000000000..9ab4fc4d4d --- /dev/null +++ b/arch/kvx/lib/asm-offsets.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <linux/kbuild.h> + +int main(void) +{ + return 0; +} diff --git a/arch/kvx/lib/board.c b/arch/kvx/lib/board.c new file mode 100644 index 0000000000..4d6ca6983d --- /dev/null +++ b/arch/kvx/lib/board.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <common.h> +#include <malloc.h> +#include <memory.h> +#include <asm-generic/memory_layout.h> + +static int find_memory_malloc(u32 na, u32 ns, u64 addr, u64 *membase, + u64 *memsize, const __be32 *reg) +{ + int i; + u64 memsize64 = 0, membase64 = 0; + + for (i = 0; i < na; i++) + membase64 = (membase64 << 32) | fdt32_to_cpu(*reg++); + + for (i = 0; i < ns; i++) + memsize64 = (memsize64 << 32) | fdt32_to_cpu(*reg++); + + if (addr > membase64 && addr < (membase64 + memsize64)) { + *membase = membase64; + *memsize = memsize64; + return 1; + } + + return 0; +} + +/** + * of_find_mem - Find the first memory range (from fdt) in which an address is + * contained + * @fdt: fdt blob containing memory nodes + * @addr: Address to search in available memories + * @membase: Returned memory base address + * @memsize: Returned memory size + */ +static void of_find_mem(void *fdt, u64 addr, u64 *membase, u64 *memsize) +{ + const __be32 *nap, *nsp, *reg; + u32 na, ns, reg_size; + int node, size, i, ret; + + /* Make sure FDT blob is sane */ + if (fdt_check_header(fdt) != 0) { + pr_err("Invalid device tree blob\n"); + goto err; + } + + /* Find the #address-cells and #size-cells properties */ + node = fdt_path_offset(fdt, "/"); + if (node < 0) { + pr_err("Cannot find root node\n"); + goto err; + } + + nap = fdt_getprop(fdt, node, "#address-cells", &size); + if (!nap || (size != 4)) { + pr_err("Cannot find #address-cells property"); + goto err; + } + na = fdt32_to_cpu(*nap); + + nsp = fdt_getprop(fdt, node, "#size-cells", &size); + if (!nsp || (size != 4)) { + pr_err("Cannot find #size-cells property"); + goto err; + } + ns = fdt32_to_cpu(*nap); + + node = -1; + /* Iterate on the memory devices */ + while (1) { + /* Find the memory node */ + node = fdt_node_offset_by_prop_value(fdt, node, "device_type", + "memory", + sizeof("memory")); + if (node < 0) { + pr_err("Cannot find memory node\n"); + goto err; + } + + reg_size = na + ns * sizeof(u32); + reg = fdt_getprop(fdt, node, "reg", &size); + if (size < reg_size) { + pr_err("cannot get memory range\n"); + goto err; + } + + /* Iterate on reg content */ + for (i = 0; i < size; i += reg_size) { + ret = find_memory_malloc(na, ns, addr, membase, memsize, + reg); + if (ret) + return; + reg += na + ns; + } + } +err: + pr_err("No memory, cannot continue\n"); + while (1); +} + +void __noreturn kvx_start_barebox(void) +{ + u64 memsize = 0, membase = 0; + u64 barebox_text_end = (u64) &__end; + + of_find_mem(boot_dtb, barebox_text_end, &membase, &memsize); + + mem_malloc_init((void *) barebox_text_end, + (void *) (membase + memsize)); + + start_barebox(); + + hang(); +} diff --git a/arch/kvx/lib/cpuinfo.c b/arch/kvx/lib/cpuinfo.c new file mode 100644 index 0000000000..f17a0dc6b9 --- /dev/null +++ b/arch/kvx/lib/cpuinfo.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <common.h> +#include <command.h> + +static int do_cpuinfo(int argc, char *argv[]) +{ + printf("Kalray Coolidge\n"); + + return 0; +} + +BAREBOX_CMD_START(cpuinfo) + .cmd = do_cpuinfo, + BAREBOX_CMD_DESC("show CPU information") + BAREBOX_CMD_GROUP(CMD_GRP_INFO) +BAREBOX_CMD_END diff --git a/arch/kvx/lib/dtb.c b/arch/kvx/lib/dtb.c new file mode 100644 index 0000000000..17dcab197f --- /dev/null +++ b/arch/kvx/lib/dtb.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <common.h> +#include <init.h> +#include <of.h> + +static int of_kvx_init(void) +{ + int ret; + struct device_node *root; + + root = of_unflatten_dtb(boot_dtb); + if (IS_ERR(root)) { + ret = PTR_ERR(root); + panic("Failed to parse DTB: %d\n", ret); + } + + ret = of_set_root_node(root); + if (ret) + panic("Failed to set of root node\n"); + + of_probe(); + + return 0; +} +core_initcall(of_kvx_init); diff --git a/arch/kvx/lib/poweroff.c b/arch/kvx/lib/poweroff.c new file mode 100644 index 0000000000..f2683a5835 --- /dev/null +++ b/arch/kvx/lib/poweroff.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Kalray Inc. + */ + +#include <init.h> +#include <common.h> +#include <poweroff.h> + +static void __noreturn kvx_poweroff(struct poweroff_handler *handler) +{ + register int status asm("r0") = 0; + + shutdown_barebox(); + + asm volatile ("scall 0xfff\n\t;;" + : : "r"(status) + : "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "memory"); + hang(); +} + +static int kvx_scall_poweroff_probe(struct device_d *dev) +{ + poweroff_handler_register_fn(kvx_poweroff); + + return 0; +} + +static __maybe_unused struct of_device_id kvx_scall_poweroff_id[] = { + { + .compatible = "kalray,kvx-scall-poweroff", + }, { + } +}; + +static struct driver_d kvx_scall_poweroff = { + .name = "kvx_scall_poweroff", + .probe = kvx_scall_poweroff_probe, + .of_compatible = DRV_OF_COMPAT(kvx_scall_poweroff_id), +}; + +device_platform_driver(kvx_scall_poweroff); diff --git a/commands/Kconfig b/commands/Kconfig index 7784966282..a0c2828983 100644 --- a/commands/Kconfig +++ b/commands/Kconfig @@ -1871,7 +1871,7 @@ config CMD_SMC bool depends on ARM_SMCCC prompt "PSCI test command" - default CONFIG_ARM_PSCI_DEBUG + default ARM_PSCI_DEBUG help Secure monitor code test command diff --git a/common/bootm.c b/common/bootm.c index 366f314555..299985678d 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -119,8 +119,13 @@ int bootm_load_os(struct image_data *data, unsigned long load_address) data->os_res = request_sdram_region("kernel", load_address, kernel_size); - if (!data->os_res) + if (!data->os_res) { + printf("unable to request SDRAM region for kernel at" + "0x%08llx-0x%08llx\n", + (unsigned long long)load_address, + (unsigned long long)load_address + kernel_size - 1); return -ENOMEM; + } memcpy((void *)load_address, kernel, kernel_size); return 0; } @@ -227,8 +232,13 @@ int bootm_load_initrd(struct image_data *data, unsigned long load_address) data->initrd_res = request_sdram_region("initrd", load_address, initrd_size); - if (!data->initrd_res) + if (!data->initrd_res) { + printf("unable to request SDRAM region for initrd at" + "0x%08llx-0x%08llx\n", + (unsigned long long)load_address, + (unsigned long long)load_address + initrd_size - 1); return -ENOMEM; + } memcpy((void *)load_address, initrd, initrd_size); printf("Loaded initrd from FIT image\n"); goto done1; @@ -439,8 +449,13 @@ int bootm_load_devicetree(struct image_data *data, void *fdt, data->oftree_res = request_sdram_region("oftree", load_address, fdt_size); - if (!data->oftree_res) + if (!data->oftree_res) { + printf("unable to request SDRAM region for device tree at" + "0x%08llx-0x%08llx\n", + (unsigned long long)load_address, + (unsigned long long)load_address + fdt_size - 1); return -ENOMEM; + } memcpy((void *)data->oftree_res->start, fdt, fdt_size); diff --git a/common/imd.c b/common/imd.c index 9be07fef74..526308effa 100644 --- a/common/imd.c +++ b/common/imd.c @@ -349,7 +349,7 @@ static int imd_calculate_crc32(void *input, const struct imd_header *imd_start, input += end_ofs; *crc = crc32(*crc, input, size - end_ofs); - debug("Calculated checksum from %d to %d: 0x%08x\n", end_ofs, + debug("Calculated checksum from %d to %zu: 0x%08x\n", end_ofs, end_ofs + (size - end_ofs), *crc); return 0; diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index dc7b4f276f..e3fa3896fe 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -89,26 +89,6 @@ struct regmap *dev_get_regmap(struct device_d *dev, const char *name) } /* - * of_node_to_regmap - get a regmap from a device node - * - * node: The device node - * - * Returns a pointer to the regmap or a ERR_PTR if the node has no - * regmap attached. - */ -struct regmap *of_node_to_regmap(struct device_node *node) -{ - struct regmap *map; - - list_for_each_entry(map, ®maps, list) { - if (map->dev->device_node == node) - return map; - } - - return ERR_PTR(-ENOENT); -} - -/* * regmap_write - write a register in a map * * @map: The map diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index dedbf6c4dd..c05e065651 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only config HAVE_CLK bool diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 8160620dc6..09032744a0 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed.o clk-divider.o clk-fixed-factor.o \ clk-mux.o clk-gate.o clk-composite.o \ clk-fractional-divider.o clk-conf.o \ diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index bf9b27f0f4..423605f452 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only # # Makefile for at91 specific clk # @@ -6,14 +7,16 @@ obj-y += pmc.o sckc.o obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o obj-y += clk-system.o clk-peripheral.o clk-programmable.o +obj-$(CONFIG_HAVE_AT91_AUDIO_PLL) += clk-audio-pll.o obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o -obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o -obj-$(CONFIG_SOC_AT91SAM9) += at91sam9rl.o -obj-$(CONFIG_SOC_AT91SAM9) += at91sam9x5.o -obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o -obj-$(CONFIG_SOC_SAMA5D3) += dt-compat.o -obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o +obj-$(CONFIG_HAVE_AT91_I2S_MUX_CLK) += clk-i2s-mux.o +obj-$(CONFIG_HAVE_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o +obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat.o +obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o +obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o +obj-$(CONFIG_SOC_SAMA5D3) += dt-compat.o +obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c index ac67dcc8f7..066dedf2a1 100644 --- a/drivers/clk/at91/at91sam9260.c +++ b/drivers/clk/at91/at91sam9260.c @@ -47,7 +47,7 @@ static u8 sam9260_plla_out[] = { 0, 2 }; static u16 sam9260_plla_icpll[] = { 1, 1 }; -static struct clk_range sam9260_plla_outputs[] = { +static const struct clk_range sam9260_plla_outputs[] = { { .min = 80000000, .max = 160000000 }, { .min = 150000000, .max = 240000000 }, }; @@ -64,7 +64,7 @@ static u8 sam9260_pllb_out[] = { 1 }; static u16 sam9260_pllb_icpll[] = { 1 }; -static struct clk_range sam9260_pllb_outputs[] = { +static const struct clk_range sam9260_pllb_outputs[] = { { .min = 70000000, .max = 130000000 }, }; @@ -134,7 +134,7 @@ static u8 sam9g20_plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 }; static u16 sam9g20_plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 }; -static struct clk_range sam9g20_plla_outputs[] = { +static const struct clk_range sam9g20_plla_outputs[] = { { .min = 745000000, .max = 800000000 }, { .min = 695000000, .max = 750000000 }, { .min = 645000000, .max = 700000000 }, @@ -157,7 +157,7 @@ static u8 sam9g20_pllb_out[] = { 0 }; static u16 sam9g20_pllb_icpll[] = { 0 }; -static struct clk_range sam9g20_pllb_outputs[] = { +static const struct clk_range sam9g20_pllb_outputs[] = { { .min = 30000000, .max = 100000000 }, }; @@ -188,7 +188,7 @@ static const struct clk_master_characteristics sam9261_mck_characteristics = { .divisors = { 1, 2, 4, 0 }, }; -static struct clk_range sam9261_plla_outputs[] = { +static const struct clk_range sam9261_plla_outputs[] = { { .min = 80000000, .max = 200000000 }, { .min = 190000000, .max = 240000000 }, }; @@ -205,7 +205,7 @@ static u8 sam9261_pllb_out[] = { 1 }; static u16 sam9261_pllb_icpll[] = { 1 }; -static struct clk_range sam9261_pllb_outputs[] = { +static const struct clk_range sam9261_pllb_outputs[] = { { .min = 70000000, .max = 130000000 }, }; @@ -268,7 +268,7 @@ static const struct clk_master_characteristics sam9263_mck_characteristics = { .divisors = { 1, 2, 4, 0 }, }; -static struct clk_range sam9263_pll_outputs[] = { +static const struct clk_range sam9263_pll_outputs[] = { { .min = 80000000, .max = 200000000 }, { .min = 190000000, .max = 240000000 }, }; @@ -354,7 +354,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, return; mainxtal_name = of_clk_get_parent_name(np, i); - regmap = syscon_node_to_regmap(np); + regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c index 82acb38257..ff47f94a8d 100644 --- a/drivers/clk/at91/at91sam9rl.c +++ b/drivers/clk/at91/at91sam9rl.c @@ -20,7 +20,7 @@ static const struct clk_master_characteristics sam9rl_mck_characteristics = { static u8 sam9rl_plla_out[] = { 0, 2 }; -static struct clk_range sam9rl_plla_outputs[] = { +static const struct clk_range sam9rl_plla_outputs[] = { { .min = 80000000, .max = 200000000 }, { .min = 190000000, .max = 240000000 }, }; @@ -89,7 +89,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np) return; mainxtal_name = of_clk_get_parent_name(np, i); - regmap = syscon_node_to_regmap(np); + regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c index 5e0aacfbf6..baa71aa105 100644 --- a/drivers/clk/at91/at91sam9x5.c +++ b/drivers/clk/at91/at91sam9x5.c @@ -23,7 +23,7 @@ static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 }; static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 }; -static struct clk_range plla_outputs[] = { +static const struct clk_range plla_outputs[] = { { .min = 745000000, .max = 800000000 }, { .min = 695000000, .max = 750000000 }, { .min = 645000000, .max = 700000000 }, @@ -55,6 +55,13 @@ static const struct { { .n = "pck1", .p = "prog1", .id = 9 }, }; +static const struct clk_pcr_layout at91sam9x5_pcr_layout = { + .offset = 0x10c, + .cmd = BIT(12), + .pid_mask = GENMASK(5, 0), + .div_mask = GENMASK(17, 16), +}; + struct pck { char *n; u8 id; @@ -145,13 +152,12 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, return; mainxtal_name = of_clk_get_parent_name(np, i); - regmap = syscon_node_to_regmap(np); + regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; at91sam9x5_pmc = pmc_data_allocate(PMC_MAIN + 1, - nck(at91sam9x5_systemck), - nck(at91sam9x35_periphck), 0); + nck(at91sam9x5_systemck), 31, 0); if (!at91sam9x5_pmc) return; @@ -216,7 +222,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - parent_names[4] = "mck"; + parent_names[4] = "masterck"; for (i = 0; i < 2; i++) { char *name; @@ -249,6 +255,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, for (i = 0; i < ARRAY_SIZE(at91sam9x5_periphck); i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, + &at91sam9x5_pcr_layout, at91sam9x5_periphck[i].n, "masterck", at91sam9x5_periphck[i].id, @@ -261,6 +268,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, for (i = 0; extra_pcks[i].id; i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, + &at91sam9x5_pcr_layout, extra_pcks[i].n, "masterck", extra_pcks[i].id, diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c new file mode 100644 index 0000000000..47bff32fe8 --- /dev/null +++ b/drivers/clk/at91/clk-audio-pll.c @@ -0,0 +1,512 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2016 Atmel Corporation, + * Songjun Wu <songjun.wu@atmel.com>, + * Nicolas Ferre <nicolas.ferre@atmel.com> + * Copyright (C) 2017 Free Electrons, + * Quentin Schulz <quentin.schulz@free-electrons.com> + * + * The Sama5d2 SoC has two audio PLLs (PMC and PAD) that shares the same parent + * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of + * its own parent. PMC and PAD can then divide the FRAC rate to best match the + * asked rate. + * + * Traits of FRAC clock: + * enable - clk_enable writes nd, fracr parameters and enables PLL + * rate - rate is adjustable. + * clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22)) + * parent - fixed parent. No clk_set_parent support + * + * Traits of PMC clock: + * enable - clk_enable writes qdpmc, and enables PMC output + * rate - rate is adjustable. + * clk->rate = parent->rate / (qdpmc + 1) + * parent - fixed parent. No clk_set_parent support + * + * Traits of PAD clock: + * enable - clk_enable writes divisors and enables PAD output + * rate - rate is adjustable. + * clk->rate = parent->rate / (qdaudio * div)) + * parent - fixed parent. No clk_set_parent support + */ + +#include <common.h> +#include <clock.h> +#include <of.h> +#include <linux/list.h> +#include <linux/clk.h> +#include <linux/clk/at91_pmc.h> +#include <mfd/syscon.h> +#include <regmap.h> + +#include "pmc.h" + +#define AUDIO_PLL_DIV_FRAC BIT(22) +#define AUDIO_PLL_ND_MAX (AT91_PMC_AUDIO_PLL_ND_MASK >> \ + AT91_PMC_AUDIO_PLL_ND_OFFSET) + +#define AUDIO_PLL_QDPAD(qd, div) ((AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(qd) & \ + AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK) | \ + (AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \ + AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK)) + +#define AUDIO_PLL_QDPMC_MAX (AT91_PMC_AUDIO_PLL_QDPMC_MASK >> \ + AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) + +#define AUDIO_PLL_FOUT_MIN 620000000UL +#define AUDIO_PLL_FOUT_MAX 700000000UL + +struct clk_audio_frac { + struct clk clk; + struct regmap *regmap; + u32 fracr; + u8 nd; + const char *parent_name; +}; + +struct clk_audio_pad { + struct clk clk; + struct regmap *regmap; + u8 qdaudio; + u8 div; + const char *parent_name; +}; + +struct clk_audio_pmc { + struct clk clk; + struct regmap *regmap; + u8 qdpmc; + const char *parent_name; +}; + +#define to_clk_audio_frac(clk) container_of(clk, struct clk_audio_frac, clk) +#define to_clk_audio_pad(clk) container_of(clk, struct clk_audio_pad, clk) +#define to_clk_audio_pmc(clk) container_of(clk, struct clk_audio_pmc, clk) + +static int clk_audio_pll_frac_enable(struct clk *clk) +{ + struct clk_audio_frac *frac = to_clk_audio_frac(clk); + + regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_RESETN, 0); + regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_RESETN, + AT91_PMC_AUDIO_PLL_RESETN); + regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL1, + AT91_PMC_AUDIO_PLL_FRACR_MASK, frac->fracr); + + /* + * reset and enable have to be done in 2 separated writes + * for AT91_PMC_AUDIO_PLL0 + */ + regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_PLLEN | + AT91_PMC_AUDIO_PLL_ND_MASK, + AT91_PMC_AUDIO_PLL_PLLEN | + AT91_PMC_AUDIO_PLL_ND(frac->nd)); + + return 0; +} + +static int clk_audio_pll_pad_enable(struct clk *clk) +{ + struct clk_audio_pad *apad_ck = to_clk_audio_pad(clk); + + regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL1, + AT91_PMC_AUDIO_PLL_QDPAD_MASK, + AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div)); + regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_PADEN, AT91_PMC_AUDIO_PLL_PADEN); + + return 0; +} + +static int clk_audio_pll_pmc_enable(struct clk *clk) +{ + struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(clk); + + regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_PMCEN | + AT91_PMC_AUDIO_PLL_QDPMC_MASK, + AT91_PMC_AUDIO_PLL_PMCEN | + AT91_PMC_AUDIO_PLL_QDPMC(apmc_ck->qdpmc)); + return 0; +} + +static void clk_audio_pll_frac_disable(struct clk *clk) +{ + struct clk_audio_frac *frac = to_clk_audio_frac(clk); + + regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_PLLEN, 0); + /* do it in 2 separated writes */ + regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_RESETN, 0); +} + +static void clk_audio_pll_pad_disable(struct clk *clk) +{ + struct clk_audio_pad *apad_ck = to_clk_audio_pad(clk); + + regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_PADEN, 0); +} + +static void clk_audio_pll_pmc_disable(struct clk *clk) +{ + struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(clk); + + regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_PMCEN, 0); +} + +static unsigned long clk_audio_pll_fout(unsigned long parent_rate, + unsigned long nd, unsigned long fracr) +{ + unsigned long long fr = (unsigned long long)parent_rate * fracr; + + pr_debug("A PLL: %s, fr = %llu\n", __func__, fr); + + fr = DIV_ROUND_CLOSEST_ULL(fr, AUDIO_PLL_DIV_FRAC); + + pr_debug("A PLL: %s, fr = %llu\n", __func__, fr); + + return parent_rate * (nd + 1) + fr; +} + +static unsigned long clk_audio_pll_frac_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct clk_audio_frac *frac = to_clk_audio_frac(clk); + unsigned long fout; + + fout = clk_audio_pll_fout(parent_rate, frac->nd, frac->fracr); + + pr_debug("A PLL: %s, fout = %lu (nd = %u, fracr = %lu)\n", __func__, + fout, frac->nd, (unsigned long)frac->fracr); + + return fout; +} + +static unsigned long clk_audio_pll_pad_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct clk_audio_pad *apad_ck = to_clk_audio_pad(clk); + unsigned long apad_rate = 0; + + if (apad_ck->qdaudio && apad_ck->div) + apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div); + + pr_debug("A PLL/PAD: %s, apad_rate = %lu (div = %u, qdaudio = %u)\n", + __func__, apad_rate, apad_ck->div, apad_ck->qdaudio); + + return apad_rate; +} + +static unsigned long clk_audio_pll_pmc_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(clk); + unsigned long apmc_rate = 0; + + apmc_rate = parent_rate / (apmc_ck->qdpmc + 1); + + pr_debug("A PLL/PMC: %s, apmc_rate = %lu (qdpmc = %u)\n", __func__, + apmc_rate, apmc_ck->qdpmc); + + return apmc_rate; +} + +static int clk_audio_pll_frac_compute_frac(unsigned long rate, + unsigned long parent_rate, + unsigned long *nd, + unsigned long *fracr) +{ + unsigned long long tmp, rem; + + if (!rate) + return -EINVAL; + + tmp = rate; + rem = do_div(tmp, parent_rate); + if (!tmp || tmp >= AUDIO_PLL_ND_MAX) + return -EINVAL; + + *nd = tmp - 1; + + tmp = rem * AUDIO_PLL_DIV_FRAC; + tmp = DIV_ROUND_CLOSEST_ULL(tmp, parent_rate); + if (tmp > AT91_PMC_AUDIO_PLL_FRACR_MASK) + return -EINVAL; + + /* we can cast here as we verified the bounds just above */ + *fracr = (unsigned long)tmp; + + return 0; +} + +static long clk_audio_pll_pad_round_rate(struct clk *clk, unsigned long rate, + unsigned long *parent_rate) +{ + struct clk *pclk = clk_get_parent(clk); + long best_rate = -EINVAL; + unsigned long best_parent_rate; + unsigned long tmp_qd; + u32 div; + long tmp_rate; + int tmp_diff; + int best_diff = -1; + + pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__, + rate, *parent_rate); + + /* + * Rate divisor is actually made of two different divisors, multiplied + * between themselves before dividing the rate. + * tmp_qd goes from 1 to 31 and div is either 2 or 3. + * In order to avoid testing twice the rate divisor (e.g. divisor 12 can + * be found with (tmp_qd, div) = (2, 6) or (3, 4)), we remove any loop + * for a rate divisor when div is 2 and tmp_qd is a multiple of 3. + * We cannot inverse it (condition div is 3 and tmp_qd is even) or we + * would miss some rate divisor that aren't reachable with div being 2 + * (e.g. rate divisor 90 is made with div = 3 and tmp_qd = 30, thus + * tmp_qd is even so we skip it because we think div 2 could make this + * rate divisor which isn't possible since tmp_qd has to be <= 31). + */ + for (tmp_qd = 1; tmp_qd < AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX; tmp_qd++) + for (div = 2; div <= 3; div++) { + if (div == 2 && tmp_qd % 3 == 0) + continue; + + best_parent_rate = clk_round_rate(pclk, + rate * tmp_qd * div); + tmp_rate = best_parent_rate / (div * tmp_qd); + tmp_diff = abs(rate - tmp_rate); + + if (best_diff < 0 || best_diff > tmp_diff) { + *parent_rate = best_parent_rate; + best_rate = tmp_rate; + best_diff = tmp_diff; + } + } + + pr_debug("A PLL/PAD: %s, best_rate = %ld, best_parent_rate = %lu\n", + __func__, best_rate, best_parent_rate); + + return best_rate; +} + +static long clk_audio_pll_pmc_round_rate(struct clk *clk, unsigned long rate, + unsigned long *parent_rate) +{ + struct clk *pclk = clk_get_parent(clk); + long best_rate = -EINVAL; + unsigned long best_parent_rate = 0; + u32 tmp_qd = 0, div; + long tmp_rate; + int tmp_diff; + int best_diff = -1; + + pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__, + rate, *parent_rate); + + if (!rate) + return 0; + + best_parent_rate = clk_round_rate(pclk, 1); + div = max(best_parent_rate / rate, 1UL); + for (; div <= AUDIO_PLL_QDPMC_MAX; div++) { + best_parent_rate = clk_round_rate(pclk, rate * div); + tmp_rate = best_parent_rate / div; + tmp_diff = abs(rate - tmp_rate); + + if (best_diff < 0 || best_diff > tmp_diff) { + *parent_rate = best_parent_rate; + best_rate = tmp_rate; + best_diff = tmp_diff; + tmp_qd = div; + if (!best_diff) + break; /* got exact match */ + } + } + + pr_debug("A PLL/PMC: %s, best_rate = %ld, best_parent_rate = %lu (qd = %d)\n", + __func__, best_rate, *parent_rate, tmp_qd - 1); + + return best_rate; +} + +static int clk_audio_pll_frac_set_rate(struct clk *clk, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_audio_frac *frac = to_clk_audio_frac(clk); + unsigned long fracr, nd; + int ret; + + pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate, + parent_rate); + + if (rate < AUDIO_PLL_FOUT_MIN || rate > AUDIO_PLL_FOUT_MAX) + return -EINVAL; + + ret = clk_audio_pll_frac_compute_frac(rate, parent_rate, &nd, &fracr); + if (ret) + return ret; + + frac->nd = nd; + frac->fracr = fracr; + + return 0; +} + +static int clk_audio_pll_pad_set_rate(struct clk *clk, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_audio_pad *apad_ck = to_clk_audio_pad(clk); + u8 tmp_div; + + pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__, + rate, parent_rate); + + if (!rate) + return -EINVAL; + + tmp_div = parent_rate / rate; + if (tmp_div % 3 == 0) { + apad_ck->qdaudio = tmp_div / 3; + apad_ck->div = 3; + } else { + apad_ck->qdaudio = tmp_div / 2; + apad_ck->div = 2; + } + + return 0; +} + +static int clk_audio_pll_pmc_set_rate(struct clk *clk, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(clk); + + if (!rate) + return -EINVAL; + + pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__, + rate, parent_rate); + + apmc_ck->qdpmc = parent_rate / rate - 1; + + return 0; +} + +static const struct clk_ops audio_pll_frac_ops = { + .enable = clk_audio_pll_frac_enable, + .disable = clk_audio_pll_frac_disable, + .recalc_rate = clk_audio_pll_frac_recalc_rate, + .set_rate = clk_audio_pll_frac_set_rate, +}; + +static const struct clk_ops audio_pll_pad_ops = { + .enable = clk_audio_pll_pad_enable, + .disable = clk_audio_pll_pad_disable, + .recalc_rate = clk_audio_pll_pad_recalc_rate, + .round_rate = clk_audio_pll_pad_round_rate, + .set_rate = clk_audio_pll_pad_set_rate, +}; + +static const struct clk_ops audio_pll_pmc_ops = { + .enable = clk_audio_pll_pmc_enable, + .disable = clk_audio_pll_pmc_disable, + .recalc_rate = clk_audio_pll_pmc_recalc_rate, + .round_rate = clk_audio_pll_pmc_round_rate, + .set_rate = clk_audio_pll_pmc_set_rate, +}; + +struct clk * __init +at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name, + const char *parent_name) +{ + struct clk_audio_frac *frac_ck; + int ret; + + frac_ck = kzalloc(sizeof(*frac_ck), GFP_KERNEL); + if (!frac_ck) + return ERR_PTR(-ENOMEM); + + frac_ck->clk.name = name; + frac_ck->clk.ops = &audio_pll_frac_ops; + frac_ck->parent_name = parent_name; + frac_ck->clk.parent_names = &frac_ck->parent_name; + frac_ck->clk.num_parents = 1; + /* frac_ck->clk.flags = CLK_SET_RATE_GATE; */ + + frac_ck->regmap = regmap; + + ret = clk_register(&frac_ck->clk); + if (ret) { + kfree(frac_ck); + return ERR_PTR(ret); + } + + return &frac_ck->clk; +} + +struct clk * __init +at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name, + const char *parent_name) +{ + struct clk_audio_pad *apad_ck; + int ret; + + apad_ck = kzalloc(sizeof(*apad_ck), GFP_KERNEL); + if (!apad_ck) + return ERR_PTR(-ENOMEM); + + apad_ck->clk.name = name; + apad_ck->clk.ops = &audio_pll_pad_ops; + apad_ck->parent_name = parent_name; + apad_ck->clk.parent_names = &apad_ck->parent_name; + apad_ck->clk.num_parents = 1; + /* apad_ck->clk.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT; */ + + apad_ck->regmap = regmap; + + ret = clk_register(&apad_ck->clk); + if (ret) { + kfree(apad_ck); + return ERR_PTR(ret); + } + + return &apad_ck->clk; +} + +struct clk * __init +at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name, + const char *parent_name) +{ + struct clk_audio_pmc *apmc_ck; + int ret; + + apmc_ck = kzalloc(sizeof(*apmc_ck), GFP_KERNEL); + if (!apmc_ck) + return ERR_PTR(-ENOMEM); + + apmc_ck->clk.name = name; + apmc_ck->clk.ops = &audio_pll_pmc_ops; + apmc_ck->parent_name = parent_name; + apmc_ck->clk.parent_names = &apmc_ck->parent_name; + apmc_ck->clk.num_parents = 1; + /* apmc_ck.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT; */ + + apmc_ck->regmap = regmap; + + ret = clk_register(&apmc_ck->clk); + if (ret) { + kfree(apmc_ck); + return ERR_PTR(ret); + } + + return &apmc_ck->clk; +} diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index 396c35f3a7..56b800facb 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -1,14 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2015 Atmel Corporation, * Nicolas Ferre <nicolas.ferre@atmel.com> * * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> @@ -19,18 +14,23 @@ #include <linux/clk/at91_pmc.h> #include <mfd/syscon.h> #include <regmap.h> +#include <linux/bitfield.h> #include "pmc.h" #define GENERATED_MAX_DIV 255 +#define GCK_INDEX_DT_AUDIO_PLL 5 + struct clk_generated { struct clk hw; struct regmap *regmap; struct clk_range range; u32 id; u32 gckdiv; + const struct clk_pcr_layout *layout; u8 parent_id; + bool audio_pll_allowed; }; #define to_clk_generated(hw) \ @@ -43,14 +43,14 @@ static int clk_generated_enable(struct clk *hw) pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", __func__, gck->gckdiv, gck->parent_id); - regmap_write(gck->regmap, AT91_PMC_PCR, - (gck->id & AT91_PMC_PCR_PID_MASK)); - regmap_update_bits(gck->regmap, AT91_PMC_PCR, - AT91_PMC_PCR_GCKDIV_MASK | AT91_PMC_PCR_GCKCSS_MASK | - AT91_PMC_PCR_CMD | AT91_PMC_PCR_GCKEN, - AT91_PMC_PCR_GCKCSS(gck->parent_id) | - AT91_PMC_PCR_CMD | - AT91_PMC_PCR_GCKDIV(gck->gckdiv) | + regmap_write(gck->regmap, gck->layout->offset, + (gck->id & gck->layout->pid_mask)); + regmap_update_bits(gck->regmap, gck->layout->offset, + AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask | + gck->layout->cmd | AT91_PMC_PCR_GCKEN, + field_prep(gck->layout->gckcss_mask, gck->parent_id) | + gck->layout->cmd | + FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) | AT91_PMC_PCR_GCKEN); return 0; } @@ -59,11 +59,11 @@ static void clk_generated_disable(struct clk *hw) { struct clk_generated *gck = to_clk_generated(hw); - regmap_write(gck->regmap, AT91_PMC_PCR, - (gck->id & AT91_PMC_PCR_PID_MASK)); - regmap_update_bits(gck->regmap, AT91_PMC_PCR, - AT91_PMC_PCR_CMD | AT91_PMC_PCR_GCKEN, - AT91_PMC_PCR_CMD); + regmap_write(gck->regmap, gck->layout->offset, + (gck->id & gck->layout->pid_mask)); + regmap_update_bits(gck->regmap, gck->layout->offset, + gck->layout->cmd | AT91_PMC_PCR_GCKEN, + gck->layout->cmd); } static int clk_generated_is_enabled(struct clk *hw) @@ -71,9 +71,9 @@ static int clk_generated_is_enabled(struct clk *hw) struct clk_generated *gck = to_clk_generated(hw); unsigned int status; - regmap_write(gck->regmap, AT91_PMC_PCR, - (gck->id & AT91_PMC_PCR_PID_MASK)); - regmap_read(gck->regmap, AT91_PMC_PCR, &status); + regmap_write(gck->regmap, gck->layout->offset, + (gck->id & gck->layout->pid_mask)); + regmap_read(gck->regmap, gck->layout->offset, &status); return status & AT91_PMC_PCR_GCKEN ? 1 : 0; } @@ -151,18 +151,17 @@ static void clk_generated_startup(struct clk_generated *gck) { u32 tmp; - regmap_write(gck->regmap, AT91_PMC_PCR, - (gck->id & AT91_PMC_PCR_PID_MASK)); - regmap_read(gck->regmap, AT91_PMC_PCR, &tmp); + regmap_write(gck->regmap, gck->layout->offset, + (gck->id & gck->layout->pid_mask)); + regmap_read(gck->regmap, gck->layout->offset, &tmp); - gck->parent_id = (tmp & AT91_PMC_PCR_GCKCSS_MASK) - >> AT91_PMC_PCR_GCKCSS_OFFSET; - gck->gckdiv = (tmp & AT91_PMC_PCR_GCKDIV_MASK) - >> AT91_PMC_PCR_GCKDIV_OFFSET; + gck->parent_id = field_get(gck->layout->gckcss_mask, tmp); + gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp); } struct clk * __init at91_clk_register_generated(struct regmap *regmap, + const struct clk_pcr_layout *layout, const char *name, const char **parent_names, u8 num_parents, u8 id, bool pll_audio, const struct clk_range *range) @@ -184,18 +183,21 @@ at91_clk_register_generated(struct regmap *regmap, gck->hw.parent_names = xmemdup(parent_names, parents_array_size); gck->hw.num_parents = num_parents; - /* gck->hw.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; */ + /* gck->hw.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_PARENT; */ gck->regmap = regmap; gck->range = *range; - /* gck->audio_pll_allowed = pll_audio; */ + gck->audio_pll_allowed = pll_audio; + gck->layout = layout; + clk_generated_startup(gck); hw = &gck->hw; ret = clk_register(&gck->hw); if (ret) { kfree(gck); hw = ERR_PTR(ret); - } else - clk_generated_startup(gck); + } else { + pmc_register_id(id); + } return hw; } diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c index 31906a9e29..6052886cca 100644 --- a/drivers/clk/at91/clk-h32mx.c +++ b/drivers/clk/at91/clk-h32mx.c @@ -1,15 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * clk-h32mx.c * * Copyright (C) 2014 Atmel * * Alexandre Belloni <alexandre.belloni@free-electrons.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> @@ -88,7 +83,7 @@ static const struct clk_ops h32mx_ops = { .set_rate = clk_sama5d4_h32mx_set_rate, }; -struct clk * +struct clk * __init at91_clk_register_h32mx(struct regmap *regmap, const char *name, const char *parent_name) { diff --git a/drivers/clk/at91/clk-i2s-mux.c b/drivers/clk/at91/clk-i2s-mux.c new file mode 100644 index 0000000000..1418ec8662 --- /dev/null +++ b/drivers/clk/at91/clk-i2s-mux.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Microchip Technology Inc, + * Codrin Ciubotariu <codrin.ciubotariu@microchip.com> + * + * + */ + +#include <common.h> +#include <clock.h> +#include <of.h> +#include <linux/list.h> +#include <linux/clk.h> +#include <linux/clk/at91_pmc.h> +#include <mfd/syscon.h> +#include <regmap.h> + +#include <soc/at91/atmel-sfr.h> + +#include "pmc.h" + +#define I2S_MUX_SOURCE_MAX 2 + +struct clk_i2s_mux { + struct clk clk; + struct regmap *regmap; + u8 bus_id; + const char *parent_names[I2S_MUX_SOURCE_MAX]; +}; + +#define to_clk_i2s_mux(clk) container_of(clk, struct clk_i2s_mux, clk) + +static int clk_i2s_mux_get_parent(struct clk *clk) +{ + struct clk_i2s_mux *mux = to_clk_i2s_mux(clk); + u32 val; + + regmap_read(mux->regmap, AT91_SFR_I2SCLKSEL, &val); + + return (val & BIT(mux->bus_id)) >> mux->bus_id; +} + +static int clk_i2s_mux_set_parent(struct clk *clk, u8 index) +{ + struct clk_i2s_mux *mux = to_clk_i2s_mux(clk); + + return regmap_update_bits(mux->regmap, AT91_SFR_I2SCLKSEL, + BIT(mux->bus_id), index << mux->bus_id); +} + +static const struct clk_ops clk_i2s_mux_ops = { + .set_rate = clk_parent_set_rate, + .round_rate = clk_parent_round_rate, + .get_parent = clk_i2s_mux_get_parent, + .set_parent = clk_i2s_mux_set_parent, +}; + +struct clk * __init +at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, + const char * const *parent_names, + unsigned int num_parents, u8 bus_id) +{ + struct clk_i2s_mux *i2s_ck; + int ret; + + i2s_ck = kzalloc(sizeof(*i2s_ck), GFP_KERNEL); + if (!i2s_ck) + return ERR_PTR(-ENOMEM); + + i2s_ck->clk.name = name; + i2s_ck->clk.ops = &clk_i2s_mux_ops; + memcpy(i2s_ck->parent_names, parent_names, + num_parents * sizeof(i2s_ck->parent_names[0])); + i2s_ck->clk.parent_names = &i2s_ck->parent_names[0]; + i2s_ck->clk.num_parents = num_parents; + + i2s_ck->bus_id = bus_id; + i2s_ck->regmap = regmap; + + ret = clk_register(&i2s_ck->clk); + if (ret) { + kfree(i2s_ck); + return ERR_PTR(ret); + } + + return &i2s_ck->clk; +} diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index abae35566c..08abb1673b 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -1,11 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> #include <clock.h> @@ -26,6 +21,10 @@ #define MOR_KEY_MASK (0xff << 16) +#define clk_main_parent_select(s) (((s) & \ + (AT91_PMC_MOSCEN | \ + AT91_PMC_OSCBYPASS)) ? 1 : 0) + struct clk_main_osc { struct clk clk; struct regmap *regmap; @@ -119,7 +118,7 @@ static int clk_main_osc_is_enabled(struct clk *clk) regmap_read(regmap, AT91_PMC_SR, &status); - return (status & AT91_PMC_MOSCS) && (tmp & AT91_PMC_MOSCEN); + return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp); } static const struct clk_ops main_osc_ops = { @@ -128,7 +127,7 @@ static const struct clk_ops main_osc_ops = { .is_enabled = clk_main_osc_is_enabled, }; -struct clk * +struct clk * __init at91_clk_register_main_osc(struct regmap *regmap, const char *name, const char *parent_name, @@ -234,7 +233,7 @@ static const struct clk_ops main_rc_osc_ops = { .recalc_rate = clk_main_rc_osc_recalc_rate, }; -struct clk * +struct clk * __init at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name, u32 frequency, u32 accuracy) @@ -325,7 +324,7 @@ static const struct clk_ops rm9200_main_ops = { .recalc_rate = clk_rm9200_main_recalc_rate, }; -struct clk * +struct clk * __init at91_clk_register_rm9200_main(struct regmap *regmap, const char *name, const char *parent_name) @@ -422,7 +421,7 @@ static int clk_sam9x5_main_get_parent(struct clk *clk) regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status); - return status & AT91_PMC_MOSCEN ? 1 : 0; + return clk_main_parent_select(status); } static const struct clk_ops sam9x5_main_ops = { @@ -433,7 +432,7 @@ static const struct clk_ops sam9x5_main_ops = { .get_parent = clk_sam9x5_main_get_parent, }; -struct clk * +struct clk * __init at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name, const char **parent_names, @@ -462,7 +461,7 @@ at91_clk_register_sam9x5_main(struct regmap *regmap, clkmain->regmap = regmap; regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status); - clkmain->parent = status & AT91_PMC_MOSCEN ? 1 : 0; + clkmain->parent = clk_main_parent_select(status); ret = clk_register(&clkmain->clk); if (ret) { diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index f7a0fb1d18..4e3b512aaa 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -1,11 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> #include <clock.h> @@ -32,6 +27,7 @@ struct clk_master { const struct clk_master_layout *layout; const struct clk_master_characteristics *characteristics; const char *parents[MASTER_SOURCE_MAX]; + u32 mckr; }; static inline bool clk_master_ready(struct regmap *regmap) @@ -72,7 +68,7 @@ static unsigned long clk_master_recalc_rate(struct clk *clk, master->characteristics; unsigned int mckr; - regmap_read(master->regmap, AT91_PMC_MCKR, &mckr); + regmap_read(master->regmap, master->layout->offset, &mckr); mckr &= layout->mask; pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK; @@ -98,7 +94,7 @@ static int clk_master_get_parent(struct clk *clk) struct clk_master *master = to_clk_master(clk); unsigned int mckr; - regmap_read(master->regmap, AT91_PMC_MCKR, &mckr); + regmap_read(master->regmap, master->layout->offset, &mckr); return mckr & AT91_PMC_CSS; } @@ -110,7 +106,7 @@ static const struct clk_ops master_ops = { .get_parent = clk_master_get_parent, }; -struct clk * +struct clk * __init at91_clk_register_master(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, @@ -149,9 +145,11 @@ at91_clk_register_master(struct regmap *regmap, const struct clk_master_layout at91rm9200_master_layout = { .mask = 0x31F, .pres_shift = 2, + .offset = AT91_PMC_MCKR, }; const struct clk_master_layout at91sam9x5_master_layout = { .mask = 0x373, .pres_shift = 4, + .offset = AT91_PMC_MCKR, }; diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c index 00852672da..2b9008eb2c 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -1,11 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> @@ -42,6 +37,7 @@ struct clk_sam9x5_peripheral { struct clk_range range; u32 id; u32 div; + const struct clk_pcr_layout *layout; bool auto_div; const char *parent; }; @@ -99,7 +95,7 @@ static const struct clk_ops peripheral_ops = { .is_enabled = clk_peripheral_is_enabled, }; -struct clk * +struct clk * __init at91_clk_register_peripheral(struct regmap *regmap, const char *name, const char *parent_name, u32 id) { @@ -164,13 +160,13 @@ static int clk_sam9x5_peripheral_enable(struct clk *clk) if (periph->id < PERIPHERAL_ID_MIN) return 0; - regmap_write(periph->regmap, AT91_PMC_PCR, - (periph->id & AT91_PMC_PCR_PID_MASK)); - regmap_write_bits(periph->regmap, AT91_PMC_PCR, - AT91_PMC_PCR_DIV_MASK | AT91_PMC_PCR_CMD | + regmap_write(periph->regmap, periph->layout->offset, + (periph->id & periph->layout->pid_mask)); + regmap_write_bits(periph->regmap, periph->layout->offset, + periph->layout->div_mask | periph->layout->cmd | AT91_PMC_PCR_EN, - AT91_PMC_PCR_DIV(periph->div) | - AT91_PMC_PCR_CMD | + field_prep(periph->layout->div_mask, periph->div) | + periph->layout->cmd | AT91_PMC_PCR_EN); return 0; @@ -183,11 +179,11 @@ static void clk_sam9x5_peripheral_disable(struct clk *clk) if (periph->id < PERIPHERAL_ID_MIN) return; - regmap_write(periph->regmap, AT91_PMC_PCR, - (periph->id & AT91_PMC_PCR_PID_MASK)); - regmap_write_bits(periph->regmap, AT91_PMC_PCR, - AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD, - AT91_PMC_PCR_CMD); + regmap_write(periph->regmap, periph->layout->offset, + (periph->id & periph->layout->pid_mask)); + regmap_write_bits(periph->regmap, periph->layout->offset, + AT91_PMC_PCR_EN | periph->layout->cmd, + periph->layout->cmd); } static int clk_sam9x5_peripheral_is_enabled(struct clk *clk) @@ -198,9 +194,9 @@ static int clk_sam9x5_peripheral_is_enabled(struct clk *clk) if (periph->id < PERIPHERAL_ID_MIN) return 1; - regmap_write(periph->regmap, AT91_PMC_PCR, - (periph->id & AT91_PMC_PCR_PID_MASK)); - regmap_read(periph->regmap, AT91_PMC_PCR, &status); + regmap_write(periph->regmap, periph->layout->offset, + (periph->id & periph->layout->pid_mask)); + regmap_read(periph->regmap, periph->layout->offset, &status); return status & AT91_PMC_PCR_EN ? 1 : 0; } @@ -215,12 +211,12 @@ clk_sam9x5_peripheral_recalc_rate(struct clk *clk, if (periph->id < PERIPHERAL_ID_MIN) return parent_rate; - regmap_write(periph->regmap, AT91_PMC_PCR, - (periph->id & AT91_PMC_PCR_PID_MASK)); - regmap_read(periph->regmap, AT91_PMC_PCR, &status); + regmap_write(periph->regmap, periph->layout->offset, + (periph->id & periph->layout->pid_mask)); + regmap_read(periph->regmap, periph->layout->offset, &status); if (status & AT91_PMC_PCR_EN) { - periph->div = PERIPHERAL_RSHIFT(status); + periph->div = field_get(periph->layout->div_mask, status); periph->auto_div = false; } else { clk_sam9x5_peripheral_autodiv(periph); @@ -311,8 +307,9 @@ static const struct clk_ops sam9x5_peripheral_ops = { .set_rate = clk_sam9x5_peripheral_set_rate, }; -struct clk * +struct clk * __init at91_clk_register_sam9x5_peripheral(struct regmap *regmap, + const struct clk_pcr_layout *layout, const char *name, const char *parent_name, u32 id, const struct clk_range *range) { @@ -336,7 +333,9 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regmap, periph->id = id; periph->div = 0; periph->regmap = regmap; - periph->auto_div = true; + if (layout->div_mask) + periph->auto_div = true; + periph->layout = layout; periph->range = *range; ret = clk_register(&periph->clk); @@ -346,6 +345,7 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regmap, } clk_sam9x5_peripheral_autodiv(periph); + pmc_register_id(id); return &periph->clk; } diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c index bc504e8a95..5cb156e784 100644 --- a/drivers/clk/at91/clk-pll.c +++ b/drivers/clk/at91/clk-pll.c @@ -1,11 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> @@ -121,19 +116,11 @@ static unsigned long clk_pll_recalc_rate(struct clk *clk, unsigned long parent_rate) { struct clk_pll *pll = to_clk_pll(clk); - unsigned int pllr; - u16 mul; - u8 div; - - regmap_read(pll->regmap, PLL_REG(pll->id), &pllr); - - div = PLL_DIV(pllr); - mul = PLL_MUL(pllr, pll->layout); - if (!div || !mul) + if (!pll->div || !pll->mul) return 0; - return (parent_rate / div) * (mul + 1); + return (parent_rate / pll->div) * (pll->mul + 1); } static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate, @@ -285,7 +272,7 @@ static const struct clk_ops pll_ops = { .set_rate = clk_pll_set_rate, }; -struct clk * +struct clk * __init at91_clk_register_pll(struct regmap *regmap, const char *name, const char *parent_name, u8 id, const struct clk_pll_layout *layout, diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c index 98d79ef599..1cbb61bb2c 100644 --- a/drivers/clk/at91/clk-plldiv.c +++ b/drivers/clk/at91/clk-plldiv.c @@ -1,11 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> @@ -78,7 +73,7 @@ static const struct clk_ops plldiv_ops = { .set_rate = clk_plldiv_set_rate, }; -struct clk * +struct clk * __init at91_clk_register_plldiv(struct regmap *regmap, const char *name, const char *parent_name) { diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c index 857ede1ca9..26c36a882d 100644 --- a/drivers/clk/at91/clk-programmable.c +++ b/drivers/clk/at91/clk-programmable.c @@ -1,11 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> @@ -23,8 +18,7 @@ #define PROG_ID_MAX 7 #define PROG_STATUS_MASK(id) (1 << ((id) + 8)) -#define PROG_PRES_MASK 0x7 -#define PROG_PRES(layout, pckr) ((pckr >> layout->pres_shift) & PROG_PRES_MASK) +#define PROG_PRES(layout, pckr) ((pckr >> layout->pres_shift) & layout->pres_mask) #define PROG_MAX_RM9200_CSS 3 struct clk_programmable { @@ -41,11 +35,18 @@ static unsigned long clk_programmable_recalc_rate(struct clk *clk, unsigned long parent_rate) { struct clk_programmable *prog = to_clk_programmable(clk); + const struct clk_programmable_layout *layout = prog->layout; unsigned int pckr; + unsigned long rate; regmap_read(prog->regmap, AT91_PMC_PCKR(prog->id), &pckr); - return parent_rate >> PROG_PRES(prog->layout, pckr); + if (layout->is_pres_direct) + rate = parent_rate / (PROG_PRES(layout, pckr) + 1); + else + rate = parent_rate >> PROG_PRES(layout, pckr); + + return rate; } static int clk_programmable_set_parent(struct clk *clk, u8 index) @@ -93,25 +94,29 @@ static int clk_programmable_set_rate(struct clk *clk, unsigned long rate, struct clk_programmable *prog = to_clk_programmable(clk); const struct clk_programmable_layout *layout = prog->layout; unsigned long div = parent_rate / rate; - unsigned int pckr; int shift = 0; - regmap_read(prog->regmap, AT91_PMC_PCKR(prog->id), &pckr); - if (!div) return -EINVAL; - shift = fls(div) - 1; + if (layout->is_pres_direct) { + shift = div - 1; - if (div != (1 << shift)) - return -EINVAL; + if (shift > layout->pres_mask) + return -EINVAL; + } else { + shift = fls(div) - 1; - if (shift >= PROG_PRES_MASK) - return -EINVAL; + if (div != (1 << shift)) + return -EINVAL; + + if (shift >= layout->pres_mask) + return -EINVAL; + } regmap_write_bits(prog->regmap, AT91_PMC_PCKR(prog->id), - PROG_PRES_MASK << layout->pres_shift, - shift << layout->pres_shift); + layout->pres_mask << layout->pres_shift, + shift << layout->pres_shift); return 0; } @@ -123,7 +128,7 @@ static const struct clk_ops programmable_ops = { .set_rate = clk_programmable_set_rate, }; -struct clk * +struct clk * __init at91_clk_register_programmable(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents, u8 id, @@ -157,23 +162,31 @@ at91_clk_register_programmable(struct regmap *regmap, return ERR_PTR(ret); } + pmc_register_pck(id); + return &prog->clk; } const struct clk_programmable_layout at91rm9200_programmable_layout = { + .pres_mask = 0x7, .pres_shift = 2, .css_mask = 0x3, .have_slck_mck = 0, + .is_pres_direct = 0, }; const struct clk_programmable_layout at91sam9g45_programmable_layout = { + .pres_mask = 0x7, .pres_shift = 2, .css_mask = 0x3, .have_slck_mck = 1, + .is_pres_direct = 0, }; const struct clk_programmable_layout at91sam9x5_programmable_layout = { + .pres_mask = 0x7, .pres_shift = 4, .css_mask = 0x7, .have_slck_mck = 0, + .is_pres_direct = 0, }; diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c new file mode 100644 index 0000000000..9ca77f8722 --- /dev/null +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * + */ + +#include <common.h> +#include <clock.h> +#include <of.h> +#include <linux/list.h> +#include <linux/clk.h> +#include <linux/clk/at91_pmc.h> +#include <mfd/syscon.h> +#include <regmap.h> +#include <linux/bitfield.h> + +#include "pmc.h" + +#define PMC_PLL_CTRL0 0xc +#define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0) +#define PMC_PLL_CTRL0_ENPLL BIT(28) +#define PMC_PLL_CTRL0_ENPLLCK BIT(29) +#define PMC_PLL_CTRL0_ENLOCK BIT(31) + +#define PMC_PLL_CTRL1 0x10 +#define PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0) +#define PMC_PLL_CTRL1_MUL_MSK GENMASK(30, 24) + +#define PMC_PLL_ACR 0x18 +#define PMC_PLL_ACR_DEFAULT_UPLL 0x12020010UL +#define PMC_PLL_ACR_DEFAULT_PLLA 0x00020010UL +#define PMC_PLL_ACR_UTMIVR BIT(12) +#define PMC_PLL_ACR_UTMIBG BIT(13) +#define PMC_PLL_ACR_LOOP_FILTER_MSK GENMASK(31, 24) + +#define PMC_PLL_UPDT 0x1c +#define PMC_PLL_UPDT_UPDATE BIT(8) + +#define PMC_PLL_ISR0 0xec + +#define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1) +#define UPLL_DIV 2 +#define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1) + +#define PLL_MAX_ID 1 + +struct sam9x60_pll { + struct clk clk; + struct regmap *regmap; + const struct clk_pll_characteristics *characteristics; + u32 frac; + u8 id; + u8 div; + u16 mul; + const char *parent_name; +}; + +#define to_sam9x60_pll(clk) container_of(clk, struct sam9x60_pll, clk) + +static inline bool sam9x60_pll_ready(struct regmap *regmap, int id) +{ + unsigned int status; + + regmap_read(regmap, PMC_PLL_ISR0, &status); + + return !!(status & BIT(id)); +} + +static int sam9x60_pll_enable(struct clk *clk) +{ + struct sam9x60_pll *pll = to_sam9x60_pll(clk); + struct regmap *regmap = pll->regmap; + u8 div; + u16 mul; + u32 val; + + regmap_write(regmap, PMC_PLL_UPDT, pll->id); + + regmap_read(regmap, PMC_PLL_CTRL0, &val); + div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val); + + regmap_read(regmap, PMC_PLL_CTRL1, &val); + mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val); + + if (sam9x60_pll_ready(regmap, pll->id) && + (div == pll->div && mul == pll->mul)) { + return 0; + } + + /* Recommended value for PMC_PLL_ACR */ + if (pll->characteristics->upll) + val = PMC_PLL_ACR_DEFAULT_UPLL; + else + val = PMC_PLL_ACR_DEFAULT_PLLA; + regmap_write(regmap, PMC_PLL_ACR, val); + + regmap_write(regmap, PMC_PLL_CTRL1, + FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul)); + + if (pll->characteristics->upll) { + /* Enable the UTMI internal bandgap */ + val |= PMC_PLL_ACR_UTMIBG; + regmap_write(regmap, PMC_PLL_ACR, val); + + udelay(10); + + /* Enable the UTMI internal regulator */ + val |= PMC_PLL_ACR_UTMIVR; + regmap_write(regmap, PMC_PLL_ACR, val); + + udelay(10); + } + + regmap_update_bits(regmap, PMC_PLL_UPDT, + PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE); + + regmap_write(regmap, PMC_PLL_CTRL0, + PMC_PLL_CTRL0_ENLOCK | PMC_PLL_CTRL0_ENPLL | + PMC_PLL_CTRL0_ENPLLCK | pll->div); + + regmap_update_bits(regmap, PMC_PLL_UPDT, + PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE); + + while (!sam9x60_pll_ready(regmap, pll->id)) + cpu_relax(); + + return 0; +} + +static int sam9x60_pll_is_enabled(struct clk *clk) +{ + struct sam9x60_pll *pll = to_sam9x60_pll(clk); + + return sam9x60_pll_ready(pll->regmap, pll->id); +} + +static void sam9x60_pll_disable(struct clk *clk) +{ + struct sam9x60_pll *pll = to_sam9x60_pll(clk); + + regmap_write(pll->regmap, PMC_PLL_UPDT, pll->id); + + regmap_update_bits(pll->regmap, PMC_PLL_CTRL0, + PMC_PLL_CTRL0_ENPLLCK, 0); + + regmap_update_bits(pll->regmap, PMC_PLL_UPDT, + PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE); + + regmap_update_bits(pll->regmap, PMC_PLL_CTRL0, PMC_PLL_CTRL0_ENPLL, 0); + + if (pll->characteristics->upll) + regmap_update_bits(pll->regmap, PMC_PLL_ACR, + PMC_PLL_ACR_UTMIBG | PMC_PLL_ACR_UTMIVR, 0); + + regmap_update_bits(pll->regmap, PMC_PLL_UPDT, + PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE); +} + +static unsigned long sam9x60_pll_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct sam9x60_pll *pll = to_sam9x60_pll(clk); + + return (parent_rate * (pll->mul + 1)) / (pll->div + 1); +} + +static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll, + unsigned long rate, + unsigned long parent_rate, + bool update) +{ + const struct clk_pll_characteristics *characteristics = + pll->characteristics; + unsigned long bestremainder = ULONG_MAX; + unsigned long maxdiv, mindiv, tmpdiv; + long bestrate = -ERANGE; + unsigned long bestdiv = 0; + unsigned long bestmul = 0; + unsigned long bestfrac = 0; + + if (rate < characteristics->output[0].min || + rate > characteristics->output[0].max) + return -ERANGE; + + if (!pll->characteristics->upll) { + mindiv = parent_rate / rate; + if (mindiv < 2) + mindiv = 2; + + maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX, rate); + if (maxdiv > PLL_DIV_MAX) + maxdiv = PLL_DIV_MAX; + } else { + mindiv = maxdiv = UPLL_DIV; + } + + for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) { + unsigned long remainder; + unsigned long tmprate; + unsigned long tmpmul; + unsigned long tmpfrac = 0; + + /* + * Calculate the multiplier associated with the current + * divider that provide the closest rate to the requested one. + */ + tmpmul = mult_frac(rate, tmpdiv, parent_rate); + tmprate = mult_frac(parent_rate, tmpmul, tmpdiv); + remainder = rate - tmprate; + + if (remainder) { + tmpfrac = DIV_ROUND_CLOSEST_ULL((u64)remainder * tmpdiv * (1 << 22), + parent_rate); + + tmprate += DIV_ROUND_CLOSEST_ULL((u64)tmpfrac * parent_rate, + tmpdiv * (1 << 22)); + + if (tmprate > rate) + remainder = tmprate - rate; + else + remainder = rate - tmprate; + } + + /* + * Compare the remainder with the best remainder found until + * now and elect a new best multiplier/divider pair if the + * current remainder is smaller than the best one. + */ + if (remainder < bestremainder) { + bestremainder = remainder; + bestdiv = tmpdiv; + bestmul = tmpmul; + bestrate = tmprate; + bestfrac = tmpfrac; + } + + /* We've found a perfect match! */ + if (!remainder) + break; + } + + /* Check if bestrate is a valid output rate */ + if (bestrate < characteristics->output[0].min && + bestrate > characteristics->output[0].max) + return -ERANGE; + + if (update) { + pll->div = bestdiv - 1; + pll->mul = bestmul - 1; + pll->frac = bestfrac; + } + + return bestrate; +} + +static long sam9x60_pll_round_rate(struct clk *clk, unsigned long rate, + unsigned long *parent_rate) +{ + struct sam9x60_pll *pll = to_sam9x60_pll(clk); + + return sam9x60_pll_get_best_div_mul(pll, rate, *parent_rate, false); +} + +static int sam9x60_pll_set_rate(struct clk *clk, unsigned long rate, + unsigned long parent_rate) +{ + struct sam9x60_pll *pll = to_sam9x60_pll(clk); + + return sam9x60_pll_get_best_div_mul(pll, rate, parent_rate, true); +} + +static const struct clk_ops pll_ops = { + .enable = sam9x60_pll_enable, + .disable = sam9x60_pll_disable, + .is_enabled = sam9x60_pll_is_enabled, + .recalc_rate = sam9x60_pll_recalc_rate, + .round_rate = sam9x60_pll_round_rate, + .set_rate = sam9x60_pll_set_rate, +}; + +struct clk * __init +sam9x60_clk_register_pll(struct regmap *regmap, + const char *name, const char *parent_name, u8 id, + const struct clk_pll_characteristics *characteristics) +{ + struct sam9x60_pll *pll; + unsigned int pllr; + int ret; + + if (id > PLL_MAX_ID) + return ERR_PTR(-EINVAL); + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->clk.name = name; + pll->clk.ops = &pll_ops; + pll->parent_name = parent_name; + pll->clk.parent_names = &pll->parent_name; + pll->clk.num_parents = 1; + /* pll->clk.flags = CLK_SET_RATE_GATE; */ + + pll->id = id; + pll->characteristics = characteristics; + pll->regmap = regmap; + + regmap_write(regmap, PMC_PLL_UPDT, id); + regmap_read(regmap, PMC_PLL_CTRL0, &pllr); + pll->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, pllr); + regmap_read(regmap, PMC_PLL_CTRL1, &pllr); + pll->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, pllr); + + ret = clk_register(&pll->clk); + if (ret) { + kfree(pll); + return ERR_PTR(ret); + } + + return &pll->clk; +} + diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c index d19f7e15ac..960678db1c 100644 --- a/drivers/clk/at91/clk-slow.c +++ b/drivers/clk/at91/clk-slow.c @@ -1,13 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * drivers/clk/at91/clk-slow.c * * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c index e81f0d4d4e..0027ebc8bb 100644 --- a/drivers/clk/at91/clk-smd.c +++ b/drivers/clk/at91/clk-smd.c @@ -1,11 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> @@ -114,7 +109,7 @@ static const struct clk_ops at91sam9x5_smd_ops = { .set_rate = at91sam9x5_clk_smd_set_rate, }; -struct clk * +struct clk * __init at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents) { diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c index 8be5c7f2b3..77f0dff98b 100644 --- a/drivers/clk/at91/clk-system.c +++ b/drivers/clk/at91/clk-system.c @@ -1,11 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> #include <clock.h> @@ -90,7 +85,7 @@ static const struct clk_ops system_ops = { .is_enabled = clk_system_is_enabled, }; -struct clk * +struct clk * __init at91_clk_register_system(struct regmap *regmap, const char *name, const char *parent_name, u8 id) { diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c index 0eb0b1f5bc..2cf68593c0 100644 --- a/drivers/clk/at91/clk-usb.c +++ b/drivers/clk/at91/clk-usb.c @@ -1,11 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> @@ -27,10 +22,14 @@ #define RM9200_USB_DIV_SHIFT 28 #define RM9200_USB_DIV_TAB_SIZE 4 +#define SAM9X5_USBS_MASK GENMASK(0, 0) +#define SAM9X60_USBS_MASK GENMASK(1, 0) + struct at91sam9x5_clk_usb { struct clk clk; struct regmap *regmap; const char *parent_names[USB_SOURCE_MAX]; + u32 usbs_mask; }; #define to_at91sam9x5_clk_usb(clk) \ @@ -66,8 +65,7 @@ static int at91sam9x5_clk_usb_set_parent(struct clk *clk, u8 index) if (index > 1) return -EINVAL; - regmap_write_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_USBS, - index ? AT91_PMC_USBS : 0); + regmap_write_bits(usb->regmap, AT91_PMC_USB, usb->usbs_mask, index); return 0; } @@ -79,7 +77,7 @@ static int at91sam9x5_clk_usb_get_parent(struct clk *clk) regmap_read(usb->regmap, AT91_PMC_USB, &usbr); - return usbr & AT91_PMC_USBS; + return usbr & usb->usbs_mask; } static int at91sam9x5_clk_usb_set_rate(struct clk *clk, unsigned long rate, @@ -143,9 +141,10 @@ static const struct clk_ops at91sam9n12_usb_ops = { .set_rate = at91sam9x5_clk_usb_set_rate, }; -struct clk * -at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents) +static struct clk * __init +_at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, + const char **parent_names, u8 num_parents, + u32 usbs_mask) { struct at91sam9x5_clk_usb *usb; int ret; @@ -161,6 +160,7 @@ at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, /* init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | */ /* CLK_SET_RATE_PARENT; */ usb->regmap = regmap; + usb->usbs_mask = SAM9X5_USBS_MASK; ret = clk_register(&usb->clk); if (ret) { @@ -171,7 +171,23 @@ at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, return &usb->clk; } -struct clk * +struct clk * __init +at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, + const char **parent_names, u8 num_parents) +{ + return _at91sam9x5_clk_register_usb(regmap, name, parent_names, + num_parents, SAM9X5_USBS_MASK); +} + +struct clk * __init +sam9x60_clk_register_usb(struct regmap *regmap, const char *name, + const char **parent_names, u8 num_parents) +{ + return _at91sam9x5_clk_register_usb(regmap, name, parent_names, + num_parents, SAM9X60_USBS_MASK); +} + +struct clk * __init at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name, const char *parent_name) { @@ -281,7 +297,7 @@ static const struct clk_ops at91rm9200_usb_ops = { .set_rate = at91rm9200_clk_usb_set_rate, }; -struct clk * +struct clk * __init at91rm9200_clk_register_usb(struct regmap *regmap, const char *name, const char *parent_name, const u32 *divisors) { diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index c40af34d0d..3d71cd615f 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -1,11 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index beb86230f6..b888249199 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -23,95 +23,13 @@ #define SYSTEM_MAX_ID 31 -#ifdef CONFIG_HAVE_AT91_GENERATED_CLK -#define GENERATED_SOURCE_MAX 6 - -#define GCK_ID_I2S0 54 -#define GCK_ID_I2S1 55 -#define GCK_ID_CLASSD 59 - -static void __init of_sama5d2_clk_generated_setup(struct device_node *np) -{ - int num; - u32 id; - const char *name; - struct clk *hw; - unsigned int num_parents; - const char *parent_names[GENERATED_SOURCE_MAX]; - struct device_node *gcknp; - struct clk_range range = CLK_RANGE(0, 0); - struct regmap *regmap; - - num_parents = of_clk_get_parent_count(np); - if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX) - return; - - of_clk_parent_fill(np, parent_names, num_parents); - - num = of_get_child_count(np); - if (!num || num > PERIPHERAL_MAX) - return; - - regmap = syscon_node_to_regmap(of_get_parent(np)); - if (IS_ERR(regmap)) - return; - - for_each_child_of_node(np, gcknp) { - bool pll_audio = false; - - if (of_property_read_u32(gcknp, "reg", &id)) - continue; - - if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX) - continue; - - if (of_property_read_string(np, "clock-output-names", &name)) - name = gcknp->name; - - of_at91_get_clk_range(gcknp, "atmel,clk-output-range", - &range); - - if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") && - (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 || - id == GCK_ID_CLASSD)) - pll_audio = true; - - hw = at91_clk_register_generated(regmap, name, - parent_names, num_parents, - id, pll_audio, &range); - if (IS_ERR(hw)) - continue; - - of_clk_add_provider(gcknp, of_clk_src_simple_get, hw); - } -} -CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated", - of_sama5d2_clk_generated_setup); -#endif /* CONFIG_HAVE_AT91_GENERATED_CLK */ - -#ifdef CONFIG_HAVE_AT91_H32MX -static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np) -{ - struct clk *hw; - const char *name = np->name; - const char *parent_name; - struct regmap *regmap; - - regmap = syscon_node_to_regmap(of_get_parent(np)); - if (IS_ERR(regmap)) - return; - - parent_name = of_clk_get_parent_name(np, 0); - - hw = at91_clk_register_h32mx(regmap, name, parent_name); - if (IS_ERR(hw)) - return; - - of_clk_add_provider(np, of_clk_src_simple_get, hw); -} -CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx", - of_sama5d4_clk_h32mx_setup); -#endif /* CONFIG_HAVE_AT91_H32MX */ +static const struct clk_pcr_layout dt_pcr_layout = { + .offset = 0x10c, + .cmd = BIT(12), + .pid_mask = GENMASK(5, 0), + .div_mask = GENMASK(17, 16), + .gckcss_mask = GENMASK(10, 8), +}; static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np) { @@ -338,6 +256,7 @@ of_at91_clk_periph_setup(struct device_node *np, u8 type) &range); hw = at91_clk_register_sam9x5_peripheral(regmap, + &dt_pcr_layout, name, parent_name, id, &range); @@ -505,20 +424,6 @@ static void __init of_at91rm9200_clk_pll_setup(struct device_node *np) CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll", of_at91rm9200_clk_pll_setup); -static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np) -{ - of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout); -} -CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll", - of_at91sam9g45_clk_pll_setup); - -static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np) -{ - of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout); -} -CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb", - of_at91sam9g20_clk_pllb_setup); - static void __init of_sama5d3_clk_pll_setup(struct device_node *np) { of_at91_clk_pll_setup(np, &sama5d3_pll_layout); @@ -616,35 +521,6 @@ static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np) CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable", of_at91sam9x5_clk_prog_setup); -static void __init of_at91sam9260_clk_slow_setup(struct device_node *np) -{ - struct clk *hw; - const char *parent_names[2]; - unsigned int num_parents; - const char *name = np->name; - struct regmap *regmap; - - num_parents = of_clk_get_parent_count(np); - if (num_parents != 2) - return; - - of_clk_parent_fill(np, parent_names, num_parents); - regmap = syscon_node_to_regmap(of_get_parent(np)); - if (IS_ERR(regmap)) - return; - - of_property_read_string(np, "clock-output-names", &name); - - hw = at91_clk_register_sam9260_slow(regmap, name, parent_names, - num_parents); - if (IS_ERR(hw)) - return; - - of_clk_add_provider(np, of_clk_src_simple_get, hw); -} -CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow", - of_at91sam9260_clk_slow_setup); - #ifdef CONFIG_HAVE_AT91_SMD #define SMD_SOURCE_MAX 2 diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index 86a50b680b..171b62cbfd 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -1,11 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <module.h> @@ -94,22 +89,22 @@ struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, return NULL; pmc_data->ncore = ncore; - pmc_data->chws = kcalloc(ncore, sizeof(struct clk_hw *), GFP_KERNEL); + pmc_data->chws = kcalloc(ncore, sizeof(struct clk *), GFP_KERNEL); if (!pmc_data->chws) goto err; pmc_data->nsystem = nsystem; - pmc_data->shws = kcalloc(nsystem, sizeof(struct clk_hw *), GFP_KERNEL); + pmc_data->shws = kcalloc(nsystem, sizeof(struct clk *), GFP_KERNEL); if (!pmc_data->shws) goto err; pmc_data->nperiph = nperiph; - pmc_data->phws = kcalloc(nperiph, sizeof(struct clk_hw *), GFP_KERNEL); + pmc_data->phws = kcalloc(nperiph, sizeof(struct clk *), GFP_KERNEL); if (!pmc_data->phws) goto err; pmc_data->ngck = ngck; - pmc_data->ghws = kcalloc(ngck, sizeof(struct clk_hw *), GFP_KERNEL); + pmc_data->ghws = kcalloc(ngck, sizeof(struct clk *), GFP_KERNEL); if (!pmc_data->ghws) goto err; @@ -140,6 +135,8 @@ static struct u32 imr; u32 pcsr1; u32 pcr[PMC_MAX_IDS]; + u32 audio_pll0; + u32 audio_pll1; u32 pckr[PMC_MAX_PCKS]; } pmc_cache; @@ -274,7 +271,7 @@ static int __init pmc_register_ops(void) np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids); - pmcreg = syscon_node_to_regmap(np); + pmcreg = device_node_to_regmap(np); if (IS_ERR(pmcreg)) return PTR_ERR(pmcreg); diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index b553ea259c..d96a94e6e5 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -1,19 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * drivers/clk/at91/pmc.h * * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ #ifndef __PMC_H_ #define __PMC_H_ #include <io.h> -#include <linux/spinlock.h> +#include <linux/bitops.h> #include <printk.h> struct pmc_data { @@ -35,6 +31,7 @@ struct clk_range { #define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,} struct clk_master_layout { + u32 offset; u32 mask; u8 pres_shift; }; @@ -62,21 +59,35 @@ extern const struct clk_pll_layout sama5d3_pll_layout; struct clk_pll_characteristics { struct clk_range input; int num_output; - struct clk_range *output; + const struct clk_range *output; u16 *icpll; u8 *out; + u8 upll : 1; }; struct clk_programmable_layout { + u8 pres_mask; u8 pres_shift; u8 css_mask; u8 have_slck_mck; + u8 is_pres_direct; }; extern const struct clk_programmable_layout at91rm9200_programmable_layout; extern const struct clk_programmable_layout at91sam9g45_programmable_layout; extern const struct clk_programmable_layout at91sam9x5_programmable_layout; +struct clk_pcr_layout { + u32 offset; + u32 cmd; + u32 div_mask; + u32 gckcss_mask; + u32 pid_mask; +}; + +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + #define ndck(a, s) (a[s - 1].id + 1) #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, @@ -88,83 +99,111 @@ int of_at91_get_clk_range(struct device_node *np, const char *propname, struct clk *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data); -struct clk * +struct clk * __init +at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name, + const char *parent_name); + +struct clk * __init +at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name, + const char *parent_name); + +struct clk * __init +at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name, + const char *parent_name); + +struct clk * __init at91_clk_register_generated(struct regmap *regmap, + const struct clk_pcr_layout *layout, const char *name, const char **parent_names, u8 num_parents, u8 id, bool pll_audio, const struct clk_range *range); -struct clk * +struct clk * __init at91_clk_register_h32mx(struct regmap *regmap, const char *name, const char *parent_name); -struct clk * +struct clk * __init +at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, + const char * const *parent_names, + unsigned int num_parents, u8 bus_id); + +struct clk * __init at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name, u32 frequency, u32 accuracy); -struct clk * +struct clk * __init at91_clk_register_main_osc(struct regmap *regmap, const char *name, const char *parent_name, bool bypass); -struct clk * +struct clk * __init at91_clk_register_rm9200_main(struct regmap *regmap, const char *name, const char *parent_name); -struct clk * +struct clk * __init at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name, const char **parent_names, int num_parents); -struct clk * +struct clk * __init at91_clk_register_master(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics); -struct clk * +struct clk * __init at91_clk_register_peripheral(struct regmap *regmap, const char *name, const char *parent_name, u32 id); -struct clk * +struct clk * __init at91_clk_register_sam9x5_peripheral(struct regmap *regmap, + const struct clk_pcr_layout *layout, const char *name, const char *parent_name, u32 id, const struct clk_range *range); -struct clk * +struct clk * __init at91_clk_register_pll(struct regmap *regmap, const char *name, const char *parent_name, u8 id, const struct clk_pll_layout *layout, const struct clk_pll_characteristics *characteristics); -struct clk * +struct clk * __init at91_clk_register_plldiv(struct regmap *regmap, const char *name, const char *parent_name); -struct clk * +struct clk * __init +sam9x60_clk_register_pll(struct regmap *regmap, + const char *name, const char *parent_name, u8 id, + const struct clk_pll_characteristics *characteristics); + +struct clk * __init at91_clk_register_programmable(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents, u8 id, const struct clk_programmable_layout *layout); -struct clk * +struct clk * __init at91_clk_register_sam9260_slow(struct regmap *regmap, const char *name, const char **parent_names, int num_parents); -struct clk * +struct clk * __init at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents); -struct clk * +struct clk * __init at91_clk_register_system(struct regmap *regmap, const char *name, const char *parent_name, u8 id); -struct clk * +struct clk * __init at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents); -struct clk * +struct clk * __init at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name, const char *parent_name); -struct clk * +struct clk * __init +sam9x60_clk_register_usb(struct regmap *regmap, const char *name, + const char **parent_names, u8 num_parents); + +struct clk * __init at91rm9200_clk_register_usb(struct regmap *regmap, const char *name, const char *parent_name, const u32 *divisors); -struct clk * +struct clk * __init at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr, const char *name, const char *parent_name); diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c new file mode 100644 index 0000000000..36a7a846ef --- /dev/null +++ b/drivers/clk/at91/sam9x60.c @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <driver.h> +#include <regmap.h> +#include <stdio.h> +#include <mfd/syscon.h> + +#include <linux/clk.h> +#include <linux/slab.h> +#include <linux/types.h> + +#include <dt-bindings/clock/at91.h> + +#include "pmc.h" + +static const struct clk_master_characteristics mck_characteristics = { + .output = { .min = 140000000, .max = 200000000 }, + .divisors = { 1, 2, 4, 3 }, + .have_div3_pres = 1, +}; + +static const struct clk_master_layout sam9x60_master_layout = { + .mask = 0x373, + .pres_shift = 4, + .offset = 0x28, +}; + +static const struct clk_range plla_outputs[] = { + { .min = 300000000, .max = 600000000 }, +}; + +static const struct clk_pll_characteristics plla_characteristics = { + .input = { .min = 12000000, .max = 48000000 }, + .num_output = ARRAY_SIZE(plla_outputs), + .output = plla_outputs, +}; + +static const struct clk_range upll_outputs[] = { + { .min = 300000000, .max = 500000000 }, +}; + +static const struct clk_pll_characteristics upll_characteristics = { + .input = { .min = 12000000, .max = 48000000 }, + .num_output = ARRAY_SIZE(upll_outputs), + .output = upll_outputs, + .upll = true, +}; + +static const struct clk_programmable_layout sam9x60_programmable_layout = { + .pres_mask = 0xff, + .pres_shift = 8, + .css_mask = 0x1f, + .have_slck_mck = 0, + .is_pres_direct = 1, +}; + +static const struct clk_pcr_layout sam9x60_pcr_layout = { + .offset = 0x88, + .cmd = BIT(31), + .gckcss_mask = GENMASK(12, 8), + .pid_mask = GENMASK(6, 0), +}; + +static const struct { + char *n; + char *p; + u8 id; +} sam9x60_systemck[] = { + { .n = "ddrck", .p = "masterck", .id = 2 }, + { .n = "uhpck", .p = "usbck", .id = 6 }, + { .n = "pck0", .p = "prog0", .id = 8 }, + { .n = "pck1", .p = "prog1", .id = 9 }, + { .n = "qspick", .p = "masterck", .id = 19 }, +}; + +static const struct { + char *n; + u8 id; +} sam9x60_periphck[] = { + { .n = "pioA_clk", .id = 2, }, + { .n = "pioB_clk", .id = 3, }, + { .n = "pioC_clk", .id = 4, }, + { .n = "flex0_clk", .id = 5, }, + { .n = "flex1_clk", .id = 6, }, + { .n = "flex2_clk", .id = 7, }, + { .n = "flex3_clk", .id = 8, }, + { .n = "flex6_clk", .id = 9, }, + { .n = "flex7_clk", .id = 10, }, + { .n = "flex8_clk", .id = 11, }, + { .n = "sdmmc0_clk", .id = 12, }, + { .n = "flex4_clk", .id = 13, }, + { .n = "flex5_clk", .id = 14, }, + { .n = "flex9_clk", .id = 15, }, + { .n = "flex10_clk", .id = 16, }, + { .n = "tcb0_clk", .id = 17, }, + { .n = "pwm_clk", .id = 18, }, + { .n = "adc_clk", .id = 19, }, + { .n = "dma0_clk", .id = 20, }, + { .n = "matrix_clk", .id = 21, }, + { .n = "uhphs_clk", .id = 22, }, + { .n = "udphs_clk", .id = 23, }, + { .n = "macb0_clk", .id = 24, }, + { .n = "lcd_clk", .id = 25, }, + { .n = "sdmmc1_clk", .id = 26, }, + { .n = "macb1_clk", .id = 27, }, + { .n = "ssc_clk", .id = 28, }, + { .n = "can0_clk", .id = 29, }, + { .n = "can1_clk", .id = 30, }, + { .n = "flex11_clk", .id = 32, }, + { .n = "flex12_clk", .id = 33, }, + { .n = "i2s_clk", .id = 34, }, + { .n = "qspi_clk", .id = 35, }, + { .n = "gfx2d_clk", .id = 36, }, + { .n = "pit64b_clk", .id = 37, }, + { .n = "trng_clk", .id = 38, }, + { .n = "aes_clk", .id = 39, }, + { .n = "tdes_clk", .id = 40, }, + { .n = "sha_clk", .id = 41, }, + { .n = "classd_clk", .id = 42, }, + { .n = "isi_clk", .id = 43, }, + { .n = "pioD_clk", .id = 44, }, + { .n = "tcb1_clk", .id = 45, }, + { .n = "dbgu_clk", .id = 47, }, + { .n = "mpddr_clk", .id = 49, }, +}; + +static const struct { + char *n; + u8 id; + struct clk_range r; + bool pll; +} sam9x60_gck[] = { + { .n = "flex0_gclk", .id = 5, }, + { .n = "flex1_gclk", .id = 6, }, + { .n = "flex2_gclk", .id = 7, }, + { .n = "flex3_gclk", .id = 8, }, + { .n = "flex6_gclk", .id = 9, }, + { .n = "flex7_gclk", .id = 10, }, + { .n = "flex8_gclk", .id = 11, }, + { .n = "sdmmc0_gclk", .id = 12, .r = { .min = 0, .max = 105000000 }, }, + { .n = "flex4_gclk", .id = 13, }, + { .n = "flex5_gclk", .id = 14, }, + { .n = "flex9_gclk", .id = 15, }, + { .n = "flex10_gclk", .id = 16, }, + { .n = "tcb0_gclk", .id = 17, }, + { .n = "adc_gclk", .id = 19, }, + { .n = "lcd_gclk", .id = 25, .r = { .min = 0, .max = 140000000 }, }, + { .n = "sdmmc1_gclk", .id = 26, .r = { .min = 0, .max = 105000000 }, }, + { .n = "flex11_gclk", .id = 32, }, + { .n = "flex12_gclk", .id = 33, }, + { .n = "i2s_gclk", .id = 34, .r = { .min = 0, .max = 105000000 }, + .pll = true, }, + { .n = "pit64b_gclk", .id = 37, }, + { .n = "classd_gclk", .id = 42, .r = { .min = 0, .max = 100000000 }, + .pll = true, }, + { .n = "tcb1_gclk", .id = 45, }, + { .n = "dbgu_gclk", .id = 47, }, +}; + +static void __init sam9x60_pmc_setup(struct device_node *np) +{ + struct clk_range range = CLK_RANGE(0, 0); + const char *td_slck_name, *md_slck_name, *mainxtal_name; + struct pmc_data *sam9x60_pmc; + const char *parent_names[6]; + struct regmap *regmap; + struct clk *hw; + int i; + bool bypass; + + i = of_property_match_string(np, "clock-names", "td_slck"); + if (i < 0) + return; + + td_slck_name = of_clk_get_parent_name(np, i); + + i = of_property_match_string(np, "clock-names", "md_slck"); + if (i < 0) + return; + + md_slck_name = of_clk_get_parent_name(np, i); + + i = of_property_match_string(np, "clock-names", "main_xtal"); + if (i < 0) + return; + mainxtal_name = of_clk_get_parent_name(np, i); + + regmap = syscon_node_to_regmap(np); + if (IS_ERR(regmap)) + return; + + sam9x60_pmc = pmc_data_allocate(PMC_MAIN + 1, + nck(sam9x60_systemck), + nck(sam9x60_periphck), + nck(sam9x60_gck)); + if (!sam9x60_pmc) + return; + + hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 24000000, + 50000000); + if (IS_ERR(hw)) + goto err_free; + + bypass = of_property_read_bool(np, "atmel,osc-bypass"); + + hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, + bypass); + if (IS_ERR(hw)) + goto err_free; + + parent_names[0] = "main_rc_osc"; + parent_names[1] = "main_osc"; + hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2); + if (IS_ERR(hw)) + goto err_free; + + sam9x60_pmc->chws[PMC_MAIN] = hw; + + hw = sam9x60_clk_register_pll(regmap, "pllack", + "mainck", 0, &plla_characteristics); + if (IS_ERR(hw)) + goto err_free; + + hw = sam9x60_clk_register_pll(regmap, "upllck", + "main_osc", 1, &upll_characteristics); + if (IS_ERR(hw)) + goto err_free; + + sam9x60_pmc->chws[PMC_UTMI] = hw; + + parent_names[0] = md_slck_name; + parent_names[1] = "mainck"; + parent_names[2] = "pllack"; + hw = at91_clk_register_master(regmap, "masterck", 3, parent_names, + &sam9x60_master_layout, + &mck_characteristics); + if (IS_ERR(hw)) + goto err_free; + + sam9x60_pmc->chws[PMC_MCK] = hw; + + parent_names[0] = "pllack"; + parent_names[1] = "upllck"; + parent_names[2] = "mainck"; + parent_names[3] = "mainck"; + hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 4); + if (IS_ERR(hw)) + goto err_free; + + parent_names[0] = md_slck_name; + parent_names[1] = td_slck_name; + parent_names[2] = "mainck"; + parent_names[3] = "masterck"; + parent_names[4] = "pllack"; + parent_names[5] = "upllck"; + for (i = 0; i < 8; i++) { + char name[6]; + + snprintf(name, sizeof(name), "prog%d", i); + + hw = at91_clk_register_programmable(regmap, name, + parent_names, 6, i, + &sam9x60_programmable_layout); + if (IS_ERR(hw)) + goto err_free; + } + + for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) { + hw = at91_clk_register_system(regmap, sam9x60_systemck[i].n, + sam9x60_systemck[i].p, + sam9x60_systemck[i].id); + if (IS_ERR(hw)) + goto err_free; + + sam9x60_pmc->shws[sam9x60_systemck[i].id] = hw; + } + + for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) { + hw = at91_clk_register_sam9x5_peripheral(regmap, + &sam9x60_pcr_layout, + sam9x60_periphck[i].n, + "masterck", + sam9x60_periphck[i].id, + &range); + if (IS_ERR(hw)) + goto err_free; + + sam9x60_pmc->phws[sam9x60_periphck[i].id] = hw; + } + + for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) { + hw = at91_clk_register_generated(regmap, + &sam9x60_pcr_layout, + sam9x60_gck[i].n, + parent_names, 6, + sam9x60_gck[i].id, + sam9x60_gck[i].pll, + &sam9x60_gck[i].r); + if (IS_ERR(hw)) + goto err_free; + + sam9x60_pmc->ghws[sam9x60_gck[i].id] = hw; + } + + of_clk_add_provider(np, of_clk_hw_pmc_get, sam9x60_pmc); + + return; + +err_free: + pmc_data_free(sam9x60_pmc); +} +/* Some clks are used for a clocksource */ +CLK_OF_DECLARE(sam9x60_pmc, "microchip,sam9x60-pmc", sam9x60_pmc_setup); diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index 7627c584ac..731637e4ab 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -22,18 +22,25 @@ static u8 plla_out[] = { 0 }; static u16 plla_icpll[] = { 0 }; -static struct clk_range plla_outputs[] = { +static const struct clk_range plla_outputs[] = { { .min = 600000000, .max = 1200000000 }, }; static const struct clk_pll_characteristics plla_characteristics = { - .input = { .min = 12000000, .max = 12000000 }, + .input = { .min = 12000000, .max = 24000000 }, .num_output = ARRAY_SIZE(plla_outputs), .output = plla_outputs, .icpll = plla_icpll, .out = plla_out, }; +static const struct clk_pcr_layout sama5d2_pcr_layout = { + .offset = 0x10c, + .cmd = BIT(12), + .gckcss_mask = GENMASK(10, 8), + .pid_mask = GENMASK(6, 0), +}; + static const struct { char *n; char *p; @@ -84,6 +91,8 @@ static const struct { { .n = "trng_clk", .id = 47, .r = { .min = 0, .max = 83000000 }, }, { .n = "pdmic_clk", .id = 48, .r = { .min = 0, .max = 83000000 }, }, { .n = "securam_clk", .id = 51, }, + { .n = "i2s0_clk", .id = 54, .r = { .min = 0, .max = 83000000 }, }, + { .n = "i2s1_clk", .id = 55, .r = { .min = 0, .max = 83000000 }, }, { .n = "can0_clk", .id = 56, .r = { .min = 0, .max = 83000000 }, }, { .n = "can1_clk", .id = 57, .r = { .min = 0, .max = 83000000 }, }, { .n = "classd_clk", .id = 59, .r = { .min = 0, .max = 83000000 }, }, @@ -121,18 +130,28 @@ static const struct { { .n = "pwm_gclk", .id = 38, .r = { .min = 0, .max = 83000000 }, }, { .n = "isc_gclk", .id = 46, }, { .n = "pdmic_gclk", .id = 48, }, + { .n = "i2s0_gclk", .id = 54, .pll = true }, + { .n = "i2s1_gclk", .id = 55, .pll = true }, { .n = "can0_gclk", .id = 56, .r = { .min = 0, .max = 80000000 }, }, { .n = "can1_gclk", .id = 57, .r = { .min = 0, .max = 80000000 }, }, { .n = "classd_gclk", .id = 59, .r = { .min = 0, .max = 100000000 }, .pll = true }, }; +static const struct clk_programmable_layout sama5d2_programmable_layout = { + .pres_mask = 0xff, + .pres_shift = 4, + .css_mask = 0x7, + .have_slck_mck = 0, + .is_pres_direct = 1, +}; + static void __init sama5d2_pmc_setup(struct device_node *np) { struct clk_range range = CLK_RANGE(0, 0); const char *slck_name, *mainxtal_name; struct pmc_data *sama5d2_pmc; - const char *parent_names[5]; + const char *parent_names[6]; struct regmap *regmap, *regmap_sfr; struct clk *hw; int i; @@ -149,11 +168,11 @@ static void __init sama5d2_pmc_setup(struct device_node *np) return; mainxtal_name = of_clk_get_parent_name(np, i); - regmap = syscon_node_to_regmap(np); + regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; - sama5d2_pmc = pmc_data_allocate(PMC_MCK2 + 1, + sama5d2_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1, nck(sama5d2_systemck), nck(sama5d2_periph32ck), nck(sama5d2_gck)); @@ -189,6 +208,21 @@ static void __init sama5d2_pmc_setup(struct device_node *np) if (IS_ERR(hw)) goto err_free; + hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck", + "mainck"); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck", + "audiopll_fracck"); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck", + "audiopll_fracck"); + if (IS_ERR(hw)) + goto err_free; + regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr"); if (IS_ERR(regmap_sfr)) regmap_sfr = NULL; @@ -227,15 +261,16 @@ static void __init sama5d2_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - parent_names[4] = "mck"; + parent_names[4] = "masterck"; + parent_names[5] = "audiopll_pmcck"; for (i = 0; i < 3; i++) { char *name; name = xasprintf("prog%d", i); hw = at91_clk_register_programmable(regmap, name, - parent_names, 5, i, - &at91sam9x5_programmable_layout); + parent_names, 6, i, + &sama5d2_programmable_layout); if (IS_ERR(hw)) goto err_free; } @@ -252,6 +287,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np) for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, + &sama5d2_pcr_layout, sama5d2_periphck[i].n, "masterck", sama5d2_periphck[i].id, @@ -264,6 +300,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np) for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, + &sama5d2_pcr_layout, sama5d2_periph32ck[i].n, "h32mxck", sama5d2_periph32ck[i].id, @@ -278,11 +315,13 @@ static void __init sama5d2_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - parent_names[4] = "mck"; + parent_names[4] = "masterck"; + parent_names[5] = "audiopll_pmcck"; for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) { hw = at91_clk_register_generated(regmap, + &sama5d2_pcr_layout, sama5d2_gck[i].n, - parent_names, 5, + parent_names, 6, sama5d2_gck[i].id, sama5d2_gck[i].pll, &sama5d2_gck[i].r); @@ -292,6 +331,26 @@ static void __init sama5d2_pmc_setup(struct device_node *np) sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw; } + if (regmap_sfr) { + parent_names[0] = "i2s0_clk"; + parent_names[1] = "i2s0_gclk"; + hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk", + parent_names, 2, 0); + if (IS_ERR(hw)) + goto err_free; + + sama5d2_pmc->chws[PMC_I2S0_MUX] = hw; + + parent_names[0] = "i2s1_clk"; + parent_names[1] = "i2s1_gclk"; + hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk", + parent_names, 2, 1); + if (IS_ERR(hw)) + goto err_free; + + sama5d2_pmc->chws[PMC_I2S1_MUX] = hw; + } + of_clk_add_provider(np, of_clk_hw_pmc_get, sama5d2_pmc); return; diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c index 2fbfca6f85..77ccd77404 100644 --- a/drivers/clk/at91/sama5d4.c +++ b/drivers/clk/at91/sama5d4.c @@ -22,7 +22,7 @@ static u8 plla_out[] = { 0 }; static u16 plla_icpll[] = { 0 }; -static struct clk_range plla_outputs[] = { +static const struct clk_range plla_outputs[] = { { .min = 600000000, .max = 1200000000 }, }; @@ -34,6 +34,12 @@ static const struct clk_pll_characteristics plla_characteristics = { .out = plla_out, }; +static const struct clk_pcr_layout sama5d4_pcr_layout = { + .offset = 0x10c, + .cmd = BIT(12), + .pid_mask = GENMASK(6, 0), +}; + static const struct { char *n; char *p; @@ -136,7 +142,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np) return; mainxtal_name = of_clk_get_parent_name(np, i); - regmap = syscon_node_to_regmap(np); + regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; @@ -213,7 +219,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np) parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; - parent_names[4] = "mck"; + parent_names[4] = "masterck"; for (i = 0; i < 3; i++) { char *name; @@ -238,6 +244,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np) for (i = 0; i < ARRAY_SIZE(sama5d4_periphck); i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, + &sama5d4_pcr_layout, sama5d4_periphck[i].n, "masterck", sama5d4_periphck[i].id, @@ -250,6 +257,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np) for (i = 0; i < ARRAY_SIZE(sama5d4_periph32ck); i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, + &sama5d4_pcr_layout, sama5d4_periph32ck[i].n, "h32mxck", sama5d4_periph32ck[i].id, diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index bac28999ea..1a33a64421 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -1,13 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * drivers/clk/at91/sckc.c * * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> @@ -25,18 +20,22 @@ #define SLOW_CLOCK_FREQ 32768 #define SLOWCK_SW_CYCLES 5 -#define SLOWCK_SW_TIME_USEC ((SLOWCK_SW_CYCLES * SECOND) / \ +#define SLOWCK_SW_TIME_USEC ((SLOWCK_SW_CYCLES * USEC_PER_SEC) / \ SLOW_CLOCK_FREQ) #define AT91_SCKC_CR 0x00 -#define AT91_SCKC_RCEN (1 << 0) -#define AT91_SCKC_OSC32EN (1 << 1) -#define AT91_SCKC_OSC32BYP (1 << 2) -#define AT91_SCKC_OSCSEL (1 << 3) + +struct clk_slow_bits { + u32 cr_rcen; + u32 cr_osc32en; + u32 cr_osc32byp; + u32 cr_oscsel; +}; struct clk_slow_osc { struct clk clk; void __iomem *sckcr; + const struct clk_slow_bits *bits; unsigned long startup_usec; const char *parent_name; }; @@ -46,6 +45,7 @@ struct clk_slow_osc { struct clk_sama5d4_slow_osc { struct clk clk; void __iomem *sckcr; + const struct clk_slow_bits *bits; unsigned long startup_usec; bool prepared; const char *parent_name; @@ -56,6 +56,7 @@ struct clk_sama5d4_slow_osc { struct clk_slow_rc_osc { struct clk clk; void __iomem *sckcr; + const struct clk_slow_bits *bits; unsigned long frequency; unsigned long startup_usec; const char *parent_name; @@ -66,6 +67,7 @@ struct clk_slow_rc_osc { struct clk_sam9x5_slow { struct clk clk; void __iomem *sckcr; + const struct clk_slow_bits *bits; u8 parent; const char *parent_names[2]; }; @@ -78,10 +80,10 @@ static int clk_slow_osc_enable(struct clk *clk) void __iomem *sckcr = osc->sckcr; u32 tmp = readl(sckcr); - if (tmp & (AT91_SCKC_OSC32BYP | AT91_SCKC_OSC32EN)) + if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en)) return 0; - writel(tmp | AT91_SCKC_OSC32EN, sckcr); + writel(tmp | osc->bits->cr_osc32en, sckcr); udelay(osc->startup_usec); @@ -94,10 +96,10 @@ static void clk_slow_osc_disable(struct clk *clk) void __iomem *sckcr = osc->sckcr; u32 tmp = readl(sckcr); - if (tmp & AT91_SCKC_OSC32BYP) + if (tmp & osc->bits->cr_osc32byp) return; - writel(tmp & ~AT91_SCKC_OSC32EN, sckcr); + writel(tmp & ~osc->bits->cr_osc32en, sckcr); } static int clk_slow_osc_is_enabled(struct clk *clk) @@ -106,10 +108,10 @@ static int clk_slow_osc_is_enabled(struct clk *clk) void __iomem *sckcr = osc->sckcr; u32 tmp = readl(sckcr); - if (tmp & AT91_SCKC_OSC32BYP) + if (tmp & osc->bits->cr_osc32byp) return 1; - return !!(tmp & AT91_SCKC_OSC32EN); + return !!(tmp & osc->bits->cr_osc32en); } static const struct clk_ops slow_osc_ops = { @@ -118,12 +120,13 @@ static const struct clk_ops slow_osc_ops = { .is_enabled = clk_slow_osc_is_enabled, }; -static struct clk * +static struct clk * __init at91_clk_register_slow_osc(void __iomem *sckcr, const char *name, const char *parent_name, unsigned long startup, - bool bypass) + bool bypass, + const struct clk_slow_bits *bits) { int ret; struct clk_slow_osc *osc; @@ -138,13 +141,15 @@ at91_clk_register_slow_osc(void __iomem *sckcr, osc->parent_name = parent_name; osc->clk.parent_names = &osc->parent_name; osc->clk.num_parents = 1; + /* osc->clk.flags = CLK_IGNORE_UNUSED; */ osc->sckcr = sckcr; osc->startup_usec = startup; + osc->bits = bits; if (bypass) - writel((readl(sckcr) & ~AT91_SCKC_OSC32EN) | AT91_SCKC_OSC32BYP, - sckcr); + writel((readl(sckcr) & ~osc->bits->cr_osc32en) | + osc->bits->cr_osc32byp, sckcr); ret = clk_register(&osc->clk); if (ret) { @@ -155,26 +160,12 @@ at91_clk_register_slow_osc(void __iomem *sckcr, return &osc->clk; } -static void -of_at91sam9x5_clk_slow_osc_setup(struct device_node *np, void __iomem *sckcr) +static void at91_clk_unregister_slow_osc(struct clk *clk) { - struct clk *clk; - const char *parent_name; - const char *name = np->name; - u32 startup; - bool bypass; - - parent_name = of_clk_get_parent_name(np, 0); - of_property_read_string(np, "clock-output-names", &name); - of_property_read_u32(np, "atmel,startup-time-usec", &startup); - bypass = of_property_read_bool(np, "atmel,osc-bypass"); - - clk = at91_clk_register_slow_osc(sckcr, name, parent_name, startup, - bypass); - if (IS_ERR(clk)) - return; + struct clk_slow_osc *osc = to_clk_slow_osc(clk); - of_clk_add_provider(np, of_clk_src_simple_get, clk); + clk_unregister(clk); + kfree(osc); } static unsigned long clk_slow_rc_osc_recalc_rate(struct clk *clk, @@ -190,7 +181,7 @@ static int clk_slow_rc_osc_enable(struct clk *clk) struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(clk); void __iomem *sckcr = osc->sckcr; - writel(readl(sckcr) | AT91_SCKC_RCEN, sckcr); + writel(readl(sckcr) | osc->bits->cr_rcen, sckcr); udelay(osc->startup_usec); @@ -202,14 +193,14 @@ static void clk_slow_rc_osc_disable(struct clk *clk) struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(clk); void __iomem *sckcr = osc->sckcr; - writel(readl(sckcr) & ~AT91_SCKC_RCEN, sckcr); + writel(readl(sckcr) & ~osc->bits->cr_rcen, sckcr); } static int clk_slow_rc_osc_is_enabled(struct clk *clk) { struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(clk); - return !!(readl(osc->sckcr) & AT91_SCKC_RCEN); + return !!(readl(osc->sckcr) & osc->bits->cr_rcen); } static const struct clk_ops slow_rc_osc_ops = { @@ -219,11 +210,13 @@ static const struct clk_ops slow_rc_osc_ops = { .recalc_rate = clk_slow_rc_osc_recalc_rate, }; -static struct clk * +static struct clk * __init at91_clk_register_slow_rc_osc(void __iomem *sckcr, const char *name, unsigned long frequency, - unsigned long startup) + unsigned long accuracy, + unsigned long startup, + const struct clk_slow_bits *bits) { struct clk_slow_rc_osc *osc; int ret; @@ -239,6 +232,7 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, /* init.flags = CLK_IGNORE_UNUSED; */ osc->sckcr = sckcr; + osc->bits = bits; osc->frequency = frequency; osc->startup_usec = startup; @@ -251,23 +245,12 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, return &osc->clk; } -static void -of_at91sam9x5_clk_slow_rc_osc_setup(struct device_node *np, void __iomem *sckcr) +static void at91_clk_unregister_slow_rc_osc(struct clk *clk) { - struct clk *clk; - u32 frequency = 0; - u32 startup = 0; - const char *name = np->name; - - of_property_read_string(np, "clock-output-names", &name); - of_property_read_u32(np, "clock-frequency", &frequency); - of_property_read_u32(np, "atmel,startup-time-usec", &startup); - - clk = at91_clk_register_slow_rc_osc(sckcr, name, frequency, startup); - if (IS_ERR(clk)) - return; + struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(clk); - of_clk_add_provider(np, of_clk_src_simple_get, clk); + clk_unregister(clk); + kfree(osc); } static int clk_sam9x5_slow_set_parent(struct clk *clk, u8 index) @@ -281,14 +264,14 @@ static int clk_sam9x5_slow_set_parent(struct clk *clk, u8 index) tmp = readl(sckcr); - if ((!index && !(tmp & AT91_SCKC_OSCSEL)) || - (index && (tmp & AT91_SCKC_OSCSEL))) + if ((!index && !(tmp & slowck->bits->cr_oscsel)) || + (index && (tmp & slowck->bits->cr_oscsel))) return 0; if (index) - tmp |= AT91_SCKC_OSCSEL; + tmp |= slowck->bits->cr_oscsel; else - tmp &= ~AT91_SCKC_OSCSEL; + tmp &= ~slowck->bits->cr_oscsel; writel(tmp, sckcr); @@ -301,7 +284,7 @@ static int clk_sam9x5_slow_get_parent(struct clk *clk) { struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(clk); - return !!(readl(slowck->sckcr) & AT91_SCKC_OSCSEL); + return !!(readl(slowck->sckcr) & slowck->bits->cr_oscsel); } static const struct clk_ops sam9x5_slow_ops = { @@ -309,11 +292,12 @@ static const struct clk_ops sam9x5_slow_ops = { .get_parent = clk_sam9x5_slow_get_parent, }; -static struct clk * +static struct clk * __init at91_clk_register_sam9x5_slow(void __iomem *sckcr, const char *name, const char **parent_names, - int num_parents) + int num_parents, + const struct clk_slow_bits *bits) { struct clk_sam9x5_slow *slowck; int ret; @@ -330,7 +314,8 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr, slowck->clk.parent_names = slowck->parent_names; slowck->clk.num_parents = num_parents; slowck->sckcr = sckcr; - slowck->parent = !!(readl(sckcr) & AT91_SCKC_OSCSEL); + slowck->bits = bits; + slowck->parent = !!(readl(sckcr) & slowck->bits->cr_oscsel); ret = clk_register(&slowck->clk); if (ret) { @@ -341,69 +326,183 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr, return &slowck->clk; } -static int -of_at91sam9x5_clk_slow_setup(struct device_node *np, void __iomem *sckcr) +static void at91_clk_unregister_sam9x5_slow(struct clk *clk) { - struct clk *clk; - const char *parent_names[2]; - unsigned int num_parents; - const char *name = np->name; + struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(clk); - num_parents = of_clk_get_parent_count(np); - if (num_parents == 0 || num_parents > 2) - return -EINVAL; + clk_unregister(clk); + kfree(slowck); +} + +static void __init at91sam9x5_sckc_register(struct device_node *np, + unsigned int rc_osc_startup_us, + const struct clk_slow_bits *bits) +{ + const char *parent_names[2] = { "slow_rc_osc", "slow_osc" }; + void __iomem *regbase = of_iomap(np, 0); + struct device_node *child = NULL; + const char *xtal_name; + struct clk *slow_rc, *slow_osc, *slowck; + bool bypass; + int ret; + + if (!regbase) + return; + + slow_rc = at91_clk_register_slow_rc_osc(regbase, parent_names[0], + 32768, 50000000, + rc_osc_startup_us, bits); + if (IS_ERR(slow_rc)) + return; + + xtal_name = of_clk_get_parent_name(np, 0); + if (!xtal_name) { + /* DT backward compatibility */ + child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow-osc"); + if (!child) + goto unregister_slow_rc; + + xtal_name = of_clk_get_parent_name(child, 0); + bypass = of_property_read_bool(child, "atmel,osc-bypass"); + + child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow"); + } else { + bypass = of_property_read_bool(np, "atmel,osc-bypass"); + } + + if (!xtal_name) + goto unregister_slow_rc; + + slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1], + xtal_name, 1200000, bypass, bits); + if (IS_ERR(slow_osc)) + goto unregister_slow_rc; + + slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, + 2, bits); + if (IS_ERR(slowck)) + goto unregister_slow_osc; + + /* DT backward compatibility */ + if (child) + ret = of_clk_add_provider(child, of_clk_src_simple_get, + slowck); + else + ret = of_clk_add_provider(np, of_clk_src_simple_get, slowck); + + if (WARN_ON(ret)) + goto unregister_slowck; - of_clk_parent_fill(np, parent_names, num_parents); + return; - of_property_read_string(np, "clock-output-names", &name); +unregister_slowck: + at91_clk_unregister_sam9x5_slow(slowck); +unregister_slow_osc: + at91_clk_unregister_slow_osc(slow_osc); +unregister_slow_rc: + at91_clk_unregister_slow_rc_osc(slow_rc); +} + +static const struct clk_slow_bits at91sam9x5_bits = { + .cr_rcen = BIT(0), + .cr_osc32en = BIT(1), + .cr_osc32byp = BIT(2), + .cr_oscsel = BIT(3), +}; - clk = at91_clk_register_sam9x5_slow(sckcr, name, parent_names, - num_parents); - if (IS_ERR(clk)) - return PTR_ERR(clk); +static void __init of_at91sam9x5_sckc_setup(struct device_node *np) +{ + at91sam9x5_sckc_register(np, 75, &at91sam9x5_bits); +} +CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc", + of_at91sam9x5_sckc_setup); - return of_clk_add_provider(np, of_clk_src_simple_get, clk); +static void __init of_sama5d3_sckc_setup(struct device_node *np) +{ + at91sam9x5_sckc_register(np, 500, &at91sam9x5_bits); } +CLK_OF_DECLARE(sama5d3_clk_sckc, "atmel,sama5d3-sckc", + of_sama5d3_sckc_setup); -static const struct of_device_id sckc_clk_ids[] = { - /* Slow clock */ - { - .compatible = "atmel,at91sam9x5-clk-slow-osc", - .data = of_at91sam9x5_clk_slow_osc_setup, - }, - { - .compatible = "atmel,at91sam9x5-clk-slow-rc-osc", - .data = of_at91sam9x5_clk_slow_rc_osc_setup, - }, - { - .compatible = "atmel,at91sam9x5-clk-slow", - .data = of_at91sam9x5_clk_slow_setup, - }, - { /*sentinel*/ } +static const struct clk_slow_bits at91sam9x60_bits = { + .cr_osc32en = BIT(1), + .cr_osc32byp = BIT(2), + .cr_oscsel = BIT(24), }; -static int of_at91sam9x5_sckc_setup(struct device_node *np) +static void __init of_sam9x60_sckc_setup(struct device_node *np) { - struct device_node *childnp; - void (*clk_setup)(struct device_node *, void __iomem *); - const struct of_device_id *clk_id; void __iomem *regbase = of_iomap(np, 0); + struct clk_onecell_data *clk_data; + struct clk *slow_rc, *slow_osc; + const char *xtal_name; + const char *parent_names[2] = { "slow_rc_osc", "slow_osc" }; + bool bypass; + int ret; if (!regbase) - return -ENOMEM; - - for_each_child_of_node(np, childnp) { - clk_id = of_match_node(sckc_clk_ids, childnp); - if (!clk_id) - continue; - clk_setup = clk_id->data; - clk_setup(childnp, regbase); - } + return; - return 0; + slow_rc = clk_register_fixed_rate(parent_names[0], NULL, 0, + 32768); + if (IS_ERR(slow_rc)) + return; + + xtal_name = of_clk_get_parent_name(np, 0); + if (!xtal_name) + goto unregister_slow_rc; + + bypass = of_property_read_bool(np, "atmel,osc-bypass"); + slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1], + xtal_name, 5000000, bypass, + &at91sam9x60_bits); + if (IS_ERR(slow_osc)) + goto unregister_slow_rc; + + clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) + goto unregister_slow_osc; + + /* MD_SLCK and TD_SLCK. */ + clk_data->clk_num = 2; + clk_data->clks = kcalloc(clk_data->clk_num, + sizeof(*clk_data->clks), GFP_KERNEL); + if (!clk_data->clks) + goto clk_data_free; + + clk_data->clks[0] = clk_register_fixed_rate("md_slck", + parent_names[0], + 0, 32768); + if (IS_ERR(clk_data->clks[0])) + goto clks_free; + + clk_data->clks[1] = at91_clk_register_sam9x5_slow(regbase, "td_slck", + parent_names, 2, + &at91sam9x60_bits); + if (IS_ERR(clk_data->clks[1])) + goto unregister_md_slck; + + ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); + if (WARN_ON(ret)) + goto unregister_td_slck; + + return; + +unregister_td_slck: + at91_clk_unregister_sam9x5_slow(clk_data->clks[1]); +unregister_md_slck: + clk_unregister(clk_data->clks[0]); +clks_free: + kfree(clk_data->clks); +clk_data_free: + kfree(clk_data); +unregister_slow_osc: + at91_clk_unregister_slow_osc(slow_osc); +unregister_slow_rc: + clk_unregister(slow_rc); } -CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc", - of_at91sam9x5_sckc_setup); +CLK_OF_DECLARE(sam9x60_clk_sckc, "microchip,sam9x60-sckc", + of_sam9x60_sckc_setup); static int clk_sama5d4_slow_osc_enable(struct clk *clk) { @@ -416,7 +515,7 @@ static int clk_sama5d4_slow_osc_enable(struct clk *clk) * Assume that if it has already been selected (for example by the * bootloader), enough time has aready passed. */ - if ((readl(osc->sckcr) & AT91_SCKC_OSCSEL)) { + if ((readl(osc->sckcr) & osc->bits->cr_oscsel)) { osc->prepared = true; return 0; } @@ -439,23 +538,24 @@ static const struct clk_ops sama5d4_slow_osc_ops = { .is_enabled = clk_sama5d4_slow_osc_is_enabled, }; -static int of_sama5d4_sckc_setup(struct device_node *np) +static const struct clk_slow_bits at91sama5d4_bits = { + .cr_oscsel = BIT(3), +}; + +static void __init of_sama5d4_sckc_setup(struct device_node *np) { void __iomem *regbase = of_iomap(np, 0); - struct clk *clk; + struct clk *slow_rc, *slowck; struct clk_sama5d4_slow_osc *osc; const char *parent_names[2] = { "slow_rc_osc", "slow_osc" }; - bool bypass; int ret; if (!regbase) - return -ENOMEM; - - clk = clk_fixed(parent_names[0], 32768); - if (IS_ERR(clk)) - return PTR_ERR(clk); + return; - bypass = of_property_read_bool(np, "atmel,osc-bypass"); + slow_rc = clk_fixed(parent_names[0], 32768); + if (IS_ERR(slow_rc)) + return; osc = xzalloc(sizeof(*osc)); osc->parent_name = of_clk_get_parent_name(np, 0); @@ -463,23 +563,36 @@ static int of_sama5d4_sckc_setup(struct device_node *np) osc->clk.ops = &sama5d4_slow_osc_ops; osc->clk.parent_names = &osc->parent_name; osc->clk.num_parents = 1; + + /* osc->clk.flags = CLK_IGNORE_UNUSED; */ + osc->sckcr = regbase; osc->startup_usec = 1200000; - - if (bypass) - writel((readl(regbase) | AT91_SCKC_OSC32BYP), regbase); + osc->bits = &at91sama5d4_bits; ret = clk_register(&osc->clk); - if (ret) { - kfree(osc); - return ret; - } - - clk = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2); - if (IS_ERR(clk)) - return PTR_ERR(clk); - - return of_clk_add_provider(np, of_clk_src_simple_get, clk); + if (ret) + goto free_slow_osc_data; + + slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", + parent_names, 2, + &at91sama5d4_bits); + if (IS_ERR(slowck)) + goto unregister_slow_osc; + + ret = of_clk_add_provider(np, of_clk_src_simple_get, slowck); + if (WARN_ON(ret)) + goto unregister_slowck; + + return; + +unregister_slowck: + at91_clk_unregister_sam9x5_slow(slowck); +unregister_slow_osc: + clk_unregister(&osc->clk); +free_slow_osc_data: + kfree(osc); + clk_unregister(slow_rc); } CLK_OF_DECLARE(sama5d4_clk_sckc, "atmel,sama5d4-sckc", of_sama5d4_sckc_setup); diff --git a/drivers/clk/clk-ar933x.c b/drivers/clk/clk-ar933x.c index f5cfd39cd8..875e9f506f 100644 --- a/drivers/clk/clk-ar933x.c +++ b/drivers/clk/clk-ar933x.c @@ -1,19 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com> * * Based on the Linux ath79 clock code - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> diff --git a/drivers/clk/clk-ar9344.c b/drivers/clk/clk-ar9344.c index c3c49fb109..ad0e5c10e9 100644 --- a/drivers/clk/clk-ar9344.c +++ b/drivers/clk/clk-ar9344.c @@ -1,14 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2017 Oleksij Rempel <linux@rempel-privat.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. */ #include <common.h> diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index e21ab98453..e0f543bc1c 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -1,19 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Taken from linux/drivers/clk/ * * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c index 93271b4f99..0bd99993cc 100644 --- a/drivers/clk/clk-conf.c +++ b/drivers/clk/clk-conf.c @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Samsung Electronics Co., Ltd. * Sylwester Nawrocki <s.nawrocki@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <common.h> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 78b4153171..cad902fd32 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -1,18 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * clk-divider.c - generic barebox clock support. Based on Linux clk support * * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> #include <io.h> diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 021c43339f..e7738775f8 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -1,18 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * clk-fixed-factor.c - generic barebox clock support. Based on Linux clk support * * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> #include <io.h> diff --git a/drivers/clk/clk-fixed.c b/drivers/clk/clk-fixed.c index 57bf36b39e..d7ac59c4d4 100644 --- a/drivers/clk/clk-fixed.c +++ b/drivers/clk/clk-fixed.c @@ -1,18 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * clk-fixed.c - generic barebox clock support. Based on Linux clk support * * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> #include <malloc.h> @@ -37,17 +27,31 @@ static struct clk_ops clk_fixed_ops = { .is_enabled = clk_is_enabled_always, }; -struct clk *clk_fixed(const char *name, int rate) +struct clk *clk_register_fixed_rate(const char *name, + const char *parent_name, unsigned long flags, + unsigned long rate) { struct clk_fixed *fix = xzalloc(sizeof *fix); + const char **parent_names = NULL; int ret; fix->rate = rate; fix->clk.ops = &clk_fixed_ops; fix->clk.name = name; + fix->clk.flags = flags; + + if (parent_name) { + parent_names = kzalloc(sizeof(const char *), GFP_KERNEL); + if (!parent_names) + return ERR_PTR(-ENOMEM); + + fix->clk.parent_names = parent_names; + fix->clk.num_parents = 1; + } ret = clk_register(&fix->clk); if (ret) { + free(parent_names); free(fix); return ERR_PTR(ret); } diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index 1504f7a728..6f0763b05f 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Intel Corporation * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Adjustable fractional divider clock implementation. * Output rate = (m / n) * parent_rate. */ diff --git a/drivers/clk/clk-gate-shared.c b/drivers/clk/clk-gate-shared.c index c3b678a311..54c002e836 100644 --- a/drivers/clk/clk-gate-shared.c +++ b/drivers/clk/clk-gate-shared.c @@ -1,18 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * clk-gate-shared.c - generic barebox clock support. Based on Linux clk support * * Copyright (c) 2017 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> #include <io.h> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index b2b160555e..59dd643b99 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -1,18 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * clk-gate.c - generic barebox clock support. Based on Linux clk support * * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> #include <io.h> diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c index 352c85dfe2..1345fbc9ea 100644 --- a/drivers/clk/clk-gpio.c +++ b/drivers/clk/clk-gpio.c @@ -1,19 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * clk-gpio.c - clock that can be enabled and disabled via GPIO output * Based on Linux clk support * * Copyright (c) 2018 Nikita Yushchenko <nikita.yoush@cogentembedded.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> #include <malloc.h> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index e9cb614005..a4743c51b0 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -1,18 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * clk-mux.c - generic barebox clock support. Based on Linux clk support * * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> #include <io.h> diff --git a/drivers/clk/clk-qoric.c b/drivers/clk/clk-qoric.c index c40c6e90d9..2ffc7613fa 100644 --- a/drivers/clk/clk-qoric.c +++ b/drivers/clk/clk-qoric.c @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright 2013 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * clock driver for Freescale QorIQ SoCs. */ diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index b27ad6d249..4386c95aa9 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1,18 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * clk.c - generic barebox clock support. Based on Linux clk support * * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> #include <errno.h> diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c index f67a5c4d98..462a7e16ef 100644 --- a/drivers/clk/clkdev.c +++ b/drivers/clk/clkdev.c @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * drivers/clk/lookup_clkdev.c * * Copyright (C) 2008 Russell King. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Helper for the clk API to assist looking up a struct clk. */ diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index e627ef4a09..b1ce9d3d3e 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_COMMON_CLK) += \ clk-composite-8m.o \ clk-pllv1.o \ diff --git a/drivers/clk/imx/clk-cpu.c b/drivers/clk/imx/clk-cpu.c index 473500131e..13b2dfc9ad 100644 --- a/drivers/clk/imx/clk-cpu.c +++ b/drivers/clk/imx/clk-cpu.c @@ -1,12 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 Lucas Stach <l.stach@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <common.h> diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c index def870e244..b3d665cff9 100644 --- a/drivers/clk/imx/clk-frac-pll.c +++ b/drivers/clk/imx/clk-frac-pll.c @@ -1,12 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2017 NXP. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <common.h> diff --git a/drivers/clk/imx/clk-gate-exclusive.c b/drivers/clk/imx/clk-gate-exclusive.c index db88db0237..4bf4de8bd3 100644 --- a/drivers/clk/imx/clk-gate-exclusive.c +++ b/drivers/clk/imx/clk-gate-exclusive.c @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright 2014 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <common.h> diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index 8d5ed7e05c..88eaae8db3 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -1,16 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * clk-gate2.c - barebox 2-bit clock support. Based on Linux clk support - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> diff --git a/drivers/clk/imx/clk-imx1.c b/drivers/clk/imx/clk-imx1.c index 9a817c36c0..258b9dd582 100644 --- a/drivers/clk/imx/clk-imx1.c +++ b/drivers/clk/imx/clk-imx1.c @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. */ #include <common.h> diff --git a/drivers/clk/imx/clk-imx21.c b/drivers/clk/imx/clk-imx21.c index 546461b8ee..0026a55f86 100644 --- a/drivers/clk/imx/clk-imx21.c +++ b/drivers/clk/imx/clk-imx21.c @@ -1,21 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. */ #include <common.h> diff --git a/drivers/clk/imx/clk-imx25.c b/drivers/clk/imx/clk-imx25.c index ce4fbed68c..7c2140c215 100644 --- a/drivers/clk/imx/clk-imx25.c +++ b/drivers/clk/imx/clk-imx25.c @@ -1,19 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2009 by Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. */ #include <common.h> diff --git a/drivers/clk/imx/clk-imx27.c b/drivers/clk/imx/clk-imx27.c index 4b63244211..cba655c6fe 100644 --- a/drivers/clk/imx/clk-imx27.c +++ b/drivers/clk/imx/clk-imx27.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only #include <common.h> #include <init.h> #include <driver.h> diff --git a/drivers/clk/imx/clk-imx31.c b/drivers/clk/imx/clk-imx31.c index dbb5c15d12..5fded58b11 100644 --- a/drivers/clk/imx/clk-imx31.c +++ b/drivers/clk/imx/clk-imx31.c @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. */ #include <common.h> diff --git a/drivers/clk/imx/clk-imx35.c b/drivers/clk/imx/clk-imx35.c index af6c4058d7..17e2ae5e69 100644 --- a/drivers/clk/imx/clk-imx35.c +++ b/drivers/clk/imx/clk-imx35.c @@ -1,10 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * */ #include <common.h> #include <init.h> diff --git a/drivers/clk/imx/clk-imx5.c b/drivers/clk/imx/clk-imx5.c index 69ac2f5e3e..6a07816427 100644 --- a/drivers/clk/imx/clk-imx5.c +++ b/drivers/clk/imx/clk-imx5.c @@ -1,10 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * */ #include <common.h> #include <init.h> diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c index ed29e8c271..b8b37a0c68 100644 --- a/drivers/clk/imx/clk-imx6.c +++ b/drivers/clk/imx/clk-imx6.c @@ -1,13 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <common.h> diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c index 89ede769f8..6ccc36e3b9 100644 --- a/drivers/clk/imx/clk-imx6sl.c +++ b/drivers/clk/imx/clk-imx6sl.c @@ -1,12 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2014 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <dt-bindings/clock/imx6sl-clock.h> diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index d758957d4d..d682e41e7c 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -1,12 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2014 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <dt-bindings/clock/imx6sx-clock.h> diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index 35483efde6..79b52b7ce9 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -1,12 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <common.h> diff --git a/drivers/clk/imx/clk-imx7.c b/drivers/clk/imx/clk-imx7.c index 781bc43e09..1f15d7ef11 100644 --- a/drivers/clk/imx/clk-imx7.c +++ b/drivers/clk/imx/clk-imx7.c @@ -1,12 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <common.h> @@ -866,4 +860,4 @@ static int imx7_ccm_init(void) { return platform_driver_register(&imx7_ccm_driver); } -core_initcall(imx7_ccm_init);
\ No newline at end of file +core_initcall(imx7_ccm_init); diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c index 8f6d5ad7a8..eb2b1700ae 100644 --- a/drivers/clk/imx/clk-pfd.c +++ b/drivers/clk/imx/clk-pfd.c @@ -1,13 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2012 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <common.h> diff --git a/drivers/clk/imx/clk-pllv1.c b/drivers/clk/imx/clk-pllv1.c index f992134f7e..9b5d28f22f 100644 --- a/drivers/clk/imx/clk-pllv1.c +++ b/drivers/clk/imx/clk-pllv1.c @@ -1,15 +1,5 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later + #include <common.h> #include <init.h> #include <driver.h> diff --git a/drivers/clk/imx/clk-pllv2.c b/drivers/clk/imx/clk-pllv2.c index 5ba07fa5e6..56005ca725 100644 --- a/drivers/clk/imx/clk-pllv2.c +++ b/drivers/clk/imx/clk-pllv2.c @@ -1,15 +1,5 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later + #include <common.h> #include <init.h> #include <driver.h> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 44642e88f3..e10b61b040 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -1,15 +1,5 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later + #include <common.h> #include <init.h> #include <driver.h> diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c index bbfd95a11c..aabab27a22 100644 --- a/drivers/clk/imx/clk-sccg-pll.c +++ b/drivers/clk/imx/clk-sccg-pll.c @@ -1,12 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2017 NXP. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <common.h> diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c index 4f7e097a89..1bd1fe5c44 100644 --- a/drivers/clk/imx/clk-vf610.c +++ b/drivers/clk/imx/clk-vf610.c @@ -1,11 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012-2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * */ #include <common.h> diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index 7488dfcdc8..0994a149ad 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only #include <common.h> #include <init.h> #include <driver.h> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 39eff9ee74..5cd2c56a1b 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __IMX_CLK_H #define __IMX_CLK_H diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile index 53c759e4ef..63beb80722 100644 --- a/drivers/clk/mvebu/Makefile +++ b/drivers/clk/mvebu/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only obj-y += common.o obj-$(CONFIG_ARCH_ARMADA_370) += armada-370.o corediv.o obj-$(CONFIG_ARCH_ARMADA_XP) += armada-xp.o corediv.o diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c index 8d02ed93d9..d2ad1ba0cc 100644 --- a/drivers/clk/mvebu/armada-370.c +++ b/drivers/clk/mvebu/armada-370.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Marvell Armada 370 SoC clocks * @@ -5,10 +6,6 @@ * * Based on Linux Marvell MVEBU clock providers * Copyright (C) 2012 Marvell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include <common.h> diff --git a/drivers/clk/mvebu/armada-38x.c b/drivers/clk/mvebu/armada-38x.c index d2d7c2a225..627de7de6c 100644 --- a/drivers/clk/mvebu/armada-38x.c +++ b/drivers/clk/mvebu/armada-38x.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Marvell Armada 380/385 SoC clocks * @@ -6,10 +7,6 @@ * Gregory CLEMENT <gregory.clement@free-electrons.com> * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> * Andrew Lunn <andrew@lunn.ch> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include <common.h> diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c index ffe4f2736d..d79f846d3f 100644 --- a/drivers/clk/mvebu/armada-xp.c +++ b/drivers/clk/mvebu/armada-xp.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Marvell Armada XP SoC clocks * @@ -5,10 +6,6 @@ * * Based on Linux Marvell MVEBU clock providers * Copyright (C) 2012 Marvell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include <common.h> diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c index 609e63697c..c7de00ac77 100644 --- a/drivers/clk/mvebu/common.c +++ b/drivers/clk/mvebu/common.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Marvell EBU SoC common clock handling * @@ -5,10 +6,6 @@ * * Based on Linux Marvell MVEBU clock providers * Copyright (C) 2012 Marvell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include <common.h> diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h index a3b27247f7..8256d9c2f0 100644 --- a/drivers/clk/mvebu/common.h +++ b/drivers/clk/mvebu/common.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Marvell EBU SoC common clock handling * @@ -5,10 +6,6 @@ * * Based on Linux Marvell MVEBU clock providers * Copyright (C) 2012 Marvell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #ifndef __CLK_MVEBU_COMMON_H_ diff --git a/drivers/clk/mvebu/corediv.c b/drivers/clk/mvebu/corediv.c index 87b1f8bd7c..f740161e45 100644 --- a/drivers/clk/mvebu/corediv.c +++ b/drivers/clk/mvebu/corediv.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * MVEBU Core divider clock * @@ -6,10 +7,6 @@ * Based on Linux driver * Copyright (C) 2013 Marvell * Ezequiel Garcia <ezequiel.garcia@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include <common.h> diff --git a/drivers/clk/mvebu/dove.c b/drivers/clk/mvebu/dove.c index 9bdf89a623..ca9af2671d 100644 --- a/drivers/clk/mvebu/dove.c +++ b/drivers/clk/mvebu/dove.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Marvell Dove SoC clocks * @@ -5,10 +6,6 @@ * * Based on Linux Marvell MVEBU clock providers * Copyright (C) 2012 Marvell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include <common.h> diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c index 5024baf18e..252bf2c69a 100644 --- a/drivers/clk/mvebu/kirkwood.c +++ b/drivers/clk/mvebu/kirkwood.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Marvell Kirkwood SoC clocks * @@ -5,10 +6,6 @@ * * Based on Linux Marvell MVEBU clock providers * Copyright (C) 2012 Marvell - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include <common.h> diff --git a/drivers/clk/mxs/Makefile b/drivers/clk/mxs/Makefile index fb4e5dbeea..e1e3e5d70f 100644 --- a/drivers/clk/mxs/Makefile +++ b/drivers/clk/mxs/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_ARCH_MXS) += clk-ref.o clk-pll.o clk-frac.o clk-div.o obj-$(CONFIG_DRIVER_VIDEO_STM) += clk-lcdif.o diff --git a/drivers/clk/mxs/clk-div.c b/drivers/clk/mxs/clk-div.c index 797e5a274f..104587a8dc 100644 --- a/drivers/clk/mxs/clk-div.c +++ b/drivers/clk/mxs/clk-div.c @@ -1,12 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <common.h> diff --git a/drivers/clk/mxs/clk-frac.c b/drivers/clk/mxs/clk-frac.c index 7aa85045a4..21e572ff6f 100644 --- a/drivers/clk/mxs/clk-frac.c +++ b/drivers/clk/mxs/clk-frac.c @@ -1,12 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <common.h> diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c index 526efc52be..dae8e348e2 100644 --- a/drivers/clk/mxs/clk-imx23.c +++ b/drivers/clk/mxs/clk-imx23.c @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. */ #include <common.h> diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index 12bc9dd977..4adb1c6866 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. */ #include <common.h> diff --git a/drivers/clk/mxs/clk-lcdif.c b/drivers/clk/mxs/clk-lcdif.c index 86dfe890f9..246e68068d 100644 --- a/drivers/clk/mxs/clk-lcdif.c +++ b/drivers/clk/mxs/clk-lcdif.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only #include <common.h> #include <io.h> #include <linux/clk.h> diff --git a/drivers/clk/mxs/clk-pll.c b/drivers/clk/mxs/clk-pll.c index 1b1c9b3543..7527a77731 100644 --- a/drivers/clk/mxs/clk-pll.c +++ b/drivers/clk/mxs/clk-pll.c @@ -1,12 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <common.h> diff --git a/drivers/clk/mxs/clk-ref.c b/drivers/clk/mxs/clk-ref.c index 8d0be05615..16a2fc2991 100644 --- a/drivers/clk/mxs/clk-ref.c +++ b/drivers/clk/mxs/clk-ref.c @@ -1,12 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <common.h> diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h index 00895de507..60f2408cba 100644 --- a/drivers/clk/mxs/clk.h +++ b/drivers/clk/mxs/clk.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __MXS_CLK_H #define __MXS_CLK_H diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index e43f57304c..5fcf0c2515 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only obj-y += clk-cpu.o clk-pll.o clk.o obj-$(CONFIG_ARCH_RK3188) += clk-rk3188.o obj-$(CONFIG_ARCH_RK3288) += clk-rk3288.o diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 226b819242..71a64f71f6 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> @@ -6,10 +7,6 @@ * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Author: Thomas Abraham <thomas.ab@samsung.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * A CPU clock is defined as a clock supplied to a CPU or a group of CPUs. * The CPU clock is typically derived from a hierarchy of clock * blocks which includes mux and divider blocks. There are a number of other diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 39ccf0a226..8d3fd6cf1c 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1,16 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <asm-generic/div64.h> diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index 9340739945..61dfb27ef4 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -1,16 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index dcfaae2407..b6c122d393 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -1,16 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 9e0cbadd57..833e9bed0e 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> @@ -8,16 +9,6 @@ * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Copyright (c) 2013 Linaro Ltd. * Author: Thomas Abraham <thomas.ab@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index d6798a9055..006225b7e8 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> @@ -8,16 +9,6 @@ * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Copyright (c) 2013 Linaro Ltd. * Author: Thomas Abraham <thomas.ab@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef CLK_ROCKCHIP_CLK_H diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile index 341e6433e5..0a195cbf3f 100644 --- a/drivers/clk/socfpga/Makefile +++ b/drivers/clk/socfpga/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only obj-y += clk.o obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += clk-gate-a10.o clk-periph-a10.o clk-pll-a10.o diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index 07f6026c2e..401eb20d24 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Altera Corporation. All rights reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c index 9dd7fc9c25..4ef00052e4 100644 --- a/drivers/clk/socfpga/clk-periph-a10.c +++ b/drivers/clk/socfpga/clk-periph-a10.c @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Altera Corporation. All rights reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index 4dae3e537b..12d6ef6fc3 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Altera Corporation. All rights reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> #include <io.h> diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c index ade608ffe3..1d34b15caf 100644 --- a/drivers/clk/socfpga/clk.c +++ b/drivers/clk/socfpga/clk.c @@ -1,14 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h index cea3fcf5ee..9d291f7243 100644 --- a/drivers/clk/socfpga/clk.h +++ b/drivers/clk/socfpga/clk.h @@ -1,17 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de> * * based on drivers/clk/tegra/clk.h - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * */ #ifndef __SOCFPGA_CLK_H diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index 75569c79fe..343eb8ab83 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only obj-y += clk.o obj-y += clk-divider.o obj-y += clk-periph.o diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index 0ddd64ecd6..28a1342bbf 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -1,19 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> * * Based on the Linux Tegra clock code - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index b4182861e7..0cd5200e84 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c @@ -1,19 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de> * * Based on the Linux Tegra clock code - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c index 52d8473d67..e186275563 100644 --- a/drivers/clk/tegra/clk-pll-out.c +++ b/drivers/clk/tegra/clk-pll-out.c @@ -1,19 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> * * Based on the Linux Tegra clock code - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index e677effba2..3ac49cae47 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1,19 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> * * Based on the Linux Tegra clock code - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index cec7b5f803..f5704b83c5 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1,19 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> * * Based on the Linux Tegra clock code - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 2f843bb9ac..9fccff6136 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1,19 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> * * Based on the Linux Tegra clock code - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 77f31d213e..3d3a7854ff 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1,19 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> * * Based on the Linux Tegra clock code - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index cb4d920203..26ff9f2580 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -1,19 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de> * * Based on the Linux Tegra clock code - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 10d03573fd..5195e6dba4 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -1,19 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> * * Based on the Linux Tegra clock code - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ /* struct tegra_clk_frac_div - fractional divider */ diff --git a/drivers/clk/vexpress/Makefile b/drivers/clk/vexpress/Makefile index c6869bac83..eae11492ec 100644 --- a/drivers/clk/vexpress/Makefile +++ b/drivers/clk/vexpress/Makefile @@ -1 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only obj-y += clk-vexpress-osc.o clk-sp810.o diff --git a/drivers/clk/vexpress/clk-sp810.c b/drivers/clk/vexpress/clk-sp810.c index 959661e19e..78ec67fd15 100644 --- a/drivers/clk/vexpress/clk-sp810.c +++ b/drivers/clk/vexpress/clk-sp810.c @@ -1,13 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * Copyright (C) 2013 ARM Limited */ diff --git a/drivers/clk/vexpress/clk-vexpress-osc.c b/drivers/clk/vexpress/clk-vexpress-osc.c index c0d6e6066e..6a24fa56c3 100644 --- a/drivers/clk/vexpress/clk-vexpress-osc.c +++ b/drivers/clk/vexpress/clk-vexpress-osc.c @@ -1,13 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only #include <common.h> #include <malloc.h> diff --git a/drivers/clk/zynq/Makefile b/drivers/clk/zynq/Makefile index 8fedfc77e4..a438159ab0 100644 --- a/drivers/clk/zynq/Makefile +++ b/drivers/clk/zynq/Makefile @@ -1 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only obj-y += clkc.o diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index a6d8ba92ca..1d9d28ea14 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013 Josh Cartwright <joshc@eso.teric.us> * Copyright (c) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> @@ -7,18 +8,6 @@ * Copyright (c) 2012 National Instruments * * Josh Cartwright <josh.cartwright@ni.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. */ #include <common.h> #include <init.h> diff --git a/drivers/clk/zynqmp/Makefile b/drivers/clk/zynqmp/Makefile index 9432cd3980..70f10bc22b 100644 --- a/drivers/clk/zynqmp/Makefile +++ b/drivers/clk/zynqmp/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only obj-y += clkc.o obj-y += clk-pll-zynqmp.o obj-y += clk-gate-zynqmp.o diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 39ddd159f9..8805cda39e 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -47,6 +47,10 @@ config CLOCKSOURCE_EFI_X86 bool "EFI X86 HW driver" depends on EFI_BOOTUP && X86 +config CLOCKSOURCE_KVX + bool "KVX core timer clocksource" + depends on KVX + config CLOCKSOURCE_MVEBU bool depends on ARCH_MVEBU diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index cba6344bbb..b4607f787f 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_CLOCKSOURCE_CLPS711X) += clps711x.o obj-$(CONFIG_CLOCKSOURCE_DIGIC) += digic.o obj-$(CONFIG_CLOCKSOURCE_EFI) += efi.o obj-$(CONFIG_CLOCKSOURCE_EFI_X86) += efi_x86.o +obj-$(CONFIG_CLOCKSOURCE_KVX) += kvx_timer.o obj-$(CONFIG_CLOCKSOURCE_MVEBU) += mvebu.o obj-$(CONFIG_CLOCKSOURCE_NOMADIK) += nomadik.o obj-$(CONFIG_CLOCKSOURCE_ORION) += orion.o diff --git a/drivers/clocksource/kvx_timer.c b/drivers/clocksource/kvx_timer.c new file mode 100644 index 0000000000..f16d77b9dd --- /dev/null +++ b/drivers/clocksource/kvx_timer.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2018 Kalray Inc. + */ + +#include <common.h> +#include <clock.h> +#include <init.h> + +#include <linux/clk.h> +#include <linux/err.h> + +#include <asm/sfr.h> + +static uint64_t kvx_pm_read(void) +{ + return kvx_sfr_get(PM0); +} + +static struct clocksource kvx_clksrc = { + .read = kvx_pm_read, + .mask = CLOCKSOURCE_MASK(64), + .shift = 0, +}; + +static int kvx_timer_probe(struct device_d *dev) +{ + struct clk *clk; + uint32_t clk_freq; + struct device_node *np = dev->device_node; + + /* Get clock frequency */ + clk = clk_get(dev, NULL); + if (IS_ERR(clk)) { + dev_err(dev, "Failed to get CPU clock: %ld\n", PTR_ERR(clk)); + return PTR_ERR(clk); + } + + clk_freq = clk_get_rate(clk); + clk_put(clk); + + /* Init clocksource */ + kvx_clksrc.mult = clocksource_hz2mult(clk_freq, kvx_clksrc.shift); + + return init_clock(&kvx_clksrc); +} + +static struct of_device_id kvx_timer_dt_ids[] = { + { .compatible = "kalray,kvx-core-timer", }, + { } +}; + +static struct driver_d kvx_timer_driver = { + .name = "kvx-timer", + .probe = kvx_timer_probe, + .of_compatible = DRV_OF_COMPAT(kvx_timer_dt_ids), +}; + +device_platform_driver(kvx_timer_driver); diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index f4cc71ef0e..412ec926c8 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1,4 +1,4 @@ -menu MFD +menu "Multifunction device drivers" config MFD_ACT8846 depends on I2C diff --git a/drivers/mfd/rave-sp.c b/drivers/mfd/rave-sp.c index 67f7d4c654..c6ad57d517 100644 --- a/drivers/mfd/rave-sp.c +++ b/drivers/mfd/rave-sp.c @@ -661,7 +661,7 @@ static int rave_sp_emulated_get_status(struct rave_sp *sp, return ret; status->general_status = - firmware_mode ? RAVE_SP_STATUS_GS_FIRMWARE_MODE : 0; + firmware_mode ? 0 : RAVE_SP_STATUS_GS_FIRMWARE_MODE; return 0; } diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c index f1e6559d71..38b25858ed 100644 --- a/drivers/mfd/syscon.c +++ b/drivers/mfd/syscon.c @@ -44,9 +44,6 @@ static struct syscon *of_syscon_register(struct device_node *np, bool check_clk) struct syscon *syscon; struct resource res; - if (!of_device_is_compatible(np, "syscon")) - return ERR_PTR(-EINVAL); - syscon = xzalloc(sizeof(*syscon)); if (of_address_to_resource(np, 0, &res)) { @@ -83,7 +80,7 @@ err_map: return ERR_PTR(ret); } -static struct syscon *node_to_syscon(struct device_node *np) +static struct syscon *node_to_syscon(struct device_node *np, bool check_clk) { struct syscon *entry, *syscon = NULL; @@ -94,7 +91,7 @@ static struct syscon *node_to_syscon(struct device_node *np) } if (!syscon) - syscon = of_syscon_register(np, true); + syscon = of_syscon_register(np, check_clk); if (IS_ERR(syscon)) return ERR_CAST(syscon); @@ -104,11 +101,25 @@ static struct syscon *node_to_syscon(struct device_node *np) static void __iomem *syscon_node_to_base(struct device_node *np) { - struct syscon *syscon = node_to_syscon(np); + struct syscon *syscon; + struct clk *clk; + + if (!of_device_is_compatible(np, "syscon")) + return ERR_PTR(-EINVAL); + syscon = node_to_syscon(np, true); if (IS_ERR(syscon)) return ERR_CAST(syscon); + /* Returning the direct pointer here side steps the regmap + * and any specified clock wouldn't be enabled on access. + * Deal with this by enabling the clock permanently if any + * syscon_node_to_base users exist. + */ + clk = of_clk_get(np, 0); + if (!IS_ERR(clk)) + clk_enable(clk); + return syscon->base; } @@ -143,16 +154,31 @@ void __iomem *syscon_base_lookup_by_phandle(struct device_node *np, return syscon_node_to_base(syscon_np); } -struct regmap *syscon_node_to_regmap(struct device_node *np) +static struct regmap *__device_node_to_regmap(struct device_node *np, + bool check_clk) { - struct syscon *syscon = node_to_syscon(np); + struct syscon *syscon; + syscon = node_to_syscon(np, check_clk); if (IS_ERR(syscon)) return ERR_CAST(syscon); return syscon->regmap; } +struct regmap *device_node_to_regmap(struct device_node *np) +{ + return __device_node_to_regmap(np, false); +} + +struct regmap *syscon_node_to_regmap(struct device_node *np) +{ + if (!of_device_is_compatible(np, "syscon")) + return ERR_PTR(-EINVAL); + + return __device_node_to_regmap(np, true); +} + struct regmap *syscon_regmap_lookup_by_compatible(const char *s) { struct device_node *syscon_np; diff --git a/drivers/mtd/nand/nand_denali.c b/drivers/mtd/nand/nand_denali.c index ddb03813fe..8995845649 100644 --- a/drivers/mtd/nand/nand_denali.c +++ b/drivers/mtd/nand/nand_denali.c @@ -171,7 +171,7 @@ static void reset_bank(struct denali_nand_info *denali) /* wait for completion */ while (ioread32(denali->flash_reg + DEVICE_RESET) & (1 << denali->flash_bank)) - barrier(); + cpu_relax(); } /* Reset the flash controller */ @@ -187,8 +187,7 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali) iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) - /* cpu_relax(); */ - barrier(); + cpu_relax(); if (ioread32(denali->flash_reg + INTR_STATUS(i)) & INTR_STATUS__TIME_OUT) dev_dbg(denali->dev, @@ -953,8 +952,7 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, */ while (!(read_interrupt_status(denali) & INTR_STATUS__ECC_TRANSACTION_DONE)) - /* cpu_relax(); */ - barrier(); + cpu_relax(); clear_interrupts(denali); denali_set_intr_modes(denali, true); } diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig index 7436fc2de1..9ed86afd74 100644 --- a/drivers/of/Kconfig +++ b/drivers/of/Kconfig @@ -4,7 +4,7 @@ config OFTREE config OFTREE_MEM_GENERIC depends on OFTREE - depends on PPC || ARM || EFI_BOOTUP || OPENRISC || SANDBOX || RISCV + depends on PPC || ARM || EFI_BOOTUP || OPENRISC || SANDBOX || RISCV || KVX def_bool y config DTC diff --git a/drivers/of/base.c b/drivers/of/base.c index 6d13b66a0e..72a3df4e6f 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -1681,6 +1681,31 @@ int of_get_available_child_count(const struct device_node *parent) EXPORT_SYMBOL(of_get_available_child_count); /** + * of_get_compatible_child - Find compatible child node + * @parent: parent node + * @compatible: compatible string + * + * Lookup child node whose compatible property contains the given compatible + * string. + * + * Returns a node pointer with refcount incremented, use of_node_put() on it + * when done; or NULL if not found. + */ +struct device_node *of_get_compatible_child(const struct device_node *parent, + const char *compatible) +{ + struct device_node *child; + + for_each_child_of_node(parent, child) { + if (of_device_is_compatible(child, compatible)) + return child; + } + + return NULL; +} +EXPORT_SYMBOL(of_get_compatible_child); + +/** * of_get_child_by_name - Find the child node by name for a given parent * @node: parent node * @name: child name to look for. diff --git a/drivers/pci/pci-layerscape.c b/drivers/pci/pci-layerscape.c index c4ed529181..53be43b28f 100644 --- a/drivers/pci/pci-layerscape.c +++ b/drivers/pci/pci-layerscape.c @@ -396,8 +396,8 @@ static int ls_pcie_of_fixup(struct device_node *root, void *ctx) ret = ls_pcie_get_iommu_handle(np, &iommu_handle); if (ret) { - dev_err(pcie->pci.dev, "Unable to get iommu phandle\n"); - return ret; + dev_info(pcie->pci.dev, "No iommu phandle, won't fixup\n"); + return 0; } if (ls_pcie_share_stream_id) { diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index 9d4344a94c..c8c8fa98e0 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -177,9 +177,9 @@ static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = { [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) }, [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) }, [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) }, - [IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) }, - [IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) }, - [IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) }, + [IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) }, + [IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) }, + [IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) }, [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) }, [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, @@ -228,9 +228,9 @@ static int imx8mq_reset_set(struct reset_controller_dev *rcdev, case IMX8MQ_RESET_PCIE_CTRL_APPS_EN: case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */ - case IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N: /* fallthrough */ - case IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N: /* fallthrough */ - case IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: /* fallthrough */ + case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */ case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */ case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */ value = assert ? 0 : bit; diff --git a/drivers/usb/gadget/dfu.c b/drivers/usb/gadget/dfu.c index c2b3d481af..9117a5b063 100644 --- a/drivers/usb/gadget/dfu.c +++ b/drivers/usb/gadget/dfu.c @@ -55,6 +55,8 @@ #include <libbb.h> #include <init.h> #include <fs.h> +#include <ioctl.h> +#include <linux/mtd/mtd-abi.h> #define USB_DT_DFU 0x21 @@ -132,6 +134,10 @@ struct file_list_entry *dfu_file_entry; static int dfufd = -EINVAL; static struct file_list *dfu_files; static int dfudetach; +static struct mtd_info_user dfu_mtdinfo; +static loff_t dfu_written; +static loff_t dfu_erased; +static int prog_erase; /* USB DFU functional descriptor */ static struct usb_dfu_func_descriptor usb_dfu_func = { @@ -233,7 +239,7 @@ dfu_bind(struct usb_configuration *c, struct usb_function *f) desc[i].bNumEndpoints = 0; desc[i].bInterfaceClass = 0xfe; desc[i].bInterfaceSubClass = 1; - desc[i].bInterfaceProtocol = 1; + desc[i].bInterfaceProtocol = 2; desc[i].bAlternateSetting = i; desc[i].iInterface = us[i + 1].id; header[i] = (struct usb_descriptor_header *)&desc[i]; @@ -271,6 +277,10 @@ dfu_unbind(struct usb_configuration *c, struct usb_function *f) { struct f_dfu *dfu = func_to_dfu(f); + dfu_files = NULL; + dfu_file_entry = NULL; + dfudetach = 0; + usb_free_all_descriptors(f); dma_free(dfu->dnreq->buf); @@ -315,6 +325,11 @@ static void dfu_cleanup(struct f_dfu *dfu) { struct stat s; + memset(&dfu_mtdinfo, 0, sizeof(dfu_mtdinfo)); + dfu_written = 0; + dfu_erased = 0; + prog_erase = 0; + if (dfufd > 0) { close(dfufd); dfufd = -EINVAL; @@ -327,8 +342,22 @@ static void dfu_cleanup(struct f_dfu *dfu) static void dn_complete(struct usb_ep *ep, struct usb_request *req) { struct f_dfu *dfu = req->context; + loff_t size; int ret; + if (prog_erase && (dfu_written + req->length) > dfu_erased) { + size = roundup(req->length, dfu_mtdinfo.erasesize); + ret = erase(dfufd, size, dfu_erased); + dfu_erased += size; + if (ret && ret != -ENOSYS) { + perror("erase"); + dfu->dfu_status = DFU_STATUS_errERASE; + dfu_cleanup(dfu); + return; + } + } + + dfu_written += req->length; ret = write(dfufd, req->buf, req->length); if (ret < (int)req->length) { perror("write"); @@ -342,38 +371,14 @@ static int handle_dnload(struct usb_function *f, const struct usb_ctrlrequest *c struct f_dfu *dfu = func_to_dfu(f); struct usb_composite_dev *cdev = f->config->cdev; u16 w_length = le16_to_cpu(ctrl->wLength); - int ret; if (w_length == 0) { - dfu->dfu_state = DFU_STATE_dfuIDLE; if (dfu_file_entry->flags & FILE_LIST_FLAG_SAFE) { - int fd; - unsigned flags = O_WRONLY; - - if (dfu_file_entry->flags & FILE_LIST_FLAG_CREATE) - flags |= O_CREAT | O_TRUNC; - - fd = open(dfu_file_entry->filename, flags); - if (fd < 0) { - perror("open"); - ret = -EINVAL; - goto err_out; - } - ret = erase(fd, ERASE_SIZE_ALL, 0); - close(fd); - if (ret && ret != -ENOSYS) { - perror("erase"); - ret = -EINVAL; - goto err_out; - } - ret = copy_file(DFU_TEMPFILE, dfu_file_entry->filename, 0); - if (ret) { - printf("copy file failed\n"); - ret = -EINVAL; - goto err_out; - } + dfu->dfu_state = DFU_STATE_dfuMANIFEST; + } else { + dfu->dfu_state = DFU_STATE_dfuIDLE; + dfu_cleanup(dfu); } - dfu_cleanup(dfu); return 0; } @@ -382,8 +387,51 @@ static int handle_dnload(struct usb_function *f, const struct usb_ctrlrequest *c usb_ep_queue(cdev->gadget->ep0, dfu->dnreq); return 0; +} -err_out: +static int handle_manifest(struct usb_function *f, const struct usb_ctrlrequest *ctrl) +{ + struct f_dfu *dfu = func_to_dfu(f); + int ret; + + dfu->dfu_state = DFU_STATE_dfuIDLE; + + if (dfu_file_entry->flags & FILE_LIST_FLAG_SAFE) { + int fd; + unsigned flags = O_WRONLY; + + if (dfu_file_entry->flags & FILE_LIST_FLAG_CREATE) + flags |= O_CREAT | O_TRUNC; + + fd = open(dfu_file_entry->filename, flags); + if (fd < 0) { + perror("open"); + dfu->dfu_status = DFU_STATUS_errERASE; + ret = -EINVAL; + goto out; + } + + ret = erase(fd, ERASE_SIZE_ALL, 0); + close(fd); + if (ret && ret != -ENOSYS) { + dfu->dfu_status = DFU_STATUS_errERASE; + perror("erase"); + goto out; + } + + ret = copy_file(DFU_TEMPFILE, dfu_file_entry->filename, 0); + if (ret) { + printf("copy file failed\n"); + ret = -EINVAL; + goto out; + } + } + + return 0; + +out: + dfu->dfu_status = DFU_STATUS_errWRITE; + dfu->dfu_state = DFU_STATE_dfuERROR; dfu_cleanup(dfu); return ret; } @@ -438,23 +486,17 @@ static int dfu_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) goto out; } - /* Allow GETSTATUS in every state */ - if (ctrl->bRequest == USB_REQ_DFU_GETSTATUS) { - value = dfu_status(f, ctrl); - value = min(value, w_length); - goto out; - } - - /* Allow GETSTATE in every state */ - if (ctrl->bRequest == USB_REQ_DFU_GETSTATE) { - *(u8 *)req->buf = dfu->dfu_state; - value = sizeof(u8); - goto out; - } - switch (dfu->dfu_state) { case DFU_STATE_dfuIDLE: switch (ctrl->bRequest) { + case USB_REQ_DFU_GETSTATUS: + value = dfu_status(f, ctrl); + value = min(value, w_length); + break; + case USB_REQ_DFU_GETSTATE: + *(u8 *)req->buf = dfu->dfu_state; + value = sizeof(u8); + break; case USB_REQ_DFU_DNLOAD: if (w_length == 0) { dfu->dfu_state = DFU_STATE_dfuERROR; @@ -479,11 +521,10 @@ static int dfu_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) goto out; } - ret = erase(dfufd, ERASE_SIZE_ALL, 0); - if (ret && ret != -ENOSYS) { - dfu->dfu_status = DFU_STATUS_errERASE; - perror("erase"); - goto out; + if (!(dfu_file_entry->flags & FILE_LIST_FLAG_SAFE)) { + ret = ioctl(dfufd, MEMGETINFO, &dfu_mtdinfo); + if (!ret) /* file is on a mtd device */ + prog_erase = 1; } value = handle_dnload(f, ctrl); @@ -520,9 +561,17 @@ static int dfu_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) break; case DFU_STATE_dfuDNLOAD_IDLE: switch (ctrl->bRequest) { + case USB_REQ_DFU_GETSTATUS: + value = dfu_status(f, ctrl); + value = min(value, w_length); + break; + case USB_REQ_DFU_GETSTATE: + *(u8 *)req->buf = dfu->dfu_state; + value = sizeof(u8); + break; case USB_REQ_DFU_DNLOAD: value = handle_dnload(f, ctrl); - if (dfu->dfu_state != DFU_STATE_dfuIDLE) { + if (dfu->dfu_state == DFU_STATE_dfuDNLOAD_IDLE) { return 0; } break; @@ -538,6 +587,14 @@ static int dfu_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) break; case DFU_STATE_dfuUPLOAD_IDLE: switch (ctrl->bRequest) { + case USB_REQ_DFU_GETSTATUS: + value = dfu_status(f, ctrl); + value = min(value, w_length); + break; + case USB_REQ_DFU_GETSTATE: + *(u8 *)req->buf = dfu->dfu_state; + value = sizeof(u8); + break; case USB_REQ_DFU_UPLOAD: handle_upload(f, ctrl); return 0; @@ -553,6 +610,14 @@ static int dfu_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) break; case DFU_STATE_dfuERROR: switch (ctrl->bRequest) { + case USB_REQ_DFU_GETSTATUS: + value = dfu_status(f, ctrl); + value = min(value, w_length); + break; + case USB_REQ_DFU_GETSTATE: + *(u8 *)req->buf = dfu->dfu_state; + value = sizeof(u8); + break; case USB_REQ_DFU_CLRSTATUS: dfu_abort(dfu); /* no zlp? */ @@ -564,10 +629,48 @@ static int dfu_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) break; } break; - case DFU_STATE_dfuDNLOAD_SYNC: - case DFU_STATE_dfuDNBUSY: case DFU_STATE_dfuMANIFEST_SYNC: + switch (ctrl->bRequest) { + case USB_REQ_DFU_GETSTATUS: + value = dfu_status(f, ctrl); + if (dfu_file_entry->flags & FILE_LIST_FLAG_SAFE) + dfu->dfu_state = DFU_STATE_dfuMANIFEST; + else + dfu->dfu_state = DFU_STATE_dfuIDLE; + value = min(value, w_length); + break; + case USB_REQ_DFU_GETSTATE: + *(u8 *)req->buf = dfu->dfu_state; + value = sizeof(u8); + break; + default: + dfu->dfu_state = DFU_STATE_dfuERROR; + value = -EINVAL; + break; + } + break; case DFU_STATE_dfuMANIFEST: + value = handle_manifest(f, ctrl); + if (dfu->dfu_state != DFU_STATE_dfuIDLE) { + return 0; + } + switch (ctrl->bRequest) { + case USB_REQ_DFU_GETSTATUS: + value = dfu_status(f, ctrl); + value = min(value, w_length); + break; + case USB_REQ_DFU_GETSTATE: + *(u8 *)req->buf = dfu->dfu_state; + value = sizeof(u8); + break; + default: + dfu->dfu_state = DFU_STATE_dfuERROR; + value = -EINVAL; + break; + } + break; + case DFU_STATE_dfuDNLOAD_SYNC: + case DFU_STATE_dfuDNBUSY: dfu->dfu_state = DFU_STATE_dfuERROR; value = -EINVAL; break; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 45dd41a2a2..fe979d9306 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -70,6 +70,12 @@ config WATCHDOG_ORION help Add support for watchdog on the Marvall Armada XP +config WATCHDOG_KVX + bool "KVX Core watchdog" + depends on KVX + help + Add support for the KVX core watchdog. + config WATCHDOG_BCM2835 bool "Watchdog for BCM283x SoCs" depends on ARCH_BCM283X diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 63efc2a87e..3af64db3f2 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_WATCHDOG_DW) += dw_wdt.o obj-$(CONFIG_WATCHDOG_JZ4740) += jz4740.o obj-$(CONFIG_WATCHDOG_IMX_RESET_SOURCE) += imxwd.o obj-$(CONFIG_WATCHDOG_IMX) += imxwd.o +obj-$(CONFIG_WATCHDOG_KVX) += kvx_wdt.o obj-$(CONFIG_WATCHDOG_ORION) += orion_wdt.o obj-$(CONFIG_ARCH_BCM283X) += bcm2835_wdt.o obj-$(CONFIG_RAVE_SP_WATCHDOG) += rave-sp-wdt.o diff --git a/drivers/watchdog/kvx_wdt.c b/drivers/watchdog/kvx_wdt.c new file mode 100644 index 0000000000..da19136fda --- /dev/null +++ b/drivers/watchdog/kvx_wdt.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2018 Kalray Inc. + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <of.h> +#include <watchdog.h> + +#include <linux/clk.h> +#include <linux/err.h> + +#include <asm/sfr.h> + +struct kvx_wdt { + uint64_t clk_rate; + struct watchdog wdd; +}; + +static void kvx_watchdog_disable(void) +{ + kvx_sfr_set_field(TCR, WUI, 0); + kvx_sfr_set_field(TCR, WCE, 0); +} + +static int kvx_wdt_set_timeout(struct watchdog *wdd, unsigned int timeout) +{ + struct kvx_wdt *wdt = container_of(wdd, struct kvx_wdt, wdd); + uint64_t cycle_timeout = wdt->clk_rate * timeout; + + /* Disable watchdog */ + if (timeout == 0) { + kvx_watchdog_disable(); + return 0; + } + + kvx_sfr_set(WDV, cycle_timeout); + kvx_sfr_set(WDR, 0); + + /* Start watchdog counting */ + kvx_sfr_set_field(TCR, WUI, 1); + kvx_sfr_set_field(TCR, WCE, 1); + + return 0; +} + +static int count; + +static int kvx_wdt_drv_probe(struct device_d *dev) +{ + struct watchdog *wdd; + struct clk *clk; + struct kvx_wdt *kvx_wdt; + + if (count != 0) { + dev_warn(dev, "Tried to register core watchdog twice\n"); + return -EINVAL; + } + count++; + + kvx_wdt = xzalloc(sizeof(*kvx_wdt)); + clk = clk_get(dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + kvx_wdt->clk_rate = clk_get_rate(clk); + clk_put(clk); + + wdd = &kvx_wdt->wdd; + wdd->name = "kvx_wdt"; + wdd->hwdev = dev; + wdd->set_timeout = kvx_wdt_set_timeout; + + /* Be sure that interrupt are disable */ + kvx_sfr_set_field(TCR, WIE, 0); + + kvx_watchdog_disable(); + + return watchdog_register(wdd); +} + +static struct of_device_id kvx_wdt_of_match[] = { + { .compatible = "kalray,kvx-core-watchdog", }, + { /* sentinel */ } +}; + +static struct driver_d kvx_wdt_driver = { + .name = "kvx-wdt", + .probe = kvx_wdt_drv_probe, + .of_compatible = DRV_OF_COMPAT(kvx_wdt_of_match), +}; +device_platform_driver(kvx_wdt_driver); diff --git a/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml b/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml index 33c7842917..8b9a8f337f 100644 --- a/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml +++ b/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml @@ -23,6 +23,8 @@ properties: - items: - const: allwinner,sun7i-a20-crypto - const: allwinner,sun4i-a10-crypto + - items: + - const: allwinner,sun8i-a33-crypto reg: maxItems: 1 diff --git a/dts/Bindings/input/cypress,tm2-touchkey.txt b/dts/Bindings/input/cypress,tm2-touchkey.txt index ef2ae72971..921172f689 100644 --- a/dts/Bindings/input/cypress,tm2-touchkey.txt +++ b/dts/Bindings/input/cypress,tm2-touchkey.txt @@ -5,6 +5,7 @@ Required properties: * "cypress,tm2-touchkey" - for the touchkey found on the tm2 board * "cypress,midas-touchkey" - for the touchkey found on midas boards * "cypress,aries-touchkey" - for the touchkey found on aries boards + * "coreriver,tc360-touchkey" - for the Coreriver TouchCore 360 touchkey - reg: I2C address of the chip. - interrupts: interrupt to which the chip is connected (see interrupt binding[0]). diff --git a/dts/Bindings/vendor-prefixes.yaml b/dts/Bindings/vendor-prefixes.yaml index 9e67944bec..b3c8c62374 100644 --- a/dts/Bindings/vendor-prefixes.yaml +++ b/dts/Bindings/vendor-prefixes.yaml @@ -205,6 +205,8 @@ patternProperties: description: Colorful GRP, Shenzhen Xueyushi Technology Ltd. "^compulab,.*": description: CompuLab Ltd. + "^coreriver,.*": + description: CORERIVER Semiconductor Co.,Ltd. "^corpro,.*": description: Chengdu Corpro Technology Co., Ltd. "^cortina,.*": diff --git a/dts/include/dt-bindings/input/linux-event-codes.h b/dts/include/dt-bindings/input/linux-event-codes.h index 0f1db1cccc..6923dc7e02 100644 --- a/dts/include/dt-bindings/input/linux-event-codes.h +++ b/dts/include/dt-bindings/input/linux-event-codes.h @@ -652,6 +652,9 @@ /* Electronic privacy screen control */ #define KEY_PRIVACY_SCREEN_TOGGLE 0x279 +/* Select an area of screen to be copied */ +#define KEY_SELECTIVE_SCREENSHOT 0x27a + /* * Some keyboards have keys which do not have a defined meaning, these keys * are intended to be programmed / bound to macros by the user. For most diff --git a/dts/src/arm/bcm2835-rpi-zero-w.dts b/dts/src/arm/bcm2835-rpi-zero-w.dts index b75af21069..4c3f606e5b 100644 --- a/dts/src/arm/bcm2835-rpi-zero-w.dts +++ b/dts/src/arm/bcm2835-rpi-zero-w.dts @@ -112,6 +112,7 @@ &sdhci { #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; bus-width = <4>; mmc-pwrseq = <&wifi_pwrseq>; diff --git a/dts/src/arm/bcm2835-rpi.dtsi b/dts/src/arm/bcm2835-rpi.dtsi index 394c8a71b1..fd2c766e0f 100644 --- a/dts/src/arm/bcm2835-rpi.dtsi +++ b/dts/src/arm/bcm2835-rpi.dtsi @@ -15,6 +15,7 @@ firmware: firmware { compatible = "raspberrypi,bcm2835-firmware", "simple-bus"; mboxes = <&mailbox>; + dma-ranges; }; power: power { diff --git a/dts/src/arm/dm8148-evm.dts b/dts/src/arm/dm8148-evm.dts index 3931fb068f..91d1018ab7 100644 --- a/dts/src/arm/dm8148-evm.dts +++ b/dts/src/arm/dm8148-evm.dts @@ -24,12 +24,12 @@ &cpsw_emac0 { phy-handle = <ðphy0>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &cpsw_emac1 { phy-handle = <ðphy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &davinci_mdio { diff --git a/dts/src/arm/dm8148-t410.dts b/dts/src/arm/dm8148-t410.dts index 9e43d5ec0b..79ccdd4470 100644 --- a/dts/src/arm/dm8148-t410.dts +++ b/dts/src/arm/dm8148-t410.dts @@ -33,12 +33,12 @@ &cpsw_emac0 { phy-handle = <ðphy0>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &cpsw_emac1 { phy-handle = <ðphy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &davinci_mdio { diff --git a/dts/src/arm/dra62x-j5eco-evm.dts b/dts/src/arm/dra62x-j5eco-evm.dts index 861ab90a3f..c16e183822 100644 --- a/dts/src/arm/dra62x-j5eco-evm.dts +++ b/dts/src/arm/dra62x-j5eco-evm.dts @@ -24,12 +24,12 @@ &cpsw_emac0 { phy-handle = <ðphy0>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &cpsw_emac1 { phy-handle = <ðphy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &davinci_mdio { diff --git a/dts/src/arm/dra7.dtsi b/dts/src/arm/dra7.dtsi index 4305051bb7..5f5ee16f07 100644 --- a/dts/src/arm/dra7.dtsi +++ b/dts/src/arm/dra7.dtsi @@ -148,6 +148,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0xc0000000>; + dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; ti,hwmods = "l3_main_1", "l3_main_2"; reg = <0x0 0x44000000 0x0 0x1000000>, <0x0 0x45000000 0x0 0x1000>; diff --git a/dts/src/arm/exynos4412-galaxy-s3.dtsi b/dts/src/arm/exynos4412-galaxy-s3.dtsi index 31719c079d..44f97546dd 100644 --- a/dts/src/arm/exynos4412-galaxy-s3.dtsi +++ b/dts/src/arm/exynos4412-galaxy-s3.dtsi @@ -33,7 +33,7 @@ }; }; - lcd_vdd3_reg: voltage-regulator-6 { + lcd_vdd3_reg: voltage-regulator-7 { compatible = "regulator-fixed"; regulator-name = "LCD_VDD_2.2V"; regulator-min-microvolt = <2200000>; @@ -42,7 +42,7 @@ enable-active-high; }; - ps_als_reg: voltage-regulator-7 { + ps_als_reg: voltage-regulator-8 { compatible = "regulator-fixed"; regulator-name = "LED_A_3.0V"; regulator-min-microvolt = <3000000>; diff --git a/dts/src/arm/exynos4412-n710x.dts b/dts/src/arm/exynos4412-n710x.dts index 98cd1284cd..4189e1fb20 100644 --- a/dts/src/arm/exynos4412-n710x.dts +++ b/dts/src/arm/exynos4412-n710x.dts @@ -13,7 +13,7 @@ /* bootargs are passed in by bootloader */ - cam_vdda_reg: voltage-regulator-6 { + cam_vdda_reg: voltage-regulator-7 { compatible = "regulator-fixed"; regulator-name = "CAM_SENSOR_CORE_1.2V"; regulator-min-microvolt = <1200000>; diff --git a/dts/src/arm/imx6qdl-phytec-phycore-som.dtsi b/dts/src/arm/imx6qdl-phytec-phycore-som.dtsi index 4d18952658..77d871340e 100644 --- a/dts/src/arm/imx6qdl-phytec-phycore-som.dtsi +++ b/dts/src/arm/imx6qdl-phytec-phycore-som.dtsi @@ -112,7 +112,7 @@ regulators { vdd_arm: buck1 { regulator-name = "vdd_arm"; - regulator-min-microvolt = <730000>; + regulator-min-microvolt = <925000>; regulator-max-microvolt = <1380000>; regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; regulator-always-on; @@ -120,7 +120,7 @@ vdd_soc: buck2 { regulator-name = "vdd_soc"; - regulator-min-microvolt = <730000>; + regulator-min-microvolt = <1150000>; regulator-max-microvolt = <1380000>; regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; regulator-always-on; diff --git a/dts/src/arm/motorola-mapphone-common.dtsi b/dts/src/arm/motorola-mapphone-common.dtsi index b6e82b165f..9067e0ef42 100644 --- a/dts/src/arm/motorola-mapphone-common.dtsi +++ b/dts/src/arm/motorola-mapphone-common.dtsi @@ -429,7 +429,7 @@ reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */ /* gpio_183 with sys_nirq2 pad as wakeup */ - interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING>, + interrupts-extended = <&gpio6 23 IRQ_TYPE_LEVEL_LOW>, <&omap4_pmx_core 0x160>; interrupt-names = "irq", "wakeup"; wakeup-source; diff --git a/dts/src/arm/omap3-n900.dts b/dts/src/arm/omap3-n900.dts index c3c6d7d04a..4089d97405 100644 --- a/dts/src/arm/omap3-n900.dts +++ b/dts/src/arm/omap3-n900.dts @@ -854,34 +854,46 @@ compatible = "ti,omap2-onenand"; reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ + /* + * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported + * bootloader set values when booted with v5.1 + * (OneNAND Manufacturer: Samsung): + * + * cs0 GPMC_CS_CONFIG1: 0xfb001202 + * cs0 GPMC_CS_CONFIG2: 0x00111100 + * cs0 GPMC_CS_CONFIG3: 0x00020200 + * cs0 GPMC_CS_CONFIG4: 0x11001102 + * cs0 GPMC_CS_CONFIG5: 0x03101616 + * cs0 GPMC_CS_CONFIG6: 0x90060000 + */ gpmc,sync-read; gpmc,sync-write; gpmc,burst-length = <16>; gpmc,burst-read; gpmc,burst-wrap; gpmc,burst-write; - gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ - gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ + gpmc,device-width = <2>; + gpmc,mux-add-data = <2>; gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <87>; - gpmc,cs-wr-off-ns = <87>; + gpmc,cs-rd-off-ns = <102>; + gpmc,cs-wr-off-ns = <102>; gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <15>; - gpmc,oe-off-ns = <87>; + gpmc,adv-rd-off-ns = <12>; + gpmc,adv-wr-off-ns = <12>; + gpmc,oe-on-ns = <12>; + gpmc,oe-off-ns = <102>; gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <87>; - gpmc,rd-cycle-ns = <112>; - gpmc,wr-cycle-ns = <112>; - gpmc,access-ns = <81>; - gpmc,page-burst-access-ns = <15>; + gpmc,we-off-ns = <102>; + gpmc,rd-cycle-ns = <132>; + gpmc,wr-cycle-ns = <132>; + gpmc,access-ns = <96>; + gpmc,page-burst-access-ns = <18>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <5>; - gpmc,wr-data-mux-bus-ns = <30>; - gpmc,wr-access-ns = <81>; + gpmc,clk-activation-ns = <6>; + gpmc,wr-data-mux-bus-ns = <36>; + gpmc,wr-access-ns = <96>; gpmc,sync-clk-ps = <15000>; /* diff --git a/dts/src/arm/omap5.dtsi b/dts/src/arm/omap5.dtsi index d0ecf54d5a..a7562d3deb 100644 --- a/dts/src/arm/omap5.dtsi +++ b/dts/src/arm/omap5.dtsi @@ -143,6 +143,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xc0000000>; + dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; reg = <0 0x44000000 0 0x2000>, <0 0x44800000 0 0x3000>, diff --git a/dts/src/arm/ox810se.dtsi b/dts/src/arm/ox810se.dtsi index 9f6c2b660e..0755e5864c 100644 --- a/dts/src/arm/ox810se.dtsi +++ b/dts/src/arm/ox810se.dtsi @@ -323,8 +323,8 @@ interrupt-controller; reg = <0 0x200>; #interrupt-cells = <1>; - valid-mask = <0xFFFFFFFF>; - clear-mask = <0>; + valid-mask = <0xffffffff>; + clear-mask = <0xffffffff>; }; timer0: timer@200 { diff --git a/dts/src/arm/ox820.dtsi b/dts/src/arm/ox820.dtsi index c9b3277320..90846a7655 100644 --- a/dts/src/arm/ox820.dtsi +++ b/dts/src/arm/ox820.dtsi @@ -240,8 +240,8 @@ reg = <0 0x200>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; - valid-mask = <0xFFFFFFFF>; - clear-mask = <0>; + valid-mask = <0xffffffff>; + clear-mask = <0xffffffff>; }; timer0: timer@200 { diff --git a/dts/src/arm/sun8i-a33.dtsi b/dts/src/arm/sun8i-a33.dtsi index 1532a0e59a..a2c37adacf 100644 --- a/dts/src/arm/sun8i-a33.dtsi +++ b/dts/src/arm/sun8i-a33.dtsi @@ -215,7 +215,7 @@ }; crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun4i-a10-crypto"; + compatible = "allwinner,sun8i-a33-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; diff --git a/dts/src/arm/sun8i-a83t-tbs-a711.dts b/dts/src/arm/sun8i-a83t-tbs-a711.dts index 2fd31a0a0b..e8b3669e0e 100644 --- a/dts/src/arm/sun8i-a83t-tbs-a711.dts +++ b/dts/src/arm/sun8i-a83t-tbs-a711.dts @@ -374,8 +374,8 @@ }; ®_dldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-name = "vdd-csi"; }; @@ -498,7 +498,8 @@ }; &usbphy { - usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + usb0_id_det-gpios = <&pio 7 11 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH11 */ + usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_drivevbus>; usb1_vbus-supply = <®_vmain>; usb2_vbus-supply = <®_vmain>; diff --git a/dts/src/arm/sun8i-a83t.dtsi b/dts/src/arm/sun8i-a83t.dtsi index 74ac7ee938..e7b9bef1be 100644 --- a/dts/src/arm/sun8i-a83t.dtsi +++ b/dts/src/arm/sun8i-a83t.dtsi @@ -1006,10 +1006,10 @@ reg = <0x01c30000 0x104>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; - resets = <&ccu CLK_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu RST_BUS_EMAC>; + clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; status = "disabled"; mdio: mdio { diff --git a/dts/src/arm/sun8i-r40.dtsi b/dts/src/arm/sun8i-r40.dtsi index 8f09a24b36..a9d5d6ddbd 100644 --- a/dts/src/arm/sun8i-r40.dtsi +++ b/dts/src/arm/sun8i-r40.dtsi @@ -181,6 +181,32 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; }; + spi0: spi@1c05000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + csi0: csi@1c09000 { compatible = "allwinner,sun8i-r40-csi0", "allwinner,sun7i-a20-csi0"; @@ -290,6 +316,29 @@ resets = <&ccu RST_BUS_CE>; }; + spi2: spi@1c17000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ahci: sata@1c18000 { + compatible = "allwinner,sun8i-r40-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; + resets = <&ccu RST_BUS_SATA>; + reset-names = "ahci"; + status = "disabled"; + }; + ehci1: usb@1c19000 { compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; reg = <0x01c19000 0x100>; @@ -336,6 +385,19 @@ status = "disabled"; }; + spi3: spi@1c1f000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c1f000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c20000 0x400>; @@ -653,69 +715,6 @@ #size-cells = <0>; }; - spi0: spi@1c05000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c06000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi2: spi@1c07000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c07000 0x1000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi3: spi@1c0f000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c0f000 0x1000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ahci: sata@1c18000 { - compatible = "allwinner,sun8i-r40-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; - resets = <&ccu RST_BUS_SATA>; - reset-names = "ahci"; - status = "disabled"; - - }; - gmac: ethernet@1c50000 { compatible = "allwinner,sun8i-r40-gmac"; syscon = <&ccu>; diff --git a/dts/src/arm64/freescale/fsl-ls1028a.dtsi b/dts/src/arm64/freescale/fsl-ls1028a.dtsi index 0bf375ec95..55b71bb4ba 100644 --- a/dts/src/arm64/freescale/fsl-ls1028a.dtsi +++ b/dts/src/arm64/freescale/fsl-ls1028a.dtsi @@ -53,7 +53,7 @@ * PSCI node is not added default, U-boot will add missing * parts if it determines to use PSCI. */ - entry-method = "arm,psci"; + entry-method = "psci"; CPU_PW20: cpu-pw20 { compatible = "arm,idle-state"; diff --git a/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts b/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts index 4223a2352d..dde50c88f5 100644 --- a/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts +++ b/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts @@ -119,12 +119,12 @@ ethernet@e4000 { phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-txid"; + phy-connection-type = "rgmii-id"; }; ethernet@e6000 { phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii-txid"; + phy-connection-type = "rgmii-id"; }; ethernet@e8000 { diff --git a/dts/src/arm64/freescale/fsl-ls1046a-rdb.dts b/dts/src/arm64/freescale/fsl-ls1046a-rdb.dts index dbc23d6cd3..d53ccc56bb 100644 --- a/dts/src/arm64/freescale/fsl-ls1046a-rdb.dts +++ b/dts/src/arm64/freescale/fsl-ls1046a-rdb.dts @@ -131,12 +131,12 @@ &fman0 { ethernet@e4000 { phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii"; + phy-connection-type = "rgmii-id"; }; ethernet@e6000 { phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii"; + phy-connection-type = "rgmii-id"; }; ethernet@e8000 { diff --git a/dts/src/arm64/sprd/sc9863a.dtsi b/dts/src/arm64/sprd/sc9863a.dtsi index cd80756c88..2c590ca1d0 100644 --- a/dts/src/arm64/sprd/sc9863a.dtsi +++ b/dts/src/arm64/sprd/sc9863a.dtsi @@ -108,7 +108,7 @@ }; idle-states { - entry-method = "arm,psci"; + entry-method = "psci"; CORE_PD: core-pd { compatible = "arm,idle-state"; entry-latency-us = <4000>; diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h deleted file mode 100644 index 57c592498a..0000000000 --- a/include/dt-bindings/reset/imx8mq-reset.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Zodiac Inflight Innovations - * - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - */ - -#ifndef DT_BINDING_RESET_IMX8MQ_H -#define DT_BINDING_RESET_IMX8MQ_H - -#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0 -#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1 -#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2 -#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3 -#define IMX8MQ_RESET_A53_CORE_RESET0 4 -#define IMX8MQ_RESET_A53_CORE_RESET1 5 -#define IMX8MQ_RESET_A53_CORE_RESET2 6 -#define IMX8MQ_RESET_A53_CORE_RESET3 7 -#define IMX8MQ_RESET_A53_DBG_RESET0 8 -#define IMX8MQ_RESET_A53_DBG_RESET1 9 -#define IMX8MQ_RESET_A53_DBG_RESET2 10 -#define IMX8MQ_RESET_A53_DBG_RESET3 11 -#define IMX8MQ_RESET_A53_ETM_RESET0 12 -#define IMX8MQ_RESET_A53_ETM_RESET1 13 -#define IMX8MQ_RESET_A53_ETM_RESET2 14 -#define IMX8MQ_RESET_A53_ETM_RESET3 15 -#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16 -#define IMX8MQ_RESET_A53_L2RESET 17 -#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 -#define IMX8MQ_RESET_OTG1_PHY_RESET 19 -#define IMX8MQ_RESET_OTG2_PHY_RESET 20 -#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 -#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 -#define IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N 23 -#define IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N 24 -#define IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N 25 -#define IMX8MQ_RESET_PCIEPHY 26 -#define IMX8MQ_RESET_PCIEPHY_PERST 27 -#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 -#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 -#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 -#define IMX8MQ_RESET_DISP_RESET 31 -#define IMX8MQ_RESET_GPU_RESET 32 -#define IMX8MQ_RESET_VPU_RESET 33 -#define IMX8MQ_RESET_PCIEPHY2 34 -#define IMX8MQ_RESET_PCIEPHY2_PERST 35 -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 -#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 -#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 -#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 -#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 -#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 -#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 -#define IMX8MQ_RESET_DDRC1_PRST 44 -#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 -#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 -#define IMX8MQ_RESET_DDRC2_PRST 47 -#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 -#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 - -#define IMX8MQ_RESET_NUM 50 - -#endif diff --git a/include/linux/barebox-wrapper.h b/include/linux/barebox-wrapper.h index e998932d12..82c52dd933 100644 --- a/include/linux/barebox-wrapper.h +++ b/include/linux/barebox-wrapper.h @@ -52,4 +52,6 @@ typedef int irqreturn_t; #define __clk_get_rate clk_get_rate #define __clk_get_parent clk_get_parent +#define cpu_relax() barrier() + #endif /* __INCLUDE_LINUX_BAREBOX_WRAPPER_H */ diff --git a/include/linux/clk.h b/include/linux/clk.h index c3aeea80dd..a005e7233d 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -325,7 +325,14 @@ struct clk_div_table { unsigned int div; }; -struct clk *clk_fixed(const char *name, int rate); +struct clk *clk_register_fixed_rate(const char *name, + const char *parent_name, unsigned long flags, + unsigned long fixed_rate); + +static inline struct clk *clk_fixed(const char *name, int rate) +{ + return clk_register_fixed_rate(name, NULL, 0, rate); +} struct clk_divider { struct clk clk; @@ -551,4 +558,8 @@ int clk_name_complete(struct string_list *sl, char *instr); char *of_clk_get_parent_name(struct device_node *np, unsigned int index); +static inline void clk_unregister(struct clk *clk) +{ +} + #endif diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h index 17f413bbbe..390437887b 100644 --- a/include/linux/clk/at91_pmc.h +++ b/include/linux/clk/at91_pmc.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * include/linux/clk/at91_pmc.h * @@ -6,11 +7,6 @@ * * Power Management Controller (PMC) - System peripherals registers. * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ #ifndef AT91_PMC_H @@ -47,8 +43,10 @@ #define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ +#define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */ #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ +#define AT91_PMC_KEY_MASK (0xff << 16) #define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ #define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ @@ -72,6 +70,8 @@ #define AT91_PMC_USBDIV_4 (2 << 28) #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ +#define AT91_PMC_CPU_CKR 0x28 /* CPU Clock Register */ + #define AT91_PMC_MCKR 0x30 /* Master Clock Register */ #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ #define AT91_PMC_CSS_SLOW (0 << 0) @@ -155,6 +155,20 @@ #define AT91_PMC_GCKRDY (1 << 24) /* Generated Clocks */ #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ +#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */ +#define AT91_PMC_FSTT(n) BIT(n) +#define AT91_PMC_RTTAL BIT(16) +#define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */ +#define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */ +#define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */ +#define AT91_PMC_LPM BIT(20) /* Low-power Mode */ +#define AT91_PMC_RXLP_MCE BIT(24) /* Backup UART Receive Enable */ +#define AT91_PMC_ACC_CE BIT(25) /* ACC Enable */ + +#define AT91_PMC_FSPR 0x74 /* Fast Startup Polarity Reg */ + +#define AT91_PMC_FS_INPUT_MASK 0x7ff + #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ @@ -172,17 +186,34 @@ #define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ #define AT91_PMC_PCR_PID_MASK 0x3f -#define AT91_PMC_PCR_GCKCSS_OFFSET 8 -#define AT91_PMC_PCR_GCKCSS_MASK (0x7 << AT91_PMC_PCR_GCKCSS_OFFSET) -#define AT91_PMC_PCR_GCKCSS(n) ((n) << AT91_PMC_PCR_GCKCSS_OFFSET) /* GCK Clock Source Selection */ #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ -#define AT91_PMC_PCR_DIV_OFFSET 16 -#define AT91_PMC_PCR_DIV_MASK (0x3 << AT91_PMC_PCR_DIV_OFFSET) -#define AT91_PMC_PCR_DIV(n) ((n) << AT91_PMC_PCR_DIV_OFFSET) /* Divisor Value */ -#define AT91_PMC_PCR_GCKDIV_OFFSET 20 -#define AT91_PMC_PCR_GCKDIV_MASK (0xff << AT91_PMC_PCR_GCKDIV_OFFSET) -#define AT91_PMC_PCR_GCKDIV(n) ((n) << AT91_PMC_PCR_GCKDIV_OFFSET) /* Generated Clock Divisor Value */ +#define AT91_PMC_PCR_GCKDIV_MASK GENMASK(27, 20) #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ #define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */ +#define AT91_PMC_AUDIO_PLL0 0x14c +#define AT91_PMC_AUDIO_PLL_PLLEN (1 << 0) +#define AT91_PMC_AUDIO_PLL_PADEN (1 << 1) +#define AT91_PMC_AUDIO_PLL_PMCEN (1 << 2) +#define AT91_PMC_AUDIO_PLL_RESETN (1 << 3) +#define AT91_PMC_AUDIO_PLL_ND_OFFSET 8 +#define AT91_PMC_AUDIO_PLL_ND_MASK (0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET) +#define AT91_PMC_AUDIO_PLL_ND(n) ((n) << AT91_PMC_AUDIO_PLL_ND_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPMC_OFFSET 16 +#define AT91_PMC_AUDIO_PLL_QDPMC_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPMC(n) ((n) << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) + +#define AT91_PMC_AUDIO_PLL1 0x150 +#define AT91_PMC_AUDIO_PLL_FRACR_MASK 0x3fffff +#define AT91_PMC_AUDIO_PLL_QDPAD_OFFSET 24 +#define AT91_PMC_AUDIO_PLL_QDPAD_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET AT91_PMC_AUDIO_PLL_QDPAD_OFFSET +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK (0x3 << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET 26 +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX 0x1f +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK (AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) + #endif diff --git a/include/linux/kernel.h b/include/linux/kernel.h index b320f7e902..23c23a73f5 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -6,6 +6,7 @@ #include <linux/bug.h> #include <linux/barebox-wrapper.h> #include <linux/limits.h> +#include <asm-generic/div64.h> #define ALIGN(x, a) __ALIGN_MASK(x, (typeof(x))(a) - 1) #define ALIGN_DOWN(x, a) ALIGN((x) - ((a) - 1), (a)) @@ -41,6 +42,18 @@ (((x) + ((__divisor) / 2)) / (__divisor)); \ } \ ) +/* + * Same as above but for u64 dividends. divisor must be a 32-bit + * number. + */ +#define DIV_ROUND_CLOSEST_ULL(x, divisor)( \ +{ \ + typeof(divisor) __d = divisor; \ + unsigned long long _tmp = (x) + (__d) / 2; \ + do_div(_tmp, __d); \ + _tmp; \ +} \ +) /** * upper_32_bits - return bits 32-63 of a number diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 8a28b8e068..e2fe42d90e 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -248,7 +248,7 @@ static inline struct usb_phy *phy_to_usbphy(struct phy *phy) return NULL; } -static struct phy *phy_get_by_index(struct device_d *dev, int index) +static inline struct phy *phy_get_by_index(struct device_d *dev, int index) { return ERR_PTR(-ENODEV); } diff --git a/include/mfd/syscon.h b/include/mfd/syscon.h index ac33f2d347..b47aa1e160 100644 --- a/include/mfd/syscon.h +++ b/include/mfd/syscon.h @@ -21,6 +21,7 @@ void __iomem *syscon_base_lookup_by_pdevname(const char *s); void __iomem *syscon_base_lookup_by_phandle (struct device_node *np, const char *property); struct regmap *syscon_node_to_regmap(struct device_node *np); +struct regmap *device_node_to_regmap(struct device_node *np); struct regmap *syscon_regmap_lookup_by_compatible(const char *s); extern struct regmap *syscon_regmap_lookup_by_phandle( struct device_node *np, @@ -41,6 +42,10 @@ static inline struct regmap *syscon_node_to_regmap(struct device_node *np) { return ERR_PTR(-ENOSYS); } +static inline struct regmap *device_node_to_regmap(struct device_node *np) +{ + return ERR_PTR(-ENOSYS); +} static inline struct regmap *syscon_regmap_lookup_by_compatible(const char *s) { return ERR_PTR(-ENOSYS); diff --git a/include/of.h b/include/of.h index 8d6c018b73..3a613dcdcf 100644 --- a/include/of.h +++ b/include/of.h @@ -177,6 +177,8 @@ struct device_node *of_get_next_child(const struct device_node *node, struct device_node *prev); extern int of_get_child_count(const struct device_node *parent); extern int of_get_available_child_count(const struct device_node *parent); +extern struct device_node *of_get_compatible_child(const struct device_node *parent, + const char *compatible); extern struct device_node *of_get_child_by_name(const struct device_node *node, const char *name); extern char *of_get_reproducible_name(struct device_node *node); @@ -378,6 +380,12 @@ static inline int of_get_available_child_count(const struct device_node *parent) return -ENOSYS; } +static inline struct device_node *of_get_compatible_child(const struct device_node *parent, + const char *compatible) +{ + return NULL; +} + static inline struct device_node *of_get_child_by_name( const struct device_node *node, const char *name) { diff --git a/include/regmap.h b/include/regmap.h index 3bcd9fe038..53f8d0d6e7 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -98,7 +98,6 @@ void regmap_mmio_detach_clk(struct regmap *map); void regmap_exit(struct regmap *map); struct regmap *dev_get_regmap(struct device_d *dev, const char *name); -struct regmap *of_node_to_regmap(struct device_node *node); int regmap_register_cdev(struct regmap *map, const char *name); diff --git a/include/regulator.h b/include/regulator.h index dfa808d662..12d8e816cd 100644 --- a/include/regulator.h +++ b/include/regulator.h @@ -212,7 +212,6 @@ static inline int regulator_bulk_disable(int num_consumers, static inline void regulator_bulk_free(int num_consumers, struct regulator_bulk_data *consumers) { - return 0; } #endif |