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-rw-r--r--arch/openrisc/cpu/cache.c2
-rw-r--r--arch/openrisc/lib/cpuinfo.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/openrisc/cpu/cache.c b/arch/openrisc/cpu/cache.c
index db6403634a..a124d6612c 100644
--- a/arch/openrisc/cpu/cache.c
+++ b/arch/openrisc/cpu/cache.c
@@ -131,7 +131,7 @@ void icache_disable(void)
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE);
}
-int cache_init(void)
+static int cache_init(void)
{
if (mfspr(SPR_UPR) & SPR_UPR_ICP) {
icache_disable();
diff --git a/arch/openrisc/lib/cpuinfo.c b/arch/openrisc/lib/cpuinfo.c
index 4c52a65421..d94178ea59 100644
--- a/arch/openrisc/lib/cpuinfo.c
+++ b/arch/openrisc/lib/cpuinfo.c
@@ -95,7 +95,7 @@ static void cpu_implementation(ulong vr2, char *string)
}
}
-int checkcpu(void)
+static int checkcpu(void)
{
ulong upr = mfspr(SPR_UPR);
ulong vr = mfspr(SPR_VR);