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-rw-r--r--Documentation/devicetree/bindings/barebox/barebox,environment.rst15
-rw-r--r--Documentation/devicetree/bindings/barebox/barebox,state.rst5
-rw-r--r--Makefile4
-rw-r--r--arch/arm/Kconfig23
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/boards/Makefile2
-rw-r--r--arch/arm/boards/at91sam9x5ek/hw_version.c2
-rw-r--r--arch/arm/boards/highbank/init.c4
-rw-r--r--arch/arm/boards/raspberry-pi/Makefile2
-rw-r--r--arch/arm/boards/raspberry-pi/rpi-common.c294
-rw-r--r--arch/arm/boards/raspberry-pi/rpi.c277
-rw-r--r--arch/arm/boards/raspberry-pi/rpi.h28
-rw-r--r--arch/arm/boards/raspberry-pi/rpi2.c21
-rw-r--r--arch/arm/configs/rpi2_defconfig72
-rw-r--r--arch/arm/configs/rpi_defconfig70
-rw-r--r--arch/arm/configs/socfpga_defconfig1
-rw-r--r--arch/arm/cpu/Makefile5
-rw-r--r--arch/arm/cpu/mmu.c10
-rw-r--r--arch/arm/cpu/no-mmu.c61
-rw-r--r--arch/arm/dts/am33xx-strip.dtsi1
-rw-r--r--arch/arm/dts/imx6q-embedsky-e9.dts8
-rw-r--r--arch/arm/dts/socfpga.dtsi8
-rw-r--r--arch/arm/include/asm/system.h20
-rw-r--r--arch/arm/mach-at91/bootstrap.c8
-rw-r--r--arch/arm/mach-bcm2835/Kconfig15
-rw-r--r--arch/arm/mach-bcm283x/Kconfig25
-rw-r--r--arch/arm/mach-bcm283x/Makefile (renamed from arch/arm/mach-bcm2835/Makefile)0
-rw-r--r--arch/arm/mach-bcm283x/core.c (renamed from arch/arm/mach-bcm2835/core.c)0
-rw-r--r--arch/arm/mach-bcm283x/include/mach/core.h (renamed from arch/arm/mach-bcm2835/include/mach/core.h)2
-rw-r--r--arch/arm/mach-bcm283x/include/mach/debug_ll.h (renamed from arch/arm/mach-bcm2835/include/mach/debug_ll.h)0
-rw-r--r--arch/arm/mach-bcm283x/include/mach/mbox.h (renamed from arch/arm/mach-bcm2835/include/mach/mbox.h)9
-rw-r--r--arch/arm/mach-bcm283x/include/mach/platform.h (renamed from arch/arm/mach-bcm2835/include/mach/platform.h)9
-rw-r--r--arch/arm/mach-bcm283x/include/mach/wd.h (renamed from arch/arm/mach-bcm2835/include/mach/wd.h)0
-rw-r--r--arch/arm/mach-bcm283x/mbox.c (renamed from arch/arm/mach-bcm2835/mbox.c)0
-rw-r--r--arch/arm/mach-imx/ocotp.c1
-rw-r--r--arch/arm/mach-omap/include/mach/sys_info.h2
-rw-r--r--arch/arm/mach-omap/omap3_generic.c2
-rw-r--r--arch/arm/mach-socfpga/generic.c38
-rw-r--r--commands/devinfo.c7
-rw-r--r--commands/ubiformat.c5
-rw-r--r--common/partitions.c20
-rw-r--r--common/partitions/Kconfig1
-rw-r--r--common/partitions/efi.c1
-rw-r--r--common/state.c25
-rw-r--r--drivers/clocksource/Kconfig4
-rw-r--r--drivers/clocksource/Makefile2
-rw-r--r--drivers/gpio/Kconfig6
-rw-r--r--drivers/gpio/Makefile2
-rw-r--r--drivers/input/gpio_keys.c23
-rw-r--r--drivers/mci/Kconfig6
-rw-r--r--drivers/mci/Makefile2
-rw-r--r--drivers/of/Kconfig7
-rw-r--r--drivers/of/barebox.c47
-rw-r--r--drivers/of/of_path.c132
-rw-r--r--drivers/pci/pci-imx6.c75
-rw-r--r--drivers/regulator/Kconfig4
-rw-r--r--drivers/regulator/Makefile2
-rw-r--r--drivers/reset/core.c1
-rw-r--r--drivers/usb/imx/chipidea-imx.c3
-rw-r--r--drivers/video/Kconfig8
-rw-r--r--drivers/video/Makefile2
-rw-r--r--dts/Bindings/arc/archs-pct.txt17
-rw-r--r--dts/Bindings/arm/amlogic.txt10
-rw-r--r--dts/Bindings/arm/apm/scu.txt17
-rw-r--r--dts/Bindings/arm/arm,scpi.txt188
-rw-r--r--dts/Bindings/arm/atmel-at91.txt17
-rw-r--r--dts/Bindings/arm/bcm/brcm,brcmstb.txt162
-rw-r--r--dts/Bindings/arm/bcm/brcm,nsp.txt34
-rw-r--r--dts/Bindings/arm/bcm/ns2.txt9
-rw-r--r--dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt14
-rw-r--r--dts/Bindings/arm/coherency-fabric.txt5
-rw-r--r--dts/Bindings/arm/coresight.txt1
-rw-r--r--dts/Bindings/arm/cpus.txt3
-rw-r--r--dts/Bindings/arm/fsl.txt16
-rw-r--r--dts/Bindings/arm/hisilicon/hisilicon.txt39
-rw-r--r--dts/Bindings/arm/idle-states.txt2
-rw-r--r--dts/Bindings/arm/keystone/keystone.txt20
-rw-r--r--dts/Bindings/arm/l2cc.txt6
-rw-r--r--dts/Bindings/arm/marvell,kirkwood.txt2
-rw-r--r--dts/Bindings/arm/mediatek.txt13
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,imgsys.txt22
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,mmsys.txt22
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,vdecsys.txt22
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,vencltsys.txt22
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,vencsys.txt22
-rw-r--r--dts/Bindings/arm/mvebu-cpu-config.txt20
-rw-r--r--dts/Bindings/arm/omap/omap.txt3
-rw-r--r--dts/Bindings/arm/pmu.txt15
-rw-r--r--dts/Bindings/arm/psci.txt6
-rw-r--r--dts/Bindings/arm/rockchip.txt46
-rw-r--r--dts/Bindings/arm/samsung-boards.txt27
-rw-r--r--dts/Bindings/arm/samsung/samsung-boards.txt69
-rw-r--r--dts/Bindings/arm/shmobile.txt10
-rw-r--r--dts/Bindings/arm/sp810.txt46
-rw-r--r--dts/Bindings/arm/sunxi.txt3
-rw-r--r--dts/Bindings/arm/tegra/nvidia,nvec.txt (renamed from dts/Bindings/nvec/nvidia,nvec.txt)0
-rw-r--r--dts/Bindings/arm/twd.txt5
-rw-r--r--dts/Bindings/arm/uniphier/cache-uniphier.txt60
-rw-r--r--dts/Bindings/ata/ahci-fsl-qoriq.txt21
-rw-r--r--dts/Bindings/ata/ahci-platform.txt2
-rw-r--r--dts/Bindings/board/fsl-board.txt (renamed from dts/Bindings/powerpc/fsl/board.txt)14
-rw-r--r--dts/Bindings/bus/sunxi-rsb.txt47
-rw-r--r--dts/Bindings/chosen.txt8
-rw-r--r--dts/Bindings/clock/at91-clock.txt35
-rw-r--r--dts/Bindings/clock/brcm,bcm2835-cprman.txt45
-rw-r--r--dts/Bindings/clock/brcm,iproc-clocks.txt78
-rw-r--r--dts/Bindings/clock/gpio-mux-clock.txt19
-rw-r--r--dts/Bindings/clock/hi6220-clock.txt19
-rw-r--r--dts/Bindings/clock/imx6ul-clock.txt13
-rw-r--r--dts/Bindings/clock/mt8173-cpu-dvfs.txt83
-rw-r--r--dts/Bindings/clock/nvidia,tegra124-dfll.txt79
-rw-r--r--dts/Bindings/clock/qcom,gcc.txt4
-rw-r--r--dts/Bindings/clock/qcom,mmcc.txt4
-rw-r--r--dts/Bindings/clock/qoriq-clock.txt61
-rw-r--r--dts/Bindings/clock/renesas,cpg-div6-clocks.txt2
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.txt69
-rw-r--r--dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt29
-rw-r--r--dts/Bindings/clock/renesas,r8a7779-cpg-clocks.txt30
-rw-r--r--dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt26
-rw-r--r--dts/Bindings/clock/renesas,rz-cpg-clocks.txt29
-rw-r--r--dts/Bindings/clock/rockchip,rk3368-cru.txt61
-rw-r--r--dts/Bindings/clock/silabs,si514.txt24
-rw-r--r--dts/Bindings/clock/st/st,clkgen-pll.txt5
-rw-r--r--dts/Bindings/clock/ux500.txt64
-rw-r--r--dts/Bindings/cpufreq/tegra124-cpufreq.txt44
-rw-r--r--dts/Bindings/crypto/fsl-sec4.txt108
-rw-r--r--dts/Bindings/crypto/sun4i-ss.txt23
-rw-r--r--dts/Bindings/devfreq/event/exynos-ppmu.txt43
-rw-r--r--dts/Bindings/display/arm,pl11x.txt (renamed from dts/Bindings/video/arm,pl11x.txt)0
-rw-r--r--dts/Bindings/display/armada/marvell,dove-lcd.txt (renamed from dts/Bindings/drm/armada/marvell,dove-lcd.txt)0
-rw-r--r--dts/Bindings/display/atmel,lcdc.txt (renamed from dts/Bindings/video/atmel,lcdc.txt)0
-rw-r--r--dts/Bindings/display/atmel/hlcdc-dc.txt (renamed from dts/Bindings/drm/atmel/hlcdc-dc.txt)0
-rw-r--r--dts/Bindings/display/brcm,bcm-vc4.txt65
-rw-r--r--dts/Bindings/display/bridge/adi,adv7123.txt (renamed from dts/Bindings/video/adi,adv7123.txt)0
-rw-r--r--dts/Bindings/display/bridge/adi,adv7511.txt (renamed from dts/Bindings/video/adi,adv7511.txt)0
-rw-r--r--dts/Bindings/display/bridge/dw_hdmi.txt (renamed from dts/Bindings/drm/bridge/dw_hdmi.txt)4
-rw-r--r--dts/Bindings/display/bridge/ps8622.txt (renamed from dts/Bindings/video/bridge/ps8622.txt)0
-rw-r--r--dts/Bindings/display/bridge/ptn3460.txt (renamed from dts/Bindings/video/bridge/ptn3460.txt)0
-rw-r--r--dts/Bindings/display/bridge/tda998x.txt (renamed from dts/Bindings/drm/i2c/tda998x.txt)0
-rw-r--r--dts/Bindings/display/bridge/thine,thc63lvdm83d.txt (renamed from dts/Bindings/video/thine,thc63lvdm83d)0
-rw-r--r--dts/Bindings/display/cirrus,clps711x-fb.txt (renamed from dts/Bindings/video/cirrus,clps711x-fb.txt)2
-rw-r--r--dts/Bindings/display/connector/analog-tv-connector.txt (renamed from dts/Bindings/video/analog-tv-connector.txt)0
-rw-r--r--dts/Bindings/display/connector/dvi-connector.txt (renamed from dts/Bindings/video/dvi-connector.txt)0
-rw-r--r--dts/Bindings/display/connector/hdmi-connector.txt (renamed from dts/Bindings/video/hdmi-connector.txt)0
-rw-r--r--dts/Bindings/display/connector/vga-connector.txt (renamed from dts/Bindings/video/vga-connector.txt)0
-rw-r--r--dts/Bindings/display/exynos/exynos-mic.txt (renamed from dts/Bindings/video/exynos-mic.txt)0
-rw-r--r--dts/Bindings/display/exynos/exynos5433-decon.txt (renamed from dts/Bindings/video/exynos5433-decon.txt)0
-rw-r--r--dts/Bindings/display/exynos/exynos7-decon.txt (renamed from dts/Bindings/video/exynos7-decon.txt)2
-rw-r--r--dts/Bindings/display/exynos/exynos_dp.txt (renamed from dts/Bindings/video/exynos_dp.txt)2
-rw-r--r--dts/Bindings/display/exynos/exynos_dsim.txt (renamed from dts/Bindings/video/exynos_dsim.txt)2
-rw-r--r--dts/Bindings/display/exynos/exynos_hdmi.txt (renamed from dts/Bindings/video/exynos_hdmi.txt)0
-rw-r--r--dts/Bindings/display/exynos/exynos_hdmiddc.txt (renamed from dts/Bindings/video/exynos_hdmiddc.txt)0
-rw-r--r--dts/Bindings/display/exynos/exynos_hdmiphy.txt (renamed from dts/Bindings/video/exynos_hdmiphy.txt)0
-rw-r--r--dts/Bindings/display/exynos/exynos_mixer.txt (renamed from dts/Bindings/video/exynos_mixer.txt)0
-rw-r--r--dts/Bindings/display/exynos/samsung-fimd.txt (renamed from dts/Bindings/video/samsung-fimd.txt)2
-rw-r--r--dts/Bindings/display/fsl,dcu.txt22
-rw-r--r--dts/Bindings/display/imx/fsl,imx-fb.txt (renamed from dts/Bindings/video/fsl,imx-fb.txt)2
-rw-r--r--dts/Bindings/display/imx/fsl-imx-drm.txt (renamed from dts/Bindings/drm/imx/fsl-imx-drm.txt)26
-rw-r--r--dts/Bindings/display/imx/hdmi.txt (renamed from dts/Bindings/drm/imx/hdmi.txt)0
-rw-r--r--dts/Bindings/display/imx/ldb.txt (renamed from dts/Bindings/drm/imx/ldb.txt)2
-rw-r--r--dts/Bindings/display/marvell,pxa2xx-lcdc.txt34
-rw-r--r--dts/Bindings/display/mipi-dsi-bus.txt (renamed from dts/Bindings/mipi/dsi/mipi-dsi-bus.txt)0
-rw-r--r--dts/Bindings/display/msm/dsi.txt (renamed from dts/Bindings/drm/msm/dsi.txt)43
-rw-r--r--dts/Bindings/display/msm/edp.txt (renamed from dts/Bindings/drm/msm/edp.txt)0
-rw-r--r--dts/Bindings/display/msm/gpu.txt (renamed from dts/Bindings/drm/msm/gpu.txt)0
-rw-r--r--dts/Bindings/display/msm/hdmi.txt (renamed from dts/Bindings/drm/msm/hdmi.txt)6
-rw-r--r--dts/Bindings/display/msm/mdp.txt (renamed from dts/Bindings/drm/msm/mdp.txt)3
-rw-r--r--dts/Bindings/display/mxsfb.txt (renamed from dts/Bindings/fb/mxsfb.txt)0
-rw-r--r--dts/Bindings/display/panel/ampire,am800480r3tmqwa1h.txt (renamed from dts/Bindings/panel/ampire,am800480r3tmqwa1h.txt)0
-rw-r--r--dts/Bindings/display/panel/auo,b080uan01.txt7
-rw-r--r--dts/Bindings/display/panel/auo,b101aw03.txt (renamed from dts/Bindings/panel/auo,b101aw03.txt)0
-rw-r--r--dts/Bindings/display/panel/auo,b101ean01.txt (renamed from dts/Bindings/panel/auo,b101ean01.txt)0
-rw-r--r--dts/Bindings/display/panel/auo,b101xtn01.txt (renamed from dts/Bindings/panel/auo,b101xtn01.txt)0
-rw-r--r--dts/Bindings/display/panel/auo,b116xw03.txt (renamed from dts/Bindings/panel/auo,b116xw03.txt)0
-rw-r--r--dts/Bindings/display/panel/auo,b133htn01.txt (renamed from dts/Bindings/panel/auo,b133htn01.txt)0
-rw-r--r--dts/Bindings/display/panel/auo,b133xtn01.txt (renamed from dts/Bindings/panel/auo,b133xtn01.txt)0
-rw-r--r--dts/Bindings/display/panel/avic,tm070ddh03.txt (renamed from dts/Bindings/panel/avic,tm070ddh03.txt)0
-rw-r--r--dts/Bindings/display/panel/chunghwa,claa101wa01a.txt (renamed from dts/Bindings/panel/chunghwa,claa101wa01a.txt)0
-rw-r--r--dts/Bindings/display/panel/chunghwa,claa101wb03.txt (renamed from dts/Bindings/panel/chunghwa,claa101wb03.txt)0
-rw-r--r--dts/Bindings/display/panel/display-timing.txt (renamed from dts/Bindings/video/display-timing.txt)0
-rw-r--r--dts/Bindings/display/panel/edt,et057090dhu.txt (renamed from dts/Bindings/panel/edt,et057090dhu.txt)0
-rw-r--r--dts/Bindings/display/panel/edt,et070080dh6.txt (renamed from dts/Bindings/panel/edt,et070080dh6.txt)0
-rw-r--r--dts/Bindings/display/panel/edt,etm0700g0dh6.txt (renamed from dts/Bindings/panel/edt,etm0700g0dh6.txt)0
-rw-r--r--dts/Bindings/display/panel/foxlink,fl500wvr00-a0t.txt (renamed from dts/Bindings/panel/foxlink,fl500wvr00-a0t.txt)0
-rw-r--r--dts/Bindings/display/panel/giantplus,gpg482739qs5.txt (renamed from dts/Bindings/panel/giantplus,gpg482739qs5.txt)0
-rw-r--r--dts/Bindings/display/panel/hannstar,hsd070pww1.txt (renamed from dts/Bindings/panel/hannstar,hsd070pww1.txt)0
-rw-r--r--dts/Bindings/display/panel/hannstar,hsd100pxn1.txt (renamed from dts/Bindings/panel/hannstar,hsd100pxn1.txt)0
-rw-r--r--dts/Bindings/display/panel/hit,tx23d38vm0caa.txt (renamed from dts/Bindings/panel/hit,tx23d38vm0caa.txt)0
-rw-r--r--dts/Bindings/display/panel/innolux,at043tn24.txt (renamed from dts/Bindings/panel/innolux,at043tn24.txt)0
-rw-r--r--dts/Bindings/display/panel/innolux,g121i1-l01.txt (renamed from dts/Bindings/panel/innolux,g121i1-l01.txt)0
-rw-r--r--dts/Bindings/display/panel/innolux,n116bge.txt (renamed from dts/Bindings/panel/innolux,n116bge.txt)0
-rw-r--r--dts/Bindings/display/panel/innolux,n156bge-l21.txt (renamed from dts/Bindings/panel/innolux,n156bge-l21.txt)0
-rw-r--r--dts/Bindings/display/panel/innolux,zj070na-01p.txt (renamed from dts/Bindings/panel/innolux,zj070na-01p.txt)0
-rw-r--r--dts/Bindings/display/panel/lg,lb070wv8.txt (renamed from dts/Bindings/panel/lg,lb070wv8.txt)0
-rw-r--r--dts/Bindings/display/panel/lg,ld070wx3-sl01.txt (renamed from dts/Bindings/panel/lg,ld070wx3-sl01.txt)0
-rw-r--r--dts/Bindings/display/panel/lg,lg4573.txt19
-rw-r--r--dts/Bindings/display/panel/lg,lh500wx1-sd03.txt (renamed from dts/Bindings/panel/lg,lh500wx1-sd03.txt)0
-rw-r--r--dts/Bindings/display/panel/lg,lp129qe.txt (renamed from dts/Bindings/panel/lg,lp129qe.txt)0
-rw-r--r--dts/Bindings/display/panel/lgphilips,lb035q02.txt (renamed from dts/Bindings/video/lgphilips,lb035q02.txt)0
-rw-r--r--dts/Bindings/display/panel/nec,nl4827hc19-05b.txt7
-rw-r--r--dts/Bindings/display/panel/okaya,rs800480t-7x0gp.txt7
-rw-r--r--dts/Bindings/display/panel/ortustech,com43h4m85ulc.txt (renamed from dts/Bindings/panel/ortustech,com43h4m85ulc.txt)0
-rw-r--r--dts/Bindings/display/panel/panasonic,vvx10f004b00.txt (renamed from dts/Bindings/panel/panasonic,vvx10f004b00.txt)0
-rw-r--r--dts/Bindings/display/panel/panel-dpi.txt (renamed from dts/Bindings/video/panel-dpi.txt)2
-rw-r--r--dts/Bindings/display/panel/panel-dsi-cm.txt (renamed from dts/Bindings/video/panel-dsi-cm.txt)0
-rw-r--r--dts/Bindings/display/panel/samsung,ld9040.txt (renamed from dts/Bindings/panel/samsung,ld9040.txt)2
-rw-r--r--dts/Bindings/display/panel/samsung,ltn101nt05.txt (renamed from dts/Bindings/panel/samsung,ltn101nt05.txt)0
-rw-r--r--dts/Bindings/display/panel/samsung,ltn140at29-301.txt (renamed from dts/Bindings/panel/samsung,ltn140at29-301.txt)0
-rw-r--r--dts/Bindings/display/panel/samsung,s6e8aa0.txt (renamed from dts/Bindings/panel/samsung,s6e8aa0.txt)2
-rw-r--r--dts/Bindings/display/panel/sharp,lq101r1sx01.txt (renamed from dts/Bindings/panel/sharp,lq101r1sx01.txt)0
-rw-r--r--dts/Bindings/display/panel/sharp,ls037v7dw01.txt (renamed from dts/Bindings/video/sharp,ls037v7dw01.txt)0
-rw-r--r--dts/Bindings/display/panel/shelly,sca07010-bfn-lnn.txt (renamed from dts/Bindings/panel/shelly,sca07010-bfn-lnn.txt)0
-rw-r--r--dts/Bindings/display/panel/simple-panel.txt (renamed from dts/Bindings/panel/simple-panel.txt)0
-rw-r--r--dts/Bindings/display/panel/sony,acx565akm.txt (renamed from dts/Bindings/video/sony,acx565akm.txt)0
-rw-r--r--dts/Bindings/display/panel/toppoly,td028ttec1.txt (renamed from dts/Bindings/video/toppoly,td028ttec1.txt)0
-rw-r--r--dts/Bindings/display/panel/tpo,td043mtea1.txt (renamed from dts/Bindings/video/tpo,td043mtea1.txt)0
-rw-r--r--dts/Bindings/display/renesas,du.txt (renamed from dts/Bindings/video/renesas,du.txt)14
-rw-r--r--dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt (renamed from dts/Bindings/video/dw_hdmi-rockchip.txt)0
-rw-r--r--dts/Bindings/display/rockchip/rockchip-drm.txt (renamed from dts/Bindings/video/rockchip-drm.txt)2
-rw-r--r--dts/Bindings/display/rockchip/rockchip-vop.txt (renamed from dts/Bindings/video/rockchip-vop.txt)0
-rw-r--r--dts/Bindings/display/simple-framebuffer-sunxi.txt (renamed from dts/Bindings/video/simple-framebuffer-sunxi.txt)0
-rw-r--r--dts/Bindings/display/simple-framebuffer.txt (renamed from dts/Bindings/video/simple-framebuffer.txt)0
-rw-r--r--dts/Bindings/display/sm501fb.txt (renamed from dts/Bindings/fb/sm501fb.txt)0
-rw-r--r--dts/Bindings/display/ssd1289fb.txt (renamed from dts/Bindings/video/ssd1289fb.txt)0
-rw-r--r--dts/Bindings/display/ssd1307fb.txt (renamed from dts/Bindings/video/ssd1307fb.txt)3
-rw-r--r--dts/Bindings/display/st,stih4xx.txt (renamed from dts/Bindings/gpu/st,stih4xx.txt)76
-rw-r--r--dts/Bindings/display/tegra/nvidia,tegra114-mipi.txt (renamed from dts/Bindings/mipi/nvidia,tegra114-mipi.txt)0
-rw-r--r--dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt (renamed from dts/Bindings/gpu/nvidia,tegra20-host1x.txt)10
-rw-r--r--dts/Bindings/display/ti/ti,dra7-dss.txt (renamed from dts/Bindings/video/ti,dra7-dss.txt)2
-rw-r--r--dts/Bindings/display/ti/ti,omap-dss.txt (renamed from dts/Bindings/video/ti,omap-dss.txt)0
-rw-r--r--dts/Bindings/display/ti/ti,omap2-dss.txt (renamed from dts/Bindings/video/ti,omap2-dss.txt)2
-rw-r--r--dts/Bindings/display/ti/ti,omap3-dss.txt (renamed from dts/Bindings/video/ti,omap3-dss.txt)2
-rw-r--r--dts/Bindings/display/ti/ti,omap4-dss.txt (renamed from dts/Bindings/video/ti,omap4-dss.txt)2
-rw-r--r--dts/Bindings/display/ti/ti,omap5-dss.txt (renamed from dts/Bindings/video/ti,omap5-dss.txt)2
-rw-r--r--dts/Bindings/display/ti/ti,opa362.txt (renamed from dts/Bindings/video/ti,opa362.txt)0
-rw-r--r--dts/Bindings/display/ti/ti,tfp410.txt (renamed from dts/Bindings/video/ti,tfp410.txt)0
-rw-r--r--dts/Bindings/display/ti/ti,tpd12s015.txt (renamed from dts/Bindings/video/ti,tpd12s015.txt)0
-rw-r--r--dts/Bindings/display/tilcdc/panel.txt (renamed from dts/Bindings/drm/tilcdc/panel.txt)2
-rw-r--r--dts/Bindings/display/tilcdc/tfp410.txt (renamed from dts/Bindings/drm/tilcdc/tfp410.txt)0
-rw-r--r--dts/Bindings/display/tilcdc/tilcdc.txt (renamed from dts/Bindings/drm/tilcdc/tilcdc.txt)0
-rw-r--r--dts/Bindings/display/via,vt8500-fb.txt (renamed from dts/Bindings/video/via,vt8500-fb.txt)0
-rw-r--r--dts/Bindings/display/wm,prizm-ge-rops.txt (renamed from dts/Bindings/video/wm,prizm-ge-rops.txt)0
-rw-r--r--dts/Bindings/display/wm,wm8505-fb.txt (renamed from dts/Bindings/video/wm,wm8505-fb.txt)0
-rw-r--r--dts/Bindings/dma/adi,axi-dmac.txt61
-rw-r--r--dts/Bindings/dma/apm-xgene-dma.txt2
-rw-r--r--dts/Bindings/dma/arm-pl08x.txt54
-rw-r--r--dts/Bindings/dma/lpc1850-dmamux.txt54
-rw-r--r--dts/Bindings/dma/mv-xor.txt10
-rw-r--r--dts/Bindings/dma/sun4i-dma.txt46
-rw-r--r--dts/Bindings/dma/ti-dma-crossbar.txt15
-rw-r--r--dts/Bindings/dma/ti-edma.txt117
-rw-r--r--dts/Bindings/dma/zxdma.txt38
-rw-r--r--dts/Bindings/edac/apm-xgene-edac.txt23
-rw-r--r--dts/Bindings/eeprom/at25.txt (renamed from dts/Bindings/misc/at25.txt)0
-rw-r--r--dts/Bindings/eeprom/eeprom.txt (renamed from dts/Bindings/eeprom.txt)0
-rw-r--r--dts/Bindings/extcon/extcon-arizona.txt15
-rw-r--r--dts/Bindings/extcon/extcon-palmas.txt5
-rw-r--r--dts/Bindings/fpga/altera-socfpga-fpga-mgr.txt2
-rw-r--r--dts/Bindings/fpga/xilinx-zynq-fpga-mgr.txt19
-rw-r--r--dts/Bindings/gpio/brcm,brcmstb-gpio.txt35
-rw-r--r--dts/Bindings/gpio/gpio-etraxfs.txt3
-rw-r--r--dts/Bindings/gpio/gpio-mpc8xxx.txt22
-rw-r--r--dts/Bindings/gpio/gpio-msm.txt26
-rw-r--r--dts/Bindings/gpio/gpio-pca953x.txt1
-rw-r--r--dts/Bindings/gpio/gpio-zynq.txt9
-rw-r--r--dts/Bindings/gpio/gpio.txt45
-rw-r--r--dts/Bindings/gpio/netxbig-gpio-ext.txt22
-rw-r--r--dts/Bindings/gpio/renesas,gpio-rcar.txt1
-rw-r--r--dts/Bindings/gpio/zx296702-gpio.txt24
-rw-r--r--dts/Bindings/hwmon/ina2xx.txt (renamed from dts/Bindings/i2c/ina2xx.txt)1
-rw-r--r--dts/Bindings/hwmon/lm70.txt21
-rw-r--r--dts/Bindings/hwmon/ltc2978.txt12
-rw-r--r--dts/Bindings/hwmon/max6697.txt (renamed from dts/Bindings/i2c/max6697.txt)0
-rw-r--r--dts/Bindings/hwmon/pwm-fan.txt29
-rw-r--r--dts/Bindings/i2c/i2c-cadence.txt6
-rw-r--r--dts/Bindings/i2c/i2c-davinci.txt6
-rw-r--r--dts/Bindings/i2c/i2c-emev2.txt22
-rw-r--r--dts/Bindings/i2c/i2c-imx.txt9
-rw-r--r--dts/Bindings/i2c/i2c-lpc2k.txt33
-rw-r--r--dts/Bindings/i2c/i2c-mux-reg.txt74
-rw-r--r--dts/Bindings/i2c/i2c-rcar.txt1
-rw-r--r--dts/Bindings/i2c/i2c-sh_mobile.txt1
-rw-r--r--dts/Bindings/i2c/i2c-uniphier-f.txt25
-rw-r--r--dts/Bindings/i2c/i2c-uniphier.txt25
-rw-r--r--dts/Bindings/i2c/i2c.txt45
-rw-r--r--dts/Bindings/i2c/ina209.txt18
-rw-r--r--dts/Bindings/i2c/trivial-devices.txt5
-rw-r--r--dts/Bindings/iio/accel/bma180.txt8
-rw-r--r--dts/Bindings/iio/accel/lis302.txt (renamed from dts/Bindings/misc/lis302.txt)0
-rw-r--r--dts/Bindings/iio/accel/mma8452.txt24
-rw-r--r--dts/Bindings/iio/adc/hi8435.txt21
-rw-r--r--dts/Bindings/iio/adc/mcp320x.txt1
-rw-r--r--dts/Bindings/iio/adc/vf610-adc.txt5
-rw-r--r--dts/Bindings/iio/dac/ti,dac7512.txt (renamed from dts/Bindings/misc/ti,dac7512.txt)0
-rw-r--r--dts/Bindings/iio/light/apds9960.txt22
-rw-r--r--dts/Bindings/iio/light/us5182d.txt34
-rw-r--r--dts/Bindings/iio/magnetometer/mmc35240.txt13
-rw-r--r--dts/Bindings/iio/pressure/bmp085.txt (renamed from dts/Bindings/misc/bmp085.txt)0
-rw-r--r--dts/Bindings/iio/st-sensors.txt2
-rw-r--r--dts/Bindings/input/ads7846.txt5
-rw-r--r--dts/Bindings/input/cap11xx.txt19
-rw-r--r--dts/Bindings/input/cypress,cyapa.txt44
-rw-r--r--dts/Bindings/input/da9062-onkey.txt32
-rw-r--r--dts/Bindings/input/elants_i2c.txt3
-rw-r--r--dts/Bindings/input/gpio-keys-polled.txt12
-rw-r--r--dts/Bindings/input/gpio-keys.txt3
-rw-r--r--dts/Bindings/input/gpio-matrix-keypad.txt3
-rw-r--r--dts/Bindings/input/hid-over-i2c.txt (renamed from dts/Bindings/hid/hid-over-i2c.txt)0
-rw-r--r--dts/Bindings/input/nvidia,tegra20-kbc.txt3
-rw-r--r--dts/Bindings/input/qcom,pm8xxx-keypad.txt3
-rw-r--r--dts/Bindings/input/rotary-encoder.txt10
-rw-r--r--dts/Bindings/input/samsung-keypad.txt7
-rw-r--r--dts/Bindings/input/snvs-pwrkey.txt1
-rw-r--r--dts/Bindings/input/touchscreen/colibri-vf50-ts.txt36
-rw-r--r--dts/Bindings/input/touchscreen/edt-ft5x06.txt8
-rw-r--r--dts/Bindings/input/touchscreen/focaltech-ft6236.txt35
-rw-r--r--dts/Bindings/input/touchscreen/imx6ul_tsc.txt36
-rw-r--r--dts/Bindings/input/touchscreen/pixcir_i2c_ts.txt3
-rw-r--r--dts/Bindings/input/touchscreen/tsc2005.txt34
-rw-r--r--dts/Bindings/input/touchscreen/zforce_ts.txt8
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic-v3.txt (renamed from dts/Bindings/arm/gic-v3.txt)5
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic.txt (renamed from dts/Bindings/arm/gic.txt)24
-rw-r--r--dts/Bindings/interrupt-controller/arm,versatile-fpga-irq.txt (renamed from dts/Bindings/arm/versatile-fpga-irq.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/arm,vic.txt (renamed from dts/Bindings/arm/vic.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/axis,crisv32-intc.txt (renamed from dts/Bindings/cris/interrupts.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt25
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt37
-rw-r--r--dts/Bindings/interrupt-controller/img,meta-intc.txt (renamed from dts/Bindings/metag/meta-intc.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/img,pdc-intc.txt (renamed from dts/Bindings/metag/pdc-intc.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/intel,ce4100-ioapic.txt (renamed from dts/Bindings/x86/interrupt.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/mediatek,sysirq.txt (renamed from dts/Bindings/arm/mediatek/mediatek,sysirq.txt)4
-rw-r--r--dts/Bindings/interrupt-controller/mrvl,intc.txt (renamed from dts/Bindings/arm/mrvl/intc.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/msi.txt135
-rw-r--r--dts/Bindings/interrupt-controller/nxp,lpc3220-mic.txt (renamed from dts/Bindings/arm/lpc32xx-mic.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/open-pic.txt (renamed from dts/Bindings/open-pic.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt20
-rw-r--r--dts/Bindings/interrupt-controller/renesas,irqc.txt1
-rw-r--r--dts/Bindings/interrupt-controller/samsung,exynos4210-combiner.txt (renamed from dts/Bindings/arm/samsung/interrupt-combiner.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/snps,arc700-intc.txt (renamed from dts/Bindings/arc/interrupts.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt (renamed from dts/Bindings/arc/archs-idu-intc.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/snps,archs-intc.txt (renamed from dts/Bindings/arc/archs-intc.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/st,spear3xx-shirq.txt (renamed from dts/Bindings/arm/spear/shirq.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt (renamed from dts/Bindings/c6x/interrupt.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/ti,cp-intc.txt (renamed from dts/Bindings/arm/davinci/cp-intc.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/ti,omap2-intc.txt (renamed from dts/Bindings/arm/omap/intc.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/via,vt8500-intc.txt (renamed from dts/Bindings/arm/vt8500/via,vt8500-intc.txt)0
-rw-r--r--dts/Bindings/iommu/arm,smmu-v3.txt22
-rw-r--r--dts/Bindings/iommu/arm,smmu.txt6
-rw-r--r--dts/Bindings/iommu/samsung,sysmmu.txt2
-rw-r--r--dts/Bindings/iommu/ti,omap-iommu.txt33
-rw-r--r--dts/Bindings/ipmi.txt25
-rw-r--r--dts/Bindings/leds/backlight/88pm860x.txt (renamed from dts/Bindings/video/backlight/88pm860x.txt)0
-rw-r--r--dts/Bindings/leds/backlight/gpio-backlight.txt (renamed from dts/Bindings/video/backlight/gpio-backlight.txt)0
-rw-r--r--dts/Bindings/leds/backlight/lp855x.txt (renamed from dts/Bindings/video/backlight/lp855x.txt)0
-rw-r--r--dts/Bindings/leds/backlight/max8925-backlight.txt (renamed from dts/Bindings/video/backlight/max8925-backlight.txt)0
-rw-r--r--dts/Bindings/leds/backlight/pm8941-wled.txt (renamed from dts/Bindings/leds/leds-pm8941-wled.txt)7
-rw-r--r--dts/Bindings/leds/backlight/pwm-backlight.txt (renamed from dts/Bindings/video/backlight/pwm-backlight.txt)0
-rw-r--r--dts/Bindings/leds/backlight/sky81452-backlight.txt (renamed from dts/Bindings/video/backlight/sky81452-backlight.txt)0
-rw-r--r--dts/Bindings/leds/backlight/tps65217-backlight.txt (renamed from dts/Bindings/video/backlight/tps65217-backlight.txt)0
-rw-r--r--dts/Bindings/leds/common.txt27
-rw-r--r--dts/Bindings/leds/leds-aat1290.txt8
-rw-r--r--dts/Bindings/leds/leds-bcm6328.txt10
-rw-r--r--dts/Bindings/leds/leds-netxbig.txt92
-rw-r--r--dts/Bindings/leds/leds-ns2.txt9
-rw-r--r--dts/Bindings/leds/leds-powernv.txt26
-rw-r--r--dts/Bindings/mailbox/omap-mailbox.txt8
-rw-r--r--dts/Bindings/mailbox/sti-mailbox.txt51
-rw-r--r--dts/Bindings/media/exynos-jpeg-codec.txt3
-rw-r--r--dts/Bindings/media/i2c/adv7604.txt21
-rw-r--r--dts/Bindings/media/i2c/tc358743.txt48
-rw-r--r--dts/Bindings/media/renesas,jpu.txt24
-rw-r--r--dts/Bindings/media/stih407-c8sectpfe.txt89
-rw-r--r--dts/Bindings/memory-controllers/arm,pl172.txt127
-rw-r--r--dts/Bindings/memory-controllers/calxeda-ddr-ctrlr.txt (renamed from dts/Bindings/arm/calxeda/mem-ctrlr.txt)0
-rw-r--r--dts/Bindings/memory-controllers/fsl/ifc.txt3
-rw-r--r--dts/Bindings/memory-controllers/renesas-memory-controllers.txt6
-rw-r--r--dts/Bindings/memory-controllers/synopsys.txt4
-rw-r--r--dts/Bindings/memory-controllers/ti/emif.txt1
-rw-r--r--dts/Bindings/mfd/arizona.txt15
-rw-r--r--dts/Bindings/mfd/atmel-flexcom.txt63
-rw-r--r--dts/Bindings/mfd/atmel-hlcdc.txt6
-rw-r--r--dts/Bindings/mfd/axp20x.txt8
-rw-r--r--dts/Bindings/mfd/cros-ec.txt4
-rw-r--r--dts/Bindings/mfd/da9062.txt88
-rw-r--r--dts/Bindings/mfd/da9150.txt33
-rw-r--r--dts/Bindings/mfd/max77686.txt65
-rw-r--r--dts/Bindings/mfd/max77802.txt26
-rw-r--r--dts/Bindings/mfd/rk808.txt8
-rw-r--r--dts/Bindings/mfd/s2mps11.txt28
-rw-r--r--dts/Bindings/mfd/sky81452.txt2
-rw-r--r--dts/Bindings/mfd/tc3589x.txt5
-rw-r--r--dts/Bindings/mips/img/xilfpga.txt83
-rw-r--r--dts/Bindings/misc/sram.txt16
-rw-r--r--dts/Bindings/mmc/arasan,sdhci.txt2
-rw-r--r--dts/Bindings/mmc/fsl-esdhc.txt2
-rw-r--r--dts/Bindings/mmc/fsl-imx-esdhc.txt8
-rw-r--r--dts/Bindings/mmc/mmc.txt6
-rw-r--r--dts/Bindings/mmc/mtk-sd.txt11
-rw-r--r--dts/Bindings/mmc/renesas,mmcif.txt5
-rw-r--r--dts/Bindings/mmc/rockchip-dw-mshc.txt13
-rw-r--r--dts/Bindings/mmc/sdhci-atmel.txt21
-rw-r--r--dts/Bindings/mmc/synopsys-dw-mshc.txt25
-rw-r--r--dts/Bindings/mmc/ti-omap-hsmmc.txt2
-rw-r--r--dts/Bindings/mtd/fsl-quadspi.txt3
-rw-r--r--dts/Bindings/mtd/fsmc-nand.txt6
-rw-r--r--dts/Bindings/mtd/nxp-spifi.txt58
-rw-r--r--dts/Bindings/mtd/partition.txt71
-rw-r--r--dts/Bindings/mtd/pxa3xx-nand.txt3
-rw-r--r--dts/Bindings/mtd/vf610-nfc.txt59
-rw-r--r--dts/Bindings/net/apm-xgene-enet.txt10
-rw-r--r--dts/Bindings/net/brcm,iproc-mdio.txt23
-rw-r--r--dts/Bindings/net/can/sun4i_can.txt36
-rw-r--r--dts/Bindings/net/cpsw.txt19
-rw-r--r--dts/Bindings/net/dsa/dsa.txt38
-rw-r--r--dts/Bindings/net/ethernet.txt4
-rw-r--r--dts/Bindings/net/fixed-link.txt14
-rw-r--r--dts/Bindings/net/fsl-tsec-phy.txt4
-rw-r--r--dts/Bindings/net/hisilicon-hip04-net.txt4
-rw-r--r--dts/Bindings/net/hisilicon-hns-dsaf.txt49
-rw-r--r--dts/Bindings/net/hisilicon-hns-mdio.txt22
-rw-r--r--dts/Bindings/net/hisilicon-hns-nic.txt47
-rw-r--r--dts/Bindings/net/ieee802154/mrf24j40.txt20
-rw-r--r--dts/Bindings/net/keystone-netcp.txt6
-rw-r--r--dts/Bindings/net/marvell-armada-370-neta.txt6
-rw-r--r--dts/Bindings/net/maxim,ds26522.txt13
-rw-r--r--dts/Bindings/net/nfc/nfcmrvl.txt61
-rw-r--r--dts/Bindings/net/nfc/s3fwrn5.txt27
-rw-r--r--dts/Bindings/net/nfc/st-nci-i2c.txt (renamed from dts/Bindings/net/nfc/st-nci.txt)7
-rw-r--r--dts/Bindings/net/nfc/st-nci-spi.txt38
-rw-r--r--dts/Bindings/net/renesas,ravb.txt69
-rw-r--r--dts/Bindings/net/smsc-lan87xx.txt24
-rw-r--r--dts/Bindings/net/snps,dwc-qos-ethernet.txt75
-rw-r--r--dts/Bindings/nvmem/allwinner,sunxi-sid.txt (renamed from dts/Bindings/misc/allwinner,sunxi-sid.txt)4
-rw-r--r--dts/Bindings/nvmem/imx-ocotp.txt20
-rw-r--r--dts/Bindings/nvmem/mxs-ocotp.txt25
-rw-r--r--dts/Bindings/nvmem/nvmem.txt80
-rw-r--r--dts/Bindings/nvmem/qfprom.txt35
-rw-r--r--dts/Bindings/nvmem/rockchip-efuse.txt38
-rw-r--r--dts/Bindings/nvmem/vf610-ocotp.txt19
-rw-r--r--dts/Bindings/opp/opp.txt (renamed from dts/Bindings/power/opp.txt)40
-rw-r--r--dts/Bindings/pci/altera-pcie-msi.txt28
-rw-r--r--dts/Bindings/pci/altera-pcie.txt49
-rw-r--r--dts/Bindings/pci/arm,juno-r1-pcie.txt10
-rw-r--r--dts/Bindings/pci/brcm,iproc-pcie.txt20
-rw-r--r--dts/Bindings/pci/designware-pcie.txt12
-rw-r--r--dts/Bindings/pci/hisilicon-pcie.txt44
-rw-r--r--dts/Bindings/pci/host-generic-pci.txt5
-rw-r--r--dts/Bindings/pci/layerscape-pci.txt14
-rw-r--r--dts/Bindings/pci/pci-msi.txt220
-rw-r--r--dts/Bindings/pci/pci-rcar-gen2.txt3
-rw-r--r--dts/Bindings/pci/pci.txt4
-rw-r--r--dts/Bindings/pci/plda,xpressrich3-axi.txt12
-rw-r--r--dts/Bindings/pci/ti-pci.txt3
-rw-r--r--dts/Bindings/phy/brcm,cygnus-pcie-phy.txt47
-rw-r--r--dts/Bindings/phy/calxeda-combophy.txt (renamed from dts/Bindings/arm/calxeda/combophy.txt)0
-rw-r--r--dts/Bindings/phy/keystone-usb-phy.txt (renamed from dts/Bindings/usb/keystone-phy.txt)0
-rw-r--r--dts/Bindings/phy/mxs-usb-phy.txt (renamed from dts/Bindings/usb/mxs-phy.txt)0
-rw-r--r--dts/Bindings/phy/nvidia,tegra20-usb-phy.txt (renamed from dts/Bindings/usb/nvidia,tegra20-usb-phy.txt)0
-rw-r--r--dts/Bindings/phy/phy-lpc18xx-usb-otg.txt26
-rw-r--r--dts/Bindings/phy/phy-mt65xx-usb.txt68
-rw-r--r--dts/Bindings/phy/qcom,usb-8x16-phy.txt76
-rw-r--r--dts/Bindings/phy/samsung-phy.txt3
-rw-r--r--dts/Bindings/phy/sun4i-usb-phy.txt22
-rw-r--r--dts/Bindings/phy/ti-phy.txt16
-rw-r--r--dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt38
-rw-r--r--dts/Bindings/pinctrl/atmel,at91-pio4-pinctrl.txt90
-rw-r--r--dts/Bindings/pinctrl/berlin,pinctrl.txt5
-rw-r--r--dts/Bindings/pinctrl/brcm,cygnus-gpio.txt16
-rw-r--r--dts/Bindings/pinctrl/cnxt,cx92755-pinctrl.txt86
-rw-r--r--dts/Bindings/pinctrl/fsl,imx6ul-pinctrl.txt36
-rw-r--r--dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt63
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1505 files changed, 65115 insertions, 9201 deletions
diff --git a/Documentation/devicetree/bindings/barebox/barebox,environment.rst b/Documentation/devicetree/bindings/barebox/barebox,environment.rst
index d5e52ea..12b103b 100644
--- a/Documentation/devicetree/bindings/barebox/barebox,environment.rst
+++ b/Documentation/devicetree/bindings/barebox/barebox,environment.rst
@@ -6,7 +6,10 @@ This driver provides an environment for barebox from the devicetree.
Required properties:
* ``compatible``: should be ``barebox,environment``
-* ``device-path``: path to the environment
+* ``device-path``: path to the device environment is on
+
+Optional properties:
+* ``file-path``: path to a file in the device named by device-path
The device-path is a multistring property. The first string should contain
a nodepath to the node containing the physical device of the environment or
@@ -19,9 +22,19 @@ the path to the environment. Supported values for <type>:
be the label for MTD partitions, the number for DOS
partitions (beginning with 0) or the name for GPT partitions.
+The file-path is the name of a file located in a FAT filesystem on the
+device named in device-path. This filesystem will be mounted and the
+environment loaded from the file's location in the directory tree.
+
Example::
environment@0 {
compatible = "barebox,environment";
device-path = &flash, "partname:barebox-environment";
};
+
+ environment@1 {
+ compatible = "barebox,environment";
+ device-path = &mmc, "partname:1";
+ file-path = "barebox.env";
+ };
diff --git a/Documentation/devicetree/bindings/barebox/barebox,state.rst b/Documentation/devicetree/bindings/barebox/barebox,state.rst
index ef66029..d1b0627 100644
--- a/Documentation/devicetree/bindings/barebox/barebox,state.rst
+++ b/Documentation/devicetree/bindings/barebox/barebox,state.rst
@@ -55,8 +55,8 @@ Required properties:
``#size-cells = <1>``. Defines the ``offset`` and ``size`` of the
variable in the ``raw`` backend. ``size`` must fit the node
``type``. Variables are not allowed to overlap.
-* ``type``: Should be ``uint8``, ``uint32``, ``enum32``, ``mac`` or
- ``string`` for the type of the variable
+* ``type``: Should be ``uint8``, ``uint32``, ``int32``. ``enum32``, ``mac``
+ or ``string`` for the type of the variable
* ``names``: For ``enum32`` values only, this specifies the values
possible for ``enum32``.
@@ -93,6 +93,7 @@ Variable Types
* ``uint8``:
* ``uint32``:
+* ``int32``:
* ``enum32``: The ``default`` value is an integer representing an
offset into the names array.
* ``mac``:
diff --git a/Makefile b/Makefile
index be53d83..22e569d 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
-VERSION = 2015
-PATCHLEVEL = 12
+VERSION = 2016
+PATCHLEVEL = 01
SUBLEVEL = 0
EXTRAVERSION =
NAME = None
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9f4d8e9..71d4336 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -22,6 +22,15 @@ config ARM_USE_COMPRESSED_DTB
select UNCOMPRESS
select LZO_DECOMPRESS
+config ARCH_BCM283X
+ bool
+ select GPIOLIB
+ select CLKDEV_LOOKUP
+ select COMMON_CLK
+ select CLOCKSOURCE_BCM283X
+ select ARM_AMBA
+ select HAS_DEBUG_LL
+
menu "System Type"
config BUILTIN_DTB
@@ -52,13 +61,13 @@ config ARCH_AT91
config ARCH_BCM2835
bool "Broadcom BCM2835 boards"
- select GPIOLIB
+ select ARCH_BCM283X
select CPU_ARM1176
- select CLKDEV_LOOKUP
- select COMMON_CLK
- select CLOCKSOURCE_BCM2835
- select ARM_AMBA
- select HAS_DEBUG_LL
+
+config ARCH_BCM2836
+ bool "Broadcom BCM2836 boards"
+ select ARCH_BCM283X
+ select CPU_V7
config ARCH_CLPS711X
bool "Cirrus Logic EP711x/EP721x/EP731x"
@@ -251,7 +260,7 @@ endchoice
source arch/arm/cpu/Kconfig
source arch/arm/mach-at91/Kconfig
-source arch/arm/mach-bcm2835/Kconfig
+source arch/arm/mach-bcm283x/Kconfig
source arch/arm/mach-clps711x/Kconfig
source arch/arm/mach-davinci/Kconfig
source arch/arm/mach-digic/Kconfig
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index cae05ff..9ce16b9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -57,7 +57,7 @@ AFLAGS += -include asm/unified.h -msoft-float $(AFLAGS_THUMB2)
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_AT91) := at91
-machine-$(CONFIG_ARCH_BCM2835) := bcm2835
+machine-$(CONFIG_ARCH_BCM283X) := bcm283x
machine-$(CONFIG_ARCH_CLPS711X) := clps711x
machine-$(CONFIG_ARCH_DAVINCI) := davinci
machine-$(CONFIG_ARCH_DIGIC) := digic
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 2e58f15..1029e8f 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -95,7 +95,7 @@ obj-$(CONFIG_MACH_QIL_A9260) += qil-a926x/
obj-$(CONFIG_MACH_QIL_A9G20) += qil-a926x/
obj-$(CONFIG_MACH_RADXA_ROCK) += radxa-rock/
obj-$(CONFIG_MACH_REALQ7) += datamodul-edm-qmx6/
-obj-$(CONFIG_MACH_RPI) += raspberry-pi/
+obj-$(CONFIG_MACH_RPI_COMMON) += raspberry-pi/
obj-$(CONFIG_MACH_SABRELITE) += freescale-mx6-sabrelite/
obj-$(CONFIG_MACH_SABRESD) += freescale-mx6-sabresd/
obj-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += freescale-mx6sx-sabresdb/
diff --git a/arch/arm/boards/at91sam9x5ek/hw_version.c b/arch/arm/boards/at91sam9x5ek/hw_version.c
index 37eb1f8..2f84d82 100644
--- a/arch/arm/boards/at91sam9x5ek/hw_version.c
+++ b/arch/arm/boards/at91sam9x5ek/hw_version.c
@@ -235,7 +235,7 @@ static int cm_cogent_fixup(struct device_node *root, void *unused)
int ret;
struct device_node *node;
- for_each_compatible_node(node, NULL, "atmel,hsmci") {
+ for_each_compatible_node_from(node, root, NULL, "atmel,hsmci") {
struct device_node *slotnode =
of_get_child_by_name(node, "slot");
if (!slotnode)
diff --git a/arch/arm/boards/highbank/init.c b/arch/arm/boards/highbank/init.c
index a0d4b30..1cb02e6 100644
--- a/arch/arm/boards/highbank/init.c
+++ b/arch/arm/boards/highbank/init.c
@@ -35,13 +35,13 @@ static int hb_fixup(struct device_node *root, void *unused)
__be32 latency;
if (!(reg & HB_PWRDOM_STAT_SATA)) {
- for_each_compatible_node(node, NULL, "calxeda,hb-ahci")
+ for_each_compatible_node_from(node, root, NULL, "calxeda,hb-ahci")
of_set_property(node, "status", "disabled",
sizeof("disabled"), 1);
}
if (!(reg & HB_PWRDOM_STAT_EMMC)) {
- for_each_compatible_node(node, NULL, "calxeda,hb-sdhci")
+ for_each_compatible_node_from(node, root, NULL, "calxeda,hb-sdhci")
of_set_property(node, "status", "disabled",
sizeof("disabled"), 1);
}
diff --git a/arch/arm/boards/raspberry-pi/Makefile b/arch/arm/boards/raspberry-pi/Makefile
index 978383a..7a3d7de 100644
--- a/arch/arm/boards/raspberry-pi/Makefile
+++ b/arch/arm/boards/raspberry-pi/Makefile
@@ -1,2 +1,4 @@
+obj-$(CONFIG_MACH_RPI_COMMON) += rpi-common.o
obj-$(CONFIG_MACH_RPI) += rpi.o
+obj-$(CONFIG_MACH_RPI2) += rpi2.o
lwl-y += lowlevel.o
diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c
new file mode 100644
index 0000000..0e17587
--- /dev/null
+++ b/arch/arm/boards/raspberry-pi/rpi-common.c
@@ -0,0 +1,294 @@
+/*
+ * Copyright (C) 2009 Carlo Caione <carlo@carlocaione.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <fs.h>
+#include <linux/stat.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <envfs.h>
+#include <malloc.h>
+#include <gpio.h>
+#include <net.h>
+#include <led.h>
+#include <asm/armlinux.h>
+#include <generated/mach-types.h>
+
+#include <mach/core.h>
+#include <mach/mbox.h>
+
+#include "rpi.h"
+
+struct msg_get_arm_mem {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
+ u32 end_tag;
+};
+
+struct msg_get_clock_rate {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_clock_rate get_clock_rate;
+ u32 end_tag;
+};
+
+struct msg_get_board_rev {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_board_rev get_board_rev;
+ u32 end_tag;
+};
+
+struct msg_get_mac_address {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_mac_address get_mac_address;
+ u32 end_tag;
+};
+
+static int rpi_get_arm_mem(u32 *size)
+{
+ BCM2835_MBOX_STACK_ALIGN(struct msg_get_arm_mem, msg);
+ int ret;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret)
+ return ret;
+
+ *size = msg->get_arm_mem.body.resp.mem_size;
+
+ return 0;
+}
+
+static int rpi_register_clkdev(u32 clock_id, const char *name)
+{
+ BCM2835_MBOX_STACK_ALIGN(struct msg_get_clock_rate, msg);
+ struct clk *clk;
+ int ret;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_clock_rate, GET_CLOCK_RATE);
+ msg->get_clock_rate.body.req.clock_id = clock_id;
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret)
+ return ret;
+
+ clk = clk_fixed(name, msg->get_clock_rate.body.resp.rate_hz);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ if (!clk_register_clkdev(clk, NULL, name))
+ return -ENODEV;
+
+ return 0;
+}
+
+void rpi_set_usbethaddr(void)
+{
+ BCM2835_MBOX_STACK_ALIGN(struct msg_get_mac_address, msg);
+ int ret;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret) {
+ printf("bcm2835: Could not query MAC address\n");
+ /* Ignore error; not critical */
+ return;
+ }
+
+ eth_register_ethaddr(0, msg->get_mac_address.body.resp.mac);
+}
+
+struct gpio_led rpi_leds[] = {
+ {
+ .gpio = -EINVAL,
+ .led = {
+ .name = "ACT",
+ },
+ }, {
+ .gpio = -EINVAL,
+ .led = {
+ .name = "PWR",
+ },
+ },
+};
+
+void rpi_add_led(void)
+{
+ int i;
+ struct gpio_led *l;
+
+ for (i = 0; i < ARRAY_SIZE(rpi_leds); i++) {
+ l = &rpi_leds[i];
+
+ if (gpio_is_valid(l->gpio))
+ led_gpio_register(l);
+ }
+
+ l = &rpi_leds[0];
+ if (gpio_is_valid(l->gpio))
+ led_set_trigger(LED_TRIGGER_HEARTBEAT, &l->led);
+}
+
+void rpi_b_plus_init(void)
+{
+ rpi_leds[0].gpio = 47;
+ rpi_leds[1].gpio = 35;
+ rpi_set_usbethaddr();
+}
+
+static int rpi_board_rev = 0;
+
+static void rpi_get_board_rev(void)
+{
+ int ret;
+ char *name;
+
+ BCM2835_MBOX_STACK_ALIGN(struct msg_get_board_rev, msg);
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret) {
+ printf("bcm2835: Could not query board revision\n");
+ /* Ignore error; not critical */
+ return;
+ }
+
+ /* Comments from u-boot:
+ * For details of old-vs-new scheme, see:
+ * https://github.com/pimoroni/RPi.version/blob/master/RPi/version.py
+ * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=99293&p=690282
+ * (a few posts down)
+ *
+ * For the RPi 1, bit 24 is the "warranty bit", so we mask off just the
+ * lower byte to use as the board rev:
+ * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=98367&start=250
+ * http://www.raspberrypi.org/forums/viewtopic.php?f=31&t=20594
+ */
+ rpi_board_rev = msg->get_board_rev.body.resp.rev;
+ if (rpi_board_rev & 0x800000)
+ rpi_board_rev = (rpi_board_rev >> 4) & 0xff;
+ else
+ rpi_board_rev &= 0xff;
+ if (rpi_board_rev >= rpi_models_size) {
+ printf("RPI: Board rev %u outside known range\n",
+ rpi_board_rev);
+ goto unknown_rev;
+ }
+
+ if (!rpi_models[rpi_board_rev].name) {
+ printf("RPI: Board rev %u unknown\n", rpi_board_rev);
+ goto unknown_rev;
+ }
+
+ if (!rpi_board_rev)
+ goto unknown_rev;
+
+ name = asprintf("RaspberryPi %s %s", rpi_models[rpi_board_rev].name,
+ rpi_model_string);
+ barebox_set_model(name);
+ free(name);
+
+ return;
+
+unknown_rev:
+ rpi_board_rev = 0;
+ name = asprintf("RaspberryPi %s", rpi_model_string);
+ barebox_set_model(name);
+ free(name);
+}
+
+static void rpi_model_init(void)
+{
+ if (!rpi_models[rpi_board_rev].init)
+ return;
+
+ rpi_models[rpi_board_rev].init();
+ rpi_add_led();
+}
+
+static int rpi_mem_init(void)
+{
+ u32 size = 0;
+ int ret;
+
+ ret = rpi_get_arm_mem(&size);
+ if (ret)
+ printf("could not query ARM memory size\n");
+
+ bcm2835_add_device_sdram(size);
+
+ return ret;
+}
+mem_initcall(rpi_mem_init);
+
+static int rpi_console_init(void)
+{
+ rpi_get_board_rev();
+ barebox_set_hostname("rpi");
+
+ bcm2835_register_uart();
+ return 0;
+}
+console_initcall(rpi_console_init);
+
+static int rpi_clock_init(void)
+{
+ rpi_register_clkdev(BCM2835_MBOX_CLOCK_ID_EMMC, "bcm2835_mci0");
+ return 0;
+}
+postconsole_initcall(rpi_clock_init);
+
+static int rpi_env_init(void)
+{
+ struct stat s;
+ const char *diskdev = "/dev/disk0.0";
+ int ret;
+
+ device_detect_by_name("mci0");
+
+ ret = stat(diskdev, &s);
+ if (ret) {
+ printf("no %s. using default env\n", diskdev);
+ return 0;
+ }
+
+ mkdir("/boot", 0666);
+ ret = mount(diskdev, "fat", "/boot", NULL);
+ if (ret) {
+ printf("failed to mount %s\n", diskdev);
+ return 0;
+ }
+
+ default_environment_path_set("/boot/barebox.env");
+
+ return 0;
+}
+
+static int rpi_devices_init(void)
+{
+ rpi_model_init();
+ bcm2835_register_mci();
+ bcm2835_register_fb();
+ armlinux_set_architecture(MACH_TYPE_BCM2708);
+ rpi_env_init();
+ return 0;
+}
+late_initcall(rpi_devices_init);
diff --git a/arch/arm/boards/raspberry-pi/rpi.c b/arch/arm/boards/raspberry-pi/rpi.c
index f9406d4..dd2ad7f 100644
--- a/arch/arm/boards/raspberry-pi/rpi.c
+++ b/arch/arm/boards/raspberry-pi/rpi.c
@@ -13,161 +13,17 @@
*
*/
-#include <common.h>
-#include <init.h>
-#include <fs.h>
-#include <linux/stat.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <envfs.h>
-#include <malloc.h>
-#include <gpio.h>
-#include <net.h>
-#include <led.h>
-#include <asm/armlinux.h>
-#include <generated/mach-types.h>
-
-#include <mach/core.h>
-#include <mach/mbox.h>
-
-struct msg_get_arm_mem {
- struct bcm2835_mbox_hdr hdr;
- struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
- u32 end_tag;
-};
-
-struct msg_get_clock_rate {
- struct bcm2835_mbox_hdr hdr;
- struct bcm2835_mbox_tag_get_clock_rate get_clock_rate;
- u32 end_tag;
-};
-
-struct msg_get_board_rev {
- struct bcm2835_mbox_hdr hdr;
- struct bcm2835_mbox_tag_get_board_rev get_board_rev;
- u32 end_tag;
-};
-
-struct msg_get_mac_address {
- struct bcm2835_mbox_hdr hdr;
- struct bcm2835_mbox_tag_get_mac_address get_mac_address;
- u32 end_tag;
-};
-
-static int rpi_get_arm_mem(u32 *size)
-{
- BCM2835_MBOX_STACK_ALIGN(struct msg_get_arm_mem, msg);
- int ret;
-
- BCM2835_MBOX_INIT_HDR(msg);
- BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY);
-
- ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
- if (ret)
- return ret;
-
- *size = msg->get_arm_mem.body.resp.mem_size;
-
- return 0;
-}
-
-static int rpi_register_clkdev(u32 clock_id, const char *name)
-{
- BCM2835_MBOX_STACK_ALIGN(struct msg_get_clock_rate, msg);
- struct clk *clk;
- int ret;
-
- BCM2835_MBOX_INIT_HDR(msg);
- BCM2835_MBOX_INIT_TAG(&msg->get_clock_rate, GET_CLOCK_RATE);
- msg->get_clock_rate.body.req.clock_id = clock_id;
-
- ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
- if (ret)
- return ret;
-
- clk = clk_fixed(name, msg->get_clock_rate.body.resp.rate_hz);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
- if (!clk_register_clkdev(clk, NULL, name))
- return -ENODEV;
-
- return 0;
-}
-
-static void rpi_set_usbethaddr(void)
-{
- BCM2835_MBOX_STACK_ALIGN(struct msg_get_mac_address, msg);
- int ret;
-
- BCM2835_MBOX_INIT_HDR(msg);
- BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS);
-
- ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
- if (ret) {
- printf("bcm2835: Could not query MAC address\n");
- /* Ignore error; not critical */
- return;
- }
-
- eth_register_ethaddr(0, msg->get_mac_address.body.resp.mac);
-}
-
-static struct gpio_led leds[] = {
- {
- .gpio = -EINVAL,
- .led = {
- .name = "ACT",
- },
- }, {
- .gpio = -EINVAL,
- .led = {
- .name = "PWR",
- },
- },
-};
-
-static void rpi_add_led(void)
-{
- int i;
- struct gpio_led *l;
-
- for (i = 0; i < ARRAY_SIZE(leds); i++) {
- l = &leds[i];
-
- if (gpio_is_valid(l->gpio))
- led_gpio_register(l);
- }
-
- l = &leds[0];
- if (gpio_is_valid(l->gpio))
- led_set_trigger(LED_TRIGGER_HEARTBEAT, &l->led);
-}
-
-static void rpi_b_plus_init(void)
-{
- leds[0].gpio = 47;
- leds[1].gpio = 35;
- rpi_set_usbethaddr();
-}
+#include "rpi.h"
static void rpi_b_init(void)
{
- leds[0].gpio = 16;
- leds[0].active_low = 1;
+ rpi_leds[0].gpio = 16;
+ rpi_leds[0].active_low = 1;
rpi_set_usbethaddr();
}
-#define RPI_MODEL(_id, _name, _init) \
- [_id] = { \
- .name = _name,\
- .init = _init,\
- }
/* See comments in mbox.h for data source */
-static const struct {
- const char *name;
- void (*init)(void);
-} models[] = {
+const struct rpi_model rpi_models[] = {
RPI_MODEL(0, "Unknown model", NULL),
RPI_MODEL(BCM2835_BOARD_REV_B_I2C0_2, "Model B (no P5)", rpi_b_init),
RPI_MODEL(BCM2835_BOARD_REV_B_I2C0_3, "Model B (no P5)", rpi_b_init),
@@ -184,126 +40,5 @@ static const struct {
RPI_MODEL(BCM2835_BOARD_REV_CM, "Compute Module", NULL),
RPI_MODEL(BCM2835_BOARD_REV_A_PLUS, "Model A+", NULL),
};
-
-static int rpi_board_rev = 0;
-
-static void rpi_get_board_rev(void)
-{
- int ret;
- char *name;
-
- BCM2835_MBOX_STACK_ALIGN(struct msg_get_board_rev, msg);
- BCM2835_MBOX_INIT_HDR(msg);
- BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV);
-
- ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
- if (ret) {
- printf("bcm2835: Could not query board revision\n");
- /* Ignore error; not critical */
- return;
- }
-
- rpi_board_rev = msg->get_board_rev.body.resp.rev;
- if (rpi_board_rev >= ARRAY_SIZE(models)) {
- printf("RPI: Board rev %u outside known range\n",
- rpi_board_rev);
- goto unknown_rev;
- }
-
- if (!models[rpi_board_rev].name) {
- printf("RPI: Board rev %u unknown\n", rpi_board_rev);
- goto unknown_rev;
- }
-
- if (!rpi_board_rev)
- goto unknown_rev;
-
- name = asprintf("RaspberryPi %s (BCM2835/ARM1176JZF-S)",
- models[rpi_board_rev].name);
- barebox_set_model(name);
- free(name);
-
- return;
-
-unknown_rev:
- rpi_board_rev = 0;
- barebox_set_model("RaspberryPi (BCM2835/ARM1176JZF-S)");
-}
-
-static void rpi_model_init(void)
-{
- if (!models[rpi_board_rev].init)
- return;
-
- models[rpi_board_rev].init();
- rpi_add_led();
-}
-
-static int rpi_mem_init(void)
-{
- u32 size = 0;
- int ret;
-
- ret = rpi_get_arm_mem(&size);
- if (ret)
- printf("could not query ARM memory size\n");
-
- bcm2835_add_device_sdram(size);
-
- return ret;
-}
-mem_initcall(rpi_mem_init);
-
-static int rpi_console_init(void)
-{
- rpi_get_board_rev();
- barebox_set_hostname("rpi");
-
- bcm2835_register_uart();
- return 0;
-}
-console_initcall(rpi_console_init);
-
-static int rpi_clock_init(void)
-{
- rpi_register_clkdev(BCM2835_MBOX_CLOCK_ID_EMMC, "bcm2835_mci0");
- return 0;
-}
-postconsole_initcall(rpi_clock_init);
-
-static int rpi_env_init(void)
-{
- struct stat s;
- const char *diskdev = "/dev/disk0.0";
- int ret;
-
- device_detect_by_name("mci0");
-
- ret = stat(diskdev, &s);
- if (ret) {
- printf("no %s. using default env\n", diskdev);
- return 0;
- }
-
- mkdir("/boot", 0666);
- ret = mount(diskdev, "fat", "/boot", NULL);
- if (ret) {
- printf("failed to mount %s\n", diskdev);
- return 0;
- }
-
- default_environment_path_set("/boot/barebox.env");
-
- return 0;
-}
-
-static int rpi_devices_init(void)
-{
- rpi_model_init();
- bcm2835_register_mci();
- bcm2835_register_fb();
- armlinux_set_architecture(MACH_TYPE_BCM2708);
- rpi_env_init();
- return 0;
-}
-late_initcall(rpi_devices_init);
+const size_t rpi_models_size = ARRAY_SIZE(rpi_models);
+const char *rpi_model_string = "(BCM2835/ARM1176JZF-S)";
diff --git a/arch/arm/boards/raspberry-pi/rpi.h b/arch/arm/boards/raspberry-pi/rpi.h
new file mode 100644
index 0000000..739cdee
--- /dev/null
+++ b/arch/arm/boards/raspberry-pi/rpi.h
@@ -0,0 +1,28 @@
+#ifndef __ARCH_ARM_BOARDS_RPI_H__
+#define __ARCH_ARM_BOARDS_RPI_H__
+
+#include <types.h>
+#include <led.h>
+
+#include <mach/mbox.h>
+
+#define RPI_MODEL(_id, _name, _init) \
+ [_id] = { \
+ .name = _name,\
+ .init = _init,\
+ }
+
+struct rpi_model {
+ const char *name;
+ void (*init)(void);
+};
+
+extern const struct rpi_model rpi_models[];
+extern const size_t rpi_models_size;
+extern const char *rpi_model_string;
+extern struct gpio_led rpi_leds[];
+
+void rpi_b_plus_init(void);
+void rpi_set_usbethaddr(void);
+
+#endif /* __ARCH_ARM_BOARDS_RPI_H__ */
diff --git a/arch/arm/boards/raspberry-pi/rpi2.c b/arch/arm/boards/raspberry-pi/rpi2.c
new file mode 100644
index 0000000..2cfc06f
--- /dev/null
+++ b/arch/arm/boards/raspberry-pi/rpi2.c
@@ -0,0 +1,21 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include "rpi.h"
+
+const struct rpi_model rpi_models[] = {
+ RPI_MODEL(0, "Unknown model", NULL),
+ RPI_MODEL(BCM2836_BOARD_REV_2_B, "2 Model B", rpi_b_plus_init),
+};
+const size_t rpi_models_size = ARRAY_SIZE(rpi_models);
+const char *rpi_model_string = "(BCM2836/CORTEX-A7)";
diff --git a/arch/arm/configs/rpi2_defconfig b/arch/arm/configs/rpi2_defconfig
new file mode 100644
index 0000000..81f821a
--- /dev/null
+++ b/arch/arm/configs/rpi2_defconfig
@@ -0,0 +1,72 @@
+CONFIG_ARCH_BCM2836=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_PROMPT="R-Pi> "
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+CONFIG_BLSPEC=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/raspberry-pi/env"
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_LOGIN=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_PASSWD=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_MCI=y
+CONFIG_MCI_BCM283X=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_GPIO_BCM283X=y
+CONFIG_REGULATOR=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_DIGEST_SHA1_GENERIC=y
+CONFIG_DIGEST_SHA256_GENERIC=y
diff --git a/arch/arm/configs/rpi_defconfig b/arch/arm/configs/rpi_defconfig
index 25770a0..f7b5910 100644
--- a/arch/arm/configs/rpi_defconfig
+++ b/arch/arm/configs/rpi_defconfig
@@ -6,7 +6,6 @@ CONFIG_MMU=y
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_PROMPT="R-Pi> "
-CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
@@ -14,52 +13,57 @@ CONFIG_MENU=y
CONFIG_BLSPEC=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/raspberry-pi/env"
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_MSLEEP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_LET=y
-CONFIG_CMD_MENU=y
-CONFIG_CMD_MENU_MANAGEMENT=y
-CONFIG_CMD_LOGIN=y
-CONFIG_CMD_PASSWD=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_LN=y
-CONFIG_CMD_FILETYPE=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_LOADY=y
-CONFIG_CMD_MEMINFO=y
+CONFIG_LONGHELP=y
CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MM=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_CRC_CMP=y
-CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
-CONFIG_CMD_OFTREE=y
-CONFIG_CMD_OF_PROPERTY=y
-CONFIG_CMD_OF_NODE=y
-CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_UIMAGE=y
CONFIG_CMD_PARTITION=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_GPIO=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_LOGIN=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_PASSWD=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MM=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DETECT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_MCI=y
-CONFIG_MCI_BCM2835=y
-CONFIG_GPIO_BCM2835=y
+CONFIG_MCI_BCM283X=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_GPIO_BCM283X=y
+CONFIG_REGULATOR=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 0a31de5..7fbe045 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -67,6 +67,7 @@ CONFIG_NET=y
CONFIG_NET_NETCONSOLE=y
CONFIG_NET_RESOLV=y
CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_OF_BAREBOX_ENV_IN_FS=y
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_NET_DESIGNWARE=y
CONFIG_MCI=y
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 418bcab..854df60e 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -11,6 +11,11 @@ obj-$(CONFIG_CMD_ARM_MMUINFO) += mmuinfo.o
obj-$(CONFIG_OFDEVICE) += dtb.o
obj-$(CONFIG_MMU) += mmu.o cache.o mmu-early.o
pbl-$(CONFIG_MMU) += mmu-early.o
+
+ifeq ($(CONFIG_MMU),)
+obj-y += no-mmu.o
+endif
+
obj-$(CONFIG_CPU_32v4T) += cache-armv4.o
pbl-$(CONFIG_CPU_32v4T) += cache-armv4.o
obj-$(CONFIG_CPU_32v5) += cache-armv5.o
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 784221c..bc5325f 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -302,6 +302,16 @@ static void vectors_init(void)
* live without being able to catch NULL pointer dereferences
*/
exc = arm_create_pte(0x0);
+
+ if (cpu_architecture() >= CPU_ARCH_ARMv7) {
+ /*
+ * ARMv7 CPUs allow to remap low vectors from
+ * 0x0 to an arbitrary address using VBAR
+ * register, so let's make sure we have it
+ * pointing to the correct address
+ */
+ set_vbar(0x0);
+ }
}
arm_fixup_vectors();
diff --git a/arch/arm/cpu/no-mmu.c b/arch/arm/cpu/no-mmu.c
new file mode 100644
index 0000000..e227b45
--- /dev/null
+++ b/arch/arm/cpu/no-mmu.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2015 Zodiac Inflight Innovation
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt) "nommu: " fmt
+
+#include <common.h>
+#include <dma-dir.h>
+#include <init.h>
+#include <mmu.h>
+#include <errno.h>
+#include <linux/sizes.h>
+#include <asm/memory.h>
+#include <asm/barebox-arm.h>
+#include <asm/system.h>
+#include <asm/cache.h>
+#include <memory.h>
+#include <asm/system_info.h>
+#include <debug_ll.h>
+
+
+#define __exceptions_size (__exceptions_stop - __exceptions_start)
+
+static int nommu_v7_vectors_init(void)
+{
+ void *vectors;
+ u32 cr;
+
+ if (cpu_architecture() < CPU_ARCH_ARMv7)
+ return 0;
+
+ /*
+ * High vectors cannot be re-mapped, so we have to use normal
+ * vectors
+ */
+ cr = get_cr();
+ cr &= ~CR_V;
+ set_cr(cr);
+
+ arm_fixup_vectors();
+
+ vectors = xmemalign(PAGE_SIZE, PAGE_SIZE);
+ memset(vectors, 0, PAGE_SIZE);
+ memcpy(vectors, __exceptions_start, __exceptions_size);
+
+ set_vbar((unsigned int)vectors);
+
+ return 0;
+}
+mmu_initcall(nommu_v7_vectors_init);
diff --git a/arch/arm/dts/am33xx-strip.dtsi b/arch/arm/dts/am33xx-strip.dtsi
index 04cf315..2943fd1 100644
--- a/arch/arm/dts/am33xx-strip.dtsi
+++ b/arch/arm/dts/am33xx-strip.dtsi
@@ -45,3 +45,4 @@
/delete-node/ &rng;
/delete-node/ &rtc;
/delete-node/ &wkup_m3;
+/delete-node/ &wkup_m3_ipc;
diff --git a/arch/arm/dts/imx6q-embedsky-e9.dts b/arch/arm/dts/imx6q-embedsky-e9.dts
index 4514d4e..726d620 100644
--- a/arch/arm/dts/imx6q-embedsky-e9.dts
+++ b/arch/arm/dts/imx6q-embedsky-e9.dts
@@ -22,13 +22,13 @@
environment-mmc1 {
compatible = "barebox,environment";
- device-path = &usdhc2, "partname:barebox-environment";
+ device-path = &environment_mmc1;
status = "disabled";
};
environment-mmc3 {
compatible = "barebox,environment";
- device-path = &usdhc4, "partname:barebox-environment";
+ device-path = &environment_mmc3;
status = "disabled";
};
@@ -43,7 +43,7 @@
label = "barebox";
reg = <0x0 0x80000>;
};
- partition@1 {
+ environment_mmc1: partition@1 {
label = "barebox-environment";
reg = <0x80000 0x80000>;
};
@@ -57,7 +57,7 @@
label = "barebox";
reg = <0x0 0x80000>;
};
- partition@1 {
+ environment_mmc3: partition@1 {
label = "barebox-environment";
reg = <0x80000 0x80000>;
};
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index d4d498b..d16758f 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -1,4 +1,12 @@
/ {
+ chosen {
+ environment@0 {
+ compatible = "barebox,environment";
+ device-path = &mmc, "partname:1";
+ file-path = "barebox.env";
+ };
+ };
+
aliases {
mmc0 = &mmc;
};
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 26fb18c..b118a42 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -71,6 +71,26 @@ static inline void set_cr(unsigned int val)
isb();
}
+#ifdef CONFIG_CPU_32v7
+static inline unsigned int get_vbar(void)
+{
+ unsigned int vbar;
+ asm volatile("mrc p15, 0, %0, c12, c0, 0 @ get VBAR"
+ : "=r" (vbar) : : "cc");
+ return vbar;
+}
+
+static inline void set_vbar(unsigned int vbar)
+{
+ asm volatile("mcr p15, 0, %0, c12, c0, 0 @ set VBAR"
+ : : "r" (vbar) : "cc");
+ isb();
+}
+#else
+static inline unsigned int get_vbar(void) { return 0; }
+static inline void set_vbar(unsigned int vbar) {}
+#endif
+
#endif
#endif /* __ASM_ARM_SYSTEM_H */
diff --git a/arch/arm/mach-at91/bootstrap.c b/arch/arm/mach-at91/bootstrap.c
index 1baf732..47e7896 100644
--- a/arch/arm/mach-at91/bootstrap.c
+++ b/arch/arm/mach-at91/bootstrap.c
@@ -51,7 +51,7 @@ static char* is_barebox_to_str(bool is_barebox)
static void at91bootstrap_boot_m25p80(bool is_barebox)
{
char *name = is_barebox_to_str(is_barebox);
- int (*func)(void) = NULL;
+ kernel_entry_func func = NULL;
func = bootstrap_board_read_m25p80();
printf("Boot %s from m25p80\n", name);
@@ -63,7 +63,7 @@ static void at91bootstrap_boot_m25p80(bool is_barebox)
static void at91bootstrap_boot_dataflash(bool is_barebox)
{
char *name = is_barebox_to_str(is_barebox);
- int (*func)(void) = NULL;
+ kernel_entry_func func = NULL;
printf("Boot %s from dataflash\n", name);
func = bootstrap_board_read_dataflash();
@@ -75,7 +75,7 @@ static void at91bootstrap_boot_dataflash(bool is_barebox)
static void at91bootstrap_boot_nand(bool is_barebox)
{
char *name = is_barebox_to_str(is_barebox);
- int (*func)(void) = NULL;
+ kernel_entry_func func = NULL;
printf("Boot %s from nand\n", name);
func = bootstrap_read_devfs("nand0", true, SZ_128K, SZ_256K, SZ_1M);
@@ -86,7 +86,7 @@ static void at91bootstrap_boot_nand(bool is_barebox)
static void at91bootstrap_boot_mmc(void)
{
- int (*func)(void) = NULL;
+ kernel_entry_func func = NULL;
printf("Boot from mmc\n");
func = bootstrap_read_disk("disk0.0", NULL);
diff --git a/arch/arm/mach-bcm2835/Kconfig b/arch/arm/mach-bcm2835/Kconfig
deleted file mode 100644
index 134ad9b..0000000
--- a/arch/arm/mach-bcm2835/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if ARCH_BCM2835
-
-config ARCH_TEXT_BASE
- hex
- default 0x04000000 if MACH_RPI
-
-choice
- prompt "Broadcom Board type"
-
-config MACH_RPI
- bool "RaspberryPi (BCM2835/ARM1176JZF-S)"
-
-endchoice
-
-endif
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
new file mode 100644
index 0000000..e861268
--- /dev/null
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -0,0 +1,25 @@
+if ARCH_BCM283X
+
+config ARCH_TEXT_BASE
+ hex
+ default 0x04000000
+
+config MACH_RPI_COMMON
+ bool
+
+choice
+ prompt "Broadcom Board type"
+
+config MACH_RPI
+ bool "RaspberryPi (BCM2835/ARM1176JZF-S)"
+ depends on ARCH_BCM2835
+ select MACH_RPI_COMMON
+
+config MACH_RPI2
+ bool "RaspberryPi 2 (BCM2836/CORTEX-A7)"
+ depends on ARCH_BCM2836
+ select MACH_RPI_COMMON
+
+endchoice
+
+endif
diff --git a/arch/arm/mach-bcm2835/Makefile b/arch/arm/mach-bcm283x/Makefile
index 940f98c..940f98c 100644
--- a/arch/arm/mach-bcm2835/Makefile
+++ b/arch/arm/mach-bcm283x/Makefile
diff --git a/arch/arm/mach-bcm2835/core.c b/arch/arm/mach-bcm283x/core.c
index 64f3781..64f3781 100644
--- a/arch/arm/mach-bcm2835/core.c
+++ b/arch/arm/mach-bcm283x/core.c
diff --git a/arch/arm/mach-bcm2835/include/mach/core.h b/arch/arm/mach-bcm283x/include/mach/core.h
index 477ecb9..b0bed80 100644
--- a/arch/arm/mach-bcm2835/include/mach/core.h
+++ b/arch/arm/mach-bcm283x/include/mach/core.h
@@ -24,7 +24,7 @@ void bcm2835_add_device_sdram(u32 size);
static void inline bcm2835_register_mci(void)
{
add_generic_device("bcm2835_mci", 0, NULL, BCM2835_EMMC_BASE, 0xFC,
- IORESOURCE_MEM, NULL);
+ IORESOURCE_MEM, NULL);
}
static void inline bcm2835_register_fb(void)
diff --git a/arch/arm/mach-bcm2835/include/mach/debug_ll.h b/arch/arm/mach-bcm283x/include/mach/debug_ll.h
index be93cd9..be93cd9 100644
--- a/arch/arm/mach-bcm2835/include/mach/debug_ll.h
+++ b/arch/arm/mach-bcm283x/include/mach/debug_ll.h
diff --git a/arch/arm/mach-bcm2835/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
index 4c3fd77..cd9ee1f 100644
--- a/arch/arm/mach-bcm2835/include/mach/mbox.h
+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
@@ -11,6 +11,8 @@
#include <common.h>
+#include <mach/platform.h>
+
/*
* The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU")
* and the ARM CPU. The ARM CPU is often thought of as the main CPU.
@@ -40,7 +42,7 @@
/* Raw mailbox HW */
-#define BCM2835_MBOX_PHYSADDR 0x2000b880
+#define BCM2835_MBOX_PHYSADDR (BCM2835_ARM_BASE + 0x880)
struct bcm2835_mbox_regs {
u32 read;
@@ -74,7 +76,7 @@ struct bcm2835_mbox_hdr {
#define BCM2835_MBOX_RESP_CODE_SUCCESS 0x80000000
#define BCM2835_MBOX_STACK_ALIGN(type, name) \
- STACK_ALIGN_ARRAY(type, name, 1, BCM2835_CHAN_MASK + 1)
+ STACK_ALIGN_ARRAY(type, name, 1, BCM2835_CACHELINE_SIZE)
#define BCM2835_MBOX_INIT_HDR(_m_) { \
memset((_m_), 0, sizeof(*(_m_))); \
@@ -126,6 +128,9 @@ struct bcm2835_mbox_tag_hdr {
#define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002
+/* RPi 2 */
+#define BCM2836_BOARD_REV_2_B 0x4
+
/*
* 0x2..0xf from:
* http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/
diff --git a/arch/arm/mach-bcm2835/include/mach/platform.h b/arch/arm/mach-bcm283x/include/mach/platform.h
index e55085a..3b73831 100644
--- a/arch/arm/mach-bcm2835/include/mach/platform.h
+++ b/arch/arm/mach-bcm283x/include/mach/platform.h
@@ -28,7 +28,16 @@
* This file is manually generated.
*/
+#ifdef CONFIG_ARCH_BCM2835
#define BCM2835_PERI_BASE 0x20000000
+#define BCM2835_CACHELINE_SIZE 32
+#elif defined CONFIG_ARCH_BCM2836
+#define BCM2835_PERI_BASE 0x3f000000
+#define BCM2835_CACHELINE_SIZE 64
+#else
+#error "no CONFIG_ARCH_BCM283X defined"
+#endif
+
#define BCM2835_ST_BASE (BCM2835_PERI_BASE + 0x3000) /* System Timer */
#define BCM2835_DMA_BASE (BCM2835_PERI_BASE + 0x7000) /* DMA controller */
#define BCM2835_ARM_BASE (BCM2835_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
diff --git a/arch/arm/mach-bcm2835/include/mach/wd.h b/arch/arm/mach-bcm283x/include/mach/wd.h
index ad8b762..ad8b762 100644
--- a/arch/arm/mach-bcm2835/include/mach/wd.h
+++ b/arch/arm/mach-bcm283x/include/mach/wd.h
diff --git a/arch/arm/mach-bcm2835/mbox.c b/arch/arm/mach-bcm283x/mbox.c
index 9d69bc8..9d69bc8 100644
--- a/arch/arm/mach-bcm2835/mbox.c
+++ b/arch/arm/mach-bcm283x/mbox.c
diff --git a/arch/arm/mach-imx/ocotp.c b/arch/arm/mach-imx/ocotp.c
index 6ff5ee4..c99a003 100644
--- a/arch/arm/mach-imx/ocotp.c
+++ b/arch/arm/mach-imx/ocotp.c
@@ -426,7 +426,6 @@ static int imx_ocotp_probe(struct device_d *dev)
cdev->priv = priv;
cdev->size = 192;
cdev->name = "imx-ocotp";
- cdev->device_node = dev->device_node;
ret = devfs_create(cdev);
diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h
index fbac9b5..e36f49d 100644
--- a/arch/arm/mach-omap/include/mach/sys_info.h
+++ b/arch/arm/mach-omap/include/mach/sys_info.h
@@ -90,7 +90,7 @@ u32 get_cpu_type(void);
u32 get_cpu_rev(void);
u32 get_sdr_cs_size(u32 offset);
u32 get_sdr_cs1_base(void);
-inline u32 get_sysboot_value(void);
+u32 get_sysboot_value(void);
u32 get_boot_type(void);
u32 get_device_type(void);
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index 5c29fea..5327bad 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -200,7 +200,7 @@ EXPORT_SYMBOL(get_sdr_cs1_base);
*
* @return - Return the value of SYSBOOT.
*/
-inline u32 get_sysboot_value(void)
+u32 get_sysboot_value(void)
{
return (0x0000003F & readl(OMAP3_CONTROL_REG(STATUS)));
}
diff --git a/arch/arm/mach-socfpga/generic.c b/arch/arm/mach-socfpga/generic.c
index 2d4afd0..906bc63 100644
--- a/arch/arm/mach-socfpga/generic.c
+++ b/arch/arm/mach-socfpga/generic.c
@@ -103,41 +103,3 @@ static int socfpga_init(void)
return 0;
}
core_initcall(socfpga_init);
-
-#if defined(CONFIG_ENV_HANDLING)
-#define ENV_PATH "/boot/barebox.env"
-static int socfpga_env_init(void)
-{
- struct stat s;
- char *diskdev, *partname;
- int ret;
-
- diskdev = "mmc0";
-
- device_detect_by_name(diskdev);
-
- partname = asprintf("/dev/%s.1", diskdev);
-
- ret = stat(partname, &s);
-
- if (ret) {
- pr_err("Failed to load environment: no device '%s'\n", diskdev);
- goto out_free;
- }
-
- mkdir("/boot", 0666);
- ret = mount(partname, "fat", "/boot", NULL);
- if (ret) {
- pr_err("Failed to load environment: mount %s failed (%d)\n", partname, ret);
- goto out_free;
- }
-
- pr_debug("Loading default env from %s on device %s\n", ENV_PATH, diskdev);
- default_environment_path_set(ENV_PATH);
-
-out_free:
- free(partname);
- return 0;
-}
-late_initcall(socfpga_env_init);
-#endif
diff --git a/commands/devinfo.c b/commands/devinfo.c
index 3c9d6a6..c78efcb 100644
--- a/commands/devinfo.c
+++ b/commands/devinfo.c
@@ -21,7 +21,7 @@
static int do_devinfo_subtree(struct device_d *dev, int depth)
{
struct device_d *child;
- struct cdev *cdev;
+ struct cdev *cdev, *cdevl;
int i;
for (i = 0; i < depth; i++)
@@ -33,11 +33,14 @@ static int do_devinfo_subtree(struct device_d *dev, int depth)
list_for_each_entry(cdev, &dev->cdevs, devices_list) {
for (i = 0; i < depth + 1; i++)
printf(" ");
- printf("`-- 0x%08llx-0x%08llx (%10s): /dev/%s\n",
+ printf("`-- 0x%08llx-0x%08llx (%10s): /dev/%s",
cdev->offset,
cdev->offset + cdev->size - 1,
size_human_readable(cdev->size),
cdev->name);
+ list_for_each_entry(cdevl, &cdev->links, link_entry)
+ printf(", %s", cdevl->name);
+ printf("\n");
}
} else {
printf("\n");
diff --git a/commands/ubiformat.c b/commands/ubiformat.c
index 8516e11..f9c50b7 100644
--- a/commands/ubiformat.c
+++ b/commands/ubiformat.c
@@ -503,9 +503,8 @@ static int format(const struct mtd_dev_info *mtd,
write_size, eb);
if (errno != EIO) {
- if (!args.subpage_size != mtd->min_io_size)
- normsg("may be sub-page size is "
- "incorrect?");
+ if (args.subpage_size != mtd->min_io_size)
+ normsg("may be sub-page size is incorrect?");
goto out_free;
}
diff --git a/common/partitions.c b/common/partitions.c
index 4f50bfe..82ec508 100644
--- a/common/partitions.c
+++ b/common/partitions.c
@@ -71,20 +71,14 @@ static int register_one_partition(struct block_device *blk,
if (!part->name[0])
return 0;
- partition_name = asprintf("%s.%s", blk->cdev.name, part->name);
- if (!partition_name)
- return -ENOMEM;
-
- dev_dbg(blk->dev, "Registering partition %s on drive %s\n",
- partition_name, blk->cdev.name);
- cdev = devfs_add_partition(blk->cdev.name,
- start, size, 0, partition_name);
-
- if (IS_ERR(cdev))
- dev_warn(blk->dev, "Registering partition %s on drive %s failed\n",
- partition_name, blk->cdev.name);
+ partition_name = xasprintf("%s.%s", blk->cdev.name, part->name);
+ ret = devfs_create_link(cdev, partition_name);
+ if (ret)
+ dev_warn(blk->dev, "Failed to create link from %s to %s\n",
+ partition_name, blk->cdev.name);
+ free(partition_name);
- ret = 0;
+ return 0;
out:
free(partition_name);
return ret;
diff --git a/common/partitions/Kconfig b/common/partitions/Kconfig
index 90238ad..be9405a 100644
--- a/common/partitions/Kconfig
+++ b/common/partitions/Kconfig
@@ -16,6 +16,7 @@ config PARTITION_DISK_DOS
config PARTITION_DISK_EFI
depends on PARTITION_DISK
select CRC32
+ select PRINTF_UUID
bool "EFI: GPT partition support"
help
Add support to handle partitions in GUID Partition Table style.
diff --git a/common/partitions/efi.c b/common/partitions/efi.c
index 61abf00..a9945dd 100644
--- a/common/partitions/efi.c
+++ b/common/partitions/efi.c
@@ -457,6 +457,7 @@ static void efi_partition(void *buf, struct block_device *blk,
pentry->size = le64_to_cpu(ptes[i].ending_lba) - pentry->first_sec;
pentry->size++;
part_set_efi_name(&ptes[i], pentry->name);
+ snprintf(pentry->partuuid, sizeof(pentry->partuuid), "%pUl", &ptes[i].unique_partition_guid);
pd->used_entries++;
}
diff --git a/common/state.c b/common/state.c
index ec72dbd..d1fa47f 100644
--- a/common/state.c
+++ b/common/state.c
@@ -66,6 +66,7 @@ enum state_variable_type {
STATE_TYPE_ENUM,
STATE_TYPE_U8,
STATE_TYPE_U32,
+ STATE_TYPE_S32,
STATE_TYPE_MAC,
STATE_TYPE_STRING,
};
@@ -209,8 +210,8 @@ static struct state_variable *state_uint8_create(struct state *state,
return &su32->var;
}
-static struct state_variable *state_uint32_create(struct state *state,
- const char *name, struct device_node *node)
+static struct state_variable *state_int32_create(struct state *state,
+ const char *name, struct device_node *node, const char *format)
{
struct state_uint32 *su32;
struct param_d *param;
@@ -218,7 +219,7 @@ static struct state_variable *state_uint32_create(struct state *state,
su32 = xzalloc(sizeof(*su32));
param = dev_add_param_int(&state->dev, name, state_set_dirty,
- NULL, &su32->value, "%u", state);
+ NULL, &su32->value, format, state);
if (IS_ERR(param)) {
free(su32);
return ERR_CAST(param);
@@ -231,6 +232,18 @@ static struct state_variable *state_uint32_create(struct state *state,
return &su32->var;
}
+static struct state_variable *state_uint32_create(struct state *state,
+ const char *name, struct device_node *node)
+{
+ return state_int32_create(state, name, node, "%u");
+}
+
+static struct state_variable *state_sint32_create(struct state *state,
+ const char *name, struct device_node *node)
+{
+ return state_int32_create(state, name, node, "%d");
+}
+
/*
* enum32
*/
@@ -605,6 +618,12 @@ static struct variable_type types[] = {
.export = state_string_export,
.import = state_string_import,
.create = state_string_create,
+ }, {
+ .type = STATE_TYPE_S32,
+ .type_name = "int32",
+ .export = state_uint32_export,
+ .import = state_uint32_import,
+ .create = state_sint32_create,
},
};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 598edc9..3fb09fb 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -6,9 +6,9 @@ config ARM_SMP_TWD
bool
depends on ARM && CPU_V7
-config CLOCKSOURCE_BCM2835
+config CLOCKSOURCE_BCM283X
bool
- depends on ARCH_BCM2835
+ depends on ARCH_BCM283X
config CLOCKSOURCE_CLPS711X
bool
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index f5f5141..4eb1656 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -1,6 +1,6 @@
obj-$(CONFIG_AMBA_SP804) += amba-sp804.o
obj-$(CONFIG_ARM_SMP_TWD) += arm_smp_twd.o
-obj-$(CONFIG_CLOCKSOURCE_BCM2835) += bcm2835.o
+obj-$(CONFIG_CLOCKSOURCE_BCM283X) += bcm2835.o
obj-$(CONFIG_CLOCKSOURCE_CLPS711X) += clps711x.o
obj-$(CONFIG_CLOCKSOURCE_DIGIC) += digic.o
obj-$(CONFIG_CLOCKSOURCE_MVEBU) += mvebu.o
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 9cb2261..d839d7a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -21,9 +21,9 @@ config GPIO_74164
shift registers. This driver can be used to provide access
to more gpio outputs.
-config GPIO_BCM2835
- bool "GPIO support for BCM2835"
- depends on ARCH_BCM2835
+config GPIO_BCM283X
+ bool "GPIO support for BCM283X"
+ depends on ARCH_BCM283X
config GPIO_CLPS711X
bool "GPIO support for CLPS711X"
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index f39e8da..8767eed 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -2,7 +2,7 @@ obj-$(CONFIG_GPIOLIB) += gpiolib.o
obj-$(CONFIG_GPIO_74164) += gpio-74164.o
obj-$(CONFIG_MACH_MIPS_ATH79) += gpio-ath79.o
-obj-$(CONFIG_GPIO_BCM2835) += gpio-bcm2835.o
+obj-$(CONFIG_GPIO_BCM283X) += gpio-bcm2835.o
obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o
obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o
obj-$(CONFIG_GPIO_DIGIC) += gpio-digic.o
diff --git a/drivers/input/gpio_keys.c b/drivers/input/gpio_keys.c
index d017594..5b03fd7 100644
--- a/drivers/input/gpio_keys.c
+++ b/drivers/input/gpio_keys.c
@@ -21,6 +21,9 @@ struct gpio_key {
int active_low;
int previous_state;
+
+ int debounce_interval;
+ u64 debounce_start;
};
struct gpio_keys {
@@ -60,11 +63,17 @@ static void gpio_key_poller(struct poller_struct *poller)
gb = &gk->buttons[i];
val = gpio_get_value(gb->gpio);
- if (val != gb->previous_state && val != gb->active_low) {
- kfifo_put(gk->recv_fifo, (u_char*)&gb->code, sizeof(int));
- debug("pressed gpio(%d) as %d\n", gb->gpio, gb->code);
+ if (!is_timeout(gb->debounce_start, gb->debounce_interval * MSECOND))
+ continue;
+
+ if (val != gb->previous_state) {
+ gb->debounce_start = get_time_ns();
+ if (val != gb->active_low) {
+ kfifo_put(gk->recv_fifo, (u_char*)&gb->code, sizeof(int));
+ debug("pressed gpio(%d) as %d\n", gb->gpio, gb->code);
+ }
+ gb->previous_state = val;
}
- gb->previous_state = val;
}
}
@@ -111,6 +120,7 @@ static int gpio_keys_probe_pdata(struct gpio_keys *gk, struct device_d *dev)
gk->buttons[i].gpio = pdata->buttons[i].gpio;
gk->buttons[i].code = pdata->buttons[i].code;
gk->buttons[i].active_low = pdata->buttons[i].active_low;
+ gk->buttons[i].debounce_interval = 20;
}
return 0;
@@ -142,6 +152,11 @@ static int gpio_keys_probe_dt(struct gpio_keys *gk, struct device_d *dev)
if (ret)
return ret;
+ gk->buttons[i].debounce_interval = 20;
+
+ of_property_read_u32(npkey, "debounce-interval",
+ &gk->buttons[i].debounce_interval);
+
gk->buttons[i].code = keycode;
i++;
diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig
index ebd8da9..0f3504c 100644
--- a/drivers/mci/Kconfig
+++ b/drivers/mci/Kconfig
@@ -62,9 +62,9 @@ config MCI_S3C
Enable this entry to add support to read and write SD cards on a
Samsung S3C24xx based system.
-config MCI_BCM2835
- bool "MCI support for BCM2835"
- depends on ARCH_BCM2835
+config MCI_BCM283X
+ bool "MCI support for BCM283X"
+ depends on ARCH_BCM283X
config MCI_IMX
bool "i.MX"
diff --git a/drivers/mci/Makefile b/drivers/mci/Makefile
index 1e8443c..88ec456 100644
--- a/drivers/mci/Makefile
+++ b/drivers/mci/Makefile
@@ -1,6 +1,6 @@
obj-$(CONFIG_MCI) += mci-core.o
obj-$(CONFIG_MCI_ATMEL) += atmel_mci.o
-obj-$(CONFIG_MCI_BCM2835) += mci-bcm2835.o
+obj-$(CONFIG_MCI_BCM283X) += mci-bcm2835.o
obj-$(CONFIG_MCI_IMX) += imx.o
obj-$(CONFIG_MCI_IMX_ESDHC) += imx-esdhc.o
obj-$(CONFIG_MCI_MXS) += mxs.o
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index 90475cf..d0a62bd 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -43,3 +43,10 @@ config OF_BAREBOX_DRIVERS
support for this feature. This currently allows to configure the
environment path from devicetree and to partition devices. See
Documentation/devicetree/bindings/barebox/ for more information.
+
+config OF_BAREBOX_ENV_IN_FS
+ depends on OF_BAREBOX_DRIVERS
+ bool "Allow environment to come from file"
+ help
+ Allow the devie tree configuration of the barebox environment path
+ to specify a file in filesystem, which will be mounted.
diff --git a/drivers/of/barebox.c b/drivers/of/barebox.c
index 1b3078e..125feef 100644
--- a/drivers/of/barebox.c
+++ b/drivers/of/barebox.c
@@ -24,7 +24,46 @@
#include <malloc.h>
#include <partition.h>
#include <envfs.h>
-#include <linux/mtd/mtd.h>
+#include <fs.h>
+
+#define ENV_MNT_DIR "/boot" /* If env on filesystem, where to mount */
+
+/* If dev describes a file on a fs, mount the fs and change devpath to
+ * point to the file's path. Otherwise leave devpath alone. Does
+ * nothing in env in a file support isn't enabled. */
+static int environment_check_mount(struct device_d *dev, char **devpath)
+{
+ const char *filepath;
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_OF_BAREBOX_ENV_IN_FS))
+ return 0;
+
+ ret = of_property_read_string(dev->device_node, "file-path", &filepath);
+ if (ret == -EINVAL) {
+ /* No file-path so just use device-path */
+ return 0;
+ } else if (ret) {
+ /* file-path property exists, but has error */
+ dev_err(dev, "Problem with file-path property\n");
+ return ret;
+ }
+
+ /* Get device env is on and mount it */
+ mkdir(ENV_MNT_DIR, 0777);
+ ret = mount(*devpath, "fat", ENV_MNT_DIR, NULL);
+ if (ret) {
+ dev_err(dev, "Failed to load environment: mount %s failed (%d)\n",
+ *devpath, ret);
+ return ret;
+ }
+
+ /* Set env to be in a file on the now mounted device */
+ dev_dbg(dev, "Loading default env from %s on device %s\n",
+ filepath, *devpath);
+ *devpath = asprintf("%s/%s", ENV_MNT_DIR, filepath);
+ return 0;
+}
static int environment_probe(struct device_d *dev)
{
@@ -35,8 +74,12 @@ static int environment_probe(struct device_d *dev)
if (ret)
return ret;
- dev_info(dev, "setting default environment path to %s\n", path);
+ /* Do we need to mount a fs and find env there? */
+ ret = environment_check_mount(dev, &path);
+ if (ret)
+ return ret;
+ dev_dbg(dev, "Setting default environment path to %s\n", path);
default_environment_path_set(path);
return 0;
diff --git a/drivers/of/of_path.c b/drivers/of/of_path.c
index 6903905..ed620f1 100644
--- a/drivers/of/of_path.c
+++ b/drivers/of/of_path.c
@@ -23,16 +23,6 @@
#include <linux/mtd/mtd.h>
-struct of_path {
- struct cdev *cdev;
- struct device_d *dev;
-};
-
-struct of_path_type {
- const char *name;
- int (*parse)(struct of_path *op, const char *str);
-};
-
struct device_d *of_find_device_by_node_path(const char *path)
{
struct device_d *dev;
@@ -48,102 +38,44 @@ struct device_d *of_find_device_by_node_path(const char *path)
}
/**
- * of_path_type_partname - find a partition based on physical device and
- * partition name
- * @op: of_path context
- * @name: the partition name to find
+ * __of_find_path
+ *
+ * @node: The node to find the cdev for, can be the device or a
+ * partition in the device
+ * @part: Optionally, a description of a parition of @node. See of_find_path
+ * @outpath: if this function returns 0 outpath will contain the path belonging
+ * to the input path description. Must be freed with free().
+ * @flags: use OF_FIND_PATH_FLAGS_BB to return the .bb device if available
+ *
*/
-static int of_path_type_partname(struct of_path *op, const char *name)
-{
- if (!op->dev)
- return -EINVAL;
-
- op->cdev = device_find_partition(op->dev, name);
- if (op->cdev) {
- pr_debug("%s: found part '%s'\n", __func__, name);
- return 0;
- } else {
- pr_debug("%s: cannot find part '%s'\n", __func__, name);
- return -ENODEV;
- }
-}
-
-static struct of_path_type of_path_types[] = {
- {
- .name = "partname",
- .parse = of_path_type_partname,
- },
-};
-
-static int of_path_parse_one(struct of_path *op, const char *str)
+static int __of_find_path(struct device_node *node, const char *part, char **outpath, unsigned flags)
{
- int i, ret;
- char *name, *desc;
-
- pr_debug("parsing: %s\n", str);
-
- name = xstrdup(str);
- desc = strchr(name, ':');
- if (!desc) {
- free(name);
- return -EINVAL;
- }
-
- *desc = 0;
- desc++;
-
- for (i = 0; i < ARRAY_SIZE(of_path_types); i++) {
- if (!strcmp(of_path_types[i].name, name)) {
- ret = of_path_types[i].parse(op, desc);
- goto out;
- }
- }
-
- ret = -EINVAL;
-out:
- free(name);
-
- return ret;
-}
-
-static int __of_find_path(struct device_node *node, const char *propname, char **outpath, unsigned flags)
-{
- struct of_path op = {};
- const char *str;
+ struct device_d *dev;
+ struct cdev *cdev;
bool add_bb = false;
- int i, ret;
- op.dev = of_find_device_by_node_path(node->full_name);
- if (!op.dev) {
- op.dev = of_find_device_by_node_path(node->parent->full_name);
- if (!op.dev)
+ dev = of_find_device_by_node_path(node->full_name);
+ if (!dev) {
+ dev = of_find_device_by_node_path(node->parent->full_name);
+ if (!dev)
return -ENODEV;
}
- device_detect(op.dev);
-
- op.cdev = cdev_by_device_node(node);
+ device_detect(dev);
- i = 1;
+ if (part)
+ cdev = device_find_partition(dev, part);
+ else
+ cdev = cdev_by_device_node(node);
- while (propname) {
- ret = of_property_read_string_index(node, propname, i++, &str);
- if (ret)
- break;
-
- ret = of_path_parse_one(&op, str);
- if (ret)
- return ret;
- }
-
- if (!op.cdev)
+ if (!cdev)
return -ENOENT;
- if ((flags & OF_FIND_PATH_FLAGS_BB) && op.cdev->mtd &&
- mtd_can_have_bb(op.cdev->mtd))
+ if ((flags & OF_FIND_PATH_FLAGS_BB) && cdev->mtd &&
+ mtd_can_have_bb(cdev->mtd))
add_bb = true;
- *outpath = asprintf("/dev/%s%s", op.cdev->name, add_bb ? ".bb" : "");
+ *outpath = asprintf("/dev/%s%s", cdev->name, add_bb ? ".bb" : "");
return 0;
}
@@ -193,6 +125,8 @@ int of_find_path(struct device_node *node, const char *propname, char **outpath,
{
struct device_node *rnode;
const char *path;
+ const char *part = NULL;
+ const char partnamestr[] = "partname:";
path = of_get_property(node, propname, NULL);
if (!path)
@@ -202,5 +136,15 @@ int of_find_path(struct device_node *node, const char *propname, char **outpath,
if (!rnode)
return -ENODEV;
- return __of_find_path(rnode, propname, outpath, flags);
+ of_property_read_string_index(node, propname, 1, &part);
+ if (part) {
+ if (!strncmp(part, partnamestr, sizeof(partnamestr) - 1)) {
+ part += sizeof(partnamestr) - 1;
+ } else {
+ pr_err("Invalid device-path: %s\n", part);
+ return -EINVAL;
+ }
+ }
+
+ return __of_find_path(rnode, part, outpath, flags);
}
diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c
index eaa5f0e..d32bd2b 100644
--- a/drivers/pci/pci-imx6.c
+++ b/drivers/pci/pci-imx6.c
@@ -13,6 +13,7 @@
#include <common.h>
#include <clock.h>
+#include <abort.h>
#include <malloc.h>
#include <io.h>
#include <init.h>
@@ -51,6 +52,8 @@ struct imx6_pcie {
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
+#define PCIE_RC_LCSR 0x80
+
/* PCIe Port Logic registers (memory-mapped) */
#define PL_OFFSET 0x700
#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
@@ -235,7 +238,10 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
val = readl(pp->dbi_base + PCIE_PL_PFLR);
val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
val |= PCIE_PL_PFLR_FORCE_LINK;
+
+ data_abort_mask();
writel(val, pp->dbi_base + PCIE_PL_PFLR);
+ data_abort_unmask();
gpr12 &= ~IMX6Q_GPR12_PCIE_CTL_2;
writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
@@ -360,13 +366,29 @@ static int imx6_pcie_wait_for_link(struct pcie_port *pp)
}
}
+static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
+{
+ uint32_t tmp;
+ uint64_t start = get_time_ns();
+
+ while (!is_timeout(start, SECOND)) {
+ tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
+ /* Test if the speed change finished. */
+ if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
+ return 0;
+ }
+
+ dev_err(pp->dev, "Speed change timeout\n");
+ return -EINVAL;
+}
+
+
static int imx6_pcie_start_link(struct pcie_port *pp)
{
struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
uint32_t tmp;
int ret;
u32 gpr12;
- u64 start;
/*
* Force Gen1 operation when starting the link. In case the link is
@@ -401,28 +423,22 @@ static int imx6_pcie_start_link(struct pcie_port *pp)
tmp |= PORT_LOGIC_SPEED_CHANGE;
writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
- start = get_time_ns();
- while (!is_timeout(start, SECOND)) {
- tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
- /* Test if the speed change finished. */
- if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
- break;
+ ret = imx6_pcie_wait_for_speed_change(pp);
+ if (ret) {
+ dev_err(pp->dev, "Failed to bring link up!\n");
+ return ret;
}
/* Make sure link training is finished as well! */
- if (tmp & PORT_LOGIC_SPEED_CHANGE)
- ret = -EINVAL;
- else
- ret = imx6_pcie_wait_for_link(pp);
-
+ ret = imx6_pcie_wait_for_link(pp);
if (ret) {
dev_err(pp->dev, "Failed to bring link up!\n");
- } else {
- tmp = readl(pp->dbi_base + 0x80);
- dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
+ return ret;
}
- return ret;
+ tmp = readl(pp->dbi_base + PCIE_RC_LCSR);
+ dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
+ return 0;
}
static void imx6_pcie_host_init(struct pcie_port *pp)
@@ -592,9 +608,35 @@ static int __init imx6_pcie_probe(struct device_d *dev)
if (ret < 0)
return ret;
+ dev->priv = imx6_pcie;
+
return 0;
}
+static void imx6_pcie_remove(struct device_d *dev)
+{
+ struct imx6_pcie *imx6_pcie = dev->priv;
+ u32 val;
+
+ val = readl(imx6_pcie->pp.dbi_base + PCIE_PL_PFLR);
+ val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
+ val |= PCIE_PL_PFLR_FORCE_LINK;
+ data_abort_mask();
+ writel(val, imx6_pcie->pp.dbi_base + PCIE_PL_PFLR);
+ data_abort_unmask();
+
+ val = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
+ val &= ~IMX6Q_GPR12_PCIE_CTL_2;
+ writel(val, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
+
+ val = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR1);
+ val |= IMX6Q_GPR1_PCIE_TEST_PD;
+ writel(val, imx6_pcie->iomuxc_gpr + IOMUXC_GPR1);
+
+ val &= ~IMX6Q_GPR1_PCIE_REF_CLK_EN;
+ writel(val, imx6_pcie->iomuxc_gpr + IOMUXC_GPR1);
+}
+
static struct of_device_id imx6_pcie_of_match[] = {
{ .compatible = "fsl,imx6q-pcie", },
{},
@@ -604,6 +646,7 @@ static struct driver_d imx6_pcie_driver = {
.name = "imx6-pcie",
.of_compatible = DRV_OF_COMPAT(imx6_pcie_of_match),
.probe = imx6_pcie_probe,
+ .remove = imx6_pcie_remove,
};
device_platform_driver(imx6_pcie_driver);
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 05c3f48..4b41252 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -11,9 +11,9 @@ config REGULATOR_FIXED
This enables a simple fixed regulator. It is used for regulators
which are not software controllable or controllable via gpio.
-config REGULATOR_BCM2835
+config REGULATOR_BCM283X
bool
- depends on ARCH_BCM2835
+ depends on ARCH_BCM283X
default y
endif
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index d663c16..a8dd9bd 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_REGULATOR) += core.o
obj-$(CONFIG_REGULATOR_FIXED) += fixed.o
-obj-$(CONFIG_REGULATOR_BCM2835) += bcm2835.o
+obj-$(CONFIG_REGULATOR_BCM283X) += bcm2835.o
diff --git a/drivers/reset/core.c b/drivers/reset/core.c
index 0f900a9..59f75ca 100644
--- a/drivers/reset/core.c
+++ b/drivers/reset/core.c
@@ -190,6 +190,7 @@ struct reset_control *of_reset_control_get(struct device_node *node,
rstc->rcdev = rcdev;
rstc->id = rstc_id;
+ rstc->gpio = -ENODEV;
return rstc;
}
diff --git a/drivers/usb/imx/chipidea-imx.c b/drivers/usb/imx/chipidea-imx.c
index ae30718..a1c36cf 100644
--- a/drivers/usb/imx/chipidea-imx.c
+++ b/drivers/usb/imx/chipidea-imx.c
@@ -242,7 +242,8 @@ static int imx_chipidea_probe(struct device_d *dev)
ci->vbus = regulator_get(dev, "vbus");
- regulator_enable(ci->vbus);
+ if (!IS_ERR(ci->vbus))
+ regulator_enable(ci->vbus);
base = dev_request_mem_region(dev, 0);
if (IS_ERR(base))
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index eabd246..7ff67e5 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -82,11 +82,11 @@ config DRIVER_VIDEO_PXA
Add support for the frame buffer device found on the PXA270
CPU.
-config DRIVER_VIDEO_BCM2835
- bool "BCM2835 framebuffer driver"
- depends on ARCH_BCM2835
+config DRIVER_VIDEO_BCM283X
+ bool "BCM283X framebuffer driver"
+ depends on ARCH_BCM283X
help
- Add support for the BCM2835/VideoCore frame buffer device.
+ Add support for the BCM283X/VideoCore frame buffer device.
source drivers/video/imx-ipu-v3/Kconfig
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 57e4864..a64fc5f 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -17,6 +17,6 @@ obj-$(CONFIG_DRIVER_VIDEO_S3C24XX) += s3c24xx.o
obj-$(CONFIG_DRIVER_VIDEO_PXA) += pxa.o
obj-$(CONFIG_DRIVER_VIDEO_SDL) += sdl.o
obj-$(CONFIG_DRIVER_VIDEO_OMAP) += omap.o
-obj-$(CONFIG_DRIVER_VIDEO_BCM2835) += bcm2835.o
+obj-$(CONFIG_DRIVER_VIDEO_BCM283X) += bcm2835.o
obj-$(CONFIG_DRIVER_VIDEO_SIMPLEFB) += simplefb.o
obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3) += imx-ipu-v3/
diff --git a/dts/Bindings/arc/archs-pct.txt b/dts/Bindings/arc/archs-pct.txt
new file mode 100644
index 0000000..1ae98b8
--- /dev/null
+++ b/dts/Bindings/arc/archs-pct.txt
@@ -0,0 +1,17 @@
+* ARC HS Performance Counters
+
+The ARC HS can be configured with a pipeline performance monitor for counting
+CPU and cache events like cache misses and hits. Like conventional PCT there
+are 100+ hardware conditions dynamically mapped to upto 32 counters.
+It also supports overflow interrupts.
+
+Required properties:
+
+- compatible : should contain
+ "snps,archs-pct"
+
+Example:
+
+pmu {
+ compatible = "snps,archs-pct";
+};
diff --git a/dts/Bindings/arm/amlogic.txt b/dts/Bindings/arm/amlogic.txt
index 973884a..1dfee20 100644
--- a/dts/Bindings/arm/amlogic.txt
+++ b/dts/Bindings/arm/amlogic.txt
@@ -9,6 +9,12 @@ Boards with the Amlogic Meson8 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson8";
+Boards with the Amlogic Meson8b SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,meson8b";
+
Board compatible values:
- - "geniatech,atv1200"
- - "minix,neo-x8"
+ - "geniatech,atv1200" (Meson6)
+ - "minix,neo-x8" (Meson8)
+ - "tronfy,mxq" (Meson8b)
+ - "hardkernel,odroid-c1" (Meson8b)
diff --git a/dts/Bindings/arm/apm/scu.txt b/dts/Bindings/arm/apm/scu.txt
new file mode 100644
index 0000000..b45be06
--- /dev/null
+++ b/dts/Bindings/arm/apm/scu.txt
@@ -0,0 +1,17 @@
+APM X-GENE SoC series SCU Registers
+
+This system clock unit contain various register that control block resets,
+clock enable/disables, clock divisors and other deepsleep registers.
+
+Properties:
+ - compatible : should contain two values. First value must be:
+ - "apm,xgene-scu"
+ second value must be always "syscon".
+
+ - reg : offset and length of the register set.
+
+Example :
+ scu: system-clk-controller@17000000 {
+ compatible = "apm,xgene-scu","syscon";
+ reg = <0x0 0x17000000 0x0 0x400>;
+ };
diff --git a/dts/Bindings/arm/arm,scpi.txt b/dts/Bindings/arm/arm,scpi.txt
new file mode 100644
index 0000000..86302de
--- /dev/null
+++ b/dts/Bindings/arm/arm,scpi.txt
@@ -0,0 +1,188 @@
+System Control and Power Interface (SCPI) Message Protocol
+----------------------------------------------------------
+
+Firmware implementing the SCPI described in ARM document number ARM DUI 0922B
+("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be used
+by Linux to initiate various system control and power operations.
+
+Required properties:
+
+- compatible : should be "arm,scpi"
+- mboxes: List of phandle and mailbox channel specifiers
+ All the channels reserved by remote SCP firmware for use by
+ SCPI message protocol should be specified in any order
+- shmem : List of phandle pointing to the shared memory(SHM) area between the
+ processors using these mailboxes for IPC, one for each mailbox
+ SHM can be any memory reserved for the purpose of this communication
+ between the processors.
+
+See Documentation/devicetree/bindings/mailbox/mailbox.txt
+for more details about the generic mailbox controller and
+client driver bindings.
+
+Clock bindings for the clocks based on SCPI Message Protocol
+------------------------------------------------------------
+
+This binding uses the common clock binding[1].
+
+Container Node
+==============
+Required properties:
+- compatible : should be "arm,scpi-clocks"
+ All the clocks provided by SCP firmware via SCPI message
+ protocol much be listed as sub-nodes under this node.
+
+Sub-nodes
+=========
+Required properties:
+- compatible : shall include one of the following
+ "arm,scpi-dvfs-clocks" - all the clocks that are variable and index based.
+ These clocks don't provide an entire range of values between the
+ limits but only discrete points within the range. The firmware
+ provides the mapping for each such operating frequency and the
+ index associated with it. The firmware also manages the
+ voltage scaling appropriately with the clock scaling.
+ "arm,scpi-variable-clocks" - all the clocks that are variable and provide full
+ range within the specified range. The firmware provides the
+ range of values within a specified range.
+
+Other required properties for all clocks(all from common clock binding):
+- #clock-cells : Should be 1. Contains the Clock ID value used by SCPI commands.
+- clock-output-names : shall be the corresponding names of the outputs.
+- clock-indices: The identifying number for the clocks(i.e.clock_id) in the
+ node. It can be non linear and hence provide the mapping of identifiers
+ into the clock-output-names array.
+
+SRAM and Shared Memory for SCPI
+-------------------------------
+
+A small area of SRAM is reserved for SCPI communication between application
+processors and SCP.
+
+Required properties:
+- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM on Juno
+
+The rest of the properties should follow the generic mmio-sram description
+found in ../../misc/sysram.txt
+
+Each sub-node represents the reserved area for SCPI.
+
+Required sub-node properties:
+- reg : The base offset and size of the reserved area with the SRAM
+- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
+ shared memory on Juno platforms
+
+Sensor bindings for the sensors based on SCPI Message Protocol
+--------------------------------------------------------------
+SCPI provides an API to access the various sensors on the SoC.
+
+Required properties:
+- compatible : should be "arm,scpi-sensors".
+- #thermal-sensor-cells: should be set to 1. This property follows the
+ thermal device tree bindings[2].
+
+ Valid cell values are raw identifiers (Sensor
+ ID) as used by the firmware. Refer to
+ platform documentation for your
+ implementation for the IDs to use. For Juno
+ R0 and Juno R1 refer to [3].
+
+[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/thermal/thermal.txt
+[3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html
+
+Example:
+
+sram: sram@50000000 {
+ compatible = "arm,juno-sram-ns", "mmio-sram";
+ reg = <0x0 0x50000000 0x0 0x10000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x50000000 0x10000>;
+
+ cpu_scp_lpri: scp-shmem@0 {
+ compatible = "arm,juno-scp-shmem";
+ reg = <0x0 0x200>;
+ };
+
+ cpu_scp_hpri: scp-shmem@200 {
+ compatible = "arm,juno-scp-shmem";
+ reg = <0x200 0x200>;
+ };
+};
+
+mailbox: mailbox0@40000000 {
+ ....
+ #mbox-cells = <1>;
+};
+
+scpi_protocol: scpi@2e000000 {
+ compatible = "arm,scpi";
+ mboxes = <&mailbox 0 &mailbox 1>;
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+ clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_dvfs: scpi_clocks@0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <1>;
+ clock-indices = <0>, <1>, <2>;
+ clock-output-names = "atlclk", "aplclk","gpuclk";
+ };
+ scpi_clk: scpi_clocks@3 {
+ compatible = "arm,scpi-variable-clocks";
+ #clock-cells = <1>;
+ clock-indices = <3>, <4>;
+ clock-output-names = "pxlclk0", "pxlclk1";
+ };
+ };
+
+ scpi_sensors0: sensors {
+ compatible = "arm,scpi-sensors";
+ #thermal-sensor-cells = <1>;
+ };
+};
+
+cpu@0 {
+ ...
+ reg = <0 0>;
+ clocks = <&scpi_dvfs 0>;
+};
+
+hdlcd@7ff60000 {
+ ...
+ reg = <0 0x7ff60000 0 0x1000>;
+ clocks = <&scpi_clk 4>;
+};
+
+thermal-zones {
+ soc_thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <1000>;
+
+ /* sensor ID */
+ thermal-sensors = <&scpi_sensors0 3>;
+ ...
+ };
+};
+
+In the above example, the #clock-cells is set to 1 as required.
+scpi_dvfs has 3 output clocks namely: atlclk, aplclk, and gpuclk with 0,
+1 and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0
+and pxlclk1 with 3 and 4 as clock-indices.
+
+The first consumer in the example is cpu@0 and it has '0' as the clock
+specifier which points to the first entry in the output clocks of
+scpi_dvfs i.e. "atlclk".
+
+Similarly the second example is hdlcd@7ff60000 and it has pxlclk1 as input
+clock. '4' in the clock specifier here points to the second entry
+in the output clocks of scpi_clocks i.e. "pxlclk1"
+
+The thermal-sensors property in the soc_thermal node uses the
+temperature sensor provided by SCP firmware to setup a thermal
+zone. The ID "3" is the sensor identifier for the temperature sensor
+as used by the firmware.
diff --git a/dts/Bindings/arm/atmel-at91.txt b/dts/Bindings/arm/atmel-at91.txt
index 424ac8c..7fd64ec 100644
--- a/dts/Bindings/arm/atmel-at91.txt
+++ b/dts/Bindings/arm/atmel-at91.txt
@@ -27,6 +27,8 @@ compatible: must be one of:
o "atmel,at91sam9xe"
* "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
SoC family:
+ o "atmel,sama5d2" shall be extended with the specific SoC compatible:
+ - "atmel,sama5d27"
o "atmel,sama5d3" shall be extended with the specific SoC compatible:
- "atmel,sama5d31"
- "atmel,sama5d33"
@@ -50,6 +52,7 @@ System Timer (ST) required properties:
- reg: Should contain registers location and length
- interrupts: Should contain interrupt for the ST which is the IRQ line
shared across all System Controller members.
+- clocks: phandle to input clock.
Its subnodes can be:
- watchdog: compatible should be "atmel,at91rm9200-wdt"
@@ -61,7 +64,7 @@ TC/TCLIB Timer required properties:
Note that you can specify several interrupt cells if the TC
block has one interrupt per channel.
- clock-names: tuple listing input clock names.
- Required elements: "t0_clk"
+ Required elements: "t0_clk", "slow_clk"
Optional elements: "t1_clk", "t2_clk"
- clocks: phandles to input clocks.
@@ -87,14 +90,16 @@ One interrupt per TC channel in a TC block:
RSTC Reset Controller required properties:
- compatible: Should be "atmel,<chip>-rstc".
- <chip> can be "at91sam9260" or "at91sam9g45"
+ <chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3"
- reg: Should contain registers location and length
+- clocks: phandle to input clock.
Example:
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
+ clocks = <&clk32k>;
};
RAMC SDRAM/DDR Controller required properties:
@@ -117,6 +122,7 @@ required properties:
- compatible: Should be "atmel,<chip>-shdwc".
<chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
- reg: Should contain registers location and length
+- clocks: phandle to input clock.
optional properties:
- atmel,wakeup-mode: String, operation mode of the wakeup mode.
@@ -135,9 +141,10 @@ optional at91sam9x5 properties:
Example:
- rstc@fffffd00 {
- compatible = "atmel,at91sam9260-rstc";
- reg = <0xfffffd00 0x10>;
+ shdwc@fffffd10 {
+ compatible = "atmel,at91sam9260-shdwc";
+ reg = <0xfffffd10 0x10>;
+ clocks = <&clk32k>;
};
Special Function Registers (SFR)
diff --git a/dts/Bindings/arm/bcm/brcm,brcmstb.txt b/dts/Bindings/arm/bcm/brcm,brcmstb.txt
index 430608e..0d0c1ae 100644
--- a/dts/Bindings/arm/bcm/brcm,brcmstb.txt
+++ b/dts/Bindings/arm/bcm/brcm,brcmstb.txt
@@ -20,6 +20,25 @@ system control is required:
- compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
- compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
+hif-cpubiuctrl node
+-------------------
+SoCs with Broadcom Brahma15 ARM-based CPUs have a specific Bus Interface Unit
+(BIU) block which controls and interfaces the CPU complex to the different
+Memory Controller Ports (MCP), one per memory controller (MEMC). This BIU block
+offers a feature called Write Pairing which consists in collapsing two adjacent
+cache lines into a single (bursted) write transaction towards the memory
+controller (MEMC) to maximize write bandwidth.
+
+Required properties:
+
+ - compatible: must be "brcm,bcm7445-hif-cpubiuctrl", "syscon"
+
+Optional properties:
+
+ - brcm,write-pairing:
+ Boolean property, which when present indicates that the chip
+ supports write-pairing.
+
example:
rdb {
#address-cells = <1>;
@@ -35,6 +54,7 @@ example:
hif_cpubiuctrl: syscon@3e2400 {
compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
reg = <0x3e2400 0x5b4>;
+ brcm,write-pairing;
};
hif_continuation: syscon@452000 {
@@ -43,8 +63,7 @@ example:
};
};
-Lastly, nodes that allow for support of SMP initialization and reboot are
-required:
+Nodes that allow for support of SMP initialization and reboot are required:
smpboot
-------
@@ -95,3 +114,142 @@ example:
compatible = "brcm,brcmstb-reboot";
syscon = <&sun_top_ctrl 0x304 0x308>;
};
+
+
+
+Power management
+----------------
+
+For power management (particularly, S2/S3/S5 system suspend), the following SoC
+components are needed:
+
+= Always-On control block (AON CTRL)
+
+This hardware provides control registers for the "always-on" (even in low-power
+modes) hardware, such as the Power Management State Machine (PMSM).
+
+Required properties:
+- compatible : should contain "brcm,brcmstb-aon-ctrl"
+- reg : the register start and length for the AON CTRL block
+
+Example:
+
+aon-ctrl@410000 {
+ compatible = "brcm,brcmstb-aon-ctrl";
+ reg = <0x410000 0x400>;
+};
+
+= Memory controllers
+
+A Broadcom STB SoC typically has a number of independent memory controllers,
+each of which may have several associated hardware blocks, which are versioned
+independently (control registers, DDR PHYs, etc.). One might consider
+describing these controllers as a parent "memory controllers" block, which
+contains N sub-nodes (one for each controller in the system), each of which is
+associated with a number of hardware register resources (e.g., its PHY). See
+the example device tree snippet below.
+
+== MEMC (MEMory Controller)
+
+Represents a single memory controller instance.
+
+Required properties:
+- compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
+
+Should contain subnodes for any of the following relevant hardware resources:
+
+== DDR PHY control
+
+Control registers for this memory controller's DDR PHY.
+
+Required properties:
+- compatible : should contain one of these
+ "brcm,brcmstb-ddr-phy-v225.1"
+ "brcm,brcmstb-ddr-phy-v240.1"
+ "brcm,brcmstb-ddr-phy-v240.2"
+
+- reg : the DDR PHY register range
+
+== DDR SHIMPHY
+
+Control registers for this memory controller's DDR SHIMPHY.
+
+Required properties:
+- compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
+- reg : the DDR SHIMPHY register range
+
+== MEMC DDR control
+
+Sequencer DRAM parameters and control registers. Used for Self-Refresh
+Power-Down (SRPD), among other things.
+
+Required properties:
+- compatible : should contain "brcm,brcmstb-memc-ddr"
+- reg : the MEMC DDR register range
+
+Example:
+
+memory_controllers {
+ ranges;
+ compatible = "simple-bus";
+
+ memc@0 {
+ compatible = "brcm,brcmstb-memc", "simple-bus";
+ ranges;
+
+ ddr-phy@f1106000 {
+ compatible = "brcm,brcmstb-ddr-phy-v240.1";
+ reg = <0xf1106000 0x21c>;
+ };
+
+ shimphy@f1108000 {
+ compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
+ reg = <0xf1108000 0xe4>;
+ };
+
+ memc-ddr@f1102000 {
+ reg = <0xf1102000 0x800>;
+ compatible = "brcm,brcmstb-memc-ddr";
+ };
+ };
+
+ memc@1 {
+ compatible = "brcm,brcmstb-memc", "simple-bus";
+ ranges;
+
+ ddr-phy@f1186000 {
+ compatible = "brcm,brcmstb-ddr-phy-v240.1";
+ reg = <0xf1186000 0x21c>;
+ };
+
+ shimphy@f1188000 {
+ compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
+ reg = <0xf1188000 0xe4>;
+ };
+
+ memc-ddr@f1182000 {
+ reg = <0xf1182000 0x800>;
+ compatible = "brcm,brcmstb-memc-ddr";
+ };
+ };
+
+ memc@2 {
+ compatible = "brcm,brcmstb-memc", "simple-bus";
+ ranges;
+
+ ddr-phy@f1206000 {
+ compatible = "brcm,brcmstb-ddr-phy-v240.1";
+ reg = <0xf1206000 0x21c>;
+ };
+
+ shimphy@f1208000 {
+ compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
+ reg = <0xf1208000 0xe4>;
+ };
+
+ memc-ddr@f1202000 {
+ reg = <0xf1202000 0x800>;
+ compatible = "brcm,brcmstb-memc-ddr";
+ };
+ };
+};
diff --git a/dts/Bindings/arm/bcm/brcm,nsp.txt b/dts/Bindings/arm/bcm/brcm,nsp.txt
new file mode 100644
index 0000000..eae53e4
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,nsp.txt
@@ -0,0 +1,34 @@
+Broadcom Northstar Plus device tree bindings
+--------------------------------------------
+
+Broadcom Northstar Plus family of SoCs are used for switching control
+and management applications as well as residential router/gateway
+applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
+several peripheral interfaces including multiple Gigabit Ethernet PHYs,
+DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
+SATA and several other IO controllers.
+
+Boards with Northstar Plus SoCs shall have the following properties:
+
+Required root node property:
+
+BCM58522
+compatible = "brcm,bcm58522", "brcm,nsp";
+
+BCM58525
+compatible = "brcm,bcm58525", "brcm,nsp";
+
+BCM58535
+compatible = "brcm,bcm58535", "brcm,nsp";
+
+BCM58622
+compatible = "brcm,bcm58622", "brcm,nsp";
+
+BCM58623
+compatible = "brcm,bcm58623", "brcm,nsp";
+
+BCM58625
+compatible = "brcm,bcm58625", "brcm,nsp";
+
+BCM88312
+compatible = "brcm,bcm88312", "brcm,nsp";
diff --git a/dts/Bindings/arm/bcm/ns2.txt b/dts/Bindings/arm/bcm/ns2.txt
new file mode 100644
index 0000000..35f056f
--- /dev/null
+++ b/dts/Bindings/arm/bcm/ns2.txt
@@ -0,0 +1,9 @@
+Broadcom North Star 2 (NS2) device tree bindings
+------------------------------------------------
+
+Boards with NS2 shall have the following properties:
+
+Required root node property:
+
+NS2 SVK board
+compatible = "brcm,ns2-svk", "brcm,ns2";
diff --git a/dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt b/dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt
new file mode 100644
index 0000000..6824b31
--- /dev/null
+++ b/dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt
@@ -0,0 +1,14 @@
+Raspberry Pi VideoCore firmware driver
+
+Required properties:
+
+- compatible: Should be "raspberrypi,bcm2835-firmware"
+- mboxes: Phandle to the firmware device's Mailbox.
+ (See: ../mailbox/mailbox.txt for more information)
+
+Example:
+
+firmware {
+ compatible = "raspberrypi,bcm2835-firmware";
+ mboxes = <&mailbox>;
+};
diff --git a/dts/Bindings/arm/coherency-fabric.txt b/dts/Bindings/arm/coherency-fabric.txt
index 8dd4661..9b5c3f6 100644
--- a/dts/Bindings/arm/coherency-fabric.txt
+++ b/dts/Bindings/arm/coherency-fabric.txt
@@ -27,6 +27,11 @@ Required properties:
* For "marvell,armada-380-coherency-fabric", only one pair is needed
for the per-CPU fabric registers.
+Optional properties:
+
+- broken-idle: boolean to set when the Idle mode is not supported by the
+ hardware.
+
Examples:
coherency-fabric@d0020200 {
diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt
index 65a6db2..62938eb 100644
--- a/dts/Bindings/arm/coresight.txt
+++ b/dts/Bindings/arm/coresight.txt
@@ -17,6 +17,7 @@ its hardware characteristcs.
- "arm,coresight-tmc", "arm,primecell";
- "arm,coresight-funnel", "arm,primecell";
- "arm,coresight-etm3x", "arm,primecell";
+ - "arm,coresight-etm4x", "arm,primecell";
- "qcom,coresight-replicator1x", "arm,primecell";
* reg: physical base address and length of the register
diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt
index d6b794c..3a07a87 100644
--- a/dts/Bindings/arm/cpus.txt
+++ b/dts/Bindings/arm/cpus.txt
@@ -195,10 +195,13 @@ nodes to be present and contain the properties described below.
"marvell,armada-380-smp"
"marvell,armada-390-smp"
"marvell,armada-xp-smp"
+ "mediatek,mt6589-smp"
+ "mediatek,mt81xx-tz-smp"
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
"rockchip,rk3066-smp"
+ "ste,dbx500-smp"
- cpu-release-addr
Usage: required for systems that have an "enable-method"
diff --git a/dts/Bindings/arm/fsl.txt b/dts/Bindings/arm/fsl.txt
index 2a3ba73..34c88b0 100644
--- a/dts/Bindings/arm/fsl.txt
+++ b/dts/Bindings/arm/fsl.txt
@@ -128,10 +128,18 @@ Example:
reg = <0x0 0x1ee0000 0x0 0x10000>;
};
-Freescale LS2085A SoC Device Tree Bindings
-------------------------------------------
+Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
+----------------------------------------------------------------
-LS2085A ARMv8 based Simulator model
+LS2080A ARMv8 based Simulator model
Required root node properties:
- - compatible = "fsl,ls2085a-simu", "fsl,ls2085a";
+ - compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
+
+LS2080A ARMv8 based QDS Board
+Required root node properties:
+ - compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
+
+LS2080A ARMv8 based RDB Board
+Required root node properties:
+ - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
diff --git a/dts/Bindings/arm/hisilicon/hisilicon.txt b/dts/Bindings/arm/hisilicon/hisilicon.txt
index c431c67..6ac7c00 100644
--- a/dts/Bindings/arm/hisilicon/hisilicon.txt
+++ b/dts/Bindings/arm/hisilicon/hisilicon.txt
@@ -20,6 +20,10 @@ HiKey Board
Required root node properties:
- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
+HiP05 D02 Board
+Required root node properties:
+ - compatible = "hisilicon,hip05-d02";
+
Hisilicon system controller
Required properties:
@@ -127,6 +131,24 @@ Example:
#clock-cells = <1>;
};
+
+Hisilicon Hi6220 SRAM controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-sramctrl", "syscon"
+- reg : Register address and size
+
+Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
+SRAM banks for power management, modem, security, etc. Further, use "syscon"
+managing the common sram which can be shared by multiple modules.
+
+Example:
+ /*for Hi6220*/
+ sram: sram@fff80000 {
+ compatible = "hisilicon,hi6220-sramctrl", "syscon";
+ reg = <0x0 0xfff80000 0x0 0x12000>;
+ };
+
-----------------------------------------------------------------------
Hisilicon HiP01 system controller
@@ -149,6 +171,23 @@ Example:
};
-----------------------------------------------------------------------
+Hisilicon HiP05 PCIe-SAS system controller
+
+Required properties:
+- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
+- reg : Register address and size
+
+The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in
+HiP05 Soc to implement some basic configurations.
+
+Example:
+ /* for HiP05 PCIe-SAS system */
+ pcie_sas: system_controller@0xb0000000 {
+ compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+ reg = <0xb0000000 0x10000>;
+ };
+
+-----------------------------------------------------------------------
Hisilicon CPU controller
Required properties:
diff --git a/dts/Bindings/arm/idle-states.txt b/dts/Bindings/arm/idle-states.txt
index a8274ea..b8e41c1 100644
--- a/dts/Bindings/arm/idle-states.txt
+++ b/dts/Bindings/arm/idle-states.txt
@@ -497,7 +497,7 @@ cpus {
};
idle-states {
- entry-method = "arm,psci";
+ entry-method = "psci";
CPU_RETENTION_0_0: cpu-retention-0-0 {
compatible = "arm,idle-state";
diff --git a/dts/Bindings/arm/keystone/keystone.txt b/dts/Bindings/arm/keystone/keystone.txt
index 59d7a46..3090a8a 100644
--- a/dts/Bindings/arm/keystone/keystone.txt
+++ b/dts/Bindings/arm/keystone/keystone.txt
@@ -9,12 +9,26 @@ Required properties:
the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
type UART should use the specified compatible for those devices.
+SoC families:
+
+- Keystone 2 generic SoC:
+ compatible = "ti,keystone"
+
+SoCs:
+
+- Keystone 2 Hawking/Kepler
+ compatible = "ti,k2hk", "ti,keystone"
+- Keystone 2 Lamarr
+ compatible = "ti,k2l", "ti,keystone"
+- Keystone 2 Edison
+ compatible = "ti,k2e", "ti,keystone"
+
Boards:
- Keystone 2 Hawking/Kepler EVM
- compatible = "ti,k2hk-evm","ti,keystone"
+ compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"
- Keystone 2 Lamarr EVM
- compatible = "ti,k2l-evm","ti,keystone"
+ compatible = "ti,k2l-evm", "ti, k2l", "ti,keystone"
- Keystone 2 Edison EVM
- compatible = "ti,k2e-evm","ti,keystone"
+ compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"
diff --git a/dts/Bindings/arm/l2cc.txt b/dts/Bindings/arm/l2cc.txt
index 2251dcc..06c88a4 100644
--- a/dts/Bindings/arm/l2cc.txt
+++ b/dts/Bindings/arm/l2cc.txt
@@ -67,6 +67,12 @@ Optional properties:
disable if zero.
- arm,prefetch-offset : Override prefetch offset value. Valid values are
0-7, 15, 23, and 31.
+- arm,shared-override : The default behavior of the pl310 cache controller with
+ respect to the shareable attribute is to transform "normal memory
+ non-cacheable transactions" into "cacheable no allocate" (for reads) or
+ "write through no write allocate" (for writes).
+ On systems where this may cause DMA buffer corruption, this property must be
+ specified to indicate that such transforms are precluded.
- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>
(forcibly enable), property absent (retain settings set by firmware)
- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
diff --git a/dts/Bindings/arm/marvell,kirkwood.txt b/dts/Bindings/arm/marvell,kirkwood.txt
index 4f40ff3..5171ad8 100644
--- a/dts/Bindings/arm/marvell,kirkwood.txt
+++ b/dts/Bindings/arm/marvell,kirkwood.txt
@@ -20,6 +20,8 @@ And in addition, the compatible shall be extended with the specific
board. Currently known boards are:
"buffalo,lschlv2"
+"buffalo,lswvl"
+"buffalo,lswxl"
"buffalo,lsxhl"
"buffalo,lsxl"
"dlink,dns-320"
diff --git a/dts/Bindings/arm/mediatek.txt b/dts/Bindings/arm/mediatek.txt
index dd7550a..618a919 100644
--- a/dts/Bindings/arm/mediatek.txt
+++ b/dts/Bindings/arm/mediatek.txt
@@ -1,12 +1,15 @@
-MediaTek mt65xx & mt81xx Platforms Device Tree Bindings
+MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings
-Boards with a MediaTek mt65xx/mt81xx SoC shall have the following property:
+Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the
+following property:
Required root node property:
compatible: Must contain one of
+ "mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
+ "mediatek,mt6795"
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
@@ -14,12 +17,18 @@ compatible: Must contain one of
Supported boards:
+- Evaluation board for MT6580:
+ Required root node properties:
+ - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
- bq Aquaris5 smart phone:
Required root node properties:
- compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";
- Evaluation board for MT6592:
Required root node properties:
- compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
+- Evaluation board for MT6795(Helio X10):
+ Required root node properties:
+ - compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
- MTK mt8127 tablet moose EVB:
Required root node properties:
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
diff --git a/dts/Bindings/arm/mediatek/mediatek,imgsys.txt b/dts/Bindings/arm/mediatek/mediatek,imgsys.txt
new file mode 100644
index 0000000..b1f2ce1
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,imgsys.txt
@@ -0,0 +1,22 @@
+Mediatek imgsys controller
+============================
+
+The Mediatek imgsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt8173-imgsys", "syscon"
+- #clock-cells: Must be 1
+
+The imgsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+imgsys: clock-controller@15000000 {
+ compatible = "mediatek,mt8173-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/dts/Bindings/arm/mediatek/mediatek,mmsys.txt b/dts/Bindings/arm/mediatek/mediatek,mmsys.txt
new file mode 100644
index 0000000..4385946
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,mmsys.txt
@@ -0,0 +1,22 @@
+Mediatek mmsys controller
+============================
+
+The Mediatek mmsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt8173-mmsys", "syscon"
+- #clock-cells: Must be 1
+
+The mmsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+mmsys: clock-controller@14000000 {
+ compatible = "mediatek,mt8173-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt b/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt
new file mode 100644
index 0000000..1faacf1
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt
@@ -0,0 +1,22 @@
+Mediatek vdecsys controller
+============================
+
+The Mediatek vdecsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt8173-vdecsys", "syscon"
+- #clock-cells: Must be 1
+
+The vdecsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+vdecsys: clock-controller@16000000 {
+ compatible = "mediatek,mt8173-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/dts/Bindings/arm/mediatek/mediatek,vencltsys.txt b/dts/Bindings/arm/mediatek/mediatek,vencltsys.txt
new file mode 100644
index 0000000..3cc299f
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,vencltsys.txt
@@ -0,0 +1,22 @@
+Mediatek vencltsys controller
+============================
+
+The Mediatek vencltsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt8173-vencltsys", "syscon"
+- #clock-cells: Must be 1
+
+The vencltsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+vencltsys: clock-controller@19000000 {
+ compatible = "mediatek,mt8173-vencltsys", "syscon";
+ reg = <0 0x19000000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/dts/Bindings/arm/mediatek/mediatek,vencsys.txt b/dts/Bindings/arm/mediatek/mediatek,vencsys.txt
new file mode 100644
index 0000000..5bb2866a
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,vencsys.txt
@@ -0,0 +1,22 @@
+Mediatek vencsys controller
+============================
+
+The Mediatek vencsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt8173-vencsys", "syscon"
+- #clock-cells: Must be 1
+
+The vencsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+vencsys: clock-controller@18000000 {
+ compatible = "mediatek,mt8173-vencsys", "syscon";
+ reg = <0 0x18000000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/dts/Bindings/arm/mvebu-cpu-config.txt b/dts/Bindings/arm/mvebu-cpu-config.txt
new file mode 100644
index 0000000..2cdcd71
--- /dev/null
+++ b/dts/Bindings/arm/mvebu-cpu-config.txt
@@ -0,0 +1,20 @@
+MVEBU CPU Config registers
+--------------------------
+
+MVEBU (Marvell SOCs: Armada 370/XP)
+
+Required properties:
+
+- compatible: one of:
+ - "marvell,armada-370-cpu-config"
+ - "marvell,armada-xp-cpu-config"
+
+- reg: Should contain CPU config registers location and length, in
+ their per-CPU variant
+
+Example:
+
+ cpu-config@21000 {
+ compatible = "marvell,armada-xp-cpu-config";
+ reg = <0x21000 0x8>;
+ };
diff --git a/dts/Bindings/arm/omap/omap.txt b/dts/Bindings/arm/omap/omap.txt
index 4f6a82c..9f4e513 100644
--- a/dts/Bindings/arm/omap/omap.txt
+++ b/dts/Bindings/arm/omap/omap.txt
@@ -135,6 +135,9 @@ Boards:
- AM335X OrionLXm : Substation Automation Platform
compatible = "novatech,am335x-lxm", "ti,am33xx"
+- AM335X phyBOARD-WEGA: Single Board Computer dev kit
+ compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"
+
- OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5"
diff --git a/dts/Bindings/arm/pmu.txt b/dts/Bindings/arm/pmu.txt
index 3b5f5d1..97ba45a 100644
--- a/dts/Bindings/arm/pmu.txt
+++ b/dts/Bindings/arm/pmu.txt
@@ -7,7 +7,10 @@ representation in the device tree should be done as under:-
Required properties:
- compatible : should be one of
+ "apm,potenza-pmu"
"arm,armv8-pmuv3"
+ "arm.cortex-a57-pmu"
+ "arm.cortex-a53-pmu"
"arm,cortex-a17-pmu"
"arm,cortex-a15-pmu"
"arm,cortex-a12-pmu"
@@ -26,13 +29,19 @@ Required properties:
Optional properties:
-- interrupt-affinity : Valid only when using SPIs, specifies a list of phandles
- to CPU nodes corresponding directly to the affinity of
+- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
+ nodes corresponding directly to the affinity of
the SPIs listed in the interrupts property.
- This property should be present when there is more than
+ When using a PPI, specifies a list of phandles to CPU
+ nodes corresponding to the set of CPUs which have
+ a PMU of this type signalling the PPI listed in the
+ interrupts property.
+
+ This property should be present when there is more than
a single SPI.
+
- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
events.
diff --git a/dts/Bindings/arm/psci.txt b/dts/Bindings/arm/psci.txt
index 5aa40ed..a9adab8 100644
--- a/dts/Bindings/arm/psci.txt
+++ b/dts/Bindings/arm/psci.txt
@@ -31,6 +31,10 @@ Main node required properties:
support, but are permitted to be present for compatibility with
existing software when "arm,psci" is later in the compatible list.
+ * "arm,psci-1.0" : for implementations complying to PSCI 1.0. PSCI 1.0 is
+ backward compatible with PSCI 0.2 with minor specification updates,
+ as defined in the PSCI specification[2].
+
- method : The method of calling the PSCI firmware. Permitted
values are:
@@ -100,3 +104,5 @@ Case 3: PSCI v0.2 and PSCI v0.1.
[1] Kernel documentation - ARM idle states bindings
Documentation/devicetree/bindings/arm/idle-states.txt
+[2] Power State Coordination Interface (PSCI) specification
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
diff --git a/dts/Bindings/arm/rockchip.txt b/dts/Bindings/arm/rockchip.txt
index 60d4a1e..8e985dd 100644
--- a/dts/Bindings/arm/rockchip.txt
+++ b/dts/Bindings/arm/rockchip.txt
@@ -17,6 +17,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "radxa,rock", "rockchip,rk3188";
+- Radxa Rock2 Square board:
+ Required root node properties:
+ - compatible = "radxa,rock2-square", "rockchip,rk3288";
+
- Firefly Firefly-RK3288 board:
Required root node properties:
- compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
@@ -26,3 +30,45 @@ Rockchip platforms device tree bindings
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
+
+- Netxeon R89 board:
+ Required root node properties:
+ - compatible = "netxeon,r89", "rockchip,rk3288";
+
+- Google Jaq (Haier Chromebook 11 and more):
+ Required root node properties:
+ - compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
+ "google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
+ "google,veyron-jaq-rev1", "google,veyron-jaq",
+ "google,veyron", "rockchip,rk3288";
+
+- Google Jerry (Hisense Chromebook C11 and more):
+ Required root node properties:
+ - compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
+ "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
+ "google,veyron-jerry-rev3", "google,veyron-jerry",
+ "google,veyron", "rockchip,rk3288";
+
+- Google Minnie (Asus Chromebook Flip C100P):
+ Required root node properties:
+ - compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
+ "google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
+ "google,veyron-minnie-rev0", "google,veyron-minnie",
+ "google,veyron", "rockchip,rk3288";
+
+- Google Pinky (dev-board):
+ Required root node properties:
+ - compatible = "google,veyron-pinky-rev2", "google,veyron-pinky",
+ "google,veyron", "rockchip,rk3288";
+
+- Google Speedy (Asus C201 Chromebook):
+ Required root node properties:
+ - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
+ "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
+ "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
+ "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
+ "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
+
+- Rockchip R88 board:
+ Required root node properties:
+ - compatible = "rockchip,r88", "rockchip,rk3368";
diff --git a/dts/Bindings/arm/samsung-boards.txt b/dts/Bindings/arm/samsung-boards.txt
deleted file mode 100644
index 43589d2..0000000
--- a/dts/Bindings/arm/samsung-boards.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* Samsung's Exynos SoC based boards
-
-Required root node properties:
- - compatible = should be one or more of the following.
- - "samsung,monk" - for Exynos3250-based Samsung Simband board.
- - "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
- - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
- - "samsung,trats" - for Exynos4210-based Tizen Reference board.
- - "samsung,universal_c210" - for Exynos4210-based Samsung board.
- - "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board.
- - "samsung,trats2" - for Exynos4412-based Tizen Reference board.
- - "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board.
- - "samsung,xyref5260" - for Exynos5260-based Samsung board.
- - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
- - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
- - "samsung,sd5v1" - for Exynos5440-based Samsung board.
- - "samsung,ssdk5440" - for Exynos5440-based Samsung board.
-
-Optional:
- - firmware node, specifying presence and type of secure firmware:
- - compatible: only "samsung,secure-firmware" is currently supported
- - reg: address of non-secure SYSRAM used for communication with firmware
-
- firmware@0203F000 {
- compatible = "samsung,secure-firmware";
- reg = <0x0203F000 0x1000>;
- };
diff --git a/dts/Bindings/arm/samsung/samsung-boards.txt b/dts/Bindings/arm/samsung/samsung-boards.txt
new file mode 100644
index 0000000..12129c0
--- /dev/null
+++ b/dts/Bindings/arm/samsung/samsung-boards.txt
@@ -0,0 +1,69 @@
+* Samsung's Exynos SoC based boards
+
+Required root node properties:
+ - compatible = should be one or more of the following.
+ - "samsung,monk" - for Exynos3250-based Samsung Simband board.
+ - "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
+ - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
+ - "samsung,trats" - for Exynos4210-based Tizen Reference board.
+ - "samsung,universal_c210" - for Exynos4210-based Samsung board.
+ - "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board.
+ - "samsung,trats2" - for Exynos4412-based Tizen Reference board.
+ - "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board.
+ - "samsung,xyref5260" - for Exynos5260-based Samsung board.
+ - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
+ - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
+ - "samsung,sd5v1" - for Exynos5440-based Samsung board.
+ - "samsung,ssdk5440" - for Exynos5440-based Samsung board.
+
+* Other companies Exynos SoC based
+ * FriendlyARM
+ - "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM
+ TINY4412 board.
+
+ * Google
+ - "google,pi" - for Exynos5800-based Google Peach Pi
+ Rev 10+ board,
+ also: "google,pi-rev16", "google,pi-rev15", "google,pi-rev14",
+ "google,pi-rev13", "google,pi-rev12", "google,pi-rev11",
+ "google,pi-rev10", "google,peach".
+
+ - "google,pit" - for Exynos5420-based Google Peach Pit
+ Rev 6+ (Exynos5420),
+ also: "google,pit-rev16", "google,pit-rev15", "google,pit-rev14",
+ "google,pit-rev13", "google,pit-rev12", "google,pit-rev11",
+ "google,pit-rev10", "google,pit-rev9", "google,pit-rev8",
+ "google,pit-rev7", "google,pit-rev6", "google,peach".
+
+ - "google,snow-rev4" - for Exynos5250-based Google Snow board,
+ also: "google,snow"
+ - "google,snow-rev5" - for Exynos5250-based Google Snow
+ Rev 5+ board.
+ - "google,spring" - for Exynos5250-based Google Spring board.
+
+ * Hardkernel
+ - "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3.
+ - "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X.
+ - "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2.
+ - "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
+ - "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
+ Odroid XU3 Lite board.
+ - "hardkernel,odroid-xu4" - for Exynos5422-based Hardkernel Odroid XU4.
+
+ * Insignal
+ - "insignal,arndale" - for Exynos5250-based Insignal Arndale board.
+ - "insignal,arndale-octa" - for Exynos5420-based Insignal Arndale
+ Octa board.
+ - "insignal,origen" - for Exynos4210-based Insignal Origen board.
+ - "insignal,origen4412 - for Exynos4412-based Insignal Origen board.
+
+
+Optional nodes:
+ - firmware node, specifying presence and type of secure firmware:
+ - compatible: only "samsung,secure-firmware" is currently supported
+ - reg: address of non-secure SYSRAM used for communication with firmware
+
+ firmware@0203F000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x0203F000 0x1000>;
+ };
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
index c4f19b2..40bb900 100644
--- a/dts/Bindings/arm/shmobile.txt
+++ b/dts/Bindings/arm/shmobile.txt
@@ -39,8 +39,6 @@ Boards:
compatible = "renesas,armadillo800eva"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
- - BOCK-W - Reference Device Tree Implementation
- compatible = "renesas,bockw-reference", "renesas,r8a7778"
- Genmai (RTK772100BC00000BR)
compatible = "renesas,genmai", "renesas,r7s72100"
- Gose
@@ -57,7 +55,7 @@ Boards:
compatible = "renesas,lager", "renesas,r8a7790"
- Marzen
compatible = "renesas,marzen", "renesas,r8a7779"
-
-Note: Reference Device Tree Implementations are temporary implementations
- to ease the migration from platform devices to Device Tree, and are
- intended to be removed in the future.
+ - Porter (M2-LCDP)
+ compatible = "renesas,porter", "renesas,r8a7791"
+ - SILK (RTP0RC7794LCB00011S)
+ compatible = "renesas,silk", "renesas,r8a7794"
diff --git a/dts/Bindings/arm/sp810.txt b/dts/Bindings/arm/sp810.txt
new file mode 100644
index 0000000..6808fb5
--- /dev/null
+++ b/dts/Bindings/arm/sp810.txt
@@ -0,0 +1,46 @@
+SP810 System Controller
+-----------------------
+
+Required properties:
+
+- compatible: standard compatible string for a Primecell peripheral,
+ see Documentation/devicetree/bindings/arm/primecell.txt
+ for more details
+ should be: "arm,sp810", "arm,primecell"
+
+- reg: standard registers property, physical address and size
+ of the control registers
+
+- clock-names: from the common clock bindings, for more details see
+ Documentation/devicetree/bindings/clock/clock-bindings.txt;
+ should be: "refclk", "timclk", "apb_pclk"
+
+- clocks: from the common clock bindings, phandle and clock
+ specifier pairs for the entries of clock-names property
+
+- #clock-cells: from the common clock bindings;
+ should be: <1>
+
+- clock-output-names: from the common clock bindings;
+ should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3"
+
+- assigned-clocks: from the common clock binding;
+ should be: clock specifier for each output clock of this
+ provider node
+
+- assigned-clock-parents: from the common clock binding;
+ should be: phandle of input clock listed in clocks
+ property with the highest frequency
+
+Example:
+ v2m_sysctl: sysctl@020000 {
+ compatible = "arm,sp810", "arm,primecell";
+ reg = <0x020000 0x1000>;
+ clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
+ clock-names = "refclk", "timclk", "apb_pclk";
+ #clock-cells = <1>;
+ clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
+ assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
+ assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
+
+ };
diff --git a/dts/Bindings/arm/sunxi.txt b/dts/Bindings/arm/sunxi.txt
index 42941fd..bb9b0fa 100644
--- a/dts/Bindings/arm/sunxi.txt
+++ b/dts/Bindings/arm/sunxi.txt
@@ -6,7 +6,10 @@ using one of the following compatible strings:
allwinner,sun4i-a10
allwinner,sun5i-a10s
allwinner,sun5i-a13
+ allwinner,sun5i-r8
allwinner,sun6i-a31
allwinner,sun7i-a20
allwinner,sun8i-a23
+ allwinner,sun8i-a33
+ allwinner,sun8i-h3
allwinner,sun9i-a80
diff --git a/dts/Bindings/nvec/nvidia,nvec.txt b/dts/Bindings/arm/tegra/nvidia,nvec.txt
index 5ae601e..5ae601e 100644
--- a/dts/Bindings/nvec/nvidia,nvec.txt
+++ b/dts/Bindings/arm/tegra/nvidia,nvec.txt
diff --git a/dts/Bindings/arm/twd.txt b/dts/Bindings/arm/twd.txt
index 75b8610..383ea19 100644
--- a/dts/Bindings/arm/twd.txt
+++ b/dts/Bindings/arm/twd.txt
@@ -19,6 +19,11 @@ interrupts.
- reg : Specify the base address and the size of the TWD timer
register window.
+Optional
+
+- always-on : a boolean property. If present, the timer is powered through
+ an always-on power domain, therefore it never loses context.
+
Example:
twd-timer@2c000600 {
diff --git a/dts/Bindings/arm/uniphier/cache-uniphier.txt b/dts/Bindings/arm/uniphier/cache-uniphier.txt
new file mode 100644
index 0000000..d27a646
--- /dev/null
+++ b/dts/Bindings/arm/uniphier/cache-uniphier.txt
@@ -0,0 +1,60 @@
+UniPhier outer cache controller
+
+UniPhier SoCs are integrated with a full-custom outer cache controller system.
+All of them have a level 2 cache controller, and some have a level 3 cache
+controller as well.
+
+Required properties:
+- compatible: should be "socionext,uniphier-system-cache"
+- reg: offsets and lengths of the register sets for the device. It should
+ contain 3 regions: control register, revision register, operation register,
+ in this order.
+- cache-unified: specifies the cache is a unified cache.
+- cache-size: specifies the size in bytes of the cache
+- cache-sets: specifies the number of associativity sets of the cache
+- cache-line-size: specifies the line size in bytes
+- cache-level: specifies the level in the cache hierarchy. The value should
+ be 2 for L2 cache, 3 for L3 cache, etc.
+
+Optional properties:
+- next-level-cache: phandle to the next level cache if present. The next level
+ cache should be also compatible with "socionext,uniphier-system-cache".
+
+The L2 cache must exist to use the L3 cache; the cache hierarchy must be
+indicated correctly with "next-level-cache" properties.
+
+Example 1 (system with L2):
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+ <0x506c0000 0x400>;
+ cache-unified;
+ cache-size = <0x80000>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+
+Example 2 (system with L2 and L3):
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
+ <0x506c0000 0x400>;
+ cache-unified;
+ cache-size = <0x200000>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ next-level-cache = <&l3>;
+ };
+
+ l3: l3-cache@500c8000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
+ <0x506c8000 0x400>;
+ cache-unified;
+ cache-size = <0x400000>;
+ cache-sets = <512>;
+ cache-line-size = <256>;
+ cache-level = <3>;
+ };
diff --git a/dts/Bindings/ata/ahci-fsl-qoriq.txt b/dts/Bindings/ata/ahci-fsl-qoriq.txt
new file mode 100644
index 0000000..032a760
--- /dev/null
+++ b/dts/Bindings/ata/ahci-fsl-qoriq.txt
@@ -0,0 +1,21 @@
+Binding for Freescale QorIQ AHCI SATA Controller
+
+Required properties:
+ - reg: Physical base address and size of the controller's register area.
+ - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
+ chip could be ls1021a, ls2080a, ls1043a etc.
+ - clocks: Input clock specifier. Refer to common clock bindings.
+ - interrupts: Interrupt specifier. Refer to interrupt binding.
+
+Optional properties:
+ - dma-coherent: Enable AHCI coherent DMA operation.
+ - reg-names: register area names when there are more than 1 register area.
+
+Examples:
+ sata@3200000 {
+ compatible = "fsl,ls1021a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ dma-coherent;
+ };
diff --git a/dts/Bindings/ata/ahci-platform.txt b/dts/Bindings/ata/ahci-platform.txt
index a232181..c2340ee 100644
--- a/dts/Bindings/ata/ahci-platform.txt
+++ b/dts/Bindings/ata/ahci-platform.txt
@@ -16,8 +16,6 @@ Required properties:
- "snps,dwc-ahci"
- "snps,exynos5440-ahci"
- "snps,spear-ahci"
- - "fsl,qoriq-ahci" : for qoriq series socs which include ls1021, ls2085, etc.
- - "fsl,<chip>-ahci" : chip could be ls1021, ls2085 etc.
- "generic-ahci"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
diff --git a/dts/Bindings/powerpc/fsl/board.txt b/dts/Bindings/board/fsl-board.txt
index cff38bd..fb7b03e 100644
--- a/dts/Bindings/powerpc/fsl/board.txt
+++ b/dts/Bindings/board/fsl-board.txt
@@ -21,11 +21,14 @@ Example:
This is the memory-mapped registers for on board FPGA.
-Required properities:
+Required properties:
- compatible: should be a board-specific string followed by a string
indicating the type of FPGA. Example:
- "fsl,<board>-fpga", "fsl,fpga-pixis"
+ "fsl,<board>-fpga", "fsl,fpga-pixis", or
+ "fsl,<board>-fpga", "fsl,fpga-qixis"
- reg: should contain the address and the length of the FPGA register set.
+
+Optional properties:
- interrupt-parent: should specify phandle for the interrupt controller.
- interrupts: should specify event (wakeup) IRQ.
@@ -38,6 +41,13 @@ Example (P1022DS):
interrupts = <8 8 0 0>;
};
+Example (LS2080A-RDB):
+
+ cpld@3,0 {
+ compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
+ reg = <0x3 0 0x10000>;
+ };
+
* Freescale BCSR GPIO banks
Some BCSR registers act as simple GPIO controllers, each such
diff --git a/dts/Bindings/bus/sunxi-rsb.txt b/dts/Bindings/bus/sunxi-rsb.txt
new file mode 100644
index 0000000..3dd2834
--- /dev/null
+++ b/dts/Bindings/bus/sunxi-rsb.txt
@@ -0,0 +1,47 @@
+Allwinner Reduced Serial Bus (RSB) controller
+
+The RSB controller found on later Allwinner SoCs is an SMBus like 2 wire
+serial bus with 1 master and up to 15 slaves. It is represented by a node
+for the controller itself, and child nodes representing the slave devices.
+
+Required properties :
+
+ - reg : Offset and length of the register set for the controller.
+ - compatible : Shall be "allwinner,sun8i-a23-rsb".
+ - interrupts : The interrupt line associated to the RSB controller.
+ - clocks : The gate clk associated to the RSB controller.
+ - resets : The reset line associated to the RSB controller.
+ - #address-cells : shall be 1
+ - #size-cells : shall be 0
+
+Optional properties :
+
+ - clock-frequency : Desired RSB bus clock frequency in Hz. Maximum is 20MHz.
+ If not set this defaults to 3MHz.
+
+Child nodes:
+
+An RSB controller node can contain zero or more child nodes representing
+slave devices on the bus. Child 'reg' properties should contain the slave
+device's hardware address. The hardware address is hardwired in the device,
+which can normally be found in the datasheet.
+
+Example:
+
+ rsb@01f03400 {
+ compatible = "allwinner,sun8i-a23-rsb";
+ reg = <0x01f03400 0x400>;
+ interrupts = <0 39 4>;
+ clocks = <&apb0_gates 3>;
+ clock-frequency = <3000000>;
+ resets = <&apb0_rst 3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic@3e3 {
+ compatible = "...";
+ reg = <0x3e3>;
+
+ /* ... */
+ };
+ };
diff --git a/dts/Bindings/chosen.txt b/dts/Bindings/chosen.txt
index ed838f4..6ae9d82 100644
--- a/dts/Bindings/chosen.txt
+++ b/dts/Bindings/chosen.txt
@@ -44,3 +44,11 @@ Implementation note: Linux will look for the property "linux,stdout-path" or
on PowerPC "stdout" if "stdout-path" is not found. However, the
"linux,stdout-path" and "stdout" properties are deprecated. New platforms
should only use the "stdout-path" property.
+
+linux,booted-from-kexec
+-----------------------
+
+This property is set (currently only on PowerPC, and only needed on
+book3e) by some versions of kexec-tools to tell the new kernel that it
+is being booted by kexec, as the booting environment may differ (e.g.
+a different secondary CPU release mechanism)
diff --git a/dts/Bindings/clock/at91-clock.txt b/dts/Bindings/clock/at91-clock.txt
index 5ba6450..181bc8a 100644
--- a/dts/Bindings/clock/at91-clock.txt
+++ b/dts/Bindings/clock/at91-clock.txt
@@ -77,6 +77,9 @@ Required properties:
"atmel,sama5d4-clk-h32mx":
at91 h32mx clock
+ "atmel,sama5d2-clk-generated":
+ at91 generated clock
+
Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
@@ -461,3 +464,35 @@ For example:
compatible = "atmel,sama5d4-clk-h32mx";
clocks = <&mck>;
};
+
+Required properties for generated clocks:
+- #size-cells : shall be 0 (reg is used to encode clk id).
+- #address-cells : shall be 1 (reg is used to encode clk id).
+- clocks : shall be the generated clock source phandles.
+ e.g. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
+- name: device tree node describing a specific generated clock.
+ * #clock-cells : from common clock binding; shall be set to 0.
+ * reg: peripheral id. See Atmel's datasheets to get a full
+ list of peripheral ids.
+ * atmel,clk-output-range : minimum and maximum clock frequency
+ (two u32 fields).
+
+For example:
+ gck {
+ compatible = "atmel,sama5d2-clk-generated";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
+
+ tcb0_gclk: tcb0_gclk {
+ #clock-cells = <0>;
+ reg = <35>;
+ atmel,clk-output-range = <0 83000000>;
+ };
+
+ pwm_gclk: pwm_gclk {
+ #clock-cells = <0>;
+ reg = <38>;
+ atmel,clk-output-range = <0 83000000>;
+ };
+ };
diff --git a/dts/Bindings/clock/brcm,bcm2835-cprman.txt b/dts/Bindings/clock/brcm,bcm2835-cprman.txt
new file mode 100644
index 0000000..e56a1df
--- /dev/null
+++ b/dts/Bindings/clock/brcm,bcm2835-cprman.txt
@@ -0,0 +1,45 @@
+Broadcom BCM2835 CPRMAN clocks
+
+This binding uses the common clock binding:
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The CPRMAN clock controller generates clocks in the audio power domain
+of the BCM2835. There is a level of PLLs deriving from an external
+oscillator, a level of PLL dividers that produce channels off of the
+few PLLs, and a level of mostly-generic clock generators sourcing from
+the PLL channels. Most other hardware components source from the
+clock generators, but a few (like the ARM or HDMI) will source from
+the PLL dividers directly.
+
+Required properties:
+- compatible: Should be "brcm,bcm2835-cprman"
+- #clock-cells: Should be <1>. The permitted clock-specifier values can be
+ found in include/dt-bindings/clock/bcm2835.h
+- reg: Specifies base physical address and size of the registers
+- clocks: The external oscillator clock phandle
+
+Example:
+
+ clk_osc: clock@3 {
+ compatible = "fixed-clock";
+ reg = <3>;
+ #clock-cells = <0>;
+ clock-output-names = "osc";
+ clock-frequency = <19200000>;
+ };
+
+ clocks: cprman@7e101000 {
+ compatible = "brcm,bcm2835-cprman";
+ #clock-cells = <1>;
+ reg = <0x7e101000 0x2000>;
+ clocks = <&clk_osc>;
+ };
+
+ i2c0: i2c@7e205000 {
+ compatible = "brcm,bcm2835-i2c";
+ reg = <0x7e205000 0x1000>;
+ interrupts = <2 21>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/dts/Bindings/clock/brcm,iproc-clocks.txt b/dts/Bindings/clock/brcm,iproc-clocks.txt
index da8d9bb..ede65a5 100644
--- a/dts/Bindings/clock/brcm,iproc-clocks.txt
+++ b/dts/Bindings/clock/brcm,iproc-clocks.txt
@@ -130,3 +130,81 @@ These clock IDs are defined in:
ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
+
+Northstar and Northstar Plus
+------
+PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
+ "brcm,nsp-armpll"
+ "brcm,nsp-genpll"
+ "brcm,nsp-lcpll0"
+
+The following table defines the set of PLL/clock index and ID for Northstar and
+Northstar Plus. These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-nsp.h"
+
+ Clock Source Index ID
+ --- ----- ----- ---------
+ crystal N/A N/A N/A
+
+ armpll crystal N/A N/A
+
+ genpll crystal 0 BCM_NSP_GENPLL
+ phy genpll 1 BCM_NSP_GENPLL_PHY_CLK
+ ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
+ usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK
+ iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK
+ sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK
+ sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK
+
+ lcpll0 crystal 0 BCM_NSP_LCPLL0
+ pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
+ sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
+ ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
+
+Northstar 2
+-----------
+PLL and leaf clock compatible strings for Northstar 2 are:
+ "brcm,ns2-genpll-scr"
+ "brcm,ns2-genpll-sw"
+ "brcm,ns2-lcpll-ddr"
+ "brcm,ns2-lcpll-ports"
+
+The following table defines the set of PLL/clock index and ID for Northstar 2.
+These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-ns2.h"
+
+ Clock Source Index ID
+ --- ----- ----- ---------
+ crystal N/A N/A N/A
+
+ genpll_scr crystal 0 BCM_NS2_GENPLL_SCR
+ scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK
+ fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK
+ audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK
+ ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED
+ ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED
+ ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED
+
+ genpll_sw crystal 0 BCM_NS2_GENPLL_SW
+ rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK
+ 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
+ nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK
+ chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK
+ port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK
+ sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK
+
+ lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR
+ pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
+ ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK
+ ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED
+ ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED
+ ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED
+ ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED
+
+ lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS
+ wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK
+ rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK
+ ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED
+ ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
+ ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
+ ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
diff --git a/dts/Bindings/clock/gpio-mux-clock.txt b/dts/Bindings/clock/gpio-mux-clock.txt
new file mode 100644
index 0000000..2be1e03
--- /dev/null
+++ b/dts/Bindings/clock/gpio-mux-clock.txt
@@ -0,0 +1,19 @@
+Binding for simple gpio clock multiplexer.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "gpio-mux-clock".
+- clocks: list of two references to parent clocks.
+- #clock-cells : from common clock binding; shall be set to 0.
+- select-gpios : GPIO reference for selecting the parent clock.
+
+Example:
+ clock {
+ compatible = "gpio-mux-clock";
+ clocks = <&parentclk1>, <&parentclk2>;
+ #clock-cells = <0>;
+ select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/dts/Bindings/clock/hi6220-clock.txt b/dts/Bindings/clock/hi6220-clock.txt
index 259e30a..e4d5fea 100644
--- a/dts/Bindings/clock/hi6220-clock.txt
+++ b/dts/Bindings/clock/hi6220-clock.txt
@@ -15,19 +15,36 @@ Required Properties:
- "hisilicon,hi6220-sysctrl"
- "hisilicon,hi6220-mediactrl"
- "hisilicon,hi6220-pmctrl"
+ - "hisilicon,hi6220-stub-clk"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
-For example:
+Optional Properties:
+
+- hisilicon,hi6220-clk-sram: phandle to the syscon managing the SoC internal sram;
+ the driver need use the sram to pass parameters for frequency change.
+
+- mboxes: use the label reference for the mailbox as the first parameter, the
+ second parameter is the channel number.
+
+Example 1:
sys_ctrl: sys_ctrl@f7030000 {
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf7030000 0x0 0x2000>;
#clock-cells = <1>;
};
+Example 2:
+ stub_clock: stub_clock {
+ compatible = "hisilicon,hi6220-stub-clk";
+ hisilicon,hi6220-clk-sram = <&sram>;
+ #clock-cells = <1>;
+ mboxes = <&mailbox 1>;
+ };
+
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
diff --git a/dts/Bindings/clock/imx6ul-clock.txt b/dts/Bindings/clock/imx6ul-clock.txt
new file mode 100644
index 0000000..571d503
--- /dev/null
+++ b/dts/Bindings/clock/imx6ul-clock.txt
@@ -0,0 +1,13 @@
+* Clock bindings for Freescale i.MX6 UltraLite
+
+Required properties:
+- compatible: Should be "fsl,imx6ul-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+- clocks: list of clock specifiers, must contain an entry for each required
+ entry in clock-names
+- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6ul-clock.h
+for the full list of i.MX6 UltraLite clock IDs.
diff --git a/dts/Bindings/clock/mt8173-cpu-dvfs.txt b/dts/Bindings/clock/mt8173-cpu-dvfs.txt
new file mode 100644
index 0000000..52b457c
--- /dev/null
+++ b/dts/Bindings/clock/mt8173-cpu-dvfs.txt
@@ -0,0 +1,83 @@
+Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
+
+Required properties:
+- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
+- clock-names: Should contain the following:
+ "cpu" - The multiplexer for clock input of CPU cluster.
+ "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
+ source (usually MAINPLL) when the original CPU PLL is under
+ transition and not stable yet.
+ Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
+ generic clock consumer properties.
+- proc-supply: Regulator for Vproc of CPU cluster.
+
+Optional properties:
+- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
+ needs to do "voltage tracking" to step by step scale up/down Vproc and
+ Vsram to fit SoC specific needs. When absent, the voltage scaling
+ flow is handled by hardware, hence no software "voltage tracking" is
+ needed.
+
+Example:
+--------
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ };
+
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ };
+
+ &cpu0 {
+ proc-supply = <&mt6397_vpca15_reg>;
+ };
+
+ &cpu1 {
+ proc-supply = <&mt6397_vpca15_reg>;
+ };
+
+ &cpu2 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+ };
+
+ &cpu3 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+ };
diff --git a/dts/Bindings/clock/nvidia,tegra124-dfll.txt b/dts/Bindings/clock/nvidia,tegra124-dfll.txt
new file mode 100644
index 0000000..ee7e5fd
--- /dev/null
+++ b/dts/Bindings/clock/nvidia,tegra124-dfll.txt
@@ -0,0 +1,79 @@
+NVIDIA Tegra124 DFLL FCPU clocksource
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The DFLL IP block on Tegra is a root clocksource designed for clocking
+the fast CPU cluster. It consists of a free-running voltage controlled
+oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
+control module that will automatically adjust the VDD_CPU voltage by
+communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
+Currently only the I2C mode is supported by these bindings.
+
+Required properties:
+- compatible : should be "nvidia,tegra124-dfll"
+- reg : Defines the following set of registers, in the order listed:
+ - registers for the DFLL control logic.
+ - registers for the I2C output logic.
+ - registers for the integrated I2C master controller.
+ - look-up table RAM for voltage register values.
+- interrupts: Should contain the DFLL block interrupt.
+- clocks: Must contain an entry for each entry in clock-names.
+ See clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - soc: Clock source for the DFLL control logic.
+ - ref: The closed loop reference clock
+ - i2c: Clock source for the integrated I2C master.
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+ - dvco: Reset control for the DFLL DVCO.
+- #clock-cells: Must be 0.
+- clock-output-names: Name of the clock output.
+- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL
+ hardware will start controlling. The regulator will be queried for
+ the I2C register, control values and supported voltages.
+
+Required properties for the control loop parameters:
+- nvidia,sample-rate: Sample rate of the DFLL control loop.
+- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
+- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
+- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
+- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
+- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.
+
+Optional properties for the control loop parameters:
+- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
+
+Required properties for I2C mode:
+- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
+
+Example:
+
+clock@0,70110000 {
+ compatible = "nvidia,tegra124-dfll";
+ reg = <0 0x70110000 0 0x100>, /* DFLL control */
+ <0 0x70110000 0 0x100>, /* I2C output control */
+ <0 0x70110100 0 0x100>, /* Integrated I2C controller */
+ <0 0x70110200 0 0x100>; /* Look-up table RAM */
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
+ <&tegra_car TEGRA124_CLK_DFLL_REF>,
+ <&tegra_car TEGRA124_CLK_I2C5>;
+ clock-names = "soc", "ref", "i2c";
+ resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
+ reset-names = "dvco";
+ #clock-cells = <0>;
+ clock-output-names = "dfllCPU_out";
+ vdd-cpu-supply = <&vdd_cpu>;
+ status = "okay";
+
+ nvidia,sample-rate = <12500>;
+ nvidia,droop-ctrl = <0x00000f00>;
+ nvidia,force-mode = <1>;
+ nvidia,cf = <10>;
+ nvidia,ci = <0>;
+ nvidia,cg = <2>;
+
+ nvidia,i2c-fs-rate = <400000>;
+};
diff --git a/dts/Bindings/clock/qcom,gcc.txt b/dts/Bindings/clock/qcom,gcc.txt
index 54c23f3..152dfaa 100644
--- a/dts/Bindings/clock/qcom,gcc.txt
+++ b/dts/Bindings/clock/qcom,gcc.txt
@@ -18,10 +18,14 @@ Required properties :
- #clock-cells : shall contain 1
- #reset-cells : shall contain 1
+Optional properties :
+- #power-domain-cells : shall contain 1
+
Example:
clock-controller@900000 {
compatible = "qcom,gcc-msm8960";
reg = <0x900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
};
diff --git a/dts/Bindings/clock/qcom,mmcc.txt b/dts/Bindings/clock/qcom,mmcc.txt
index 29ebf84..34e7614 100644
--- a/dts/Bindings/clock/qcom,mmcc.txt
+++ b/dts/Bindings/clock/qcom,mmcc.txt
@@ -14,10 +14,14 @@ Required properties :
- #clock-cells : shall contain 1
- #reset-cells : shall contain 1
+Optional properties :
+- #power-domain-cells : shall contain 1
+
Example:
clock-controller@4000000 {
compatible = "qcom,mmcc-msm8960";
reg = <0x4000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
};
diff --git a/dts/Bindings/clock/qoriq-clock.txt b/dts/Bindings/clock/qoriq-clock.txt
index df4a259..16a3ec4 100644
--- a/dts/Bindings/clock/qoriq-clock.txt
+++ b/dts/Bindings/clock/qoriq-clock.txt
@@ -1,6 +1,6 @@
* Clock Block on Freescale QorIQ Platforms
-Freescale qoriq chips take primary clocking input from the external
+Freescale QorIQ chips take primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
@@ -13,14 +13,16 @@ which the chip complies.
Chassis Version Example Chips
--------------- -------------
1.0 p4080, p5020, p5040
-2.0 t4240, b4860, t1040
+2.0 t4240, b4860
1. Clock Block Binding
Required properties:
-- compatible: Should contain a specific clock block compatible string
- and a single chassis clock compatible string.
- Clock block strings include, but not limited to, one of the:
+- compatible: Should contain a chip-specific clock block compatible
+ string and (if applicable) may contain a chassis-version clock
+ compatible string.
+
+ Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
* "fsl,p2041-clockgen"
* "fsl,p3041-clockgen"
* "fsl,p4080-clockgen"
@@ -30,15 +32,14 @@ Required properties:
* "fsl,b4420-clockgen"
* "fsl,b4860-clockgen"
* "fsl,ls1021a-clockgen"
- Chassis clock strings include:
+ Chassis-version clock strings include:
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
- reg: Describes the address of the device's resources within the
address space defined by its parent bus, and resource zero
represents the clock register set
-- clock-frequency: Input system clock frequency
-Recommended properties:
+Optional properties:
- ranges: Allows valid translation between child's address space and
parent's. Must be present if the device has sub-nodes.
- #address-cells: Specifies the number of cells used to represent
@@ -47,8 +48,46 @@ Recommended properties:
- #size-cells: Specifies the number of cells used to represent
the size of an address. Must be present if the device has
sub-nodes and set to 1 if present
+- clock-frequency: Input system clock frequency (SYSCLK)
+- clocks: If clock-frequency is not specified, sysclk may be provided
+ as an input clock. Either clock-frequency or clocks must be
+ provided.
+
+2. Clock Provider
+
+The clockgen node should act as a clock provider, though in older device
+trees the children of the clockgen node are the clock providers.
+
+When the clockgen node is a clock provider, #clock-cells = <2>.
+The first cell of the clock specifier is the clock type, and the
+second cell is the clock index for the specified type.
+
+ Type# Name Index Cell
+ 0 sysclk must be 0
+ 1 cmux index (n in CLKCnCSR)
+ 2 hwaccel index (n in CLKCGnHWACSR)
+ 3 fman 0 for fm1, 1 for fm2
+ 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+
+3. Example
+
+ clockgen: global-utilities@e1000 {
+ compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+ clock-frequency = <133333333>;
+ reg = <0xe1000 0x1000>;
+ #clock-cells = <2>;
+ };
+
+ fman@400000 {
+ ...
+ clocks = <&clockgen 3 0>;
+ ...
+ };
+}
+4. Legacy Child Nodes
-2. Clock Provider/Consumer Binding
+NOTE: These nodes are deprecated. Kernels should continue to support
+device trees with these nodes, but new device trees should not use them.
Most of the bindings are from the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -82,7 +121,7 @@ Recommended properties:
- reg: Should be the offset and length of clock block base address.
The length should be 4.
-Example for clock block and clock provider:
+Legacy Example:
/ {
clockgen: global-utilities@e1000 {
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
@@ -142,7 +181,7 @@ Example for clock block and clock provider:
};
};
-Example for clock consumer:
+Example for legacy clock consumer:
/ {
cpu0: PowerPC,e5500@0 {
diff --git a/dts/Bindings/clock/renesas,cpg-div6-clocks.txt b/dts/Bindings/clock/renesas,cpg-div6-clocks.txt
index 5ddb684..38dcf03 100644
--- a/dts/Bindings/clock/renesas,cpg-div6-clocks.txt
+++ b/dts/Bindings/clock/renesas,cpg-div6-clocks.txt
@@ -1,7 +1,7 @@
* Renesas CPG DIV6 Clock
The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
-Generator (CPG). They clock input is divided by a configurable factor from 1
+Generator (CPG). Their clock input is divided by a configurable factor from 1
to 64.
Required Properties:
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.txt b/dts/Bindings/clock/renesas,cpg-mssr.txt
new file mode 100644
index 0000000..59297d3
--- /dev/null
+++ b/dts/Bindings/clock/renesas,cpg-mssr.txt
@@ -0,0 +1,69 @@
+* Renesas Clock Pulse Generator / Module Standby and Software Reset
+
+On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
+and MSSR (Module Standby and Software Reset) blocks are intimately connected,
+and share the same register block.
+
+They provide the following functionalities:
+ - The CPG block generates various core clocks,
+ - The MSSR block provides two functions:
+ 1. Module Standby, providing a Clock Domain to control the clock supply
+ to individual SoC devices,
+ 2. Reset Control, to perform a software reset of individual SoC devices.
+
+Required Properties:
+ - compatible: Must be one of:
+ - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC
+
+ - reg: Base address and length of the memory resource used by the CPG/MSSR
+ block
+
+ - clocks: References to external parent clocks, one entry for each entry in
+ clock-names
+ - clock-names: List of external parent clock names. Valid names are:
+ - "extal" (r8a7795)
+ - "extalr" (r8a7795)
+
+ - #clock-cells: Must be 2
+ - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
+ and a core clock reference, as defined in
+ <dt-bindings/clock/*-cpg-mssr.h>.
+ - For module clocks, the two clock specifier cells must be "CPG_MOD" and
+ a module number, as defined in the datasheet.
+
+ - #power-domain-cells: Must be 0
+ - SoC devices that are part of the CPG/MSSR Clock Domain and can be
+ power-managed through Module Standby should refer to the CPG device
+ node in their "power-domains" property, as documented by the generic PM
+ Domain bindings in
+ Documentation/devicetree/bindings/power/power_domain.txt.
+
+
+Examples
+--------
+
+ - CPG device node:
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7795-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&extalr_clk>;
+ clock-names = "extal", "extalr";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSSR Clock Domain member device node:
+
+ scif2: serial@e6e88000 {
+ compatible = "renesas,scif-r8a7795", "renesas,scif";
+ reg = <0 0xe6e88000 0 64>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 310>;
+ clock-names = "sci_ick";
+ dmas = <&dmac1 0x13>, <&dmac1 0x12>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
diff --git a/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt b/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
index 2f3747f..e4cdaf1 100644
--- a/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
+++ b/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
@@ -1,7 +1,9 @@
* Renesas R8A7778 Clo