diff options
144 files changed, 2156 insertions, 583 deletions
diff --git a/Documentation/devel/project-ideas.rst b/Documentation/devel/project-ideas.rst index f27e4d5406..a3643298ab 100644 --- a/Documentation/devel/project-ideas.rst +++ b/Documentation/devel/project-ideas.rst @@ -13,16 +13,26 @@ If you find a project interesting and would like to work on it, reach out to the :ref:`mailing list <feedback>` and we can together try to figure out whether you are a good match for the project. +For GSoC, following barebox developers are mentoring: + + - Ahmad Fatoum (IRC: ``a3f``) + - Sascha Hauer (IRC: ``_sha_``) + - Rouven Czerwinski (IRC: ``Emantor``) + This list can be edited and extended by sending patches to the mailing list. Other interesting ideas: Support for new file systems (EROFS, extfat, btrfs). Switch device framework (currently scripts write into a ``/dev/switch`` file to configure passthrough), Improvements for barebox-efi (e.g. as a coreboot payload), ... etc. +Ideas listed below should contain a title, description, expected outcomes, +skills (and HW if any) required and a difficulty rating. +Projects are meant to be about 175 hours of effort, unless otherwise noted. + Address static analyzer feedback for barebox ============================================ -Skills: C +Skills: C. Difficulty: Lowest barebox is automatically tested using Synopsys' free "Coverity Scan" service. The static analyzer has so far identified 191 possible defects at @@ -36,13 +46,15 @@ To make this service more useful, the project would involve categorizing reported issues and handling them as appropriate: Mark them as not applicable if false positive or provide patches to fix real issues. +Expected outcome is that barebox is coverity-clean. + This project does not require dedicated hardware. QEMU or barebox built to run under Linux (sandbox) may be used. Update barebox networking stack for IPv6 support ================================================ -Skills: C, Networking +Skills: C, Networking. Difficulty: Medium The barebox network stack is mainly used for TFTP and NFSv3 (over UDP) boot. Most embedded systems barebox runs on aren't deployed to IPv6 networks yet, @@ -55,13 +67,15 @@ makes it possible to integrate an IPv6 stack, e.g. lwIP. There are also community patches to integrate a TCP stack into barebox. These can be evaluated as time allows. +Expected outcome is that barebox can TFTP/NFS boot over IPv6. + This project does not require dedicated hardware. QEMU or barebox built to run under Linux (sandbox) may be used. Improving barebox test coverage =============================== -Skills: C +Skills: C. Difficulty: Lowest barebox is normally tested end-to-end as part of a deployed system. More selftests/emulated tests would reduce the round trip time for testing @@ -78,13 +92,16 @@ tests for barebox functionality and by fuzzing the parsers available in barebox, with special consideration to the FIT parser, which is used in secure booting setups. +Expected outcome is a richer test suite for barebox and an automated +setup for fuzzing security-critical parsers. + This project does not require dedicated hardware. QEMU or barebox built to run under Linux (sandbox) may be used. Porting barebox to new hardware =============================== -Skills: C, low-level affinity +Skills: C, low-level affinity. Difficulty: Medium While Linux and Linux userspace can be quite generic with respect to the hardware it runs on, the bucket needs to stop somewhere: barebox needs @@ -102,6 +119,9 @@ If time allows (because most drivers are already available in barebox), new drivers can be ported to enable not only running Linux on the board, but bareDOOM as well. +Expected outcome is upstreamed barebox drivers and board support to +enable running on previously unsupported hardware. + This project requires embedded hardware with preferably an ARM SoC, as these have the widest barebox support, but other architectures are ok as well. @@ -109,7 +129,7 @@ as well. Improve barebox RISC-V support ============================== -Skills: C, RISC-V interest, low-level affinity +Skills: C, RISC-V interest, low-level affinity. Difficulty: Medium barebox supports a number of both soft and hardRISC-V targets, e.g.: BeagleV, HiFive, LiteX and the QEMU/TinyEMU Virt machine. @@ -121,12 +141,16 @@ stage, so much opportunity in implementing the gritty details: - MMU support in S-Mode to trap access violations - Improve barebox support for multiple harts (hardware threads) +Expected outcome is better RISC-V support: Access violations are +trapped in both S- and M-Mode. Virtual memory is implemented and +Linux can be booted on multiple harts. + This project does not require dedicated hardware. QEMU can be used. Improve barebox I/O performance =============================== -Skills: C, low-level affinity +Skills: C, low-level affinity. Difficulty: Medium On a normal modern system, booting may involve mounting and traversing a file system, which employs caching for directory entries and sits @@ -145,13 +169,15 @@ possible to increase throughput of barebox I/O: and write performance. This may not be optimal for all devices and can be revisited. +Expected outcome is faster read/write/erasure of MMC block devices. + This project requires embedded hardware with SD/eMMC that is supported by a barebox media card interface (MCI) driver. Improve JSBarebox, the barebox web demo ======================================= -Skills: C (Basics), Javascript/Web-assembly, Browser-Profiling +Skills: C (Basics), Javascript/Web-assembly, Browser-Profiling. Difficulty: Medium While Linux and Linux userspace can be quite generic with respect to the hardware it runs on, the bucket needs to stop somewhere: barebox needs @@ -170,5 +196,9 @@ provided with modern browsers. The remainder of the project can then focus on improving the jsbarebox tutorial. e.g. by adding new peripherals to the virtual machine. +Expected outcome is snappier and less CPU-intensive barebox demo. +TinyEMU is extended, so the RISC-V machine is more like real +hardware and tutorial is extended to make use of the new pripherals. + This project does not require dedicated hardware. The development machine need only support a recent browser. @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 2022 -PATCHLEVEL = 02 +PATCHLEVEL = 03 SUBLEVEL = 0 EXTRAVERSION = NAME = None diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c index 09437b047f..dfc26cd835 100644 --- a/arch/arm/boards/ccxmx51/ccxmx51.c +++ b/arch/arm/boards/ccxmx51/ccxmx51.c @@ -174,7 +174,7 @@ static void ccxmx51_power_init(struct mc13xxx *mc13xxx) static void ccxmx51_disable_device(struct device_node *root, const char *label) { - struct device_node *np = of_find_node_by_name(root, label); + struct device_node *np = of_find_node_by_name_address(root, label); if (np) of_device_disable(np); } diff --git a/arch/arm/boards/gateworks-ventana/board.c b/arch/arm/boards/gateworks-ventana/board.c index 163f8338c6..c4c6960192 100644 --- a/arch/arm/boards/gateworks-ventana/board.c +++ b/arch/arm/boards/gateworks-ventana/board.c @@ -19,9 +19,9 @@ static int gw54xx_wdog_of_fixup(struct device_node *root, void *context) struct device_node *np; /* switch to the watchdog with internal reset capabilities */ - np = of_find_node_by_name(root, "wdog@020c0000"); + np = of_find_node_by_name_address(root, "wdog@020c0000"); of_device_disable(np); - np = of_find_node_by_name(root, "wdog@020bc000"); + np = of_find_node_by_name_address(root, "wdog@020bc000"); of_device_enable(np); return 0; diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c index 1e515a093a..c540aaeb3f 100644 --- a/arch/arm/boards/phytec-som-imx6/board.c +++ b/arch/arm/boards/phytec-som-imx6/board.c @@ -107,7 +107,7 @@ static int phycore_da9062_setup_buck_mode(void) unsigned char value; int ret; - pmic_np = of_find_node_by_name(NULL, "pmic@58"); + pmic_np = of_find_node_by_name_address(NULL, "pmic@58"); if (!pmic_np) return -ENODEV; diff --git a/arch/arm/boards/protonic-imx6/board.c b/arch/arm/boards/protonic-imx6/board.c index 9b2a00c6c3..adde1be8d9 100644 --- a/arch/arm/boards/protonic-imx6/board.c +++ b/arch/arm/boards/protonic-imx6/board.c @@ -736,7 +736,7 @@ static int prt_imx6_get_id(struct prt_imx6_priv *priv) struct device_node *gpio_np = NULL; int ret; - gpio_np = of_find_node_by_name(NULL, "gpio@20a0000"); + gpio_np = of_find_node_by_name_address(NULL, "gpio@20a0000"); if (!gpio_np) return -ENODEV; diff --git a/arch/arm/boards/skov-imx6/board.c b/arch/arm/boards/skov-imx6/board.c index cd7b8e208d..2702bc1de9 100644 --- a/arch/arm/boards/skov-imx6/board.c +++ b/arch/arm/boards/skov-imx6/board.c @@ -496,7 +496,7 @@ static void skov_init_board(const struct board_description *variant) char *environment_path, *envdev; int ret; - gpio_np = of_find_node_by_name(NULL, "gpio@20b4000"); + gpio_np = of_find_node_by_name_address(NULL, "gpio@20b4000"); if (gpio_np) { ret = of_device_ensure_probed(gpio_np); if (ret) @@ -568,7 +568,7 @@ static void skov_init_board(const struct board_description *variant) pr_err("Cannot find \"fsl,imx6q-ldb\" node\n"); /* ... as well as its channel 0 */ - np = of_find_node_by_name(np, "lvds-channel@0"); + np = of_find_node_by_name_address(np, "lvds-channel@0"); if (np) of_device_enable(np); else diff --git a/arch/arm/boards/zii-common/pn-fixup.c b/arch/arm/boards/zii-common/pn-fixup.c index 80785285b7..3c69f1a022 100644 --- a/arch/arm/boards/zii-common/pn-fixup.c +++ b/arch/arm/boards/zii-common/pn-fixup.c @@ -11,7 +11,7 @@ char *zii_read_part_number(const char *cell_name, size_t cell_size) { struct device_node *np; - np = of_find_node_by_name(NULL, "device-info"); + np = of_find_node_by_name_address(NULL, "device-info"); if (!np) { pr_warn("No device information found\n"); return ERR_PTR(-ENOENT); diff --git a/arch/arm/boards/zii-imx51-rdu1/board.c b/arch/arm/boards/zii-imx51-rdu1/board.c index 8fdcb76260..42c99ecc1e 100644 --- a/arch/arm/boards/zii-imx51-rdu1/board.c +++ b/arch/arm/boards/zii-imx51-rdu1/board.c @@ -99,7 +99,7 @@ static int zii_rdu1_load_config(void) file = "shadow copy in RAVE SP EEPROM"; root = of_get_root_node(); - np = of_find_node_by_name(root, "eeprom@a4"); + np = of_find_node_by_name_address(root, "eeprom@a4"); if (!np) return -ENODEV; diff --git a/arch/arm/boards/zii-imx6q-rdu2/board.c b/arch/arm/boards/zii-imx6q-rdu2/board.c index b915a05dd2..f57827cd13 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/board.c +++ b/arch/arm/boards/zii-imx6q-rdu2/board.c @@ -199,19 +199,19 @@ static int rdu2_fixup_dsa(struct device_node *root, void *context) if (!switch_np) return -ENODEV; - np = of_find_node_by_name(switch_np, "port@2"); + np = of_find_node_by_name_address(switch_np, "port@2"); if (!np) return -ENODEV; of_delete_node(np); - np = of_find_node_by_name(root, "i210@0"); + np = of_find_node_by_name_address(root, "i210@0"); if (!np) return -ENODEV; i210_handle = of_node_create_phandle(np); - np = of_find_node_by_name(switch_np, "port@0"); + np = of_find_node_by_name_address(switch_np, "port@0"); if (!np) return -ENODEV; @@ -265,7 +265,7 @@ static int rdu2_fixup_lvds(struct device_node *root, /* * LVDS panels need the correct timings */ - np = of_find_node_by_name(root, "panel"); + np = of_find_node_by_name_address(root, "panel"); if (!np) return -ENODEV; @@ -280,7 +280,7 @@ static int rdu2_fixup_lvds(struct device_node *root, * Delete all mode entries, which aren't suited for the * current display */ - np = of_find_node_by_name(np, "display-timings"); + np = of_find_node_by_name_address(np, "display-timings"); if (!np) return -ENODEV; @@ -305,7 +305,7 @@ static int rdu2_fixup_lvds(struct device_node *root, if (fixup->type == IT_DUAL_LVDS) of_set_property(np, "fsl,dual-channel", NULL, 0, 1); - np = of_find_node_by_name(np, "lvds-channel@0"); + np = of_find_node_by_name_address(np, "lvds-channel@0"); if (!np) return -ENODEV; diff --git a/arch/arm/boards/zii-imx8mq-dev/board.c b/arch/arm/boards/zii-imx8mq-dev/board.c index 4ad09663ac..02e257f35f 100644 --- a/arch/arm/boards/zii-imx8mq-dev/board.c +++ b/arch/arm/boards/zii-imx8mq-dev/board.c @@ -106,7 +106,7 @@ static int zii_imx8mq_dev_fixup_deb_internal(void) unregister_device(dev); - np = of_find_node_by_name(NULL, "i210@0"); + np = of_find_node_by_name_address(NULL, "i210@0"); if (!np) return -ENODEV; diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig index b28c868a99..fe6398cc87 100644 --- a/arch/arm/configs/imx_v8_defconfig +++ b/arch/arm/configs/imx_v8_defconfig @@ -99,6 +99,7 @@ CONFIG_NET_USB=y CONFIG_NET_USB_ASIX=y CONFIG_NET_USB_SMSC95XX=y CONFIG_DRIVER_SPI_IMX=y +CONFIG_SPI_NXP_FLEXSPI=y CONFIG_I2C=y CONFIG_I2C_IMX=y CONFIG_MTD=y diff --git a/arch/arm/dts/imx8mn-evk.dts b/arch/arm/dts/imx8mn-evk.dts index 9fe24b3184..b8e7e1acf5 100644 --- a/arch/arm/dts/imx8mn-evk.dts +++ b/arch/arm/dts/imx8mn-evk.dts @@ -60,3 +60,33 @@ &ocotp { barebox,provide-mac-address = <&fec1 0x640>; }; + +&iomuxc { + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; +}; + +&flexspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + + system_flash: flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index e56da3cb76..d3dbfff423 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -320,6 +320,7 @@ static int vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) #define DDRC_MSTR_LPDDR4 BIT(5) #define DDRC_MSTR_DATA_BUS_WIDTH GENMASK(13, 12) #define DDRC_MSTR_ACTIVE_RANKS GENMASK(27, 24) +#define DDRC_MSTR_DEVICE_CONFIG GENMASK(31, 30) #define DDRC_ADDRMAP0_CS_BIT1 GENMASK(12, 8) @@ -346,13 +347,19 @@ static int vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) #define DDRC_ADDRMAP7_ROW_B17 GENMASK(11, 8) #define DDRC_ADDRMAP7_ROW_B16 GENMASK( 3, 0) +#define DDRC_ADDRMAP8_BG_B1 GENMASK(13, 8) +#define DDRC_ADDRMAP8_BG_B0 GENMASK(4, 0) + static unsigned int imx_ddrc_count_bits(unsigned int bits, const u8 config[], unsigned int config_num) { unsigned int i; - for (i = 0; i < config_num && config[i] == 0b1111; i++) - bits--; + + for (i = 0; i < config_num; i++) { + if (config[i] == 0b1111) + bits--; + } return bits; } @@ -361,7 +368,7 @@ static resource_size_t imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[], u8 col_max, const u8 col_b[], unsigned int col_b_num, u8 row_max, const u8 row_b[], unsigned int row_b_num, - bool reduced_adress_space) + bool reduced_adress_space, bool is_imx8) { const u32 mstr = readl(ddrc + DDRC_MSTR); unsigned int banks, ranks, columns, rows, active_ranks, width; @@ -384,15 +391,20 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[], BUG(); } + /* Bus width in bytes, 0 means half byte or 4-bit mode */ + if (is_imx8) + width = (1 << FIELD_GET(DDRC_MSTR_DEVICE_CONFIG, mstr)) >> 1; + else + width = 4; + switch (FIELD_GET(DDRC_MSTR_DATA_BUS_WIDTH, mstr)) { case 0b00: /* Full DQ bus */ - width = 4; break; - case 0b01: /* Half DQ bus */ - width = 2; + case 0b01: /* Half DQ bus */ + width >>= 1; break; case 0b10: /* Quarter DQ bus */ - width = 1; + width >>= 2; break; default: BUG(); @@ -409,10 +421,25 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[], if (FIELD_GET(DDRC_ADDRMAP1_BANK_B2, addrmap[1]) != 0b11111) banks++; + if (addrmap[8]) { + if (FIELD_GET(DDRC_ADDRMAP8_BG_B0, addrmap[8]) != 0b11111) + banks++; + if (FIELD_GET(DDRC_ADDRMAP8_BG_B1, addrmap[8]) != 0b111111) + banks++; + } + columns = imx_ddrc_count_bits(col_max, col_b, col_b_num); rows = imx_ddrc_count_bits(row_max, row_b, row_b_num); - size = memory_sdram_size(columns, rows, 1 << banks, width) << ranks; + /* + * Special case when bus width is 0 or x4 mode, + * calculate the mem size and then divide the size by 2. + */ + if (width) + size = memory_sdram_size(columns, rows, 1 << banks, width); + else + size = memory_sdram_size(columns, rows, 1 << banks, 1) >> 1; + size <<= ranks; return reduced_adress_space ? size * 3 / 4 : size; } @@ -427,7 +454,8 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc) readl(ddrc + DDRC_ADDRMAP(4)), readl(ddrc + DDRC_ADDRMAP(5)), readl(ddrc + DDRC_ADDRMAP(6)), - readl(ddrc + DDRC_ADDRMAP(7)) + readl(ddrc + DDRC_ADDRMAP(7)), + readl(ddrc + DDRC_ADDRMAP(8)) }; const u8 col_b[] = { /* @@ -445,15 +473,8 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc) FIELD_GET(DDRC_ADDRMAP2_COL_B4, addrmap[2]), }; const u8 row_b[] = { - /* - * FIXME: RM mentions the following fields as being - * present, but looking at the code generated by DDR - * tool it doesn't look like those registers are - * really implemented/used. - * - * FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]), - * FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]), - */ + FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]), + FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]), FIELD_GET(DDRC_ADDRMAP6_ROW_B15, addrmap[6]), FIELD_GET(DDRC_ADDRMAP6_ROW_B14, addrmap[6]), FIELD_GET(DDRC_ADDRMAP6_ROW_B13, addrmap[6]), @@ -466,7 +487,7 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc) return imx_ddrc_sdram_size(ddrc, addrmap, 12, ARRAY_AND_SIZE(col_b), 16, ARRAY_AND_SIZE(row_b), - reduced_adress_space); + reduced_adress_space, true); } static int imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) @@ -508,7 +529,7 @@ static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc) return imx_ddrc_sdram_size(ddrc, addrmap, 11, ARRAY_AND_SIZE(col_b), 15, ARRAY_AND_SIZE(row_b), - reduced_adress_space); + reduced_adress_space, false); } static int imx7d_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index 3ee42fd966..697a8a21fa 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -31,17 +31,31 @@ #define MX6_OCOTP_CFG0 0x410 #define MX6_OCOTP_CFG1 0x420 +static void imx6_configure_aips(void __iomem *aips) +{ + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, aips); + writel(0x77777777, aips + 0x4); + + /* + * Set all OPACRx to be non-bufferable, not require + * supervisor privilege level for access,allow for + * write access and untrusted master access. + */ + writel(0, aips + 0x40); + writel(0, aips + 0x44); + writel(0, aips + 0x48); + writel(0, aips + 0x4c); + writel(0, aips + 0x50); +} + static void imx6_init_lowlevel(void) { - void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR; - void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR; - bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q; - bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D; - uint32_t val_480; - uint32_t val_528; - uint32_t periph_sel_1; - uint32_t periph_sel_2; - uint32_t reg; + bool is_imx6ull = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6ULL; + bool is_imx6sx = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6SX; /* * Before reset the controller imx6_boot_save_loc() must be called to @@ -51,61 +65,10 @@ static void imx6_init_lowlevel(void) if ((readl(MXC_CCM_CCGR6) & 0x3)) imx_reset_otg_controller(IOMEM(MX6_OTG_BASE_ADDR)); - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - writel(0x77777777, aips1); - writel(0x77777777, aips1 + 0x4); - writel(0, aips1 + 0x40); - writel(0, aips1 + 0x44); - writel(0, aips1 + 0x48); - writel(0, aips1 + 0x4c); - writel(0, aips1 + 0x50); - - writel(0x77777777, aips2); - writel(0x77777777, aips2 + 0x4); - writel(0, aips2 + 0x40); - writel(0, aips2 + 0x44); - writel(0, aips2 + 0x48); - writel(0, aips2 + 0x4c); - writel(0, aips2 + 0x50); - - /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs - * to make sure PFD is working right, otherwise, PFDs may - * not output clock after reset, MX6DL and MX6SL have added 396M pfd - * workaround in ROM code, as bus clock need it. - * Don't reset PLL2 PFD0 / PLL2 PFD2 if is's used by periph_clk. - */ - if (is_imx6q || is_imx6d) { - val_480 = BM_ANADIG_PFD_480_PFD3_CLKGATE | - BM_ANADIG_PFD_480_PFD2_CLKGATE | - BM_ANADIG_PFD_480_PFD1_CLKGATE | - BM_ANADIG_PFD_480_PFD0_CLKGATE; - - val_528 = BM_ANADIG_PFD_528_PFD3_CLKGATE | - BM_ANADIG_PFD_528_PFD1_CLKGATE; - - reg = readl(MXC_CCM_CBCMR); - periph_sel_1 = (reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) - >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET; - - periph_sel_2 = (reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) - >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET; - - if ((periph_sel_1 != 0x2) && (periph_sel_2 != 0x2)) - val_528 |= BM_ANADIG_PFD_528_PFD0_CLKGATE; - - if ((periph_sel_1 != 0x1) && (periph_sel_2 != 0x1) - && (periph_sel_1 != 0x3) && (periph_sel_2 != 0x3)) - val_528 |= BM_ANADIG_PFD_528_PFD2_CLKGATE; - - writel(val_480, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET); - writel(val_528, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET); - - writel(val_480, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR); - writel(val_528, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR); - } + imx6_configure_aips(IOMEM(MX6_AIPS1_ON_BASE_ADDR)); + imx6_configure_aips(IOMEM(MX6_AIPS2_ON_BASE_ADDR)); + if (is_imx6ull || is_imx6sx) + imx6_configure_aips(IOMEM(MX6_AIPS3_ON_BASE_ADDR)); } static bool imx6_has_ipu(void) @@ -363,7 +326,7 @@ static int imx6_fixup_cpus(struct device_node *root, void *context) unsigned long scu_phys_base; unsigned int max_core_index; - cpus_node = of_find_node_by_name(root, "cpus"); + cpus_node = of_find_node_by_name_address(root, "cpus"); if (!cpus_node) return 0; diff --git a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf-template.h b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf-template.h index a60b485292..45da2981cb 100644 --- a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf-template.h +++ b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf-template.h @@ -39,6 +39,18 @@ hab Engine = SETUP_HABV4_ENGINE hab Features = SETUP_HABV4_FEATURES #endif +/* +// allow fusing FIELD_RETURN +// # ocotp0.permanent_write_enable=1 +// # mw -l -d /dev/imx-ocotp 0xb8 0x1 +hab [Unlock] +hab Engine = OCOTP +hab Features = FIELD RETURN +// device-specific UID: +// $ dd if=/sys/bus/nvmem/devices/imx-ocotp0/nvmem bs=4 skip=1 count=2 status=none | hexdump -ve '1/1 "0x%.2x, "' | sed 's/, $//' +hab UID = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08 +*/ + hab [Install Key] /* verification key index in key store (0, 2...4) */ hab Verification index = 0 diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h index b2753b0fa7..35f03036cb 100644 --- a/arch/arm/mach-imx/include/mach/imx6-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6-regs.h @@ -11,9 +11,13 @@ #define MX6_AIPS1_ARB_BASE_ADDR 0x02000000 #define MX6_AIPS2_ARB_BASE_ADDR 0x02100000 +#define MX6_AIPS3_ARB_BASE_ADDR 0x02200000 +#define MX6_AIPS3_ARB_END_ADDR 0x022FFFFF + /* Defines for Blocks connected via AIPS (SkyBlue) */ #define MX6_ATZ1_BASE_ADDR MX6_AIPS1_ARB_BASE_ADDR #define MX6_ATZ2_BASE_ADDR MX6_AIPS2_ARB_BASE_ADDR +#define MX6_ATZ3_BASE_ADDR MX6_AIPS3_ARB_BASE_ADDR /* slots 0,7 of SDMA reserved, therefore left unused in IPMUX3 */ #define MX6_SPDIF_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x04000) @@ -81,6 +85,12 @@ #define MX6_CAAM_BASE_ADDR (MX6_ATZ2_BASE_ADDR) #define MX6_ARM_BASE_ADDR (MX6_ATZ2_BASE_ADDR + 0x40000) +/* ATZ#3- On Platform */ +#define MX6_AIPS3_ON_BASE_ADDR (MX6_ATZ3_BASE_ADDR + 0x7C000) + +/* ATZ#2- Off Platform */ +#define MX6_AIPS3_OFF_BASE_ADDR (MX6_ATZ3_BASE_ADDR + 0x80000) + #define MX6_USBOH3_PL301_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x0000) #define MX6_USBOH3_USB_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x4000) #define MX6_OTG_BASE_ADDR MX6_USBOH3_USB_BASE_ADDR diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c index 01961ae456..bcd04b210a 100644 --- a/arch/arm/mach-stm32mp/init.c +++ b/arch/arm/mach-stm32mp/init.c @@ -140,7 +140,7 @@ static int stm32mp15_fixup_cpus(struct device_node *root, void *_ctx) unsigned long ctx = (unsigned long)_ctx; struct device_node *cpus_node, *np, *tmp; - cpus_node = of_find_node_by_name(root, "cpus"); + cpus_node = of_find_node_by_name_address(root, "cpus"); if (!cpus_node) return 0; diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S index 0b81bd7d8d..cd4e4ccfe8 100644 --- a/arch/mips/lib/memset.S +++ b/arch/mips/lib/memset.S @@ -34,8 +34,8 @@ */ LEAF(memset) - beqz a1, 1f move v0, a0 /* result */ + beqz a1, 1f andi a1, 0xff /* spread fillword */ LONG_SLL t1, a1, 8 diff --git a/arch/riscv/boards/riscvemu/Makefile b/arch/riscv/boards/riscvemu/Makefile index 75f52ada8f..56949c2357 100644 --- a/arch/riscv/boards/riscvemu/Makefile +++ b/arch/riscv/boards/riscvemu/Makefile @@ -2,3 +2,4 @@ obj-y += board.o obj-y += overlay-of-sram.dtb.o +bbenv-$(CONFIG_CMD_TUTORIAL) += defaultenv-riscvemu diff --git a/arch/riscv/boards/riscvemu/board.c b/arch/riscv/boards/riscvemu/board.c index 31d0c70be6..d9c7bd77b8 100644 --- a/arch/riscv/boards/riscvemu/board.c +++ b/arch/riscv/boards/riscvemu/board.c @@ -5,6 +5,7 @@ #include <common.h> #include <driver.h> +#include <envfs.h> #include <poweroff.h> #include <restart.h> #include <deep-probe.h> @@ -45,6 +46,9 @@ static int riscvemu_probe(struct device_d *dev) of_overlay_apply_tree(dev->device_node, overlay); /* of_probe() will happen later at of_populate_initcall */ + if (IS_ENABLED(CONFIG_CMD_TUTORIAL)) + defaultenv_append_directory(defaultenv_riscvemu); + of_chosen = of_find_node_by_path("/chosen"); if (of_property_read_u64(of_chosen, "riscv,kernel-start", &start)) diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/00-init b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/00-init new file mode 100644 index 0000000000..1ff43142ba --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/00-init @@ -0,0 +1,12 @@ + +You are using Hush, barebox' default shell. You are currently using it +interactively, but it can execute scripts as part of the startup and boot +procedure as well. See for yourself: +``` + cat /env/init/90-tutorial-intro +``` +Look around as you like. When you are ready to continue the tutorial, +type `next` again. The `prev` command does the inverse and shows previous +tutorial steps. The `help` command will show help usage text, +e.g. `help next`. + diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/01-interactive b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/01-interactive new file mode 100644 index 0000000000..8b285cd9f4 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/01-interactive @@ -0,0 +1,7 @@ + +The interactive shell, its commands and the nodes in the virtual +file system they operate on enable quick UNIX-like prototyping +and debugging. Let's give it a try, shall we? +Type `of_dump` to list the open firmware (OF) device tree barebox +used to discover the hardware and `next` to continue the tutorial. + diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/02-ofdump b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/02-ofdump new file mode 100644 index 0000000000..3271f734b2 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/02-ofdump @@ -0,0 +1,6 @@ + +That's a lot of output, so let's restrict ourselves to just part +of the tree: +``` + of_dump /soc/virtio@40010000 +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/03-devinfo b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/03-devinfo new file mode 100644 index 0000000000..74bc9aa88a --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/03-devinfo @@ -0,0 +1,5 @@ + +This node tells barebox enough information to instantiate a device and +to try match it with existing drivers. Type `devinfo` to see the tree of +devices known to barebox. + diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/04-cs0 b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/04-cs0 new file mode 100644 index 0000000000..fdb878fa93 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/04-cs0 @@ -0,0 +1,11 @@ + +In this tree, you will find 40010000.virtio@40010000.of, the +device corresponding to the device tree node we've just seen. +Devices can have child devices themselves. This device's +grandchild is `cs0`, the virtual console device that prints +you this very text. + +See for yourself: +``` + echo -a /dev/cs0 Append this text to virtio console +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/05-drvinfo b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/05-drvinfo new file mode 100644 index 0000000000..068bf303d8 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/05-drvinfo @@ -0,0 +1,4 @@ + +Let's look at more devices. Type `drvinfo` to see what drivers are +available and what devices they were successfully matched with. + diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/06-devinfo-dev b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/06-devinfo-dev new file mode 100644 index 0000000000..f706915ba2 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/06-devinfo-dev @@ -0,0 +1,6 @@ + +Let's pick another device out of the list: HTIF. We can display some extra +info with `devinfo`. (Use the tab completion to avoid writing it all out!) +``` +devinfo 40008000.htif.of +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/07-mw b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/07-mw new file mode 100644 index 0000000000..4278f8f391 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/07-mw @@ -0,0 +1,9 @@ + +We see that the device has a memory mapped I/O region of 8 bytes that +can be used for communication. Poking 0x010100000000002e in little- +endian into that region should print a period '.'. +Let's do that quad-word memory write (`mw -q`) 80 times by having a shell +local variable keep count: +``` +i=0; while [ $i -lt 80 ]; do mw -q 0x40008000 0x010100000000002e; let i=$i+1; done +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/08-devfs b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/08-devfs new file mode 100644 index 0000000000..b117e4bb16 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/08-devfs @@ -0,0 +1,8 @@ + +`mw` is complemented by `md` for memory display. There are further commands +like `mm` (memory modify), `memcpy` and `memcmp` (copy/compare ranges). +These commands operate on `/dev/mem` by default, but any seekable device +or file can be used instead. Let's see what device files we got here: +``` +ls /dev +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/09-partitions b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/09-partitions new file mode 100644 index 0000000000..552ab2ab1e --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/09-partitions @@ -0,0 +1,9 @@ + +The `mtdram0` looks interesting. That's the 64K SRAM at the start of the +address space. The virtual machine places the boot "rom" there as well +as the flattened (compiled) device tree (FDT). barebox can be informed +about partitioning and will create extra devices for each partition. +This allows you to reference them from commands easily: +``` +of_dump -f /dev/mtdram0.fdt +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/10-environment b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/10-environment new file mode 100644 index 0000000000..d1a6f85119 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/10-environment @@ -0,0 +1,8 @@ + +Not all of the 64K is used, so the barebox board support here uses +the unused mtd-ram space for saving modified environment and state. +The barebox environment is a file system which contains scripts, variables +and data: +``` +ls -R /env +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/11-env-data b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/11-env-data new file mode 100644 index 0000000000..81e3f47ee7 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/11-env-data @@ -0,0 +1,12 @@ + +The environment you see here is the built-in environment barebox was +compiled with. It contains default values for non-volatile variables, +(init) scripts and data. It's generated from directories on the host +system specified during build and stored as an archive within +barebox. This environment may also be compressed allowing shipping +larger files and even binaries. For example, this barebox binary +has the option CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW_IKCONFIG=y, +which ships a copy of the used barebox configuration. See for yourself: +``` +cat /env/data/config +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/12-dmesg b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/12-dmesg new file mode 100644 index 0000000000..61cdd2adaf --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/12-dmesg @@ -0,0 +1,9 @@ + +In the field, you will probably want to depend exclusively on the built-in +environment, but it can be very handy to persist environment changes during +development. You may recall that barebox told us at first boot that the +environment was never written? If you don't, no problem, log messages are, +you guessed it, logged: +``` +dmesg +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/13-env-bin b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/13-env-bin new file mode 100644 index 0000000000..34b7ab554b --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/13-env-bin @@ -0,0 +1,11 @@ + +Let's modify the environment to add a new script (Remember +`help` can show you the usage, e.g. `help mw`): +``` +cd /env/bin +echo -o putc '#!/bin/sh' +echo -a putc 'mw -l 0x40008000 $1' +echo -a putc 'mw -l 0x40008004 0x01010000' +cd / +putc 0x40 # Print an @ character +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/14-env-init b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/14-env-init new file mode 100644 index 0000000000..184a4f571f --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/14-env-init @@ -0,0 +1,8 @@ + +We could have added the last script anywhere in `/env`. But `/env/bin` is +already in the executable search `PATH`, so you don't have to write out +the full path when invoking the script. Another special directory is +`/env/init`. Anything there will be sourced on shell startup. +Let's poke the HTIF a bit every time we start: Open a new file with +`edit /env/init/99-percent` and type into it `putc 0x40`. + diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/15-magicvar b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/15-magicvar new file mode 100644 index 0000000000..ec2912da9f --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/15-magicvar @@ -0,0 +1,10 @@ + +As init scripts only run on initialization, we'll have to do a reset to +see them in action. But first, we'll want to save our tutorial progress. +This happens via $global.variables. Many parts of barebox monitor reads +and writes to such variables to make information available to the shell. + +The `next` command also does it. How would you know? +``` +magicvar +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/16-env-nv b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/16-env-nv new file mode 100644 index 0000000000..3440e01947 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/16-env-nv @@ -0,0 +1,12 @@ + +Now that you know that $global.tutorial.step holds the next step, you +will want to initialize it on the next reset. We could write an init shell +script for that, but there is something much more convenient: + +On startup, barebox needs to assign initial values for each +$global.variable; if a suitably named non-volatile $nv.variable already +exists, it will be used as initial value. Let's see what global variables +we got (leading asterisk '*' means it was initialized from NV): +``` +global +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/17-env-saveenv b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/17-env-saveenv new file mode 100644 index 0000000000..f929838138 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/17-env-saveenv @@ -0,0 +1,7 @@ + +Now that we have written a normal script and an init script, add a +nv variable to the mix, save the environment and reset to see them +all in action: +``` +nv tutorial.step=$global.tutorial.step; saveenv; reset +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/17-env-usage b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/17-env-usage new file mode 100644 index 0000000000..1f4ff37f86 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/17-env-usage @@ -0,0 +1,5 @@ + +Welcome back! You have successfully saved the environment. Make sure +to reset your environment with `saveenv -z` when you are done. You wouldn't +want to chase ghosts, because you changed an init script and forgot about it. :) + diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/18-mnt b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/18-mnt new file mode 100644 index 0000000000..3122e6ffa4 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/18-mnt @@ -0,0 +1,11 @@ + +We now have seen `/dev`, which holds the devfs, and `/env` which holds the +active environment. `/tmp` is as you have guessed it a directory where temporary +files can be placed. `/pstore` is short for persistent storage, a Linux +mechanism to store and retrieve error records even after a kernel panic. + +This leaves `/mnt`. Let's take a peek at it as well at our active mounts: +``` +mount +ls /mnt +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/19-automount b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/19-automount new file mode 100644 index 0000000000..4d4787a9a8 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/19-automount @@ -0,0 +1,9 @@ + +Strangely, nothing inside `/mnt` is seen in the `mount` output. Why you +ask? Because these are automounts that are deferred until first access. +So when you `bootm /mnt/nfs/boot/Image.gz` the first time, barebox will +bring up the network and mount the network file system (provided you do +have network). We can list what automounts there are: +``` +automount -l +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/20-mount-fs b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/20-mount-fs new file mode 100644 index 0000000000..cc5e64c66c --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/20-mount-fs @@ -0,0 +1,11 @@ + +`/mnt/virtioblk0` is an interesting one. Block device partitions +automatically get automount entries created. On first access, +barebox will determine what file system is located in the partition +and mount it. Thus you can just use `/mnt/virtioblk0/DOOM1.WAD` in +your script and not incur the overhead of mounting unless it's accessed: +``` +mount +ll /mnt/virtioblk0/DOOM1.WAD +mount +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/21-state b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/21-state new file mode 100644 index 0000000000..1a71204cf5 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/21-state @@ -0,0 +1,11 @@ + +You'll note most file systems in barebox are read-only. While those that aren't +could be used with `saveenv` to store a packed environment for Linux use, that's +murky waters: atomicity, limiting scope, authentication and journal handling +complicate things. barebox state is the mechanism how barebox stores variables +(and only variables) in a power-fail safe manner that's also accessible to Linux. + +Check the `state` device: +``` +devinfo state +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/22-device-params b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/22-device-params new file mode 100644 index 0000000000..3f8d31f171 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/22-device-params @@ -0,0 +1,11 @@ + +The state driver parses the device tree to learn the state layout +and how it's (redundantly) placed. The information it learns are +registered with the device as device parameters. Device Parameters +make it easy to interact with the shell. For example, the MAC address +of a network adapter is a device parameter. We already saw some other +device parameters before. Those of the global and nv device: +``` +devinfo global +devinfo nv +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/23-device-param-types b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/23-device-param-types new file mode 100644 index 0000000000..36a311d011 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/23-device-param-types @@ -0,0 +1,8 @@ + +Many device parameters are simple strings, some have specific types +and run actions on read/write or accept only specific values. +`devinfo` will show you what type a variable has and writing an +invalid value will give you an error: +``` +global.tutorial.step=non-existent +``` diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/24-boot b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/24-boot new file mode 100644 index 0000000000..90c2266973 --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/24-boot @@ -0,0 +1,12 @@ + +You should now know enough about barebox' architecture, that +we could talk about barebox' actual function without it +seeming too magical: Booting. + +We still need to add that part to the tutorial though, but you +can check out `help boot`, `help bootm` as well as the barebox +documentation linked below. Also give the graphical mode a +try! + +Tutorial to be continued.. + diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/99-end b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/99-end new file mode 100644 index 0000000000..4744f2b3ee --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/data/tutorial/99-end @@ -0,0 +1 @@ +End of tutorial reached! diff --git a/arch/riscv/boards/riscvemu/defaultenv-riscvemu/init/90-tutorial-intro b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/init/90-tutorial-intro new file mode 100644 index 0000000000..716905534c --- /dev/null +++ b/arch/riscv/boards/riscvemu/defaultenv-riscvemu/init/90-tutorial-intro @@ -0,0 +1,6 @@ +source /env/data/ansi-colors + +echo -e $YELLOW +echo -e This is the barebox shell. See ${RED}help${YELLOW} for a listing of commands. +echo -e Type ${RED}next${YELLOW} for the next tutorial tip. +echo -e $NC diff --git a/arch/riscv/cpu/core.c b/arch/riscv/cpu/core.c index 1d5902a51f..c075301b1b 100644 --- a/arch/riscv/cpu/core.c +++ b/arch/riscv/cpu/core.c @@ -43,7 +43,7 @@ static int riscv_fixup_cpus(struct device_node *root, void *context) { struct device_node *cpus_node, *np, *tmp; - cpus_node = of_find_node_by_name(root, "cpus"); + cpus_node = of_find_node_by_name_address(root, "cpus"); if (!cpus_node) return 0; diff --git a/commands/of_display_timings.c b/commands/of_display_timings.c index 4e5ec223b7..aab57b17d6 100644 --- a/commands/of_display_timings.c +++ b/commands/of_display_timings.c @@ -98,7 +98,7 @@ static int do_of_display_timings(int argc, char *argv[]) int found = 0; const char *node = "display-timings"; - for_each_node_by_name_from(display, root, node) { + for_each_node_by_name_address_from(display, root, node) { for_each_child_of_node(display, timings) { printf("%s\n", timings->full_name); found = 1; @@ -113,7 +113,7 @@ static int do_of_display_timings(int argc, char *argv[]) int found = 0; const char *node = "display-timings"; - for_each_node_by_name_from(display, root, node) { + for_each_node_by_name_address_from(display, root, node) { timings = of_parse_phandle_from(display, root, "native-mode", 0); if (!timings) diff --git a/commands/tutorial.c b/commands/tutorial.c index 81e2f93716..4441777643 100644 --- a/commands/tutorial.c +++ b/commands/tutorial.c @@ -152,7 +152,7 @@ static __maybe_unused const char *const prev_alias[] = { "prev", NULL}; BAREBOX_CMD_START(next) .cmd = do_tutorial_next, .aliases = prev_alias, - BAREBOX_CMD_DESC("print next tip for barebox tutorial") + BAREBOX_CMD_DESC("navigate the barebox tutorial") BAREBOX_CMD_OPTS("[-hr] [STEP]") BAREBOX_CMD_HELP(cmd_next_help) BAREBOX_CMD_GROUP(CMD_GRP_INFO) diff --git a/common/bootm.c b/common/bootm.c index 4652467448..3c80e8bf94 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -113,7 +113,7 @@ int bootm_load_os(struct image_data *data, unsigned long load_address) load_address, kernel_size); if (!data->os_res) { pr_err("unable to request SDRAM region for kernel at" - "0x%08llx-0x%08llx\n", + " 0x%08llx-0x%08llx\n", (unsigned long long)load_address, (unsigned long long)load_address + kernel_size - 1); return -ENOMEM; diff --git a/common/imd.c b/common/imd.c index 9ca0248523..1100e6878a 100644 --- a/common/imd.c +++ b/common/imd.c @@ -22,7 +22,8 @@ static inline void read_file_2_free(void *buf) free(buf); } -static int imd_read_file(const char *filename, size_t *size, void **outbuf) +static int imd_read_file(const char *filename, size_t *size, void **outbuf, + bool allow_mmap) { return read_file_2(filename, size, outbuf, 0x100000); } @@ -439,6 +440,7 @@ int imd_command(int argc, char *argv[]) char *str; uint32_t checksum = 0; uint32_t verify = 0; + bool allow_mmap = true; imd_command_verbose = 0; @@ -462,6 +464,7 @@ int imd_command(int argc, char *argv[]) break; case 'c': checksum = 1; + allow_mmap = false; break; case 'V': verify = 1; @@ -478,7 +481,7 @@ int imd_command(int argc, char *argv[]) filename = argv[optind]; - ret = imd_read_file(filename, &size, &buf); + ret = imd_read_file(filename, &size, &buf, allow_mmap); if (ret && ret != -EFBIG) return -errno; diff --git a/common/oftree.c b/common/oftree.c index 0738ab6e9e..bce0ff09d6 100644 --- a/common/oftree.c +++ b/common/oftree.c @@ -405,7 +405,7 @@ int of_autoenable_device_by_path(char *path) struct device_node *node; int ret; - node = of_find_node_by_name(NULL, path); + node = of_find_node_by_name_address(NULL, path); if (!node) node = of_find_node_by_path(path); @@ -442,7 +442,7 @@ int of_autoenable_i2c_by_component(char *path) if (!IS_ENABLED(CONFIG_I2C)) return -ENODEV; - node = of_find_node_by_name(NULL, path); + node = of_find_node_by_name_address(NULL, path); if (!node) node = of_find_node_by_path(path); if (!node) diff --git a/drivers/aiodev/qoriq_thermal.c b/drivers/aiodev/qoriq_thermal.c index d62048ef13..1acb06a9de 100644 --- a/drivers/aiodev/qoriq_thermal.c +++ b/drivers/aiodev/qoriq_thermal.c @@ -118,7 +118,7 @@ static int qoriq_tmu_get_sensor_id(void) struct of_phandle_args sensor_specs; struct device_node *np, *sensor_np; - np = of_find_node_by_name(NULL, "thermal-zones"); + np = of_find_node_by_name_address(NULL, "thermal-zones"); if (!np) return -ENODEV; diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 63056b7696..4ebdd399b4 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -181,9 +181,13 @@ struct clk_hw *clk_hw_register_composite(struct device_d *dev, unsigned long flags) { struct clk *clk; - mux_hw->clk.ops = mux_ops; - rate_hw->clk.ops = rate_ops; - gate_hw->clk.ops = gate_ops; + + if (mux_hw) + mux_hw->clk.ops = mux_ops; + if (rate_hw) + rate_hw->clk.ops = rate_ops; + if (gate_hw) + gate_hw->clk.ops = gate_ops; parent_names = memdup_array(parent_names, num_parents); if (!parent_names) diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c index e3afcf7858..06cc992b72 100644 --- a/drivers/clk/imx/clk-imx6.c +++ b/drivers/clk/imx/clk-imx6.c @@ -91,6 +91,13 @@ static const char *periph_pre_sels[] = { static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", + "osc", + "dummy", +}; + +static const char *periph2_clk2_sels[] = { + "pll3_usb_otg", + "pll2_bus", }; static const char *periph_sels[] = { @@ -106,6 +113,7 @@ static const char *periph2_sels[] = { static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", + "periph", "pll3_pfd1_540m", }; @@ -131,6 +139,13 @@ static const char *enfc_sels_plus[] = { }; static const char *eim_sels[] = { + "pll2_pfd2_396m", + "pll3_usb_otg", + "axi", + "pll2_pfd0_352m", +}; + +static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", @@ -151,8 +166,8 @@ static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", - "pll5_video", - "dummy", + "pll5_video_div", + "video_27m", "axi", "enfc", "ipu1_di0", @@ -163,7 +178,7 @@ static const char *cko1_sels[] = { "ipg", "ipg_per", "ckil", - "pll4_audio", + "pll4_audio_div", }; static const char *cko2_sels[] = { @@ -573,10 +588,6 @@ static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb, struct dev clks[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", cb + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); clks[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", cb + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); - disable_anatop_clocks(anab); - - imx6q_mmdc_ch1_mask_handshake(cb); - if (cpu_mx6_has_err009219()) { /* * The LDB_DI0/1_SEL muxes should be read-only due to a hardware @@ -612,6 +623,8 @@ static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb, struct dev clks[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", cb + 0x38, 3, 3); clks[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", cb + 0x38, 12, 3); + clks[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", cb + 0x70, 0); + clks[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "mipi_core_cfg", cb + 0x70, 4); clks[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", cb + 0x74, 0); clks[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", cb + 0x74, 2); clks[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", cb + 0x74, 4); @@ -620,6 +633,8 @@ static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb, struct dev clks[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", cb + 0x74, 12); clks[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", cb + 0x74, 14); clks[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", cb + 0x74, 10); + clks[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2("mipi_core_cfg", "video_27m", cb + 0x74, 16); + clks[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20); clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI0_SEL], clks[IMX6QDL_CLK_IPU1_DI0_PRE]); clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI1_SEL], clks[IMX6QDL_CLK_IPU1_DI1_PRE]); @@ -695,7 +710,7 @@ static int imx6_ccm_probe(struct device_d *dev) clks[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); clks[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); clks[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); - clks[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clks[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); clks[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); clks[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); clks[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); @@ -706,7 +721,7 @@ static int imx6_ccm_probe(struct device_d *dev) else clks[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); clks[IMX6QDL_CLK_EIM_SEL] = imx_clk_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels)); - clks[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_sels, ARRAY_SIZE(eim_sels)); + clks[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_sels, ARRAY_SIZE(eim_slow_sels)); clks[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); clks[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); clks[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); @@ -788,6 +803,10 @@ static int imx6_ccm_probe(struct device_d *dev) clkdev_add_physbase(clks[IMX6QDL_CLK_IPG], MX6_OCOTP_BASE_ADDR, NULL); + disable_anatop_clocks(anatop_base); + + imx6q_mmdc_ch1_mask_handshake(ccm_base); + if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3)) imx6_add_video_clks(anatop_base, ccm_base, dev->device_node); diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index b3af3c4263..cf532b1399 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -727,6 +727,7 @@ static const struct spi_device_id spi_nor_ids[] = { { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, + { "mt25qu256a", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 6725c7b9bd..748aa861f1 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -1224,7 +1224,7 @@ static void cpsw_add_slave(struct cpsw_slave *slave, struct device_node *child, uint32_t phy_id[2] = {-1, -1}; int ret; - if (!of_find_node_by_name(child, "fixed-link")) { + if (!of_find_node_by_name_address(child, "fixed-link")) { ret = of_property_read_u32_array(child, "phy_id", phy_id, 2); if (!ret) dev_warn(slave->cpsw->dev, "phy_id is deprecated, use phy-handle\n"); diff --git a/drivers/net/designware_rockchip.c b/drivers/net/designware_rockchip.c index da57ed1717..dcf65c9ad4 100644 --- a/drivers/net/designware_rockchip.c +++ b/drivers/net/designware_rockchip.c @@ -21,6 +21,7 @@ struct rk_gmac_ops { void (*set_rmii_speed)(struct eqos *eqos, int speed); void (*set_rgmii_speed)(struct eqos *eqos, int speed); void (*integrated_phy_powerup)(struct eqos *eqos); + u32 regs[]; }; struct eqos_rk_gmac { @@ -174,6 +175,11 @@ static const struct rk_gmac_ops rk3568_ops = { .set_to_rmii = rk3568_set_to_rmii, .set_rmii_speed = rk3568_set_gmac_speed, .set_rgmii_speed = rk3568_set_gmac_speed, + .regs = { + 0xfe2a0000, /* gmac0 */ + 0xfe010000, /* gmac1 */ + 0x0, /* sentinel */ + }, }; static int rk_gmac_powerup(struct eqos *eqos) @@ -228,7 +234,7 @@ static int eqos_init_rk_gmac(struct device_d *dev, struct eqos *eqos) { struct device_node *np = dev->device_node; struct eqos_rk_gmac *priv = to_rk_gmac(eqos); - int ret; + int i = 0, ret; const char *strings; priv->dev = dev; @@ -247,7 +253,15 @@ static int eqos_init_rk_gmac(struct device_d *dev, struct eqos *eqos) priv->ops = device_get_match_data(dev); - priv->bus_id = of_alias_get_id(np, "ethernet"); + if (dev->num_resources > 0) { + while (priv->ops->regs[i]) { + if (priv->ops->regs[i] == dev->resource[0].start) { + priv->bus_id = i; + break; + } + i++; + } + } priv->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); if (IS_ERR(priv->grf)) { diff --git a/drivers/net/phy/mv88e6xxx/port.c b/drivers/net/phy/mv88e6xxx/port.c index ba2b03e18d..79694e5237 100644 --- a/drivers/net/phy/mv88e6xxx/port.c +++ b/drivers/net/phy/mv88e6xxx/port.c @@ -558,7 +558,7 @@ int mv88e6xxx_port_probe(struct mv88e6xxx_chip *chip) struct device_node *port_nodes[DSA_MAX_PORTS] = { NULL }; int err, i; - switch_node = of_find_node_by_name(np, "ports"); + switch_node = of_find_node_by_name_address(np, "ports"); if (!switch_node) return -EINVAL; diff --git a/drivers/of/base.c b/drivers/of/base.c index 723bf2132d..83291c4785 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -23,6 +23,21 @@ static struct device_node *root_node; +bool of_node_name_eq(const struct device_node *np, const char *name) +{ + const char *node_name; + size_t len; + + if (!np) + return false; + + node_name = kbasename(np->full_name); + len = strchrnul(node_name, '@') - node_name; + + return (strlen(name) == len) && (strncmp(node_name, name, len) == 0); +} +EXPORT_SYMBOL(of_node_name_eq); + /* * Iterate over all nodes of a tree. As a devicetree does not * have a dedicated list head, the start node (usually the root @@ -538,6 +553,29 @@ int of_device_is_compatible(const struct device_node *device, EXPORT_SYMBOL(of_device_is_compatible); /** + * of_find_node_by_name_address - Find a node by its full name + * @from: The node to start searching from or NULL, the node + * you pass will not be searched, only the next one + * will; typically, you pass what the previous call + * returned. + * @name: The name string to match against + * + * Returns a pointer to the node found or NULL. + */ +struct device_node *of_find_node_by_name_address(struct device_node *from, + const char *name) +{ + struct device_node *np; + + of_tree_for_each_node_from(np, from) + if (np->name && !of_node_cmp(np->name, name)) + return np; + + return NULL; +} +EXPORT_SYMBOL(of_find_node_by_name_address); + +/** * of_find_node_by_name - Find a node by its "name" property * @from: The node to start searching from or NULL, the node * you pass will not be searched, only the next one @@ -553,7 +591,7 @@ struct device_node *of_find_node_by_name(struct device_node *from, struct device_node *np; of_tree_for_each_node_from(np, from) - if (np->name && !of_node_cmp(np->name, name)) + if (np->name && of_node_name_eq(np, name)) return np; return NULL; diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index 770126c78e..5ccbd1bb69 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -486,7 +486,7 @@ void *of_flatten_dtb(struct device_node *node) if (ret) goto out_free; - memreserve = of_find_node_by_name(node, "memreserve"); + memreserve = of_find_node_by_name_address(node, "memreserve"); if (memreserve) { const void *entries = of_get_property(memreserve, "reg", &len); diff --git a/drivers/of/platform.c b/drivers/of/platform.c index 0e718469db..7f377b8b37 100644 --- a/drivers/of/platform.c +++ b/drivers/of/platform.c @@ -202,7 +202,7 @@ struct device_d *of_device_enable_and_register_by_name(const char *name) { struct device_node *node; - node = of_find_node_by_name(NULL, name); + node = of_find_node_by_name_address(NULL, name); if (!node) node = of_find_node_by_path(name); @@ -422,7 +422,9 @@ int of_device_ensure_probed(struct device_node *np) if (IS_ERR(dev)) return PTR_ERR(dev); - BUG_ON(!dev); + if (!dev) + panic("deep-probe: device for '%s' couldn't be created\n", + np->full_name); /* * The deep-probe mechanism relies on the fact that all necessary @@ -455,6 +457,9 @@ int of_device_ensure_probed_by_alias(const char *alias) { struct device_node *dev_node; + if (!deep_probe_is_supported()) + return 0; + dev_node = of_find_node_by_alias(NULL, alias); if (!dev_node) return -EINVAL; @@ -480,6 +485,9 @@ int of_devices_ensure_probed_by_dev_id(const struct of_device_id *ids) struct device_node *np; int err, ret = 0; + if (!deep_probe_is_supported()) + return 0; + for_each_matching_node(np, ids) { if (!of_device_is_available(np)) continue; @@ -508,19 +516,39 @@ EXPORT_SYMBOL_GPL(of_devices_ensure_probed_by_dev_id); int of_devices_ensure_probed_by_property(const char *property_name) { struct device_node *node; + int err, ret = 0; - for_each_node_with_property(node, property_name) { - int ret; + if (!deep_probe_is_supported()) + return 0; + for_each_node_with_property(node, property_name) { ret = of_device_ensure_probed(node); - if (ret) - return ret; + if (err) + ret = err; } return 0; } EXPORT_SYMBOL_GPL(of_devices_ensure_probed_by_property); +int of_devices_ensure_probed_by_name(const char *name) +{ + struct device_node *node; + int err, ret = 0; + + if (!deep_probe_is_supported()) + return 0; + + for_each_node_by_name(node, name) { + ret = of_device_ensure_probed(node); + if (err) + ret = err; + } + + return 0; +} +EXPORT_SYMBOL_GPL(of_devices_ensure_probed_by_name); + static int of_stdoutpath_init(void) { struct device_node *np; @@ -537,3 +565,11 @@ static int of_stdoutpath_init(void) return of_device_ensure_probed(np); } postconsole_initcall(of_stdoutpath_init); + +static int of_timer_init(void) +{ + of_devices_ensure_probed_by_name("timer"); + + return 0; +} +postcore_initcall(of_timer_init); diff --git a/drivers/of/resolver.c b/drivers/of/resolver.c index 242775099e..2457ae96a4 100644 --- a/drivers/of/resolver.c +++ b/drivers/of/resolver.c @@ -214,7 +214,7 @@ struct device_node *of_resolve_phandles(struct device_node *root, * to a phandle defined in the overlay. We must update the references, * because we just adjusted the definitions. */ - local_fixups = of_find_node_by_name(result, "__local_fixups__"); + local_fixups = of_find_node_by_name_address(result, "__local_fixups__"); err = adjust_local_phandle_references(local_fixups, result, delta); if (err) { pr_err("failed to fix phandles in overlay\n"); @@ -227,7 +227,7 @@ struct device_node *of_resolve_phandles(struct device_node *root, * the base device tree. We must update the references, because they * are otherwise undefined. */ - overlay_fixups = of_find_node_by_name(result, "__fixups__"); + overlay_fixups = of_find_node_by_name_address(result, "__fixups__"); if (!overlay_fixups) { pr_debug("overlay does not contain phandles to base devicetree\n"); goto out; diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 997b986d5f..af8a0cb4fc 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -130,7 +130,7 @@ static struct regulator_internal * __regulator_register(struct regulator_dev *rd if (name) ri->name = xstrdup(name); - if (rd->boot_on && rd->always_on) { + if (rd->boot_on || rd->always_on) { ret = regulator_enable_internal(ri); if (ret && ret != -ENOSYS) goto err; @@ -199,14 +199,14 @@ static struct regulator_internal *of_regulator_get(struct device_d *dev, const c struct device_node *node, *node_parent; int ret; - propname = basprintf("%s-supply", supply); - /* * If the device does have a device node return the dummy regulator. */ if (!dev->device_node) return NULL; + propname = basprintf("%s-supply", supply); + /* * If the device node does not contain a supply property, this device doesn't * need a regulator. Return the dummy regulator in this case. @@ -246,7 +246,8 @@ static struct regulator_internal *of_regulator_get(struct device_d *dev, const c goto out; } - return ERR_PTR(ret); + ri = ERR_PTR(ret); + goto out; } list_for_each_entry(ri, ®ulator_list, list) { diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index b0137d21e0..7df7561718 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -114,6 +114,16 @@ config DRIVER_SPI_STM32 Enable the STM32 Serial Peripheral Interface (SPI) driver for STM32MP SoCs. +config SPI_NXP_FLEXSPI + tristate "NXP Flex SPI controller" + depends on ARCH_IMX8M || COMPILE_TEST + help + This enables support for the Flex SPI controller in master mode. + Up to four slave devices can be connected on two buses with two + chipselects each. + This controller does not support generic SPI messages and only + supports the high-level SPI memory interface. + endif endmenu diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 39be9d41e4..64c8e2645a 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -15,4 +15,5 @@ obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o obj-$(CONFIG_DRIVER_SPI_OMAP3) += omap3_spi.o obj-$(CONFIG_DRIVER_SPI_DSPI) += dspi_spi.o obj-$(CONFIG_SPI_ZYNQ_QSPI) += zynq_qspi.o +obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o obj-$(CONFIG_DRIVER_SPI_STM32) += stm32_spi.o diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c new file mode 100644 index 0000000000..673b91d6dc --- /dev/null +++ b/drivers/spi/spi-nxp-fspi.c @@ -0,0 +1,1061 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * NXP FlexSPI(FSPI) controller driver. + * + * Copyright 2019-2020 NXP + * Copyright 2020 Puresoftware Ltd. + * Copyright 2021 Westermo Network Technologies AB + * + * FlexSPI is a flexsible SPI host controller which supports two SPI + * channels and up to 4 external devices. Each channel supports + * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional + * data lines). + * + * FlexSPI controller is driven by the LUT(Look-up Table) registers + * LUT registers are a look-up-table for sequences of instructions. + * A valid sequence consists of four LUT registers. + * Maximum 32 LUT sequences can be programmed simultaneously. + * + * LUTs are being created at run-time based on the commands passed + * from the spi-mem framework, thus using single LUT index. + * + * Software triggered Flash read/write access by IP Bus. + * + * Memory mapped read access by AHB Bus. + * + * Based on SPI MEM interface and spi-fsl-qspi.c driver. + * + * Author: + * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> + * Boris Brezillon <bbrezillon@kernel.org> + * Frieder Schrempf <frieder.schrempf@kontron.de> + * Joacim Zetterling <joacim.zetterling@westermo.com> + */ + +#include <common.h> +#include <driver.h> +#include <errno.h> +#include <init.h> +#include <io.h> +#include <regmap.h> +#include <linux/types.h> +#include <linux/bitops.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/iopoll.h> +#include <linux/mutex.h> +#include <linux/sizes.h> +#include <of.h> +#include <of_device.h> +#include <stdbool.h> + +#include <spi/spi.h> +#include <linux/spi/spi-mem.h> + +/* + * The driver only uses one single LUT entry, that is updated on + * each call of exec_op(). Index 0 is preset at boot with a basic + * read operation, so let's use the last entry (31). + */ +#define SEQID_LUT 31 + +/* Registers used by the driver */ +#define FSPI_MCR0 0x00 +#define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) +#define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16) +#define FSPI_MCR0_LEARN_EN BIT(15) +#define FSPI_MCR0_SCRFRUN_EN BIT(14) +#define FSPI_MCR0_OCTCOMB_EN BIT(13) +#define FSPI_MCR0_DOZE_EN BIT(12) +#define FSPI_MCR0_HSEN BIT(11) +#define FSPI_MCR0_SERCLKDIV BIT(8) +#define FSPI_MCR0_ATDF_EN BIT(7) +#define FSPI_MCR0_ARDF_EN BIT(6) +#define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) +#define FSPI_MCR0_END_CFG(x) ((x) << 2) +#define FSPI_MCR0_MDIS BIT(1) +#define FSPI_MCR0_SWRST BIT(0) + +#define FSPI_MCR1 0x04 +#define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16) +#define FSPI_MCR1_AHB_TIMEOUT(x) (x) + +#define FSPI_MCR2 0x08 +#define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24) +#define FSPI_MCR2_SAMEDEVICEEN BIT(15) +#define FSPI_MCR2_CLRLRPHS BIT(14) +#define FSPI_MCR2_ABRDATSZ BIT(8) +#define FSPI_MCR2_ABRLEARN BIT(7) +#define FSPI_MCR2_ABR_READ BIT(6) +#define FSPI_MCR2_ABRWRITE BIT(5) +#define FSPI_MCR2_ABRDUMMY BIT(4) +#define FSPI_MCR2_ABR_MODE BIT(3) +#define FSPI_MCR2_ABRCADDR BIT(2) +#define FSPI_MCR2_ABRRADDR BIT(1) +#define FSPI_MCR2_ABR_CMD BIT(0) + +#define FSPI_AHBCR 0x0c +#define FSPI_AHBCR_RDADDROPT BIT(6) +#define FSPI_AHBCR_PREF_EN BIT(5) +#define FSPI_AHBCR_BUFF_EN BIT(4) +#define FSPI_AHBCR_CACH_EN BIT(3) +#define FSPI_AHBCR_CLRTXBUF BIT(2) +#define FSPI_AHBCR_CLRRXBUF BIT(1) +#define FSPI_AHBCR_PAR_EN BIT(0) + +#define FSPI_INTEN 0x10 +#define FSPI_INTEN_SCLKSBWR BIT(9) +#define FSPI_INTEN_SCLKSBRD BIT(8) +#define FSPI_INTEN_DATALRNFL BIT(7) +#define FSPI_INTEN_IPTXWE BIT(6) +#define FSPI_INTEN_IPRXWA BIT(5) +#define FSPI_INTEN_AHBCMDERR BIT(4) +#define FSPI_INTEN_IPCMDERR BIT(3) +#define FSPI_INTEN_AHBCMDGE BIT(2) +#define FSPI_INTEN_IPCMDGE BIT(1) +#define FSPI_INTEN_IPCMDDONE BIT(0) + +#define FSPI_INTR 0x14 +#define FSPI_INTR_SCLKSBWR BIT(9) +#define FSPI_INTR_SCLKSBRD BIT(8) +#define FSPI_INTR_DATALRNFL BIT(7) +#define FSPI_INTR_IPTXWE BIT(6) +#define FSPI_INTR_IPRXWA BIT(5) +#define FSPI_INTR_AHBCMDERR BIT(4) +#define FSPI_INTR_IPCMDERR BIT(3) +#define FSPI_INTR_AHBCMDGE BIT(2) +#define FSPI_INTR_IPCMDGE BIT(1) +#define FSPI_INTR_IPCMDDONE BIT(0) + +#define FSPI_LUTKEY 0x18 +#define FSPI_LUTKEY_VALUE 0x5AF05AF0 + +#define FSPI_LCKCR 0x1C + +#define FSPI_LCKER_LOCK 0x1 +#define FSPI_LCKER_UNLOCK 0x2 + +#define FSPI_BUFXCR_INVALID_MSTRID 0xE +#define FSPI_AHBRX_BUF0CR0 0x20 +#define FSPI_AHBRX_BUF1CR0 0x24 +#define FSPI_AHBRX_BUF2CR0 0x28 +#define FSPI_AHBRX_BUF3CR0 0x2C +#define FSPI_AHBRX_BUF4CR0 0x30 +#define FSPI_AHBRX_BUF5CR0 0x34 +#define FSPI_AHBRX_BUF6CR0 0x38 +#define FSPI_AHBRX_BUF7CR0 0x3C +#define FSPI_AHBRXBUF0CR7_PREF BIT(31) + +#define FSPI_AHBRX_BUF0CR1 0x40 +#define FSPI_AHBRX_BUF1CR1 0x44 +#define FSPI_AHBRX_BUF2CR1 0x48 +#define FSPI_AHBRX_BUF3CR1 0x4C +#define FSPI_AHBRX_BUF4CR1 0x50 +#define FSPI_AHBRX_BUF5CR1 0x54 +#define FSPI_AHBRX_BUF6CR1 0x58 +#define FSPI_AHBRX_BUF7CR1 0x5C + +#define FSPI_FLSHA1CR0 0x60 +#define FSPI_FLSHA2CR0 0x64 +#define FSPI_FLSHB1CR0 0x68 +#define FSPI_FLSHB2CR0 0x6C +#define FSPI_FLSHXCR0_SZ_KB 10 +#define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB) + +#define FSPI_FLSHA1CR1 0x70 +#define FSPI_FLSHA2CR1 0x74 +#define FSPI_FLSHB1CR1 0x78 +#define FSPI_FLSHB2CR1 0x7C +#define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16) +#define FSPI_FLSHXCR1_CAS(x) ((x) << 11) +#define FSPI_FLSHXCR1_WA BIT(10) +#define FSPI_FLSHXCR1_TCSH(x) ((x) << 5) +#define FSPI_FLSHXCR1_TCSS(x) (x) + +#define FSPI_FLSHA1CR2 0x80 +#define FSPI_FLSHA2CR2 0x84 +#define FSPI_FLSHB1CR2 0x88 +#define FSPI_FLSHB2CR2 0x8C +#define FSPI_FLSHXCR2_CLRINSP BIT(24) +#define FSPI_FLSHXCR2_AWRWAIT BIT(16) +#define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13 +#define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8 +#define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5 +#define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0 + +#define FSPI_IPCR0 0xA0 + +#define FSPI_IPCR1 0xA4 +#define FSPI_IPCR1_IPAREN BIT(31) +#define FSPI_IPCR1_SEQNUM_SHIFT 24 +#define FSPI_IPCR1_SEQID_SHIFT 16 +#define FSPI_IPCR1_IDATSZ(x) (x) + +#define FSPI_IPCMD 0xB0 +#define FSPI_IPCMD_TRG BIT(0) + +#define FSPI_DLPR 0xB4 + +#define FSPI_IPRXFCR 0xB8 +#define FSPI_IPRXFCR_CLR BIT(0) +#define FSPI_IPRXFCR_DMA_EN BIT(1) +#define FSPI_IPRXFCR_WMRK(x) ((x) << 2) + +#define FSPI_IPTXFCR 0xBC +#define FSPI_IPTXFCR_CLR BIT(0) +#define FSPI_IPTXFCR_DMA_EN BIT(1) +#define FSPI_IPTXFCR_WMRK(x) ((x) << 2) + +#define FSPI_DLLACR 0xC0 +#define FSPI_DLLACR_OVRDEN BIT(8) + +#define FSPI_DLLBCR 0xC4 +#define FSPI_DLLBCR_OVRDEN BIT(8) + +#define FSPI_STS0 0xE0 +#define FSPI_STS0_DLPHB(x) ((x) << 8) +#define FSPI_STS0_DLPHA(x) ((x) << 4) +#define FSPI_STS0_CMD_SRC(x) ((x) << 2) +#define FSPI_STS0_ARB_IDLE BIT(1) +#define FSPI_STS0_SEQ_IDLE BIT(0) + +#define FSPI_STS1 0xE4 +#define FSPI_STS1_IP_ERRCD(x) ((x) << 24) +#define FSPI_STS1_IP_ERRID(x) ((x) << 16) +#define FSPI_STS1_AHB_ERRCD(x) ((x) << 8) +#define FSPI_STS1_AHB_ERRID(x) (x) + +#define FSPI_AHBSPNST 0xEC +#define FSPI_AHBSPNST_DATLFT(x) ((x) << 16) +#define FSPI_AHBSPNST_BUFID(x) ((x) << 1) +#define FSPI_AHBSPNST_ACTIVE BIT(0) + +#define FSPI_IPRXFSTS 0xF0 +#define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16) +#define FSPI_IPRXFSTS_FILL(x) (x) + +#define FSPI_IPTXFSTS 0xF4 +#define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16) +#define FSPI_IPTXFSTS_FILL(x) (x) + +#define FSPI_RFDR 0x100 +#define FSPI_TFDR 0x180 + +#define FSPI_LUT_BASE 0x200 +#define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) +#define FSPI_LUT_REG(idx) \ + (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4) + +/* register map end */ + +/* Instruction set for the LUT register. */ +#define LUT_STOP 0x00 +#define LUT_CMD 0x01 +#define LUT_ADDR 0x02 +#define LUT_CADDR_SDR 0x03 +#define LUT_MODE 0x04 +#define LUT_MODE2 0x05 +#define LUT_MODE4 0x06 +#define LUT_MODE8 0x07 +#define LUT_NXP_WRITE 0x08 +#define LUT_NXP_READ 0x09 +#define LUT_LEARN_SDR 0x0A +#define LUT_DATSZ_SDR 0x0B +#define LUT_DUMMY 0x0C +#define LUT_DUMMY_RWDS_SDR 0x0D +#define LUT_JMP_ON_CS 0x1F +#define LUT_CMD_DDR 0x21 +#define LUT_ADDR_DDR 0x22 +#define LUT_CADDR_DDR 0x23 +#define LUT_MODE_DDR 0x24 +#define LUT_MODE2_DDR 0x25 +#define LUT_MODE4_DDR 0x26 +#define LUT_MODE8_DDR 0x27 +#define LUT_WRITE_DDR 0x28 +#define LUT_READ_DDR 0x29 +#define LUT_LEARN_DDR 0x2A +#define LUT_DATSZ_DDR 0x2B +#define LUT_DUMMY_DDR 0x2C +#define LUT_DUMMY_RWDS_DDR 0x2D + +/* + * Calculate number of required PAD bits for LUT register. + * + * The pad stands for the number of IO lines [0:7]. + * For example, the octal read needs eight IO lines, + * so you should use LUT_PAD(8). This macro + * returns 3 i.e. use eight (2^3) IP lines for read. + */ +#define LUT_PAD(x) (fls(x) - 1) + +/* + * Macro for constructing the LUT entries with the following + * register layout: + * + * --------------------------------------------------- + * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | + * --------------------------------------------------- + */ +#define PAD_SHIFT 8 +#define INSTR_SHIFT 10 +#define OPRND_SHIFT 16 + +/* Macros for constructing the LUT register. */ +#define LUT_DEF(idx, ins, pad, opr) \ + ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \ + (opr)) << (((idx) % 2) * OPRND_SHIFT)) + +#define POLL_TOUT 5000 +#define NXP_FSPI_MAX_CHIPSELECT 4 +#define NXP_FSPI_MIN_IOMAP SZ_4M + +#define DCFG_RCWSR1 0x100 + +/* Access flash memory using IP bus only */ +#define FSPI_QUIRK_USE_IP_ONLY BIT(0) + +struct nxp_fspi_devtype_data { + unsigned int rxfifo; + unsigned int txfifo; + unsigned int ahb_buf_size; + unsigned int quirks; + bool little_endian; +}; + +static struct nxp_fspi_devtype_data imx8mm_data = { + .rxfifo = SZ_512, /* (64 * 64 bits) */ + .txfifo = SZ_1K, /* (128 * 64 bits) */ + .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ + .quirks = 0, + .little_endian = true, /* little-endian */ +}; + +static struct nxp_fspi_devtype_data imx8qxp_data = { + .rxfifo = SZ_512, /* (64 * 64 bits) */ + .txfifo = SZ_1K, /* (128 * 64 bits) */ + .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ + .quirks = 0, + .little_endian = true, /* little-endian */ +}; + +static struct nxp_fspi_devtype_data imx8dxl_data = { + .rxfifo = SZ_512, /* (64 * 64 bits) */ + .txfifo = SZ_1K, /* (128 * 64 bits) */ + .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ + .quirks = FSPI_QUIRK_USE_IP_ONLY, + .little_endian = true, /* little-endian */ +}; + +struct nxp_fspi { + void __iomem *iobase; + void __iomem *ahb_addr; + u32 memmap_phy; + u32 memmap_phy_size; + u32 memmap_start; + u32 memmap_len; + struct clk *clk, *clk_en; + struct device_d *dev; + struct spi_controller ctlr; + const struct nxp_fspi_devtype_data *devtype_data; + struct mutex lock; + int selected; +}; + +static inline int needs_ip_only(struct nxp_fspi *f) +{ + return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY; +} + +/* + * R/W functions for big- or little-endian registers: + * The FSPI controller's endianness is independent of + * the CPU core's endianness. So far, although the CPU + * core is little-endian the FSPI controller can use + * big-endian or little-endian. + */ +static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr) +{ + if (f->devtype_data->little_endian) + iowrite32(val, addr); + else + iowrite32be(val, addr); +} + +static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr) +{ + if (f->devtype_data->little_endian) + return ioread32(addr); + else + return ioread32be(addr); +} + +static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width) +{ + switch (width) { + case 1: + case 2: + case 4: + case 8: + return 0; + } + + return -ENOTSUPP; +} + +static bool nxp_fspi_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); + int ret; + + ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth); + + if (op->addr.nbytes) + ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth); + + if (op->dummy.nbytes) + ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth); + + if (op->data.nbytes) + ret |= nxp_fspi_check_buswidth(f, op->data.buswidth); + + if (ret) + return false; + + /* + * The number of address bytes should be equal to or less than 4 bytes. + */ + if (op->addr.nbytes > 4) + return false; + + /* + * If requested address value is greater than controller assigned + * memory mapped space, return error as it didn't fit in the range + * of assigned address space. + */ + if (op->addr.val >= f->memmap_phy_size) + return false; + + /* Max 64 dummy clock cycles supported */ + if (op->dummy.buswidth && + (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) + return false; + + /* Max data length, check controller limits and alignment */ + if (op->data.dir == SPI_MEM_DATA_IN && + (op->data.nbytes > f->devtype_data->ahb_buf_size || + (op->data.nbytes > f->devtype_data->rxfifo - 4 && + !IS_ALIGNED(op->data.nbytes, 8)))) + return false; + + if (op->data.dir == SPI_MEM_DATA_OUT && + op->data.nbytes > f->devtype_data->txfifo) + return false; + + return true; +} + +/* Instead of busy looping invoke readl_poll_timeout functionality. */ +static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base, + u32 mask, u32 delay_us, + u32 timeout_us, bool c) +{ + u32 reg = 0; + + if (!f->devtype_data->little_endian) + mask = (u32)cpu_to_be32(mask); + + if (c) + return readl_poll_timeout(base, reg, (reg & mask), timeout_us); + else + return readl_poll_timeout(base, reg, !(reg & mask), timeout_us); +} + +/* + * If the slave device content being changed by Write/Erase, need to + * invalidate the AHB buffer. This can be achieved by doing the reset + * of controller after setting MCR0[SWRESET] bit. + */ +static inline void nxp_fspi_invalid(struct nxp_fspi *f) +{ + u32 reg; + int ret; + + reg = fspi_readl(f, f->iobase + FSPI_MCR0); + fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0); + + /* w1c register, wait unit clear */ + ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, + FSPI_MCR0_SWRST, 0, POLL_TOUT, false); + WARN_ON(ret); +} + +static void nxp_fspi_prepare_lut(struct nxp_fspi *f, + const struct spi_mem_op *op) +{ + void __iomem *base = f->iobase; + u32 lutval[4] = {}; + int lutidx = 1, i; + + /* cmd */ + lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), + op->cmd.opcode); + + /* addr bytes */ + if (op->addr.nbytes) { + lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR, + LUT_PAD(op->addr.buswidth), + op->addr.nbytes * 8); + lutidx++; + } + + /* dummy bytes, if needed */ + if (op->dummy.nbytes) { + lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, + /* + * Due to FlexSPI controller limitation number of PAD for dummy + * buswidth needs to be programmed as equal to data buswidth. + */ + LUT_PAD(op->data.buswidth), + op->dummy.nbytes * 8 / + op->dummy.buswidth); + lutidx++; + } + + /* read/write data bytes */ + if (op->data.nbytes) { + lutval[lutidx / 2] |= LUT_DEF(lutidx, + op->data.dir == SPI_MEM_DATA_IN ? + LUT_NXP_READ : LUT_NXP_WRITE, + LUT_PAD(op->data.buswidth), + 0); + lutidx++; + } + + /* stop condition. */ + lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); + + /* unlock LUT */ + fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); + fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); + + /* fill LUT */ + for (i = 0; i < ARRAY_SIZE(lutval); i++) + fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i)); + + dev_dbg((const struct device_d *)f->dev, + "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x], size: 0x%08x\n", + op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], + op->data.nbytes); + + /* lock LUT */ + fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); + fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR); +} + +static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f) +{ + int ret; + + ret = clk_enable(f->clk_en); + if (ret) + return ret; + + ret = clk_enable(f->clk); + if (ret) { + clk_disable(f->clk_en); + return ret; + } + + return 0; +} + +static int nxp_fspi_clk_disable_unprep(struct nxp_fspi *f) +{ + clk_disable(f->clk); + clk_disable(f->clk_en); + + return 0; +} + +/* + * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0 + * register and start base address of the slave device. + * + * (Higher address) + * -------- <-- FLSHB2CR0 + * | B2 | + * | | + * B2 start address --> -------- <-- FLSHB1CR0 + * | B1 | + * | | + * B1 start address --> -------- <-- FLSHA2CR0 + * | A2 | + * | | + * A2 start address --> -------- <-- FLSHA1CR0 + * | A1 | + * | | + * A1 start address --> -------- (Lower address) + * + * + * Start base address defines the starting address range for given CS and + * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS. + * + * But, different targets are having different combinations of number of CS, + * some targets only have single CS or two CS covering controller's full + * memory mapped space area. + * Thus, implementation is being done as independent of the size and number + * of the connected slave device. + * Assign controller memory mapped space size as the size to the connected + * slave device. + * Mark FLSHxxCR0 as zero initially and then assign value only to the selected + * chip-select Flash configuration register. + * + * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the + * memory mapped size of the controller. + * Value for rest of the CS FLSHxxCR0 register would be zero. + * + */ +static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) +{ + unsigned long rate = spi->max_speed_hz; + int ret; + uint64_t size_kb; + + /* + * Return, if previously selected slave device is same as current + * requested slave device. + */ + if (f->selected == spi->chip_select) + return; + + /* Reset FLSHxxCR0 registers */ + fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0); + fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0); + fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0); + fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0); + + /* Assign controller memory mapped space as size, KBytes, of flash. */ + size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size); + + fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + + 4 * spi->chip_select); + + dev_dbg((const struct device_d *)f->dev, "Slave device [CS:%x] selected\n", + spi->chip_select); + + nxp_fspi_clk_disable_unprep(f); + + ret = clk_set_rate(f->clk, rate); + if (ret) + return; + + ret = nxp_fspi_clk_prep_enable(f); + if (ret) + return; + + f->selected = spi->chip_select; +} + +static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op) +{ + /* Read out the data directly from the AHB buffer. */ + memcpy_fromio(op->data.buf.in, + f->ahb_addr + op->addr.val - f->memmap_start, op->data.nbytes); + + return 0; +} + +static void nxp_fspi_fill_txfifo(struct nxp_fspi *f, + const struct spi_mem_op *op) +{ + void __iomem *base = f->iobase; + int i, ret; + u8 *buf = (u8 *) op->data.buf.out; + + /* clear the TX FIFO. */ + fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR); + + /* + * Default value of water mark level is 8 bytes, hence in single + * write request controller can write max 8 bytes of data. + */ + + for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) { + /* Wait for TXFIFO empty */ + ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, + FSPI_INTR_IPTXWE, 0, + POLL_TOUT, true); + WARN_ON(ret); + + fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR); + fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4); + fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); + } + + if (i < op->data.nbytes) { + u32 data = 0; + int j; + /* Wait for TXFIFO empty */ + ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, + FSPI_INTR_IPTXWE, 0, + POLL_TOUT, true); + WARN_ON(ret); + + for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) { + memcpy(&data, buf + i + j, 4); + fspi_writel(f, data, base + FSPI_TFDR + j); + } + fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); + } +} + +static void nxp_fspi_read_rxfifo(struct nxp_fspi *f, + const struct spi_mem_op *op) +{ + void __iomem *base = f->iobase; + int i, ret; + int len = op->data.nbytes; + u8 *buf = (u8 *) op->data.buf.in; + + /* + * Default value of water mark level is 8 bytes, hence in single + * read request controller can read max 8 bytes of data. + */ + for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) { + /* Wait for RXFIFO available */ + ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, + FSPI_INTR_IPRXWA, 0, + POLL_TOUT, true); + WARN_ON(ret); + + *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR); + *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4); + /* move the FIFO pointer */ + fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); + } + + if (i < len) { + u32 tmp; + int size, j; + + buf = op->data.buf.in + i; + /* Wait for RXFIFO available */ + ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, + FSPI_INTR_IPRXWA, 0, + POLL_TOUT, true); + WARN_ON(ret); + + len = op->data.nbytes - i; + for (j = 0; j < op->data.nbytes - i; j += 4) { + tmp = fspi_readl(f, base + FSPI_RFDR + j); + size = min(len, 4); + memcpy(buf + j, &tmp, size); + len -= size; + } + } + + /* invalid the RXFIFO */ + fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR); + /* move the FIFO pointer */ + fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); +} + +static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) +{ + void __iomem *base = f->iobase; + int seqnum = 0; + int err = 0; + u32 reg; + + reg = fspi_readl(f, base + FSPI_IPRXFCR); + /* invalid RXFIFO first */ + reg &= ~FSPI_IPRXFCR_DMA_EN; + reg = reg | FSPI_IPRXFCR_CLR; + fspi_writel(f, reg, base + FSPI_IPRXFCR); + + fspi_writel(f, op->addr.val, base + FSPI_IPCR0); + /* + * Always start the sequence at the same index since we update + * the LUT at each exec_op() call. And also specify the DATA + * length, since it's has not been specified in the LUT. + */ + fspi_writel(f, op->data.nbytes | + (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) | + (seqnum << FSPI_IPCR1_SEQNUM_SHIFT), + base + FSPI_IPCR1); + + /* Trigger the LUT now. */ + fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD); + + /* Wait for the completion. */ + err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, + FSPI_STS0_ARB_IDLE, 1, 1000 * 1000, true); + + /* Invoke IP data read, if request is of data read. */ + if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) + nxp_fspi_read_rxfifo(f, op); + + return err; +} + +static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); + int err = 0; + + mutex_lock(&f->lock); + + /* Wait for controller being ready. */ + err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, + FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true); + WARN_ON(err); + + nxp_fspi_select_mem(f, mem->spi); + + nxp_fspi_prepare_lut(f, op); + /* + * If we have large chunks of data, we read them through the AHB bus by + * accessing the mapped memory. In all other cases we use IP commands + * to access the flash. Read via AHB bus may be corrupted due to + * existence of an errata and therefore discard AHB read in such cases. + */ + if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && + op->data.dir == SPI_MEM_DATA_IN && + !needs_ip_only(f)) { + err = nxp_fspi_read_ahb(f, op); + } else { + if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) + nxp_fspi_fill_txfifo(f, op); + + err = nxp_fspi_do_op(f, op); + } + + /* Invalidate the data in the AHB buffer. */ + nxp_fspi_invalid(f); + + mutex_unlock(&f->lock); + + return err; +} + +static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) +{ + struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); + + if (op->data.dir == SPI_MEM_DATA_OUT) { + if (op->data.nbytes > f->devtype_data->txfifo) + op->data.nbytes = f->devtype_data->txfifo; + } else { + if (op->data.nbytes > f->devtype_data->ahb_buf_size) + op->data.nbytes = f->devtype_data->ahb_buf_size; + else if (op->data.nbytes > (f->devtype_data->rxfifo - 4)) + op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); + } + + /* Limit data bytes to RX FIFO in case of IP read only */ + if (op->data.dir == SPI_MEM_DATA_IN && + needs_ip_only(f) && + op->data.nbytes > f->devtype_data->rxfifo) + op->data.nbytes = f->devtype_data->rxfifo; + + return 0; +} + +static int nxp_fspi_setup(struct spi_device *spi) +{ + struct nxp_fspi *f = container_of(spi->controller, struct nxp_fspi, ctlr); + void __iomem *base = f->iobase; + int ret, i; + u32 reg; + + /* disable and unprepare clock to avoid glitch pass to controller */ + nxp_fspi_clk_disable_unprep(f); + + /* the default frequency, we will change it later if necessary. */ + ret = clk_set_rate(f->clk, 20000000); + if (ret) + return ret; + + ret = nxp_fspi_clk_prep_enable(f); + if (ret) + return ret; + + /* Reset the module */ + /* w1c register, wait unit clear */ + ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, + FSPI_MCR0_SWRST, 0, POLL_TOUT, false); + WARN_ON(ret); + + /* Disable the module */ + fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); + + /* Reset the DLL register to default value */ + fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR); + fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR); + + /* enable module */ + fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | + FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN, + base + FSPI_MCR0); + + /* + * Disable same device enable bit and configure all slave devices + * independently. + */ + reg = fspi_readl(f, f->iobase + FSPI_MCR2); + reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN); + fspi_writel(f, reg, base + FSPI_MCR2); + + /* AHB configuration for access buffer 0~7. */ + for (i = 0; i < 7; i++) + fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i); + + /* + * Set ADATSZ with the maximum AHB buffer size to improve the read + * performance. + */ + fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 | + FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0); + + /* prefetch and no start address alignment limitation */ + fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT, + base + FSPI_AHBCR); + + /* AHB Read - Set lut sequence ID for all CS. */ + fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2); + fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2); + fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2); + fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2); + + f->selected = -1; + + return 0; +} + +static const char *nxp_fspi_get_name(struct spi_mem *mem) +{ + struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); + struct device_d *dev = (struct device_d *)&mem->spi->dev; + const char *name; + + /* Set custom name derived from the platform_device of the controller. + */ + if (of_get_available_child_count(f->dev->device_node) == 1) + return dev_name(f->dev); + + name = basprintf("%s-%d", dev_name(f->dev), mem->spi->chip_select); + if (!name) { + dev_err(dev, "failed to get memory for custom flash name\n"); + return ERR_PTR(-ENOMEM); + } + + return name; +} + +static const struct spi_controller_mem_ops nxp_fspi_mem_ops = { + .adjust_op_size = nxp_fspi_adjust_op_size, + .supports_op = nxp_fspi_supports_op, + .exec_op = nxp_fspi_exec_op, + .get_name = nxp_fspi_get_name, +}; + +static int nxp_fspi_probe(struct device_d *dev) +{ + struct spi_controller *ctlr; + struct resource *res; + struct nxp_fspi *f; + int ret; + + f = xzalloc(sizeof(*f)); + + f->dev = dev; + f->devtype_data = of_device_get_match_data(dev); + if (!f->devtype_data) { + ret = -ENODEV; + goto err_put_ctrl; + } + + ctlr = &f->ctlr; + + /* ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | \ */ + /* SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL; */ + + ctlr->dev = dev; + ctlr->bus_num = dev->id; + ctlr->setup = nxp_fspi_setup; + ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT; + ctlr->mem_ops = &nxp_fspi_mem_ops; + + spi_controller_set_devdata(ctlr, f); + + /* find the resources */ + res = dev_request_mem_resource(dev, 0); + f->iobase = IOMEM(res->start); + if (IS_ERR(f->iobase)) { + ret = PTR_ERR(f->iobase); + goto err_put_ctrl; + } + + res = dev_request_mem_resource(dev, 1); + f->ahb_addr = IOMEM(res->start); + if (IS_ERR(f->ahb_addr)) { + ret = PTR_ERR(f->ahb_addr); + goto err_put_ctrl; + } + + /* assign memory mapped starting address and mapped size. */ + f->memmap_phy = res->start; + f->memmap_phy_size = resource_size(res); + + /* find the clocks */ + f->clk_en = clk_get(dev, "fspi_en"); + if (IS_ERR(f->clk_en)) { + ret = PTR_ERR(f->clk_en); + goto err_put_ctrl; + } + + f->clk = clk_get(dev, "fspi"); + if (IS_ERR(f->clk)) { + ret = PTR_ERR(f->clk); + goto err_put_ctrl; + } + + ret = nxp_fspi_clk_prep_enable(f); + if (ret) { + dev_err(dev, "can not enable the clock\n"); + goto err_put_ctrl; + } + + mutex_init(&f->lock); + + ret = spi_register_controller(ctlr); + if (ret) + goto err_disable_clk; + + return 0; + +err_disable_clk: + nxp_fspi_clk_disable_unprep(f); + +err_put_ctrl: + dev_err(dev, "NXP FSPI probe failed\n"); + return ret; +} + +static const struct of_device_id nxp_fspi_dt_ids[] = { + { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, }, + { .compatible = "nxp,imx8mn-fspi", .data = (void *)&imx8mm_data, }, + { .compatible = "nxp,imx8mp-fspi", .data = (void *)&imx8mm_data, }, + { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, }, + { .compatible = "nxp,imx8dxl-fspi", .data = (void *)&imx8dxl_data, }, + { /* sentinel */ } +}; + +static struct driver_d nxp_fspi_driver = { + .name = "nxp-fspi", + .probe = nxp_fspi_probe, + .of_compatible = DRV_OF_COMPAT(nxp_fspi_dt_ids), +}; +device_platform_driver(nxp_fspi_driver); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index facfb3a95b..068504557b 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1421,20 +1421,6 @@ static int ehci_probe(struct device_d *dev) */ data.flags = EHCI_HAS_TT; - iores = dev_request_mem_resource(dev, 0); - if (IS_ERR(iores)) - return PTR_ERR(iores); - data.hccr = IOMEM(iores->start); - - if (dev->num_resources > 1) { - iores = dev_request_mem_resource(dev, 1); - if (IS_ERR(iores)) - return PTR_ERR(iores); - data.hcor = IOMEM(iores->start); - } - else - data.hcor = NULL; - usb2_generic_phy = phy_optional_get(dev, "usb"); if (IS_ERR(usb2_generic_phy)) return PTR_ERR(usb2_generic_phy); @@ -1456,6 +1442,20 @@ static int ehci_probe(struct device_d *dev) if (ret) return ret; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + data.hccr = IOMEM(iores->start); + + if (dev->num_resources > 1) { + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + data.hcor = IOMEM(iores->start); + } + else + data.hcor = NULL; + ehci = ehci_register(dev, &data); if (IS_ERR(ehci)) return PTR_ERR(ehci); diff --git a/drivers/watchdog/wdat_wdt.c b/drivers/watchdog/wdat_wdt.c index 39e8cc4a3d..f58aee1283 100644 --- a/drivers/watchdog/wdat_wdt.c +++ b/drivers/watchdog/wdat_wdt.c @@ -48,12 +48,12 @@ enum acpi_wdat_instructions { /* WDAT Instruction Entries (actions) */ struct __packed acpi_wdat_entry { - u8 action; - u8 instruction; - u16 reserved; - struct acpi_generic_address register_region; - u32 value; /* Value used with Read/Write register */ - u32 mask; /* Bitmask required for this register instruction */ + u8 action; + u8 instruction; + u16 reserved; + struct acpi_generic_address register_region; + u32 value; /* Value used with Read/Write register */ + u32 mask; /* Bitmask required for this register instruction */ }; /** @@ -82,7 +82,7 @@ struct wdat_instruction { struct wdat_wdt { struct watchdog wdd; unsigned int period; - bool stopped_in_sleep; + bool stopped_in_sleep; bool stopped; struct list_head *instructions[MAX_WDAT_ACTIONS]; }; @@ -90,17 +90,17 @@ struct wdat_wdt { struct __packed acpi_table_wdat { struct acpi_table_header header; /* Common ACPI table header */ u32 header_length; /* Watchdog Header Length */ - u16 pci_segment; /* PCI Segment number */ - u8 pci_bus; /* PCI Bus number */ - u8 pci_device; /* PCI Device number */ - u8 pci_function; /* PCI Function number */ - u8 reserved[3]; - u32 timer_period; /* Period of one timer count (msec) */ - u32 max_count; /* Maximum counter value supported */ - u32 min_count; /* Minimum counter value */ - u8 flags; - u8 reserved2[3]; - u32 nr_entries; /* Number of watchdog entries that follow */ + u16 pci_segment; /* PCI Segment number */ + u8 pci_bus; /* PCI Bus number */ + u8 pci_device; /* PCI Device number */ + u8 pci_function; /* PCI Function number */ + u8 reserved[3]; + u32 timer_period; /* Period of one timer count (msec) */ + u32 max_count; /* Maximum counter value supported */ + u32 min_count; /* Minimum counter value */ + u8 flags; + u8 reserved2[3]; + u32 nr_entries; /* Number of watchdog entries that follow */ struct acpi_wdat_entry entries[]; }; diff --git a/dts/Bindings/arm/atmel-at91.yaml b/dts/Bindings/arm/atmel-at91.yaml index c612e1f48d..ff91df04f9 100644 --- a/dts/Bindings/arm/atmel-at91.yaml +++ b/dts/Bindings/arm/atmel-at91.yaml @@ -8,7 +8,8 @@ title: Atmel AT91 device tree bindings. maintainers: - Alexandre Belloni <alexandre.belloni@bootlin.com> - - Ludovic Desroches <ludovic.desroches@microchip.com> + - Claudiu Beznea <claudiu.beznea@microchip.com> + - Nicolas Ferre <nicolas.ferre@microchip.com> description: | Boards with a SoC of the Atmel AT91 or SMART family shall have the following diff --git a/dts/Bindings/arm/freescale/fsl,layerscape-dcfg.txt b/dts/Bindings/arm/freescale/fsl,layerscape-dcfg.txt index b5cb374dc4..10a91cc8b9 100644 --- a/dts/Bindings/arm/freescale/fsl,layerscape-dcfg.txt +++ b/dts/Bindings/arm/freescale/fsl,layerscape-dcfg.txt @@ -8,7 +8,7 @@ Required properties: - compatible: Should contain a chip-specific compatible string, Chip-specific strings are of the form "fsl,<chip>-dcfg", The following <chip>s are known to be supported: - ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. + ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a - reg : should contain base address and length of DCFG memory-mapped registers diff --git a/dts/Bindings/arm/omap/omap.txt b/dts/Bindings/arm/omap/omap.txt index e77635c542..fa8b31660c 100644 --- a/dts/Bindings/arm/omap/omap.txt +++ b/dts/Bindings/arm/omap/omap.txt @@ -119,6 +119,9 @@ Boards (incomplete list of examples): - OMAP3 BeagleBoard : Low cost community board compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3" +- OMAP3 BeagleBoard A to B4 : Early BeagleBoard revisions A to B4 with a timer quirk + compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3" + - OMAP3 Tobi with Overo : Commercial expansion board with daughter board compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3" diff --git a/dts/Bindings/clock/qoriq-clock.txt b/dts/Bindings/clock/qoriq-clock.txt index f7d48f23da..10119d9ef4 100644 --- a/dts/Bindings/clock/qoriq-clock.txt +++ b/dts/Bindings/clock/qoriq-clock.txt @@ -44,6 +44,7 @@ Required properties: * "fsl,ls1046a-clockgen" * "fsl,ls1088a-clockgen" * "fsl,ls2080a-clockgen" + * "fsl,lx2160a-clockgen" Chassis-version clock strings include: * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks diff --git a/dts/Bindings/gpio/sifive,gpio.yaml b/dts/Bindings/gpio/sifive,gpio.yaml index e04349567e..427c5873f9 100644 --- a/dts/Bindings/gpio/sifive,gpio.yaml +++ b/dts/Bindings/gpio/sifive,gpio.yaml @@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SiFive GPIO controller maintainers: - - Yash Shah <yash.shah@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> properties: diff --git a/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 0dfa6b26e0..27092c6a86 100644 --- a/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -35,6 +35,10 @@ description: contains a specific memory layout, which is documented in chapter 8 of the SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. + The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the + T-HEAD PLIC implementation requires setting a delegation bit to allow access + from S-mode. So add thead,c900-plic to distinguish them. + maintainers: - Sagar Kadam <sagar.kadam@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> @@ -42,12 +46,17 @@ maintainers: properties: compatible: - items: - - enum: - - sifive,fu540-c000-plic - - starfive,jh7100-plic - - canaan,k210-plic - - const: sifive,plic-1.0.0 + oneOf: + - items: + - enum: + - sifive,fu540-c000-plic + - starfive,jh7100-plic + - canaan,k210-plic + - const: sifive,plic-1.0.0 + - items: + - enum: + - allwinner,sun20i-d1-plic + - const: thead,c900-plic reg: maxItems: 1 diff --git a/dts/Bindings/mfd/ti,j721e-system-controller.yaml b/dts/Bindings/mfd/ti,j721e-system-controller.yaml index 272832e9f8..fa86691ebf 100644 --- a/dts/Bindings/mfd/ti,j721e-system-controller.yaml +++ b/dts/Bindings/mfd/ti,j721e-system-controller.yaml @@ -20,7 +20,7 @@ description: | maintainers: - Kishon Vijay Abraham I <kishon@ti.com> - - Roger Quadros <rogerq@ti.com + - Roger Quadros <rogerq@kernel.org> properties: compatible: diff --git a/dts/Bindings/net/qcom,ipa.yaml b/dts/Bindings/net/qcom,ipa.yaml index b86edf67ce..58ecc62adf 100644 --- a/dts/Bindings/net/qcom,ipa.yaml +++ b/dts/Bindings/net/qcom,ipa.yaml @@ -107,6 +107,10 @@ properties: - const: imem - const: config + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the AOSS side-channel message RAM + qcom,smem-states: $ref: /schemas/types.yaml#/definitions/phandle-array description: State bits used in by the AP to signal the modem. @@ -222,6 +226,8 @@ examples: "imem", "config"; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; qcom,smem-state-names = "ipa-clock-enabled-valid", diff --git a/dts/Bindings/phy/ti,omap-usb2.yaml b/dts/Bindings/phy/ti,omap-usb2.yaml index cbbf5e8b11..f78d3246fb 100644 --- a/dts/Bindings/phy/ti,omap-usb2.yaml +++ b/dts/Bindings/phy/ti,omap-usb2.yaml @@ -8,7 +8,7 @@ title: OMAP USB2 PHY maintainers: - Kishon Vijay Abraham I <kishon@ti.com> - - Roger Quadros <rogerq@ti.com> + - Roger Quadros <rogerq@kernel.org> properties: compatible: diff --git a/dts/Bindings/pwm/pwm-sifive.yaml b/dts/Bindings/pwm/pwm-sifive.yaml index 84e66913d0..db41cd7bf1 100644 --- a/dts/Bindings/pwm/pwm-sifive.yaml +++ b/dts/Bindings/pwm/pwm-sifive.yaml @@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SiFive PWM controller maintainers: - - Yash Shah <yash.shah@sifive.com> - Sagar Kadam <sagar.kadam@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> diff --git a/dts/Bindings/riscv/sifive-l2-cache.yaml b/dts/Bindings/riscv/sifive-l2-cache.yaml index 2b1f916038..e2d330bd46 100644 --- a/dts/Bindings/riscv/sifive-l2-cache.yaml +++ b/dts/Bindings/riscv/sifive-l2-cache.yaml @@ -9,7 +9,6 @@ title: SiFive L2 Cache Controller maintainers: - Sagar Kadam <sagar.kadam@sifive.com> - - Yash Shah <yash.shah@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> description: diff --git a/dts/Bindings/sound/google,cros-ec-codec.yaml b/dts/Bindings/sound/google,cros-ec-codec.yaml index 77adbebed8..c3e9f34854 100644 --- a/dts/Bindings/sound/google,cros-ec-codec.yaml +++ b/dts/Bindings/sound/google,cros-ec-codec.yaml @@ -8,6 +8,7 @@ title: Audio codec controlled by ChromeOS EC maintainers: - Cheng-Yi Chiang <cychiang@chromium.org> + - Tzung-Bi Shih <tzungbi@google.com> description: | Google's ChromeOS EC codec is a digital mic codec provided by the diff --git a/dts/Bindings/spi/spi-peripheral-props.yaml b/dts/Bindings/spi/spi-peripheral-props.yaml index 5dd209206e..3ec2d7b837 100644 --- a/dts/Bindings/spi/spi-peripheral-props.yaml +++ b/dts/Bindings/spi/spi-peripheral-props.yaml @@ -23,8 +23,9 @@ properties: minItems: 1 maxItems: 256 items: - minimum: 0 - maximum: 256 + items: + - minimum: 0 + maximum: 256 description: Chip select used by the device. diff --git a/dts/Bindings/usb/dwc2.yaml b/dts/Bindings/usb/dwc2.yaml index f00867ebc1..481aaa09f3 100644 --- a/dts/Bindings/usb/dwc2.yaml +++ b/dts/Bindings/usb/dwc2.yaml @@ -53,6 +53,7 @@ properties: - const: st,stm32mp15-hsotg - const: snps,dwc2 - const: samsung,s3c6400-hsotg + - const: intel,socfpga-agilex-hsotg reg: maxItems: 1 diff --git a/dts/Bindings/usb/ti,j721e-usb.yaml b/dts/Bindings/usb/ti,j721e-usb.yaml index a634774c53..eedde385d2 100644 --- a/dts/Bindings/usb/ti,j721e-usb.yaml +++ b/dts/Bindings/usb/ti,j721e-usb.yaml @@ -7,7 +7,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller maintainers: - - Roger Quadros <rogerq@ti.com> + - Roger Quadros <rogerq@kernel.org> properties: compatible: diff --git a/dts/Bindings/usb/ti,keystone-dwc3.yaml b/dts/Bindings/usb/ti,keystone-dwc3.yaml index f6e91a5fd8..4f7a212fdd 100644 --- a/dts/Bindings/usb/ti,keystone-dwc3.yaml +++ b/dts/Bindings/usb/ti,keystone-dwc3.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: TI Keystone Soc USB Controller maintainers: - - Roger Quadros <rogerq@ti.com> + - Roger Quadros <rogerq@kernel.org> properties: compatible: diff --git a/dts/include/dt-bindings/clock/dra7.h b/dts/include/dt-bindings/clock/dra7.h index 7d57063b8a..29ff6b8958 100644 --- a/dts/include/dt-bindings/clock/dra7.h +++ b/dts/include/dt-bindings/clock/dra7.h @@ -84,17 +84,10 @@ #define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -/* iva clocks */ -#define DRA7_IVA_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_SL2IF_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) - /* dss clocks */ #define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) -/* gpu clocks */ -#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - /* l3init clocks */ #define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) @@ -267,10 +260,17 @@ #define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +/* iva clocks */ +#define DRA7_IVA_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_SL2IF_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) + /* dss clocks */ #define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +/* gpu clocks */ +#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) + /* l3init clocks */ #define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) diff --git a/dts/include/dt-bindings/input/linux-event-codes.h b/dts/include/dt-bindings/input/linux-event-codes.h index 225ec87d4f..7989d9483e 100644 --- a/dts/include/dt-bindings/input/linux-event-codes.h +++ b/dts/include/dt-bindings/input/linux-event-codes.h @@ -278,7 +278,8 @@ #define KEY_PAUSECD 201 #define KEY_PROG3 202 #define KEY_PROG4 203 -#define KEY_DASHBOARD 204 /* AL Dashboard */ +#define KEY_ALL_APPLICATIONS 204 /* AC Desktop Show All Applications */ +#define KEY_DASHBOARD KEY_ALL_APPLICATIONS #define KEY_SUSPEND 205 #define KEY_CLOSE 206 /* AC Close */ #define KEY_PLAY 207 @@ -612,6 +613,7 @@ #define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */ #define KEY_KBD_LAYOUT_NEXT 0x248 /* AC Next Keyboard Layout Select */ #define KEY_EMOJI_PICKER 0x249 /* Show/hide emoji picker (HUTRR101) */ +#define KEY_DICTATE 0x24a /* Start or Stop Voice Dictation Session (HUTRR99) */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ diff --git a/dts/src/arm/am335x-wega.dtsi b/dts/src/arm/am335x-wega.dtsi index 673159d93a..f957fea820 100644 --- a/dts/src/arm/am335x-wega.dtsi +++ b/dts/src/arm/am335x-wega.dtsi @@ -55,7 +55,7 @@ 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */ >; tx-num-evt = <16>; - rt-num-evt = <16>; + rx-num-evt = <16>; status = "okay"; }; diff --git a/dts/src/arm/dra7.dtsi b/dts/src/arm/dra7.dtsi index 6b485cbed8..42bff11765 100644 --- a/dts/src/arm/dra7.dtsi +++ b/dts/src/arm/dra7.dtsi @@ -160,7 +160,7 @@ target-module@48210000 { compatible = "ti,sysc-omap4-simple", "ti,sysc"; power-domains = <&prm_mpu>; - clocks = <&mpu_clkctrl DRA7_MPU_CLKCTRL 0>; + clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; @@ -875,10 +875,10 @@ <0x58000014 4>; reg-names = "rev", "syss"; ti,syss-mask = <1>; - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>, - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>, - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 11>; clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; #address-cells = <1>; #size-cells = <1>; @@ -912,7 +912,7 @@ SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,syss-mask = <1>; - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; @@ -939,8 +939,8 @@ <SYSC_IDLE_SMART>, <SYSC_IDLE_SMART_WKUP>; ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; clock-names = "fck", "dss_clk"; #address-cells = <1>; #size-cells = <1>; @@ -979,7 +979,7 @@ compatible = "vivante,gc"; reg = <0x0 0x700>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dss_clkctrl DRA7_BB2D_CLKCTRL 0>; + clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>; clock-names = "core"; }; }; @@ -1333,7 +1333,7 @@ ti,no-reset-on-init; ti,no-idle; timer@0 { - assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; + assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; assigned-clock-parents = <&sys_32k_ck>; }; }; diff --git a/dts/src/arm/imx23-evk.dts b/dts/src/arm/imx23-evk.dts index 8cbaf1c811..3b609d987d 100644 --- a/dts/src/arm/imx23-evk.dts +++ b/dts/src/arm/imx23-evk.dts @@ -79,7 +79,6 @@ MX23_PAD_LCD_RESET__GPIO_1_18 MX23_PAD_PWM3__GPIO_1_29 MX23_PAD_PWM4__GPIO_1_30 - MX23_PAD_SSP1_DETECT__SSP1_DETECT >; fsl,drive-strength = <MXS_DRIVE_4mA>; fsl,voltage = <MXS_VOLTAGE_HIGH>; diff --git a/dts/src/arm/imx6qdl-udoo.dtsi b/dts/src/arm/imx6qdl-udoo.dtsi index d07d8f8345..ccfa8e320b 100644 --- a/dts/src/arm/imx6qdl-udoo.dtsi +++ b/dts/src/arm/imx6qdl-udoo.dtsi @@ -5,6 +5,8 @@ * Author: Fabio Estevam <fabio.estevam@freescale.com> */ +#include <dt-bindings/gpio/gpio.h> + / { aliases { backlight = &backlight; @@ -226,6 +228,7 @@ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 >; }; @@ -304,7 +307,7 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/dts/src/arm/imx7ulp.dtsi b/dts/src/arm/imx7ulp.dtsi index b7ea37ad4e..bcec98b964 100644 --- a/dts/src/arm/imx7ulp.dtsi +++ b/dts/src/arm/imx7ulp.dtsi @@ -259,7 +259,7 @@ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pcc2 IMX7ULP_CLK_WDG1>; assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; - assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; timeout-sec = <40>; }; diff --git a/dts/src/arm/meson.dtsi b/dts/src/arm/meson.dtsi index 3be7cba603..26eaba3fa9 100644 --- a/dts/src/arm/meson.dtsi +++ b/dts/src/arm/meson.dtsi @@ -59,7 +59,7 @@ }; uart_A: serial@84c0 { - compatible = "amlogic,meson6-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson6-uart"; reg = <0x84c0 0x18>; interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; fifo-size = <128>; @@ -67,7 +67,7 @@ }; uart_B: serial@84dc { - compatible = "amlogic,meson6-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson6-uart"; reg = <0x84dc 0x18>; interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; status = "disabled"; @@ -105,7 +105,7 @@ }; uart_C: serial@8700 { - compatible = "amlogic,meson6-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson6-uart"; reg = <0x8700 0x18>; interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; status = "disabled"; @@ -228,7 +228,7 @@ }; uart_AO: serial@4c0 { - compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart"; reg = <0x4c0 0x18>; interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; status = "disabled"; diff --git a/dts/src/arm/meson8.dtsi b/dts/src/arm/meson8.dtsi index f80ddc98d3..9997a5d033 100644 --- a/dts/src/arm/meson8.dtsi +++ b/dts/src/arm/meson8.dtsi @@ -736,27 +736,27 @@ }; &uart_AO { - compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart"; + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &uart_A { - compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8-uart"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &uart_B { - compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8-uart"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &uart_C { - compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8-uart"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &usb0 { diff --git a/dts/src/arm/meson8b.dtsi b/dts/src/arm/meson8b.dtsi index b49b7cbaed..94f1c03dec 100644 --- a/dts/src/arm/meson8b.dtsi +++ b/dts/src/arm/meson8b.dtsi @@ -724,27 +724,27 @@ }; &uart_AO { - compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart"; + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &uart_A { - compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8b-uart"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &uart_B { - compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8b-uart"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &uart_C { - compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8b-uart"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &usb0 { diff --git a/dts/src/arm/omap3-beagle-ab4.dts b/dts/src/arm/omap3-beagle-ab4.dts new file mode 100644 index 0000000000..990ff2d846 --- /dev/null +++ b/dts/src/arm/omap3-beagle-ab4.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include "omap3-beagle.dts" + +/ { + model = "TI OMAP3 BeagleBoard A to B4"; + compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3"; +}; + +/* + * Workaround for capacitor C70 issue, see "Boards revision A and < B5" + * section at https://elinux.org/BeagleBoard_Community + */ + +/* Unusable as clocksource because of unreliable oscillator */ +&counter32k { + status = "disabled"; +}; + +/* Unusable as clockevent because of unreliable oscillator, allow to idle */ +&timer1_target { + /delete-property/ti,no-reset-on-init; + /delete-property/ti,no-idle; + timer@0 { + /delete-property/ti,timer-alwon; + }; +}; + +/* Preferred always-on timer for clocksource */ +&timer12_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + /* Always clocked by secure_32k_fck */ + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt2_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; diff --git a/dts/src/arm/omap3-beagle.dts b/dts/src/arm/omap3-beagle.dts index f9f34b8458..0548b39133 100644 --- a/dts/src/arm/omap3-beagle.dts +++ b/dts/src/arm/omap3-beagle.dts @@ -304,39 +304,6 @@ phys = <0 &hsusb2_phy>; }; -/* Unusable as clocksource because of unreliable oscillator */ -&counter32k { - status = "disabled"; -}; - -/* Unusable as clockevent because if unreliable oscillator, allow to idle */ -&timer1_target { - /delete-property/ti,no-reset-on-init; - /delete-property/ti,no-idle; - timer@0 { - /delete-property/ti,timer-alwon; - }; -}; - -/* Preferred always-on timer for clocksource */ -&timer12_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - /* Always clocked by secure_32k_fck */ - }; -}; - -/* Preferred timer for clockevent */ -&timer2_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&gpt2_fck>; - assigned-clock-parents = <&sys_ck>; - }; -}; - &twl_gpio { ti,use-leds; /* pullups: BIT(1) */ diff --git a/dts/src/arm/omap3-devkit8000-common.dtsi b/dts/src/arm/omap3-devkit8000-common.dtsi index 5e55198e45..54cd37336b 100644 --- a/dts/src/arm/omap3-devkit8000-common.dtsi +++ b/dts/src/arm/omap3-devkit8000-common.dtsi @@ -158,6 +158,24 @@ status = "disabled"; }; +/* Unusable as clockevent because if unreliable oscillator, allow to idle */ +&timer1_target { + /delete-property/ti,no-reset-on-init; + /delete-property/ti,no-idle; + timer@0 { + /delete-property/ti,timer-alwon; + }; +}; + +/* Preferred timer for clockevent */ +&timer12_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + /* Always clocked by secure_32k_fck */ + }; +}; + &twl_gpio { ti,use-leds; /* diff --git a/dts/src/arm/omap3-devkit8000.dts b/dts/src/arm/omap3-devkit8000.dts index c2995a2807..162d0726b0 100644 --- a/dts/src/arm/omap3-devkit8000.dts +++ b/dts/src/arm/omap3-devkit8000.dts @@ -14,36 +14,3 @@ display2 = &tv0; }; }; - -/* Unusable as clocksource because of unreliable oscillator */ -&counter32k { - status = "disabled"; -}; - -/* Unusable as clockevent because if unreliable oscillator, allow to idle */ -&timer1_target { - /delete-property/ti,no-reset-on-init; - /delete-property/ti,no-idle; - timer@0 { - /delete-property/ti,timer-alwon; - }; -}; - -/* Preferred always-on timer for clocksource */ -&timer12_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - /* Always clocked by secure_32k_fck */ - }; -}; - -/* Preferred timer for clockevent */ -&timer2_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&gpt2_fck>; - assigned-clock-parents = <&sys_ck>; - }; -}; diff --git a/dts/src/arm/rk322x.dtsi b/dts/src/arm/rk322x.dtsi index 8eed9e3a92..5868eb512f 100644 --- a/dts/src/arm/rk322x.dtsi +++ b/dts/src/arm/rk322x.dtsi @@ -718,8 +718,8 @@ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; assigned-clocks = <&cru SCLK_HDMI_PHY>; assigned-clock-parents = <&hdmi_phy>; - clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; - clock-names = "isfr", "iahb", "cec"; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; + clock-names = "iahb", "isfr", "cec"; pinctrl-names = "default"; pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; resets = <&cru SRST_HDMI_P>; diff --git a/dts/src/arm/rk3288.dtsi b/dts/src/arm/rk3288.dtsi index aaaa618757..45a9d9b908 100644 --- a/dts/src/arm/rk3288.dtsi +++ b/dts/src/arm/rk3288.dtsi @@ -971,7 +971,7 @@ status = "disabled"; }; - crypto: cypto-controller@ff8a0000 { + crypto: crypto@ff8a0000 { compatible = "rockchip,rk3288-crypto"; reg = <0x0 0xff8a0000 0x0 0x4000>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/src/arm/spear320-hmi.dts b/dts/src/arm/spear320-hmi.dts index 367ba48aac..b587e4ec11 100644 --- a/dts/src/arm/spear320-hmi.dts +++ b/dts/src/arm/spear320-hmi.dts @@ -235,7 +235,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x41>; - irq-over-gpio; irq-gpios = <&gpiopinctrl 29 0x4>; id = <0>; blocks = <0x5>; diff --git a/dts/src/arm/ste-ux500-samsung-skomer.dts b/dts/src/arm/ste-ux500-samsung-skomer.dts index 580ca497f3..f8c5899fbd 100644 --- a/dts/src/arm/ste-ux500-samsung-skomer.dts +++ b/dts/src/arm/ste-ux500-samsung-skomer.dts @@ -185,10 +185,6 @@ cap-sd-highspeed; cap-mmc-highspeed; /* All direction control is used */ - st,sig-dir-cmd; - st,sig-dir-dat0; - st,sig-dir-dat2; - st,sig-dir-dat31; st,sig-pin-fbclk; full-pwr-cycle; vmmc-supply = <&ab8500_ldo_aux3_reg>; diff --git a/dts/src/arm/tegra124-nyan-big.dts b/dts/src/arm/tegra124-nyan-big.dts index 1d2aac2cb6..fdc1d64dff 100644 --- a/dts/src/arm/tegra124-nyan-big.dts +++ b/dts/src/arm/tegra124-nyan-big.dts @@ -13,12 +13,15 @@ "google,nyan-big-rev1", "google,nyan-big-rev0", "google,nyan-big", "google,nyan", "nvidia,tegra124"; - panel: panel { - compatible = "auo,b133xtn01"; - - power-supply = <&vdd_3v3_panel>; - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; + host1x@50000000 { + dpaux@545c0000 { + aux-bus { + panel: panel { + compatible = "auo,b133xtn01"; + backlight = <&backlight>; + }; + }; + }; }; mmc@700b0400 { /* SD Card on this bus */ diff --git a/dts/src/arm/tegra124-nyan-blaze.dts b/dts/src/arm/tegra124-nyan-blaze.dts index 677babde64..abdf445682 100644 --- a/dts/src/arm/tegra124-nyan-blaze.dts +++ b/dts/src/arm/tegra124-nyan-blaze.dts @@ -15,12 +15,15 @@ "google,nyan-blaze-rev0", "google,nyan-blaze", "google,nyan", "nvidia,tegra124"; - panel: panel { - compatible = "samsung,ltn140at29-301"; - - power-supply = <&vdd_3v3_panel>; - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; + host1x@50000000 { + dpaux@545c0000 { + aux-bus { + panel: panel { + compatible = "samsung,ltn140at29-301"; + backlight = <&backlight>; + }; + }; + }; }; sound { diff --git a/dts/src/arm/tegra124-venice2.dts b/dts/src/arm/tegra124-venice2.dts index 232c90604d..6a9592ceb5 100644 --- a/dts/src/arm/tegra124-venice2.dts +++ b/dts/src/arm/tegra124-venice2.dts @@ -48,6 +48,13 @@ dpaux@545c0000 { vdd-supply = <&vdd_3v3_panel>; status = "okay"; + + aux-bus { + panel: panel { + compatible = "lg,lp129qe"; + backlight = <&backlight>; + }; + }; }; }; @@ -1080,13 +1087,6 @@ }; }; - panel: panel { - compatible = "lg,lp129qe"; - power-supply = <&vdd_3v3_panel>; - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; - }; - vdd_mux: regulator-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; diff --git a/dts/src/arm64/amlogic/meson-g12-common.dtsi b/dts/src/arm64/amlogic/meson-g12-common.dtsi index 517519e6e8..f84d4b489e 100644 --- a/dts/src/arm64/amlogic/meson-g12-common.dtsi +++ b/dts/src/arm64/amlogic/meson-g12-common.dtsi @@ -107,6 +107,12 @@ no-map; }; + /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ + secmon_reserved_bl32: secmon@5300000 { + reg = <0x0 0x05300000 0x0 0x2000000>; + no-map; + }; + linux,cma { compatible = "shared-dma-pool"; reusable; diff --git a/dts/src/arm64/amlogic/meson-g12a-sei510.dts b/dts/src/arm64/amlogic/meson-g12a-sei510.dts index d8838dde0f..4fb31c2ba3 100644 --- a/dts/src/arm64/amlogic/meson-g12a-sei510.dts +++ b/dts/src/arm64/amlogic/meson-g12a-sei510.dts @@ -157,14 +157,6 @@ regulator-always-on; }; - reserved-memory { - /* TEE Reserved Memory */ - bl32_reserved: bl32@5000000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - }; - sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; diff --git a/dts/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi b/dts/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi index 3e968b2441..fd3fa82e4c 100644 --- a/dts/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi +++ b/dts/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi @@ -17,7 +17,7 @@ rtc1 = &vrtc; }; - dioo2133: audio-amplifier-0 { + dio2133: audio-amplifier-0 { compatible = "simple-audio-amplifier"; enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; VCC-supply = <&vcc_5v>; @@ -219,7 +219,7 @@ audio-widgets = "Line", "Lineout"; audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>, <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>, - <&dioo2133>; + <&dio2133>; audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", "TDMOUT_B IN 1", "FRDDR_B OUT 1", "TDMOUT_B IN 2", "FRDDR_C OUT 1", diff --git a/dts/src/arm64/amlogic/meson-gx.dtsi b/dts/src/arm64/amlogic/meson-gx.dtsi index 6b457b2c30..aa14ea017a 100644 --- a/dts/src/arm64/amlogic/meson-gx.dtsi +++ b/dts/src/arm64/amlogic/meson-gx.dtsi @@ -49,6 +49,12 @@ no-map; }; + /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ + secmon_reserved_bl32: secmon@5300000 { + reg = <0x0 0x05300000 0x0 0x2000000>; + no-map; + }; + linux,cma { compatible = "shared-dma-pool"; reusable; diff --git a/dts/src/arm64/amlogic/meson-sm1-bananapi-m5.dts b/dts/src/arm64/amlogic/meson-sm1-bananapi-m5.dts index 212c6aa5a3..5751c48620 100644 --- a/dts/src/arm64/amlogic/meson-sm1-bananapi-m5.dts +++ b/dts/src/arm64/amlogic/meson-sm1-bananapi-m5.dts @@ -123,7 +123,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>; + enable-gpio = <&gpio_ao GPIOE_2 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; diff --git a/dts/src/arm64/amlogic/meson-sm1-odroid.dtsi b/dts/src/arm64/amlogic/meson-sm1-odroid.dtsi index 0bd1e98a0e..ddb1b34539 100644 --- a/dts/src/arm64/amlogic/meson-sm1-odroid.dtsi +++ b/dts/src/arm64/amlogic/meson-sm1-odroid.dtsi @@ -48,7 +48,7 @@ regulator-max-microvolt = <3300000>; vin-supply = <&vcc_5v>; - enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>; + enable-gpio = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>; enable-active-high; regulator-always-on; diff --git a/dts/src/arm64/amlogic/meson-sm1-sei610.dts b/dts/src/arm64/amlogic/meson-sm1-sei610.dts index 427475846f..a5d79f2f7c 100644 --- a/dts/src/arm64/amlogic/meson-sm1-sei610.dts +++ b/dts/src/arm64/amlogic/meson-sm1-sei610.dts @@ -203,14 +203,6 @@ regulator-always-on; }; - reserved-memory { - /* TEE Reserved Memory */ - bl32_reserved: bl32@5000000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - }; - sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; diff --git a/dts/src/arm64/arm/juno-base.dtsi b/dts/src/arm64/arm/juno-base.dtsi index 6288e104a0..a2635b14da 100644 --- a/dts/src/arm64/arm/juno-base.dtsi +++ b/dts/src/arm64/arm/juno-base.dtsi @@ -543,8 +543,7 @@ <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; /* Standard AXI Translation entries as programmed by EDK2 */ - dma-ranges = <0x02000000 0x0 0x2c1c0000 0x0 0x2c1c0000 0x0 0x00040000>, - <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>, + dma-ranges = <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>, <0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; diff --git a/dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28.dts b/dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28.dts index d74e738e40..c03f4e1833 100644 --- a/dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28.dts @@ -157,6 +157,10 @@ }; }; +&ftm_alarm0 { + status = "okay"; +}; + &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", diff --git a/dts/src/arm64/freescale/imx8mm.dtsi b/dts/src/arm64/freescale/imx8mm.dtsi index f77f90ed41..0c7a72c51a 100644 --- a/dts/src/arm64/freescale/imx8mm.dtsi +++ b/dts/src/arm64/freescale/imx8mm.dtsi @@ -707,7 +707,6 @@ clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>; - resets = <&src IMX8MQ_RESET_VPU_RESET>; }; pgc_vpu_g1: power-domain@7 { diff --git a/dts/src/arm64/freescale/imx8mq-librem5.dtsi b/dts/src/arm64/freescale/imx8mq-librem5.dtsi index f3e3418f7e..2d4a472af6 100644 --- a/dts/src/arm64/freescale/imx8mq-librem5.dtsi +++ b/dts/src/arm64/freescale/imx8mq-librem5.dtsi @@ -1115,8 +1115,8 @@ status = "okay"; ports { - port@1 { - reg = <1>; + port@0 { + reg = <0>; mipi1_sensor_ep: endpoint { remote-endpoint = <&camera1_ep>; diff --git a/dts/src/arm64/freescale/imx8mq.dtsi b/dts/src/arm64/freescale/imx8mq.dtsi index 2df2510d01..e92ebb6147 100644 --- a/dts/src/arm64/freescale/imx8mq.dtsi +++ b/dts/src/arm64/freescale/imx8mq.dtsi @@ -554,7 +554,7 @@ assigned-clock-rates = <0>, <0>, <0>, <594000000>; status = "disabled"; - port@0 { + port { lcdif_mipi_dsi: endpoint { remote-endpoint = <&mipi_dsi_lcdif_in>; }; @@ -1151,8 +1151,8 @@ #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; + port@1 { + reg = <1>; csi1_mipi_ep: endpoint { remote-endpoint = <&csi1_ep>; @@ -1203,8 +1203,8 @@ #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; + port@1 { + reg = <1>; csi2_mipi_ep: endpoint { remote-endpoint = <&csi2_ep>; diff --git a/dts/src/arm64/freescale/imx8ulp.dtsi b/dts/src/arm64/freescale/imx8ulp.dtsi index a987ff7156..09f7364dd1 100644 --- a/dts/src/arm64/freescale/imx8ulp.dtsi +++ b/dts/src/arm64/freescale/imx8ulp.dtsi @@ -132,7 +132,7 @@ scmi_sensor: protocol@15 { reg = <0x15>; - #thermal-sensor-cells = <0>; + #thermal-sensor-cells = <1>; }; }; }; diff --git a/dts/src/arm64/freescale/mba8mx.dtsi b/dts/src/arm64/freescale/mba8mx.dtsi index f27e3c8de9..ce6d5bdba0 100644 --- a/dts/src/arm64/freescale/mba8mx.dtsi +++ b/dts/src/arm64/freescale/mba8mx.dtsi @@ -91,7 +91,7 @@ sound { compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "tqm-tlv320aic32"; + model = "imx-audio-tlv320aic32x4"; ssi-controller = <&sai3>; audio-codec = <&tlv320aic3x04>; }; diff --git a/dts/src/arm64/intel/socfpga_agilex.dtsi b/dts/src/arm64/intel/socfpga_agilex.dtsi index 0dd2d2ee76..f4270cf189 100644 --- a/dts/src/arm64/intel/socfpga_agilex.dtsi +++ b/dts/src/arm64/intel/socfpga_agilex.dtsi @@ -502,7 +502,7 @@ }; usb0: usb@ffb00000 { - compatible = "snps,dwc2"; + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; reg = <0xffb00000 0x40000>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbphy0>; @@ -515,7 +515,7 @@ }; usb1: usb@ffb40000 { - compatible = "snps,dwc2"; + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; reg = <0xffb40000 0x40000>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbphy0>; diff --git a/dts/src/arm64/rockchip/px30.dtsi b/dts/src/arm64/rockchip/px30.dtsi index f972704dfe..56dfbb2e2f 100644 --- a/dts/src/arm64/rockchip/px30.dtsi +++ b/dts/src/arm64/rockchip/px30.dtsi @@ -711,7 +711,7 @@ clock-names = "pclk", "timer"; }; - dmac: dmac@ff240000 { + dmac: dma-controller@ff240000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff240000 0x0 0x4000>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/src/arm64/rockchip/rk3328.dtsi b/dts/src/arm64/rockchip/rk3328.dtsi index 39db0b85b4..b822533dc7 100644 --- a/dts/src/arm64/rockchip/rk3328.dtsi +++ b/dts/src/arm64/rockchip/rk3328.dtsi @@ -489,7 +489,7 @@ status = "disabled"; }; - dmac: dmac@ff1f0000 { + dmac: dma-controller@ff1f0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff1f0000 0x0 0x4000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/src/arm64/rockchip/rk3399-gru.dtsi b/dts/src/arm64/rockchip/rk3399-gru.dtsi index 45a5ae5d20..162f08bca0 100644 --- a/dts/src/arm64/rockchip/rk3399-gru.dtsi +++ b/dts/src/arm64/rockchip/rk3399-gru.dtsi @@ -286,7 +286,7 @@ sound: sound { compatible = "rockchip,rk3399-gru-sound"; - rockchip,cpu = <&i2s0 &i2s2>; + rockchip,cpu = <&i2s0 &spdif>; }; }; @@ -437,10 +437,6 @@ ap_i2c_audio: &i2c8 { status = "okay"; }; -&i2s2 { - status = "okay"; -}; - &io_domains { status = "okay"; @@ -537,6 +533,17 @@ ap_i2c_audio: &i2c8 { vqmmc-supply = <&ppvar_sd_card_io>; }; +&spdif { + status = "okay"; + + /* + * SPDIF is routed internally to DP; we either don't use these pins, or + * mux them to something else. + */ + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; +}; + &spi1 { status = "okay"; diff --git a/dts/src/arm64/rockchip/rk3399-puma-haikou.dts b/dts/src/arm64/rockchip/rk3399-puma-haikou.dts index 292bb7e80c..3ae5d727e3 100644 --- a/dts/src/arm64/rockchip/rk3399-puma-haikou.dts +++ b/dts/src/arm64/rockchip/rk3399-puma-haikou.dts @@ -232,6 +232,7 @@ &usbdrd_dwc3_0 { dr_mode = "otg"; + extcon = <&extcon_usb3>; status = "okay"; }; diff --git a/dts/src/arm64/rockchip/rk3399-puma.dtsi b/dts/src/arm64/rockchip/rk3399-puma.dtsi index fb67db4619..08fa00364b 100644 --- a/dts/src/arm64/rockchip/rk3399-puma.dtsi +++ b/dts/src/arm64/rockchip/rk3399-puma.dtsi @@ -25,6 +25,13 @@ }; }; + extcon_usb3: extcon-usb3 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_id>; + }; + clkin_gmac: external-gmac-clock { compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -422,9 +429,22 @@ <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb3 { + usb3_id: usb3-id { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &sdhci { + /* + * Signal integrity isn't great at 200MHz but 100MHz has proven stable + * enough. + */ + max-frequency = <100000000>; + bus-width = <8>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; diff --git a/dts/src/arm64/rockchip/rk3399.dtsi b/dts/src/arm64/rockchip/rk3399.dtsi index d3cdf6f42a..080457a68e 100644 --- a/dts/src/arm64/rockchip/rk3399.dtsi +++ b/dts/src/arm64/rockchip/rk3399.dtsi @@ -1881,10 +1881,10 @@ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, - <&cru PLL_VPLL>, + <&cru SCLK_HDMI_CEC>, <&cru PCLK_VIO_GRF>, - <&cru SCLK_HDMI_CEC>; - clock-names = "iahb", "isfr", "vpll", "grf", "cec"; + <&cru PLL_VPLL>; + clock-names = "iahb", "isfr", "cec", "grf", "vpll"; power-domains = <&power RK3399_PD_HDCP>; reg-io-width = <4>; rockchip,grf = <&grf>; diff --git a/dts/src/arm64/rockchip/rk3566-quartz64-a.dts b/dts/src/arm64/rockchip/rk3566-quartz64-a.dts index 166399b7f1..d9eb92d590 100644 --- a/dts/src/arm64/rockchip/rk3566-quartz64-a.dts +++ b/dts/src/arm64/rockchip/rk3566-quartz64-a.dts @@ -285,8 +285,6 @@ vcc_ddr: DCDC_REG3 { regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; regulator-initial-mode = <0x2>; regulator-name = "vcc_ddr"; regulator-state-mem { diff --git a/dts/src/arm64/rockchip/rk3568.dtsi b/dts/src/arm64/rockchip/rk3568.dtsi index 2fd313a295..d91df1cde7 100644 --- a/dts/src/arm64/rockchip/rk3568.dtsi +++ b/dts/src/arm64/rockchip/rk3568.dtsi @@ -32,13 +32,11 @@ clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, - <&cru PCLK_XPCS>; + <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>; clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_refout", "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref", - "pclk_xpcs"; + "clk_mac_speed", "ptp_ref"; resets = <&cru SRST_A_GMAC0>; reset-names = "stmmaceth"; rockchip,grf = <&grf>; diff --git a/dts/src/arm64/rockchip/rk356x.dtsi b/dts/src/arm64/rockchip/rk356x.dtsi index a68033a239..8ccce54ee8 100644 --- a/dts/src/arm64/rockchip/rk356x.dtsi +++ b/dts/src/arm64/rockchip/rk356x.dtsi @@ -651,7 +651,7 @@ status = "disabled"; }; - dmac0: dmac@fe530000 { + dmac0: dma-controller@fe530000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xfe530000 0x0 0x4000>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, @@ -662,7 +662,7 @@ #dma-cells = <1>; }; - dmac1: dmac@fe550000 { + dmac1: dma-controller@fe550000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xfe550000 0x0 0x4000>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/src/arm64/ti/k3-j721s2-common-proc-board.dts b/dts/src/arm64/ti/k3-j721s2-common-proc-board.dts index a5a24f9f46..b210cc07c5 100644 --- a/dts/src/arm64/ti/k3-j721s2-common-proc-board.dts +++ b/dts/src/arm64/ti/k3-j721s2-common-proc-board.dts @@ -15,8 +15,18 @@ model = "Texas Instruments J721S2 EVM"; chosen { - stdout-path = "serial10:115200n8"; - bootargs = "console=ttyS10,115200n8 earlycon=ns16550a,mmio32,2880000"; + stdout-path = "serial2:115200n8"; + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,2880000"; + }; + + aliases { + serial1 = &mcu_uart0; + serial2 = &main_uart8; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + can0 = &main_mcan16; + can1 = &mcu_mcan0; + can2 = &mcu_mcan1; }; evm_12v0: fixedregulator-evm12v0 { diff --git a/dts/src/arm64/ti/k3-j721s2.dtsi b/dts/src/arm64/ti/k3-j721s2.dtsi index 80d3cae03e..fe5234c40f 100644 --- a/dts/src/arm64/ti/k3-j721s2.dtsi +++ b/dts/src/arm64/ti/k3-j721s2.dtsi @@ -21,28 +21,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - serial9 = &main_uart7; - serial10 = &main_uart8; - serial11 = &main_uart9; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - can0 = &main_mcan16; - can1 = &mcu_mcan0; - can2 = &mcu_mcan1; - can3 = &main_mcan3; - can4 = &main_mcan5; - }; - chosen { }; cpus { diff --git a/dts/src/mips/ingenic/ci20.dts b/dts/src/mips/ingenic/ci20.dts index 3e336b3dbb..ab6e3dc0bc 100644 --- a/dts/src/mips/ingenic/ci20.dts +++ b/dts/src/mips/ingenic/ci20.dts @@ -83,6 +83,8 @@ label = "HDMI OUT"; type = "a"; + ddc-en-gpios = <&gpa 25 GPIO_ACTIVE_HIGH>; + port { hdmi_con: endpoint { remote-endpoint = <&dw_hdmi_out>; @@ -114,17 +116,6 @@ gpio = <&gpf 14 GPIO_ACTIVE_LOW>; enable-active-high; }; - - hdmi_power: fixedregulator@3 { - compatible = "regulator-fixed"; - - regulator-name = "hdmi_power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpa 25 0>; - enable-active-high; - }; }; &ext { @@ -576,8 +567,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pins_hdmi_ddc>; - hdmi-5v-supply = <&hdmi_power>; - ports { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/riscv/canaan/k210.dtsi b/dts/src/riscv/canaan/k210.dtsi index 56f57118c6..44d3385147 100644 --- a/dts/src/riscv/canaan/k210.dtsi +++ b/dts/src/riscv/canaan/k210.dtsi @@ -113,7 +113,8 @@ compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; reg = <0xC000000 0x4000000>; interrupt-controller; - interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>; riscv,ndev = <65>; }; diff --git a/include/linux/clk.h b/include/linux/clk.h index c0e998e54a..42c64d650d 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -63,63 +63,6 @@ struct clk_bulk_data { struct clk *clk_get(struct device_d *dev, const char *id); /** - * clk_bulk_get - lookup and obtain a number of references to clock producer. - * @dev: device for clock "consumer" - * @num_clks: the number of clk_bulk_data - * @clks: the clk_bulk_data table of consumer - * - * This helper function allows drivers to get several clk consumers in one - * operation. If any of the clk cannot be acquired then any clks - * that were obtained will be freed before returning to the caller. - * - * Returns 0 if all clocks specified in clk_bulk_data table are obtained - * successfully, or valid IS_ERR() condition containing errno. - * The implementation uses @dev and @clk_bulk_data.id to determine the - * clock consumer, and thereby the clock producer. - * The clock returned is stored in each @clk_bulk_data.clk field. - * - * Drivers must assume that the clock source is not enabled. - * - * clk_bulk_get should not be called from within interrupt context. - */ -int __must_check clk_bulk_get(struct device_d *dev, int num_clks, - struct clk_bulk_data *clks); - -/** - * clk_bulk_get_optional - lookup and obtain a number of references to clock producer - * @dev: device for clock "consumer" - * @num_clks: the number of clk_bulk_data - * @clks: the clk_bulk_data table of consumer - * - * Behaves the same as clk_bulk_get() except where there is no clock producer. - * In this case, instead of returning -ENOENT, the function returns 0 and - * NULL for a clk for which a clock producer could not be determined. - */ -int __must_check clk_bulk_get_optional(struct device_d *dev, int num_clks, - struct clk_bulk_data *clks); - -/** - * clk_bulk_get_all - lookup and obtain all available references to clock - * producer. - * @dev: device for clock "consumer" - * @clks: pointer to the clk_bulk_data table of consumer - * - * This helper function allows drivers to get all clk consumers in one - * operation. If any of the clk cannot be acquired then any clks - * that were obtained will be freed before returning to the caller. - * - * Returns a positive value for the number of clocks obtained while the - * clock references are stored in the clk_bulk_data table in @clks field. - * Returns 0 if there're none and a negative value if something failed. - * - * Drivers must assume that the clock source is not enabled. - * - * clk_bulk_get should not be called from within interrupt context. - */ -int __must_check clk_bulk_get_all(struct device_d *dev, - struct clk_bulk_data **clks); - -/** * clk_enable - inform the system when the clock source should be running. * @clk: clock source * @@ -130,18 +73,6 @@ int __must_check clk_bulk_get_all(struct device_d *dev, int clk_enable(struct clk *clk); /** - * clk_bulk_enable - inform the system when the set of clks should be running. - * @num_clks: the number of clk_bulk_data - * @clks: the clk_bulk_data table of consumer - * - * May be called from atomic contexts. - * - * Returns success (0) or negative errno. - */ -int __must_check clk_bulk_enable(int num_clks, - const struct clk_bulk_data *clks); - -/** * clk_disable - inform the system when the clock source is no longer required. * @clk: clock source * @@ -156,24 +87,6 @@ int __must_check clk_bulk_enable(int num_clks, void clk_disable(struct clk *clk); /** - * clk_bulk_disable - inform the system when the set of clks is no - * longer required. - * @num_clks: the number of clk_bulk_data - * @clks: the clk_bulk_data table of consumer - * - * Inform the system that a set of clks is no longer required by - * a driver and may be shut down. - * - * May be called from atomic contexts. - * - * Implementation detail: if the set of clks is shared between - * multiple drivers, clk_bulk_enable() calls must be balanced by the - * same number of clk_bulk_disable() calls for the clock source to be - * disabled. - */ -void clk_bulk_disable(int num_clks, const struct clk_bulk_data *clks); - -/** * clk_get_rate - obtain the current clock rate (in Hz) for a clock source. * This is only valid once the clock source has been enabled. * @clk: clock source @@ -181,32 +94,6 @@ void clk_bulk_disable(int num_clks, const struct clk_bulk_data *clks); unsigned long clk_get_rate(struct clk *clk); unsigned long clk_hw_get_rate(struct clk_hw *hw); -/** - * clk_bulk_put - "free" the clock source - * @num_clks: the number of clk_bulk_data - * @clks: the clk_bulk_data table of consumer - * - * Note: drivers must ensure that all clk_bulk_enable calls made on this - * clock source are balanced by clk_bulk_disable calls prior to calling - * this function. - * - * clk_bulk_put should not be called from within interrupt context. - */ -void clk_bulk_put(int num_clks, struct clk_bulk_data *clks); - -/** - * clk_bulk_put_all - "free" all the clock source - * @num_clks: the number of clk_bulk_data - * @clks: the clk_bulk_data table of consumer - * - * Note: drivers must ensure that all clk_bulk_enable calls made on this - * clock source are balanced by clk_bulk_disable calls prior to calling - * this function. - * - * clk_bulk_put_all should not be called from within interrupt context. - */ -void clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks); - /* * The remaining APIs are optional for machine class support. */ @@ -291,46 +178,15 @@ static inline struct clk *clk_get(struct device_d *dev, const char *id) return NULL; } -static inline int __must_check clk_bulk_get(struct device_d *dev, int num_clks, - struct clk_bulk_data *clks) -{ - return 0; -} - -static inline int __must_check clk_bulk_get_optional(struct device_d *dev, - int num_clks, - struct clk_bulk_data *clks) -{ - return 0; -} - -static inline int __must_check clk_bulk_get_all(struct device_d *dev, - struct clk_bulk_data **clks) -{ - return 0; -} - -static inline void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) {} - -static inline void clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks) {} - static inline int clk_enable(struct clk *clk) { return 0; } -static inline int __must_check clk_bulk_enable(int num_clks, struct clk_bulk_data *clks) -{ - return 0; -} - static inline void clk_disable(struct clk *clk) { } -static inline void clk_bulk_disable(int num_clks, - struct clk_bulk_data *clks) {} - static inline unsigned long clk_get_rate(struct clk *clk) { return 0; @@ -895,4 +751,153 @@ static inline void clk_unregister(struct clk *clk) { } +#ifdef CONFIG_COMMON_CLK + +/** + * clk_bulk_get - lookup and obtain a number of references to clock producer. + * @dev: device for clock "consumer" + * @num_clks: the number of clk_bulk_data + * @clks: the clk_bulk_data table of consumer + * + * This helper function allows drivers to get several clk consumers in one + * operation. If any of the clk cannot be acquired then any clks + * that were obtained will be freed before returning to the caller. + * + * Returns 0 if all clocks specified in clk_bulk_data table are obtained + * successfully, or valid IS_ERR() condition containing errno. + * The implementation uses @dev and @clk_bulk_data.id to determine the + * clock consumer, and thereby the clock producer. + * The clock returned is stored in each @clk_bulk_data.clk field. + * + * Drivers must assume that the clock source is not enabled. + * + * clk_bulk_get should not be called from within interrupt context. + */ +int __must_check clk_bulk_get(struct device_d *dev, int num_clks, + struct clk_bulk_data *clks); + +/** + * clk_bulk_get_optional - lookup and obtain a number of references to clock producer + * @dev: device for clock "consumer" + * @num_clks: the number of clk_bulk_data + * @clks: the clk_bulk_data table of consumer + * + * Behaves the same as clk_bulk_get() except where there is no clock producer. + * In this case, instead of returning -ENOENT, the function returns 0 and + * NULL for a clk for which a clock producer could not be determined. + */ +int __must_check clk_bulk_get_optional(struct device_d *dev, int num_clks, + struct clk_bulk_data *clks); + +/** + * clk_bulk_get_all - lookup and obtain all available references to clock + * producer. + * @dev: device for clock "consumer" + * @clks: pointer to the clk_bulk_data table of consumer + * + * This helper function allows drivers to get all clk consumers in one + * operation. If any of the clk cannot be acquired then any clks + * that were obtained will be freed before returning to the caller. + * + * Returns a positive value for the number of clocks obtained while the + * clock references are stored in the clk_bulk_data table in @clks field. + * Returns 0 if there're none and a negative value if something failed. + * + * Drivers must assume that the clock source is not enabled. + * + * clk_bulk_get should not be called from within interrupt context. + */ +int __must_check clk_bulk_get_all(struct device_d *dev, + struct clk_bulk_data **clks); + +/** + * clk_bulk_put - "free" the clock source + * @num_clks: the number of clk_bulk_data + * @clks: the clk_bulk_data table of consumer + * + * Note: drivers must ensure that all clk_bulk_enable calls made on this + * clock source are balanced by clk_bulk_disable calls prior to calling + * this function. + * + * clk_bulk_put should not be called from within interrupt context. + */ +void clk_bulk_put(int num_clks, struct clk_bulk_data *clks); + +/** + * clk_bulk_put_all - "free" all the clock source + * @num_clks: the number of clk_bulk_data + * @clks: the clk_bulk_data table of consumer + * + * Note: drivers must ensure that all clk_bulk_enable calls made on this + * clock source are balanced by clk_bulk_disable calls prior to calling + * this function. + * + * clk_bulk_put_all should not be called from within interrupt context. + */ +void clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks); + +/** + * clk_bulk_enable - inform the system when the set of clks should be running. + * @num_clks: the number of clk_bulk_data + * @clks: the clk_bulk_data table of consumer + * + * May be called from atomic contexts. + * + * Returns success (0) or negative errno. + */ +int __must_check clk_bulk_enable(int num_clks, + const struct clk_bulk_data *clks); + +/** + * clk_bulk_disable - inform the system when the set of clks is no + * longer required. + * @num_clks: the number of clk_bulk_data + * @clks: the clk_bulk_data table of consumer + * + * Inform the system that a set of clks is no longer required by + * a driver and may be shut down. + * + * May be called from atomic contexts. + * + * Implementation detail: if the set of clks is shared between + * multiple drivers, clk_bulk_enable() calls must be balanced by the + * same number of clk_bulk_disable() calls for the clock source to be + * disabled. + */ +void clk_bulk_disable(int num_clks, const struct clk_bulk_data *clks); + +#else +static inline int __must_check clk_bulk_get(struct device_d *dev, int num_clks, + struct clk_bulk_data *clks) +{ + return 0; +} + +static inline int __must_check clk_bulk_get_optional(struct device_d *dev, + int num_clks, + struct clk_bulk_data *clks) +{ + return 0; +} + +static inline int __must_check clk_bulk_get_all(struct device_d *dev, + struct clk_bulk_data **clks) +{ + return 0; +} + +static inline void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) {} + +static inline void clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks) {} + +static inline int __must_check clk_bulk_enable(int num_clks, struct clk_bulk_data *clks) +{ + return 0; +} + +static inline void clk_bulk_disable(int num_clks, + struct clk_bulk_data *clks) {} + +#endif + #endif diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h index aa9cbcac77..bc1b43aab0 100644 --- a/include/linux/compiler_types.h +++ b/include/linux/compiler_types.h @@ -112,6 +112,27 @@ struct ftrace_likely_data { #define __deprecated #define __deprecated_for_modules +#ifndef __has_attribute +#define __has_attribute(...) 0 +#endif + +/* + * Add the pseudo keyword 'fallthrough' so case statement blocks + * must end with any of these keywords: + * break; + * fallthrough; + * continue; + * goto <label>; + * return [expression]; + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Statement-Attributes.html#Statement-Attributes + */ +#if __has_attribute(__fallthrough__) +# define fallthrough __attribute__((__fallthrough__)) +#else +# define fallthrough do {} while (0) /* fallthrough */ +#endif + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 679ce6e420..321e546f90 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -195,7 +195,7 @@ static inline struct phy *phy_get(struct device_d *dev, const char *string) static inline struct phy *phy_optional_get(struct device_d *dev, const char *string) { - return ERR_PTR(-ENOSYS); + return NULL; } static inline struct phy *of_phy_get_by_phandle(struct device_d *dev, diff --git a/include/of.h b/include/of.h index b449d10ec7..cf9950e9b3 100644 --- a/include/of.h +++ b/include/of.h @@ -120,6 +120,7 @@ extern int of_bus_n_addr_cells(struct device_node *np); extern int of_n_addr_cells(struct device_node *np); extern int of_bus_n_size_cells(struct device_node *np); extern int of_n_size_cells(struct device_node *np); +extern bool of_node_name_eq(const struct device_node *np, const char *name); extern struct property *of_find_property(const struct device_node *np, const char *name, int *lenp); @@ -138,6 +139,8 @@ extern void of_delete_property(struct property *pp); extern struct device_node *of_find_node_by_name(struct device_node *from, const char *name); +extern struct device_node *of_find_node_by_name_address(struct device_node *from, + const char *name); extern struct device_node *of_find_node_by_path_from(struct device_node *from, const char *path); extern struct device_node *of_find_node_by_path(const char *path); @@ -284,6 +287,7 @@ extern struct device_d *of_device_enable_and_register_by_alias( extern int of_device_ensure_probed(struct device_node *np); extern int of_device_ensure_probed_by_alias(const char *alias); extern int of_devices_ensure_probed_by_property(const char *property_name); +extern int of_devices_ensure_probed_by_name(const char *name); extern int of_devices_ensure_probed_by_dev_id(const struct of_device_id *ids); extern int of_partition_ensure_probed(struct device_node *np); @@ -313,6 +317,11 @@ struct device_node *of_find_node_by_path_or_alias(struct device_node *root, int of_autoenable_device_by_path(char *path); int of_autoenable_i2c_by_component(char *path); #else +static inline bool of_node_name_eq(const struct device_node *np, const char *name) +{ + return false; +} + static inline int of_parse_partitions(struct cdev *cdev, struct device_node *node) { @@ -659,6 +668,12 @@ static inline struct device_node *of_find_node_by_name(struct device_node *from, return NULL; } +static inline struct device_node *of_find_node_by_name_address(struct device_node *from, + const char *name) +{ + return NULL; +} + static inline struct device_node *of_find_node_by_phandle(phandle phandle) { return NULL; @@ -827,12 +842,18 @@ static inline int of_autoenable_i2c_by_component(char *path) #define for_each_node_by_name(dn, name) \ for (dn = of_find_node_by_name(NULL, name); dn; \ dn = of_find_node_by_name(dn, name)) +#define for_each_node_by_name_address(dn, name) \ + for (dn = of_find_node_by_name_address(NULL, name); dn; \ + dn = of_find_node_by_name_address(dn, name)) #define for_each_node_by_type(dn, type) \ for (dn = of_find_node_by_type(NULL, type); dn; \ dn = of_find_node_by_type(dn, type)) #define for_each_node_by_name_from(dn, root, name) \ for (dn = of_find_node_by_name(root, name); dn; \ dn = of_find_node_by_name(dn, name)) +#define for_each_node_by_name_address_from(dn, root, name) \ + for (dn = of_find_node_by_name_address(root, name); dn; \ + dn = of_find_node_by_name_address(dn, name)) /* Iterate over compatible nodes starting from given root */ #define for_each_compatible_node_from(dn, root, type, compatible) \ for (dn = of_find_compatible_node(root, type, compatible); dn; \ diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include index 838ab11e7c..ab092e455c 100644 --- a/scripts/Kbuild.include +++ b/scripts/Kbuild.include @@ -111,7 +111,7 @@ as-option = $(call try-run,\ # Usage: cflags-y += $(call as-instr,instr,option1,option2) as-instr = $(call try-run,\ - /bin/echo -e "$(1)" | $(CC) $(KBUILD_AFLAGS) -c -xassembler -o "$$TMP" -,$(2),$(3)) + printf "%b\n" "$(1)" | $(CC) $(KBUILD_AFLAGS) -c -xassembler -o "$$TMP" -,$(2),$(3)) # cc-option # Usage: cflags-y += $(call cc-option,-march=winchip-c6,-march=i586) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index e3c1297352..a830364a8b 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -339,7 +339,7 @@ $(obj)/%.dtb.S: $(obj)/%.dtb $(srctree)/scripts/gen-dtb-s FORCE dts-frags = $(subst $(quote),,$(CONFIG_EXTERNAL_DTS_FRAGMENTS)) quiet_cmd_dtc = DTC $@ # For compatibility between make 4.2 and 4.3 -cmd_dtc = /bin/echo -e '$(pound)define $(subst -,_,$(*F))_dts 1\n'$(foreach f,$< $(dts-frags),'$(pound)include "$(f)"\n') | \ +cmd_dtc = /usr/bin/env echo -e '$(pound)define $(subst -,_,$(*F))_dts 1\n'$(foreach f,$< $(dts-frags),'$(pound)include "$(f)"\n') | \ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) - ; \ $(objtree)/scripts/dtc/dtc -O dtb -o $@ -b 0 \ -i $(srctree)/arch/$(SRCARCH)/dts $(DTC_FLAGS) \ diff --git a/scripts/bareboximd.c b/scripts/bareboximd.c index 2d4750d7fb..d01bd27007 100644 --- a/scripts/bareboximd.c +++ b/scripts/bareboximd.c @@ -55,9 +55,10 @@ static unsigned long simple_strtoul(const char *cp, char **endp, unsigned int ba return strtoul(cp, endp, base); } -static int imd_read_file(const char *filename, size_t *size, void **outbuf) +static int imd_read_file(const char *filename, size_t *size, void **outbuf, + bool allow_mmap) { - void *buf; + void *buf = MAP_FAILED; int fd, ret; size_t fsize; @@ -74,7 +75,9 @@ static int imd_read_file(const char *filename, size_t *size, void **outbuf) goto close; } - buf = mmap(NULL, fsize, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); + if (allow_mmap) + buf = mmap(NULL, fsize, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); + if (buf == MAP_FAILED) { close(fd); return read_file_2(filename, size, outbuf, 0x100000); |