diff options
45 files changed, 2368 insertions, 219 deletions
@@ -1,3 +1,193 @@ +commit 4f4b602ec7524a032bdf3c6d28c7f525a4a67eaa +Author: Wolfgang Denk <wd@pollux.denx.de> +Date: Mon Nov 27 22:53:53 2006 +0100 + + Update CHANGELOG + +commit f6e495f54cdb8fe340b9c03deab40ad746d52fae +Author: Stefan Roese <sr@denx.de> +Date: Mon Nov 27 17:43:25 2006 +0100 + + [PATCH] 4xx_enet.c: Correct the setting of zmiifer register + + Patch below corrects the setting of the zmiifer register, it was + overwritting the register rather than ORing the settings. + + Signed-off-by: Neil Wilson <NWilson@airspan.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit d1a72545296800b7e219f93104ad5836f0003d66 +Author: Stefan Roese <sr@denx.de> +Date: Mon Nov 27 17:34:10 2006 +0100 + + [PATCH] Select NAND embedded environment from board configuration + + The current NAND Bootloader setup forces the environment + variables to be in line with the bootloader. This change + enables the configuration to be made in the board include + file instead so that it can be individually enabled. + + Signed-off-by: Nick Spence <nick.spence@freescale.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 15784862857c3c2214498defcfed84ff137fb81e +Author: Stefan Roese <sr@denx.de> +Date: Mon Nov 27 17:22:19 2006 +0100 + + [PATCH] nand_wait() timeout fixes + + Two fixes for the nand_wait() function in + drivers/nand/nand_base.c: + + 1. Use correct timeouts. The original timeouts in Linux + source are 400ms and 20ms not 40s and 20s + + 2. Return correct error value in case of timeout. 0 is + interpreted as OK. + + Signed-off-by: Rui Sousa <rui.sousa@laposte.net> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit da5553b095bf04f4f109ad7e565dae3aba47b230 +Author: Stefan Roese <sr@denx.de> +Date: Mon Nov 27 17:04:06 2006 +0100 + + [PATCH] Allow CONFIG_OF_FLAT_TREE to boot a non-arch/powerpc kernel + + This patch allows an arch/ppc kernel to be booted by just passing 1 or 2 + arguments to bootm. It removes the getenv("disable_of") test that used + to be used for this purpose. + + Signed-off-by: Grant Likely <grant.likely@secretlab.ca> + Acked-by: Jon Loeliger <jdl@freescale.com> + +commit a9398e018593782c5fa7d0741955fc1256b34c1e +Author: Wolfgang Denk <wd@pollux.denx.de> +Date: Mon Nov 27 15:32:42 2006 +0100 + + Minor code cleanup. Update CHANGELOG. + +commit 78d620ebb5871d252270dedfad60c6568993b780 +Author: Wolfgang Denk <wd@atlas.denx.de> +Date: Thu Nov 23 22:58:58 2006 +0100 + + Updates for TQM5200 modules: + - fix off-by-one error in board/tqm5200/cam5200_flash.c error message + - simplify "udate" definitions + +commit 2053283304eeddf250d109e6791eb6fa4cad14f7 +Author: Stefan Roese <sr@denx.de> +Date: Wed Nov 22 13:20:50 2006 +0100 + + [PATCH] PPC4xx start.S: Fix for processor errata + + Fixed cpu/ppc4xx/start.S for 440EPx Errata: further corrects PPC440EPx + errata 1.12: 440_33 by moving patch up in code. + + Signed-off-by: Jeff Mann <mannj@embeddedplanet.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 4ef6251403f637841000e0fef9e832aa01339822 +Author: Stefan Roese <sr@denx.de> +Date: Mon Nov 20 20:39:52 2006 +0100 + + [PATCH] Update AMCC Sequoia config file to support 64MByte NOR FLASH + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit e4bbd8da164b976d38616bd9c69c5e86e193cdf0 +Author: Wolfgang Denk <wd@pollux.denx.de> +Date: Mon Nov 20 10:28:30 2006 +0100 + + Update CHANGELOG + +commit 260421a21e934a68d31fb6125b0fbd2631a8ca20 +Author: Stefan Roese <sr@denx.de> +Date: Mon Nov 13 13:55:24 2006 +0100 + + [PATCH] CFI driver AMD Command Set Top boot geometry reversal, etc. [Updated] + + * Adds support for AMD command set Top Boot flash geometry reversal + * Adds support for reading JEDEC Manufacturer ID and Device ID + * Adds support for displaying command set, manufacturer id and + device ids (flinfo) + * Makes flinfo output to be consistent when CFG_FLASH_EMPTY_INFO defined + * Removes outdated change history (refer to git log instead) + + Signed-off-by: Tolunay Orkun <listmember@orkun.us> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit b21b511d4c50408f4853f46f06b601272196223f +Author: Wolfgang Denk <wd@pollux.denx.de> +Date: Sun Nov 12 21:13:23 2006 +0100 + + Update CHANGELOG + +commit ce3f1a40c507afbab06c5eb58ccdc6713eda3245 +Author: Bartlomiej Sieka <tur@semihalf.com> +Date: Sat Nov 11 22:48:22 2006 +0100 + + Disable the watchdog in the default config for the V38B board. + +commit 44a47e6db2694841211f1c8fdbafd36992e9cd1a +Author: Bartlomiej Sieka <tur@semihalf.com> +Date: Sat Nov 11 22:43:00 2006 +0100 + + Change the GPIO pin multiplexing configuration for V38B. The USB GPIO pin + group is enabled for USB earlier (in cpu_init_f() instead of + usb_lowlevel_init()). + +commit 91650b3e4de688038d4f71279c44858e3e2c6870 +Author: Wolfgang Denk <wd@pollux.denx.de> +Date: Mon Nov 6 17:06:36 2006 +0100 + + Sequential accesses to non-existent memory must be synchronized, + at least on G2 cores. + + This fixes get_ram_size() problems on MPC5200 Rev. B boards. + +commit c59200443072353044aa4bf737a5a60f9a9af231 +Author: Wolfgang Denk <wd@pollux.denx.de> +Date: Thu Nov 2 15:15:01 2006 +0100 + + Release U-Boot 1.1.6 + +commit 25721b5cec2be4bce79cfade17ec8f6aa1e67526 +Author: Bartlomiej Sieka <tur@semihalf.com> +Date: Wed Nov 1 02:04:38 2006 +0100 + + Finish up support for MarelV38B board + - add watchdog support + - enable GPIO_WKUP_7 pin for input + - code cleanup + +commit ffa150bc90c943ca265170bd1be3f293674dd5c7 +Author: Bartlomiej Sieka <tur@semihalf.com> +Date: Wed Nov 1 01:45:46 2006 +0100 + + - Fix issues related to the use of ELDK 4 when compiling for MarelV38B: + * remove warnings when compiling ethaddr.c + * adjust linker script (fixes a crash resulting from incorrect + definition of __u_boot_cmd_start) + - Some MarelV38B code cleanup. + +commit dae80f3caf9754a6dd3ddf3cf903d0c46cbd4385 +Author: Bartlomiej Sieka <tur@semihalf.com> +Date: Wed Nov 1 01:38:16 2006 +0100 + + - Add MPC5XXX register definition MPC5XXX_WU_GPIO_DATA_I and change the + MPC5XXX_WU_GPIO_DATA macro to MPC5XXX_WU_GPIO_DATA_O (per MPC5200 User's + Manual). Replace the uses of MPC5XXX_WU_GPIO_DATA with + MPC5XXX_WU_GPIO_DATA_O for affected boards. + + - Add defintions for some MPC5XXX GPIO pins. + +commit 82d9c9ec29a1bec1b03ba616425ebaed231072c8 +Author: Bartlomiej Sieka <tur@semihalf.com> +Date: Wed Nov 1 01:34:29 2006 +0100 + + Changed MarelV38B board make target to lowercase. Config file cleanup. + commit 1954be6e9c9421b45d0a9d05b10356acc7563150 Author: Wolfgang Denk <wd@pollux.denx.de> Date: Sun Oct 29 01:03:51 2006 +0200 diff --git a/MAINTAINERS b/MAINTAINERS index a423f22c66..19fbd0f233 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -281,6 +281,7 @@ Stefan Roese <sr@denx.de> TQM85xx MPC8540/8541/8555/8560 + alpr PPC440GX bamboo PPC440EP bunbinga PPC405EP ebony PPC440GP @@ -74,21 +74,21 @@ LIST_8xx=" \ ######################################################################### LIST_4xx=" \ - ADCIOP AP1000 AR405 ASH405 \ - bamboo bubinga CANBT CMS700 \ - CPCI2DP CPCI405 CPCI4052 CPCI405AB \ - CPCI405DT CPCI440 CPCIISER4 CRAYL1 \ - csb272 csb472 DASA_SIM DP405 \ - DU405 ebony ERIC EXBITGEN \ - G2000 HH405 HUB405 JSE \ - KAREF luan METROBOX MIP405 \ - MIP405T ML2 ml300 ocotea \ - OCRTC ORSG p3p440 PCI405 \ - pcs440ep PIP405 PLU405 PMC405 \ - PPChameleonEVB sbc405 sequoia sequoia_nand \ - VOH405 VOM405 W7OLMC W7OLMG \ - walnut WUH405 XPEDITE1K yellowstone \ - yosemite yucca bamboo \ + ADCIOP alpr AP1000 AR405 \ + ASH405 bamboo bubinga CANBT \ + CMS700 CPCI2DP CPCI405 CPCI4052 \ + CPCI405AB CPCI405DT CPCI440 CPCIISER4 \ + CRAYL1 csb272 csb472 DASA_SIM \ + DP405 DU405 ebony ERIC \ + EXBITGEN G2000 HH405 HUB405 \ + JSE KAREF luan METROBOX \ + MIP405 MIP405T ML2 ml300 \ + ocotea OCRTC ORSG p3p440 \ + PCI405 pcs440ep PIP405 PLU405 \ + PMC405 PPChameleonEVB sbc405 sequoia \ + sequoia_nand VOH405 VOM405 W7OLMC \ + W7OLMG walnut WUH405 XPEDITE1K \ + yellowstone yosemite yucca \ " ######################################################################### @@ -984,6 +984,9 @@ xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$( ADCIOP_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd +alpr_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx alpr prodrive + AP1000_config:unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx ap1000 amirix @@ -1511,8 +1511,8 @@ The following options need to be configured: Enable auto completion of commands using TAB. - Note that this feature has NOT been implemented yet - for the "hush" shell. + Note that this feature has NOT been implemented yet + for the "hush" shell. CFG_HUSH_PARSER @@ -3173,11 +3173,11 @@ loadaddr=200000 oftaddr=0x300000 => bootm $loadaddr - $oftaddr ## Booting image at 00200000 ... - Image Name: Linux-2.6.17-dirty - Image Type: PowerPC Linux Kernel Image (gzip compressed) - Data Size: 1029343 Bytes = 1005.2 kB + Image Name: Linux-2.6.17-dirty + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 1029343 Bytes = 1005.2 kB Load Address: 00000000 - Entry Point: 00000000 + Entry Point: 00000000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK Booting using flat device tree at 0x300000 diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c index 92dc9d4c02..754ae449c1 100644 --- a/board/amcc/yellowstone/yellowstone.c +++ b/board/amcc/yellowstone/yellowstone.c @@ -552,3 +552,9 @@ void hw_watchdog_reset(void) } #endif + +void board_reset(void) +{ + /* give reset to BCSR */ + *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09; +} diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 7f2e718203..588ee900da 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -548,3 +548,9 @@ void hw_watchdog_reset(void) } #endif + +void board_reset(void) +{ + /* give reset to BCSR */ + *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09; +} diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index 71a691b5db..5d74bdeb42 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -27,6 +27,7 @@ #include <common.h> #include <mpc5xxx.h> #include <pci.h> +#include <asm/processor.h> /* Two MT48LC8M32B2 for 32 MB */ /* #include "mt48lc8m32b2-6-7.h" */ @@ -98,6 +99,7 @@ long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; + uint svr, pvr; #ifndef CFG_RAMBOOT ulong test1, test2; @@ -192,6 +194,22 @@ long int initdram (int board_type) #endif /* CFG_RAMBOOT */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + return dramsize + dramsize2; } diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile new file mode 100644 index 0000000000..00dc180bbd --- /dev/null +++ b/board/prodrive/alpr/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o fpga.o nand.o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c new file mode 100644 index 0000000000..2389561271 --- /dev/null +++ b/board/prodrive/alpr/alpr.c @@ -0,0 +1,328 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#include <asm/processor.h> +#include <spd_sdram.h> +#include <ppc4xx_enet.h> +#include <miiphy.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern int alpr_fpga_init(void); + +int board_early_init_f (void) +{ + /*------------------------------------------------------------------------- + * Initialize EBC CONFIG + *-------------------------------------------------------------------------*/ + mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK | + EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | + EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | + EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (uic0pr, 0xfffffe03); /* per manual */ + mtdcr (uic0tr, 0x01c00000); /* per manual */ + mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + + mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (uic1er, 0x00000000); /* disable all */ + mtdcr (uic1cr, 0x00000000); /* all non-critical */ + mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic1sr, 0xffffffff); /* clear all */ + + mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (uic2er, 0x00000000); /* disable all */ + mtdcr (uic2cr, 0x00000000); /* all non-critical */ + mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ + mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic2sr, 0xffffffff); /* clear all */ + + mtdcr (uicb0sr, 0xfc000000); /* clear all */ + mtdcr (uicb0er, 0x00000000); /* disable all */ + mtdcr (uicb0cr, 0x00000000); /* all non-critical */ + mtdcr (uicb0pr, 0xfc000000); /* */ + mtdcr (uicb0tr, 0x00000000); /* */ + mtdcr (uicb0vr, 0x00000001); /* */ + + /* Setup GPIO/IRQ multiplexing */ + mtsdr(sdr_pfc0, 0x01a03e00); + + return 0; +} + +int last_stage_init(void) +{ + unsigned short reg; + + /* + * Configure LED's of both Marvell 88E1111 PHY's + * + * This has to be done after the 4xx ethernet driver is loaded, + * so "last_stage_init()" is the right place. + */ + miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®); + reg |= 0x0001; + miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg); + miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®); + reg |= 0x0001; + miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg); + + return 0; +} + +static int board_rev(void) +{ + int rev; + u32 pfc0; + + /* Setup GPIO14 & 15 as GPIO */ + mfsdr(sdr_pfc0, pfc0); + pfc0 |= CFG_GPIO_REV0 | CFG_GPIO_REV1; + mtsdr(sdr_pfc0, pfc0); + + /* Setup as input */ + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0)); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0)); + + rev = (in32(GPIO0_IR) >> 16) & 0x3; + + /* Setup GPIO14 & 15 as non GPIO again */ + mfsdr(sdr_pfc0, pfc0); + pfc0 &= ~(CFG_GPIO_REV0 | CFG_GPIO_REV1); + mtsdr(sdr_pfc0, pfc0); + + return rev; +} + +int checkboard (void) +{ + char *s = getenv ("serial#"); + + printf ("Board: ALPR"); + if (s != NULL) { + puts (", serial# "); + puts (s); + } + printf(" (Rev. %d)\n", board_rev()); + + return (0); +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x08000000; + uint *p; + + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + return 0; +} +#endif + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller * hose ) +{ + unsigned long strap; + + /*--------------------------------------------------------------------------+ + * The ocotea board is always configured as the host & requires the + * PCI arbiter to be enabled. + *--------------------------------------------------------------------------*/ + mfsdr(sdr_sdstp1, strap); + if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ + printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); + return 0; + } + + /* FPGA Init */ + alpr_fpga_init (); + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller * hose ) +{ + /*--------------------------------------------------------------------------+ + * Disable everything + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0SA, 0 ); /* disable */ + out32r( PCIX0_PIM1SA, 0 ); /* disable */ + out32r( PCIX0_PIM2SA, 0 ); /* disable */ + out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + + /*--------------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping + * options to not support sizes such as 128/256 MB. + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAH, 0 ); + out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + + out32r( PCIX0_BAR0, 0 ); + + /*--------------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *--------------------------------------------------------------------------*/ + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + + out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) + +static void wait_for_pci_ready(void) +{ + /* + * Configure EREADY as input + */ + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY); + udelay(1000); + + for (;;) { + if (in32(GPIO0_IR) & CFG_GPIO_EREADY) + return; + } + +} + +int is_pci_host(struct pci_controller *hose) +{ + wait_for_pci_ready(); + return 1; /* return 1 for host controller */ +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + /*--------------------------------------------------------------------------+ + | PowerPC440 PCI Master configuration. + | Map PLB/processor addresses to PCI memory space. + | PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r( PCIX0_POM0SA, 0 ); /* disable */ + out32r( PCIX0_POM1SA, 0 ); /* disable */ + out32r( PCIX0_POM2SA, 0 ); /* disable */ + + out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */ + out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ + + out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */ + out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + + return (ctrlc()); +} +#endif diff --git a/board/prodrive/alpr/config.mk b/board/prodrive/alpr/config.mk new file mode 100644 index 0000000000..9e1833591a --- /dev/null +++ b/board/prodrive/alpr/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# AMCC 440GX Reference Platform (Ocotea) board +# + +#TEXT_BASE = 0xFFFE0000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFFC0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c new file mode 100644 index 0000000000..e94360f814 --- /dev/null +++ b/board/prodrive/alpr/fpga.c @@ -0,0 +1,257 @@ +/* + * (C) Copyright 2006 + * Heiko Schocher, DENX Software Engineering, hs@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Altera FPGA configuration support for the ALPR computer from prodrive + */ + +#include <common.h> +#include <altera.h> +#include <ACEX1K.h> +#include <command.h> +#include <asm-ppc/processor.h> +#include <ppc440.h> +#include "fpga.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_FPGA) + +#ifdef FPGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +static unsigned long regval; + +#define SET_GPIO_REG_0(reg, bit) { \ + regval = in32(reg); \ + regval &= ~(0x80000000 >> bit); \ + out32(reg, regval); \ + } + +#define SET_GPIO_REG_1(reg, bit) { \ + regval = in32(reg); \ + regval |= (0x80000000 >> bit); \ + out32(reg, regval); \ + } + +#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit) +#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit) + +#define FPGA_PRG (0x80000000 >> CFG_GPIO_PROG_EN) +#define FPGA_CONFIG (0x80000000 >> CFG_GPIO_CONFIG) +#define FPGA_DATA (0x80000000 >> CFG_GPIO_DATA) +#define FPGA_CLK (0x80000000 >> CFG_GPIO_CLK) +#define OLD_VAL (FPGA_PRG | FPGA_CONFIG) + +#define SET_FPGA(data) out32(GPIO0_OR, data) + +#define FPGA_WRITE_1 { \ + SET_FPGA(OLD_VAL | 0 | FPGA_DATA); /* set data to 1 */ \ + SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ + +#define FPGA_WRITE_0 { \ + SET_FPGA(OLD_VAL | 0 | 0 ); /* set data to 0 */ \ + SET_FPGA(OLD_VAL | FPGA_CLK | 0 );} /* set data to 1 */ + +/* Plattforminitializations */ +/* Here we have to set the FPGA Chain */ +/* PROGRAM_PROG_EN = HIGH */ +/* PROGRAM_SEL_DPR = LOW */ +int fpga_pre_fn (int cookie) +{ + unsigned long reg; + + reg = in32(GPIO0_IR); + /* Enable the FPGA Chain */ + SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_PROG_EN); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_PROG_EN); + SET_GPIO_1(CFG_GPIO_PROG_EN); + SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_SEL_DPR); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR); + SET_GPIO_0((CFG_GPIO_SEL_DPR)); + + /* initialize the GPIO Pins */ + /* output */ + SET_GPIO_0(CFG_GPIO_CLK); + SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CLK); + + /* output */ + SET_GPIO_0(CFG_GPIO_DATA); + SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_DATA); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_DATA); + + /* First we set STATUS to 0 then as an input */ + SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_STATUS); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS); + SET_GPIO_0(CFG_GPIO_STATUS); + SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_STATUS); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS); + + /* output */ + SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CONFIG); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CONFIG); + SET_GPIO_0(CFG_GPIO_CONFIG); + + /* input */ + SET_GPIO_0(CFG_GPIO_CON_DON); + SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_CON_DON); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CON_DON); + + /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ + SET_GPIO_0(CFG_GPIO_CONFIG); + return FPGA_SUCCESS; +} + +/* Set the state of CONFIG Pin */ +int fpga_config_fn (int assert_config, int flush, int cookie) +{ + if (assert_config) { + SET_GPIO_1(CFG_GPIO_CONFIG); + } else { + SET_GPIO_0(CFG_GPIO_CONFIG); + } + return FPGA_SUCCESS; +} + +/* Returns the state of STATUS Pin */ +int fpga_status_fn (int cookie) +{ + unsigned long reg; + + reg = in32(GPIO0_IR); + if (reg &= (0x80000000 >> CFG_GPIO_STATUS)) { + PRINTF("STATUS = HIGH\n"); + return FPGA_FAIL; + } + PRINTF("STATUS = LOW\n"); + return FPGA_SUCCESS; +} + +/* Returns the state of CONF_DONE Pin */ +int fpga_done_fn (int cookie) +{ + unsigned long reg; + reg = in32(GPIO0_IR); + if (reg &= (0x80000000 >> CFG_GPIO_CON_DON)) { + PRINTF("CONF_DON = HIGH\n"); + return FPGA_FAIL; + } + PRINTF("CONF_DON = LOW\n"); + return FPGA_SUCCESS; +} + +/* writes the complete buffer to the FPGA + writing the complete buffer in one function is much faster, + then calling it for every bit */ +int fpga_write_fn (void *buf, size_t len, int flush, int cookie) +{ + size_t bytecount = 0; + unsigned char *data = (unsigned char *) buf; + unsigned char val=0; + int i; + int len_40 = len / 40; + + while (bytecount < len) { + val = data[bytecount++]; + i = 8; + do { + if (val & 0x01) { + FPGA_WRITE_1; + } else { + FPGA_WRITE_0; + } + val >>= 1; + i --; + } while (i > 0); + +#ifdef CFG_FPGA_PROG_FEEDBACK + if (bytecount % len_40 == 0) { + putc ('.'); /* let them know we are alive */ +#ifdef CFG_FPGA_CHECK_CTRLC + if (ctrlc ()) + return FPGA_FAIL; +#endif + } +#endif + } + return FPGA_SUCCESS; +} + +/* called, when programming is aborted */ +int fpga_abort_fn (int cookie) +{ + SET_GPIO_1((CFG_GPIO_SEL_DPR)); + return FPGA_SUCCESS; +} + +/* called, when programming was succesful */ +int fpga_post_fn (int cookie) +{ + return fpga_abort_fn (cookie); +} + +/* Note that these are pointers to code that is in Flash. They will be + * relocated at runtime. + */ +Altera_CYC2_Passive_Serial_fns fpga_fns = { + fpga_pre_fn, + fpga_config_fn, + fpga_status_fn, + fpga_done_fn, + fpga_write_fn, + fpga_abort_fn, + fpga_post_fn +}; + +Altera_desc fpga[CONFIG_FPGA_COUNT] = { + {Altera_CYC2, + passive_serial, + Altera_EP2C35_SIZE, + (void *) &fpga_fns, + NULL, + 0} +}; + +/* + * Initialize the fpga. Return 1 on success, 0 on failure. + */ +int alpr_fpga_init (void) +{ + int i; + + PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off); + fpga_init (gd->reloc_off); + + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i); + fpga_add (fpga_altera, &fpga[i]); + } + return 1; +} + +#endif diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S new file mode 100644 index 0000000000..135674c26a --- /dev/null +++ b/board/prodrive/alpr/init.S @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I ) + + /* NAND */ + tlbentry( CFG_NAND_BASE, SZ_4K, CFG_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbtab_end diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c new file mode 100644 index 0000000000..e63c921eff --- /dev/null +++ b/board/prodrive/alpr/nand.c @@ -0,0 +1,173 @@ +/* + * (C) Copyright 2006 + * Heiko Schocher, DENX Software Engineering, hs@denx.de + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <asm/processor.h> +#include <nand.h> + +struct alpr_ndfc_regs { + u8 cmd[4]; + u8 addr_wait; + u8 term; + u8 dummy; + u8 dummy2; + u8 data; +}; + +static u8 hwctl; +static struct alpr_ndfc_regs *alpr_ndfc = NULL; + +#define readb(addr) (u8)(*(volatile u8 *)(addr)) +#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d)) + +/* + * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to + * the NAND devices. The NDFC has command, address and data registers that + * when accessed will set up the NAND flash pins appropriately. We'll use the + * hwcontrol function to save the configuration in a global variable. + * We can then use this information in the read and write functions to + * determine which NDFC register to access. + * + * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte). + */ +static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + switch (cmd) { + case NAND_CTL_SETCLE: + hwctl |= 0x1; + break; + case NAND_CTL_CLRCLE: + hwctl &= ~0x1; + break; + case NAND_CTL_SETALE: + hwctl |= 0x2; + break; + case NAND_CTL_CLRALE: + hwctl &= ~0x2; + break; + case NAND_CTL_SETNCE: + break; + case NAND_CTL_CLRNCE: + writeb(0x00, &(alpr_ndfc->term)); + break; + } +} + +static void alpr_nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + struct nand_chip *nand = mtd->priv; + + if (hwctl & 0x1) + /* + * IO_ADDR_W used as CMD[i] reg to support multiple NAND + * chips. + */ + writeb(byte, nand->IO_ADDR_W); + else if (hwctl & 0x2) { + writeb(byte, &(alpr_ndfc->addr_wait)); + } else + writeb(byte, &(alpr_ndfc->data)); +} + +static u_char alpr_nand_read_byte(struct mtd_info *mtd) +{ + return readb(&(alpr_ndfc->data)); +} + +static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + struct nand_chip *nand = mtd->priv; + int i; + + for (i = 0; i < len; i++) { + if (hwctl & 0x1) + /* + * IO_ADDR_W used as CMD[i] reg to support multiple NAND + * chips. + */ + writeb(buf[i], nand->IO_ADDR_W); + else if (hwctl & 0x2) + writeb(buf[i], &(alpr_ndfc->addr_wait)); + else + writeb(buf[i], &(alpr_ndfc->data)); + } +} + +static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) { + buf[i] = readb(&(alpr_ndfc->data)); + } +} + +static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + if (buf[i] != readb(&(alpr_ndfc->data))) + return i; + + return 0; +} + +static int alpr_nand_dev_ready(struct mtd_info *mtd) +{ + volatile u_char val; + + /* + * Blocking read to wait for NAND to be ready + */ + val = readb(&(alpr_ndfc->addr_wait)); + + /* + * Return always true + */ + return 1; +} + +void board_nand_init(struct nand_chip *nand) +{ + alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE; + + nand->eccmode = NAND_ECC_SOFT; + + /* Reference hardware control function */ + nand->hwcontrol = alpr_nand_hwcontrol; + /* Set command delay time */ + nand->write_byte = alpr_nand_write_byte; + nand->read_byte = alpr_nand_read_byte; + nand->write_buf = alpr_nand_write_buf; + nand->read_buf = alpr_nand_read_buf; + nand->verify_buf = alpr_nand_verify_buf; + nand->dev_ready = alpr_nand_dev_ready; +} +#endif diff --git a/board/prodrive/alpr/u-boot.lds b/board/prodrive/alpr/u-boot.lds new file mode 100644 index 0000000000..4f04089c94 --- /dev/null +++ b/board/prodrive/alpr/u-boot.lds @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/prodrive/alpr/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/prodrive/common/flash.c b/board/prodrive/common/flash.c index 8630cc1664..363631fd84 100644 --- a/board/prodrive/common/flash.c +++ b/board/prodrive/common/flash.c @@ -48,6 +48,7 @@ void flash_print_info(flash_info_t *info) case FLASH_MAN_AMD: printf ("AMD "); break; case FLASH_MAN_FUJ: printf ("FUJITSU "); break; case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("ST "); break; case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; default: printf ("Unknown Vendor "); break; } @@ -156,6 +157,9 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; + case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: info->flash_id = FLASH_MAN_EXCEL; break; diff --git a/board/tqm5200/cam5200_flash.c b/board/tqm5200/cam5200_flash.c index 1a40633e56..8c3f62e398 100644 --- a/board/tqm5200/cam5200_flash.c +++ b/board/tqm5200/cam5200_flash.c @@ -759,7 +759,7 @@ unsigned long flash_init(void) if (flash_info[i].flash_id == FLASH_UNKNOWN) { printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); + i+1, size_b[i], size_b[i] << 20); flash_info[i].sector_count = -1; flash_info[i].size = 0; } diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index cb57a5e269..a4322b6661 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -289,7 +289,7 @@ int checkboard (void) #elif defined(CONFIG_TB5200) # define CARRIER_NAME "TB5200" #elif defined(CONFIG_CAM5200) -# define CARRIER_NAME "Cam5200" +# define CARRIER_NAME "CAM5200" #elif defined(CONFIG_FO300) # define CARRIER_NAME "FO300" #else diff --git a/common/Makefile b/common/Makefile index 07ddc95453..0106088e24 100644 --- a/common/Makefile +++ b/common/Makefile @@ -41,7 +41,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \ cmd_pci.o cmd_pcmcia.o cmd_portio.o \ cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \ cmd_usb.o cmd_vfd.o \ - command.o console.o devices.o dlmalloc.o docecc.o \ + command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \ environment.o env_common.o \ env_nand.o env_dataflash.o env_flash.o env_eeprom.o \ env_nvram.o env_nowhere.o \ diff --git a/common/altera.c b/common/altera.c index ebd50382c6..06e8a95015 100644 --- a/common/altera.c +++ b/common/altera.c @@ -50,15 +50,20 @@ int altera_load( Altera_desc *desc, void *buf, size_t bsize ) { int ret_val = FPGA_FAIL; /* assume a failure */ - if (!altera_validate (desc, __FUNCTION__)) { + if (!altera_validate (desc, (char *)__FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); } else { switch (desc->family) { case Altera_ACEX1K: + case Altera_CYC2: #if (CONFIG_FPGA & CFG_ACEX1K) PRINTF ("%s: Launching the ACEX1K Loader...\n", __FUNCTION__); ret_val = ACEX1K_load (desc, buf, bsize); +#elif (CONFIG_FPGA & CFG_CYCLON2) + PRINTF ("%s: Launching the CYCLON II Loader...\n", + __FUNCTION__); + ret_val = CYC2_load (desc, buf, bsize); #else printf ("%s: No support for ACEX1K devices.\n", __FUNCTION__); @@ -78,7 +83,7 @@ int altera_dump( Altera_desc *desc, void *buf, size_t bsize ) { int ret_val = FPGA_FAIL; /* assume a failure */ - if (!altera_validate (desc, __FUNCTION__)) { + if (!altera_validate (desc, (char *)__FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); } else { switch (desc->family) { @@ -106,13 +111,16 @@ int altera_info( Altera_desc *desc ) { int ret_val = FPGA_FAIL; - if (altera_validate (desc, __FUNCTION__)) { + if (altera_validate (desc, (char *)__FUNCTION__)) { printf ("Family: \t"); switch (desc->family) { case Altera_ACEX1K: printf ("ACEX1K\n"); break; /* Add new family types here */ + case Altera_CYC2: + printf ("CYCLON II\n"); + break; default: printf ("Unknown family type, %d\n", desc->family); } @@ -147,8 +155,11 @@ int altera_info( Altera_desc *desc ) printf ("Device Function Table @ 0x%p\n", desc->iface_fns); switch (desc->family) { case Altera_ACEX1K: + case Altera_CYC2: #if (CONFIG_FPGA & CFG_ACEX1K) ACEX1K_info (desc); +#elif (CONFIG_FPGA & CFG_CYCLON2) + CYC2_info (desc); #else /* just in case */ printf ("%s: No support for ACEX1K devices.\n", @@ -176,7 +187,7 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset) { int ret_val = FPGA_FAIL; /* assume a failure */ - if (!altera_validate (desc, __FUNCTION__)) { + if (!altera_validate (desc, (char *)__FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); } else { switch (desc->family) { @@ -188,6 +199,14 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset) __FUNCTION__); #endif break; + case Altera_CYC2: +#if (CONFIG_FPGA & CFG_CYCLON2) + ret_val = CYC2_reloc (desc, reloc_offset); +#else + printf ("%s: No support for CYCLON II devices.\n", + __FUNCTION__); +#endif + break; /* Add new family types here */ default: printf ("%s: Unsupported family type, %d\n", diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 3091a58897..7aae8a6d1b 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -833,10 +833,6 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, printf ("ERROR: flat device tree size does not agree with image\n"); return; } - - } else if (getenv("disable_of") == NULL) { - printf ("ERROR: bootm needs flat device tree as third argument\n"); - return; } #endif if (!data) { @@ -913,23 +909,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, SHOW_BOOT_PROGRESS (15); -#ifndef CONFIG_OF_FLAT_TREE - #if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) unlock_ram_in_cache(); #endif - /* - * Linux Kernel Parameters: - * r3: ptr to board info data - * r4: initrd_start or 0 if no initrd - * r5: initrd_end - unused if r4 is 0 - * r6: Start of command line string - * r7: End of command line string - */ - (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); - -#else /* CONFIG_OF_FLAT_TREE */ +#ifdef CONFIG_OF_FLAT_TREE /* move of_flat_tree if needed */ if (of_data) { ulong of_start, of_len; @@ -948,30 +932,36 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, of_start, of_start + of_len - 1); memmove ((void *)of_start, (void *)of_data, of_len); } +#endif - ft_setup(of_flat_tree, kbd, initrd_start, initrd_end); - /* ft_dump_blob(of_flat_tree); */ - -#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) - unlock_ram_in_cache(); + /* + * Linux Kernel Parameters (passing board info data): + * r3: ptr to board info data + * r4: initrd_start or 0 if no initrd + * r5: initrd_end - unused if r4 is 0 + * r6: Start of command line string + * r7: End of command line string + */ +#ifdef CONFIG_OF_FLAT_TREE + if (!of_flat_tree) /* no device tree; boot old style */ #endif + (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); + /* does not return */ + +#ifdef CONFIG_OF_FLAT_TREE /* - * Linux Kernel Parameters: + * Linux Kernel Parameters (passing device tree): * r3: ptr to OF flat tree, followed by the board info data * r4: physical pointer to the kernel itself * r5: NULL * r6: NULL * r7: NULL */ - if (getenv("disable_of") != NULL) - (*kernel) ((bd_t *)of_flat_tree, initrd_start, initrd_end, - cmd_start, cmd_end); - else { - ft_setup(of_flat_tree, kbd, initrd_start, initrd_end); - /* ft_dump_blob(of_flat_tree); */ - (*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0); - } -#endif /* CONFIG_OF_FLAT_TREE */ + ft_setup(of_flat_tree, kbd, initrd_start, initrd_end); + /* ft_dump_blob(of_flat_tree); */ + + (*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0); +#endif } #endif /* CONFIG_PPC */ diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index 9a01e7df8b..3444091858 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -55,6 +55,7 @@ static int fpga_get_op (char *opstr); #define FPGA_LOAD 1 #define FPGA_LOADB 2 #define FPGA_DUMP 3 +#define FPGA_LOADMK 4 /* Convert bitstream data and load into the fpga */ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) @@ -251,6 +252,23 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) rc = fpga_loadbitstream(dev, fpga_data, data_size); break; + case FPGA_LOADMK: + { + image_header_t header; + image_header_t *hdr = &header; + ulong data; + + memmove (&header, (char *)fpga_data, sizeof(image_header_t)); + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + puts ("Bad Magic Number\n"); + return 1; + } + data = ((ulong)fpga_data + sizeof(image_header_t)); + data_size = ntohl(hdr->ih_size); + rc = fpga_load (dev, (void *)data, data_size); + } + break; + case FPGA_DUMP: rc = fpga_dump (dev, fpga_data, data_size); break; @@ -282,6 +300,8 @@ static int fpga_get_op (char *opstr) op = FPGA_LOADB; } else if (!strcmp ("load", opstr)) { op = FPGA_LOAD; + } else if (!strcmp ("loadmk", opstr)) { + op = FPGA_LOADMK; } else if (!strcmp ("dump", opstr)) { op = FPGA_DUMP; } @@ -299,5 +319,6 @@ U_BOOT_CMD (fpga, 6, 1, do_fpga, "\tinfo\tlist known device information\n" "\tload\tLoad device from memory buffer\n" "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n" + "\tloadmk\tLoad device generated with mkimage\n" "\tdump\tLoad device to memory buffer\n"); #endif /* CONFIG_FPGA && CONFIG_COMMANDS & CFG_CMD_FPGA */ diff --git a/common/cyclon2.c b/common/cyclon2.c new file mode 100644 index 0000000000..dce13b50d0 --- /dev/null +++ b/common/cyclon2.c @@ -0,0 +1,305 @@ +/* + * (C) Copyright 2006 + * Heiko Schocher, hs@denx.de + * Based on ACE1XK.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> /* core U-Boot definitions */ +#include <altera.h> +#include <ACEX1K.h> /* ACEX device family */ + +#if (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) + +/* Define FPGA_DEBUG to get debug printf's */ +#ifdef FPGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +/* Note: The assumption is that we cannot possibly run fast enough to + * overrun the device (the Slave Parallel mode can free run at 50MHz). + * If there is a need to operate slower, define CONFIG_FPGA_DELAY in + * the board config file to slow things down. + */ +#ifndef CONFIG_FPGA_DELAY +#define CONFIG_FPGA_DELAY() +#endif + +#ifndef CFG_FPGA_WAIT +#define CFG_FPGA_WAIT CFG_HZ/10 /* 100 ms */ +#endif + +static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize ); +static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); +/* static int CYC2_ps_info( Altera_desc *desc ); */ +static int CYC2_ps_reloc( Altera_desc *desc, ulong reloc_offset ); + +/* ------------------------------------------------------------------------- */ +/* CYCLON2 Generic Implementation */ +int CYC2_load (Altera_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case passive_serial: + PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__); + ret_val = CYC2_ps_load (desc, buf, bsize); + break; + + /* Add new interface types here */ + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + +int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case passive_serial: + PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__); + ret_val = CYC2_ps_dump (desc, buf, bsize); + break; + + /* Add new interface types here */ + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + +int CYC2_info( Altera_desc *desc ) +{ + return FPGA_SUCCESS; +} + +int CYC2_reloc (Altera_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; /* assume a failure */ + + if (desc->family != Altera_CYC2) { + printf ("%s: Unsupported family type, %d\n", + __FUNCTION__, desc->family); + return FPGA_FAIL; + } else + switch (desc->iface) { + case passive_serial: + ret_val = CYC2_ps_reloc (desc, reloc_offset); + break; + + /* Add new interface types here */ + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + +/* ------------------------------------------------------------------------- */ +/* CYCLON2 Passive Serial Generic Implementation */ +static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns; + int ret = 0; + + PRINTF ("%s: start with interface functions @ 0x%p\n", + __FUNCTION__, fn); + + if (fn) { + int cookie = desc->cookie; /* make a local copy */ + unsigned long ts; /* timestamp */ + + PRINTF ("%s: Function Table:\n" + "ptr:\t0x%p\n" + "struct: 0x%p\n" + "config:\t0x%p\n" + "status:\t0x%p\n" + "write:\t0x%p\n" + "done:\t0x%p\n\n", + __FUNCTION__, &fn, fn, fn->config, fn->status, + fn->write, fn->done); +#ifdef CFG_FPGA_PROG_FEEDBACK + printf ("Loading FPGA Device %d...", cookie); +#endif + + /* + * Run the pre configuration function if there is one. + */ + if (*fn->pre) { + (*fn->pre) (cookie); + } + + /* Establish the initial state */ + (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */ + + udelay(2); /* T_cfg > 2us */ + + /* Wait for nSTATUS to be asserted */ + ts = get_timer (0); /* get current time */ + do { + CONFIG_FPGA_DELAY (); + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for STATUS to go high.\n"); + (*fn->abort) (cookie); + return FPGA_FAIL; + } + } while (!(*fn->status) (cookie)); + + /* Get ready for the burn */ + CONFIG_FPGA_DELAY (); + + ret = (*fn->write) (buf, bsize, TRUE, cookie); + if (ret) { + puts ("** Write failed.\n"); + (*fn->abort) (cookie); + return FPGA_FAIL; + } +#ifdef CFG_FPGA_PROG_FEEDBACK + puts(" OK? ..."); +#endif + + CONFIG_FPGA_DELAY (); + +#ifdef CFG_FPGA_PROG_FEEDBACK + putc (' '); /* terminate the dotted line */ +#endif + + /* + * Checking FPGA's CONF_DONE signal - correctly booted ? + */ + + if ( ! (*fn->done) (cookie) ) { + puts ("** Booting failed! CONF_DONE is still deasserted.\n"); + (*fn->abort) (cookie); + return (FPGA_FAIL); + } +#ifdef CFG_FPGA_PROG_FEEDBACK + puts(" OK\n"); +#endif + + ret_val = FPGA_SUCCESS; + +#ifdef CFG_FPGA_PROG_FEEDBACK + if (ret_val == FPGA_SUCCESS) { + puts ("Done.\n"); + } + else { + puts ("Fail.\n"); + } +#endif + (*fn->post) (cookie); + + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; +} + +static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize) +{ + /* Readback is only available through the Slave Parallel and */ + /* boundary-scan interfaces. */ + printf ("%s: Passive Serial Dumping is unavailable\n", + __FUNCTION__); + return FPGA_FAIL; +} + +static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Altera_CYC2_Passive_Serial_fns *fn_r, *fn = + (Altera_CYC2_Passive_Serial_fns *) (desc->iface_fns); + + if (fn) { + ulong addr; + + /* Get the relocated table address */ + addr = (ulong) fn + reloc_offset; + fn_r = (Altera_CYC2_Passive_Serial_fns *) addr; + + if (!fn_r->relocated) { + + if (memcmp (fn_r, fn, + sizeof (Altera_CYC2_Passive_Serial_fns)) + == 0) { + /* good copy of the table, fix the descriptor pointer */ + desc->iface_fns = fn_r; + } else { + PRINTF ("%s: Invalid function table at 0x%p\n", + __FUNCTION__, fn_r); + return FPGA_FAIL; + } + + PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, + desc); + + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Altera_pre_fn) addr; + + addr = (ulong) (fn->config) + reloc_offset; + fn_r->config = (Altera_config_fn) addr; + + addr = (ulong) (fn->status) + reloc_offset; + fn_r->status = (Altera_status_fn) addr; + + addr = (ulong) (fn->done) + reloc_offset; + fn_r->done = (Altera_done_fn) addr; + + addr = (ulong) (fn->write) + reloc_offset; + fn_r->write = (Altera_write_fn) addr; + + addr = (ulong) (fn->abort) + reloc_offset; + fn_r->abort = (Altera_abort_fn) addr; + + addr = (ulong) (fn->post) + reloc_offset; + fn_r->post = (Altera_post_fn) addr; + + fn_r->relocated = TRUE; + + } else { + /* this table has already been moved */ + /* XXX - should check to see if the descriptor is correct */ + desc->iface_fns = fn_r; + } + + ret_val = FPGA_SUCCESS; + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; +} + +#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) */ diff --git a/common/fpga.c b/common/fpga.c index 02d3e42b3b..2eff239c47 100644 --- a/common/fpga.c +++ b/common/fpga.c @@ -139,7 +139,7 @@ static int fpga_dev_info( int devnum ) printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc ); ret_val = xilinx_info( desc->devdesc ); #else - fpga_no_sup( __FUNCTION__, "Xilinx devices" ); + fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); #endif break; case fpga_altera: @@ -178,7 +178,7 @@ int fpga_reloc( fpga_type devtype, void *desc, ulong reloc_off ) #if CONFIG_FPGA & CFG_FPGA_XILINX ret_val = xilinx_reloc( desc, reloc_off ); #else - fpga_no_sup( __FUNCTION__, "Xilinx devices" ); + fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); #endif break; case fpga_altera: @@ -271,7 +271,7 @@ int fpga_load( int devnum, void *buf, size_t bsize ) #if CONFIG_FPGA & CFG_FPGA_XILINX ret_val = xilinx_load( desc->devdesc, buf, bsize ); #else - fpga_no_sup( __FUNCTION__, "Xilinx devices" ); + fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); #endif break; case fpga_altera: @@ -304,7 +304,7 @@ int fpga_dump( int devnum, void *buf, size_t bsize ) #if CONFIG_FPGA & CFG_FPGA_XILINX ret_val = xilinx_dump( desc->devdesc, buf, bsize ); #else - fpga_no_sup( __FUNCTION__, "Xilinx devices" ); + fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); #endif break; case fpga_altera: diff --git a/common/memsize.c b/common/memsize.c index dbc812dfc5..6c275c9b25 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -21,6 +21,16 @@ * MA 02111-1307 USA */ +#include <config.h> +#ifdef __PPC__ +/* + * At least on G2 PowerPC cores, sequential accesses to non-existent + * memory must be synchronized. + */ +# include <asm/io.h> /* for sync() */ +#else +# define sync() /* nothing */ +#endif /* * Check memory range for valid RAM. A simple memory test determines @@ -38,20 +48,27 @@ long get_ram_size(volatile long *base, long maxsize) for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { addr = base + cnt; /* pointer arith! */ + sync (); save[i++] = *addr; + sync (); *addr = ~cnt; } addr = base; + sync (); save[i] = *addr; + sync (); *addr = 0; + sync (); if ((val = *addr) != 0) { /* Restore the original data before leaving the function. */ + sync (); *addr = save[i]; for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) { addr = base + cnt; + sync (); *addr = save[--i]; } return (0); diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index 03128d3f6d..9b711e2ebf 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -475,7 +475,11 @@ void pci_440_init (struct pci_controller *hose) pci_set_region(hose->regions + reg_num++, CFG_PCI_TARGBASE, CFG_PCI_MEMBASE, +#ifdef CFG_PCI_MEMSIZE + CFG_PCI_MEMSIZE, +#else 0x10000000, +#endif PCI_REGION_MEM ); #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \ diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 81d49ffdfe..427ea94626 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -264,10 +264,10 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) bis->bi_phymode[3] = BI_PHYMODE_ZMII; break; case 2: - zmiifer = ZMII_FER_SMII << ZMII_FER_V(0); - zmiifer = ZMII_FER_SMII << ZMII_FER_V(1); - zmiifer = ZMII_FER_SMII << ZMII_FER_V(2); - zmiifer = ZMII_FER_SMII << ZMII_FER_V(3); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); bis->bi_phymode[0] = BI_PHYMODE_ZMII; bis->bi_phymode[1] = BI_PHYMODE_ZMII; bis->bi_phymode[2] = BI_PHYMODE_ZMII; @@ -470,8 +470,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #else if ((devnum == 0) || (devnum == 1)) { out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); - } - else { /* ((devnum == 2) || (devnum == 3)) */ + } else { /* ((devnum == 2) || (devnum == 3)) */ out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | (RGMII_FER_RGMII << RGMII_FER_V (3)))); @@ -561,22 +560,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) * otherwise, just check the speeds & feeds */ if (hw_p->first_init == 0) { -#if defined(CONFIG_88E1111_CLK_DELAY) - /* - * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs - * the "RGMII transmit timing control" and "RGMII receive - * timing control" bits set, so that Gbit communication works - * without problems. - * Also set the "Transmitter disable" to 1 to enable the - * transmitter. - * After setting these bits a soft-reset must occur for this - * change to become active. - */ - miiphy_read (dev->name, reg, 0x14, ®_short); - reg_short |= (1 << 7) | (1 << 1) | (1 << 0); - miiphy_write (dev->name, reg, 0x14, reg_short); -#endif -#if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */ +#if defined(CONFIG_M88E1111_PHY) miiphy_write (dev->name, reg, 0x14, 0x0ce3); miiphy_write (dev->name, reg, 0x18, 0x4101); miiphy_write (dev->name, reg, 0x09, 0x0e00); @@ -808,7 +792,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; hw_p->rx_ready[i] = -1; #if 0 - printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr); + printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr); #endif } diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index f4a7208c8f..447383f8d3 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -41,6 +41,10 @@ DECLARE_GLOBAL_DATA_PTR; #endif +#if defined(CONFIG_BOARD_RESET) +void board_reset(void); +#endif + #if defined(CONFIG_440) #define FREQ_EBC (sys_info.freqEPB) #else @@ -422,23 +426,19 @@ int ppc440spe_revB() { int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE) - /*give reset to BCSR*/ - *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09; - +#if defined(CONFIG_BOARD_RESET) + board_reset(); +#else +#if defined(CFG_4xx_RESET_TYPE) + mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28); #else - /* * Initiate system reset in debug control register DBCR */ - __asm__ __volatile__("lis 3, 0x3000" ::: "r3"); -#if defined(CONFIG_440) - __asm__ __volatile__("mtspr 0x134, 3"); -#else - __asm__ __volatile__("mtspr 0x3f2, 3"); -#endif + mtspr(dbcr0, 0x30000000); +#endif /* defined(CFG_4xx_RESET_TYPE) */ +#endif /* defined(CONFIG_BOARD_RESET) */ -#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/ return 1; } diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index def46f15ca..4b746b072e 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -321,6 +321,10 @@ cpu_init_f (void) #else val |= 0xf0000000; /* generate system reset after 2.684 seconds */ #endif +#if defined(CFG_4xx_RESET_TYPE) + val &= ~0x30000000; /* clear WRC bits */ + val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */ +#endif mtspr(tcr, val); val = mfspr(tsr); diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index faeea5c91e..f06038e998 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -351,6 +351,14 @@ long int initdram(int board_type) int i; int tr1_bank1; +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) + /* + * Soft-reset SDRAM controller. + */ + mtsdr(sdr_srst, SDR0_SRST_DMC); + mtsdr(sdr_srst, 0x00000000); +#endif + for (i=0; i<N_MB0CF; i++) { /* * Disable memory controller. diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 3fe13daaf3..8e000d3092 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -204,6 +204,18 @@ _start_440: mfspr r1,mcsr mtspr mcsr,r1 #endif + + /*----------------------------------------------------------------*/ + /* CCR0 init */ + /*----------------------------------------------------------------*/ + /* Disable store gathering & broadcast, guarantee inst/data + * cache block touch, force load/store alignment + * (see errata 1.12: 440_33) + */ + lis r1,0x0030 /* store gathering & broadcast disable */ + ori r1,r1,0x6000 /* cache touch */ + mtspr ccr0,r1 + /*----------------------------------------------------------------*/ /* Initialize debug */ /*----------------------------------------------------------------*/ @@ -225,17 +237,6 @@ _start_440: mtspr dbsr,r1 /* Clear all valid bits */ skip_debug_init: - /*----------------------------------------------------------------*/ - /* CCR0 init */ - /*----------------------------------------------------------------*/ - /* Disable store gathering & broadcast, guarantee inst/data - * cache block touch, force load/store alignment - * (see errata 1.12: 440_33) - */ - lis r1,0x0030 /* store gathering & broadcast disable */ - ori r1,r1,0x6000 /* cache touch */ - mtspr ccr0,r1 - #if defined (CONFIG_440SPE) /*----------------------------------------------------------------+ | Initialize Core Configuration Reg1. diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index fd0a186828..9b10220fc7 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -4,11 +4,12 @@ * * Copyright (C) 2003 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> - * Modified to work with AMD flashes * * Copyright (C) 2004 * Ed Okerson - * Modified to work with little-endian systems. + * + * Copyright (C) 2006 + * Tolunay Orkun <listmember@orkun.us> * * See file CREDITS for list of people who contributed to this * project. @@ -28,17 +29,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * - * History - * 01/20/2004 - combined variants of original driver. - * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay) - * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud) - * 01/27/2004 - Little endian support Ed Okerson - * - * Tested Architectures - * Port Width Chip Width # of banks Flash Chip Board - * 32 16 1 28F128J3 seranoa/eagle - * 64 16 1 28F128J3 seranoa/falcon - * */ /* The DEBUG define must be before common to enable debugging */ @@ -54,21 +44,16 @@ * This file implements a Common Flash Interface (CFI) driver for U-Boot. * The width of the port and the width of the chips are determined at initialization. * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation and AMD 29F016D. * * References * JEDEC Standard JESD68 - Common Flash Interface (CFI) * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * AMD CFI Specification, Release 2.0 December 1, 2001 + * AMD/Spansion Application Note: Migration from Single-byte to Three-byte + * Device IDs, Publication Number 25538 Revision A, November 8, 2001 * - * TODO - * - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query - * Table (ALT) to determine if protection is available - * - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. */ #ifndef CFG_FLASH_BANKS_LIST @@ -114,6 +99,10 @@ #define AMD_ADDR_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555) #define AMD_ADDR_ACK ((info->portwidth == FLASH_CFI_8BIT) ? 0x555 : 0x2AA) +#define FLASH_OFFSET_MANUFACTURER_ID 0x00 +#define FLASH_OFFSET_DEVICE_ID 0x01 +#define FLASH_OFFSET_DEVICE_ID2 0x0E +#define FLASH_OFFSET_DEVICE_ID3 0x0F #define FLASH_OFFSET_CFI 0x55 #define FLASH_OFFSET_CFI_RESP 0x10 #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 @@ -135,25 +124,20 @@ #define FLASH_OFFSET_USER_PROTECTION 0x85 #define FLASH_OFFSET_INTEL_PROTECTION 0x81 - -#define FLASH_MAN_CFI 0x01000000 - -#define CFI_CMDSET_NONE 0 -#define CFI_CMDSET_INTEL_EXTENDED 1 -#define CFI_CMDSET_AMD_STANDARD 2 -#define CFI_CMDSET_INTEL_STANDARD 3 -#define CFI_CMDSET_AMD_EXTENDED 4 -#define CFI_CMDSET_MITSU_STANDARD 256 -#define CFI_CMDSET_MITSU_EXTENDED 257 -#define CFI_CMDSET_SST 258 - +#define CFI_CMDSET_NONE 0 +#define CFI_CMDSET_INTEL_EXTENDED 1 +#define CFI_CMDSET_AMD_STANDARD 2 +#define CFI_CMDSET_INTEL_STANDARD 3 +#define CFI_CMDSET_AMD_EXTENDED 4 +#define CFI_CMDSET_MITSU_STANDARD 256 +#define CFI_CMDSET_MITSU_EXTENDED 257 +#define CFI_CMDSET_SST 258 #ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ # undef FLASH_CMD_RESET -# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ +# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ #endif - typedef union { unsigned char c; unsigned short w; @@ -168,7 +152,7 @@ typedef union { volatile unsigned long long *llp; } cfiptr_t; -#define NUM_ERASE_REGIONS 4 +#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ /* use CFG_MAX_FLASH_BANKS_DETECT if defined */ #ifdef CFG_MAX_FLASH_BANKS_DETECT @@ -200,6 +184,7 @@ static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect); static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static void flash_read_jedec_ids (flash_info_t * info); static int flash_detect_cfi (flash_info_t * info); static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword); static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, @@ -307,7 +292,7 @@ ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset) } /*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum + * read a long word by picking the least significant byte of each maximum * port size word. Swap for ppc format. */ ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset) @@ -529,14 +514,42 @@ void flash_print_info (flash_info_t * info) (info->portwidth << 3), (info->chipwidth << 3)); printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + printf (" "); + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + printf ("Intel Standard"); + break; + case CFI_CMDSET_INTEL_EXTENDED: + printf ("Intel Extended"); + break; + case CFI_CMDSET_AMD_STANDARD: + printf ("AMD Standard"); + break; + case CFI_CMDSET_AMD_EXTENDED: + printf ("AMD Extended"); + break; + default: + printf ("Unknown (%d)", info->vendor); + break; + } + printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x%02X", + info->manufacturer_id, info->device_id); + if (info->device_id == 0x7E) { + printf("%04X", info->device_id2); + } + printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n", info->erase_blk_tout, - info->write_tout, + info->write_tout); + if (info->buffer_size > 1) { + printf (" Buffer write timeout: %ld ms, buffer size: %d bytes\n", info->buffer_write_tout, info->buffer_size); + } - puts (" Sector Start Addresses:"); + puts ("\n Sector Start Addresses:"); for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n"); #ifdef CFG_FLASH_EMPTY_INFO int k; int size; @@ -560,18 +573,15 @@ void flash_print_info (flash_info_t * info) } } - if ((i % 5) == 0) - printf ("\n"); /* print empty and read-only info */ - printf (" %08lX%s%s", + printf (" %08lX %c %s ", info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); + erased ? 'E' : ' ', + info->protect[i] ? "RO" : " "); #else /* ! CFG_FLASH_EMPTY_INFO */ - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); + printf (" %08lX %s ", + info->start[i], + info->protect[i] ? "RO" : " "); #endif } putc ('\n'); @@ -1071,6 +1081,55 @@ static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uc } /*----------------------------------------------------------------------- + * read jedec ids from device and set corresponding fields in info struct + * + * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct + * +*/ +static void flash_read_jedec_ids (flash_info_t * info) +{ + info->manufacturer_id = 0; + info->device_id = 0; + info->device_id2 = 0; + + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); + udelay(1000); /* some flash are slow to respond */ + info->manufacturer_id = flash_read_uchar (info, + FLASH_OFFSET_MANUFACTURER_ID); + info->device_id = flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID); + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); + flash_unlock_seq(info, 0); + flash_write_cmd(info, 0, AMD_ADDR_START, FLASH_CMD_READ_ID); + udelay(1000); /* some flash are slow to respond */ + info->manufacturer_id = flash_read_uchar (info, + FLASH_OFFSET_MANUFACTURER_ID); + info->device_id = flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID); + if (info->device_id == 0x7E) { + /* AMD 3-byte (expanded) device ids */ + info->device_id2 = flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID2); + info->device_id2 <<= 8; + info->device_id2 |= flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID3); + } + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); + break; + default: + break; + } +} + +/*----------------------------------------------------------------------- * detect if flash is compatible with the Common Flash Interface (CFI) * http://www.jedec.org/download/search/jesd68.pdf * @@ -1120,15 +1179,31 @@ ulong flash_get_size (ulong base, int banknum) uchar num_erase_regions; int erase_region_size; int erase_region_count; + int geometry_reversed = 0; + + info->ext_addr = 0; + info->cfi_version = 0; #ifdef CFG_FLASH_PROTECTION - int ext_addr; info->legacy_unlock = 0; #endif info->start[0] = base; if (flash_detect_cfi (info)) { - info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR); + info->vendor = flash_read_ushort (info, 0, + FLASH_OFFSET_PRIMARY_VENDOR); + flash_read_jedec_ids (info); + flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + num_erase_regions = flash_read_uchar (info, + FLASH_OFFSET_NUM_ERASE_REGIONS); + info->ext_addr = flash_read_ushort (info, 0, + FLASH_OFFSET_EXT_QUERY_T_P_ADDR); + if (info->ext_addr) { + info->cfi_version = (ushort) flash_read_uchar (info, + info->ext_addr + 3) << 8; + info->cfi_version |= (ushort) flash_read_uchar (info, + info->ext_addr + 4); + } #ifdef DEBUG flash_printqry (info, 0); #endif @@ -1139,26 +1214,46 @@ ulong flash_get_size (ulong base, int banknum) info->cmd_reset = FLASH_CMD_RESET; #ifdef CFG_FLASH_PROTECTION /* read legacy lock/unlock bit from intel flash */ - ext_addr = flash_read_ushort (info, 0, - FLASH_OFFSET_EXT_QUERY_T_P_ADDR); - info->legacy_unlock = - flash_read_uchar (info, ext_addr + 5) & 0x08; + if (info->ext_addr) { + info->legacy_unlock = flash_read_uchar (info, + info->ext_addr + 5) & 0x08; + } #endif break; case CFI_CMDSET_AMD_STANDARD: case CFI_CMDSET_AMD_EXTENDED: info->cmd_reset = AMD_CMD_RESET; + /* check if flash geometry needs reversal */ + if (num_erase_regions <= 1) + break; + /* reverse geometry if top boot part */ + if (info->cfi_version < 0x3131) { + /* CFI < 1.1, try to guess from device id */ + if ((info->device_id & 0x80) != 0) { + geometry_reversed = 1; + } + break; + } + /* CFI >= 1.1, deduct from top/bottom flag */ + /* note: ext_addr is valid since cfi_version > 0 */ + if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { + geometry_reversed = 1; + } break; } debug ("manufacturer is %d\n", info->vendor); + debug ("manufacturer id is 0x%x\n", info->manufacturer_id); + debug ("device id is 0x%x\n", info->device_id); + debug ("device id2 is 0x%x\n", info->device_id2); + debug ("cfi version is 0x%04x\n", info->cfi_version); + size_ratio = info->portwidth / info->chipwidth; /* if the chip is x8/x16 reduce the ratio by half */ if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) { size_ratio >>= 1; } - num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS); debug ("size_ratio %d port %d bits chip %d bits\n", size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); @@ -1171,7 +1266,12 @@ ulong flash_get_size (ulong base, int banknum) num_erase_regions, NUM_ERASE_REGIONS); break; } - tmp = flash_read_long (info, 0, + if (geometry_reversed) + tmp = flash_read_long (info, 0, + FLASH_OFFSET_ERASE_REGIONS + + (num_erase_regions - 1 - i) * 4); + else + tmp = flash_read_long (info, 0, FLASH_OFFSET_ERASE_REGIONS + i * 4); erase_region_size = diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c index 6b13c4e0e3..851df1176d 100644 --- a/drivers/nand/nand_base.c +++ b/drivers/nand/nand_base.c @@ -838,9 +838,9 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state) unsigned long timeo; if (state == FL_ERASING) - timeo = CFG_HZ * 400; + timeo += (HZ * 400) / 1000; else - timeo = CFG_HZ * 20; + timeo += (HZ * 20) / 1000; if ((state == FL_ERASING) && (this->options & NAND_IS_AND)) this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); @@ -852,8 +852,8 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state) while (1) { if (get_timer(0) > timeo) { printf("Timeout!"); - return 0; - } + return 0x01; + } if (this->dev_ready) { if (this->dev_ready(mtd)) @@ -2408,7 +2408,9 @@ int nand_scan (struct mtd_info *mtd, int maxchips) } if (!nand_flash_ids[i].name) { +#ifndef CFG_NAND_QUIET_TEST printk (KERN_WARNING "No NAND device found!!!\n"); +#endif this->select_chip(mtd, -1); return 1; } diff --git a/include/ACEX1K.h b/include/ACEX1K.h index f75c463f33..f249d6402d 100644 --- a/include/ACEX1K.h +++ b/include/ACEX1K.h @@ -35,6 +35,11 @@ extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize ); extern int ACEX1K_info( Altera_desc *desc ); extern int ACEX1K_reloc( Altera_desc *desc, ulong reloc_off ); +extern int CYC2_load( Altera_desc *desc, void *image, size_t size ); +extern int CYC2_dump( Altera_desc *desc, void *buf, size_t bsize ); +extern int CYC2_info( Altera_desc *desc ); +extern int CYC2_reloc( Altera_desc *desc, ulong reloc_off ); + /* Slave Serial Implementation function table */ typedef struct { Altera_pre_fn pre; @@ -48,6 +53,18 @@ typedef struct { int relocated; } Altera_ACEX1K_Passive_Serial_fns; +/* Slave Serial Implementation function table */ +typedef struct { + Altera_pre_fn pre; + Altera_config_fn config; + Altera_status_fn status; + Altera_done_fn done; + Altera_write_fn write; + Altera_abort_fn abort; + Altera_post_fn post; + int relocated; +} Altera_CYC2_Passive_Serial_fns; + /* Device Image Sizes *********************************************************************/ /* ACEX1K */ @@ -60,6 +77,8 @@ typedef struct { #endif #define Altera_EP1K100_SIZE (166965*8) +#define Altera_EP2C35_SIZE 883905 + /* Descriptor Macros *********************************************************************/ /* ACEX1K devices */ diff --git a/include/altera.h b/include/altera.h index 74b6729f90..7b8cb4a55d 100644 --- a/include/altera.h +++ b/include/altera.h @@ -34,8 +34,10 @@ /* Altera Model definitions *********************************************************************/ #define CFG_ACEX1K CFG_FPGA_DEV( 0x1 ) +#define CFG_CYCLON2 CFG_FPGA_DEV( 0x2 ) #define CFG_ALTERA_ACEX1K (CFG_FPGA_ALTERA | CFG_ACEX1K) +#define CFG_ALTERA_CYCLON2 (CFG_FPGA_ALTERA | CFG_CYCLON2) /* Add new models here */ /* Altera Interface definitions @@ -56,6 +58,7 @@ typedef enum { /* typedef Altera_iface */ typedef enum { /* typedef Altera_Family */ min_altera_type, /* insert all new types after this */ Altera_ACEX1K, /* ACEX1K Family */ + Altera_CYC2, /* CYCLONII Family */ /* Add new models here */ max_altera_type /* insert all new types before this */ } Altera_Family; /* end, typedef Altera_Family */ @@ -84,6 +87,7 @@ typedef int (*Altera_status_fn)( int cookie ); typedef int (*Altera_done_fn)( int cookie ); typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie ); typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie ); +typedef int (*Altera_write_fn)(void *buf, size_t len, int flush, int cookie); typedef int (*Altera_abort_fn)( int cookie ); typedef int (*Altera_post_fn)( int cookie ); diff --git a/include/common.h b/include/common.h index 0be8372cc5..982d6a8637 100644 --- a/include/common.h +++ b/include/common.h @@ -270,7 +270,7 @@ int misc_init_r (void); void jumptable_init(void); /* common/memsize.c */ -int get_ram_size (volatile long *, long); +long get_ram_size (volatile long *, long); /* $(BOARD)/$(BOARD).c */ void reset_phy (void); diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 4bae103e09..08674ca49f 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -217,43 +217,19 @@ #undef CONFIG_BOOTARGS -#ifdef CONFIG_STK52XX -# if defined(CONFIG_TQM5200_B) -# if defined(CFG_LOWBOOT) -# define ENV_UPDT \ - "update=protect off FC000000 FC07FFFF;" \ - "erase FC000000 FC07FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC07FFFF\0" -# else /* highboot */ -# define ENV_UPDT \ - "update=protect off FFF00000 FFF7FFFF;" \ - "erase FFF00000 FFF7FFFF;" \ +#if defined(CONFIG_TQM5200_B) && !defined(CFG_LOWBOOT) +# define ENV_UPDT \ + "update=protect off FFF00000 +${filesize};" \ + "erase FFF00000 +${filesize};" \ "cp.b 200000 FFF00000 ${filesize};" \ - "protect on FFF00000 FFF7FFFF\0" -# endif /* CFG_LOWBOOT */ -# else /* !CONFIG_TQM5200_B */ -# define ENV_UPDT \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" -# endif /* CONFIG_TQM5200_B */ -#elif defined (CONFIG_CAM5200) -# define ENV_UPDT \ - "update=protect off FC000000 FC03FFFF;" \ - "erase FC000000 FC03FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC03FFFF\0" -#elif defined (CONFIG_FO300) + "protect on FFF00000 +${filesize}\0" +#else /* default lowboot configuration */ # define ENV_UPDT \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ + "update=protect off FC000000 +${filesize};" \ + "erase FC000000 +${filesize};" \ "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" -#else -# error "Unknown Carrier Board" -#endif /* CONFIG_STK52XX */ + "protect on FC000000 +${filesize}\0" +#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ @@ -432,7 +408,7 @@ */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */ -#if defined(CONFIG_TQM5200_B) +#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200) #define CFG_ENV_SECT_SIZE 0x40000 #else #define CFG_ENV_SECT_SIZE 0x20000 diff --git a/include/configs/alpr.h b/include/configs/alpr.h new file mode 100644 index 0000000000..bbe6b76bff --- /dev/null +++ b/include/configs/alpr.h @@ -0,0 +1,346 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_ALPR 1 /* Board is ebony */ +#define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ +#undef CFG_DRAM_TEST /* Disable-takes long time! */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + + +#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) +#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK +#define CONFIG_BAUDRATE 115200 +#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI 1 /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */ +#undef CONFIG_SDRAM_ECC /* enable ECC support */ +#define CFG_SDRAM_TABLE { \ + {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ + {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (PCF8594C) + *----------------------------------------------------------------------*/ +#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ + /* 8 byte page write mode using */ + /* last 3 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth3\0" \ + "hostname=alpr\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \ + "mem=193M\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/projects/alpr/nfs_root\0" \ + "bootfile=/alpr/uImage\0" \ + "kernel_addr=fff00000\0" \ + "ramdisk_addr=fff10000\0" \ + "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */ +#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */ +#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */ +#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */ +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_FPGA | \ + CFG_CMD_NAND | \ + CFG_CMD_REGINFO) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ +#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/*----------------------------------------------------------------------- + * FPGA stuff + *-----------------------------------------------------------------------*/ +#define CONFIG_FPGA CFG_ALTERA_CYCLON2 +#define CFG_FPGA_CHECK_CTRLC +#define CFG_FPGA_PROG_FEEDBACK +#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in + Reihe geschaltet -> sollte gehen, + aufpassen mit Datasize ist jetzt + halt doppelt so gross ... Seite 306 + ist das mit den multiple Device in PS + Mode erklaert ...*/ + +/* FPGA program pin configuration */ +#define CFG_GPIO_CLK 18 /* FPGA clk pin (cpu output) */ +#define CFG_GPIO_DATA 19 /* FPGA data pin (cpu output) */ +#define CFG_GPIO_STATUS 20 /* FPGA status pin (cpu input) */ +#define CFG_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */ +#define CFG_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */ + +#define CFG_GPIO_SEL_DPR 14 /* cpu output */ +#define CFG_GPIO_SEL_AVR 15 /* cpu output */ +#define CFG_GPIO_PROG_EN 23 /* cpu output */ + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup + *-----------------------------------------------------------------------*/ +#define CFG_GPIO_EREADY (0x80000000 >> 26) +#define CFG_GPIO_REV0 (0x80000000 >> 14) +#define CFG_GPIO_REV1 (0x80000000 >> 15) + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *-----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 4 +#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE +#define CFG_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE + 0, CFG_NAND_BASE + 2, \ + CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 } +#define CFG_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (NAND-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x01840380 /* TWT=3 */ +#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 3a76315b44..00b92220c1 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -53,7 +53,7 @@ #define CFG_BOOT_BASE_ADDR 0xf0000000 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ #define CFG_MONITOR_BASE TEXT_BASE #define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ #define CFG_OCM_BASE 0xe0010000 /* ocm */ @@ -102,6 +102,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #else #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ #endif /*----------------------------------------------------------------------- @@ -234,10 +235,10 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ + "rootpath=/opt/eldk/ppc_4xxFP\0" \ "bootfile=/tftpboot/sequoia/uImage\0" \ - "kernel_addr=FE000000\0" \ - "ramdisk_addr=FE180000\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC180000\0" \ "load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ "cp.b 100000 FFFA0000 60000\0" \ @@ -378,7 +379,7 @@ #define CFG_NAND_CS 3 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x03017300 -#define CFG_EBC_PB0CR (CFG_FLASH | 0xba000) +#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) /* Memory Bank 3 (NAND-FLASH) initialization */ #define CFG_EBC_PB3AP 0x018003c0 @@ -387,7 +388,7 @@ #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ /* Memory Bank 3 (NOR-FLASH) initialization */ #define CFG_EBC_PB3AP 0x03017300 -#define CFG_EBC_PB3CR (CFG_FLASH | 0xba000) +#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000) /* Memory Bank 0 (NAND-FLASH) initialization */ #define CFG_EBC_PB0AP 0x018003c0 diff --git a/include/configs/v38b.h b/include/configs/v38b.h index cf2d031c9f..554a7a41b8 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -34,7 +34,7 @@ #define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ #define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ -#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ +#undef CONFIG_HW_WATCHDOG /* don't use watchdog */ #define CONFIG_NETCONSOLE 1 @@ -246,7 +246,7 @@ /* * GPIO configuration */ -#define CFG_GPS_PORT_CONFIG 0x90000404 +#define CFG_GPS_PORT_CONFIG 0x90001404 /* * Miscellaneous configurable options diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h index ba27f37f6e..58717f8a60 100644 --- a/include/configs/yellowstone.h +++ b/include/configs/yellowstone.h @@ -37,6 +37,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_BOARD_RESET 1 /* call board_reset() */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 3d7b4a2f4b..6e942abcaa 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -37,6 +37,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_BOARD_RESET 1 /* call board_reset() */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the diff --git a/include/environment.h b/include/environment.h index 26b07120da..af605ab7a9 100644 --- a/include/environment.h +++ b/include/environment.h @@ -79,8 +79,7 @@ # ifdef CFG_ENV_OFFSET_REDUND # define CFG_REDUNDAND_ENVIRONMENT # endif -# if defined(CONFIG_NAND_U_BOOT) -/* Use embedded environment in NAND boot versions */ +# ifdef CFG_ENV_IS_EMBEDDED # define ENV_IS_EMBEDDED 1 # endif #endif /* CFG_ENV_IS_IN_NAND */ diff --git a/include/flash.h b/include/flash.h index d91589a6c0..9c57cbc427 100644 --- a/include/flash.h +++ b/include/flash.h @@ -43,9 +43,14 @@ typedef struct { ulong write_tout; /* maximum write timeout */ ulong buffer_write_tout; /* maximum buffer write timeout */ ushort vendor; /* the primary vendor id */ - ushort cmd_reset; /* Vendor specific reset command */ + ushort cmd_reset; /* vendor specific reset command */ ushort interface; /* used for x8/x16 adjustments */ ushort legacy_unlock; /* support Intel legacy (un)locking */ + uchar manufacturer_id; /* manufacturer id */ + ushort device_id; /* device id */ + ushort device_id2; /* extended device id */ + ushort ext_addr; /* extended query table address */ + ushort cfi_version; /* cfi version */ #endif } flash_info_t; @@ -439,6 +444,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define FLASH_MAN_MT 0x00400000 #define FLASH_MAN_SHARP 0x00500000 #define FLASH_MAN_ATM 0x00600000 +#define FLASH_MAN_CFI 0x01000000 #define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */ diff --git a/include/ppc440.h b/include/ppc440.h index e407320a9e..407daaebe8 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -3183,7 +3183,7 @@ #define GPIO0 0 #define GPIO1 1 -#if defined(CONFIG_440GP) +#if defined(CONFIG_440GP) || defined(CONFIG_440GX) #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) #define GPIO0_OR (GPIO0_BASE+0x0) |