diff options
84 files changed, 5082 insertions, 404 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c7ab166888..a8b7bdeaa6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -248,6 +248,7 @@ config ARCH_ZYNQ bool "Xilinx Zynq-based boards" select HAS_DEBUG_LL select PBL_IMAGE + select GPIOLIB config ARCH_ZYNQMP bool "Xilinx ZynqMP-based boards" @@ -258,6 +259,7 @@ config ARCH_ZYNQMP select COMMON_CLK select COMMON_CLK_OF_PROVIDER select CLKDEV_LOOKUP + select GPIOLIB select OFDEVICE select OFTREE select RELOCATABLE diff --git a/arch/arm/boards/guf-santaro/board.c b/arch/arm/boards/guf-santaro/board.c index 34005ff7bf..cfc85af59e 100644 --- a/arch/arm/boards/guf-santaro/board.c +++ b/arch/arm/boards/guf-santaro/board.c @@ -22,12 +22,11 @@ static int i2c_device_present(struct i2c_adapter *adapter, int addr) { struct i2c_client client = {}; - u8 reg; client.adapter = adapter; client.addr = addr; - return i2c_write_reg(&client, 0x00, ®, 0) < 0 ? false : true; + return i2c_write_reg(&client, 0x00, NULL, 0) < 0 ? false : true; } #define TOUCH_RESET_GPIO IMX_GPIO_NR(1, 20) diff --git a/arch/arm/boards/netgear-rn2120/board.c b/arch/arm/boards/netgear-rn2120/board.c index caf106af50..d5756e0969 100644 --- a/arch/arm/boards/netgear-rn2120/board.c +++ b/arch/arm/boards/netgear-rn2120/board.c @@ -2,7 +2,7 @@ #include <init.h> #include <of.h> #include <gpio.h> -#include <printk.h> +#include <linux/printk.h> #include <linux/kernel.h> #include <asm/armlinux.h> #include <generated/mach-types.h> diff --git a/arch/arm/configs/stm32mp_defconfig b/arch/arm/configs/stm32mp_defconfig index 49041b1f48..eb3c95b12c 100644 --- a/arch/arm/configs/stm32mp_defconfig +++ b/arch/arm/configs/stm32mp_defconfig @@ -82,6 +82,7 @@ CONFIG_CMD_FLASH=y CONFIG_CMD_GPIO=y CONFIG_CMD_LED=y CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SPI=y CONFIG_CMD_WD=y CONFIG_CMD_BAREBOX_UPDATE=y CONFIG_CMD_OF_DIFF=y @@ -102,9 +103,12 @@ CONFIG_DRIVER_NET_DESIGNWARE_STM32=y CONFIG_AT803X_PHY=y CONFIG_MICREL_PHY=y CONFIG_REALTEK_PHY=y -# CONFIG_SPI is not set +CONFIG_DRIVER_SPI_STM32=y CONFIG_I2C=y CONFIG_I2C_STM32=y +CONFIG_MTD=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SST25L=y CONFIG_USB_HOST=y CONFIG_USB_DWC2_HOST=y CONFIG_USB_DWC2_GADGET=y @@ -126,6 +130,7 @@ CONFIG_LED_GPIO=y CONFIG_LED_PWM=y CONFIG_LED_GPIO_OF=y CONFIG_LED_TRIGGERS=y +CONFIG_EEPROM_AT25=y CONFIG_EEPROM_AT24=y CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_SPECIALKEYS=y diff --git a/arch/arm/configs/zynq_defconfig b/arch/arm/configs/zynq_defconfig index a16c57d5ce..38662eeb5d 100644 --- a/arch/arm/configs/zynq_defconfig +++ b/arch/arm/configs/zynq_defconfig @@ -45,3 +45,4 @@ CONFIG_DRIVER_NET_MACB=y # CONFIG_PINCTRL is not set CONFIG_FS_TFTP=y CONFIG_DIGEST=y +CONFIG_GPIO_ZYNQ=y diff --git a/arch/arm/configs/zynqmp_defconfig b/arch/arm/configs/zynqmp_defconfig index 2cd8781332..8dd0f40b3d 100644 --- a/arch/arm/configs/zynqmp_defconfig +++ b/arch/arm/configs/zynqmp_defconfig @@ -64,3 +64,4 @@ CONFIG_FS_NFS=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_DIGEST=y +CONFIG_GPIO_ZYNQ=y diff --git a/arch/arm/mach-mvebu/kwb_bbu.c b/arch/arm/mach-mvebu/kwb_bbu.c index f79464fe53..3de575740c 100644 --- a/arch/arm/mach-mvebu/kwb_bbu.c +++ b/arch/arm/mach-mvebu/kwb_bbu.c @@ -1,6 +1,6 @@ #include <bbu.h> #include <libfile.h> -#include <printk.h> +#include <linux/printk.h> #include <mach/bbu.h> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 2786fadeaf..b2376c18d0 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -1,4 +1,3 @@ - menu "Rockchip Features" depends on ARCH_ROCKCHIP @@ -51,10 +50,10 @@ config MACH_RK3568_EVB help Say Y here if you are using a RK3568 EVB -endmenu - config ARCH_RK3568_OPTEE bool "Build OP-TEE binary into barebox" help With this option enabled the RK3568 OP-TEE binary is compiled into barebox and started along with the BL31 trusted firmware. + +endmenu diff --git a/commands/md.c b/commands/md.c index d80c7cca0c..7a96634e27 100644 --- a/commands/md.c +++ b/commands/md.c @@ -88,7 +88,7 @@ out: BAREBOX_CMD_HELP_START(md) -BAREBOX_CMD_HELP_TEXT("Display (hex dump) a memory region.") +BAREBOX_CMD_HELP_TEXT("Display (hex dump) a memory REGION.") BAREBOX_CMD_HELP_TEXT("") BAREBOX_CMD_HELP_TEXT("Options:") BAREBOX_CMD_HELP_OPT ("-b", "byte access") @@ -108,7 +108,7 @@ BAREBOX_CMD_HELP_END BAREBOX_CMD_START(md) .cmd = do_mem_md, BAREBOX_CMD_DESC("memory display") - BAREBOX_CMD_OPTS("[-bwlsx] REGION") + BAREBOX_CMD_OPTS("[-bwlqx] [-s FILE] REGION") BAREBOX_CMD_GROUP(CMD_GRP_MEM) BAREBOX_CMD_HELP(cmd_md_help) BAREBOX_CMD_END diff --git a/commands/memcmp.c b/commands/memcmp.c index 2b3783d66a..8122b99f17 100644 --- a/commands/memcmp.c +++ b/commands/memcmp.c @@ -97,7 +97,7 @@ BAREBOX_CMD_HELP_END BAREBOX_CMD_START(memcmp) .cmd = do_memcmp, BAREBOX_CMD_DESC("memory compare") - BAREBOX_CMD_OPTS("[-bwlsd] ADDR1 ADDR2 COUNT") + BAREBOX_CMD_OPTS("[-bwlq] [-s FILE] [-d FILE] ADDR1 ADDR2 COUNT") BAREBOX_CMD_GROUP(CMD_GRP_MEM) BAREBOX_CMD_HELP(cmd_memcmp_help) BAREBOX_CMD_END diff --git a/commands/memcpy.c b/commands/memcpy.c index 2477bba359..1b480f27f0 100644 --- a/commands/memcpy.c +++ b/commands/memcpy.c @@ -72,7 +72,9 @@ out: } BAREBOX_CMD_HELP_START(memcpy) -BAREBOX_CMD_HELP_TEXT("Copy memory at SRC of COUNT bytes to DEST") +BAREBOX_CMD_HELP_TEXT("Copy memory of COUNT bytes from offsets SRC to DEST.") +BAREBOX_CMD_HELP_TEXT("If source is a file, COUNT can be left unspecified") +BAREBOX_CMD_HELP_TEXT("in which case the whole file is copied.") BAREBOX_CMD_HELP_TEXT("") BAREBOX_CMD_HELP_TEXT("Options:") BAREBOX_CMD_HELP_OPT ("-b", "byte access") @@ -86,7 +88,7 @@ BAREBOX_CMD_HELP_END BAREBOX_CMD_START(memcpy) .cmd = do_memcpy, BAREBOX_CMD_DESC("memory copy") - BAREBOX_CMD_OPTS("[-bwlsd] SRC DEST COUNT") + BAREBOX_CMD_OPTS("[-bwlq] [-s FILE] [-d FILE] SRC DEST COUNT") BAREBOX_CMD_GROUP(CMD_GRP_MEM) BAREBOX_CMD_HELP(cmd_memcpy_help) BAREBOX_CMD_END diff --git a/commands/memset.c b/commands/memset.c index 716cba26de..e4412533f1 100644 --- a/commands/memset.c +++ b/commands/memset.c @@ -84,7 +84,7 @@ BAREBOX_CMD_HELP_END BAREBOX_CMD_START(memset) .cmd = do_memset, BAREBOX_CMD_DESC("memory fill") - BAREBOX_CMD_OPTS("[-bwld] ADDR DATA COUNT") + BAREBOX_CMD_OPTS("[-bwlq [-d FILE] ADDR DATA COUNT") BAREBOX_CMD_GROUP(CMD_GRP_MEM) BAREBOX_CMD_HELP(cmd_memset_help) BAREBOX_CMD_END diff --git a/commands/mm.c b/commands/mm.c index f6d66320fb..9ce8839644 100644 --- a/commands/mm.c +++ b/commands/mm.c @@ -116,7 +116,7 @@ BAREBOX_CMD_HELP_END BAREBOX_CMD_START(mm) .cmd = do_mem_mm, BAREBOX_CMD_DESC("memory modify with mask") - BAREBOX_CMD_OPTS("[-bwld] ADDR VAL MASK") + BAREBOX_CMD_OPTS("[-bwlq] [-d FILE] ADDR VAL MASK") BAREBOX_CMD_GROUP(CMD_GRP_MEM) BAREBOX_CMD_HELP(cmd_mm_help) BAREBOX_CMD_END diff --git a/commands/mw.c b/commands/mw.c index 5bd4bdd58f..5dcef7e2fc 100644 --- a/commands/mw.c +++ b/commands/mw.c @@ -110,12 +110,17 @@ BAREBOX_CMD_HELP_OPT ("-l", "long access (32 bit)") BAREBOX_CMD_HELP_OPT ("-q", "quad access (64 bit)") BAREBOX_CMD_HELP_OPT ("-d FILE", "write file (default /dev/mem)") BAREBOX_CMD_HELP_OPT ("-x", "swap bytes") +BAREBOX_CMD_HELP_TEXT("") +BAREBOX_CMD_HELP_TEXT("Memory regions can be specified in two different forms: START+SIZE") +BAREBOX_CMD_HELP_TEXT("or START-END, If START is omitted it defaults to 0x100") +BAREBOX_CMD_HELP_TEXT("Sizes can be specified as decimal, or if prefixed with 0x as hexadecimal.") +BAREBOX_CMD_HELP_TEXT("An optional suffix of k, M or G is for kbytes, Megabytes or Gigabytes.") BAREBOX_CMD_HELP_END BAREBOX_CMD_START(mw) .cmd = do_mem_mw, BAREBOX_CMD_DESC("memory write") - BAREBOX_CMD_OPTS("[-bwldx] REGION DATA...") + BAREBOX_CMD_OPTS("[-bwlqx] [-d FILE] REGION DATA...") BAREBOX_CMD_GROUP(CMD_GRP_MEM) BAREBOX_CMD_HELP(cmd_mw_help) BAREBOX_CMD_END diff --git a/commands/nandtest.c b/commands/nandtest.c index 1bb59c7fdb..4a7db9cc74 100644 --- a/commands/nandtest.c +++ b/commands/nandtest.c @@ -169,8 +169,10 @@ static int erase_and_write(loff_t ofs, unsigned char *data, printf("\ncompare failed. seed %d\n", seed); for (i = 0; i < meminfo.erasesize; i++) { if (data[i] != rbuf[i]) - printf("Byte 0x%x is %02x should be %02x\n", - i, rbuf[i], data[i]); + printf("Block 0x%llx byte 0x%0x (page 0x%x offset 0x%x) is %02x should be %02x\n", + div64_ul(ofs, meminfo.erasesize), i, + i / meminfo.writesize, i % meminfo.writesize, + rbuf[i], data[i]); } return ret; } diff --git a/common/bootchooser.c b/common/bootchooser.c index 2f22e03c47..75dfbc6166 100644 --- a/common/bootchooser.c +++ b/common/bootchooser.c @@ -13,7 +13,7 @@ #include <libfile.h> #include <common.h> #include <malloc.h> -#include <printk.h> +#include <linux/printk.h> #include <xfuncs.h> #include <envfs.h> #include <errno.h> diff --git a/common/optee.c b/common/optee.c index d542dde118..b460fbcd01 100644 --- a/common/optee.c +++ b/common/optee.c @@ -3,7 +3,7 @@ #define pr_fmt(fmt) "optee: " fmt #include <tee/optee.h> -#include <printk.h> +#include <linux/printk.h> #include <asm-generic/errno.h> int optee_verify_header(struct optee_header *hdr) diff --git a/common/startup.c b/common/startup.c index f72902fc53..f53b73f81a 100644 --- a/common/startup.c +++ b/common/startup.c @@ -68,70 +68,6 @@ static int mount_root(void) fs_initcall(mount_root); #endif -#ifdef CONFIG_ENV_HANDLING -static bool region_overlap(loff_t starta, loff_t lena, - loff_t startb, loff_t lenb) -{ - if (starta + lena <= startb) - return 0; - if (startb + lenb <= starta) - return 0; - return 1; -} - -static int check_overlap(const char *path) -{ - struct cdev *cenv, *cdisk, *cpart; - const char *name; - - name = devpath_to_name(path); - - if (name == path) - /* - * no /dev/ in front, so *path is some file. No need to - * check further. - */ - return 0; - - cenv = cdev_by_name(name); - if (!cenv) - return -EINVAL; - - if (cenv->mtd) - return 0; - - cdisk = cenv->master; - - if (!cdisk) - return 0; - - list_for_each_entry(cpart, &cdisk->partitions, partition_entry) { - if (cpart == cenv) - continue; - - if (region_overlap(cpart->offset, cpart->size, - cenv->offset, cenv->size)) - goto conflict; - } - - return 0; - -conflict: - pr_err("Environment partition (0x%08llx-0x%08llx) " - "overlaps with partition %s (0x%08llx-0x%08llx), not using it\n", - cenv->offset, cenv->offset + cenv->size - 1, - cpart->name, - cpart->offset, cpart->offset + cpart->size - 1); - - return -EINVAL; -} -#else -static int check_overlap(const char *path) -{ - return 0; -} -#endif - static int load_environment(void) { const char *default_environment_path; @@ -143,11 +79,7 @@ static int load_environment(void) defaultenv_load("/env", 0); if (IS_ENABLED(CONFIG_ENV_HANDLING)) { - ret = check_overlap(default_environment_path); - if (ret) - default_environment_path_set(NULL); - else - envfs_load(default_environment_path, "/env", 0); + envfs_load(default_environment_path, "/env", 0); } else { if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT)) pr_notice("No support for persistent environment. Using default environment\n"); diff --git a/common/state/backend_bucket_direct.c b/common/state/backend_bucket_direct.c index 4522f0170f..517aec6063 100644 --- a/common/state/backend_bucket_direct.c +++ b/common/state/backend_bucket_direct.c @@ -17,7 +17,7 @@ #include <libfile.h> #include <linux/kernel.h> #include <malloc.h> -#include <printk.h> +#include <linux/printk.h> #include "state.h" diff --git a/common/state/backend_storage.c b/common/state/backend_storage.c index fe7e89e8fb..7fc7acfdcb 100644 --- a/common/state/backend_storage.c +++ b/common/state/backend_storage.c @@ -21,7 +21,7 @@ #include <linux/mtd/mtd-abi.h> #include <sys/stat.h> #include <malloc.h> -#include <printk.h> +#include <linux/printk.h> #include "state.h" diff --git a/common/state/state_variables.c b/common/state/state_variables.c index 66c66f38bd..f112c60bf6 100644 --- a/common/state/state_variables.c +++ b/common/state/state_variables.c @@ -21,7 +21,7 @@ #include <linux/types.h> #include <malloc.h> #include <net.h> -#include <printk.h> +#include <linux/printk.h> #include <of.h> #include <stdio.h> diff --git a/drivers/aiodev/core.c b/drivers/aiodev/core.c index 7240de2c40..559695c4f6 100644 --- a/drivers/aiodev/core.c +++ b/drivers/aiodev/core.c @@ -37,7 +37,7 @@ struct aiochannel *aiochannel_by_name(const char *name) return ERR_PTR(-ENOENT); } -EXPORT_SYMBOL(aiochannel_get_by_name); +EXPORT_SYMBOL(aiochannel_by_name); struct aiochannel *aiochannel_get(struct device_d *dev, int index) { diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c index 640af533d6..5a3602649f 100644 --- a/drivers/clk/analogbits/wrpll-cln28hpc.c +++ b/drivers/clk/analogbits/wrpll-cln28hpc.c @@ -23,7 +23,7 @@ #include <linux/kernel.h> #include <stdio.h> -#include <printk.h> +#include <linux/printk.h> #include <linux/bug.h> #include <linux/err.h> #include <linux/log2.h> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 4e6ec8231e..f9b2324f6a 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -10,7 +10,7 @@ #include <io.h> #include <linux/bitops.h> -#include <printk.h> +#include <linux/printk.h> struct pmc_data { unsigned int ncore; diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index 1701a2c5a0..fa0d1dc432 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -8,7 +8,7 @@ #include <linux/list.h> #include <linux/clkdev.h> #include <linux/overflow.h> -#include <printk.h> +#include <linux/printk.h> #include <clock.h> #include <io.h> #include <of.h> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 7bc69afd78..12a81e627c 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -108,8 +108,8 @@ config RISCV_TIMER required for all RISC-V systems. config CLINT_TIMER - bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST - depends on OFDEVICE + bool "CLINT Timer for the RISC-V platform" + depends on RISCV && OFDEVICE help This option enables the CLINT timer for RISC-V systems. The CLINT driver is usually used for NoMMU RISC-V systems. diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index b12bf8f777..9e5c096301 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -1,6 +1,6 @@ config DDR_FSL - bool "Freescale DDR support" if COMPILE_TEST - depends on ARM + bool "Freescale DDR support" + depends on ARCH_LAYERSCAPE if DDR_FSL diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f79c9ea67d..347a719f5f 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -197,6 +197,13 @@ config GPIO_LIBFTDI1 bool "libftdi1 driver" depends on SANDBOX +config GPIO_ZYNQ + tristate "Xilinx Zynq GPIO support" + depends on ARCH_ZYNQ || ARCH_ZYNQMP || CROSS_COMPILE + depends on OFDEVICE + help + Say yes here to support Xilinx Zynq GPIO controller. + endmenu endif diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 023973cb63..d9f96e34c5 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -26,3 +26,4 @@ obj-$(CONFIG_GPIO_VF610) += gpio-vf610.o obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o obj-$(CONFIG_GPIO_SIFIVE) += gpio-sifive.o obj-$(CONFIG_GPIO_STARFIVE) += gpio-starfive-vic.o +obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c index 63f2c097e4..58ffd87788 100644 --- a/drivers/gpio/gpio-sifive.c +++ b/drivers/gpio/gpio-sifive.c @@ -4,7 +4,7 @@ */ #include <linux/basic_mmio_gpio.h> -#include <printk.h> +#include <linux/printk.h> #include <driver.h> #include <errno.h> diff --git a/drivers/gpio/gpio-starfive-vic.c b/drivers/gpio/gpio-starfive-vic.c index baa4f584d5..4f8c0c6cd7 100644 --- a/drivers/gpio/gpio-starfive-vic.c +++ b/drivers/gpio/gpio-starfive-vic.c @@ -6,7 +6,7 @@ #include <linux/basic_mmio_gpio.h> #include <linux/reset.h> #include <linux/clk.h> -#include <printk.h> +#include <linux/printk.h> #include <driver.h> #include <errno.h> #include <pinctrl.h> diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c new file mode 100644 index 0000000000..bb77857611 --- /dev/null +++ b/drivers/gpio/gpio-zynq.c @@ -0,0 +1,436 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Xilinx Zynq GPIO device driver + * + * Copyright (C) 2009 - 2014 Xilinx, Inc. + * + * Based on the Linux kernel driver (drivers/gpio/gpio-zynq.c). + */ + +#include <common.h> +#include <errno.h> +#include <gpio.h> +#include <init.h> +#include <io.h> +#include <of.h> + +/* Maximum banks */ +#define ZYNQ_GPIO_MAX_BANK 4 +#define ZYNQMP_GPIO_MAX_BANK 6 + +#define ZYNQ_GPIO_BANK0_NGPIO 32 +#define ZYNQ_GPIO_BANK1_NGPIO 22 +#define ZYNQ_GPIO_BANK2_NGPIO 32 +#define ZYNQ_GPIO_BANK3_NGPIO 32 + +#define ZYNQMP_GPIO_BANK0_NGPIO 26 +#define ZYNQMP_GPIO_BANK1_NGPIO 26 +#define ZYNQMP_GPIO_BANK2_NGPIO 26 +#define ZYNQMP_GPIO_BANK3_NGPIO 32 +#define ZYNQMP_GPIO_BANK4_NGPIO 32 +#define ZYNQMP_GPIO_BANK5_NGPIO 32 + +#define ZYNQ_GPIO_NR_GPIOS 118 +#define ZYNQMP_GPIO_NR_GPIOS 174 + +#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0 +#define ZYNQ_GPIO_BANK0_PIN_MAX(str) \ + (ZYNQ_GPIO_BANK0_PIN_MIN(str) + ZYNQ##str##_GPIO_BANK0_NGPIO - 1) +#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK1_PIN_MAX(str) \ + (ZYNQ_GPIO_BANK1_PIN_MIN(str) + ZYNQ##str##_GPIO_BANK1_NGPIO - 1) +#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK2_PIN_MAX(str) \ + (ZYNQ_GPIO_BANK2_PIN_MIN(str) + ZYNQ##str##_GPIO_BANK2_NGPIO - 1) +#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK3_PIN_MAX(str) \ + (ZYNQ_GPIO_BANK3_PIN_MIN(str) + ZYNQ##str##_GPIO_BANK3_NGPIO - 1) +#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK4_PIN_MAX(str) \ + (ZYNQ_GPIO_BANK4_PIN_MIN(str) + ZYNQ##str##_GPIO_BANK4_NGPIO - 1) +#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK5_PIN_MAX(str) \ + (ZYNQ_GPIO_BANK5_PIN_MIN(str) + ZYNQ##str##_GPIO_BANK5_NGPIO - 1) + +/* Register offsets for the GPIO device */ +/* LSW Mask & Data -WO */ +#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) +/* MSW Mask & Data -WO */ +#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) +/* Data Register-RW */ +#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK)) +#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) +/* Direction mode reg-RW */ +#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) +/* Output enable reg-RW */ +#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) +/* Interrupt mask reg-RO */ +#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) +/* Interrupt enable reg-WO */ +#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) +/* Interrupt disable reg-WO */ +#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) +/* Interrupt status reg-RO */ +#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) +/* Interrupt type reg-RW */ +#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) +/* Interrupt polarity reg-RW */ +#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) +/* Interrupt on any, reg-RW */ +#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) + +/* Disable all interrupts mask */ +#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF + +/* Mid pin number of a bank */ +#define ZYNQ_GPIO_MID_PIN_NUM 16 + +/* GPIO upper 16 bit mask */ +#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 + +/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */ +#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0) +#define GPIO_QUIRK_DATA_RO_BUG BIT(1) + +/** + * struct zynq_gpio - GPIO device private data structure + * @chip: instance of the gpio_chip + * @base_addr: base address of the GPIO device + * @p_data: pointer to platform data + */ +struct zynq_gpio { + struct gpio_chip chip; + void __iomem *base_addr; + const struct zynq_platform_data *p_data; +}; + +/** + * struct zynq_platform_data - Zynq GPIO platform data structure + * @quirks: Flags is used to identify the platform + * @ngpio: max number of gpio pins + * @max_bank: maximum number of gpio banks + * @bank_min: this array represents bank's min pin + * @bank_max: this array represents bank's max pin + */ +struct zynq_platform_data { + u32 quirks; + u16 ngpio; + int max_bank; + int bank_min[ZYNQMP_GPIO_MAX_BANK]; + int bank_max[ZYNQMP_GPIO_MAX_BANK]; +}; + +/** + * zynq_gpio_is_zynq - Test if HW is Zynq or ZynqMP + * @gpio: Pointer to driver data struct + * + * Return: 0 if ZynqMP, 1 if Zynq. + */ +static int zynq_gpio_is_zynq(struct zynq_gpio *gpio) +{ + return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ); +} + +/** + * gpio_data_ro_bug - Test if HW bug exists or not + * @gpio: Pointer to driver data struct + * + * Return: 0 if bug does not exist, 1 if bug exists. + */ +static int gpio_data_ro_bug(struct zynq_gpio *gpio) +{ + return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG); +} + +/** + * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank + * for a given pin in the GPIO device + * @pin_num: gpio pin number within the device + * @bank_num: an output parameter used to return the bank number of the gpio + * pin + * @bank_pin_num: an output parameter used to return pin number within a bank + * for the given gpio pin + * @gpio: gpio device data structure + * + * Returns the bank number and pin offset within the bank. + */ +static int zynq_gpio_get_bank_pin(unsigned int pin_num, unsigned int *bank_num, + unsigned int *bank_pin_num, + struct zynq_gpio *gpio) +{ + int bank; + + for (bank = 0; bank < gpio->p_data->max_bank; bank++) { + if ((pin_num >= gpio->p_data->bank_min[bank]) && + (pin_num <= gpio->p_data->bank_max[bank])) { + *bank_num = bank; + *bank_pin_num = pin_num - gpio->p_data->bank_min[bank]; + return 0; + } + } + + *bank_num = 0; + *bank_pin_num = 0; + return -ENODEV; +} + +/** + * zynq_gpio_get_value - Get the state of the specified pin of GPIO device + * @chip: gpio_chip instance to be worked on + * @pin: gpio pin number within the device + * + * This function reads the state of the specified pin of the GPIO device. + * + * Return: 0 if the pin is low, 1 if pin is high. + */ +static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin) +{ + u32 data; + unsigned int bank_num, bank_pin_num; + struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); + + if (zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio) < 0) + return -EINVAL; + + if (gpio_data_ro_bug(gpio)) { + if (zynq_gpio_is_zynq(gpio)) { + if (bank_num <= 1) { + data = readl_relaxed( + gpio->base_addr + + ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); + } else { + data = readl_relaxed( + gpio->base_addr + + ZYNQ_GPIO_DATA_OFFSET(bank_num)); + } + } else { + if (bank_num <= 2) { + data = readl_relaxed( + gpio->base_addr + + ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); + } else { + data = readl_relaxed( + gpio->base_addr + + ZYNQ_GPIO_DATA_OFFSET(bank_num)); + } + } + } else { + data = readl_relaxed(gpio->base_addr + + ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); + } + return (data >> bank_pin_num) & 1; +} + +/** + * zynq_gpio_set_value - Modify the state of the pin with specified value + * @chip: gpio_chip instance to be worked on + * @pin: gpio pin number within the device + * @state: value used to modify the state of the specified pin + * + * This function calculates the register offset (i.e to lower 16 bits or + * upper 16 bits) based on the given pin number and sets the state of a + * gpio pin to the specified value. The state is either 0 or non-zero. + */ +static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin, + int state) +{ + unsigned int reg_offset, bank_num, bank_pin_num; + struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); + + if (zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio) < 0) + return; + + if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { + bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; + reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); + } else { + reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); + } + + /* + * get the 32 bit value to be written to the mask/data register where + * the upper 16 bits is the mask and lower 16 bits is the data + */ + state = !!state; + state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & + ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK); + + writel_relaxed(state, gpio->base_addr + reg_offset); +} + +/** + * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input + * @chip: gpio_chip instance to be worked on + * @pin: gpio pin number within the device + * + * This function uses the read-modify-write sequence to set the direction of + * the gpio pin as input. + * + * Return: 0 always + */ +static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) +{ + u32 reg; + unsigned int bank_num, bank_pin_num; + struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); + + if (zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio) < 0) + return -EINVAL; + /* + * On zynq bank 0 pins 7 and 8 are special and cannot be used + * as inputs. + */ + if (zynq_gpio_is_zynq(gpio) && bank_num == 0 && + (bank_pin_num == 7 || bank_pin_num == 8)) + return -EINVAL; + + /* clear the bit in direction mode reg to set the pin as input */ + reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + reg &= ~BIT(bank_pin_num); + writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + + return 0; +} + +/** + * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output + * @chip: gpio_chip instance to be worked on + * @pin: gpio pin number within the device + * @state: value to be written to specified pin + * + * This function sets the direction of specified GPIO pin as output, configures + * the Output Enable register for the pin and uses zynq_gpio_set to set + * the state of the pin to the value specified. + * + * Return: 0 always + */ +static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, + int state) +{ + u32 reg; + unsigned int bank_num, bank_pin_num; + struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); + + if (zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio) < 0) + return -EINVAL; + + /* set the GPIO pin as output */ + reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + reg |= BIT(bank_pin_num); + writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + + /* configure the output enable reg for the pin */ + reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); + reg |= BIT(bank_pin_num); + writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); + + /* set the state of the pin */ + zynq_gpio_set_value(chip, pin, state); + return 0; +} + +/** + * zynq_gpio_get_direction - Read the direction of the specified GPIO pin + * @chip: gpio_chip instance to be worked on + * @pin: gpio pin number within the device + * + * This function returns the direction of the specified GPIO. + * + * Return: 0 for output, 1 for input + */ +static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) +{ + u32 reg; + unsigned int bank_num, bank_pin_num; + struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); + + if (zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio) < 0) + return -EINVAL; + + reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + + return !(reg & BIT(bank_pin_num)); +} + +static struct gpio_ops zynq_gpio_ops = { + .direction_input = zynq_gpio_dir_in, + .direction_output = zynq_gpio_dir_out, + .get = zynq_gpio_get_value, + .set = zynq_gpio_set_value, + .get_direction = zynq_gpio_get_direction, +}; + +static int zynqmp_gpio_probe(struct device_d *dev) +{ + struct resource *iores; + struct zynq_gpio *gpio; + const struct zynq_platform_data *p_data; + int ret; + + gpio = xzalloc(sizeof(*gpio)); + p_data = device_get_match_data(dev); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); + goto free_gpio; + } + + gpio->base_addr = IOMEM(iores->start); + gpio->chip.base = of_alias_get_id(dev->device_node, "gpio"); + gpio->chip.ops = &zynq_gpio_ops; + gpio->chip.ngpio = p_data->ngpio; + gpio->chip.dev = dev; + gpio->p_data = p_data; + + return gpiochip_add(&gpio->chip); + +free_gpio: + kfree(gpio); + return ret; +} + +static const struct zynq_platform_data zynqmp_gpio_def = { + .quirks = GPIO_QUIRK_DATA_RO_BUG, + .ngpio = ZYNQMP_GPIO_NR_GPIOS, + .max_bank = ZYNQMP_GPIO_MAX_BANK, + .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), + .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP), + .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP), + .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP), + .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP), + .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP), + .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP), + .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP), + .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP), + .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP), + .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP), + .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP), +}; + +static const struct zynq_platform_data zynq_gpio_def = { + .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG, + .ngpio = ZYNQ_GPIO_NR_GPIOS, + .max_bank = ZYNQ_GPIO_MAX_BANK, + .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), + .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(), + .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(), + .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(), + .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(), + .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(), + .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(), + .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(), +}; + +static const struct of_device_id zynq_gpio_of_match[] = { + { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def }, + { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def }, + { /* end of table */ } +}; + +static struct driver_d zynqmp_gpio_driver = { + .name = "zynqmp-gpio", + .of_compatible = zynq_gpio_of_match, + .probe = zynqmp_gpio_probe, +}; + +postcore_platform_driver(zynqmp_gpio_driver); diff --git a/drivers/i2c/i2c.c b/drivers/i2c/i2c.c index 12aac42794..125322406a 100644 --- a/drivers/i2c/i2c.c +++ b/drivers/i2c/i2c.c @@ -215,7 +215,8 @@ int i2c_write_reg(struct i2c_client *client, u32 addr, const u8 *buf, u16 count) msgbuf[i++] = addr; msg->len += i; - memcpy(msg->buf + i, buf, count); + if (count) + memcpy(msg->buf + i, buf, count); status = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); dev_dbg(&client->adapter->dev, "%s: %u@%u --> %d\n", __func__, diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c index aa7dcb8c31..0b397185c9 100644 --- a/drivers/i2c/muxes/i2c-mux-pca954x.c +++ b/drivers/i2c/muxes/i2c-mux-pca954x.c @@ -210,10 +210,8 @@ static int pca954x_probe(struct device_d *dev) * that the mux is in fact present. This also * initializes the mux to disconnected state. */ - if (i2c_smbus_write_byte(client, 0) < 0) { - dev_warn(&client->dev, "probe failed\n"); + if (i2c_smbus_write_byte(client, 0) < 0) goto exit_free; - } ret = dev_get_drvdata(dev, (const void **)&tmp); data->type = tmp; diff --git a/drivers/misc/acpi-test.c b/drivers/misc/acpi-test.c index 1d6814ebcf..784c80cc5b 100644 --- a/drivers/misc/acpi-test.c +++ b/drivers/misc/acpi-test.c @@ -47,7 +47,7 @@ static int acpi_test_probe(struct device_d *dev) static void acpi_test_remove(struct device_d *dev) { - dev_info(dev, "FADT driver removed\n"); + dev_dbg(dev, "FADT driver removed\n"); } static struct acpi_driver acpi_test_driver = { diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 58d53b7a78..130e0d401c 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -858,10 +858,6 @@ static int __init atmel_pmecc_nand_init_params(struct device_d *dev, if (IS_ERR(iores)) return PTR_ERR(iores); host->ecc = IOMEM(iores->start); - if (IS_ERR(host->ecc)) { - dev_err(host->dev, "ioremap failed\n"); - return -EIO; - } iores = dev_request_mem_resource(dev, 2); if (IS_ERR(iores)) { @@ -1215,10 +1211,6 @@ static int atmel_hw_nand_init_params(struct device_d *dev, if (IS_ERR(iores)) return PTR_ERR(iores); host->ecc = IOMEM(iores->start); - if (IS_ERR(host->ecc)) { - dev_err(host->dev, "ioremap failed\n"); - return -EIO; - } /* ECC is calculated for the whole page (1 step) */ nand_chip->ecc.size = mtd->writesize; diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index ea53d2cd84..2cd2bc06eb 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -1203,21 +1203,11 @@ static int cqspi_probe(struct device_d *dev) if (IS_ERR(iores)) return PTR_ERR(iores); cqspi->iobase = IOMEM(iores->start); - if (IS_ERR(cqspi->iobase)) { - dev_err(dev, "dev_request_mem_region 0 failed\n"); - ret = PTR_ERR(cqspi->iobase); - goto probe_failed; - } iores = dev_request_mem_resource(dev, 1); if (IS_ERR(iores)) return PTR_ERR(iores); cqspi->ahb_base = IOMEM(iores->start); - if (IS_ERR(cqspi->ahb_base)) { - dev_err(dev, "dev_request_mem_region 0 failed\n"); - ret = PTR_ERR(cqspi->ahb_base); - goto probe_failed; - } cqspi_wait_idle(cqspi); cqspi_controller_init(cqspi); diff --git a/drivers/net/ksz8864rmn.c b/drivers/net/ksz8864rmn.c index 85063ff0d8..72ab86579b 100644 --- a/drivers/net/ksz8864rmn.c +++ b/drivers/net/ksz8864rmn.c @@ -31,48 +31,55 @@ #define CMD_WRITE 0x02 #define CMD_READ 0x03 +enum ksz_type { + unknown, + ksz87, + ksz88 +}; + struct micrel_switch_priv { struct cdev cdev; struct spi_device *spi; unsigned int p_enable; + unsigned int addr_width; + unsigned int pad; }; -static int micrel_switch_read_reg(struct spi_device *spi, uint8_t reg) +static int micrel_switch_read_reg(const struct micrel_switch_priv *priv, uint8_t reg) { uint8_t tx[2]; uint8_t rx[1]; int ret; - tx[0] = CMD_READ; - tx[1] = reg; + tx[0] = CMD_READ << (priv->addr_width + priv->pad - 8) | reg >> (8 - priv->pad); + tx[1] = reg << priv->pad; - ret = spi_write_then_read(spi, tx, 2, rx, 1); + ret = spi_write_then_read(priv->spi, tx, 2, rx, 1); if (ret < 0) return ret; return rx[0]; } -static void micrel_switch_write_reg(struct spi_device *spi, uint8_t reg, uint8_t val) +static void micrel_switch_write_reg(const struct micrel_switch_priv *priv, uint8_t reg, uint8_t val) { uint8_t tx[3]; - tx[0] = CMD_WRITE; - tx[1] = reg; + tx[0] = CMD_WRITE << (priv->addr_width + priv->pad - 8) | reg >> (8 - priv->pad); + tx[1] = reg << priv->pad; tx[2] = val; - spi_write_then_read(spi, tx, 3, NULL, 0); + spi_write_then_read(priv->spi, tx, 3, NULL, 0); } static int micrel_switch_enable_set(struct param_d *param, void *_priv) { struct micrel_switch_priv *priv = _priv; - struct spi_device *spi = priv->spi; if (priv->p_enable) - micrel_switch_write_reg(spi, REG_ID1, 1); + micrel_switch_write_reg(priv, REG_ID1, 1); else - micrel_switch_write_reg(spi, REG_ID1, 0); + micrel_switch_write_reg(priv, REG_ID1, 0); return 0; } @@ -84,7 +91,7 @@ static ssize_t micel_switch_read(struct cdev *cdev, void *_buf, size_t count, lo struct micrel_switch_priv *priv = cdev->priv; for (i = 0; i < count; i++) { - ret = micrel_switch_read_reg(priv->spi, offset); + ret = micrel_switch_read_reg(priv, offset); if (ret < 0) return ret; *buf = ret; @@ -102,7 +109,7 @@ static ssize_t micel_switch_write(struct cdev *cdev, const void *_buf, size_t co struct micrel_switch_priv *priv = cdev->priv; for (i = 0; i < count; i++) { - micrel_switch_write_reg(priv->spi, offset, *buf); + micrel_switch_write_reg(priv, offset, *buf); buf++; offset++; } @@ -119,6 +126,11 @@ static int micrel_switch_probe(struct device_d *dev) { struct micrel_switch_priv *priv; int ret = 0; + enum ksz_type kind = (enum ksz_type)device_get_match_data(dev); + uint8_t id; + + if (kind == unknown) + return -ENODEV; priv = xzalloc(sizeof(*priv)); @@ -128,12 +140,27 @@ static int micrel_switch_probe(struct device_d *dev) priv->spi->mode = SPI_MODE_0; priv->spi->bits_per_word = 8; - ret = micrel_switch_read_reg(priv->spi, REG_ID0); + switch (kind) { + case ksz87: + priv->addr_width = 12; + priv->pad = 1; + id = 0x87; + break; + case ksz88: + priv->addr_width = 8; + priv->pad = 0; + id = 0x95; + break; + default: + return -ENODEV; + }; + + ret = micrel_switch_read_reg(priv, REG_ID0); if (ret < 0) { dev_err(&priv->spi->dev, "failed to read device id\n"); return ret; } - if (ret != 0x95) { + if (ret != id) { dev_err(&priv->spi->dev, "unknown device id: %02x\n", ret); return -ENODEV; } @@ -149,13 +176,20 @@ static int micrel_switch_probe(struct device_d *dev) NULL, &priv->p_enable, priv); priv->p_enable = 1; - micrel_switch_write_reg(priv->spi, REG_ID1, 1); + micrel_switch_write_reg(priv, REG_ID1, 1); return 0; } +static const struct platform_device_id ksz_ids[] = { + { .name = "ksz8864rmn", .driver_data = ksz88 }, + { .name = "ksz8795", .driver_data = ksz87 }, + { } +}; + static struct driver_d micrel_switch_driver = { .name = "ksz8864rmn", .probe = micrel_switch_probe, + .id_table = ksz_ids, }; device_spi_driver(micrel_switch_driver); diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index ea193c84a7..cf593ee6a6 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -14,6 +14,7 @@ #include <common.h> #include <init.h> +#include <linux/clk.h> #include <linux/mii.h> #include <linux/ethtool.h> #include <linux/phy.h> @@ -24,16 +25,17 @@ /* Operation Mode Strap Override */ #define MII_KSZPHY_OMSO 0x16 #define KSZPHY_OMSO_B_CAST_OFF BIT(9) +#define KSZPHY_OMSO_NAND_TREE_ON BIT(5) #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) /* general PHY control reg in vendor specific block. */ -#define MII_KSZPHY_CTRL 0x1F +#define MII_KSZPHY_CTRL 0x1f /* bitmap of PHY register to set interrupt mode */ #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) #define KSZ9021_CTRL_INT_ACTIVE_HIGH BIT(14) #define KS8737_CTRL_INT_ACTIVE_HIGH BIT(14) -#define KSZ8051_RMII_50MHZ_CLK BIT(7) +#define KSZPHY_RMII_REF_CLK_SEL BIT(7) /* PHY Control 1 */ #define MII_KSZPHY_CTRL_1 0x1e @@ -52,6 +54,47 @@ #define PS_TO_REG 200 +struct kszphy_type { + u32 led_mode_reg; + bool has_broadcast_disable; + bool has_nand_tree_disable; + bool has_rmii_ref_clk_sel; +}; + +struct kszphy_priv { + const struct kszphy_type *type; + int led_mode; + bool rmii_ref_clk_sel; + bool rmii_ref_clk_sel_val; +}; + +static const struct kszphy_type ksz8001_type = { + .led_mode_reg = MII_KSZPHY_CTRL_1, +}; + +static const struct kszphy_type ksz8021_type = { + .led_mode_reg = MII_KSZPHY_CTRL, + .has_broadcast_disable = true, + .has_nand_tree_disable = true, + .has_rmii_ref_clk_sel = true, +}; + +static const struct kszphy_type ksz8041_type = { + .led_mode_reg = MII_KSZPHY_CTRL_1, +}; + +static const struct kszphy_type ksz8051_type = { + .led_mode_reg = MII_KSZPHY_CTRL, + .has_nand_tree_disable = true, +}; + +static const struct kszphy_type ksz8081_type = { + .led_mode_reg = MII_KSZPHY_CTRL, + .has_broadcast_disable = true, + .has_nand_tree_disable = true, + .has_rmii_ref_clk_sel = true, +}; + static int kszphy_extended_write(struct phy_device *phydev, u32 regnum, u16 val) { @@ -66,6 +109,22 @@ static int kszphy_extended_read(struct phy_device *phydev, return phy_read(phydev, MII_KSZPHY_EXTREG_READ); } +static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) +{ + int ctrl; + + ctrl = phy_read(phydev, MII_KSZPHY_CTRL); + if (ctrl < 0) + return ctrl; + + if (val) + ctrl |= KSZPHY_RMII_REF_CLK_SEL; + else + ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; + + return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); +} + /* Handle LED mode, shift = position of first led mode bit, usually 4 or 14 */ static int kszphy_led_mode(struct phy_device *phydev, int reg, int shift) { @@ -83,37 +142,119 @@ static int kszphy_led_mode(struct phy_device *phydev, int reg, int shift) return 0; } -static int kszphy_config_init(struct phy_device *phydev) +static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) { - kszphy_led_mode(phydev, MII_KSZPHY_CTRL_1, 14); + const struct device_d *dev = &phydev->dev; + int rc, temp, shift; - return 0; + switch (reg) { + case MII_KSZPHY_CTRL_1: + shift = 14; + break; + case MII_KSZPHY_CTRL: + shift = 4; + break; + default: + return -EINVAL; + } + + temp = phy_read(phydev, reg); + if (temp < 0) { + rc = temp; + goto out; + } + + temp &= ~(3 << shift); + temp |= val << shift; + rc = phy_write(phydev, reg, temp); +out: + if (rc < 0) + dev_err(dev, "failed to set led mode\n"); + + return rc; } -static int ksz8021_config_init(struct phy_device *phydev) +/* Disable PHY address 0 as the broadcast address, so that it can be used as a + * unique (non-broadcast) address on a shared bus. + */ +static int kszphy_broadcast_disable(struct phy_device *phydev) { - phy_set_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_B_CAST_OFF); + const struct device_d *dev = &phydev->dev; + int ret; - kszphy_led_mode(phydev, MII_KSZPHY_CTRL, 4); + ret = phy_read(phydev, MII_KSZPHY_OMSO); + if (ret < 0) + goto out; - return 0; + ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); +out: + if (ret) + dev_err(dev, "failed to disable broadcast address\n"); + + return ret; } -static int ks8051_config_init(struct phy_device *phydev) +static int kszphy_nand_tree_disable(struct phy_device *phydev) { - int regval; + const struct device_d *dev = &phydev->dev; + int ret; + + ret = phy_read(phydev, MII_KSZPHY_OMSO); + if (ret < 0) + goto out; + + if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) + return 0; + + ret = phy_write(phydev, MII_KSZPHY_OMSO, + ret & ~KSZPHY_OMSO_NAND_TREE_ON); +out: + if (ret) + dev_err(dev, "failed to disable NAND tree mode\n"); + + return ret; +} + +/* Some config bits need to be set again on resume, handle them here. */ +static int kszphy_config_reset(struct phy_device *phydev) +{ + struct kszphy_priv *priv = phydev->priv; + int ret; - if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { - regval = phy_read(phydev, MII_KSZPHY_CTRL); - regval |= KSZ8051_RMII_50MHZ_CLK; - phy_write(phydev, MII_KSZPHY_CTRL, regval); + if (priv->rmii_ref_clk_sel) { + ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); + if (ret) { + dev_err(&phydev->dev, + "failed to set rmii reference clock\n"); + return ret; + } } - kszphy_led_mode(phydev, MII_KSZPHY_CTRL, 4); + if (priv->led_mode >= 0) + kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); return 0; } +static int kszphy_config_init(struct phy_device *phydev) +{ + struct kszphy_priv *priv = phydev->priv; + const struct kszphy_type *type; + + if (!priv) + return 0; + + type = priv->type; + + if (type->has_broadcast_disable) + kszphy_broadcast_disable(phydev); + + if (type->has_nand_tree_disable) + kszphy_nand_tree_disable(phydev); + + return kszphy_config_reset(phydev); +} + static int ksz9021_load_values_from_of(struct phy_device *phydev, const struct device_node *of_node, u16 reg, const char *field[]) @@ -468,13 +609,66 @@ static int ksz8873mll_config_init(struct phy_device *phydev) return 0; } +static int kszphy_probe(struct phy_device *phydev) +{ + struct device_d *dev = &phydev->dev; + struct device_node *np = dev->device_node; + struct phy_driver *drv = to_phy_driver(dev->driver); + const struct kszphy_type *type = drv->driver_data; + struct kszphy_priv *priv; + struct clk *clk; + int ret; + + priv = xzalloc(sizeof(*priv)); + + phydev->priv = priv; + + priv->type = type; + + if (type->led_mode_reg) { + ret = of_property_read_u32(np, "micrel,led-mode", + &priv->led_mode); + if (ret) + priv->led_mode = -1; + + if (priv->led_mode > 3) { + dev_err(dev, "invalid led mode: 0x%02x\n", + priv->led_mode); + priv->led_mode = -1; + } + } else { + priv->led_mode = -1; + } + + clk = clk_get(dev, "rmii-ref"); + /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ + if (!IS_ERR_OR_NULL(clk)) { + unsigned long rate = clk_get_rate(clk); + bool rmii_ref_clk_sel_25_mhz; + + priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; + rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, + "micrel,rmii-reference-clock-select-25-mhz"); + + if (rate > 24500000 && rate < 25500000) { + priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; + } else if (rate > 49500000 && rate < 50500000) { + priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; + } else { + dev_err(dev, "Clock rate out of range: %ld\n", rate); + return -EINVAL; + } + } + + return 0; +} + static struct phy_driver ksphy_driver[] = { { .phy_id = PHY_ID_KS8737, .phy_id_mask = 0x00fffff0, .drv.name = "Micrel KS8737", .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), - .config_init = kszphy_config_init, .config_aneg = genphy_config_aneg, .read_status = genphy_read_status, }, { @@ -483,7 +677,9 @@ static struct phy_driver ksphy_driver[] = { .drv.name = "Micrel KSZ8021", .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | SUPPORTED_Asym_Pause), - .config_init = ksz8021_config_init, + .driver_data = &ksz8021_type, + .probe = kszphy_probe, + .config_init = kszphy_config_init, .config_aneg = genphy_config_aneg, .read_status = genphy_read_status, }, { @@ -492,7 +688,9 @@ static struct phy_driver ksphy_driver[] = { .drv.name = "Micrel KSZ8031", .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | SUPPORTED_Asym_Pause), - .config_init = ksz8021_config_init, + .driver_data = &ksz8021_type, + .probe = kszphy_probe, + .config_init = kszphy_config_init, .config_aneg = genphy_config_aneg, .read_status = genphy_read_status, }, { @@ -501,6 +699,8 @@ static struct phy_driver ksphy_driver[] = { .drv.name = "Micrel KSZ8041", .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | SUPPORTED_Asym_Pause), + .driver_data = &ksz8041_type, + .probe = kszphy_probe, .config_init = kszphy_config_init, .config_aneg = genphy_config_aneg, .read_status = genphy_read_status, @@ -510,22 +710,28 @@ static struct phy_driver ksphy_driver[] = { .drv.name = "Micrel KSZ8051", .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | SUPPORTED_Asym_Pause), - .config_init = ks8051_config_init, + .driver_data = &ksz8051_type, + .probe = kszphy_probe, + .config_init = kszphy_config_init, .config_aneg = genphy_config_aneg, .read_status = genphy_read_status, }, { .phy_id = PHY_ID_KSZ8081, .phy_id_mask = MICREL_PHY_ID_MASK, .drv.name = "Micrel KSZ8081/91", + .driver_data = &ksz8081_type, .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), - .config_init = ksz8021_config_init, + .probe = kszphy_probe, + .config_init = kszphy_config_init, .config_aneg = genphy_config_aneg, .read_status = genphy_read_status, }, { .phy_id = PHY_ID_KSZ8001, - .drv.name = "Micrel KSZ8001 or KS8721", .phy_id_mask = 0x00ffffff, + .drv.name = "Micrel KSZ8001 or KS8721", + .driver_data = &ksz8001_type, .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), + .probe = kszphy_probe, .config_init = kszphy_config_init, .config_aneg = genphy_config_aneg, .read_status = genphy_read_status, diff --git a/drivers/net/usb/Kconfig b/drivers/net/usb/Kconfig index 614b1f0c9a..380d1ed02a 100644 --- a/drivers/net/usb/Kconfig +++ b/drivers/net/usb/Kconfig @@ -23,4 +23,11 @@ config NET_USB_SMSC95XX select PHYLIB bool "SMSC95xx" +config NET_USB_RTL8152 + bool "Realtek RTL8152B/RTL8153 support" + help + Say Y here if you would like to support Realtek RTL8152B/RTL8153 base + USB Ethernet Devices. This driver also supports compatible devices + from Samsung, Lenovo, TP-LINK and Nvidia. + endif diff --git a/drivers/net/usb/Makefile b/drivers/net/usb/Makefile index cbb69080da..69dcfe1e46 100644 --- a/drivers/net/usb/Makefile +++ b/drivers/net/usb/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_NET_USB) += usbnet.o obj-$(CONFIG_NET_USB_ASIX) += asix.o obj-$(CONFIG_USB_NET_AX88179_178A) += ax88179_178a.o obj-$(CONFIG_NET_USB_SMSC95XX) += smsc95xx.o +obj-$(CONFIG_NET_USB_RTL8152) += r8152.o r8152_fw.o diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c new file mode 100644 index 0000000000..3647be02c3 --- /dev/null +++ b/drivers/net/usb/r8152.c @@ -0,0 +1,1593 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved. */ + +#include <common.h> +#include <dma.h> +#include <errno.h> +#include <init.h> +#include <linux/ethtool.h> +#include <linux/mii.h> +#include <linux/phy.h> +#include <usb/usb.h> +#include <usb/usbnet.h> +#include "r8152.h" + +#define R8152_TX_BURST_SIZE 512 +#define R8152_RX_BURST_SIZE 64 + +struct r8152_version { + unsigned short tcr; + unsigned short version; + bool gmii; +}; + +static const struct r8152_version r8152_versions[] = { + { 0x4c00, RTL_VER_01, 0 }, + { 0x4c10, RTL_VER_02, 0 }, + { 0x5c00, RTL_VER_03, 1 }, + { 0x5c10, RTL_VER_04, 1 }, + { 0x5c20, RTL_VER_05, 1 }, + { 0x5c30, RTL_VER_06, 1 }, + { 0x4800, RTL_VER_07, 0 }, + { 0x6000, RTL_VER_08, 1 }, + { 0x6010, RTL_VER_09, 1 }, +}; + +static inline struct r8152 *r8152_get_priv(struct usbnet *dev) +{ + return (struct r8152 *)dev->driver_priv; +} + +static int r8152_get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, + void *data) +{ + int ret; + + if (WARN_ON(size > R8152_RX_BURST_SIZE)) + return -EINVAL; + + ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), + RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, + value, index, tp->rxbuf, size, 500); + memcpy(data, tp->rxbuf, size); + + return ret; +} + +static int r8152_set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, + const void *data) +{ + int ret; + + if (WARN_ON(size > R8152_TX_BURST_SIZE)) + return -EINVAL; + + memcpy(tp->txbuf, data, size); + ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), + RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, + value, index, tp->txbuf, size, 500); + + return ret; +} + +static int r8152_generic_ocp_read(struct r8152 *tp, u16 index, u16 size, + void *data, u16 type) +{ + u16 burst_size = R8152_RX_BURST_SIZE; + int txsize; + int ret; + + /* both size and index must be 4 bytes align */ + if ((size & 3) || !size || (index & 3) || !data) + return -EINVAL; + + if (index + size > 0xffff) + return -EINVAL; + + while (size) { + txsize = min(size, burst_size); + ret = r8152_get_registers(tp, index, type, txsize, data); + if (ret < 0) + break; + + index += txsize; + data += txsize; + size -= txsize; + } + + return ret; +} + +int r8152_generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, + u16 size, const void *data, u16 type) +{ + u16 byteen_start, byteen_end, byte_en_to_hw; + u16 burst_size = R8152_TX_BURST_SIZE; + int txsize; + int ret; + + /* both size and index must be 4 bytes align */ + if ((size & 3) || !size || (index & 3) || !data) + return -EINVAL; + + if (index + size > 0xffff) + return -EINVAL; + + byteen_start = byteen & BYTE_EN_START_MASK; + byteen_end = byteen & BYTE_EN_END_MASK; + + byte_en_to_hw = byteen_start | (byteen_start << 4); + ret = r8152_set_registers(tp, index, type | byte_en_to_hw, 4, data); + if (ret < 0) + return ret; + + index += 4; + data += 4; + size -= 4; + + if (size) { + size -= 4; + + while (size) { + txsize = min(size, burst_size); + + ret = r8152_set_registers(tp, index, + type | BYTE_EN_DWORD, + txsize, data); + if (ret < 0) + return ret; + + index += txsize; + data += txsize; + size -= txsize; + } + + byte_en_to_hw = byteen_end | (byteen_end >> 4); + ret = r8152_set_registers(tp, index, type | byte_en_to_hw, 4, + data); + if (ret < 0) + return ret; + } + + return ret; +} + +static int r8152_pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) +{ + return r8152_generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); +} + +static int r8152_pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, + u16 size, const void *data) +{ + return r8152_generic_ocp_write(tp, index, byteen, size, data, + MCU_TYPE_PLA); +} + +static int r8152_usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, + u16 size, const void *data) +{ + return r8152_generic_ocp_write(tp, index, byteen, size, data, + MCU_TYPE_USB); +} + +static u32 r8152_ocp_read_dword(struct r8152 *tp, u16 type, u16 index) +{ + __le32 data; + + r8152_generic_ocp_read(tp, index, sizeof(data), &data, type); + + return __le32_to_cpu(data); +} + +static void r8152_ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) +{ + __le32 tmp = __cpu_to_le32(data); + + r8152_generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, + type); +} + +u16 r8152_ocp_read_word(struct r8152 *tp, u16 type, u16 index) +{ + u32 data; + __le32 tmp; + u8 shift = index & 2; + + index &= ~3; + + r8152_generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); + + data = __le32_to_cpu(tmp); + data >>= (shift * 8); + data &= 0xffff; + + return data; +} + +void r8152_ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) +{ + u32 mask = 0xffff; + __le32 tmp; + u16 byen = BYTE_EN_WORD; + u8 shift = index & 2; + + data &= mask; + + if (index & 2) { + byen <<= shift; + mask <<= (shift * 8); + data <<= (shift * 8); + index &= ~3; + } + + tmp = __cpu_to_le32(data); + + r8152_generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); +} + +u8 r8152_ocp_read_byte(struct r8152 *tp, u16 type, u16 index) +{ + u32 data; + __le32 tmp; + u8 shift = index & 3; + + index &= ~3; + + r8152_generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); + + data = __le32_to_cpu(tmp); + data >>= (shift * 8); + data &= 0xff; + + return data; +} + +void r8152_ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) +{ + u32 mask = 0xff; + __le32 tmp; + u16 byen = BYTE_EN_BYTE; + u8 shift = index & 3; + + data &= mask; + + if (index & 3) { + byen <<= shift; + mask <<= (shift * 8); + data <<= (shift * 8); + index &= ~3; + } + + tmp = __cpu_to_le32(data); + + r8152_generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); +} + +u16 r8152_ocp_reg_read(struct r8152 *tp, u16 addr) +{ + u16 ocp_base, ocp_index; + + ocp_base = addr & 0xf000; + if (ocp_base != tp->ocp_base) { + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, + ocp_base); + tp->ocp_base = ocp_base; + } + + ocp_index = (addr & 0x0fff) | 0xb000; + return r8152_ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); +} + +void r8152_ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) +{ + u16 ocp_base, ocp_index; + + ocp_base = addr & 0xf000; + if (ocp_base != tp->ocp_base) { + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, + ocp_base); + tp->ocp_base = ocp_base; + } + + ocp_index = (addr & 0x0fff) | 0xb000; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); +} + +static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) +{ + r8152_ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); +} + +static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) +{ + return r8152_ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); +} + +void r8152_sram_write(struct r8152 *tp, u16 addr, u16 data) +{ + r8152_ocp_reg_write(tp, OCP_SRAM_ADDR, addr); + r8152_ocp_reg_write(tp, OCP_SRAM_DATA, data); +} + +static u16 r8152_sram_read(struct r8152 *tp, u16 addr) +{ + r8152_ocp_reg_write(tp, OCP_SRAM_ADDR, addr); + return r8152_ocp_reg_read(tp, OCP_SRAM_DATA); +} + +static int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, + u16 index, const u32 mask, bool set, + unsigned int timeout) +{ + u32 val; + u64 start; + + start = get_time_ns(); + do { + if (ocp_reg) + val = r8152_ocp_reg_read(tp, index); + else + val = r8152_ocp_read_dword(tp, type, index); + + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + mdelay(2); + } while (!is_timeout(start, timeout * MSECOND)); + + dev_dbg(&tp->dev->edev.dev, "%s: Timeout (index=%04x mask=%08x timeout=%d)\n", + __func__, index, mask, timeout); + + return -ETIMEDOUT; +} + +static void r8152b_reset_packet_filter(struct r8152 *tp) +{ + u32 ocp_data; + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); + ocp_data &= ~FMC_FCR_MCU_EN; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); + ocp_data |= FMC_FCR_MCU_EN; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); +} + +static void r8152_wait_fifo_empty(struct r8152 *tp) +{ + int ret; + + ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR, + PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT); + if (ret) + dev_dbg(&tp->dev->edev.dev, "Timeout waiting for FIFO empty\n"); + + ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0, + TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT); + if (ret) + dev_dbg(&tp->dev->edev.dev, "Timeout waiting for TX empty\n"); +} + +static void r8152_nic_reset(struct r8152 *tp) +{ + int ret; + u32 ocp_data; + + ocp_data = r8152_ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL); + ocp_data |= BIST_CTRL_SW_RESET; + r8152_ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data); + + ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL, + BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT); + if (ret) + dev_dbg(&tp->dev->edev.dev, "Timeout waiting for NIC reset\n"); +} + +static u8 r8152_get_speed(struct r8152 *tp) +{ + return r8152_ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); +} + +static void r8152_set_eee_plus(struct r8152 *tp) +{ + u32 ocp_data; + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); + ocp_data &= ~EEEP_CR_EEEP_TX; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); +} + +static void rxdy_gated_en(struct r8152 *tp, bool enable) +{ + u32 ocp_data; + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); + if (enable) + ocp_data |= RXDY_GATED_EN; + else + ocp_data &= ~RXDY_GATED_EN; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); +} + +static void rtl8152_set_rx_mode(struct r8152 *tp) +{ + u32 ocp_data; + __le32 tmp[2]; + + tmp[0] = 0xffffffff; + tmp[1] = 0xffffffff; + + r8152_pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); + + ocp_data = r8152_ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); + ocp_data |= RCR_APM | RCR_AM | RCR_AB; + r8152_ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); +} + +static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) +{ + r8152_ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, + OWN_UPDATE | OWN_CLEAR); +} + +static int rtl_enable(struct r8152 *tp) +{ + u32 ocp_data; + + r8152b_reset_packet_filter(tp); + + ocp_data = r8152_ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); + ocp_data |= PLA_CR_RE | PLA_CR_TE; + r8152_ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); + + switch (tp->version) { + case RTL_VER_08: + case RTL_VER_09: + r8153b_rx_agg_chg_indicate(tp); + break; + default: + break; + } + + rxdy_gated_en(tp, false); + + rtl8152_set_rx_mode(tp); + + return 0; +} + +static int rtl8152_enable(struct r8152 *tp) +{ + r8152_set_eee_plus(tp); + + return rtl_enable(tp); +} + +static void r8153_set_rx_early_timeout(struct r8152 *tp) +{ + u32 ocp_data = tp->coalesce / 8; + + switch (tp->version) { + case RTL_VER_03: + case RTL_VER_04: + case RTL_VER_05: + case RTL_VER_06: + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, + ocp_data); + break; + + case RTL_VER_08: + case RTL_VER_09: + /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout + * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 1264ns. + */ + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, + RX_AUXILIARY_TIMER / 8); + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, + ocp_data); + break; + + default: + dev_dbg(&tp->dev->edev.dev, "** %s Invalid Device\n", __func__); + break; + } +} + +static void r8153_set_rx_early_size(struct r8152 *tp) +{ + u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS - + sizeof(struct rx_desc)); + + switch (tp->version) { + case RTL_VER_03: + case RTL_VER_04: + case RTL_VER_05: + case RTL_VER_06: + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, + ocp_data / 4); + break; + + case RTL_VER_08: + case RTL_VER_09: + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, + ocp_data / 8); + break; + + default: + dev_dbg(&tp->dev->edev.dev, "** %s Invalid Device\n", __func__); + break; + } +} + +static int rtl8153_enable(struct r8152 *tp) +{ + r8152_set_eee_plus(tp); + r8153_set_rx_early_timeout(tp); + r8153_set_rx_early_size(tp); + + return rtl_enable(tp); +} + +static void rtl_disable(struct r8152 *tp) +{ + u32 ocp_data; + + ocp_data = r8152_ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); + ocp_data &= ~RCR_ACPT_ALL; + r8152_ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + + rxdy_gated_en(tp, true); + + r8152_wait_fifo_empty(tp); + r8152_nic_reset(tp); +} + +static void r8152_power_cut_en(struct r8152 *tp, bool enable) +{ + u32 ocp_data; + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); + if (enable) + ocp_data |= POWER_CUT; + else + ocp_data &= ~POWER_CUT; + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); + ocp_data &= ~RESUME_INDICATE; + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); +} + +static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) +{ + u32 ocp_data; + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); + if (enable) + ocp_data |= CPCR_RX_VLAN; + else + ocp_data &= ~CPCR_RX_VLAN; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); +} + +static void r8153_u1u2en(struct r8152 *tp, bool enable) +{ + u8 u1u2[8]; + + if (enable) + memset(u1u2, 0xff, sizeof(u1u2)); + else + memset(u1u2, 0x00, sizeof(u1u2)); + + r8152_usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), + u1u2); +} + +static void r8153b_u1u2en(struct r8152 *tp, bool enable) +{ + u16 ocp_data; + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); + if (enable) + ocp_data |= LPM_U1U2_EN; + else + ocp_data &= ~LPM_U1U2_EN; + + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); +} + +static void r8153_u2p3en(struct r8152 *tp, bool enable) +{ + u32 ocp_data; + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); + if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04) + ocp_data |= U2P3_ENABLE; + else + ocp_data &= ~U2P3_ENABLE; + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); +} + +static void r8153_power_cut_en(struct r8152 *tp, bool enable) +{ + u32 ocp_data; + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); + if (enable) + ocp_data |= PWR_EN | PHASE2_EN; + else + ocp_data &= ~(PWR_EN | PHASE2_EN); + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); + ocp_data &= ~PCUT_STATUS; + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); +} + +static void rtl_reset_bmu(struct r8152 *tp) +{ + u8 ocp_data; + + ocp_data = r8152_ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); + ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); + r8152_ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); + ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; + r8152_ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); +} + +static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr) +{ + int ret; + unsigned char enetaddr[8] = {0}; + + ret = r8152_pla_ocp_read(tp, PLA_IDR, 8, enetaddr); + if (ret < 0) + return ret; + + memcpy(macaddr, enetaddr, ETH_ALEN); + return 0; +} + +static void r8152b_disable_aldps(struct r8152 *tp) +{ + r8152_ocp_reg_write(tp, OCP_ALDPS_CONFIG, + ENPDNPS | LINKENA | DIS_SDSAVE); + mdelay(20); +} + +static void r8152b_enable_aldps(struct r8152 *tp) +{ + r8152_ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | + LINKENA | DIS_SDSAVE); +} + +static void rtl8152_disable(struct r8152 *tp) +{ + r8152b_disable_aldps(tp); + rtl_disable(tp); + r8152b_enable_aldps(tp); +} + +static void r8152b_hw_phy_cfg(struct r8152 *tp) +{ + u16 data; + + data = r8152_mdio_read(tp, MII_BMCR); + if (data & BMCR_PDOWN) { + data &= ~BMCR_PDOWN; + r8152_mdio_write(tp, MII_BMCR, data); + } + + r8152b_firmware(tp); +} + +static void rtl8152_reinit_ll(struct r8152 *tp) +{ + u32 ocp_data; + int ret; + + ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR, + PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT); + if (ret) + dev_dbg(&tp->dev->edev.dev, "Timeout waiting for link list ready\n"); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); + ocp_data |= RE_INIT_LL; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + + ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR, + PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT); + if (ret) + dev_dbg(&tp->dev->edev.dev, "Timeout waiting for link list ready\n"); +} + +static void r8152b_exit_oob(struct r8152 *tp) +{ + u32 ocp_data; + + ocp_data = r8152_ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); + ocp_data &= ~RCR_ACPT_ALL; + r8152_ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + + rxdy_gated_en(tp, true); + r8152b_hw_phy_cfg(tp); + + r8152_ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); + r8152_ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); + + ocp_data = r8152_ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); + ocp_data &= ~NOW_IS_OOB; + r8152_ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); + ocp_data &= ~MCU_BORW_EN; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + + rtl8152_reinit_ll(tp); + r8152_nic_reset(tp); + + /* rx share fifo credit full threshold */ + r8152_ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, + RXFIFO_THR1_NORMAL); + + if (tp->udev->speed == USB_SPEED_FULL || + tp->udev->speed == USB_SPEED_LOW) { + /* rx share fifo credit near full threshold */ + r8152_ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, + RXFIFO_THR2_FULL); + r8152_ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, + RXFIFO_THR3_FULL); + } else { + /* rx share fifo credit near full threshold */ + r8152_ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, + RXFIFO_THR2_HIGH); + r8152_ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, + RXFIFO_THR3_HIGH); + } + + /* TX share fifo free credit full threshold */ + r8152_ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, + TXFIFO_THR_NORMAL); + + r8152_ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); + r8152_ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); + r8152_ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, + TEST_MODE_DISABLE | TX_SIZE_ADJUST1); + + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); + ocp_data |= TCR0_AUTO_FIFO; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); +} + +static void r8153_hw_phy_cfg(struct r8152 *tp) +{ + u32 ocp_data; + u16 data; + + if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || + tp->version == RTL_VER_05) + r8152_ocp_reg_write(tp, OCP_ADC_CFG, + CKADSEL_L | ADC_EN | EN_EMI_L); + + data = r8152_mdio_read(tp, MII_BMCR); + if (data & BMCR_PDOWN) { + data &= ~BMCR_PDOWN; + r8152_mdio_write(tp, MII_BMCR, data); + } + + r8153_firmware(tp); + + if (tp->version == RTL_VER_03) { + data = r8152_ocp_reg_read(tp, OCP_EEE_CFG); + data &= ~CTAP_SHORT_EN; + r8152_ocp_reg_write(tp, OCP_EEE_CFG, data); + } + + data = r8152_ocp_reg_read(tp, OCP_POWER_CFG); + data |= EEE_CLKDIV_EN; + r8152_ocp_reg_write(tp, OCP_POWER_CFG, data); + + data = r8152_ocp_reg_read(tp, OCP_DOWN_SPEED); + data |= EN_10M_BGOFF; + r8152_ocp_reg_write(tp, OCP_DOWN_SPEED, data); + data = r8152_ocp_reg_read(tp, OCP_POWER_CFG); + data |= EN_10M_PLLOFF; + r8152_ocp_reg_write(tp, OCP_POWER_CFG, data); + r8152_sram_write(tp, SRAM_IMPEDANCE, 0x0b13); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); + ocp_data |= PFM_PWM_SWITCH; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); + + /* Enable LPF corner auto tune */ + r8152_sram_write(tp, SRAM_LPF_CFG, 0xf70f); + + /* Adjust 10M Amplitude */ + r8152_sram_write(tp, SRAM_10M_AMP1, 0x00af); + r8152_sram_write(tp, SRAM_10M_AMP2, 0x0208); +} + +static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) +{ + u32 ocp_data; + + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, + EFUSE_READ_CMD | addr); + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); + ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ + ocp_data |= r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); + + return ocp_data; +} + +static void r8153b_hw_phy_cfg(struct r8152 *tp) +{ + u32 ocp_data; + u16 data; + + data = r8152_mdio_read(tp, MII_BMCR); + if (data & BMCR_PDOWN) { + data &= ~BMCR_PDOWN; + r8152_mdio_write(tp, MII_BMCR, data); + } + + /* U1/U2/L1 idle timer. 500 us */ + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); + + r8153b_firmware(tp); + + data = r8152_sram_read(tp, SRAM_GREEN_CFG); + data |= R_TUNE_EN; + r8152_sram_write(tp, SRAM_GREEN_CFG, data); + data = r8152_ocp_reg_read(tp, OCP_NCTL_CFG); + data |= PGA_RETURN_EN; + r8152_ocp_reg_write(tp, OCP_NCTL_CFG, data); + + /* ADC Bias Calibration: + * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake + * bit (bit3) to rebuild the real 16-bit data. Write the data to the + * ADC ioffset. + */ + ocp_data = r8152_efuse_read(tp, 0x7d); + ocp_data = ((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7); + if (ocp_data != 0xffff) + r8152_ocp_reg_write(tp, OCP_ADC_IOFFSET, ocp_data); + + /* ups mode tx-link-pulse timing adjustment: + * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] + * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt + */ + ocp_data = r8152_ocp_reg_read(tp, 0xc426); + ocp_data &= 0x3fff; + if (ocp_data) { + u32 swr_cnt_1ms_ini; + + swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); + ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); + } + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); + ocp_data |= PFM_PWM_SWITCH; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); +} + +static void r8153_first_init(struct r8152 *tp) +{ + u32 ocp_data; + + rxdy_gated_en(tp, true); + + ocp_data = r8152_ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); + ocp_data &= ~RCR_ACPT_ALL; + r8152_ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + + r8153_hw_phy_cfg(tp); + + r8152_nic_reset(tp); + rtl_reset_bmu(tp); + + ocp_data = r8152_ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); + ocp_data &= ~NOW_IS_OOB; + r8152_ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); + ocp_data &= ~MCU_BORW_EN; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + + rtl8152_reinit_ll(tp); + + rtl_rx_vlan_en(tp, false); + + ocp_data = RTL8153_RMS; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); + r8152_ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); + ocp_data |= TCR0_AUTO_FIFO; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); + + r8152_nic_reset(tp); + + /* rx share fifo credit full threshold */ + r8152_ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, + RXFIFO_THR1_NORMAL); + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, + RXFIFO_THR2_NORMAL); + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, + RXFIFO_THR3_NORMAL); + /* TX share fifo free credit full threshold */ + r8152_ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, + TXFIFO_THR_NORMAL2); + + /* rx aggregation */ + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); + + ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); +} + +static void r8153_disable_aldps(struct r8152 *tp) +{ + u16 data; + + data = r8152_ocp_reg_read(tp, OCP_POWER_CFG); + data &= ~EN_ALDPS; + r8152_ocp_reg_write(tp, OCP_POWER_CFG, data); + mdelay(20); +} + +static void rtl8153_disable(struct r8152 *tp) +{ + r8153_disable_aldps(tp); + rtl_disable(tp); + rtl_reset_bmu(tp); +} + +static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) +{ + u16 bmcr, anar, gbcr; + + anar = r8152_mdio_read(tp, MII_ADVERTISE); + anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | + ADVERTISE_100HALF | ADVERTISE_100FULL); + if (tp->supports_gmii) { + gbcr = r8152_mdio_read(tp, MII_CTRL1000); + gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); + } else { + gbcr = 0; + } + + if (autoneg == AUTONEG_DISABLE) { + if (speed == SPEED_10) { + bmcr = 0; + anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; + } else if (speed == SPEED_100) { + bmcr = BMCR_SPEED100; + anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; + } else if (speed == SPEED_1000 && tp->supports_gmii) { + bmcr = BMCR_SPEED1000; + gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; + } else { + return -EINVAL; + } + + if (duplex == DUPLEX_FULL) + bmcr |= BMCR_FULLDPLX; + } else { + if (speed == SPEED_10) { + if (duplex == DUPLEX_FULL) + anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; + else + anar |= ADVERTISE_10HALF; + } else if (speed == SPEED_100) { + if (duplex == DUPLEX_FULL) { + anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; + anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; + } else { + anar |= ADVERTISE_10HALF; + anar |= ADVERTISE_100HALF; + } + } else if (speed == SPEED_1000 && tp->supports_gmii) { + if (duplex == DUPLEX_FULL) { + anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; + anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; + gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; + } else { + anar |= ADVERTISE_10HALF; + anar |= ADVERTISE_100HALF; + gbcr |= ADVERTISE_1000HALF; + } + } else { + return -EINVAL; + } + + bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET; + } + + if (tp->supports_gmii) + r8152_mdio_write(tp, MII_CTRL1000, gbcr); + + r8152_mdio_write(tp, MII_ADVERTISE, anar); + r8152_mdio_write(tp, MII_BMCR, bmcr); + + return 0; +} + +static void rtl8152_up(struct r8152 *tp) +{ + r8152b_disable_aldps(tp); + r8152b_exit_oob(tp); + r8152b_enable_aldps(tp); +} + +static void rtl8153_up(struct r8152 *tp) +{ + r8153_u1u2en(tp, false); + r8153_disable_aldps(tp); + r8153_first_init(tp); + r8153_u2p3en(tp, false); +} + +static void rtl8153b_up(struct r8152 *tp) +{ + r8153_first_init(tp); +} + +static void r8152_get_version(struct r8152 *tp) +{ + u32 ocp_data; + u16 tcr; + int i; + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); + tcr = (u16)(ocp_data & VERSION_MASK); + + for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) { + if (tcr == r8152_versions[i].tcr) { + /* Found a supported version */ + tp->version = r8152_versions[i].version; + tp->supports_gmii = r8152_versions[i].gmii; + break; + } + } + + if (tp->version == RTL_VER_UNKNOWN) + dev_dbg(&tp->dev->edev.dev, + "r8152 Unknown tcr version 0x%04x\n", tcr); +} + +static void r8152b_enable_fc(struct r8152 *tp) +{ + u16 anar; + + anar = r8152_mdio_read(tp, MII_ADVERTISE); + anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; + r8152_mdio_write(tp, MII_ADVERTISE, anar); +} + +static void rtl_tally_reset(struct r8152 *tp) +{ + u32 ocp_data; + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); + ocp_data |= TALLY_RESET; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); +} + +static void rtl8152b_init(struct r8152 *tp) +{ + u32 ocp_data; + + r8152b_disable_aldps(tp); + + if (tp->version == RTL_VER_01) { + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, + PLA_LED_FEATURE); + ocp_data &= ~LED_MODE_MASK; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); + } + + r8152_power_cut_en(tp, false); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); + ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); + ocp_data = r8152_ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); + ocp_data &= ~MCU_CLK_RATIO_MASK; + ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; + r8152_ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); + ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | + SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER); + ocp_data |= BIT(15); + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data); + r8152_ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8); + ocp_data &= ~BIT(15); + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data); + + r8152b_enable_fc(tp); + rtl_tally_reset(tp); + + /* enable rx aggregation */ + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); + + ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); +} + +static void rtl8153_init(struct r8152 *tp) +{ + int i; + u32 ocp_data; + + r8153_disable_aldps(tp); + r8153_u1u2en(tp, false); + + r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL, + AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT); + + for (i = 0; i < R8152_WAIT_TIMEOUT; i++) { + ocp_data = r8152_ocp_reg_read(tp, OCP_PHY_STATUS) & + PHY_STAT_MASK; + if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) + break; + + mdelay(1); + } + + r8153_u2p3en(tp, false); + + if (tp->version == RTL_VER_04) { + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, + USB_SSPHYLINK2); + ocp_data &= ~pwd_dn_scale_mask; + ocp_data |= pwd_dn_scale(96); + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, + ocp_data); + + ocp_data = r8152_ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); + ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; + r8152_ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); + } else if (tp->version == RTL_VER_05) { + ocp_data = r8152_ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); + ocp_data &= ~ECM_ALDPS; + r8152_ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); + + ocp_data = r8152_ocp_read_byte(tp, MCU_TYPE_USB, + USB_CSR_DUMMY1); + if (r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) + ocp_data &= ~DYNAMIC_BURST; + else + ocp_data |= DYNAMIC_BURST; + r8152_ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, + ocp_data); + } else if (tp->version == RTL_VER_06) { + ocp_data = r8152_ocp_read_byte(tp, MCU_TYPE_USB, + USB_CSR_DUMMY1); + if (r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) + ocp_data &= ~DYNAMIC_BURST; + else + ocp_data |= DYNAMIC_BURST; + r8152_ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, + ocp_data); + } + + ocp_data = r8152_ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); + ocp_data |= EP4_FULL_FC; + r8152_ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); + ocp_data &= ~TIMER11_EN; + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); + ocp_data &= ~LED_MODE_MASK; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); + + ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; + if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER) + ocp_data |= LPM_TIMER_500MS; + else + ocp_data |= LPM_TIMER_500US; + r8152_ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); + ocp_data &= ~SEN_VAL_MASK; + ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); + + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); + + r8153_power_cut_en(tp, false); + + r8152b_enable_fc(tp); + rtl_tally_reset(tp); +} + +static void r8153b_init(struct r8152 *tp) +{ + u32 ocp_data; + int i; + + r8153_disable_aldps(tp); + r8153b_u1u2en(tp, false); + + r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL, + AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT); + + for (i = 0; i < R8152_WAIT_TIMEOUT; i++) { + ocp_data = r8152_ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; + if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) + break; + + mdelay(1); + } + + r8153_u2p3en(tp, false); + + /* MSC timer = 0xfff * 8ms = 32760 ms */ + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); + + r8153_power_cut_en(tp, false); + + /* MAC clock speed down */ + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); + ocp_data |= MAC_CLK_SPDWN_EN; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); + ocp_data &= ~PLA_MCU_SPDWN_EN; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); + + if (tp->version == RTL_VER_09) { + /* Disable Test IO for 32QFN */ + if (r8152_ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) { + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_PLA, + PLA_PHY_PWR); + ocp_data |= TEST_IO_OFF; + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, + ocp_data); + } + } + + /* rx aggregation */ + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); + ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); + + rtl_tally_reset(tp); + r8153b_hw_phy_cfg(tp); + r8152b_enable_fc(tp); +} + +static int r8152_ops_init(struct r8152 *tp) +{ + struct rtl_ops *ops = &tp->rtl_ops; + int ret = 0; + + switch (tp->version) { + case RTL_VER_01: + case RTL_VER_02: + case RTL_VER_07: + ops->init = rtl8152b_init; + ops->enable = rtl8152_enable; + ops->disable = rtl8152_disable; + ops->up = rtl8152_up; + break; + + case RTL_VER_03: + case RTL_VER_04: + case RTL_VER_05: + case RTL_VER_06: + ops->init = rtl8153_init; + ops->enable = rtl8153_enable; + ops->disable = rtl8153_disable; + ops->up = rtl8153_up; + break; + + case RTL_VER_08: + case RTL_VER_09: + ops->init = r8153b_init; + ops->enable = rtl8153_enable; + ops->disable = rtl8153_disable; + ops->up = rtl8153b_up; + break; + + default: + ret = -ENODEV; + dev_warn(&tp->dev->edev.dev, "r8152 Unknown Device\n"); + break; + } + + return ret; +} + +static int r8152_init_common(struct r8152 *tp) +{ + int link_detected; + u64 start; + u8 speed; + + dev_dbg(&tp->dev->edev.dev, "** %s()\n", __func__); + + dev_info(&tp->dev->edev.dev, "Waiting for Ethernet connection...\n"); + start = get_time_ns(); + while (1) { + speed = r8152_get_speed(tp); + + link_detected = speed & LINK_STATUS; + if (link_detected) { + tp->rtl_ops.enable(tp); + dev_info(&tp->dev->edev.dev, "done.\n"); + break; + } + + mdelay(TIMEOUT_RESOLUTION); + if (is_timeout(start, PHY_CONNECT_TIMEOUT * MSECOND)) { + dev_warn(&tp->dev->edev.dev, "unable to connect.\n"); + return -ETIMEDOUT; + } + }; + + return 0; +} + +static int r8152_tx_fixup(struct usbnet *dev, void *buf, int len, void *nbuf, + int *nlen) +{ + struct tx_desc *tx_desc = (struct tx_desc *)nbuf; + u32 opts1; + + dev_dbg(&dev->edev.dev, "** %s(), len %d\n", __func__, len); + + opts1 = len | TX_FS | TX_LS; + + tx_desc->opts1 = cpu_to_le32(opts1); + tx_desc->opts2 = 0; + + memcpy(nbuf + sizeof(struct tx_desc), buf, len); + + *nlen = len + sizeof(struct tx_desc); + + return 0; +} + +static int r8152_rx_fixup(struct usbnet *dev, void *buf, int len) +{ + struct rx_desc *rx_desc; + unsigned char *packet; + u16 packet_len; + + rx_desc = (struct rx_desc *)buf; + packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; + packet_len -= CRC_SIZE; + + dev_dbg(&dev->edev.dev, "%s: buf len=%d, packet len=%d\n", __func__, + len, packet_len); + + if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) { + dev_dbg(&dev->edev.dev, "Rx: too large packet: %d\n", + packet_len); + return -EIO; + } + + packet = buf + sizeof(struct rx_desc); + net_receive(&dev->edev, packet, len - sizeof(struct rx_desc)); + + return 0; +} + +static int r8152_eth_reset(struct usbnet *dev) +{ + struct r8152 *tp = r8152_get_priv(dev); + + dev_dbg(&tp->dev->edev.dev, "** %s (%d)\n", __func__, __LINE__); + + tp->rtl_ops.disable(tp); + return r8152_init_common(tp); +} + +static int r8152_common_mdio_read(struct mii_bus *bus, int phy_id, int idx) +{ + struct usbnet *dev = bus->priv; + struct r8152 *tp = r8152_get_priv(dev); + u32 val; + + /* No phy_id is supported, so fake support of address 0 */ + if (phy_id) + return 0xffff; + + val = r8152_mdio_read(tp, idx); + + return val & 0xffff; +} + +static int r8152_common_mdio_write(struct mii_bus *bus, int phy_id, int idx, + u16 regval) +{ + struct usbnet *dev = bus->priv; + struct r8152 *tp = r8152_get_priv(dev); + + /* No phy_id is supported, so fake support of address 0 */ + if (phy_id) + return -EIO; + + r8152_mdio_write(tp, idx, regval); + + return 0; +} + +static int r8152_init_mii(struct usbnet *dev) +{ + dev->miibus.read = r8152_common_mdio_read; + dev->miibus.write = r8152_common_mdio_write; + dev->phy_addr = 0; + dev->miibus.priv = dev; + dev->miibus.parent = &dev->udev->dev; + + return mdiobus_register(&dev->miibus); +} + +static int r8152_write_hwaddr(struct eth_device *edev, const unsigned char *adr) +{ + struct usbnet *dev = container_of(edev, struct usbnet, edev); + struct r8152 *tp = r8152_get_priv(dev); + + dev_dbg(&tp->dev->edev.dev, "** %s (%d)\n", __func__, __LINE__); + + r8152_ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); + r8152_pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, ETH_ALEN, adr); + r8152_ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); + + dev_dbg(&tp->dev->edev.dev, "MAC %pM\n", adr); + return 0; +} + +static int r8152_read_rom_hwaddr(struct eth_device *edev, unsigned char *adr) +{ + struct usbnet *dev = container_of(edev, struct usbnet, edev); + struct r8152 *tp = r8152_get_priv(dev); + + dev_dbg(&tp->dev->edev.dev, "** %s (%d)\n", __func__, __LINE__); + return r8152_read_mac(tp, adr); +} + +static int r8152_eth_bind(struct usbnet *dev) +{ + struct r8152 *tp; + int ret; + + usbnet_get_endpoints(dev); + + tp = xzalloc(sizeof(*tp)); + if (!tp) + return -ENOMEM; + + tp->txbuf = dma_alloc(R8152_TX_BURST_SIZE); + if (!tp->txbuf) + return -ENOMEM; + + tp->rxbuf = dma_alloc(R8152_RX_BURST_SIZE); + if (!tp->rxbuf) + return -ENOMEM; + + dev->driver_priv = tp; + + dev->edev.set_ethaddr = r8152_write_hwaddr; + dev->edev.get_ethaddr = r8152_read_rom_hwaddr; + + r8152_init_mii(dev); + + tp->udev = dev->udev; + tp->dev = dev; + + r8152_get_version(tp); + + ret = r8152_ops_init(tp); + if (ret) + return ret; + + tp->rtl_ops.init(tp); + tp->rtl_ops.up(tp); + + dev->rx_urb_size = RTL8152_AGG_BUF_SZ; + return rtl8152_set_speed(tp, AUTONEG_ENABLE, + tp->supports_gmii ? SPEED_1000 : SPEED_100, + DUPLEX_FULL); +} + +static void r8152_unbind(struct usbnet *dev) +{ + struct r8152 *tp = r8152_get_priv(dev); + + tp->rtl_ops.disable(tp); + mdiobus_unregister(&dev->miibus); + free(tp->txbuf); + free(tp->rxbuf); + free(tp); +} + +static struct driver_info r8152_info = { + .description = R8152_BASE_NAME, + .bind = r8152_eth_bind, + .reset = r8152_eth_reset, + .unbind = r8152_unbind, + .flags = FLAG_ETHER | FLAG_FRAMING_AX, + .rx_fixup = r8152_rx_fixup, + .tx_fixup = r8152_tx_fixup, +}; + +static const struct usb_device_id products[] = { +{ + /* Realtek */ + USB_DEVICE(0x0bda, 0x8050), + .driver_info = &r8152_info, +}, { + USB_DEVICE(0x0bda, 0x8152), + .driver_info = &r8152_info, +}, { + USB_DEVICE(0x0bda, 0x8153), + .driver_info = &r8152_info, +}, { + /* Samsung */ + USB_DEVICE(0x04e8, 0xa101), + .driver_info = &r8152_info, +}, { + /* Lenovo */ + USB_DEVICE(0x17ef, 0x304f), + .driver_info = &r8152_info, +}, { + USB_DEVICE(0x17ef, 0x3052), + .driver_info = &r8152_info, +}, { + USB_DEVICE(0x17ef, 0x3054), + .driver_info = &r8152_info, +}, { + USB_DEVICE(0x17ef, 0x3057), + .driver_info = &r8152_info, +}, { + USB_DEVICE(0x17ef, 0x7205), + .driver_info = &r8152_info, +}, { + USB_DEVICE(0x17ef, 0x720a), + .driver_info = &r8152_info, +}, { + USB_DEVICE(0x17ef, 0x720b), + .driver_info = &r8152_info, +}, { + USB_DEVICE(0x17ef, 0x720c), + .driver_info = &r8152_info, +}, { + /* TP-LINK */ + USB_DEVICE(0x2357, 0x0601), + .driver_info = &r8152_info, +}, { + /* Nvidia */ + USB_DEVICE(0x0955, 0x09ff), + .driver_info = &r8152_info, +}, + + { } /* Terminating entry */ +}; + +static struct usb_driver r8152_driver = { + .name = R8152_BASE_NAME, + .id_table = products, + .probe = usbnet_probe, + .disconnect = usbnet_disconnect, +}; + +static int __init r8152_init(void) +{ + return usb_driver_register(&r8152_driver); +} +device_initcall(r8152_init); diff --git a/drivers/net/usb/r8152.h b/drivers/net/usb/r8152.h new file mode 100644 index 0000000000..696a414660 --- /dev/null +++ b/drivers/net/usb/r8152.h @@ -0,0 +1,619 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved. */ + +#ifndef _RTL8152_ETH_H +#define _RTL8152_ETH_H + +#define R8152_BASE_NAME "r8152" + +#define PLA_IDR 0xc000 +#define PLA_RCR 0xc010 +#define PLA_RMS 0xc016 +#define PLA_RXFIFO_CTRL0 0xc0a0 +#define PLA_RXFIFO_CTRL1 0xc0a4 +#define PLA_RXFIFO_CTRL2 0xc0a8 +#define PLA_DMY_REG0 0xc0b0 +#define PLA_FMC 0xc0b4 +#define PLA_CFG_WOL 0xc0b6 +#define PLA_TEREDO_CFG 0xc0bc +#define PLA_MAR 0xcd00 +#define PLA_BACKUP 0xd000 +#define PLA_BDC_CR 0xd1a0 +#define PLA_TEREDO_TIMER 0xd2cc +#define PLA_REALWOW_TIMER 0xd2e8 +#define PLA_EXTRA_STATUS 0xd398 +#define PLA_EFUSE_DATA 0xdd00 +#define PLA_EFUSE_CMD 0xdd02 +#define PLA_LEDSEL 0xdd90 +#define PLA_LED_FEATURE 0xdd92 +#define PLA_PHYAR 0xde00 +#define PLA_BOOT_CTRL 0xe004 +#define PLA_GPHY_INTR_IMR 0xe022 +#define PLA_EEE_CR 0xe040 +#define PLA_EEEP_CR 0xe080 +#define PLA_MAC_PWR_CTRL 0xe0c0 +#define PLA_MAC_PWR_CTRL2 0xe0ca +#define PLA_MAC_PWR_CTRL3 0xe0cc +#define PLA_MAC_PWR_CTRL4 0xe0ce +#define PLA_WDT6_CTRL 0xe428 +#define PLA_TCR0 0xe610 +#define PLA_TCR1 0xe612 +#define PLA_MTPS 0xe615 +#define PLA_TXFIFO_CTRL 0xe618 +#define PLA_RSTTALLY 0xe800 +#define BIST_CTRL 0xe810 +#define PLA_CR 0xe813 +#define PLA_CRWECR 0xe81c +#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ +#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ +#define PLA_CONFIG5 0xe822 +#define PLA_PHY_PWR 0xe84c +#define PLA_OOB_CTRL 0xe84f +#define PLA_CPCR 0xe854 +#define PLA_MISC_0 0xe858 +#define PLA_MISC_1 0xe85a +#define PLA_OCP_GPHY_BASE 0xe86c +#define PLA_TALLYCNT 0xe890 +#define PLA_SFF_STS_7 0xe8de +#define PLA_PHYSTATUS 0xe908 +#define PLA_BP_BA 0xfc26 +#define PLA_BP_0 0xfc28 +#define PLA_BP_1 0xfc2a +#define PLA_BP_2 0xfc2c +#define PLA_BP_3 0xfc2e +#define PLA_BP_4 0xfc30 +#define PLA_BP_5 0xfc32 +#define PLA_BP_6 0xfc34 +#define PLA_BP_7 0xfc36 +#define PLA_BP_EN 0xfc38 + +#define USB_USB2PHY 0xb41e +#define USB_SSPHYLINK2 0xb428 +#define USB_U2P3_CTRL 0xb460 +#define USB_CSR_DUMMY1 0xb464 +#define USB_CSR_DUMMY2 0xb466 +#define USB_DEV_STAT 0xb808 +#define USB_CONNECT_TIMER 0xcbf8 +#define USB_MSC_TIMER 0xcbfc +#define USB_BURST_SIZE 0xcfc0 +#define USB_FW_FIX_EN1 0xcfcc +#define USB_LPM_CONFIG 0xcfd8 +#define USB_USB_CTRL 0xd406 +#define USB_PHY_CTRL 0xd408 +#define USB_TX_AGG 0xd40a +#define USB_RX_BUF_TH 0xd40c +#define USB_USB_TIMER 0xd428 +#define USB_RX_EARLY_TIMEOUT 0xd42c +#define USB_RX_EARLY_SIZE 0xd42e +#define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ +#define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ +#define USB_TX_DMA 0xd434 +#define USB_UPT_RXDMA_OWN 0xd437 +#define USB_TOLERANCE 0xd490 +#define USB_LPM_CTRL 0xd41a +#define USB_BMU_RESET 0xd4b0 +#define USB_U1U2_TIMER 0xd4da +#define USB_UPS_CTRL 0xd800 +#define USB_POWER_CUT 0xd80a +#define USB_MISC_0 0xd81a +#define USB_AFE_CTRL2 0xd824 +#define USB_UPS_CFG 0xd842 +#define USB_WDT11_CTRL 0xe43c +#define USB_BP_BA PLA_BP_BA +#define USB_BP(n) (0xfc28 + 2 * (n)) +#define USB_BP_EN PLA_BP_EN /* RTL8153A */ +#define USB_BP2_EN 0xfc48 + +/* OCP Registers */ +#define OCP_ALDPS_CONFIG 0x2010 +#define OCP_EEE_CONFIG1 0x2080 +#define OCP_EEE_CONFIG2 0x2092 +#define OCP_EEE_CONFIG3 0x2094 +#define OCP_BASE_MII 0xa400 +#define OCP_EEE_AR 0xa41a +#define OCP_EEE_DATA 0xa41c +#define OCP_PHY_STATUS 0xa420 +#define OCP_NCTL_CFG 0xa42c +#define OCP_POWER_CFG 0xa430 +#define OCP_EEE_CFG 0xa432 +#define OCP_SRAM_ADDR 0xa436 +#define OCP_SRAM_DATA 0xa438 +#define OCP_DOWN_SPEED 0xa442 +#define OCP_EEE_ABLE 0xa5c4 +#define OCP_EEE_ADV 0xa5d0 +#define OCP_EEE_LPABLE 0xa5d2 +#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ +#define OCP_ADC_IOFFSET 0xbcfc +#define OCP_ADC_CFG 0xbc06 + +/* SRAM Register */ +#define SRAM_GREEN_CFG 0x8011 +#define SRAM_LPF_CFG 0x8012 +#define SRAM_10M_AMP1 0x8080 +#define SRAM_10M_AMP2 0x8082 +#define SRAM_IMPEDANCE 0x8084 + +/* PLA_RCR */ +#define RCR_AAP 0x00000001 +#define RCR_APM 0x00000002 +#define RCR_AM 0x00000004 +#define RCR_AB 0x00000008 +#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) + +/* PLA_RXFIFO_CTRL0 */ +#define RXFIFO_THR1_NORMAL 0x00080002 +#define RXFIFO_THR1_OOB 0x01800003 + +/* PLA_RXFIFO_CTRL1 */ +#define RXFIFO_THR2_FULL 0x00000060 +#define RXFIFO_THR2_HIGH 0x00000038 +#define RXFIFO_THR2_OOB 0x0000004a +#define RXFIFO_THR2_NORMAL 0x00a0 + +/* PLA_RXFIFO_CTRL2 */ +#define RXFIFO_THR3_FULL 0x00000078 +#define RXFIFO_THR3_HIGH 0x00000048 +#define RXFIFO_THR3_OOB 0x0000005a +#define RXFIFO_THR3_NORMAL 0x0110 + +/* PLA_TXFIFO_CTRL */ +#define TXFIFO_THR_NORMAL 0x00400008 +#define TXFIFO_THR_NORMAL2 0x01000008 + +/* PLA_DMY_REG0 */ +#define ECM_ALDPS 0x0002 + +/* PLA_FMC */ +#define FMC_FCR_MCU_EN 0x0001 + +/* PLA_EEEP_CR */ +#define EEEP_CR_EEEP_TX 0x0002 + +/* PLA_WDT6_CTRL */ +#define WDT6_SET_MODE 0x0010 + +/* PLA_TCR0 */ +#define TCR0_TX_EMPTY 0x0800 +#define TCR0_AUTO_FIFO 0x0080 + +/* PLA_TCR1 */ +#define VERSION_MASK 0x7cf0 + +/* PLA_MTPS */ +#define MTPS_JUMBO (12 * 1024 / 64) +#define MTPS_DEFAULT (6 * 1024 / 64) + +/* PLA_RSTTALLY */ +#define TALLY_RESET 0x0001 + +/* PLA_CR */ +#define PLA_CR_RST 0x10 +#define PLA_CR_RE 0x08 +#define PLA_CR_TE 0x04 + +/* PLA_BIST_CTRL */ +#define BIST_CTRL_SW_RESET (0x10 << 24) + +/* PLA_CRWECR */ +#define CRWECR_NORAML 0x00 +#define CRWECR_CONFIG 0xc0 + +/* PLA_OOB_CTRL */ +#define NOW_IS_OOB 0x80 +#define TXFIFO_EMPTY 0x20 +#define RXFIFO_EMPTY 0x10 +#define LINK_LIST_READY 0x02 +#define DIS_MCU_CLROOB 0x01 +#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) + +/* PLA_PHY_PWR */ +#define PLA_PHY_PWR_LLR (LINK_LIST_READY << 24) +#define PLA_PHY_PWR_TXEMP (TXFIFO_EMPTY << 24) +#define TEST_IO_OFF BIT(4) + +/* PLA_MISC_1 */ +#define RXDY_GATED_EN 0x0008 + +/* PLA_SFF_STS_7 */ +#define RE_INIT_LL 0x8000 +#define MCU_BORW_EN 0x4000 + +/* PLA_CPCR */ +#define CPCR_RX_VLAN 0x0040 + +/* PLA_CFG_WOL */ +#define MAGIC_EN 0x0001 + +/* PLA_TEREDO_CFG */ +#define TEREDO_SEL 0x8000 +#define TEREDO_WAKE_MASK 0x7f00 +#define TEREDO_RS_EVENT_MASK 0x00fe +#define OOB_TEREDO_EN 0x0001 + +/* PLA_BDC_CR */ +#define ALDPS_PROXY_MODE 0x0001 + +/* PLA_EFUSE_CMD */ +#define EFUSE_READ_CMD BIT(15) +#define EFUSE_DATA_BIT16 BIT(7) + +/* PLA_CONFIG34 */ +#define LINK_ON_WAKE_EN 0x0010 +#define LINK_OFF_WAKE_EN 0x0008 + +/* PLA_CONFIG5 */ +#define BWF_EN 0x0040 +#define MWF_EN 0x0020 +#define UWF_EN 0x0010 +#define LAN_WAKE_EN 0x0002 + +/* PLA_LED_FEATURE */ +#define LED_MODE_MASK 0x0700 + +/* PLA_PHY_PWR */ +#define TX_10M_IDLE_EN 0x0080 +#define PFM_PWM_SWITCH 0x0040 + +/* PLA_MAC_PWR_CTRL */ +#define D3_CLK_GATED_EN 0x00004000 +#define MCU_CLK_RATIO 0x07010f07 +#define MCU_CLK_RATIO_MASK 0x0f0f0f0f +#define ALDPS_SPDWN_RATIO 0x0f87 + +/* PLA_MAC_PWR_CTRL2 */ +#define EEE_SPDWN_RATIO 0x8007 +#define MAC_CLK_SPDWN_EN BIT(15) + +/* PLA_MAC_PWR_CTRL3 */ +#define PLA_MCU_SPDWN_EN BIT(14) +#define PKT_AVAIL_SPDWN_EN 0x0100 +#define SUSPEND_SPDWN_EN 0x0004 +#define U1U2_SPDWN_EN 0x0002 +#define L1_SPDWN_EN 0x0001 + +/* PLA_MAC_PWR_CTRL4 */ +#define PWRSAVE_SPDWN_EN 0x1000 +#define RXDV_SPDWN_EN 0x0800 +#define TX10MIDLE_EN 0x0100 +#define TP100_SPDWN_EN 0x0020 +#define TP500_SPDWN_EN 0x0010 +#define TP1000_SPDWN_EN 0x0008 +#define EEE_SPDWN_EN 0x0001 + +/* PLA_GPHY_INTR_IMR */ +#define GPHY_STS_MSK 0x0001 +#define SPEED_DOWN_MSK 0x0002 +#define SPDWN_RXDV_MSK 0x0004 +#define SPDWN_LINKCHG_MSK 0x0008 + +/* PLA_PHYAR */ +#define PHYAR_FLAG 0x80000000 + +/* PLA_EEE_CR */ +#define EEE_RX_EN 0x0001 +#define EEE_TX_EN 0x0002 + +/* PLA_BOOT_CTRL */ +#define AUTOLOAD_DONE 0x0002 + +/* PLA_EXTRA_STATUS */ +#define U3P3_CHECK_EN BIT(7) + +/* USB_USB2PHY */ +#define USB2PHY_SUSPEND 0x0001 +#define USB2PHY_L1 0x0002 + +/* USB_SSPHYLINK2 */ +#define pwd_dn_scale_mask 0x3ffe +#define pwd_dn_scale(x) ((x) << 1) + +/* USB_CSR_DUMMY1 */ +#define DYNAMIC_BURST 0x0001 + +/* USB_CSR_DUMMY2 */ +#define EP4_FULL_FC 0x0001 + +/* USB_DEV_STAT */ +#define STAT_SPEED_MASK 0x0006 +#define STAT_SPEED_HIGH 0x0000 +#define STAT_SPEED_FULL 0x0002 + +/* USB_FW_FIX_EN1 */ +#define FW_IP_RESET_EN BIT(9) + +/* USB_LPM_CONFIG */ +#define LPM_U1U2_EN BIT(0) + +/* USB_TX_AGG */ +#define TX_AGG_MAX_THRESHOLD 0x03 + +/* USB_RX_BUF_TH */ +#define RX_THR_SUPPER 0x0c350180 +#define RX_THR_HIGH 0x7a120180 +#define RX_THR_SLOW 0xffff0180 + +/* USB_RX_EARLY_TIMEOUT */ +#define RX_AUXILIARY_TIMER 1264 + +/* USB_TX_DMA */ +#define TEST_MODE_DISABLE 0x00000001 +#define TX_SIZE_ADJUST1 0x00000100 + +/* USB_BMU_RESET */ +#define BMU_RESET_EP_IN 0x01 +#define BMU_RESET_EP_OUT 0x02 + +/* USB_UPT_RXDMA_OWN */ +#define OWN_UPDATE BIT(0) +#define OWN_CLEAR BIT(1) + +/* USB_UPS_CTRL */ +#define POWER_CUT 0x0100 + +/* USB_PM_CTRL_STATUS */ +#define RESUME_INDICATE 0x0001 + +/* USB_USB_CTRL */ +#define RX_AGG_DISABLE 0x0010 +#define RX_ZERO_EN 0x0080 + +/* USB_U2P3_CTRL */ +#define U2P3_ENABLE 0x0001 + +/* USB_POWER_CUT */ +#define PWR_EN 0x0001 +#define PHASE2_EN 0x0008 + +/* USB_MISC_0 */ +#define PCUT_STATUS 0x0001 + +/* USB_RX_EARLY_TIMEOUT */ +#define COALESCE_SUPER 85000U +#define COALESCE_HIGH 250000U +#define COALESCE_SLOW 524280U + +/* USB_WDT11_CTRL */ +#define TIMER11_EN 0x0001 + +/* USB_LPM_CTRL */ +/* bit 4 ~ 5: fifo empty boundary */ +#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ +/* bit 2 ~ 3: LMP timer */ +#define LPM_TIMER_MASK 0x0c +#define LPM_TIMER_500MS 0x04 /* 500 ms */ +#define LPM_TIMER_500US 0x0c /* 500 us */ +#define ROK_EXIT_LPM 0x02 + +/* USB_AFE_CTRL2 */ +#define SEN_VAL_MASK 0xf800 +#define SEN_VAL_NORMAL 0xa000 +#define SEL_RXIDLE 0x0100 + +/* USB_UPS_CFG */ +#define SAW_CNT_1MS_MASK 0x0fff + +/* OCP_ALDPS_CONFIG */ +#define ENPWRSAVE 0x8000 +#define ENPDNPS 0x0200 +#define LINKENA 0x0100 +#define DIS_SDSAVE 0x0010 + +/* OCP_PHY_STATUS */ +#define PHY_STAT_MASK 0x0007 +#define PHY_STAT_LAN_ON 3 +#define PHY_STAT_PWRDN 5 + +/* OCP_NCTL_CFG */ +#define PGA_RETURN_EN BIT(1) + +/* OCP_POWER_CFG */ +#define EEE_CLKDIV_EN 0x8000 +#define EN_ALDPS 0x0004 +#define EN_10M_PLLOFF 0x0001 + +/* OCP_EEE_CONFIG1 */ +#define RG_TXLPI_MSK_HFDUP 0x8000 +#define RG_MATCLR_EN 0x4000 +#define EEE_10_CAP 0x2000 +#define EEE_NWAY_EN 0x1000 +#define TX_QUIET_EN 0x0200 +#define RX_QUIET_EN 0x0100 +#define sd_rise_time_mask 0x0070 +#define sd_rise_time(x) (min((x), 7) << 4) /* bit 4 ~ 6 */ +#define RG_RXLPI_MSK_HFDUP 0x0008 +#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ + +/* OCP_EEE_CONFIG2 */ +#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ +#define RG_DACQUIET_EN 0x0400 +#define RG_LDVQUIET_EN 0x0200 +#define RG_CKRSEL 0x0020 +#define RG_EEEPRG_EN 0x0010 + +/* OCP_EEE_CONFIG3 */ +#define fast_snr_mask 0xff80 +#define fast_snr(x) (min((x), 0x1ff) << 7) /* bit 7 ~ 15 */ +#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ +#define MSK_PH 0x0006 /* bit 0 ~ 3 */ + +/* OCP_EEE_AR */ +/* bit[15:14] function */ +#define FUN_ADDR 0x0000 +#define FUN_DATA 0x4000 +/* bit[4:0] device addr */ + +/* OCP_EEE_CFG */ +#define CTAP_SHORT_EN 0x0040 +#define EEE10_EN 0x0010 + +/* OCP_DOWN_SPEED */ +#define EN_10M_BGOFF 0x0080 + +/* OCP_PHY_STATE */ +#define TXDIS_STATE 0x01 +#define ABD_STATE 0x02 + +/* OCP_ADC_CFG */ +#define CKADSEL_L 0x0100 +#define ADC_EN 0x0080 +#define EN_EMI_L 0x0040 + +/* SRAM_GREEN_CFG */ +#define GREEN_ETH_EN BIT(15) +#define R_TUNE_EN BIT(11) + +/* SRAM_LPF_CFG */ +#define LPF_AUTO_TUNE 0x8000 + +/* SRAM_10M_AMP1 */ +#define GDAC_IB_UPALL 0x0008 + +/* SRAM_10M_AMP2 */ +#define AMP_DN 0x0200 + +/* SRAM_IMPEDANCE */ +#define RX_DRIVING_MASK 0x6000 + +#define RTL8152_MAX_TX 4 +#define RTL8152_MAX_RX 10 +#define INTBUFSIZE 2 +#define CRC_SIZE 4 +#define TX_ALIGN 4 +#define RX_ALIGN 8 + +#define INTR_LINK 0x0004 + +#define RTL8152_REQT_READ 0xc0 +#define RTL8152_REQT_WRITE 0x40 +#define RTL8152_REQ_GET_REGS 0x05 +#define RTL8152_REQ_SET_REGS 0x05 + +#define BYTE_EN_DWORD 0xff +#define BYTE_EN_WORD 0x33 +#define BYTE_EN_BYTE 0x11 +#define BYTE_EN_SIX_BYTES 0x3f +#define BYTE_EN_START_MASK 0x0f +#define BYTE_EN_END_MASK 0xf0 + +#define RTL8152_ETH_FRAME_LEN 1514 +#define RTL8152_AGG_BUF_SZ 2048 + +#define RTL8152_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE) +#define RTL8153_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE) +#define RTL8152_TX_TIMEOUT (5 * HZ) + +#define MCU_TYPE_PLA 0x0100 +#define MCU_TYPE_USB 0x0000 + +#define TIMEOUT_RESOLUTION 50 +#define PHY_CONNECT_TIMEOUT 5000 +#define USB_BULK_SEND_TIMEOUT 5000 +#define USB_BULK_RECV_TIMEOUT 5000 +#define R8152_WAIT_TIMEOUT 2000 + +struct rx_desc { + __le32 opts1; +#define RD_CRC BIT(15) +#define RX_LEN_MASK 0x7fff + + __le32 opts2; +#define RD_UDP_CS BIT(23) +#define RD_TCP_CS BIT(22) +#define RD_IPV6_CS BIT(20) +#define RD_IPV4_CS BIT(19) + + __le32 opts3; +#define IPF BIT(23) /* IP checksum fail */ +#define UDPF BIT(22) /* UDP checksum fail */ +#define TCPF BIT(21) /* TCP checksum fail */ +#define RX_VLAN_TAG BIT(16) + + __le32 opts4; + __le32 opts5; + __le32 opts6; +}; + +struct tx_desc { + __le32 opts1; +#define TX_FS BIT(31) /* First segment of a packet */ +#define TX_LS BIT(30) /* Final segment of a packet */ +#define LGSEND BIT(29) +#define GTSENDV4 BIT(28) +#define GTSENDV6 BIT(27) +#define GTTCPHO_SHIFT 18 +#define GTTCPHO_MAX 0x7fU +#define TX_LEN_MAX 0x3ffffU + + __le32 opts2; +#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ +#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ +#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ +#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ +#define MSS_SHIFT 17 +#define MSS_MAX 0x7ffU +#define TCPHO_SHIFT 17 +#define TCPHO_MAX 0x7ffU +#define TX_VLAN_TAG BIT(16) +}; + +enum rtl_version { + RTL_VER_UNKNOWN = 0, + RTL_VER_01, + RTL_VER_02, + RTL_VER_03, + RTL_VER_04, + RTL_VER_05, + RTL_VER_06, + RTL_VER_07, + RTL_VER_08, + RTL_VER_09, + RTL_VER_MAX +}; + +enum rtl_register_content { + _1000bps = 0x10, + _100bps = 0x08, + _10bps = 0x04, + LINK_STATUS = 0x02, + FULL_DUP = 0x01, +}; + +struct r8152 { + struct usb_device *udev; + struct usbnet *dev; + struct usb_interface *intf; + bool supports_gmii; + void *txbuf; + void *rxbuf; + + struct rtl_ops { + void (*init)(struct r8152 *tp); + int (*enable)(struct r8152 *tp); + void (*disable)(struct r8152 *tp); + void (*up)(struct r8152 *tp); + } rtl_ops; + + u32 coalesce; + u16 ocp_base; + + u8 version; +}; + +int r8152_generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, + u16 size, const void *data, u16 type); + +u16 r8152_ocp_read_word(struct r8152 *tp, u16 type, u16 index); +void r8152_ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data); + +u8 r8152_ocp_read_byte(struct r8152 *tp, u16 type, u16 index); +void r8152_ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data); + +u16 r8152_ocp_reg_read(struct r8152 *tp, u16 addr); +void r8152_ocp_reg_write(struct r8152 *tp, u16 addr, u16 data); + +void r8152_sram_write(struct r8152 *tp, u16 addr, u16 data); + +void r8152b_firmware(struct r8152 *tp); +void r8153_firmware(struct r8152 *tp); +void r8153b_firmware(struct r8152 *tp); +#endif diff --git a/drivers/net/usb/r8152_fw.c b/drivers/net/usb/r8152_fw.c new file mode 100644 index 0000000000..46f48d276b --- /dev/null +++ b/drivers/net/usb/r8152_fw.c @@ -0,0 +1,1199 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved. */ + +#include <common.h> +#include <usb/usb.h> +#include <usb/usbnet.h> +#include "r8152.h" + +static const u8 r8152b_pla_patch_a[] = { + 0x08, 0xe0, 0x40, 0xe0, 0x78, 0xe0, 0x85, 0xe0, + 0x5d, 0xe1, 0xa1, 0xe1, 0xa3, 0xe1, 0xab, 0xe1, + 0x31, 0xc3, 0x60, 0x72, 0xa0, 0x49, 0x10, 0xf0, + 0xa4, 0x49, 0x0e, 0xf0, 0x2c, 0xc3, 0x62, 0x72, + 0x26, 0x70, 0x80, 0x49, 0x05, 0xf0, 0x2f, 0x48, + 0x62, 0x9a, 0x24, 0x70, 0x60, 0x98, 0x24, 0xc3, + 0x60, 0x99, 0x23, 0xc3, 0x00, 0xbb, 0x2c, 0x75, + 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13, 0x0a, 0xf0, + 0x03, 0x13, 0x08, 0xf0, 0x02, 0x13, 0x06, 0xf0, + 0x01, 0x13, 0x04, 0xf0, 0x08, 0x13, 0x02, 0xf0, + 0x03, 0xe0, 0xd4, 0x49, 0x04, 0xf1, 0x14, 0xc2, + 0x12, 0xc3, 0x00, 0xbb, 0x12, 0xc3, 0x60, 0x75, + 0xd0, 0x49, 0x05, 0xf1, 0x50, 0x48, 0x60, 0x9d, + 0x09, 0xc6, 0x00, 0xbe, 0xd0, 0x48, 0x60, 0x9d, + 0xf3, 0xe7, 0xc2, 0xc0, 0x38, 0xd2, 0xc6, 0xd2, + 0x84, 0x17, 0xa2, 0x13, 0x0c, 0x17, 0xbc, 0xc0, + 0xa2, 0xd1, 0x33, 0xc5, 0xa0, 0x74, 0xc0, 0x49, + 0x1f, 0xf0, 0x30, 0xc5, 0xa0, 0x73, 0x00, 0x13, + 0x04, 0xf1, 0xa2, 0x73, 0x00, 0x13, 0x14, 0xf0, + 0x28, 0xc5, 0xa0, 0x74, 0xc8, 0x49, 0x1b, 0xf1, + 0x26, 0xc5, 0xa0, 0x76, 0xa2, 0x74, 0x01, 0x06, + 0x20, 0x37, 0xa0, 0x9e, 0xa2, 0x9c, 0x1e, 0xc5, + 0xa2, 0x73, 0x23, 0x40, 0x10, 0xf8, 0x04, 0xf3, + 0xa0, 0x73, 0x33, 0x40, 0x0c, 0xf8, 0x15, 0xc5, + 0xa0, 0x74, 0x41, 0x48, 0xa0, 0x9c, 0x14, 0xc5, + 0xa0, 0x76, 0x62, 0x48, 0xe0, 0x48, 0xa0, 0x9e, + 0x10, 0xc6, 0x00, 0xbe, 0x0a, 0xc5, 0xa0, 0x74, + 0x48, 0x48, 0xa0, 0x9c, 0x0b, 0xc5, 0x20, 0x1e, + 0xa0, 0x9e, 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7, + 0xbc, 0xc0, 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4, + 0x22, 0x02, 0xf0, 0xc0, 0x0b, 0xc0, 0x00, 0x71, + 0x0a, 0xc0, 0x00, 0x72, 0xa0, 0x49, 0x04, 0xf0, + 0xa4, 0x49, 0x02, 0xf0, 0x93, 0x48, 0x04, 0xc0, + 0x00, 0xb8, 0x00, 0xe4, 0xc2, 0xc0, 0x8c, 0x09, + 0x14, 0xc2, 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b, + 0x11, 0xc2, 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0, + 0xbf, 0x49, 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd, + 0xb1, 0x49, 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b, + 0x02, 0xc2, 0x00, 0xba, 0x82, 0x18, 0x00, 0xa0, + 0x1e, 0xfc, 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8, + 0x00, 0x80, 0x00, 0x60, 0x2c, 0x75, 0xd4, 0x49, + 0x12, 0xf1, 0x29, 0xe0, 0xf8, 0xc2, 0x46, 0x71, + 0xf7, 0xc2, 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1, + 0xf5, 0xc7, 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30, + 0x26, 0x62, 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72, + 0xa0, 0x49, 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f, + 0x97, 0x30, 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75, + 0x32, 0xc3, 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1, + 0xdc, 0x21, 0xbc, 0x25, 0x27, 0xc6, 0xc0, 0x77, + 0x04, 0x13, 0x18, 0xf0, 0x03, 0x13, 0x19, 0xf0, + 0x02, 0x13, 0x1a, 0xf0, 0x01, 0x13, 0x1b, 0xf0, + 0xd4, 0x49, 0x03, 0xf1, 0x1c, 0xc5, 0x00, 0xbd, + 0xcd, 0xc6, 0xc6, 0x67, 0x2e, 0x75, 0xd7, 0x22, + 0xdd, 0x26, 0x05, 0x15, 0x1a, 0xf0, 0x14, 0xc6, + 0x00, 0xbe, 0x13, 0xc5, 0x00, 0xbd, 0x12, 0xc5, + 0x00, 0xbd, 0xf1, 0x49, 0xfb, 0xf1, 0xef, 0xe7, + 0xf4, 0x49, 0xfa, 0xf1, 0xec, 0xe7, 0xf3, 0x49, + 0xf7, 0xf1, 0xe9, 0xe7, 0xf2, 0x49, 0xf4, 0xf1, + 0xe6, 0xe7, 0xb6, 0xc0, 0x6a, 0x14, 0xac, 0x13, + 0xd6, 0x13, 0xfa, 0x14, 0xa0, 0xd1, 0x00, 0x00, + 0xc0, 0x75, 0xd0, 0x49, 0x46, 0xf0, 0x26, 0x72, + 0xa7, 0x49, 0x43, 0xf0, 0x22, 0x72, 0x25, 0x25, + 0x20, 0x1f, 0x97, 0x30, 0x91, 0x30, 0x40, 0x73, + 0xf3, 0xc4, 0x1c, 0x40, 0x04, 0xf0, 0xd7, 0x49, + 0x05, 0xf1, 0x37, 0xe0, 0x53, 0x48, 0xc0, 0x9d, + 0x08, 0x02, 0x40, 0x66, 0x64, 0x27, 0x06, 0x16, + 0x30, 0xf1, 0x46, 0x63, 0x3b, 0x13, 0x2d, 0xf1, + 0x34, 0x9b, 0x18, 0x1b, 0x93, 0x30, 0x2b, 0xc3, + 0x10, 0x1c, 0x2b, 0xe8, 0x01, 0x14, 0x25, 0xf1, + 0x00, 0x1d, 0x26, 0x1a, 0x8a, 0x30, 0x22, 0x73, + 0xb5, 0x25, 0x0e, 0x0b, 0x00, 0x1c, 0x2c, 0xe8, + 0x1f, 0xc7, 0x27, 0x40, 0x1a, 0xf1, 0x38, 0xe8, + 0x32, 0x1f, 0x8f, 0x30, 0x08, 0x1b, 0x24, 0xe8, + 0x36, 0x72, 0x46, 0x77, 0x00, 0x17, 0x0d, 0xf0, + 0x13, 0xc3, 0x1f, 0x40, 0x03, 0xf1, 0x00, 0x1f, + 0x46, 0x9f, 0x44, 0x77, 0x9f, 0x44, 0x5f, 0x44, + 0x17, 0xe8, 0x0a, 0xc7, 0x27, 0x40, 0x05, 0xf1, + 0x02, 0xc3, 0x00, 0xbb, 0x50, 0x1a, 0x06, 0x1a, + 0xff, 0xc7, 0x00, 0xbf, 0xb8, 0xcd, 0xff, 0xff, + 0x02, 0x0c, 0x54, 0xa5, 0xdc, 0xa5, 0x2f, 0x40, + 0x05, 0xf1, 0x00, 0x14, 0xfa, 0xf1, 0x01, 0x1c, + 0x02, 0xe0, 0x00, 0x1c, 0x80, 0xff, 0xb0, 0x49, + 0x04, 0xf0, 0x01, 0x0b, 0xd3, 0xa1, 0x03, 0xe0, + 0x02, 0x0b, 0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37, + 0x02, 0x0b, 0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37, + 0x00, 0x13, 0xfb, 0xf1, 0x80, 0xff, 0x22, 0x73, + 0xb5, 0x25, 0x18, 0x1e, 0xde, 0x30, 0xd9, 0x30, + 0x64, 0x72, 0x11, 0x1e, 0x68, 0x23, 0x16, 0x31, + 0x80, 0xff, 0xd4, 0x49, 0x28, 0xf0, 0x02, 0xb4, + 0x2a, 0xc4, 0x00, 0x1d, 0x2e, 0xe8, 0xe0, 0x73, + 0xb9, 0x21, 0xbd, 0x25, 0x04, 0x13, 0x02, 0xf0, + 0x1a, 0xe0, 0x22, 0xc4, 0x23, 0xc3, 0x2f, 0xe8, + 0x23, 0xc3, 0x2d, 0xe8, 0x00, 0x1d, 0x21, 0xe8, + 0xe2, 0x73, 0xbb, 0x49, 0xfc, 0xf0, 0xe0, 0x73, + 0xb7, 0x48, 0x03, 0xb4, 0x81, 0x1d, 0x19, 0xe8, + 0x40, 0x1a, 0x84, 0x1d, 0x16, 0xe8, 0x12, 0xc3, + 0x1e, 0xe8, 0x03, 0xb0, 0x81, 0x1d, 0x11, 0xe8, + 0x0e, 0xc3, 0x19, 0xe8, 0x02, 0xb0, 0x06, 0xc7, + 0x04, 0x1e, 0xe0, 0x9e, 0x02, 0xc6, 0x00, 0xbe, + 0x22, 0x02, 0x20, 0xe4, 0x04, 0xb8, 0x34, 0xb0, + 0x00, 0x02, 0x00, 0x03, 0x00, 0x0e, 0x00, 0x0c, + 0x09, 0xc7, 0xe0, 0x9b, 0xe2, 0x9a, 0xe4, 0x9c, + 0xe6, 0x8d, 0xe6, 0x76, 0xef, 0x49, 0xfe, 0xf1, + 0x80, 0xff, 0x08, 0xea, 0x82, 0x1d, 0xf5, 0xef, + 0x00, 0x1a, 0x88, 0x1d, 0xf2, 0xef, 0xed, 0xc2, + 0xf0, 0xef, 0x80, 0xff, 0x02, 0xc6, 0x00, 0xbe, + 0x46, 0x06, 0x08, 0xc2, 0x40, 0x73, 0x3a, 0x48, + 0x40, 0x9b, 0x06, 0xff, 0x02, 0xc6, 0x00, 0xbe, + 0x86, 0x17, 0x1e, 0xfc, 0x36, 0xf0, 0x08, 0x1c, + 0xea, 0x8c, 0xe3, 0x64, 0xc7, 0x49, 0x25, 0xf1, + 0xe0, 0x75, 0xff, 0x1b, 0xeb, 0x47, 0xff, 0x1b, + 0x6b, 0x47, 0xe0, 0x9d, 0x15, 0xc3, 0x60, 0x75, + 0xd8, 0x49, 0x04, 0xf0, 0x81, 0x1d, 0xe2, 0x8d, + 0x05, 0xe0, 0xe2, 0x63, 0x81, 0x1d, 0xdd, 0x47, + 0xe2, 0x8b, 0x0b, 0xc3, 0x00, 0x1d, 0x61, 0x8d, + 0x3c, 0x03, 0x60, 0x75, 0xd8, 0x49, 0x06, 0xf1, + 0xdf, 0x48, 0x61, 0x95, 0x16, 0xe0, 0x4e, 0xe8, + 0x12, 0xe8, 0x21, 0xc5, 0xa0, 0x73, 0xb0, 0x49, + 0x03, 0xf0, 0x31, 0x48, 0xa0, 0x9b, 0x0d, 0xe0, + 0xc0, 0x49, 0x0b, 0xf1, 0xe2, 0x63, 0x7e, 0x1d, + 0xdd, 0x46, 0xe2, 0x8b, 0xe0, 0x75, 0x83, 0x1b, + 0xeb, 0x46, 0xfe, 0x1b, 0x6b, 0x46, 0xe0, 0x9d, + 0xe4, 0x49, 0x11, 0xf0, 0x10, 0x1d, 0xea, 0x8d, + 0xe3, 0x64, 0xc6, 0x49, 0x09, 0xf1, 0x07, 0xc5, + 0xa0, 0x73, 0xb1, 0x48, 0xa0, 0x9b, 0x02, 0xc5, + 0x00, 0xbd, 0xe6, 0x04, 0xa0, 0xd1, 0x02, 0xc5, + 0x00, 0xbd, 0xfe, 0x04, 0x02, 0xc5, 0x00, 0xbd, + 0x30, 0x05, 0x00, 0x00 }; + +static const u16 r8152b_ram_code1[] = { + 0x9700, 0x7fe0, 0x4c00, 0x4007, 0x4400, 0x4800, 0x7c1f, 0x4c00, + 0x5310, 0x6000, 0x7c07, 0x6800, 0x673e, 0x0000, 0x0000, 0x571f, + 0x5ffb, 0xaa05, 0x5b58, 0x7d80, 0x6100, 0x3019, 0x5b64, 0x7d80, + 0x6080, 0xa6f8, 0xdcdb, 0x0015, 0xb915, 0xb511, 0xd16b, 0x000f, + 0xb40f, 0xd06b, 0x000d, 0xb206, 0x7c01, 0x5800, 0x7c04, 0x5c00, + 0x3011, 0x7c01, 0x5801, 0x7c04, 0x5c04, 0x3019, 0x30a5, 0x3127, + 0x31d5, 0x7fe0, 0x4c60, 0x7c07, 0x6803, 0x7d00, 0x6900, 0x65a0, + 0x0000, 0x0000, 0xaf03, 0x6015, 0x303e, 0x6017, 0x57e0, 0x580c, + 0x588c, 0x7fdd, 0x5fa2, 0x4827, 0x7c1f, 0x4c00, 0x7c1f, 0x4c10, + 0x8400, 0x7c30, 0x6020, 0x48bf, 0x7c1f, 0x4c00, 0x7c1f, 0x4c01, + 0x7c07, 0x6803, 0xb806, 0x7c08, 0x6800, 0x0000, 0x0000, 0x305c, + 0x7c08, 0x6808, 0x0000, 0x0000, 0xae06, 0x7c02, 0x5c02, 0x0000, + 0x0000, 0x3067, 0x8e05, 0x7c02, 0x5c00, 0x0000, 0x0000, 0xad06, + 0x7c20, 0x5c20, 0x0000, 0x0000, 0x3072, 0x8d05, 0x7c20, 0x5c00, + 0x0000, 0x0000, 0xa008, 0x7c07, 0x6800, 0xb8db, 0x7c07, 0x6803, + 0xd9b3, 0x00d7, 0x7fe0, 0x4c80, 0x7c08, 0x6800, 0x0000, 0x0000, + 0x7c23, 0x5c23, 0x481d, 0x7c1f, 0x4c00, 0x7c1f, 0x4c02, 0x5310, + 0x81ff, 0x30f5, 0x7fe0, 0x4d00, 0x4832, 0x7c1f, 0x4c00, 0x7c1f, + 0x4c10, 0x7c08, 0x6000, 0xa49e, 0x7c07, 0x6800, 0xb89b, 0x7c07, + 0x6803, 0xd9b3, 0x00f9, 0x7fe0, 0x4d20, 0x7e00, 0x6200, 0x3001, + 0x7fe0, 0x4dc0, 0xd09d, 0x0002, 0xb4fe, 0x7fe0, 0x4d80, 0x7c04, + 0x6004, 0x7c07, 0x6802, 0x6728, 0x0000, 0x0000, 0x7c08, 0x6000, + 0x486c, 0x7c1f, 0x4c00, 0x7c1f, 0x4c01, 0x9503, 0x7e00, 0x6200, + 0x571f, 0x5fbb, 0xaa05, 0x5b58, 0x7d80, 0x6100, 0x30c2, 0x5b64, + 0x7d80, 0x6080, 0xcdab, 0x0063, 0xcd8d, 0x0061, 0xd96b, 0x005f, + 0xd0a0, 0x00d7, 0xcba0, 0x0003, 0x80ec, 0x30cf, 0x30dc, 0x7fe0, + 0x4ce0, 0x4832, 0x7c1f, 0x4c00, 0x7c1f, 0x4c08, 0x7c08, 0x6008, + 0x8300, 0xb902, 0x30a5, 0x308a, 0x7fe0, 0x4da0, 0x65a8, 0x0000, + 0x0000, 0x56a0, 0x590c, 0x7ffd, 0x5fa2, 0xae06, 0x7c02, 0x5c02, + 0x0000, 0x0000, 0x30f0, 0x8e05, 0x7c02, 0x5c00, 0x0000, 0x0000, + 0xcba4, 0x0004, 0xcd8d, 0x0002, 0x80f1, 0x7fe0, 0x4ca0, 0x7c08, + 0x6408, 0x0000, 0x0000, 0x7d00, 0x6800, 0xb603, 0x7c10, 0x6010, + 0x7d1f, 0x551f, 0x5fb3, 0xaa07, 0x7c80, 0x5800, 0x5b58, 0x7d80, + 0x6100, 0x310f, 0x7c80, 0x5800, 0x5b64, 0x7d80, 0x6080, 0x4827, + 0x7c1f, 0x4c00, 0x7c1f, 0x4c10, 0x8400, 0x7c10, 0x6000, 0x7fe0, + 0x4cc0, 0x5fbb, 0x4824, 0x7c1f, 0x4c00, 0x7c1f, 0x4c04, 0x8200, + 0x7ce0, 0x5400, 0x6728, 0x0000, 0x0000, 0x30cf, 0x3001, 0x7fe0, + 0x4e00, 0x4007, 0x4400, 0x5310, 0x7c07, 0x6800, 0x673e, 0x0000, + 0x0000, 0x570f, 0x5fff, 0xaa05, 0x585b, 0x7d80, 0x6100, 0x313b, + 0x5867, 0x7d80, 0x6080, 0x9403, 0x7e00, 0x6200, 0xcda3, 0x00e7, + 0xcd85, 0x00e5, 0xd96b, 0x00e3, 0x96e3, 0x7c07, 0x6800, 0x673e, + 0x0000, 0x0000, 0x7fe0, 0x4e20, 0x96db, 0x8b04, 0x7c08, 0x5008, + 0xab03, 0x7c08, 0x5000, 0x7c07, 0x6801, 0x677e, 0x0000, 0x0000, + 0xdb7c, 0x00ec, 0x0000, 0x7fe1, 0x4f40, 0x4837, 0x4418, 0x41c7, + 0x7fe0, 0x4e40, 0x7c40, 0x5400, 0x7c1f, 0x4c01, 0x7c1f, 0x4c01, + 0x8fbf, 0xd2a0, 0x004b, 0x9204, 0xa042, 0x3168, 0x3127, 0x7fe1, + 0x4f60, 0x489c, 0x4628, 0x7fe0, 0x4e60, 0x7e28, 0x4628, 0x7c40, + 0x5400, 0x7c01, 0x5800, 0x7c04, 0x5c00, 0x41e8, 0x7c1f, 0x4c01, + 0x7c1f, 0x4c01, 0x8fa5, 0xb241, 0xa02a, 0x3182, 0x7fe0, 0x4ea0, + 0x7c02, 0x4402, 0x4448, 0x4894, 0x7c1f, 0x4c01, 0x7c1f, 0x4c03, + 0x4824, 0x7c1f, 0x4c07, 0x41ef, 0x41ff, 0x4891, 0x7c1f, 0x4c07, + 0x7c1f, 0x4c17, 0x8400, 0x8ef8, 0x41c7, 0x8f8a, 0x92d5, 0xa10f, + 0xd480, 0x0008, 0xd580, 0x00b8, 0xa202, 0x319d, 0x7c04, 0x4404, + 0x319d, 0xd484, 0x00f3, 0xd484, 0x00f1, 0x3127, 0x7fe0, 0x4ee0, + 0x7c40, 0x5400, 0x4488, 0x41cf, 0x3127, 0x7fe0, 0x4ec0, 0x48f3, + 0x7c1f, 0x4c01, 0x7c1f, 0x4c09, 0x4508, 0x41c7, 0x8fb0, 0xd218, + 0x00ae, 0xd2a4, 0x009e, 0x31be, 0x7fe0, 0x4e80, 0x4832, 0x7c1f, + 0x4c01, 0x7c1f, 0x4c11, 0x4428, 0x7c40, 0x5440, 0x7c01, 0x5801, + 0x7c04, 0x5c04, 0x41e8, 0xa4b3, 0x31d3, 0x7fe0, 0x4f20, 0x7c07, + 0x6800, 0x673e, 0x0000, 0x0000, 0x570f, 0x5fff, 0xaa04, 0x585b, + 0x6100, 0x31e4, 0x5867, 0x6080, 0xbcf1, 0x3001 }; + +static const u16 r8152b_pla_patch_a_bp[] = { + 0xfc26, 0x8000, 0xfc28, 0x170b, 0xfc2a, 0x01e1, 0xfc2c, 0x0989, + 0xfc2e, 0x1349, 0xfc30, 0x01b7, 0xfc32, 0x061d, 0xe422, 0x0020, + 0xe420, 0x0018, 0xfc34, 0x1785, 0xfc36, 0x047b }; + +static const u8 r8152b_pla_patch_a2[] = { + 0x08, 0xe0, 0x1a, 0xe0, 0xf2, 0xe0, 0xfa, 0xe0, + 0x32, 0xe1, 0x34, 0xe1, 0x36, 0xe1, 0x38, 0xe1, + 0x2c, 0x75, 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13, + 0x0b, 0xf0, 0x03, 0x13, 0x09, 0xf0, 0x02, 0x13, + 0x07, 0xf0, 0x01, 0x13, 0x05, 0xf0, 0x08, 0x13, + 0x03, 0xf0, 0x04, 0xc3, 0x00, 0xbb, 0x03, 0xc3, + 0x00, 0xbb, 0xd2, 0x17, 0xbc, 0x17, 0x14, 0xc2, + 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b, 0x11, 0xc2, + 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0, 0xbf, 0x49, + 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd, 0xb1, 0x49, + 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b, 0x02, 0xc2, + 0x00, 0xba, 0x4e, 0x19, 0x00, 0xa0, 0x1e, 0xfc, + 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8, 0x00, 0x80, + 0x00, 0x60, 0x2c, 0x75, 0xd4, 0x49, 0x12, 0xf1, + 0x29, 0xe0, 0xf8, 0xc2, 0x46, 0x71, 0xf7, 0xc2, + 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1, 0xf5, 0xc7, + 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30, 0x26, 0x62, + 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72, 0xa0, 0x49, + 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f, 0x97, 0x30, + 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75, 0x32, 0xc3, + 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1, 0xdc, 0x21, + 0xbc, 0x25, 0x27, 0xc6, 0xc0, 0x77, 0x04, 0x13, + 0x18, 0xf0, 0x03, 0x13, 0x19, 0xf0, 0x02, 0x13, + 0x1a, 0xf0, 0x01, 0x13, 0x1b, 0xf0, 0xd4, 0x49, + 0x03, 0xf1, 0x1c, 0xc5, 0x00, 0xbd, 0xcd, 0xc6, + 0xc6, 0x67, 0x2e, 0x75, 0xd7, 0x22, 0xdd, 0x26, + 0x05, 0x15, 0x1a, 0xf0, 0x14, 0xc6, 0x00, 0xbe, + 0x13, 0xc5, 0x00, 0xbd, 0x12, 0xc5, 0x00, 0xbd, + 0xf1, 0x49, 0xfb, 0xf1, 0xef, 0xe7, 0xf4, 0x49, + 0xfa, 0xf1, 0xec, 0xe7, 0xf3, 0x49, 0xf7, 0xf1, + 0xe9, 0xe7, 0xf2, 0x49, 0xf4, 0xf1, 0xe6, 0xe7, + 0xb6, 0xc0, 0xf6, 0x14, 0x36, 0x14, 0x62, 0x14, + 0x86, 0x15, 0xa0, 0xd1, 0x00, 0x00, 0xc0, 0x75, + 0xd0, 0x49, 0x46, 0xf0, 0x26, 0x72, 0xa7, 0x49, + 0x43, 0xf0, 0x22, 0x72, 0x25, 0x25, 0x20, 0x1f, + 0x97, 0x30, 0x91, 0x30, 0x40, 0x73, 0xf3, 0xc4, + 0x1c, 0x40, 0x04, 0xf0, 0xd7, 0x49, 0x05, 0xf1, + 0x37, 0xe0, 0x53, 0x48, 0xc0, 0x9d, 0x08, 0x02, + 0x40, 0x66, 0x64, 0x27, 0x06, 0x16, 0x30, 0xf1, + 0x46, 0x63, 0x3b, 0x13, 0x2d, 0xf1, 0x34, 0x9b, + 0x18, 0x1b, 0x93, 0x30, 0x2b, 0xc3, 0x10, 0x1c, + 0x2b, 0xe8, 0x01, 0x14, 0x25, 0xf1, 0x00, 0x1d, + 0x26, 0x1a, 0x8a, 0x30, 0x22, 0x73, 0xb5, 0x25, + 0x0e, 0x0b, 0x00, 0x1c, 0x2c, 0xe8, 0x1f, 0xc7, + 0x27, 0x40, 0x1a, 0xf1, 0x38, 0xe8, 0x32, 0x1f, + 0x8f, 0x30, 0x08, 0x1b, 0x24, 0xe8, 0x36, 0x72, + 0x46, 0x77, 0x00, 0x17, 0x0d, 0xf0, 0x13, 0xc3, + 0x1f, 0x40, 0x03, 0xf1, 0x00, 0x1f, 0x46, 0x9f, + 0x44, 0x77, 0x9f, 0x44, 0x5f, 0x44, 0x17, 0xe8, + 0x0a, 0xc7, 0x27, 0x40, 0x05, 0xf1, 0x02, 0xc3, + 0x00, 0xbb, 0x1c, 0x1b, 0xd2, 0x1a, 0xff, 0xc7, + 0x00, 0xbf, 0xb8, 0xcd, 0xff, 0xff, 0x02, 0x0c, + 0x54, 0xa5, 0xdc, 0xa5, 0x2f, 0x40, 0x05, 0xf1, + 0x00, 0x14, 0xfa, 0xf1, 0x01, 0x1c, 0x02, 0xe0, + 0x00, 0x1c, 0x80, 0xff, 0xb0, 0x49, 0x04, 0xf0, + 0x01, 0x0b, 0xd3, 0xa1, 0x03, 0xe0, 0x02, 0x0b, + 0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37, 0x02, 0x0b, + 0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37, 0x00, 0x13, + 0xfb, 0xf1, 0x80, 0xff, 0x22, 0x73, 0xb5, 0x25, + 0x18, 0x1e, 0xde, 0x30, 0xd9, 0x30, 0x64, 0x72, + 0x11, 0x1e, 0x68, 0x23, 0x16, 0x31, 0x80, 0xff, + 0x08, 0xc2, 0x40, 0x73, 0x3a, 0x48, 0x40, 0x9b, + 0x06, 0xff, 0x02, 0xc6, 0x00, 0xbe, 0x4e, 0x18, + 0x1e, 0xfc, 0x33, 0xc5, 0xa0, 0x74, 0xc0, 0x49, + 0x1f, 0xf0, 0x30, 0xc5, 0xa0, 0x73, 0x00, 0x13, + 0x04, 0xf1, 0xa2, 0x73, 0x00, 0x13, 0x14, 0xf0, + 0x28, 0xc5, 0xa0, 0x74, 0xc8, 0x49, 0x1b, 0xf1, + 0x26, 0xc5, 0xa0, 0x76, 0xa2, 0x74, 0x01, 0x06, + 0x20, 0x37, 0xa0, 0x9e, 0xa2, 0x9c, 0x1e, 0xc5, + 0xa2, 0x73, 0x23, 0x40, 0x10, 0xf8, 0x04, 0xf3, + 0xa0, 0x73, 0x33, 0x40, 0x0c, 0xf8, 0x15, 0xc5, + 0xa0, 0x74, 0x41, 0x48, 0xa0, 0x9c, 0x14, 0xc5, + 0xa0, 0x76, 0x62, 0x48, 0xe0, 0x48, 0xa0, 0x9e, + 0x10, 0xc6, 0x00, 0xbe, 0x0a, 0xc5, 0xa0, 0x74, + 0x48, 0x48, 0xa0, 0x9c, 0x0b, 0xc5, 0x20, 0x1e, + 0xa0, 0x9e, 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7, + 0xbc, 0xc0, 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4, + 0x22, 0x02, 0xf0, 0xc0, 0x02, 0xc6, 0x00, 0xbe, + 0x00, 0x00, 0x02, 0xc6, 0x00, 0xbe, 0x00, 0x00, + 0x02, 0xc6, 0x00, 0xbe, 0x00, 0x00, 0x02, 0xc6, + 0x00, 0xbe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + +static const u16 r8152b_pla_patch_a2_bp[] = { + 0xfc26, 0x8000, 0xfc28, 0x17a5, 0xfc2a, 0x13ad, + 0xfc2c, 0x184d, 0xfc2e, 0x01e1 }; + +static const u16 r8153_ram_code_a[] = { + 0xE86C, 0xA000, 0xB436, 0xB820, 0xB438, 0x0290, 0xB436, 0xA012, + 0xB438, 0x0000, 0xB436, 0xA014, 0xB438, 0x2c04, 0xB438, 0x2c18, + 0xB438, 0x2c45, 0xB438, 0x2c45, 0xB438, 0xd502, 0xB438, 0x8301, + 0xB438, 0x8306, 0xB438, 0xd500, 0xB438, 0x8208, 0xB438, 0xd501, + 0xB438, 0xe018, 0xB438, 0x0308, 0xB438, 0x60f2, 0xB438, 0x8404, + 0xB438, 0x607d, 0xB438, 0xc117, 0xB438, 0x2c16, 0xB438, 0xc116, + 0xB438, 0x2c16, 0xB438, 0x607d, 0xB438, 0xc117, 0xB438, 0xa404, + 0xB438, 0xd500, 0xB438, 0x0800, 0xB438, 0xd501, 0xB438, 0x62d2, + 0xB438, 0x615d, 0xB438, 0xc115, 0xB438, 0xa404, 0xB438, 0xc307, + 0xB438, 0xd502, 0xB438, 0x8301, 0xB438, 0x8306, 0xB438, 0xd500, + 0xB438, 0x8208, 0xB438, 0x2c42, 0xB438, 0xc114, 0xB438, 0x8404, + 0xB438, 0xc317, 0xB438, 0xd701, 0xB438, 0x435d, 0xB438, 0xd500, + 0xB438, 0xa208, 0xB438, 0xd502, 0xB438, 0xa306, 0xB438, 0xa301, + 0xB438, 0x2c42, 0xB438, 0x8404, 0xB438, 0x613d, 0xB438, 0xc115, + 0xB438, 0xc307, 0xB438, 0xd502, 0xB438, 0x8301, 0xB438, 0x8306, + 0xB438, 0xd500, 0xB438, 0x8208, 0xB438, 0x2c42, 0xB438, 0xc114, + 0xB438, 0xc317, 0xB438, 0xd701, 0xB438, 0x40dd, 0xB438, 0xd500, + 0xB438, 0xa208, 0xB438, 0xd502, 0xB438, 0xa306, 0xB438, 0xa301, + 0xB438, 0xd500, 0xB438, 0xd702, 0xB438, 0x0800, 0xB436, 0xA01A, + 0xB438, 0x0000, 0xB436, 0xA006, 0xB438, 0x0fff, 0xB436, 0xA004, + 0xB438, 0x0fff, 0xB436, 0xA002, 0xB438, 0x05a3, 0xB436, 0xA000, + 0xB438, 0x3591, 0xB436, 0xB820, 0xB438, 0x0210 }; + +static const u8 r8153_usb_patch_c[] = { + 0x08, 0xe0, 0x0a, 0xe0, 0x14, 0xe0, 0x58, 0xe0, + 0x64, 0xe0, 0x79, 0xe0, 0xab, 0xe0, 0xb6, 0xe0, + 0x02, 0xc5, 0x00, 0xbd, 0x38, 0x3b, 0xdb, 0x49, + 0x04, 0xf1, 0x06, 0xc3, 0x00, 0xbb, 0x5a, 0x02, + 0x05, 0xc4, 0x03, 0xc3, 0x00, 0xbb, 0xa4, 0x04, + 0x7e, 0x02, 0x30, 0xd4, 0x65, 0xc6, 0x66, 0x61, + 0x92, 0x49, 0x12, 0xf1, 0x3e, 0xc0, 0x02, 0x61, + 0x97, 0x49, 0x05, 0xf0, 0x3c, 0xc0, 0x00, 0x61, + 0x90, 0x49, 0x0a, 0xf1, 0xca, 0x63, 0xb0, 0x49, + 0x09, 0xf1, 0xb1, 0x49, 0x05, 0xf0, 0x32, 0xc0, + 0x00, 0x71, 0x9e, 0x49, 0x03, 0xf1, 0xb0, 0x48, + 0x05, 0xe0, 0x30, 0x48, 0xda, 0x61, 0x10, 0x48, + 0xda, 0x89, 0x4a, 0xc6, 0xc0, 0x60, 0x85, 0x49, + 0x03, 0xf0, 0x31, 0x48, 0x04, 0xe0, 0xb1, 0x48, + 0xb2, 0x48, 0x0f, 0xe0, 0x30, 0x18, 0x1b, 0xc1, + 0x0f, 0xe8, 0x1a, 0xc6, 0xc7, 0x65, 0xd0, 0x49, + 0x05, 0xf0, 0x32, 0x48, 0x02, 0xc2, 0x00, 0xba, + 0x3e, 0x16, 0x02, 0xc2, 0x00, 0xba, 0x48, 0x16, + 0x02, 0xc2, 0x00, 0xba, 0x4a, 0x16, 0x02, 0xb4, + 0x09, 0xc2, 0x40, 0x99, 0x0e, 0x48, 0x42, 0x98, + 0x42, 0x70, 0x8e, 0x49, 0xfe, 0xf1, 0x02, 0xb0, + 0x80, 0xff, 0xc0, 0xd4, 0xe4, 0x40, 0x20, 0xd4, + 0xca, 0xcf, 0x00, 0xcf, 0x3c, 0xe4, 0x0c, 0xc0, + 0x00, 0x63, 0xb5, 0x49, 0x09, 0xc0, 0x30, 0x18, + 0x06, 0xc1, 0xea, 0xef, 0xf5, 0xc7, 0x02, 0xc0, + 0x00, 0xb8, 0xd0, 0x10, 0xe4, 0x4b, 0x00, 0xd8, + 0x14, 0xc3, 0x60, 0x61, 0x90, 0x49, 0x06, 0xf0, + 0x11, 0xc3, 0x70, 0x61, 0x12, 0x48, 0x70, 0x89, + 0x08, 0xe0, 0x0a, 0xc6, 0xd4, 0x61, 0x93, 0x48, + 0xd4, 0x89, 0x02, 0xc1, 0x00, 0xb9, 0x72, 0x17, + 0x02, 0xc1, 0x00, 0xb9, 0x9c, 0x15, 0x00, 0xd8, + 0xef, 0xcf, 0x20, 0xd4, 0x30, 0x18, 0xe7, 0xc1, + 0xcb, 0xef, 0x2b, 0xc5, 0xa0, 0x77, 0x00, 0x1c, + 0xa0, 0x9c, 0x28, 0xc5, 0xa0, 0x64, 0xc0, 0x48, + 0xc1, 0x48, 0xc2, 0x48, 0xa0, 0x8c, 0xb1, 0x64, + 0xc0, 0x48, 0xb1, 0x8c, 0x20, 0xc5, 0xa0, 0x64, + 0x40, 0x48, 0x41, 0x48, 0xc2, 0x48, 0xa0, 0x8c, + 0x19, 0xc5, 0xa4, 0x64, 0x44, 0x48, 0xa4, 0x8c, + 0xb1, 0x64, 0x40, 0x48, 0xb1, 0x8c, 0x14, 0xc4, + 0x80, 0x73, 0x13, 0xc4, 0x82, 0x9b, 0x11, 0x1b, + 0x80, 0x9b, 0x0c, 0xc5, 0xa0, 0x64, 0x40, 0x48, + 0x41, 0x48, 0x42, 0x48, 0xa0, 0x8c, 0x05, 0xc5, + 0xa0, 0x9f, 0x02, 0xc5, 0x00, 0xbd, 0x6c, 0x3a, + 0x1e, 0xfc, 0x10, 0xd8, 0x86, 0xd4, 0xf8, 0xcb, + 0x20, 0xe4, 0x0a, 0xc0, 0x16, 0x61, 0x91, 0x48, + 0x16, 0x89, 0x07, 0xc0, 0x11, 0x19, 0x0c, 0x89, + 0x02, 0xc1, 0x00, 0xb9, 0x02, 0x06, 0x00, 0xd4, + 0x40, 0xb4, 0xfe, 0xc0, 0x16, 0x61, 0x91, 0x48, + 0x16, 0x89, 0xfb, 0xc0, 0x11, 0x19, 0x0c, 0x89, + 0x02, 0xc1, 0x00, 0xb9, 0xd2, 0x05, 0x00, 0x00 }; + +static const u16 r8153_usb_patch_c_bp[] = { + 0xfc26, 0xa000, 0xfc28, 0x3b34, 0xfc2a, 0x027c, 0xfc2c, 0x15de, + 0xfc2e, 0x10ce, 0xfc30, 0x1adc, 0xfc32, 0x3a28, 0xfc34, 0x05f8, + 0xfc36, 0x05c8, 0xfc38, 0x00f3 }; + +static const u8 r8153_pla_patch_c[] = { + 0x5d, 0xe0, 0x07, 0xe0, 0x0f, 0xe0, 0x5a, 0xe0, + 0x59, 0xe0, 0x1f, 0xe0, 0x57, 0xe0, 0x3e, 0xe1, + 0x08, 0xc2, 0x40, 0x73, 0x3a, 0x48, 0x40, 0x9b, + 0x06, 0xff, 0x02, 0xc6, 0x00, 0xbe, 0xcc, 0x17, + 0x1e, 0xfc, 0x2c, 0x75, 0xdc, 0x21, 0xbc, 0x25, + 0x04, 0x13, 0x0b, 0xf0, 0x03, 0x13, 0x09, 0xf0, + 0x02, 0x13, 0x07, 0xf0, 0x01, 0x13, 0x05, 0xf0, + 0x08, 0x13, 0x03, 0xf0, 0x04, 0xc3, 0x00, 0xbb, + 0x03, 0xc3, 0x00, 0xbb, 0x50, 0x17, 0x3a, 0x17, + 0x33, 0xc5, 0xa0, 0x74, 0xc0, 0x49, 0x1f, 0xf0, + 0x30, 0xc5, 0xa0, 0x73, 0x00, 0x13, 0x04, 0xf1, + 0xa2, 0x73, 0x00, 0x13, 0x14, 0xf0, 0x28, 0xc5, + 0xa0, 0x74, 0xc8, 0x49, 0x1b, 0xf1, 0x26, 0xc5, + 0xa0, 0x76, 0xa2, 0x74, 0x01, 0x06, 0x20, 0x37, + 0xa0, 0x9e, 0xa2, 0x9c, 0x1e, 0xc5, 0xa2, 0x73, + 0x23, 0x40, 0x10, 0xf8, 0x04, 0xf3, 0xa0, 0x73, + 0x33, 0x40, 0x0c, 0xf8, 0x15, 0xc5, 0xa0, 0x74, + 0x41, 0x48, 0xa0, 0x9c, 0x14, 0xc5, 0xa0, 0x76, + 0x62, 0x48, 0xe0, 0x48, 0xa0, 0x9e, 0x10, 0xc6, + 0x00, 0xbe, 0x0a, 0xc5, 0xa0, 0x74, 0x48, 0x48, + 0xa0, 0x9c, 0x0b, 0xc5, 0x20, 0x1e, 0xa0, 0x9e, + 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7, 0xbc, 0xc0, + 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4, 0xfa, 0x01, + 0xf0, 0xc0, 0x18, 0x89, 0x74, 0xc0, 0xcd, 0xe8, + 0x80, 0x76, 0x00, 0x1d, 0x6e, 0xc3, 0x66, 0x62, + 0xa0, 0x49, 0x06, 0xf0, 0x64, 0xc0, 0x02, 0x71, + 0x60, 0x99, 0x62, 0xc1, 0x03, 0xe0, 0x5f, 0xc0, + 0x60, 0xc1, 0x02, 0x99, 0x00, 0x61, 0x0f, 0x1b, + 0x59, 0x41, 0x03, 0x13, 0x18, 0xf1, 0xe4, 0x49, + 0x20, 0xf1, 0xe5, 0x49, 0x1e, 0xf0, 0x59, 0xc6, + 0xd0, 0x73, 0xb7, 0x49, 0x08, 0xf0, 0x01, 0x0b, + 0x80, 0x13, 0x03, 0xf0, 0xd0, 0x8b, 0x03, 0xe0, + 0x3f, 0x48, 0xd0, 0x9b, 0x51, 0xc0, 0x10, 0x1a, + 0x84, 0x1b, 0xb1, 0xe8, 0x4b, 0xc2, 0x40, 0x63, + 0x30, 0x48, 0x0a, 0xe0, 0xe5, 0x49, 0x09, 0xf0, + 0x47, 0xc0, 0x00, 0x1a, 0x84, 0x1b, 0xa7, 0xe8, + 0x41, 0xc2, 0x40, 0x63, 0xb0, 0x48, 0x40, 0x8b, + 0x67, 0x11, 0x3f, 0xf1, 0x69, 0x33, 0x32, 0xc0, + 0x28, 0x40, 0xd2, 0xf1, 0x33, 0xc0, 0x00, 0x19, + 0x81, 0x1b, 0x99, 0xe8, 0x30, 0xc0, 0x04, 0x1a, + 0x84, 0x1b, 0x95, 0xe8, 0x8a, 0xe8, 0xa3, 0x49, + 0xfe, 0xf0, 0x2a, 0xc0, 0x86, 0xe8, 0xa1, 0x48, + 0x84, 0x1b, 0x8d, 0xe8, 0x00, 0x1d, 0x69, 0x33, + 0x00, 0x1e, 0x01, 0x06, 0xff, 0x18, 0x30, 0x40, + 0xfd, 0xf1, 0x1f, 0xc0, 0x00, 0x76, 0x2e, 0x40, + 0xf7, 0xf1, 0x21, 0x48, 0x19, 0xc0, 0x84, 0x1b, + 0x7e, 0xe8, 0x74, 0x08, 0x72, 0xe8, 0xa1, 0x49, + 0xfd, 0xf0, 0x11, 0xc0, 0x00, 0x1a, 0x84, 0x1b, + 0x76, 0xe8, 0x6b, 0xe8, 0xa5, 0x49, 0xfe, 0xf0, + 0x09, 0xc0, 0x01, 0x19, 0x81, 0x1b, 0x6f, 0xe8, + 0x5a, 0xe0, 0xb8, 0x0b, 0x50, 0xe8, 0x83, 0x00, + 0x82, 0x00, 0x20, 0xb4, 0x10, 0xd8, 0x84, 0xd4, + 0x88, 0xd3, 0x10, 0xe0, 0x00, 0xd8, 0x24, 0xd4, + 0xf9, 0xc0, 0x57, 0xe8, 0x48, 0x33, 0xf3, 0xc0, + 0x00, 0x61, 0x6a, 0xc0, 0x47, 0x11, 0x03, 0xf0, + 0x57, 0x11, 0x05, 0xf1, 0x00, 0x61, 0x17, 0x48, + 0x00, 0x89, 0x41, 0xe0, 0x9c, 0x20, 0x9c, 0x24, + 0xd0, 0x49, 0x09, 0xf0, 0x04, 0x11, 0x07, 0xf1, + 0x00, 0x61, 0x97, 0x49, 0x38, 0xf0, 0x97, 0x48, + 0x00, 0x89, 0x2b, 0xe0, 0x00, 0x11, 0x05, 0xf1, + 0x00, 0x61, 0x92, 0x48, 0x00, 0x89, 0x2f, 0xe0, + 0x06, 0x11, 0x05, 0xf1, 0x00, 0x61, 0x11, 0x48, + 0x00, 0x89, 0x29, 0xe0, 0x05, 0x11, 0x0f, 0xf1, + 0x00, 0x61, 0x93, 0x49, 0x1a, 0xf1, 0x91, 0x49, + 0x0a, 0xf0, 0x91, 0x48, 0x00, 0x89, 0x0f, 0xe0, + 0xc6, 0xc0, 0x00, 0x61, 0x98, 0x20, 0x98, 0x24, + 0x25, 0x11, 0x80, 0xff, 0xfa, 0xef, 0x17, 0xf1, + 0x38, 0xc0, 0x1f, 0xe8, 0x95, 0x49, 0x13, 0xf0, + 0xf4, 0xef, 0x11, 0xf1, 0x31, 0xc0, 0x00, 0x61, + 0x92, 0x49, 0x0d, 0xf1, 0x12, 0x48, 0x00, 0x89, + 0x29, 0xc0, 0x00, 0x19, 0x00, 0x89, 0x27, 0xc0, + 0x01, 0x89, 0x23, 0xc0, 0x0e, 0xe8, 0x12, 0x48, + 0x81, 0x1b, 0x15, 0xe8, 0xae, 0xc3, 0x66, 0x62, + 0xa0, 0x49, 0x04, 0xf0, 0x64, 0x71, 0xa3, 0xc0, + 0x02, 0x99, 0x02, 0xc0, 0x00, 0xb8, 0xd6, 0x07, + 0x13, 0xc4, 0x84, 0x98, 0x00, 0x1b, 0x86, 0x8b, + 0x86, 0x73, 0xbf, 0x49, 0xfe, 0xf1, 0x80, 0x71, + 0x82, 0x72, 0x80, 0xff, 0x09, 0xc4, 0x84, 0x98, + 0x80, 0x99, 0x82, 0x9a, 0x86, 0x8b, 0x86, 0x73, + 0xbf, 0x49, 0xfe, 0xf1, 0x80, 0xff, 0x08, 0xea, + 0x30, 0xd4, 0x10, 0xc0, 0x12, 0xe8, 0x8a, 0xd3, + 0x00, 0xd8, 0x02, 0xc6, 0x00, 0xbe, 0xe0, 0x08 }; + +static const u16 r8153_pla_patch_c_bp[] = { + 0xfc26, 0x8000, 0xfc28, 0x1306, 0xfc2a, 0x17ca, 0xfc2c, 0x171e, + 0xfc2e, 0x0000, 0xfc30, 0x0000, 0xfc32, 0x01b4, 0xfc34, 0x07d4, + 0xfc36, 0x0894, 0xfc38, 0x00e6 }; + +static const u16 r8153_ram_code_bc[] = { + 0xB436, 0xB820, 0xB438, 0x0290, 0xB436, 0xA012, 0xB438, 0x0000, + 0xB436, 0xA014, 0xB438, 0x2c04, 0xB438, 0x2c07, 0xB438, 0x2c0a, + 0xB438, 0x2c0d, 0xB438, 0xa240, 0xB438, 0xa104, 0xB438, 0x292d, + 0xB438, 0x8620, 0xB438, 0xa480, 0xB438, 0x2a2c, 0xB438, 0x8480, + 0xB438, 0xa101, 0xB438, 0x2a36, 0xB438, 0xd056, 0xB438, 0x2223, + 0xB436, 0xA01A, 0xB438, 0x0000, 0xB436, 0xA006, 0xB438, 0x0222, + 0xB436, 0xA004, 0xB438, 0x0a35, 0xB436, 0xA002, 0xB438, 0x0a2b, + 0xB436, 0xA000, 0xB438, 0xf92c, 0xB436, 0xB820, 0xB438, 0x0210 }; + +static const u8 r8153_usb_patch_b[] = { + 0x08, 0xe0, 0x0f, 0xe0, 0x18, 0xe0, 0x24, 0xe0, + 0x26, 0xe0, 0x3a, 0xe0, 0x84, 0xe0, 0x9c, 0xe0, + 0xc2, 0x49, 0x04, 0xf0, 0x02, 0xc0, 0x00, 0xb8, + 0x14, 0x18, 0x02, 0xc0, 0x00, 0xb8, 0x2e, 0x18, + 0x06, 0x89, 0x08, 0xc0, 0x0c, 0x61, 0x92, 0x48, + 0x93, 0x48, 0x0c, 0x89, 0x02, 0xc0, 0x00, 0xb8, + 0x08, 0x05, 0x40, 0xb4, 0x16, 0x89, 0x6d, 0xc0, + 0x00, 0x61, 0x95, 0x49, 0x06, 0xf0, 0xfa, 0xc0, + 0x0c, 0x61, 0x92, 0x48, 0x93, 0x48, 0x0c, 0x89, + 0x02, 0xc0, 0x00, 0xb8, 0xe2, 0x04, 0x02, 0xc2, + 0x00, 0xba, 0xec, 0x11, 0x60, 0x60, 0x85, 0x49, + 0x0d, 0xf1, 0x11, 0xc6, 0xd2, 0x61, 0x91, 0x49, + 0xfd, 0xf0, 0x74, 0x60, 0x04, 0x48, 0x74, 0x88, + 0x08, 0xc6, 0x08, 0xc0, 0xc4, 0x98, 0x01, 0x18, + 0xc0, 0x88, 0x02, 0xc0, 0x00, 0xb8, 0x6e, 0x12, + 0x04, 0xe4, 0x0d, 0x00, 0x00, 0xd4, 0xd1, 0x49, + 0x3c, 0xf1, 0xd2, 0x49, 0x16, 0xf1, 0xd3, 0x49, + 0x18, 0xf1, 0xd4, 0x49, 0x19, 0xf1, 0xd5, 0x49, + 0x1a, 0xf1, 0xd6, 0x49, 0x1b, 0xf1, 0xd7, 0x49, + 0x1c, 0xf1, 0xd8, 0x49, 0x1d, 0xf1, 0xd9, 0x49, + 0x20, 0xf1, 0xda, 0x49, 0x23, 0xf1, 0xdb, 0x49, + 0x24, 0xf1, 0x02, 0xc4, 0x00, 0xbc, 0x20, 0x04, + 0xe5, 0x8e, 0x02, 0xc4, 0x00, 0xbc, 0x14, 0x02, + 0x02, 0xc4, 0x00, 0xbc, 0x16, 0x02, 0x02, 0xc4, + 0x00, 0xbc, 0x18, 0x02, 0x02, 0xc4, 0x00, 0xbc, + 0x1a, 0x02, 0x02, 0xc4, 0x00, 0xbc, 0x1c, 0x02, + 0x02, 0xc4, 0x00, 0xbc, 0x94, 0x02, 0x10, 0xc7, + 0xe0, 0x8e, 0x02, 0xc4, 0x00, 0xbc, 0x8a, 0x02, + 0x0b, 0xc7, 0xe4, 0x8e, 0x02, 0xc4, 0x00, 0xbc, + 0x88, 0x02, 0x02, 0xc4, 0x00, 0xbc, 0x6e, 0x02, + 0x02, 0xc4, 0x00, 0xbc, 0x5a, 0x02, 0x30, 0xe4, + 0x0c, 0xc3, 0x60, 0x64, 0xc5, 0x49, 0x04, 0xf1, + 0x74, 0x64, 0xc4, 0x48, 0x74, 0x8c, 0x06, 0xc3, + 0x64, 0x8e, 0x02, 0xc4, 0x00, 0xbc, 0x20, 0x04, + 0x00, 0xd8, 0x00, 0xe4, 0xb2, 0xc0, 0x00, 0x61, + 0x90, 0x49, 0x09, 0xf1, 0x8b, 0xc6, 0xca, 0x61, + 0x94, 0x49, 0x0e, 0xf1, 0xf6, 0xc6, 0xda, 0x60, + 0x81, 0x49, 0x0a, 0xf0, 0x65, 0x60, 0x03, 0x48, + 0x65, 0x88, 0xef, 0xc6, 0xdc, 0x60, 0x80, 0x48, + 0xdc, 0x88, 0x05, 0xc6, 0x00, 0xbe, 0x02, 0xc6, + 0x00, 0xbe, 0x36, 0x13, 0x4c, 0x17, 0x99, 0xc4, + 0x80, 0x65, 0xd0, 0x49, 0x04, 0xf1, 0xfa, 0x75, + 0x04, 0xc4, 0x00, 0xbc, 0x03, 0xc4, 0x00, 0xbc, + 0x9a, 0x00, 0xee, 0x01 }; + +static const u16 r8153_usb_patch_b_bp[] = { + 0xfc26, 0xa000, 0xfc28, 0x180c, 0xfc2a, 0x0506, 0xfc2c, 0x04E0, + 0xfc2e, 0x11E4, 0xfc30, 0x125C, 0xfc32, 0x0232, 0xfc34, 0x131E, + 0xfc36, 0x0098, 0xfc38, 0x00FF }; + +static const u8 r8153_pla_patch_b[] = { + 0x08, 0xe0, 0xea, 0xe0, 0xf2, 0xe0, 0x04, 0xe1, + 0x09, 0xe1, 0x0e, 0xe1, 0x46, 0xe1, 0xf7, 0xe1, + 0x14, 0xc2, 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b, + 0x11, 0xc2, 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0, + 0xbf, 0x49, 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd, + 0xb1, 0x49, 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b, + 0x02, 0xc2, 0x00, 0xba, 0x1a, 0x17, 0x00, 0xe0, + 0x1e, 0xfc, 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8, + 0x00, 0x80, 0x00, 0x20, 0x2c, 0x75, 0xd4, 0x49, + 0x12, 0xf1, 0x32, 0xe0, 0xf8, 0xc2, 0x46, 0x71, + 0xf7, 0xc2, 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1, + 0xf5, 0xc7, 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30, + 0x26, 0x62, 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72, + 0xa0, 0x49, 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f, + 0x97, 0x30, 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75, + 0x3c, 0xc3, 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1, + 0xdc, 0x21, 0xbc, 0x25, 0x30, 0xc6, 0xc0, 0x77, + 0x04, 0x13, 0x21, 0xf0, 0x03, 0x13, 0x22, 0xf0, + 0x02, 0x13, 0x23, 0xf0, 0x01, 0x13, 0x24, 0xf0, + 0x08, 0x13, 0x08, 0xf1, 0x2e, 0x73, 0xba, 0x21, + 0xbd, 0x25, 0x05, 0x13, 0x03, 0xf1, 0x24, 0xc5, + 0x00, 0xbd, 0xd4, 0x49, 0x03, 0xf1, 0x1c, 0xc5, + 0x00, 0xbd, 0xc4, 0xc6, 0xc6, 0x67, 0x2e, 0x75, + 0xd7, 0x22, 0xdd, 0x26, 0x05, 0x15, 0x1b, 0xf0, + 0x14, 0xc6, 0x00, 0xbe, 0x13, 0xc5, 0x00, 0xbd, + 0x12, 0xc5, 0x00, 0xbd, 0xf1, 0x49, 0xfb, 0xf1, + 0xef, 0xe7, 0xf4, 0x49, 0xfa, 0xf1, 0xec, 0xe7, + 0xf3, 0x49, 0xf7, 0xf1, 0xe9, 0xe7, 0xf2, 0x49, + 0xf4, 0xf1, 0xe6, 0xe7, 0xb6, 0xc0, 0x9e, 0x12, + 0xde, 0x11, 0x0a, 0x12, 0x3c, 0x13, 0x00, 0xa0, + 0xa0, 0xd1, 0x00, 0x00, 0xc0, 0x75, 0xd0, 0x49, + 0x46, 0xf0, 0x26, 0x72, 0xa7, 0x49, 0x43, 0xf0, + 0x22, 0x72, 0x25, 0x25, 0x20, 0x1f, 0x97, 0x30, + 0x91, 0x30, 0x40, 0x73, 0xf3, 0xc4, 0x1c, 0x40, + 0x04, 0xf0, 0xd7, 0x49, 0x05, 0xf1, 0x37, 0xe0, + 0x53, 0x48, 0xc0, 0x9d, 0x08, 0x02, 0x40, 0x66, + 0x64, 0x27, 0x06, 0x16, 0x30, 0xf1, 0x46, 0x63, + 0x3b, 0x13, 0x2d, 0xf1, 0x34, 0x9b, 0x18, 0x1b, + 0x93, 0x30, 0x2b, 0xc3, 0x10, 0x1c, 0x2b, 0xe8, + 0x01, 0x14, 0x25, 0xf1, 0x00, 0x1d, 0x26, 0x1a, + 0x8a, 0x30, 0x22, 0x73, 0xb5, 0x25, 0x0e, 0x0b, + 0x00, 0x1c, 0x2c, 0xe8, 0x1f, 0xc7, 0x27, 0x40, + 0x1a, 0xf1, 0x38, 0xe8, 0x32, 0x1f, 0x8f, 0x30, + 0x08, 0x1b, 0x24, 0xe8, 0x36, 0x72, 0x46, 0x77, + 0x00, 0x17, 0x0d, 0xf0, 0x13, 0xc3, 0x1f, 0x40, + 0x03, 0xf1, 0x00, 0x1f, 0x46, 0x9f, 0x44, 0x77, + 0x9f, 0x44, 0x5f, 0x44, 0x17, 0xe8, 0x0a, 0xc7, + 0x27, 0x40, 0x05, 0xf1, 0x02, 0xc3, 0x00, 0xbb, + 0xfa, 0x18, 0xb0, 0x18, 0xff, 0xc7, 0x00, 0xbf, + 0xb8, 0xcd, 0xff, 0xff, 0x02, 0x0c, 0x54, 0xa5, + 0xdc, 0xa5, 0x2f, 0x40, 0x05, 0xf1, 0x00, 0x14, + 0xfa, 0xf1, 0x01, 0x1c, 0x02, 0xe0, 0x00, 0x1c, + 0x80, 0xff, 0xb0, 0x49, 0x04, 0xf0, 0x01, 0x0b, + 0xd3, 0xa1, 0x03, 0xe0, 0x02, 0x0b, 0xd3, 0xa5, + 0x27, 0x31, 0x20, 0x37, 0x02, 0x0b, 0xd3, 0xa5, + 0x27, 0x31, 0x20, 0x37, 0x00, 0x13, 0xfb, 0xf1, + 0x80, 0xff, 0x22, 0x73, 0xb5, 0x25, 0x18, 0x1e, + 0xde, 0x30, 0xd9, 0x30, 0x64, 0x72, 0x11, 0x1e, + 0x68, 0x23, 0x16, 0x31, 0x80, 0xff, 0x08, 0xc2, + 0x40, 0x73, 0x3a, 0x48, 0x40, 0x9b, 0x06, 0xff, + 0x02, 0xc6, 0x00, 0xbe, 0x08, 0x16, 0x1e, 0xfc, + 0x2c, 0x75, 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13, + 0x0b, 0xf0, 0x03, 0x13, 0x09, 0xf0, 0x02, 0x13, + 0x07, 0xf0, 0x01, 0x13, 0x05, 0xf0, 0x08, 0x13, + 0x03, 0xf0, 0x04, 0xc3, 0x00, 0xbb, 0x03, 0xc3, + 0x00, 0xbb, 0x8c, 0x15, 0x76, 0x15, 0xa0, 0x64, + 0x40, 0x48, 0xa0, 0x8c, 0x02, 0xc4, 0x00, 0xbc, + 0x82, 0x00, 0xa0, 0x62, 0x21, 0x48, 0xa0, 0x8a, + 0x02, 0xc2, 0x00, 0xba, 0x40, 0x03, 0x33, 0xc5, + 0xa0, 0x74, 0xc0, 0x49, 0x1f, 0xf0, 0x30, 0xc5, + 0xa0, 0x73, 0x00, 0x13, 0x04, 0xf1, 0xa2, 0x73, + 0x00, 0x13, 0x14, 0xf0, 0x28, 0xc5, 0xa0, 0x74, + 0xc8, 0x49, 0x1b, 0xf1, 0x26, 0xc5, 0xa0, 0x76, + 0xa2, 0x74, 0x01, 0x06, 0x20, 0x37, 0xa0, 0x9e, + 0xa2, 0x9c, 0x1e, 0xc5, 0xa2, 0x73, 0x23, 0x40, + 0x10, 0xf8, 0x04, 0xf3, 0xa0, 0x73, 0x33, 0x40, + 0x0c, 0xf8, 0x15, 0xc5, 0xa0, 0x74, 0x41, 0x48, + 0xa0, 0x9c, 0x14, 0xc5, 0xa0, 0x76, 0x62, 0x48, + 0xe0, 0x48, 0xa0, 0x9e, 0x10, 0xc6, 0x00, 0xbe, + 0x0a, 0xc5, 0xa0, 0x74, 0x48, 0x48, 0xa0, 0x9c, + 0x0b, 0xc5, 0x20, 0x1e, 0xa0, 0x9e, 0xe5, 0x48, + 0xa0, 0x9e, 0xf0, 0xe7, 0xbc, 0xc0, 0xc8, 0xd2, + 0xcc, 0xd2, 0x28, 0xe4, 0xe6, 0x01, 0xf0, 0xc0, + 0x18, 0x89, 0x00, 0x1d, 0x3c, 0xc3, 0x64, 0x71, + 0x3c, 0xc0, 0x02, 0x99, 0x00, 0x61, 0x67, 0x11, + 0x3c, 0xf1, 0x69, 0x33, 0x35, 0xc0, 0x28, 0x40, + 0xf6, 0xf1, 0x34, 0xc0, 0x00, 0x19, 0x81, 0x1b, + 0x91, 0xe8, 0x31, 0xc0, 0x04, 0x1a, 0x84, 0x1b, + 0x8d, 0xe8, 0x82, 0xe8, 0xa3, 0x49, 0xfe, 0xf0, + 0x2b, 0xc0, 0x7e, 0xe8, 0xa1, 0x48, 0x28, 0xc0, + 0x84, 0x1b, 0x84, 0xe8, 0x00, 0x1d, 0x69, 0x33, + 0x00, 0x1e, 0x01, 0x06, 0xff, 0x18, 0x30, 0x40, + 0xfd, 0xf1, 0x19, 0xc0, 0x00, 0x76, 0x2e, 0x40, + 0xf7, 0xf1, 0x21, 0x48, 0x19, 0xc0, 0x84, 0x1b, + 0x75, 0xe8, 0x10, 0xc0, 0x69, 0xe8, 0xa1, 0x49, + 0xfd, 0xf0, 0x11, 0xc0, 0x00, 0x1a, 0x84, 0x1b, + 0x6d, 0xe8, 0x62, 0xe8, 0xa5, 0x49, 0xfe, 0xf0, + 0x09, 0xc0, 0x01, 0x19, 0x81, 0x1b, 0x66, 0xe8, + 0x54, 0xe0, 0x10, 0xd4, 0x88, 0xd3, 0xb8, 0x0b, + 0x50, 0xe8, 0x20, 0xb4, 0x10, 0xd8, 0x84, 0xd4, + 0xfd, 0xc0, 0x52, 0xe8, 0x48, 0x33, 0xf9, 0xc0, + 0x00, 0x61, 0x9c, 0x20, 0x9c, 0x24, 0xd0, 0x49, + 0x04, 0xf0, 0x04, 0x11, 0x02, 0xf1, 0x03, 0xe0, + 0x00, 0x11, 0x06, 0xf1, 0x5c, 0xc0, 0x00, 0x61, + 0x92, 0x48, 0x00, 0x89, 0x3a, 0xe0, 0x06, 0x11, + 0x06, 0xf1, 0x55, 0xc0, 0x00, 0x61, 0x11, 0x48, + 0x00, 0x89, 0x33, 0xe0, 0x05, 0x11, 0x08, 0xf1, + 0x4e, 0xc0, 0x00, 0x61, 0x91, 0x49, 0x04, 0xf0, + 0x91, 0x48, 0x00, 0x89, 0x11, 0xe0, 0xd9, 0xc0, + 0x00, 0x61, 0x98, 0x20, 0x98, 0x24, 0x25, 0x11, + 0x24, 0xf1, 0x44, 0xc0, 0x29, 0xe8, 0x95, 0x49, + 0x20, 0xf0, 0xcf, 0xc0, 0x00, 0x61, 0x98, 0x20, + 0x98, 0x24, 0x25, 0x11, 0x1a, 0xf1, 0x37, 0xc0, + 0x00, 0x61, 0x92, 0x49, 0x16, 0xf1, 0x12, 0x48, + 0x00, 0x89, 0x2f, 0xc0, 0x00, 0x19, 0x00, 0x89, + 0x2d, 0xc0, 0x01, 0x89, 0x2d, 0xc0, 0x04, 0x19, + 0x81, 0x1b, 0x1c, 0xe8, 0x2a, 0xc0, 0x14, 0x19, + 0x81, 0x1b, 0x18, 0xe8, 0x21, 0xc0, 0x0c, 0xe8, + 0x1f, 0xc0, 0x12, 0x48, 0x81, 0x1b, 0x12, 0xe8, + 0xae, 0xc3, 0x66, 0x71, 0xae, 0xc0, 0x02, 0x99, + 0x02, 0xc0, 0x00, 0xb8, 0x96, 0x07, 0x13, 0xc4, + 0x84, 0x98, 0x00, 0x1b, 0x86, 0x8b, 0x86, 0x73, + 0xbf, 0x49, 0xfe, 0xf1, 0x80, 0x71, 0x82, 0x72, + 0x80, 0xff, 0x09, 0xc4, 0x84, 0x98, 0x80, 0x99, + 0x82, 0x9a, 0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49, + 0xfe, 0xf1, 0x80, 0xff, 0x08, 0xea, 0x30, 0xd4, + 0x10, 0xc0, 0x12, 0xe8, 0x8a, 0xd3, 0x28, 0xe4, + 0x2c, 0xe4, 0x00, 0xd8, 0x00, 0x00, 0x00, 0x00 }; + +static const u16 r8153_pla_patch_b_bp[] = { + 0xfc26, 0x8000, 0xfc28, 0x1154, 0xfc2a, 0x1606, 0xfc2c, 0x155a, + 0xfc2e, 0x0080, 0xfc30, 0x033c, 0xfc32, 0x01a0, 0xfc34, 0x0794, + 0xfc36, 0x0000, 0xfc38, 0x007f }; + +static const u16 r8153_ram_code_d[] = { + 0xB436, 0xB820, 0xB438, 0x0290, 0xB436, 0xA012, 0xB438, 0x0000, + 0xB436, 0xA014, 0xB438, 0x2c04, 0xB438, 0x2c07, 0xB438, 0x2c07, + 0xB438, 0x2c07, 0xB438, 0xa240, 0xB438, 0xa104, 0xB438, 0x2944, + 0xB436, 0xA01A, 0xB438, 0x0000, 0xB436, 0xA006, 0xB438, 0x0fff, + 0xB436, 0xA004, 0xB438, 0x0fff, 0xB436, 0xA002, 0xB438, 0x0fff, + 0xB436, 0xA000, 0xB438, 0x1943, 0xB436, 0xB820, 0xB438, 0x0210 }; + +static const u8 usb_patch_d[] = { + 0x08, 0xe0, 0x0e, 0xe0, 0x11, 0xe0, 0x24, 0xe0, + 0x2b, 0xe0, 0x33, 0xe0, 0x3a, 0xe0, 0x3c, 0xe0, + 0x1e, 0xc3, 0x70, 0x61, 0x12, 0x48, 0x70, 0x89, + 0x02, 0xc3, 0x00, 0xbb, 0x02, 0x17, 0x32, 0x19, + 0x02, 0xc3, 0x00, 0xbb, 0x44, 0x14, 0x30, 0x18, + 0x11, 0xc1, 0x05, 0xe8, 0x10, 0xc6, 0x02, 0xc2, + 0x00, 0xba, 0x94, 0x17, 0x02, 0xb4, 0x09, 0xc2, + 0x40, 0x99, 0x0e, 0x48, 0x42, 0x98, 0x42, 0x70, + 0x8e, 0x49, 0xfe, 0xf1, 0x02, 0xb0, 0x80, 0xff, + 0xc0, 0xd4, 0xe4, 0x40, 0x20, 0xd4, 0x30, 0x18, + 0x06, 0xc1, 0xf1, 0xef, 0xfc, 0xc7, 0x02, 0xc0, + 0x00, 0xb8, 0x38, 0x12, 0xe4, 0x4b, 0x0c, 0x61, + 0x92, 0x48, 0x93, 0x48, 0x95, 0x48, 0x96, 0x48, + 0x0c, 0x89, 0x02, 0xc0, 0x00, 0xb8, 0x0e, 0x06, + 0x30, 0x18, 0xf5, 0xc1, 0xe0, 0xef, 0x04, 0xc5, + 0x02, 0xc4, 0x00, 0xbc, 0x76, 0x3c, 0x1e, 0xfc, + 0x02, 0xc6, 0x00, 0xbe, 0x00, 0x00, 0x02, 0xc6, + 0x00, 0xbe, 0x00, 0x00 }; + +static const u16 r8153_usb_patch_d_bp[] = { + 0xfc26, 0xa000, 0xfc28, 0x16de, 0xfc2a, 0x1442, 0xfc2c, 0x1792, + 0xfc2e, 0x1236, 0xfc30, 0x0606, 0xfc32, 0x3c74, 0xfc34, 0x0000, + 0xfc36, 0x0000, 0xfc38, 0x003e }; + +static const u8 pla_patch_d[] = { + 0x03, 0xe0, 0x16, 0xe0, 0x30, 0xe0, 0x12, 0xc2, + 0x40, 0x73, 0xb0, 0x49, 0x08, 0xf0, 0xb8, 0x49, + 0x06, 0xf0, 0xb8, 0x48, 0x40, 0x9b, 0x0b, 0xc2, + 0x40, 0x76, 0x05, 0xe0, 0x02, 0x61, 0x02, 0xc3, + 0x00, 0xbb, 0x54, 0x08, 0x02, 0xc3, 0x00, 0xbb, + 0x64, 0x08, 0x98, 0xd3, 0x1e, 0xfc, 0xfe, 0xc0, + 0x02, 0x62, 0xa0, 0x48, 0x02, 0x8a, 0x00, 0x72, + 0xa0, 0x49, 0x11, 0xf0, 0x13, 0xc1, 0x20, 0x62, + 0x2e, 0x21, 0x2f, 0x25, 0x00, 0x71, 0x9f, 0x24, + 0x0a, 0x40, 0x09, 0xf0, 0x00, 0x71, 0x18, 0x48, + 0xa0, 0x49, 0x03, 0xf1, 0x9f, 0x48, 0x02, 0xe0, + 0x1f, 0x48, 0x00, 0x99, 0x02, 0xc2, 0x00, 0xba, + 0xac, 0x0c, 0x08, 0xe9, 0x36, 0xc0, 0x00, 0x61, + 0x9c, 0x20, 0x9c, 0x24, 0x33, 0xc0, 0x07, 0x11, + 0x05, 0xf1, 0x00, 0x61, 0x17, 0x48, 0x00, 0x89, + 0x0d, 0xe0, 0x04, 0x11, 0x0b, 0xf1, 0x00, 0x61, + 0x97, 0x49, 0x08, 0xf0, 0x97, 0x48, 0x00, 0x89, + 0x23, 0xc0, 0x0e, 0xe8, 0x12, 0x48, 0x81, 0x1b, + 0x15, 0xe8, 0x1f, 0xc0, 0x00, 0x61, 0x67, 0x11, + 0x04, 0xf0, 0x02, 0xc0, 0x00, 0xb8, 0x42, 0x09, + 0x02, 0xc0, 0x00, 0xb8, 0x90, 0x08, 0x13, 0xc4, + 0x84, 0x98, 0x00, 0x1b, 0x86, 0x8b, 0x86, 0x73, + 0xbf, 0x49, 0xfe, 0xf1, 0x80, 0x71, 0x82, 0x72, + 0x80, 0xff, 0x09, 0xc4, 0x84, 0x98, 0x80, 0x99, + 0x82, 0x9a, 0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49, + 0xfe, 0xf1, 0x80, 0xff, 0x08, 0xea, 0x30, 0xd4, + 0x50, 0xe8, 0x8a, 0xd3 }; + +static const u16 r8153_pla_patch_d_bp[] = { + 0xfc26, 0x8000, 0xfc28, 0x0852, 0xfc2a, 0x0c92, 0xfc2c, 0x088c, + 0xfc2e, 0x0000, 0xfc30, 0x0000, 0xfc32, 0x0000, 0xfc34, 0x0000, + 0xfc36, 0x0000, 0xfc38, 0x0007 }; + +static const u8 usb_patch2_b[] = { + 0x10, 0xe0, 0x26, 0xe0, 0x3a, 0xe0, 0x58, 0xe0, + 0x6c, 0xe0, 0x85, 0xe0, 0xa5, 0xe0, 0xbe, 0xe0, + 0xd8, 0xe0, 0xdb, 0xe0, 0xf3, 0xe0, 0xf5, 0xe0, + 0xf7, 0xe0, 0xf9, 0xe0, 0xfb, 0xe0, 0xfd, 0xe0, + 0x16, 0xc0, 0x00, 0x75, 0xd1, 0x49, 0x0d, 0xf0, + 0x0f, 0xc0, 0x0f, 0xc5, 0x00, 0x1e, 0x08, 0x9e, + 0x0c, 0x9d, 0x0c, 0xc6, 0x0a, 0x9e, 0x8f, 0x1c, + 0x0e, 0x8c, 0x0e, 0x74, 0xcf, 0x49, 0xfe, 0xf1, + 0x02, 0xc0, 0x00, 0xb8, 0x96, 0x31, 0x00, 0xdc, + 0x24, 0xe4, 0x80, 0x02, 0x34, 0xd3, 0xff, 0xc3, + 0x60, 0x72, 0xa1, 0x49, 0x0d, 0xf0, 0xf8, 0xc3, + 0xf8, 0xc2, 0x00, 0x1c, 0x68, 0x9c, 0xf6, 0xc4, + 0x6a, 0x9c, 0x6c, 0x9a, 0x8f, 0x1c, 0x6e, 0x8c, + 0x6e, 0x74, 0xcf, 0x49, 0xfe, 0xf1, 0x04, 0xc0, + 0x02, 0xc2, 0x00, 0xba, 0xa8, 0x28, 0xf8, 0xc7, + 0xea, 0xc0, 0x00, 0x75, 0xd1, 0x49, 0x15, 0xf0, + 0x19, 0xc7, 0x17, 0xc2, 0xec, 0x9a, 0x00, 0x19, + 0xee, 0x89, 0xee, 0x71, 0x9f, 0x49, 0xfe, 0xf1, + 0xea, 0x71, 0x9f, 0x49, 0x0a, 0xf0, 0xd9, 0xc2, + 0xec, 0x9a, 0x00, 0x19, 0xe8, 0x99, 0x81, 0x19, + 0xee, 0x89, 0xee, 0x71, 0x9f, 0x49, 0xfe, 0xf1, + 0x06, 0xc3, 0x02, 0xc2, 0x00, 0xba, 0xf0, 0x1d, + 0x4c, 0xe8, 0x00, 0xdc, 0x00, 0xd4, 0xcb, 0xc0, + 0x00, 0x75, 0xd1, 0x49, 0x0d, 0xf0, 0xc4, 0xc0, + 0xc4, 0xc5, 0x00, 0x1e, 0x08, 0x9e, 0xc2, 0xc6, + 0x0a, 0x9e, 0x0c, 0x9d, 0x8f, 0x1c, 0x0e, 0x8c, + 0x0e, 0x74, 0xcf, 0x49, 0xfe, 0xf1, 0x04, 0xc0, + 0x02, 0xc1, 0x00, 0xb9, 0xc4, 0x16, 0x20, 0xd4, + 0xb6, 0xc0, 0x00, 0x75, 0xd1, 0x48, 0x00, 0x9d, + 0xe5, 0xc7, 0xaf, 0xc2, 0xec, 0x9a, 0x00, 0x19, + 0xe8, 0x9a, 0x81, 0x19, 0xee, 0x89, 0xee, 0x71, + 0x9f, 0x49, 0xfe, 0xf1, 0x2c, 0xc1, 0xec, 0x99, + 0x81, 0x19, 0xee, 0x89, 0xee, 0x71, 0x9f, 0x49, + 0xfe, 0xf1, 0x04, 0xc3, 0x02, 0xc2, 0x00, 0xba, + 0x96, 0x1c, 0xc0, 0xd4, 0xc0, 0x88, 0x1e, 0xc6, + 0xc0, 0x70, 0x8f, 0x49, 0x0e, 0xf0, 0x8f, 0x48, + 0x93, 0xc6, 0xca, 0x98, 0x11, 0x18, 0xc8, 0x98, + 0x16, 0xc0, 0xcc, 0x98, 0x8f, 0x18, 0xce, 0x88, + 0xce, 0x70, 0x8f, 0x49, 0xfe, 0xf1, 0x0b, 0xe0, + 0x43, 0xc6, 0x00, 0x18, 0xc8, 0x98, 0x0b, 0xc0, + 0xcc, 0x98, 0x81, 0x18, 0xce, 0x88, 0xce, 0x70, + 0x8f, 0x49, 0xfe, 0xf1, 0x02, 0xc0, 0x00, 0xb8, + 0xf2, 0x19, 0x40, 0xd3, 0x20, 0xe4, 0x33, 0xc2, + 0x40, 0x71, 0x91, 0x48, 0x40, 0x99, 0x30, 0xc2, + 0x00, 0x19, 0x48, 0x99, 0xf8, 0xc1, 0x4c, 0x99, + 0x81, 0x19, 0x4e, 0x89, 0x4e, 0x71, 0x9f, 0x49, + 0xfe, 0xf1, 0x0b, 0xc1, 0x4c, 0x99, 0x81, 0x19, + 0x4e, 0x89, 0x4e, 0x71, 0x9f, 0x49, 0xfe, 0xf1, + 0x02, 0x71, 0x02, 0xc2, 0x00, 0xba, 0x0e, 0x34, + 0x24, 0xe4, 0x19, 0xc2, 0x40, 0x71, 0x91, 0x48, + 0x40, 0x99, 0x16, 0xc2, 0x00, 0x19, 0x48, 0x99, + 0xde, 0xc1, 0x4c, 0x99, 0x81, 0x19, 0x4e, 0x89, + 0x4e, 0x71, 0x9f, 0x49, 0xfe, 0xf1, 0xf1, 0xc1, + 0x4c, 0x99, 0x81, 0x19, 0x4e, 0x89, 0x4e, 0x71, + 0x9f, 0x49, 0xfe, 0xf1, 0x02, 0x71, 0x02, 0xc2, + 0x00, 0xba, 0x60, 0x33, 0x34, 0xd3, 0x00, 0xdc, + 0x1e, 0x89, 0x02, 0xc0, 0x00, 0xb8, 0xfa, 0x12, + 0x18, 0xc0, 0x00, 0x65, 0xd1, 0x49, 0x0e, 0xf0, + 0x11, 0xc0, 0x11, 0xc5, 0x00, 0x1e, 0x08, 0x9e, + 0x0c, 0x9d, 0x0e, 0xc6, 0x0a, 0x9e, 0x8f, 0x1c, + 0x0e, 0x8c, 0x0e, 0x74, 0xcf, 0x49, 0xfe, 0xf1, + 0x04, 0xc0, 0x02, 0xc2, 0x00, 0xba, 0xa0, 0x41, + 0x06, 0xd4, 0x00, 0xdc, 0x24, 0xe4, 0x80, 0x02, + 0x34, 0xd3, 0x02, 0xc0, 0x00, 0xb8, 0x00, 0x00, + 0x02, 0xc0, 0x00, 0xb8, 0x00, 0x00, 0x02, 0xc0, + 0x00, 0xb8, 0x00, 0x00, 0x02, 0xc0, 0x00, 0xb8, + 0x00, 0x00, 0x02, 0xc0, 0x00, 0xb8, 0x00, 0x00, + 0x02, 0xc0, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x00 }; + +static const u16 r8153b_usb_patch_b_bp[] = { + 0xfc26, 0xa000, 0xfc28, 0x2a20, 0xfc2a, 0x28a6, 0xfc2c, 0x1dee, + 0xfc2e, 0x16c2, 0xfc30, 0x1c94, 0xfc32, 0x19f0, 0xfc34, 0x340c, + 0xfc36, 0x335e, 0xfc38, 0x12f8, 0xfc3a, 0x419e, 0xfc3c, 0x0000, + 0xfc3e, 0x0000, 0xfc40, 0x0000, 0xfc42, 0x0000, 0xfc44, 0x0000, + 0xfc46, 0x0000, 0xfc48, 0x03ff }; + +static const u8 pla_patch2_b[] = { + 0x05, 0xe0, 0x1b, 0xe0, 0x2c, 0xe0, 0x60, 0xe0, + 0x73, 0xe0, 0x15, 0xc6, 0xc2, 0x64, 0xd2, 0x49, + 0x06, 0xf1, 0xc4, 0x48, 0xc5, 0x48, 0xc6, 0x48, + 0xc7, 0x48, 0x05, 0xe0, 0x44, 0x48, 0x45, 0x48, + 0x46, 0x48, 0x47, 0x48, 0xc2, 0x8c, 0xc0, 0x64, + 0x46, 0x48, 0xc0, 0x8c, 0x05, 0xc5, 0x02, 0xc4, + 0x00, 0xbc, 0x18, 0x02, 0x06, 0xdc, 0xb0, 0xc0, + 0x10, 0xc5, 0xa0, 0x77, 0xa0, 0x74, 0x46, 0x48, + 0x47, 0x48, 0xa0, 0x9c, 0x0b, 0xc5, 0xa0, 0x74, + 0x44, 0x48, 0x43, 0x48, 0xa0, 0x9c, 0x05, 0xc5, + 0xa0, 0x9f, 0x02, 0xc5, 0x00, 0xbd, 0x3c, 0x03, + 0x1c, 0xe8, 0x20, 0xe8, 0xd4, 0x49, 0x04, 0xf1, + 0xd5, 0x49, 0x20, 0xf1, 0x28, 0xe0, 0x2a, 0xc7, + 0xe0, 0x75, 0xda, 0x49, 0x14, 0xf0, 0x27, 0xc7, + 0xe0, 0x75, 0xdc, 0x49, 0x10, 0xf1, 0x24, 0xc7, + 0xe0, 0x75, 0x25, 0xc7, 0xe0, 0x74, 0x2c, 0x40, + 0x0a, 0xfa, 0x1f, 0xc7, 0xe4, 0x75, 0xd0, 0x49, + 0x09, 0xf1, 0x1c, 0xc5, 0xe6, 0x9d, 0x11, 0x1d, + 0xe4, 0x8d, 0x04, 0xe0, 0x16, 0xc7, 0x00, 0x1d, + 0xe4, 0x8d, 0xe0, 0x8e, 0x11, 0x1d, 0xe0, 0x8d, + 0x07, 0xe0, 0x0c, 0xc7, 0xe0, 0x75, 0xda, 0x48, + 0xe0, 0x9d, 0x0b, 0xc7, 0xe4, 0x8e, 0x02, 0xc4, + 0x00, 0xbc, 0x28, 0x03, 0x02, 0xc4, 0x00, 0xbc, + 0x14, 0x03, 0x12, 0xe8, 0x4e, 0xe8, 0x1c, 0xe6, + 0x20, 0xe4, 0x80, 0x02, 0xa4, 0xc0, 0x12, 0xc2, + 0x40, 0x73, 0xb0, 0x49, 0x08, 0xf0, 0xb8, 0x49, + 0x06, 0xf0, 0xb8, 0x48, 0x40, 0x9b, 0x0b, 0xc2, + 0x40, 0x76, 0x05, 0xe0, 0x02, 0x61, 0x02, 0xc3, + 0x00, 0xbb, 0x0a, 0x0a, 0x02, 0xc3, 0x00, 0xbb, + 0x1a, 0x0a, 0x98, 0xd3, 0x1e, 0xfc, 0xfe, 0xc0, + 0x02, 0x62, 0xa0, 0x48, 0x02, 0x8a, 0x00, 0x72, + 0xa0, 0x49, 0x11, 0xf0, 0x13, 0xc1, 0x20, 0x62, + 0x2e, 0x21, 0x2f, 0x25, 0x00, 0x71, 0x9f, 0x24, + 0x0a, 0x40, 0x09, 0xf0, 0x00, 0x71, 0x18, 0x48, + 0xa0, 0x49, 0x03, 0xf1, 0x9f, 0x48, 0x02, 0xe0, + 0x1f, 0x48, 0x00, 0x99, 0x02, 0xc2, 0x00, 0xba, + 0xda, 0x0e, 0x08, 0xe9 }; + +static const u16 r8153b_pla_patch_b_bp[] = { + 0xfc26, 0x8000, 0xfc28, 0x0216, 0xfc2a, 0x0332, 0xfc2c, 0x030c, + 0xfc2e, 0x0a08, 0xfc30, 0x0ec0, 0xfc32, 0x0000, 0xfc34, 0x0000, + 0xfc36, 0x0000, 0xfc38, 0x001e }; + +static void rtl_clear_bp(struct r8152 *tp, u16 type) +{ + u8 zeros[16] = {0}; + + switch (tp->version) { + case RTL_VER_01: + case RTL_VER_02: + case RTL_VER_07: + break; + case RTL_VER_03: + case RTL_VER_04: + case RTL_VER_05: + case RTL_VER_06: + r8152_ocp_write_byte(tp, type, PLA_BP_EN, 0); + break; + case RTL_VER_08: + case RTL_VER_09: + default: + if (type == MCU_TYPE_USB) { + r8152_ocp_write_byte(tp, MCU_TYPE_USB, USB_BP2_EN, 0); + + r8152_generic_ocp_write(tp, USB_BP(8), 0xff, + sizeof(zeros), zeros, type); + } else { + r8152_ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); + } + break; + } + + r8152_generic_ocp_write(tp, USB_BP(0), 0xff, sizeof(zeros), zeros, + type); + + mdelay(6); + + r8152_ocp_write_word(tp, type, PLA_BP_BA, 0); +} + +static void r8152b_set_dq_desc(struct r8152 *tp) +{ + u8 data; + + data = r8152_ocp_read_byte(tp, MCU_TYPE_USB, 0xd429); + data |= 0x80; + r8152_ocp_write_byte(tp, MCU_TYPE_USB, 0xd429, data); + r8152_ocp_write_word(tp, MCU_TYPE_USB, 0xc0ce, 0x0210); + data = r8152_ocp_read_byte(tp, MCU_TYPE_USB, 0xd429); + data &= ~0x80; + r8152_ocp_write_byte(tp, MCU_TYPE_USB, 0xd429, data); +} + +static void r8153_pre_ram_code(struct r8152 *tp, u16 patch_key) +{ + u64 start; + u16 data; + + data = r8152_ocp_reg_read(tp, 0xb820); + data |= 0x0010; + r8152_ocp_reg_write(tp, 0xb820, data); + + start = get_time_ns(); + do { + mdelay(2); + data = r8152_ocp_reg_read(tp, 0xb800) & 0x0040; + if (is_timeout(start, 10 * SECOND)) { + dev_dbg(&tp->dev->edev.dev, "pre_ram_code timeout!\n"); + break; + } + } while (!data); + + r8152_sram_write(tp, 0x8146, patch_key); + r8152_sram_write(tp, 0xb82e, 0x0001); +} + +static int r8153_post_ram_code(struct r8152 *tp) +{ + u16 data; + + r8152_sram_write(tp, 0x0000, 0x0000); + + data = r8152_ocp_reg_read(tp, 0xb82e); + data &= ~0x0001; + r8152_ocp_reg_write(tp, 0xb82e, data); + + r8152_sram_write(tp, 0x8146, 0x0000); + + data = r8152_ocp_reg_read(tp, 0xb820); + data &= ~0x0010; + r8152_ocp_reg_write(tp, 0xb820, data); + + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base); + + return 0; +} + +static void r8153_wdt1_end(struct r8152 *tp) +{ + u64 start; + + start = get_time_ns(); + do { + if (!(r8152_ocp_read_byte(tp, MCU_TYPE_USB, 0xe404) & 1)) + break; + mdelay(2); + } while (!is_timeout(start, 208 * MSECOND)); +} + +void r8152b_firmware(struct r8152 *tp) +{ + int i; + + if (tp->version == RTL_VER_01) { + int i; + + r8152b_set_dq_desc(tp); + rtl_clear_bp(tp, MCU_TYPE_PLA); + + r8152_generic_ocp_write(tp, 0xf800, 0x3f, + sizeof(r8152b_pla_patch_a), + r8152b_pla_patch_a, MCU_TYPE_PLA); + + for (i = 0; i < ARRAY_SIZE(r8152b_pla_patch_a_bp); i += 2) + r8152_ocp_write_word(tp, MCU_TYPE_PLA, + r8152b_pla_patch_a_bp[i], + r8152b_pla_patch_a_bp[i + 1]); + + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, + 0x2000); + r8152_ocp_write_word(tp, MCU_TYPE_PLA, 0xb092, 0x7070); + r8152_ocp_write_word(tp, MCU_TYPE_PLA, 0xb098, 0x0600); + for (i = 0; i < ARRAY_SIZE(r8152b_ram_code1); i++) + r8152_ocp_write_word(tp, MCU_TYPE_PLA, 0xb09a, + r8152b_ram_code1[i]); + + r8152_ocp_write_word(tp, MCU_TYPE_PLA, 0xb098, 0x0200); + r8152_ocp_write_word(tp, MCU_TYPE_PLA, 0xb092, 0x7030); + } else if (tp->version == RTL_VER_02) { + rtl_clear_bp(tp, MCU_TYPE_PLA); + + r8152_generic_ocp_write(tp, 0xf800, 0xff, + sizeof(r8152b_pla_patch_a2), + r8152b_pla_patch_a2, MCU_TYPE_PLA); + + for (i = 0; i < ARRAY_SIZE(r8152b_pla_patch_a2_bp); + i += 2) + r8152_ocp_write_word(tp, MCU_TYPE_PLA, + r8152b_pla_patch_a2_bp[i], + r8152b_pla_patch_a2_bp[i + 1]); + } +} + +void r8153_firmware(struct r8152 *tp) +{ + int i; + + if (tp->version == RTL_VER_03) { + r8153_pre_ram_code(tp, 0x7000); + + for (i = 0; i < ARRAY_SIZE(r8153_ram_code_a); i += 2) + r8152_ocp_write_word(tp, MCU_TYPE_PLA, + r8153_ram_code_a[i], + r8153_ram_code_a[i + 1]); + + r8153_post_ram_code(tp); + } else if (tp->version == RTL_VER_04) { + r8153_pre_ram_code(tp, 0x7001); + + for (i = 0; i < ARRAY_SIZE(r8153_ram_code_bc); i += 2) + r8152_ocp_write_word(tp, MCU_TYPE_PLA, + r8153_ram_code_bc[i], + r8153_ram_code_bc[i + 1]); + + r8153_post_ram_code(tp); + + r8153_wdt1_end(tp); + + rtl_clear_bp(tp, MCU_TYPE_USB); + + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x0000); + r8152_generic_ocp_write(tp, 0xf800, 0xff, + sizeof(r8153_usb_patch_b), + r8153_usb_patch_b, MCU_TYPE_USB); + + for (i = 0; i < ARRAY_SIZE(r8153_usb_patch_b_bp); i += 2) + r8152_ocp_write_word(tp, MCU_TYPE_USB, + r8153_usb_patch_b_bp[i], + r8153_usb_patch_b_bp[i + 1]); + + if (!(r8152_ocp_read_word(tp, MCU_TYPE_PLA, 0xd38e) & BIT(0))) { + r8152_ocp_write_word(tp, MCU_TYPE_PLA, 0xd38c, 0x0082); + r8152_ocp_write_word(tp, MCU_TYPE_PLA, 0xd38e, 0x0082); + } + + rtl_clear_bp(tp, MCU_TYPE_PLA); + + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, 0x0000); + r8152_generic_ocp_write(tp, 0xf800, 0xff, + sizeof(r8153_pla_patch_b), + r8153_pla_patch_b, MCU_TYPE_PLA); + + for (i = 0; i < ARRAY_SIZE(r8153_pla_patch_b_bp); i += 2) + r8152_ocp_write_word(tp, MCU_TYPE_PLA, + r8153_pla_patch_b_bp[i], + r8153_pla_patch_b_bp[i + 1]); + + r8152_ocp_write_word(tp, MCU_TYPE_PLA, 0xd388, 0x08ca); + } else if (tp->version == RTL_VER_05) { + u32 ocp_data; + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, 0xcfca); + ocp_data &= ~0x4000; + r8152_ocp_write_word(tp, MCU_TYPE_USB, 0xcfca, ocp_data); + + r8153_pre_ram_code(tp, 0x7001); + + for (i = 0; i < ARRAY_SIZE(r8153_ram_code_bc); i += 2) + r8152_ocp_write_word(tp, MCU_TYPE_PLA, + r8153_ram_code_bc[i], + r8153_ram_code_bc[i + 1]); + + r8153_post_ram_code(tp); + + r8153_wdt1_end(tp); + + rtl_clear_bp(tp, MCU_TYPE_USB); + + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x0000); + r8152_generic_ocp_write(tp, 0xf800, 0xff, + sizeof(r8153_usb_patch_c), + r8153_usb_patch_c, MCU_TYPE_USB); + + for (i = 0; i < ARRAY_SIZE(r8153_usb_patch_c_bp); i += 2) + r8152_ocp_write_word(tp, MCU_TYPE_USB, + r8153_usb_patch_c_bp[i], + r8153_usb_patch_c_bp[i + 1]); + + if (r8152_ocp_read_byte(tp, MCU_TYPE_USB, 0xcfef) & 1) { + r8152_ocp_write_word(tp, MCU_TYPE_USB, 0xfc30, 0x1578); + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, + 0x00ff); + } else { + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, + 0x00ef); + } + + rtl_clear_bp(tp, MCU_TYPE_PLA); + + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, 0x0000); + r8152_generic_ocp_write(tp, 0xf800, 0xff, + sizeof(r8153_pla_patch_c), + r8153_pla_patch_c, MCU_TYPE_PLA); + + for (i = 0; i < ARRAY_SIZE(r8153_pla_patch_c_bp); i += 2) + r8152_ocp_write_word(tp, MCU_TYPE_PLA, + r8153_pla_patch_c_bp[i], + r8153_pla_patch_c_bp[i + 1]); + + r8152_ocp_write_word(tp, MCU_TYPE_PLA, 0xd388, 0x08ca); + + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + U3P3_CHECK_EN | 4); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, 0xcfca); + ocp_data |= 0x4000; + r8152_ocp_write_word(tp, MCU_TYPE_USB, 0xcfca, ocp_data); + + ocp_data = r8152_ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); + ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; + r8152_ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); + } else if (tp->version == RTL_VER_06) { + u32 ocp_data; + + r8153_pre_ram_code(tp, 0x7002); + + for (i = 0; i < ARRAY_SIZE(r8153_ram_code_d); i += 2) + r8152_ocp_write_word(tp, MCU_TYPE_PLA, + r8153_ram_code_d[i], + r8153_ram_code_d[i + 1]); + + r8153_post_ram_code(tp); + + rtl_clear_bp(tp, MCU_TYPE_USB); + + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x0000); + r8152_generic_ocp_write(tp, 0xf800, 0xff, sizeof(usb_patch_d), + usb_patch_d, MCU_TYPE_USB); + + for (i = 0; i < ARRAY_SIZE(r8153_usb_patch_d_bp); i += 2) + r8152_ocp_write_word(tp, MCU_TYPE_USB, + r8153_usb_patch_d_bp[i], + r8153_usb_patch_d_bp[i + 1]); + + rtl_clear_bp(tp, MCU_TYPE_PLA); + + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, 0x0000); + r8152_generic_ocp_write(tp, 0xf800, 0xff, sizeof(pla_patch_d), + pla_patch_d, MCU_TYPE_PLA); + + for (i = 0; i < ARRAY_SIZE(r8153_pla_patch_d_bp); i += 2) + r8152_ocp_write_word(tp, MCU_TYPE_PLA, + r8153_pla_patch_d_bp[i], + r8153_pla_patch_d_bp[i + 1]); + + ocp_data = r8152_ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); + ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; + r8152_ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, + USB_FW_FIX_EN1); + ocp_data |= FW_IP_RESET_EN; + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, + ocp_data); + } +} + +void r8153b_firmware(struct r8152 *tp) +{ + u32 ocp_data; + int i; + + if (tp->version != RTL_VER_09) + return; + + rtl_clear_bp(tp, MCU_TYPE_USB); + + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x0000); + r8152_generic_ocp_write(tp, 0xe600, 0xff, sizeof(usb_patch2_b), + usb_patch2_b, MCU_TYPE_USB); + + for (i = 0; i < ARRAY_SIZE(r8153b_usb_patch_b_bp); i += 2) + r8152_ocp_write_word(tp, MCU_TYPE_USB, + r8153b_usb_patch_b_bp[i], + r8153b_usb_patch_b_bp[i + 1]); + + rtl_clear_bp(tp, MCU_TYPE_PLA); + + r8152_ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, 0x0000); + r8152_generic_ocp_write(tp, 0xf800, 0xff, sizeof(pla_patch2_b), + pla_patch2_b, MCU_TYPE_PLA); + + for (i = 0; i < ARRAY_SIZE(r8153b_pla_patch_b_bp); i += 2) + r8152_ocp_write_word(tp, MCU_TYPE_PLA, + r8153b_pla_patch_b_bp[i], + r8153b_pla_patch_b_bp[i + 1]); + + ocp_data = r8152_ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); + ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; + r8152_ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); + + ocp_data = r8152_ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); + ocp_data |= FW_IP_RESET_EN; + r8152_ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); +} diff --git a/drivers/of/partition.c b/drivers/of/partition.c index 10081363de..18b138f00e 100644 --- a/drivers/of/partition.c +++ b/drivers/of/partition.c @@ -256,6 +256,9 @@ static int of_partition_fixup(struct device_node *root, void *ctx) if (!cdev->device_node) return -EINVAL; + if (list_empty(&cdev->partitions)) + return 0; + name = of_get_reproducible_name(cdev->device_node); np = of_find_node_by_reproducible_name(root, name); free(name); diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index 7fa394934a..1c6214594c 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c @@ -12,7 +12,7 @@ #include <common.h> #include <driver.h> #include <module.h> -#include <printk.h> +#include <linux/printk.h> #include <stdio.h> #include <init.h> #include <pwm.h> diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 097f7d779b..071131a1ca 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -573,7 +573,7 @@ int regulator_get_voltage(struct regulator *regulator) return ret; } -EXPORT_SYMBOL_GPL(regulator_get_voltage_rdev); +EXPORT_SYMBOL_GPL(regulator_get_voltage); static void regulator_print_one(struct regulator_internal *ri) { diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 073f8faea8..56d301378f 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -88,9 +88,10 @@ static int socfpga_reset_probe(struct device_d *dev) data = xzalloc(sizeof(*data)); res = dev_request_mem_resource(dev, 0); + if (IS_ERR(res)) + return PTR_ERR(res); + data->membase = IOMEM(res->start); - if (IS_ERR(data->membase)) - return PTR_ERR(data->membase); if (of_property_read_u32(np, "altr,modrst-offset", &modrst_offset)) { dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n"); diff --git a/drivers/serial/atmel.c b/drivers/serial/atmel.c index 8394273f9f..612265692f 100644 --- a/drivers/serial/atmel.c +++ b/drivers/serial/atmel.c @@ -427,6 +427,7 @@ static int atmel_serial_probe(struct device_d *dev) { struct atmel_uart_port *uart; struct console_device *cdev; + int ret; uart = xzalloc(sizeof(struct atmel_uart_port)); cdev = &uart->uart; @@ -438,7 +439,9 @@ static int atmel_serial_probe(struct device_d *dev) cdev->set_mode = atmel_serial_set_mode; cdev->linux_console_name = "ttyAT"; - atmel_serial_init_port(cdev); + ret = atmel_serial_init_port(cdev); + if (ret) + return ret; /* Enable UART */ diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c index a1e9a10622..c1b7fda9c8 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_l2_cache.c @@ -9,7 +9,7 @@ #define pr_fmt(fmt) "sifive-l2: " fmt #include <io.h> -#include <printk.h> +#include <linux/printk.h> #include <stdio.h> #include <driver.h> #include <init.h> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index e92cf675ab..2859e83227 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -106,6 +106,13 @@ config SPI_ZYNQ_QSPI This enables support for the Zynq Quad SPI controller in master mode. This controller only supports SPI memory interface. +config DRIVER_SPI_STM32 + bool "STM32 SPI driver" + depends on ARCH_STM32MP || COMPILE_TEST + help + Enable the STM32 Serial Peripheral Interface (SPI) driver for STM32MP + SoCs. + endif endmenu diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index ac95ffc1db..e85373c7c6 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o obj-$(CONFIG_DRIVER_SPI_OMAP3) += omap3_spi.o obj-$(CONFIG_DRIVER_SPI_DSPI) += dspi_spi.o obj-$(CONFIG_SPI_ZYNQ_QSPI) += zynq_qspi.o +obj-$(CONFIG_DRIVER_SPI_STM32) += stm32_spi.o diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c new file mode 100644 index 0000000000..0cb04a968c --- /dev/null +++ b/drivers/spi/stm32_spi.c @@ -0,0 +1,590 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + * + * Driver for STMicroelectronics Serial peripheral interface (SPI) + */ + +#include <common.h> +#include <linux/clk.h> +#include <driver.h> +#include <init.h> +#include <errno.h> +#include <linux/reset.h> +#include <spi/spi.h> +#include <linux/bitops.h> +#include <clock.h> +#include <gpio.h> +#include <of_gpio.h> +#include <linux/bitfield.h> +#include <linux/iopoll.h> + +/* STM32 SPI registers */ +#define STM32_SPI_CR1 0x00 +#define STM32_SPI_CR2 0x04 +#define STM32_SPI_CFG1 0x08 +#define STM32_SPI_CFG2 0x0C +#define STM32_SPI_SR 0x14 +#define STM32_SPI_IFCR 0x18 +#define STM32_SPI_TXDR 0x20 +#define STM32_SPI_RXDR 0x30 +#define STM32_SPI_I2SCFGR 0x50 + +/* STM32_SPI_CR1 bit fields */ +#define SPI_CR1_SPE BIT(0) +#define SPI_CR1_MASRX BIT(8) +#define SPI_CR1_CSTART BIT(9) +#define SPI_CR1_CSUSP BIT(10) +#define SPI_CR1_HDDIR BIT(11) +#define SPI_CR1_SSI BIT(12) + +/* STM32_SPI_CR2 bit fields */ +#define SPI_CR2_TSIZE GENMASK(15, 0) + +/* STM32_SPI_CFG1 bit fields */ +#define SPI_CFG1_DSIZE GENMASK(4, 0) +#define SPI_CFG1_DSIZE_MIN 3 +#define SPI_CFG1_FTHLV_SHIFT 5 +#define SPI_CFG1_FTHLV GENMASK(8, 5) +#define SPI_CFG1_MBR_SHIFT 28 +#define SPI_CFG1_MBR GENMASK(30, 28) +#define SPI_CFG1_MBR_MIN 0 +#define SPI_CFG1_MBR_MAX FIELD_GET(SPI_CFG1_MBR, SPI_CFG1_MBR) + +/* STM32_SPI_CFG2 bit fields */ +#define SPI_CFG2_COMM_SHIFT 17 +#define SPI_CFG2_COMM GENMASK(18, 17) +#define SPI_CFG2_MASTER BIT(22) +#define SPI_CFG2_LSBFRST BIT(23) +#define SPI_CFG2_CPHA BIT(24) +#define SPI_CFG2_CPOL BIT(25) +#define SPI_CFG2_SSM BIT(26) +#define SPI_CFG2_AFCNTR BIT(31) + +/* STM32_SPI_SR bit fields */ +#define SPI_SR_RXP BIT(0) +#define SPI_SR_TXP BIT(1) +#define SPI_SR_EOT BIT(3) +#define SPI_SR_TXTF BIT(4) +#define SPI_SR_OVR BIT(6) +#define SPI_SR_SUSP BIT(11) +#define SPI_SR_RXPLVL_SHIFT 13 +#define SPI_SR_RXPLVL GENMASK(14, 13) +#define SPI_SR_RXWNE BIT(15) + +/* STM32_SPI_IFCR bit fields */ +#define SPI_IFCR_ALL GENMASK(11, 3) + +/* STM32_SPI_I2SCFGR bit fields */ +#define SPI_I2SCFGR_I2SMOD BIT(0) + +/* SPI Master Baud Rate min/max divisor */ +#define STM32_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN) +#define STM32_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX) + +/* SPI Communication mode */ +#define SPI_FULL_DUPLEX 0 +#define SPI_SIMPLEX_TX 1 +#define SPI_SIMPLEX_RX 2 +#define SPI_HALF_DUPLEX 3 + +struct stm32_spi_priv { + struct spi_master master; + int *cs_gpios; + void __iomem *base; + struct clk *clk; + ulong bus_clk_rate; + unsigned int fifo_size; + unsigned int cur_bpw; + unsigned int cur_hz; + unsigned int cur_xferlen; /* current transfer length in bytes */ + unsigned int tx_len; /* number of data to be written in bytes */ + unsigned int rx_len; /* number of data to be read in bytes */ + const void *tx_buf; /* data to be written, or NULL */ + void *rx_buf; /* data to be read, or NULL */ + u32 cur_mode; +}; + +static inline struct stm32_spi_priv *to_stm32_spi_priv(struct spi_master *master) +{ + return container_of(master, struct stm32_spi_priv, master); +} + +static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv) +{ + while ((priv->tx_len > 0) && + (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) { + u32 offs = priv->cur_xferlen - priv->tx_len; + + if (priv->tx_len >= sizeof(u32) && + IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) { + const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs); + + writel(*tx_buf32, priv->base + STM32_SPI_TXDR); + priv->tx_len -= sizeof(u32); + } else if (priv->tx_len >= sizeof(u16) && + IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) { + const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs); + + writew(*tx_buf16, priv->base + STM32_SPI_TXDR); + priv->tx_len -= sizeof(u16); + } else { + const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs); + + writeb(*tx_buf8, priv->base + STM32_SPI_TXDR); + priv->tx_len -= sizeof(u8); + } + } + + dev_dbg(priv->master.dev, "%d bytes left\n", priv->tx_len); +} + +static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv) +{ + u32 sr = readl(priv->base + STM32_SPI_SR); + u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT; + + while ((priv->rx_len > 0) && + ((sr & SPI_SR_RXP) || + ((sr & SPI_SR_EOT) && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) { + u32 offs = priv->cur_xferlen - priv->rx_len; + + if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u32)) && + (priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) { + u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs); + + *rx_buf32 = readl(priv->base + STM32_SPI_RXDR); + priv->rx_len -= sizeof(u32); + } else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) && + (priv->rx_len >= sizeof(u16) || + (!(sr & SPI_SR_RXWNE) && + (rxplvl >= 2 || priv->cur_bpw > 8)))) { + u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs); + + *rx_buf16 = readw(priv->base + STM32_SPI_RXDR); + priv->rx_len -= sizeof(u16); + } else { + u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs); + + *rx_buf8 = readb(priv->base + STM32_SPI_RXDR); + priv->rx_len -= sizeof(u8); + } + + sr = readl(priv->base + STM32_SPI_SR); + rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT; + } + + dev_dbg(priv->master.dev, "%d bytes left\n", priv->rx_len); +} + +static void stm32_spi_enable(struct stm32_spi_priv *priv) +{ + setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE); +} + +static void stm32_spi_disable(struct stm32_spi_priv *priv) +{ + clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE); +} + +static void stm32_spi_stopxfer(struct stm32_spi_priv *priv) +{ + struct device_d *dev = priv->master.dev; + u32 cr1, sr; + int ret; + + dev_dbg(dev, "%s\n", __func__); + + cr1 = readl(priv->base + STM32_SPI_CR1); + + if (!(cr1 & SPI_CR1_SPE)) + return; + + /* Wait on EOT or suspend the flow */ + ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr, + !(sr & SPI_SR_EOT), USEC_PER_SEC); + if (ret < 0) { + if (cr1 & SPI_CR1_CSTART) { + writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1); + if (readl_poll_timeout(priv->base + STM32_SPI_SR, + sr, !(sr & SPI_SR_SUSP), + 100000) < 0) + dev_err(dev, "Suspend request timeout\n"); + } + } + + /* clear status flags */ + setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL); +} + +static void stm32_spi_set_cs(struct spi_device *spi, bool en) +{ + struct stm32_spi_priv *priv = to_stm32_spi_priv(spi->master); + int gpio = priv->cs_gpios[spi->chip_select]; + int ret = -EINVAL; + + dev_dbg(priv->master.dev, "cs=%d en=%d\n", gpio, en); + + if (gpio_is_valid(gpio)) + ret = gpio_direction_output(gpio, (spi->mode & SPI_CS_HIGH) ? en : !en); + + if (ret) + dev_warn(priv->master.dev, "couldn't toggle cs#%u\n", spi->chip_select); +} + +static void stm32_spi_set_mode(struct stm32_spi_priv *priv, unsigned mode) +{ + u32 cfg2_clrb = 0, cfg2_setb = 0; + + dev_dbg(priv->master.dev, "mode=%d\n", mode); + + if (mode & SPI_CPOL) + cfg2_setb |= SPI_CFG2_CPOL; + else + cfg2_clrb |= SPI_CFG2_CPOL; + + if (mode & SPI_CPHA) + cfg2_setb |= SPI_CFG2_CPHA; + else + cfg2_clrb |= SPI_CFG2_CPHA; + + if (mode & SPI_LSB_FIRST) + cfg2_setb |= SPI_CFG2_LSBFRST; + else + cfg2_clrb |= SPI_CFG2_LSBFRST; + + if (cfg2_clrb || cfg2_setb) + clrsetbits_le32(priv->base + STM32_SPI_CFG2, + cfg2_clrb, cfg2_setb); +} + +static void stm32_spi_set_fthlv(struct stm32_spi_priv *priv, u32 xfer_len) +{ + u32 fthlv, half_fifo; + + /* data packet should not exceed 1/2 of fifo space */ + half_fifo = (priv->fifo_size / 2); + + /* data_packet should not exceed transfer length */ + fthlv = (half_fifo > xfer_len) ? xfer_len : half_fifo; + + /* align packet size with data registers access */ + fthlv -= (fthlv % 4); + + if (!fthlv) + fthlv = 1; + clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV, + (fthlv - 1) << SPI_CFG1_FTHLV_SHIFT); +} + +static int stm32_spi_set_speed(struct stm32_spi_priv *priv, uint hz) +{ + u32 mbrdiv; + long div; + + dev_dbg(priv->master.dev, "hz=%d\n", hz); + + if (priv->cur_hz == hz) + return 0; + + div = DIV_ROUND_UP(priv->bus_clk_rate, hz); + + if (div < STM32_MBR_DIV_MIN || div > STM32_MBR_DIV_MAX) + return -EINVAL; + + /* Determine the first power of 2 greater than or equal to div */ + if (div & (div - 1)) + mbrdiv = fls(div); + else + mbrdiv = fls(div) - 1; + + if (!mbrdiv) + return -EINVAL; + + clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR, + (mbrdiv - 1) << SPI_CFG1_MBR_SHIFT); + + priv->cur_hz = hz; + + return 0; +} + +static int stm32_spi_setup(struct spi_device *spi) +{ + struct stm32_spi_priv *priv = to_stm32_spi_priv(spi->master); + int ret; + + stm32_spi_set_cs(spi, false); + stm32_spi_enable(priv); + + stm32_spi_set_mode(priv, spi->mode); + + ret = stm32_spi_set_speed(priv, spi->max_speed_hz); + if (ret) + goto out; + + priv->cur_bpw = spi->bits_per_word; + clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE, + priv->cur_bpw - 1); + + dev_dbg(priv->master.dev, "%s mode 0x%08x bits_per_word: %d speed: %d\n", + __func__, spi->mode, spi->bits_per_word, + spi->max_speed_hz); +out: + stm32_spi_disable(priv); + return ret; +} + +static int stm32_spi_transfer_one(struct stm32_spi_priv *priv, + struct spi_transfer *t) +{ + struct device_d *dev = priv->master.dev; + u32 sr; + u32 ifcr = 0; + u32 mode; + int xfer_status = 0; + + if (t->len <= SPI_CR2_TSIZE) + writel(t->len, priv->base + STM32_SPI_CR2); + else + return -EMSGSIZE; + + priv->tx_buf = t->tx_buf; + priv->rx_buf = t->rx_buf; + priv->tx_len = priv->tx_buf ? t->len : 0; + priv->rx_len = priv->rx_buf ? t->len : 0; + + mode = SPI_FULL_DUPLEX; + if (!priv->tx_buf) + mode = SPI_SIMPLEX_RX; + else if (!priv->rx_buf) + mode = SPI_SIMPLEX_TX; + + if (priv->cur_xferlen != t->len || priv->cur_mode != mode) { + priv->cur_mode = mode; + priv->cur_xferlen = t->len; + + /* Disable the SPI hardware to unlock CFG1/CFG2 registers */ + stm32_spi_disable(priv); + + clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM, + mode << SPI_CFG2_COMM_SHIFT); + + stm32_spi_set_fthlv(priv, t->len); + + /* Enable the SPI hardware */ + stm32_spi_enable(priv); + } + + dev_dbg(dev, "priv->tx_len=%d priv->rx_len=%d\n", + priv->tx_len, priv->rx_len); + + /* Be sure to have data in fifo before starting data transfer */ + if (priv->tx_buf) + stm32_spi_write_txfifo(priv); + + setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART); + + while (1) { + sr = readl(priv->base + STM32_SPI_SR); + + if (sr & SPI_SR_OVR) { + dev_err(dev, "Overrun: RX data lost\n"); + xfer_status = -EIO; + break; + } + + if (sr & SPI_SR_SUSP) { + dev_warn(dev, "System too slow is limiting data throughput\n"); + + if (priv->rx_buf && priv->rx_len > 0) + stm32_spi_read_rxfifo(priv); + + ifcr |= SPI_SR_SUSP; + } + + if (sr & SPI_SR_TXTF) + ifcr |= SPI_SR_TXTF; + + if (sr & SPI_SR_TXP) + if (priv->tx_buf && priv->tx_len > 0) + stm32_spi_write_txfifo(priv); + + if (sr & SPI_SR_RXP) + if (priv->rx_buf && priv->rx_len > 0) + stm32_spi_read_rxfifo(priv); + + if (sr & SPI_SR_EOT) { + if (priv->rx_buf && priv->rx_len > 0) + stm32_spi_read_rxfifo(priv); + break; + } + + writel(ifcr, priv->base + STM32_SPI_IFCR); + } + + /* clear status flags */ + setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL); + stm32_spi_stopxfer(priv); + + return xfer_status; +} + +static int stm32_spi_transfer(struct spi_device *spi, struct spi_message *mesg) +{ + struct stm32_spi_priv *priv = to_stm32_spi_priv(spi->master); + struct spi_transfer *t; + unsigned int cs_change; + const int nsecs = 50; + int ret = 0; + + stm32_spi_enable(priv); + + stm32_spi_set_cs(spi, true); + + cs_change = 0; + + mesg->actual_length = 0; + + list_for_each_entry(t, &mesg->transfers, transfer_list) { + if (cs_change) { + ndelay(nsecs); + stm32_spi_set_cs(spi, false); + ndelay(nsecs); + stm32_spi_set_cs(spi, true); + } + + cs_change = t->cs_change; + + ret = stm32_spi_transfer_one(priv, t); + if (ret) + goto out; + + mesg->actual_length += t->len; + + if (cs_change) + stm32_spi_set_cs(spi, true); + } + + if (!cs_change) + stm32_spi_set_cs(spi, false); + +out: + stm32_spi_disable(priv); + return ret; +} + +static int stm32_spi_get_fifo_size(struct stm32_spi_priv *priv) +{ + u32 count = 0; + + stm32_spi_enable(priv); + + while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP) + writeb(++count, priv->base + STM32_SPI_TXDR); + + stm32_spi_disable(priv); + + dev_dbg(priv->master.dev, "%d x 8-bit fifo size\n", count); + + return count; +} + +static void stm32_spi_dt_probe(struct stm32_spi_priv *priv) +{ + struct device_node *node = priv->master.dev->device_node; + int i; + + priv->master.num_chipselect = of_gpio_named_count(node, "cs-gpios"); + priv->cs_gpios = xzalloc(sizeof(u32) * priv->master.num_chipselect); + + for (i = 0; i < priv->master.num_chipselect; i++) + priv->cs_gpios[i] = of_get_named_gpio(node, "cs-gpios", i); +} + +static int stm32_spi_probe(struct device_d *dev) +{ + struct resource *iores; + struct spi_master *master; + struct stm32_spi_priv *priv; + int ret; + + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + + priv = dev->priv = xzalloc(sizeof(*priv)); + + priv->base = IOMEM(iores->start); + + master = &priv->master; + master->dev = dev; + + master->setup = stm32_spi_setup; + master->transfer = stm32_spi_transfer; + + master->bus_num = -1; + stm32_spi_dt_probe(priv); + + priv->clk = clk_get(dev, NULL); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + ret = clk_enable(priv->clk); + if (ret) + return ret; + + priv->bus_clk_rate = clk_get_rate(priv->clk); + + ret = device_reset_us(dev, 2); + if (ret) + return ret; + + priv->fifo_size = stm32_spi_get_fifo_size(priv); + + priv->cur_mode = SPI_FULL_DUPLEX; + priv->cur_xferlen = 0; + + /* Ensure I2SMOD bit is kept cleared */ + clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD); + + /* + * - SS input value high + * - transmitter half duplex direction + * - automatic communication suspend when RX-Fifo is full + */ + setbits_le32(priv->base + STM32_SPI_CR1, + SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); + + /* + * - Set the master mode (default Motorola mode) + * - Consider 1 master/n slaves configuration and + * SS input value is determined by the SSI bit + * - keep control of all associated GPIOs + */ + setbits_le32(priv->base + STM32_SPI_CFG2, + SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR); + + return spi_register_master(master); +} + +static void stm32_spi_remove(struct device_d *dev) +{ + struct stm32_spi_priv *priv = dev->priv; + + stm32_spi_stopxfer(priv); + stm32_spi_disable(priv); +}; + +static const struct of_device_id stm32_spi_ids[] = { + { .compatible = "st,stm32h7-spi", }, + { /* sentinel */ } +}; + +static struct driver_d stm32_spi_driver = { + .name = "stm32_spi", + .probe = stm32_spi_probe, + .remove = stm32_spi_remove, + .of_compatible = stm32_spi_ids, +}; +coredevice_platform_driver(stm32_spi_driver); diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index d01e4a8e6c..bd3418a3fb 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -559,13 +559,13 @@ static int zynq_qspi_probe(struct device_d *dev) xqspi->regs = IOMEM(iores->start); xqspi->pclk = clk_get(dev, "pclk"); - if (IS_ERR_OR_NULL(xqspi->pclk)) { + if (IS_ERR(xqspi->pclk)) { dev_err(dev, "pclk clock not found.\n"); return PTR_ERR(xqspi->pclk); } xqspi->refclk = clk_get(dev, "ref_clk"); - if (IS_ERR_OR_NULL(xqspi->refclk)) { + if (IS_ERR(xqspi->refclk)) { dev_err(dev, "ref_clk clock not found.\n"); return PTR_ERR(xqspi->refclk); } diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 04b700d12d..2a4d1c066d 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1114,8 +1114,6 @@ static int dwc3_probe(struct device_d *dev) if (of_find_property(dev->device_node, "clocks", NULL)) { ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks); - if (ret == -EPROBE_DEFER) - return ret; if (ret) return ret; } diff --git a/drivers/watchdog/f71808e_wdt.c b/drivers/watchdog/f71808e_wdt.c index 925c2f809d..b2cf0f8ddd 100644 --- a/drivers/watchdog/f71808e_wdt.c +++ b/drivers/watchdog/f71808e_wdt.c @@ -13,7 +13,7 @@ #include <asm/io.h> #include <driver.h> #include <watchdog.h> -#include <printk.h> +#include <linux/printk.h> #include <reset_source.h> #include <superio.h> #include <common.h> diff --git a/fs/devfs-core.c b/fs/devfs-core.c index 30ad0e0508..3715e543e6 100644 --- a/fs/devfs-core.c +++ b/fs/devfs-core.c @@ -301,6 +301,37 @@ int devfs_remove(struct cdev *cdev) return 0; } +static bool region_overlap(loff_t starta, loff_t lena, + loff_t startb, loff_t lenb) +{ + if (starta + lena <= startb) + return 0; + if (startb + lenb <= starta) + return 0; + return 1; +} + +static int check_overlap(struct cdev *cdev, const char *name, loff_t offset, loff_t size) +{ + struct cdev *cpart; + + list_for_each_entry(cpart, &cdev->partitions, partition_entry) { + if (region_overlap(cpart->offset, cpart->size, + offset, size)) + goto conflict; + } + + return 0; + +conflict: + pr_err("New partition %s (0x%08llx-0x%08llx) on %s " + "overlaps with partition %s (0x%08llx-0x%08llx), not creating it\n", + name, offset, offset + size - 1, cpart->name, + cpart->name, cpart->offset, cpart->offset + cpart->size - 1); + + return -EINVAL; +} + static struct cdev *__devfs_add_partition(struct cdev *cdev, const struct devfs_partition *partinfo, loff_t *end) { @@ -336,6 +367,9 @@ static struct cdev *__devfs_add_partition(struct cdev *cdev, return ERR_PTR(-EINVAL); } + if (check_overlap(cdev, partinfo->name, offset, size)) + return ERR_PTR(-EINVAL); + if (IS_ENABLED(CONFIG_MTD) && cdev->mtd) { struct mtd_info *mtd; diff --git a/fs/pstore/platform.c b/fs/pstore/platform.c index f4b77226d9..50a1bffdd0 100644 --- a/fs/pstore/platform.c +++ b/fs/pstore/platform.c @@ -27,7 +27,7 @@ #include <linux/mutex.h> #include <console.h> #include <malloc.h> -#include <printk.h> +#include <linux/printk.h> #include <module.h> #include "internal.h" diff --git a/fs/pstore/ram.c b/fs/pstore/ram.c index 958f46b0ea..0d8bb8f418 100644 --- a/fs/pstore/ram.c +++ b/fs/pstore/ram.c @@ -31,7 +31,7 @@ #include <linux/log2.h> #include <linux/spinlock.h> #include <malloc.h> -#include <printk.h> +#include <linux/printk.h> #include <stdio.h> #include <globalvar.h> #include <init.h> diff --git a/fs/ramfs.c b/fs/ramfs.c index 14ba877660..bdaa91dd9e 100644 --- a/fs/ramfs.c +++ b/fs/ramfs.c @@ -447,7 +447,6 @@ static int ramfs_probe(struct device_d *dev) static void ramfs_remove(struct device_d *dev) { - free(dev->priv); } static struct fs_driver_d ramfs_driver = { diff --git a/fs/squashfs/squashfs.h b/fs/squashfs/squashfs.h index 825df2aedd..9ddcfbf1c2 100644 --- a/fs/squashfs/squashfs.h +++ b/fs/squashfs/squashfs.h @@ -17,7 +17,7 @@ * squashfs.h */ -#include <printk.h> +#include <linux/printk.h> #include <fs.h> #include <linux/fs.h> #include <linux/kernel.h> diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h index 82b78261fc..6aa3eada0e 100644 --- a/include/asm-generic/bug.h +++ b/include/asm-generic/bug.h @@ -2,6 +2,8 @@ #define _ASM_GENERIC_BUG_H #include <linux/compiler.h> +#include <linux/kernel.h> +#include <printk.h> #define BUG() do { \ printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ @@ -28,8 +30,7 @@ int __ret_warn_on = !!(condition); \ if (unlikely(__ret_warn_on)) { \ __WARN(); \ - puts("WARNING: "); \ - printf(format); \ + printf("WARNING: " format); \ } \ unlikely(__ret_warn_on); \ }) diff --git a/include/common.h b/include/common.h index 693f5bf970..4167d4676e 100644 --- a/include/common.h +++ b/include/common.h @@ -18,7 +18,7 @@ #include <linux/stddef.h> #include <asm/common.h> #include <asm/io.h> -#include <printk.h> +#include <linux/printk.h> /* * sanity check. The Linux Kernel defines only one of __LITTLE_ENDIAN and @@ -62,15 +62,6 @@ void ctrlc_handled(void); static inline void ctrlc_handled(void) { } #endif -#ifdef CONFIG_ARCH_HAS_STACK_DUMP -void dump_stack(void); -#else -static inline void dump_stack(void) -{ - printf("no stack data available\n"); -} -#endif - int parse_area_spec(const char *str, loff_t *start, loff_t *size); /* Just like simple_strtoul(), but this one honors a K/M/G suffix */ @@ -97,8 +88,6 @@ enum autoboot_state do_autoboot_countdown(void); void __noreturn start_barebox(void); void shutdown_barebox(void); -#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) - /* * The STACK_ALIGN_ARRAY macro is used to allocate a buffer on the stack that * meets a minimum alignment requirement. diff --git a/include/linux/barebox-wrapper.h b/include/linux/barebox-wrapper.h index 82c52dd933..83fa9223de 100644 --- a/include/linux/barebox-wrapper.h +++ b/include/linux/barebox-wrapper.h @@ -4,6 +4,7 @@ #include <malloc.h> #include <xfuncs.h> #include <linux/slab.h> +#include <printk.h> #define vmalloc(len) malloc(len) #define __vmalloc(len, mode, pgsz) malloc(len) @@ -13,20 +14,6 @@ static inline void vfree(const void *addr) free((void *)addr); } -#define KERN_EMERG "" /* system is unusable */ -#define KERN_ALERT "" /* action must be taken immediately */ -#define KERN_CRIT "" /* critical conditions */ -#define KERN_ERR "" /* error conditions */ -#define KERN_WARNING "" /* warning conditions */ -#define KERN_NOTICE "" /* normal but significant condition */ -#define KERN_INFO "" /* informational */ -#define KERN_DEBUG "" /* debug-level messages */ -#define KERN_CONT "" - -#define printk printf - -#define pr_warn pr_warning - #define __init #define MODULE_AUTHOR(x) diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 31345c219d..dd13bf9311 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -24,11 +24,6 @@ #define GENMASK_ULL(h, l) \ (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) -extern unsigned int __sw_hweight8(unsigned int w); -extern unsigned int __sw_hweight16(unsigned int w); -extern unsigned int __sw_hweight32(unsigned int w); -extern unsigned long __sw_hweight64(__u64 w); - /* * Include this here because some architectures need generic_ffs/fls in * scope diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 9ccdd60224..4483d33e65 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -15,6 +15,7 @@ #define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr)) +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) /* * This looks more complex than it should be. But we need to diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index b17e590f5e..f9c4645180 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -11,7 +11,7 @@ #include <driver.h> #include <errno.h> -#include <printk.h> +#include <linux/printk.h> #include <linux/types.h> #include <linux/list.h> #include <linux/mtd/mtd-abi.h> diff --git a/include/linux/phy.h b/include/linux/phy.h index a4cda3e28d..202eeb4d44 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -212,6 +212,7 @@ struct phy_device { * phy_id_mask: Defines the important bits of the phy_id * features: A list of features (speed, duplex, etc) supported * by this PHY + * @driver_data: Static driver data * * The drivers must implement config_aneg and read_status. All * other functions are optional. Note that none of these @@ -225,6 +226,7 @@ struct phy_driver { u32 phy_id; unsigned int phy_id_mask; u32 features; + const void *driver_data; /* * Called to initialize the PHY, diff --git a/include/linux/printk.h b/include/linux/printk.h new file mode 100644 index 0000000000..3f370adb90 --- /dev/null +++ b/include/linux/printk.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __LINUX_PRINTK_H +#define __LINUX_PRINTK_H + +#include <linux/list.h> +#include <printk.h> + +#define MSG_EMERG 0 /* system is unusable */ +#define MSG_ALERT 1 /* action must be taken immediately */ +#define MSG_CRIT 2 /* critical conditions */ +#define MSG_ERR 3 /* error conditions */ +#define MSG_WARNING 4 /* warning conditions */ +#define MSG_NOTICE 5 /* normal but significant condition */ +#define MSG_INFO 6 /* informational */ +#define MSG_DEBUG 7 /* debug-level messages */ +#define MSG_VDEBUG 8 /* verbose debug messages */ + +#ifdef VERBOSE_DEBUG +#define LOGLEVEL MSG_VDEBUG +#elif defined DEBUG +#define LOGLEVEL MSG_DEBUG +#else +#define LOGLEVEL CONFIG_COMPILE_LOGLEVEL +#endif + +/* debugging and troubleshooting/diagnostic helpers. */ +struct device_d; + +#ifndef CONFIG_CONSOLE_NONE +int dev_printf(int level, const struct device_d *dev, const char *format, ...) + __attribute__ ((format(__printf__, 3, 4))); +#else +static inline int dev_printf(int level, const struct device_d *dev, const char *format, ...) +{ + return 0; +} +#endif + +#if (!defined(__PBL__) && !defined(CONFIG_CONSOLE_NONE)) || \ + (defined(__PBL__) && defined(CONFIG_PBL_CONSOLE)) +int pr_print(int level, const char *format, ...) + __attribute__ ((format(__printf__, 2, 3))); +#else +static int pr_print(int level, const char *format, ...) + __attribute__ ((format(__printf__, 2, 3))); +static inline int pr_print(int level, const char *format, ...) +{ + return 0; +} +#endif + +#define __dev_printf(level, dev, format, args...) \ + ({ \ + (level) <= LOGLEVEL ? dev_printf((level), (dev), (format), ##args) : 0; \ + }) + + +#define dev_emerg(dev, format, arg...) \ + __dev_printf(0, (dev) , format , ## arg) +#define dev_alert(dev, format, arg...) \ + __dev_printf(1, (dev) , format , ## arg) +#define dev_crit(dev, format, arg...) \ + __dev_printf(2, (dev) , format , ## arg) +#define dev_err(dev, format, arg...) \ + __dev_printf(3, (dev) , format , ## arg) +#define dev_warn(dev, format, arg...) \ + __dev_printf(4, (dev) , format , ## arg) +#define dev_notice(dev, format, arg...) \ + __dev_printf(5, (dev) , format , ## arg) +#define dev_info(dev, format, arg...) \ + __dev_printf(6, (dev) , format , ## arg) +#define dev_dbg(dev, format, arg...) \ + __dev_printf(7, (dev) , format , ## arg) +#define dev_vdbg(dev, format, arg...) \ + __dev_printf(8, (dev) , format , ## arg) + +#define __pr_printk(level, format, args...) \ + ({ \ + (level) <= LOGLEVEL ? pr_print((level), (format), ##args) : 0; \ + }) + +#ifndef pr_fmt +#define pr_fmt(fmt) fmt +#endif + +#define pr_emerg(fmt, arg...) __pr_printk(0, pr_fmt(fmt), ##arg) +#define pr_alert(fmt, arg...) __pr_printk(1, pr_fmt(fmt), ##arg) +#define pr_crit(fmt, arg...) __pr_printk(2, pr_fmt(fmt), ##arg) +#define pr_err(fmt, arg...) __pr_printk(3, pr_fmt(fmt), ##arg) +#define pr_warning(fmt, arg...) __pr_printk(4, pr_fmt(fmt), ##arg) +#define pr_notice(fmt, arg...) __pr_printk(5, pr_fmt(fmt), ##arg) +#define pr_info(fmt, arg...) __pr_printk(6, pr_fmt(fmt), ##arg) +#define pr_debug(fmt, arg...) __pr_printk(7, pr_fmt(fmt), ##arg) +#define debug(fmt, arg...) __pr_printk(7, pr_fmt(fmt), ##arg) +#define pr_vdebug(fmt, arg...) __pr_printk(8, pr_fmt(fmt), ##arg) +#define pr_cont(fmt, arg...) __pr_printk(-1, fmt, ##arg) + +#define pr_warn pr_warning + +int memory_display(const void *addr, loff_t offs, unsigned nbytes, int size, + int swab); +int __pr_memory_display(int level, const void *addr, loff_t offs, unsigned nbytes, + int size, int swab, const char *format, ...); + +#define pr_memory_display(level, addr, offs, nbytes, size, swab) \ + ({ \ + (level) <= LOGLEVEL ? __pr_memory_display((level), (addr), \ + (offs), (nbytes), (size), (swab), pr_fmt("")) : 0; \ + }) + +struct log_entry { + struct list_head list; + char *msg; + void *dummy; + uint64_t timestamp; + int level; +}; + +extern struct list_head barebox_logbuf; + +extern void log_clean(unsigned int limit); + +#define BAREBOX_LOG_PRINT_RAW BIT(2) +#define BAREBOX_LOG_DIFF_TIME BIT(1) +#define BAREBOX_LOG_PRINT_TIME BIT(0) + +#define BAREBOX_LOG_PRINT_VDEBUG BIT(8) +#define BAREBOX_LOG_PRINT_DEBUG BIT(7) +#define BAREBOX_LOG_PRINT_INFO BIT(6) +#define BAREBOX_LOG_PRINT_NOTICE BIT(5) +#define BAREBOX_LOG_PRINT_WARNING BIT(4) +#define BAREBOX_LOG_PRINT_ERR BIT(3) +#define BAREBOX_LOG_PRINT_CRIT BIT(2) +#define BAREBOX_LOG_PRINT_ALERT BIT(1) +#define BAREBOX_LOG_PRINT_EMERG BIT(0) + +int log_writefile(const char *filepath); +void log_print(unsigned flags, unsigned levels); + +struct va_format { + const char *fmt; + va_list *va; +}; + +#if LOGLEVEL >= MSG_DEBUG +#define print_hex_dump_debug(prefix_str, prefix_type, rowsize, \ + groupsize, buf, len, ascii) \ + print_hex_dump(KERN_DEBUG, prefix_str, prefix_type, rowsize, \ + groupsize, buf, len, ascii) +#else +static inline void print_hex_dump_debug(const char *prefix_str, int prefix_type, + int rowsize, int groupsize, + const void *buf, size_t len, bool ascii) +{ +} +#endif + +/** + * print_hex_dump_bytes - shorthand form of print_hex_dump() with default params + * @prefix_str: string to prefix each line with; + * caller supplies trailing spaces for alignment if desired + * @prefix_type: controls whether prefix of an offset, address, or none + * is printed (%DUMP_PREFIX_OFFSET, %DUMP_PREFIX_ADDRESS, %DUMP_PREFIX_NONE) + * @buf: data blob to dump + * @len: number of bytes in the @buf + * + * Calls print_hex_dump(), with log level of KERN_DEBUG, + * rowsize of 16, groupsize of 1, and ASCII output included. + */ +#define print_hex_dump_bytes(prefix_str, prefix_type, buf, len) \ + print_hex_dump_debug(prefix_str, prefix_type, 16, 1, buf, len, true) + +#endif diff --git a/include/printk.h b/include/printk.h index f83ad3bf07..baf2cca202 100644 --- a/include/printk.h +++ b/include/printk.h @@ -2,97 +2,28 @@ #ifndef __PRINTK_H #define __PRINTK_H -#include <linux/list.h> - -#define MSG_EMERG 0 /* system is unusable */ -#define MSG_ALERT 1 /* action must be taken immediately */ -#define MSG_CRIT 2 /* critical conditions */ -#define MSG_ERR 3 /* error conditions */ -#define MSG_WARNING 4 /* warning conditions */ -#define MSG_NOTICE 5 /* normal but significant condition */ -#define MSG_INFO 6 /* informational */ -#define MSG_DEBUG 7 /* debug-level messages */ -#define MSG_VDEBUG 8 /* verbose debug messages */ - -#ifdef VERBOSE_DEBUG -#define LOGLEVEL MSG_VDEBUG -#elif defined DEBUG -#define LOGLEVEL MSG_DEBUG -#else -#define LOGLEVEL CONFIG_COMPILE_LOGLEVEL -#endif - -/* debugging and troubleshooting/diagnostic helpers. */ -struct device_d; - -#ifndef CONFIG_CONSOLE_NONE -int dev_printf(int level, const struct device_d *dev, const char *format, ...) - __attribute__ ((format(__printf__, 3, 4))); -#else -static inline int dev_printf(int level, const struct device_d *dev, const char *format, ...) -{ - return 0; -} -#endif +#define KERN_EMERG "" /* system is unusable */ +#define KERN_ALERT "" /* action must be taken immediately */ +#define KERN_CRIT "" /* critical conditions */ +#define KERN_ERR "" /* error conditions */ +#define KERN_WARNING "" /* warning conditions */ +#define KERN_NOTICE "" /* normal but significant condition */ +#define KERN_INFO "" /* informational */ +#define KERN_DEBUG "" /* debug-level messages */ +#define KERN_CONT "" #if (!defined(__PBL__) && !defined(CONFIG_CONSOLE_NONE)) || \ (defined(__PBL__) && defined(CONFIG_PBL_CONSOLE)) -int pr_print(int level, const char *format, ...) - __attribute__ ((format(__printf__, 2, 3))); +int printf(const char *fmt, ...) __attribute__ ((format(__printf__, 1, 2))); #else -static int pr_print(int level, const char *format, ...) - __attribute__ ((format(__printf__, 2, 3))); -static inline int pr_print(int level, const char *format, ...) +static int printf(const char *fmt, ...) __attribute__ ((format(__printf__, 1, 2))); +static inline int printf(const char *fmt, ...) { return 0; } #endif -#define __dev_printf(level, dev, format, args...) \ - ({ \ - (level) <= LOGLEVEL ? dev_printf((level), (dev), (format), ##args) : 0; \ - }) - - -#define dev_emerg(dev, format, arg...) \ - __dev_printf(0, (dev) , format , ## arg) -#define dev_alert(dev, format, arg...) \ - __dev_printf(1, (dev) , format , ## arg) -#define dev_crit(dev, format, arg...) \ - __dev_printf(2, (dev) , format , ## arg) -#define dev_err(dev, format, arg...) \ - __dev_printf(3, (dev) , format , ## arg) -#define dev_warn(dev, format, arg...) \ - __dev_printf(4, (dev) , format , ## arg) -#define dev_notice(dev, format, arg...) \ - __dev_printf(5, (dev) , format , ## arg) -#define dev_info(dev, format, arg...) \ - __dev_printf(6, (dev) , format , ## arg) -#define dev_dbg(dev, format, arg...) \ - __dev_printf(7, (dev) , format , ## arg) -#define dev_vdbg(dev, format, arg...) \ - __dev_printf(8, (dev) , format , ## arg) - -#define __pr_printk(level, format, args...) \ - ({ \ - (level) <= LOGLEVEL ? pr_print((level), (format), ##args) : 0; \ - }) - -#ifndef pr_fmt -#define pr_fmt(fmt) fmt -#endif - -#define pr_emerg(fmt, arg...) __pr_printk(0, pr_fmt(fmt), ##arg) -#define pr_alert(fmt, arg...) __pr_printk(1, pr_fmt(fmt), ##arg) -#define pr_crit(fmt, arg...) __pr_printk(2, pr_fmt(fmt), ##arg) -#define pr_err(fmt, arg...) __pr_printk(3, pr_fmt(fmt), ##arg) -#define pr_warning(fmt, arg...) __pr_printk(4, pr_fmt(fmt), ##arg) -#define pr_notice(fmt, arg...) __pr_printk(5, pr_fmt(fmt), ##arg) -#define pr_info(fmt, arg...) __pr_printk(6, pr_fmt(fmt), ##arg) -#define pr_debug(fmt, arg...) __pr_printk(7, pr_fmt(fmt), ##arg) -#define debug(fmt, arg...) __pr_printk(7, pr_fmt(fmt), ##arg) -#define pr_vdebug(fmt, arg...) __pr_printk(8, pr_fmt(fmt), ##arg) -#define pr_cont(fmt, arg...) __pr_printk(-1, fmt, ##arg) +#define printk printf #define printk_once(fmt, ...) \ ({ \ @@ -104,51 +35,6 @@ static inline int pr_print(int level, const char *format, ...) } \ }) -int memory_display(const void *addr, loff_t offs, unsigned nbytes, int size, - int swab); -int __pr_memory_display(int level, const void *addr, loff_t offs, unsigned nbytes, - int size, int swab, const char *format, ...); - -#define pr_memory_display(level, addr, offs, nbytes, size, swab) \ - ({ \ - (level) <= LOGLEVEL ? __pr_memory_display((level), (addr), \ - (offs), (nbytes), (size), (swab), pr_fmt("")) : 0; \ - }) - -struct log_entry { - struct list_head list; - char *msg; - void *dummy; - uint64_t timestamp; - int level; -}; - -extern struct list_head barebox_logbuf; - -extern void log_clean(unsigned int limit); - -#define BAREBOX_LOG_PRINT_RAW BIT(2) -#define BAREBOX_LOG_DIFF_TIME BIT(1) -#define BAREBOX_LOG_PRINT_TIME BIT(0) - -#define BAREBOX_LOG_PRINT_VDEBUG BIT(8) -#define BAREBOX_LOG_PRINT_DEBUG BIT(7) -#define BAREBOX_LOG_PRINT_INFO BIT(6) -#define BAREBOX_LOG_PRINT_NOTICE BIT(5) -#define BAREBOX_LOG_PRINT_WARNING BIT(4) -#define BAREBOX_LOG_PRINT_ERR BIT(3) -#define BAREBOX_LOG_PRINT_CRIT BIT(2) -#define BAREBOX_LOG_PRINT_ALERT BIT(1) -#define BAREBOX_LOG_PRINT_EMERG BIT(0) - -int log_writefile(const char *filepath); -void log_print(unsigned flags, unsigned levels); - -struct va_format { - const char *fmt; - va_list *va; -}; - enum { DUMP_PREFIX_NONE, DUMP_PREFIX_ADDRESS, @@ -161,32 +47,14 @@ extern void print_hex_dump(const char *level, const char *prefix_str, int prefix_type, int rowsize, int groupsize, const void *buf, size_t len, bool ascii); -#if LOGLEVEL >= MSG_DEBUG -#define print_hex_dump_debug(prefix_str, prefix_type, rowsize, \ - groupsize, buf, len, ascii) \ - print_hex_dump(KERN_DEBUG, prefix_str, prefix_type, rowsize, \ - groupsize, buf, len, ascii) +#ifdef CONFIG_ARCH_HAS_STACK_DUMP +void dump_stack(void); #else -static inline void print_hex_dump_debug(const char *prefix_str, int prefix_type, - int rowsize, int groupsize, - const void *buf, size_t len, bool ascii) +static inline void dump_stack(void) { + printf("no stack data available\n"); } #endif -/** - * print_hex_dump_bytes - shorthand form of print_hex_dump() with default params - * @prefix_str: string to prefix each line with; - * caller supplies trailing spaces for alignment if desired - * @prefix_type: controls whether prefix of an offset, address, or none - * is printed (%DUMP_PREFIX_OFFSET, %DUMP_PREFIX_ADDRESS, %DUMP_PREFIX_NONE) - * @buf: data blob to dump - * @len: number of bytes in the @buf - * - * Calls print_hex_dump(), with log level of KERN_DEBUG, - * rowsize of 16, groupsize of 1, and ASCII output included. - */ -#define print_hex_dump_bytes(prefix_str, prefix_type, buf, len) \ - print_hex_dump_debug(prefix_str, prefix_type, 16, 1, buf, len, true) #endif diff --git a/include/stdio.h b/include/stdio.h index 1cb11e88de..49f3d0cf77 100644 --- a/include/stdio.h +++ b/include/stdio.h @@ -4,6 +4,7 @@ #include <stdarg.h> #include <console.h> +#include <printk.h> /* * STDIO based functions (can always be used) @@ -71,8 +72,6 @@ static inline int ctrlc (void) #if (!defined(__PBL__) && !defined(CONFIG_CONSOLE_NONE)) || \ (defined(__PBL__) && defined(CONFIG_PBL_CONSOLE)) -int printf(const char *fmt, ...) __attribute__ ((format(__printf__, 1, 2))); - static inline int puts(const char *s) { return console_puts(CONSOLE_STDOUT, s); @@ -83,11 +82,6 @@ static inline void putchar(char c) console_putc(CONSOLE_STDOUT, c); } #else -static int printf(const char *fmt, ...) __attribute__ ((format(__printf__, 1, 2))); -static inline int printf(const char *fmt, ...) -{ - return 0; -} static inline int puts(const char *s) { return 0; diff --git a/lib/hexdump.c b/lib/hexdump.c index 93f345e881..fb80ef9724 100644 --- a/lib/hexdump.c +++ b/lib/hexdump.c @@ -7,7 +7,7 @@ #include <linux/types.h> #include <linux/ctype.h> #include <linux/log2.h> -#include <printk.h> +#include <linux/printk.h> #include <asm/unaligned.h> const char hex_asc[] = "0123456789abcdef"; diff --git a/lib/kasan/report.c b/lib/kasan/report.c index b7b2d032ee..79442c00f4 100644 --- a/lib/kasan/report.c +++ b/lib/kasan/report.c @@ -17,7 +17,7 @@ #include <common.h> #include <linux/bitops.h> #include <linux/kernel.h> -#include <printk.h> +#include <linux/printk.h> #include <asm-generic/sections.h> #include "kasan.h" diff --git a/lib/logo/Kconfig b/lib/logo/Kconfig index 0718053e5c..7d55f7fa27 100644 --- a/lib/logo/Kconfig +++ b/lib/logo/Kconfig @@ -1,9 +1,9 @@ menuconfig BAREBOX_LOGO bool "include barebox logos in build" help - Say yes here to build the barebox logos. This adds inkscape to the build - dependencies. The logo can be found under /logo/barebox-logo-<width>.png - in the running barebox. + Say yes here to build the barebox logos. This adds ImageMagick's + convert tool to the build dependencies. The logo can be found under + /logo/barebox-logo-<width>.png in the running barebox. if BAREBOX_LOGO diff --git a/lib/logo/Makefile b/lib/logo/Makefile index 4149d4ff6c..f08beef76b 100644 --- a/lib/logo/Makefile +++ b/lib/logo/Makefile @@ -1,17 +1,17 @@ -OPTS_barebox-logo-w64.bblogo = --export-width=64 +OPTS_barebox-logo-w64.bblogo = -resize 64 bblogo-$(CONFIG_BAREBOX_LOGO_64) += barebox-logo-w64 -OPTS_barebox-logo-w240.bblogo = --export-width=240 +OPTS_barebox-logo-w240.bblogo = -resize 240 bblogo-$(CONFIG_BAREBOX_LOGO_240) += barebox-logo-w240 -OPTS_barebox-logo-w320.bblogo = --export-width=320 +OPTS_barebox-logo-w320.bblogo = -resize 320 bblogo-$(CONFIG_BAREBOX_LOGO_320) += barebox-logo-w320 -OPTS_barebox-logo-w400.bblogo = --export-width=400 +OPTS_barebox-logo-w400.bblogo = -resize 400 bblogo-$(CONFIG_BAREBOX_LOGO_400) += barebox-logo-w400 -OPTS_barebox-logo-w640.bblogo = --export-width=640 +OPTS_barebox-logo-w640.bblogo = -resize 640 bblogo-$(CONFIG_BAREBOX_LOGO_640) += barebox-logo-w640 obj-y += $(patsubst %,%.bblogo.o,$(bblogo-y)) @@ -38,15 +38,12 @@ cmd_logo_S = \ %.bblogo.S: %.bblogo FORCE $(call if_changed,logo_S) -# Inkscape 0.92.4 supports -z -e but Inkscape 1.0 uses --export-type=png -INKSCAPEOPTS += $(call try-run, inkscape -z -e -,-z -e -,--export-type=png) -# Inkscape 1.0 supports -o - -INKSCAPEOPTS += $(call try-run, inkscape -o -,-o -,) +CONVERTOPTS += -background none -quiet_cmd_logo = LOGO.S $@ +quiet_cmd_logo = PNG $@ cmd_logo = \ ( \ - inkscape $(OPTS_$(@F)) $(INKSCAPEOPTS) $< > $@; \ + convert $(OPTS_$(@F)) $(CONVERTOPTS) $< png:$@; \ ) %.bblogo: $(srctree)/Documentation/barebox.svg FORCE @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include <linux/libfdt.h> #include <pbl.h> -#include <printk.h> +#include <linux/printk.h> void fdt_find_mem(const void *fdt, unsigned long *membase, unsigned long *memsize) { diff --git a/scripts/include/asm-generic/bitops/__ffs.h b/scripts/include/asm-generic/bitops/__ffs.h index c94175015a..15ffaa12c5 100644 --- a/scripts/include/asm-generic/bitops/__ffs.h +++ b/scripts/include/asm-generic/bitops/__ffs.h @@ -2,6 +2,7 @@ #define _TOOLS_LINUX_ASM_GENERIC_BITOPS___FFS_H_ #include <asm/types.h> +#include <asm-generic/bitsperlong.h> /** * __ffs - find first bit in word. @@ -13,7 +14,7 @@ static __always_inline unsigned long __ffs(unsigned long word) { int num = 0; -#if __BITS_PER_LONG == 64 +#if BITS_PER_LONG == 64 if ((word & 0xffffffff) == 0) { num += 32; word >>= 32; diff --git a/scripts/include/asm-generic/bitops/arch_hweight.h b/scripts/include/asm-generic/bitops/arch_hweight.h deleted file mode 100644 index 318bb2b202..0000000000 --- a/scripts/include/asm-generic/bitops/arch_hweight.h +++ /dev/null @@ -1 +0,0 @@ -#include "../../../../include/asm-generic/bitops/arch_hweight.h" diff --git a/scripts/include/asm-generic/bitops/atomic.h b/scripts/include/asm-generic/bitops/atomic.h index 4bccd7c3d5..03fe804024 100644 --- a/scripts/include/asm-generic/bitops/atomic.h +++ b/scripts/include/asm-generic/bitops/atomic.h @@ -2,21 +2,22 @@ #define _TOOLS_LINUX_ASM_GENERIC_BITOPS_ATOMIC_H_ #include <asm/types.h> +#include <asm-generic/bitsperlong.h> static inline void set_bit(int nr, unsigned long *addr) { - addr[nr / __BITS_PER_LONG] |= 1UL << (nr % __BITS_PER_LONG); + addr[nr / BITS_PER_LONG] |= 1UL << (nr % BITS_PER_LONG); } static inline void clear_bit(int nr, unsigned long *addr) { - addr[nr / __BITS_PER_LONG] &= ~(1UL << (nr % __BITS_PER_LONG)); + addr[nr / BITS_PER_LONG] &= ~(1UL << (nr % BITS_PER_LONG)); } static __always_inline int test_bit(unsigned int nr, const unsigned long *addr) { - return ((1UL << (nr % __BITS_PER_LONG)) & - (((unsigned long *)addr)[nr / __BITS_PER_LONG])) != 0; + return ((1UL << (nr % BITS_PER_LONG)) & + (((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0; } #endif /* _TOOLS_LINUX_ASM_GENERIC_BITOPS_ATOMIC_H_ */ diff --git a/scripts/include/asm-generic/bitops/const_hweight.h b/scripts/include/asm-generic/bitops/const_hweight.h deleted file mode 100644 index 0afd644aff..0000000000 --- a/scripts/include/asm-generic/bitops/const_hweight.h +++ /dev/null @@ -1 +0,0 @@ -#include "../../../../include/asm-generic/bitops/const_hweight.h" diff --git a/scripts/include/asm-generic/bitops/hweight.h b/scripts/include/asm-generic/bitops/hweight.h index 290120c01a..eb95ca33d5 100644 --- a/scripts/include/asm-generic/bitops/hweight.h +++ b/scripts/include/asm-generic/bitops/hweight.h @@ -1,7 +1,6 @@ #ifndef _TOOLS_LINUX_ASM_GENERIC_BITOPS_HWEIGHT_H_ #define _TOOLS_LINUX_ASM_GENERIC_BITOPS_HWEIGHT_H_ -#include <asm-generic/bitops/arch_hweight.h> -#include <asm-generic/bitops/const_hweight.h> +#include "../../../../include/asm-generic/bitops/hweight.h" #endif /* _TOOLS_LINUX_ASM_GENERIC_BITOPS_HWEIGHT_H_ */ diff --git a/scripts/include/asm-generic/bitsperlong.h b/scripts/include/asm-generic/bitsperlong.h new file mode 100644 index 0000000000..eb2dfd9065 --- /dev/null +++ b/scripts/include/asm-generic/bitsperlong.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __BITS_PER_LONG_H_ +#define __BITS_PER_LONG_H_ + +#ifndef __WORDSIZE +#define __WORDSIZE (__SIZEOF_LONG__ * 8) +#endif + +#define BITS_PER_LONG __WORDSIZE + +#endif diff --git a/scripts/include/linux/bitops.h b/scripts/include/linux/bitops.h index 5ad9ee1dd7..60f5c5b4f9 100644 --- a/scripts/include/linux/bitops.h +++ b/scripts/include/linux/bitops.h @@ -4,12 +4,7 @@ #include <asm/types.h> #include <linux/kernel.h> #include <linux/compiler.h> - -#ifndef __WORDSIZE -#define __WORDSIZE (__SIZEOF_LONG__ * 8) -#endif - -#define BITS_PER_LONG __WORDSIZE +#include <asm-generic/bitsperlong.h> #define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) @@ -19,10 +14,6 @@ #define BITS_TO_U32(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(u32)) #define BITS_TO_BYTES(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE) -extern unsigned int __sw_hweight8(unsigned int w); -extern unsigned int __sw_hweight16(unsigned int w); -extern unsigned int __sw_hweight32(unsigned int w); -extern unsigned long __sw_hweight64(__u64 w); /* * Include this here because some architectures need generic_ffs/fls in diff --git a/scripts/include/linux/kernel.h b/scripts/include/linux/kernel.h index dc2e64e164..f3083ff354 100644 --- a/scripts/include/linux/kernel.h +++ b/scripts/include/linux/kernel.h @@ -9,6 +9,7 @@ #define __ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) #define ALIGN(x, a) __ALIGN_MASK(x, (typeof(x))(a) - 1) #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) |