diff options
80 files changed, 775 insertions, 730 deletions
diff --git a/Documentation/boards/efi.rst b/Documentation/boards/efi.rst index 8f78a800ef..f59bb1d5ba 100644 --- a/Documentation/boards/efi.rst +++ b/Documentation/boards/efi.rst @@ -1,3 +1,5 @@ +.. _barebox_on_uefi: + barebox on (U)EFI ================= @@ -47,6 +49,31 @@ has to be put into the ``EFI/barebox/`` directory. Supported backends for EFI are raw partitions that can be discovered via a partition UUID. +With this sample script you can create bootable image and transfer it to the +flash driver: + +.. code-block:: sh + + truncate --size 128M barebox-boot.img + echo 'start=2048, type=ef' | sfdisk barebox-boot.img + + LOOPDEV=$(losetup --find --show barebox-boot.img) + partprobe ${LOOPDEV} + + # Create filesystems + mkfs.fat -F32 ${LOOPDEV}p1 + MOUNTDIR=$(mktemp -d -t demoXXXXXX) + mount ${LOOPDEV}p1 $MOUNTDIR + mkdir -p ${MOUNTDIR}/EFI/BOOT/ + cp barebox.efi ${MOUNTDIR}/EFI/BOOT/BOOTx64.EFI + if [ -d network-drivers ]; then + cp -r network-drivers ${MOUNTDIR}/ + fi + umount ${MOUNTDIR} + losetup -d ${LOOPDEV} + + dd if=barebox-boot.img of=/dev/sdX + Running EFI barebox on qemu ^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/Documentation/boards/ibase-mi991af.rst b/Documentation/boards/ibase-mi991af.rst new file mode 100644 index 0000000000..a22e5fcf79 --- /dev/null +++ b/Documentation/boards/ibase-mi991af.rst @@ -0,0 +1,43 @@ +iBASE MI991AF +============= + +The iBASE MI991AF Mini-ITX motherboard has + + * 7th/6th Generation Intel® Xeon® E3 / Core™ i7 / i5 /i3 / Pentium® / Celeron® QC/DC processors, up to 4GHz + * 2x DDR4 SO-DIMM, Max. 32GB, ECC compatible + * Intel® Processor integrated graphics device, supports DVI-D, HDMI and DisplayPort + * Dual Intel® Gigabit LAN + * 2x USB 2.0, 6x USB 3.0, 4x COM, 4x SATAIII + * 2x Mini PCI-E slots, 1x mSATA, 1x PCI-E(x16) + * Watchdog timer, Digital I/O, iAMT (11.0), TPM (1.2), iSMART + +Running barebox +--------------- + +Building the barebox image for this target is covered by the ``efi_defconfig`` + +BIOS should be configured as follow: + + * When you turn on the computer, the BIOS is immediately activated. Pressing + the <Del> key immediately allows you to enter the BIOS Setup utility. If you are + a little bit late pressing the <Del> key, POST (Power On Self Test) will + continue with its test routines, thus preventing you from invoking the Setup. + In this case restart the system by pressing the ”Reset” button or simultaneously + pressing the <Ctrl>, <Alt> and <Delete> keys. You can also restart by turning the + system Off and back On again. + * Reset BIOS settings. With this step we wont to make sure BIOS has defined common state to avoid + undocumented issues. Switch to "Save & Exit" tab, choice "Restore Defaults" + and press Enter. Answer "Yes" and press Enter again. Then choice "Save Changes and Exit" + and press Enter. + * Enable UEFI support. Switch to "Boot" tab. Choice "Boot mode select" and set it to "UEFI". + Switch in the "Save & Exit" tab to "Save Changes and Exit" and press Enter. + +To make network work in barebox you will need to prepare efi binary network drivers and put them in to +"network-drivers" directory. + +To continue please proceed with barebox :ref:`barebox_on_uefi` documentation. + +Links +----- + + * https://www.ibase.com.tw/english/ProductDetail/EmbeddedComputing/MI991 @@ -1,5 +1,5 @@ VERSION = 2017 -PATCHLEVEL = 08 +PATCHLEVEL = 09 SUBLEVEL = 0 EXTRAVERSION = NAME = None diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c index 72716b8186..58f253b1a6 100644 --- a/arch/arm/boards/at91sam9261ek/init.c +++ b/arch/arm/boards/at91sam9261ek/init.c @@ -158,22 +158,6 @@ static void ek_add_device_udc(void) {} * LCD Controller */ #if defined(CONFIG_DRIVER_VIDEO_ATMEL) -static int ek_gpio_request_output(int gpio, const char *name) -{ - int ret; - - ret = gpio_request(gpio, name); - if (ret) { - pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret); - return ret; - } - - ret = gpio_direction_output(gpio, 1); - if (ret) - pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret); - return ret; -} - /* TFT */ static struct fb_videomode at91_tft_vga_modes[] = { { @@ -195,35 +179,20 @@ static struct fb_videomode at91_tft_vga_modes[] = { | ATMEL_LCDC_DISTYPE_TFT \ | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) -static void at91_lcdc_tft_power_control(int on) -{ - if (on) - gpio_set_value(AT91_PIN_PA12, 0); /* power up */ - else - gpio_set_value(AT91_PIN_PA12, 1); /* power down */ -} - static struct atmel_lcdfb_platform_data ek_lcdc_data = { .lcdcon_is_backlight = true, .default_bpp = 16, .default_dmacon = ATMEL_LCDC_DMAEN, .default_lcdcon2 = AT91SAM9261_DEFAULT_TFT_LCDCON2, .guard_time = 1, - .atmel_lcdfb_power_control = at91_lcdc_tft_power_control, + .gpio_power_control = AT91_PIN_PA12, + .gpio_power_control_active_low = true, .mode_list = at91_tft_vga_modes, .num_modes = ARRAY_SIZE(at91_tft_vga_modes), }; -static int at91_lcdc_gpio(void) -{ - return ek_gpio_request_output(AT91_PIN_PA12, "lcdc_tft_power"); -} - static void ek_add_device_lcdc(void) { - if (at91_lcdc_gpio()) - return; - if (machine_is_at91sam9g10ek()) ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB; diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c index 682449b7be..b71cc55179 100644 --- a/arch/arm/boards/at91sam9263ek/init.c +++ b/arch/arm/boards/at91sam9263ek/init.c @@ -156,22 +156,6 @@ static void ek_add_device_udc(void) {} * LCD Controller */ #if defined(CONFIG_DRIVER_VIDEO_ATMEL) -static int ek_gpio_request_output(int gpio, const char *name) -{ - int ret; - - ret = gpio_request(gpio, name); - if (ret) { - pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret); - return ret; - } - - ret = gpio_direction_output(gpio, 1); - if (ret) - pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret); - return ret; -} - static struct fb_videomode at91_tft_vga_modes[] = { { .name = "TX09D50VM1CCA @ 60", @@ -192,11 +176,6 @@ static struct fb_videomode at91_tft_vga_modes[] = { | ATMEL_LCDC_DISTYPE_TFT \ | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) -static void at91_lcdc_power_control(int on) -{ - gpio_set_value(AT91_PIN_PA30, on); -} - /* Driver datas */ static struct atmel_lcdfb_platform_data ek_lcdc_data = { .lcdcon_is_backlight = true, @@ -204,16 +183,13 @@ static struct atmel_lcdfb_platform_data ek_lcdc_data = { .default_dmacon = ATMEL_LCDC_DMAEN, .default_lcdcon2 = AT91SAM9263_DEFAULT_LCDCON2, .guard_time = 1, - .atmel_lcdfb_power_control = at91_lcdc_power_control, + .gpio_power_control = AT91_PIN_PA30, .mode_list = at91_tft_vga_modes, .num_modes = ARRAY_SIZE(at91_tft_vga_modes), }; static void ek_add_device_lcdc(void) { - if (ek_gpio_request_output(AT91_PIN_PA30, "lcdc_power")) - return; - at91_add_device_lcdc(&ek_lcdc_data); } diff --git a/arch/arm/boards/at91sam9m10ihd/init.c b/arch/arm/boards/at91sam9m10ihd/init.c index dcd93c10b3..de601d53b3 100644 --- a/arch/arm/boards/at91sam9m10ihd/init.c +++ b/arch/arm/boards/at91sam9m10ihd/init.c @@ -177,22 +177,6 @@ static int at91sam9m10g45ek_mem_init(void) mem_initcall(at91sam9m10g45ek_mem_init); #if defined(CONFIG_DRIVER_VIDEO_ATMEL) -static int ek_gpio_request_output(int gpio, const char *name) -{ - int ret; - - ret = gpio_request(gpio, name); - if (ret) { - pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret); - return ret; - } - - ret = gpio_direction_output(gpio, 1); - if (ret) - pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret); - return ret; -} - static struct fb_videomode at91fb_default_monspecs[] = { { .name = "MULTEK", @@ -213,11 +197,6 @@ static struct fb_videomode at91fb_default_monspecs[] = { | ATMEL_LCDC_DISTYPE_TFT \ | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) -static void at91_lcdc_power_control(int on) -{ - gpio_set_value(AT91_PIN_PE6, on); -} - /* Driver datas */ static struct atmel_lcdfb_platform_data ek_lcdc_data = { .lcdcon_is_backlight = true, @@ -226,16 +205,13 @@ static struct atmel_lcdfb_platform_data ek_lcdc_data = { .default_lcdcon2 = AT91SAM9G45_DEFAULT_LCDCON2, .guard_time = 9, .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, - .atmel_lcdfb_power_control = at91_lcdc_power_control, + .gpio_power_control = AT91_PIN_PE6, .mode_list = at91fb_default_monspecs, .num_modes = ARRAY_SIZE(at91fb_default_monspecs), }; static void ek_add_device_lcd(void) { - if (ek_gpio_request_output(AT91_PIN_PE6, "lcdc_power")) - return; - at91_add_device_lcdc(&ek_lcdc_data); } #else diff --git a/arch/arm/boards/at91sam9n12ek/init.c b/arch/arm/boards/at91sam9n12ek/init.c index b9431b2ee1..bc3fb8e089 100644 --- a/arch/arm/boards/at91sam9n12ek/init.c +++ b/arch/arm/boards/at91sam9n12ek/init.c @@ -127,23 +127,6 @@ static void __init ek_add_device_ks8851(void) {} #endif /* CONFIG_DRIVER_NET_KS8851_MLL */ #if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) -static int ek_gpio_request_output(int gpio, const char *name) -{ - int ret; - - ret = gpio_request(gpio, name); - if (ret) { - pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret); - return ret; - } - - ret = gpio_direction_output(gpio, 1); - if (ret) - pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret); - return ret; -} - - /* * LCD Controller */ @@ -166,11 +149,6 @@ static struct fb_videomode at91_tft_vga_modes[] = { /* Default output mode is TFT 24 bit */ #define BPP_OUT_DEFAULT_LCDCFG5 (LCDC_LCDCFG5_MODE_OUTPUT_24BPP) -static void at91_lcdc_power_control(int on) -{ - gpio_set_value(AT91_PIN_PC25, !on); -} - /* Driver datas */ static struct atmel_lcdfb_platform_data ek_lcdc_data = { .lcdcon_is_backlight = true, @@ -179,16 +157,14 @@ static struct atmel_lcdfb_platform_data ek_lcdc_data = { .default_lcdcon2 = BPP_OUT_DEFAULT_LCDCFG5, .guard_time = 9, .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, - .atmel_lcdfb_power_control = at91_lcdc_power_control, + .gpio_power_control = AT91_PIN_PC25, + .gpio_power_control_active_low = true, .mode_list = at91_tft_vga_modes, .num_modes = ARRAY_SIZE(at91_tft_vga_modes), }; static void ek_add_device_lcdc(void) { - if (ek_gpio_request_output(AT91_PIN_PC25, "lcdc_power")) - return; - at91_add_device_lcdc(&ek_lcdc_data); } #else diff --git a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg index b1608dd9c7..6c256e8fc5 100644 --- a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg +++ b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg @@ -13,64 +13,66 @@ soc imx7 loadaddr 0x80000000 dcdofs 0x400 +#include <mach/imx7-ddr-regs.h> + wm 32 0x30340004 0x4F400005 /* Clear then set bit30 to ensure exit from DDR retention */ wm 32 0x30360388 0x40000000 wm 32 0x30360384 0x40000000 wm 32 0x30391000 0x00000002 -wm 32 0x307a0000 0x01040001 -wm 32 0x307a01a0 0x80400003 -wm 32 0x307a01a4 0x00100020 -wm 32 0x307a01a8 0x80100004 -wm 32 0x307a0064 0x00400046 -wm 32 0x307a0490 0x00000001 -wm 32 0x307a00d0 0x00020083 -wm 32 0x307a00d4 0x00690000 -wm 32 0x307a00dc 0x09300004 -wm 32 0x307a00e0 0x04080000 -wm 32 0x307a00e4 0x00100004 -wm 32 0x307a00f4 0x0000033f -wm 32 0x307a0100 0x09081109 -wm 32 0x307a0104 0x0007020d -wm 32 0x307a0108 0x03040407 -wm 32 0x307a010c 0x00002006 -wm 32 0x307a0110 0x04020205 -wm 32 0x307a0114 0x03030202 -wm 32 0x307a0120 0x00000803 -wm 32 0x307a0180 0x00800020 -wm 32 0x307a0184 0x02000100 -wm 32 0x307a0190 0x02098204 -wm 32 0x307a0194 0x00030303 -wm 32 0x307a0200 0x00000016 -wm 32 0x307a0204 0x00171717 -wm 32 0x307a0214 0x04040404 -wm 32 0x307a0218 0x0f040404 -wm 32 0x307a0240 0x06000604 -wm 32 0x307a0244 0x00000001 +wm 32 MX7_DDRC_MSTR 0x01040001 +wm 32 MX7_DDRC_DFIUPD0 0x80400003 +wm 32 MX7_DDRC_DFIUPD1 0x00100020 +wm 32 MX7_DDRC_DFIUPD2 0x80100004 +wm 32 MX7_DDRC_RFSHTMG 0x00400046 +wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001 +wm 32 MX7_DDRC_INIT0 0x00020083 +wm 32 MX7_DDRC_INIT1 0x00690000 +wm 32 MX7_DDRC_INIT3 0x09300004 +wm 32 MX7_DDRC_INIT4 0x04080000 +wm 32 MX7_DDRC_INIT5 0x00100004 +wm 32 MX7_DDRC_RANKCTL 0x0000033f +wm 32 MX7_DDRC_DRAMTMG0 0x09081109 +wm 32 MX7_DDRC_DRAMTMG1 0x0007020d +wm 32 MX7_DDRC_DRAMTMG2 0x03040407 +wm 32 MX7_DDRC_DRAMTMG3 0x00002006 +wm 32 MX7_DDRC_DRAMTMG4 0x04020205 +wm 32 MX7_DDRC_DRAMTMG5 0x03030202 +wm 32 MX7_DDRC_DRAMTMG8 0x00000803 +wm 32 MX7_DDRC_ZQCTL0 0x00800020 +wm 32 MX7_DDRC_ZQCTL1 0x02000100 +wm 32 MX7_DDRC_DFITMG0 0x02098204 +wm 32 MX7_DDRC_DFITMG1 0x00030303 +wm 32 MX7_DDRC_ADDRMAP0 0x00000016 +wm 32 MX7_DDRC_ADDRMAP1 0x00171717 +wm 32 MX7_DDRC_ADDRMAP5 0x04040404 +wm 32 MX7_DDRC_ADDRMAP6 0x0f040404 +wm 32 MX7_DDRC_ODTCFG 0x06000604 +wm 32 MX7_DDRC_ODTMAP 0x00000001 wm 32 0x30391000 0x00000000 -wm 32 0x30790000 0x17420f40 -wm 32 0x30790004 0x10210100 -wm 32 0x30790010 0x00060807 -wm 32 0x307900b0 0x1010007e -wm 32 0x3079009c 0x00000d6e -wm 32 0x30790020 0x08080808 -wm 32 0x30790030 0x08080808 -wm 32 0x30790050 0x01000010 -wm 32 0x30790050 0x00000010 +wm 32 MX7_DDR_PHY_PHY_CON0 0x17420f40 +wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100 +wm 32 MX7_DDR_PHY_PHY_CON4 0x00060807 +wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e +wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e +wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x08080808 +wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x08080808 +wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000010 +wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000010 -wm 32 0x307900c0 0x0e407304 -wm 32 0x307900c0 0x0e447304 -wm 32 0x307900c0 0x0e447306 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306 -check 32 while_any_bit_clear 0x307900c4 0x1 +check 32 while_any_bit_clear MX7_DDR_PHY_ZQ_CON1 0x1 -wm 32 0x307900c0 0x0e447304 -wm 32 0x307900c0 0x0e407304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 wm 32 0x30384130 0x00000000 wm 32 0x30340020 0x00000178 wm 32 0x30384130 0x00000002 -wm 32 0x30790018 0x0000000f +wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f -check 32 while_any_bit_clear 0x307a0004 0x1 +check 32 while_any_bit_clear MX7_DDRC_STAT 0x1 diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi index 96beef4e72..8cec1296a7 100644 --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi @@ -176,3 +176,7 @@ }; }; }; + +&ocotp { + barebox,provide-mac-address = <&fec1 0x620 &fec2 0x632>; +}; diff --git a/arch/arm/mach-at91/include/mach/barebox-arm-head.h b/arch/arm/mach-at91/include/mach/barebox-arm-head.h index d4bb96f634..e0e07500a2 100644 --- a/arch/arm/mach-at91/include/mach/barebox-arm-head.h +++ b/arch/arm/mach-at91/include/mach/barebox-arm-head.h @@ -7,13 +7,13 @@ #define AT91_EXV6 ".word _barebox_bare_init_size\n" #endif -static inline void barebox_arm_head(void) +static inline void __barebox_arm_head(void) { __asm__ __volatile__ ( #ifdef CONFIG_THUMB2_BAREBOX #error Thumb2 is not supported #else - "b barebox_arm_reset_vector\n" + "b 2f\n" "1: b 1b\n" "1: b 1b\n" "1: b 1b\n" @@ -27,7 +27,19 @@ static inline void barebox_arm_head(void) * barebox can skip relocation */ ".word _barebox_image_size\n" /* image size to copy */ + ".rept 8\n" + ".word 0x55555555\n" + ".endr\n" + "2:\n" + ); +} + +static inline void barebox_arm_head(void) +{ + __barebox_arm_head(); + __asm__ __volatile__ ( + "b barebox_arm_reset_vector\n" ); } -#endif /* __ASM_ARM_HEAD_H */ +#endif /* __MACH_ARM_HEAD_H */ diff --git a/drivers/clk/imx/clk-cpu.c b/drivers/clk/imx/clk-cpu.c index bd1749fd87..5ac0ed1789 100644 --- a/drivers/clk/imx/clk-cpu.c +++ b/drivers/clk/imx/clk-cpu.c @@ -82,14 +82,22 @@ static const struct clk_ops clk_cpu_ops = { .set_rate = clk_cpu_set_rate, }; +struct imx_clk_cpu { + struct clk_cpu cpu; + const char *parent_name; +}; + struct clk *imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step) { + struct imx_clk_cpu *icpu; struct clk_cpu *cpu; int ret; - cpu = xzalloc(sizeof(*cpu)); + icpu = xzalloc(sizeof(*icpu)); + icpu->parent_name = parent_name; + cpu = &icpu->cpu; cpu->div = div; cpu->mux = mux; @@ -99,7 +107,7 @@ struct clk *imx_clk_cpu(const char *name, const char *parent_name, cpu->clk.name = name; cpu->clk.ops = &clk_cpu_ops; cpu->clk.flags = 0; - cpu->clk.parent_names = &parent_name; + cpu->clk.parent_names = &icpu->parent_name; cpu->clk.num_parents = 1; ret = clk_register(&cpu->clk); diff --git a/drivers/gpio/gpio-clps711x.c b/drivers/gpio/gpio-clps711x.c index d71c606690..769e6ca4f7 100644 --- a/drivers/gpio/gpio-clps711x.c +++ b/drivers/gpio/gpio-clps711x.c @@ -74,6 +74,7 @@ out_err: static struct of_device_id __maybe_unused clps711x_gpio_dt_ids[] = { { .compatible = "cirrus,clps711x-gpio", }, + { /* sentinel */ } }; static struct driver_d clps711x_gpio_driver = { diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c index 876699a02d..78198798a5 100644 --- a/drivers/spi/imx_spi.c +++ b/drivers/spi/imx_spi.c @@ -32,14 +32,17 @@ #include <linux/err.h> #include <clock.h> +/* time to wait for STAT_RR getting set */ +#define IMX_SPI_RR_TIMEOUT 10000 /* ns */ + struct imx_spi { struct spi_master master; int *cs_array; void __iomem *regs; struct clk *clk; - unsigned int (*xchg_single)(struct imx_spi *imx, u32 data); - void (*do_transfer)(struct spi_device *spi); + int (*xchg_single)(struct imx_spi *imx, u32 txdata, u32 *rxdata); + int (*do_transfer)(struct spi_device *spi); void (*chipselect)(struct spi_device *spi, int active); const void *tx_buf; @@ -49,8 +52,8 @@ struct imx_spi { }; struct spi_imx_devtype_data { - unsigned int (*xchg_single)(struct imx_spi *imx, u32 data); - void (*do_transfer)(struct spi_device *spi); + int (*xchg_single)(struct imx_spi *imx, u32 txdata, u32 *rxdata); + int (*do_transfer)(struct spi_device *spi); void (*chipselect)(struct spi_device *spi, int active); void (*init)(struct imx_spi *imx); }; @@ -86,21 +89,29 @@ static unsigned int imx_spi_maybe_reverse_bits(struct spi_device *spi, unsigned return result; } -static unsigned int cspi_0_0_xchg_single(struct imx_spi *imx, unsigned int data) +static int cspi_0_0_xchg_single(struct imx_spi *imx, u32 txdata, u32 *rxdata) { void __iomem *base = imx->regs; + int ret; unsigned int cfg_reg = readl(base + CSPI_0_0_CTRL); - writel(data, base + CSPI_0_0_TXDATA); + writel(txdata, base + CSPI_0_0_TXDATA); cfg_reg |= CSPI_0_0_CTRL_XCH; writel(cfg_reg, base + CSPI_0_0_CTRL); - while (!(readl(base + CSPI_0_0_INT) & CSPI_0_0_STAT_RR)); + ret = wait_on_timeout(IMX_SPI_RR_TIMEOUT, + readl(base + CSPI_0_0_INT) & CSPI_0_0_STAT_RR); + if (ret) { + dev_err(imx->master.dev, "Timeout waiting for received data\n"); + return ret; + } + + *rxdata = readl(base + CSPI_0_0_RXDATA); - return readl(base + CSPI_0_0_RXDATA); + return 0; } static void cspi_0_0_chipselect(struct spi_device *spi, int is_active) @@ -152,22 +163,28 @@ static void cspi_0_0_init(struct imx_spi *imx) } while (readl(base + CSPI_0_0_RESET) & CSPI_0_0_RESET_START); } -static unsigned int cspi_0_7_xchg_single(struct imx_spi *imx, unsigned int data) +static int cspi_0_7_xchg_single(struct imx_spi *imx, u32 txdata, u32 *rxdata) { void __iomem *base = imx->regs; + int ret; unsigned int cfg_reg = readl(base + CSPI_0_7_CTRL); - writel(data, base + CSPI_0_7_TXDATA); + writel(txdata, base + CSPI_0_7_TXDATA); cfg_reg |= CSPI_0_7_CTRL_XCH; writel(cfg_reg, base + CSPI_0_7_CTRL); - while (!(readl(base + CSPI_0_7_STAT) & CSPI_0_7_STAT_RR)) - ; + ret = wait_on_timeout(IMX_SPI_RR_TIMEOUT, + readl(base + CSPI_0_7_STAT) & CSPI_0_7_STAT_RR); + if (ret) { + dev_err(imx->master.dev, "Timeout waiting for received data\n"); + return ret; + } - return readl(base + CSPI_0_7_RXDATA); + *rxdata = readl(base + CSPI_0_7_RXDATA); + return 0; } /* MX1, MX31, MX35, MX51 CSPI */ @@ -242,15 +259,23 @@ static void cspi_0_7_init(struct imx_spi *imx) readl(base + CSPI_0_7_RXDATA); } -static unsigned int cspi_2_3_xchg_single(struct imx_spi *imx, unsigned int data) +static int cspi_2_3_xchg_single(struct imx_spi *imx, u32 txdata, u32 *rxdata) { void __iomem *base = imx->regs; + int ret; + + writel(txdata, base + CSPI_2_3_TXDATA); - writel(data, base + CSPI_2_3_TXDATA); + ret = wait_on_timeout(IMX_SPI_RR_TIMEOUT, + readl(base + CSPI_2_3_STAT) & CSPI_2_3_STAT_RR); + if (ret) { + dev_err(imx->master.dev, "Timeout waiting for received data\n"); + return ret; + } - while (!(readl(base + CSPI_2_3_STAT) & CSPI_2_3_STAT_RR)); + *rxdata = readl(base + CSPI_2_3_RXDATA); - return readl(base + CSPI_2_3_RXDATA); + return 0; } static unsigned int cspi_2_3_clkdiv(unsigned int fin, unsigned int fspi) @@ -336,16 +361,20 @@ static void cspi_2_3_chipselect(struct spi_device *spi, int is_active) gpio_set_value(gpio, gpio_cs); } -static u32 imx_xchg_single(struct spi_device *spi, u32 tx_val) +static int imx_xchg_single(struct spi_device *spi, u32 tx_val, u32* rx_val) { - u32 rx_val; struct imx_spi *imx = container_of(spi->master, struct imx_spi, master); - + u32 local_rx_val; + int ret; tx_val = imx_spi_maybe_reverse_bits(spi, tx_val); - rx_val = imx->xchg_single(imx, tx_val); + ret = imx->xchg_single(imx, tx_val, &local_rx_val); + if (ret) + return ret; - return imx_spi_maybe_reverse_bits(spi, rx_val); + *rx_val = imx_spi_maybe_reverse_bits(spi, local_rx_val); + + return 0; } static void cspi_2_3_init(struct imx_spi *imx) @@ -355,18 +384,21 @@ static void cspi_2_3_init(struct imx_spi *imx) writel(0, base + CSPI_2_3_CTRL); } -static void imx_spi_do_transfer(struct spi_device *spi) +static int imx_spi_do_transfer(struct spi_device *spi) { struct imx_spi *imx = container_of(spi->master, struct imx_spi, master); unsigned i; + u32 rx_val; + int ret; if (imx->bits_per_word <= 8) { const u8 *tx_buf = imx->tx_buf; u8 *rx_buf = imx->rx_buf; - u8 rx_val; for (i = 0; i < imx->xfer_len; i++) { - rx_val = imx_xchg_single(spi, tx_buf ? tx_buf[i] : 0); + ret = imx_xchg_single(spi, tx_buf ? tx_buf[i] : 0, &rx_val); + if (ret) + return ret; if (rx_buf) rx_buf[i] = rx_val; @@ -374,10 +406,11 @@ static void imx_spi_do_transfer(struct spi_device *spi) } else if (imx->bits_per_word <= 16) { const u16 *tx_buf = imx->tx_buf; u16 *rx_buf = imx->rx_buf; - u16 rx_val; for (i = 0; i < imx->xfer_len >> 1; i++) { - rx_val = imx_xchg_single(spi, tx_buf ? tx_buf[i] : 0); + ret = imx_xchg_single(spi, tx_buf ? tx_buf[i] : 0, &rx_val); + if (ret) + return ret; if (rx_buf) rx_buf[i] = rx_val; @@ -385,15 +418,18 @@ static void imx_spi_do_transfer(struct spi_device *spi) } else if (imx->bits_per_word <= 32) { const u32 *tx_buf = imx->tx_buf; u32 *rx_buf = imx->rx_buf; - u32 rx_val; for (i = 0; i < imx->xfer_len >> 2; i++) { - rx_val = imx_xchg_single(spi, tx_buf ? tx_buf[i] : 0); + ret = imx_xchg_single(spi, tx_buf ? tx_buf[i] : 0, &rx_val); + if (ret) + return ret; if (rx_buf) rx_buf[i] = rx_val; } } + + return 0; } static int cspi_2_3_xchg_burst(struct spi_device *spi) @@ -448,7 +484,7 @@ static int cspi_2_3_xchg_burst(struct spi_device *spi) return now; } -static void cspi_2_3_do_transfer(struct spi_device *spi) +static int cspi_2_3_do_transfer(struct spi_device *spi) { struct imx_spi *imx = container_of(spi->master, struct imx_spi, master); u32 ctrl; @@ -457,14 +493,14 @@ static void cspi_2_3_do_transfer(struct spi_device *spi) while (cspi_2_3_xchg_burst(spi) > 0); if (!imx->xfer_len) - return; + return 0; ctrl = readl(imx->regs + CSPI_2_3_CTRL); ctrl &= ~(0xfff << CSPI_2_3_CTRL_BL_OFFSET); ctrl |= (spi->bits_per_word - 1) << CSPI_2_3_CTRL_BL_OFFSET; writel(ctrl, imx->regs + CSPI_2_3_CTRL); - imx_spi_do_transfer(spi); + return imx_spi_do_transfer(spi); } static int imx_spi_transfer(struct spi_device *spi, struct spi_message *mesg) @@ -473,6 +509,7 @@ static int imx_spi_transfer(struct spi_device *spi, struct spi_message *mesg) struct spi_transfer *t; unsigned int cs_change; const int nsecs = 50; + int ret; imx->chipselect(spi, 1); @@ -494,7 +531,9 @@ static int imx_spi_transfer(struct spi_device *spi, struct spi_message *mesg) imx->rx_buf = t->rx_buf; imx->xfer_len = t->len; imx->bits_per_word = spi->bits_per_word; - imx->do_transfer(spi); + ret = imx->do_transfer(spi); + if (ret) + return ret; mesg->actual_length += t->len; diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c index 5f6bebc733..18427114d1 100644 --- a/drivers/usb/gadget/at91_udc.c +++ b/drivers/usb/gadget/at91_udc.c @@ -21,7 +21,7 @@ #include <clock.h> #include <usb/ch9.h> #include <usb/gadget.h> -#include <gpio.h> +#include <of_gpio.h> #include <linux/list.h> #include <linux/clk.h> @@ -1375,6 +1375,22 @@ static void at91_udc_gadget_poll(struct usb_gadget *gadget) at91_udc_irq(udc); } +static void __init at91udc_of_init(struct at91_udc *udc, struct device_node *np) +{ + enum of_gpio_flags flags; + struct at91_udc_data *board; + + board = &udc->board; + + board->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0, + &flags); + board->vbus_active_low = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0; + + board->pullup_pin = of_get_named_gpio_flags(np, "atmel,pullup-gpio", 0, + &flags); + board->pullup_active_low = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0; +} + /*-------------------------------------------------------------------------*/ static int __init at91udc_probe(struct device_d *dev) @@ -1382,18 +1398,29 @@ static int __init at91udc_probe(struct device_d *dev) struct resource *iores; struct at91_udc *udc = &controller; int retval; - - if (!dev->platform_data) { - /* small (so we copy it) but critical! */ - DBG(udc, "missing platform_data\n"); - return -ENODEV; - } + const char *iclk_name; + const char *fclk_name; /* init software state */ udc->dev = dev; - udc->board = *(struct at91_udc_data *) dev->platform_data; udc->enabled = 0; + if (dev->platform_data) { + /* small (so we copy it) */ + udc->board = *(struct at91_udc_data *)dev->platform_data; + iclk_name = "udc_clk"; + fclk_name = "udpck"; + } else { + if (!IS_ENABLED(CONFIG_OFDEVICE) || !dev->device_node) { + dev_err(dev, "no DT and no platform_data\n"); + return -ENODEV; + } + + at91udc_of_init(udc, dev->device_node); + iclk_name = "pclk"; + fclk_name = "hclk"; + } + /* rm9200 needs manual D+ pullup; off by default */ if (cpu_is_at91rm9200()) { if (udc->board.pullup_pin <= 0) { @@ -1435,8 +1462,8 @@ static int __init at91udc_probe(struct device_d *dev) udc_reinit(udc); /* get interface and function clocks */ - udc->iclk = clk_get(dev, "udc_clk"); - udc->fclk = clk_get(dev, "udpck"); + udc->iclk = clk_get(dev, iclk_name); + udc->fclk = clk_get(dev, fclk_name); if (IS_ERR(udc->iclk) || IS_ERR(udc->fclk)) { DBG(udc, "clocks missing\n"); retval = -ENODEV; @@ -1491,10 +1518,17 @@ fail0: DBG(udc, "%s probe failed, %d\n", driver_name, retval); return retval; } - +static const struct of_device_id at91_udc_dt_ids[] = { + { .compatible = "atmel,at91rm9200-udc" }, + { .compatible = "atmel,at91sam9260-udc" }, + { .compatible = "atmel,at91sam9261-udc" }, + { .compatible = "atmel,at91sam9263-udc" }, + { /* sentinel */ } +}; static struct driver_d at91_udc_driver = { .name = driver_name, .probe = at91udc_probe, + .of_compatible = DRV_OF_COMPAT(at91_udc_dt_ids), }; device_platform_driver(at91_udc_driver); diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index f7aab7f454..5d130f598e 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -178,7 +178,6 @@ static u32 atmel_hlcdfb_get_rgbmode(struct fb_info *info) static void atmel_hlcdfb_setup_core_base(struct fb_info *info) { struct atmel_lcdfb_info *sinfo = info->priv; - struct atmel_lcdfb_platform_data *pdata = sinfo->pdata; struct fb_videomode *mode = info->mode; unsigned long value; unsigned long clk_value_khz; @@ -205,8 +204,8 @@ static void atmel_hlcdfb_setup_core_base(struct fb_info *info) lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG0, value); /* Initialize control register 5 */ - /* In 9x5, the default_lcdcon2 will use for LCDCFG5 */ - value = pdata->default_lcdcon2; + /* In 9x5, the lcdcon2 will use for LCDCFG5 */ + value = sinfo->lcdcon2; value |= (sinfo->guard_time << LCDC_LCDCFG5_GUARDTIME_OFFSET) | LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS; diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index a0e41d10c2..7c05e857b3 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -81,9 +81,7 @@ static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo, u32 flags) static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo) { - struct atmel_lcdfb_platform_data *pdata = sinfo->pdata; - - lcdc_writel(sinfo, ATMEL_LCDC_DMACON, pdata->default_dmacon); + lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->dmacon); lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, (sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR); @@ -123,7 +121,6 @@ static void atmel_lcdfb_limit_screeninfo(struct fb_videomode *mode) static void atmel_lcdfb_setup_core(struct fb_info *info) { struct atmel_lcdfb_info *sinfo = info->priv; - struct atmel_lcdfb_platform_data *pdata = sinfo->pdata; struct fb_videomode *mode = info->mode; unsigned long clk_value_khz; unsigned long pix_factor = 2; @@ -159,7 +156,7 @@ static void atmel_lcdfb_setup_core(struct fb_info *info) } /* Initialize control register 2 */ - value = pdata->default_lcdcon2; + value = sinfo->lcdcon2; if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT)) value |= ATMEL_LCDC_INVLINE_INVERTED; @@ -246,8 +243,20 @@ static int atmel_lcdc_probe(struct device_d *dev) return atmel_lcdc_register(dev, &atmel_lcdfb_data); } +static __maybe_unused struct of_device_id atmel_lcdfb_compatible[] = { + { .compatible = "atmel,at91sam9261-lcdc", }, + { .compatible = "atmel,at91sam9263-lcdc", }, + { .compatible = "atmel,at91sam9g10-lcdc", }, + { .compatible = "atmel,at91sam9g45-lcdc", }, + { .compatible = "atmel,at91sam9g45es-lcdc", }, + { .compatible = "atmel,at91sam9rl-lcdc", }, + { .compatible = "atmel,at32ap-lcdc", }, + { /* sentinel */ } +}; + static struct driver_d atmel_lcdc_driver = { .name = "atmel_lcdfb", .probe = atmel_lcdc_probe, + .of_compatible = DRV_OF_COMPAT(atmel_lcdfb_compatible), }; device_platform_driver(atmel_lcdc_driver); diff --git a/drivers/video/atmel_lcdfb.h b/drivers/video/atmel_lcdfb.h index ea4c7e647a..a011d42019 100644 --- a/drivers/video/atmel_lcdfb.h +++ b/drivers/video/atmel_lcdfb.h @@ -21,10 +21,16 @@ struct atmel_lcdfb_info { unsigned int guard_time; unsigned int smem_len; + unsigned int lcdcon2; + unsigned int dmacon; + unsigned int lcd_wiring_mode; + bool have_intensity_bit; + + int gpio_power_control; + bool gpio_power_control_active_low; struct clk *bus_clk; struct clk *lcdc_clk; - struct atmel_lcdfb_platform_data *pdata; struct atmel_lcdfb_devdata *dev_data; void *dma_desc; }; diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c index f6c5d7c051..45b0c63d06 100644 --- a/drivers/video/atmel_lcdfb_core.c +++ b/drivers/video/atmel_lcdfb_core.c @@ -19,6 +19,8 @@ */ #include <common.h> +#include <of_gpio.h> +#include <gpio.h> #include <dma.h> #include <io.h> #include <linux/err.h> @@ -39,13 +41,17 @@ static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo) clk_disable(sinfo->lcdc_clk); } -static void atmel_lcdc_power_controller(struct fb_info *fb_info, int i) +static void atmel_lcdc_power_controller(struct fb_info *fb_info, int on) { struct atmel_lcdfb_info *sinfo = fb_info->priv; - struct atmel_lcdfb_platform_data *pdata = sinfo->pdata; - if (pdata->atmel_lcdfb_power_control) - pdata->atmel_lcdfb_power_control(1); + if (sinfo->gpio_power_control < 0) + return; + + if (sinfo->gpio_power_control_active_low) + gpio_set_value(sinfo->gpio_power_control, !on); + else + gpio_set_value(sinfo->gpio_power_control, on); } /** @@ -69,7 +75,6 @@ static int atmel_lcdfb_check_var(struct fb_info *info) { struct device_d *dev = &info->dev; struct atmel_lcdfb_info *sinfo = info->priv; - struct atmel_lcdfb_platform_data *pdata = sinfo->pdata; struct fb_videomode *mode = info->mode; unsigned long clk_value_khz; @@ -126,11 +131,11 @@ static int atmel_lcdfb_check_var(struct fb_info *info) break; case 16: /* Older SOCs use IBGR:555 rather than BGR:565. */ - if (pdata->have_intensity_bit) + if (sinfo->have_intensity_bit) info->green.length = 5; else info->green.length = 6; - if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) { + if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) { /* RGB:5X5 mode */ info->red.offset = info->green.length + 5; info->blue.offset = 0; @@ -147,7 +152,7 @@ static int atmel_lcdfb_check_var(struct fb_info *info) info->transp.length = 8; /* fall through */ case 24: - if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) { + if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) { /* RGB:888 mode */ info->red.offset = 16; info->blue.offset = 0; @@ -243,42 +248,228 @@ static struct fb_ops atmel_lcdc_ops = { .fb_disable = atmel_lcdc_disable_controller, }; -int atmel_lcdc_register(struct device_d *dev, struct atmel_lcdfb_devdata *data) +static int power_control_init(struct device_d *dev, + struct atmel_lcdfb_info *sinfo, + int gpio, + bool active_low) { - struct resource *iores; - struct atmel_lcdfb_info *sinfo; - struct atmel_lcdfb_platform_data *pdata = dev->platform_data; - int ret = 0; - struct fb_info *info; + int ret; + const char *name = "lcdc_power"; - if (!pdata) { - dev_err(dev, "missing platform_data\n"); - return -EINVAL; + sinfo->gpio_power_control = gpio; + sinfo->gpio_power_control_active_low = active_low; + + /* If no GPIO specified then stop */ + if (!gpio_is_valid(gpio)) + return 0; + + ret = gpio_request(gpio, name); + if (ret) { + dev_err(dev, "%s: can not request gpio %d (%d)\n", + name, gpio, ret); + return ret; + } + ret = gpio_direction_output(gpio, 1); + if (ret) { + dev_err(dev, "%s: can not configure gpio %d as output (%d)\n", + name, gpio, ret); + return ret; } - sinfo = xzalloc(sizeof(*sinfo)); - sinfo->pdata = pdata; + return ret; +} + +/* + * Syntax: atmel,lcd-wiring-mode: lcd wiring mode "RGB", "BRG", "IRGB", "IBRG" + * The optional "I" indicates that green has an intensity bit as used by some + * older displays + */ +static int of_get_wiring_mode(struct device_node *np, + struct atmel_lcdfb_info *sinfo) +{ + const char *mode; + int ret; + + ret = of_property_read_string(np, "atmel,lcd-wiring-mode", &mode); + if (ret < 0) { + /* Not present, use defaults */ + sinfo->lcd_wiring_mode = ATMEL_LCDC_WIRING_BGR; + sinfo->have_intensity_bit = false; + return 0; + } + + if (!strcasecmp(mode, "BGR")) { + sinfo->lcd_wiring_mode = ATMEL_LCDC_WIRING_BGR; + sinfo->have_intensity_bit = false; + } else if (!strcasecmp(mode, "RGB")) { + sinfo->lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB; + sinfo->have_intensity_bit = false; + } else if (!strcasecmp(mode, "IBGR")) { + sinfo->lcd_wiring_mode = ATMEL_LCDC_WIRING_BGR; + sinfo->have_intensity_bit = true; + } else if (!strcasecmp(mode, "IRGB")) { + sinfo->lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB; + sinfo->have_intensity_bit = true; + } else { + return -ENODEV; + } + return 0; +} + +static int of_get_power_control(struct device_d *dev, + struct device_node *np, + struct atmel_lcdfb_info *sinfo) +{ + enum of_gpio_flags flags; + bool active_low; + int gpio; + + gpio = of_get_named_gpio_flags(np, "atmel,power-control-gpio", 0, &flags); + if (!gpio_is_valid(gpio)) { + /* No power control - ignore */ + return 0; + } + active_low = (flags & OF_GPIO_ACTIVE_LOW ? true : false); + return power_control_init(dev, sinfo, gpio, active_low); +} + +static int lcdfb_of_init(struct device_d *dev, struct atmel_lcdfb_info *sinfo) +{ + struct fb_info *info = &sinfo->info; + struct display_timings *modes; + struct device_node *display; + int ret; + + /* Required properties */ + display = of_parse_phandle(dev->device_node, "display", 0); + if (!display) { + dev_err(dev, "no display phandle\n"); + return -ENOENT; + } + ret = of_property_read_u32(display, "atmel,guard-time", &sinfo->guard_time); + if (ret < 0) { + dev_err(dev, "failed to get atmel,guard-time property\n"); + goto err; + } + ret = of_property_read_u32(display, "atmel,lcdcon2", &sinfo->lcdcon2); + if (ret < 0) { + dev_err(dev, "failed to get atmel,lcdcon2 property\n"); + goto err; + } + ret = of_property_read_u32(display, "atmel,dmacon", &sinfo->dmacon); + if (ret < 0) { + dev_err(dev, "failed to get atmel,dmacon property\n"); + goto err; + } + ret = of_property_read_u32(display, "bits-per-pixel", &info->bits_per_pixel); + if (ret < 0) { + dev_err(dev, "failed to get bits-per-pixel property\n"); + goto err; + } + modes = of_get_display_timings(display); + if (IS_ERR(modes)) { + dev_err(dev, "unable to parse display timings\n"); + ret = PTR_ERR(modes); + goto err; + } + info->modes.modes = modes->modes; + info->modes.num_modes = modes->num_modes; + + /* Optional properties */ + ret = of_get_wiring_mode(display, sinfo); + if (ret < 0) { + dev_err(dev, "failed to get atmel,lcd-wiring-mode property\n"); + goto err; + } + ret = of_get_power_control(dev, display, sinfo); + if (ret < 0) { + dev_err(dev, "failed to get power control gpio\n"); + goto err; + } + return 0; +err: + return ret; +} + +static int lcdfb_pdata_init(struct device_d *dev, struct atmel_lcdfb_info *sinfo) +{ + struct atmel_lcdfb_platform_data *pdata; + struct fb_info *info; + bool active_low; + int gpio; + int ret; + + pdata = dev->platform_data; + + /* If gpio == 0 (default in pdata) then we assume no power control */ + gpio = pdata->gpio_power_control; + if (gpio == 0) + gpio = -1; + + active_low = pdata->gpio_power_control_active_low; + ret = power_control_init(dev, sinfo, gpio, active_low); + if (ret) + goto err; + sinfo->guard_time = pdata->guard_time; + sinfo->lcdcon2 = pdata->default_lcdcon2; + sinfo->dmacon = pdata->default_dmacon; + sinfo->lcd_wiring_mode = pdata->lcd_wiring_mode; + sinfo->have_intensity_bit = pdata->have_intensity_bit; + + info = &sinfo->info; + info->modes.modes = pdata->mode_list; + info->modes.num_modes = pdata->num_modes; + info->mode = &info->modes.modes[0]; + info->xres = info->mode->xres; + info->yres = info->mode->yres; + info->bits_per_pixel = pdata->default_bpp; + +err: + return ret; +} + +int atmel_lcdc_register(struct device_d *dev, struct atmel_lcdfb_devdata *data) +{ + struct atmel_lcdfb_info *sinfo; + const char *bus_clk_name; + struct resource *iores; + struct fb_info *info; + int ret = 0; + iores = dev_request_mem_resource(dev, 0); if (IS_ERR(iores)) return PTR_ERR(iores); - sinfo->mmio = IOMEM(iores->start); + sinfo = xzalloc(sizeof(*sinfo)); sinfo->dev_data = data; + sinfo->mmio = IOMEM(iores->start); - /* just init */ info = &sinfo->info; info->priv = sinfo; info->fbops = &atmel_lcdc_ops; - info->modes.modes = pdata->mode_list; - info->modes.num_modes = pdata->num_modes; - info->mode = &info->modes.modes[0]; - info->xres = info->mode->xres; - info->yres = info->mode->yres; - info->bits_per_pixel = pdata->default_bpp; + + if (dev->platform_data) { + ret = lcdfb_pdata_init(dev, sinfo); + if (ret) { + dev_err(dev, "failed to init lcdfb from pdata\n"); + goto err; + } + bus_clk_name = "hck1"; + } else { + if (!IS_ENABLED(CONFIG_OFDEVICE) || !dev->device_node) + return -EINVAL; + + ret = lcdfb_of_init(dev, sinfo); + if (ret) { + dev_err(dev, "failed to init lcdfb from DT\n"); + goto err; + } + bus_clk_name = "hclk"; + } /* Enable LCDC Clocks */ - sinfo->bus_clk = clk_get(dev, "hck1"); + sinfo->bus_clk = clk_get(dev, bus_clk_name); if (IS_ERR(sinfo->bus_clk)) { ret = PTR_ERR(sinfo->bus_clk); goto err; diff --git a/dts/Bindings/ata/sata_rcar.txt b/dts/Bindings/ata/sata_rcar.txt index 0764f9ab63..e20eac7a30 100644 --- a/dts/Bindings/ata/sata_rcar.txt +++ b/dts/Bindings/ata/sata_rcar.txt @@ -1,14 +1,22 @@ * Renesas R-Car SATA Required properties: -- compatible : should contain one of the following: +- compatible : should contain one or more of the following: - "renesas,sata-r8a7779" for R-Car H1 - ("renesas,rcar-sata" is deprecated) - "renesas,sata-r8a7790-es1" for R-Car H2 ES1 - "renesas,sata-r8a7790" for R-Car H2 other than ES1 - "renesas,sata-r8a7791" for R-Car M2-W - "renesas,sata-r8a7793" for R-Car M2-N - "renesas,sata-r8a7795" for R-Car H3 + - "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device + - "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device + - "renesas,rcar-sata" is deprecated + + When compatible with the generic version nodes + must list the SoC-specific version corresponding + to the platform first followed by the generic + version. + - reg : address and length of the SATA registers; - interrupts : must consist of one interrupt specifier. - clocks : must contain a reference to the functional clock. @@ -16,7 +24,7 @@ Required properties: Example: sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7791"; + compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; reg = <0 0xee300000 0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/Bindings/crypto/inside-secure-safexcel.txt b/dts/Bindings/crypto/inside-secure-safexcel.txt index f69773f425..941bb6a6fb 100644 --- a/dts/Bindings/crypto/inside-secure-safexcel.txt +++ b/dts/Bindings/crypto/inside-secure-safexcel.txt @@ -8,7 +8,6 @@ Required properties: Optional properties: - clocks: Reference to the crypto engine clock. -- dma-mask: The address mask limitation. Defaults to 64. Example: @@ -24,6 +23,5 @@ Example: interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cpm_syscon0 1 26>; - dma-mask = <0xff 0xffffffff>; status = "disabled"; }; diff --git a/dts/Bindings/gpio/gpio-exar.txt b/dts/Bindings/gpio/gpio-exar.txt new file mode 100644 index 0000000000..4540d61824 --- /dev/null +++ b/dts/Bindings/gpio/gpio-exar.txt @@ -0,0 +1,5 @@ +Exportable MPIO interface of Exar UART chips + +Required properties of the device: + - exar,first-pin: first exportable pins (0..15) + - ngpios: number of exportable pins (1..16) diff --git a/dts/Bindings/gpu/arm,mali-midgard.txt b/dts/Bindings/gpu/arm,mali-midgard.txt index d3b6e1a471..5aa5926029 100644 --- a/dts/Bindings/gpu/arm,mali-midgard.txt +++ b/dts/Bindings/gpu/arm,mali-midgard.txt @@ -40,7 +40,7 @@ Optional properties: Example for a Mali-T760: gpu@ffa30000 { - compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard"; + compatible = "rockchip,rk3288-mali", "arm,mali-t760"; reg = <0xffa30000 0x10000>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/Bindings/mmc/exynos-dw-mshc.txt b/dts/Bindings/mmc/exynos-dw-mshc.txt index aad9844278..a58c173b7a 100644 --- a/dts/Bindings/mmc/exynos-dw-mshc.txt +++ b/dts/Bindings/mmc/exynos-dw-mshc.txt @@ -78,7 +78,6 @@ Example: }; dwmmc0@12200000 { - num-slots = <1>; cap-mmc-highspeed; cap-sd-highspeed; broken-cd; diff --git a/dts/Bindings/mmc/img-dw-mshc.txt b/dts/Bindings/mmc/img-dw-mshc.txt index 85de99fcaa..c54e577eea 100644 --- a/dts/Bindings/mmc/img-dw-mshc.txt +++ b/dts/Bindings/mmc/img-dw-mshc.txt @@ -24,6 +24,5 @@ Example: fifo-depth = <0x20>; bus-width = <4>; - num-slots = <1>; disable-wp; }; diff --git a/dts/Bindings/mmc/k3-dw-mshc.txt b/dts/Bindings/mmc/k3-dw-mshc.txt index 8af1afcb86..07242d1417 100644 --- a/dts/Bindings/mmc/k3-dw-mshc.txt +++ b/dts/Bindings/mmc/k3-dw-mshc.txt @@ -36,7 +36,6 @@ Example: /* Board portion */ dwmmc0@fcd03000 { - num-slots = <1>; vmmc-supply = <&ldo12>; fifo-depth = <0x100>; pinctrl-names = "default"; @@ -52,7 +51,6 @@ Example: dwmmc_1: dwmmc1@f723e000 { compatible = "hisilicon,hi6220-dw-mshc"; - num-slots = <0x1>; bus-width = <0x4>; disable-wp; cap-sd-highspeed; diff --git a/dts/Bindings/mmc/synopsys-dw-mshc.txt b/dts/Bindings/mmc/synopsys-dw-mshc.txt index 9cb55ca574..ef3e5f1406 100644 --- a/dts/Bindings/mmc/synopsys-dw-mshc.txt +++ b/dts/Bindings/mmc/synopsys-dw-mshc.txt @@ -12,12 +12,12 @@ Required Properties: * #address-cells: should be 1. * #size-cells: should be 0. -# Slots: The slot specific information are contained within child-nodes with - each child-node representing a supported slot. There should be atleast one - child node representing a card slot. The name of the child node representing - the slot is recommended to be slot@n where n is the unique number of the slot - connected to the controller. The following are optional properties which - can be included in the slot child node. +# Slots (DEPRECATED): The slot specific information are contained within + child-nodes with each child-node representing a supported slot. There should + be atleast one child node representing a card slot. The name of the child node + representing the slot is recommended to be slot@n where n is the unique number + of the slot connected to the controller. The following are optional properties + which can be included in the slot child node. * reg: specifies the physical slot number. The valid values of this property is 0 to (num-slots -1), where num-slots is the value @@ -63,7 +63,7 @@ Optional properties: clock(cclk_out). If it's not specified, max is 200MHZ and min is 400KHz by default. (Use the "max-frequency" instead of "clock-freq-min-max".) -* num-slots: specifies the number of slots supported by the controller. +* num-slots (DEPRECATED): specifies the number of slots supported by the controller. The number of physical slots actually used could be equal or less than the value specified by num-slots. If this property is not specified, the value of num-slot property is assumed to be 1. @@ -124,7 +124,6 @@ board specific portions as listed below. dwmmc0@12200000 { clock-frequency = <400000000>; clock-freq-min-max = <400000 200000000>; - num-slots = <1>; broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; @@ -139,7 +138,6 @@ board specific portions as listed below. dwmmc0@12200000 { clock-frequency = <400000000>; clock-freq-min-max = <400000 200000000>; - num-slots = <1>; broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; diff --git a/dts/Bindings/mmc/zx-dw-mshc.txt b/dts/Bindings/mmc/zx-dw-mshc.txt index eaade0e5ad..906819a90c 100644 --- a/dts/Bindings/mmc/zx-dw-mshc.txt +++ b/dts/Bindings/mmc/zx-dw-mshc.txt @@ -25,7 +25,6 @@ Example: clock-frequency = <50000000>; clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>; clock-names = "biu", "ciu"; - num-slots = <1>; max-frequency = <50000000>; cap-sdio-irq; cap-sd-highspeed; diff --git a/dts/Bindings/net/dwmac-sun8i.txt b/dts/Bindings/net/dwmac-sun8i.txt deleted file mode 100644 index 725f3b1878..0000000000 --- a/dts/Bindings/net/dwmac-sun8i.txt +++ /dev/null @@ -1,84 +0,0 @@ -* Allwinner sun8i GMAC ethernet controller - -This device is a platform glue layer for stmmac. -Please see stmmac.txt for the other unchanged properties. - -Required properties: -- compatible: should be one of the following string: - "allwinner,sun8i-a83t-emac" - "allwinner,sun8i-h3-emac" - "allwinner,sun8i-v3s-emac" - "allwinner,sun50i-a64-emac" -- reg: address and length of the register for the device. -- interrupts: interrupt for the device -- interrupt-names: should be "macirq" -- clocks: A phandle to the reference clock for this device -- clock-names: should be "stmmaceth" -- resets: A phandle to the reset control for this device -- reset-names: should be "stmmaceth" -- phy-mode: See ethernet.txt -- phy-handle: See ethernet.txt -- #address-cells: shall be 1 -- #size-cells: shall be 0 -- syscon: A phandle to the syscon of the SoC with one of the following - compatible string: - - allwinner,sun8i-h3-system-controller - - allwinner,sun8i-v3s-system-controller - - allwinner,sun50i-a64-system-controller - - allwinner,sun8i-a83t-system-controller - -Optional properties: -- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0) -- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0) -Both delay properties need to be a multiple of 100. They control the delay for -external PHY. - -Optional properties for the following compatibles: - - "allwinner,sun8i-h3-emac", - - "allwinner,sun8i-v3s-emac": -- allwinner,leds-active-low: EPHY LEDs are active low - -Required child node of emac: -- mdio bus node: should be named mdio - -Required properties of the mdio node: -- #address-cells: shall be 1 -- #size-cells: shall be 0 - -The device node referenced by "phy" or "phy-handle" should be a child node -of the mdio node. See phy.txt for the generic PHY bindings. - -Required properties of the phy node with the following compatibles: - - "allwinner,sun8i-h3-emac", - - "allwinner,sun8i-v3s-emac": -- clocks: a phandle to the reference clock for the EPHY -- resets: a phandle to the reset control for the EPHY - -Example: - -emac: ethernet@1c0b000 { - compatible = "allwinner,sun8i-h3-emac"; - syscon = <&syscon>; - reg = <0x01c0b000 0x104>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - #address-cells = <1>; - #size-cells = <0>; - - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { - reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; - }; - }; -}; diff --git a/dts/src/arc/axc001.dtsi b/dts/src/arc/axc001.dtsi index 53ce226f77..a380ffa1a4 100644 --- a/dts/src/arc/axc001.dtsi +++ b/dts/src/arc/axc001.dtsi @@ -15,15 +15,15 @@ / { compatible = "snps,arc"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; cpu_card { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x00000000 0xf0000000 0x10000000>; + ranges = <0x00000000 0x0 0xf0000000 0x10000000>; core_clk: core_clk { #clock-cells = <0>; @@ -91,23 +91,21 @@ mb_intc: dw-apb-ictl@0xe0012000 { #interrupt-cells = <1>; compatible = "snps,dw-apb-ictl"; - reg = < 0xe0012000 0x200 >; + reg = < 0x0 0xe0012000 0x0 0x200 >; interrupt-controller; interrupt-parent = <&core_intc>; interrupts = < 7 >; }; memory { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x80000000 0x20000000>; device_type = "memory"; - reg = <0x80000000 0x1b000000>; /* (512 - 32) MiB */ + /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */ + reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */ }; reserved-memory { - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; /* * We just move frame buffer area to the very end of @@ -118,7 +116,7 @@ */ frame_buffer: frame_buffer@9e000000 { compatible = "shared-dma-pool"; - reg = <0x9e000000 0x2000000>; + reg = <0x0 0x9e000000 0x0 0x2000000>; no-map; }; }; diff --git a/dts/src/arc/axc003.dtsi b/dts/src/arc/axc003.dtsi index 14df46f141..cc9239ef8d 100644 --- a/dts/src/arc/axc003.dtsi +++ b/dts/src/arc/axc003.dtsi @@ -14,15 +14,15 @@ / { compatible = "snps,arc"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; cpu_card { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x00000000 0xf0000000 0x10000000>; + ranges = <0x00000000 0x0 0xf0000000 0x10000000>; core_clk: core_clk { #clock-cells = <0>; @@ -94,30 +94,29 @@ mb_intc: dw-apb-ictl@0xe0012000 { #interrupt-cells = <1>; compatible = "snps,dw-apb-ictl"; - reg = < 0xe0012000 0x200 >; + reg = < 0x0 0xe0012000 0x0 0x200 >; interrupt-controller; interrupt-parent = <&core_intc>; interrupts = < 24 >; }; memory { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x80000000 0x40000000>; device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512MiB */ + /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */ + reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */ + 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */ }; reserved-memory { - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; /* * Move frame buffer out of IOC aperture (0x8z-0xAz). */ frame_buffer: frame_buffer@be000000 { compatible = "shared-dma-pool"; - reg = <0xbe000000 0x2000000>; + reg = <0x0 0xbe000000 0x0 0x2000000>; no-map; }; }; diff --git a/dts/src/arc/axc003_idu.dtsi b/dts/src/arc/axc003_idu.dtsi index 695f9fa199..4ebb2170ab 100644 --- a/dts/src/arc/axc003_idu.dtsi +++ b/dts/src/arc/axc003_idu.dtsi @@ -14,15 +14,15 @@ / { compatible = "snps,arc"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; cpu_card { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x00000000 0xf0000000 0x10000000>; + ranges = <0x00000000 0x0 0xf0000000 0x10000000>; core_clk: core_clk { #clock-cells = <0>; @@ -100,30 +100,29 @@ mb_intc: dw-apb-ictl@0xe0012000 { #interrupt-cells = <1>; compatible = "snps,dw-apb-ictl"; - reg = < 0xe0012000 0x200 >; + reg = < 0x0 0xe0012000 0x0 0x200 >; interrupt-controller; interrupt-parent = <&idu_intc>; interrupts = <0>; }; memory { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x80000000 0x40000000>; device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512MiB */ + /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */ + reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */ + 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */ }; reserved-memory { - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; /* * Move frame buffer out of IOC aperture (0x8z-0xAz). */ frame_buffer: frame_buffer@be000000 { compatible = "shared-dma-pool"; - reg = <0xbe000000 0x2000000>; + reg = <0x0 0xbe000000 0x0 0x2000000>; no-map; }; }; diff --git a/dts/src/arc/axs10x_mb.dtsi b/dts/src/arc/axs10x_mb.dtsi index 41cfb29b62..0ff7e07edc 100644 --- a/dts/src/arc/axs10x_mb.dtsi +++ b/dts/src/arc/axs10x_mb.dtsi @@ -13,7 +13,7 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x00000000 0xe0000000 0x10000000>; + ranges = <0x00000000 0x0 0xe0000000 0x10000000>; interrupt-parent = <&mb_intc>; i2sclk: i2sclk@100a0 { diff --git a/dts/src/arm/armada-388-gp.dts b/dts/src/arm/armada-388-gp.dts index 895fa6cfa1..563901e0ec 100644 --- a/dts/src/arm/armada-388-gp.dts +++ b/dts/src/arm/armada-388-gp.dts @@ -75,7 +75,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pca0_pins>; interrupt-parent = <&gpio0>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -87,7 +87,7 @@ compatible = "nxp,pca9555"; pinctrl-names = "default"; interrupt-parent = <&gpio0>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/dts/src/arm/da850-evm.dts b/dts/src/arm/da850-evm.dts index a423e8ebfb..67e72bc72e 100644 --- a/dts/src/arm/da850-evm.dts +++ b/dts/src/arm/da850-evm.dts @@ -301,25 +301,4 @@ pinctrl-names = "default"; pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>; status = "okay"; - - /* VPIF capture port */ - port@0 { - vpif_input_ch0: endpoint@0 { - reg = <0>; - bus-width = <8>; - }; - - vpif_input_ch1: endpoint@1 { - reg = <1>; - bus-width = <8>; - data-shift = <8>; - }; - }; - - /* VPIF display port */ - port@1 { - vpif_output_ch0: endpoint { - bus-width = <8>; - }; - }; }; diff --git a/dts/src/arm/da850-lcdk.dts b/dts/src/arm/da850-lcdk.dts index b837fec70e..a0f0916156 100644 --- a/dts/src/arm/da850-lcdk.dts +++ b/dts/src/arm/da850-lcdk.dts @@ -318,11 +318,4 @@ pinctrl-names = "default"; pinctrl-0 = <&vpif_capture_pins>; status = "okay"; - - /* VPIF capture port */ - port { - vpif_ch0: endpoint { - bus-width = <8>; - }; - }; }; diff --git a/dts/src/arm/dm8168-evm.dts b/dts/src/arm/dm8168-evm.dts index 1865976db5..c72a2132aa 100644 --- a/dts/src/arm/dm8168-evm.dts +++ b/dts/src/arm/dm8168-evm.dts @@ -68,6 +68,34 @@ DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ >; }; + + nandflash_pins: nandflash_pins { + pinctrl-single,pins = < + DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/ + DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */ + DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0) /* PINCTRL214 GPMC_OE_RE */ + DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0) /* PINCTRL215 GPMC_BE0_CLE */ + DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0) /* PINCTRL213 GPMC_WE */ + DM816X_IOPAD(0x0b6c, MUX_MODE0) /* PINCTRL220 GPMC_WAIT */ + DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0) /* PINCTRL250 GPMC_CLK */ + DM816X_IOPAD(0x0ba4, MUX_MODE0) /* PINCTRL234 GPMC_D0 */ + DM816X_IOPAD(0x0ba8, MUX_MODE0) /* PINCTRL234 GPMC_D1 */ + DM816X_IOPAD(0x0bac, MUX_MODE0) /* PINCTRL234 GPMC_D2 */ + DM816X_IOPAD(0x0bb0, MUX_MODE0) /* PINCTRL234 GPMC_D3 */ + DM816X_IOPAD(0x0bb4, MUX_MODE0) /* PINCTRL234 GPMC_D4 */ + DM816X_IOPAD(0x0bb8, MUX_MODE0) /* PINCTRL234 GPMC_D5 */ + DM816X_IOPAD(0x0bbc, MUX_MODE0) /* PINCTRL234 GPMC_D6 */ + DM816X_IOPAD(0x0bc0, MUX_MODE0) /* PINCTRL234 GPMC_D7 */ + DM816X_IOPAD(0x0bc4, MUX_MODE0) /* PINCTRL234 GPMC_D8 */ + DM816X_IOPAD(0x0bc8, MUX_MODE0) /* PINCTRL234 GPMC_D9 */ + DM816X_IOPAD(0x0bcc, MUX_MODE0) /* PINCTRL234 GPMC_D10 */ + DM816X_IOPAD(0x0bd0, MUX_MODE0) /* PINCTRL234 GPMC_D11 */ + DM816X_IOPAD(0x0bd4, MUX_MODE0) /* PINCTRL234 GPMC_D12 */ + DM816X_IOPAD(0x0bd8, MUX_MODE0) /* PINCTRL234 GPMC_D13 */ + DM816X_IOPAD(0x0bdc, MUX_MODE0) /* PINCTRL234 GPMC_D14 */ + DM816X_IOPAD(0x0be0, MUX_MODE0) /* PINCTRL234 GPMC_D15 */ + >; + }; }; &i2c1 { @@ -90,6 +118,8 @@ &gpmc { ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; nand@0,0 { compatible = "ti,omap2-nand"; @@ -98,9 +128,11 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; nand-bus-width = <16>; gpmc,device-width = <2>; gpmc,sync-clk-ps = <0>; @@ -164,7 +196,7 @@ vmmc-supply = <&vmmcsd_fixed>; bus-width = <4>; cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; }; /* At least dm8168-evm rev c won't support multipoint, later may */ diff --git a/dts/src/arm/dm816x.dtsi b/dts/src/arm/dm816x.dtsi index 59cbf958fc..566b2a8c8b 100644 --- a/dts/src/arm/dm816x.dtsi +++ b/dts/src/arm/dm816x.dtsi @@ -145,7 +145,7 @@ }; elm: elm@48080000 { - compatible = "ti,816-elm"; + compatible = "ti,am3352-elm"; ti,hwmods = "elm"; reg = <0x48080000 0x2000>; interrupts = <4>; diff --git a/dts/src/arm/dra71-evm.dts b/dts/src/arm/dra71-evm.dts index 4d57a55473..a6298eb569 100644 --- a/dts/src/arm/dra71-evm.dts +++ b/dts/src/arm/dra71-evm.dts @@ -190,7 +190,7 @@ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; - ti,impedance-control = <0x1f>; + ti,min-output-impedance; }; dp83867_1: ethernet-phy@3 { @@ -198,7 +198,7 @@ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; - ti,impedance-control = <0x1f>; + ti,min-output-impedance; }; }; diff --git a/dts/src/arm/exynos4.dtsi b/dts/src/arm/exynos4.dtsi index 497a9470c8..5739389f5b 100644 --- a/dts/src/arm/exynos4.dtsi +++ b/dts/src/arm/exynos4.dtsi @@ -59,6 +59,9 @@ compatible = "samsung,exynos4210-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, + <&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; i2s0: i2s@03830000 { diff --git a/dts/src/arm/exynos5422-odroidxu3-common.dtsi b/dts/src/arm/exynos5422-odroidxu3-common.dtsi index f92f957412..a183b56283 100644 --- a/dts/src/arm/exynos5422-odroidxu3-common.dtsi +++ b/dts/src/arm/exynos5422-odroidxu3-common.dtsi @@ -266,6 +266,7 @@ &hdmicec { status = "okay"; + needs-hpd; }; &hsi2c_4 { diff --git a/dts/src/arm/imx25.dtsi b/dts/src/arm/imx25.dtsi index dfcc8e00cf..0ade3619f3 100644 --- a/dts/src/arm/imx25.dtsi +++ b/dts/src/arm/imx25.dtsi @@ -297,6 +297,7 @@ #address-cells = <1>; #size-cells = <1>; status = "disabled"; + ranges; adc: adc@50030800 { compatible = "fsl,imx25-gcq"; diff --git a/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi b/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi index aeaa5a6e4f..a24e4f1911 100644 --- a/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi +++ b/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi @@ -507,7 +507,7 @@ pinctrl_pcie: pciegrp { fsl,pins = < /* PCIe reset */ - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0 + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0 MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0 >; }; @@ -668,7 +668,7 @@ &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio3 0 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/dts/src/arm/imx7d-sdb.dts b/dts/src/arm/imx7d-sdb.dts index 54c4540228..0a24d1bf3c 100644 --- a/dts/src/arm/imx7d-sdb.dts +++ b/dts/src/arm/imx7d-sdb.dts @@ -557,6 +557,14 @@ >; }; + pinctrl_spi4: spi4grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + pinctrl_tsc2046_pendown: tsc2046_pendown { fsl,pins = < MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 @@ -697,13 +705,5 @@ fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0 >; - - pinctrl_spi4: spi4grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 - MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 - >; - }; }; }; diff --git a/dts/src/arm/rk3288.dtsi b/dts/src/arm/rk3288.dtsi index 2484f11761..858e1fed76 100644 --- a/dts/src/arm/rk3288.dtsi +++ b/dts/src/arm/rk3288.dtsi @@ -1126,8 +1126,8 @@ }; }; - gpu: mali@ffa30000 { - compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard"; + gpu: gpu@ffa30000 { + compatible = "rockchip,rk3288-mali", "arm,mali-t760"; reg = <0xffa30000 0x10000>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/src/arm/sama5d2.dtsi b/dts/src/arm/sama5d2.dtsi index cc06da3943..60e69aeacb 100644 --- a/dts/src/arm/sama5d2.dtsi +++ b/dts/src/arm/sama5d2.dtsi @@ -303,7 +303,7 @@ #size-cells = <1>; atmel,smc = <&hsmc>; reg = <0x10000000 0x10000000 - 0x40000000 0x30000000>; + 0x60000000 0x30000000>; ranges = <0x0 0x0 0x10000000 0x10000000 0x1 0x0 0x60000000 0x10000000 0x2 0x0 0x70000000 0x10000000 @@ -1048,18 +1048,18 @@ }; hsmc: hsmc@f8014000 { - compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; + compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; reg = <0xf8014000 0x1000>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; clocks = <&hsmc_clk>; #address-cells = <1>; #size-cells = <1>; ranges; - pmecc: ecc-engine@ffffc070 { + pmecc: ecc-engine@f8014070 { compatible = "atmel,sama5d2-pmecc"; - reg = <0xffffc070 0x490>, - <0xffffc500 0x100>; + reg = <0xf8014070 0x490>, + <0xf8014500 0x100>; }; }; diff --git a/dts/src/arm/sun8i-a83t.dtsi b/dts/src/arm/sun8i-a83t.dtsi index 8923ba625b..19a8f4fcfa 100644 --- a/dts/src/arm/sun8i-a83t.dtsi +++ b/dts/src/arm/sun8i-a83t.dtsi @@ -44,7 +44,9 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun8i-a83t-ccu.h> #include <dt-bindings/clock/sun8i-r-ccu.h> +#include <dt-bindings/reset/sun8i-a83t-ccu.h> / { interrupt-parent = <&gic>; @@ -175,8 +177,8 @@ compatible = "allwinner,sun8i-a83t-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu 21>; - resets = <&ccu 7>; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; #dma-cells = <1>; }; @@ -195,7 +197,7 @@ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01c20800 0x400>; - clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -247,8 +249,8 @@ "allwinner,sun8i-h3-spdif"; reg = <0x01c21000 0x400>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu 44>, <&ccu 76>; - resets = <&ccu 32>; + clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; + resets = <&ccu RST_BUS_SPDIF>; clock-names = "apb", "spdif"; dmas = <&dma 2>; dma-names = "tx"; @@ -263,8 +265,8 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 53>; - resets = <&ccu 40>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; diff --git a/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts b/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts index 6713d0f2b3..b1502df7b5 100644 --- a/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts +++ b/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts @@ -56,8 +56,6 @@ aliases { serial0 = &uart0; - /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ - ethernet0 = &emac; ethernet1 = &xr819; }; @@ -104,13 +102,6 @@ status = "okay"; }; -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>; diff --git a/dts/src/arm/sun8i-h3-bananapi-m2-plus.dts b/dts/src/arm/sun8i-h3-bananapi-m2-plus.dts index d756ff8251..a337af1de3 100644 --- a/dts/src/arm/sun8i-h3-bananapi-m2-plus.dts +++ b/dts/src/arm/sun8i-h3-bananapi-m2-plus.dts @@ -52,7 +52,6 @@ compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; aliases { - ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -115,30 +114,12 @@ status = "okay"; }; -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - - allwinner,leds-active-low; - status = "okay"; -}; - &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; status = "okay"; }; -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/dts/src/arm/sun8i-h3-nanopi-neo.dts b/dts/src/arm/sun8i-h3-nanopi-neo.dts index 78f6c24952..8d2cc6e9a0 100644 --- a/dts/src/arm/sun8i-h3-nanopi-neo.dts +++ b/dts/src/arm/sun8i-h3-nanopi-neo.dts @@ -46,10 +46,3 @@ model = "FriendlyARM NanoPi NEO"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; }; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; diff --git a/dts/src/arm/sun8i-h3-orangepi-2.dts b/dts/src/arm/sun8i-h3-orangepi-2.dts index 17cdeae19c..8ff71b1bb4 100644 --- a/dts/src/arm/sun8i-h3-orangepi-2.dts +++ b/dts/src/arm/sun8i-h3-orangepi-2.dts @@ -54,7 +54,6 @@ aliases { serial0 = &uart0; /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ - ethernet0 = &emac; ethernet1 = &rtl8189; }; @@ -118,13 +117,6 @@ status = "okay"; }; -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/dts/src/arm/sun8i-h3-orangepi-one.dts b/dts/src/arm/sun8i-h3-orangepi-one.dts index 6880268e8b..5fea430e0e 100644 --- a/dts/src/arm/sun8i-h3-orangepi-one.dts +++ b/dts/src/arm/sun8i-h3-orangepi-one.dts @@ -52,7 +52,6 @@ compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; aliases { - ethernet0 = &emac; serial0 = &uart0; }; @@ -98,13 +97,6 @@ status = "okay"; }; -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/dts/src/arm/sun8i-h3-orangepi-pc-plus.dts b/dts/src/arm/sun8i-h3-orangepi-pc-plus.dts index a10281b455..8b93f5c781 100644 --- a/dts/src/arm/sun8i-h3-orangepi-pc-plus.dts +++ b/dts/src/arm/sun8i-h3-orangepi-pc-plus.dts @@ -53,11 +53,6 @@ }; }; -&emac { - /* LEDs changed to active high on the plus */ - /delete-property/ allwinner,leds-active-low; -}; - &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_a>; diff --git a/dts/src/arm/sun8i-h3-orangepi-pc.dts b/dts/src/arm/sun8i-h3-orangepi-pc.dts index 998b60f8d2..1a044b17d6 100644 --- a/dts/src/arm/sun8i-h3-orangepi-pc.dts +++ b/dts/src/arm/sun8i-h3-orangepi-pc.dts @@ -52,7 +52,6 @@ compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; aliases { - ethernet0 = &emac; serial0 = &uart0; }; @@ -114,13 +113,6 @@ status = "okay"; }; -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/dts/src/arm/sun8i-h3-orangepi-plus.dts b/dts/src/arm/sun8i-h3-orangepi-plus.dts index 331ed683ac..828ae7a526 100644 --- a/dts/src/arm/sun8i-h3-orangepi-plus.dts +++ b/dts/src/arm/sun8i-h3-orangepi-plus.dts @@ -47,10 +47,6 @@ model = "Xunlong Orange Pi Plus / Plus 2"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; - aliases { - ethernet0 = &emac; - }; - reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; regulator-name = "gmac-3v3"; @@ -78,24 +74,6 @@ status = "okay"; }; -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - - allwinner,leds-active-low; - status = "okay"; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; diff --git a/dts/src/arm/sun8i-h3-orangepi-plus2e.dts b/dts/src/arm/sun8i-h3-orangepi-plus2e.dts index 80026f3caa..97920b12a9 100644 --- a/dts/src/arm/sun8i-h3-orangepi-plus2e.dts +++ b/dts/src/arm/sun8i-h3-orangepi-plus2e.dts @@ -61,19 +61,3 @@ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ }; }; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff --git a/dts/src/arm/sunxi-h3-h5.dtsi b/dts/src/arm/sunxi-h3-h5.dtsi index 6f21626080..11240a8313 100644 --- a/dts/src/arm/sunxi-h3-h5.dtsi +++ b/dts/src/arm/sunxi-h3-h5.dtsi @@ -391,32 +391,6 @@ clocks = <&osc24M>; }; - emac: ethernet@1c30000 { - compatible = "allwinner,sun8i-h3-emac"; - syscon = <&syscon>; - reg = <0x01c30000 0x104>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; - }; - }; - }; - spi0: spi@01c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; diff --git a/dts/src/arm/tango4-vantage-1172.dts b/dts/src/arm/tango4-vantage-1172.dts index 86d8df9880..13bcc460bc 100644 --- a/dts/src/arm/tango4-vantage-1172.dts +++ b/dts/src/arm/tango4-vantage-1172.dts @@ -22,7 +22,7 @@ }; ð0 { - phy-connection-type = "rgmii"; + phy-connection-type = "rgmii-id"; phy-handle = <ð0_phy>; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts b/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts index 0d1f026d83..6872135d7f 100644 --- a/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts +++ b/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts @@ -67,14 +67,6 @@ }; }; -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - status = "okay"; -}; - &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -85,13 +77,6 @@ bias-pull-up; }; -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/dts/src/arm64/allwinner/sun50i-a64-pine64-plus.dts b/dts/src/arm64/allwinner/sun50i-a64-pine64-plus.dts index 24f1aac366..f82ccf332c 100644 --- a/dts/src/arm64/allwinner/sun50i-a64-pine64-plus.dts +++ b/dts/src/arm64/allwinner/sun50i-a64-pine64-plus.dts @@ -48,18 +48,3 @@ /* TODO: Camera, touchscreen, etc. */ }; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - status = "okay"; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff --git a/dts/src/arm64/allwinner/sun50i-a64-pine64.dts b/dts/src/arm64/allwinner/sun50i-a64-pine64.dts index 08cda24ea1..7c533b6d4b 100644 --- a/dts/src/arm64/allwinner/sun50i-a64-pine64.dts +++ b/dts/src/arm64/allwinner/sun50i-a64-pine64.dts @@ -78,15 +78,6 @@ status = "okay"; }; -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; - phy-mode = "rmii"; - phy-handle = <&ext_rmii_phy1>; - status = "okay"; - -}; - &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -97,13 +88,6 @@ bias-pull-up; }; -&mdio { - ext_rmii_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts b/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts index 17eb1cc5bf..d891a1a27f 100644 --- a/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts @@ -76,21 +76,6 @@ status = "okay"; }; -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - status = "okay"; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; diff --git a/dts/src/arm64/allwinner/sun50i-a64.dtsi b/dts/src/arm64/allwinner/sun50i-a64.dtsi index 9d00622ce8..68aadc9b96 100644 --- a/dts/src/arm64/allwinner/sun50i-a64.dtsi +++ b/dts/src/arm64/allwinner/sun50i-a64.dtsi @@ -449,26 +449,6 @@ #size-cells = <0>; }; - emac: ethernet@1c30000 { - compatible = "allwinner,sun50i-a64-emac"; - syscon = <&syscon>; - reg = <0x01c30000 0x100>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, diff --git a/dts/src/arm64/allwinner/sun50i-h5-nanopi-neo2.dts b/dts/src/arm64/allwinner/sun50i-h5-nanopi-neo2.dts index 9689087611..1c2387bd5d 100644 --- a/dts/src/arm64/allwinner/sun50i-h5-nanopi-neo2.dts +++ b/dts/src/arm64/allwinner/sun50i-h5-nanopi-neo2.dts @@ -50,7 +50,6 @@ compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; aliases { - ethernet0 = &emac; serial0 = &uart0; }; @@ -109,22 +108,6 @@ status = "okay"; }; -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <7>; - }; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/dts/src/arm64/allwinner/sun50i-h5-orangepi-pc2.dts b/dts/src/arm64/allwinner/sun50i-h5-orangepi-pc2.dts index a8296feee8..4f77c8470f 100644 --- a/dts/src/arm64/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/dts/src/arm64/allwinner/sun50i-h5-orangepi-pc2.dts @@ -59,7 +59,6 @@ }; aliases { - ethernet0 = &emac; serial0 = &uart0; }; @@ -137,28 +136,12 @@ status = "okay"; }; -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - status = "okay"; -}; - &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; status = "okay"; }; -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/dts/src/arm64/allwinner/sun50i-h5-orangepi-prime.dts b/dts/src/arm64/allwinner/sun50i-h5-orangepi-prime.dts index d906b302cb..6be06873e5 100644 --- a/dts/src/arm64/allwinner/sun50i-h5-orangepi-prime.dts +++ b/dts/src/arm64/allwinner/sun50i-h5-orangepi-prime.dts @@ -54,7 +54,6 @@ compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5"; aliases { - ethernet0 = &emac; serial0 = &uart0; }; @@ -144,28 +143,12 @@ status = "okay"; }; -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - status = "okay"; -}; - &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; status = "okay"; }; -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/dts/src/arm64/allwinner/sun50i-h5.dtsi b/dts/src/arm64/allwinner/sun50i-h5.dtsi index 732e2e06f5..d9a720bff0 100644 --- a/dts/src/arm64/allwinner/sun50i-h5.dtsi +++ b/dts/src/arm64/allwinner/sun50i-h5.dtsi @@ -120,5 +120,8 @@ }; &pio { + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; compatible = "allwinner,sun50i-h5-pinctrl"; }; diff --git a/dts/src/arm64/amlogic/meson-gx.dtsi b/dts/src/arm64/amlogic/meson-gx.dtsi index 35b8c88c32..738ed689ff 100644 --- a/dts/src/arm64/amlogic/meson-gx.dtsi +++ b/dts/src/arm64/amlogic/meson-gx.dtsi @@ -400,7 +400,7 @@ }; pwm_AO_ab: pwm@550 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; + compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; reg = <0x0 0x00550 0x0 0x10>; #pwm-cells = <3>; status = "disabled"; diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts b/dts/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts index 72c5a9f64c..94567eb178 100644 --- a/dts/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/dts/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -109,8 +109,8 @@ status = "okay"; pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; + clocks = <&xtal> , <&xtal>; + clock-names = "clkin0", "clkin1" ; }; &pwm_ef { diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts b/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts index 890821d6e5..266fbcf3e4 100644 --- a/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -10,12 +10,20 @@ #include <dt-bindings/input/input.h> -#include "meson-gxl-s905x-p212.dtsi" +#include "meson-gxl-s905x.dtsi" / { compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl"; model = "Libre Technology CC"; + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + cvbs-connector { compatible = "composite-video-connector"; @@ -26,6 +34,11 @@ }; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + hdmi-connector { compatible = "hdmi-connector"; type = "a"; @@ -53,6 +66,39 @@ linux,default-trigger = "heartbeat"; }; }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_card: regulator-vcc-card { + compatible = "regulator-gpio"; + + regulator-name = "VCC_CARD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + + states = <3300000 0>, + <1800000 1>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &cvbs_vdac_port { @@ -61,6 +107,16 @@ }; }; +ðmac { + status = "okay"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + &hdmi_tx { status = "okay"; pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; @@ -73,20 +129,43 @@ }; }; -/* - * The following devices exists but are exposed on the general - * purpose GPIO header. End user may well decide to use those pins - * for another purpose - */ +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; -&sd_emmc_a { - status = "disabled"; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_card>; }; -&uart_A { - status = "disabled"; +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <50000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; }; -&wifi32k { - status = "disabled"; +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; }; diff --git a/dts/src/arm64/marvell/armada-37xx.dtsi b/dts/src/arm64/marvell/armada-37xx.dtsi index dbcc3d4e2e..51763d6740 100644 --- a/dts/src/arm64/marvell/armada-37xx.dtsi +++ b/dts/src/arm64/marvell/armada-37xx.dtsi @@ -219,7 +219,7 @@ reg = <0x18800 0x100>, <0x18C00 0x20>; gpiosb: gpio { #gpio-cells = <2>; - gpio-ranges = <&pinctrl_sb 0 0 29>; + gpio-ranges = <&pinctrl_sb 0 0 30>; gpio-controller; interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/src/arm64/marvell/armada-ap806.dtsi b/dts/src/arm64/marvell/armada-ap806.dtsi index 1eb1f1e9aa..4d360713ed 100644 --- a/dts/src/arm64/marvell/armada-ap806.dtsi +++ b/dts/src/arm64/marvell/armada-ap806.dtsi @@ -268,10 +268,10 @@ ap_gpio: gpio { compatible = "marvell,armada-8k-gpio"; offset = <0x1040>; - ngpios = <19>; + ngpios = <20>; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&ap_pinctrl 0 0 19>; + gpio-ranges = <&ap_pinctrl 0 0 20>; }; }; }; diff --git a/dts/src/arm64/marvell/armada-cp110-master.dtsi b/dts/src/arm64/marvell/armada-cp110-master.dtsi index 726528ce54..4c68605675 100644 --- a/dts/src/arm64/marvell/armada-cp110-master.dtsi +++ b/dts/src/arm64/marvell/armada-cp110-master.dtsi @@ -270,6 +270,7 @@ interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cpm_clk 1 26>; + dma-coherent; }; }; diff --git a/dts/src/arm64/marvell/armada-cp110-slave.dtsi b/dts/src/arm64/marvell/armada-cp110-slave.dtsi index 95f8e5f607..923f354b02 100644 --- a/dts/src/arm64/marvell/armada-cp110-slave.dtsi +++ b/dts/src/arm64/marvell/armada-cp110-slave.dtsi @@ -64,7 +64,7 @@ compatible = "marvell,armada-8k-rtc"; reg = <0x284000 0x20>, <0x284080 0x24>; reg-names = "rtc", "rtc-soc"; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; }; cps_ethernet: ethernet@0 { @@ -261,6 +261,7 @@ interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cps_clk 1 26>; + dma-coherent; /* * The cryptographic engine found on the cp110 * master is enabled by default at the SoC diff --git a/dts/src/arm64/renesas/salvator-common.dtsi b/dts/src/arm64/renesas/salvator-common.dtsi index aef35e0b68..f903957da5 100644 --- a/dts/src/arm64/renesas/salvator-common.dtsi +++ b/dts/src/arm64/renesas/salvator-common.dtsi @@ -45,7 +45,7 @@ stdout-path = "serial0:115200n8"; }; - audio_clkout: audio_clkout { + audio_clkout: audio-clkout { /* * This is same as <&rcar_sound 0> * but needed to avoid cs2000/rcar_sound probe dead-lock @@ -508,7 +508,7 @@ /* audio_clkout0/1/2/3 */ #clock-cells = <1>; - clock-frequency = <11289600 12288000>; + clock-frequency = <12288000 11289600>; status = "okay"; diff --git a/dts/src/arm64/renesas/ulcb.dtsi b/dts/src/arm64/renesas/ulcb.dtsi index b5c6ee07d7..d1a3f3b7a0 100644 --- a/dts/src/arm64/renesas/ulcb.dtsi +++ b/dts/src/arm64/renesas/ulcb.dtsi @@ -281,7 +281,7 @@ /* audio_clkout0/1/2/3 */ #clock-cells = <1>; - clock-frequency = <11289600 12288000>; + clock-frequency = <12288000 11289600>; status = "okay"; @@ -558,4 +558,4 @@ static struct efi_driver efi_fs_driver = { .probe = efi_fs_probe, .guid = EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID, }; -device_efi_driver(efi_fs_driver); +fs_efi_driver(efi_fs_driver); @@ -145,6 +145,7 @@ char *normalise_path(const char *pathname) EXPORT_SYMBOL(normalise_path); static int __lstat(const char *filename, struct stat *s); +static struct fs_device_d *get_fsdevice_by_path(const char *path); static char *__canonicalize_path(const char *_pathname, int level) { @@ -158,8 +159,8 @@ static char *__canonicalize_path(const char *_pathname, int level) path = freep = xstrdup(_pathname); - if (*path == '/') - outpath = xstrdup("/"); + if (*path == '/' || !strcmp(cwd, "/")) + outpath = xstrdup(""); else outpath = __canonicalize_path(cwd, level + 1); @@ -167,6 +168,7 @@ static char *__canonicalize_path(const char *_pathname, int level) char *p = strsep(&path, "/"); char *tmp; char link[PATH_MAX] = {}; + struct fs_device_d *fsdev; if (!p) break; @@ -185,6 +187,14 @@ static char *__canonicalize_path(const char *_pathname, int level) free(outpath); outpath = tmp; + /* + * Don't bother filesystems without link support + * with an additional stat() call. + */ + fsdev = get_fsdevice_by_path(outpath); + if (!fsdev->driver->readlink) + continue; + ret = __lstat(outpath, &s); if (ret) goto out; @@ -212,6 +222,11 @@ static char *__canonicalize_path(const char *_pathname, int level) out: free(freep); + if (!*outpath) { + free(outpath); + outpath = xstrdup("/"); + } + return outpath; } diff --git a/include/efi/efi-device.h b/include/efi/efi-device.h index 8f5f1f3f13..15c293bb1b 100644 --- a/include/efi/efi-device.h +++ b/include/efi/efi-device.h @@ -33,6 +33,8 @@ static inline struct efi_driver *to_efi_driver(struct driver_d *drv) #define device_efi_driver(drv) \ register_driver_macro(device, efi, drv) +#define fs_efi_driver(drv) \ + register_driver_macro(fs, efi, drv) static inline int efi_driver_register(struct efi_driver *efidrv) { efidrv->driver.bus = &efi_bus; diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h index 132ee598a5..07a30e2e6f 100644 --- a/include/video/atmel_lcdc.h +++ b/include/video/atmel_lcdc.h @@ -44,7 +44,8 @@ struct atmel_lcdfb_platform_data { u8 lcd_wiring_mode; unsigned int default_lcdcon2; unsigned int default_dmacon; - void (*atmel_lcdfb_power_control)(int on); + int gpio_power_control; + bool gpio_power_control_active_low; struct fb_videomode *mode_list; unsigned num_modes; diff --git a/scripts/imx/imx-image.c b/scripts/imx/imx-image.c index dd5799cccc..b241e8c4b6 100644 --- a/scripts/imx/imx-image.c +++ b/scripts/imx/imx-image.c @@ -762,10 +762,6 @@ int main(int argc, char *argv[]) create_usb_image = 0; } - buf = calloc(1, HEADER_LEN); - if (!buf) - exit(1); - if (data.image_dcd_offset == 0xffffffff) { if (create_usb_image) data.image_dcd_offset = 0x0; @@ -790,6 +786,10 @@ int main(int argc, char *argv[]) switch (data.header_version) { case 1: + buf = calloc(1, HEADER_LEN); + if (!buf) + exit(1); + add_header_v1(&data, buf); if (data.srkfile) { ret = add_srk(buf, data.image_dcd_offset, data.image_load_addr, @@ -799,6 +799,10 @@ int main(int argc, char *argv[]) } break; case 2: + buf = calloc(1, data.image_dcd_offset + sizeof(struct imx_flash_header_v2) + MAX_DCD * sizeof(u32)); + if (!buf) + exit(1); + add_header_v2(&data, buf); break; default: |