diff options
55 files changed, 1514 insertions, 80 deletions
diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst index 27d0123c87..71cc6bb09a 100644 --- a/Documentation/boards/imx.rst +++ b/Documentation/boards/imx.rst @@ -31,6 +31,21 @@ the i.MX images are generated with the ``scripts/imx/imx-image`` tool. Normally it's not necessary to call this tool manually, it is executed automatically at the end of the build process. +Required entries for an i.MX image in ``images/Makefile.imx`` are for example: + +.. code-block:: none + + pblb-$(CONFIG_MACH_MYBOARD) += start_imx6dl_myboard + CFG_start_imx6dl_myboard.pblb.imximg = $(board)/myboard/flash-header-imx6dl-myboard.imxcfg + FILE_barebox-imx6dl-myboard.img = start_imx6dl_myboard.pblb.imximg + image-$(CONFIG_MACH_MYBOARD) += barebox-imx6dl-myboard.img + +The first line defines the entry function of the pre-bootloader. +This function must be defined in the board's ``lowlevel.c``. +The second line describes the flash header to be used for the image, which is +then compiled into an imximg file. +The prebootloader is then added to the final barebox image. + The images generated by the build process can be directly written to an SD card: @@ -68,6 +83,65 @@ The images can also always be started as second stage on the target: barebox@Board Name:/ bootm /mnt/tftp/barebox-freescale-imx51-babbage.img +High Assurance Boot +^^^^^^^^^^^^^^^^^^^ + +HAB is an NXP ROM code feature which is able to authenticate software in +external memory at boot time. +This is done by verifying signatures as defined in the Command Sequence File +(CSF) as compiled into the i.MX boot header. + +barebox supports generating signed images, signed USB images suitable for +*imx-usb-loader* and encrypted images. + +In contrast to normal (unsigned) images booting signed images via +imx-usb-loader requires special images: +DCD data is invalidated (DCD pointer set to zero), the image is then signed and +afterwards the DCD pointer is set to the DCD data again (practically making +the signature invalid). +This works because the imx-usb-loader transmits the DCD table setup prior to +the actual image to set up the RAM in order to load the barebox image. +Now the DCD pointer is set to zero (making the signature valid again) and the +image is loaded and verified by the ROM code. + +Note that the device-specific Data Encryption Key (DEK) blob needs to be +appended to the image after the build process for appropriately encrypted +images. + +In order to generate these special image types barebox is equipped with +corresponding static pattern rules in ``images/Makefile.imx``. +Unlike the typical ``imximg`` file extension the following ones are used for +these cases: + +* ``simximg``: generate signed image +* ``usimximg``: generate signed USB image +* ``esimximg``: generate encrypted and signed image + +The imx-image tool is then automatically called with the appropriate flags +during image creation. +This again calls Freescale's Code Signing Tool (CST) which must be installed in +the path or given via the environment variable "CST". + +Assuming ``CONFIG_HAB`` and ``CONFIG_HABV4`` are enabled the necessary +keys/certificates are expected in these config variables (assuming HABv4): + +.. code-block:: none + + CONFIG_HABV4_TABLE_BIN + CONFIG_HABV4_CSF_CRT_PEM + CONFIG_HABV4_IMG_CRT_PEM + +A CSF template is located in +``arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h`` which is preprocessed +by barebox. +It must be included in the board's flash header: + +.. code-block:: none + + #include <mach/habv4-imx6-gencsf.h> + +Analogous to HABv4 options and a template exist for HABv3. + Using GPT on i.MX ^^^^^^^^^^^^^^^^^ diff --git a/Documentation/boards/imx/digi-ccimx6ulsbcpro.rst b/Documentation/boards/imx/digi-ccimx6ulsbcpro.rst new file mode 100644 index 0000000000..bcb2ec2f07 --- /dev/null +++ b/Documentation/boards/imx/digi-ccimx6ulsbcpro.rst @@ -0,0 +1,26 @@ +Digi CC-IMX6UL-SBC-PRO +====================== + +This board is based on the i.MX6UL SoC. + +The SBC Pro is shipped with: + + * 256MiB NAND flash + * 256MiB DDR3 SDRAM + +see https://www.digi.com/products/embedded-systems/single-board-computers/connectcore-for-i-mx6ul-sbc-pro +for more information. + +MAC addresses +------------- +The Digi modules save their MAC addresses not in the OCOTP nodes, but in the +U-Boot environment. It is advised to boot the board using the shipped U-Boot +Bootloader and to read out and save the MAC addresses for the board. +The environment variables which contain the addresses are `$ethaddr` and +`$eth1addr`. +The MAC addresses can than be persisted to the barebox environment by using + +.. code-block:: sh + + nv dev.eth0.ethaddr=<eth0addr> + nv dev.eth1.ethaddr=<eth1addr> diff --git a/Documentation/boards/imx/zii-imx6-rdu2/bootstrap.sh b/Documentation/boards/imx/zii-imx6-rdu2/bootstrap.sh new file mode 100755 index 0000000000..7342e890ec --- /dev/null +++ b/Documentation/boards/imx/zii-imx6-rdu2/bootstrap.sh @@ -0,0 +1,6 @@ +#!/bin/sh + +OPENOCD=${OPENOCD:-openocd} +DIR=$(CDPATH= cd -- "$(dirname -- "$0")" && pwd) + +${OPENOCD} -f ${DIR}/openocd.cfg --command "adapter_khz 10000; init; reset init; start_barebox" diff --git a/Documentation/boards/imx/zii-imx6-rdu2/openocd.cfg b/Documentation/boards/imx/zii-imx6-rdu2/openocd.cfg new file mode 100644 index 0000000000..c5a65c44e6 --- /dev/null +++ b/Documentation/boards/imx/zii-imx6-rdu2/openocd.cfg @@ -0,0 +1,282 @@ +# +# Board configuration file for the Zodiac RDU2 boards (6Q/6Q+ based) +# +interface ftdi +ftdi_vid_pid 0x0403 0x6011 + +ftdi_layout_init 0x0038 0x003b +ftdi_layout_signal nSRST -data 0x0010 +ftdi_layout_signal LED -data 0x0020 + +# select JTAG +transport select jtag + +reset_config srst_only srst_push_pull connect_deassert_srst + +# set a slow default JTAG clock, can be overridden later +adapter_khz 1000 + +# delay after SRST goes inactive +adapter_nsrst_delay 30 + +# board has i.MX6Q(+) with 4 Cortex-A9 cores +set CHIPNAME imx6q +set IMX_FLAVOUR q + +source [find target/imx6.cfg] +source [find mem_helper.tcl] + +proc disable_wdog { } { + echo "Bootstrap: Disabling SoC watchdog" + mwh phys 0x020bc000 0x30 +} + +proc ddr_init_imx6q { } { + echo "Bootstrap: Initializing DDR for i.MX6Q" + + mww phys 0x020e0798 0x000C0000 + mww phys 0x020e0758 0x00000000 + mww phys 0x020e0588 0x00000030 + mww phys 0x020e0594 0x00000030 + mww phys 0x020e056c 0x00000030 + mww phys 0x020e0578 0x00000030 + mww phys 0x020e074c 0x00000030 + mww phys 0x020e057c 0x00000030 + mww phys 0x020e058c 0x00000000 + mww phys 0x020e059c 0x00000030 + mww phys 0x020e05a0 0x00000030 + mww phys 0x020e078c 0x00000030 + mww phys 0x020e0750 0x00020000 + mww phys 0x020e05a8 0x00000028 + mww phys 0x020e05b0 0x00000028 + mww phys 0x020e0524 0x00000028 + mww phys 0x020e051c 0x00000028 + mww phys 0x020e0518 0x00000028 + mww phys 0x020e050c 0x00000028 + mww phys 0x020e05b8 0x00000028 + mww phys 0x020e05c0 0x00000028 + mww phys 0x020e0774 0x00020000 + mww phys 0x020e0784 0x00000028 + mww phys 0x020e0788 0x00000028 + mww phys 0x020e0794 0x00000028 + mww phys 0x020e079c 0x00000028 + mww phys 0x020e07a0 0x00000028 + mww phys 0x020e07a4 0x00000028 + mww phys 0x020e07a8 0x00000028 + mww phys 0x020e0748 0x00000028 + mww phys 0x020e05ac 0x00000028 + mww phys 0x020e05b4 0x00000028 + mww phys 0x020e0528 0x00000028 + mww phys 0x020e0520 0x00000028 + mww phys 0x020e0514 0x00000028 + mww phys 0x020e0510 0x00000028 + mww phys 0x020e05bc 0x00000028 + mww phys 0x020e05c4 0x00000028 + mww phys 0x021b0800 0xa1390003 + mww phys 0x021b080c 0x001F001F + mww phys 0x021b0810 0x001F001F + mww phys 0x021b480c 0x001F001F + mww phys 0x021b4810 0x001F001F + mww phys 0x021b083c 0x43260335 + mww phys 0x021b0840 0x031A030B + mww phys 0x021b483c 0x4323033B + mww phys 0x021b4840 0x0323026F + mww phys 0x021b0848 0x483D4545 + mww phys 0x021b4848 0x44433E48 + mww phys 0x021b0850 0x41444840 + mww phys 0x021b4850 0x4835483E + mww phys 0x021b081c 0x33333333 + mww phys 0x021b0820 0x33333333 + mww phys 0x021b0824 0x33333333 + mww phys 0x021b0828 0x33333333 + mww phys 0x021b481c 0x33333333 + mww phys 0x021b4820 0x33333333 + mww phys 0x021b4824 0x33333333 + mww phys 0x021b4828 0x33333333 + mww phys 0x021b08b8 0x00000800 + mww phys 0x021b48b8 0x00000800 + mww phys 0x021b0004 0x00020036 + mww phys 0x021b0008 0x09444040 + mww phys 0x021b000c 0x8A8F7955 + mww phys 0x021b0010 0xFF328F64 + mww phys 0x021b0014 0x01FF00DB + mww phys 0x021b0018 0x00001740 + mww phys 0x021b001c 0x00008000 + mww phys 0x021b002c 0x000026d2 + mww phys 0x021b0030 0x008F1023 + mww phys 0x021b0040 0x00000047 + mww phys 0x021b0000 0x841A0000 + mww phys 0x021b001c 0x04088032 + mww phys 0x021b001c 0x00008033 + mww phys 0x021b001c 0x00048031 + mww phys 0x021b001c 0x09408030 + mww phys 0x021b001c 0x04008040 + mww phys 0x021b0020 0x00005800 + mww phys 0x021b0818 0x00011117 + mww phys 0x021b4818 0x00011117 + mww phys 0x021b0004 0x00025576 + mww phys 0x021b0404 0x00011006 + mww phys 0x021b001c 0x00000000 + + # set the default clock gate to save power + mww phys 0x020c4068 0x00C03F3F + mww phys 0x020c406c 0x0030FC03 + mww phys 0x020c4070 0x0FFFC000 + mww phys 0x020c4074 0x3FF00000 + mww phys 0x020c4078 0xFFFFF300 + mww phys 0x020c407c 0x0F0000F3 + mww phys 0x020c4080 0x00000FFF + + # enable AXI cache for VDOA/VPU/IPU + mww phys 0x020e0010 0xF00000CF + # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 + mww phys 0x020e0018 0x007F007F + mww phys 0x020e001c 0x007F007F +} + +proc ddr_init_imx6qp { } { + echo "Bootstrap: Initializing DDR for i.MX6Q+" + + mww phys 0x020e0798 0x000C0000 + mww phys 0x020e0758 0x00000000 + mww phys 0x020e0588 0x00000030 + mww phys 0x020e0594 0x00000030 + mww phys 0x020e056c 0x00000030 + mww phys 0x020e0578 0x00000030 + mww phys 0x020e074c 0x00000030 + mww phys 0x020e057c 0x00000030 + mww phys 0x020e058c 0x00000000 + mww phys 0x020e059c 0x00000030 + mww phys 0x020e05a0 0x00000030 + mww phys 0x020e078c 0x00000030 + mww phys 0x020e0750 0x00020000 + mww phys 0x020e05a8 0x00000030 + mww phys 0x020e05b0 0x00000030 + mww phys 0x020e0524 0x00000030 + mww phys 0x020e051c 0x00000030 + mww phys 0x020e0518 0x00000030 + mww phys 0x020e050c 0x00000030 + mww phys 0x020e05b8 0x00000030 + mww phys 0x020e05c0 0x00000030 + mww phys 0x020e0774 0x00020000 + mww phys 0x020e0784 0x00000030 + mww phys 0x020e0788 0x00000030 + mww phys 0x020e0794 0x00000030 + mww phys 0x020e079c 0x00000030 + mww phys 0x020e07a0 0x00000030 + mww phys 0x020e07a4 0x00000030 + mww phys 0x020e07a8 0x00000030 + mww phys 0x020e0748 0x00000030 + mww phys 0x020e05ac 0x00000030 + mww phys 0x020e05b4 0x00000030 + mww phys 0x020e0528 0x00000030 + mww phys 0x020e0520 0x00000030 + mww phys 0x020e0514 0x00000030 + mww phys 0x020e0510 0x00000030 + mww phys 0x020e05bc 0x00000030 + mww phys 0x020e05c4 0x00000030 + mww phys 0x021b0800 0xa1390003 + mww phys 0x021b080c 0x001b001e + mww phys 0x021b0810 0x002e0029 + mww phys 0x021b480c 0x001b002a + mww phys 0x021b4810 0x0019002c + mww phys 0x021b083c 0x43240334 + mww phys 0x021b0840 0x0324031a + mww phys 0x021b483c 0x43340344 + mww phys 0x021b4840 0x03280276 + mww phys 0x021b0848 0x44383A3E + mww phys 0x021b4848 0x3C3C3846 + mww phys 0x021b0850 0x2e303230 + mww phys 0x021b4850 0x38283E34 + mww phys 0x021b081c 0x33333333 + mww phys 0x021b0820 0x33333333 + mww phys 0x021b0824 0x33333333 + mww phys 0x021b0828 0x33333333 + mww phys 0x021b481c 0x33333333 + mww phys 0x021b4820 0x33333333 + mww phys 0x021b4824 0x33333333 + mww phys 0x021b4828 0x33333333 + mww phys 0x021b08c0 0x24912492 + mww phys 0x021b48c0 0x24912492 + mww phys 0x021b08b8 0x00000800 + mww phys 0x021b48b8 0x00000800 + mww phys 0x021b0004 0x00020036 + mww phys 0x021b0008 0x09444040 + mww phys 0x021b000c 0x898E7955 + mww phys 0x021b0010 0xFF328F64 + mww phys 0x021b0014 0x01FF00DB + mww phys 0x021b0018 0x00001740 + mww phys 0x021b001c 0x00008000 + + mww phys 0x021b002c 0x000026d2 + mww phys 0x021b0030 0x008E1023 + mww phys 0x021b0040 0x00000047 + mww phys 0x021b0400 0x14420000 + mww phys 0x021b0000 0x841A0000 + mww phys 0x00bb0008 0x00000004 + mww phys 0x00bb000c 0x2891E41A + mww phys 0x00bb0038 0x00000564 + mww phys 0x00bb0014 0x00000040 + mww phys 0x00bb0028 0x00000020 + mww phys 0x00bb002c 0x00000020 + mww phys 0x021b001c 0x04088032 + mww phys 0x021b001c 0x00008033 + mww phys 0x021b001c 0x00048031 + mww phys 0x021b001c 0x09408030 + mww phys 0x021b001c 0x04008040 + mww phys 0x021b0020 0x00005800 + mww phys 0x021b0818 0x00011117 + mww phys 0x021b4818 0x00011117 + mww phys 0x021b0004 0x00025576 + mww phys 0x021b0404 0x00011006 + mww phys 0x021b001c 0x00000000 + + # set the default clock gate to save power + mww phys 0x020c4068 0x00C03F3F + mww phys 0x020c406c 0x0030FC03 + mww phys 0x020c4070 0x0FFFC000 + mww phys 0x020c4074 0x3FF00000 + mww phys 0x020c4078 0xFFFFF300 + mww phys 0x020c407c 0x0F0000F3 + mww phys 0x020c4080 0x00000FFF + + # enable AXI cache for VDOA/VPU/IPU + mww phys 0x020e0010 0xF00000CF + # set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 + mww phys 0x020e0018 0x77177717 + mww phys 0x020e001c 0x77177717 +} + +proc ddr_init { } { + # + # Steps to detect 6Q vs 6Q+ are borrowed from + # arch/arm/mach-imx/inclue/mach/imx6.h + # + set MX6_ANATOP_BASE_ADDR 0x020c8000 + set IMX6_ANATOP_SI_REV 0x260 + set si_rev [mrw [expr $MX6_ANATOP_BASE_ADDR + $IMX6_ANATOP_SI_REV]] + set rev_major [expr ($si_rev >> 8) & 0xF] + + if { $rev_major >= 1 } { + ddr_init_imx6qp + } else { + ddr_init_imx6q + } +} + +proc start_barebox { } { + set MX6_DDR_BASE_ADDR 0x10000000 + echo "Bootstrap: Loading Barebox" + halt + load_image images/barebox-zii-imx6-rdu2.img $MX6_DDR_BASE_ADDR bin + arm core_state arm + echo [format "Bootstrap: Jumping to 0x%08x" $MX6_DDR_BASE_ADDR] + resume $MX6_DDR_BASE_ADDR +} + +proc board_init { } { + disable_wdog + ddr_init +} + +${_TARGETNAME}.0 configure -event reset-init { board_init } diff --git a/Documentation/boards/imx/zii-imx6-rdu2/readme.rst b/Documentation/boards/imx/zii-imx6-rdu2/readme.rst new file mode 100644 index 0000000000..4694f2e30e --- /dev/null +++ b/Documentation/boards/imx/zii-imx6-rdu2/readme.rst @@ -0,0 +1,31 @@ +ZII i.MX6 RDU2 Boards +===================== + +Building Barebox +---------------- + +To build Barebox for ZII RDU2 boards do the following: + +.. code-block:: sh + + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> mrproper + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> imx_v7_defconfig + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> + +Uploading Barebox via JTAG +-------------------------- + +Barebox can be bootstrapped via JTAG using OpenOCD (latest master) as +follows: + +.. code-block:: sh + + cd barebox + Documentation/boards/imx/zii-imx6-rdu2/bootstrap.sh + +A custom OpenOCD binary and options can be specified as follows: + +.. code-block:: sh + + OPENOCD="../openocd/src/openocd -s ../openocd/tcl " \ + Documentation/boards/imx/zii-imx6-rdu2/bootstrap.sh diff --git a/Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh b/Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh new file mode 100755 index 0000000000..49bab03200 --- /dev/null +++ b/Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh @@ -0,0 +1,6 @@ +#!/bin/sh + +OPENOCD=${OPENOCD:-openocd} +DIR=$(CDPATH= cd -- "$(dirname -- "$0")" && pwd) + +${OPENOCD} -f ${DIR}/openocd.cfg --command "adapter_khz 10000; init; safe_reset; start_barebox;" diff --git a/Documentation/boards/imx/zii-imx7d-rpu2/openocd.cfg b/Documentation/boards/imx/zii-imx7d-rpu2/openocd.cfg new file mode 100644 index 0000000000..675832b7cf --- /dev/null +++ b/Documentation/boards/imx/zii-imx7d-rpu2/openocd.cfg @@ -0,0 +1,143 @@ +# +# Board configuration file for the Zodiac RPU2 board +# + +interface ftdi +ftdi_vid_pid 0x0403 0x6011 + +ftdi_layout_init 0x0038 0x007b +ftdi_layout_signal nSRST -data 0x0010 +ftdi_layout_signal LED -data 0x0020 + +transport select jtag + +reset_config srst_only srst_push_pull connect_deassert_srst + +# set a slow default JTAG clock, can be overridden later +adapter_khz 1000 + +# need at least 100ms delay after SRST release for JTAG +adapter_nsrst_delay 100 + +# source the target file +source [find target/imx7.cfg] +source [find mem_helper.tcl] + +# function to disable the on-chip watchdog +proc disable_wdog { } { + echo "Bootstrap: Disabling SoC watchdog" + mwh phys 0x30280008 0x00 +} + +set ddr_init_failed 0 + +proc check_bits_set_32 { addr mask } { + while { [expr [mrw $addr] & $mask == 0] } { } +} + +proc ddr_init { } { + echo "Bootstrap: Initializing DDR" + + mww phys 0x30340004 0x4F400005 + # Clear then set bit30 to ensure exit from DDR retention + mww phys 0x30360388 0x40000000 + mww phys 0x30360384 0x40000000 + + mww phys 0x30391000 0x00000002 + mww phys 0x307a0000 0x01040001 + mww phys 0x307a01a0 0x80400003 + mww phys 0x307a01a4 0x00100020 + mww phys 0x307a01a8 0x80100004 + mww phys 0x307a0064 0x00400046 + mww phys 0x307a0490 0x00000001 + mww phys 0x307a00d0 0x00020083 + mww phys 0x307a00d4 0x00690000 + mww phys 0x307a00dc 0x09300004 + mww phys 0x307a00e0 0x04080000 + mww phys 0x307a00e4 0x00100004 + mww phys 0x307a00f4 0x0000033f + mww phys 0x307a0100 0x09081109 + mww phys 0x307a0104 0x0007020d + mww phys 0x307a0108 0x03040407 + mww phys 0x307a010c 0x00002006 + mww phys 0x307a0110 0x04020205 + mww phys 0x307a0114 0x03030202 + mww phys 0x307a0120 0x00000803 + mww phys 0x307a0180 0x00800020 + mww phys 0x307a0184 0x02000100 + mww phys 0x307a0190 0x02098204 + mww phys 0x307a0194 0x00030303 + mww phys 0x307a0200 0x00000016 + mww phys 0x307a0204 0x00171717 + mww phys 0x307a0214 0x04040404 + mww phys 0x307a0218 0x0f040404 + mww phys 0x307a0240 0x06000604 + mww phys 0x307a0244 0x00000001 + mww phys 0x30391000 0x00000000 + mww phys 0x30790000 0x17420f40 + mww phys 0x30790004 0x10210100 + mww phys 0x30790010 0x00060807 + mww phys 0x307900b0 0x1010007e + mww phys 0x3079009c 0x00000d6e + mww phys 0x30790020 0x08080808 + mww phys 0x30790030 0x08080808 + mww phys 0x30790050 0x01000010 + mww phys 0x30790050 0x00000010 + + mww phys 0x307900c0 0x0e407304 + mww phys 0x307900c0 0x0e447304 + mww phys 0x307900c0 0x0e447306 + + check_bits_set_32 0x307900c4 0x1 + + mww phys 0x307900c0 0x0e447304 + mww phys 0x307900c0 0x0e407304 + + mww phys 0x30384130 0x00000000 + mww phys 0x30340020 0x00000178 + mww phys 0x30384130 0x00000002 + mww phys 0x30790018 0x0000000f + + check_bits_set_32 0x307900c4 0x1 +} + +# This function applies the initial configuration after a "reset init" +# command +proc board_init { } { + global ddr_init_failed + disable_wdog + + if {[catch {ddr_init} errmsg]} { + set ddr_init_failed 1 + } else { + set ddr_init_failed 0 + } +} + +proc safe_reset {} { + global ddr_init_failed + + set status 5 + while { $status != 0 } { + reset init + if { $ddr_init_failed == 1 } { + incr status -1 + } else { + set status 0 + } + } +} + +proc start_barebox { } { + set MX7_DDR_BASE_ADDR 0x80000000 + echo "Bootstrap: Loading Barebox" + halt + load_image images/barebox-zii-imx7d-rpu2.img $MX7_DDR_BASE_ADDR bin + arm core_state arm + echo [format "Bootstrap: Jumping to 0x%08x" $MX7_DDR_BASE_ADDR] + resume $MX7_DDR_BASE_ADDR +} + +# hook the init function into the reset-init event +${_TARGETNAME}.0 configure -event reset-init { board_init } + diff --git a/Documentation/boards/imx/zii-imx7d-rpu2/readme.rst b/Documentation/boards/imx/zii-imx7d-rpu2/readme.rst new file mode 100644 index 0000000000..dd984ac176 --- /dev/null +++ b/Documentation/boards/imx/zii-imx7d-rpu2/readme.rst @@ -0,0 +1,47 @@ +ZII i.MX7D Based Boards +======================= + +Building Barebox +---------------- + +To build Barebox for ZII i.MX7 based boards do the following: + +.. code-block:: sh + + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> mrproper + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> imx_v7_defconfig + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> + +Uploading Barebox via JTAG +-------------------------- + +Barebox can be bootstrapped via JTAG using OpenOCD (latest master) as +follows: + +.. code-block:: sh + + cd barebox + Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh + +A custom OpenOCD binary and options can be specified as follows: + +.. code-block:: sh + + OPENOCD="../openocd/src/openocd -s ../openocd/tcl " \ + Documentation/boards/imx/zii-imx7d-rpu2/bootstrap.sh + + +Disabling DSA in Embedeed Switch +-------------------------------- + +Booting the Linux kernel that the device ships with will re-configure the on-board +switch into DSA mode, which would make the Ethernet connection unusable in +Barebox. To undo that and re-configure the switch into dumb/pass-through +mode, do the following: + +.. code-block:: sh + + memset -b -d /dev/switch-eeprom 0x00 0xff 4 + +Once that is done, power cycling the device should force the switch to +re-read the EEPROM and reconfigure itself. diff --git a/Documentation/boards/imx/zii-imx8mq-dev/bootstrap.sh b/Documentation/boards/imx/zii-imx8mq-dev/bootstrap.sh new file mode 100755 index 0000000000..7342e890ec --- /dev/null +++ b/Documentation/boards/imx/zii-imx8mq-dev/bootstrap.sh @@ -0,0 +1,6 @@ +#!/bin/sh + +OPENOCD=${OPENOCD:-openocd} +DIR=$(CDPATH= cd -- "$(dirname -- "$0")" && pwd) + +${OPENOCD} -f ${DIR}/openocd.cfg --command "adapter_khz 10000; init; reset init; start_barebox" diff --git a/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg b/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg index 31f94227e6..cc0bec6b74 100644 --- a/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg +++ b/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg @@ -1,3 +1,7 @@ +# +# Board configuration file for the Zodiac RDU3 boards +# + interface ftdi ftdi_vid_pid 0x0403 0x6011 @@ -5,13 +9,11 @@ ftdi_layout_init 0x0038 0x003b ftdi_layout_signal nSRST -data 0x0010 ftdi_layout_signal LED -data 0x0020 -# Board has a standard ARM-20 JTAG connector with -# nSRST available. -reset_config srst_only srst_push_pull connect_deassert_srst - # select JTAG transport select jtag +reset_config srst_only srst_push_pull connect_deassert_srst + # set a slow default JTAG clock, can be overridden later adapter_khz 1000 @@ -27,60 +29,61 @@ source [find target/imx8m.cfg] source [find mem_helper.tcl] proc ddr_init { } { - # - # We use the same start address as is configured in our i.MX boot - # header (address originally taken from U-Boot). - # - set IMX8MQ_TCM_BASE_ADDR 0x007e1000 - set IMX8MQ_TCM_MAX_SIZE 0x3f000 - # - # Header word at offset 0x28 is not used on AArch64 and is just - # filled with placeholder value 0xffff_ffff, see - # arch/arm/include/asm/barebox-arm-head.h for more details - # - set RDU3_TCM_MAIC_LOCATION [expr $IMX8MQ_TCM_BASE_ADDR + 0x28] - set RDU3_TCM_MAGIC_REQUEST 0xdeadbeef - set RDU3_TCM_MAGIC_REPLY 0xbaadf00d - - echo "==== Uploading DDR helper ====" - - halt - load_image images/start_zii_imx8mq_dev.pblb \ - $IMX8MQ_TCM_BASE_ADDR \ + echo "Bootstrap: Initializing DDR" + # + # We use the same start address as is configured in our i.MX boot + # header (address originally taken from U-Boot). + # + set IMX8MQ_TCM_BASE_ADDR 0x007e1000 + set IMX8MQ_TCM_MAX_SIZE 0x3f000 + # + # Header word at offset 0x28 is not used on AArch64 and is just + # filled with placeholder value 0xffff_ffff, see + # arch/arm/include/asm/barebox-arm-head.h for more details + # + set RDU3_TCM_MAIC_LOCATION [expr $IMX8MQ_TCM_BASE_ADDR + 0x28] + set RDU3_TCM_MAGIC_REQUEST 0xdeadbeef + set RDU3_TCM_MAGIC_REPLY 0xbaadf00d + + echo "Bootstrap: Uploading DDR helper" + + halt + load_image images/start_zii_imx8mq_dev.pblb \ + $IMX8MQ_TCM_BASE_ADDR \ bin \ $IMX8MQ_TCM_BASE_ADDR \ $IMX8MQ_TCM_MAX_SIZE - echo "==== Running DDR helper ====" + echo "Bootstrap: Running DDR helper" - mww phys $RDU3_TCM_MAIC_LOCATION $RDU3_TCM_MAGIC_REQUEST - resume $IMX8MQ_TCM_BASE_ADDR + mww phys $RDU3_TCM_MAIC_LOCATION $RDU3_TCM_MAGIC_REQUEST + resume $IMX8MQ_TCM_BASE_ADDR - echo "==== Waiting for DDR helper to finish ====" + echo "Bootstrap: Waiting for DDR helper to finish" - if {[catch {wait_halt} errmsg] || - [mrw $RDU3_TCM_MAIC_LOCATION] != $RDU3_TCM_MAGIC_REPLY} { - echo "==== DDR initialization FAILED ====" - } else { - echo "==== DDR is ready ====" - } + if {[catch {wait_halt} errmsg] || + [mrw $RDU3_TCM_MAIC_LOCATION] != $RDU3_TCM_MAGIC_REPLY} { + echo "Bootstrap: DDR initialization FAILED" + } else { + echo "Bootstrap: DDR is ready" + } } proc start_barebox {} { - # - # We have to place our image at MX8MQ_ATF_BL33_BASE_ADDR in order - # to be able to initialize ATF firmware since that's where it - # expects entry point to BL33 would be - # - set MX8MQ_ATF_BL33_BASE_ADDR 0x40200000 - - echo "==== Starting Barebox ====" - load_image images/start_zii_imx8mq_dev.pblb $MX8MQ_ATF_BL33_BASE_ADDR bin - resume $MX8MQ_ATF_BL33_BASE_ADDR + # + # We have to place our image at MX8MQ_ATF_BL33_BASE_ADDR in order + # to be able to initialize ATF firmware since that's where it + # expects entry point to BL33 would be + # + set MX8MQ_ATF_BL33_BASE_ADDR 0x40200000 + echo "Bootstrap: Loading Barebox" + load_image images/start_zii_imx8mq_dev.pblb $MX8MQ_ATF_BL33_BASE_ADDR bin + echo [format "Bootstrap: Jumping to 0x%08x" $MX8MQ_ATF_BL33_BASE_ADDR] + resume $MX8MQ_ATF_BL33_BASE_ADDR } -# proc board_init { } { -# ddr_init -# } +proc board_init { } { + ddr_init +} -# ${_TARGETNAME}.0 configure -event reset-init { board_init } +${_TARGETNAME}.0 configure -event reset-init { board_init } diff --git a/Documentation/boards/imx/zii-imx8mq-dev/readme.rst b/Documentation/boards/imx/zii-imx8mq-dev/readme.rst index dc031e4af4..363e00e6ca 100644 --- a/Documentation/boards/imx/zii-imx8mq-dev/readme.rst +++ b/Documentation/boards/imx/zii-imx8mq-dev/readme.rst @@ -20,5 +20,5 @@ follows: .. code-block:: sh - cd barebox - openocd -f Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg --command "init; ddr_init; start_barebox" + cd barebox + Documentation/boards/imx/zii-imx8mq-dev/bootstrap.sh diff --git a/Documentation/boards/imx/zii-vf610-dev/bootstrap.sh b/Documentation/boards/imx/zii-vf610-dev/bootstrap.sh new file mode 100755 index 0000000000..49bab03200 --- /dev/null +++ b/Documentation/boards/imx/zii-vf610-dev/bootstrap.sh @@ -0,0 +1,6 @@ +#!/bin/sh + +OPENOCD=${OPENOCD:-openocd} +DIR=$(CDPATH= cd -- "$(dirname -- "$0")" && pwd) + +${OPENOCD} -f ${DIR}/openocd.cfg --command "adapter_khz 10000; init; safe_reset; start_barebox;" diff --git a/Documentation/boards/imx/zii-vf610-dev/openocd.cfg b/Documentation/boards/imx/zii-vf610-dev/openocd.cfg new file mode 100644 index 0000000000..509f9e33c2 --- /dev/null +++ b/Documentation/boards/imx/zii-vf610-dev/openocd.cfg @@ -0,0 +1,259 @@ +# +# Board configuration file for the Zodiac VF6xx based boards +# + +interface ftdi +ftdi_vid_pid 0x0403 0x6011 + +ftdi_layout_init 0x0038 0x007b +ftdi_layout_signal nSRST -data 0x0010 +ftdi_layout_signal LED -data 0x0020 + +# select JTAG +transport select jtag + +# Board has a standard ARM-20 JTAG connector with +# nSRST available. +reset_config srst_only srst_push_pull connect_deassert_srst + +# set a slow default JTAG clock, can be overridden later +adapter_khz 1000 + +# Source generic VF6xx target configuration +source [find target/vybrid_vf6xx.cfg] +source [find mem_helper.tcl] + +set ddr_init_failed 0 + +proc check_bits_set_32 { addr mask } { + while { [expr [mrw $addr] & $mask == 0] } { } +} + +proc ddr_init { } { + echo "Bootstrap: Initializing DDR" + + mww phys 0x40048220 0x00000180 + mww phys 0x40048224 0x00000180 + mww phys 0x40048228 0x00000180 + mww phys 0x4004822c 0x00000180 + mww phys 0x40048230 0x00000180 + mww phys 0x40048234 0x00000180 + mww phys 0x40048238 0x00000180 + mww phys 0x4004823c 0x00000180 + mww phys 0x40048240 0x00000180 + mww phys 0x40048244 0x00000180 + mww phys 0x40048248 0x00000180 + mww phys 0x4004824c 0x00000180 + mww phys 0x40048250 0x00000180 + mww phys 0x40048254 0x00000180 + mww phys 0x40048258 0x00000180 + mww phys 0x4004825c 0x00000180 + mww phys 0x40048260 0x00000180 + mww phys 0x40048264 0x00000180 + mww phys 0x40048268 0x00000180 + mww phys 0x4004826c 0x00000180 + mww phys 0x40048270 0x00000180 + mww phys 0x40048274 0x00010180 + mww phys 0x40048278 0x00000180 + mww phys 0x4004827c 0x00000180 + mww phys 0x40048280 0x00000180 + mww phys 0x40048284 0x00000180 + mww phys 0x40048288 0x00000180 + mww phys 0x4004828c 0x00000180 + mww phys 0x40048290 0x00000180 + mww phys 0x40048294 0x00000180 + mww phys 0x40048298 0x00000180 + mww phys 0x4004829c 0x00000180 + mww phys 0x400482a0 0x00000180 + mww phys 0x400482a4 0x00000180 + mww phys 0x400482a8 0x00000180 + mww phys 0x400482ac 0x00000180 + mww phys 0x400482b0 0x00000180 + mww phys 0x400482b4 0x00000180 + mww phys 0x400482b8 0x00000180 + mww phys 0x400482bc 0x00000180 + mww phys 0x400482c0 0x00000180 + mww phys 0x400482c4 0x00010180 + mww phys 0x400482c8 0x00010180 + mww phys 0x400482cc 0x00000180 + mww phys 0x400482d0 0x00000180 + mww phys 0x400482d4 0x00000180 + mww phys 0x400482d8 0x00000180 + mww phys 0x4004821c 0x00000180 + + mww phys 0x400482dc 0x00000180 + mww phys 0x400482e0 0x00000180 + + mww phys 0x400ae000 0x00000600 + mww phys 0x400ae008 0x00000005 + mww phys 0x400ae028 0x00013880 + mww phys 0x400ae02c 0x00030d40 + mww phys 0x400ae030 0x0000050c + mww phys 0x400ae034 0x15040400 + mww phys 0x400ae038 0x1406040f + mww phys 0x400ae040 0x04040000 + mww phys 0x400ae044 0x006db00c + mww phys 0x400ae048 0x00000403 + mww phys 0x400ae050 0x01000000 + mww phys 0x400ae054 0x00060001 + mww phys 0x400ae058 0x000c0000 + mww phys 0x400ae05c 0x03000200 + mww phys 0x400ae060 0x00000006 + mww phys 0x400ae064 0x00010000 + mww phys 0x400ae068 0x0c300068 + mww phys 0x400ae070 0x00000000 + mww phys 0x400ae074 0x00000003 + mww phys 0x400ae078 0x0000000a + mww phys 0x400ae07c 0x006c0200 + mww phys 0x400ae084 0x00010000 + mww phys 0x400ae088 0x00050500 + mww phys 0x400ae098 0x00000000 + mww phys 0x400ae09c 0x04001002 + mww phys 0x400ae0a4 0x00000001 + mww phys 0x400ae0c0 0x00460420 + mww phys 0x400ae108 0x01000200 + mww phys 0x400ae10c 0x00000040 + mww phys 0x400ae114 0x00000200 + mww phys 0x400ae118 0x00000040 + mww phys 0x400ae120 0x00000000 + mww phys 0x400ae124 0x0a010100 + mww phys 0x400ae128 0x01014040 + mww phys 0x400ae12c 0x01010101 + mww phys 0x400ae130 0x03030100 + mww phys 0x400ae134 0x01000101 + mww phys 0x400ae138 0x0700000c + mww phys 0x400ae13c 0x00000000 + mww phys 0x400ae148 0x10000000 + mww phys 0x400ae15c 0x01000000 + mww phys 0x400ae160 0x00040000 + mww phys 0x400ae164 0x00000002 + mww phys 0x400ae16c 0x00020000 + mww phys 0x400ae180 0x00002819 + mww phys 0x400ae184 0x01000000 + mww phys 0x400ae188 0x00000000 + mww phys 0x400ae18c 0x00000000 + mww phys 0x400ae198 0x00010100 + mww phys 0x400ae1a4 0x00000000 + mww phys 0x400ae1a8 0x00000004 + mww phys 0x400ae1b8 0x00040000 + mww phys 0x400ae1d4 0x00000000 + mww phys 0x400ae1d8 0x01010000 + mww phys 0x400ae1e0 0x02020000 + mww phys 0x400ae1e4 0x00000202 + mww phys 0x400ae1e8 0x01010064 + mww phys 0x400ae1ec 0x00010101 + mww phys 0x400ae1f0 0x00000064 + mww phys 0x400ae1f8 0x00000800 + mww phys 0x400ae210 0x00000506 + mww phys 0x400ae224 0x00020000 + mww phys 0x400ae228 0x01000100 + mww phys 0x400ae22c 0x04070303 + mww phys 0x400ae230 0x00000040 + mww phys 0x400ae23c 0x06000080 + mww phys 0x400ae240 0x04070303 + mww phys 0x400ae244 0x00000040 + mww phys 0x400ae248 0x00000040 + mww phys 0x400ae24c 0x000f0000 + mww phys 0x400ae250 0x000f0000 + mww phys 0x400ae25c 0x00000101 + mww phys 0x400ae268 0x682c4000 + mww phys 0x400ae26c 0x00000081 + mww phys 0x400ae278 0x00000006 + mww phys 0x400ae284 0x00010606 + + mww phys 0x400ae400 0x00002613 + mww phys 0x400ae440 0x00002613 + mww phys 0x400ae404 0x00002615 + mww phys 0x400ae444 0x00002615 + mww phys 0x400ae408 0x00210000 + mww phys 0x400ae448 0x00210000 + mww phys 0x400ae488 0x00210000 + mww phys 0x400ae40c 0x0001012a + mww phys 0x400ae44c 0x0001012a + mww phys 0x400ae48c 0x0001012a + mww phys 0x400ae410 0x00002400 + mww phys 0x400ae450 0x00002400 + mww phys 0x400ae490 0x00002400 + mww phys 0x400ae4c4 0x00000000 + mww phys 0x400ae4c8 0x00001100 + mww phys 0x400ae4d0 0x00010101 + + mww phys 0x400ae000 0x00000601 +} + +proc clock_init { } { + echo "Bootstrap: Initializing clocks" + # + # This code assumes that debugger would be unable to prevent + # MaskROM initialization code from running before halting the + # processor. TODO: Port the initial clock settings as + # specified in TRM + # + # Ungate all of the peripheral clocks + # + mww phys 0x4006b040 0xffffffff + mww phys 0x4006b044 0xffffffff + mww phys 0x4006b048 0xffffffff + mww phys 0x4006b04c 0xffffffff + mww phys 0x4006b050 0xffffffff + mww phys 0x4006b058 0xffffffff + mww phys 0x4006b05c 0xffffffff + mww phys 0x4006b060 0xffffffff + mww phys 0x4006b064 0xffffffff + mww phys 0x4006b068 0xffffffff + mww phys 0x4006b06c 0xffffffff + # + # There are two possibilities for clocking DDR controller: ARM + # Cortex A core clock or PLL2 PFD4. Mask ROM configures ARM + # Cortex A clock to run at 264Mhz which is not sufficient to + # run DDR (it requres 300Mhz minimum) so instead we configure + # PLL2 PFD4 as a DDR clock + # + # PLL2 on, Fout = Fin * 22 + # + mww phys 0x40050030 0x00002001 + + check_bits_set_32 0x40050030 0x80000000 + + mww phys 0x4006b008 [expr [mrw 0x4006b008] & ~0x00000040] + mww phys 0x4006b008 [expr [mrw 0x4006b008] | 0x00002000] +} + +# This function applies the initial configuration after a "reset init" +# command +proc board_init { } { + global ddr_init_failed + clock_init + + if {[catch {ddr_init} errmsg]} { + set ddr_init_failed 1 + } else { + set ddr_init_failed 0 + } +} + +proc safe_reset {} { + global ddr_init_failed + + set status 5 + while { $status != 0 } { + reset init + if { $ddr_init_failed == 1 } { + incr status -1 + } else { + set status 0 + } + } +} + +proc start_barebox { } { + set VF610_DDR_BASE_ADDR 0x80000000 + echo "Bootstrap: Loading Barebox" + halt + load_image images/barebox-zii-vf610-dev.img $VF610_DDR_BASE_ADDR bin + arm core_state arm + echo [format "Bootstrap: Jumping to 0x%08x" $VF610_DDR_BASE_ADDR] + resume $VF610_DDR_BASE_ADDR +} + +${_TARGETNAME}0 configure -event reset-init { board_init } diff --git a/Documentation/boards/imx/zii-vf610-dev/readme.rst b/Documentation/boards/imx/zii-vf610-dev/readme.rst new file mode 100644 index 0000000000..08ae0e0e67 --- /dev/null +++ b/Documentation/boards/imx/zii-vf610-dev/readme.rst @@ -0,0 +1,53 @@ +ZII VF610 Based Boards +====================== + +Building Barebox +---------------- + +To build Barebox for ZII VF610 based boards do the following: + +.. code-block:: sh + + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> mrproper + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> zii_vf610_dev_defconfig + make ARCH=arm CROSS_COMPILE=<ARM toolchain prefix> + +Uploading Barebox via JTAG +-------------------------- + +Barebox can be bootstrapped via JTAG using OpenOCD (latest master) as +follows: + +.. code-block:: sh + + cd barebox + Documentation/boards/imx/zii-vf610-dev/bootstrap.sh + +A custom OpenOCD binary and options can be specified as follows: + +.. code-block:: sh + + OPENOCD="../openocd/src/openocd -s ../openocd/tcl " \ + Documentation/boards/imx/zii-vf610-dev/bootstrap.sh + +Writing Barebox to NVM +---------------------- + +With exception of Dev boards, all of ZII's VF610 based boards should +come with eMMC. To permanently write Barebox to it do: + +.. code-block:: sh + + barebox_update -t eMMC -y barebox.img + +This should also automatically configure your board to boot that +image. Note that the original ZII stack's bootloader in eMMC should be +left intact. Barebox is configured to be programmed to one of the MMC boot +partitions, whereas the original bootloader is located in user partition. + +To restore the board to booting using the original bootloader do: + +.. code-block:: sh + + detect mmc0 + mmc0.boot=disabled diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index cbd6bd1ed6..bdf78d068d 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_MACH_CFA10036) += crystalfontz-cfa10036/ obj-$(CONFIG_MACH_CHUMBY) += chumby_falconwing/ obj-$(CONFIG_MACH_CLEP7212) += clep7212/ obj-$(CONFIG_MACH_DFI_FS700_M60) += dfi-fs700-m60/ +obj-$(CONFIG_MACH_DIGI_CCIMX6ULSBCPRO) += digi-ccimx6ulsom/ obj-$(CONFIG_MACH_DUCKBILL) += duckbill/ obj-$(CONFIG_MACH_DSS11) += dss11/ obj-$(CONFIG_MACH_EDB93012) += edb93xx/ @@ -166,4 +167,4 @@ obj-$(CONFIG_MACH_ZII_VF610_DEV) += zii-vf610-dev/ obj-$(CONFIG_MACH_ZII_IMX7D_RPU2) += zii-imx7d-rpu2/ obj-$(CONFIG_MACH_WAGO_PFC_AM35XX) += wago-pfc-am35xx/ obj-$(CONFIG_MACH_LS1046ARDB) += ls1046ardb/ -obj-$(CONFIG_MACH_TQMLS1046A) += tqmls1046a/
\ No newline at end of file +obj-$(CONFIG_MACH_TQMLS1046A) += tqmls1046a/ diff --git a/arch/arm/boards/digi-ccimx6ulsom/Makefile b/arch/arm/boards/digi-ccimx6ulsom/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/digi-ccimx6ulsom/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/digi-ccimx6ulsom/board.c b/arch/arm/boards/digi-ccimx6ulsom/board.c new file mode 100644 index 0000000000..1fb451548f --- /dev/null +++ b/arch/arm/boards/digi-ccimx6ulsom/board.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2019 Rouven Czerwinski, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation. + * + */ + +#include <common.h> +#include <init.h> +#include <mach/generic.h> +#include <mach/bbu.h> + +static int digi_ccimx6ulsbcpro_device_init(void) +{ + if (!of_machine_is_compatible("digi,ccimx6ulsbcpro")) + return 0; + + imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); + + barebox_set_hostname("ccimx6ulsbcpro"); + + return 0; +} +device_initcall(digi_ccimx6ulsbcpro_device_init); diff --git a/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg b/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg new file mode 100644 index 0000000000..36edad7a3e --- /dev/null +++ b/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg @@ -0,0 +1,82 @@ +loadaddr 0x80000000 +soc imx6 +dcdofs 0x400 + +/* Enable all clocks */ +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff + +/* IOMUX */ +/* DDR IO type */ +wm 32 0x020E04B4 0x000C0000 +wm 32 0x020E04AC 0x00000000 +/* Clock */ +wm 32 0x020E027C 0x00000030 +/* Control */ +wm 32 0x020E0250 0x00000030 +wm 32 0x020E024C 0x00000030 +wm 32 0x020E0490 0x00000030 +wm 32 0x020E0288 0x00000030 +wm 32 0x020E0270 0x00000000 +wm 32 0x020E0260 0x00000030 +wm 32 0x020E0264 0x00000030 +wm 32 0x020E04A0 0x00000030 +/* Data strobe */ +wm 32 0x020E0494 0x00020000 +wm 32 0x020E0280 0x00000030 +wm 32 0x020E0284 0x00000030 +/* Data */ +wm 32 0x020E04B0 0x00020000 +wm 32 0x020E0498 0x00000030 +wm 32 0x020E04A4 0x00000030 +wm 32 0x020E0244 0x00000030 +wm 32 0x020E0248 0x00000030 + +/* DDR Controller registers */ +wm 32 0x021B001C 0x00008000 +wm 32 0x021B0800 0xA1390003 +/* Calibration values */ +wm 32 0x021B080C 0x00000000 +wm 32 0x021B083C 0x413B013B +wm 32 0x021B0848 0x4040373E +wm 32 0x021B0850 0x40405954 +wm 32 0x021B081C 0x33333333 +wm 32 0x021B0820 0x33333333 +wm 32 0x021B082C 0xf3333333 +wm 32 0x021B0830 0xf3333333 +/* END of calibration values */ +wm 32 0x021B08C0 0x00921012 +wm 32 0x021B08b8 0x00000800 + +/* MMDC init */ +wm 32 0x021B0004 0x0002002D +wm 32 0x021B0008 0x1b333030 +wm 32 0x021B000C 0x676B52F3 +wm 32 0x021B0010 0xB66D0B63 +wm 32 0x021B0014 0x01FF00DB +/* Consider reducing RALAT (currently set to 5) */ +wm 32 0x021B0018 0x00201740 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B002C 0x000026D2 +wm 32 0x021B0030 0x006B1023 +wm 32 0x021B0040 0x00000047 +wm 32 0x021B0000 0x83180000 + +/* Mode registers writes for CS0 */ +wm 32 0x021B001C 0x02008032 +wm 32 0x021B001C 0x00008033 +wm 32 0x021B001C 0x00048031 +wm 32 0x021B001C 0x15208030 +wm 32 0x021B001C 0x04008040 + +/* Final DDR setup */ +wm 32 0x021B0020 0x00000800 +wm 32 0x021B0818 0x00000227 +wm 32 0x021B0004 0x0002552D +wm 32 0x021B0404 0x00011006 +wm 32 0x021B001C 0x00000000 diff --git a/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c b/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c new file mode 100644 index 0000000000..ac76a843ac --- /dev/null +++ b/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c @@ -0,0 +1,32 @@ +#include <common.h> +#include <mach/generic.h> +#include <asm/barebox-arm.h> +#include <mach/esdctl.h> +#include <asm/cache.h> + + +extern char __dtb_z_imx6ul_ccimx6ulsbcpro_start[]; + +ENTRY_FUNCTION(start_imx6ul_ccimx6ulsbcpro, r0, r1, r2) +{ + void *fdt; + + imx6ul_cpu_lowlevel_init(); + + arm_setup_stack(0x00910000 - 8); + + arm_early_mmu_cache_invalidate(); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + /* disable all watchdog powerdown counters */ + writew(0x0, 0x020bc008); + writew(0x0, 0x020c0008); + writew(0x0, 0x021e4008); + + fdt = __dtb_z_imx6ul_ccimx6ulsbcpro_start; + + imx6ul_barebox_entry(fdt); +} diff --git a/arch/arm/boards/zii-common/pn-fixup.h b/arch/arm/boards/zii-common/pn-fixup.h index 39b848bd00..925e8ad634 100644 --- a/arch/arm/boards/zii-common/pn-fixup.h +++ b/arch/arm/boards/zii-common/pn-fixup.h @@ -15,6 +15,8 @@ #ifndef __ZII_PN_FIXUP__ #define __ZII_PN_FIXUP__ +#include <linux/stddef.h> + struct zii_pn_fixup { const char *pn; void (*callback) (const struct zii_pn_fixup *fixup); diff --git a/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/net b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/net new file mode 100644 index 0000000000..4090c2f4a9 --- /dev/null +++ b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/net @@ -0,0 +1,24 @@ +#!/bin/sh + +path="/mnt/tftp" + +# clear seat network config +global.linux.bootargs.rdu_network= + +global.bootm.image="${path}/${global.user}-linux-${global.hostname}" + +oftree="${path}/${global.user}-oftree-${global.hostname}" +if [ -f "${oftree}" ]; then + global.bootm.oftree="$oftree" +fi + +nfsroot="/home/${global.user}/nfsroot/${global.hostname}" + +ip_route_get -b ${global.net.server} global.linux.bootargs.dyn.ip + +initramfs="${path}/${global.user}-initramfs-${global.hostname}" +if [ -f "${initramfs}" ]; then + global.bootm.initrd="$initramfs" +else + global.linux.bootargs.dyn.root="root=/dev/nfs nfsroot=$nfsroot,v3,tcp" +fi
\ No newline at end of file diff --git a/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/nfs b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/nfs new file mode 100644 index 0000000000..4f9671f9cd --- /dev/null +++ b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/nfs @@ -0,0 +1,7 @@ +#!/bin/sh + +# clear seat network config +global.linux.bootargs.rdu_network= + +backlight0.brightness=0 +boot /mnt/nfs diff --git a/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/rdu-default b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/rdu-default new file mode 100644 index 0000000000..f391d91eba --- /dev/null +++ b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/rdu-default @@ -0,0 +1,13 @@ +#!/bin/sh + +backlight0.brightness=0 +if [ "$bootsource" = "spi-nor" ]; then + boot mmc1 +else + detect mmc3 + if [ "$mmc3.boot" = "boot0" ]; then + boot mmc3.0 + else + boot mmc3.1 + fi +fi diff --git a/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/network/eth0-discover b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/network/eth0-discover new file mode 100644 index 0000000000..00f3120115 --- /dev/null +++ b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/network/eth0-discover @@ -0,0 +1,4 @@ +#!/bin/sh + +# reset switch to clear DSA config +rave_reset_switch diff --git a/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/nv/autoboot_abort_key b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/nv/autoboot_abort_key new file mode 100644 index 0000000000..55920c9a58 --- /dev/null +++ b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/nv/autoboot_abort_key @@ -0,0 +1 @@ +ctrl-c
\ No newline at end of file diff --git a/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/nv/boot.default b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/nv/boot.default index 3cfe9bafdc..9076a1e64e 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/nv/boot.default +++ b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/nv/boot.default @@ -1 +1 @@ -mmc1
\ No newline at end of file +rdu-default
\ No newline at end of file diff --git a/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/nv/dev.eth1.mode b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/nv/dev.eth1.mode new file mode 100644 index 0000000000..87e7bdaaec --- /dev/null +++ b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/nv/dev.eth1.mode @@ -0,0 +1 @@ +disabled
\ No newline at end of file diff --git a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c index a5ac6f64c2..9672a69bfd 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c +++ b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c @@ -271,11 +271,6 @@ static noinline void rdu2_sram_setup(void) enum bootsource bootsrc; int instance; - imx6_ungate_all_peripherals(); - - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); - arm_setup_stack(0x00920000 - 8); relocate_to_current_adr(); setup_c(); @@ -296,6 +291,11 @@ ENTRY_FUNCTION(start_imx6_zii_rdu2, r0, r1, r2) { imx6_cpu_lowlevel_init(); + imx6_ungate_all_peripherals(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + /* * When still running in SRAM, we need to setup the DRAM now and load * the remaining image. diff --git a/arch/arm/boards/zii-imx8mq-dev/Makefile b/arch/arm/boards/zii-imx8mq-dev/Makefile index 2995f06f0f..d0148b5067 100644 --- a/arch/arm/boards/zii-imx8mq-dev/Makefile +++ b/arch/arm/boards/zii-imx8mq-dev/Makefile @@ -1,2 +1,3 @@ obj-y += board.o lwl-y += lowlevel.o ddr_init.o ddrphy_train.o +bbenv-y += defaultenv-imx8mq-zii-dev diff --git a/arch/arm/boards/zii-imx8mq-dev/board.c b/arch/arm/boards/zii-imx8mq-dev/board.c index 94e71f58ce..144adb9cef 100644 --- a/arch/arm/boards/zii-imx8mq-dev/board.c +++ b/arch/arm/boards/zii-imx8mq-dev/board.c @@ -4,7 +4,9 @@ * Author: Andrey Smirnov <andrew.smirnov@gmail.com> */ +#include <bootsource.h> #include <common.h> +#include <envfs.h> #include <init.h> #include <asm/memory.h> #include <linux/sizes.h> @@ -19,6 +21,13 @@ static int zii_imx8mq_dev_init(void) imx8mq_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", 0); + if (bootsource_get_instance() == 0) + of_device_enable_path("/chosen/environment-emmc"); + else + of_device_enable_path("/chosen/environment-sd"); + + defaultenv_append_directory(defaultenv_imx8mq_zii_dev); + return 0; } device_initcall(zii_imx8mq_dev_init); diff --git a/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/boot/net b/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/boot/net new file mode 100644 index 0000000000..4090c2f4a9 --- /dev/null +++ b/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/boot/net @@ -0,0 +1,24 @@ +#!/bin/sh + +path="/mnt/tftp" + +# clear seat network config +global.linux.bootargs.rdu_network= + +global.bootm.image="${path}/${global.user}-linux-${global.hostname}" + +oftree="${path}/${global.user}-oftree-${global.hostname}" +if [ -f "${oftree}" ]; then + global.bootm.oftree="$oftree" +fi + +nfsroot="/home/${global.user}/nfsroot/${global.hostname}" + +ip_route_get -b ${global.net.server} global.linux.bootargs.dyn.ip + +initramfs="${path}/${global.user}-initramfs-${global.hostname}" +if [ -f "${initramfs}" ]; then + global.bootm.initrd="$initramfs" +else + global.linux.bootargs.dyn.root="root=/dev/nfs nfsroot=$nfsroot,v3,tcp" +fi
\ No newline at end of file diff --git a/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/boot/nfs b/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/boot/nfs new file mode 100644 index 0000000000..cd3a545409 --- /dev/null +++ b/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/boot/nfs @@ -0,0 +1,6 @@ +#!/bin/sh + +# clear seat network config +global.linux.bootargs.rdu_network= + +boot /mnt/nfs diff --git a/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/boot/rdu-default b/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/boot/rdu-default new file mode 100644 index 0000000000..f5d8fe2125 --- /dev/null +++ b/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/boot/rdu-default @@ -0,0 +1,7 @@ +#!/bin/sh + +if [ "$bootsource_instance" = "0" ]; then + boot mmc0 +else + boot mmc1 +fi diff --git a/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/nv/autoboot_abort_key b/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/nv/autoboot_abort_key new file mode 100644 index 0000000000..55920c9a58 --- /dev/null +++ b/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/nv/autoboot_abort_key @@ -0,0 +1 @@ +ctrl-c
\ No newline at end of file diff --git a/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/nv/boot.default b/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/nv/boot.default new file mode 100644 index 0000000000..9076a1e64e --- /dev/null +++ b/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/nv/boot.default @@ -0,0 +1 @@ +rdu-default
\ No newline at end of file diff --git a/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/nv/dev.eth1.mode b/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/nv/dev.eth1.mode new file mode 100644 index 0000000000..87e7bdaaec --- /dev/null +++ b/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/nv/dev.eth1.mode @@ -0,0 +1 @@ +disabled
\ No newline at end of file diff --git a/arch/arm/boards/zii-vf610-dev/defaultenv-zii-vf610-dev/nv/dev.eth1.mode b/arch/arm/boards/zii-vf610-dev/defaultenv-zii-vf610-dev/nv/dev.eth1.mode new file mode 100644 index 0000000000..87e7bdaaec --- /dev/null +++ b/arch/arm/boards/zii-vf610-dev/defaultenv-zii-vf610-dev/nv/dev.eth1.mode @@ -0,0 +1 @@ +disabled
\ No newline at end of file diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c3292354a1..561653930b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -23,6 +23,7 @@ pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o pbl-dtb-$(CONFIG_MACH_TX53) += imx53-tx53-xx30.dtb.o imx53-tx53-1011.dtb.o pbl-dtb-$(CONFIG_MACH_CCMX51) += imx51-ccxmx51.dtb.o pbl-dtb-$(CONFIG_MACH_CCMX53) += imx53-ccxmx53.dtb.o +pbl-dtb-$(CONFIG_MACH_DIGI_CCIMX6ULSBCPRO) += imx6ul-ccimx6ulsbcpro.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += imx7d-sdb.dtb.o pbl-dtb-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o diff --git a/arch/arm/dts/imx51-zii-rdu1.dts b/arch/arm/dts/imx51-zii-rdu1.dts index 01e46baf2d..a4f6654e3f 100644 --- a/arch/arm/dts/imx51-zii-rdu1.dts +++ b/arch/arm/dts/imx51-zii-rdu1.dts @@ -25,6 +25,23 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Address will be determined by the bootloader */ + ramoops@afe00000 { + compatible = "ramoops"; + reg = <0xafe00000 0x200000>; + ecc-size = <16>; + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x20000>; + pmsg-size = <0x20000>; + }; + }; + aliases { /* * NVMEM device corresponding to EEPROM attached to @@ -91,6 +108,10 @@ }; }; +&fec { + status = "disabled"; +}; + &iomuxc { pinctrl_usbh1: usbh1grp { diff --git a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi index bfc75ba606..5d141fcb34 100644 --- a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi @@ -65,6 +65,23 @@ switch-eeprom = &switch; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Address will be determined by the bootloader */ + ramoops@2fe00000 { + compatible = "ramoops"; + reg = <0x2fe00000 0x200000>; + ecc-size = <16>; + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x20000>; + pmsg-size = <0x20000>; + }; + }; + panel { compatible = "simple-panel"; /* Timings for all supported panels, the correct one is enabled diff --git a/arch/arm/dts/imx6sx-sdb.dts b/arch/arm/dts/imx6sx-sdb.dts index 18d873ccf2..8cf412a39f 100644 --- a/arch/arm/dts/imx6sx-sdb.dts +++ b/arch/arm/dts/imx6sx-sdb.dts @@ -19,6 +19,10 @@ }; }; +&fec1 { + /delete-property/ phy-reset-gpios; +}; + &ocotp { barebox,provide-mac-address = <&fec1 0x620 &fec2 0x632>; }; diff --git a/arch/arm/dts/imx6sx-udoo-neo-full.dts b/arch/arm/dts/imx6sx-udoo-neo-full.dts index 9203d40207..1609781b7f 100644 --- a/arch/arm/dts/imx6sx-udoo-neo-full.dts +++ b/arch/arm/dts/imx6sx-udoo-neo-full.dts @@ -1,4 +1,29 @@ #include <arm/imx6sx-udoo-neo-full.dts> -/{ +/ { + chosen { + environment { + compatible = "barebox,environment"; + device-path = &environment_usdhc2; + }; + }; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + environment_usdhc2: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&ocotp { + barebox,provide-mac-address = <&fec1 0x620>; }; diff --git a/arch/arm/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/dts/imx6ul-ccimx6ulsbcpro.dts new file mode 100644 index 0000000000..1139c4b7d6 --- /dev/null +++ b/arch/arm/dts/imx6ul-ccimx6ulsbcpro.dts @@ -0,0 +1,41 @@ +#include <arm/imx6ul-ccimx6ulsbcpro.dts> + +/{ + chosen { + stdout-path = &uart5; + + environment-nand { + compatible = "barebox,environment"; + device-path = &gpmi, "partname:barebox-environment"; + status = "okay"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x400000>; + }; + + partition@400000 { + label = "barebox-environment"; + reg = <0x400000 0x100000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x0>; + }; + }; +}; diff --git a/arch/arm/dts/imx8mq-zii-ultra.dtsi b/arch/arm/dts/imx8mq-zii-ultra.dtsi index ccf80d3de8..53679b0d3c 100644 --- a/arch/arm/dts/imx8mq-zii-ultra.dtsi +++ b/arch/arm/dts/imx8mq-zii-ultra.dtsi @@ -10,6 +10,17 @@ / { chosen { stdout-path = &uart1; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &usdhc1, "partname:barebox-environment"; + status = "disabled"; + }; + environment-sd { + compatible = "barebox,environment"; + device-path = &usdhc2, "partname:barebox-environment"; + status = "disabled"; + }; }; mdio0: bitbang-mdio { @@ -348,6 +359,19 @@ no-sd; no-sdio; status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; }; &usdhc2 { @@ -358,6 +382,19 @@ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; vmmc-supply = <®_usdhc2_vmmc>; status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; }; &iomuxc { diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 71d37cee90..6a6aab634c 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -505,6 +505,12 @@ config MACH_GRINN_LITEBOARD bool "Grinn liteboard" select ARCH_IMX6UL +config MACH_DIGI_CCIMX6ULSBCPRO + bool "Digi Internal CC-IMX6UL SBC Pro" + select ARCH_IMX6 + select ARCH_IMX6UL + select ARM_USE_COMPRESSED_DTB + endif # ---------------------------------------------------------- diff --git a/arch/arm/mach-imx/imx8-ddrc.c b/arch/arm/mach-imx/imx8-ddrc.c index 18454a9153..736865eb6f 100644 --- a/arch/arm/mach-imx/imx8-ddrc.c +++ b/arch/arm/mach-imx/imx8-ddrc.c @@ -29,7 +29,7 @@ static u32 ddrc_phy_get_message(void __iomem *phy, int type) /* * When BIT0 set to 0, the PMU has a message for the user - * 10ms seems not enough for poll message, so use 1s here. + * Wait for it indefinitely. */ readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004), r, !(r & BIT(0)), 0); @@ -104,4 +104,4 @@ void ddrc_phy_wait_training_complete(void __iomem *phy) putc_ll('\r'); putc_ll('\n'); } -}
\ No newline at end of file +} diff --git a/commands/mw.c b/commands/mw.c index 2912997a31..3ed6c820d0 100644 --- a/commands/mw.c +++ b/commands/mw.c @@ -63,23 +63,31 @@ static int do_mem_mw(int argc, char *argv[]) u64 val64; switch (mode) { case O_RWSIZE_1: - val8 = simple_strtoul(argv[optind], NULL, 0); + ret = kstrtou8(argv[optind], 0, &val8); + if (ret) + goto illegal_number; ret = write(fd, &val8, 1); break; case O_RWSIZE_2: - val16 = simple_strtoul(argv[optind], NULL, 0); + ret = kstrtou16(argv[optind], 0, &val16); + if (ret) + goto illegal_number; if (swab) val16 = __swab16(val16); ret = write(fd, &val16, 2); break; case O_RWSIZE_4: - val32 = simple_strtoul(argv[optind], NULL, 0); + ret = kstrtou32(argv[optind], 0, &val32); + if (ret) + goto illegal_number; if (swab) val32 = __swab32(val32); ret = write(fd, &val32, 4); break; case O_RWSIZE_8: - val64 = simple_strtoull(argv[optind], NULL, 0); + ret = kstrtou64(argv[optind], 0, &val64); + if (ret) + goto illegal_number; if (swab) val64 = __swab64(val64); ret = write(fd, &val64, 8); @@ -96,6 +104,14 @@ static int do_mem_mw(int argc, char *argv[]) close(fd); return ret ? 1 : 0; + +illegal_number: + printf("\"%s\" is not a valid %d bit number\n", argv[optind], + (mode >> O_RWSIZE_SHIFT) * 8); + + close(fd); + + return 1; } BAREBOX_CMD_HELP_START(mw) diff --git a/common/imx-bbu-nand-fcb.c b/common/imx-bbu-nand-fcb.c index a29a1bf91a..6d773b59df 100644 --- a/common/imx-bbu-nand-fcb.c +++ b/common/imx-bbu-nand-fcb.c @@ -606,9 +606,10 @@ static int imx_bbu_write_firmware(struct mtd_info *mtd, unsigned num, void *buf, int ret, i, newbadblock = 0; int num_blocks = imx_bbu_firmware_max_blocks(mtd); int block = imx_bbu_firmware_start_block(mtd, num); + int page = block * mtd->erasesize / mtd->writesize; - pr_info("writing firmware %d to block %d (ofs 0x%08x)\n", - num, block, block * mtd->erasesize); + pr_info("writing firmware to slot %d on pages %d-%d\n", + num, page, page + len / mtd->writesize); for (i = 0; i < num_blocks; i++) { if (mtd_peb_is_bad(mtd, block + i)) @@ -976,6 +977,9 @@ static int imx_bbu_write_fcbs_dbbts(struct mtd_info *mtd, struct fcb_block *fcb) */ memset(fcb_raw_page + mtd->writesize, 0xFF, 2); + pr_info("Writing FCBs/DBBTs with primary/secondary Firmwares at pages %d/%d\n", + fcb->Firmware1_startingPage, fcb->Firmware2_startingPage); + for (i = 0; i < 4; i++) { if (mtd_peb_is_bad(mtd, i)) continue; @@ -1108,7 +1112,7 @@ err: if (need_cleaning) { pr_warn("Firmware at page %d needs cleanup\n", first_page); - return -EUCLEAN; + return 1; } return 0; @@ -1162,13 +1166,14 @@ static void read_firmware_all(struct mtd_info *mtd, struct fcb_block *fcb, void *unused_refresh = 1; *used = first; *data = primary; - return; } else if (secondary && !primary) { *used_refresh = secondary_refresh; *unused_refresh = 1; *used = !first; *data = secondary; } else { + *unused_refresh = secondary_refresh; + if (memcmp(primary, secondary, fcb->PagesInFirmware1 * mtd->writesize)) *unused_refresh = 1; @@ -1178,15 +1183,20 @@ static void read_firmware_all(struct mtd_info *mtd, struct fcb_block *fcb, void free(secondary); } - pr_info("Primary firmware is on pages %d-%d, %svalid, %s\n", fcb->Firmware1_startingPage, + pr_info("Primary firmware is in slot %d on pages %d-%d, %svalid, %s\n", + first, + fcb->Firmware1_startingPage, fcb->Firmware1_startingPage + fcb->PagesInFirmware1, primary ? "" : "in", primary_refresh ? "needs cleanup" : "clean"); - pr_info("Secondary firmware is on pages %d-%d, %svalid, %s\n", fcb->Firmware2_startingPage, + pr_info("Secondary firmware is in slot %d on pages %d-%d, %svalid, %s\n", + !first, + fcb->Firmware2_startingPage, fcb->Firmware2_startingPage + fcb->PagesInFirmware2, secondary ? "" : "in", secondary_refresh ? "needs cleanup" : "clean"); - pr_info("ROM uses slot %d\n", *used); + pr_info("ROM uses slot %d (%s firmware)\n", + *used, primary ? "primary" : secondary ? "secondary" : "no"); } static int imx_bbu_nand_update(struct bbu_handler *handler, struct bbu_data *data) @@ -1331,6 +1341,12 @@ static int imx_bbu_nand_update(struct bbu_handler *handler, struct bbu_data *dat fw = fw_orig; fw_size = fw_orig_len; pr_info("Refreshing existing firmware\n"); + + if (used_refresh) { + fcb->Firmware1_startingPage = imx_bbu_firmware_fcb_start_page(mtd, !used); + fcb->Firmware2_startingPage = imx_bbu_firmware_fcb_start_page(mtd, used); + fcb_create(imx_handler, fcb, mtd); + } } if (num_blocks_fw * mtd->erasesize < fw_size) { diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c index d70f4416cb..4f7e097a89 100644 --- a/drivers/clk/imx/clk-vf610.c +++ b/drivers/clk/imx/clk-vf610.c @@ -535,7 +535,7 @@ static int vf610_switch_cpu_clock_to_400mhz(void) { int ret; uint32_t cr117; - void * __iomem ddrmc = IOMEM(VF610_DDR_BASE_ADDR); + void __iomem *ddrmc = IOMEM(VF610_DDR_BASE_ADDR); ret = clk_set_parent(clk[VF610_CLK_PLL2_PFD_SEL], clk[VF610_CLK_PLL2_PFD2]); if (ret < 0) { diff --git a/drivers/nvmem/ocotp.c b/drivers/nvmem/ocotp.c index 5b8b925cb4..3f9f162860 100644 --- a/drivers/nvmem/ocotp.c +++ b/drivers/nvmem/ocotp.c @@ -51,7 +51,7 @@ #define OCOTP_CTRL_WR_UNLOCK_KEY 0x3E77 #define OCOTP_CTRL_WR_UNLOCK_MASK 0xFFFF0000 #define OCOTP_CTRL_ADDR 0 -#define OCOTP_CTRL_ADDR_MASK 0x0000007F +#define OCOTP_CTRL_ADDR_MASK 0x000000FF #define OCOTP_CTRL_BUSY (1 << 8) #define OCOTP_CTRL_ERROR (1 << 9) #define OCOTP_CTRL_RELOAD_SHADOWS (1 << 10) @@ -59,6 +59,7 @@ #define OCOTP_TIMING_STROBE_READ_MASK 0x003F0000 #define OCOTP_TIMING_RELAX_MASK 0x0000F000 #define OCOTP_TIMING_STROBE_PROG_MASK 0x00000FFF +#define OCOTP_TIMING_WAIT_MASK 0x0FC00000 #define OCOTP_READ_CTRL_READ_FUSE 0x00000001 @@ -68,7 +69,9 @@ /* Other definitions */ #define IMX6_OTP_DATA_ERROR_VAL 0xBADABADA -#define DEF_RELAX 20 +#define TIMING_STROBE_PROG_US 10 +#define TIMING_STROBE_READ_NS 37 +#define TIMING_RELAX_NS 17 #define MAC_OFFSET_0 (0x22 * 4) #define IMX6UL_MAC_OFFSET_1 (0x23 * 4) #define MAC_OFFSET_1 (0x24 * 4) @@ -118,13 +121,42 @@ static int imx6_ocotp_set_timing(struct ocotp_priv *priv) u32 relax, strobe_read, strobe_prog; u32 timing; + /* + * Note: there are minimum timings required to ensure an OTP fuse burns + * correctly that are independent of the ipg_clk. Those values are not + * formally documented anywhere however, working from the minimum + * timings given in u-boot we can say: + * + * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10 + * microseconds feels about right as representative of a minimum time + * to physically burn out a fuse. + * + * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before + * performing another read is 37 nanoseconds + * + * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum + * timing is not entirely clear the documentation says "This + * count value specifies the time to add to all default timing + * parameters other than the Tpgm and Trd. It is given in number + * of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG + * and STROBE_READ respectively. What the other timing parameters + * are though, is not specified. Experience shows a zero RELAX + * value will mess up a re-load of the shadow registers post OTP + * burn. + */ clk_rate = clk_get_rate(priv->clk); - relax = clk_rate / (1000000000 / DEF_RELAX) - 1; - strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1; - strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1; + relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1; + + strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS, + 1000000000); + strobe_read += 2 * (relax + 1) - 1; + strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US, + 1000000); + strobe_prog += 2 * (relax + 1) - 1; - timing = BF(relax, OCOTP_TIMING_RELAX); + timing = readl(priv->base + OCOTP_TIMING) & OCOTP_TIMING_WAIT_MASK; + timing |= BF(relax, OCOTP_TIMING_RELAX); timing |= BF(strobe_read, OCOTP_TIMING_STROBE_READ); timing |= BF(strobe_prog, OCOTP_TIMING_STROBE_PROG); diff --git a/images/.gitignore b/images/.gitignore index 7a74937814..fcde7f3c42 100644 --- a/images/.gitignore +++ b/images/.gitignore @@ -4,7 +4,6 @@ *.imximg *.imximg.prep *.imximg.signed -*.imx-sram-img *.map *.src *.kwbimg diff --git a/images/Makefile b/images/Makefile index e525e0d277..479647a827 100644 --- a/images/Makefile +++ b/images/Makefile @@ -181,5 +181,5 @@ $(flash-list): $(image-y-path) clean-files := *.pbl *.pblb *.map start_*.imximg *.img barebox.z start_*.kwbimg \ start_*.kwbuartimg *.socfpgaimg *.mlo *.t20img *.t20img.cfg *.t30img \ *.t30img.cfg *.t124img *.t124img.cfg *.mlospi *.mlo *.mxsbs *.mxssd \ - start_*.simximg start_*.usimximg *.imx-sram-img *.image + start_*.simximg start_*.usimximg *.image clean-files += pbl.lds diff --git a/images/Makefile.imx b/images/Makefile.imx index e6f741cdb4..9a7187ac78 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -519,6 +519,11 @@ CFG_start_imx6ul_pico_hobbit_512mb.pblb.imximg = $(board)/technexion-pico-hobbit FILE_barebox-imx6ul-pico-hobbit-512mb.img = start_imx6ul_pico_hobbit_512mb.pblb.imximg image-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += barebox-imx6ul-pico-hobbit-512mb.img +pblb-$(CONFIG_MACH_DIGI_CCIMX6ULSBCPRO) += start_imx6ul_ccimx6ulsbcpro +CFG_start_imx6ul_ccimx6ulsbcpro.pblb.imximg = $(board)/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg +FILE_barebox-imx6ul-ccimx6ulsbcpro.img = start_imx6ul_ccimx6ulsbcpro.pblb.imximg +image-$(CONFIG_MACH_DIGI_CCIMX6ULSBCPRO) += barebox-imx6ul-ccimx6ulsbcpro.img + # ----------------------- vf6xx based boards --------------------------- pblb-$(CONFIG_MACH_VF610_TWR) += start_vf610_twr CFG_start_vf610_twr.pblb.imximg = $(board)/freescale-vf610-twr/flash-header-vf610-twr.imxcfg diff --git a/scripts/imx/imx-image.c b/scripts/imx/imx-image.c index a7f1421fa3..90be8a9b9b 100644 --- a/scripts/imx/imx-image.c +++ b/scripts/imx/imx-image.c @@ -363,6 +363,15 @@ static void usage(const char *prgname) "-b add barebox header to image. If used, barebox recognizes\n" " the image as regular barebox image which can be used as\n" " second stage image\n" + "-d write DCD table only\n" + "-e prepare image for encryption and use Freescale's Code Signing\n" + " to encrypt image. Note that the device-specific encapsulated\n" + " DEK as cryptgraphic blob needs to be appended afterwards\n" + "-s use Freescale's Code Signing Tool (CST) to sign the image\n" + " 'cst' is expected to be in PATH or given via the environment\n" + " variable 'CST'\n" + "-u create USB image suitable for imx-usb-loader\n" + " necessary for signed images (-s) only\n" "-h this help\n", prgname); exit(1); } diff --git a/scripts/imx/imx-usb-loader.c b/scripts/imx/imx-usb-loader.c index d4fba0ce54..e3d3b8fce1 100644 --- a/scripts/imx/imx-usb-loader.c +++ b/scripts/imx/imx-usb-loader.c @@ -185,6 +185,13 @@ static const struct mach_id imx_ids[] = { .header_type = HDR_MX53, .mode = MODE_HID, .max_transfer = 1024, + }, { + .vid = 0x1fc9, + .pid = 0x012b, + .name = "i.MX8M", + .header_type = HDR_MX53, + .mode = MODE_HID, + .max_transfer = 1024, }, }; |