diff options
1139 files changed, 68008 insertions, 15086 deletions
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index be395a6d55..b208ade9e6 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -543,7 +543,6 @@ static int imx8mp_clocks_init(struct device_node *ccm_np) hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200); hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1); - hws[IMX8MP_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", ccm_base + 0x9180, 0, 1); hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000); hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080); diff --git a/dts/Bindings/Makefile b/dts/Bindings/Makefile index c9abfbe3f0..41c555181b 100644 --- a/dts/Bindings/Makefile +++ b/dts/Bindings/Makefile @@ -65,7 +65,9 @@ DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd))) override DTC_FLAGS := \ -Wno-avoid_unnecessary_addr_size \ -Wno-graph_child_address \ - -Wno-interrupt_provider + -Wno-interrupt_provider \ + -Wno-unique_unit_address \ + -Wunique_unit_address_if_enabled # Disable undocumented compatible checks until warning free override DT_CHECKER_FLAGS ?= diff --git a/dts/Bindings/arm/apple.yaml b/dts/Bindings/arm/apple.yaml index 1e772c8520..8d93e8a6cc 100644 --- a/dts/Bindings/arm/apple.yaml +++ b/dts/Bindings/arm/apple.yaml @@ -12,12 +12,19 @@ maintainers: description: | ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon". - This currently includes devices based on the "M1" SoC, starting with the - three Mac models released in late 2020: + This currently includes devices based on the "M1" SoC: - Mac mini (M1, 2020) - MacBook Pro (13-inch, M1, 2020) - MacBook Air (M1, 2020) + - iMac (24-inch, M1, 2021) + + And devices based on the "M1 Pro" and "M1 Max" SoCs: + + - MacBook Pro (14-inch, M1 Pro, 2021) + - MacBook Pro (14-inch, M1 Max, 2021) + - MacBook Pro (16-inch, M1 Pro, 2021) + - MacBook Pro (16-inch, M1 Max, 2021) The compatible property should follow this format: @@ -56,8 +63,24 @@ properties: - apple,j274 # Mac mini (M1, 2020) - apple,j293 # MacBook Pro (13-inch, M1, 2020) - apple,j313 # MacBook Air (M1, 2020) + - apple,j456 # iMac (24-inch, 4x USB-C, M1, 2021) + - apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021) - const: apple,t8103 - const: apple,arm-platform + - description: Apple M1 Pro SoC based platforms + items: + - enum: + - apple,j314s # MacBook Pro (14-inch, M1 Pro, 2021) + - apple,j316s # MacBook Pro (16-inch, M1 Pro, 2021) + - const: apple,t6000 + - const: apple,arm-platform + - description: Apple M1 Max SoC based platforms + items: + - enum: + - apple,j314c # MacBook Pro (14-inch, M1 Max, 2021) + - apple,j316c # MacBook Pro (16-inch, M1 Max, 2021) + - const: apple,t6001 + - const: apple,arm-platform additionalProperties: true diff --git a/dts/Bindings/arm/apple/apple,pmgr.yaml b/dts/Bindings/arm/apple/apple,pmgr.yaml new file mode 100644 index 0000000000..b6b5d3a912 --- /dev/null +++ b/dts/Bindings/arm/apple/apple,pmgr.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/apple/apple,pmgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC Power Manager (PMGR) + +maintainers: + - Hector Martin <marcan@marcan.st> + +description: | + Apple SoCs include PMGR blocks responsible for power management, + which can control various clocks, resets, power states, and + performance features. This node represents the PMGR as a syscon, + with sub-nodes representing individual features. + +properties: + $nodename: + pattern: "^power-management@[0-9a-f]+$" + + compatible: + items: + - enum: + - apple,t8103-pmgr + - apple,t6000-pmgr + - const: apple,pmgr + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +patternProperties: + "power-controller@[0-9a-f]+$": + description: + The individual power management domains within this controller + type: object + $ref: /power/apple,pmgr-pwrstate.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + power-management@23b700000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3b700000 0x0 0x14000>; + + ps_sio: power-controller@1c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c0 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + apple,always-on; + }; + + ps_uart_p: power-controller@220 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x220 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart_p"; + power-domains = <&ps_sio>; + }; + + ps_uart0: power-controller@270 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x270 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_uart_p>; + }; + }; + + power-management@23d280000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3d280000 0x0 0xc000>; + + ps_aop_filter: power-controller@4000 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4000 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_filter"; + }; + + ps_aop_base: power-controller@4010 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4010 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_base"; + power-domains = <&ps_aop_filter>; + }; + + ps_aop_shim: power-controller@4038 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4038 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_shim"; + power-domains = <&ps_aop_base>; + }; + + ps_aop_uart0: power-controller@4048 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4048 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_uart0"; + power-domains = <&ps_aop_shim>; + }; + }; + }; diff --git a/dts/Bindings/arm/arm,cci-400.yaml b/dts/Bindings/arm/arm,cci-400.yaml index 4682f991a5..f8530a5086 100644 --- a/dts/Bindings/arm/arm,cci-400.yaml +++ b/dts/Bindings/arm/arm,cci-400.yaml @@ -166,16 +166,6 @@ examples: }; }; - dma0: dma@3000000 { - /* compatible = "arm,pl330", "arm,primecell"; */ - cci-control-port = <&cci_control0>; - reg = <0x0 0x3000000 0x0 0x1000>; - interrupts = <10>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - cci@2c090000 { compatible = "arm,cci-400"; #address-cells = <1>; diff --git a/dts/Bindings/arm/arm-dsu-pmu.txt b/dts/Bindings/arm/arm-dsu-pmu.txt deleted file mode 100644 index 6efabba530..0000000000 --- a/dts/Bindings/arm/arm-dsu-pmu.txt +++ /dev/null @@ -1,27 +0,0 @@ -* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) - -ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores -with a shared L3 memory system, control logic and external interfaces to -form a multicore cluster. The PMU enables to gather various statistics on -the operations of the DSU. The PMU provides independent 32bit counters that -can count any of the supported events, along with a 64bit cycle counter. -The PMU is accessed via CPU system registers and has no MMIO component. - -** DSU PMU required properties: - -- compatible : should be one of : - - "arm,dsu-pmu" - -- interrupts : Exactly 1 SPI must be listed. - -- cpus : List of phandles for the CPUs connected to this DSU instance. - - -** Example: - -dsu-pmu-0 { - compatible = "arm,dsu-pmu"; - interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>; - cpus = <&cpu_0>, <&cpu_1>; -}; diff --git a/dts/Bindings/arm/aspeed/aspeed,sbc.yaml b/dts/Bindings/arm/aspeed/aspeed,sbc.yaml new file mode 100644 index 0000000000..c72aab7064 --- /dev/null +++ b/dts/Bindings/arm/aspeed/aspeed,sbc.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +# Copyright 2021 Joel Stanley, IBM Corp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ASPEED Secure Boot Controller + +maintainers: + - Joel Stanley <joel@jms.id.au> + - Andrew Jeffery <andrew@aj.id.au> + +description: | + The ASPEED SoCs have a register bank for interacting with the secure boot + controller. + +properties: + compatible: + items: + - const: aspeed,ast2600-sbc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + sbc: secure-boot-controller@1e6f2000 { + compatible = "aspeed,ast2600-sbc"; + reg = <0x1e6f2000 0x1000>; + }; diff --git a/dts/Bindings/arm/bcm/brcm,bcm4908.yaml b/dts/Bindings/arm/bcm/brcm,bcm4908.yaml index 2cd4e4a322..9b745531ff 100644 --- a/dts/Bindings/arm/bcm/brcm,bcm4908.yaml +++ b/dts/Bindings/arm/bcm/brcm,bcm4908.yaml @@ -29,6 +29,7 @@ properties: items: - enum: - asus,gt-ac5300 + - netgear,raxe500 - const: brcm,bcm4908 - description: BCM49408 based boards diff --git a/dts/Bindings/arm/cpus.yaml b/dts/Bindings/arm/cpus.yaml index f2ab6423b4..0dcebc48ea 100644 --- a/dts/Bindings/arm/cpus.yaml +++ b/dts/Bindings/arm/cpus.yaml @@ -137,6 +137,9 @@ properties: - arm,cortex-a75 - arm,cortex-a76 - arm,cortex-a77 + - arm,cortex-a78 + - arm,cortex-a510 + - arm,cortex-a710 - arm,cortex-m0 - arm,cortex-m0+ - arm,cortex-m1 @@ -145,8 +148,12 @@ properties: - arm,cortex-r4 - arm,cortex-r5 - arm,cortex-r7 + - arm,cortex-x1 + - arm,cortex-x2 - arm,neoverse-e1 - arm,neoverse-n1 + - arm,neoverse-n2 + - arm,neoverse-v1 - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan @@ -174,6 +181,7 @@ properties: - qcom,kryo560 - qcom,kryo570 - qcom,kryo685 + - qcom,kryo780 - qcom,scorpion enable-method: diff --git a/dts/Bindings/arm/firmware/linaro,optee-tz.yaml b/dts/Bindings/arm/firmware/linaro,optee-tz.yaml index c24047c1fd..9a426110a1 100644 --- a/dts/Bindings/arm/firmware/linaro,optee-tz.yaml +++ b/dts/Bindings/arm/firmware/linaro,optee-tz.yaml @@ -24,6 +24,12 @@ properties: compatible: const: linaro,optee-tz + interrupts: + maxItems: 1 + description: | + This interrupt which is used to signal an event by the secure world + software is expected to be edge-triggered. + method: enum: [smc, hvc] description: | @@ -42,10 +48,12 @@ additionalProperties: false examples: - | + #include <dt-bindings/interrupt-controller/arm-gic.h> firmware { optee { compatible = "linaro,optee-tz"; method = "smc"; + interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>; }; }; diff --git a/dts/Bindings/arm/fsl.yaml b/dts/Bindings/arm/fsl.yaml index 0b595b2606..97f6eebad7 100644 --- a/dts/Bindings/arm/fsl.yaml +++ b/dts/Bindings/arm/fsl.yaml @@ -240,6 +240,7 @@ properties: - uniwest,imx6q-evi # Uniwest Evi - variscite,dt6customboard - wand,imx6q-wandboard # Wandboard i.MX6 Quad Board + - ysoft,imx6q-yapp4-crux # i.MX6 Quad Y Soft IOTA Crux board - zealz,imx6q-gk802 # Zealz GK802 - zii,imx6q-zii-rdu2 # ZII RDU2 Board - const: fsl,imx6q @@ -323,6 +324,20 @@ properties: - const: toradex,apalis_imx6q - const: fsl,imx6q + - description: TQ-Systems TQMa6Q SoM (variant A) on MBa6x + items: + - const: tq,imx6q-mba6x-a + - const: tq,mba6a # Expected by bootloader, to be removed in the future + - const: tq,imx6q-tqma6q-a + - const: fsl,imx6q + + - description: TQ-Systems TQMa6Q SoM (variant B) on MBa6x + items: + - const: tq,imx6q-mba6x-b + - const: tq,mba6b # Expected by bootloader, to be removed in the future + - const: tq,imx6q-tqma6q-b + - const: fsl,imx6q + - description: i.MX6QP based Boards items: - enum: @@ -334,6 +349,7 @@ properties: - kvg,vicutp # Kverneland UT1P board - prt,prtwd3 # Protonic WD3 board - wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board + - ysoft,imx6qp-yapp4-crux-plus # i.MX6 Quad Plus Y Soft IOTA Crux+ board - zii,imx6qp-zii-rdu2 # ZII RDU2+ Board - const: fsl,imx6qp @@ -344,6 +360,13 @@ properties: - const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6 - const: fsl,imx6qp + - description: TQ-Systems TQMa6QP SoM on MBa6x + items: + - const: tq,imx6qp-mba6x-b + - const: tq,mba6b # Expected by bootloader, to be removed in the future + - const: tq,imx6qp-tqma6qp-b + - const: fsl,imx6qp + - description: i.MX6DL based Boards items: - enum: @@ -482,6 +505,20 @@ properties: - const: dh,imx6s-dhcom-som - const: fsl,imx6dl + - description: TQ-Systems TQMa6DL SoM (variant A) on MBa6x + items: + - const: tq,imx6dl-mba6x-a + - const: tq,mba6a # Expected by bootloader, to be removed in the future + - const: tq,imx6dl-tqma6dl-a + - const: fsl,imx6dl + + - description: TQ-Systems TQMa6DL SoM (variant B) on MBa6x + items: + - const: tq,imx6dl-mba6x-b + - const: tq,mba6b # Expected by bootloader, to be removed in the future + - const: tq,imx6dl-tqma6dl-b + - const: fsl,imx6dl + - description: i.MX6SL based Boards items: - enum: @@ -580,6 +617,7 @@ properties: items: - enum: - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board + - joz,jozacp # JOZ Access Point - kontron,imx6ull-n6411-som # Kontron N6411 SOM - myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board - toradex,colibri-imx6ull # Colibri iMX6ULL Modules @@ -632,6 +670,7 @@ properties: - description: i.MX6ULZ based Boards items: - enum: + - bsh,imx6ulz-bsh-smm-m2 # i.MX6 ULZ BSH SystemMaster - fsl,imx6ulz-14x14-evk # i.MX6 ULZ 14x14 EVK Board - const: fsl,imx6ull # This seems odd. Should be last? - const: fsl,imx6ulz @@ -754,10 +793,23 @@ properties: - const: variscite,var-som-mx8mm - const: fsl,imx8mm + - description: + TQMa8MxML is a series of SOM featuring NXP i.MX8MM system-on-chip + variants. It is designed to be soldered on different carrier boards. + All variants (TQMa8M[Q,D,S][L]ML) use the same device tree, hence only + one compatible is needed. + items: + - enum: + - tq,imx8mm-tqma8mqml-mba8mx # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM on MBa8Mx + - const: tq,imx8mm-tqma8mqml # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM + - const: fsl,imx8mm + - description: i.MX8MN based Boards items: - enum: - beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit + - bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2 + - bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board - gw,imx8mn-gw7902 # i.MX8MM Gateworks Board @@ -769,6 +821,17 @@ properties: - const: variscite,var-som-mx8mn - const: fsl,imx8mn + - description: + TQMa8MxNL is a series of SOM featuring NXP i.MX8MN system-on-chip + variants. It is designed to be soldered on different carrier boards. + All variants (TQMa8M[Q,D,S][L]NL) use the same device tree, hence only + one compatible is needed. + items: + - enum: + - tq,imx8mn-tqma8mqnl-mba8mx # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM on MBa8Mx + - const: tq,imx8mn-tqma8mqnl # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM + - const: fsl,imx8mn + - description: i.MX8MP based Boards items: - enum: @@ -805,6 +868,15 @@ properties: - const: purism,librem5 - const: fsl,imx8mq + - description: + TQMa8Mx is a series of SOM featuring NXP i.MX8MQ system-on-chip + variants. It is designed to be clicked on different carrier boards. + items: + - enum: + - tq,imx8mq-tqma8mq-mba8mx # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM on MBa8Mx + - const: tq,imx8mq-tqma8mq # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM + - const: fsl,imx8mq + - description: Zodiac Inflight Innovations Ultra Boards items: - enum: @@ -834,6 +906,12 @@ properties: - const: toradex,colibri-imx8x - const: fsl,imx8qxp + - description: i.MX8ULP based Boards + items: + - enum: + - fsl,imx8ulp-evk # i.MX8ULP EVK Board + - const: fsl,imx8ulp + - description: Freescale Vybrid Platform Device Tree Bindings diff --git a/dts/Bindings/arm/mediatek.yaml b/dts/Bindings/arm/mediatek.yaml index 0fa55497b9..0ffe1acf13 100644 --- a/dts/Bindings/arm/mediatek.yaml +++ b/dts/Bindings/arm/mediatek.yaml @@ -79,6 +79,14 @@ properties: - const: mediatek,mt7629 - items: - enum: + - mediatek,mt7986a-rfb + - const: mediatek,mt7986a + - items: + - enum: + - mediatek,mt7986b-rfb + - const: mediatek,mt7986b + - items: + - enum: - mediatek,mt8127-moose - const: mediatek,mt8127 - items: @@ -134,6 +142,10 @@ properties: - google,krane-sku176 - const: google,krane - const: mediatek,mt8183 + - description: Google Cozmo (Acer Chromebook 314) + items: + - const: google,cozmo + - const: mediatek,mt8183 - description: Google Damu (ASUS Chromebook Flip CM3) items: - const: google,damu @@ -143,7 +155,9 @@ properties: - enum: - google,fennel-sku0 - google,fennel-sku1 + - google,fennel-sku2 - google,fennel-sku6 + - google,fennel-sku7 - const: google,fennel - const: mediatek,mt8183 - description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311) @@ -159,6 +173,12 @@ properties: - const: google,kakadu-rev2 - const: google,kakadu - const: mediatek,mt8183 + - description: Google Kakadu (ASUS Chromebook Detachable CM3) + items: + - const: google,kakadu-rev3-sku22 + - const: google,kakadu-rev2-sku22 + - const: google,kakadu + - const: mediatek,mt8183 - description: Google Kappa (HP Chromebook 11a) items: - const: google,kappa diff --git a/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt b/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt index ea827e8763..3fa7558665 100644 --- a/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -14,6 +14,7 @@ Required Properties: - "mediatek,mt7622-apmixedsys" - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" - "mediatek,mt7629-apmixedsys" + - "mediatek,mt7986-apmixedsys" - "mediatek,mt8135-apmixedsys" - "mediatek,mt8167-apmixedsys", "syscon" - "mediatek,mt8173-apmixedsys" diff --git a/dts/Bindings/arm/mediatek/mediatek,ethsys.txt b/dts/Bindings/arm/mediatek/mediatek,ethsys.txt index 6b7e8067e7..0502db7368 100644 --- a/dts/Bindings/arm/mediatek/mediatek,ethsys.txt +++ b/dts/Bindings/arm/mediatek/mediatek,ethsys.txt @@ -10,6 +10,7 @@ Required Properties: - "mediatek,mt7622-ethsys", "syscon" - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" - "mediatek,mt7629-ethsys", "syscon" + - "mediatek,mt7986-ethsys", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt b/dts/Bindings/arm/mediatek/mediatek,infracfg.txt index eb3523c7a7..f66bd72057 100644 --- a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt +++ b/dts/Bindings/arm/mediatek/mediatek,infracfg.txt @@ -15,6 +15,7 @@ Required Properties: - "mediatek,mt7622-infracfg", "syscon" - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" - "mediatek,mt7629-infracfg", "syscon" + - "mediatek,mt7986-infracfg", "syscon" - "mediatek,mt8135-infracfg", "syscon" - "mediatek,mt8167-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" diff --git a/dts/Bindings/arm/mediatek/mediatek,sgmiisys.txt b/dts/Bindings/arm/mediatek/mediatek,sgmiisys.txt index 30cb645c0e..29ca7a10b3 100644 --- a/dts/Bindings/arm/mediatek/mediatek,sgmiisys.txt +++ b/dts/Bindings/arm/mediatek/mediatek,sgmiisys.txt @@ -8,6 +8,8 @@ Required Properties: - compatible: Should be: - "mediatek,mt7622-sgmiisys", "syscon" - "mediatek,mt7629-sgmiisys", "syscon" + - "mediatek,mt7986-sgmiisys_0", "syscon" + - "mediatek,mt7986-sgmiisys_1", "syscon" - #clock-cells: Must be 1 The SGMIISYS controller uses the common clk binding from diff --git a/dts/Bindings/arm/mediatek/mediatek,topckgen.txt b/dts/Bindings/arm/mediatek/mediatek,topckgen.txt index 5ce7578cf2..b82422bb71 100644 --- a/dts/Bindings/arm/mediatek/mediatek,topckgen.txt +++ b/dts/Bindings/arm/mediatek/mediatek,topckgen.txt @@ -14,6 +14,7 @@ Required Properties: - "mediatek,mt7622-topckgen" - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" - "mediatek,mt7629-topckgen" + - "mediatek,mt7986-topckgen", "syscon" - "mediatek,mt8135-topckgen" - "mediatek,mt8167-topckgen", "syscon" - "mediatek,mt8173-topckgen" diff --git a/dts/Bindings/arm/msm/qcom,llcc.yaml b/dts/Bindings/arm/msm/qcom,llcc.yaml index 62fcbd8833..03882aac8d 100644 --- a/dts/Bindings/arm/msm/qcom,llcc.yaml +++ b/dts/Bindings/arm/msm/qcom,llcc.yaml @@ -24,6 +24,7 @@ properties: - qcom,sc7180-llcc - qcom,sc7280-llcc - qcom,sdm845-llcc + - qcom,sm6350-llcc - qcom,sm8150-llcc - qcom,sm8250-llcc @@ -44,7 +45,6 @@ required: - compatible - reg - reg-names - - interrupts additionalProperties: false diff --git a/dts/Bindings/arm/pmu.yaml b/dts/Bindings/arm/pmu.yaml index e17ac049e8..981bac4516 100644 --- a/dts/Bindings/arm/pmu.yaml +++ b/dts/Bindings/arm/pmu.yaml @@ -44,10 +44,18 @@ properties: - arm,cortex-a76-pmu - arm,cortex-a77-pmu - arm,cortex-a78-pmu + - arm,cortex-a510-pmu + - arm,cortex-a710-pmu + - arm,cortex-x1-pmu + - arm,cortex-x2-pmu - arm,neoverse-e1-pmu - arm,neoverse-n1-pmu + - arm,neoverse-n2-pmu + - arm,neoverse-v1-pmu - brcm,vulcan-pmu - cavium,thunder-pmu + - nvidia,denver-pmu + - nvidia,carmel-pmu - qcom,krait-pmu - qcom,scorpion-pmu - qcom,scorpion-mp-pmu diff --git a/dts/Bindings/arm/qcom.yaml b/dts/Bindings/arm/qcom.yaml index c8808e0f9e..370aab274c 100644 --- a/dts/Bindings/arm/qcom.yaml +++ b/dts/Bindings/arm/qcom.yaml @@ -48,8 +48,10 @@ description: | sdx65 sm7225 sm8150 + sdx65 sm8250 sm8350 + sm8450 The 'board' element must be one of the following strings: @@ -201,8 +203,10 @@ properties: - items: - enum: + - qcom,sc7280-crd - qcom,sc7280-idp - qcom,sc7280-idp2 + - google,hoglin - google,piglin - google,senor - const: qcom,sc7280 @@ -226,6 +230,11 @@ properties: - items: - enum: + - qcom,sdx65-mtp + - const: qcom,sdx65 + + - items: + - enum: - qcom,ipq6018-cp01 - qcom,ipq6018-cp01-c1 - const: qcom,ipq6018 @@ -257,6 +266,11 @@ properties: - qcom,sm8350-mtp - const: qcom,sm8350 + - items: + - enum: + - qcom,sm8450-qrd + - const: qcom,sm8450 + additionalProperties: true ... diff --git a/dts/Bindings/arm/renesas.yaml b/dts/Bindings/arm/renesas.yaml index 5172065078..6a9350ee69 100644 --- a/dts/Bindings/arm/renesas.yaml +++ b/dts/Bindings/arm/renesas.yaml @@ -315,6 +315,18 @@ properties: - const: renesas,falcon-cpu - const: renesas,r8a779a0 + - description: R-Car S4-8 (R8A779F0) + items: + - enum: + - renesas,spider-cpu # Spider CPU board (RTP8A779F0ASKB0SC2S) + - const: renesas,r8a779f0 + + - items: + - enum: + - renesas,spider-breakout # Spider BreakOut board (RTP8A779F0ASKB0SB0S) + - const: renesas,spider-cpu + - const: renesas,r8a779f0 + - description: R-Car H3e (R8A779M0) items: - enum: diff --git a/dts/Bindings/arm/samsung/samsung-boards.yaml b/dts/Bindings/arm/samsung/samsung-boards.yaml index ef6dc14be4..052cd94113 100644 --- a/dts/Bindings/arm/samsung/samsung-boards.yaml +++ b/dts/Bindings/arm/samsung/samsung-boards.yaml @@ -199,6 +199,18 @@ properties: - samsung,exynos7-espresso # Samsung Exynos7 Espresso - const: samsung,exynos7 + - description: Exynos7885 based boards + items: + - enum: + - samsung,jackpotlte # Samsung Galaxy A8 (2018) + - const: samsung,exynos7885 + + - description: Exynos850 based boards + items: + - enum: + - winlink,e850-96 # WinLink E850-96 + - const: samsung,exynos850 + - description: Exynos Auto v9 based boards items: - enum: diff --git a/dts/Bindings/arm/stm32/stm32.yaml b/dts/Bindings/arm/stm32/stm32.yaml index bcaf7be3ab..b07720ea96 100644 --- a/dts/Bindings/arm/stm32/stm32.yaml +++ b/dts/Bindings/arm/stm32/stm32.yaml @@ -77,6 +77,7 @@ properties: items: - enum: - engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 + - engicam,icore-stm32mp1-ctouch2-of10 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF - engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit - const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM - const: st,stm32mp157 diff --git a/dts/Bindings/arm/sunxi.yaml b/dts/Bindings/arm/sunxi.yaml index 889128acf4..c8a3102c0f 100644 --- a/dts/Bindings/arm/sunxi.yaml +++ b/dts/Bindings/arm/sunxi.yaml @@ -808,6 +808,11 @@ properties: - const: oranth,tanix-tx6 - const: allwinner,sun50i-h6 + - description: Tanix TX6 mini + items: + - const: oranth,tanix-tx6-mini + - const: allwinner,sun50i-h6 + - description: TBS A711 Tablet items: - const: tbs-biometrics,a711 diff --git a/dts/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/dts/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml index 29c9961ee2..8eee312c2e 100644 --- a/dts/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml +++ b/dts/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -32,12 +32,38 @@ properties: - allwinner,sun8i-h3-mbus - allwinner,sun8i-r40-mbus - allwinner,sun50i-a64-mbus + - allwinner,sun50i-h5-mbus reg: - maxItems: 1 + minItems: 1 + items: + - description: MBUS interconnect/bandwidth limit/PMU registers + - description: DRAM controller/PHY registers + + reg-names: + minItems: 1 + items: + - const: mbus + - const: dram clocks: + minItems: 1 + items: + - description: MBUS interconnect module clock + - description: DRAM controller/PHY module clock + - description: Register bus clock, shared by MBUS and DRAM + + clock-names: + minItems: 1 + items: + - const: mbus + - const: dram + - const: bus + + interrupts: maxItems: 1 + description: + MBUS PMU activity interrupt. dma-ranges: description: @@ -54,13 +80,55 @@ required: - clocks - dma-ranges +if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-h3-mbus + - allwinner,sun50i-a64-mbus + - allwinner,sun50i-h5-mbus + +then: + properties: + reg: + minItems: 2 + + reg-names: + minItems: 2 + + clocks: + minItems: 3 + + clock-names: + minItems: 3 + + required: + - reg-names + - clock-names + +else: + properties: + reg: + maxItems: 1 + + reg-names: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + additionalProperties: false examples: - | - #include <dt-bindings/clock/sun5i-ccu.h> + #include <dt-bindings/clock/sun50i-a64-ccu.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> - mbus: dram-controller@1c01000 { + dram-controller@1c01000 { compatible = "allwinner,sun5i-a13-mbus"; reg = <0x01c01000 0x1000>; clocks = <&ccu CLK_MBUS>; @@ -70,4 +138,21 @@ examples: #interconnect-cells = <1>; }; + - | + dram-controller@1c62000 { + compatible = "allwinner,sun50i-a64-mbus"; + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x40000000 0xc0000000>; + #interconnect-cells = <1>; + }; + ... diff --git a/dts/Bindings/arm/tegra.yaml b/dts/Bindings/arm/tegra.yaml index d79d36ac0c..49841ca272 100644 --- a/dts/Bindings/arm/tegra.yaml +++ b/dts/Bindings/arm/tegra.yaml @@ -37,6 +37,9 @@ properties: - const: toradex,colibri_t20 - const: nvidia,tegra20 - items: + - const: asus,tf101 + - const: nvidia,tegra20 + - items: - const: acer,picasso - const: nvidia,tegra20 - items: @@ -50,6 +53,18 @@ properties: - const: nvidia,cardhu - const: nvidia,tegra30 - items: + - const: asus,tf201 + - const: nvidia,tegra30 + - items: + - const: asus,tf300t + - const: nvidia,tegra30 + - items: + - const: asus,tf300tg + - const: nvidia,tegra30 + - items: + - const: asus,tf700t + - const: nvidia,tegra30 + - items: - const: toradex,apalis_t30-eval - const: toradex,apalis_t30 - const: nvidia,tegra30 @@ -75,7 +90,11 @@ properties: - const: ouya,ouya - const: nvidia,tegra30 - items: + - const: pegatron,chagall + - const: nvidia,tegra30 + - items: - enum: + - asus,tf701t - nvidia,dalmore - nvidia,roth - nvidia,tn7 @@ -108,14 +127,17 @@ properties: - nvidia,p2571 - nvidia,p2894-0050-a08 - const: nvidia,tegra210 - - items: - - enum: - - nvidia,p2771-0000 - - nvidia,p3509-0000+p3636-0001 + - description: Jetson TX2 Developer Kit + items: + - const: nvidia,p2771-0000 - const: nvidia,tegra186 - - items: - - enum: - - nvidia,p2972-0000 + - description: Jetson TX2 NX Developer Kit + items: + - const: nvidia,p3509-0000+p3636-0001 + - const: nvidia,tegra186 + - description: Jetson AGX Xavier Developer Kit + items: + - const: nvidia,p2972-0000 - const: nvidia,tegra194 - description: Jetson Xavier NX items: @@ -134,8 +156,16 @@ properties: - const: nvidia,p3509-0000+p3668-0001 - const: nvidia,tegra194 - items: - - enum: - - nvidia,tegra234-vdk + - const: nvidia,tegra234-vdk + - const: nvidia,tegra234 + - description: Jetson AGX Orin + items: + - const: nvidia,p3701-0000 + - const: nvidia,tegra234 + - description: Jetson AGX Orin Developer Kit + items: + - const: nvidia,p3737-0000+p3701-0000 + - const: nvidia,p3701-0000 - const: nvidia,tegra234 additionalProperties: true diff --git a/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt deleted file mode 100644 index 576462fae2..0000000000 --- a/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt +++ /dev/null @@ -1,133 +0,0 @@ -NVIDIA Tegra Power Management Controller (PMC) - -Required properties: -- compatible: Should contain one of the following: - - "nvidia,tegra186-pmc": for Tegra186 - - "nvidia,tegra194-pmc": for Tegra194 - - "nvidia,tegra234-pmc": for Tegra234 -- reg: Must contain an (offset, length) pair of the register set for each - entry in reg-names. -- reg-names: Must include the following entries: - - "pmc" - - "wake" - - "aotag" - - "scratch" - - "misc" (Only for Tegra194 and later) - -Optional properties: -- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value must be 2. - -Example: - -SoC DTSI: - - pmc@c3600000 { - compatible = "nvidia,tegra186-pmc"; - reg = <0 0x0c360000 0 0x10000>, - <0 0x0c370000 0 0x10000>, - <0 0x0c380000 0 0x10000>, - <0 0x0c390000 0 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch"; - }; - -Board DTS: - - pmc@c360000 { - nvidia,invert-interrupt; - }; - -== Pad Control == - -On Tegra SoCs a pad is a set of pins which are configured as a group. -The pin grouping is a fixed attribute of the hardware. The PMC can be -used to set pad power state and signaling voltage. A pad can be either -in active or power down mode. The support for power state and signaling -voltage configuration varies depending on the pad in question. 3.3 V and -1.8 V signaling voltages are supported on pins where software -controllable signaling voltage switching is available. - -Pad configurations are described with pin configuration nodes which -are placed under the pmc node and they are referred to by the pinctrl -client properties. For more information see -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. - -The following pads are present on Tegra186: -csia csib dsi mipi-bias -pex-clk-bias pex-clk3 pex-clk2 pex-clk1 -usb0 usb1 usb2 usb-bias -uart audio hsic dbg -hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv -sdmmc4 cam dsib dsic -dsid csic csid csie -dsif spi ufs dmic-hv -edp sdmmc1-hv sdmmc3-hv conn -audio-hv ao-hv - -Required pin configuration properties: - - pins: A list of strings, each of which contains the name of a pad - to be configured. - -Optional pin configuration properties: - - low-power-enable: Configure the pad into power down mode - - low-power-disable: Configure the pad into active mode - - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or - TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. - The values are defined in - include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. - -Note: The power state can be configured on all of the above pads except - for ao-hv. Following pads have software configurable signaling - voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv, - ao-hv. - -Pad configuration state example: - pmc: pmc@7000e400 { - compatible = "nvidia,tegra186-pmc"; - reg = <0 0x0c360000 0 0x10000>, - <0 0x0c370000 0 0x10000>, - <0 0x0c380000 0 0x10000>, - <0 0x0c390000 0 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch"; - - ... - - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1-hv"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; - - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1-hv"; - power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; - }; - - hdmi_off: hdmi-off { - pins = "hdmi"; - low-power-enable; - } - - hdmi_on: hdmi-on { - pins = "hdmi"; - low-power-disable; - } - }; - -Pinctrl client example: - sdmmc1: sdhci@3400000 { - ... - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - }; - - ... - - sor0: sor@15540000 { - ... - pinctrl-0 = <&hdmi_off>; - pinctrl-1 = <&hdmi_on>; - pinctrl-names = "hdmi-on", "hdmi-off"; - }; diff --git a/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.yaml new file mode 100644 index 0000000000..0faa403f68 --- /dev/null +++ b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Power Management Controller (PMC) + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + enum: + - nvidia,tegra186-pmc + - nvidia,tegra194-pmc + - nvidia,tegra234-pmc + + reg: + minItems: 4 + maxItems: 5 + + reg-names: + minItems: 4 + items: + - const: pmc + - const: wake + - const: aotag + - const: scratch + - const: misc + + interrupt-controller: true + + "#interrupt-cells": + description: Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + const: 2 + + nvidia,invert-interrupt: + description: If present, inverts the PMU interrupt signal. + $ref: /schemas/types.yaml#/definitions/flag + +if: + properties: + compatible: + contains: + const: nvidia,tegra186-pmc +then: + properties: + reg: + maxItems: 4 + + reg-names: + maxItems: 4 +else: + properties: + reg: + minItems: 5 + + reg-names: + minItems: 5 + +patternProperties: + "^[a-z0-9]+-[a-z0-9]+$": + if: + type: object + then: + description: | + These are pad configuration nodes. On Tegra SoCs a pad is a set of + pins which are configured as a group. The pin grouping is a fixed + attribute of the hardware. The PMC can be used to set pad power + state and signaling voltage. A pad can be either in active or + power down mode. The support for power state and signaling voltage + configuration varies depending on the pad in question. 3.3 V and + 1.8 V signaling voltages are supported on pins where software + controllable signaling voltage switching is available. + + Pad configurations are described with pin configuration nodes + which are placed under the pmc node and they are referred to by + the pinctrl client properties. For more information see + + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + + The following pads are present on Tegra186: + + csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, + pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg, + hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib, + dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp, + sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv + + The following pads are present on Tegra194: + + csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, + pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart, + pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12, + soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2, + hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst, + pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif, + spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn, + audio-hv, ao-hv + + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string + description: Must contain the name of the pad(s) to be + configured. + + low-power-enable: + description: Configure the pad into power down mode. + $ref: /schemas/types.yaml#/definitions/flag + + low-power-disable: + description: Configure the pad into active mode. + $ref: /schemas/types.yaml#/definitions/flag + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling + voltages. + + The values are defined in + + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h + + The power state can be configured on all of the above pads + except for ao-hv. Following pads have software configurable + signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, + audio-hv, ao-hv. + + phandle: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +dependencies: + interrupt-controller: ['#interrupt-cells'] + "#interrupt-cells": + required: + - interrupt-controller + +examples: + - | + #include <dt-bindings/clock/tegra186-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> + #include <dt-bindings/memory/tegra186-mc.h> + #include <dt-bindings/reset/tegra186-reset.h> + + pmc@c3600000 { + compatible = "nvidia,tegra186-pmc"; + reg = <0x0c360000 0x10000>, + <0x0c370000 0x10000>, + <0x0c380000 0x10000>, + <0x0c390000 0x10000>; + reg-names = "pmc", "wake", "aotag", "scratch"; + nvidia,invert-interrupt; + + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; + }; + }; + + sdmmc1: mmc@3400000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x03400000 0x10000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA186_CLK_SDMMC1>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; + resets = <&bpmp TEGRA186_RESET_SDMMC1>; + reset-names = "sdhci"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_SDMMC1>; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; + }; diff --git a/dts/Bindings/arm/ti/k3.yaml b/dts/Bindings/arm/ti/k3.yaml index cf327230fc..b03c10fa2e 100644 --- a/dts/Bindings/arm/ti/k3.yaml +++ b/dts/Bindings/arm/ti/k3.yaml @@ -53,6 +53,12 @@ properties: - ti,am642-sk - const: ti,am642 + - description: K3 J721s2 SoC + items: + - enum: + - ti,j721s2-evm + - const: ti,j721s2 + additionalProperties: true ... diff --git a/dts/Bindings/arm/ux500.yaml b/dts/Bindings/arm/ux500.yaml index 5db7cfba81..a46193ad94 100644 --- a/dts/Bindings/arm/ux500.yaml +++ b/dts/Bindings/arm/ux500.yaml @@ -20,6 +20,11 @@ properties: - const: st-ericsson,mop500 - const: st-ericsson,u8500 + - description: ST-Ericsson HREF520 + items: + - const: st-ericsson,href520 + - const: st-ericsson,u8500 + - description: ST-Ericsson HREF (v60+) items: - const: st-ericsson,hrefv60+ @@ -30,9 +35,34 @@ properties: - const: calaosystems,snowball-a9500 - const: st-ericsson,u9500 + - description: Samsung Galaxy Ace 2 (GT-I8160) + items: + - const: samsung,codina + - const: st-ericsson,u8500 + + - description: Samsung Galaxy Beam (GT-I8530) + items: + - const: samsung,gavini + - const: st-ericsson,u8500 + - description: Samsung Galaxy S III mini (GT-I8190) items: - const: samsung,golden - const: st-ericsson,u8500 + - description: Samsung Galaxy S Advance (GT-I9070) + items: + - const: samsung,janice + - const: st-ericsson,u8500 + + - description: Samsung Galaxy Amp (SGH-I407) + items: + - const: samsung,kyle + - const: st-ericsson,u8500 + + - description: Samsung Galaxy XCover 2 (GT-S7710) + items: + - const: samsung,skomer + - const: st-ericsson,u8500 + additionalProperties: true diff --git a/dts/Bindings/arm/xen.txt b/dts/Bindings/arm/xen.txt index db5c56db30..61d77acbeb 100644 --- a/dts/Bindings/arm/xen.txt +++ b/dts/Bindings/arm/xen.txt @@ -7,15 +7,17 @@ the following properties: compatible = "xen,xen-<version>", "xen,xen"; where <version> is the version of the Xen ABI of the platform. -- reg: specifies the base physical address and size of a region in - memory where the grant table should be mapped to, using an - HYPERVISOR_memory_op hypercall. The memory region is large enough to map - the whole grant table (it is larger or equal to gnttab_max_grant_frames()). - This property is unnecessary when booting Dom0 using ACPI. +- reg: specifies the base physical address and size of the regions in memory + where the special resources should be mapped to, using an HYPERVISOR_memory_op + hypercall. + Region 0 is reserved for mapping grant table, it must be always present. + The memory region is large enough to map the whole grant table (it is larger + or equal to gnttab_max_grant_frames()). + Regions 1...N are extended regions (unused address space) for mapping foreign + GFNs and grants, they might be absent if there is nothing to expose. - interrupts: the interrupt used by Xen to inject event notifications. A GIC node is also required. - This property is unnecessary when booting Dom0 using ACPI. To support UEFI on Xen ARM virtual platforms, Xen populates the FDT "uefi" node under /hypervisor with following parameters: diff --git a/dts/Bindings/ata/brcm,sata-brcm.txt b/dts/Bindings/ata/brcm,sata-brcm.txt deleted file mode 100644 index b9ae4ce4a0..0000000000 --- a/dts/Bindings/ata/brcm,sata-brcm.txt +++ /dev/null @@ -1,45 +0,0 @@ -* Broadcom SATA3 AHCI Controller - -SATA nodes are defined to describe on-chip Serial ATA controllers. -Each SATA controller should have its own node. - -Required properties: -- compatible : should be one or more of - "brcm,bcm7216-ahci" - "brcm,bcm7425-ahci" - "brcm,bcm7445-ahci" - "brcm,bcm-nsp-ahci" - "brcm,sata3-ahci" - "brcm,bcm63138-ahci" -- reg : register mappings for AHCI and SATA_TOP_CTRL -- reg-names : "ahci" and "top-ctrl" -- interrupts : interrupt mapping for SATA IRQ - -Optional properties: - -- reset: for "brcm,bcm7216-ahci" must be a valid reset phandle - pointing to the RESCAL reset controller provider node. -- reset-names: for "brcm,bcm7216-ahci", must be "rescal". - -Also see ahci-platform.txt. - -Example: - - sata@f045a000 { - compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; - reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>; - reg-names = "ahci", "top-ctrl"; - interrupts = <0 30 0>; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy 0>; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy 1>; - }; - }; diff --git a/dts/Bindings/ata/brcm,sata-brcm.yaml b/dts/Bindings/ata/brcm,sata-brcm.yaml new file mode 100644 index 0000000000..235a93ac86 --- /dev/null +++ b/dts/Bindings/ata/brcm,sata-brcm.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom SATA3 AHCI Controller + +description: + SATA nodes are defined to describe on-chip Serial ATA controllers. + Each SATA controller should have its own node. + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +allOf: + - $ref: sata-common.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - brcm,bcm7216-ahci + - brcm,bcm7445-ahci + - brcm,bcm7425-ahci + - brcm,bcm63138-ahci + - const: brcm,sata3-ahci + - items: + - const: brcm,bcm-nsp-ahci + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: ahci + - const: top-ctrl + + interrupts: + maxItems: 1 + + dma-coherent: true + +if: + properties: + compatible: + contains: + enum: + - brcm,bcm7216-ahci + - brcm,bcm63138-ahci +then: + properties: + resets: + maxItems: 1 + reset-names: + enum: + - rescal + - ahci + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#size-cells" + +unevaluatedProperties: false + +examples: + - | + sata@f045a000 { + compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; + reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>; + reg-names = "ahci", "top-ctrl"; + interrupts = <0 30 0>; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy 0>; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy 1>; + }; + }; diff --git a/dts/Bindings/bus/brcm,gisb-arb.txt b/dts/Bindings/bus/brcm,gisb-arb.txt deleted file mode 100644 index 10f6d0a815..0000000000 --- a/dts/Bindings/bus/brcm,gisb-arb.txt +++ /dev/null @@ -1,34 +0,0 @@ -Broadcom GISB bus Arbiter controller - -Required properties: - -- compatible: - "brcm,bcm7278-gisb-arb" for V7 28nm chips - "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips - "brcm,bcm7435-gisb-arb" for newer 40nm chips - "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips - "brcm,bcm7038-gisb-arb" for 130nm chips -- reg: specifies the base physical address and size of the registers -- interrupts: specifies the two interrupts (timeout and TEA) to be used from - the parent interrupt controller. A third optional interrupt may be specified - for breakpoints. - -Optional properties: - -- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB - masters are valid at the system level -- brcm,gisb-arb-master-names: string list of the litteral name of the GISB - masters. Should match the number of bits set in brcm,gisb-master-mask and - the order in which they appear - -Example: - -gisb-arb@f0400000 { - compatible = "brcm,gisb-arb"; - reg = <0xf0400000 0x800>; - interrupts = <0>, <2>; - interrupt-parent = <&sun_l2_intc>; - - brcm,gisb-arb-master-mask = <0x7>; - brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; -}; diff --git a/dts/Bindings/bus/brcm,gisb-arb.yaml b/dts/Bindings/bus/brcm,gisb-arb.yaml new file mode 100644 index 0000000000..b23c300199 --- /dev/null +++ b/dts/Bindings/bus/brcm,gisb-arb.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom GISB bus Arbiter controller + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - brcm,bcm7445-gisb-arb # for other 28nm chips + - const: brcm,gisb-arb + - items: + - enum: + - brcm,bcm7278-gisb-arb # for V7 28nm chips + - brcm,bcm7435-gisb-arb # for newer 40nm chips + - brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips + - brcm,bcm7038-gisb-arb # for 130nm chips + - brcm,gisb-arb # fallback compatible + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + items: + - description: timeout interrupt line + - description: target abort interrupt line + - description: breakpoint interrupt line + + brcm,gisb-arb-master-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + 32-bits wide bitmask used to specify which GISB masters are valid at the + system level + + brcm,gisb-arb-master-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: > + String list of the litteral name of the GISB masters. Should match the + number of bits set in brcm,gisb-master-mask and the order in which they + appear from MSB to LSB. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + gisb-arb@f0400000 { + compatible = "brcm,gisb-arb"; + reg = <0xf0400000 0x800>; + interrupts = <0>, <2>; + interrupt-parent = <&sun_l2_intc>; + brcm,gisb-arb-master-mask = <0x7>; + brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; + }; diff --git a/dts/Bindings/bus/fsl,spba-bus.yaml b/dts/Bindings/bus/fsl,spba-bus.yaml new file mode 100644 index 0000000000..d42dbb0bbc --- /dev/null +++ b/dts/Bindings/bus/fsl,spba-bus.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,spba-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Shared Peripherals Bus Interface + +maintainers: + - Shawn Guo <shawnguo@kernel.org> + +description: | + A simple bus enabling access to shared peripherals. + + The "spba-bus" follows the "simple-bus" set of properties, as + specified in the Devicetree Specification. It is an extension of + "simple-bus" because the SDMA controller uses this compatible flag to + determine which peripherals are available to it and the range over which + the SDMA can access. There are no special clocks for the bus, because + the SDMA controller itself has its interrupt and clock assignments. + +select: + properties: + compatible: + contains: + const: fsl,spba-bus + required: + - compatible + +properties: + $nodename: + pattern: "^spba-bus(@[0-9a-f]+)?$" + + compatible: + items: + - const: fsl,spba-bus + - const: simple-bus + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + reg: + maxItems: 1 + + ranges: true + +required: + - compatible + - '#address-cells' + - '#size-cells' + - reg + - ranges + +additionalProperties: + type: object + +examples: + - | + spba-bus@30000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x100000>; + ranges; + }; diff --git a/dts/Bindings/bus/imx-weim.txt b/dts/Bindings/bus/imx-weim.txt index 1b1d1c5c21..e7f502070d 100644 --- a/dts/Bindings/bus/imx-weim.txt +++ b/dts/Bindings/bus/imx-weim.txt @@ -48,6 +48,11 @@ Optional properties: devices, the presence of this property indicates that the weim bus should operate in Burst Clock Mode. + - fsl,continuous-burst-clk Make Burst Clock to output continuous clock. + Without this option Burst Clock will output clock + only when necessary. This takes effect only if + "fsl,burst-clk-enable" is set. + Timing property for child nodes. It is mandatory, not optional. - fsl,weim-cs-timing: The timing array, contains timing values for the diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml index c4b7243ddc..15ed64d352 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml @@ -34,6 +34,8 @@ properties: - allwinner,sun8i-v3-ccu - allwinner,sun8i-v3s-ccu - allwinner,sun9i-a80-ccu + - allwinner,sun20i-d1-ccu + - allwinner,sun20i-d1-r-ccu - allwinner,sun50i-a64-ccu - allwinner,sun50i-a64-r-ccu - allwinner,sun50i-a100-ccu @@ -79,6 +81,7 @@ if: enum: - allwinner,sun8i-a83t-r-ccu - allwinner,sun8i-h3-r-ccu + - allwinner,sun20i-d1-r-ccu - allwinner,sun50i-a64-r-ccu - allwinner,sun50i-a100-r-ccu - allwinner,sun50i-h6-r-ccu @@ -99,6 +102,7 @@ else: properties: compatible: enum: + - allwinner,sun20i-d1-ccu - allwinner,sun50i-a100-ccu - allwinner,sun50i-h6-ccu - allwinner,sun50i-h616-ccu diff --git a/dts/Bindings/clock/exynos5260-clock.txt b/dts/Bindings/clock/exynos5260-clock.txt deleted file mode 100644 index c79d31f7f6..0000000000 --- a/dts/Bindings/clock/exynos5260-clock.txt +++ /dev/null @@ -1,190 +0,0 @@ -* Samsung Exynos5260 Clock Controller - -Exynos5260 has 13 clock controllers which are instantiated -independently from the device-tree. These clock controllers -generate and supply clocks to various hardware blocks within -the SoC. - -Each clock is assigned an identifier and client nodes can use -this identifier to specify the clock which they consume. All -available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos5260-clk.h header and can be used in -device tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It -is expected that they are defined using standard clock bindings -with following clock-output-names: - - - "fin_pll" - PLL input clock from XXTI - - "xrtcxti" - input clock from XRTCXTI - - "ioclk_pcm_extclk" - pcm external operation clock - - "ioclk_spdif_extclk" - spdif external operation clock - - "ioclk_i2s_cdclk" - i2s0 codec clock - -Phy clocks: - -There are several clocks which are generated by specific PHYs. -These clocks are fed into the clock controller and then routed to -the hardware blocks. These clocks are defined as fixed clocks in the -driver with following names: - - - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3 - - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2 - - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1 - - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0 - - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock - - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock - - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link - - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock - - "phyclk_dptx_phy_clk_div2" - - "phyclk_mipi_dphy_4l_m_rxclkesc0" - - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock - - "phyclk_usbhost20_phy_freeclk" - - "phyclk_usbhost20_phy_clk48mohci" - - "phyclk_usbdrd30_udrd30_pipe_pclk" - - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock - -Required Properties for Clock Controller: - - - compatible: should be one of the following. - 1) "samsung,exynos5260-clock-top" - 2) "samsung,exynos5260-clock-peri" - 3) "samsung,exynos5260-clock-egl" - 4) "samsung,exynos5260-clock-kfc" - 5) "samsung,exynos5260-clock-g2d" - 6) "samsung,exynos5260-clock-mif" - 7) "samsung,exynos5260-clock-mfc" - 8) "samsung,exynos5260-clock-g3d" - 9) "samsung,exynos5260-clock-fsys" - 10) "samsung,exynos5260-clock-aud" - 11) "samsung,exynos5260-clock-isp" - 12) "samsung,exynos5260-clock-gscl" - 13) "samsung,exynos5260-clock-disp" - - - reg: physical base address of the controller and the length of - memory mapped region. - - - #clock-cells: should be 1. - - - clocks: list of clock identifiers which are fed as the input to - the given clock controller. Please refer the next section to find - the input clocks for a given controller. - - - clock-names: list of names of clocks which are fed as the input - to the given clock controller. - -Input clocks for top clock controller: - - fin_pll - - dout_mem_pll - - dout_bus_pll - - dout_media_pll - -Input clocks for peri clock controller: - - fin_pll - - ioclk_pcm_extclk - - ioclk_i2s_cdclk - - ioclk_spdif_extclk - - phyclk_hdmi_phy_ref_cko - - dout_aclk_peri_66 - - dout_sclk_peri_uart0 - - dout_sclk_peri_uart1 - - dout_sclk_peri_uart2 - - dout_sclk_peri_spi0_b - - dout_sclk_peri_spi1_b - - dout_sclk_peri_spi2_b - - dout_aclk_peri_aud - - dout_sclk_peri_spi0_b - -Input clocks for egl clock controller: - - fin_pll - - dout_bus_pll - -Input clocks for kfc clock controller: - - fin_pll - - dout_media_pll - -Input clocks for g2d clock controller: - - fin_pll - - dout_aclk_g2d_333 - -Input clocks for mif clock controller: - - fin_pll - -Input clocks for mfc clock controller: - - fin_pll - - dout_aclk_mfc_333 - -Input clocks for g3d clock controller: - - fin_pll - -Input clocks for fsys clock controller: - - fin_pll - - phyclk_usbhost20_phy_phyclock - - phyclk_usbhost20_phy_freeclk - - phyclk_usbhost20_phy_clk48mohci - - phyclk_usbdrd30_udrd30_pipe_pclk - - phyclk_usbdrd30_udrd30_phyclock - - dout_aclk_fsys_200 - -Input clocks for aud clock controller: - - fin_pll - - fout_aud_pll - - ioclk_i2s_cdclk - - ioclk_pcm_extclk - -Input clocks for isp clock controller: - - fin_pll - - dout_aclk_isp1_266 - - dout_aclk_isp1_400 - - mout_aclk_isp1_266 - -Input clocks for gscl clock controller: - - fin_pll - - dout_aclk_gscl_400 - - dout_aclk_gscl_333 - -Input clocks for disp clock controller: - - fin_pll - - phyclk_dptx_phy_ch3_txd_clk - - phyclk_dptx_phy_ch2_txd_clk - - phyclk_dptx_phy_ch1_txd_clk - - phyclk_dptx_phy_ch0_txd_clk - - phyclk_hdmi_phy_tmds_clko - - phyclk_hdmi_phy_ref_clko - - phyclk_hdmi_phy_pixel_clko - - phyclk_hdmi_link_o_tmds_clkhi - - phyclk_mipi_dphy_4l_m_txbyte_clkhs - - phyclk_dptx_phy_o_ref_clk_24m - - phyclk_dptx_phy_clk_div2 - - phyclk_mipi_dphy_4l_m_rxclkesc0 - - phyclk_hdmi_phy_ref_cko - - ioclk_spdif_extclk - - dout_aclk_peri_aud - - dout_aclk_disp_222 - - dout_sclk_disp_pixel - - dout_aclk_disp_333 - -Example 1: An example of a clock controller node is listed below. - - clock_mfc: clock-controller@11090000 { - compatible = "samsung,exynos5260-clock-mfc"; - clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>; - clock-names = "fin_pll", "dout_aclk_mfc_333"; - reg = <0x11090000 0x10000>; - #clock-cells = <1>; - }; - -Example 2: UART controller node that consumes the clock generated by the - peri clock controller. Refer to the standard clock bindings for - information about 'clocks' and 'clock-names' property. - - serial@12c00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 146 0>; - clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - }; - diff --git a/dts/Bindings/clock/exynos5410-clock.txt b/dts/Bindings/clock/exynos5410-clock.txt deleted file mode 100644 index 217beb27c3..0000000000 --- a/dts/Bindings/clock/exynos5410-clock.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Samsung Exynos5410 Clock Controller - -The Exynos5410 clock controller generates and supplies clock to various -controllers within the Exynos5410 SoC. - -Required Properties: - -- compatible: should be "samsung,exynos5410-clock" - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -- clocks: should contain an entry specifying the root clock from external - oscillator supplied through XXTI or XusbXTI pin. This clock should be - defined using standard clock bindings with "fin_pll" clock-output-name. - That clock is being passed internally to the 9 PLLs. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos5410.h header and can be used in device -tree sources. - -Example 1: An example of a clock controller node is listed below. - - fin_pll: xxti { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5410-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - clocks = <&fin_pll>; - }; - -Example 2: UART controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - serial@12c20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 51 0>; - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - }; diff --git a/dts/Bindings/clock/exynos5433-clock.txt b/dts/Bindings/clock/exynos5433-clock.txt deleted file mode 100644 index 183c327a7d..0000000000 --- a/dts/Bindings/clock/exynos5433-clock.txt +++ /dev/null @@ -1,507 +0,0 @@ -* Samsung Exynos5433 CMU (Clock Management Units) - -The Exynos5433 clock controller generates and supplies clock to various -controllers within the Exynos5433 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP - which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - domains and bus clocks. - - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF - which generates clocks for LLI (Low Latency Interface) IP. - - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF - which generates clocks for DRAM Memory Controller domain. - - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC - which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. - - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS - which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. - - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS - which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. - - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D - which generates clocks for G2D/MDMA IPs. - - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP - which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. - - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD - which generates clocks for Cortex-A5/BUS/AUDIO clocks. - - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" - and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS - which generates global data buses clock and global peripheral buses clock. - - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D - which generates clocks for 3D Graphics Engine IP. - - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL - which generates clocks for GSCALER IPs. - - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO - which generates clocks for Cortex-A53 Quad-core processor. - - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS - which generates clocks for Cortex-A57 Quad-core processor, CoreSight and - L2 cache controller. - - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL - which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs. - - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC - which generates clocks for MFC(Multi-Format Codec) IP. - - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC - which generates clocks for HEVC(High Efficiency Video Codec) decoder IP. - - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP - which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0 - which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} - IPs. - - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1 - which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs. - - "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM - which generates clocks for SSS (Security SubSystem) and SlimSSS IPs. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -- clocks: list of the clock controller input clock identifiers, - from common clock bindings. Please refer the next section - to find the input clocks for a given controller. - -- clock-names: list of the clock controller input clock names, - as described in clock-bindings.txt. - - Input clocks for top clock controller: - - oscclk - - sclk_mphy_pll - - sclk_mfc_pll - - sclk_bus_pll - - Input clocks for cpif clock controller: - - oscclk - - Input clocks for mif clock controller: - - oscclk - - sclk_mphy_pll - - Input clocks for fsys clock controller: - - oscclk - - sclk_ufs_mphy - - aclk_fsys_200 - - sclk_pcie_100_fsys - - sclk_ufsunipro_fsys - - sclk_mmc2_fsys - - sclk_mmc1_fsys - - sclk_mmc0_fsys - - sclk_usbhost30_fsys - - sclk_usbdrd30_fsys - - Input clocks for g2d clock controller: - - oscclk - - aclk_g2d_266 - - aclk_g2d_400 - - Input clocks for disp clock controller: - - oscclk - - sclk_dsim1_disp - - sclk_dsim0_disp - - sclk_dsd_disp - - sclk_decon_tv_eclk_disp - - sclk_decon_vclk_disp - - sclk_decon_eclk_disp - - sclk_decon_tv_vclk_disp - - aclk_disp_333 - - Input clocks for audio clock controller: - - oscclk - - fout_aud_pll - - Input clocks for bus0 clock controller: - - aclk_bus0_400 - - Input clocks for bus1 clock controller: - - aclk_bus1_400 - - Input clocks for bus2 clock controller: - - oscclk - - aclk_bus2_400 - - Input clocks for g3d clock controller: - - oscclk - - aclk_g3d_400 - - Input clocks for gscl clock controller: - - oscclk - - aclk_gscl_111 - - aclk_gscl_333 - - Input clocks for apollo clock controller: - - oscclk - - sclk_bus_pll_apollo - - Input clocks for atlas clock controller: - - oscclk - - sclk_bus_pll_atlas - - Input clocks for mscl clock controller: - - oscclk - - sclk_jpeg_mscl - - aclk_mscl_400 - - Input clocks for mfc clock controller: - - oscclk - - aclk_mfc_400 - - Input clocks for hevc clock controller: - - oscclk - - aclk_hevc_400 - - Input clocks for isp clock controller: - - oscclk - - aclk_isp_dis_400 - - aclk_isp_400 - - Input clocks for cam0 clock controller: - - oscclk - - aclk_cam0_333 - - aclk_cam0_400 - - aclk_cam0_552 - - Input clocks for cam1 clock controller: - - oscclk - - sclk_isp_uart_cam1 - - sclk_isp_spi1_cam1 - - sclk_isp_spi0_cam1 - - aclk_cam1_333 - - aclk_cam1_400 - - aclk_cam1_552 - - Input clocks for imem clock controller: - - oscclk - - aclk_imem_sssx_266 - - aclk_imem_266 - - aclk_imem_200 - -Optional properties: - - power-domains: a phandle to respective power domain node as described by - generic PM domain bindings (see power/power_domain.txt for more - information). - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos5433.h header and can be used in device -tree sources. - -Example 1: Examples of 'oscclk' source clock node are listed below. - - xxti: xxti { - compatible = "fixed-clock"; - clock-output-names = "oscclk"; - #clock-cells = <0>; - }; - -Example 2: Examples of clock controller nodes are listed below. - - cmu_top: clock-controller@10030000 { - compatible = "samsung,exynos5433-cmu-top"; - reg = <0x10030000 0x0c04>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_mphy_pll", - "sclk_mfc_pll", - "sclk_bus_pll"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_MPHY_PLL>, - <&cmu_mif CLK_SCLK_MFC_PLL>, - <&cmu_mif CLK_SCLK_BUS_PLL>; - }; - - cmu_cpif: clock-controller@10fc0000 { - compatible = "samsung,exynos5433-cmu-cpif"; - reg = <0x10fc0000 0x0c04>; - #clock-cells = <1>; - - clock-names = "oscclk"; - clocks = <&xxti>; - }; - - cmu_mif: clock-controller@105b0000 { - compatible = "samsung,exynos5433-cmu-mif"; - reg = <0x105b0000 0x100c>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_mphy_pll"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_MPHY_PLL>; - }; - - cmu_peric: clock-controller@14c80000 { - compatible = "samsung,exynos5433-cmu-peric"; - reg = <0x14c80000 0x0b08>; - #clock-cells = <1>; - }; - - cmu_peris: clock-controller@10040000 { - compatible = "samsung,exynos5433-cmu-peris"; - reg = <0x10040000 0x0b20>; - #clock-cells = <1>; - }; - - cmu_fsys: clock-controller@156e0000 { - compatible = "samsung,exynos5433-cmu-fsys"; - reg = <0x156e0000 0x0b04>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_ufs_mphy", - "aclk_fsys_200", - "sclk_pcie_100_fsys", - "sclk_ufsunipro_fsys", - "sclk_mmc2_fsys", - "sclk_mmc1_fsys", - "sclk_mmc0_fsys", - "sclk_usbhost30_fsys", - "sclk_usbdrd30_fsys"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_UFS_MPHY>, - <&cmu_top CLK_ACLK_FSYS_200>, - <&cmu_top CLK_SCLK_PCIE_100_FSYS>, - <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, - <&cmu_top CLK_SCLK_MMC2_FSYS>, - <&cmu_top CLK_SCLK_MMC1_FSYS>, - <&cmu_top CLK_SCLK_MMC0_FSYS>, - <&cmu_top CLK_SCLK_USBHOST30_FSYS>, - <&cmu_top CLK_SCLK_USBDRD30_FSYS>; - }; - - cmu_g2d: clock-controller@12460000 { - compatible = "samsung,exynos5433-cmu-g2d"; - reg = <0x12460000 0x0b08>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_g2d_266", - "aclk_g2d_400"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_G2D_266>, - <&cmu_top CLK_ACLK_G2D_400>; - power-domains = <&pd_g2d>; - }; - - cmu_disp: clock-controller@13b90000 { - compatible = "samsung,exynos5433-cmu-disp"; - reg = <0x13b90000 0x0c04>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_dsim1_disp", - "sclk_dsim0_disp", - "sclk_dsd_disp", - "sclk_decon_tv_eclk_disp", - "sclk_decon_vclk_disp", - "sclk_decon_eclk_disp", - "sclk_decon_tv_vclk_disp", - "aclk_disp_333"; - clocks = <&xxti>, - <&cmu_mif CLK_SCLK_DSIM1_DISP>, - <&cmu_mif CLK_SCLK_DSIM0_DISP>, - <&cmu_mif CLK_SCLK_DSD_DISP>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, - <&cmu_mif CLK_ACLK_DISP_333>; - power-domains = <&pd_disp>; - }; - - cmu_aud: clock-controller@114c0000 { - compatible = "samsung,exynos5433-cmu-aud"; - reg = <0x114c0000 0x0b04>; - #clock-cells = <1>; - - clock-names = "oscclk", "fout_aud_pll"; - clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; - power-domains = <&pd_aud>; - }; - - cmu_bus0: clock-controller@13600000 { - compatible = "samsung,exynos5433-cmu-bus0"; - reg = <0x13600000 0x0b04>; - #clock-cells = <1>; - - clock-names = "aclk_bus0_400"; - clocks = <&cmu_top CLK_ACLK_BUS0_400>; - }; - - cmu_bus1: clock-controller@14800000 { - compatible = "samsung,exynos5433-cmu-bus1"; - reg = <0x14800000 0x0b04>; - #clock-cells = <1>; - - clock-names = "aclk_bus1_400"; - clocks = <&cmu_top CLK_ACLK_BUS1_400>; - }; - - cmu_bus2: clock-controller@13400000 { - compatible = "samsung,exynos5433-cmu-bus2"; - reg = <0x13400000 0x0b04>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_bus2_400"; - clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; - }; - - cmu_g3d: clock-controller@14aa0000 { - compatible = "samsung,exynos5433-cmu-g3d"; - reg = <0x14aa0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_g3d_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; - power-domains = <&pd_g3d>; - }; - - cmu_gscl: clock-controller@13cf0000 { - compatible = "samsung,exynos5433-cmu-gscl"; - reg = <0x13cf0000 0x0b10>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_gscl_111", - "aclk_gscl_333"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_GSCL_111>, - <&cmu_top CLK_ACLK_GSCL_333>; - power-domains = <&pd_gscl>; - }; - - cmu_apollo: clock-controller@11900000 { - compatible = "samsung,exynos5433-cmu-apollo"; - reg = <0x11900000 0x1088>; - #clock-cells = <1>; - - clock-names = "oscclk", "sclk_bus_pll_apollo"; - clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; - }; - - cmu_atlas: clock-controller@11800000 { - compatible = "samsung,exynos5433-cmu-atlas"; - reg = <0x11800000 0x1088>; - #clock-cells = <1>; - - clock-names = "oscclk", "sclk_bus_pll_atlas"; - clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; - }; - - cmu_mscl: clock-controller@105d0000 { - compatible = "samsung,exynos5433-cmu-mscl"; - reg = <0x105d0000 0x0b10>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_jpeg_mscl", - "aclk_mscl_400"; - clocks = <&xxti>, - <&cmu_top CLK_SCLK_JPEG_MSCL>, - <&cmu_top CLK_ACLK_MSCL_400>; - power-domains = <&pd_mscl>; - }; - - cmu_mfc: clock-controller@15280000 { - compatible = "samsung,exynos5433-cmu-mfc"; - reg = <0x15280000 0x0b08>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_mfc_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; - power-domains = <&pd_mfc>; - }; - - cmu_hevc: clock-controller@14f80000 { - compatible = "samsung,exynos5433-cmu-hevc"; - reg = <0x14f80000 0x0b08>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_hevc_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; - power-domains = <&pd_hevc>; - }; - - cmu_isp: clock-controller@146d0000 { - compatible = "samsung,exynos5433-cmu-isp"; - reg = <0x146d0000 0x0b0c>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_isp_dis_400", - "aclk_isp_400"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_ISP_DIS_400>, - <&cmu_top CLK_ACLK_ISP_400>; - power-domains = <&pd_isp>; - }; - - cmu_cam0: clock-controller@120d0000 { - compatible = "samsung,exynos5433-cmu-cam0"; - reg = <0x120d0000 0x0b0c>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_cam0_333", - "aclk_cam0_400", - "aclk_cam0_552"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_CAM0_333>, - <&cmu_top CLK_ACLK_CAM0_400>, - <&cmu_top CLK_ACLK_CAM0_552>; - power-domains = <&pd_cam0>; - }; - - cmu_cam1: clock-controller@145d0000 { - compatible = "samsung,exynos5433-cmu-cam1"; - reg = <0x145d0000 0x0b08>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_isp_uart_cam1", - "sclk_isp_spi1_cam1", - "sclk_isp_spi0_cam1", - "aclk_cam1_333", - "aclk_cam1_400", - "aclk_cam1_552"; - clocks = <&xxti>, - <&cmu_top CLK_SCLK_ISP_UART_CAM1>, - <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, - <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, - <&cmu_top CLK_ACLK_CAM1_333>, - <&cmu_top CLK_ACLK_CAM1_400>, - <&cmu_top CLK_ACLK_CAM1_552>; - power-domains = <&pd_cam1>; - }; - - cmu_imem: clock-controller@11060000 { - compatible = "samsung,exynos5433-cmu-imem"; - reg = <0x11060000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_imem_sssx_266", - "aclk_imem_266", - "aclk_imem_200"; - clocks = <&xxti>, - <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>, - <&cmu_top CLK_DIV_ACLK_IMEM_266>, - <&cmu_top CLK_DIV_ACLK_IMEM_200>; - }; - -Example 3: UART controller node that consumes the clock generated by the clock - controller. - - serial_0: serial@14c10000 { - compatible = "samsung,exynos5433-uart"; - reg = <0x14C10000 0x100>; - interrupts = <0 421 0>; - clocks = <&cmu_peric CLK_PCLK_UART0>, - <&cmu_peric CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_bus>; - }; diff --git a/dts/Bindings/clock/exynos7-clock.txt b/dts/Bindings/clock/exynos7-clock.txt deleted file mode 100644 index 6bf1e7493f..0000000000 --- a/dts/Bindings/clock/exynos7-clock.txt +++ /dev/null @@ -1,108 +0,0 @@ -* Samsung Exynos7 Clock Controller - -Exynos7 clock controller has various blocks which are instantiated -independently from the device-tree. These clock controllers -generate and supply clocks to various hardware blocks within -the SoC. - -Each clock is assigned an identifier and client nodes can use -this identifier to specify the clock which they consume. All -available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos7-clk.h header and can be used in -device tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It -is expected that they are defined using standard clock bindings -with following clock-output-names: - - - "fin_pll" - PLL input clock from XXTI - -Required Properties for Clock Controller: - - - compatible: clock controllers will use one of the following - compatible strings to indicate the clock controller - functionality. - - - "samsung,exynos7-clock-topc" - - "samsung,exynos7-clock-top0" - - "samsung,exynos7-clock-top1" - - "samsung,exynos7-clock-ccore" - - "samsung,exynos7-clock-peric0" - - "samsung,exynos7-clock-peric1" - - "samsung,exynos7-clock-peris" - - "samsung,exynos7-clock-fsys0" - - "samsung,exynos7-clock-fsys1" - - "samsung,exynos7-clock-mscl" - - "samsung,exynos7-clock-aud" - - - reg: physical base address of the controller and the length of - memory mapped region. - - - #clock-cells: should be 1. - - - clocks: list of clock identifiers which are fed as the input to - the given clock controller. Please refer the next section to - find the input clocks for a given controller. - -- clock-names: list of names of clocks which are fed as the input - to the given clock controller. - -Input clocks for top0 clock controller: - - fin_pll - - dout_sclk_bus0_pll - - dout_sclk_bus1_pll - - dout_sclk_cc_pll - - dout_sclk_mfc_pll - - dout_sclk_aud_pll - -Input clocks for top1 clock controller: - - fin_pll - - dout_sclk_bus0_pll - - dout_sclk_bus1_pll - - dout_sclk_cc_pll - - dout_sclk_mfc_pll - -Input clocks for ccore clock controller: - - fin_pll - - dout_aclk_ccore_133 - -Input clocks for peric0 clock controller: - - fin_pll - - dout_aclk_peric0_66 - - sclk_uart0 - -Input clocks for peric1 clock controller: - - fin_pll - - dout_aclk_peric1_66 - - sclk_uart1 - - sclk_uart2 - - sclk_uart3 - - sclk_spi0 - - sclk_spi1 - - sclk_spi2 - - sclk_spi3 - - sclk_spi4 - - sclk_i2s1 - - sclk_pcm1 - - sclk_spdif - -Input clocks for peris clock controller: - - fin_pll - - dout_aclk_peris_66 - -Input clocks for fsys0 clock controller: - - fin_pll - - dout_aclk_fsys0_200 - - dout_sclk_mmc2 - -Input clocks for fsys1 clock controller: - - fin_pll - - dout_aclk_fsys1_200 - - dout_sclk_mmc0 - - dout_sclk_mmc1 - -Input clocks for aud clock controller: - - fin_pll - - fout_aud_pll diff --git a/dts/Bindings/clock/imx5-clock.yaml b/dts/Bindings/clock/imx5-clock.yaml index b1740d7abe..c0e19ff92c 100644 --- a/dts/Bindings/clock/imx5-clock.yaml +++ b/dts/Bindings/clock/imx5-clock.yaml @@ -55,11 +55,4 @@ examples: <0 72 IRQ_TYPE_LEVEL_HIGH>; #clock-cells = <1>; }; - - can@53fc8000 { - compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; - reg = <0x53fc8000 0x4000>; - interrupts = <82>; - clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>; - clock-names = "ipg", "per"; - }; +... diff --git a/dts/Bindings/clock/microchip,lan966x-gck.yaml b/dts/Bindings/clock/microchip,lan966x-gck.yaml new file mode 100644 index 0000000000..df2bec1887 --- /dev/null +++ b/dts/Bindings/clock/microchip,lan966x-gck.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip LAN966X Generic Clock Controller + +maintainers: + - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> + +description: | + The LAN966X Generic clock controller contains 3 PLLs - cpu_clk, + ddr_clk and sys_clk. This clock controller generates and supplies + clock to various peripherals within the SoC. + +properties: + compatible: + const: microchip,lan966x-gck + + reg: + minItems: 1 + items: + - description: Generic clock registers + - description: Optional gate clock registers + + clocks: + items: + - description: CPU clock source + - description: DDR clock source + - description: System clock source + + clock-names: + items: + - const: cpu + - const: ddr + - const: sys + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clks: clock-controller@e00c00a8 { + compatible = "microchip,lan966x-gck"; + #clock-cells = <1>; + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; + clock-names = "cpu", "ddr", "sys"; + reg = <0xe00c00a8 0x38>; + }; +... diff --git a/dts/Bindings/clock/nvidia,tegra20-car.yaml b/dts/Bindings/clock/nvidia,tegra20-car.yaml index 459d2a5253..f832abb7f1 100644 --- a/dts/Bindings/clock/nvidia,tegra20-car.yaml +++ b/dts/Bindings/clock/nvidia,tegra20-car.yaml @@ -42,6 +42,36 @@ properties: "#reset-cells": const: 1 +patternProperties: + "^(sclk)|(pll-[cem])$": + type: object + properties: + compatible: + enum: + - nvidia,tegra20-sclk + - nvidia,tegra30-sclk + - nvidia,tegra30-pllc + - nvidia,tegra30-plle + - nvidia,tegra30-pllm + + operating-points-v2: true + + clocks: + items: + - description: node's clock + + power-domains: + maxItems: 1 + description: phandle to the core SoC power domain + + required: + - compatible + - operating-points-v2 + - clocks + - power-domains + + additionalProperties: false + required: - compatible - reg @@ -59,6 +89,13 @@ examples: reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + sclk { + compatible = "nvidia,tegra20-sclk"; + operating-points-v2 = <&opp_table>; + clocks = <&tegra_car TEGRA20_CLK_SCLK>; + power-domains = <&domain>; + }; }; usb-controller@c5004000 { diff --git a/dts/Bindings/clock/qcom,gcc-msm8976.yaml b/dts/Bindings/clock/qcom,gcc-msm8976.yaml new file mode 100644 index 0000000000..f3430b159c --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-msm8976.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for MSM8976 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on MSM8976. + + See also: + - dt-bindings/clock/qcom,gcc-msm8976.h + +properties: + compatible: + enum: + - qcom,gcc-msm8976 + - qcom,gcc-msm8976-v1.1 + + clocks: + items: + - description: XO source + - description: Always-on XO source + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY1 + - description: Byte clock from DSI PHY1 + + clock-names: + items: + - const: xo + - const: xo_a + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + + vdd_gfx-supply: + description: + Phandle to voltage regulator providing power to the GX domain. + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - vdd_gfx-supply + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,gcc-msm8976"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x1800000 0x80000>; + + clocks = <&xo_board>, + <&xo_board>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>; + + clock-names = "xo", + "xo_a", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; + + vdd_gfx-supply = <&pm8004_s5>; + }; +... diff --git a/dts/Bindings/clock/qcom,gcc-sdx65.yaml b/dts/Bindings/clock/qcom,gcc-sdx65.yaml new file mode 100644 index 0000000000..16c4cdc7b4 --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-sdx65.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SDX65 + +maintainers: + - Vamsi krishna Lanka <quic_vamslank@quicinc.com> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SDX65 + + See also: + - dt-bindings/clock/qcom,gcc-sdx65.h + +properties: + compatible: + const: qcom,gcc-sdx65 + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + - description: PCIE Pipe clock source + - description: USB3 phy wrapper pipe clock source + - description: PLL test clock source (Optional clock) + minItems: 5 + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + - const: pcie_pipe_clk + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk + - const: core_bi_pll_test_se # Optional clock + minItems: 5 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sdx65"; + reg = <0x100000 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, + <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", + "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,gcc-sm8450.yaml b/dts/Bindings/clock/qcom,gcc-sm8450.yaml new file mode 100644 index 0000000000..58d98a766d --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-sm8450.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SM8450 + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SM8450 + + See also: + - dt-bindings/clock/qcom,gcc-sm8450.h + +properties: + compatible: + const: qcom,gcc-sm8450 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source (Optional clock) + - description: PCIE 1 Pipe clock source (Optional clock) + - description: PCIE 1 Phy Auxillary clock source (Optional clock) + - description: UFS Phy Rx symbol 0 clock source (Optional clock) + - description: UFS Phy Rx symbol 1 clock source (Optional clock) + - description: UFS Phy Tx symbol 0 clock source (Optional clock) + - description: USB3 Phy wrapper pipe clock source (Optional clock) + minItems: 2 + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + - const: pcie_0_pipe_clk # Optional clock + - const: pcie_1_pipe_clk # Optional clock + - const: pcie_1_phy_aux_clk # Optional clock + - const: ufs_phy_rx_symbol_0_clk # Optional clock + - const: ufs_phy_rx_symbol_1_clk # Optional clock + - const: ufs_phy_tx_symbol_0_clk # Optional clock + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock + minItems: 2 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sm8450"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/dts/Bindings/clock/qcom,rpmhcc.yaml b/dts/Bindings/clock/qcom,rpmhcc.yaml index 72212970e6..8406dde179 100644 --- a/dts/Bindings/clock/qcom,rpmhcc.yaml +++ b/dts/Bindings/clock/qcom,rpmhcc.yaml @@ -22,10 +22,12 @@ properties: - qcom,sc8180x-rpmh-clk - qcom,sdm845-rpmh-clk - qcom,sdx55-rpmh-clk + - qcom,sdx65-rpmh-clk - qcom,sm6350-rpmh-clk - qcom,sm8150-rpmh-clk - qcom,sm8250-rpmh-clk - qcom,sm8350-rpmh-clk + - qcom,sm8450-rpmh-clk clocks: maxItems: 1 diff --git a/dts/Bindings/clock/renesas,cpg-mssr.yaml b/dts/Bindings/clock/renesas,cpg-mssr.yaml index 9b414fbde6..e0b86214f0 100644 --- a/dts/Bindings/clock/renesas,cpg-mssr.yaml +++ b/dts/Bindings/clock/renesas,cpg-mssr.yaml @@ -48,6 +48,7 @@ properties: - renesas,r8a77990-cpg-mssr # R-Car E3 - renesas,r8a77995-cpg-mssr # R-Car D3 - renesas,r8a779a0-cpg-mssr # R-Car V3U + - renesas,r8a779f0-cpg-mssr # R-Car S4-8 reg: maxItems: 1 diff --git a/dts/Bindings/clock/samsung,exynos5260-clock.yaml b/dts/Bindings/clock/samsung,exynos5260-clock.yaml new file mode 100644 index 0000000000..a3fac5c680 --- /dev/null +++ b/dts/Bindings/clock/samsung,exynos5260-clock.yaml @@ -0,0 +1,382 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos5260 SoC clock controller + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Expected external clocks, defined in DTS as fixed-rate clocks with a matching + name:: + - "fin_pll" - PLL input clock from XXTI + - "xrtcxti" - input clock from XRTCXTI + - "ioclk_pcm_extclk" - pcm external operation clock + - "ioclk_spdif_extclk" - spdif external operation clock + - "ioclk_i2s_cdclk" - i2s0 codec clock + + Phy clocks:: + There are several clocks which are generated by specific PHYs. These clocks + are fed into the clock controller and then routed to the hardware blocks. + These clocks are defined as fixed clocks in the driver with following names:: + - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3 + - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2 + - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1 + - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0 + - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock + - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock + - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link + - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock + - "phyclk_dptx_phy_clk_div2" + - "phyclk_mipi_dphy_4l_m_rxclkesc0" + - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock + - "phyclk_usbhost20_phy_freeclk" + - "phyclk_usbhost20_phy_clk48mohci" + - "phyclk_usbdrd30_udrd30_pipe_pclk" + - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock + + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/exynos5260-clk.h header. + +properties: + compatible: + enum: + - samsung,exynos5260-clock-top + - samsung,exynos5260-clock-peri + - samsung,exynos5260-clock-egl + - samsung,exynos5260-clock-kfc + - samsung,exynos5260-clock-g2d + - samsung,exynos5260-clock-mif + - samsung,exynos5260-clock-mfc + - samsung,exynos5260-clock-g3d + - samsung,exynos5260-clock-fsys + - samsung,exynos5260-clock-aud + - samsung,exynos5260-clock-isp + - samsung,exynos5260-clock-gscl + - samsung,exynos5260-clock-disp + + clocks: + minItems: 1 + maxItems: 19 + + clock-names: + minItems: 1 + maxItems: 19 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-top + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: fin_pll + - const: dout_mem_pll + - const: dout_bus_pll + - const: dout_media_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-peri + then: + properties: + clocks: + minItems: 13 + maxItems: 13 + clock-names: + items: + - const: fin_pll + - const: ioclk_pcm_extclk + - const: ioclk_i2s_cdclk + - const: ioclk_spdif_extclk + - const: phyclk_hdmi_phy_ref_cko + - const: dout_aclk_peri_66 + - const: dout_sclk_peri_uart0 + - const: dout_sclk_peri_uart1 + - const: dout_sclk_peri_uart2 + - const: dout_sclk_peri_spi0_b + - const: dout_sclk_peri_spi1_b + - const: dout_sclk_peri_spi2_b + - const: dout_aclk_peri_aud + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-egl + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: fin_pll + - const: dout_bus_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-kfc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: fin_pll + - const: dout_media_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-g2d + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_g2d_333 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-mif + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: fin_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-mfc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_mfc_333 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-g3d + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: fin_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-fsys + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: fin_pll + - const: phyclk_usbhost20_phy_phyclock + - const: phyclk_usbhost20_phy_freeclk + - const: phyclk_usbhost20_phy_clk48mohci + - const: phyclk_usbdrd30_udrd30_pipe_pclk + - const: phyclk_usbdrd30_udrd30_phyclock + - const: dout_aclk_fsys_200 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-aud + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: fin_pll + - const: fout_aud_pll + - const: ioclk_i2s_cdclk + - const: ioclk_pcm_extclk + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-isp + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_isp1_266 + - const: dout_aclk_isp1_400 + - const: mout_aclk_isp1_266 + + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-gscl + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_gscl_400 + - const: dout_aclk_gscl_333 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-disp + then: + properties: + clocks: + minItems: 19 + maxItems: 19 + clock-names: + items: + - const: fin_pll + - const: phyclk_dptx_phy_ch3_txd_clk + - const: phyclk_dptx_phy_ch2_txd_clk + - const: phyclk_dptx_phy_ch1_txd_clk + - const: phyclk_dptx_phy_ch0_txd_clk + - const: phyclk_hdmi_phy_tmds_clko + - const: phyclk_hdmi_phy_ref_clko + - const: phyclk_hdmi_phy_pixel_clko + - const: phyclk_hdmi_link_o_tmds_clkhi + - const: phyclk_mipi_dphy_4l_m_txbyte_clkhs + - const: phyclk_dptx_phy_o_ref_clk_24m + - const: phyclk_dptx_phy_clk_div2 + - const: phyclk_mipi_dphy_4l_m_rxclkesc0 + - const: phyclk_hdmi_phy_ref_cko + - const: ioclk_spdif_extclk + - const: dout_aclk_peri_aud + - const: dout_aclk_disp_222 + - const: dout_sclk_disp_pixel + - const: dout_aclk_disp_333 + required: + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos5260-clk.h> + + fin_pll: clock { + compatible = "fixed-clock"; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + clock-controller@10010000 { + compatible = "samsung,exynos5260-clock-top"; + reg = <0x10010000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_mif MIF_DOUT_MEM_PLL>, + <&clock_mif MIF_DOUT_BUS_PLL>, + <&clock_mif MIF_DOUT_MEDIA_PLL>; + clock-names = "fin_pll", + "dout_mem_pll", + "dout_bus_pll", + "dout_media_pll"; + }; diff --git a/dts/Bindings/clock/samsung,exynos5410-clock.yaml b/dts/Bindings/clock/samsung,exynos5410-clock.yaml new file mode 100644 index 0000000000..032862e9f5 --- /dev/null +++ b/dts/Bindings/clock/samsung,exynos5410-clock.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos5410 SoC clock controller + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Expected external clocks, defined in DTS as fixed-rate clocks with a matching + name:: + - "fin_pll" - PLL input clock from XXTI + + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/exynos5410.h header. + +properties: + compatible: + oneOf: + - enum: + - samsung,exynos5410-clock + + clocks: + description: + Should contain an entry specifying the root clock from external + oscillator supplied through XXTI or XusbXTI pin. This clock should be + defined using standard clock bindings with "fin_pll" clock-output-name. + That clock is being passed internally to the 9 PLLs. + maxItems: 1 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos5410.h> + + fin_pll: osc-clock { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + clock-controller@10010000 { + compatible = "samsung,exynos5410-clock"; + reg = <0x10010000 0x30000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + }; diff --git a/dts/Bindings/clock/samsung,exynos5433-clock.yaml b/dts/Bindings/clock/samsung,exynos5433-clock.yaml new file mode 100644 index 0000000000..edd1b4ac43 --- /dev/null +++ b/dts/Bindings/clock/samsung,exynos5433-clock.yaml @@ -0,0 +1,524 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos5433 SoC clock controller + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Expected external clocks, defined in DTS as fixed-rate clocks with a matching + name:: + - "oscclk" - PLL input clock from XXTI + + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/exynos5433.h header. + +properties: + compatible: + enum: + # CMU_TOP which generates clocks for + # IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS domains and bus + # clocks + - samsung,exynos5433-cmu-top + # CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP + - samsung,exynos5433-cmu-cpif + # CMU_MIF which generates clocks for DRAM Memory Controller domain + - samsung,exynos5433-cmu-mif + # CMU_PERIC which generates clocks for + # UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs + - samsung,exynos5433-cmu-peric + # CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs + - samsung,exynos5433-cmu-peris + # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs + - samsung,exynos5433-cmu-fsys + - samsung,exynos5433-cmu-g2d + # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs + - samsung,exynos5433-cmu-disp + - samsung,exynos5433-cmu-aud + - samsung,exynos5433-cmu-bus0 + - samsung,exynos5433-cmu-bus1 + - samsung,exynos5433-cmu-bus2 + - samsung,exynos5433-cmu-g3d + - samsung,exynos5433-cmu-gscl + - samsung,exynos5433-cmu-apollo + # CMU_ATLAS which generates clocks for Cortex-A57 Quad-core processor, + # CoreSight and L2 cache controller + - samsung,exynos5433-cmu-atlas + # CMU_MSCL which generates clocks for M2M (Memory to Memory) scaler and + # JPEG IPs + - samsung,exynos5433-cmu-mscl + - samsung,exynos5433-cmu-mfc + - samsung,exynos5433-cmu-hevc + # CMU_ISP which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs + - samsung,exynos5433-cmu-isp + # CMU_CAM0 which generates clocks for + # MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs + - samsung,exynos5433-cmu-cam0 + # CMU_CAM1 which generates clocks for + # Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs + - samsung,exynos5433-cmu-cam1 + # CMU_IMEM which generates clocks for SSS (Security SubSystem) and + # SlimSSS IPs + - samsung,exynos5433-cmu-imem + + clocks: + minItems: 1 + maxItems: 10 + + clock-names: + minItems: 1 + maxItems: 10 + + "#clock-cells": + const: 1 + + power-domains: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-top + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: oscclk + - const: sclk_mphy_pll + - const: sclk_mfc_pll + - const: sclk_bus_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-cpif + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: oscclk + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-mif + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: sclk_mphy_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-fsys + then: + properties: + clocks: + minItems: 10 + maxItems: 10 + clock-names: + items: + - const: oscclk + - const: sclk_ufs_mphy + - const: aclk_fsys_200 + - const: sclk_pcie_100_fsys + - const: sclk_ufsunipro_fsys + - const: sclk_mmc2_fsys + - const: sclk_mmc1_fsys + - const: sclk_mmc0_fsys + - const: sclk_usbhost30_fsys + - const: sclk_usbdrd30_fsys + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-g2d + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: oscclk + - const: aclk_g2d_266 + - const: aclk_g2d_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-disp + then: + properties: + clocks: + minItems: 9 + maxItems: 9 + clock-names: + items: + - const: oscclk + - const: sclk_dsim1_disp + - const: sclk_dsim0_disp + - const: sclk_dsd_disp + - const: sclk_decon_tv_eclk_disp + - const: sclk_decon_vclk_disp + - const: sclk_decon_eclk_disp + - const: sclk_decon_tv_vclk_disp + - const: aclk_disp_333 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-aud + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: fout_aud_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-bus0 + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: aclk_bus0_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-bus1 + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: aclk_bus1_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-bus2 + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: aclk_bus2_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-g3d + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: aclk_g3d_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-gscl + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: oscclk + - const: aclk_gscl_111 + - const: aclk_gscl_333 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-apollo + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: sclk_bus_pll_apollo + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-atlas + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: sclk_bus_pll_atlas + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-mscl + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: oscclk + - const: sclk_jpeg_mscl + - const: aclk_mscl_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-mfc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: aclk_mfc_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-hevc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: aclk_hevc_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-isp + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: oscclk + - const: aclk_isp_dis_400 + - const: aclk_isp_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-cam0 + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: oscclk + - const: aclk_cam0_333 + - const: aclk_cam0_400 + - const: aclk_cam0_552 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-cam1 + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: oscclk + - const: sclk_isp_uart_cam1 + - const: sclk_isp_spi1_cam1 + - const: sclk_isp_spi0_cam1 + - const: aclk_cam1_333 + - const: aclk_cam1_400 + - const: aclk_cam1_552 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-imem + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: oscclk + - const: aclk_imem_sssx_266 + - const: aclk_imem_266 + - const: aclk_imem_200 + required: + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos5433.h> + xxti: clock { + compatible = "fixed-clock"; + clock-output-names = "oscclk"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + clock-controller@10030000 { + compatible = "samsung,exynos5433-cmu-top"; + reg = <0x10030000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_mphy_pll", + "sclk_mfc_pll", + "sclk_bus_pll"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_MPHY_PLL>, + <&cmu_mif CLK_SCLK_MFC_PLL>, + <&cmu_mif CLK_SCLK_BUS_PLL>; + }; diff --git a/dts/Bindings/clock/samsung,exynos7-clock.yaml b/dts/Bindings/clock/samsung,exynos7-clock.yaml new file mode 100644 index 0000000000..599baf0b72 --- /dev/null +++ b/dts/Bindings/clock/samsung,exynos7-clock.yaml @@ -0,0 +1,272 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos7 SoC clock controller + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Expected external clocks, defined in DTS as fixed-rate clocks with a matching + name:: + - "fin_pll" - PLL input clock from XXTI + + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/exynos7-clk.h header. + +properties: + compatible: + enum: + - samsung,exynos7-clock-topc + - samsung,exynos7-clock-top0 + - samsung,exynos7-clock-top1 + - samsung,exynos7-clock-ccore + - samsung,exynos7-clock-peric0 + - samsung,exynos7-clock-peric1 + - samsung,exynos7-clock-peris + - samsung,exynos7-clock-fsys0 + - samsung,exynos7-clock-fsys1 + - samsung,exynos7-clock-mscl + - samsung,exynos7-clock-aud + + clocks: + minItems: 1 + maxItems: 13 + + clock-names: + minItems: 1 + maxItems: 13 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-top0 + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: fin_pll + - const: dout_sclk_bus0_pll + - const: dout_sclk_bus1_pll + - const: dout_sclk_cc_pll + - const: dout_sclk_mfc_pll + - const: dout_sclk_aud_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-top1 + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + items: + - const: fin_pll + - const: dout_sclk_bus0_pll + - const: dout_sclk_bus1_pll + - const: dout_sclk_cc_pll + - const: dout_sclk_mfc_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-ccore + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_ccore_133 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-peric0 + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_peric0_66 + - const: sclk_uart0 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-peric1 + then: + properties: + clocks: + minItems: 13 + maxItems: 13 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_peric1_66 + - const: sclk_uart1 + - const: sclk_uart2 + - const: sclk_uart3 + - const: sclk_spi0 + - const: sclk_spi1 + - const: sclk_spi2 + - const: sclk_spi3 + - const: sclk_spi4 + - const: sclk_i2s1 + - const: sclk_pcm1 + - const: sclk_spdif + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-peris + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_peris_66 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-fsys0 + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_fsys0_200 + - const: dout_sclk_mmc2 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-fsys1 + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_fsys1_200 + - const: dout_sclk_mmc0 + - const: dout_sclk_mmc1 + - const: dout_sclk_ufsunipro20 + - const: dout_sclk_phy_fsys1 + - const: dout_sclk_phy_fsys1_26m + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-aud + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: fin_pll + - const: fout_aud_pll + required: + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos7-clk.h> + + fin_pll: clock { + compatible = "fixed-clock"; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + clock-controller@105e0000 { + compatible = "samsung,exynos7-clock-top1"; + reg = <0x105e0000 0xb000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_topc DOUT_SCLK_BUS0_PLL>, + <&clock_topc DOUT_SCLK_BUS1_PLL>, + <&clock_topc DOUT_SCLK_CC_PLL>, + <&clock_topc DOUT_SCLK_MFC_PLL>; + clock-names = "fin_pll", + "dout_sclk_bus0_pll", + "dout_sclk_bus1_pll", + "dout_sclk_cc_pll", + "dout_sclk_mfc_pll"; + }; diff --git a/dts/Bindings/clock/samsung,exynos7885-clock.yaml b/dts/Bindings/clock/samsung,exynos7885-clock.yaml new file mode 100644 index 0000000000..7e5a9cac2f --- /dev/null +++ b/dts/Bindings/clock/samsung,exynos7885-clock.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos7885 SoC clock controller + +maintainers: + - Dávid Virág <virag.david003@gmail.com> + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Exynos7885 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clock in that root tree + is an external clock: OSCCLK (26 MHz). This external clock must be defined + as a fixed-rate clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'dt-bindings/clock/exynos7885.h' header. + +properties: + compatible: + enum: + - samsung,exynos7885-cmu-top + - samsung,exynos7885-cmu-core + - samsung,exynos7885-cmu-peri + + clocks: + minItems: 1 + maxItems: 10 + + clock-names: + minItems: 1 + maxItems: 10 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos7885-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos7885-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CORE bus clock (from CMU_TOP) + - description: CCI clock (from CMU_TOP) + - description: G3D clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_core_bus + - const: dout_core_cci + - const: dout_core_g3d + + - if: + properties: + compatible: + contains: + const: samsung,exynos7885-cmu-peri + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERI bus clock (from CMU_TOP) + - description: SPI0 clock (from CMU_TOP) + - description: SPI1 clock (from CMU_TOP) + - description: UART0 clock (from CMU_TOP) + - description: UART1 clock (from CMU_TOP) + - description: UART2 clock (from CMU_TOP) + - description: USI0 clock (from CMU_TOP) + - description: USI1 clock (from CMU_TOP) + - description: USI2 clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_peri_bus + - const: dout_peri_spi0 + - const: dout_peri_spi1 + - const: dout_peri_uart0 + - const: dout_peri_uart1 + - const: dout_peri_uart2 + - const: dout_peri_usi0 + - const: dout_peri_usi1 + - const: dout_peri_usi2 + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_PERI + - | + #include <dt-bindings/clock/exynos7885.h> + + cmu_peri: clock-controller@10010000 { + compatible = "samsung,exynos7885-cmu-peri"; + reg = <0x10010000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_PERI_BUS>, + <&cmu_top CLK_DOUT_PERI_SPI0>, + <&cmu_top CLK_DOUT_PERI_SPI1>, + <&cmu_top CLK_DOUT_PERI_UART0>, + <&cmu_top CLK_DOUT_PERI_UART1>, + <&cmu_top CLK_DOUT_PERI_UART2>, + <&cmu_top CLK_DOUT_PERI_USI0>, + <&cmu_top CLK_DOUT_PERI_USI1>, + <&cmu_top CLK_DOUT_PERI_USI2>; + clock-names = "oscclk", + "dout_peri_bus", + "dout_peri_spi0", + "dout_peri_spi1", + "dout_peri_uart0", + "dout_peri_uart1", + "dout_peri_uart2", + "dout_peri_usi0", + "dout_peri_usi1", + "dout_peri_usi2"; + }; + +... diff --git a/dts/Bindings/clock/samsung,exynos850-clock.yaml b/dts/Bindings/clock/samsung,exynos850-clock.yaml index 7f8c91a29b..80ba60838f 100644 --- a/dts/Bindings/clock/samsung,exynos850-clock.yaml +++ b/dts/Bindings/clock/samsung,exynos850-clock.yaml @@ -32,6 +32,8 @@ properties: compatible: enum: - samsung,exynos850-cmu-top + - samsung,exynos850-cmu-apm + - samsung,exynos850-cmu-cmgp - samsung,exynos850-cmu-core - samsung,exynos850-cmu-dpu - samsung,exynos850-cmu-hsi @@ -72,6 +74,42 @@ allOf: properties: compatible: contains: + const: samsung,exynos850-cmu-apm + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_APM bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_apm_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-cmgp + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CMGP bus clock (from CMU_APM) + + clock-names: + items: + - const: oscclk + - const: gout_clkcmu_cmgp_bus + + - if: + properties: + compatible: + contains: const: samsung,exynos850-cmu-core then: diff --git a/dts/Bindings/clock/samsung,s5pv210-clock.txt b/dts/Bindings/clock/samsung,s5pv210-clock.txt deleted file mode 100644 index a86c83bf9d..0000000000 --- a/dts/Bindings/clock/samsung,s5pv210-clock.txt +++ /dev/null @@ -1,77 +0,0 @@ -* Samsung S5P6442/S5PC110/S5PV210 Clock Controller - -Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock -controller, which generates and supplies clock to various controllers -within the SoC. - -Required Properties: - -- compatible: should be one of following: - - "samsung,s5pv210-clock" : for clock controller of Samsung - S5PC110/S5PV210 SoCs, - - "samsung,s5p6442-clock" : for clock controller of Samsung - S5P6442 SoC. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s5pv210.h header and can be used in device tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xxti": external crystal oscillator connected to XXTI and XXTO pins of -the SoC, - - "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO -pins of the SoC, - -A subset of above clocks available on given board shall be specified in -board device tree, including the system base clock, as selected by XOM[0] -pin of the SoC. Refer to generic fixed rate clock bindings -documentation[1] for more information how to specify these clocks. - -[1] Documentation/devicetree/bindings/clock/fixed-clock.yaml - -Example: Clock controller node: - - clock: clock-controller@7e00f000 { - compatible = "samsung,s5pv210-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; - -Example: Required external clocks: - - xxti: clock-xxti { - compatible = "fixed-clock"; - clock-output-names = "xxti"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - xusbxti: clock-xusbxti { - compatible = "fixed-clock"; - clock-output-names = "xusbxti"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - uart0: serial@e2900000 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900000 0x400>; - interrupt-parent = <&vic1>; - interrupts = <10>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks UART0>, <&clocks UART0>, - <&clocks SCLK_UART0>; - }; diff --git a/dts/Bindings/clock/samsung,s5pv210-clock.yaml b/dts/Bindings/clock/samsung,s5pv210-clock.yaml new file mode 100644 index 0000000000..dcb29a2d11 --- /dev/null +++ b/dts/Bindings/clock/samsung,s5pv210-clock.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Expected external clocks, defined in DTS as fixed-rate clocks with a matching + name:: + - "xxti" - external crystal oscillator connected to XXTI and XXTO pins of + the SoC, + - "xusbxti" - external crystal oscillator connected to XUSBXTI and XUSBXTO + pins of the SoC, + + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/s5pv210.h header. + +properties: + compatible: + enum: + - samsung,s5pv210-clock + - samsung,s5p6442-clock + + clocks: + items: + - description: xxti clock + - description: xusbxti clock + + clock-names: + items: + - const: xxti + - const: xusbxti + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/s5pv210.h> + + xxti: clock-0 { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "xxti"; + #clock-cells = <0>; + }; + + xusbxti: clock-1 { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "xusbxti"; + #clock-cells = <0>; + }; + + clock-controller@e0100000 { + compatible = "samsung,s5pv210-clock"; + reg = <0xe0100000 0x10000>; + clock-names = "xxti", "xusbxti"; + clocks = <&xxti>, <&xusbxti>; + #clock-cells = <1>; + }; diff --git a/dts/Bindings/clock/starfive,jh7100-clkgen.yaml b/dts/Bindings/clock/starfive,jh7100-clkgen.yaml new file mode 100644 index 0000000000..12f17b60ec --- /dev/null +++ b/dts/Bindings/clock/starfive,jh7100-clkgen.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 Clock Generator + +maintainers: + - Geert Uytterhoeven <geert@linux-m68k.org> + - Emil Renner Berthing <kernel@esmil.dk> + +properties: + compatible: + const: starfive,jh7100-clkgen + + reg: + maxItems: 1 + + clocks: + items: + - description: Main clock source (25 MHz) + - description: Application-specific clock source (12-27 MHz) + - description: RMII reference clock (50 MHz) + - description: RGMII RX clock (125 MHz) + + clock-names: + items: + - const: osc_sys + - const: osc_aud + - const: gmac_rmii_ref + - const: gmac_gr_mii_rxclk + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive-jh7100.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@11800000 { + compatible = "starfive,jh7100-clkgen"; + reg = <0x11800000 0x10000>; + clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>; + clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk"; + #clock-cells = <1>; + }; diff --git a/dts/Bindings/clock/toshiba,tmpv770x-pipllct.yaml b/dts/Bindings/clock/toshiba,tmpv770x-pipllct.yaml new file mode 100644 index 0000000000..7b7300ce96 --- /dev/null +++ b/dts/Bindings/clock/toshiba,tmpv770x-pipllct.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pipllct.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti5 TMPV770X PLL Controller Device Tree Bindings + +maintainers: + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + +description: + Toshia Visconti5 PLL controller which supports the PLLs on TMPV770X. + +properties: + compatible: + const: toshiba,tmpv7708-pipllct + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + description: External reference clock (OSC2) + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - clocks + +additionalProperties: false + +examples: + - | + + osc2_clk: osc2-clk { + compatible = "fixed-clock"; + clock-frequency = <20000000>; + #clock-cells = <0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pipllct: clock-controller@24220000 { + compatible = "toshiba,tmpv7708-pipllct"; + reg = <0 0x24220000 0 0x820>; + #clock-cells = <1>; + clocks = <&osc2_clk>; + }; + }; +... diff --git a/dts/Bindings/clock/toshiba,tmpv770x-pismu.yaml b/dts/Bindings/clock/toshiba,tmpv770x-pismu.yaml new file mode 100644 index 0000000000..ed79f16fe6 --- /dev/null +++ b/dts/Bindings/clock/toshiba,tmpv770x-pismu.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pismu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti5 TMPV770x SMU controller Device Tree Bindings + +maintainers: + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + +description: + Toshia Visconti5 SMU (System Management Unit) which supports the clock + and resets on TMPV770x. + +properties: + compatible: + items: + - const: toshiba,tmpv7708-pismu + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pismu: syscon@24200000 { + compatible = "toshiba,tmpv7708-pismu", "syscon"; + reg = <0 0x24200000 0 0x2140>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +... diff --git a/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml b/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml index 0429fb774f..dedc99e34e 100644 --- a/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml +++ b/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml @@ -44,6 +44,16 @@ properties: - const: ahb - const: mod + dmas: + items: + - description: RX DMA Channel + - description: TX DMA Channel + + dma-names: + items: + - const: rx + - const: tx + resets: maxItems: 1 diff --git a/dts/Bindings/crypto/qcom,prng.txt b/dts/Bindings/crypto/qcom,prng.txt deleted file mode 100644 index 7ee0e9eac9..0000000000 --- a/dts/Bindings/crypto/qcom,prng.txt +++ /dev/null @@ -1,19 +0,0 @@ -Qualcomm MSM pseudo random number generator. - -Required properties: - -- compatible : should be "qcom,prng" for 8916 etc - : should be "qcom,prng-ee" for 8996 and later using EE - (Execution Environment) slice of prng -- reg : specifies base physical address and size of the registers map -- clocks : phandle to clock-controller plus clock-specifier pair -- clock-names : "core" clocks all registers, FIFO and circuits in PRNG IP block - -Example: - - rng@f9bff000 { - compatible = "qcom,prng"; - reg = <0xf9bff000 0x200>; - clocks = <&clock GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; diff --git a/dts/Bindings/crypto/qcom,prng.yaml b/dts/Bindings/crypto/qcom,prng.yaml new file mode 100644 index 0000000000..bb42f4588b --- /dev/null +++ b/dts/Bindings/crypto/qcom,prng.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/qcom,prng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Pseudo Random Number Generator + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +properties: + compatible: + enum: + - qcom,prng # 8916 etc. + - qcom,prng-ee # 8996 and later using EE + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + rng@f9bff000 { + compatible = "qcom,prng"; + reg = <0xf9bff000 0x200>; + clocks = <&clk 125>; + clock-names = "core"; + }; diff --git a/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml b/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml index cf5a208f2f..343598c9f4 100644 --- a/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml +++ b/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml @@ -10,6 +10,9 @@ title: Amlogic specific extensions to the Synopsys Designware HDMI Controller maintainers: - Neil Armstrong <narmstrong@baylibre.com> +allOf: + - $ref: /schemas/sound/name-prefix.yaml# + description: | The Amlogic Meson Synopsys Designware Integration is composed of - A Synopsys DesignWare HDMI Controller IP @@ -99,6 +102,8 @@ properties: "#sound-dai-cells": const: 0 + sound-name-prefix: true + required: - compatible - reg diff --git a/dts/Bindings/display/amlogic,meson-vpu.yaml b/dts/Bindings/display/amlogic,meson-vpu.yaml index 851cb07812..047fd69e03 100644 --- a/dts/Bindings/display/amlogic,meson-vpu.yaml +++ b/dts/Bindings/display/amlogic,meson-vpu.yaml @@ -78,6 +78,10 @@ properties: interrupts: maxItems: 1 + amlogic,canvas: + description: should point to a canvas provider node + $ref: /schemas/types.yaml#/definitions/phandle + power-domains: maxItems: 1 description: phandle to the associated power domain @@ -106,6 +110,7 @@ required: - port@1 - "#address-cells" - "#size-cells" + - amlogic,canvas additionalProperties: false @@ -118,6 +123,7 @@ examples: interrupts = <3>; #address-cells = <1>; #size-cells = <0>; + amlogic,canvas = <&canvas>; /* CVBS VDAC output port */ port@0 { diff --git a/dts/Bindings/display/bridge/analogix,anx7625.yaml b/dts/Bindings/display/bridge/analogix,anx7625.yaml index ab48ab2f42..1d3e88daca 100644 --- a/dts/Bindings/display/bridge/analogix,anx7625.yaml +++ b/dts/Bindings/display/bridge/analogix,anx7625.yaml @@ -43,14 +43,70 @@ properties: vdd33-supply: description: Regulator that provides the supply 3.3V power. + analogix,lane0-swing: + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 1 + maxItems: 20 + description: + an array of swing register setting for DP tx lane0 PHY. + Registers 0~9 are Swing0_Pre0, Swing1_Pre0, Swing2_Pre0, + Swing3_Pre0, Swing0_Pre1, Swing1_Pre1, Swing2_Pre1, Swing0_Pre2, + Swing1_Pre2, Swing0_Pre3, they are for [Boost control] and + [Swing control] setting. + Registers 0~9, bit 3:0 is [Boost control], these bits control + post cursor manual, increase the [Boost control] to increase + Pre-emphasis value. + Registers 0~9, bit 6:4 is [Swing control], these bits control + swing manual, increase [Swing control] setting to add Vp-p value + for each Swing, Pre. + Registers 10~19 are Swing0_Pre0, Swing1_Pre0, Swing2_Pre0, + Swing3_Pre0, Swing0_Pre1, Swing1_Pre1, Swing2_Pre1, Swing0_Pre2, + Swing1_Pre2, Swing0_Pre3, they are for [R select control] and + [R Termination control] setting. + Registers 10~19, bit 4:0 is [R select control], these bits are + compensation manual, increase it can enhance IO driven strength + and Vp-p. + Registers 10~19, bit 5:6 is [R termination control], these bits + adjust 50ohm impedance of DP tx termination. 00:55 ohm, + 01:50 ohm(default), 10:45 ohm, 11:40 ohm. + + analogix,lane1-swing: + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 1 + maxItems: 20 + description: + an array of swing register setting for DP tx lane1 PHY. + DP TX lane1 swing register setting same with lane0 + swing, please refer lane0-swing property description. + + analogix,audio-enable: + type: boolean + description: let the driver enable audio HDMI codec function or not. + ports: $ref: /schemas/graph.yaml#/properties/ports properties: port@0: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: - Video port for MIPI DSI input. + MIPI DSI/DPI input. + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + type: object + additionalProperties: false + + properties: + remote-endpoint: true + + bus-type: + enum: [1, 5] + default: 1 + + data-lanes: true port@1: $ref: /schemas/graph.yaml#/properties/port @@ -87,6 +143,9 @@ examples: vdd10-supply = <&pp1000_mipibrdg>; vdd18-supply = <&pp1800_mipibrdg>; vdd33-supply = <&pp3300_mipibrdg>; + analogix,audio-enable; + analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>; + analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74>; ports { #address-cells = <1>; @@ -96,6 +155,8 @@ examples: reg = <0>; anx7625_in: endpoint { remote-endpoint = <&mipi_dsi>; + bus-type = <5>; + data-lanes = <0 1 2 3>; }; }; diff --git a/dts/Bindings/display/bridge/analogix,anx7814.yaml b/dts/Bindings/display/bridge/analogix,anx7814.yaml index 8e13f27b28..bce96b5b0d 100644 --- a/dts/Bindings/display/bridge/analogix,anx7814.yaml +++ b/dts/Bindings/display/bridge/analogix,anx7814.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analogix ANX7814 SlimPort (Full-HD Transmitter) maintainers: - - Enric Balletbo i Serra <enric.balletbo@collabora.com> + - Andrzej Hajda <andrzej.hajda@intel.com> + - Neil Armstrong <narmstrong@baylibre.com> + - Robert Foss <robert.foss@linaro.org> properties: compatible: diff --git a/dts/Bindings/display/bridge/google,cros-ec-anx7688.yaml b/dts/Bindings/display/bridge/google,cros-ec-anx7688.yaml index 9f7cc6b757..a88a5d8c7b 100644 --- a/dts/Bindings/display/bridge/google,cros-ec-anx7688.yaml +++ b/dts/Bindings/display/bridge/google,cros-ec-anx7688.yaml @@ -8,7 +8,6 @@ title: ChromeOS EC ANX7688 HDMI to DP Converter through Type-C Port maintainers: - Nicolas Boichat <drinkcat@chromium.org> - - Enric Balletbo i Serra <enric.balletbo@collabora.com> description: | ChromeOS EC ANX7688 is a display bridge that converts HDMI 2.0 to diff --git a/dts/Bindings/display/bridge/lvds-codec.yaml b/dts/Bindings/display/bridge/lvds-codec.yaml index 1faae3e323..5079c1cc33 100644 --- a/dts/Bindings/display/bridge/lvds-codec.yaml +++ b/dts/Bindings/display/bridge/lvds-codec.yaml @@ -79,6 +79,14 @@ properties: - port@0 - port@1 + pclk-sample: + description: + Data sampling on rising or falling edge. + enum: + - 0 # Falling edge + - 1 # Rising edge + default: 0 + powerdown-gpios: description: The GPIO used to control the power down line of this device. @@ -86,21 +94,32 @@ properties: power-supply: true -if: - not: - properties: - compatible: - contains: - const: lvds-decoder -then: - properties: - ports: +allOf: + - if: + not: + properties: + compatible: + contains: + const: lvds-decoder + then: properties: - port@0: + ports: properties: - endpoint: + port@0: properties: - data-mapping: false + endpoint: + properties: + data-mapping: false + + - if: + not: + properties: + compatible: + contains: + const: lvds-encoder + then: + properties: + pclk-sample: false required: - compatible diff --git a/dts/Bindings/display/bridge/nxp,ptn3460.yaml b/dts/Bindings/display/bridge/nxp,ptn3460.yaml new file mode 100644 index 0000000000..107dd138e6 --- /dev/null +++ b/dts/Bindings/display/bridge/nxp,ptn3460.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/nxp,ptn3460.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP PTN3460 eDP to LVDS bridge + +maintainers: + - Sean Paul <seanpaul@chromium.org> + +properties: + compatible: + const: nxp,ptn3460 + + reg: + description: I2C address of the bridge + maxItems: 1 + + edid-emulation: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: + The EDID emulation entry to use + Value Resolution Description + 0 1024x768 NXP Generic + 1 1920x1080 NXP Generic + 2 1920x1080 NXP Generic + 3 1600x900 Samsung LTM200KT + 4 1920x1080 Samsung LTM230HT + 5 1366x768 NXP Generic + 6 1600x900 ChiMei M215HGE + enum: [0, 1, 2, 3, 4, 5, 6] + + powerdown-gpios: + description: GPIO connected to the PD_N signal. + maxItems: 1 + + reset-gpios: + description: GPIO connected to the RST_N signal. + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for LVDS output + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for eDP input + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - edid-emulation + - powerdown-gpios + - reset-gpios + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + bridge@20 { + compatible = "nxp,ptn3460"; + reg = <0x20>; + edid-emulation = <5>; + powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + port@1 { + reg = <1>; + bridge_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/bridge/ps8640.yaml b/dts/Bindings/display/bridge/ps8640.yaml index cdaf7a7a8f..186e17be51 100644 --- a/dts/Bindings/display/bridge/ps8640.yaml +++ b/dts/Bindings/display/bridge/ps8640.yaml @@ -8,7 +8,6 @@ title: MIPI DSI to eDP Video Format Converter Device Tree Bindings maintainers: - Nicolas Boichat <drinkcat@chromium.org> - - Enric Balletbo i Serra <enric.balletbo@collabora.com> description: | The PS8640 is a low power MIPI-to-eDP video format converter supporting diff --git a/dts/Bindings/display/bridge/ptn3460.txt b/dts/Bindings/display/bridge/ptn3460.txt deleted file mode 100644 index 361971ba10..0000000000 --- a/dts/Bindings/display/bridge/ptn3460.txt +++ /dev/null @@ -1,39 +0,0 @@ -ptn3460 bridge bindings - -Required properties: - - compatible: "nxp,ptn3460" - - reg: i2c address of the bridge - - powerdown-gpio: OF device-tree gpio specification for PD_N pin. - - reset-gpio: OF device-tree gpio specification for RST_N pin. - - edid-emulation: The EDID emulation entry to use - +-------+------------+------------------+ - | Value | Resolution | Description | - | 0 | 1024x768 | NXP Generic | - | 1 | 1920x1080 | NXP Generic | - | 2 | 1920x1080 | NXP Generic | - | 3 | 1600x900 | Samsung LTM200KT | - | 4 | 1920x1080 | Samsung LTM230HT | - | 5 | 1366x768 | NXP Generic | - | 6 | 1600x900 | ChiMei M215HGE | - +-------+------------+------------------+ - - - video interfaces: Device node can contain video interface port - nodes for panel according to [1]. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - lvds-bridge@20 { - compatible = "nxp,ptn3460"; - reg = <0x20>; - powerdown-gpio = <&gpy2 5 1 0 0>; - reset-gpio = <&gpx1 5 1 0 0>; - edid-emulation = <5>; - ports { - port@0 { - bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; diff --git a/dts/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml b/dts/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml new file mode 100644 index 0000000000..afeeb96739 --- /dev/null +++ b/dts/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car MIPI DSI/CSI-2 Encoder + +maintainers: + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> + +description: | + This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas + R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up + to four data lanes. + +properties: + compatible: + enum: + - renesas,r8a779a0-dsi-csi2-tx # for V3U + + reg: + maxItems: 1 + + clocks: + items: + - description: Functional clock + - description: DSI (and CSI-2) functional clock + - description: PLL reference clock + + clock-names: + items: + - const: fck + - const: dsi + - const: pll + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Parallel input port + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: DSI/CSI-2 output port + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - power-domains + - resets + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a779a0-cpg-mssr.h> + #include <dt-bindings/power/r8a779a0-sysc.h> + + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779a0-dsi-csi2-tx"; + reg = <0xfed80000 0x10000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779A0_CLK_DSI>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "fck", "dsi", "pll"; + resets = <&cpg 415>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&sn65dsi86_in>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/bridge/sii9234.txt b/dts/Bindings/display/bridge/sii9234.txt deleted file mode 100644 index a55bf77bd9..0000000000 --- a/dts/Bindings/display/bridge/sii9234.txt +++ /dev/null @@ -1,49 +0,0 @@ -Silicon Image SiI9234 HDMI/MHL bridge bindings - -Required properties: - - compatible : "sil,sii9234". - - reg : I2C address for TPI interface, use 0x39 - - avcc33-supply : MHL/USB Switch Supply Voltage (3.3V) - - iovcc18-supply : I/O Supply Voltage (1.8V) - - avcc12-supply : TMDS Analog Supply Voltage (1.2V) - - cvcc12-supply : Digital Core Supply Voltage (1.2V) - - interrupts: interrupt specifier of INT pin - - reset-gpios: gpio specifier of RESET pin (active low) - - video interfaces: Device node can contain two video interface port - nodes for HDMI encoder and connector according to [1]. - - port@0 - MHL to HDMI - - port@1 - MHL to connector - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - - -Example: - sii9234@39 { - compatible = "sil,sii9234"; - reg = <0x39>; - avcc33-supply = <&vcc33mhl>; - iovcc18-supply = <&vcc18mhl>; - avcc12-supply = <&vsil12>; - cvcc12-supply = <&vsil12>; - reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpf3>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mhl_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_mhl>; - }; - }; - port@1 { - reg = <1>; - mhl_to_connector: endpoint { - remote-endpoint = <&connector_to_mhl>; - }; - }; - }; - }; diff --git a/dts/Bindings/display/bridge/sil,sii9234.yaml b/dts/Bindings/display/bridge/sil,sii9234.yaml new file mode 100644 index 0000000000..f88ddfe481 --- /dev/null +++ b/dts/Bindings/display/bridge/sil,sii9234.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/sil,sii9234.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Image SiI9234 HDMI/MHL bridge + +maintainers: + - Maciej Purski <m.purski@samsung.com> + +properties: + compatible: + const: sil,sii9234 + + reg: + description: I2C address for TPI interface + maxItems: 1 + + avcc12-supply: + description: TMDS Analog Supply Voltage, 1.2V + + avcc33-supply: + description: MHL/USB Switch Supply Voltage, 3.3V + + cvcc12-supply: + description: Digital Core Supply Voltage, 1.2V + + iovcc18-supply: + description: I/O voltage supply, 1.8V + + interrupts: + maxItems: 1 + + reset-gpios: + description: GPIO connected to the reset pin. + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for HDMI (encoder) input + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + MHL to connector port + + required: + - port@0 + +required: + - compatible + - reg + - avcc12-supply + - avcc33-supply + - cvcc12-supply + - iovcc18-supply + - interrupts + - reset-gpios + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + bridge@39 { + compatible = "sil,sii9234"; + reg = <0x39>; + avcc12-supply = <&vsil12>; + avcc33-supply = <&vcc33mhl>; + cvcc12-supply = <&vsil12>; + iovcc18-supply = <&vcc18mhl>; + interrupt-parent = <&gpf3>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mhl_to_hdmi: endpoint { + remote-endpoint = <&hdmi_to_mhl>; + }; + }; + + port@1 { + reg = <1>; + mhl_to_connector: endpoint { + remote-endpoint = <&connector_to_mhl>; + }; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/msm/dp-controller.yaml b/dts/Bindings/display/msm/dp-controller.yaml index 63e585f487..5457612ab1 100644 --- a/dts/Bindings/display/msm/dp-controller.yaml +++ b/dts/Bindings/display/msm/dp-controller.yaml @@ -17,6 +17,8 @@ properties: compatible: enum: - qcom,sc7180-dp + - qcom,sc7280-dp + - qcom,sc7280-edp - qcom,sc8180x-dp - qcom,sc8180x-edp diff --git a/dts/Bindings/display/msm/dpu-sdm845.yaml b/dts/Bindings/display/msm/dpu-sdm845.yaml index b4ea7c92fb..0dca4b3d66 100644 --- a/dts/Bindings/display/msm/dpu-sdm845.yaml +++ b/dts/Bindings/display/msm/dpu-sdm845.yaml @@ -31,13 +31,11 @@ properties: clocks: items: - description: Display AHB clock from gcc - - description: Display AXI clock - description: Display core clock clock-names: items: - const: iface - - const: bus - const: core interrupts: @@ -160,9 +158,8 @@ examples: power-domains = <&dispcc MDSS_GDSC>; clocks = <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "core"; + clock-names = "iface", "core"; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; diff --git a/dts/Bindings/display/msm/edp.txt b/dts/Bindings/display/msm/edp.txt deleted file mode 100644 index eff9daff41..0000000000 --- a/dts/Bindings/display/msm/edp.txt +++ /dev/null @@ -1,56 +0,0 @@ -Qualcomm Technologies Inc. adreno/snapdragon eDP output - -Required properties: -- compatible: - * "qcom,mdss-edp" -- reg: Physical base address and length of the registers of controller and PLL -- reg-names: The names of register regions. The following regions are required: - * "edp" - * "pll_base" -- interrupts: The interrupt signal from the eDP block. -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: the following clocks are required: - * "core" - * "iface" - * "mdp_core" - * "pixel" - * "link" -- #clock-cells: The value should be 1. -- vdda-supply: phandle to vdda regulator device node -- lvl-vdd-supply: phandle to regulator device node which is used to supply power - to HPD receiving chip -- panel-en-gpios: GPIO pin to supply power to panel. -- panel-hpd-gpios: GPIO pin used for eDP hpd. - - -Example: - mdss_edp: qcom,mdss_edp@fd923400 { - compatible = "qcom,mdss-edp"; - reg-names = - "edp", - "pll_base"; - reg = <0xfd923400 0x700>, - <0xfd923a00 0xd4>; - interrupt-parent = <&mdss_mdp>; - interrupts = <12 0>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = - "core", - "pixel", - "iface", - "link", - "mdp_core"; - clocks = - <&mmcc MDSS_EDPAUX_CLK>, - <&mmcc MDSS_EDPPIXEL_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_EDPLINK_CLK>, - <&mmcc MDSS_MDP_CLK>; - #clock-cells = <1>; - vdda-supply = <&pma8084_l12>; - lvl-vdd-supply = <&lvl_vreg>; - panel-en-gpios = <&tlmm 137 0>; - panel-hpd-gpios = <&tlmm 103 0>; - }; diff --git a/dts/Bindings/display/panel/abt,y030xx067a.yaml b/dts/Bindings/display/panel/abt,y030xx067a.yaml index a108029ecf..acd2f3faa6 100644 --- a/dts/Bindings/display/panel/abt,y030xx067a.yaml +++ b/dts/Bindings/display/panel/abt,y030xx067a.yaml @@ -6,15 +6,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Asia Better Technology 3.0" (320x480 pixels) 24-bit IPS LCD panel -description: | - The panel must obey the rules for a SPI slave device as specified in - spi/spi-controller.yaml - maintainers: - Paul Cercueil <paul@crapouillou.net> allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: diff --git a/dts/Bindings/display/panel/boe,bf060y8m-aj0.yaml b/dts/Bindings/display/panel/boe,bf060y8m-aj0.yaml new file mode 100644 index 0000000000..a8f3afa922 --- /dev/null +++ b/dts/Bindings/display/panel/boe,bf060y8m-aj0.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/boe,bf060y8m-aj0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BOE BF060Y8M-AJ0 5.99" 1080x2160 AMOLED Panel + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> + +description: | + This is a 5.99" 1080x2160 16.7M Color active matrix AMOLED + video mode panel module on MIPI-DSI 4-Lane interface, GGRB + pixel arrangement, 63 micrometers pitch, with an active + area of 68.04 x 136.08 millimeters. + Each pixel is divided into red and green dots, or blue and + green dots, and two pixels share red or blue dots which are + arranged in vertical stripe. + The DriverIC for this panel module is SW43404. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: boe,bf060y8m-aj0 + + elvdd-supply: + description: EL Driving positive (VDD) supply (4.40-4.80V) + elvss-supply: + description: EL Driving negative (VSS) supply (-5.00V to -1.40V) + vcc-supply: + description: Core (TSP) voltage supply (2.70-3.60V) + vci-supply: + description: DriverIC Operation supply (2.60-3.60V) + vddio-supply: + description: I/O voltage supply (1.62-1.98V) + + port: true + reg: true + reset-gpios: true + +required: + - compatible + - elvdd-supply + - elvss-supply + - vcc-supply + - vci-supply + - vddio-supply + - reg + - reset-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "boe,bf060y8m-aj0"; + reg = <0>; + + reset-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>; + + vcc-supply = <&disp_vcc_vreg>; + vddio-supply = <&disp_vddio_vreg>; + vci-supply = <&disp_vci_vreg>; + elvdd-supply = <&disp_elvdd_vreg>; + elvss-supply = <&disp_elvss_vreg>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/panel/ilitek,ili9163.yaml b/dts/Bindings/display/panel/ilitek,ili9163.yaml new file mode 100644 index 0000000000..7e7a8362b9 --- /dev/null +++ b/dts/Bindings/display/panel/ilitek,ili9163.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/ilitek,ili9163.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ilitek ILI9163 display panels device tree bindings + +maintainers: + - Daniel Mack <daniel@zonque.org> + +description: + This binding is for display panels using an Ilitek ILI9163 controller in SPI + mode. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - newhaven,1.8-128160EF + - const: ilitek,ili9163 + + spi-max-frequency: + maximum: 32000000 + + dc-gpios: + maxItems: 1 + description: Display data/command selection (D/CX) + + backlight: true + reg: true + reset-gpios: true + rotation: true + +required: + - compatible + - reg + - dc-gpios + - reset-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + }; + spi { + #address-cells = <1>; + #size-cells = <0>; + + display@0 { + compatible = "newhaven,1.8-128160EF", "ilitek,ili9163"; + reg = <0>; + spi-max-frequency = <32000000>; + dc-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + rotation = <180>; + backlight = <&backlight>; + }; + }; + +... diff --git a/dts/Bindings/display/panel/ilitek,ili9322.yaml b/dts/Bindings/display/panel/ilitek,ili9322.yaml index e89c1ea62f..7d221ef354 100644 --- a/dts/Bindings/display/panel/ilitek,ili9322.yaml +++ b/dts/Bindings/display/panel/ilitek,ili9322.yaml @@ -15,11 +15,9 @@ description: | 960 TFT source driver pins and 240 TFT gate driver pins, VCOM, VCOML and VCOMH outputs. - The panel must obey the rules for a SPI slave device as specified in - spi/spi-controller.yaml - allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: diff --git a/dts/Bindings/display/panel/ilitek,ili9881c.yaml b/dts/Bindings/display/panel/ilitek,ili9881c.yaml index b2fcec4f22..c5d1df6808 100644 --- a/dts/Bindings/display/panel/ilitek,ili9881c.yaml +++ b/dts/Bindings/display/panel/ilitek,ili9881c.yaml @@ -9,24 +9,28 @@ title: Ilitek ILI9881c based MIPI-DSI panels maintainers: - Maxime Ripard <mripard@kernel.org> +allOf: + - $ref: panel-common.yaml# + properties: compatible: items: - enum: - bananapi,lhr050h41 - feixin,k101-im2byl02 + - wanchanglong,w552946aba - const: ilitek,ili9881c backlight: true power-supply: true reg: true reset-gpios: true + rotation: true required: - compatible - power-supply - reg - - reset-gpios additionalProperties: false diff --git a/dts/Bindings/display/panel/innolux,ej030na.yaml b/dts/Bindings/display/panel/innolux,ej030na.yaml index cda36c04e8..72788e3e6c 100644 --- a/dts/Bindings/display/panel/innolux,ej030na.yaml +++ b/dts/Bindings/display/panel/innolux,ej030na.yaml @@ -6,15 +6,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Innolux EJ030NA 3.0" (320x480 pixels) 24-bit TFT LCD panel -description: | - The panel must obey the rules for a SPI slave device as specified in - spi/spi-controller.yaml - maintainers: - Paul Cercueil <paul@crapouillou.net> allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: diff --git a/dts/Bindings/display/panel/jdi,lt070me05000.yaml b/dts/Bindings/display/panel/jdi,lt070me05000.yaml index 4f92365e88..63c82a4378 100644 --- a/dts/Bindings/display/panel/jdi,lt070me05000.yaml +++ b/dts/Bindings/display/panel/jdi,lt070me05000.yaml @@ -35,6 +35,8 @@ properties: phandle of the gpio for power ic line Power IC supply enable, High active + port: true + required: - compatible - reg diff --git a/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml b/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml index c45c92a3d4..2a2756d196 100644 --- a/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml +++ b/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml @@ -6,15 +6,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: King Display KD035G6-54NT 3.5" (320x240 pixels) 24-bit TFT LCD panel -description: | - The panel must obey the rules for a SPI slave device as specified in - spi/spi-controller.yaml - maintainers: - Paul Cercueil <paul@crapouillou.net> allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: diff --git a/dts/Bindings/display/panel/lgphilips,lb035q02.yaml b/dts/Bindings/display/panel/lgphilips,lb035q02.yaml index 830e335ddb..5e4e0e552c 100644 --- a/dts/Bindings/display/panel/lgphilips,lb035q02.yaml +++ b/dts/Bindings/display/panel/lgphilips,lb035q02.yaml @@ -6,15 +6,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: LG.Philips LB035Q02 Panel -description: | - The panel must obey the rules for a SPI slave device as specified in - spi/spi-controller.yaml - maintainers: - Tomi Valkeinen <tomi.valkeinen@ti.com> allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: diff --git a/dts/Bindings/display/panel/novatek,nt35950.yaml b/dts/Bindings/display/panel/novatek,nt35950.yaml new file mode 100644 index 0000000000..377a05d48a --- /dev/null +++ b/dts/Bindings/display/panel/novatek,nt35950.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/novatek,nt35950.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek NT35950-based display panels + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> + +description: | + The nt35950 IC from Novatek is a Driver IC used to drive MIPI-DSI panels, + with Static RAM for content retention in command mode and also supports + video mode with VESA Frame Buffer Compression or Display Stream Compression + on single, or dual dsi port(s). + This DDIC is also capable of upscaling an input image to the panel's native + resolution, for example it can upscale a 1920x1080 input to 3840x2160 with + either bilinear interpolation or pixel duplication. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - sharp,ls055d1sx04 + - const: novatek,nt35950 + description: This indicates the panel manufacturer of the panel + that is in turn using the NT35950 panel driver. The compatible + string determines how the NT35950 panel driver shall be configured + to work with the indicated panel. The novatek,nt35950 compatible shall + always be provided as a fallback. + + reset-gpios: + maxItems: 1 + description: phandle of gpio for reset line - This should be 8mA, gpio + can be configured using mux, pinctrl, pinctrl-names (active high) + + avdd-supply: + description: positive boost supply regulator + avee-supply: + description: negative boost supply regulator + dvdd-supply: + description: regulator that supplies the digital voltage + vddio-supply: + description: regulator that supplies the I/O voltage + + backlight: true + ports: true + reg: true + +required: + - compatible + - reg + - reset-gpios + - avdd-supply + - avee-supply + - dvdd-supply + - vddio-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "sharp,ls055d1sx04", "novatek,nt35950"; + reg = <0>; + + backlight = <&pmi8998_wled>; + reset-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>; + + avdd-supply = <&lab>; + avee-supply = <&ibb>; + dvdd-supply = <&disp_dvdd_vreg>; + vddio-supply = <&vreg_l14a_1p85>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + panel_in1: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/panel/novatek,nt36672a.yaml b/dts/Bindings/display/panel/novatek,nt36672a.yaml index ef4c0a2451..563766d283 100644 --- a/dts/Bindings/display/panel/novatek,nt36672a.yaml +++ b/dts/Bindings/display/panel/novatek,nt36672a.yaml @@ -34,7 +34,7 @@ properties: description: phandle of gpio for reset line - This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names (active high) - vddio-supply: + vddi0-supply: description: phandle of the regulator that provides the supply voltage Power IC supply @@ -75,8 +75,6 @@ examples: reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; - #address-cells = <1>; - #size-cells = <0>; port { tianma_nt36672a_in_0: endpoint { remote-endpoint = <&dsi0_out>; diff --git a/dts/Bindings/display/panel/panel-simple-dsi.yaml b/dts/Bindings/display/panel/panel-simple-dsi.yaml index fbd7166924..2c00813f5d 100644 --- a/dts/Bindings/display/panel/panel-simple-dsi.yaml +++ b/dts/Bindings/display/panel/panel-simple-dsi.yaml @@ -35,6 +35,8 @@ properties: - boe,tv080wum-nl0 # Innolux P079ZCA 7.85" 768x1024 TFT LCD panel - innolux,p079zca + # JDI FHD_R63452 1080x1920 5.2" IPS LCD Panel + - jdi,fhd-r63452 # Khadas TS050 5" 1080x1920 LCD panel - khadas,ts050 # Kingdisplay KD097D04 9.7" 1536x2048 TFT LCD panel diff --git a/dts/Bindings/display/panel/panel-simple.yaml b/dts/Bindings/display/panel/panel-simple.yaml index f3c9395d23..62f5f050c1 100644 --- a/dts/Bindings/display/panel/panel-simple.yaml +++ b/dts/Bindings/display/panel/panel-simple.yaml @@ -290,6 +290,8 @@ properties: - starry,kr070pe2t # Starry 12.2" (1920x1200 pixels) TFT LCD panel - starry,kr122ea0sra + # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel + - team-source-display,tst043015cmhx # Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel - tianma,tm070jdhg30 # Tianma Micro-electronics TM070JVHG33 7.0" WXGA TFT LCD panel diff --git a/dts/Bindings/display/panel/samsung,ld9040.yaml b/dts/Bindings/display/panel/samsung,ld9040.yaml index 060ee27a47..d525165d6d 100644 --- a/dts/Bindings/display/panel/samsung,ld9040.yaml +++ b/dts/Bindings/display/panel/samsung,ld9040.yaml @@ -6,15 +6,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung LD9040 AMOLED LCD parallel RGB panel with SPI control bus -description: | - The panel must obey the rules for a SPI slave device as specified in - spi/spi-controller.yaml - maintainers: - Andrzej Hajda <a.hajda@samsung.com> allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: @@ -63,8 +60,6 @@ examples: lcd@0 { compatible = "samsung,ld9040"; - #address-cells = <1>; - #size-cells = <0>; reg = <0>; vdd3-supply = <&ldo7_reg>; diff --git a/dts/Bindings/display/panel/samsung,s6e63m0.yaml b/dts/Bindings/display/panel/samsung,s6e63m0.yaml index ea58df4926..940f7f8852 100644 --- a/dts/Bindings/display/panel/samsung,s6e63m0.yaml +++ b/dts/Bindings/display/panel/samsung,s6e63m0.yaml @@ -12,6 +12,7 @@ maintainers: allOf: - $ref: panel-common.yaml# - $ref: /schemas/leds/backlight/common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: diff --git a/dts/Bindings/display/panel/sitronix,st7789v.yaml b/dts/Bindings/display/panel/sitronix,st7789v.yaml index fa46d151e7..9e1d707c2a 100644 --- a/dts/Bindings/display/panel/sitronix,st7789v.yaml +++ b/dts/Bindings/display/panel/sitronix,st7789v.yaml @@ -6,15 +6,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Sitronix ST7789V RGB panel with SPI control bus -description: | - The panel must obey the rules for a SPI slave device as specified in - spi/spi-controller.yaml - maintainers: - Maxime Ripard <mripard@kernel.org> allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: diff --git a/dts/Bindings/display/panel/sony,acx565akm.yaml b/dts/Bindings/display/panel/sony,acx565akm.yaml index 95d053c548..98abdf4dde 100644 --- a/dts/Bindings/display/panel/sony,acx565akm.yaml +++ b/dts/Bindings/display/panel/sony,acx565akm.yaml @@ -6,15 +6,12 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Sony ACX565AKM SDI Panel -description: | - The panel must obey the rules for a SPI slave device as specified in - spi/spi-controller.yaml - maintainers: - Tomi Valkeinen <tomi.valkeinen@ti.com> allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: diff --git a/dts/Bindings/display/panel/sony,tulip-truly-nt35521.yaml b/dts/Bindings/display/panel/sony,tulip-truly-nt35521.yaml new file mode 100644 index 0000000000..9679729395 --- /dev/null +++ b/dts/Bindings/display/panel/sony,tulip-truly-nt35521.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sony,tulip-truly-nt35521.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony Tulip Truly NT35521 5.24" 1280x720 MIPI-DSI Panel + +maintainers: + - Shawn Guo <shawn.guo@linaro.org> + +description: | + The Sony Tulip Truly NT35521 is a 5.24" 1280x720 MIPI-DSI panel, which + can be found no Sony Xperia M4 phone. The panel backlight is managed + through DSI link. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: sony,tulip-truly-nt35521 + + reg: true + + positive5-supply: + description: Positive 5V supply + + negative5-supply: + description: Negative 5V supply + + reset-gpios: true + + enable-gpios: true + + port: true + +required: + - compatible + - reg + - positive5-supply + - negative5-supply + - reset-gpios + - enable-gpios + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "sony,tulip-truly-nt35521"; + reg = <0>; + positive5-supply = <&positive5_reg>; + negative5-supply = <&negative5_reg>; + reset-gpios = <&msmgpio 25 GPIO_ACTIVE_LOW>; + enable-gpios = <&msmgpio 10 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/panel/tpo,td.yaml b/dts/Bindings/display/panel/tpo,td.yaml index 4aa6056134..f902a9d741 100644 --- a/dts/Bindings/display/panel/tpo,td.yaml +++ b/dts/Bindings/display/panel/tpo,td.yaml @@ -6,16 +6,13 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Toppoly TD Panels -description: | - The panel must obey the rules for a SPI slave device as specified in - spi/spi-controller.yaml - maintainers: - Marek Belisko <marek@goldelico.com> - H. Nikolaus Schaller <hns@goldelico.com> allOf: - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: diff --git a/dts/Bindings/display/rockchip/rockchip,rk3066-hdmi.yaml b/dts/Bindings/display/rockchip/rockchip,rk3066-hdmi.yaml index 008c144257..1a68a940d1 100644 --- a/dts/Bindings/display/rockchip/rockchip,rk3066-hdmi.yaml +++ b/dts/Bindings/display/rockchip/rockchip,rk3066-hdmi.yaml @@ -26,14 +26,6 @@ properties: clock-names: const: hclk - pinctrl-0: - maxItems: 2 - - pinctrl-names: - const: default - description: - Switch the iomux for the HPD/I2C pins to HDMI function. - power-domains: maxItems: 1 diff --git a/dts/Bindings/display/simple-framebuffer.yaml b/dts/Bindings/display/simple-framebuffer.yaml index c2499a7906..44a29d813f 100644 --- a/dts/Bindings/display/simple-framebuffer.yaml +++ b/dts/Bindings/display/simple-framebuffer.yaml @@ -83,13 +83,25 @@ properties: format: description: > Format of the framebuffer: + * `a1r5g5b5` - 16-bit pixels, d[15]=a, d[14:10]=r, d[9:5]=g, d[4:0]=b + * `a2r10g10b10` - 32-bit pixels, d[31:30]=a, d[29:20]=r, d[19:10]=g, d[9:0]=b * `a8b8g8r8` - 32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r + * `a8r8g8b8` - 32-bit pixels, d[31:24]=a, d[23:16]=r, d[15:8]=g, d[7:0]=b * `r5g6b5` - 16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b + * `r5g5b5a1` - 16-bit pixels, d[15:11]=r, d[10:6]=g, d[5:1]=b d[1:0]=a + * `r8g8b8` - 24-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b + * `x1r5g5b5` - 16-bit pixels, d[14:10]=r, d[9:5]=g, d[4:0]=b * `x2r10g10b10` - 32-bit pixels, d[29:20]=r, d[19:10]=g, d[9:0]=b * `x8r8g8b8` - 32-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b enum: + - a1r5g5b5 + - a2r10g10b10 - a8b8g8r8 + - a8r8g8b8 - r5g6b5 + - r5g5b5a1 + - r8g8b8 + - x1r5g5b5 - x2r10g10b10 - x8r8g8b8 diff --git a/dts/Bindings/display/sprd/sprd,display-subsystem.yaml b/dts/Bindings/display/sprd/sprd,display-subsystem.yaml new file mode 100644 index 0000000000..3d107e9434 --- /dev/null +++ b/dts/Bindings/display/sprd/sprd,display-subsystem.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unisoc DRM master device + +maintainers: + - Kevin Tang <kevin.tang@unisoc.com> + +description: | + The Unisoc DRM master device is a virtual device needed to list all + DPU devices or other display interface nodes that comprise the + graphics subsystem. + + Unisoc's display pipeline have several components as below description, + multi display controllers and corresponding physical interfaces. + For different display scenarios, dpu0 and dpu1 maybe binding to different + encoder. + + E.g: + dpu0 and dpu1 both binding to DSI for dual mipi-dsi display; + dpu0 binding to DSI for primary display, and dpu1 binding to DP for external display; + + +-----------------------------------------+ + | | + | +---------+ | + +----+ | +----+ +---------+ |DPHY/CPHY| | +------+ + | +----->+dpu0+--->+MIPI|DSI +--->+Combo +----->+Panel0| + |AXI | | +----+ +---------+ +---------+ | +------+ + | | | ^ | + | | | | | + | | | +-----------+ | + | | | | | + |APB | | +--+-+ +-----------+ +---+ | +------+ + | +----->+dpu1+--->+DisplayPort+--->+PHY+--------->+Panel1| + | | | +----+ +-----------+ +---+ | +------+ + +----+ | | + +-----------------------------------------+ + +properties: + compatible: + const: sprd,display-subsystem + + ports: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should contain a list of phandles pointing to display interface port + of DPU devices. + +required: + - compatible + - ports + +additionalProperties: false + +examples: + - | + display-subsystem { + compatible = "sprd,display-subsystem"; + ports = <&dpu_out>; + }; + diff --git a/dts/Bindings/display/sprd/sprd,sharkl3-dpu.yaml b/dts/Bindings/display/sprd/sprd,sharkl3-dpu.yaml new file mode 100644 index 0000000000..4ebea60b8c --- /dev/null +++ b/dts/Bindings/display/sprd/sprd,sharkl3-dpu.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unisoc Sharkl3 Display Processor Unit (DPU) + +maintainers: + - Kevin Tang <kevin.tang@unisoc.com> + +description: | + DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs + which transfers the image data from a video memory buffer to an internal + LCD interface. + +properties: + compatible: + const: sprd,sharkl3-dpu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + + clock-names: + items: + - const: clk_src_128m + - const: clk_src_384m + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + port: + type: object + description: + A port node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + That port should be the output endpoint, usually output to + the associated DSI. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/sprd,sc9860-clk.h> + dpu: dpu@63000000 { + compatible = "sprd,sharkl3-dpu"; + reg = <0x63000000 0x1000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "clk_src_128m", "clk_src_384m"; + + clocks = <&pll CLK_TWPLL_128M>, + <&pll CLK_TWPLL_384M>; + + dpu_port: port { + dpu_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; diff --git a/dts/Bindings/display/sprd/sprd,sharkl3-dsi-host.yaml b/dts/Bindings/display/sprd/sprd,sharkl3-dsi-host.yaml new file mode 100644 index 0000000000..bc5594d186 --- /dev/null +++ b/dts/Bindings/display/sprd/sprd,sharkl3-dsi-host.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dsi-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unisoc MIPI DSI Controller + +maintainers: + - Kevin Tang <kevin.tang@unisoc.com> + +properties: + compatible: + const: sprd,sharkl3-dsi-host + + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + clocks: + minItems: 1 + + clock-names: + items: + - const: clk_src_96m + + power-domains: + maxItems: 1 + + ports: + type: object + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: + A port node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + That port should be the input endpoint, usually coming from + the associated DPU. + + required: + - "#address-cells" + - "#size-cells" + - port@0 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/sprd,sc9860-clk.h> + dsi: dsi@63100000 { + compatible = "sprd,sharkl3-dsi-host"; + reg = <0x63100000 0x1000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "clk_src_96m"; + clocks = <&pll CLK_TWPLL_96M>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&dpu_out>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/st,stm32-dsi.yaml b/dts/Bindings/display/st,stm32-dsi.yaml index ce1ef93cce..54f67cb510 100644 --- a/dts/Bindings/display/st,stm32-dsi.yaml +++ b/dts/Bindings/display/st,stm32-dsi.yaml @@ -110,7 +110,7 @@ examples: }; }; - panel-dsi@0 { + panel@0 { compatible = "orisetech,otm8009a"; reg = <0>; reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; @@ -125,4 +125,3 @@ examples: }; ... - diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt b/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt index 8a6d3e1ee3..e61999ce54 100644 --- a/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -19,6 +19,19 @@ Required properties: See ../reset/reset.txt for details. - reset-names: Must include the following entries: - host1x + - mc + +Optional properties: +- operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. + +For each opp entry in 'operating-points-v2' table of host1x and its modules: +- opp-supported-hw: One bitfield indicating: + On Tegra20: SoC process ID mask + On Tegra30+: SoC speedo ID mask + + A bitwise AND is performed against the value and if any bit + matches, the OPP gets enabled. Each host1x client module having to perform DMA through the Memory Controller should have the interconnect endpoints set to the Memory Client and External @@ -45,6 +58,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to MPE power domain. - vi: video input @@ -128,6 +143,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to VENC power domain. - epp: encoder pre-processor @@ -147,6 +164,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. - isp: image signal processor @@ -166,6 +185,7 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - power-domains: Phandle to VENC or core power domain. - gr2d: 2D graphics engine @@ -179,12 +199,15 @@ of the following host1x client modules: See ../reset/reset.txt for details. - reset-names: Must include the following entries: - 2d + - mc Optional properties: - interconnects: Must contain entry for the GR2D memory clients. - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. - gr3d: 3D graphics engine @@ -203,12 +226,16 @@ of the following host1x client modules: - reset-names: Must include the following entries: - 3d - 3d2 (Only required on SoCs with two 3D clocks) + - mc + - mc2 (Only required on SoCs with two 3D clocks) Optional properties: - interconnects: Must contain entry for the GR3D memory clients. - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandles to 3D or core power domain. - dc: display controller @@ -241,6 +268,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to core power domain. - hdmi: High Definition Multimedia Interface @@ -267,6 +296,7 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - operating-points-v2: See ../bindings/opp/opp.txt for details. - tvo: TV encoder output @@ -277,6 +307,10 @@ of the following host1x client modules: - clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. + Optional properties: + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to core power domain. + - dsi: display serial interface Required properties: @@ -305,6 +339,7 @@ of the following host1x client modules: - nvidia,panel: phandle of a display panel - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang up with in order to support up to 8 data lanes + - operating-points-v2: See ../bindings/opp/opp.txt for details. - sor: serial output resource @@ -408,6 +443,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_HOST1X>; resets = <&tegra_car 28>; reset-names = "host1x"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; #address-cells = <1>; #size-cells = <1>; @@ -421,6 +458,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; vi@54080000 { @@ -429,6 +468,7 @@ Example: interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + operating-points-v2 = <&dvfs_opp_table>; clocks = <&tegra_car TEGRA210_CLK_VI>; power-domains = <&pd_venc>; @@ -510,6 +550,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; isp { @@ -528,6 +570,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; gr3d { @@ -536,6 +580,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; dc@54200000 { @@ -547,6 +593,8 @@ Example: clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, <&mc TEGRA20_MC_DISPLAY0B &emc>, @@ -571,6 +619,8 @@ Example: clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, <&mc TEGRA20_MC_DISPLAY0BB &emc>, @@ -596,6 +646,7 @@ Example: resets = <&tegra_car 51>; reset-names = "hdmi"; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; tvo { @@ -604,6 +655,7 @@ Example: interrupts = <0 76 0x04>; clocks = <&tegra_car TEGRA20_CLK_TVO>; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; dsi { @@ -615,6 +667,7 @@ Example: resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; }; diff --git a/dts/Bindings/dma/arm,pl330.yaml b/dts/Bindings/dma/arm,pl330.yaml new file mode 100644 index 0000000000..decab185cf --- /dev/null +++ b/dts/Bindings/dma/arm,pl330.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/arm,pl330.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM PrimeCell PL330 DMA Controller + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: + The ARM PrimeCell PL330 DMA controller can move blocks of memory contents + between memory and peripherals or memory to memory. + +# We need a select here so we don't match all nodes with 'arm,primecell' +select: + properties: + compatible: + contains: + const: arm,pl330 + required: + - compatible + +allOf: + - $ref: dma-controller.yaml# + - $ref: /schemas/arm/primecell.yaml# + +properties: + compatible: + items: + - enum: + - arm,pl330 + - const: arm,primecell + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 32 + description: A single combined interrupt or an interrupt per event + + '#dma-cells': + const: 1 + description: Contains the DMA request number for the consumer + + arm,pl330-broken-no-flushp: + type: boolean + description: quirk for avoiding to execute DMAFLUSHP + + arm,pl330-periph-burst: + type: boolean + description: quirk for performing burst transfer only + + dma-coherent: true + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + items: + - const: dma + - const: dma-ocp + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + dma-controller@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = <99>; + #dma-cells = <1>; + }; +... diff --git a/dts/Bindings/dma/arm-pl08x.yaml b/dts/Bindings/dma/arm-pl08x.yaml index 3bd9eea543..9193b18fb7 100644 --- a/dts/Bindings/dma/arm-pl08x.yaml +++ b/dts/Bindings/dma/arm-pl08x.yaml @@ -10,6 +10,7 @@ maintainers: - Vinod Koul <vkoul@kernel.org> allOf: + - $ref: /schemas/arm/primecell.yaml# - $ref: "dma-controller.yaml#" # We need a select here so we don't match all nodes with 'arm,primecell' @@ -89,6 +90,9 @@ properties: - 64 description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits + resets: + maxItems: 1 + required: - reg - interrupts diff --git a/dts/Bindings/dma/arm-pl330.txt b/dts/Bindings/dma/arm-pl330.txt deleted file mode 100644 index 315e90122a..0000000000 --- a/dts/Bindings/dma/arm-pl330.txt +++ /dev/null @@ -1,49 +0,0 @@ -* ARM PrimeCell PL330 DMA Controller - -The ARM PrimeCell PL330 DMA controller can move blocks of memory contents -between memory and peripherals or memory to memory. - -Required properties: - - compatible: should include both "arm,pl330" and "arm,primecell". - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: interrupt number to the cpu. - -Optional properties: - - dma-coherent : Present if dma operations are coherent - - #dma-cells: must be <1>. used to represent the number of integer - cells in the dmas property of client device. - - dma-channels: contains the total number of DMA channels supported by the DMAC - - dma-requests: contains the total number of DMA requests supported by the DMAC - - arm,pl330-broken-no-flushp: quirk for avoiding to execute DMAFLUSHP - - arm,pl330-periph-burst: quirk for performing burst transfer only - - resets: contains an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: must contain at least "dma", and optional is "dma-ocp". - -Example: - - pdma0: pdma@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = <99>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - -Client drivers (device nodes requiring dma transfers from dev-to-mem or -mem-to-dev) should specify the DMA channel numbers and dma channel names -as shown below. - - [property name] = <[phandle of the dma controller] [dma request id]>; - [property name] = <[dma channel name]> - - where 'dma request id' is the dma request number which is connected - to the client controller. The 'property name' 'dmas' and 'dma-names' - as required by the generic dma device tree binding helpers. The dma - names correspond 1:1 with the dma request ids in the dmas property. - - Example: dmas = <&pdma0 12 - &pdma1 11>; - dma-names = "tx", "rx"; diff --git a/dts/Bindings/dma/dma-controller.yaml b/dts/Bindings/dma/dma-controller.yaml index 0043b91da9..6d3727267f 100644 --- a/dts/Bindings/dma/dma-controller.yaml +++ b/dts/Bindings/dma/dma-controller.yaml @@ -24,10 +24,10 @@ examples: dma: dma-controller@48000000 { compatible = "ti,omap-sdma"; reg = <0x48000000 0x1000>; - interrupts = <0 12 0x4 - 0 13 0x4 - 0 14 0x4 - 0 15 0x4>; + interrupts = <0 12 0x4>, + <0 13 0x4>, + <0 14 0x4>, + <0 15 0x4>; #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; diff --git a/dts/Bindings/dma/ingenic,dma.yaml b/dts/Bindings/dma/ingenic,dma.yaml index dc059d6fd0..3b0b3b919a 100644 --- a/dts/Bindings/dma/ingenic,dma.yaml +++ b/dts/Bindings/dma/ingenic,dma.yaml @@ -14,15 +14,23 @@ allOf: properties: compatible: - enum: - - ingenic,jz4740-dma - - ingenic,jz4725b-dma - - ingenic,jz4760-dma - - ingenic,jz4760b-dma - - ingenic,jz4770-dma - - ingenic,jz4780-dma - - ingenic,x1000-dma - - ingenic,x1830-dma + oneOf: + - enum: + - ingenic,jz4740-dma + - ingenic,jz4725b-dma + - ingenic,jz4760-dma + - ingenic,jz4760-bdma + - ingenic,jz4760-mdma + - ingenic,jz4760b-dma + - ingenic,jz4760b-bdma + - ingenic,jz4760b-mdma + - ingenic,jz4770-dma + - ingenic,jz4780-dma + - ingenic,x1000-dma + - ingenic,x1830-dma + - items: + - const: ingenic,jz4770-bdma + - const: ingenic,jz4760b-bdma reg: items: @@ -36,13 +44,19 @@ properties: maxItems: 1 "#dma-cells": - const: 2 + enum: [2, 3] description: > DMA clients must use the format described in dma.txt, giving a phandle - to the DMA controller plus the following 2 integer cells: - - - Request type: The DMA request type for transfers to/from the - device on the allocated channel, as defined in the SoC documentation. + to the DMA controller plus the following integer cells: + + - Request type: The DMA request type specifies the device endpoint that + will be the source or destination of the DMA transfer. + If "#dma-cells" is 2, the request type is a single cell, and the + direction will be unidirectional (either RX or TX but not both). + If "#dma-cells" is 3, the request type has two cells; the first + one corresponds to the host to device direction (TX), the second one + corresponds to the device to host direction (RX). The DMA channel is + then bidirectional. - Channel: If set to 0xffffffff, any available channel will be allocated for the client. Otherwise, the exact channel specified will be used. diff --git a/dts/Bindings/dma/renesas,rcar-dmac.yaml b/dts/Bindings/dma/renesas,rcar-dmac.yaml index d8142cbd13..7c6badf399 100644 --- a/dts/Bindings/dma/renesas,rcar-dmac.yaml +++ b/dts/Bindings/dma/renesas,rcar-dmac.yaml @@ -44,6 +44,10 @@ properties: - items: - const: renesas,dmac-r8a779a0 # R-Car V3U + - items: + - const: renesas,dmac-r8a779f0 # R-Car S4-8 + - const: renesas,rcar-gen4-dmac + reg: true interrupts: @@ -118,6 +122,7 @@ if: contains: enum: - renesas,dmac-r8a779a0 + - renesas,rcar-gen4-dmac then: properties: reg: diff --git a/dts/Bindings/dma/sifive,fu540-c000-pdma.yaml b/dts/Bindings/dma/sifive,fu540-c000-pdma.yaml index d32a71b975..75ad898c59 100644 --- a/dts/Bindings/dma/sifive,fu540-c000-pdma.yaml +++ b/dts/Bindings/dma/sifive,fu540-c000-pdma.yaml @@ -50,7 +50,7 @@ examples: dma@3000000 { compatible = "sifive,fu540-c000-pdma"; reg = <0x3000000 0x8000>; - interrupts = <23 24 25 26 27 28 29 30>; + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>; #dma-cells = <1>; }; diff --git a/dts/Bindings/dma/snps,dw-axi-dmac.yaml b/dts/Bindings/dma/snps,dw-axi-dmac.yaml index 79e241498e..4324a94b26 100644 --- a/dts/Bindings/dma/snps,dw-axi-dmac.yaml +++ b/dts/Bindings/dma/snps,dw-axi-dmac.yaml @@ -53,6 +53,9 @@ properties: minimum: 1 maximum: 8 + resets: + maxItems: 1 + snps,dma-masters: description: | Number of AXI masters supported by the hardware. diff --git a/dts/Bindings/dma/ti/k3-bcdma.yaml b/dts/Bindings/dma/ti/k3-bcdma.yaml index df29d59d13..08627d91e6 100644 --- a/dts/Bindings/dma/ti/k3-bcdma.yaml +++ b/dts/Bindings/dma/ti/k3-bcdma.yaml @@ -30,6 +30,7 @@ description: | allOf: - $ref: /schemas/dma/dma-controller.yaml# + - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# properties: compatible: diff --git a/dts/Bindings/dma/ti/k3-pktdma.yaml b/dts/Bindings/dma/ti/k3-pktdma.yaml index ea19d12a93..507d16d84a 100644 --- a/dts/Bindings/dma/ti/k3-pktdma.yaml +++ b/dts/Bindings/dma/ti/k3-pktdma.yaml @@ -25,6 +25,7 @@ description: | allOf: - $ref: /schemas/dma/dma-controller.yaml# + - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# properties: compatible: diff --git a/dts/Bindings/eeprom/at24.yaml b/dts/Bindings/eeprom/at24.yaml index 4c5396a974..6b61a8cf61 100644 --- a/dts/Bindings/eeprom/at24.yaml +++ b/dts/Bindings/eeprom/at24.yaml @@ -87,6 +87,10 @@ properties: - items: pattern: cs1024$ - items: + pattern: c1025$ + - items: + pattern: cs1025$ + - items: pattern: c2048$ - items: pattern: cs2048$ @@ -95,18 +99,21 @@ properties: # These are special cases that don't conform to the above pattern. # Each requires a standard at24 model as fallback. - items: - - const: nxp,se97b - - const: atmel,24c02 + - enum: + - rohm,br24g01 + - rohm,br24t01 + - const: atmel,24c01 - items: - - const: onnn,cat24c04 - - const: atmel,24c04 + - enum: + - nxp,se97b + - renesas,r1ex24002 + - const: atmel,24c02 - items: - - const: onnn,cat24c05 + - enum: + - onnn,cat24c04 + - onnn,cat24c05 - const: atmel,24c04 - items: - - const: renesas,r1ex24002 - - const: atmel,24c02 - - items: - const: renesas,r1ex24016 - const: atmel,24c16 - items: @@ -115,12 +122,6 @@ properties: - items: - const: renesas,r1ex24128 - const: atmel,24c128 - - items: - - const: rohm,br24g01 - - const: atmel,24c01 - - items: - - const: rohm,br24t01 - - const: atmel,24c01 label: description: Descriptive name of the EEPROM. diff --git a/dts/Bindings/extcon/extcon-usbc-cros-ec.yaml b/dts/Bindings/extcon/extcon-usbc-cros-ec.yaml index 20e1ccfc86..2d82b44268 100644 --- a/dts/Bindings/extcon/extcon-usbc-cros-ec.yaml +++ b/dts/Bindings/extcon/extcon-usbc-cros-ec.yaml @@ -8,7 +8,6 @@ title: ChromeOS EC USB Type-C cable and accessories detection maintainers: - Benson Leung <bleung@chromium.org> - - Enric Balletbo i Serra <enric.balletbo@collabora.com> description: | On ChromeOS systems with USB Type C ports, the ChromeOS Embedded Controller is diff --git a/dts/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/dts/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml index c435c9f369..9a785bbaaf 100644 --- a/dts/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml +++ b/dts/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml @@ -37,6 +37,20 @@ properties: should be named with the instance number of the NPE engine used for the crypto engine. + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + hss@[0-9]+$: + $ref: /schemas/net/intel,ixp4xx-hss.yaml# + type: object + description: Optional node for the High Speed Serial link (HSS), the + node should be named with the instance number of the NPE engine + used for the HSS. + required: - compatible - reg @@ -45,9 +59,30 @@ additionalProperties: false examples: - | + #include <dt-bindings/gpio/gpio.h> + npe: npe@c8006000 { compatible = "intel,ixp4xx-network-processing-engine"; reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + hss@0 { + compatible = "intel,ixp4xx-hss"; + reg = <0>; + intel,npe-handle = <&npe 0>; + intel,queue-chl-rxtrig = <&qmgr 12>; + intel,queue-chl-txready = <&qmgr 34>; + intel,queue-pkt-rx = <&qmgr 13>; + intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>; + intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>; + intel,queue-pkt-txdone = <&qmgr 22>; + cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>; + clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>; + }; crypto { compatible = "intel,ixp4xx-crypto"; diff --git a/dts/Bindings/firmware/nvidia,tegra186-bpmp.txt b/dts/Bindings/firmware/nvidia,tegra186-bpmp.txt deleted file mode 100644 index e44a13bc06..0000000000 --- a/dts/Bindings/firmware/nvidia,tegra186-bpmp.txt +++ /dev/null @@ -1,107 +0,0 @@ -NVIDIA Tegra Boot and Power Management Processor (BPMP) - -The BPMP is a specific processor in Tegra chip, which is designed for -booting process handling and offloading the power management, clock -management, and reset control tasks from the CPU. The binding document -defines the resources that would be used by the BPMP firmware driver, -which can create the interprocessor communication (IPC) between the CPU -and BPMP. - -Required properties: -- compatible - Array of strings - One of: - - "nvidia,tegra186-bpmp" -- mboxes : The phandle of mailbox controller and the mailbox specifier. -- shmem : List of the phandle of the TX and RX shared memory area that - the IPC between CPU and BPMP is based on. -- #clock-cells : Should be 1. -- #power-domain-cells : Should be 1. -- #reset-cells : Should be 1. - -This node is a mailbox consumer. See the following files for details of -the mailbox subsystem, and the specifiers implemented by the relevant -provider(s): - -- .../mailbox/mailbox.txt -- .../mailbox/nvidia,tegra186-hsp.txt - -This node is a clock, power domain, and reset provider. See the following -files for general documentation of those features, and the specifiers -implemented by this node: - -- .../clock/clock-bindings.txt -- <dt-bindings/clock/tegra186-clock.h> -- ../power/power-domain.yaml -- <dt-bindings/power/tegra186-powergate.h> -- .../reset/reset.txt -- <dt-bindings/reset/tegra186-reset.h> - -The BPMP implements some services which must be represented by separate nodes. -For example, it can provide access to certain I2C controllers, and the I2C -bindings represent each I2C controller as a device tree node. Such nodes should -be nested directly inside the main BPMP node. - -Software can determine whether a child node of the BPMP node represents a device -by checking for a compatible property. Any node with a compatible property -represents a device that can be instantiated. Nodes without a compatible -property may be used to provide configuration information regarding the BPMP -itself, although no such configuration nodes are currently defined by this -binding. - -The BPMP firmware defines no single global name-/numbering-space for such -services. Put another way, the numbering scheme for I2C buses is distinct from -the numbering scheme for any other service the BPMP may provide (e.g. a future -hypothetical SPI bus service). As such, child device nodes will have no reg -property, and the BPMP node will have no #address-cells or #size-cells property. - -The shared memory bindings for BPMP ------------------------------------ - -The shared memory area for the IPC TX and RX between CPU and BPMP are -predefined and work on top of sysram, which is an SRAM inside the chip. - -See ".../sram/sram.txt" for the bindings. - -Example: - -hsp_top0: hsp@3c00000 { - ... - #mbox-cells = <2>; -}; - -sysram@30000000 { - compatible = "nvidia,tegra186-sysram", "mmio-sram"; - reg = <0x0 0x30000000 0x0 0x50000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; - - cpu_bpmp_tx: shmem@4e000 { - compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4e000 0x0 0x1000>; - label = "cpu-bpmp-tx"; - pool; - }; - - cpu_bpmp_rx: shmem@4f000 { - compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4f000 0x0 0x1000>; - label = "cpu-bpmp-rx"; - pool; - }; -}; - -bpmp { - compatible = "nvidia,tegra186-bpmp"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - - i2c { - compatible = "..."; - ... - }; -}; diff --git a/dts/Bindings/firmware/nvidia,tegra186-bpmp.yaml b/dts/Bindings/firmware/nvidia,tegra186-bpmp.yaml new file mode 100644 index 0000000000..833c07f168 --- /dev/null +++ b/dts/Bindings/firmware/nvidia,tegra186-bpmp.yaml @@ -0,0 +1,186 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Boot and Power Management Processor (BPMP) + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: | + The BPMP is a specific processor in Tegra chip, which is designed for + booting process handling and offloading the power management, clock + management, and reset control tasks from the CPU. The binding document + defines the resources that would be used by the BPMP firmware driver, + which can create the interprocessor communication (IPC) between the + CPU and BPMP. + + This node is a mailbox consumer. See the following files for details + of the mailbox subsystem, and the specifiers implemented by the + relevant provider(s): + + - .../mailbox/mailbox.txt + - .../mailbox/nvidia,tegra186-hsp.yaml + + This node is a clock, power domain, and reset provider. See the + following files for general documentation of those features, and the + specifiers implemented by this node: + + - .../clock/clock-bindings.txt + - <dt-bindings/clock/tegra186-clock.h> + - ../power/power-domain.yaml + - <dt-bindings/power/tegra186-powergate.h> + - .../reset/reset.txt + - <dt-bindings/reset/tegra186-reset.h> + + The BPMP implements some services which must be represented by + separate nodes. For example, it can provide access to certain I2C + controllers, and the I2C bindings represent each I2C controller as a + device tree node. Such nodes should be nested directly inside the main + BPMP node. + + Software can determine whether a child node of the BPMP node + represents a device by checking for a compatible property. Any node + with a compatible property represents a device that can be + instantiated. Nodes without a compatible property may be used to + provide configuration information regarding the BPMP itself, although + no such configuration nodes are currently defined by this binding. + + The BPMP firmware defines no single global name-/numbering-space for + such services. Put another way, the numbering scheme for I2C buses is + distinct from the numbering scheme for any other service the BPMP may + provide (e.g. a future hypothetical SPI bus service). As such, child + device nodes will have no reg property, and the BPMP node will have no + "#address-cells" or "#size-cells" property. + + The shared memory area for the IPC TX and RX between CPU and BPMP are + predefined and work on top of sysram, which is an SRAM inside the + chip. See ".../sram/sram.yaml" for the bindings. + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra194-bpmp + - nvidia,tegra234-bpmp + - const: nvidia,tegra186-bpmp + - const: nvidia,tegra186-bpmp + + mboxes: + description: A phandle and channel specifier for the mailbox used to + communicate with the BPMP. + maxItems: 1 + + shmem: + description: List of the phandle to the TX and RX shared memory area + that the IPC between CPU and BPMP is based on. + minItems: 2 + maxItems: 2 + + "#clock-cells": + const: 1 + + "#power-domain-cells": + const: 1 + + "#reset-cells": + const: 1 + + interconnects: + items: + - description: memory read client + - description: memory write client + - description: DMA read client + - description: DMA write client + + interconnect-names: + items: + - const: read + - const: write + - const: dma-mem # dma-read + - const: dma-write + + iommus: + maxItems: 1 + + i2c: + type: object + + thermal: + type: object + +additionalProperties: false + +required: + - compatible + - mboxes + - shmem + - "#clock-cells" + - "#power-domain-cells" + - "#reset-cells" + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/mailbox/tegra186-hsp.h> + #include <dt-bindings/memory/tegra186-mc.h> + + hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x03c00000 0xa0000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "doorbell"; + #mbox-cells = <2>; + }; + + sram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-sram"; + reg = <0x30000000 0x50000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000000 0x50000>; + + cpu_bpmp_tx: sram@4e000 { + reg = <0x4e000 0x1000>; + label = "cpu-bpmp-tx"; + pool; + }; + + cpu_bpmp_rx: sram@4f000 { + reg = <0x4f000 0x1000>; + label = "cpu-bpmp-rx"; + pool; + }; + }; + + bpmp { + compatible = "nvidia,tegra186-bpmp"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names = "read", "write", "dma-mem", "dma-write"; + iommus = <&smmu TEGRA186_SID_BPMP>; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB + TEGRA_HSP_DB_MASTER_BPMP>; + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + + i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + nvidia,bpmp-bus-id = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + thermal { + compatible = "nvidia,tegra186-bpmp-thermal"; + #thermal-sensor-cells = <1>; + }; + }; diff --git a/dts/Bindings/firmware/qcom,scm.txt b/dts/Bindings/firmware/qcom,scm.txt index d7e3cda892..b1cd4ad188 100644 --- a/dts/Bindings/firmware/qcom,scm.txt +++ b/dts/Bindings/firmware/qcom,scm.txt @@ -26,9 +26,11 @@ Required properties: * "qcom,scm-sc7280" * "qcom,scm-sdm845" * "qcom,scm-sdx55" + * "qcom,scm-sm6350" * "qcom,scm-sm8150" * "qcom,scm-sm8250" * "qcom,scm-sm8350" + * "qcom,scm-sm8450" and: * "qcom,scm" - clocks: Specifies clocks needed by the SCM interface, if any: diff --git a/dts/Bindings/fuse/nvidia,tegra20-fuse.txt b/dts/Bindings/fuse/nvidia,tegra20-fuse.txt deleted file mode 100644 index b109911669..0000000000 --- a/dts/Bindings/fuse/nvidia,tegra20-fuse.txt +++ /dev/null @@ -1,42 +0,0 @@ -NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block. - -Required properties: -- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30, - must contain "nvidia,tegra30-efuse". For Tegra114, must contain - "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse". - For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse". - For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain - "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse". - For Tegra234 must contain "nvidia,tegra234-efuse". - Details: - nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data - due to a hardware bug. Tegra20 also lacks certain information which is - available in later generations such as fab code, lot code, wafer id,.. - nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse: - The differences between these SoCs are the size of the efuse array, - the location of the spare (OEM programmable) bits and the location of - the speedo data. -- reg: Should contain 1 entry: the entry gives the physical address and length - of the fuse registers. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - fuse -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - fuse - -Example: - - fuse@7000f800 { - compatible = "nvidia,tegra20-efuse"; - reg = <0x7000f800 0x400>, - <0x70000000 0x400>; - clocks = <&tegra_car TEGRA20_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - diff --git a/dts/Bindings/fuse/nvidia,tegra20-fuse.yaml b/dts/Bindings/fuse/nvidia,tegra20-fuse.yaml new file mode 100644 index 0000000000..4819012698 --- /dev/null +++ b/dts/Bindings/fuse/nvidia,tegra20-fuse.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fuse/nvidia,tegra20-fuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra FUSE block + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-efuse + - nvidia,tegra30-efuse + - nvidia,tegra114-efuse + - nvidia,tegra124-efuse + - nvidia,tegra210-efuse + - nvidia,tegra186-efuse + - nvidia,tegra194-efuse + - nvidia,tegra234-efuse + + - items: + - const: nvidia,tegra132-efuse + - const: nvidia,tegra124-efuse + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: fuse + + resets: + maxItems: 1 + + reset-names: + items: + - const: fuse + + operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the core power domain + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + +if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-efuse + - nvidia,tegra30-efuse + - nvidia,tegra114-efuse + - nvidia,tegra124-efuse + - nvidia,tegra132-efuse + - nvidia,tegra210-efuse +then: + required: + - resets + - reset-names + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + + fuse@7000f800 { + compatible = "nvidia,tegra20-efuse"; + reg = <0x7000f800 0x400>; + clocks = <&tegra_car TEGRA20_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; diff --git a/dts/Bindings/gpio/brcm,brcmstb-gpio.txt b/dts/Bindings/gpio/brcm,brcmstb-gpio.txt deleted file mode 100644 index 5d468ecd18..0000000000 --- a/dts/Bindings/gpio/brcm,brcmstb-gpio.txt +++ /dev/null @@ -1,83 +0,0 @@ -Broadcom STB "UPG GIO" GPIO controller - -The controller's registers are organized as sets of eight 32-bit -registers with each set controlling a bank of up to 32 pins. A single -interrupt is shared for all of the banks handled by the controller. - -Required properties: - -- compatible: - Must be "brcm,brcmstb-gpio" - -- reg: - Define the base and range of the I/O address space containing - the brcmstb GPIO controller registers - -- #gpio-cells: - Should be <2>. The first cell is the pin number (within the controller's - pin space), and the second is used for the following: - bit[0]: polarity (0 for active-high, 1 for active-low) - -- gpio-controller: - Specifies that the node is a GPIO controller. - -- brcm,gpio-bank-widths: - Number of GPIO lines for each bank. Number of elements must - correspond to number of banks suggested by the 'reg' property. - -Optional properties: - -- interrupts: - The interrupt shared by all GPIO lines for this controller. - -- interrupts-extended: - Alternate form of specifying interrupts and parents that allows for - multiple parents. This takes precedence over 'interrupts' and - 'interrupt-parent'. Wakeup-capable GPIO controllers often route their - wakeup interrupt lines through a different interrupt controller than the - primary interrupt line, making this property necessary. - -- #interrupt-cells: - Should be <2>. The first cell is the GPIO number, the second should specify - flags. The following subset of flags is supported: - - bits[3:0] trigger type and level flags - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered - 4 = active high level-sensitive - 8 = active low level-sensitive - Valid combinations are 1, 2, 3, 4, 8. - See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - -- interrupt-controller: - Marks the device node as an interrupt controller - -- wakeup-source: - GPIOs for this controller can be used as a wakeup source - -Example: - upg_gio: gpio@f040a700 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; - gpio-controller; - interrupt-controller; - reg = <0xf040a700 0x80>; - interrupt-parent = <&irq0_intc>; - interrupts = <0x6>; - brcm,gpio-bank-widths = <32 32 32 24>; - }; - - upg_gio_aon: gpio@f04172c0 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; - gpio-controller; - interrupt-controller; - reg = <0xf04172c0 0x40>; - interrupt-parent = <&irq0_aon_intc>; - interrupts = <0x6>; - interrupts-extended = <&irq0_aon_intc 0x6>, - <&aon_pm_l2_intc 0x5>; - wakeup-source; - brcm,gpio-bank-widths = <18 4>; - }; diff --git a/dts/Bindings/gpio/brcm,brcmstb-gpio.yaml b/dts/Bindings/gpio/brcm,brcmstb-gpio.yaml new file mode 100644 index 0000000000..4a896ff7ed --- /dev/null +++ b/dts/Bindings/gpio/brcm,brcmstb-gpio.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom STB "UPG GIO" GPIO controller + +description: > + The controller's registers are organized as sets of eight 32-bit + registers with each set controlling a bank of up to 32 pins. A single + interrupt is shared for all of the banks handled by the controller. + +maintainers: + - Doug Berger <opendmb@gmail.com> + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + compatible: + items: + - enum: + - brcm,bcm7445-gpio + - const: brcm,brcmstb-gpio + + reg: + maxItems: 1 + description: > + Define the base and range of the I/O address space containing + the brcmstb GPIO controller registers + + "#gpio-cells": + const: 2 + description: > + The first cell is the pin number (within the controller's + pin space), and the second is used for the following: + bit[0]: polarity (0 for active-high, 1 for active-low) + + gpio-controller: true + + brcm,gpio-bank-widths: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: > + Number of GPIO lines for each bank. Number of elements must + correspond to number of banks suggested by the 'reg' property. + + interrupts: + maxItems: 1 + description: > + The interrupt shared by all GPIO lines for this controller. + + "#interrupt-cells": + const: 2 + description: | + The first cell is the GPIO number, the second should specify + flags. The following subset of flags is supported: + - bits[3:0] trigger type and level flags + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered + 4 = active high level-sensitive + 8 = active low level-sensitive + Valid combinations are 1, 2, 3, 4, 8. + + interrupt-controller: true + + wakeup-source: + type: boolean + description: > + GPIOs for this controller can be used as a wakeup source + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - "brcm,gpio-bank-widths" + +additionalProperties: false + +examples: + - | + upg_gio: gpio@f040a700 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + gpio-controller; + interrupt-controller; + reg = <0xf040a700 0x80>; + interrupt-parent = <&irq0_intc>; + interrupts = <0x6>; + brcm,gpio-bank-widths = <32 32 32 24>; + }; + + upg_gio_aon: gpio@f04172c0 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + gpio-controller; + interrupt-controller; + reg = <0xf04172c0 0x40>; + interrupt-parent = <&irq0_aon_intc>; + interrupts = <0x6>; + wakeup-source; + brcm,gpio-bank-widths = <18 4>; + }; diff --git a/dts/Bindings/gpio/gpio-samsung.txt b/dts/Bindings/gpio/gpio-samsung.txt deleted file mode 100644 index 5375625e8c..0000000000 --- a/dts/Bindings/gpio/gpio-samsung.txt +++ /dev/null @@ -1,41 +0,0 @@ -Samsung Exynos4 GPIO Controller - -Required properties: -- compatible: Compatible property value should be "samsung,exynos4-gpio>". - -- reg: Physical base address of the controller and length of memory mapped - region. - -- #gpio-cells: Should be 4. The syntax of the gpio specifier used by client nodes - should be the following with values derived from the SoC user manual. - <[phandle of the gpio controller node] - [pin number within the gpio controller] - [mux function] - [flags and pull up/down] - [drive strength]> - - Values for gpio specifier: - - Pin number: is a value between 0 to 7. - - Flags and Pull Up/Down: 0 - Pull Up/Down Disabled. - 1 - Pull Down Enabled. - 3 - Pull Up Enabled. - Bit 16 (0x00010000) - Input is active low. - - Drive Strength: 0 - 1x, - 1 - 3x, - 2 - 2x, - 3 - 4x - -- gpio-controller: Specifies that the node is a gpio controller. -- #address-cells: should be 1. -- #size-cells: should be 1. - -Example: - - gpa0: gpio-controller@11400000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "samsung,exynos4-gpio"; - reg = <0x11400000 0x20>; - #gpio-cells = <4>; - gpio-controller; - }; diff --git a/dts/Bindings/gpio/gpio-vf610.yaml b/dts/Bindings/gpio/gpio-vf610.yaml index 19738a457a..e1359391d3 100644 --- a/dts/Bindings/gpio/gpio-vf610.yaml +++ b/dts/Bindings/gpio/gpio-vf610.yaml @@ -24,6 +24,9 @@ properties: - items: - const: fsl,imx7ulp-gpio - const: fsl,vf610-gpio + - items: + - const: fsl,imx8ulp-gpio + - const: fsl,imx7ulp-gpio reg: description: The first reg tuple represents the PORT module, the second tuple diff --git a/dts/Bindings/gpio/mstar,msc313-gpio.yaml b/dts/Bindings/gpio/mstar,msc313-gpio.yaml index fe1e1c63ff..18fe90387b 100644 --- a/dts/Bindings/gpio/mstar,msc313-gpio.yaml +++ b/dts/Bindings/gpio/mstar,msc313-gpio.yaml @@ -14,7 +14,9 @@ properties: pattern: "^gpio@[0-9a-f]+$" compatible: - const: mstar,msc313-gpio + enum: + - mstar,msc313-gpio + - sstar,ssd20xd-gpio reg: maxItems: 1 diff --git a/dts/Bindings/gpio/nvidia,tegra186-gpio.txt b/dts/Bindings/gpio/nvidia,tegra186-gpio.txt deleted file mode 100644 index adff16c71d..0000000000 --- a/dts/Bindings/gpio/nvidia,tegra186-gpio.txt +++ /dev/null @@ -1,165 +0,0 @@ -NVIDIA Tegra186 GPIO controllers - -Tegra186 contains two GPIO controllers; a main controller and an "AON" -controller. This binding document applies to both controllers. The register -layouts for the controllers share many similarities, but also some significant -differences. Hence, this document describes closely related but different -bindings and compatible values. - -The Tegra186 GPIO controller allows software to set the IO direction of, and -read/write the value of, numerous GPIO signals. Routing of GPIO signals to -package balls is under the control of a separate pin controller HW block. Two -major sets of registers exist: - -a) Security registers, which allow configuration of allowed access to the GPIO -register set. These registers exist in a single contiguous block of physical -address space. The size of this block, and the security features available, -varies between the different GPIO controllers. - -Access to this set of registers is not necessary in all circumstances. Code -that wishes to configure access to the GPIO registers needs access to these -registers to do so. Code which simply wishes to read or write GPIO data does not -need access to these registers. - -b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO -controllers, these registers are exposed via multiple "physical aliases" in -address space, each of which access the same underlying state. See the hardware -documentation for rationale. Any particular GPIO client is expected to access -just one of these physical aliases. - -Tegra HW documentation describes a unified naming convention for all GPIOs -implemented by the SoC. Each GPIO is assigned to a port, and a port may control -a number of GPIOs. Thus, each GPIO is named according to an alphabetical port -name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6, -or GPIO_PCC3. - -The number of ports implemented by each GPIO controller varies. The number of -implemented GPIOs within each port varies. GPIO registers within a controller -are grouped and laid out according to the port they affect. - -The mapping from port name to the GPIO controller that implements that port, and -the mapping from port name to register offset within a controller, are both -extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h> -describes the port-level mapping. In that file, the naming convention for ports -matches the HW documentation. The values chosen for the names are alphabetically -sorted within a particular controller. Drivers need to map between the DT GPIO -IDs and HW register offsets using a lookup table. - -Each GPIO controller can generate a number of interrupt signals. Each signal -represents the aggregate status for all GPIOs within a set of ports. Thus, the -number of interrupt signals generated by a controller varies as a rough function -of the number of ports it implements. Note that the HW documentation refers to -both the overall controller HW module and the sets-of-ports as "controllers". - -Each GPIO controller in fact generates multiple interrupts signals for each set -of ports. Each GPIO may be configured to feed into a specific one of the -interrupt signals generated by a set-of-ports. The intent is for each generated -signal to be routed to a different CPU, thus allowing different CPUs to each -handle subsets of the interrupts within a port. The status of each of these -per-port-set signals is reported via a separate register. Thus, a driver needs -to know which status register to observe. This binding currently defines no -configuration mechanism for this. By default, drivers should use register -GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could -define a property to configure this. - -Required properties: -- compatible - Array of strings. - One of: - - "nvidia,tegra186-gpio". - - "nvidia,tegra186-gpio-aon". - - "nvidia,tegra194-gpio". - - "nvidia,tegra194-gpio-aon". -- reg-names - Array of strings. - Contains a list of names for the register spaces described by the reg - property. May contain the following entries, in any order: - - "gpio": Mandatory. GPIO control registers. This may cover either: - a) The single physical alias that this OS should use. - b) All physical aliases that exist in the controller. This is - appropriate when the OS is responsible for managing assignment of - the physical aliases. - - "security": Optional. Security configuration registers. - Users of this binding MUST look up entries in the reg property by name, - using this reg-names property to do so. -- reg - Array of (physical base address, length) tuples. - Must contain one entry per entry in the reg-names property, in a matching - order. -- interrupts - Array of interrupt specifiers. - The interrupt outputs from the HW block, one per set of ports, in the - order the HW manual describes them. The number of entries required varies - depending on compatible value: - - "nvidia,tegra186-gpio": 6 entries. - - "nvidia,tegra186-gpio-aon": 1 entry. - - "nvidia,tegra194-gpio": 6 entries. - - "nvidia,tegra194-gpio-aon": 1 entry. -- gpio-controller - Boolean. - Marks the device node as a GPIO controller/provider. -- #gpio-cells - Single-cell integer. - Must be <2>. - Indicates how many cells are used in a consumer's GPIO specifier. - In the specifier: - - The first cell is the pin number. - See <dt-bindings/gpio/tegra186-gpio.h>. - - The second cell contains flags: - - Bit 0 specifies polarity - - 0: Active-high (normal). - - 1: Active-low (inverted). -- interrupt-controller - Boolean. - Marks the device node as an interrupt controller/provider. -- #interrupt-cells - Single-cell integer. - Must be <2>. - Indicates how many cells are used in a consumer's interrupt specifier. - In the specifier: - - The first cell is the GPIO number. - See <dt-bindings/gpio/tegra186-gpio.h>. - - The second cell is contains flags: - - Bits [3:0] indicate trigger type and level: - - 1: Low-to-high edge triggered. - - 2: High-to-low edge triggered. - - 4: Active high level-sensitive. - - 8: Active low level-sensitive. - Valid combinations are 1, 2, 3, 4, 8. - -Example: - -#include <dt-bindings/interrupt-controller/irq.h> - -gpio@2200000 { - compatible = "nvidia,tegra186-gpio"; - reg-names = "security", "gpio"; - reg = - <0x0 0x2200000 0x0 0x10000>, - <0x0 0x2210000 0x0 0x10000>; - interrupts = - <0 47 IRQ_TYPE_LEVEL_HIGH>, - <0 50 IRQ_TYPE_LEVEL_HIGH>, - <0 53 IRQ_TYPE_LEVEL_HIGH>, - <0 56 IRQ_TYPE_LEVEL_HIGH>, - <0 59 IRQ_TYPE_LEVEL_HIGH>, - <0 180 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; - -gpio@c2f0000 { - compatible = "nvidia,tegra186-gpio-aon"; - reg-names = "security", "gpio"; - reg = - <0x0 0xc2f0000 0x0 0x1000>, - <0x0 0xc2f1000 0x0 0x1000>; - interrupts = - <0 60 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; diff --git a/dts/Bindings/gpio/nvidia,tegra186-gpio.yaml b/dts/Bindings/gpio/nvidia,tegra186-gpio.yaml new file mode 100644 index 0000000000..4ef06b2ff1 --- /dev/null +++ b/dts/Bindings/gpio/nvidia,tegra186-gpio.yaml @@ -0,0 +1,214 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra GPIO Controller (Tegra186 and later) + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: | + Tegra186 contains two GPIO controllers; a main controller and an "AON" + controller. This binding document applies to both controllers. The register + layouts for the controllers share many similarities, but also some + significant differences. Hence, this document describes closely related but + different bindings and compatible values. + + The Tegra186 GPIO controller allows software to set the IO direction of, + and read/write the value of, numerous GPIO signals. Routing of GPIO signals + to package balls is under the control of a separate pin controller hardware + block. Two major sets of registers exist: + + a) Security registers, which allow configuration of allowed access to the + GPIO register set. These registers exist in a single contiguous block + of physical address space. The size of this block, and the security + features available, varies between the different GPIO controllers. + + Access to this set of registers is not necessary in all circumstances. + Code that wishes to configure access to the GPIO registers needs access + to these registers to do so. Code which simply wishes to read or write + GPIO data does not need access to these registers. + + b) GPIO registers, which allow manipulation of the GPIO signals. In some + GPIO controllers, these registers are exposed via multiple "physical + aliases" in address space, each of which access the same underlying + state. See the hardware documentation for rationale. Any particular + GPIO client is expected to access just one of these physical aliases. + + Tegra HW documentation describes a unified naming convention for all GPIOs + implemented by the SoC. Each GPIO is assigned to a port, and a port may + control a number of GPIOs. Thus, each GPIO is named according to an + alphabetical port name and an integer GPIO name within the port. For + example, GPIO_PA0, GPIO_PN6, or GPIO_PCC3. + + The number of ports implemented by each GPIO controller varies. The number + of implemented GPIOs within each port varies. GPIO registers within a + controller are grouped and laid out according to the port they affect. + + The mapping from port name to the GPIO controller that implements that + port, and the mapping from port name to register offset within a + controller, are both extremely non-linear. The header file + <dt-bindings/gpio/tegra186-gpio.h> describes the port-level mapping. In + that file, the naming convention for ports matches the HW documentation. + The values chosen for the names are alphabetically sorted within a + particular controller. Drivers need to map between the DT GPIO IDs and HW + register offsets using a lookup table. + + Each GPIO controller can generate a number of interrupt signals. Each + signal represents the aggregate status for all GPIOs within a set of + ports. Thus, the number of interrupt signals generated by a controller + varies as a rough function of the number of ports it implements. Note + that the HW documentation refers to both the overall controller HW + module and the sets-of-ports as "controllers". + + Each GPIO controller in fact generates multiple interrupts signals for + each set of ports. Each GPIO may be configured to feed into a specific + one of the interrupt signals generated by a set-of-ports. The intent is + for each generated signal to be routed to a different CPU, thus allowing + different CPUs to each handle subsets of the interrupts within a port. + The status of each of these per-port-set signals is reported via a + separate register. Thus, a driver needs to know which status register to + observe. This binding currently defines no configuration mechanism for + this. By default, drivers should use register + GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could + define a property to configure this. + +properties: + compatible: + enum: + - nvidia,tegra186-gpio + - nvidia,tegra186-gpio-aon + - nvidia,tegra194-gpio + - nvidia,tegra194-gpio-aon + - nvidia,tegra234-gpio + - nvidia,tegra234-gpio-aon + + reg-names: + items: + - const: security + - const: gpio + minItems: 1 + + reg: + items: + - description: Security configuration registers. + - description: | + GPIO control registers. This may cover either: + + a) The single physical alias that this OS should use. + b) All physical aliases that exist in the controller. This is + appropriate when the OS is responsible for managing assignment + of the physical aliases. + minItems: 1 + + interrupts: + description: The interrupt outputs from the HW block, one per set of + ports, in the order the HW manual describes them. The number of entries + required varies depending on compatible value. + + gpio-controller: true + + "#gpio-cells": + description: | + Indicates how many cells are used in a consumer's GPIO specifier. In the + specifier: + + - The first cell is the pin number. + See <dt-bindings/gpio/tegra186-gpio.h>. + - The second cell contains flags: + - Bit 0 specifies polarity + - 0: Active-high (normal). + - 1: Active-low (inverted). + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + description: | + Indicates how many cells are used in a consumer's interrupt specifier. + In the specifier: + + - The first cell is the GPIO number. + See <dt-bindings/gpio/tegra186-gpio.h>. + - The second cell is contains flags: + - Bits [3:0] indicate trigger type and level: + - 1: Low-to-high edge triggered. + - 2: High-to-low edge triggered. + - 4: Active high level-sensitive. + - 8: Active low level-sensitive. + + Valid combinations are 1, 2, 3, 4, 8. + const: 2 + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-gpio + - nvidia,tegra194-gpio + - nvidia,tegra234-gpio + then: + properties: + interrupts: + minItems: 6 + maxItems: 48 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-gpio-aon + - nvidia,tegra194-gpio-aon + - nvidia,tegra234-gpio-aon + then: + properties: + interrupts: + minItems: 1 + maxItems: 4 + +required: + - compatible + - reg + - reg-names + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + gpio@2200000 { + compatible = "nvidia,tegra186-gpio"; + reg-names = "security", "gpio"; + reg = <0x2200000 0x10000>, + <0x2210000 0x10000>; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>, + <0 50 IRQ_TYPE_LEVEL_HIGH>, + <0 53 IRQ_TYPE_LEVEL_HIGH>, + <0 56 IRQ_TYPE_LEVEL_HIGH>, + <0 59 IRQ_TYPE_LEVEL_HIGH>, + <0 180 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio@c2f0000 { + compatible = "nvidia,tegra186-gpio-aon"; + reg-names = "security", "gpio"; + reg = <0xc2f0000 0x1000>, + <0xc2f1000 0x1000>; + interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/dts/Bindings/gpio/nvidia,tegra20-gpio.txt b/dts/Bindings/gpio/nvidia,tegra20-gpio.txt deleted file mode 100644 index 023c9526e5..0000000000 --- a/dts/Bindings/gpio/nvidia,tegra20-gpio.txt +++ /dev/null @@ -1,40 +0,0 @@ -NVIDIA Tegra GPIO controller - -Required properties: -- compatible : "nvidia,tegra<chip>-gpio" -- reg : Physical base address and length of the controller's registers. -- interrupts : The interrupt outputs from the controller. For Tegra20, - there should be 7 interrupts specified, and for Tegra30, there should - be 8 interrupts specified. -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted) -- gpio-controller : Marks the device node as a GPIO controller. -- #interrupt-cells : Should be 2. - The first cell is the GPIO number. - The second cell is used to specify flags: - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - Valid combinations are 1, 2, 3, 4, 8. -- interrupt-controller : Marks the device node as an interrupt controller. - -Example: - -gpio: gpio@6000d000 { - compatible = "nvidia,tegra20-gpio"; - reg = < 0x6000d000 0x1000 >; - interrupts = < 0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04 >; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; -}; diff --git a/dts/Bindings/gpio/nvidia,tegra20-gpio.yaml b/dts/Bindings/gpio/nvidia,tegra20-gpio.yaml new file mode 100644 index 0000000000..94b51749ee --- /dev/null +++ b/dts/Bindings/gpio/nvidia,tegra20-gpio.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210) + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-gpio + - nvidia,tegra30-gpio + + - items: + - enum: + - nvidia,tegra114-gpio + - nvidia,tegra124-gpio + - nvidia,tegra210-gpio + - const: nvidia,tegra30-gpio + + reg: + maxItems: 1 + + interrupts: + description: The interrupt outputs from the controller. For Tegra20, + there should be 7 interrupts specified, and for Tegra30, there should + be 8 interrupts specified. + + "#gpio-cells": + description: The first cell is the pin number and the second cell is used + to specify the GPIO polarity (0 = active high, 1 = active low). + const: 2 + + gpio-controller: true + + gpio-ranges: + maxItems: 1 + + "#interrupt-cells": + description: | + Should be 2. The first cell is the GPIO number. The second cell is + used to specify flags: + + bits[3:0] trigger type and level flags: + 1 = low-to-high edge triggered. + 2 = high-to-low edge triggered. + 4 = active high level-sensitive. + 8 = active low level-sensitive. + + Valid combinations are 1, 2, 3, 4, 8. + const: 2 + + interrupt-controller: true + +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra30-gpio + then: + properties: + interrupts: + minItems: 8 + maxItems: 8 + else: + properties: + interrupts: + minItems: 7 + maxItems: 7 + +required: + - compatible + - reg + - interrupts + - "#gpio-cells" + - gpio-controller + - "#interrupt-cells" + - interrupt-controller + +additionalProperties: + type: object + required: + - gpio-hog + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra20-gpio"; + reg = <0x6000d000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; diff --git a/dts/Bindings/gpio/sifive,gpio.yaml b/dts/Bindings/gpio/sifive,gpio.yaml index c2902aac25..e04349567e 100644 --- a/dts/Bindings/gpio/sifive,gpio.yaml +++ b/dts/Bindings/gpio/sifive,gpio.yaml @@ -77,7 +77,8 @@ examples: gpio@10060000 { compatible = "sifive,fu540-c000-gpio", "sifive,gpio0"; interrupt-parent = <&plic>; - interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; + interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>, + <17>, <18>, <19>, <20>, <21>, <22>; reg = <0x10060000 0x1000>; clocks = <&tlclk PRCI_CLK_TLCLK>; gpio-controller; diff --git a/dts/Bindings/gpio/toshiba,gpio-visconti.yaml b/dts/Bindings/gpio/toshiba,gpio-visconti.yaml index 9ad470e019..b085450b52 100644 --- a/dts/Bindings/gpio/toshiba,gpio-visconti.yaml +++ b/dts/Bindings/gpio/toshiba,gpio-visconti.yaml @@ -43,7 +43,6 @@ required: - gpio-controller - interrupt-controller - "#interrupt-cells" - - interrupt-parent additionalProperties: false diff --git a/dts/Bindings/gpu/arm,mali-bifrost.yaml b/dts/Bindings/gpu/arm,mali-bifrost.yaml index 6f98dd55fb..63a08f3f32 100644 --- a/dts/Bindings/gpu/arm,mali-bifrost.yaml +++ b/dts/Bindings/gpu/arm,mali-bifrost.yaml @@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali + - renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable @@ -27,19 +28,26 @@ properties: maxItems: 1 interrupts: + minItems: 3 items: - description: Job interrupt - description: MMU interrupt - description: GPU interrupt + - description: Event interrupt interrupt-names: + minItems: 3 items: - const: job - const: mmu - const: gpu + - const: event clocks: - maxItems: 1 + minItems: 1 + maxItems: 3 + + clock-names: true mali-supply: true @@ -52,7 +60,10 @@ properties: maxItems: 3 resets: - maxItems: 2 + minItems: 1 + maxItems: 3 + + reset-names: true "#cooling-cells": const: 2 @@ -98,6 +109,36 @@ allOf: properties: compatible: contains: + const: renesas,r9a07g044-mali + then: + properties: + interrupts: + minItems: 4 + interrupt-names: + minItems: 4 + clocks: + minItems: 3 + clock-names: + items: + - const: gpu + - const: bus + - const: bus_ace + resets: + minItems: 3 + reset-names: + items: + - const: rst + - const: axi_rst + - const: ace_rst + required: + - clock-names + - power-domains + - resets + - reset-names + - if: + properties: + compatible: + contains: const: mediatek,mt8183-mali then: properties: diff --git a/dts/Bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml b/dts/Bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml new file mode 100644 index 0000000000..e63ae1a008 --- /dev/null +++ b/dts/Bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra NVENC + +description: | + NVENC is the hardware video encoder present on NVIDIA Tegra210 + and newer chips. It is located on the Host1x bus and typically + programmed through Host1x channels. + +maintainers: + - Thierry Reding <treding@gmail.com> + - Mikko Perttunen <mperttunen@nvidia.com> + +properties: + $nodename: + pattern: "^nvenc@[0-9a-f]*$" + + compatible: + enum: + - nvidia,tegra210-nvenc + - nvidia,tegra186-nvenc + - nvidia,tegra194-nvenc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nvenc + + resets: + maxItems: 1 + + reset-names: + items: + - const: nvenc + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + dma-coherent: true + + interconnects: + minItems: 2 + maxItems: 3 + + interconnect-names: + minItems: 2 + maxItems: 3 + + nvidia,host1x-class: + description: | + Host1x class of the engine, used to specify the targeted engine + when programming the engine through Host1x channels or when + configuring engine-specific behavior in Host1x. + default: 0x21 + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + +allOf: + - if: + properties: + compatible: + enum: + - nvidia,tegra210-nvenc + - nvidia,tegra186-nvenc + then: + properties: + interconnects: + items: + - description: DMA read memory client + - description: DMA write memory client + interconnect-names: + items: + - const: dma-mem + - const: write + - if: + properties: + compatible: + enum: + - nvidia,tegra194-nvenc + then: + properties: + interconnects: + items: + - description: DMA read memory client + - description: DMA read 2 memory client + - description: DMA write memory client + interconnect-names: + items: + - const: dma-mem + - const: read-1 + - const: write + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra186-clock.h> + #include <dt-bindings/memory/tegra186-mc.h> + #include <dt-bindings/power/tegra186-powergate.h> + #include <dt-bindings/reset/tegra186-reset.h> + + nvenc@154c0000 { + compatible = "nvidia,tegra186-nvenc"; + reg = <0x154c0000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA186_RESET_NVENC>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVENC>; + }; diff --git a/dts/Bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml b/dts/Bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml new file mode 100644 index 0000000000..8647404d67 --- /dev/null +++ b/dts/Bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra NVJPG + +description: | + NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210 + and newer chips. It is located on the Host1x bus and typically programmed + through Host1x channels. + +maintainers: + - Thierry Reding <treding@gmail.com> + - Mikko Perttunen <mperttunen@nvidia.com> + +properties: + $nodename: + pattern: "^nvjpg@[0-9a-f]*$" + + compatible: + enum: + - nvidia,tegra210-nvjpg + - nvidia,tegra186-nvjpg + - nvidia,tegra194-nvjpg + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nvjpg + + resets: + maxItems: 1 + + reset-names: + items: + - const: nvjpg + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + dma-coherent: true + + interconnects: + items: + - description: DMA read memory client + - description: DMA write memory client + + interconnect-names: + items: + - const: dma-mem + - const: write + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra186-clock.h> + #include <dt-bindings/memory/tegra186-mc.h> + #include <dt-bindings/power/tegra186-powergate.h> + #include <dt-bindings/reset/tegra186-reset.h> + + nvjpg@15380000 { + compatible = "nvidia,tegra186-nvjpg"; + reg = <0x15380000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA186_RESET_NVJPG>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVJPG>; + }; diff --git a/dts/Bindings/hwmon/ntc-thermistor.yaml b/dts/Bindings/hwmon/ntc-thermistor.yaml index 9e77cee07d..3d3b139a91 100644 --- a/dts/Bindings/hwmon/ntc-thermistor.yaml +++ b/dts/Bindings/hwmon/ntc-thermistor.yaml @@ -76,6 +76,7 @@ properties: - const: murata,ncp15wl333 - const: murata,ncp03wf104 - const: murata,ncp15xh103 + - const: samsung,1404-001221 # Deprecated "ntp," compatible strings - const: ntc,ncp15wb473 deprecated: true diff --git a/dts/Bindings/hwmon/ti,ina2xx.yaml b/dts/Bindings/hwmon/ti,ina2xx.yaml index 6f0443322a..47af97bb4c 100644 --- a/dts/Bindings/hwmon/ti,ina2xx.yaml +++ b/dts/Bindings/hwmon/ti,ina2xx.yaml @@ -26,6 +26,7 @@ properties: - ti,ina226 - ti,ina230 - ti,ina231 + - ti,ina238 reg: maxItems: 1 @@ -35,6 +36,27 @@ properties: Shunt resistor value in micro-Ohm. $ref: /schemas/types.yaml#/definitions/uint32 + ti,shunt-gain: + description: | + Programmable gain divisor for the shunt voltage accuracy and range. This + property only applies to devices that have configurable PGA/ADCRANGE. The + gain value is used configure the gain and to convert the shunt voltage, + current and power register values when reading measurements from the + device. + + For devices that have a configurable PGA (e.g. INA209, INA219, INA220), + the gain value maps directly with the PG bits of the config register. + + For devices that have ADCRANGE configuration (e.g. INA238) a shunt-gain + value of 1 maps to ADCRANGE=1 where no gain divisor is applied to the + shunt voltage, and a value of 4 maps to ADCRANGE=0 such that a wider + voltage range is used. + + The default value is device dependent, and is defined by the reset value + of PGA/ADCRANGE in the respective configuration registers. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8] + required: - compatible - reg diff --git a/dts/Bindings/i2c/apple,i2c.yaml b/dts/Bindings/i2c/apple,i2c.yaml index 82b953181a..4ac61fec90 100644 --- a/dts/Bindings/i2c/apple,i2c.yaml +++ b/dts/Bindings/i2c/apple,i2c.yaml @@ -21,7 +21,9 @@ allOf: properties: compatible: items: - - const: apple,t8103-i2c + - enum: + - apple,t8103-i2c + - apple,t6000-i2c - const: apple,i2c reg: @@ -40,6 +42,9 @@ properties: used. This frequency is generated by dividing the reference clock. Allowed values are between ref_clk/(16*4) and ref_clk/(16*255). + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/dts/Bindings/i2c/aspeed,i2c.yaml b/dts/Bindings/i2c/aspeed,i2c.yaml index ea643e6c3e..f597f73ccd 100644 --- a/dts/Bindings/i2c/aspeed,i2c.yaml +++ b/dts/Bindings/i2c/aspeed,i2c.yaml @@ -63,7 +63,6 @@ examples: i2c0: i2c-bus@40 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; compatible = "aspeed,ast2500-i2c-bus"; reg = <0x40 0x40>; clocks = <&syscon ASPEED_CLK_APB>; diff --git a/dts/Bindings/i2c/brcm,bcm2835-i2c.txt b/dts/Bindings/i2c/brcm,bcm2835-i2c.txt deleted file mode 100644 index a8a35df419..0000000000 --- a/dts/Bindings/i2c/brcm,bcm2835-i2c.txt +++ /dev/null @@ -1,22 +0,0 @@ -Broadcom BCM2835 I2C controller - -Required properties: -- compatible : Should be one of: - "brcm,bcm2711-i2c" - "brcm,bcm2835-i2c" -- reg: Should contain register location and length. -- interrupts: Should contain interrupt. -- clocks : The clock feeding the I2C controller. - -Recommended properties: -- clock-frequency : desired I2C bus clock frequency in Hz. - -Example: - -i2c@7e205000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e205000 0x1000>; - interrupts = <2 21>; - clocks = <&clk_i2c>; - clock-frequency = <100000>; -}; diff --git a/dts/Bindings/i2c/brcm,bcm2835-i2c.yaml b/dts/Bindings/i2c/brcm,bcm2835-i2c.yaml new file mode 100644 index 0000000000..8256490a7a --- /dev/null +++ b/dts/Bindings/i2c/brcm,bcm2835-i2c.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/brcm,bcm2835-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2835 I2C controller + +maintainers: + - Stephen Warren <swarren@wwwdotorg.org> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + oneOf: + - enum: + - brcm,bcm2835-i2c + - items: + - const: brcm,bcm2711-i2c + - const: brcm,bcm2835-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: true + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + i2c@7e205000 { + compatible = "brcm,bcm2835-i2c"; + reg = <0x7e205000 0x1000>; + interrupts = <2 21>; + clocks = <&clk_i2c>; + clock-frequency = <100000>; + }; diff --git a/dts/Bindings/i2c/google,cros-ec-i2c-tunnel.yaml b/dts/Bindings/i2c/google,cros-ec-i2c-tunnel.yaml index b386e4128a..6e1c70e927 100644 --- a/dts/Bindings/i2c/google,cros-ec-i2c-tunnel.yaml +++ b/dts/Bindings/i2c/google,cros-ec-i2c-tunnel.yaml @@ -10,7 +10,6 @@ title: I2C bus that tunnels through the ChromeOS EC (cros-ec) maintainers: - Doug Anderson <dianders@chromium.org> - Benson Leung <bleung@chromium.org> - - Enric Balletbo i Serra <enric.balletbo@collabora.com> description: | On some ChromeOS board designs we've got a connection to the EC diff --git a/dts/Bindings/i2c/i2c-exynos5.txt b/dts/Bindings/i2c/i2c-exynos5.txt deleted file mode 100644 index 2dbc0b62da..0000000000 --- a/dts/Bindings/i2c/i2c-exynos5.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Samsung's High Speed I2C controller - -The Samsung's High Speed I2C controller is used to interface with I2C devices -at various speeds ranging from 100khz to 3.4Mhz. - -Required properties: - - compatible: value should be. - -> "samsung,exynos5-hsi2c", (DEPRECATED) - for i2c compatible with HSI2C available - on Exynos5250 and Exynos5420 SoCs. - -> "samsung,exynos5250-hsi2c", for i2c compatible with HSI2C available - on Exynos5250 and Exynos5420 SoCs. - -> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available - on Exynos5260 SoCs. - -> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available - on Exynos7 SoCs. - - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: interrupt number to the cpu. - - #address-cells: always 1 (for i2c addresses) - - #size-cells: always 0 - - - Pinctrl: - - pinctrl-0: Pin control group to be used for this controller. - - pinctrl-names: Should contain only one value - "default". - -Optional properties: - - clock-frequency: Desired operating frequency in Hz of the bus. - -> If not specified, the bus operates in fast-speed mode at - at 100khz. - -> If specified, the bus operates in high-speed mode only if the - clock-frequency is >= 1Mhz. - -Example: - -hsi2c@12ca0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12ca0000 0x100>; - interrupts = <56>; - clock-frequency = <100000>; - - pinctrl-0 = <&i2c4_bus>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - }; -}; diff --git a/dts/Bindings/i2c/i2c-exynos5.yaml b/dts/Bindings/i2c/i2c-exynos5.yaml new file mode 100644 index 0000000000..19874e8b73 --- /dev/null +++ b/dts/Bindings/i2c/i2c-exynos5.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-exynos5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung's High Speed I2C controller + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + +description: | + The Samsung's High Speed I2C controller is used to interface with I2C devices + at various speeds ranging from 100kHz to 3.4MHz. + + In case the HSI2C controller is encapsulated within USI block (it's the case + e.g. for Exynos850 and Exynos Auto V9 SoCs), it might be also necessary to + define USI node in device tree file, choosing "i2c" configuration. Please see + Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml for details. + +properties: + compatible: + oneOf: + - enum: + - samsung,exynos5250-hsi2c # Exynos5250 and Exynos5420 + - samsung,exynos5260-hsi2c # Exynos5260 + - samsung,exynos7-hsi2c # Exynos7 + - samsung,exynosautov9-hsi2c # ExynosAutoV9 and Exynos850 + - const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420 + deprecated: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: + default: 100000 + description: + Desired operating frequency in Hz of the bus. + + If not specified, the bus operates in fast-speed mode at 100kHz. + + If specified, the bus operates in high-speed mode only if the + clock-frequency is >= 1MHz. + + clocks: + minItems: 1 + items: + - description: I2C operating clock + - description: Bus clock (APB) + + clock-names: + minItems: 1 + items: + - const: hsi2c + - const: hsi2c_pclk + +required: + - compatible + - reg + - interrupts + - clocks + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov9-hsi2c + + then: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + + required: + - clock-names + + else: + properties: + clocks: + maxItems: 1 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos5420.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + hsi2c_8: i2c@12e00000 { + compatible = "samsung,exynos5250-hsi2c"; + reg = <0x12e00000 0x1000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + clocks = <&clock CLK_USI4>; + clock-names = "hsi2c"; + + pmic@66 { + /* compatible = "samsung,s2mps11-pmic"; */ + reg = <0x66>; + }; + }; + + - | + #include <dt-bindings/clock/exynos850.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + hsi2c_2: i2c@138c0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x138c0000 0xc0>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + + pmic@66 { + /* compatible = "samsung,s2mps11-pmic"; */ + reg = <0x66>; + }; + }; diff --git a/dts/Bindings/i2c/i2c-gate.yaml b/dts/Bindings/i2c/i2c-gate.yaml index 66472f12a7..bd67b07665 100644 --- a/dts/Bindings/i2c/i2c-gate.yaml +++ b/dts/Bindings/i2c/i2c-gate.yaml @@ -31,7 +31,7 @@ examples: #address-cells = <1>; #size-cells = <0>; ak8975@c { - compatible = "ak,ak8975"; + compatible = "asahi-kasei,ak8975"; reg = <0x0c>; }; }; diff --git a/dts/Bindings/i2c/i2c-imx-lpi2c.yaml b/dts/Bindings/i2c/i2c-imx-lpi2c.yaml index fe0c89edf7..529bea56d3 100644 --- a/dts/Bindings/i2c/i2c-imx-lpi2c.yaml +++ b/dts/Bindings/i2c/i2c-imx-lpi2c.yaml @@ -20,7 +20,9 @@ properties: - items: - enum: - fsl,imx8qxp-lpi2c + - fsl,imx8dxl-lpi2c - fsl,imx8qm-lpi2c + - fsl,imx8ulp-lpi2c - const: fsl,imx7ulp-lpi2c reg: diff --git a/dts/Bindings/i2c/i2c-mux-gpio.txt b/dts/Bindings/i2c/i2c-mux-gpio.txt deleted file mode 100644 index d4cf10582a..0000000000 --- a/dts/Bindings/i2c/i2c-mux-gpio.txt +++ /dev/null @@ -1,80 +0,0 @@ -GPIO-based I2C Bus Mux - -This binding describes an I2C bus multiplexer that uses GPIOs to -route the I2C signals. - - +-----+ +-----+ - | dev | | dev | - +------------+ +-----+ +-----+ - | SoC | | | - | | /--------+--------+ - | +------+ | +------+ child bus A, on GPIO value set to 0 - | | I2C |-|--| Mux | - | +------+ | +--+---+ child bus B, on GPIO value set to 1 - | | | \----------+--------+--------+ - | +------+ | | | | | - | | GPIO |-|-----+ +-----+ +-----+ +-----+ - | +------+ | | dev | | dev | | dev | - +------------+ +-----+ +-----+ +-----+ - -Required properties: -- compatible: i2c-mux-gpio -- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side - port is connected to. -- mux-gpios: list of gpios used to control the muxer -* Standard I2C mux properties. See i2c-mux.yaml in this directory. -* I2C child bus nodes. See i2c-mux.yaml in this directory. - -Optional properties: -- idle-state: value to set the muxer to when idle. When no value is - given, it defaults to the last value used. - -For each i2c child node, an I2C child bus will be created. They will -be numbered based on their order in the device tree. - -Whenever an access is made to a device on a child bus, the value set -in the relevant node's reg property will be output using the list of -GPIOs, the first in the list holding the least-significant value. - -If an idle state is defined, using the idle-state (optional) property, -whenever an access is not being made to a device on a child bus, the -GPIOs will be set according to the idle value. - -If an idle state is not defined, the most recently used value will be -left programmed into hardware whenever no access is being made to a -device on a child bus. - -Example: - i2cmux { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - mux-gpios = <&gpio1 22 0 &gpio1 23 0>; - i2c-parent = <&i2c1>; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ssd1307: oled@3c { - compatible = "solomon,ssd1307fb-i2c"; - reg = <0x3c>; - pwms = <&pwm 4 3000>; - reset-gpios = <&gpio2 7 1>; - }; - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; - }; - }; diff --git a/dts/Bindings/i2c/i2c-mux-gpio.yaml b/dts/Bindings/i2c/i2c-mux-gpio.yaml new file mode 100644 index 0000000000..6e0a5686af --- /dev/null +++ b/dts/Bindings/i2c/i2c-mux-gpio.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-mux-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO-based I2C Bus Mux + +maintainers: + - Wolfram Sang <wsa@kernel.org> + +description: | + This binding describes an I2C bus multiplexer that uses GPIOs to route the I2C signals. + + +-----+ +-----+ + | dev | | dev | + +------------+ +-----+ +-----+ + | SoC | | | + | | /--------+--------+ + | +------+ | +------+ child bus A, on GPIO value set to 0 + | | I2C |-|--| Mux | + | +------+ | +--+---+ child bus B, on GPIO value set to 1 + | | | \----------+--------+--------+ + | +------+ | | | | | + | | GPIO |-|-----+ +-----+ +-----+ +-----+ + | +------+ | | dev | | dev | | dev | + +------------+ +-----+ +-----+ +-----+ + + For each I2C child node, an I2C child bus will be created. They will be numbered based on their + order in the device tree. + + Whenever an access is made to a device on a child bus, the value set in the relevant node's reg + property will be output using the list of GPIOs, the first in the list holding the least- + significant value. + + If an idle state is defined, using the idle-state (optional) property, whenever an access is not + being made to a device on a child bus, the GPIOs will be set according to the idle value. + + If an idle state is not defined, the most recently used value will be left programmed into + hardware whenever no access is being made to a device on a child bus. + +properties: + compatible: + const: i2c-mux-gpio + + i2c-parent: + description: phandle of the I2C bus that this multiplexer's master-side port is connected to + $ref: "/schemas/types.yaml#/definitions/phandle" + + mux-gpios: + description: list of GPIOs used to control the muxer + minItems: 1 + maxItems: 4 # Should be enough + + idle-state: + description: Value to set the muxer to when idle. When no value is given, it defaults to the + last value used. + $ref: "/schemas/types.yaml#/definitions/uint32" + +allOf: + - $ref: i2c-mux.yaml + +unevaluatedProperties: false + +required: + - compatible + - i2c-parent + - mux-gpios + +examples: + - | + i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&gpio1 22 0>, <&gpio1 23 0>; + i2c-parent = <&i2c1>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ssd1307: oled@3c { + compatible = "solomon,ssd1307fb-i2c"; + reg = <0x3c>; + pwms = <&pwm 4 3000>; + reset-gpios = <&gpio2 7 1>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + pca9555: pca9555@20 { |