diff options
54 files changed, 8456 insertions, 79 deletions
diff --git a/Documentation/boards/rockchip.rst b/Documentation/boards/rockchip.rst index a5599c6d5f..d03c4686df 100644 --- a/Documentation/boards/rockchip.rst +++ b/Documentation/boards/rockchip.rst @@ -45,3 +45,42 @@ Instructions. * Run "rk-makebootable FlashData barebox-radxa-rock.bin rrboot.bin" * Insert SD card and run "dd if=rrboot.bin of=</dev/sdcard> bs=$((0x200)) seek=$((0x40))" * SD card is ready + +Rockchip RK3568 +=============== + +RK3568 EVB +---------- + +Building +^^^^^^^^ + +The build process needs three binary files which have to be copied from the +`rkbin https://github.com/rockchip-linux/rkbin` repository to the barebox source tree: + +.. code-block:: sh + cp $RKBIN/rk35/rk3568_bl31_v1.24.elf firmware/rk3568-bl31.bin + cp $RKBIN/bin/rk35/rk3568_bl32_v1.05.bin firmware/rk3568-op-tee.bin + cp $RKBIN/bin/rk35/rk3568_ddr_1560MHz_v1.08.bin arch/arm/boards/rockchip-rk3568-evb/sdram-init.bin + +With these barebox can be compiled as: + +.. code-block:: sh + + make ARCH=arm rockchip_v8_defconfig + make ARCH=arm + +**NOTE** I found the bl32 firmware non working for me as of 7d631e0d5b2d373b54d4533580d08fb9bd2eaad4 in the rkbin repository. + +Creating a bootable SD card +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +A bootable SD card can be created with: + +.. code-block:: sh + + dd if=images/barebox-rk3568-evb.img of=/dev/sdx bs=1024 seek=32 + +The barebox image is written to the raw device, so make sure the partitioning +doesn't conflict with the are barebox is written to. Starting the first +partition at offset 8MiB is a safe bet. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6f28e1ec10..c7ab166888 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -145,8 +145,6 @@ config ARCH_PXA config ARCH_ROCKCHIP bool "Rockchip RX3xxx" - select CPU_V7 - select ARM_SMP_TWD select COMMON_CLK select CLKDEV_LOOKUP select COMMON_CLK_OF_PROVIDER @@ -156,7 +154,6 @@ config ARCH_ROCKCHIP select OFTREE select HAVE_PBL_MULTI_IMAGES select HAS_DEBUG_LL - select ARCH_HAS_L2X0 config ARCH_SOCFPGA bool "Altera SOCFPGA" @@ -499,4 +496,7 @@ config ARM_MODULE_PLTS Say y if your memory configuration puts the heap to far away from the barebox image, causing relocation out of range errors +config ARM_ATF + bool + endmenu diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index b3415eb4a2..5aac64fce5 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -181,3 +181,4 @@ obj-$(CONFIG_MACH_LS1046ARDB) += ls1046ardb/ obj-$(CONFIG_MACH_TQMLS1046A) += tqmls1046a/ obj-$(CONFIG_MACH_MNT_REFORM) += mnt-reform/ obj-$(CONFIG_MACH_SKOV_ARM9CPU) += skov-arm9cpu/ +obj-$(CONFIG_MACH_RK3568_EVB) += rockchip-rk3568-evb/ diff --git a/arch/arm/boards/rockchip-rk3568-evb/Makefile b/arch/arm/boards/rockchip-rk3568-evb/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/rockchip-rk3568-evb/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/rockchip-rk3568-evb/board.c b/arch/arm/boards/rockchip-rk3568-evb/board.c new file mode 100644 index 0000000000..57c24ed3c6 --- /dev/null +++ b/arch/arm/boards/rockchip-rk3568-evb/board.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <common.h> +#include <init.h> +#include <mach/bbu.h> +#include <bootsource.h> + +static int rk3568_evb_probe(struct device_d *dev) +{ + enum bootsource bootsource = bootsource_get(); + int instance = bootsource_get_instance(); + + barebox_set_model("Rockchip RK3568 EVB"); + barebox_set_hostname("rk3568-evb"); + + if (bootsource == BOOTSOURCE_MMC && instance == 1) + of_device_enable_path("/chosen/environment-sd"); + else + of_device_enable_path("/chosen/environment-emmc"); + + rk3568_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT, "/dev/emmc.barebox"); + rk3568_bbu_mmc_register("sd", 0, "/dev/sd.barebox"); + + return 0; +} + +static const struct of_device_id rk3568_evb_of_match[] = { + { .compatible = "rockchip,rk3568-evb1-v10" }, + { /* Sentinel */}, +}; + +static struct driver_d rk3568_evb_board_driver = { + .name = "board-rk3568-evb", + .probe = rk3568_evb_probe, + .of_compatible = rk3568_evb_of_match, +}; +coredevice_platform_driver(rk3568_evb_board_driver); diff --git a/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c b/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c new file mode 100644 index 0000000000..363639d21b --- /dev/null +++ b/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <linux/sizes.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/hardware.h> +#include <mach/atf.h> +#include <debug_ll.h> +#include <mach/rockchip.h> + +extern char __dtb_rk3568_evb1_v10_start[]; + +static noinline void rk3568_start(void) +{ + void *fdt; + + /* + * Enable vccio4 1.8V and vccio6 1.8V + * Needed for GMAC to work. + */ + writel(RK_SETBITS(0x50), 0xfdc20140); + + fdt = __dtb_rk3568_evb1_v10_start; + + if (current_el() == 3) { + rk3568_lowlevel_init(); + rk3568_atf_load_bl31(fdt); + /* not reached */ + } + + barebox_arm_entry(RK3568_DRAM_BOTTOM, 0x80000000 - RK3568_DRAM_BOTTOM, fdt); +} + +ENTRY_FUNCTION(start_rk3568_evb, r0, r1, r2) +{ + /* + * Image execution starts at 0x0, but this is used for ATF and + * OP-TEE later, so move away from here. + */ + if (current_el() == 3) + relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS); + else + relocate_to_current_adr(); + + setup_c(); + + rk3568_start(); +} diff --git a/arch/arm/configs/rockchip_v8_defconfig b/arch/arm/configs/rockchip_v8_defconfig new file mode 100644 index 0000000000..4e5393768c --- /dev/null +++ b/arch/arm/configs/rockchip_v8_defconfig @@ -0,0 +1,119 @@ +CONFIG_ARCH_ROCKCHIP=y +CONFIG_MACH_RK3568_EVB=y +CONFIG_BOARD_ARM_GENERIC_DT=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_PSCI_CLIENT=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_RELOCATABLE=y +CONFIG_PROMPT="barebox> " +CONFIG_BAUDRATE=1500000 +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_BOOTM_SHOW_TYPE=y +CONFIG_BOOTM_VERBOSE=y +CONFIG_BOOTM_INITRD=y +CONFIG_BOOTM_OFTREE=y +CONFIG_BOOTM_OFTREE_UIMAGE=y +CONFIG_BOOTM_AIMAGE=y +CONFIG_BLSPEC=y +CONFIG_SYSTEM_PARTITIONS=y +CONFIG_CONSOLE_ACTIVATE_NONE=y +CONFIG_CONSOLE_ALLOW_COLOR=y +CONFIG_PBL_CONSOLE=y +CONFIG_PARTITION_DISK_EFI=y +CONFIG_DEFAULT_COMPRESSION_LZO=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_STATE=y +CONFIG_BOOTCHOOSER=y +CONFIG_RESET_SOURCE=y +CONFIG_DEBUG_LL=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_GO=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_BOOTCHOOSER=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_DEFAULTENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_SHA224SUM=y +CONFIG_CMD_SHA256SUM=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_READF=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_MM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SMC=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_OF_DIFF=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OF_DISPLAY_TIMINGS=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y +CONFIG_NET_NFS=y +CONFIG_NET_NETCONSOLE=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_NET_DESIGNWARE_EQOS=y +CONFIG_DRIVER_NET_DESIGNWARE_ROCKCHIP=y +CONFIG_SMSC_PHY=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_MMC_BOOT_PARTITIONS=y +CONFIG_MCI_DW=y +CONFIG_MCI_DW_PIO=y +CONFIG_MCI_ROCKCHIP_DWCMSHC=y +CONFIG_MCI_ARASAN=y +CONFIG_MFD_ACT8846=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_POLLER=y +CONFIG_WATCHDOG_DW=y +CONFIG_GENERIC_PHY=y +# CONFIG_VIRTIO_MENU is not set +CONFIG_FS_CRAMFS=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_FS_BPKFS=y +CONFIG_FS_UIMAGEFS=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index e7a6e3e6fb..6344ab5066 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -50,6 +50,7 @@ AFLAGS-cache-armv8.pbl.o :=-Wa,-march=armv8-a pbl-y += entry.o entry_ll$(S64).o pbl-y += uncompress.o +pbl-$(CONFIG_ARM_ATF) += atf.o obj-pbl-y += common.o sections.o KASAN_SANITIZE_common.o := n diff --git a/arch/arm/cpu/atf.c b/arch/arm/cpu/atf.c new file mode 100644 index 0000000000..4753a8a559 --- /dev/null +++ b/arch/arm/cpu/atf.c @@ -0,0 +1,80 @@ +#include <common.h> +#include <asm/atf_common.h> +#include <asm/system.h> + +static inline void raw_write_daif(unsigned int daif) +{ + __asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory"); +} + +void bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry, + uintptr_t bl33_entry, uintptr_t fdt_addr) +{ + struct atf_image_info bl31_image_info = { + .h = { + .type = ATF_PARAM_IMAGE_BINARY, + .version = ATF_VERSION_1, + .size = sizeof(bl31_image_info), + }, + }; + struct atf_image_info bl32_image_info = { + .h = { + .type = ATF_PARAM_IMAGE_BINARY, + .version = ATF_VERSION_1, + .size = sizeof(bl32_image_info), + }, + }; + struct entry_point_info bl32_ep_info = { + .h = { + .type = ATF_PARAM_EP, + .version = ATF_VERSION_1, + .attr = ATF_EP_SECURE, + .size = sizeof(bl32_ep_info), + }, + .pc = bl32_entry, + .spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXECPTIONS), + .args = { + .arg3 = fdt_addr, + }, + }; + struct atf_image_info bl33_image_info = { + .h = { + .type = ATF_PARAM_IMAGE_BINARY, + .version = ATF_VERSION_1, + .size = sizeof(bl33_image_info), + }, + }; + struct entry_point_info bl33_ep_info = { + .h = { + .type = ATF_PARAM_EP, + .version = ATF_VERSION_1, + .attr = ATF_EP_NON_SECURE, + .size = sizeof(bl33_ep_info), + }, + .pc = bl33_entry, + .spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXECPTIONS), + .args = { + /* BL33 expects to receive the primary CPU MPID (through x0) */ + .arg0 = 0xffff & read_mpidr(), + }, + }; + struct bl31_params bl31_params = { + .h = { + .type = ATF_PARAM_BL31, + .version = ATF_VERSION_1, + .size = sizeof(bl31_params), + }, + .bl31_image_info = &bl31_image_info, + .bl32_ep_info = &bl32_ep_info, + .bl32_image_info = &bl32_image_info, + .bl33_ep_info = &bl33_ep_info, + .bl33_image_info = &bl33_image_info, + }; + void (*atf_entry)(struct bl31_params *params, uintptr_t plat_params); + + raw_write_daif(SPSR_EXCEPTION_MASK); + + atf_entry = (void *)bl31_entry; + + atf_entry(&bl31_params, fdt_addr); +} diff --git a/arch/arm/cpu/setupc_64.S b/arch/arm/cpu/setupc_64.S index ee9ea6cfc0..e24acbd0da 100644 --- a/arch/arm/cpu/setupc_64.S +++ b/arch/arm/cpu/setupc_64.S @@ -24,9 +24,18 @@ ENDPROC(setup_c) * executing at new address. */ .section .text.relocate_to_adr -ENTRY(relocate_to_adr) /* x0: target address */ +#ifdef __PBL__ +ENTRY(relocate_to_adr_full) + ldr x2, =__piggydata_end + b 1f +#endif + +ENTRY(relocate_to_adr) + ldr x2, =__bss_start + b 1f +1: stp x19, x20, [sp, #-16]! stp x21, x22, [sp, #-16]! @@ -45,8 +54,6 @@ ENTRY(relocate_to_adr) cmp x1, x21 /* already at correct address? */ beq 1f /* yes, skip copy to new address */ - ldr x2, =__bss_start - sub x2, x2, x0 /* x2: size */ mov x0, x21 /* x0: target */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a07a3bf33f..ffa9fe88c1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -96,6 +96,7 @@ lwl-$(CONFIG_MACH_PROTONIC_IMX8M) += imx8mm-prt8mm.dtb.o lwl-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o lwl-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o lwl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o +lwl-$(CONFIG_MACH_RK3568_EVB) += rk3568-evb1-v10.dtb.o lwl-$(CONFIG_MACH_RPI) += bcm2835-rpi.dtb.o lwl-$(CONFIG_MACH_RPI2) += bcm2836-rpi-2.dtb.o lwl-$(CONFIG_MACH_RPI3) += bcm2837-rpi-3.dtb.o diff --git a/arch/arm/dts/rk3568-evb1-v10.dts b/arch/arm/dts/rk3568-evb1-v10.dts new file mode 100644 index 0000000000..bd583015e8 --- /dev/null +++ b/arch/arm/dts/rk3568-evb1-v10.dts @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3568.dtsi" + +/ { + model = "Rockchip RK3568 EVB1 DDR4 V10 Board"; + compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568"; + + aliases { + emmc = &sdhci; + sd = &sdmmc0; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + + environment-sd { + compatible = "barebox,environment"; + device-path = &environment_sd; + status = "disabled"; + }; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &environment_emmc; + status = "disabled"; + }; + }; + + memory@a00000 { + device_type = "memory"; + reg = <0x0 0x00a00000 0x0 0x7f600000>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x3c>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reg = <0x0>; + }; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + no-sd; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@8000 { + label = "barebox"; + reg = <0x8000 0x400000>; + }; + + environment_emmc: partition@408000 { + label = "barebox-environment"; + reg = <0x408000 0x8000>; + }; + }; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@8000 { + label = "barebox"; + reg = <0x8000 0x400000>; + }; + + environment_sd: partition@408000 { + label = "barebox-environment"; + reg = <0x408000 0x8000>; + }; + }; +}; + +&uart2 { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568-pinctrl.dtsi b/arch/arm/dts/rk3568-pinctrl.dtsi new file mode 100644 index 0000000000..a588ca95ac --- /dev/null +++ b/arch/arm/dts/rk3568-pinctrl.dtsi @@ -0,0 +1,3111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/pinctrl/rockchip.h> +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + acodec { + /omit-if-no-ref/ + acodec_pins: acodec-pins { + rockchip,pins = + /* acodec_adc_sync */ + <1 RK_PB1 5 &pcfg_pull_none>, + /* acodec_adcclk */ + <1 RK_PA1 5 &pcfg_pull_none>, + /* acodec_adcdata */ + <1 RK_PA0 5 &pcfg_pull_none>, + /* acodec_dac_datal */ + <1 RK_PA7 5 &pcfg_pull_none>, + /* acodec_dac_datar */ + <1 RK_PB0 5 &pcfg_pull_none>, + /* acodec_dacclk */ + <1 RK_PA3 5 &pcfg_pull_none>, + /* acodec_dacsync */ + <1 RK_PA5 5 &pcfg_pull_none>; + }; + }; + + audiopwm { + /omit-if-no-ref/ + audiopwm_lout: audiopwm-lout { + rockchip,pins = + /* audiopwm_lout */ + <1 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_loutn: audiopwm-loutn { + rockchip,pins = + /* audiopwm_loutn */ + <1 RK_PA1 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_loutp: audiopwm-loutp { + rockchip,pins = + /* audiopwm_loutp */ + <1 RK_PA0 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_rout: audiopwm-rout { + rockchip,pins = + /* audiopwm_rout */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_routn: audiopwm-routn { + rockchip,pins = + /* audiopwm_routn */ + <1 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_routp: audiopwm-routp { + rockchip,pins = + /* audiopwm_routp */ + <1 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + bt656 { + /omit-if-no-ref/ + bt656m0_pins: bt656m0-pins { + rockchip,pins = + /* bt656_clkm0 */ + <3 RK_PA0 2 &pcfg_pull_none>, + /* bt656_d0m0 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* bt656_d1m0 */ + <2 RK_PD1 2 &pcfg_pull_none>, + /* bt656_d2m0 */ + <2 RK_PD2 2 &pcfg_pull_none>, + /* bt656_d3m0 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* bt656_d4m0 */ + <2 RK_PD4 2 &pcfg_pull_none>, + /* bt656_d5m0 */ + <2 RK_PD5 2 &pcfg_pull_none>, + /* bt656_d6m0 */ + <2 RK_PD6 2 &pcfg_pull_none>, + /* bt656_d7m0 */ + <2 RK_PD7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + bt656m1_pins: bt656m1-pins { + rockchip,pins = + /* bt656_clkm1 */ + <4 RK_PB4 5 &pcfg_pull_none>, + /* bt656_d0m1 */ + <3 RK_PC6 5 &pcfg_pull_none>, + /* bt656_d1m1 */ + <3 RK_PC7 5 &pcfg_pull_none>, + /* bt656_d2m1 */ + <3 RK_PD0 5 &pcfg_pull_none>, + /* bt656_d3m1 */ + <3 RK_PD1 5 &pcfg_pull_none>, + /* bt656_d4m1 */ + <3 RK_PD2 5 &pcfg_pull_none>, + /* bt656_d5m1 */ + <3 RK_PD3 5 &pcfg_pull_none>, + /* bt656_d6m1 */ + <3 RK_PD4 5 &pcfg_pull_none>, + /* bt656_d7m1 */ + <3 RK_PD5 5 &pcfg_pull_none>; + }; + }; + + bt1120 { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* bt1120_clk */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* bt1120_d0 */ + <3 RK_PA1 2 &pcfg_pull_none>, + /* bt1120_d1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* bt1120_d2 */ + <3 RK_PA3 2 &pcfg_pull_none>, + /* bt1120_d3 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* bt1120_d4 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* bt1120_d5 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* bt1120_d6 */ + <3 RK_PB0 2 &pcfg_pull_none>, + /* bt1120_d7 */ + <3 RK_PB1 2 &pcfg_pull_none>, + /* bt1120_d8 */ + <3 RK_PB2 2 &pcfg_pull_none>, + /* bt1120_d9 */ + <3 RK_PB3 2 &pcfg_pull_none>, + /* bt1120_d10 */ + <3 RK_PB4 2 &pcfg_pull_none>, + /* bt1120_d11 */ + <3 RK_PB5 2 &pcfg_pull_none>, + /* bt1120_d12 */ + <3 RK_PB6 2 &pcfg_pull_none>, + /* bt1120_d13 */ + <3 RK_PC1 2 &pcfg_pull_none>, + /* bt1120_d14 */ + <3 RK_PC2 2 &pcfg_pull_none>, + /* bt1120_d15 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + cam { + /omit-if-no-ref/ + cam_clkout0: cam-clkout0 { + rockchip,pins = + /* cam_clkout0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clkout1: cam-clkout1 { + rockchip,pins = + /* cam_clkout1 */ + <4 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rxm0 */ + <0 RK_PB4 2 &pcfg_pull_none>, + /* can0_txm0 */ + <0 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rxm1 */ + <2 RK_PA2 4 &pcfg_pull_none>, + /* can0_txm1 */ + <2 RK_PA1 4 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rxm0 */ + <1 RK_PA0 3 &pcfg_pull_none>, + /* can1_txm0 */ + <1 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rxm1 */ + <4 RK_PC2 3 &pcfg_pull_none>, + /* can1_txm1 */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + }; + + can2 { + /omit-if-no-ref/ + can2m0_pins: can2m0-pins { + rockchip,pins = + /* can2_rxm0 */ + <4 RK_PB4 3 &pcfg_pull_none>, + /* can2_txm0 */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can2m1_pins: can2m1-pins { + rockchip,pins = + /* can2_rxm1 */ + <2 RK_PB1 4 &pcfg_pull_none>, + /* can2_txm1 */ + <2 RK_PB2 4 &pcfg_pull_none>; + }; + }; + + cif { + /omit-if-no-ref/ + cif_clk: cif-clk { + rockchip,pins = + /* cif_clkout */ + <4 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_clk: cif-dvp-clk { + rockchip,pins = + /* cif_clkin */ + <4 RK_PC1 1 &pcfg_pull_none>, + /* cif_href */ + <4 RK_PB6 1 &pcfg_pull_none>, + /* cif_vsync */ + <4 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus16: cif-dvp-bus16 { + rockchip,pins = + /* cif_d8 */ + <3 RK_PD6 1 &pcfg_pull_none>, + /* cif_d9 */ + <3 RK_PD7 1 &pcfg_pull_none>, + /* cif_d10 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* cif_d11 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* cif_d12 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* cif_d13 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* cif_d14 */ + <4 RK_PA4 1 &pcfg_pull_none>, + /* cif_d15 */ + <4 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus8: cif-dvp-bus8 { + rockchip,pins = + /* cif_d0 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* cif_d1 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* cif_d2 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* cif_d3 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* cif_d4 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* cif_d5 */ + <3 RK_PD3 1 &pcfg_pull_none>, + /* cif_d6 */ + <3 RK_PD4 1 &pcfg_pull_none>, + /* cif_d7 */ + <3 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + clk32k { + /omit-if-no-ref/ + clk32k_in: clk32k-in { + rockchip,pins = + /* clk32k_in */ + <0 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out0: clk32k-out0 { + rockchip,pins = + /* clk32k_out0 */ + <0 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out1: clk32k-out1 { + rockchip,pins = + /* clk32k_out1 */ + <2 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_avs */ + <0 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + ebc { + /omit-if-no-ref/ + ebc_extern: ebc-extern { + rockchip,pins = + /* ebc_sdce1 */ + <4 RK_PA7 2 &pcfg_pull_none>, + /* ebc_sdce2 */ + <4 RK_PB0 2 &pcfg_pull_none>, + /* ebc_sdce3 */ + <4 RK_PB1 2 &pcfg_pull_none>, + /* ebc_sdshr */ + <4 RK_PB5 2 &pcfg_pull_none>, + /* ebc_vcom */ + <4 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + ebc_pins: ebc-pins { + rockchip,pins = + /* ebc_gdclk */ + <4 RK_PC0 2 &pcfg_pull_none>, + /* ebc_gdoe */ + <4 RK_PB3 2 &pcfg_pull_none>, + /* ebc_gdsp */ + <4 RK_PB4 2 &pcfg_pull_none>, + /* ebc_sdce0 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* ebc_sdclk */ + <4 RK_PC1 2 &pcfg_pull_none>, + /* ebc_sddo0 */ + <3 RK_PC6 2 &pcfg_pull_none>, + /* ebc_sddo1 */ + <3 RK_PC7 2 &pcfg_pull_none>, + /* ebc_sddo2 */ + <3 RK_PD0 2 &pcfg_pull_none>, + /* ebc_sddo3 */ + <3 RK_PD1 2 &pcfg_pull_none>, + /* ebc_sddo4 */ + <3 RK_PD2 2 &pcfg_pull_none>, + /* ebc_sddo5 */ + <3 RK_PD3 2 &pcfg_pull_none>, + /* ebc_sddo6 */ + <3 RK_PD4 2 &pcfg_pull_none>, + /* ebc_sddo7 */ + <3 RK_PD5 2 &pcfg_pull_none>, + /* ebc_sddo8 */ + <3 RK_PD6 2 &pcfg_pull_none>, + /* ebc_sddo9 */ + <3 RK_PD7 2 &pcfg_pull_none>, + /* ebc_sddo10 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* ebc_sddo11 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* ebc_sddo12 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* ebc_sddo13 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* ebc_sddo14 */ + <4 RK_PA4 2 &pcfg_pull_none>, + /* ebc_sddo15 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* ebc_sdle */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* ebc_sdoe */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + edpdp { + /omit-if-no-ref/ + edpdpm0_pins: edpdpm0-pins { + rockchip,pins = + /* edpdp_hpdinm0 */ + <4 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + edpdpm1_pins: edpdpm1-pins { + rockchip,pins = + /* edpdp_hpdinm1 */ + <0 RK_PC2 2 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clkout */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_datastrobe: emmc-datastrobe { + rockchip,pins = + /* emmc_datastrobe */ + <1 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + eth0 { + /omit-if-no-ref/ + eth0_pins: eth0-pins { + rockchip,pins = + /* eth0_refclko25m */ + <2 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + eth1 { + /omit-if-no-ref/ + eth1m0_pins: eth1m0-pins { + rockchip,pins = + /* eth1_refclko25mm0 */ + <3 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + eth1m1_pins: eth1m1-pins { + rockchip,pins = + /* eth1_refclko25mm1 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + flash { + /omit-if-no-ref/ + flash_pins: flash-pins { + rockchip,pins = + /* flash_ale */ + <1 RK_PD0 2 &pcfg_pull_none>, + /* flash_cle */ + <1 RK_PC6 3 &pcfg_pull_none>, + /* flash_cs0n */ + <1 RK_PD3 2 &pcfg_pull_none>, + /* flash_cs1n */ + <1 RK_PD4 2 &pcfg_pull_none>, + /* flash_d0 */ + <1 RK_PB4 2 &pcfg_pull_none>, + /* flash_d1 */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* flash_d2 */ + <1 RK_PB6 2 &pcfg_pull_none>, + /* flash_d3 */ + <1 RK_PB7 2 &pcfg_pull_none>, + /* flash_d4 */ + <1 RK_PC0 2 &pcfg_pull_none>, + /* flash_d5 */ + <1 RK_PC1 2 &pcfg_pull_none>, + /* flash_d6 */ + <1 RK_PC2 2 &pcfg_pull_none>, + /* flash_d7 */ + <1 RK_PC3 2 &pcfg_pull_none>, + /* flash_dqs */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* flash_rdn */ + <1 RK_PD2 2 &pcfg_pull_none>, + /* flash_rdy */ + <1 RK_PD1 2 &pcfg_pull_none>, + /* flash_volsel */ + <0 RK_PA7 1 &pcfg_pull_none>, + /* flash_wpn */ + <1 RK_PC7 3 &pcfg_pull_none>, + /* flash_wrn */ + <1 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PC7 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PD4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_cs1: fspi-cs1 { + rockchip,pins = + /* fspi_cs1n */ + <1 RK_PC6 2 &pcfg_pull_up>; + }; + }; + + gmac0 { + /omit-if-no-ref/ + gmac0_miim: gmac0-miim { + rockchip,pins = + /* gmac0_mdc */ + <2 RK_PC3 2 &pcfg_pull_none>, + /* gmac0_mdio */ + <2 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_clkinout: gmac0-clkinout { + rockchip,pins = + /* gmac0_mclkinout */ + <2 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_er: gmac0-rx-er { + rockchip,pins = + /* gmac0_rxer */ + <2 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_bus2: gmac0-rx-bus2 { + rockchip,pins = + /* gmac0_rxd0 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* gmac0_rxd1 */ + <2 RK_PB7 2 &pcfg_pull_none>, + /* gmac0_rxdvcrs */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_tx_bus2: gmac0-tx-bus2 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_clk: gmac0-rgmii-clk { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus: gmac0-rgmii-bus { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + gmac1 { + /omit-if-no-ref/ + gmac1m0_miim: gmac1m0-miim { + rockchip,pins = + /* gmac1_mdcm0 */ + <3 RK_PC4 3 &pcfg_pull_none>, + /* gmac1_mdiom0 */ + <3 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_clkinout: gmac1m0-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm0 */ + <3 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rx_er: gmac1m0-rx-er { + rockchip,pins = + /* gmac1_rxerm0 */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rx_bus2: gmac1m0-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m0 */ + <3 RK_PB1 3 &pcfg_pull_none>, + /* gmac1_rxd1m0 */ + <3 RK_PB2 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm0 */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_tx_bus2: gmac1m0-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m1_miim: gmac1m1-miim { + rockchip,pins = + /* gmac1_mdcm1 */ + <4 RK_PB6 3 &pcfg_pull_none>, + /* gmac1_mdiom1 */ + <4 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_clkinout: gmac1m1-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm1 */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_er: gmac1m1-rx-er { + rockchip,pins = + /* gmac1_rxerm1 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_bus2: gmac1m1-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m1 */ + <4 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_rxd1m1 */ + <4 RK_PB0 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm1 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2: gmac1m1-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk: gmac1m1-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus: gmac1m1-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC0 2 &pcfg_pull_none>, + /* gpu_pwren */ + <0 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + hdmitx { + /omit-if-no-ref/ + hdmitxm0_cec: hdmitxm0-cec { + rockchip,pins = + /* hdmitxm0_cec */ + <4 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitxm1_cec: hdmitxm1-cec { + rockchip,pins = + /* hdmitxm1_cec */ + <0 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitx_scl: hdmitx-scl { + rockchip,pins = + /* hdmitx_scl */ + <4 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitx_sda: hdmitx-sda { + rockchip,pins = + /* hdmitx_sda */ + <4 RK_PD0 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB1 1 &pcfg_pull_none_smt>, + /* i2c0_sda */ + <0 RK_PB2 1 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1_xfer: i2c1-xfer { + rockchip,pins = + /* i2c1_scl */ + <0 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c1_sda */ + <0 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_sclm0 */ + <0 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sdam0 */ + <0 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_sclm1 */ + <4 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sdam1 */ + <4 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_sclm0 */ + <1 RK_PA1 1 &pcfg_pull_none_smt>, + /* i2c3_sdam0 */ + <1 RK_PA0 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_sclm1 */ + <3 RK_PB5 4 &pcfg_pull_none_smt>, + /* i2c3_sdam1 */ + <3 RK_PB6 4 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_sclm0 */ + <4 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c4_sdam0 */ + <4 RK_PB2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_sclm1 */ + <2 RK_PB2 2 &pcfg_pull_none_smt>, + /* i2c4_sdam1 */ + <2 RK_PB1 2 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_sclm0 */ + <3 RK_PB3 4 &pcfg_pull_none_smt>, + /* i2c5_sdam0 */ + <3 RK_PB4 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_sclm1 */ + <4 RK_PC7 2 &pcfg_pull_none_smt>, + /* i2c5_sdam1 */ + <4 RK_PD0 2 &pcfg_pull_none_smt>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrckrx: i2s1m0-lrckrx { + rockchip,pins = + /* i2s1m0_lrckrx */ + <1 RK_PA6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_lrcktx: i2s1m0-lrcktx { + rockchip,pins = + /* i2s1m0_lrcktx */ + <1 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <1 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclkrx: i2s1m0-sclkrx { + rockchip,pins = + /* i2s1m0_sclkrx */ + <1 RK_PA4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclktx: i2s1m0-sclktx { + rockchip,pins = + /* i2s1m0_sclktx */ + <1 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <1 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <1 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + /* i2s1m0_sdo1 */ + <1 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + /* i2s1m0_sdo2 */ + <1 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + /* i2s1m0_sdo3 */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrckrx: i2s1m1-lrckrx { + rockchip,pins = + /* i2s1m1_lrckrx */ + <4 RK_PA7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrcktx: i2s1m1-lrcktx { + rockchip,pins = + /* i2s1m1_lrcktx */ + <3 RK_PD0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + /* i2s1m1_mclk */ + <3 RK_PC6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclkrx: i2s1m1-sclkrx { + rockchip,pins = + /* i2s1m1_sclkrx */ + <4 RK_PA6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclktx: i2s1m1-sclktx { + rockchip,pins = + /* i2s1m1_sclktx */ + <3 RK_PC7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + /* i2s1m1_sdi0 */ + <3 RK_PD2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + /* i2s1m1_sdi1 */ + <3 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + /* i2s1m1_sdi2 */ + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + /* i2s1m1_sdi3 */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + /* i2s1m1_sdo0 */ + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + /* i2s1m1_sdo1 */ + <4 RK_PB0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + /* i2s1m1_sdo2 */ + <4 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + /* i2s1m1_sdo3 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_lrckrx: i2s1m2-lrckrx { + rockchip,pins = + /* i2s1m2_lrckrx */ + <3 RK_PC5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_lrcktx: i2s1m2-lrcktx { + rockchip,pins = + /* i2s1m2_lrcktx */ + <2 RK_PD2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_mclk: i2s1m2-mclk { + rockchip,pins = + /* i2s1m2_mclk */ + <2 RK_PD0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sclkrx: i2s1m2-sclkrx { + rockchip,pins = + /* i2s1m2_sclkrx */ + <3 RK_PC3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sclktx: i2s1m2-sclktx { + rockchip,pins = + /* i2s1m2_sclktx */ + <2 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi0: i2s1m2-sdi0 { + rockchip,pins = + /* i2s1m2_sdi0 */ + <2 RK_PD3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi1: i2s1m2-sdi1 { + rockchip,pins = + /* i2s1m2_sdi1 */ + <2 RK_PD4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi2: i2s1m2-sdi2 { + rockchip,pins = + /* i2s1m2_sdi2 */ + <2 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi3: i2s1m2-sdi3 { + rockchip,pins = + /* i2s1m2_sdi3 */ + <2 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo0: i2s1m2-sdo0 { + rockchip,pins = + /* i2s1m2_sdo0 */ + <2 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo1: i2s1m2-sdo1 { + rockchip,pins = + /* i2s1m2_sdo1 */ + <3 RK_PA0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo2: i2s1m2-sdo2 { + rockchip,pins = + /* i2s1m2_sdo2 */ + <3 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo3: i2s1m2-sdo3 { + rockchip,pins = + /* i2s1m2_sdo3 */ + <3 RK_PC2 5 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrckrx: i2s2m0-lrckrx { + rockchip,pins = + /* i2s2m0_lrckrx */ + <2 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_lrcktx: i2s2m0-lrcktx { + rockchip,pins = + /* i2s2m0_lrcktx */ + <2 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2m0_mclk */ + <2 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclkrx: i2s2m0-sclkrx { + rockchip,pins = + /* i2s2m0_sclkrx */ + <2 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclktx: i2s2m0-sclktx { + rockchip,pins = + /* i2s2m0_sclktx */ + <2 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2m0_sdi */ + <2 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2m0_sdo */ + <2 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrckrx: i2s2m1-lrckrx { + rockchip,pins = + /* i2s2m1_lrckrx */ + <4 RK_PA5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrcktx: i2s2m1-lrcktx { + rockchip,pins = + /* i2s2m1_lrcktx */ + <4 RK_PA4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + /* i2s2m1_mclk */ + <4 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclkrx: i2s2m1-sclkrx { + rockchip,pins = + /* i2s2m1_sclkrx */ + <4 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclktx: i2s2m1-sclktx { + rockchip,pins = + /* i2s2m1_sclktx */ + <4 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + /* i2s2m1_sdi */ + <4 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + /* i2s2m1_sdo */ + <4 RK_PB3 5 &pcfg_pull_none>; + }; + }; + + i2s3 { + /omit-if-no-ref/ + i2s3m0_lrck: i2s3m0-lrck { + rockchip,pins = + /* i2s3m0_lrck */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_mclk: i2s3m0-mclk { + rockchip,pins = + /* i2s3m0_mclk */ + <3 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sclk: i2s3m0-sclk { + rockchip,pins = + /* i2s3m0_sclk */ + <3 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sdi: i2s3m0-sdi { + rockchip,pins = + /* i2s3m0_sdi */ + <3 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sdo: i2s3m0-sdo { + rockchip,pins = + /* i2s3m0_sdo */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_lrck: i2s3m1-lrck { + rockchip,pins = + /* i2s3m1_lrck */ + <4 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_mclk: i2s3m1-mclk { + rockchip,pins = + /* i2s3m1_mclk */ + <4 RK_PC2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sclk: i2s3m1-sclk { + rockchip,pins = + /* i2s3m1_sclk */ + <4 RK_PC3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sdi: i2s3m1-sdi { + rockchip,pins = + /* i2s3m1_sdi */ + <4 RK_PC6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sdo: i2s3m1-sdo { + rockchip,pins = + /* i2s3m1_sdo */ + <4 RK_PC5 5 &pcfg_pull_none>; + }; + }; + + isp { + /omit-if-no-ref/ + isp_pins: isp-pins { + rockchip,pins = + /* isp_flashtrigin */ + <4 RK_PB4 4 &pcfg_pull_none>, + /* isp_flashtrigout */ + <4 RK_PA6 1 &pcfg_pull_none>, + /* isp_prelighttrig */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtag_pins: jtag-pins { + rockchip,pins = + /* jtag_tck */ + <1 RK_PD7 2 &pcfg_pull_none>, + /* jtag_tms */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + lcdc { + /omit-if-no-ref/ + lcdc_ctl: lcdc-ctl { + rockchip,pins = + /* lcdc_clk */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* lcdc_d0 */ + <2 RK_PD0 1 &pcfg_pull_none>, + /* lcdc_d1 */ + <2 RK_PD1 1 &pcfg_pull_none>, + /* lcdc_d2 */ + <2 RK_PD2 1 &pcfg_pull_none>, + /* lcdc_d3 */ + <2 RK_PD3 1 &pcfg_pull_none>, + /* lcdc_d4 */ + <2 RK_PD4 1 &pcfg_pull_none>, + /* lcdc_d5 */ + <2 RK_PD5 1 &pcfg_pull_none>, + /* lcdc_d6 */ + <2 RK_PD6 1 &pcfg_pull_none>, + /* lcdc_d7 */ + <2 RK_PD7 1 &pcfg_pull_none>, + /* lcdc_d8 */ + <3 RK_PA1 1 &pcfg_pull_none>, + /* lcdc_d9 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* lcdc_d16 */ + <3 RK_PB1 1 &pcfg_pull_none>, + /* lcdc_d17 */ + <3 RK_PB2 1 &pcfg_pull_none>, + /* lcdc_d18 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* lcdc_d19 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* lcdc_d20 */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* lcdc_d21 */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* lcdc_d22 */ + <3 RK_PB7 1 &pcfg_pull_none>, + /* lcdc_d23 */ + <3 RK_PC0 1 &pcfg_pull_none>, + /* lcdc_den */ + <3 RK_PC3 1 &pcfg_pull_none>, + /* lcdc_hsync */ + <3 RK_PC1 1 &pcfg_pull_none>, + /* lcdc_vsync */ + <3 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + mcu { + /omit-if-no-ref/ + mcu_pins: mcu-pins { + rockchip,pins = + /* mcu_jtagtck */ + <0 RK_PB4 4 &pcfg_pull_none>, + /* mcu_jtagtdi */ + <0 RK_PC1 4 &pcfg_pull_none>, + /* mcu_jtagtdo */ + <0 RK_PB3 4 &pcfg_pull_none>, + /* mcu_jtagtms */ + <0 RK_PC2 4 &pcfg_pull_none>, + /* mcu_jtagtrstn */ + <0 RK_PC3 4 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + pcie20 { + /omit-if-no-ref/ + pcie20m0_pins: pcie20m0-pins { + rockchip,pins = + /* pcie20_clkreqnm0 */ + <0 RK_PA5 3 &pcfg_pull_none>, + /* pcie20_perstnm0 */ + <0 RK_PB6 3 &pcfg_pull_none>, + /* pcie20_wakenm0 */ + <0 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m1_pins: pcie20m1-pins { + rockchip,pins = + /* pcie20_clkreqnm1 */ + <2 RK_PD0 4 &pcfg_pull_none>, + /* pcie20_perstnm1 */ + <3 RK_PC1 4 &pcfg_pull_none>, + /* pcie20_wakenm1 */ + <2 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m2_pins: pcie20m2-pins { + rockchip,pins = + /* pcie20_clkreqnm2 */ + <1 RK_PB0 4 &pcfg_pull_none>, + /* pcie20_perstnm2 */ + <1 RK_PB2 4 &pcfg_pull_none>, + /* pcie20_wakenm2 */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20_buttonrstn: pcie20-buttonrstn { + rockchip,pins = + /* pcie20_buttonrstn */ + <0 RK_PB4 3 &pcfg_pull_none>; + }; + }; + + pcie30x1 { + /omit-if-no-ref/ + pcie30x1m0_pins: pcie30x1m0-pins { + rockchip,pins = + /* pcie30x1_clkreqnm0 */ + <0 RK_PA4 3 &pcfg_pull_none>, + /* pcie30x1_perstnm0 */ + <0 RK_PC3 3 &pcfg_pull_none>, + /* pcie30x1_wakenm0 */ + <0 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_pins: pcie30x1m1-pins { + rockchip,pins = + /* pcie30x1_clkreqnm1 */ + <2 RK_PD2 4 &pcfg_pull_none>, + /* pcie30x1_perstnm1 */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* pcie30x1_wakenm1 */ + <2 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_pins: pcie30x1m2-pins { + rockchip,pins = + /* pcie30x1_clkreqnm2 */ + <1 RK_PA5 4 &pcfg_pull_none>, + /* pcie30x1_perstnm2 */ + <1 RK_PA2 4 &pcfg_pull_none>, + /* pcie30x1_wakenm2 */ + <1 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_buttonrstn: pcie30x1-buttonrstn { + rockchip,pins = + /* pcie30x1_buttonrstn */ + <0 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + /omit-if-no-ref/ + pcie30x2m0_pins: pcie30x2m0-pins { + rockchip,pins = + /* pcie30x2_clkreqnm0 */ + <0 RK_PA6 2 &pcfg_pull_none>, + /* pcie30x2_perstnm0 */ + <0 RK_PC6 3 &pcfg_pull_none>, + /* pcie30x2_wakenm0 */ + <0 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + /* pcie30x2_clkreqnm1 */ + <2 RK_PD4 4 &pcfg_pull_none>, + /* pcie30x2_perstnm1 */ + <2 RK_PD6 4 &pcfg_pull_none>, + /* pcie30x2_wakenm1 */ + <2 RK_PD5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_pins: pcie30x2m2-pins { + rockchip,pins = + /* pcie30x2_clkreqnm2 */ + <4 RK_PC2 4 &pcfg_pull_none>, + /* pcie30x2_perstnm2 */ + <4 RK_PC4 4 &pcfg_pull_none>, + /* pcie30x2_wakenm2 */ + <4 RK_PC3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2_buttonrstn: pcie30x2-buttonrstn { + rockchip,pins = + /* pcie30x2_buttonrstn */ + <0 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdmm0_clk: pdmm0-clk { + rockchip,pins = + /* pdm_clk0m0 */ + <1 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_clk1: pdmm0-clk1 { + rockchip,pins = + /* pdmm0_clk1 */ + <1 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins = + /* pdmm0_sdi0 */ + <1 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins = + /* pdmm0_sdi1 */ + <1 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins = + /* pdmm0_sdi2 */ + <1 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins = + /* pdmm0_sdi3 */ + <1 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk: pdmm1-clk { + rockchip,pins = + /* pdm_clk0m1 */ + <3 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk1: pdmm1-clk1 { + rockchip,pins = + /* pdmm1_clk1 */ + <4 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi0: pdmm1-sdi0 { + rockchip,pins = + /* pdmm1_sdi0 */ + <3 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi1: pdmm1-sdi1 { + rockchip,pins = + /* pdmm1_sdi1 */ + <4 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi2: pdmm1-sdi2 { + rockchip,pins = + /* pdmm1_sdi2 */ + <4 RK_PA2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi3: pdmm1-sdi3 { + rockchip,pins = + /* pdmm1_sdi3 */ + <4 RK_PA3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_clk1: pdmm2-clk1 { + rockchip,pins = + /* pdmm2_clk1 */ + <3 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi0: pdmm2-sdi0 { + rockchip,pins = + /* pdmm2_sdi0 */ + <3 RK_PB3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi1: pdmm2-sdi1 { + rockchip,pins = + /* pdmm2_sdi1 */ + <3 RK_PB4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi2: pdmm2-sdi2 { + rockchip,pins = + /* pdmm2_sdi2 */ + <3 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi3: pdmm2-sdi3 { + rockchip,pins = + /* pdmm2_sdi3 */ + <3 RK_PC0 5 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_pins: pmic-pins { + rockchip,pins = + /* pmic_sleep */ + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug0 */ + <0 RK_PA5 4 &pcfg_pull_none>, + /* pmu_debug1 */ + <0 RK_PA6 3 &pcfg_pull_none>, + /* pmu_debug2 */ + <0 RK_PC4 4 &pcfg_pull_none>, + /* pmu_debug3 */ + <0 RK_PC5 4 &pcfg_pull_none>, + /* pmu_debug4 */ + <0 RK_PC6 4 &pcfg_pull_none>, + /* pmu_debug5 */ + <0 RK_PC7 4 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <0 RK_PC7 2 &pcfg_pull_none>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <0 RK_PB5 4 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <0 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3_pins: pwm3-pins { + rockchip,pins = + /* pwm3_ir */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4_pins: pwm4-pins { + rockchip,pins = + /* pwm4 */ + <0 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5_pins: pwm5-pins { + rockchip,pins = + /* pwm5 */ + <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6_pins: pwm6-pins { + rockchip,pins = + /* pwm6 */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7_pins: pwm7-pins { + rockchip,pins = + /* pwm7_ir */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PB1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <1 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <1 RK_PD6 4 &pcfg_pull_none>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <3 RK_PB5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_irm0 */ + <3 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_irm1 */ + <4 RK_PC0 3 &pcfg_pull_none>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <3 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <4 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <4 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <4 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_irm0 */ + <3 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_irm1 */ + <4 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + refclk { + /omit-if-no-ref/ + refclk_pins: refclk-pins { + rockchip,pins = + /* refclk_ou */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + sata { + /omit-if-no-ref/ + sata_pins: sata-pins { + rockchip,pins = + /* sata_cpdet */ + <0 RK_PA4 2 &pcfg_pull_none>, + /* sata_cppod */ + <0 RK_PA6 1 &pcfg_pull_none>, + /* sata_mpswitch */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + sata0 { + /omit-if-no-ref/ + sata0_pins: sata0-pins { + rockchip,pins = + /* sata0_actled */ + <4 RK_PC6 3 &pcfg_pull_none>; + }; + }; + + sata1 { + /omit-if-no-ref/ + sata1_pins: sata1-pins { + rockchip,pins = + /* sata1_actled */ + <4 RK_PC5 3 &pcfg_pull_none>; + }; + }; + + sata2 { + /omit-if-no-ref/ + sata2_pins: sata2-pins { + rockchip,pins = + /* sata2_actled */ + <4 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + scr { + /omit-if-no-ref/ + scr_pins: scr-pins { + rockchip,pins = + /* scr_clk */ + <1 RK_PA2 3 &pcfg_pull_none>, + /* scr_det */ + <1 RK_PA7 3 &pcfg_pull_up>, + /* scr_io */ + <1 RK_PA3 3 &pcfg_pull_up>, + /* scr_rst */ + <1 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + /* sdmmc0_det */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = + /* sdmmc0_pwren */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + /* sdmmc1_det */ + <2 RK_PB2 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + /* sdmmc1_pwren */ + <2 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + sdmmc2 { + /omit-if-no-ref/ + sdmmc2m0_bus4: sdmmc2m0-bus4 { + rockchip,pins = + /* sdmmc2_d0m0 */ + <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m0 */ + <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m0 */ + <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m0 */ + <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_clk: sdmmc2m0-clk { + rockchip,pins = + /* sdmmc2_clkm0 */ + <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_cmd: sdmmc2m0-cmd { + rockchip,pins = + /* sdmmc2_cmdm0 */ + <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_det: sdmmc2m0-det { + rockchip,pins = + /* sdmmc2_detm0 */ + <3 RK_PD4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc2m0_pwren: sdmmc2m0-pwren { + rockchip,pins = + /* sdmmc2m0_pwren */ + <3 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sdmmc2m1_bus4: sdmmc2m1-bus4 { + rockchip,pins = + /* sdmmc2_d0m1 */ + <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m1 */ + <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m1 */ + <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m1 */ + <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_clk: sdmmc2m1-clk { + rockchip,pins = + /* sdmmc2_clkm1 */ + <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_cmd: sdmmc2m1-cmd { + rockchip,pins = + /* sdmmc2_cmdm1 */ + <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_det: sdmmc2m1-det { + rockchip,pins = + /* sdmmc2_detm1 */ + <3 RK_PA7 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc2m1_pwren: sdmmc2m1-pwren { + rockchip,pins = + /* sdmmc2m1_pwren */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_tx: spdifm0-tx { + rockchip,pins = + /* spdifm0_tx */ + <1 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_tx: spdifm1-tx { + rockchip,pins = + /* spdifm1_tx */ + <3 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_tx: spdifm2-tx { + rockchip,pins = + /* spdifm2_tx */ + <4 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins = + /* spi0_clkm0 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* spi0_misom0 */ + <0 RK_PC5 2 &pcfg_pull_none>, + /* spi0_mosim0 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0m0 */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1m0 */ + <0 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins = + /* spi0_clkm1 */ + <2 RK_PD3 3 &pcfg_pull_none>, + /* spi0_misom1 */ + <2 RK_PD0 3 &pcfg_pull_none>, + /* spi0_mosim1 */ + <2 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0m1 */ + <2 RK_PD2 3 &pcfg_pull_none>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins = + /* spi1_clkm0 */ + <2 RK_PB5 3 &pcfg_pull_none>, + /* spi1_misom0 */ + <2 RK_PB6 3 &pcfg_pull_none>, + /* spi1_mosim0 */ + <2 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_cs0: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0m0 */ + <2 RK_PC0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_cs1: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1m0 */ + <2 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_none>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_none>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_cs0: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0m1 */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins = + /* spi2_clkm0 */ + <2 RK_PC1 4 &pcfg_pull_none>, + /* spi2_misom0 */ + <2 RK_PC2 4 &pcfg_pull_none>, + /* spi2_mosim0 */ + <2 RK_PC3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_cs0: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0m0 */ + <2 RK_PC4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_cs1: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1m0 */ + <2 RK_PC5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins = + /* spi2_clkm1 */ + <3 RK_PA0 3 &pcfg_pull_none>, + /* spi2_misom1 */ + <2 RK_PD7 3 &pcfg_pull_none>, + /* spi2_mosim1 */ + <2 RK_PD6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_cs0: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0m1 */ + <2 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_cs1: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1m1 */ + <2 RK_PD4 3 &pcfg_pull_none>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m0_pins: spi3m0-pins { + rockchip,pins = + /* spi3_clkm0 */ + <4 RK_PB3 4 &pcfg_pull_none>, + /* spi3_misom0 */ + <4 RK_PB0 4 &pcfg_pull_none>, + /* spi3_mosim0 */ + <4 RK_PB2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m0_cs0: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0m0 */ + <4 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m0_cs1: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1m0 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_pins: spi3m1-pins { + rockchip,pins = + /* spi3_clkm1 */ + <4 RK_PC2 2 &pcfg_pull_none>, + /* spi3_misom1 */ + <4 RK_PC5 2 &pcfg_pull_none>, + /* spi3_mosim1 */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_cs0: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0m1 */ + <4 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_cs1: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1m1 */ + <4 RK_PD1 2 &pcfg_pull_none>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm0_shut: tsadcm0-shut { + rockchip,pins = + /* tsadcm0_shut */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadcm1_shut: tsadcm1-shut { + rockchip,pins = + /* tsadcm1_shut */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shutorg: tsadc-shutorg { + rockchip,pins = + /* tsadc_shutorg */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <0 RK_PC0 3 &pcfg_pull_up>, + /* uart0_tx */ + <0 RK_PC1 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + /* uart0_ctsn */ + <0 RK_PC7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + /* uart0_rtsn */ + <0 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rxm0 */ + <2 RK_PB3 2 &pcfg_pull_up>, + /* uart1_txm0 */ + <2 RK_PB4 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <2 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rxm1 */ + <3 RK_PD7 4 &pcfg_pull_up>, + /* uart1_txm1 */ + <3 RK_PD6 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <4 RK_PC1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <4 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rxm0 */ + <0 RK_PD0 1 &pcfg_pull_up>, + /* uart2_txm0 */ + <0 RK_PD1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rxm1 */ + <1 RK_PD6 2 &pcfg_pull_up>, + /* uart2_txm1 */ + <1 RK_PD5 2 &pcfg_pull_up>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rxm0 */ + <1 RK_PA0 2 &pcfg_pull_up>, + /* uart3_txm0 */ + <1 RK_PA1 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m0_ctsn: uart3m0-ctsn { + rockchip,pins = + /* uart3m0_ctsn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m0_rtsn: uart3m0-rtsn { + rockchip,pins = + /* uart3m0_rtsn */ + <1 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rxm1 */ + <3 RK_PC0 4 &pcfg_pull_up>, + /* uart3_txm1 */ + <3 RK_PB7 4 &pcfg_pull_up>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rxm0 */ + <1 RK_PA4 2 &pcfg_pull_up>, + /* uart4_txm0 */ + <1 RK_PA6 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m0_ctsn: uart4m0-ctsn { + rockchip,pins = + /* uart4m0_ctsn */ + <1 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m0_rtsn: uart4m0-rtsn { + rockchip,pins = + /* uart4m0_rtsn */ + <1 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rxm1 */ + <3 RK_PB1 4 &pcfg_pull_up>, + /* uart4_txm1 */ + <3 RK_PB2 4 &pcfg_pull_up>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rxm0 */ + <2 RK_PA1 3 &pcfg_pull_up>, + /* uart5_txm0 */ + <2 RK_PA2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PD7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rxm1 */ + <3 RK_PC3 4 &pcfg_pull_up>, + /* uart5_txm1 */ + <3 RK_PC2 4 &pcfg_pull_up>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rxm0 */ + <2 RK_PA3 3 &pcfg_pull_up>, + /* uart6_txm0 */ + <2 RK_PA4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + /* uart6m0_ctsn */ + <2 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + /* uart6m0_rtsn */ + <2 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rxm1 */ + <1 RK_PD6 3 &pcfg_pull_up>, + /* uart6_txm1 */ + <1 RK_PD5 3 &pcfg_pull_up>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rxm0 */ + <2 RK_PA5 3 &pcfg_pull_up>, + /* uart7_txm0 */ + <2 RK_PA6 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <2 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <2 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rxm1 */ + <3 RK_PC5 4 &pcfg_pull_up>, + /* uart7_txm1 */ + <3 RK_PC4 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m2_xfer: uart7m2-xfer { + rockchip,pins = + /* uart7_rxm2 */ + <4 RK_PA3 4 &pcfg_pull_up>, + /* uart7_txm2 */ + <4 RK_PA2 4 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rxm0 */ + <2 RK_PC6 2 &pcfg_pull_up>, + /* uart8_txm0 */ + <2 RK_PC5 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + /* uart8m0_ctsn */ + <2 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + /* uart8m0_rtsn */ + <2 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rxm1 */ + <3 RK_PA0 4 &pcfg_pull_up>, + /* uart8_txm1 */ + <2 RK_PD7 4 &pcfg_pull_up>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rxm0 */ + <2 RK_PA7 3 &pcfg_pull_up>, + /* uart9_txm0 */ + <2 RK_PB0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + /* uart9m0_ctsn */ + <2 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + /* uart9m0_rtsn */ + <2 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rxm1 */ + <4 RK_PC6 4 &pcfg_pull_up>, + /* uart9_txm1 */ + <4 RK_PC5 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m2_xfer: uart9m2-xfer { + rockchip,pins = + /* uart9_rxm2 */ + <4 RK_PA5 4 &pcfg_pull_up>, + /* uart9_txm2 */ + <4 RK_PA4 4 &pcfg_pull_up>; + }; + }; + + vop { + /omit-if-no-ref/ + vopm0_pins: vopm0-pins { + rockchip,pins = + /* vop_pwmm0 */ + <0 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + vopm1_pins: vopm1-pins { + rockchip,pins = + /* vop_pwmm1 */ + <3 RK_PC4 2 &pcfg_pull_none>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + spi0-hs { + /omit-if-no-ref/ + spi0m0_pins_hs: spi0m0-pins { + rockchip,pins = + /* spi0_clkm0 */ + <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>, + /* spi0_misom0 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>, + /* spi0_mosim0 */ + <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs0_hs: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0m0 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs1_hs: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1m0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_pins_hs: spi0m1-pins { + rockchip,pins = + /* spi0_clkm1 */ + <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>, + /* spi0_misom1 */ + <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>, + /* spi0_mosim1 */ + <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_cs0_hs: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0m1 */ + <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi1-hs { + /omit-if-no-ref/ + spi1m0_pins_hs: spi1m0-pins { + rockchip,pins = + /* spi1_clkm0 */ + <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>, + /* spi1_misom0 */ + <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>, + /* spi1_mosim0 */ + <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs0_hs: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0m0 */ + <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs1_hs: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1m0 */ + <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_pins_hs: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_cs0_hs: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0m1 */ + <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi2-hs { + /omit-if-no-ref/ + spi2m0_pins_hs: spi2m0-pins { + rockchip,pins = + /* spi2_clkm0 */ + <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>, + /* spi2_misom0 */ + <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>, + /* spi2_mosim0 */ + <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs0_hs: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0m0 */ + <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs1_hs: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1m0 */ + <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_pins_hs: spi2m1-pins { + rockchip,pins = + /* spi2_clkm1 */ + <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>, + /* spi2_misom1 */ + <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>, + /* spi2_mosim1 */ + <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs0_hs: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0m1 */ + <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs1_hs: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1m1 */ + <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3-hs { + /omit-if-no-ref/ + spi3m0_pins_hs: spi3m0-pins { + rockchip,pins = + /* spi3_clkm0 */ + <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>, + /* spi3_misom0 */ + <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>, + /* spi3_mosim0 */ + <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs0_hs: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0m0 */ + <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs1_hs: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1m0 */ + <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_pins_hs: spi3m1-pins { + rockchip,pins = + /* spi3_clkm1 */ + <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>, + /* spi3_misom1 */ + <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>, + /* spi3_mosim1 */ + <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs0_hs: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0m1 */ + <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs1_hs: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1m1 */ + <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>; + }; + }; + + gmac-txd-level3 { + /omit-if-no-ref/ + gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>; + }; + }; + + gmac-txc-level2 { + /omit-if-no-ref/ + gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; + }; + }; +}; diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi new file mode 100644 index 0000000000..0f19d3f0c0 --- /dev/null +++ b/arch/arm/dts/rk3568.dtsi @@ -0,0 +1,1110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/clock/rk3568-cru.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,boot-mode.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "rockchip,rk3568"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + clocks = <&scmi_clk 0>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <900000 900000 1150000>; + clock-latency-ns = <40000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <900000 900000 1150000>; + opp-suspend; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <975000 975000 1150000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1050000 1050000 1150000>; + }; + + opp-1992000000 { + opp-hz = /bits/ 64 <1992000000>; + opp-microvolt = <1150000 1150000 1150000>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; + arm,no-tick-in-suspend; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + pinctrl-0 = <&clk32k_out0>; + pinctrl-names = "default"; + #clock-cells = <0>; + }; + + sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x0010f000 0x0 0x100>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x0010f000 0x100>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + }; + + usbdrd30: usbdrd { + compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "pipe_clk"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3: dwc3@fcc00000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfcc00000 0x0 0x400000>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_USB3OTG0>; + reset-names = "usb3-otg"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,xhci-trb-ent-quirk; + }; + }; + + usbhost30: usbhost { + compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, + <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "pipe_clk"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbhost_dwc3: dwc3@fd000000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfd000000 0x0 0x400000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_USB3OTG1>; + reset-names = "usb3-host"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,xhci-trb-ent-quirk; + }; + }; + + gic: interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ + <0x0 0xfd460000 0 0x80000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + mbi-alias = <0x0 0xfd100000>; + mbi-ranges = <296 24>; + msi-controller; + }; + + usb_host0_ehci: usb@fd800000 { + compatible = "generic-ehci"; + reg = <0x0 0xfd800000 0x0 0x40000>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>, <&usb2phy1>; + clock-names = "usbhost", "arbiter", "pclk", "utmi"; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@fd840000 { + compatible = "generic-ohci"; + reg = <0x0 0xfd840000 0x0 0x40000>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>, <&usb2phy1>; + clock-names = "usbhost", "arbiter", "pclk", "utmi"; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ehci: usb@fd880000 { + compatible = "generic-ehci"; + reg = <0x0 0xfd880000 0x0 0x40000>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>, <&usb2phy1>; + clock-names = "usbhost", "arbiter", "pclk", "utmi"; + phys = <&u2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ohci: usb@fd8c0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfd8c0000 0x0 0x40000>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>, <&usb2phy1>; + clock-names = "usbhost", "arbiter", "pclk", "utmi"; + phys = <&u2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb2phy0: usb2-phy@fe8a0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8a0000 0x0 0x10000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmucru CLK_USBPHY0_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + assigned-clocks = <&cru USB480M>; + assigned-clock-parents = <&usb2phy0>; + clock-output-names = "usb480m_phy"; + rockchip,usbgrf = <&usb2phy0_grf>; + status = "disabled"; + + u2phy0_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + usb2phy1: usb2-phy@fe8b0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8b0000 0x0 0x10000>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmucru CLK_USBPHY1_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + rockchip,usbgrf = <&usb2phy1_grf>; + status = "disabled"; + + u2phy1_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + combphy0_us: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "refclk", "apbclk", "pipe_clk"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <24000000>; + resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + status = "disabled"; + }; + + combphy1_usq: phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe830000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, + <&cru PCLK_PIPE>; + clock-names = "refclk", "apbclk", "pipe_clk"; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <24000000>; + resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + status = "disabled"; + }; + + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc70000 0x0 0x1000>; + }; + + pipe_phy_grf1: syscon@fdc80000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc80000 0x0 0x1000>; + }; + + pipe_phy_grf2: syscon@fdc90000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc90000 0x0 0x1000>; + }; + + usb2phy0_grf: syscon@fdca0000 { + compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; + reg = <0x0 0xfdca0000 0x0 0x8000>; + }; + + usb2phy1_grf: syscon@fdca8000 { + compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; + reg = <0x0 0xfdca8000 0x0 0x8000>; + }; + + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipegrf", "syscon"; + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + + pmugrf: syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc20000 0x0 0x10000>; + }; + + grf: syscon@fdc60000 { + compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc60000 0x0 0x10000>; + }; + + pmucru: clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x0 0xfdd00000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + rockchip,grf = <&grf>; + }; + + cru: clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x0 0xfdd20000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + rockchip,grf = <&grf>; + }; + + i2c0: i2c@fdd40000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfdd40000 0x0 0x1000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fdd50000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfdd50000 0x0 0x100>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 0>, <&dmac0 1>; + pinctrl-0 = <&uart0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + pwm0: pwm@fdd70000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70000 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm0m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@fdd70010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70010 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm1m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@fdd70020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70020 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm2m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@fdd70030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70030 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm3_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + sdmmc2: mmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe000000 0x0 0x4000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, + <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC2>; + reset-names = "reset"; + status = "disabled"; + }; + + gmac1: ethernet@fe010000 { + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe010000 0x0 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, + <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>, + <&cru PCLK_XPCS>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_refout", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref", + "pclk_xpcs"; + resets = <&cru SRST_A_GMAC1>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + gmac0: ethernet@fe2a0000 { + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe2a0000 0x0 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, + <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, + <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, + <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, + <&cru PCLK_XPCS>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_refout", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref", + "pclk_xpcs"; + resets = <&cru SRST_A_GMAC0>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + sdmmc0: mmc@fe2b0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, + <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc1: mmc@fe2c0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, + <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC1>; + reset-names = "reset"; + status = "disabled"; + }; + + sdhci: mmc@fe310000 { + compatible = "rockchip,rk3568-dwcmshc"; + reg = <0x0 0xfe310000 0x0 0x10000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + dmac0: dmac@fe530000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe530000 0x0 0x4000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_BUS>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + dmac1: dmac@fe550000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe550000 0x0 0x4000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_BUS>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + i2c1: i2c@fe5a0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5a0000 0x0 0x1000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c1_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@fe5b0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5b0000 0x0 0x1000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c2m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@fe5c0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5c0000 0x0 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c3m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@fe5d0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5d0000 0x0 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c4m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fe5e0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5e0000 0x0 0x1000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c5m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + wdt: watchdog@fe600000 { + compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; + reg = <0x0 0xfe600000 0x0 0x100>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; + clock-names = "tclk", "pclk"; + }; + + uart1: serial@fe650000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe650000 0x0 0x100>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + pinctrl-0 = <&uart1m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@fe660000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe660000 0x0 0x100>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 4>, <&dmac0 5>; + pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@fe670000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe670000 0x0 0x100>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 6>, <&dmac0 7>; + pinctrl-0 = <&uart3m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@fe680000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe680000 0x0 0x100>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 8>, <&dmac0 9>; + pinctrl-0 = <&uart4m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@fe690000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe690000 0x0 0x100>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 10>, <&dmac0 11>; + pinctrl-0 = <&uart5m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart6: serial@fe6a0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6a0000 0x0 0x100>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 12>, <&dmac0 13>; + pinctrl-0 = <&uart6m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart7: serial@fe6b0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6b0000 0x0 0x100>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 14>, <&dmac0 15>; + pinctrl-0 = <&uart7m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart8: serial@fe6c0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6c0000 0x0 0x100>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 16>, <&dmac0 17>; + pinctrl-0 = <&uart8m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart9: serial@fe6d0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6d0000 0x0 0x100>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 18>, <&dmac0 19>; + pinctrl-0 = <&uart9m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + pwm4: pwm@fe6e0000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0000 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm4_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@fe6e0010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0010 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm5_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@fe6e0020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0020 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm6_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@fe6e0030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0030 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm7_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm8: pwm@fe6f0000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0000 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm8m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm9: pwm@fe6f0010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0010 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm9m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm10: pwm@fe6f0020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0020 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm10m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm11: pwm@fe6f0030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0030 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm11m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm12: pwm@fe700000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700000 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm12m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm13: pwm@fe700010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700010 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm13m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm14: pwm@fe700020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700020 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm14m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm15: pwm@fe700030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700030 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm15m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + saradc: saradc@fe720000 { + compatible = "rockchip,rk3568-saradc"; + reg = <0x0 0xfe720000 0x0 0x100>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio0@fdd60000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfdd60000 0x0 0x100>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@fe740000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe740000 0x0 0x100>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@fe750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe750000 0x0 0x100>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@fe760000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe760000 0x0 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@fe770000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe770000 0x0 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3568-pinctrl.dtsi" diff --git a/arch/arm/dts/rockchip-pinconf.dtsi b/arch/arm/dts/rockchip-pinconf.dtsi new file mode 100644 index 0000000000..5c645437b5 --- /dev/null +++ b/arch/arm/dts/rockchip-pinconf.dtsi @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +&pinctrl { + /omit-if-no-ref/ + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { + bias-disable; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { + bias-disable; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { + bias-disable; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { + bias-disable; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 { + bias-disable; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 { + bias-disable; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 { + bias-disable; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 { + bias-disable; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 { + bias-disable; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 { + bias-disable; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 { + bias-disable; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 { + bias-disable; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 { + bias-disable; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 { + bias-pull-up; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 { + bias-pull-up; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 { + bias-pull-up; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 { + bias-pull-up; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 { + bias-pull-up; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 { + bias-pull-up; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 { + bias-pull-up; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 { + bias-pull-up; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 { + bias-pull-up; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { + bias-pull-down; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 { + bias-pull-down; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 { + bias-pull-down; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 { + bias-pull-down; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 { + bias-pull-down; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 { + bias-pull-down; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 { + bias-pull-down; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 { + bias-pull-down; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 { + bias-pull-down; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 { + bias-pull-down; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 { + bias-pull-down; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 { + bias-pull-down; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 { + bias-pull-down; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 { + bias-pull-down; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 { + bias-pull-down; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 { + bias-pull-down; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_smt: pcfg-pull-up-smt { + bias-pull-up; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_down_smt: pcfg-pull-down-smt { + bias-pull-down; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt { + bias-disable; + drive-strength = <0>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_output_high: pcfg-output-high { + output-high; + }; + + /omit-if-no-ref/ + pcfg_output_low: pcfg-output-low { + output-low; + }; +}; diff --git a/arch/arm/include/asm/atf_common.h b/arch/arm/include/asm/atf_common.h new file mode 100644 index 0000000000..56e2d3ffaa --- /dev/null +++ b/arch/arm/include/asm/atf_common.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * This is from the ARM TF Project, + * Repository: https://github.com/ARM-software/arm-trusted-firmware.git + * File: include/common/bl_common.h + * Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights + * reserved. + * Copyright (C) 2016-2017 Rockchip Electronic Co.,Ltd + */ + +#ifndef __BL_COMMON_H__ +#define __BL_COMMON_H__ + +#define ATF_PARAM_EP 0x01 +#define ATF_PARAM_IMAGE_BINARY 0x02 +#define ATF_PARAM_BL31 0x03 + +#define ATF_VERSION_1 0x01 + +#define ATF_EP_SECURE 0x0 +#define ATF_EP_NON_SECURE 0x1 + +#define MODE_RW_SHIFT 0x4 +#define MODE_RW_MASK 0x1 +#define MODE_RW_64 0x0 +#define MODE_RW_32 0x1 + +#define MODE_EL_SHIFT 0x2 +#define MODE_EL_MASK 0x3 +#define MODE_EL3 0x3 +#define MODE_EL2 0x2 +#define MODE_EL1 0x1 +#define MODE_EL0 0x0 + +#define MODE_SP_SHIFT 0x0 +#define MODE_SP_MASK 0x1 +#define MODE_SP_EL0 0x0 +#define MODE_SP_ELX 0x1 + +#define SPSR_DAIF_SHIFT 6 +#define SPSR_DAIF_MASK 0x0f + +#define SPSR_64(el, sp, daif) \ + (MODE_RW_64 << MODE_RW_SHIFT | \ + ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \ + ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \ + ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT) + +#define SPSR_FIQ (1 << 6) +#define SPSR_IRQ (1 << 7) +#define SPSR_SERROR (1 << 8) +#define SPSR_DEBUG (1 << 9) +#define SPSR_EXCEPTION_MASK (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG) + +#define DAIF_FIQ_BIT (1<<0) +#define DAIF_IRQ_BIT (1<<1) +#define DAIF_ABT_BIT (1<<2) +#define DAIF_DBG_BIT (1<<3) +#define DISABLE_ALL_EXECPTIONS \ + (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) + +#ifndef __ASSEMBLY__ + +/******************************************************************************* + * Structure used for telling the next BL how much of a particular type of + * memory is available for its use and how much is already used. + ******************************************************************************/ +struct aapcs64_params { + unsigned long arg0; + unsigned long arg1; + unsigned long arg2; + unsigned long arg3; + unsigned long arg4; + unsigned long arg5; + unsigned long arg6; + unsigned long arg7; +}; + +/*************************************************************************** + * This structure provides version information and the size of the + * structure, attributes for the structure it represents + ***************************************************************************/ +struct param_header { + uint8_t type; /* type of the structure */ + uint8_t version; /* version of this structure */ + uint16_t size; /* size of this structure in bytes */ + uint32_t attr; /* attributes: unused bits SBZ */ +}; + +/***************************************************************************** + * This structure represents the superset of information needed while + * switching exception levels. The only two mechanisms to do so are + * ERET & SMC. Security state is indicated using bit zero of header + * attribute + * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start + * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while + * processing SMC to jump to BL31. + *****************************************************************************/ +struct entry_point_info { + struct param_header h; + uintptr_t pc; + uint32_t spsr; + struct aapcs64_params args; +}; + +/***************************************************************************** + * Image info binary provides information from the image loader that + * can be used by the firmware to manage available trusted RAM. + * More advanced firmware image formats can provide additional + * information that enables optimization or greater flexibility in the + * common firmware code + *****************************************************************************/ +struct atf_image_info { + struct param_header h; + uintptr_t image_base; /* physical address of base of image */ + uint32_t image_size; /* bytes read from image file */ +}; + +/***************************************************************************** + * The image descriptor struct definition. + *****************************************************************************/ +struct image_desc { + /* Contains unique image id for the image. */ + unsigned int image_id; + /* + * This member contains Image state information. + * Refer IMAGE_STATE_XXX defined above. + */ + unsigned int state; + uint32_t copied_size; /* image size copied in blocks */ + struct atf_image_info atf_image_info; + struct entry_point_info ep_info; +}; + +/******************************************************************************* + * This structure represents the superset of information that can be passed to + * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be + * populated only if BL2 detects its presence. A pointer to a structure of this + * type should be passed in X0 to BL31's cold boot entrypoint. + * + * Use of this structure and the X0 parameter is not mandatory: the BL31 + * platform code can use other mechanisms to provide the necessary information + * about BL32 and BL33 to the common and SPD code. + * + * BL31 image information is mandatory if this structure is used. If either of + * the optional BL32 and BL33 image information is not provided, this is + * indicated by the respective image_info pointers being zero. + ******************************************************************************/ +struct bl31_params { + struct param_header h; + struct atf_image_info *bl31_image_info; + struct entry_point_info *bl32_ep_info; + struct atf_image_info *bl32_image_info; + struct entry_point_info *bl33_ep_info; + struct atf_image_info *bl33_image_info; +}; + +void bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry, + uintptr_t bl33_entry, uintptr_t fdt_addr); + +#endif /*__ASSEMBLY__ */ + +#endif /* __BL_COMMON_H__ */ diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h index 348a55e804..24f9bce2ef 100644 --- a/arch/arm/include/asm/barebox-arm.h +++ b/arch/arm/include/asm/barebox-arm.h @@ -53,6 +53,7 @@ void setup_c(void); void pbl_barebox_break(void); void relocate_to_current_adr(void); void relocate_to_adr(unsigned long target); +void relocate_to_adr_full(unsigned long target); void __noreturn barebox_arm_entry(unsigned long membase, unsigned long memsize, void *boarddata); struct barebox_arm_boarddata { diff --git a/arch/arm/lib64/Makefile b/arch/arm/lib64/Makefile index 69cb3d8ea1..a004af4867 100644 --- a/arch/arm/lib64/Makefile +++ b/arch/arm/lib64/Makefile @@ -6,5 +6,5 @@ obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memset.o string.o extra-y += barebox.lds obj-pbl-y += runtime-offset.o obj-pbl-y += setjmp.o - +obj-y += io.o pbl-y += div0.o pbl.o diff --git a/arch/arm/lib64/io.c b/arch/arm/lib64/io.c new file mode 100644 index 0000000000..fdf2117cc8 --- /dev/null +++ b/arch/arm/lib64/io.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Based on arch/arm/kernel/io.c + * + * Copyright (C) 2012 ARM Ltd. + */ + +#include <linux/export.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <io.h> + +/* + * Copy data from IO memory space to "real" memory space. + */ +void memcpy_fromio(void *to, const volatile void __iomem *from, size_t count) +{ + while (count && !IS_ALIGNED((unsigned long)from, 8)) { + *(u8 *)to = __raw_readb(from); + from++; + to++; + count--; + } + + while (count >= 8) { + *(u64 *)to = __raw_readq(from); + from += 8; + to += 8; + count -= 8; + } + + while (count) { + *(u8 *)to = __raw_readb(from); + from++; + to++; + count--; + } +} +EXPORT_SYMBOL(memcpy_fromio); + +/* + * Copy data from "real" memory space to IO memory space. + */ +void memcpy_toio(volatile void __iomem *to, const void *from, size_t count) +{ + while (count && !IS_ALIGNED((unsigned long)to, 8)) { + __raw_writeb(*(u8 *)from, to); + from++; + to++; + count--; + } + + while (count >= 8) { + __raw_writeq(*(u64 *)from, to); + from += 8; + to += 8; + count -= 8; + } + + while (count) { + __raw_writeb(*(u8 *)from, to); + from++; + to++; + count--; + } +} +EXPORT_SYMBOL(memcpy_toio); + +/* + * "memset" on IO memory space. + */ +void memset_io(volatile void __iomem *dst, int c, size_t count) +{ + u64 qc = (u8)c; + + qc |= qc << 8; + qc |= qc << 16; + qc |= qc << 32; + + while (count && !IS_ALIGNED((unsigned long)dst, 8)) { + __raw_writeb(c, dst); + dst++; + count--; + } + + while (count >= 8) { + __raw_writeq(qc, dst); + dst += 8; + count -= 8; + } + + while (count) { + __raw_writeb(c, dst); + dst++; + count--; + } +} +EXPORT_SYMBOL(memset_io); diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 65bcbcac96..2786fadeaf 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -13,11 +13,23 @@ config RK_TIMER config ARCH_RK3188 bool + select CPU_V7 + select ARM_SMP_TWD + select ARCH_HAS_L2X0 config ARCH_RK3288 bool + select CPU_V7 + select ARM_SMP_TWD + select ARCH_HAS_L2X0 select CLOCKSOURCE_ROCKCHIP +config ARCH_RK3568 + bool + select CPU_V8 + select ARM_ATF + select SYS_SUPPORTS_64BIT_KERNEL + comment "select Rockchip boards:" config MACH_RADXA_ROCK @@ -33,4 +45,16 @@ config MACH_PHYTEC_SOM_RK3288 help Say Y here if you are using a RK3288 based Phytecs SOM +config MACH_RK3568_EVB + select ARCH_RK3568 + bool "RK3568 EVB" + help + Say Y here if you are using a RK3568 EVB + endmenu + +config ARCH_RK3568_OPTEE + bool "Build OP-TEE binary into barebox" + help + With this option enabled the RK3568 OP-TEE binary is compiled + into barebox and started along with the BL31 trusted firmware. diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 0188d0252f..ebaa3a5450 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -1,3 +1,6 @@ obj-y += rockchip.o +pbl-$(CONFIG_ARCH_RK3568) += atf.o obj-$(CONFIG_ARCH_RK3188) += rk3188.o obj-$(CONFIG_ARCH_RK3288) += rk3288.o +obj-pbl-$(CONFIG_ARCH_RK3568) += rk3568.o +obj-$(CONFIG_ARCH_RK3568) += bootm.o diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c new file mode 100644 index 0000000000..3c4c9d1c8a --- /dev/null +++ b/arch/arm/mach-rockchip/atf.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <common.h> +#include <firmware.h> +#include <asm/system.h> +#include <mach/atf.h> +#include <elf.h> +#include <asm/atf_common.h> + +static unsigned long load_elf64_image_phdr(const void *elf) +{ + const Elf64_Ehdr *ehdr; /* Elf header structure pointer */ + const Elf64_Phdr *phdr; /* Program header structure pointer */ + int i; + + ehdr = elf; + phdr = elf + ehdr->e_phoff; + + /* Load each program header */ + for (i = 0; i < ehdr->e_phnum; ++i) { + void *dst = (void *)(ulong)phdr->p_paddr; + const void *src = elf + phdr->p_offset; + + pr_debug("Loading phdr %i to 0x%p (%lu bytes)\n", + i, dst, (ulong)phdr->p_filesz); + if (phdr->p_filesz) + memcpy(dst, src, phdr->p_filesz); + if (phdr->p_filesz != phdr->p_memsz) + memset(dst + phdr->p_filesz, 0x00, + phdr->p_memsz - phdr->p_filesz); + ++phdr; + } + + return ehdr->e_entry; +} + +void rk3568_atf_load_bl31(void *fdt) +{ + const void *bl31_elf, *optee; + unsigned long bl31; + size_t bl31_elf_size, optee_size; + uintptr_t optee_load_address = 0; + + get_builtin_firmware(rk3568_bl31_bin, &bl31_elf, &bl31_elf_size); + + bl31 = load_elf64_image_phdr(bl31_elf); + + if (IS_ENABLED(CONFIG_ARCH_RK3568_OPTEE)) { + optee_load_address = RK3568_OPTEE_LOAD_ADDRESS; + + get_builtin_firmware(rk3568_op_tee_bin, &optee, &optee_size); + + memcpy((void *)optee_load_address, optee, optee_size); + } + + /* Setup an initial stack for EL2 */ + asm volatile("msr sp_el2, %0" : : + "r" (RK3568_BAREBOX_LOAD_ADDRESS - 16) : + "cc"); + + bl31_entry(bl31, optee_load_address, + RK3568_BAREBOX_LOAD_ADDRESS, (uintptr_t)fdt); +} diff --git a/arch/arm/mach-rockchip/bootm.c b/arch/arm/mach-rockchip/bootm.c new file mode 100644 index 0000000000..5d6181ebd7 --- /dev/null +++ b/arch/arm/mach-rockchip/bootm.c @@ -0,0 +1,116 @@ +#define pr_fmt(fmt) "rockchip-bootm-barebox: " fmt + +#include <bootm.h> +#include <common.h> +#include <init.h> +#include <memory.h> + +struct newidb_entry { + uint32_t sector; + uint32_t unknown_ffffffff; + uint32_t unknown1; + uint32_t image_number; + unsigned char unknown2[8]; + unsigned char hash[64]; +}; + +struct newidb { + uint32_t magic; + unsigned char unknown1[4]; + uint32_t n_files; + uint32_t hashtype; + unsigned char unknown2[8]; + unsigned char unknown3[8]; + unsigned char unknown4[88]; + struct newidb_entry entries[4]; + unsigned char unknown5[40]; + unsigned char unknown6[512]; + unsigned char unknown7[16]; + unsigned char unknown8[32]; + unsigned char unknown9[464]; + unsigned char hash[512]; +}; + +#define SECTOR_SIZE 512 + +static int do_bootm_rkns_barebox_image(struct image_data *data) +{ + void (*barebox)(unsigned long x0, unsigned long x1, unsigned long x2, + unsigned long x3); + resource_size_t start, end; + struct newidb *idb; + int ret, i, n_files; + void *buf; + resource_size_t image_size; + + ret = memory_bank_first_find_space(&start, &end); + if (ret) + return ret; + + ret = bootm_load_os(data, start); + if (ret) + return ret; + + idb = (void *)data->os_res->start; + buf = (void *)data->os_res->start; + + image_size = resource_size(data->os_res); + + if (image_size < SECTOR_SIZE) + return -EINVAL; + + n_files = idb->n_files >> 16; + if (n_files > 4) + n_files = 4; + + if (data->verbose) + printf("RKNS image contains %d binaries:\n", n_files); + + for (i = 0; i < n_files; i++) { + struct newidb_entry *entry = &idb->entries[i]; + unsigned int entry_size = (entry->sector >> 16) * SECTOR_SIZE; + unsigned int entry_start = (entry->sector & 0xffff) * SECTOR_SIZE; + enum filetype filetype; + + filetype = file_detect_type(buf + entry_start, SECTOR_SIZE); + + if (entry_start + entry_size > image_size) { + printf("image %d expands outside the image\n", i); + continue; + } + + if (data->verbose) + printf("image %d: size: %d offset: %d type: %s\n", + i, entry_size, entry_start, + file_type_to_string(filetype)); + + if (filetype == filetype_arm_barebox) { + barebox = buf + entry_start; + goto found; + } + } + + return -EIO; + +found: + + printf("Starting barebox image at 0x%p\n", barebox); + + shutdown_barebox(); + + barebox(0, 0, 0, 0); + + return -EINVAL; +} + +static struct image_handler image_handler_rkns_barebox_image = { + .name = "Rockchip RKNS barebox image", + .bootm = do_bootm_rkns_barebox_image, + .filetype = filetype_rockchip_rkns_image, +}; + +static int rockchip_register_barebox_image_handler(void) +{ + return register_image_handler(&image_handler_rkns_barebox_image); +} +late_initcall(rockchip_register_barebox_image_handler); diff --git a/arch/arm/mach-rockchip/include/mach/atf.h b/arch/arm/mach-rockchip/include/mach/atf.h new file mode 100644 index 0000000000..337a8261c8 --- /dev/null +++ b/arch/arm/mach-rockchip/include/mach/atf.h @@ -0,0 +1,18 @@ +#ifndef __MACH_ATF_H +#define __MACH_ATF_H + +/* First usable DRAM address. Lower mem is used for ATF and OP-TEE */ +#define RK3568_DRAM_BOTTOM 0xa00000 + +/* OP-TEE expects to be loaded here */ +#define RK3568_OPTEE_LOAD_ADDRESS 0x200000 + +/* + * board lowlevel code should relocate barebox here. This is where + * OP-TEE jumps to after initialization. + */ +#define RK3568_BAREBOX_LOAD_ADDRESS (RK3568_DRAM_BOTTOM + 1024*1024) + +void rk3568_atf_load_bl31(void *fdt); + +#endif /* __MACH_ATF_H */ diff --git a/arch/arm/mach-rockchip/include/mach/bbu.h b/arch/arm/mach-rockchip/include/mach/bbu.h new file mode 100644 index 0000000000..e61e0615e2 --- /dev/null +++ b/arch/arm/mach-rockchip/include/mach/bbu.h @@ -0,0 +1,14 @@ +#ifndef __MACH_ROCKCHIP_BBU_H +#define __MACH_ROCKCHIP_BBU_H + +#include <bbu.h> + +static inline int rk3568_bbu_mmc_register(const char *name, unsigned long flags, + const char *devicefile) +{ + return bbu_register_std_file_update(name, flags, + devicefile, filetype_rockchip_rkns_image); + +} + +# endif /* __MACH_ROCKCHIP_BBU_H */ diff --git a/arch/arm/mach-rockchip/include/mach/debug_ll.h b/arch/arm/mach-rockchip/include/mach/debug_ll.h index 7806aab8bb..af6257a674 100644 --- a/arch/arm/mach-rockchip/include/mach/debug_ll.h +++ b/arch/arm/mach-rockchip/include/mach/debug_ll.h @@ -5,6 +5,7 @@ #include <io.h> #include <mach/rk3188-regs.h> #include <mach/rk3288-regs.h> +#include <mach/rk3568-regs.h> #ifdef CONFIG_DEBUG_LL @@ -22,6 +23,13 @@ #define serial_out(a, v) writel(v, a) #define serial_in(a) readl(a) +#elif defined CONFIG_DEBUG_ROCKCHIP_RK3568_UART + +#define UART_CLOCK 24000000 +#define RK_DEBUG_SOC RK3568 +#define serial_out(a, v) writel(v, a) +#define serial_in(a) readl(a) + #endif #define __RK_UART_BASE(soc, num) soc##_UART##num##_BASE diff --git a/arch/arm/mach-rockchip/include/mach/rk3568-regs.h b/arch/arm/mach-rockchip/include/mach/rk3568-regs.h new file mode 100644 index 0000000000..bb2ca7bd90 --- /dev/null +++ b/arch/arm/mach-rockchip/include/mach/rk3568-regs.h @@ -0,0 +1,18 @@ +#ifndef __MACH_RK3568_REGS_H +#define __MACH_RK3568_REGS_H + +/* UART */ +#define RK3568_UART0_BASE 0xfdd50000 +#define RK3568_UART1_BASE 0xfe650000 +#define RK3568_UART2_BASE 0xfe660000 +#define RK3568_UART3_BASE 0xfe670000 +#define RK3568_UART4_BASE 0xfe680000 +#define RK3568_UART5_BASE 0xfe690000 +#define RK3568_UART6_BASE 0xfe6a0000 +#define RK3568_UART7_BASE 0xfe6b0000 +#define RK3568_UART8_BASE 0xfe6c0000 +#define RK3568_UART9_BASE 0xfe6d0000 + +#define RK3568_IRAM_BASE 0xfdcc0000 + +#endif /* __MACH_RK3568_REGS_H */ diff --git a/arch/arm/mach-rockchip/include/mach/rockchip.h b/arch/arm/mach-rockchip/include/mach/rockchip.h index 8d37c67d4f..722b73d6f8 100644 --- a/arch/arm/mach-rockchip/include/mach/rockchip.h +++ b/arch/arm/mach-rockchip/include/mach/rockchip.h @@ -19,4 +19,15 @@ static inline int rk3288_init(void) } #endif +#ifdef CONFIG_ARCH_RK3568 +int rk3568_init(void); +#else +static inline int rk3568_init(void) +{ + return -ENOTSUPP; +} +#endif + +int rk3568_lowlevel_init(void); + #endif /* __MACH_ROCKCHIP_H */ diff --git a/arch/arm/mach-rockchip/rk3568.c b/arch/arm/mach-rockchip/rk3568.c new file mode 100644 index 0000000000..fcf3cb7053 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3568.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <io.h> +#include <bootsource.h> +#include <mach/rk3568-regs.h> +#include <mach/rockchip.h> + +#define GRF_BASE 0xfdc60000 +#define GRF_GPIO1B_DS_2 0x218 +#define GRF_GPIO1B_DS_3 0x21c +#define GRF_GPIO1C_DS_0 0x220 +#define GRF_GPIO1C_DS_1 0x224 +#define GRF_GPIO1C_DS_2 0x228 +#define GRF_GPIO1C_DS_3 0x22c +#define GRF_GPIO1D_DS_0 0x230 +#define GRF_GPIO1D_DS_1 0x234 +#define GRF_SOC_CON4 0x510 +#define EDP_PHY_GRF_BASE 0xfdcb0000 +#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00) +#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28) +#define PMU_BASE_ADDR 0xfdd90000 +#define PMU_NOC_AUTO_CON0 0x70 +#define PMU_NOC_AUTO_CON1 0x74 +#define CRU_BASE 0xfdd20000 +#define CRU_SOFTRST_CON26 0x468 +#define CRU_SOFTRST_CON28 0x470 +#define SGRF_BASE 0xFDD18000 +#define SGRF_SOC_CON3 0xC +#define SGRF_SOC_CON4 0x10 +#define PMUGRF_SOC_CON15 0xfdc20100 +#define CPU_GRF_BASE 0xfdc30000 +#define GRF_CORE_PVTPLL_CON0 0x10 +#define USBPHY_U3_GRF 0xfdca0000 +#define USBPHY_U3_GRF_CON1 (USBPHY_U3_GRF + 0x04) +#define USBPHY_U2_GRF 0xfdca8000 +#define USBPHY_U2_GRF_CON0 (USBPHY_U2_GRF + 0x00) +#define USBPHY_U2_GRF_CON1 (USBPHY_U2_GRF + 0x04) + +#define PMU_PWR_GATE_SFTCON 0xA0 +#define PMU_PWR_DWN_ST 0x98 +#define PMU_BUS_IDLE_SFTCON0 0x50 +#define PMU_BUS_IDLE_ST 0x68 +#define PMU_BUS_IDLE_ACK 0x60 + +#define EBC_PRIORITY_REG 0xfe158008 + +static void qos_priority_init(void) +{ + u32 delay; + + /* enable all pd except npu and gpu */ + writel(0xffff0000 & ~(BIT(0 + 16) | BIT(1 + 16)), + PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON); + delay = 1000; + do { + udelay(1); + delay--; + if (delay == 0) { + printf("Fail to set domain."); + hang(); + } + } while (readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST) & ~(BIT(0) | BIT(1))); + + /* release all idle request except npu and gpu */ + writel(0xffff0000 & ~(BIT(1 + 16) | BIT(2 + 16)), + PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON0); + + delay = 1000; + /* wait ack status */ + do { + udelay(1); + delay--; + if (delay == 0) { + printf("Fail to get ack on domain.\n"); + hang(); + } + } while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK) & ~(BIT(1) | BIT(2))); + + delay = 1000; + /* wait idle status */ + do { + udelay(1); + delay--; + if (delay == 0) { + printf("Fail to set idle on domain.\n"); + hang(); + } + } while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST) & ~(BIT(1) | BIT(2))); + + writel(0x303, EBC_PRIORITY_REG); +} + +int rk3568_lowlevel_init(void) +{ + /* + * When perform idle operation, corresponding clock can + * be opened or gated automatically. + */ + writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0); + writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1); + + /* Set the emmc sdmmc0 to secure */ + writel(((0x3 << 11 | 0x1 << 4) << 16), SGRF_BASE + SGRF_SOC_CON4); + /* set the emmc ds to level 2 */ + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3); + + /* Set the fspi to secure */ + writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3); + + /* Disable eDP phy by default */ + writel(0x00070007, EDP_PHY_GRF_CON10); + writel(0x0ff10ff1, EDP_PHY_GRF_CON0); + + /* Set core pvtpll ring length */ + writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0); + + /* + * Assert reset the pipephy0, pipephy1 and pipephy2, + * and de-assert reset them in Kernel combphy driver. + */ + writel(0x02a002a0, CRU_BASE + CRU_SOFTRST_CON28); + + /* + * Set USB 2.0 PHY0 port1 and PHY1 port0 and port1 + * enter suspend mode to to save power. And USB 2.0 + * PHY0 port0 for OTG interface still in normal mode. + */ + writel(0x01ff01d1, USBPHY_U3_GRF_CON1); + writel(0x01ff01d1, USBPHY_U2_GRF_CON0); + writel(0x01ff01d1, USBPHY_U2_GRF_CON1); + + qos_priority_init(); + + return 0; +} + +struct rk_bootsource { + enum bootsource src; + int instance; +}; + +static struct rk_bootsource bootdev_map[] = { + { .src = BOOTSOURCE_UNKNOWN, .instance = 0 }, + { .src = BOOTSOURCE_NAND, .instance = 0 }, + { .src = BOOTSOURCE_MMC, .instance = 0 }, + { .src = BOOTSOURCE_SPI_NOR, .instance = 0 }, + { .src = BOOTSOURCE_SPI_NAND, .instance = 0 }, + { .src = BOOTSOURCE_MMC, .instance = 1 }, +}; + +static enum bootsource rk3568_bootsource(void) +{ + u32 v; + + v = readl(RK3568_IRAM_BASE + 0x10); + + if (v >= ARRAY_SIZE(bootdev_map)) + return BOOTSOURCE_UNKNOWN; + + bootsource_set(bootdev_map[v].src); + bootsource_set_instance(bootdev_map[v].instance); + + return bootdev_map[v].src; +} + +int rk3568_init(void) +{ + rk3568_bootsource(); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index b0fbb49457..f0b2484c68 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -9,6 +9,8 @@ static int rockchip_init(void) rk3188_init(); else if (of_machine_is_compatible("rockchip,rk3288")) rk3288_init(); + else if (of_machine_is_compatible("rockchip,rk3568")) + rk3568_init(); else pr_err("Unknown rockchip SoC\n"); diff --git a/commands/clk.c b/commands/clk.c index 2e21e9df58..4d124807bd 100644 --- a/commands/clk.c +++ b/commands/clk.c @@ -54,19 +54,14 @@ BAREBOX_CMD_END static int do_clk_set_rate(int argc, char *argv[]) { - struct clk *clk; unsigned long rate; if (argc != 3) return COMMAND_ERROR_USAGE; - clk = clk_lookup(argv[1]); - if (IS_ERR(clk)) - return PTR_ERR(clk); - rate = simple_strtoul(argv[2], NULL, 0); - return clk_set_rate(clk, rate); + return clk_name_set_rate(argv[1], rate); } BAREBOX_CMD_HELP_START(clk_set_rate) @@ -214,19 +209,10 @@ BAREBOX_CMD_END static int do_clk_set_parent(int argc, char *argv[]) { - struct clk *clk, *parent; - if (argc != 3) return COMMAND_ERROR_USAGE; - clk = clk_lookup(argv[1]); - if (IS_ERR(clk)) - return PTR_ERR(clk); - parent = clk_lookup(argv[2]); - if (IS_ERR(parent)) - return PTR_ERR(parent); - - return clk_set_parent(clk, parent); + return clk_name_set_parent(argv[1], argv[2]); } BAREBOX_CMD_START(clk_set_parent) diff --git a/common/Kconfig b/common/Kconfig index 2d7888b9fa..9c9e0525e2 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1331,6 +1331,13 @@ config DEBUG_ROCKCHIP_RK3288_UART Say Y here if you want kernel low-level debugging support on RK3288. +config DEBUG_ROCKCHIP_RK3568_UART + bool "RK3568 Debug UART" + depends on ARCH_RK3568 + help + Say Y here if you want kernel low-level debugging support + on RK3568. + config DEBUG_SOCFPGA_UART0 bool "Use SOCFPGA UART0 for low-level debug" depends on ARCH_SOCFPGA @@ -1428,7 +1435,8 @@ config DEBUG_OMAP_UART_PORT config DEBUG_ROCKCHIP_UART_PORT int "RK3xxx UART debug port" if DEBUG_ROCKCHIP_RK3188_UART || \ - DEBUG_ROCKCHIP_RK3288_UART + DEBUG_ROCKCHIP_RK3288_UART || \ + DEBUG_ROCKCHIP_RK3568_UART default 2 depends on ARCH_ROCKCHIP help diff --git a/common/filetype.c b/common/filetype.c index 0cae00abaa..9edebb2cd8 100644 --- a/common/filetype.c +++ b/common/filetype.c @@ -73,6 +73,7 @@ static const struct filetype_str filetype_str[] = { [filetype_stm32_image_v1] = { "STM32 image (v1)", "stm32-image-v1" }, [filetype_zynq_image] = { "Zynq image", "zynq-image" }, [filetype_mxs_sd_image] = { "i.MX23/28 SD card image", "mxs-sd-image" }, + [filetype_rockchip_rkns_image] = { "Rockchip boot image", "rk-image" }, }; const char *file_type_to_string(enum filetype f) @@ -309,6 +310,8 @@ enum filetype file_detect_type(const void *_buf, size_t bufsize) return filetype_riscv_linux_image; if (le32_to_cpu(buf[14]) == 0x56435352 && !memcmp(&buf[12], "barebox", 8)) return filetype_riscv_barebox_image; + if (strncmp(buf8, "RKNS", 4) == 0) + return filetype_rockchip_rkns_image; if ((buf8[0] == 0x5a || buf8[0] == 0x69 || buf8[0] == 0x78 || buf8[0] == 0x8b || buf8[0] == 0x9c) && buf8[0x1] == 0 && buf8[0x2] == 0 && buf8[0x3] == 0 && diff --git a/drivers/aiodev/Kconfig b/drivers/aiodev/Kconfig index 88d013aad0..03c688ae61 100644 --- a/drivers/aiodev/Kconfig +++ b/drivers/aiodev/Kconfig @@ -50,4 +50,12 @@ config STM32_ADC Support for ADC on STM32. Supports simple one-shot readings rather than continuous sampling with DMA, etc. ADC channels should be configured via device tree, using the kernel bindings. + +config ROCKCHIP_SARADC + tristate "Rockchip SARADC driver" + depends on ARCH_RK3568 || COMPILE_TEST + depends on OFDEVICE + help + Support for Successive Approximation Register (SAR) ADC in Rockchip + SoCs. endif diff --git a/drivers/aiodev/Makefile b/drivers/aiodev/Makefile index 52652f67b7..1b480f6fa3 100644 --- a/drivers/aiodev/Makefile +++ b/drivers/aiodev/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_MC13XXX_ADC) += mc13xxx_adc.o obj-$(CONFIG_QORIQ_THERMAL) += qoriq_thermal.o obj-$(CONFIG_AM335X_ADC) += am335x_adc.o obj-$(CONFIG_STM32_ADC) += stm32-adc.o stm32-adc-core.o +obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o diff --git a/drivers/aiodev/rockchip_saradc.c b/drivers/aiodev/rockchip_saradc.c new file mode 100644 index 0000000000..302f73c2c3 --- /dev/null +++ b/drivers/aiodev/rockchip_saradc.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021, WolfVision GmbH + * Author: Michael Riesch <michael.riesch@wolfvision.net> + * + * Originally based on the Linux kernel v5.12 drivers/iio/adc/rockchip-saradc.c. + */ + +#include <common.h> +#include <aiodev.h> +#include <linux/clk.h> +#include <regulator.h> + +#define SARADC_DATA 0x00 + +#define SARADC_CTRL 0x08 +#define SARADC_CTRL_IRQ_STATUS (1 << 6) +#define SARADC_CTRL_IRQ_ENABLE (1 << 5) +#define SARADC_CTRL_POWER_CTRL (1 << 3) +#define SARADC_CTRL_CHN_MASK 0x07 + +#define SARADC_DLY_PU_SOC 0x0c + +#define SARADC_TIMEOUT_NS (100 * MSECOND) + +struct rockchip_saradc_cfg { + unsigned int num_bits; + unsigned int num_channels; +}; + +struct rockchip_saradc_data { + const struct rockchip_saradc_cfg *config; + void __iomem *base; + struct regulator *vref; + unsigned int ref_voltage_mv; + struct clk *cclk; + struct clk *pclk; + struct aiodevice aiodev; + struct aiochannel *channels; +}; + +static inline void rockchip_saradc_reg_wr(struct rockchip_saradc_data *data, + u32 value, u32 reg) +{ + writel(value, data->base + reg); +} + +static inline u32 rockchip_saradc_reg_rd(struct rockchip_saradc_data *data, + u32 reg) +{ + return readl(data->base + reg); +} + +static int rockchip_saradc_read(struct aiochannel *chan, int *val) +{ + struct rockchip_saradc_data *data; + u32 value = 0; + u32 control = 0; + u32 mask; + u64 start; + + data = container_of(chan->aiodev, struct rockchip_saradc_data, aiodev); + + rockchip_saradc_reg_wr(data, 8, SARADC_DLY_PU_SOC); + rockchip_saradc_reg_wr(data, + (chan->index & SARADC_CTRL_CHN_MASK) | + SARADC_CTRL_IRQ_ENABLE | + SARADC_CTRL_POWER_CTRL, + SARADC_CTRL); + + start = get_time_ns(); + do { + control = rockchip_saradc_reg_rd(data, SARADC_CTRL); + + if (is_timeout(start, SARADC_TIMEOUT_NS)) + return -ETIMEDOUT; + } while (!(control & SARADC_CTRL_IRQ_STATUS)); + + mask = (1 << data->config->num_bits) - 1; + value = rockchip_saradc_reg_rd(data, SARADC_DATA) & mask; + rockchip_saradc_reg_wr(data, 0, SARADC_CTRL); + + *val = (value * data->ref_voltage_mv) / mask; + + return 0; +} + +static int rockchip_saradc_probe(struct device_d *dev) +{ + struct rockchip_saradc_data *data; + int i, ret; + + data = xzalloc(sizeof(struct rockchip_saradc_data)); + + data->config = device_get_match_data(dev); + data->aiodev.hwdev = dev; + data->aiodev.read = rockchip_saradc_read; + + data->base = dev_request_mem_region(dev, 0); + if (IS_ERR(data->base)) { + ret = PTR_ERR(data->base); + goto fail_data; + } + + data->vref = regulator_get(dev, "vref"); + if (IS_ERR(data->vref)) { + dev_err(dev, "can't get vref-supply: %pe\n", data->vref); + ret = PTR_ERR(data->vref); + goto fail_data; + } + + ret = regulator_enable(data->vref); + if (ret < 0) { + dev_err(dev, "can't enable vref-supply value: %d\n", ret); + goto fail_data; + } + + ret = regulator_get_voltage(data->vref); + if (ret < 0) { + dev_warn(dev, "can't get vref-supply value: %d\n", ret); + /* use default value as fallback */ + ret = 1800000; + } + data->ref_voltage_mv = ret / 1000; + + data->cclk = clk_get(dev, "saradc"); + if (IS_ERR(data->cclk)) { + dev_err(dev, "can't get converter clock: %pe\n", data->cclk); + ret = PTR_ERR(data->cclk); + goto fail_data; + } + + ret = clk_enable(data->cclk); + if (ret < 0) { + dev_err(dev, "can't enable converter clock: %pe\n", + ERR_PTR(ret)); + goto fail_data; + } + + data->pclk = clk_get(dev, "apb_pclk"); + if (IS_ERR(data->pclk)) { + dev_err(dev, "can't get peripheral clock: %pe\n", data->pclk); + ret = PTR_ERR(data->pclk); + goto fail_data; + } + + ret = clk_enable(data->pclk); + if (ret < 0) { + dev_err(dev, "can't enable peripheral clk: %pe\n", + ERR_PTR(ret)); + goto fail_data; + } + + data->aiodev.num_channels = data->config->num_channels; + data->channels = + xzalloc(sizeof(*data->channels) * data->aiodev.num_channels); + data->aiodev.channels = xmalloc(sizeof(*data->aiodev.channels) * + data->aiodev.num_channels); + for (i = 0; i < data->aiodev.num_channels; i++) { + data->aiodev.channels[i] = &data->channels[i]; + data->channels[i].unit = "mV"; + } + + rockchip_saradc_reg_wr(data, 0, SARADC_CTRL); + + ret = aiodevice_register(&data->aiodev); + if (ret) + goto fail_channels; + + dev_info(dev, "registered as %s\n", dev_name(&data->aiodev.dev)); + return 0; + +fail_channels: + kfree(data->channels); + kfree(data->aiodev.channels); + +fail_data: + kfree(data); + return ret; +} + +static const struct rockchip_saradc_cfg rk3568_saradc_cfg = { + .num_bits = 10, + .num_channels = 8, +}; + +static const struct of_device_id of_rockchip_saradc_match[] = { + { .compatible = "rockchip,rk3568-saradc", .data = &rk3568_saradc_cfg }, + { /* end */ } +}; + +static struct driver_d rockchip_saradc_driver = { + .name = "rockchip_saradc", + .probe = rockchip_saradc_probe, + .of_compatible = DRV_OF_COMPAT(of_rockchip_saradc_match), +}; +device_platform_driver(rockchip_saradc_driver); diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index f9e771e5ea..fff1e21144 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -525,6 +525,28 @@ int clk_parent_set_rate(struct clk_hw *hw, unsigned long rate, return clk_set_rate(clk_get_parent(clk), rate); } +int clk_name_set_parent(const char *clkname, const char *clkparentname) +{ + struct clk *clk = clk_lookup(clkname); + struct clk *parent = clk_lookup(clkparentname); + + if (IS_ERR(clk)) + return -ENOENT; + if (IS_ERR(parent)) + return -ENOENT; + return clk_set_parent(clk, parent); +} + +int clk_name_set_rate(const char *clkname, unsigned long rate) +{ + struct clk *clk = clk_lookup(clkname); + + if (IS_ERR(clk)) + return -ENOENT; + + return clk_set_rate(clk, rate); +} + #if defined(CONFIG_COMMON_CLK_OF_PROVIDER) /** * struct of_clk_provider - Clock provider registration structure diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 4605158500..40ab7ee3d7 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -1619,10 +1619,19 @@ static void __init rk3568_pmu_clk_init(struct device_node *np) rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches, ARRAY_SIZE(rk3568_clk_pmu_branches)); + rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); + rockchip_clk_protect_critical(rk3568_pmucru_critical_clocks, ARRAY_SIZE(rk3568_pmucru_critical_clocks)); rockchip_clk_of_add_provider(np, ctx); + + clk_name_set_parent("ppll", "pll_ppll"); + clk_name_set_parent("clk_rtc_32k", "clk_rtc32k_frac"); + clk_name_set_rate("clk_rtc_32k", 32768); + clk_name_set_rate("pclk_pmu", 100000000); + clk_name_set_rate("pll_ppll", 200000000); } static void __init rk3568_clk_init(struct device_node *np) @@ -1654,12 +1663,37 @@ static void __init rk3568_clk_init(struct device_node *np) rockchip_clk_register_branches(ctx, rk3568_clk_branches, ARRAY_SIZE(rk3568_clk_branches)); + rockchip_register_softrst(np, 30, reg_base + RK3568_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); + rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST); rockchip_clk_protect_critical(rk3568_cru_critical_clocks, ARRAY_SIZE(rk3568_cru_critical_clocks)); rockchip_clk_of_add_provider(np, ctx); + + clk_name_set_parent("npll", "pll_npll"); + clk_name_set_parent("vpll", "pll_vpll"); + clk_name_set_parent("pclk_bus", "gpll_100m"); + clk_name_set_parent("clk_sdmmc0", "cpll_50m"); + clk_name_set_parent("cclk_emmc", "gpll_200m"); + + clk_name_set_rate("pll_cpll", 1000000000); + clk_name_set_rate("pll_gpll", 1188000000); + clk_name_set_rate("armclk", 600000000); + clk_name_set_rate("aclk_bus", 150000000); + clk_name_set_rate("pclk_bus", 100000000); + clk_name_set_rate("aclk_top_high", 300000000); + clk_name_set_rate("aclk_top_low", 200000000); + clk_name_set_rate("hclk_top", 150000000); + clk_name_set_rate("pclk_top", 100000000); + clk_name_set_rate("aclk_perimid", 300000000); + clk_name_set_rate("hclk_perimid", 150000000); + clk_name_set_rate("pll_npll", 1200000000); + clk_name_set_rate("pll_apll", 816000000); + + clk_name_set_parent("pclk_top", "gpll_100m"); } struct clk_rk3568_inits { diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 0b513b68d0..684876e260 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -23,6 +23,7 @@ config USB_NOP_XCEIV phy programming such as ISP1x04 etc. source "drivers/phy/freescale/Kconfig" +source "drivers/phy/rockchip/Kconfig" config PHY_STM32_USBPHYC tristate "STM32 USB HS PHY Controller" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 684aaed75a..f06a9df92e 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_GENERIC_PHY) += phy-core.o obj-$(CONFIG_USB_NOP_XCEIV) += usb-nop-xceiv.o obj-y += freescale/ obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o +obj-y += rockchip/ diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig new file mode 100644 index 0000000000..37a514059e --- /dev/null +++ b/drivers/phy/rockchip/Kconfig @@ -0,0 +1,14 @@ +config PHY_ROCKCHIP_INNO_USB2 + bool "Rockchip INNO USB2PHY Driver" + depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OFDEVICE + depends on COMMON_CLK + help + Support for Rockchip USB2.0 PHY with Innosilicon IP block. + +config PHY_ROCKCHIP_NANENG_COMBO_PHY + bool "Rockchip NANENG COMBO PHY Driver" + depends on ARCH_ROCKCHIP && OFDEVICE + help + Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII + combo PHY with NaNeng IP block. + diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile new file mode 100644 index 0000000000..4d75d610ef --- /dev/null +++ b/drivers/phy/rockchip/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o +obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c new file mode 100644 index 0000000000..bb1a5c747e --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -0,0 +1,981 @@ +/* + * Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <of.h> +#include <errno.h> +#include <driver.h> +#include <malloc.h> +#include <usb/phy.h> +#include <linux/phy/phy.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <mfd/syscon.h> +#include <regulator.h> + +#define U2PHY_BIT_WRITEABLE_SHIFT 16 +#define CHG_DCD_MAX_RETRIES 6 +#define CHG_PRI_MAX_RETRIES 2 +#define CHG_DCD_POLL_TIME 100 /* millisecond */ +#define CHG_PRIMARY_DET_TIME 40 /* millisecond */ +#define CHG_SECONDARY_DET_TIME 40 /* millisecond */ + +struct rockchip_usb2phy; + +enum power_supply_type { + POWER_SUPPLY_TYPE_UNKNOWN = 0, + POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ + POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ + POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ + POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ +}; + +enum rockchip_usb2phy_port_id { + USB2PHY_PORT_OTG, + USB2PHY_PORT_HOST, + USB2PHY_NUM_PORTS, +}; + +struct usb2phy_reg { + u32 offset; + u32 bitend; + u32 bitstart; + u32 disable; + u32 enable; +}; + +/** + * struct rockchip_chg_det_reg: usb charger detect registers + * @cp_det: charging port detected successfully. + * @dcp_det: dedicated charging port detected successfully. + * @dp_det: assert data pin connect successfully. + * @idm_sink_en: open dm sink curren. + * @idp_sink_en: open dp sink current. + * @idp_src_en: open dm source current. + * @rdm_pdwn_en: open dm pull down resistor. + * @vdm_src_en: open dm voltage source. + * @vdp_src_en: open dp voltage source. + * @opmode: utmi operational mode. + */ +struct rockchip_chg_det_reg { + struct usb2phy_reg cp_det; + struct usb2phy_reg dcp_det; + struct usb2phy_reg dp_det; + struct usb2phy_reg idm_sink_en; + struct usb2phy_reg idp_sink_en; + struct usb2phy_reg idp_src_en; + struct usb2phy_reg rdm_pdwn_en; + struct usb2phy_reg vdm_src_en; + struct usb2phy_reg vdp_src_en; + struct usb2phy_reg opmode; +}; + +/** + * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. + * @phy_sus: phy suspend register. + * @bvalid_det_en: vbus valid rise detection enable register. + * @bvalid_det_st: vbus valid rise detection status register. + * @bvalid_det_clr: vbus valid rise detection clear register. + * @ls_det_en: linestate detection enable register. + * @ls_det_st: linestate detection state register. + * @ls_det_clr: linestate detection clear register. + * @iddig_output: iddig output from grf. + * @iddig_en: utmi iddig select between grf and phy, + * 0: from phy; 1: from grf + * @idfall_det_en: id fall detection enable register. + * @idfall_det_st: id fall detection state register. + * @idfall_det_clr: id fall detection clear register. + * @idrise_det_en: id rise detection enable register. + * @idrise_det_st: id rise detection state register. + * @idrise_det_clr: id rise detection clear register. + * @utmi_avalid: utmi vbus avalid status register. + * @utmi_bvalid: utmi vbus bvalid status register. + * @utmi_iddig: otg port id pin status register. + * @utmi_ls: utmi linestate state register. + * @utmi_hstdet: utmi host disconnect register. + * @vbus_det_en: vbus detect function power down register. + */ +struct rockchip_usb2phy_port_cfg { + struct usb2phy_reg phy_sus; + struct usb2phy_reg bvalid_det_en; + struct usb2phy_reg bvalid_det_st; + struct usb2phy_reg bvalid_det_clr; + struct usb2phy_reg ls_det_en; + struct usb2phy_reg ls_det_st; + struct usb2phy_reg ls_det_clr; + struct usb2phy_reg iddig_output; + struct usb2phy_reg iddig_en; + struct usb2phy_reg idfall_det_en; + struct usb2phy_reg idfall_det_st; + struct usb2phy_reg idfall_det_clr; + struct usb2phy_reg idrise_det_en; + struct usb2phy_reg idrise_det_st; + struct usb2phy_reg idrise_det_clr; + struct usb2phy_reg utmi_avalid; + struct usb2phy_reg utmi_bvalid; + struct usb2phy_reg utmi_iddig; + struct usb2phy_reg utmi_ls; + struct usb2phy_reg utmi_hstdet; + struct usb2phy_reg vbus_det_en; +}; + +/** + * struct rockchip_usb2phy_cfg: usb-phy configuration. + * @reg: the address offset of grf for usb-phy config. + * @num_ports: specify how many ports that the phy has. + * @phy_tuning: phy default parameters tunning. + * @clkout_ctl: keep on/turn off output clk of phy. + * @chg_det: charger detection registers. + */ +struct rockchip_usb2phy_cfg { + u32 reg; + u32 num_ports; + int (*phy_tuning)(struct rockchip_usb2phy *); + struct usb2phy_reg clkout_ctl; + const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; + const struct rockchip_chg_det_reg chg_det; +}; + +struct rockchip_usb2phy_phy { + struct phy *phy; + struct regulator *vbus; + struct rockchip_usb2phy *usb2phy; + const struct rockchip_usb2phy_port_cfg *port_cfg; +}; + +/** + * @dcd_retries: The retry count used to track Data contact + * detection process. + * @primary_retries: The retry count used to do usb bc detection + * primary stage. + * @grf: General Register Files register base. + * @usbgrf_base : USB General Register Files register base. + * @phy_cfg: phy register configuration, assigned by driver data. + */ +struct rockchip_usb2phy { + u8 dcd_retries; + u8 primary_retries; + struct regmap *grf_base; + const struct rockchip_usb2phy_cfg *phy_cfg; + struct rockchip_usb2phy_phy phys[2]; + struct phy_provider *provider; + struct clk *clk480m; + struct clk_hw clk480m_hw; + struct device_d *dev; + struct clk *clk; +}; + +static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) +{ + return rphy->grf_base; +} + +static inline int property_enable(struct regmap *base, + const struct usb2phy_reg *reg, bool en) +{ + u32 val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); + + return regmap_write(base, reg->offset, val); +} + +static inline bool property_enabled(struct regmap *base, + const struct usb2phy_reg *reg) +{ + u32 tmp, orig; + u32 mask = GENMASK(reg->bitend, reg->bitstart); + + regmap_read(base, reg->offset, &orig); + + tmp = (orig & mask) >> reg->bitstart; + + return tmp == reg->enable; +} + +static int rockchip_usb2phy_init(struct phy *phy) +{ + struct rockchip_usb2phy_phy *p = phy_get_drvdata(phy); + struct rockchip_usb2phy *rphy = p->usb2phy; + struct regmap *base = get_reg_base(rphy); + + p->vbus = regulator_get(&phy->dev, "vbus"); + + property_enable(base, &p->port_cfg->phy_sus, false); + + /* waiting for the utmi_clk to become stable */ + udelay(2000); + + return 0; +} + +static int rockchip_usb2phy_exit(struct phy *phy) +{ + struct rockchip_usb2phy_phy *p = phy_get_drvdata(phy); + struct rockchip_usb2phy *rphy = p->usb2phy; + struct regmap *base = get_reg_base(rphy); + + property_enable(base, &p->port_cfg->phy_sus, true); + + return 0; +} + +static int rockchip_usb2phy_power_on(struct phy *phy) +{ + struct rockchip_usb2phy_phy *p = phy_get_drvdata(phy); + int ret; + + ret = regulator_enable(p->vbus); + if (ret) { + dev_err(&phy->dev, "Failed to enable VBus supply\n"); + return ret; + } + + return 0; +} + +static int rockchip_usb2phy_power_off(struct phy *phy) +{ + struct rockchip_usb2phy_phy *p = phy_get_drvdata(phy); + int ret; + + ret = regulator_disable(p->vbus); + if (ret) { + dev_err(&phy->dev, "Failed to disable VBus supply\n"); + return ret; + } + + return 0; +} + +static struct phy *rockchip_usb2phy_of_xlate(struct device_d *dev, + struct of_phandle_args *args) +{ + struct rockchip_usb2phy *rphy = dev->priv; + struct device_node *phynode = args->np; + struct rockchip_usb2phy_phy *p; + int port; + + for (port = 0; port < 2; port++) { + if (phynode == rphy->phys[port].phy->dev.device_node) { + p = &rphy->phys[port]; + return p->phy; + } + } + + return NULL; +} + +static struct phy_ops rockchip_usb2phy_ops = { + .init = rockchip_usb2phy_init, + .exit = rockchip_usb2phy_exit, + .power_on = rockchip_usb2phy_power_on, + .power_off = rockchip_usb2phy_power_off, +}; + +static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw) +{ + struct rockchip_usb2phy *rphy = + container_of(hw, struct rockchip_usb2phy, clk480m_hw); + struct regmap *base = get_reg_base(rphy); + int ret; + + /* turn on 480m clk output if it is off */ + if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) { + ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true); + if (ret) + return ret; + + /* waiting for the clk become stable */ + udelay(1200); + } + + return 0; +} + +static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw) +{ + struct rockchip_usb2phy *rphy = + container_of(hw, struct rockchip_usb2phy, clk480m_hw); + struct regmap *base = get_reg_base(rphy); + + /* turn off 480m clk output */ + property_enable(base, &rphy->phy_cfg->clkout_ctl, false); +} + +static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw) +{ + struct rockchip_usb2phy *rphy = + container_of(hw, struct rockchip_usb2phy, clk480m_hw); + struct regmap *base = get_reg_base(rphy); + + return property_enabled(base, &rphy->phy_cfg->clkout_ctl); +} + +static unsigned long +rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return 480000000; +} + +static const struct clk_ops rockchip_usb2phy_clkout_ops = { + .enable = rockchip_usb2phy_clk480m_prepare, + .disable = rockchip_usb2phy_clk480m_unprepare, + .is_enabled = rockchip_usb2phy_clk480m_prepared, + .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate, +}; + +static int rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy) +{ + struct device_node *node = rphy->dev->device_node; + struct clk_init_data init = {}; + const char *clk_name; + int ret; + + init.flags = 0; + init.name = "clk_usbphy_480m"; + init.ops = &rockchip_usb2phy_clkout_ops; + + /* optional override of the clockname */ + of_property_read_string(node, "clock-output-names", &init.name); + + if (rphy->clk) { + clk_name = __clk_get_name(rphy->clk); + init.parent_names = &clk_name; + init.num_parents = 1; + } else { + init.parent_names = NULL; + init.num_parents = 0; + } + + rphy->clk480m_hw.init = &init; + + rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw); + if (IS_ERR(rphy->clk480m)) { + ret = PTR_ERR(rphy->clk480m); + goto err_ret; + } + + ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m); + if (ret < 0) + goto err_clk_provider; + + return 0; + +err_clk_provider: + clk_unregister(rphy->clk480m); +err_ret: + return ret; +} + +static int rockchip_usb2phy_probe(struct device_d *dev) +{ + const struct rockchip_usb2phy_cfg *phy_cfgs; + struct rockchip_usb2phy *rphy; + u32 reg, index; + int ret, port = 0; + struct device_node *child, *np = dev->device_node; + struct resource *iores; + + rphy = xzalloc(sizeof(*rphy)); + + rphy->dev = dev; + + rphy->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf"); + if (IS_ERR(rphy->grf_base)) + return PTR_ERR(rphy->grf_base); + + phy_cfgs = device_get_match_data(dev); + if (!phy_cfgs) + return -EINVAL; + + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + if (of_property_read_u32(np, "reg", ®)) + return -EINVAL; + } else { + reg = iores->start; + } + + /* find out a proper config which can be matched with dt. */ + index = 0; + while (phy_cfgs[index].reg) { + if (phy_cfgs[index].reg == reg) { + rphy->phy_cfg = &phy_cfgs[index]; + break; + } + ++index; + } + + if (!rphy->phy_cfg) { + dev_err(dev, "no phy-config can be matched\n"); + return -EINVAL; + } + + for_each_child_of_node(np, child) { + struct rockchip_usb2phy_phy *p; + struct phy *phy; + + if (!strcmp(child->name, "host-port")) { + port = USB2PHY_PORT_OTG; + } else if (!strcmp(child->name, "otg-port")) { + port = USB2PHY_PORT_HOST; + } else { + dev_warn(dev, "Ignoring unknown subnode %s\n", child->name); + continue; + } + + if (rphy->phys[port].phy) + return -EINVAL; + + phy = phy_create(dev, child, &rockchip_usb2phy_ops); + if (IS_ERR(phy)) { + ret = PTR_ERR(phy); + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to create phy%d: %d\n", + port, ret); + return ret; + } + + p = xzalloc(sizeof(*p)); + + phy_set_drvdata(phy, p); + p->usb2phy = rphy; + p->port_cfg = &phy_cfgs->port_cfgs[port]; + + rphy->phys[port].phy = phy; + } + + if (rphy->phy_cfg->phy_tuning) + rphy->phy_cfg->phy_tuning(rphy); + + dev->priv = rphy; + + rphy->clk = clk_get(dev, "phyclk"); + rockchip_usb2phy_clk480m_register(rphy); + + rphy->provider = of_phy_provider_register(dev, rockchip_usb2phy_of_xlate); + if (IS_ERR(rphy->provider)) + return PTR_ERR(rphy->provider); + + return 0; +} + +static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy) +{ + struct regmap *base = get_reg_base(rphy); + int ret = 0; + + /* Open pre-emphasize in non-chirp state for PHY0 otg port */ + if (rphy->phy_cfg->reg == 0x760) + ret = regmap_write(base, 0x76c, 0x00070004); + + return ret; +} + +static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { + { + .reg = 0x100, + .num_ports = 2, + .clkout_ctl = { 0x108, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, + .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, + .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, + .iddig_output = { 0x0100, 10, 10, 0, 1 }, + .iddig_en = { 0x0100, 9, 9, 0, 1 }, + .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, + .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, + .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, + .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, + .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, + .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, + .ls_det_en = { 0x0110, 0, 0, 0, 1 }, + .ls_det_st = { 0x0114, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, + .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, + .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, + .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, + .utmi_ls = { 0x0120, 5, 4, 0, 1 }, + .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x110, 1, 1, 0, 1 }, + .ls_det_st = { 0x114, 1, 1, 0, 1 }, + .ls_det_clr = { 0x118, 1, 1, 0, 1 }, + .utmi_ls = { 0x120, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x120, 19, 19, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x0100, 3, 0, 5, 1 }, + .cp_det = { 0x0120, 24, 24, 0, 1 }, + .dcp_det = { 0x0120, 23, 23, 0, 1 }, + .dp_det = { 0x0120, 25, 25, 0, 1 }, + .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, + .idp_src_en = { 0x0108, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { + { + .reg = 0x17c, + .num_ports = 2, + .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, + .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, + .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, + .iddig_output = { 0x017c, 10, 10, 0, 1 }, + .iddig_en = { 0x017c, 9, 9, 0, 1 }, + .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, + .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, + .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, + .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, + .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, + .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, + .ls_det_en = { 0x017c, 12, 12, 0, 1 }, + .ls_det_st = { 0x017c, 13, 13, 0, 1 }, + .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, + .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, + .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, + .utmi_ls = { 0x014c, 7, 6, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0194, 14, 14, 0, 1 }, + .ls_det_st = { 0x0194, 15, 15, 0, 1 }, + .ls_det_clr = { 0x0194, 15, 15, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x017c, 3, 0, 5, 1 }, + .cp_det = { 0x02c0, 6, 6, 0, 1 }, + .dcp_det = { 0x02c0, 5, 5, 0, 1 }, + .dp_det = { 0x02c0, 7, 7, 0, 1 }, + .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, + .idp_src_en = { 0x0184, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { + { + .reg = 0x760, + .num_ports = 2, + .phy_tuning = rk322x_usb2phy_tuning, + .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, + .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, + .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, + .iddig_output = { 0x0760, 10, 10, 0, 1 }, + .iddig_en = { 0x0760, 9, 9, 0, 1 }, + .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, + .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, + .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, + .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, + .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, + .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, + .ls_det_en = { 0x0680, 2, 2, 0, 1 }, + .ls_det_st = { 0x0690, 2, 2, 0, 1 }, + .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, + .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, + .utmi_iddig = { 0x0480, 1, 1, 0, 1 }, + .utmi_ls = { 0x0480, 3, 2, 0, 1 }, + .vbus_det_en = { 0x0788, 15, 15, 1, 0 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0680, 4, 4, 0, 1 }, + .ls_det_st = { 0x0690, 4, 4, 0, 1 }, + .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x0760, 3, 0, 5, 1 }, + .cp_det = { 0x0884, 4, 4, 0, 1 }, + .dcp_det = { 0x0884, 3, 3, 0, 1 }, + .dp_det = { 0x0884, 5, 5, 0, 1 }, + .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, + .idp_src_en = { 0x0768, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, + }, + }, + { + .reg = 0x800, + .num_ports = 2, + .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x804, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0684, 1, 1, 0, 1 }, + .ls_det_st = { 0x0694, 1, 1, 0, 1 }, + .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x800, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0684, 0, 0, 0, 1 }, + .ls_det_st = { 0x0694, 0, 0, 0, 1 }, + .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } + } + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { + { + .reg = 0x100, + .num_ports = 2, + .clkout_ctl = { 0x108, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, + .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, + .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, + .iddig_output = { 0x0100, 10, 10, 0, 1 }, + .iddig_en = { 0x0100, 9, 9, 0, 1 }, + .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, + .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, + .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, + .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, + .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, + .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, + .ls_det_en = { 0x0110, 0, 0, 0, 1 }, + .ls_det_st = { 0x0114, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, + .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, + .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, + .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, + .utmi_ls = { 0x0120, 5, 4, 0, 1 }, + .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x110, 1, 1, 0, 1 }, + .ls_det_st = { 0x114, 1, 1, 0, 1 }, + .ls_det_clr = { 0x118, 1, 1, 0, 1 }, + .utmi_ls = { 0x120, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x120, 19, 19, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x0100, 3, 0, 5, 1 }, + .cp_det = { 0x0120, 24, 24, 0, 1 }, + .dcp_det = { 0x0120, 23, 23, 0, 1 }, + .dp_det = { 0x0120, 25, 25, 0, 1 }, + .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, + .idp_src_en = { 0x0108, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = { + { + .reg = 0x700, + .num_ports = 2, + .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, + .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, + .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, + .ls_det_en = { 0x0680, 2, 2, 0, 1 }, + .ls_det_st = { 0x0690, 2, 2, 0, 1 }, + .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, + .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 }, + .utmi_ls = { 0x04bc, 25, 24, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0680, 4, 4, 0, 1 }, + .ls_det_st = { 0x0690, 4, 4, 0, 1 }, + .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x0700, 3, 0, 5, 1 }, + .cp_det = { 0x04b8, 30, 30, 0, 1 }, + .dcp_det = { 0x04b8, 29, 29, 0, 1 }, + .dp_det = { 0x04b8, 31, 31, 0, 1 }, + .idm_sink_en = { 0x0718, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0718, 7, 7, 0, 1 }, + .idp_src_en = { 0x0718, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0718, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0718, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { + { + .reg = 0xe450, + .num_ports = 2, + .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 }, + .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, + .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, + .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, + .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, + .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, + .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, + .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, + .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, + .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, + .ls_det_en = { 0xe3c0, 2, 2, 0, 1 }, + .ls_det_st = { 0xe3e0, 2, 2, 0, 1 }, + .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 }, + .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, + .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, + .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, + .utmi_ls = { 0xe2ac, 14, 13, 0, 1 }, + .vbus_det_en = { 0x449c, 15, 15, 1, 0 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, + .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, + .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, + .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, + .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, + .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0xe454, 3, 0, 5, 1 }, + .cp_det = { 0xe2ac, 2, 2, 0, 1 }, + .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, + .dp_det = { 0xe2ac, 0, 0, 0, 1 }, + .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, + .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, + .idp_src_en = { 0xe450, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, + .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, + .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, + }, + }, + { + .reg = 0xe460, + .num_ports = 2, + .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 }, + .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, + .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, + .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, + .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, + .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, + .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, + .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, + .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, + .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, + .ls_det_en = { 0xe3c0, 7, 7, 0, 1 }, + .ls_det_st = { 0xe3e0, 7, 7, 0, 1 }, + .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 }, + .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, + .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, + .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, + .utmi_ls = { 0xe2ac, 18, 17, 0, 1 }, + .vbus_det_en = { 0x451c, 15, 15, 1, 0 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, + .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, + .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, + .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, + .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, + .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0xe464, 3, 0, 5, 1 }, + .cp_det = { 0xe2ac, 5, 5, 0, 1 }, + .dcp_det = { 0xe2ac, 4, 4, 0, 1 }, + .dp_det = { 0xe2ac, 3, 3, 0, 1 }, + .idm_sink_en = { 0xe460, 8, 8, 0, 1 }, + .idp_sink_en = { 0xe460, 7, 7, 0, 1 }, + .idp_src_en = { 0xe460, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 }, + .vdm_src_en = { 0xe460, 12, 12, 0, 1 }, + .vdp_src_en = { 0xe460, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { + { + .reg = 0x100, + .num_ports = 2, + .clkout_ctl = { 0x108, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, + .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, + .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, + .ls_det_en = { 0x0680, 2, 2, 0, 1 }, + .ls_det_st = { 0x0690, 2, 2, 0, 1 }, + .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, + .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, + .utmi_ls = { 0x0804, 13, 12, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0680, 4, 4, 0, 1 }, + .ls_det_st = { 0x0690, 4, 4, 0, 1 }, + .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, + .utmi_ls = { 0x0804, 9, 8, 0, 1 }, + .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x0ffa0100, 3, 0, 5, 1 }, + .cp_det = { 0x0804, 1, 1, 0, 1 }, + .dcp_det = { 0x0804, 0, 0, 0, 1 }, + .dp_det = { 0x0804, 2, 2, 0, 1 }, + .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 }, + .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + +static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { + { + .reg = 0xfe8a0000, + .num_ports = 2, + .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, + .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, + .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, + .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, + .iddig_output = { 0x0000, 10, 10, 0, 1 }, + .iddig_en = { 0x0000, 9, 9, 0, 1 }, + .idfall_det_en = { 0x0080, 5, 5, 0, 1 }, + .idfall_det_st = { 0x0084, 5, 5, 0, 1 }, + .idfall_det_clr = { 0x0088, 5, 5, 0, 1 }, + .idrise_det_en = { 0x0080, 4, 4, 0, 1 }, + .idrise_det_st = { 0x0084, 4, 4, 0, 1 }, + .idrise_det_clr = { 0x0088, 4, 4, 0, 1 }, + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, + .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, + .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, + .utmi_iddig = { 0x00c0, 6, 6, 0, 1 }, + .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0080, 1, 1, 0, 1 }, + .ls_det_st = { 0x0084, 1, 1, 0, 1 }, + .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, + .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x0000, 3, 0, 5, 1 }, + .cp_det = { 0x00c0, 24, 24, 0, 1 }, + .dcp_det = { 0x00c0, 23, 23, 0, 1 }, + .dp_det = { 0x00c0, 25, 25, 0, 1 }, + .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, + .idp_src_en = { 0x0008, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, + }, + }, + { + .reg = 0xfe8b0000, + .num_ports = 2, + .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, + .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, + .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0080, 1, 1, 0, 1 }, + .ls_det_st = { 0x0084, 1, 1, 0, 1 }, + .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, + .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } + } + }, + }, + { /* sentinel */ } +}; +static const struct of_device_id rockchip_usb2phy_dt_match[] = { + { .compatible = "rockchip,rk1808-usb2phy", .data = &rk1808_phy_cfgs }, + { .compatible = "rockchip,rk3128-usb2phy", .data = &rk312x_phy_cfgs }, + { .compatible = "rockchip,rk322x-usb2phy", .data = &rk322x_phy_cfgs }, + { .compatible = "rockchip,rk3308-usb2phy", .data = &rk3328_phy_cfgs }, + { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, + { .compatible = "rockchip,rk3368-usb2phy", .data = &rk3368_phy_cfgs }, + { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, + { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs }, + { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs }, + { } +}; + +static struct driver_d rockchip_usb2phy_driver = { + .probe = rockchip_usb2phy_probe, + .name = "rockchip-usb2phy", + .of_compatible = rockchip_usb2phy_dt_match, +}; +coredevice_platform_driver(rockchip_usb2phy_driver); diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c new file mode 100644 index 0000000000..af4340f90d --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip PIPE USB3.0 PCIE SATA combphy driver + * + * Copyright (C) 2020 Rockchip Electronics Co., Ltd. + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <of.h> +#include <errno.h> +#include <driver.h> +#include <malloc.h> +#include <usb/phy.h> +#include <linux/phy/phy.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/reset.h> +#include <mfd/syscon.h> +#include <linux/iopoll.h> +#include <dt-bindings/phy/phy.h> + +#define BIT_WRITEABLE_SHIFT 16 + +struct rockchip_combphy_priv; + +struct combphy_reg { + u16 offset; + u16 bitend; + u16 bitstart; + u16 disable; + u16 enable; +}; + +struct rockchip_combphy_grfcfg { + struct combphy_reg pcie_mode_set; + struct combphy_reg usb_mode_set; + struct combphy_reg sgmii_mode_set; + struct combphy_reg qsgmii_mode_set; + struct combphy_reg pipe_rxterm_set; + struct combphy_reg pipe_txelec_set; + struct combphy_reg pipe_txcomp_set; + struct combphy_reg pipe_clk_25m; + struct combphy_reg pipe_clk_100m; + struct combphy_reg pipe_phymode_sel; + struct combphy_reg pipe_rate_sel; + struct combphy_reg pipe_rxterm_sel; + struct combphy_reg pipe_txelec_sel; + struct combphy_reg pipe_txcomp_sel; + struct combphy_reg pipe_clk_ext; + struct combphy_reg pipe_sel_usb; + struct combphy_reg pipe_sel_qsgmii; + struct combphy_reg pipe_phy_status; + struct combphy_reg con0_for_pcie; + struct combphy_reg con1_for_pcie; + struct combphy_reg con2_for_pcie; + struct combphy_reg con3_for_pcie; + struct combphy_reg con0_for_sata; + struct combphy_reg con1_for_sata; + struct combphy_reg con2_for_sata; + struct combphy_reg con3_for_sata; + struct combphy_reg pipe_con0_for_sata; + struct combphy_reg pipe_sgmii_mac_sel; + struct combphy_reg pipe_xpcs_phy_ready; + struct combphy_reg u3otg0_port_en; + struct combphy_reg u3otg1_port_en; +}; + +struct rockchip_combphy_cfg { + const int num_clks; + const struct clk_bulk_data *clks; + const struct rockchip_combphy_grfcfg *grfcfg; + int (*combphy_cfg)(struct rockchip_combphy_priv *priv); +}; + +struct rockchip_combphy_priv { + u8 mode; + void __iomem *mmio; + int num_clks; + struct clk_bulk_data *clks; + struct device_d *dev; + struct regmap *pipe_grf; + struct regmap *phy_grf; + struct phy *phy; + struct reset_control *apb_rst; + struct reset_control *phy_rst; + const struct rockchip_combphy_cfg *cfg; +}; + +static inline bool param_read(struct regmap *base, + const struct combphy_reg *reg, u32 val) +{ + int ret; + u32 mask, orig, tmp; + + ret = regmap_read(base, reg->offset, &orig); + if (ret) + return false; + + mask = GENMASK(reg->bitend, reg->bitstart); + tmp = (orig & mask) >> reg->bitstart; + + return tmp == val; +} + +static int param_write(struct regmap *base, + const struct combphy_reg *reg, bool en) +{ + u32 val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); + + return regmap_write(base, reg->offset, val); +} + +static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 mask, val; + + mask = GENMASK(cfg->pipe_phy_status.bitend, + cfg->pipe_phy_status.bitstart); + + regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); + val = (val & mask) >> cfg->pipe_phy_status.bitstart; + + return val; +} + +static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + if (priv->cfg->combphy_cfg) { + ret = priv->cfg->combphy_cfg(priv); + if (ret) { + dev_err(priv->dev, "failed to init phy for pcie\n"); + return ret; + } + } + + return ret; +} + +static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + if (priv->cfg->combphy_cfg) { + ret = priv->cfg->combphy_cfg(priv); + if (ret) { + dev_err(priv->dev, "failed to init phy for usb3\n"); + return ret; + } + } + + return ret; +} + +static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + if (priv->cfg->combphy_cfg) { + ret = priv->cfg->combphy_cfg(priv); + if (ret) { + dev_err(priv->dev, "failed to init phy for sata\n"); + return ret; + } + } + + return ret; +} + +static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + if (priv->cfg->combphy_cfg) { + ret = priv->cfg->combphy_cfg(priv); + if (ret) { + dev_err(priv->dev, "failed to init phy for sgmii\n"); + return ret; + } + } + + return ret; +} + +static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) +{ + switch (priv->mode) { + case PHY_TYPE_PCIE: + rockchip_combphy_pcie_init(priv); + break; + case PHY_TYPE_USB3: + rockchip_combphy_usb3_init(priv); + break; + case PHY_TYPE_SATA: + rockchip_combphy_sata_init(priv); + break; + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + return rockchip_combphy_sgmii_init(priv); + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + return 0; +} + +static int rockchip_combphy_init(struct phy *phy) +{ + struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + int ret; + + ret = clk_bulk_enable(priv->num_clks, priv->clks); + if (ret) { + dev_err(priv->dev, "failed to enable clks\n"); + return ret; + } + + ret = rockchip_combphy_set_mode(priv); + if (ret) + goto err_clk; + + ret = reset_control_deassert(priv->phy_rst); + if (ret) + goto err_clk; + + if (priv->mode == PHY_TYPE_USB3) { + ret = readx_poll_timeout(rockchip_combphy_is_ready, + priv, val, + val == cfg->pipe_phy_status.enable, + 1000); + if (ret) + dev_warn(priv->dev, "wait phy status ready timeout\n"); + } + + return 0; + +err_clk: + clk_bulk_disable(priv->num_clks, priv->clks); + + return ret; +} + +static int rockchip_combphy_exit(struct phy *phy) +{ + struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); + + clk_bulk_disable(priv->num_clks, priv->clks); + reset_control_assert(priv->phy_rst); + + return 0; +} + +static const struct phy_ops rochchip_combphy_ops = { + .init = rockchip_combphy_init, + .exit = rockchip_combphy_exit, +}; + +static struct phy *rockchip_combphy_xlate(struct device_d *dev, + struct of_phandle_args *args) +{ + struct rockchip_combphy_priv *priv = dev->priv; + + if (args->args_count != 1) { + dev_err(dev, "invalid number of arguments\n"); + return ERR_PTR(-EINVAL); + } + + if (priv->mode != PHY_NONE && priv->mode != args->args[0]) + dev_warn(dev, "phy type select %d overwriting type %d\n", + args->args[0], priv->mode); + + priv->mode = args->args[0]; + + return priv->phy; +} + +static int rockchip_combphy_parse_dt(struct device_d *dev, + struct rockchip_combphy_priv *priv) +{ + struct device_node *np = dev->device_node; + const struct rockchip_combphy_cfg *phy_cfg = priv->cfg; + int ret, mac_id; + + ret = clk_bulk_get(dev, priv->num_clks, priv->clks); + if (ret == -EPROBE_DEFER) + return -EPROBE_DEFER; + if (ret) + priv->num_clks = 0; + + priv->pipe_grf = syscon_regmap_lookup_by_phandle(np, + "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); + return PTR_ERR(priv->pipe_grf); + } + + priv->phy_grf = syscon_regmap_lookup_by_phandle(np, + "rockchip,pipe-phy-grf"); + if (IS_ERR(priv->phy_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); + return PTR_ERR(priv->phy_grf); + } + + if (!of_property_read_u32(np, "rockchip,sgmii-mac-sel", &mac_id) && + (mac_id > 0)) + param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, + true); + + priv->apb_rst = reset_control_get(dev, "combphy-apb"); + if (IS_ERR(priv->apb_rst)) { + ret = PTR_ERR(priv->apb_rst); + + if (ret != -EPROBE_DEFER) + dev_warn(dev, "failed to get apb reset\n"); + + return ret; + } + + priv->phy_rst = reset_control_get(dev, "combphy"); + if (IS_ERR(priv->phy_rst)) { + ret = PTR_ERR(priv->phy_rst); + + if (ret != -EPROBE_DEFER) + dev_warn(dev, "failed to get phy reset\n"); + + return ret; + } + + return reset_control_assert(priv->phy_rst); +} + +static int rockchip_combphy_probe(struct device_d *dev) +{ + struct phy_provider *phy_provider; + struct rockchip_combphy_priv *priv; + const struct rockchip_combphy_cfg *phy_cfg; + struct resource *res; + int ret; + + phy_cfg = device_get_match_data(dev); + if (!phy_cfg) { + dev_err(dev, "No OF match data provided\n"); + return -EINVAL; + } + + priv = xzalloc(sizeof(*priv)); + if (!priv) + return -ENOMEM; + + res = dev_request_mem_resource(dev, 0); + if (IS_ERR(res)) { + ret = PTR_ERR(res); + return ret; + } + + priv->mmio = IOMEM(res->start); + + priv->num_clks = phy_cfg->num_clks; + + priv->clks = memdup(phy_cfg->clks, + phy_cfg->num_clks * sizeof(struct clk_bulk_data)); + if (!priv->clks) + return -ENOMEM; + + priv->dev = dev; + priv->mode = PHY_NONE; + priv->cfg = phy_cfg; + + ret = rockchip_combphy_parse_dt(dev, priv); + if (ret) + return ret; + + priv->phy = phy_create(dev, NULL, &rochchip_combphy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); + return PTR_ERR(priv->phy); + } + + dev->priv = priv; + phy_set_drvdata(priv->phy, priv); + + phy_provider = of_phy_provider_register(dev, rockchip_combphy_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + struct device_node *np = priv->dev->device_node; + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + struct clk *refclk = NULL; + unsigned long rate; + u32 val; + + /* Configure PHY reference clock frequency */ + refclk = priv->clks[0].clk; + if (!refclk) { + dev_err(priv->dev, "No refclk found\n"); + return -EINVAL; + } + + switch (priv->mode) { + case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x7c); + + param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x7c); + + /* Enable adaptive CTLE for USB3.0 Rx */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(0, 0); + val |= 0x01; + writel(val, priv->mmio + (0x0e << 2)); + + param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); + param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + param_write(priv->phy_grf, &cfg->usb_mode_set, true); + break; + case PHY_TYPE_SATA: + writel(0x41, priv->mmio + 0x38); + writel(0x8F, priv->mmio + 0x18); + param_write(priv->phy_grf, &cfg->con0_for_sata, true); + param_write(priv->phy_grf, &cfg->con1_for_sata, true); + param_write(priv->phy_grf, &cfg->con2_for_sata, true); + param_write(priv->phy_grf, &cfg->con3_for_sata, true); + param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); + break; + case PHY_TYPE_SGMII: + param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); + param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); + param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); + param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); + break; + case PHY_TYPE_QSGMII: + param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); + param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); + param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); + param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); + param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + rate = clk_get_rate(refclk); + + switch (rate) { + case 24000000: + if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) { + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(7, 6); + val |= 0x01 << 6; + writel(val, priv->mmio + (0x0e << 2)); + + val = readl(priv->mmio + (0x0f << 2)); + val &= ~GENMASK(7, 0); + val |= 0x5f; + writel(val, priv->mmio + (0x0f << 2)); + } + break; + case 25000000: + param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); + break; + case 100000000: + param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->mode == PHY_TYPE_PCIE) { + /* PLL KVCO tuning fine */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Enable controlling random jitter, aka RMJ */ + writel(0x4, priv->mmio + (0xb << 2)); + + val = readl(priv->mmio + (0x5 << 2)); + val &= ~(0x3 << 6); + val |= 0x1 << 6; + writel(val, priv->mmio + (0x5 << 2)); + + writel(0x32, priv->mmio + (0x11 << 2)); + writel(0xf0, priv->mmio + (0xa << 2)); + } else if (priv->mode == PHY_TYPE_SATA) { + /* downward spread spectrum +500ppm */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(7, 4); + val |= 0x50; + writel(val, priv->mmio + (0x1f << 2)); + } + break; + default: + dev_err(priv->dev, "Unsupported rate: %lu\n", rate); + return -EINVAL; + } + + if (of_property_read_bool(np, "rockchip,ext-refclk")) { + param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) { + val = readl(priv->mmio + (0xc << 2)); + val |= 0x3 << 4 | 0x1 << 7; + writel(val, priv->mmio + (0xc << 2)); + + val = readl(priv->mmio + (0xd << 2)); + val |= 0x1; + writel(val, priv->mmio + (0xd << 2)); + } + } + + if (of_property_read_bool(np, "rockchip,enable-ssc")) { + val = readl(priv->mmio + (0x7 << 2)); + val |= BIT(4); + writel(val, priv->mmio + (0x7 << 2)); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, + .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, + .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, + /* pipe-grf */ + .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, + .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, + .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, + .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, + .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct clk_bulk_data rk3568_clks[] = { + { .id = "refclk" }, + { .id = "apbclk" }, + { .id = "pipe_clk" }, +}; + +static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { + .num_clks = ARRAY_SIZE(rk3568_clks), + .clks = rk3568_clks, + .grfcfg = &rk3568_combphy_grfcfgs, + .combphy_cfg = rk3568_combphy_cfg, +}; + +static const struct of_device_id rockchip_combphy_of_match[] = { + { + .compatible = "rockchip,rk3568-naneng-combphy", + .data = &rk3568_combphy_cfgs, + }, + { }, +}; + +static struct driver_d rockchip_combphy_driver = { + .probe = rockchip_combphy_probe, + .name = "naneng-combphy", + .of_compatible = rockchip_combphy_of_match, +}; +coredevice_platform_driver(rockchip_combphy_driver); diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index be44067c8f..9b832c97d6 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -332,63 +332,52 @@ static struct gpio_ops rockchip_gpio_ops = { .get_direction = rockchip_gpiov2_get_direction, }; -static int rockchip_gpiolib_register(struct device_d *dev, - struct rockchip_pinctrl *info) +static int rockchip_gpio_probe(struct device_d *dev) { + struct rockchip_pinctrl *info = dev->parent->priv; struct rockchip_pin_ctrl *ctrl = info->ctrl; - struct rockchip_pin_bank *bank = ctrl->pin_banks; + struct rockchip_pin_bank *bank; + struct gpio_chip *gpio; void __iomem *reg_base; - int ret; - int i; + int ret, bankno; - for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { - struct gpio_chip *gpio = &bank->bgpio_chip.gc; + bankno = of_alias_get_id(dev->device_node, "gpio"); + bank = &ctrl->pin_banks[bankno]; + gpio = &bank->bgpio_chip.gc; - if (!bank->valid) { - dev_warn(dev, "bank %s is not valid\n", bank->name); - continue; - } + if (!bank->valid) + dev_warn(dev, "bank %s is not valid\n", bank->name); - reg_base = bank->reg_base; - - if (ctrl->type == RK3568) { - gpio->ngpio = 32; - gpio->dev = dev; - gpio->ops = &rockchip_gpio_ops; - gpio->base = of_alias_get_id(bank->of_node, "gpio"); - if (gpio->base < 0) - return -EINVAL; - gpio->base *= 32; - } else { - ret = bgpio_init(&bank->bgpio_chip, dev, 4, - reg_base + RK_GPIO_EXT_PORT, - reg_base + RK_GPIO_SWPORT_DR, NULL, - reg_base + RK_GPIO_SWPORT_DDR, NULL, 0); - if (ret) - goto fail; - } + reg_base = bank->reg_base; - bank->bgpio_chip.gc.dev = of_find_device_by_node(bank->of_node); + if (ctrl->type == RK3568) { + gpio->ngpio = 32; + gpio->dev = dev; + gpio->ops = &rockchip_gpio_ops; + gpio->base = bankno; + if (gpio->base < 0) + return -EINVAL; + gpio->base *= 32; + } else { + ret = bgpio_init(&bank->bgpio_chip, dev, 4, + reg_base + RK_GPIO_EXT_PORT, + reg_base + RK_GPIO_SWPORT_DR, NULL, + reg_base + RK_GPIO_SWPORT_DDR, NULL, 0); + if (ret) + return ret; + } - bank->bgpio_chip.gc.ngpio = bank->nr_pins; - ret = gpiochip_add(&bank->bgpio_chip.gc); - if (ret) { - dev_err(dev, "failed to register gpio_chip %s, error code: %d\n", - bank->name, ret); - goto fail; - } + bank->bgpio_chip.gc.dev = dev; + bank->bgpio_chip.gc.ngpio = bank->nr_pins; + ret = gpiochip_add(&bank->bgpio_chip.gc); + if (ret) { + dev_err(dev, "failed to register gpio_chip %s, error code: %d\n", + bank->name, ret); + return ret; } return 0; -fail: - for (--i, --bank; i >= 0; --i, --bank) { - if (!bank->valid) - continue; - - gpiochip_remove(&bank->bgpio_chip.gc); - } - return ret; } static struct rockchip_pinctrl *to_rockchip_pinctrl(struct pinctrl_device *pdev) @@ -1010,8 +999,6 @@ static int rockchip_pinctrl_probe(struct device_d *dev) struct rockchip_pin_ctrl *ctrl; int ret; - of_platform_populate(dev->device_node, NULL, NULL); - info = xzalloc(sizeof(struct rockchip_pinctrl)); ctrl = rockchip_pinctrl_get_soc_data(info, dev); @@ -1038,9 +1025,9 @@ static int rockchip_pinctrl_probe(struct device_d *dev) info->pctl_dev.dev = dev; info->pctl_dev.ops = &rockchip_pinctrl_ops; - ret = rockchip_gpiolib_register(dev, info); - if (ret) - return ret; + dev->priv = info; + + of_platform_populate(dev->device_node, NULL, dev); if (!IS_ENABLED(CONFIG_PINCTRL)) return 0; @@ -1282,3 +1269,20 @@ static struct driver_d rockchip_pinctrl_driver = { }; core_platform_driver(rockchip_pinctrl_driver); + +static struct of_device_id rockchip_gpio_dt_match[] = { + { + .compatible = "rockchip,gpio-bank", + .data = &rk2928_pin_ctrl, + }, { + /* sentinel */ + } +}; + +static struct driver_d rockchip_gpio_driver = { + .name = "rockchip-gpio", + .probe = rockchip_gpio_probe, + .of_compatible = DRV_OF_COMPAT(rockchip_gpio_dt_match), +}; + +core_platform_driver(rockchip_gpio_driver); diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index f416acc999..49deaf4d98 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -643,14 +643,14 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) /* Initialize the TRB ring */ dep->trb_dequeue = 0; dep->trb_enqueue = 0; - memset(dep->trb_pool, 0, + memset_io(dep->trb_pool, 0, sizeof(struct dwc3_trb) * DWC3_TRB_NUM); /* Link TRB. The HWO bit is never reset */ trb_st_hw = &dep->trb_pool[0]; trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; - memset(trb_link, 0, sizeof(*trb_link)); + memset_io(trb_link, 0, sizeof(*trb_link)); trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); @@ -2908,10 +2908,10 @@ static void dwc3_gadget_poll(struct usb_gadget * g) buf = xzalloc(count); amount = min(count, evt->length - evt->lpos); - memcpy(buf, evt->buf + evt->lpos, amount); + memcpy_fromio(buf, evt->buf + evt->lpos, amount); if (amount < count) - memcpy(buf + amount, evt->buf, count - amount); + memcpy_fromio(buf + amount, evt->buf, count - amount); evt->lpos = (evt->lpos + count) % evt->length; diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 8c4da9fd12..4dd4d1dddb 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -32,6 +32,8 @@ #include <usb/ehci.h> #include <linux/err.h> #include <linux/sizes.h> +#include <linux/clk.h> +#include <linux/phy/phy.h> #include "ehci.h" @@ -1413,6 +1415,9 @@ static int ehci_probe(struct device_d *dev) struct ehci_platform_data *pdata = dev->platform_data; struct device_node *dn = dev->device_node; struct ehci_host *ehci; + struct clk_bulk_data *clks; + int num_clocks, ret; + struct phy *usb2_generic_phy; if (pdata) data.flags = pdata->flags; @@ -1440,6 +1445,27 @@ static int ehci_probe(struct device_d *dev) else data.hcor = NULL; + usb2_generic_phy = phy_optional_get(dev, "usb"); + if (IS_ERR(usb2_generic_phy)) + return PTR_ERR(usb2_generic_phy); + + ret = phy_init(usb2_generic_phy); + if (ret) + return ret; + + ret = phy_power_on(usb2_generic_phy); + if (ret) + return ret; + + ret = clk_bulk_get_all(dev, &clks); + if (ret < 0) + return ret; + + num_clocks = ret; + ret = clk_bulk_enable(num_clocks, clks); + if (ret) + return ret; + ehci = ehci_register(dev, &data); if (IS_ERR(ehci)) return PTR_ERR(ehci); diff --git a/firmware/Makefile b/firmware/Makefile index 3a38c40079..00bdedfc6b 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -9,7 +9,8 @@ firmware-$(CONFIG_FIRMWARE_IMX_LPDDR4_PMU_TRAIN) += \ firmware-$(CONFIG_FIRMWARE_IMX8MM_ATF) += imx8mm-bl31.bin firmware-$(CONFIG_FIRMWARE_IMX8MP_ATF) += imx8mp-bl31.bin firmware-$(CONFIG_FIRMWARE_IMX8MQ_ATF) += imx8mq-bl31.bin - +firmware-$(CONFIG_ARCH_RK3568) += rk3568-bl31.bin +firmware-$(CONFIG_ARCH_RK3568_OPTEE) += rk3568-op-tee.bin firmware-$(CONFIG_DRIVER_NET_FSL_FMAN) += fsl_fman_ucode_ls1046_r1.0_106_4_18.bin firmware-$(CONFIG_ARCH_LAYERSCAPE_PPA) += ppa-ls1046a.bin diff --git a/images/Makefile.rockchip b/images/Makefile.rockchip index 16303164ae..e64fccec6b 100644 --- a/images/Makefile.rockchip +++ b/images/Makefile.rockchip @@ -9,3 +9,13 @@ image-$(CONFIG_MACH_RADXA_ROCK) += barebox-radxa-rock.img pblb-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += start_rk3288_phycore_som FILE_barebox-rk3288-phycore-som.img = start_rk3288_phycore_som.pblb image-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += barebox-rk3288-phycore-som.img + +pblb-$(CONFIG_MACH_RK3568_EVB) += start_rk3568_evb +image-$(CONFIG_MACH_RK3568_EVB) += barebox-rk3568-evb.img + +quiet_cmd_rkimg_image = RK-IMG $@ + cmd_rkimg_image = $(objtree)/scripts/rkimage -o $@ $(word 2,$^) $(word 1,$^) + +$(obj)/barebox-rk3568-evb.img: $(obj)/start_rk3568_evb.pblb \ + $(board)/rockchip-rk3568-evb/sdram-init.bin + $(call if_changed,rkimg_image) diff --git a/include/bootsource.h b/include/bootsource.h index 32295ddd96..646b0e91c1 100644 --- a/include/bootsource.h +++ b/include/bootsource.h @@ -12,6 +12,7 @@ enum bootsource { BOOTSOURCE_SPI, BOOTSOURCE_SPI_EEPROM, BOOTSOURCE_SPI_NOR, + BOOTSOURCE_SPI_NAND, BOOTSOURCE_SERIAL, BOOTSOURCE_ONENAND, BOOTSOURCE_HD, diff --git a/include/filetype.h b/include/filetype.h index ae0920320e..2640847e1f 100644 --- a/include/filetype.h +++ b/include/filetype.h @@ -54,6 +54,7 @@ enum filetype { filetype_stm32_image_v1, filetype_zynq_image, filetype_mxs_sd_image, + filetype_rockchip_rkns_image, filetype_max, }; diff --git a/include/linux/clk.h b/include/linux/clk.h index e54acdd918..6565429a9b 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -681,6 +681,9 @@ static inline const char *clk_hw_get_name(struct clk_hw *hw) return hw->clk.name; } +int clk_name_set_parent(const char *clkname, const char *clkparentname); +int clk_name_set_rate(const char *clkname, unsigned long rate); + #endif struct device_node; @@ -722,6 +725,7 @@ static inline unsigned int clk_get_num_parents(const struct clk *hw) { return hw->num_parents; } + #else diff --git a/scripts/Makefile b/scripts/Makefile index 2d322fd1c9..eb0f5c5805 100644 --- a/scripts/Makefile +++ b/scripts/Makefile @@ -25,6 +25,9 @@ hostprogs-always-$(CONFIG_ARCH_MXS) += mxsimage mxsboot hostprogs-always-$(CONFIG_ARCH_LAYERSCAPE) += pblimage hostprogs-always-$(CONFIG_ARCH_STM32MP) += stm32image hostprogs-always-$(CONFIG_RISCV) += prelink-riscv +hostprogs-always-$(CONFIG_ARCH_ROCKCHIP) += rkimage +HOSTCFLAGS_rkimage = `pkg-config --cflags openssl` +HOSTLDLIBS_rkimage = `pkg-config --libs openssl` KBUILD_HOSTCFLAGS += -I$(srctree)/scripts/include/ HOSTLDLIBS_mxsimage = `pkg-config --libs openssl` HOSTCFLAGS_omap3-usb-loader.o = `pkg-config --cflags libusb-1.0` diff --git a/scripts/rkimage.c b/scripts/rkimage.c new file mode 100644 index 0000000000..dde9724886 --- /dev/null +++ b/scripts/rkimage.c @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <stdio.h> +#include <unistd.h> +#include <getopt.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <stdlib.h> +#include <stdint.h> +#include <string.h> +#include <time.h> +#include <openssl/sha.h> +#include <errno.h> +#include <stdbool.h> + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) +#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) + +static void sha256(const void *buf, int len, void *out) +{ + SHA256_CTX sha256; + + SHA256_Init(&sha256); + SHA256_Update(&sha256, buf, len); + SHA256_Final(out, &sha256); +} + +static void sha512(const void *buf, int len, void *out) +{ + SHA512_CTX sha512; + + SHA512_Init(&sha512); + SHA512_Update(&sha512, buf, len); + SHA512_Final(out, &sha512); +} + +#define NEWIDB_MAGIC 0x534e4b52 /* 'RKNS' */ + +struct newidb_entry { + uint32_t sector; + uint32_t unknown_ffffffff; + uint32_t unknown1; + uint32_t image_number; + unsigned char unknown2[8]; + unsigned char hash[64]; +}; + +struct newidb { + uint32_t magic; + unsigned char unknown1[4]; + uint32_t n_files; + uint32_t hashtype; + unsigned char unknown2[8]; + unsigned char unknown3[8]; + unsigned char unknown4[88]; + struct newidb_entry entries[4]; + unsigned char unknown5[40]; + unsigned char unknown6[512]; + unsigned char unknown7[16]; + unsigned char unknown8[32]; + unsigned char unknown9[464]; + unsigned char hash[512]; +}; + +#define SECTOR_SIZE 512 +#define PAGE_SIZE 2048 + +typedef enum { + HASH_TYPE_SHA256 = 1, + HASH_TYPE_SHA512 = 2, +} hash_type_t; + +struct rkcode { + const char *path; + size_t size; + void *buf; +}; + +static int n_code; +struct rkcode *code; + +static int create_newidb(struct newidb *idb) +{ + hash_type_t hash_type = HASH_TYPE_SHA256; + bool keep_cert = false; + int image_offset; + int i; + unsigned char *idbu8 = (void *)idb; + + idb->magic = NEWIDB_MAGIC; + idb->n_files = (n_code << 16) | (1 << 7) | (1 << 8); + + if (hash_type == HASH_TYPE_SHA256) + idb->hashtype = (1 << 0); + else if (hash_type == HASH_TYPE_SHA512) + idb->hashtype = (1 << 1); + + if (!keep_cert) + image_offset = 4; + else + image_offset = 8; + + for (i = 0; i < n_code; i++) { + struct newidb_entry *entry = &idb->entries[i]; + struct rkcode *c = &code[i]; + unsigned int image_sector; + + image_sector = c->size / SECTOR_SIZE; + + entry->sector = (image_sector << 16) + image_offset; + entry->unknown_ffffffff = 0xffffffff; + entry->image_number = i + 1; + + if (hash_type == HASH_TYPE_SHA256) + sha256(c->buf, c->size, entry->hash); /* File size padded to sector size */ + else if (hash_type == HASH_TYPE_SHA512) + sha512(c->buf, c->size, entry->hash); + + image_offset += image_sector; + + } + + if (hash_type == HASH_TYPE_SHA256) + sha256(idbu8, 1535, idbu8 + 1536); + else if (hash_type == HASH_TYPE_SHA512) + sha512(idbu8, 1535, idbu8 + 1536); + + return 0; +} + +struct option cbootcmd[] = { + {"help", 0, NULL, 'h'}, + {"o", 1, NULL, 'o'}, + {0, 0, 0, 0}, +}; + +static void usage(const char *prgname) +{ + printf( +"Usage: %s [OPTIONS] <FILES>\n" +"\n" +"Generate a Rockchip boot image from <FILES>\n" +"This tool is suitable for SoCs beginning with rk3568. Older SoCs\n" +"have a different image format.\n" +"\n" +"Options:\n" +" -o <file> Output image to <file>\n" +" -h This help\n", + prgname); +} + +static int read_full(int fd, void *buf, size_t size) +{ + size_t insize = size; + int now; + int total = 0; + + while (size) { + now = read(fd, buf, size); + if (now == 0) + return total; + if (now < 0) + return now; + total += now; + size -= now; + buf += now; + } + + return insize; +} + +static int write_full(int fd, void *buf, size_t size) +{ + size_t insize = size; + int now; + + while (size) { + now = write(fd, buf, size); + if (now <= 0) + return now; + size -= now; + buf += now; + } + + return insize; +} + +int main(int argc, char *argv[]) +{ + int opt, i, fd; + const char *outfile = NULL; + struct newidb idb = {}; + + while ((opt = getopt_long(argc, argv, "ho:", cbootcmd, NULL)) > 0) { + switch (opt) { + case 'o': + outfile = optarg; + break; + case 'h': + usage(argv[0]); + exit(0); + } + } + + n_code = argc - optind; + if (!n_code) { + usage(argv[0]); + exit(1); + } + + code = calloc(n_code, sizeof(*code)); + if (!code) + exit(1); + + for (i = 0; i < n_code; i++) { + struct stat s; + int fd, ret; + struct rkcode *c = &code[i]; + const char *path = argv[i + optind]; + + fd = open(path, O_RDONLY); + if (fd < 0) { + fprintf(stderr, "Cannot open %s: %s\n", path, strerror(errno)); + exit(1); + } + + ret = fstat(fd, &s); + if (ret) + exit(1); + + c->path = path; + c->size = ALIGN(s.st_size, PAGE_SIZE); + c->buf = calloc(c->size, 1); + if (!c->buf) + exit(1); + + read_full(fd, c->buf, s.st_size); + close(fd); + } + + create_newidb(&idb); + + fd = creat(outfile, 0644); + if (fd < 0) { + fprintf(stderr, "Cannot open %s: %s\n", outfile, strerror(errno)); + exit(1); + } + + write_full(fd, &idb, sizeof(idb)); + + for (i = 0; i < n_code; i++) { + struct rkcode *c = &code[i]; + + write_full(fd, c->buf, c->size); + } + + close(fd); + + return 0; +} |