diff options
46 files changed, 1857 insertions, 537 deletions
diff --git a/.gitignore b/.gitignore index d83d3176e8..dd1a052ea1 100644 --- a/.gitignore +++ b/.gitignore @@ -30,6 +30,7 @@ *.so *.so.dbg *.symtypes +*.bin.gen.S Module.symvers # diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 0c21002e91..c737cf3413 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -154,3 +154,4 @@ obj-$(CONFIG_MACH_VF610_TWR) += freescale-vf610-twr/ obj-$(CONFIG_MACH_ZII_RDU1) += zii-imx51-rdu1/ obj-$(CONFIG_MACH_ZII_RDU2) += zii-imx6q-rdu2/ obj-$(CONFIG_MACH_ZII_VF610_DEV) += zii-vf610-dev/ +obj-$(CONFIG_MACH_ZII_IMX7D_RPU2) += zii-imx7d-rpu2/ diff --git a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg index 83ed2dc065..f4920bc133 100644 --- a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg +++ b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg @@ -1,82 +1,5 @@ -/* - * Copyright (C) 2016 NXP Semiconductors - * - * SPDX-License-Identifier: GPL-2.0 - * - * Refer docs/README.imxmage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - * - * Taken from upstream U-Boot git://git.denx.de/u-boot.git, commit - * 1a8150d4b16fbafa6f1d207ddb85eda7dc399e2d - */ - soc imx7 loadaddr 0x80000000 dcdofs 0x400 -#include <mach/imx7-ddr-regs.h> - -wm 32 0x30340004 0x4F400005 - -wm 32 0x30391000 0x00000002 - -wm 32 MX7_DDRC_MSTR 0x01040001 -wm 32 MX7_DDRC_DFIUPD0 0x80400003 -wm 32 MX7_DDRC_DFIUPD1 0x00100020 -wm 32 MX7_DDRC_DFIUPD2 0x80100004 -wm 32 MX7_DDRC_RFSHTMG 0x00400046 -wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001 -wm 32 MX7_DDRC_INIT0 0x00020083 -wm 32 MX7_DDRC_INIT1 0x00690000 -wm 32 MX7_DDRC_INIT3 0x09300004 -wm 32 MX7_DDRC_INIT4 0x04080000 -wm 32 MX7_DDRC_INIT5 0x00100004 -wm 32 MX7_DDRC_RANKCTL 0x0000033f -wm 32 MX7_DDRC_DRAMTMG0 0x09081109 -wm 32 MX7_DDRC_DRAMTMG1 0x0007020d -wm 32 MX7_DDRC_DRAMTMG2 0x03040407 -wm 32 MX7_DDRC_DRAMTMG3 0x00002006 -wm 32 MX7_DDRC_DRAMTMG4 0x04020205 -wm 32 MX7_DDRC_DRAMTMG5 0x03030202 -wm 32 MX7_DDRC_DRAMTMG8 0x00000803 -wm 32 MX7_DDRC_ZQCTL0 0x00800020 -wm 32 MX7_DDRC_ZQCTL1 0x02000100 -wm 32 MX7_DDRC_DFITMG0 0x02098204 -wm 32 MX7_DDRC_DFITMG1 0x00030303 -wm 32 MX7_DDRC_ADDRMAP0 0x00000016 -wm 32 MX7_DDRC_ADDRMAP1 0x00171717 -wm 32 MX7_DDRC_ADDRMAP5 0x04040404 -wm 32 MX7_DDRC_ADDRMAP6 0x0f040404 -wm 32 MX7_DDRC_ODTCFG 0x06000604 -wm 32 MX7_DDRC_ODTMAP 0x00000001 - -wm 32 0x30391000 0x00000000 - -wm 32 MX7_DDR_PHY_PHY_CON0 0x17420f40 -wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100 -wm 32 MX7_DDR_PHY_PHY_CON4 0x00060807 -wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e -wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e -wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x08080808 -wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x08080808 -wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000010 -wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000010 - -wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 -wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 -wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306 - -check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1 - -wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 -wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 - -wm 32 0x30384130 0x00000000 -wm 32 0x30340020 0x00000178 -wm 32 0x30384130 0x00000002 - -wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f - -check 32 until_any_bit_set MX7_DDRC_STAT 0x1 +#include <mach/flash-header/imx7d-ddr-sabresd.imxcfg>
\ No newline at end of file diff --git a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c index 43aa610759..f718ea73b3 100644 --- a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c +++ b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c @@ -9,6 +9,7 @@ #include <mach/iomux-mx7.h> #include <mach/debug_ll.h> #include <asm/cache.h> +#include <mach/esdctl.h> extern char __dtb_imx7d_sdb_start[]; @@ -33,14 +34,10 @@ static inline void setup_uart(void) ENTRY_FUNCTION(start_imx7d_sabresd, r0, r1, r2) { - void *fdt; - imx7_cpu_lowlevel_init(); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); - fdt = __dtb_imx7d_sdb_start + get_runtime_offset(); - - barebox_arm_entry(0x80000000, SZ_1G, fdt); + imx7d_barebox_entry(__dtb_imx7d_sdb_start + get_runtime_offset()); } diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c index 868c25ebb2..764eadb766 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/board.c +++ b/arch/arm/boards/nxp-imx8mq-evk/board.c @@ -21,11 +21,34 @@ #include <init.h> #include <asm/memory.h> #include <linux/sizes.h> +#include <linux/phy.h> #include <mach/bbu.h> +#include <envfs.h> + +#define PHY_ID_AR8031 0x004dd074 +#define AR_PHY_ID_MASK 0xffffffff + +static int ar8031_phy_fixup(struct phy_device *phydev) +{ + /* + * Enable 1.8V(SEL_1P5_1P8_POS_REG) on + * Phy control debug reg 0 + */ + phy_write(phydev, 0x1d, 0x1f); + phy_write(phydev, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, 0x1d, 0x05); + phy_write(phydev, 0x1e, 0x100); + + return 0; +} + static int imx8mq_evk_mem_init(void) { - arm_add_mem_device("ram0", 0x40000000, SZ_2G); + if (!of_machine_is_compatible("fsl,imx8mq-evk")) + return 0; request_sdram_region("ATF", 0x40000000, SZ_128K); @@ -42,6 +65,8 @@ static int nxp_imx8mq_evk_init(void) imx8mq_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc0", 0); + phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, + ar8031_phy_fixup); return 0; } device_initcall(nxp_imx8mq_evk_init); diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index 438c70c87e..1dff4b4d31 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -24,6 +24,7 @@ #include <asm/sections.h> #include <asm/mmu.h> #include <mach/atf.h> +#include <mach/esdctl.h> #include "ddr.h" @@ -121,7 +122,6 @@ ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2) /* * Standard entry we hit once we initialized both DDR and ATF */ - barebox_arm_entry(MX8MQ_DDR_CSD1_BASE_ADDR, - SZ_2G + SZ_1G, __dtb_imx8mq_evk_start); + imx8mq_barebox_entry(__dtb_imx8mq_evk_start); } diff --git a/arch/arm/boards/zii-imx51-rdu1/board.c b/arch/arm/boards/zii-imx51-rdu1/board.c index ac5232e17b..46368ccccf 100644 --- a/arch/arm/boards/zii-imx51-rdu1/board.c +++ b/arch/arm/boards/zii-imx51-rdu1/board.c @@ -23,15 +23,21 @@ static int zii_rdu1_init(void) { - if (!of_machine_is_compatible("zii,imx51-rdu1")) + const char *hostname; + + if (!of_machine_is_compatible("zii,imx51-rdu1") && + !of_machine_is_compatible("zii,imx51-scu2-mezz") && + !of_machine_is_compatible("zii,imx51-scu3-esb")) return 0; + hostname = of_get_machine_compatible() + strlen("imx51-"); + imx51_babbage_power_init(); - barebox_set_hostname("rdu1"); + barebox_set_hostname(hostname); - imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0", 0); - imx51_bbu_internal_spi_i2c_register_handler("spi", + imx51_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", 0); + imx51_bbu_internal_spi_i2c_register_handler("SPI", "/dev/dataflash0.barebox", BBU_HANDLER_FLAG_DEFAULT | IMX_BBU_FLAG_PARTITION_STARTS_AT_HEADER); diff --git a/arch/arm/boards/zii-imx51-rdu1/lowlevel.c b/arch/arm/boards/zii-imx51-rdu1/lowlevel.c index cca331a9cb..849c5624c5 100644 --- a/arch/arm/boards/zii-imx51-rdu1/lowlevel.c +++ b/arch/arm/boards/zii-imx51-rdu1/lowlevel.c @@ -29,18 +29,89 @@ static inline void setup_uart(void) putc_ll('>'); } +enum zii_platform_imx51_type { + ZII_PLATFORM_IMX51_RDU_REV_B = 0b0000, + ZII_PLATFORM_IMX51_SCU2_ESB = 0b0001, + ZII_PLATFORM_IMX51_SCU_MEZZ = 0b0010, + ZII_PLATFORM_IMX51_NIU_REV = 0b0011, + ZII_PLATFORM_IMX51_SCU2_MEZZ = 0b0100, + ZII_PLATFORM_IMX51_SCU3_ESB = 0b0101, + ZII_PLATFORM_IMX51_RDU_REV_C = 0b1101, +}; + +static unsigned int get_system_type(void) +{ +#define GPIO_DR 0x000 +#define GPIO_GDIR 0x004 +#define SYSTEM_TYPE GENMASK(6, 3) + + u32 gdir, dr; + void __iomem *gpio4 = IOMEM(MX51_GPIO4_BASE_ADDR); + void __iomem *iomuxbase = IOMEM(MX51_IOMUXC_BASE_ADDR); + + /* + * System type is encoded as a 4-bit number specified by the + * following pins (pulled up or down with resistors on the + * board). + */ + imx_setup_pad(iomuxbase, MX51_PAD_NANDF_D2__GPIO4_6); + imx_setup_pad(iomuxbase, MX51_PAD_NANDF_D3__GPIO4_5); + imx_setup_pad(iomuxbase, MX51_PAD_NANDF_D4__GPIO4_4); + imx_setup_pad(iomuxbase, MX51_PAD_NANDF_D5__GPIO4_3); + + gdir = readl(gpio4 + GPIO_GDIR); + gdir &= ~SYSTEM_TYPE; + writel(gdir, gpio4 + GPIO_GDIR); + + dr = readl(gpio4 + GPIO_DR); + + return FIELD_GET(SYSTEM_TYPE, dr); +} + extern char __dtb_imx51_zii_rdu1_start[]; +extern char __dtb_imx51_zii_scu2_mezz_start[]; +extern char __dtb_imx51_zii_scu3_esb_start[]; ENTRY_FUNCTION(start_imx51_zii_rdu1, r0, r1, r2) { void *fdt; + const unsigned int system_type = get_system_type(); imx5_cpu_lowlevel_init(); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); - fdt = __dtb_imx51_zii_rdu1_start + get_runtime_offset(); + switch (system_type) { + default: + /* + * see similar code in + * arch/arm/boards/zii-vf610-dev/lowlevel.c for + * reasoning for placing barrier() below. + */ + barrier(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) { + relocate_to_current_adr(); + setup_c(); + puts_ll("\n*********************************\n"); + puts_ll("* Unknown system type: "); + puthex_ll(system_type); + puts_ll("\n* Assuming RDU1\n"); + puts_ll("*********************************\n"); + } + /* FALLTHROUGH */ + case ZII_PLATFORM_IMX51_RDU_REV_B: + case ZII_PLATFORM_IMX51_RDU_REV_C: + fdt = __dtb_imx51_zii_rdu1_start; + break; + case ZII_PLATFORM_IMX51_SCU2_MEZZ: + fdt = __dtb_imx51_zii_scu2_mezz_start; + break; + case ZII_PLATFORM_IMX51_SCU3_ESB: + fdt = __dtb_imx51_zii_scu3_esb_start; + break; + } - imx51_barebox_entry(fdt); + imx51_barebox_entry(fdt + get_runtime_offset()); } diff --git a/arch/arm/boards/zii-imx6q-rdu2/board.c b/arch/arm/boards/zii-imx6q-rdu2/board.c index f6c908c9f1..c99f993f02 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/board.c +++ b/arch/arm/boards/zii-imx6q-rdu2/board.c @@ -146,7 +146,7 @@ static int rdu2_devices_init(void) imx6_bbu_internal_spi_i2c_register_handler("SPI", "/dev/m25p0.barebox", BBU_HANDLER_FLAG_DEFAULT); - imx6_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc3", 0); + imx6_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc3", 0); defaultenv_append_directory(defaultenv_rdu2); diff --git a/arch/arm/boards/zii-imx7d-rpu2/Makefile b/arch/arm/boards/zii-imx7d-rpu2/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/zii-imx7d-rpu2/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/zii-imx7d-rpu2/board.c b/arch/arm/boards/zii-imx7d-rpu2/board.c new file mode 100644 index 0000000000..0a99976b7d --- /dev/null +++ b/arch/arm/boards/zii-imx7d-rpu2/board.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright (C) 2018 Zodiac Inflight Innovation + * Author: Andrey Smirnov <andrew.smirnov@gmail.com> + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <gpio.h> +#include <mach/imx7-regs.h> +#include <mfd/imx7-iomuxc-gpr.h> +#include <environment.h> +#include <envfs.h> +#include <mach/bbu.h> + +static void zii_imx7d_rpu2_init_fec(void) +{ + void __iomem *gpr = IOMEM(MX7_IOMUXC_GPR_BASE_ADDR); + uint32_t gpr1; + + /* + * Make sure we do not drive ENETn_TX_CLK signal + */ + gpr1 = readl(gpr + IOMUXC_GPR1); + gpr1 &= ~(IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK | + IMX7D_GPR1_ENET1_CLK_DIR_MASK | + IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK | + IMX7D_GPR1_ENET2_CLK_DIR_MASK); + writel(gpr1, gpr + IOMUXC_GPR1); +} + +static int zii_imx7d_rpu2_coredevices_init(void) +{ + if (!of_machine_is_compatible("zii,imx7d-zii-rpu2")) + return 0; + + zii_imx7d_rpu2_init_fec(); + + imx7_bbu_internal_spi_i2c_register_handler("SPI", "/dev/m25p0.barebox", + BBU_HANDLER_FLAG_DEFAULT); + + imx7_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", 0); + + return 0; +} +coredevice_initcall(zii_imx7d_rpu2_coredevices_init); + diff --git a/arch/arm/boards/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg b/arch/arm/boards/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg new file mode 100644 index 0000000000..46f3d95048 --- /dev/null +++ b/arch/arm/boards/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg @@ -0,0 +1,6 @@ +soc imx7 +loadaddr 0x80000000 +dcdofs 0x400 + +#include <mach/flash-header/imx7d-ddr-sabresd.imxcfg> + diff --git a/arch/arm/boards/zii-imx7d-rpu2/lowlevel.c b/arch/arm/boards/zii-imx7d-rpu2/lowlevel.c new file mode 100644 index 0000000000..1eeab7d216 --- /dev/null +++ b/arch/arm/boards/zii-imx7d-rpu2/lowlevel.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright (C) 2018 Zodiac Inflight Innovation + * Author: Andrey Smirnov <andrew.smirnov@gmail.com> + */ + +#include <debug_ll.h> +#include <io.h> +#include <common.h> +#include <linux/sizes.h> +#include <mach/generic.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/imx7-ccm-regs.h> +#include <mach/iomux-mx7.h> +#include <mach/debug_ll.h> +#include <asm/cache.h> +#include <mach/esdctl.h> + +extern char __dtb_imx7d_zii_rpu2_start[]; + +static inline void setup_uart(void) +{ + void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR); + void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR); + + writel(CCM_CCGR_SETTINGn_NEEDED(0), + ccm + CCM_CCGRn_CLR(CCM_CCGR_UART2)); + writel(CCM_TARGET_ROOTn_ENABLE | UART2_CLK_ROOT__OSC_24M, + ccm + CCM_TARGET_ROOTn(UART2_CLK_ROOT)); + writel(CCM_CCGR_SETTINGn_NEEDED(0), + ccm + CCM_CCGRn_SET(CCM_CCGR_UART2)); + + mx7_setup_pad(iomux, MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX); + + imx7_uart_setup_ll(); + + putc_ll('>'); +} + +ENTRY_FUNCTION(start_zii_imx7d_rpu2, r0, r1, r2) +{ + imx7_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + imx7d_barebox_entry(__dtb_imx7d_zii_rpu2_start + get_runtime_offset()); +} diff --git a/arch/arm/boards/zii-vf610-dev/board.c b/arch/arm/boards/zii-vf610-dev/board.c index 91c653804e..275d0a432c 100644 --- a/arch/arm/boards/zii-vf610-dev/board.c +++ b/arch/arm/boards/zii-vf610-dev/board.c @@ -53,7 +53,7 @@ static int zii_vf610_cfu1_expose_signals(void) }, }; - if (!of_machine_is_compatible("zii,vf610cfu1-a")) + if (!of_machine_is_compatible("zii,vf610cfu1")) return 0; return expose_signals(signals, ARRAY_SIZE(signals)); @@ -75,8 +75,8 @@ static int zii_vf610_cfu1_spu3_expose_signals(void) }, }; - if (!of_machine_is_compatible("zii,vf610spu3-a") && - !of_machine_is_compatible("zii,vf610cfu1-a")) + if (!of_machine_is_compatible("zii,vf610spu3") && + !of_machine_is_compatible("zii,vf610cfu1")) return 0; return expose_signals(signals, ARRAY_SIZE(signals)); @@ -127,8 +127,8 @@ static int zii_vf610_dev_set_hostname(void) const char *compatible; const char *hostname; } boards[] = { - { "zii,vf610spu3-a", "spu3-rev-a" }, - { "zii,vf610cfu1-a", "cfu1-rev-a" }, + { "zii,vf610spu3", "spu3" }, + { "zii,vf610cfu1", "cfu1" }, { "zii,vf610dev-b", "dev-rev-b" }, { "zii,vf610dev-c", "dev-rev-c" }, { "zii,vf610scu4-aib-c", "scu4-aib-rev-c" }, @@ -168,14 +168,17 @@ static int zii_vf610_dev_register_bbu(void) } late_initcall(zii_vf610_dev_register_bbu); -static int zii_vf610_spu3_register_bbu(void) +static int zii_vf610_register_emmc_bbu(void) { int ret; - if (!of_machine_is_compatible("zii,vf610spu3-a")) + + if (!of_machine_is_compatible("zii,vf610spu3") && + !of_machine_is_compatible("zii,vf610cfu1")) return 0; - ret = vf610_bbu_internal_mmc_register_handler("eMMC", "/dev/disk0", - BBU_HANDLER_FLAG_DEFAULT); + ret = vf610_bbu_internal_mmcboot_register_handler("eMMC", + "/dev/mmc0", + BBU_HANDLER_FLAG_DEFAULT); if (ret) { pr_err("Failed to register eMMC BBU handler\n"); return ret; @@ -183,4 +186,4 @@ static int zii_vf610_spu3_register_bbu(void) return 0; } -late_initcall(zii_vf610_spu3_register_bbu);
\ No newline at end of file +late_initcall(zii_vf610_register_emmc_bbu);
\ No newline at end of file diff --git a/arch/arm/boards/zii-vf610-dev/lowlevel.c b/arch/arm/boards/zii-vf610-dev/lowlevel.c index c771d81ccf..d19318026c 100644 --- a/arch/arm/boards/zii-vf610-dev/lowlevel.c +++ b/arch/arm/boards/zii-vf610-dev/lowlevel.c @@ -38,7 +38,7 @@ static inline void setup_uart(void) enum zii_platform_vf610_type { ZII_PLATFORM_VF610_DEV_REV_B = 0x01, ZII_PLATFORM_VF610_SCU4_AIB = 0x02, - ZII_PLATFORM_VF610_SPU3 = 0x03, + ZII_PLATFORM_VF610_SSMB_SPU3 = 0x03, ZII_PLATFORM_VF610_CFU1 = 0x04, ZII_PLATFORM_VF610_DEV_REV_C = 0x05, }; @@ -75,8 +75,8 @@ static unsigned int get_system_type(void) extern char __dtb_vf610_zii_dev_rev_b_start[]; extern char __dtb_vf610_zii_dev_rev_c_start[]; -extern char __dtb_vf610_zii_cfu1_rev_a_start[]; -extern char __dtb_vf610_zii_spu3_rev_a_start[]; +extern char __dtb_vf610_zii_cfu1_start[]; +extern char __dtb_vf610_zii_ssmb_spu3_start[]; extern char __dtb_vf610_zii_scu4_aib_rev_c_start[]; ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2) @@ -127,10 +127,10 @@ ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2) fdt = __dtb_vf610_zii_dev_rev_c_start; break; case ZII_PLATFORM_VF610_CFU1: - fdt = __dtb_vf610_zii_cfu1_rev_a_start; + fdt = __dtb_vf610_zii_cfu1_start; break; - case ZII_PLATFORM_VF610_SPU3: - fdt = __dtb_vf610_zii_spu3_rev_a_start; + case ZII_PLATFORM_VF610_SSMB_SPU3: + fdt = __dtb_vf610_zii_ssmb_spu3_start; break; } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7ec10bf200..1caeca35b4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -103,15 +103,20 @@ pbl-dtb-$(CONFIG_MACH_VEXPRESS) += vexpress-v2p-ca15.dtb.o pbl-dtb-$(CONFIG_MACH_VSCOM_BALTOS) += am335x-baltos-minimal.dtb.o pbl-dtb-$(CONFIG_MACH_WARP7) += imx7s-warp.dtb.o pbl-dtb-$(CONFIG_MACH_VF610_TWR) += vf610-twr.dtb.o -pbl-dtb-$(CONFIG_MACH_ZII_RDU1) += imx51-zii-rdu1.dtb.o +pbl-dtb-$(CONFIG_MACH_ZII_RDU1) += \ + imx51-zii-rdu1.dtb.o \ + imx51-zii-scu2-mezz.dtb.o \ + imx51-zii-scu3-esb.dtb.o pbl-dtb-$(CONFIG_MACH_ZII_RDU2) += imx6q-zii-rdu2.dtb.o imx6qp-zii-rdu2.dtb.o pbl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \ vf610-zii-dev-rev-b.dtb.o \ vf610-zii-dev-rev-c.dtb.o \ - vf610-zii-cfu1-rev-a.dtb.o \ - vf610-zii-spu3-rev-a.dtb.o \ + vf610-zii-cfu1.dtb.o \ + vf610-zii-ssmb-spu3.dtb.o \ vf610-zii-scu4-aib-rev-c.dtb.o pbl-dtb-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o pbl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o +pbl-dtb-$(CONFIG_MACH_ZII_IMX7D_RPU2) += imx7d-zii-rpu2.dtb.o + clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo diff --git a/arch/arm/dts/imx51-zii-rdu1.dts b/arch/arm/dts/imx51-zii-rdu1.dts index bde565fe08..93bb344f51 100644 --- a/arch/arm/dts/imx51-zii-rdu1.dts +++ b/arch/arm/dts/imx51-zii-rdu1.dts @@ -53,37 +53,16 @@ &uart3 { rave-sp { - #address-cells = <1>; - #size-cells = <1>; - watchdog { nvmem-cells = <&boot_source>; nvmem-cell-names = "boot-source"; }; - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "dds-eeprom"; - }; - eeprom@a4 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa4 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - boot_source: boot-source@83 { reg = <0x83 1>; }; }; - - backlight { - compatible = "zii,rave-sp-backlight"; - }; }; }; diff --git a/arch/arm/dts/imx51-zii-scu2-mezz.dts b/arch/arm/dts/imx51-zii-scu2-mezz.dts new file mode 100644 index 0000000000..68a374bb2b --- /dev/null +++ b/arch/arm/dts/imx51-zii-scu2-mezz.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +#include <arm/imx51-zii-scu2-mezz.dts> + +&iim { + barebox,provide-mac-address = <&fec 1 9>; +}; diff --git a/arch/arm/dts/imx51-zii-scu3-esb.dts b/arch/arm/dts/imx51-zii-scu3-esb.dts new file mode 100644 index 0000000000..c83bf17316 --- /dev/null +++ b/arch/arm/dts/imx51-zii-scu3-esb.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + + +#include <arm/imx51-zii-scu3-esb.dts> + +&iim { + barebox,provide-mac-address = <&fec 1 9>; +}; diff --git a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi index a74fb47831..f63b5d2ed7 100644 --- a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi @@ -66,19 +66,7 @@ nvmem-cell-names = "boot-source"; }; - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x4000>; - zii,eeprom-name = "dds-eeprom"; - }; - eeprom@a4 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa4 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - boot_source: boot-source@83 { reg = <0x83 1>; }; @@ -91,10 +79,6 @@ reg = <0x190 6>; }; }; - - backlight { - compatible = "zii,rave-sp-backlight"; - }; }; }; diff --git a/arch/arm/dts/imx7d-ddrc.dtsi b/arch/arm/dts/imx7d-ddrc.dtsi new file mode 100644 index 0000000000..b4cd597be9 --- /dev/null +++ b/arch/arm/dts/imx7d-ddrc.dtsi @@ -0,0 +1,15 @@ +/* + * Include file to switch board DTS form using hardcoded memory node + * to dynamic memory size detection based on DDR controller settings + */ + +/ { + /delete-node/ memory; +}; + +&aips2 { + ddrc@307a0000 { + compatible = "fsl,imx7d-ddrc"; + reg = <0x307a0000 0x10000>; + }; +};
\ No newline at end of file diff --git a/arch/arm/dts/imx7d-zii-rpu2.dts b/arch/arm/dts/imx7d-zii-rpu2.dts new file mode 100644 index 0000000000..6fba73f437 --- /dev/null +++ b/arch/arm/dts/imx7d-zii-rpu2.dts @@ -0,0 +1,613 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <arm/imx7d.dtsi> + +#include "imx7d-ddrc.dtsi" + +/ { + model = "ZII RPU2 Board"; + compatible = "zii,imx7d-zii-rpu2","fsl,imx7d"; + + chosen { + stdout-path = &uart2; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + debug { + label = "zii:green:debug1"; + gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_sd1_vmmc: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + enable-active-high; + }; + + reg_can1_3v3: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + reg_can2_3v3: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + + reg_vref_1v8: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + wlreg_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "wlreg_on"; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "GEN_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v_main: regulator-5p0v-main { + compatible = "regulator-fixed"; + regulator-name = "5V_MAIN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&clks { + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <884736000>; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + + nor_flash: nor-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xc0000>; + }; + + partition@c0000 { + label = "barebox-environment"; + reg = <0xc0000 0x40000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <&port_fec1>; + status = "okay"; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom-length = <512>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + label = "eth_cu_1000_1"; + }; + port@1 { + reg = <1>; + label = "eth_cu_1000_2"; + }; + + port@2 { + reg = <2>; + label = "pic"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port_fec1: port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&fec1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port_fec2: port@6 { + reg = <6>; + label = "data"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <&port_fec1>; + fsl,magic-packet; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + nameplate_eeprom: at24c04@50 { + compatible = "atmel,24c04"; + #address-cells=<1>; + #size-cells=<1>; + reg = <0x50>; + }; + + sandbox_eeprom: at24c04@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&sdma { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + nvmem-cells = <&boot_source>; + nvmem-cell-names = "boot-source"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + + boot_source: boot-source@83 { + reg = <0x83 1>; + }; + }; + }; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + keep-power-in-suspend; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + fsl,wdog_b; +}; + + +&iomuxc { + pinctrl_leds_debug: debuggrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59 /* HB_LED */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 + MX7D_PAD_SD2_WP__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x4000007f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x4000007f + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x4000007f + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79 + MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 + >; + }; +}; + diff --git a/arch/arm/dts/imx8mq-ddrc.dtsi b/arch/arm/dts/imx8mq-ddrc.dtsi new file mode 100644 index 0000000000..26d3da8579 --- /dev/null +++ b/arch/arm/dts/imx8mq-ddrc.dtsi @@ -0,0 +1,17 @@ +/* + * Include file to switch board DTS form using hardcoded memory node + * to dynamic memory size detection based on DDR controller settings + */ + +/ { + + /delete-node/ memory@40000000; + + peripherals@0 { + ddrc@3d400000 { + compatible = "fsl,imx8mq-ddrc"; + reg = <0x3d400000 0x400000>; + }; + }; +}; + diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts index 3ac13baa18..a6e724e2e2 100644 --- a/arch/arm/dts/imx8mq-evk.dts +++ b/arch/arm/dts/imx8mq-evk.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "imx8mq.dtsi" +#include "imx8mq-ddrc.dtsi" / { model = "NXP i.MX8MQ EVK"; @@ -16,11 +17,6 @@ stdout-path = &uart1; }; - memory@40000000 { - device_type = "memory"; - reg = <0x00000000 0x40000000 0 0xc0000000>; - }; - reg_usdhc2_vmmc: regulator-vsd-3v3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usdhc2>; @@ -43,6 +39,7 @@ <&pinctrl_fec1_data_tx>, <&pinctrl_fec1_data_rx>, <&pinctrl_fec1_phy_reset>; phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index c67438a48e..f89bee200e 100644 --- a/arch/arm/dts/imx8mq.dtsi +++ b/arch/arm/dts/imx8mq.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/clock/imx8mq-clock.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> #include "imx8mq-pinfunc.h" /* first 128 KiB of memory are owned by ATF */ @@ -96,6 +97,7 @@ reg = <0x0>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_1: cpu@1 { @@ -214,6 +216,89 @@ #interrupt-cells = <2>; }; + tmu: tmu@30260000 { + compatible = "fsl,imx8mq-tmu"; + reg = <0x30260000 0x10000>; + interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; + fsl,tmu-calibration = <0x00000000 0x00000023 + 0x00000001 0x00000029 + 0x00000002 0x0000002f + 0x00000003 0x00000035 + 0x00000004 0x0000003d + 0x00000005 0x00000043 + 0x00000006 0x0000004b + 0x00000007 0x00000051 + 0x00000008 0x00000057 + 0x00000009 0x0000005f + 0x0000000a 0x00000067 + 0x0000000b 0x0000006f + + 0x00010000 0x0000001b + 0x00010001 0x00000023 + 0x00010002 0x0000002b + 0x00010003 0x00000033 + 0x00010004 0x0000003b + 0x00010005 0x00000043 + 0x00010006 0x0000004b + 0x00010007 0x00000055 + 0x00010008 0x0000005d + 0x00010009 0x00000067 + 0x0001000a 0x00000070 + + 0x00020000 0x00000017 + 0x00020001 0x00000023 + 0x00020002 0x0000002d + 0x00020003 0x00000037 + 0x00020004 0x00000041 + 0x00020005 0x0000004b + 0x00020006 0x00000057 + 0x00020007 0x00000063 + 0x00020008 0x0000006f + + 0x00030000 0x00000015 + 0x00030001 0x00000021 + 0x00030002 0x0000002d + 0x00030003 0x00000039 + 0x00030004 0x00000045 + 0x00030005 0x00000053 + 0x00030006 0x0000005f + 0x00030007 0x00000071>; + #thermal-sensor-cells = <0>; + }; + + thermal-zones { + /* cpu thermal */ + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + iomuxc: iomuxc@30330000 { compatible = "fsl,imx8mq-iomuxc"; reg = <0x30330000 0x10000>; @@ -288,6 +373,16 @@ #size-cells = <1>; ranges = <0x30800000 0x30800000 0x400000>; + ecspi1: ecspi@30820000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, + <&clk IMX8MQ_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart1: serial@30860000 { compatible = "fsl,imx8mq-uart", "fsl,imx6q-uart"; @@ -622,3 +717,35 @@ }; }; }; + + + +&clk { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_SRC>, + <&clk IMX8MQ_CLK_USDHC1_DIV>, + <&clk IMX8MQ_CLK_USDHC2_SRC>, + <&clk IMX8MQ_CLK_USDHC2_DIV>, + <&clk IMX8MQ_CLK_ENET_AXI_SRC>, + <&clk IMX8MQ_CLK_ENET_TIMER_SRC>, + <&clk IMX8MQ_CLK_ENET_REF_SRC>, + <&clk IMX8MQ_CLK_ENET_TIMER_DIV>; + + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_400M>, + <0>, + <&clk IMX8MQ_SYS1_PLL_400M>, + <0>, + <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS2_PLL_125M>, + <0>; + + assigned-clock-rates = <400000000>, + <200000000>, + <400000000>, + <200000000>, + <266000000>, + <0>, + <125000000>, + <25000000>; +}; + diff --git a/arch/arm/dts/vf610-twr.dts b/arch/arm/dts/vf610-twr.dts index 2456ade5f5..ac2774979e 100644 --- a/arch/arm/dts/vf610-twr.dts +++ b/arch/arm/dts/vf610-twr.dts @@ -8,6 +8,7 @@ */ #include <arm/vf610-twr.dts> +#include "vf610.dtsi" #include "vf610-ddrmc.dtsi" &usbdev0 { diff --git a/arch/arm/dts/vf610-zii-cfu1-rev-a.dts b/arch/arm/dts/vf610-zii-cfu1-rev-a.dts deleted file mode 100644 index 7e87a15c11..0000000000 --- a/arch/arm/dts/vf610-zii-cfu1-rev-a.dts +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - * - * Based on an original 'vf610-twr.dts' which is Copyright 2015, - * Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include <arm/vf610-zii-dev.dtsi> - -#include "vf610-zii-dev.dtsi" - -/ { - model = "ZII VF610 CFU1 Switch Management Board"; - compatible = "zii,vf610cfu1-a", "zii,vf610dev", "fsl,vf610"; - - aliases { - /delete-property/ serial1; - /delete-property/ serial2; - }; - - gpio-leds { - debug { - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; - }; - - fail { - label = "zii_fail"; - gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - max-brightness = <1>; - }; - - status { - label = "zii_status"; - gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; - max-brightness = <1>; - }; - - status_a { - label = "zii_status_a"; - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - default-state = "off"; - max-brightness = <1>; - }; - - status_b { - label = "zii_status_b"; - gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; - default-state = "on"; - max-brightness = <1>; - }; - }; -}; - -&dspi1 { - bus-num = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi1>; - status = "okay"; - - m25p128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - - partition@0 { - label = "m25p128-0"; - reg = <0x0 0x01000000>; - }; - }; -}; - -&esdhc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc0>; - bus-width = <8>; - status = "okay"; -}; - -&fec0 { - status = "disabled"; -}; - -&i2c0 { - clock-frequency = <400000>; - - pca9554@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -/delete-node/ &i2c1; -/delete-node/ &i2c2; -/delete-node/ &uart1; -/delete-node/ &uart2; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 /* SOC_SW_RSTn */ - VF610_PAD_PTB28__GPIO_98 0x31c1 /* E6352_INTn */ - - /* PTE27 is wired to signal SD on part CONN - * SFF-F4 via net FIM_DS. An active high - * on this indicates a received optical - * signal - - * SPEED=0b11 HIGH, SRE=0b0, ODE=0b0, HYS=0b0 - * DSE=0b001 150Ohm, PUS=0b10 100k UP - * PKE=0b0, PUE=0b0, OBE=0b0, IBE=0b1 - */ - VF610_PAD_PTE27__GPIO_132 0x3061 - - /* - * PTE13 is wired to signal T_DIS on part CONN - * SFF-F4 via net FIM_TDIS. Setting this high - * will disable optical output from the SFF-F4 - - * SPEED=0b11 HIGH, SRE=0b0, ODE=0b0, HYS=0b0 - * DSE=0b001 150Ohm, PUS=0b00 100k DOWN - * PKE=0b0, PUE=0b0, OBE=0b1, IBE=0b1 - * TODO: probably want IBE=0b0 - */ - VF610_PAD_PTE13__GPIO_118 0x3043 - >; - }; - - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x1182 - VF610_PAD_PTC6__DSPI1_SIN 0x1181 - VF610_PAD_PTC7__DSPI1_SOUT 0x1182 - VF610_PAD_PTC8__DSPI1_SCK 0x1182 - >; - }; - - pinctrl_esdhc0: esdhc0grp { - fsl,pins = < - VF610_PAD_PTC0__ESDHC0_CLK 0x31ef - VF610_PAD_PTC1__ESDHC0_CMD 0x31ef - VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef - VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef - VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef - VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef - VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef - VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef - VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef - VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTD3__GPIO_82 0x31c2 - VF610_PAD_PTE3__GPIO_108 0x31c2 - VF610_PAD_PTE4__GPIO_109 0x31c2 - VF610_PAD_PTE5__GPIO_110 0x31c2 - VF610_PAD_PTE6__GPIO_111 0x31c2 - >; - }; -}; diff --git a/arch/arm/dts/vf610-zii-cfu1.dts b/arch/arm/dts/vf610-zii-cfu1.dts new file mode 100644 index 0000000000..80d3f54f78 --- /dev/null +++ b/arch/arm/dts/vf610-zii-cfu1.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2015, 2016 Zodiac Inflight Innovations + */ + +#include <arm/vf610-zii-cfu1.dts> + +#include "vf610-zii-dev.dtsi" + diff --git a/arch/arm/dts/vf610-zii-dev.dtsi b/arch/arm/dts/vf610-zii-dev.dtsi index dc16280bc3..b6db262027 100644 --- a/arch/arm/dts/vf610-zii-dev.dtsi +++ b/arch/arm/dts/vf610-zii-dev.dtsi @@ -42,6 +42,7 @@ n * copy, modify, merge, publish, distribute, sublicense, and/or * OTHER DEALINGS IN THE SOFTWARE. */ +#include "vf610.dtsi" #include "vf610-ddrmc.dtsi" / { diff --git a/arch/arm/dts/vf610-zii-spu3-rev-a.dts b/arch/arm/dts/vf610-zii-spu3-rev-a.dts deleted file mode 100644 index f362e7f0b9..0000000000 --- a/arch/arm/dts/vf610-zii-spu3-rev-a.dts +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - * - * Based on an original 'vf610-twr.dts' which is Copyright 2015, - * Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include <arm/vf610-zii-dev.dtsi> - -#include "vf610-zii-dev.dtsi" - -/ { - model = "ZII VF610 SPU3 Switch Management Board"; - compatible = "zii,vf610spu3-a", "zii,vf610dev", "fsl,vf610"; - - aliases { - /delete-property/ serial2; - }; - - gpio-leds { - debug { - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&dspi1 { - bus-num = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi1>; - status = "okay"; - - m25p128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - - partition@0 { - label = "m25p128-0"; - reg = <0x0 0x01000000>; - }; - }; -}; - -&esdhc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc0>; - bus-width = <8>; - status = "okay"; -}; - -&fec0 { - status = "disabled"; -}; - -&i2c0 { - /* Board Revision */ - gpio6: pca9505@22 { - compatible = "nxp,pca9554"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -/delete-node/ &i2c1; -/delete-node/ &i2c2; -/delete-node/ &uart2; - -&iomuxc { - pinctrl_dspi1: dspi1grp { - fsl,pins = < - VF610_PAD_PTD5__DSPI1_CS0 0x1182 - VF610_PAD_PTD4__DSPI1_CS1 0x1182 - VF610_PAD_PTC6__DSPI1_SIN 0x1181 - VF610_PAD_PTC7__DSPI1_SOUT 0x1182 - VF610_PAD_PTC8__DSPI1_SCK 0x1182 - >; - }; - - pinctrl_esdhc0: esdhc0grp { - fsl,pins = < - VF610_PAD_PTC0__ESDHC0_CLK 0x31ef - VF610_PAD_PTC1__ESDHC0_CMD 0x31ef - VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef - VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef - VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef - VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef - VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef - VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef - VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef - VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef - >; - }; - - pinctrl_leds_debug: pinctrl-leds-debug { - fsl,pins = < - VF610_PAD_PTD3__GPIO_82 0x31c2 - >; - }; -}; diff --git a/arch/arm/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/dts/vf610-zii-ssmb-spu3.dts new file mode 100644 index 0000000000..e030109ce2 --- /dev/null +++ b/arch/arm/dts/vf610-zii-ssmb-spu3.dts @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include <arm/vf610-zii-ssmb-spu3.dts> + +#include "vf610-zii-dev.dtsi" diff --git a/arch/arm/dts/vf610.dtsi b/arch/arm/dts/vf610.dtsi new file mode 100644 index 0000000000..3060031b8a --- /dev/null +++ b/arch/arm/dts/vf610.dtsi @@ -0,0 +1,12 @@ +/* + * Two aliases missing in upstream DT needed to make VFxxx's SD/MMC + * device naming scheme consistent with the rest of i.MX (which the + * following aliases from upstream. + */ + +/ { + aliases { + mmc0 = &esdhc0; + mmc1 = &esdhc1; + }; +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 1d6b4e1701..63a92bd5bd 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -423,6 +423,10 @@ config MACH_ZII_VF610_DEV select ARCH_VF610 select CLKDEV_LOOKUP +config MACH_ZII_IMX7D_RPU2 + bool "ZII i.MX7D RPU2" + select ARCH_IMX7 + config MACH_PHYTEC_PHYCORE_IMX7 bool "Phytec phyCORE i.MX7" select ARCH_IMX7 diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c index f1fc40479d..0c51767c42 100644 --- a/arch/arm/mach-imx/boot.c +++ b/arch/arm/mach-imx/boot.c @@ -167,10 +167,11 @@ void imx27_boot_save_loc(void) imx_boot_save_loc(imx27_get_boot_source); } -#define IMX51_SRC_SBMR 0x4 -#define IMX51_SBMR_BT_MEM_TYPE_SHIFT 7 -#define IMX51_SBMR_BT_MEM_CTL_SHIFT 0 -#define IMX51_SBMR_BMOD_SHIFT 14 +#define IMX51_SRC_SBMR 0x4 +#define IMX51_SBMR_BT_MEM_TYPE GENMASK(8, 7) +#define IMX51_SBMR_BT_MEM_CTL GENMASK(1, 0) +#define IMX51_SBMR_BT_SRC GENMASK(20, 19) +#define IMX51_SBMR_BMOD GENMASK(15, 14) void imx51_get_boot_source(enum bootsource *src, int *instance) { @@ -180,14 +181,15 @@ void imx51_get_boot_source(enum bootsource *src, int *instance) reg = readl(src_base + IMX51_SRC_SBMR); - switch ((reg >> IMX51_SBMR_BMOD_SHIFT) & 0x3) { + switch (FIELD_GET(IMX51_SBMR_BMOD, reg)) { case 0: case 2: /* internal boot */ - ctrl = (reg >> IMX51_SBMR_BT_MEM_CTL_SHIFT) & 0x3; - type = (reg >> IMX51_SBMR_BT_MEM_TYPE_SHIFT) & 0x3; + ctrl = FIELD_GET(IMX51_SBMR_BT_MEM_CTL, reg); + type = FIELD_GET(IMX51_SBMR_BT_MEM_TYPE, reg); *src = locations[ctrl][type]; + *instance = FIELD_GET(IMX51_SBMR_BT_SRC, reg); break; case 1: /* reserved */ diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index 875e942de0..074e3ac5a1 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -23,6 +23,7 @@ #include <init.h> #include <of.h> #include <linux/err.h> +#include <linux/bitfield.h> #include <asm/barebox-arm.h> #include <asm/memory.h> #include <mach/esdctl.h> @@ -38,6 +39,8 @@ #include <mach/imx53-regs.h> #include <mach/imx6-regs.h> #include <mach/vf610-ddrmc.h> +#include <mach/imx8mq-regs.h> +#include <mach/imx7-regs.h> struct imx_esdctl_data { unsigned long base0; @@ -319,6 +322,212 @@ static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) vf610_ddrmc_sdram_size(mmdcbase)); } +#define DDRC_ADDRMAP(n) (0x200 + 4 * (n)) +#define DDRC_ADDRMAP6_LPDDR4_6GB_12GB_24GB GENMASK(30, 29) +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB BIT(31) +#define DDRC_ADDRMAP0_CS_BIT0 GENMASK(4, 0) + +#define DDRC_MSTR 0x0000 +#define DDRC_MSTR_LPDDR4 BIT(5) +#define DDRC_MSTR_DATA_BUS_WIDTH GENMASK(13, 12) +#define DDRC_MSTR_ACTIVE_RANKS GENMASK(27, 24) + +#define DDRC_ADDRMAP0_CS_BIT1 GENMASK(12, 8) + +#define DDRC_ADDRMAP1_BANK_B2 GENMASK(20, 16) + +#define DDRC_ADDRMAP2_COL_B5 GENMASK(27, 24) +#define DDRC_ADDRMAP2_COL_B4 GENMASK(19, 16) + +#define DDRC_ADDRMAP3_COL_B9 GENMASK(27, 24) +#define DDRC_ADDRMAP3_COL_B8 GENMASK(19, 16) +#define DDRC_ADDRMAP3_COL_B7 GENMASK(11, 8) +#define DDRC_ADDRMAP3_COL_B6 GENMASK( 3, 0) + +#define DDRC_ADDRMAP4_COL_B10 GENMASK(3, 0) +#define DDRC_ADDRMAP4_COL_B11 GENMASK(11, 8) + +#define DDRC_ADDRMAP5_ROW_B11 GENMASK(27, 24) + +#define DDRC_ADDRMAP6_ROW_B15 GENMASK(27, 24) +#define DDRC_ADDRMAP6_ROW_B14 GENMASK(19, 16) +#define DDRC_ADDRMAP6_ROW_B13 GENMASK(11, 8) +#define DDRC_ADDRMAP6_ROW_B12 GENMASK( 3, 0) + +#define DDRC_ADDRMAP7_ROW_B17 GENMASK(11, 8) +#define DDRC_ADDRMAP7_ROW_B16 GENMASK( 3, 0) + +static unsigned int +imx_ddrc_count_bits(unsigned int bits, const u8 config[], + unsigned int config_num) +{ + unsigned int i; + for (i = 0; i < config_num && config[i] == 0b1111; i++) + bits--; + + return bits; +} + +static resource_size_t +imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[], + u8 col_max, const u8 col_b[], unsigned int col_b_num, + u8 row_max, const u8 row_b[], unsigned int row_b_num, + bool reduced_adress_space) +{ + const u32 mstr = readl(ddrc + DDRC_MSTR); + unsigned int banks, ranks, columns, rows, active_ranks, width; + resource_size_t size; + + banks = 2; + ranks = 0; + + switch (FIELD_GET(DDRC_MSTR_ACTIVE_RANKS, mstr)) { + case 0b0001: + active_ranks = 1; + break; + case 0b0011: + active_ranks = 2; + break; + case 0b1111: + active_ranks = 4; + break; + default: + BUG(); + } + + switch (FIELD_GET(DDRC_MSTR_DATA_BUS_WIDTH, mstr)) { + case 0b00: /* Full DQ bus */ + width = 4; + break; + case 0b01: /* Half DQ bus */ + width = 2; + break; + case 0b10: /* Quarter DQ bus */ + width = 1; + break; + default: + BUG(); + } + + if (active_ranks == 4 && + FIELD_GET(DDRC_ADDRMAP0_CS_BIT1, addrmap[0]) != 0b11111) + ranks++; + + if (active_ranks > 1 && + FIELD_GET(DDRC_ADDRMAP0_CS_BIT0, addrmap[0]) != 0b11111) + ranks++; + + if (FIELD_GET(DDRC_ADDRMAP1_BANK_B2, addrmap[1]) != 0b11111) + banks++; + + columns = imx_ddrc_count_bits(col_max, col_b, col_b_num); + rows = imx_ddrc_count_bits(row_max, row_b, row_b_num); + + size = memory_sdram_size(columns, rows, 1 << banks, width) << ranks; + + return reduced_adress_space ? size * 3 / 4 : size; +} + +static resource_size_t imx8mq_ddrc_sdram_size(void __iomem *ddrc) +{ + const u32 addrmap[] = { + readl(ddrc + DDRC_ADDRMAP(0)), + readl(ddrc + DDRC_ADDRMAP(1)), + readl(ddrc + DDRC_ADDRMAP(2)), + readl(ddrc + DDRC_ADDRMAP(3)), + readl(ddrc + DDRC_ADDRMAP(4)), + readl(ddrc + DDRC_ADDRMAP(5)), + readl(ddrc + DDRC_ADDRMAP(6)), + readl(ddrc + DDRC_ADDRMAP(7)) + }; + const u8 col_b[] = { + /* + * FIXME: DDR register spreadsheet mentiones that B10 + * and B11 are 5-bit fields instead of 4. Needs to be + * clarified. + */ + FIELD_GET(DDRC_ADDRMAP4_COL_B11, addrmap[4]), + FIELD_GET(DDRC_ADDRMAP4_COL_B10, addrmap[4]), + FIELD_GET(DDRC_ADDRMAP3_COL_B9, addrmap[3]), + FIELD_GET(DDRC_ADDRMAP3_COL_B8, addrmap[3]), + FIELD_GET(DDRC_ADDRMAP3_COL_B7, addrmap[3]), + FIELD_GET(DDRC_ADDRMAP3_COL_B6, addrmap[3]), + FIELD_GET(DDRC_ADDRMAP2_COL_B5, addrmap[2]), + FIELD_GET(DDRC_ADDRMAP2_COL_B4, addrmap[2]), + }; + const u8 row_b[] = { + /* + * FIXME: RM mentions the following fields as being + * present, but looking at the code generated by DDR + * tool it doesn't look like those registers are + * really implemented/used. + * + * FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]), + * FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]), + */ + FIELD_GET(DDRC_ADDRMAP6_ROW_B15, addrmap[6]), + FIELD_GET(DDRC_ADDRMAP6_ROW_B14, addrmap[6]), + FIELD_GET(DDRC_ADDRMAP6_ROW_B13, addrmap[6]), + FIELD_GET(DDRC_ADDRMAP6_ROW_B12, addrmap[6]), + FIELD_GET(DDRC_ADDRMAP5_ROW_B11, addrmap[5]), + }; + const bool reduced_adress_space = + FIELD_GET(DDRC_ADDRMAP6_LPDDR4_6GB_12GB_24GB, addrmap[6]); + + return imx_ddrc_sdram_size(ddrc, addrmap, + 12, ARRAY_AND_SIZE(col_b), + 16, ARRAY_AND_SIZE(row_b), + reduced_adress_space); +} + +static void imx8mq_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +{ + arm_add_mem_device("ram0", data->base0, + imx8mq_ddrc_sdram_size(mmdcbase)); +} + +static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc) +{ + const u32 addrmap[] = { + readl(ddrc + DDRC_ADDRMAP(0)), + readl(ddrc + DDRC_ADDRMAP(1)), + readl(ddrc + DDRC_ADDRMAP(2)), + readl(ddrc + DDRC_ADDRMAP(3)), + readl(ddrc + DDRC_ADDRMAP(4)), + readl(ddrc + DDRC_ADDRMAP(5)), + readl(ddrc + DDRC_ADDRMAP(6)) + }; + const u8 col_b[] = { + FIELD_GET(DDRC_ADDRMAP4_COL_B10, addrmap[4]), + FIELD_GET(DDRC_ADDRMAP3_COL_B9, addrmap[3]), + FIELD_GET(DDRC_ADDRMAP3_COL_B8, addrmap[3]), + FIELD_GET(DDRC_ADDRMAP3_COL_B7, addrmap[3]), + FIELD_GET(DDRC_ADDRMAP3_COL_B6, addrmap[3]), + FIELD_GET(DDRC_ADDRMAP2_COL_B5, addrmap[2]), + FIELD_GET(DDRC_ADDRMAP2_COL_B4, addrmap[2]), + }; + const u8 row_b[] = { + FIELD_GET(DDRC_ADDRMAP6_ROW_B15, addrmap[6]), + FIELD_GET(DDRC_ADDRMAP6_ROW_B14, addrmap[6]), + FIELD_GET(DDRC_ADDRMAP6_ROW_B13, addrmap[6]), + FIELD_GET(DDRC_ADDRMAP6_ROW_B12, addrmap[6]), + FIELD_GET(DDRC_ADDRMAP5_ROW_B11, addrmap[5]), + }; + const bool reduced_adress_space = + FIELD_GET(DDRC_ADDRMAP6_LPDDR3_6GB_12GB, addrmap[6]); + + return imx_ddrc_sdram_size(ddrc, addrmap, + 11, ARRAY_AND_SIZE(col_b), + 15, ARRAY_AND_SIZE(row_b), + reduced_adress_space); +} + +static void imx7d_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +{ + arm_add_mem_device("ram0", data->base0, + imx7d_ddrc_sdram_size(mmdcbase)); +} + static int imx_esdctl_probe(struct device_d *dev) { struct resource *iores; @@ -405,6 +614,16 @@ static __maybe_unused struct imx_esdctl_data vf610_data = { .add_mem = vf610_ddrmc_add_mem, }; +static __maybe_unused struct imx_esdctl_data imx8mq_data = { + .base0 = MX8MQ_DDR_CSD1_BASE_ADDR, + .add_mem = imx8mq_ddrc_add_mem, +}; + +static __maybe_unused struct imx_esdctl_data imx7d_data = { + .base0 = MX7_DDR_BASE_ADDR, + .add_mem = imx7d_ddrc_add_mem, +}; + static struct platform_device_id imx_esdctl_ids[] = { #ifdef CONFIG_ARCH_IMX1 { @@ -470,6 +689,12 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = { .compatible = "fsl,vf610-ddrmc", .data = &vf610_data }, { + .compatible = "fsl,imx8mq-ddrc", + .data = &imx8mq_data + }, { + .compatible = "fsl,imx7d-ddrc", + .data = &imx7d_data + }, { /* sentinel */ } }; @@ -643,3 +868,30 @@ void __noreturn vf610_barebox_entry(void *boarddata) vf610_ddrmc_sdram_size(IOMEM(VF610_DDR_BASE_ADDR)), boarddata); } + +void __noreturn imx8mq_barebox_entry(void *boarddata) +{ + resource_size_t size; + + size = imx8mq_ddrc_sdram_size(IOMEM(MX8MQ_DDRC_CTL_BASE_ADDR)); + /* + * We artificially limit detected memory size to force malloc + * pool placement to be within 4GiB address space, so as to + * make it accessible to 32-bit limited DMA. + * + * This limitation affects only early boot code and malloc + * pool placement. The rest of the system should be able to + * detect and utilize full amount of memory. + */ + size = min_t(resource_size_t, SZ_4G - MX8MQ_DDR_CSD1_BASE_ADDR, size); + barebox_arm_entry(MX8MQ_DDR_CSD1_BASE_ADDR, size, boarddata); +} + +void __noreturn imx7d_barebox_entry(void *boarddata) +{ + barebox_arm_entry(MX7_DDR_BASE_ADDR, + imx7d_ddrc_sdram_size(IOMEM(MX7_DDRC_BASE_ADDR)), + boarddata); +} + + diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c index 504e359bc3..5f85b13dca 100644 --- a/arch/arm/mach-imx/imx-bbu-internal.c +++ b/arch/arm/mach-imx/imx-bbu-internal.c @@ -401,21 +401,32 @@ static int imx_bbu_update(struct bbu_handler *handler, struct bbu_data *data) return imx_handler->write_device(imx_handler, data); } -static int imx_bbu_internal_v2_mmcboot_update(struct bbu_handler *handler, - struct bbu_data *data) +static int imx_bbu_internal_mmcboot_update(struct bbu_handler *handler, + struct bbu_data *data) { - struct imx_internal_bbu_handler *imx_handler = - container_of(handler, struct imx_internal_bbu_handler, handler); + struct bbu_data _data = *data; int ret; char *bootpartvar; const char *bootpart; char *devicefile; + const char *devname = devpath_to_name(data->devicefile); + + ret = device_detect_by_name(devname); + if (ret) { + pr_err("Couldn't detect device '%s'\n", devname); + return ret; + } - ret = asprintf(&bootpartvar, "%s.boot", data->devicefile); + ret = asprintf(&bootpartvar, "%s.boot", devname); if (ret < 0) return ret; bootpart = getenv(bootpartvar); + if (!bootpart) { + pr_err("Couldn't read the value of '%s'\n", bootpartvar); + ret = -ENOENT; + goto free_bootpartvar; + } if (!strcmp(bootpart, "boot0")) { bootpart = "boot1"; @@ -423,20 +434,18 @@ static int imx_bbu_internal_v2_mmcboot_update(struct bbu_handler *handler, bootpart = "boot0"; } - ret = asprintf(&devicefile, "/dev/%s.%s", data->devicefile, bootpart); + ret = asprintf(&devicefile, "/dev/%s.%s", devname, bootpart); if (ret < 0) goto free_bootpartvar; - ret = imx_bbu_check_prereq(imx_handler, devicefile, data, - filetype_imx_image_v2); + _data.devicefile = devicefile; + + ret = imx_bbu_update(handler, &_data); if (ret) goto free_devicefile; - ret = imx_bbu_write_device(imx_handler, devicefile, data, data->image, data->len); - - if (!ret) - /* on success switch boot source */ - ret = setenv(bootpartvar, bootpart); + /* on success switch boot source */ + ret = setenv(bootpartvar, bootpart); free_devicefile: free(devicefile); @@ -586,20 +595,40 @@ int imx8mq_bbu_internal_mmc_register_handler(const char *name, * Note that no further partitioning of the boot partition is supported up to * now. */ -int imx6_bbu_internal_mmcboot_register_handler(const char *name, - const char *devicefile, - unsigned long flags) +static int imx_bbu_internal_mmcboot_register_handler(const char *name, + const char *devicefile, + unsigned long flags) { struct imx_internal_bbu_handler *imx_handler; imx_handler = __init_handler(name, devicefile, flags); imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc(); - imx_handler->handler.handler = imx_bbu_internal_v2_mmcboot_update; + imx_handler->handler.handler = imx_bbu_internal_mmcboot_update; return __register_handler(imx_handler); } +int imx6_bbu_internal_mmcboot_register_handler(const char *name, + const char *devicefile, + unsigned long flags) + __alias(imx_bbu_internal_mmcboot_register_handler); + +int imx51_bbu_internal_mmcboot_register_handler(const char *name, + const char *devicefile, + unsigned long flags) + __alias(imx_bbu_internal_mmcboot_register_handler); + +int vf610_bbu_internal_mmcboot_register_handler(const char *name, + const char *devicefile, + unsigned long flags) + __alias(imx_bbu_internal_mmcboot_register_handler); + +int imx7_bbu_internal_mmcboot_register_handler(const char *name, + const char *devicefile, + unsigned long flags) + __alias(imx_bbu_internal_mmcboot_register_handler); + /* * Register an i.MX53 internal boot update handler for i2c/spi * EEPROMs / flashes. Nearly the same as MMC/SD, but we do not need to @@ -620,6 +649,12 @@ int vf610_bbu_internal_spi_i2c_register_handler(const char *name, unsigned long flags) __alias(imx6_bbu_internal_spi_i2c_register_handler); + +int imx7_bbu_internal_spi_i2c_register_handler(const char *name, + const char *devicefile, + unsigned long flags) + __alias(imx6_bbu_internal_spi_i2c_register_handler); + int imx_bbu_external_nor_register_handler(const char *name, const char *devicefile, unsigned long flags) diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h index b64c8d1180..c8223c8405 100644 --- a/arch/arm/mach-imx/include/mach/bbu.h +++ b/arch/arm/mach-imx/include/mach/bbu.h @@ -53,6 +53,15 @@ int imx6_bbu_internal_mmc_register_handler(const char *name, const char *devicef int imx6_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile, unsigned long flags); +int imx51_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile, + unsigned long flags); + +int vf610_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile, + unsigned long flags); + +int imx7_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile, + unsigned long flags); + int imx6_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, unsigned long flags); @@ -62,6 +71,9 @@ int vf610_bbu_internal_mmc_register_handler(const char *name, const char *device int vf610_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, unsigned long flags); +int imx7_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, + unsigned long flags); + int imx8mq_bbu_internal_mmc_register_handler(const char *name, const char *devicefile, unsigned long flags); @@ -113,6 +125,28 @@ static inline int imx6_bbu_internal_mmcboot_register_handler(const char *name, return -ENOSYS; } +static inline int imx51_bbu_internal_mmcboot_register_handler(const char *name, + const char *devicefile, + unsigned long flags) +{ + return -ENOSYS; +} + + +static inline int vf610_bbu_internal_mmcboot_register_handler(const char *name, + const char *devicefile, + unsigned long flags) +{ + return -ENOSYS; +} + +static inline int imx7_bbu_internal_mmcboot_register_handler(const char *name, + const char *devicefile, + unsigned long flags) +{ + return -ENOSYS; +} + static inline int imx6_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile, unsigned long flags) { @@ -144,6 +178,13 @@ vf610_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile, return -ENOSYS; } +static inline int +imx7_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile, + unsigned long flags) +{ + return -ENOSYS; +} + #endif #if defined(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h index 117e2bbad5..bc6c733953 100644 --- a/arch/arm/mach-imx/include/mach/esdctl.h +++ b/arch/arm/mach-imx/include/mach/esdctl.h @@ -139,6 +139,8 @@ void __noreturn imx53_barebox_entry(void *boarddata); void __noreturn imx6q_barebox_entry(void *boarddata); void __noreturn imx6ul_barebox_entry(void *boarddata); void __noreturn vf610_barebox_entry(void *boarddata); +void __noreturn imx8mq_barebox_entry(void *boarddata); +void __noreturn imx7d_barebox_entry(void *boarddata); void imx_esdctl_disable(void); #endif diff --git a/arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg new file mode 100644 index 0000000000..e98f055eea --- /dev/null +++ b/arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2016 NXP Semiconductors + * + * SPDX-License-Identifier: GPL-2.0 + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + * + * Taken from upstream U-Boot git://git.denx.de/u-boot.git, commit + * 1a8150d4b16fbafa6f1d207ddb85eda7dc399e2d + */ + +#include <mach/imx7-ddr-regs.h> + +wm 32 0x30340004 0x4F400005 + +wm 32 0x30391000 0x00000002 + +wm 32 MX7_DDRC_MSTR 0x01040001 +wm 32 MX7_DDRC_DFIUPD0 0x80400003 +wm 32 MX7_DDRC_DFIUPD1 0x00100020 +wm 32 MX7_DDRC_DFIUPD2 0x80100004 +wm 32 MX7_DDRC_RFSHTMG 0x00400046 +wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001 +wm 32 MX7_DDRC_INIT0 0x00020083 +wm 32 MX7_DDRC_INIT1 0x00690000 +wm 32 MX7_DDRC_INIT3 0x09300004 +wm 32 MX7_DDRC_INIT4 0x04080000 +wm 32 MX7_DDRC_INIT5 0x00100004 +wm 32 MX7_DDRC_RANKCTL 0x0000033f +wm 32 MX7_DDRC_DRAMTMG0 0x09081109 +wm 32 MX7_DDRC_DRAMTMG1 0x0007020d +wm 32 MX7_DDRC_DRAMTMG2 0x03040407 +wm 32 MX7_DDRC_DRAMTMG3 0x00002006 +wm 32 MX7_DDRC_DRAMTMG4 0x04020205 +wm 32 MX7_DDRC_DRAMTMG5 0x03030202 +wm 32 MX7_DDRC_DRAMTMG8 0x00000803 +wm 32 MX7_DDRC_ZQCTL0 0x00800020 +wm 32 MX7_DDRC_ZQCTL1 0x02000100 +wm 32 MX7_DDRC_DFITMG0 0x02098204 +wm 32 MX7_DDRC_DFITMG1 0x00030303 +wm 32 MX7_DDRC_ADDRMAP0 0x00000016 +wm 32 MX7_DDRC_ADDRMAP1 0x00171717 +wm 32 MX7_DDRC_ADDRMAP5 0x04040404 +wm 32 MX7_DDRC_ADDRMAP6 0x0f040404 +wm 32 MX7_DDRC_ODTCFG 0x06000604 +wm 32 MX7_DDRC_ODTMAP 0x00000001 + +wm 32 0x30391000 0x00000000 + +wm 32 MX7_DDR_PHY_PHY_CON0 0x17420f40 +wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100 +wm 32 MX7_DDR_PHY_PHY_CON4 0x00060807 +wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e +wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e +wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x08080808 +wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x08080808 +wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000010 +wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000010 + +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306 + +check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1 + +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 + +wm 32 0x30384130 0x00000000 +wm 32 0x30340020 0x00000178 +wm 32 0x30384130 0x00000002 + +wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f + +check 32 until_any_bit_set MX7_DDRC_STAT 0x1 diff --git a/arch/arm/mach-imx/include/mach/imx7-regs.h b/arch/arm/mach-imx/include/mach/imx7-regs.h index 8625d0b619..21e2830b97 100644 --- a/arch/arm/mach-imx/include/mach/imx7-regs.h +++ b/arch/arm/mach-imx/include/mach/imx7-regs.h @@ -116,4 +116,6 @@ #define MX7_ENET1_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x3E0000) #define MX7_ENET2_BASE_ADDR (MX7_AIPS3_BASE_ADDR + 0x3F0000) +#define MX7_DDR_BASE_ADDR 0x80000000 + #endif /* __MACH_IMX7_REGS_H */ diff --git a/common/imx-bbu-nand-fcb.c b/common/imx-bbu-nand-fcb.c index 2c8ca97926..8842ba6c58 100644 --- a/common/imx-bbu-nand-fcb.c +++ b/common/imx-bbu-nand-fcb.c @@ -318,6 +318,17 @@ struct fcb_block *read_fcb_hamming_13_8(void *rawpage) fcb = rawpage + 12; ecc = rawpage + 512 + 12; + /* + * The ROM does the check for the correct fingerprint and version before + * correcting bitflips. This means we cannot allow bitflips in the + * fingerprint and version. We bail out with an error if it's not correct. + * This is currently done in the i.MX6qdl path. It needs to be checked if + * the same happens in the BCH encoded variants (i.MX6ul(l)) aswell. + */ + if (((struct fcb_block *)fcb)->FingerPrint != 0x20424346 || + ((struct fcb_block *)fcb)->Version != 0x01000000) + return ERR_PTR(-EINVAL); + for (i = 0; i < 512; i++) { parity = ecc[i]; np = calculate_parity_13_8(fcb[i]); @@ -459,7 +470,7 @@ static int read_fcb(struct mtd_info *mtd, int num, struct fcb_block **retfcb) fcb = read_fcb_hamming_13_8(rawpage); if (IS_ERR(fcb)) { - pr_err("Cannot read fcb\n"); + pr_err("Cannot read fcb on block %d\n", num); ret = PTR_ERR(fcb); goto err; } @@ -555,6 +566,40 @@ static int imx_bbu_firmware_start_block(struct mtd_info *mtd, int num) return 4 + num * imx_bbu_firmware_max_blocks(mtd); } +/** + * imx_bbu_firmware_fcb_start_page - get start page for a firmware slot + * @mtd: The mtd device + * @num: The slot number (0 or 1) + * + * This returns the start page for a firmware slot, to be written into the + * Firmwaren_startingPage field in the FCB. + */ +static int imx_bbu_firmware_fcb_start_page(struct mtd_info *mtd, int num) +{ + int block, blocksleft; + int pages_per_block = mtd->erasesize / mtd->writesize; + + block = imx_bbu_firmware_start_block(mtd, num); + + blocksleft = imx_bbu_firmware_max_blocks(mtd); + + /* + * The ROM only checks for a bad block when advancing the read position, + * but not if the initial block is good, hence we cannot directly point + * to the first firmware block, but must instead point to the first *good* + * firmware block. + */ + while (mtd_peb_is_bad(mtd, block)) { + block++; + blocksleft--; + if (!blocksleft) + break; + } + + return block * pages_per_block; +} + + static int imx_bbu_write_firmware(struct mtd_info *mtd, unsigned num, void *buf, size_t len) { @@ -1073,9 +1118,8 @@ static void read_firmware_all(struct mtd_info *mtd, struct fcb_block *fcb, void int *used_refresh, int *unused_refresh, int *used) { void *primary = NULL, *secondary = NULL; - int pages_per_block = mtd->erasesize / mtd->writesize; - int fw0 = imx_bbu_firmware_start_block(mtd, 0) * pages_per_block; - int fw1 = imx_bbu_firmware_start_block(mtd, 1) * pages_per_block; + int fw0 = imx_bbu_firmware_fcb_start_page(mtd, 0); + int fw1 = imx_bbu_firmware_fcb_start_page(mtd, 1); int first, ret, primary_refresh = 0, secondary_refresh = 0; *used_refresh = 0; @@ -1157,7 +1201,6 @@ static int imx_bbu_nand_update(struct bbu_handler *handler, struct bbu_data *dat unsigned fw_size, partition_size; enum filetype filetype; unsigned num_blocks_fw; - int pages_per_block; int used = 0; int fw_orig_len; int used_refresh = 0, unused_refresh = 0; @@ -1180,7 +1223,6 @@ static int imx_bbu_nand_update(struct bbu_handler *handler, struct bbu_data *dat mtd = bcb_cdev->mtd; partition_size = mtd->size; - pages_per_block = mtd->erasesize / mtd->writesize; for (i = 0; i < 4; i++) { read_fcb(mtd, i, &fcb); @@ -1263,8 +1305,8 @@ static int imx_bbu_nand_update(struct bbu_handler *handler, struct bbu_data *dat free(fcb); fcb = xzalloc(sizeof(*fcb)); - fcb->Firmware1_startingPage = imx_bbu_firmware_start_block(mtd, !used) * pages_per_block; - fcb->Firmware2_startingPage = imx_bbu_firmware_start_block(mtd, used) * pages_per_block; + fcb->Firmware1_startingPage = imx_bbu_firmware_fcb_start_page(mtd, !used); + fcb->Firmware2_startingPage = imx_bbu_firmware_fcb_start_page(mtd, used); fcb->PagesInFirmware1 = fw_size / mtd->writesize; fcb->PagesInFirmware2 = fcb->PagesInFirmware1; diff --git a/drivers/aiodev/Kconfig b/drivers/aiodev/Kconfig index 3eabd3b3ff..7f1d0fd4a9 100644 --- a/drivers/aiodev/Kconfig +++ b/drivers/aiodev/Kconfig @@ -16,6 +16,13 @@ config IMX_THERMAL Support for Temperature Monitor (TEMPMON) found on Freescale i.MX SoCs. +config QORIQ_THERMAL + tristate "QorIQ Thermal Monitoring Unit" + depends on ARCH_IMX8MQ + help + Support for Thermal Monitoring Unit (TMU) found on QorIQ and + i.MX8MQ platforms. + config LM75 tristate "LM75 driver" depends on I2C diff --git a/drivers/aiodev/Makefile b/drivers/aiodev/Makefile index 1dcf6cdc4b..d5318deeb0 100644 --- a/drivers/aiodev/Makefile +++ b/drivers/aiodev/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_AIODEV) += core.o obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o obj-$(CONFIG_LM75) += lm75.o obj-$(CONFIG_MC13XXX_ADC) += mc13xxx_adc.o +obj-$(CONFIG_QORIQ_THERMAL) += qoriq_thermal.o diff --git a/drivers/aiodev/qoriq_thermal.c b/drivers/aiodev/qoriq_thermal.c new file mode 100644 index 0000000000..d29da02a68 --- /dev/null +++ b/drivers/aiodev/qoriq_thermal.c @@ -0,0 +1,264 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include <common.h> +#include <init.h> +#include <malloc.h> +#include <clock.h> +#include <driver.h> +#include <xfuncs.h> +#include <errno.h> +#include <io.h> +#include <aiodev.h> +#include <of_address.h> +#include <linux/clk.h> + +#define SITES_MAX 16 + +#define TMU_TEMP_PASSIVE_COOL_DELTA 10000 + +/* + * QorIQ TMU Registers + */ +struct qoriq_tmu_site_regs { + u32 tritsr; /* Immediate Temperature Site Register */ + u32 tratsr; /* Average Temperature Site Register */ + u8 res0[0x8]; +}; + +struct qoriq_tmu_regs { + u32 tmr; /* Mode Register */ +#define TMR_DISABLE 0x0 +#define TMR_ME 0x80000000 +#define TMR_ALPF 0x0c000000 + u32 tsr; /* Status Register */ + u32 tmtmir; /* Temperature measurement interval Register */ +#define TMTMIR_DEFAULT 0x0000000f + u8 res0[0x14]; + u32 tier; /* Interrupt Enable Register */ +#define TIER_DISABLE 0x0 + u32 tidr; /* Interrupt Detect Register */ + u32 tiscr; /* Interrupt Site Capture Register */ + u32 ticscr; /* Interrupt Critical Site Capture Register */ + u8 res1[0x10]; + u32 tmhtcrh; /* High Temperature Capture Register */ + u32 tmhtcrl; /* Low Temperature Capture Register */ + u8 res2[0x8]; + u32 tmhtitr; /* High Temperature Immediate Threshold */ + u32 tmhtatr; /* High Temperature Average Threshold */ + u32 tmhtactr; /* High Temperature Average Crit Threshold */ + u8 res3[0x24]; + u32 ttcfgr; /* Temperature Configuration Register */ + u32 tscfgr; /* Sensor Configuration Register */ + u8 res4[0x78]; + struct qoriq_tmu_site_regs site[SITES_MAX]; + u8 res5[0x9f8]; + u32 ipbrr0; /* IP Block Revision Register 0 */ + u32 ipbrr1; /* IP Block Revision Register 1 */ + u8 res6[0x310]; + u32 ttr0cr; /* Temperature Range 0 Control Register */ + u32 ttr1cr; /* Temperature Range 1 Control Register */ + u32 ttr2cr; /* Temperature Range 2 Control Register */ + u32 ttr3cr; /* Temperature Range 3 Control Register */ +}; + +/* + * Thermal zone data + */ +struct qoriq_tmu_data { + struct device_d *dev; + struct clk *clk; + struct qoriq_tmu_regs __iomem *regs; + int sensor_id; + bool little_endian; + int temp_passive; + int temp_critical; + + struct aiodevice aiodev; + struct aiochannel aiochan; +}; + +static inline struct qoriq_tmu_data *to_qoriq_tmu_data(struct aiochannel *chan) +{ + return container_of(chan, struct qoriq_tmu_data, aiochan); +} + +static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr) +{ + if (p->little_endian) + iowrite32(val, addr); + else + iowrite32be(val, addr); +} + +static u32 tmu_read(struct qoriq_tmu_data *p, void __iomem *addr) +{ + if (p->little_endian) + return ioread32(addr); + else + return ioread32be(addr); +} + +static int tmu_get_temp(struct aiochannel *chan, int *temp) +{ + u32 val; + struct qoriq_tmu_data *data = to_qoriq_tmu_data(chan); + + val = tmu_read(data, &data->regs->site[data->sensor_id].tritsr); + + *temp = (val & 0xff) * 1000; + + return 0; +} + +static int qoriq_tmu_get_sensor_id(void) +{ + int ret, id; + struct of_phandle_args sensor_specs; + struct device_node *np, *sensor_np; + + np = of_find_node_by_name(NULL, "thermal-zones"); + if (!np) + return -ENODEV; + + sensor_np = of_get_next_child(np, NULL); + ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors", + "#thermal-sensor-cells", + 0, &sensor_specs); + if (ret) + return ret; + + if (sensor_specs.args_count >= 1) { + id = sensor_specs.args[0]; + WARN(sensor_specs.args_count > 1, + "%s: too many cells in sensor specifier %d\n", + sensor_specs.np->name, sensor_specs.args_count); + } else { + id = 0; + } + + return id; +} + +static int qoriq_tmu_calibration(struct qoriq_tmu_data *data) +{ + int i, val, len; + u32 range[4]; + const u32 *calibration; + struct device_node *np = data->dev->device_node; + + if (of_property_read_u32_array(np, "fsl,tmu-range", range, 4)) { + dev_err(data->dev, "missing calibration range.\n"); + return -ENODEV; + } + + /* Init temperature range registers */ + tmu_write(data, range[0], &data->regs->ttr0cr); + tmu_write(data, range[1], &data->regs->ttr1cr); + tmu_write(data, range[2], &data->regs->ttr2cr); + tmu_write(data, range[3], &data->regs->ttr3cr); + + calibration = of_get_property(np, "fsl,tmu-calibration", &len); + if (calibration == NULL || len % 8) { + dev_err(data->dev, "invalid calibration data.\n"); + return -ENODEV; + } + + for (i = 0; i < len; i += 8, calibration += 2) { + val = of_read_number(calibration, 1); + tmu_write(data, val, &data->regs->ttcfgr); + val = of_read_number(calibration + 1, 1); + tmu_write(data, val, &data->regs->tscfgr); + } + + return 0; +} + +static void qoriq_tmu_init_device(struct qoriq_tmu_data *data) +{ + /* Disable interrupt, using polling instead */ + tmu_write(data, TIER_DISABLE, &data->regs->tier); + + /* Set update_interval */ + tmu_write(data, TMTMIR_DEFAULT, &data->regs->tmtmir); + + /* Disable monitoring */ + tmu_write(data, TMR_DISABLE, &data->regs->tmr); +} + +static int qoriq_tmu_probe(struct device_d *dev) +{ + struct device_node *np = dev->device_node; + struct qoriq_tmu_data *data; + u32 site; + int ret; + + data = xzalloc(sizeof(*data)); + + data->dev = dev; + data->little_endian = of_property_read_bool(np, "little-endian"); + + data->sensor_id = qoriq_tmu_get_sensor_id(); + if (data->sensor_id < 0) { + dev_err(dev, "Failed to get sensor id\n"); + return -ENODEV; + } + + data->regs = dev_request_mem_region(dev, 0); + if (IS_ERR(data->regs)) { + dev_err(dev, "Failed to get memory region\n"); + return PTR_ERR(data->regs); + } + + qoriq_tmu_init_device(data); /* TMU initialization */ + + ret = qoriq_tmu_calibration(data); /* TMU calibration */ + if (ret < 0) { + dev_err(dev, "Failed to calibrate\n"); + return ret; + } + + data->aiodev.num_channels = 1; + data->aiodev.hwdev = dev; + data->aiodev.channels = xmalloc(data->aiodev.num_channels * + sizeof(data->aiodev.channels[0])); + data->aiodev.channels[0] = &data->aiochan; + data->aiochan.unit = "mC"; + data->aiodev.read = tmu_get_temp; + + ret = aiodevice_register(&data->aiodev); + if (ret < 0) { + dev_err(dev, "Failed to register aiodev\n"); + return ret; + } + + site = 0x1 << (15 - data->sensor_id); + tmu_write(data, site | TMR_ME | TMR_ALPF, &data->regs->tmr); + + return 0; +} + +static const struct of_device_id qoriq_tmu_match[] = { + { .compatible = "fsl,qoriq-tmu", }, + { .compatible = "fsl,imx8mq-tmu",}, + {}, +}; + +static struct driver_d imx_thermal_driver = { + .name = "qoriq_thermal", + .probe = qoriq_tmu_probe, + .of_compatible = DRV_OF_COMPAT(qoriq_tmu_match), +}; +device_platform_driver(imx_thermal_driver); diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 92d49d44e9..0431f61f09 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -185,6 +185,15 @@ static const char *imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_ static struct clk_onecell_data clk_data; +static int const clks_init_on[] = { + IMX8MQ_CLK_DRAM_CORE, IMX8MQ_CLK_AHB_CG, + IMX8MQ_CLK_NOC_DIV, IMX8MQ_CLK_NOC_APB_DIV, + IMX8MQ_CLK_NAND_USDHC_BUS_SRC, + IMX8MQ_CLK_MAIN_AXI_SRC, IMX8MQ_CLK_A53_CG, + IMX8MQ_CLK_AUDIO_AHB_DIV, IMX8MQ_CLK_TMU_ROOT, + IMX8MQ_CLK_DRAM_APB_SRC, +}; + static void __init imx8mq_clocks_init(struct device_node *ccm_node) { struct device_node *np; @@ -563,6 +572,7 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node) clks[IMX8MQ_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog_div", base + 0x4530, 0); clks[IMX8MQ_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog_div", base + 0x4540, 0); clks[IMX8MQ_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog_div", base + 0x4550, 0); + clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0); clks[IMX8MQ_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc_25m", 1, 8); clks[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt_div", 1, 4); @@ -572,6 +582,9 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node) pr_err("i.MX8mq clk %u register failed with %ld\n", i, PTR_ERR(clks[i])); + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) + clk_enable(clks[clks_init_on[i]]); + clk_data.clks = clks; clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); diff --git a/images/Makefile.imx b/images/Makefile.imx index f0014ac9e9..341ce8506d 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -532,6 +532,11 @@ CFG_start_imx7d_sabresd.pblx.imximg = $(board)/freescale-mx7-sabresd/flash-heade FILE_barebox-freescale-mx7-sabresd.img = start_imx7d_sabresd.pblx.imximg image-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += barebox-freescale-mx7-sabresd.img +pblx-$(CONFIG_MACH_ZII_IMX7D_RPU2) += start_zii_imx7d_rpu2 +CFG_start_zii_imx7d_rpu2.pblx.imximg = $(board)/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg +FILE_barebox-zii-imx7d-rpu2.img = start_zii_imx7d_rpu2.pblx.imximg +image-$(CONFIG_MACH_ZII_IMX7D_RPU2) += barebox-zii-imx7d-rpu2.img + # ----------------------- i.MX8mq based boards -------------------------- pblx-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += start_nxp_imx8mq_evk CFG_start_nxp_imx8mq_evk.imx-sram-img = $(board)/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg |