summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--dts/Bindings/.gitignore3
-rw-r--r--dts/Bindings/Makefile32
-rw-r--r--dts/Bindings/arm/altera/socfpga-clk-manager.yaml2
-rw-r--r--dts/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml2
-rw-r--r--dts/Bindings/arm/arm,integrator.yaml86
-rw-r--r--dts/Bindings/arm/arm,realview.yaml123
-rw-r--r--dts/Bindings/arm/arm,versatile.yaml71
-rw-r--r--dts/Bindings/arm/arm,vexpress-juno.yaml223
-rw-r--r--dts/Bindings/arm/arm-boards237
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm11351-cpu-method.txt36
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm11351.txt10
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm11351.yaml21
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm21664.txt15
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm21664.yaml21
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm23550-cpu-method.txt36
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm23550.txt15
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm23550.yaml21
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm4708.txt15
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm4708.yaml88
-rw-r--r--dts/Bindings/arm/bcm/brcm,cygnus.txt31
-rw-r--r--dts/Bindings/arm/bcm/brcm,cygnus.yaml29
-rw-r--r--dts/Bindings/arm/bcm/brcm,hr2.txt14
-rw-r--r--dts/Bindings/arm/bcm/brcm,hr2.yaml28
-rw-r--r--dts/Bindings/arm/bcm/brcm,ns2.txt9
-rw-r--r--dts/Bindings/arm/bcm/brcm,ns2.yaml23
-rw-r--r--dts/Bindings/arm/bcm/brcm,nsp-cpu-method.txt39
-rw-r--r--dts/Bindings/arm/bcm/brcm,nsp.txt34
-rw-r--r--dts/Bindings/arm/bcm/brcm,nsp.yaml36
-rw-r--r--dts/Bindings/arm/bcm/brcm,stingray.txt12
-rw-r--r--dts/Bindings/arm/bcm/brcm,stingray.yaml24
-rw-r--r--dts/Bindings/arm/bcm/brcm,vulcan-soc.txt10
-rw-r--r--dts/Bindings/arm/bcm/brcm,vulcan-soc.yaml22
-rw-r--r--dts/Bindings/arm/coresight-cti.yaml336
-rw-r--r--dts/Bindings/arm/coresight.txt7
-rw-r--r--dts/Bindings/arm/cpus.yaml46
-rw-r--r--dts/Bindings/arm/freescale/fsl,scu.txt18
-rw-r--r--dts/Bindings/arm/fsl.yaml69
-rw-r--r--dts/Bindings/arm/l2c2x0.yaml45
-rw-r--r--dts/Bindings/arm/mrvl/mrvl.yaml5
-rw-r--r--dts/Bindings/arm/msm/qcom,llcc.yaml2
-rw-r--r--dts/Bindings/arm/pmu.yaml41
-rw-r--r--dts/Bindings/arm/psci.yaml5
-rw-r--r--dts/Bindings/arm/qcom.yaml8
-rw-r--r--dts/Bindings/arm/renesas,prr.yaml2
-rw-r--r--dts/Bindings/arm/renesas.yaml1
-rw-r--r--dts/Bindings/arm/rockchip.yaml12
-rw-r--r--dts/Bindings/arm/samsung/exynos-chipid.yaml2
-rw-r--r--dts/Bindings/arm/samsung/pmu.yaml2
-rw-r--r--dts/Bindings/arm/samsung/samsung-secure-firmware.yaml2
-rw-r--r--dts/Bindings/arm/socionext/cache-uniphier.txt60
-rw-r--r--dts/Bindings/arm/socionext/socionext,uniphier-system-cache.yaml102
-rw-r--r--dts/Bindings/arm/socionext/uniphier.txt47
-rw-r--r--dts/Bindings/arm/socionext/uniphier.yaml61
-rw-r--r--dts/Bindings/arm/stm32/st,stm32-syscon.yaml2
-rw-r--r--dts/Bindings/arm/sunxi.yaml26
-rw-r--r--dts/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml1
-rw-r--r--dts/Bindings/arm/tegra/nvidia,tegra20-pmc.txt300
-rw-r--r--dts/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml354
-rw-r--r--dts/Bindings/arm/vexpress.txt229
-rw-r--r--dts/Bindings/ata/renesas,rcar-sata.yaml71
-rw-r--r--dts/Bindings/ata/sata_rcar.txt36
-rw-r--r--dts/Bindings/bus/socionext,uniphier-system-bus.yaml96
-rw-r--r--dts/Bindings/bus/ti-sysc.txt1
-rw-r--r--dts/Bindings/bus/uniphier-system-bus.txt66
-rw-r--r--dts/Bindings/chrome/google,cros-ec-typec.yaml54
-rw-r--r--dts/Bindings/clock/arm,syscon-icst.yaml103
-rw-r--r--dts/Bindings/clock/arm-integrator.txt34
-rw-r--r--dts/Bindings/clock/arm-syscon-icst.txt70
-rw-r--r--dts/Bindings/clock/clock-bindings.txt2
-rw-r--r--dts/Bindings/clock/fsl,plldig.yaml5
-rw-r--r--dts/Bindings/clock/imx8mm-clock.txt29
-rw-r--r--dts/Bindings/clock/imx8mm-clock.yaml68
-rw-r--r--dts/Bindings/clock/imx8mn-clock.yaml50
-rw-r--r--dts/Bindings/clock/imx8mp-clock.yaml2
-rw-r--r--dts/Bindings/clock/imx8mq-clock.txt20
-rw-r--r--dts/Bindings/clock/imx8mq-clock.yaml72
-rw-r--r--dts/Bindings/clock/marvell,mmp2-clock.yaml64
-rw-r--r--dts/Bindings/clock/marvell,mmp2.txt21
-rw-r--r--dts/Bindings/clock/milbeaut-clock.yaml2
-rw-r--r--dts/Bindings/clock/qcom,gcc-apq8064.yaml2
-rw-r--r--dts/Bindings/clock/qcom,gcc-ipq8074.yaml2
-rw-r--r--dts/Bindings/clock/qcom,gcc-msm8996.yaml2
-rw-r--r--dts/Bindings/clock/qcom,gcc-msm8998.yaml2
-rw-r--r--dts/Bindings/clock/qcom,gcc-qcs404.yaml2
-rw-r--r--dts/Bindings/clock/qcom,gcc-sc7180.yaml2
-rw-r--r--dts/Bindings/clock/qcom,gcc-sm8150.yaml2
-rw-r--r--dts/Bindings/clock/qcom,gcc-sm8250.yaml72
-rw-r--r--dts/Bindings/clock/qcom,gcc.yaml2
-rw-r--r--dts/Bindings/clock/qcom,mmcc.yaml2
-rw-r--r--dts/Bindings/clock/qcom,msm8998-gpucc.yaml2
-rw-r--r--dts/Bindings/clock/qcom,rpmcc.txt2
-rw-r--r--dts/Bindings/clock/qcom,rpmhcc.yaml3
-rw-r--r--dts/Bindings/clock/qcom,sc7180-dispcc.yaml2
-rw-r--r--dts/Bindings/clock/qcom,sc7180-gpucc.yaml2
-rw-r--r--dts/Bindings/clock/qcom,sc7180-mss.yaml62
-rw-r--r--dts/Bindings/clock/qcom,sc7180-videocc.yaml2
-rw-r--r--dts/Bindings/clock/qcom,sdm845-dispcc.yaml2
-rw-r--r--dts/Bindings/clock/qcom,sdm845-gpucc.yaml2
-rw-r--r--dts/Bindings/clock/qcom,sdm845-videocc.yaml2
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.txt100
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.yaml119
-rw-r--r--dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt17
-rw-r--r--dts/Bindings/clock/socionext,uniphier-clock.yaml94
-rw-r--r--dts/Bindings/clock/sprd,sc9860-clk.txt (renamed from dts/Bindings/clock/sprd.txt)2
-rw-r--r--dts/Bindings/clock/sprd,sc9863a-clk.yaml105
-rw-r--r--dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml35
-rw-r--r--dts/Bindings/clock/uniphier-clock.txt132
-rw-r--r--dts/Bindings/connector/samsung,usb-connector-11pin.txt2
-rw-r--r--dts/Bindings/connector/usb-connector.txt135
-rw-r--r--dts/Bindings/connector/usb-connector.yaml206
-rw-r--r--dts/Bindings/crypto/fsl-dcp.txt2
-rw-r--r--dts/Bindings/crypto/fsl-imx-sahara.txt2
-rw-r--r--dts/Bindings/crypto/fsl-sec4.txt2
-rw-r--r--dts/Bindings/crypto/xlnx,zynqmp-aes.yaml37
-rw-r--r--dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml6
-rw-r--r--dts/Bindings/display/amlogic,meson-vpu.yaml8
-rw-r--r--dts/Bindings/display/bridge/adi,adv7511.txt23
-rw-r--r--dts/Bindings/display/bridge/ps8640.yaml112
-rw-r--r--dts/Bindings/display/bridge/toshiba,tc358768.yaml159
-rw-r--r--dts/Bindings/display/connector/analog-tv-connector.txt6
-rw-r--r--dts/Bindings/display/etnaviv/etnaviv-drm.txt36
-rw-r--r--dts/Bindings/display/ilitek,ili9486.yaml73
-rw-r--r--dts/Bindings/display/mediatek/mediatek,dpi.txt1
-rw-r--r--dts/Bindings/display/msm/gmu.txt116
-rw-r--r--dts/Bindings/display/msm/gmu.yaml123
-rw-r--r--dts/Bindings/display/msm/gpu.txt55
-rw-r--r--dts/Bindings/display/panel/advantech,idk-1110wr.yaml69
-rw-r--r--dts/Bindings/display/panel/advantech,idk-2121wr.yaml122
-rw-r--r--dts/Bindings/display/panel/auo,b080uan01.txt7
-rw-r--r--dts/Bindings/display/panel/auo,b101aw03.txt7
-rw-r--r--dts/Bindings/display/panel/auo,b101ean01.txt7
-rw-r--r--dts/Bindings/display/panel/auo,b101xtn01.txt7
-rw-r--r--dts/Bindings/display/panel/auo,b116xw03.txt7
-rw-r--r--dts/Bindings/display/panel/auo,b133htn01.txt7
-rw-r--r--dts/Bindings/display/panel/auo,b133xtn01.txt7
-rw-r--r--dts/Bindings/display/panel/auo,g070vvn01.txt29
-rw-r--r--dts/Bindings/display/panel/auo,g101evn010.txt12
-rw-r--r--dts/Bindings/display/panel/auo,g104sn02.txt12
-rw-r--r--dts/Bindings/display/panel/auo,g133han01.txt7
-rw-r--r--dts/Bindings/display/panel/auo,g185han01.txt7
-rw-r--r--dts/Bindings/display/panel/auo,p320hvn03.txt8
-rw-r--r--dts/Bindings/display/panel/auo,t215hvn01.txt7
-rw-r--r--dts/Bindings/display/panel/avic,tm070ddh03.txt7
-rw-r--r--dts/Bindings/display/panel/boe,hv070wsa-100.txt28
-rw-r--r--dts/Bindings/display/panel/boe,nv101wxmn51.txt7
-rw-r--r--dts/Bindings/display/panel/boe,tv080wum-nl0.txt7
-rw-r--r--dts/Bindings/display/panel/boe,tv101wum-nl6.yaml80
-rw-r--r--dts/Bindings/display/panel/cdtech,s043wq26h-ct7.txt12
-rw-r--r--dts/Bindings/display/panel/cdtech,s070wv95-ct16.txt12
-rw-r--r--dts/Bindings/display/panel/chunghwa,claa070wp03xg.txt7
-rw-r--r--dts/Bindings/display/panel/chunghwa,claa101wa01a.txt7
-rw-r--r--dts/Bindings/display/panel/chunghwa,claa101wb03.txt7
-rw-r--r--dts/Bindings/display/panel/dataimage,scf0700c48ggu18.txt8
-rw-r--r--dts/Bindings/display/panel/display-timing.txt124
-rw-r--r--dts/Bindings/display/panel/display-timings.yaml77
-rw-r--r--dts/Bindings/display/panel/dlc,dlc1010gig.txt12
-rw-r--r--dts/Bindings/display/panel/edt,et-series.txt55
-rw-r--r--dts/Bindings/display/panel/elida,kd35t133.yaml49
-rw-r--r--dts/Bindings/display/panel/evervision,vgg804821.txt12
-rw-r--r--dts/Bindings/display/panel/feixin,k101-im2ba02.yaml55
-rw-r--r--dts/Bindings/display/panel/foxlink,fl500wvr00-a0t.txt7
-rw-r--r--dts/Bindings/display/panel/friendlyarm,hd702e.txt32
-rw-r--r--dts/Bindings/display/panel/giantplus,gpg482739qs5.txt7
-rw-r--r--dts/Bindings/display/panel/hannstar,hsd070pww1.txt7
-rw-r--r--dts/Bindings/display/panel/hannstar,hsd100pxn1.txt7
-rw-r--r--dts/Bindings/display/panel/hit,tx23d38vm0caa.txt7
-rw-r--r--dts/Bindings/display/panel/innolux,at043tn24.txt7
-rw-r--r--dts/Bindings/display/panel/innolux,at070tn92.txt7
-rw-r--r--dts/Bindings/display/panel/innolux,g070y2-l01.txt12
-rw-r--r--dts/Bindings/display/panel/innolux,g101ice-l01.txt7
-rw-r--r--dts/Bindings/display/panel/innolux,g121i1-l01.txt7
-rw-r--r--dts/Bindings/display/panel/innolux,g121x1-l03.txt7
-rw-r--r--dts/Bindings/display/panel/innolux,n116bge.txt7
-rw-r--r--dts/Bindings/display/panel/innolux,n156bge-l21.txt7
-rw-r--r--dts/Bindings/display/panel/innolux,zj070na-01p.txt7
-rw-r--r--dts/Bindings/display/panel/koe,tx14d24vm1bpa.txt42
-rw-r--r--dts/Bindings/display/panel/koe,tx31d200vm0baa.txt25
-rw-r--r--dts/Bindings/display/panel/kyo,tcg121xglp.txt7
-rw-r--r--dts/Bindings/display/panel/leadtek,ltk500hd1829.yaml2
-rw-r--r--dts/Bindings/display/panel/lemaker,bl035-rgb-002.txt12
-rw-r--r--dts/Bindings/display/panel/lg,lb070wv8.txt7
-rw-r--r--dts/Bindings/display/panel/lg,lp079qx1-sp0v.txt7
-rw-r--r--dts/Bindings/display/panel/lg,lp097qx1-spa1.txt7
-rw-r--r--dts/Bindings/display/panel/lg,lp120up1.txt7
-rw-r--r--dts/Bindings/display/panel/lg,lp129qe.txt7
-rw-r--r--dts/Bindings/display/panel/mitsubishi,aa070mc01.txt7
-rw-r--r--dts/Bindings/display/panel/nec,nl12880b20-05.txt8
-rw-r--r--dts/Bindings/display/panel/nec,nl4827hc19-05b.txt7
-rw-r--r--dts/Bindings/display/panel/netron-dy,e231732.txt7
-rw-r--r--dts/Bindings/display/panel/newhaven,nhd-4.3-480272ef-atxl.txt7
-rw-r--r--dts/Bindings/display/panel/nlt,nl192108ac18-02d.txt8
-rw-r--r--dts/Bindings/display/panel/novatek,nt35510.yaml56
-rw-r--r--dts/Bindings/display/panel/nvd,9128.txt7
-rw-r--r--dts/Bindings/display/panel/okaya,rs800480t-7x0gp.txt7
-rw-r--r--dts/Bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt7
-rw-r--r--dts/Bindings/display/panel/ontat,yx700wv03.txt7
-rw-r--r--dts/Bindings/display/panel/orisetech,otm8009a.txt23
-rw-r--r--dts/Bindings/display/panel/orisetech,otm8009a.yaml53
-rw-r--r--dts/Bindings/display/panel/ortustech,com37h3m05dtc.txt12
-rw-r--r--dts/Bindings/display/panel/ortustech,com37h3m99dtc.txt12
-rw-r--r--dts/Bindings/display/panel/ortustech,com43h4m85ulc.txt7
-rw-r--r--dts/Bindings/display/panel/osddisplays,osd070t1718-19ts.txt12
-rw-r--r--dts/Bindings/display/panel/osddisplays,osd101t2045-53ts.txt11
-rw-r--r--dts/Bindings/display/panel/panasonic,vvx10f004b00.txt7
-rw-r--r--dts/Bindings/display/panel/panasonic,vvx10f034n00.txt20
-rw-r--r--dts/Bindings/display/panel/panel-common.yaml15
-rw-r--r--dts/Bindings/display/panel/panel-dpi.txt50
-rw-r--r--dts/Bindings/display/panel/panel-dpi.yaml71
-rw-r--r--dts/Bindings/display/panel/panel-simple-dsi.yaml67
-rw-r--r--dts/Bindings/display/panel/panel-simple.yaml209
-rw-r--r--dts/Bindings/display/panel/panel-timing.yaml227
-rw-r--r--dts/Bindings/display/panel/qiaodian,qd43003c0-40.txt7
-rw-r--r--dts/Bindings/display/panel/raydium,rm68200.txt25
-rw-r--r--dts/Bindings/display/panel/raydium,rm68200.yaml56
-rw-r--r--dts/Bindings/display/panel/rocktech,rk070er9427.txt25
-rw-r--r--dts/Bindings/display/panel/samsung,lsn122dl01-c01.txt7
-rw-r--r--dts/Bindings/display/panel/samsung,ltn101nt05.txt7
-rw-r--r--dts/Bindings/display/panel/samsung,ltn140at29-301.txt7
-rw-r--r--dts/Bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml50
-rw-r--r--dts/Bindings/display/panel/sharp,lq035q7db03.txt12
-rw-r--r--dts/Bindings/display/panel/sharp,lq070y3dg3b.txt12
-rw-r--r--dts/Bindings/display/panel/sharp,lq101k1ly04.txt7
-rw-r--r--dts/Bindings/display/panel/sharp,lq123p1jx31.txt7
-rw-r--r--dts/Bindings/display/panel/shelly,sca07010-bfn-lnn.txt7
-rw-r--r--dts/Bindings/display/panel/starry,kr122ea0sra.txt7
-rw-r--r--dts/Bindings/display/panel/tianma,tm070jdhg30.txt7
-rw-r--r--dts/Bindings/display/panel/tianma,tm070rvhg71.txt29
-rw-r--r--dts/Bindings/display/panel/toshiba,lt089ac29000.txt8
-rw-r--r--dts/Bindings/display/panel/tpk,f07a-0102.txt8
-rw-r--r--dts/Bindings/display/panel/tpk,f10a-0102.txt8
-rw-r--r--dts/Bindings/display/panel/urt,umsh-8596md.txt16
-rw-r--r--dts/Bindings/display/panel/vl050_8048nt_c01.txt12
-rw-r--r--dts/Bindings/display/panel/winstar,wf35ltiacd.txt48
-rw-r--r--dts/Bindings/display/panel/xinpeng,xpp055c272.yaml2
-rw-r--r--dts/Bindings/display/rockchip/rockchip-drm.txt19
-rw-r--r--dts/Bindings/display/rockchip/rockchip-drm.yaml40
-rw-r--r--dts/Bindings/display/sitronix,st7735r.txt35
-rw-r--r--dts/Bindings/display/sitronix,st7735r.yaml78
-rw-r--r--dts/Bindings/display/ti/ti,am65x-dss.yaml152
-rw-r--r--dts/Bindings/display/ti/ti,j721e-dss.yaml208
-rw-r--r--dts/Bindings/display/ti/ti,k2g-dss.yaml106
-rw-r--r--dts/Bindings/dma/renesas,usb-dmac.txt1
-rw-r--r--dts/Bindings/dma/sifive,fu540-c000-pdma.yaml2
-rw-r--r--dts/Bindings/dma/socionext,uniphier-mio-dmac.yaml63
-rw-r--r--dts/Bindings/dma/socionext,uniphier-xdmac.yaml63
-rw-r--r--dts/Bindings/dma/ti-edma.txt2
-rw-r--r--dts/Bindings/dma/ti/k3-udma.yaml19
-rw-r--r--dts/Bindings/dma/uniphier-mio-dmac.txt25
-rw-r--r--dts/Bindings/dsp/fsl,dsp.yaml2
-rw-r--r--dts/Bindings/edac/dmc-520.yaml59
-rw-r--r--dts/Bindings/eeprom/at24.yaml2
-rw-r--r--dts/Bindings/example-schema.yaml4
-rw-r--r--dts/Bindings/extcon/extcon-usbc-cros-ec.txt24
-rw-r--r--dts/Bindings/extcon/extcon-usbc-cros-ec.yaml56
-rw-r--r--dts/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml3
-rw-r--r--dts/Bindings/firmware/qcom,scm.txt1
-rw-r--r--dts/Bindings/fpga/fpga-region.txt5
-rw-r--r--dts/Bindings/fsi/ibm,fsi2spi.yaml36
-rw-r--r--dts/Bindings/gnss/gnss.txt2
-rw-r--r--dts/Bindings/gpio/brcm,xgs-iproc-gpio.yaml2
-rw-r--r--dts/Bindings/gpio/gpio-mvebu.txt2
-rw-r--r--dts/Bindings/gpio/gpio-uniphier.txt51
-rw-r--r--dts/Bindings/gpio/socionext,uniphier-gpio.yaml94
-rw-r--r--dts/Bindings/gpio/xylon,logicvc-gpio.yaml2
-rw-r--r--dts/Bindings/gpu/arm,mali-bifrost.yaml8
-rw-r--r--dts/Bindings/gpu/arm,mali-midgard.yaml5
-rw-r--r--dts/Bindings/gpu/arm,mali-utgard.yaml2
-rw-r--r--dts/Bindings/gpu/samsung-rotator.yaml2
-rw-r--r--dts/Bindings/gpu/vivante,gc.yaml69
-rw-r--r--dts/Bindings/hwmon/adi,adm1177.yaml2
-rw-r--r--dts/Bindings/hwmon/adi,axi-fan-control.yaml62
-rw-r--r--dts/Bindings/hwmon/adi,ltc2947.yaml2
-rw-r--r--dts/Bindings/hwmon/adt7475.yaml84
-rw-r--r--dts/Bindings/hwmon/ltc2978.txt22
-rw-r--r--dts/Bindings/hwmon/pmbus/ti,ucd90320.yaml2
-rw-r--r--dts/Bindings/hwmon/ti,tmp513.yaml2
-rw-r--r--dts/Bindings/i2c/brcm,brcmstb-i2c.yaml97
-rw-r--r--dts/Bindings/i2c/i2c-at91.txt10
-rw-r--r--dts/Bindings/i2c/i2c-brcmstb.txt26
-rw-r--r--dts/Bindings/i2c/i2c-rk3x.txt68
-rw-r--r--dts/Bindings/i2c/i2c-rk3x.yaml136
-rw-r--r--dts/Bindings/i2c/i2c-uniphier-f.txt25
-rw-r--r--dts/Bindings/i2c/i2c-uniphier.txt25
-rw-r--r--dts/Bindings/i2c/socionext,uniphier-fi2c.yaml50
-rw-r--r--dts/Bindings/i2c/socionext,uniphier-i2c.yaml50
-rw-r--r--dts/Bindings/iio/accel/adi,adxl345.yaml10
-rw-r--r--dts/Bindings/iio/accel/bosch,bma400.yaml2
-rw-r--r--dts/Bindings/iio/adc/adi,ad7192.yaml1
-rw-r--r--dts/Bindings/iio/adc/adi,ad7780.yaml2
-rw-r--r--dts/Bindings/iio/adc/adi,ad7923.yaml65
-rw-r--r--dts/Bindings/iio/adc/avia-hx711.yaml2
-rw-r--r--dts/Bindings/iio/adc/lltc,ltc2496.yaml2
-rw-r--r--dts/Bindings/iio/adc/max1363.txt63
-rw-r--r--dts/Bindings/iio/adc/maxim,max1238.yaml76
-rw-r--r--dts/Bindings/iio/adc/maxim,max1363.yaml50
-rw-r--r--dts/Bindings/iio/adc/microchip,mcp3911.yaml2
-rw-r--r--dts/Bindings/iio/adc/nuvoton,npcm-adc.txt2
-rw-r--r--dts/Bindings/iio/adc/st,stm32-adc.txt149
-rw-r--r--dts/Bindings/iio/adc/st,stm32-adc.yaml458
-rw-r--r--dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml2
-rw-r--r--dts/Bindings/iio/amplifiers/adi,hmc425a.yaml49
-rw-r--r--dts/Bindings/iio/chemical/atlas,ec-sm.txt21
-rw-r--r--dts/Bindings/iio/chemical/atlas,orp-sm.txt21
-rw-r--r--dts/Bindings/iio/chemical/atlas,ph-sm.txt21
-rw-r--r--dts/Bindings/iio/chemical/atlas,sensor.yaml53
-rw-r--r--dts/Bindings/iio/chemical/plantower,pms7003.yaml2
-rw-r--r--dts/Bindings/iio/chemical/sensirion,sps30.yaml2
-rw-r--r--dts/Bindings/iio/dac/adi,ad5770r.yaml185
-rw-r--r--dts/Bindings/iio/dac/lltc,ltc1660.yaml2
-rw-r--r--dts/Bindings/iio/dac/ltc2632.txt8
-rw-r--r--dts/Bindings/iio/imu/inv_mpu6050.txt5
-rw-r--r--dts/Bindings/iio/light/adux1020.yaml2
-rw-r--r--dts/Bindings/iio/light/bh1750.yaml2
-rw-r--r--dts/Bindings/iio/light/dynaimage,al3010.yaml43
-rw-r--r--dts/Bindings/iio/light/dynaimage,al3320a.yaml43
-rw-r--r--dts/Bindings/iio/light/isl29018.yaml2
-rw-r--r--dts/Bindings/iio/light/noa1305.yaml2
-rw-r--r--dts/Bindings/iio/light/sharp,gp2ap002.yaml85
-rw-r--r--dts/Bindings/iio/light/stk33xx.yaml2
-rw-r--r--dts/Bindings/iio/light/tsl2583.yaml2
-rw-r--r--dts/Bindings/iio/light/tsl2772.yaml2
-rw-r--r--dts/Bindings/iio/light/veml6030.yaml2
-rw-r--r--dts/Bindings/iio/pressure/asc,dlhl60d.yaml2
-rw-r--r--dts/Bindings/iio/pressure/bmp085.yaml5
-rw-r--r--dts/Bindings/iio/proximity/devantech-srf04.yaml20
-rw-r--r--dts/Bindings/iio/proximity/parallax-ping.yaml2
-rw-r--r--dts/Bindings/iio/temperature/adi,ltc2983.yaml40
-rw-r--r--dts/Bindings/input/gpio-vibrator.yaml2
-rw-r--r--dts/Bindings/input/iqs62x-keys.yaml132
-rw-r--r--dts/Bindings/input/max77650-onkey.yaml3
-rw-r--r--dts/Bindings/input/st,stpmic1-onkey.txt28
-rw-r--r--dts/Bindings/input/touchscreen/edt-ft5x06.txt77
-rw-r--r--dts/Bindings/input/touchscreen/edt-ft5x06.yaml125
-rw-r--r--dts/Bindings/input/touchscreen/goodix.yaml2
-rw-r--r--dts/Bindings/interconnect/qcom,bcm-voter.yaml45
-rw-r--r--dts/Bindings/interconnect/qcom,osm-l3.yaml62
-rw-r--r--dts/Bindings/interconnect/qcom,sc7180.yaml85
-rw-r--r--dts/Bindings/interconnect/qcom,sdm845.txt24
-rw-r--r--dts/Bindings/interconnect/qcom,sdm845.yaml74
-rw-r--r--dts/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml2
-rw-r--r--dts/Bindings/interrupt-controller/loongson,htpic.yaml59
-rw-r--r--dts/Bindings/interrupt-controller/loongson,liointc.yaml93
-rw-r--r--dts/Bindings/interrupt-controller/msi.txt2
-rw-r--r--dts/Bindings/interrupt-controller/socionext,uniphier-aidet.txt32
-rw-r--r--dts/Bindings/interrupt-controller/socionext,uniphier-aidet.yaml61
-rw-r--r--dts/Bindings/iommu/samsung,sysmmu.yaml2
-rw-r--r--dts/Bindings/ipmi/aspeed-kcs-bmc.txt20
-rw-r--r--dts/Bindings/leds/common.yaml4
-rw-r--r--dts/Bindings/leds/leds-max77650.yaml3
-rw-r--r--dts/Bindings/leds/rohm,bd71828-leds.yaml3
-rw-r--r--dts/Bindings/mailbox/allwinner,sun6i-a31-msgbox.yaml80
-rw-r--r--dts/Bindings/mailbox/amlogic,meson-gxbb-mhu.yaml2
-rw-r--r--dts/Bindings/mailbox/fsl,mu.txt2
-rw-r--r--dts/Bindings/mailbox/mtk-gce.txt10
-rw-r--r--dts/Bindings/media/allwinner,sun8i-a83t-de2-rotate.yaml70
-rw-r--r--dts/Bindings/media/allwinner,sun8i-h3-deinterlace.yaml6
-rw-r--r--dts/Bindings/media/amlogic,gx-vdec.yaml2
-rw-r--r--dts/Bindings/media/amlogic,meson-gx-ao-cec.yaml11
-rw-r--r--dts/Bindings/media/aspeed-video.txt5
-rw-r--r--dts/Bindings/media/i2c/imx219.yaml114
-rw-r--r--dts/Bindings/media/i2c/tvp5150.txt146
-rw-r--r--dts/Bindings/media/nxp,imx8mq-vpu.yaml77
-rw-r--r--dts/Bindings/media/qcom,msm8916-venus.yaml119
-rw-r--r--dts/Bindings/media/qcom,msm8996-venus.yaml172
-rw-r--r--dts/Bindings/media/qcom,sc7180-venus.yaml140
-rw-r--r--dts/Bindings/media/qcom,sdm845-venus-v2.yaml140
-rw-r--r--dts/Bindings/media/qcom,sdm845-venus.yaml156
-rw-r--r--dts/Bindings/media/qcom,venus.txt120
-rw-r--r--dts/Bindings/media/rc.yaml1
-rw-r--r--dts/Bindings/media/renesas,ceu.yaml2
-rw-r--r--dts/Bindings/media/renesas,vin.txt217
-rw-r--r--dts/Bindings/media/renesas,vin.yaml402
-rw-r--r--dts/Bindings/media/rockchip-rga.txt5
-rw-r--r--dts/Bindings/mfd/iqs62x.yaml179
-rw-r--r--dts/Bindings/mfd/max77650.yaml2
-rw-r--r--dts/Bindings/mfd/qcom-rpm.txt4
-rw-r--r--dts/Bindings/mfd/rn5t618.txt4
-rw-r--r--dts/Bindings/mfd/rohm,bd71828-pmic.yaml5
-rw-r--r--dts/Bindings/mfd/rohm,bd71837-pmic.txt90
-rw-r--r--dts/Bindings/mfd/rohm,bd71837-pmic.yaml236
-rw-r--r--dts/Bindings/mfd/rohm,bd71847-pmic.yaml222
-rw-r--r--dts/Bindings/mfd/st,stm32-lptimer.yaml16
-rw-r--r--dts/Bindings/mfd/st,stpmic1.txt61
-rw-r--r--dts/Bindings/mfd/st,stpmic1.yaml339
-rw-r--r--dts/Bindings/mips/loongson/devices.yaml27
-rw-r--r--dts/Bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml2
-rw-r--r--dts/Bindings/mmc/cdns,sdhci.yaml143
-rw-r--r--dts/Bindings/mmc/fsl-imx-esdhc.txt5
-rw-r--r--dts/Bindings/mmc/mmc-controller.yaml2
-rw-r--r--dts/Bindings/mmc/mmci.txt2
-rw-r--r--dts/Bindings/mmc/sdhci-am654.txt21
-rw-r--r--dts/Bindings/mmc/sdhci-cadence.txt80
-rw-r--r--dts/Bindings/mmc/sdhci-msm.txt8
-rw-r--r--dts/Bindings/mmc/socionext,uniphier-sd.yaml99
-rw-r--r--dts/Bindings/mmc/synopsys-dw-mshc.yaml2
-rw-r--r--dts/Bindings/mmc/uniphier-sd.txt55
-rw-r--r--dts/Bindings/mtd/brcm,brcmnand.txt10
-rw-r--r--dts/Bindings/mtd/denali,nand.yaml148
-rw-r--r--dts/Bindings/mtd/denali-nand.txt61
-rw-r--r--dts/Bindings/mtd/nand-macronix.txt27
-rw-r--r--dts/Bindings/net/broadcom-bluetooth.txt2
-rw-r--r--dts/Bindings/net/can/bosch,m_can.yaml144
-rw-r--r--dts/Bindings/net/can/can-transceiver.txt24
-rw-r--r--dts/Bindings/net/can/can-transceiver.yaml18
-rw-r--r--dts/Bindings/net/can/m_can.txt75
-rw-r--r--dts/Bindings/net/can/tcan4x5x.txt2
-rw-r--r--dts/Bindings/net/dsa/ocelot.txt116
-rw-r--r--dts/Bindings/net/marvell,mvusb.yaml64
-rw-r--r--dts/Bindings/net/mediatek-bluetooth.txt2
-rw-r--r--dts/Bindings/net/qca,qca7000.txt2
-rw-r--r--dts/Bindings/net/qcom,ipa.yaml198
-rw-r--r--dts/Bindings/net/qcom,ipq8064-mdio.yaml53
-rw-r--r--dts/Bindings/net/qualcomm-bluetooth.txt2
-rw-r--r--dts/Bindings/net/ti,cpsw-switch.yaml25
-rw-r--r--dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml225
-rw-r--r--dts/Bindings/net/ti-bluetooth.txt3
-rw-r--r--dts/Bindings/net/wireless/mediatek,mt76.txt29
-rw-r--r--dts/Bindings/net/wireless/qcom,ath10k.txt7
-rw-r--r--dts/Bindings/net/wireless/ti,wl1251.txt3
-rw-r--r--dts/Bindings/nvmem/ingenic,jz4780-efuse.yaml45
-rw-r--r--dts/Bindings/opp/qcom-nvmem-cpufreq.txt3
-rw-r--r--dts/Bindings/pci/amlogic,meson-pcie.txt22
-rw-r--r--dts/Bindings/pci/cdns,cdns-pcie-ep.txt27
-rw-r--r--dts/Bindings/pci/cdns,cdns-pcie-ep.yaml49
-rw-r--r--dts/Bindings/pci/cdns,cdns-pcie-host.txt66
-rw-r--r--dts/Bindings/pci/cdns,cdns-pcie-host.yaml76
-rw-r--r--dts/Bindings/pci/cdns-pcie-host.yaml27
-rw-r--r--dts/Bindings/pci/cdns-pcie.yaml31
-rw-r--r--dts/Bindings/pci/layerscape-pcie-gen4.txt52
-rw-r--r--dts/Bindings/pci/nvidia,tegra194-pcie.txt127
-rw-r--r--dts/Bindings/pci/pci-ep.yaml41
-rw-r--r--dts/Bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml2
-rw-r--r--dts/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml35
-rw-r--r--dts/Bindings/phy/amlogic,meson-axg-pcie.yaml52
-rw-r--r--dts/Bindings/phy/amlogic,meson-g12a-usb2-phy.yaml14
-rw-r--r--dts/Bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml2
-rw-r--r--dts/Bindings/phy/intel,lgm-emmc-phy.yaml2
-rw-r--r--dts/Bindings/phy/marvell,mmp3-hsic-phy.yaml2
-rw-r--r--dts/Bindings/phy/marvell,mmp3-usb-phy.yaml42
-rw-r--r--dts/Bindings/phy/nvidia,tegra124-xusb-padctl.txt24
-rw-r--r--dts/Bindings/phy/phy-cadence-dp.txt30
-rw-r--r--dts/Bindings/phy/phy-cadence-torrent.yaml143
-rw-r--r--dts/Bindings/phy/phy-mmp3-usb.txt13
-rw-r--r--dts/Bindings/phy/phy-mtk-tphy.txt32
-rw-r--r--dts/Bindings/phy/phy-rockchip-inno-usb2.txt81
-rw-r--r--dts/Bindings/phy/phy-rockchip-inno-usb2.yaml155
-rw-r--r--dts/Bindings/phy/qcom,qusb2-phy.yaml185
-rw-r--r--dts/Bindings/phy/qcom,usb-hs-28nm.yaml90
-rw-r--r--dts/Bindings/phy/qcom,usb-ss.yaml83
-rw-r--r--dts/Bindings/phy/qcom-dwc3-usb-phy.txt37
-rw-r--r--dts/Bindings/phy/qcom-qmp-phy.txt15
-rw-r--r--dts/Bindings/phy/qcom-qusb2-phy.txt68
-rw-r--r--dts/Bindings/phy/ti,phy-j721e-wiz.yaml2
-rw-r--r--dts/Bindings/phy/ti-phy-gmii-sel.txt1
-rw-r--r--dts/Bindings/phy/uniphier-pcie-phy.txt13
-rw-r--r--dts/Bindings/phy/uniphier-usb3-hsphy.txt6
-rw-r--r--dts/Bindings/phy/uniphier-usb3-ssphy.txt5
-rw-r--r--dts/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml2
-rw-r--r--dts/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml2
-rw-r--r--dts/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml2
-rw-r--r--dts/Bindings/pinctrl/atmel,at91-pinctrl.txt2
-rw-r--r--dts/Bindings/pinctrl/fsl,imx8mm-pinctrl.txt36
-rw-r--r--dts/Bindings/pinctrl/fsl,imx8mm-pinctrl.yaml82
-rw-r--r--dts/Bindings/pinctrl/fsl,imx8mn-pinctrl.txt39
-rw-r--r--dts/Bindings/pinctrl/fsl,imx8mn-pinctrl.yaml82
-rw-r--r--dts/Bindings/pinctrl/fsl,imx8mp-pinctrl.yaml25
-rw-r--r--dts/Bindings/pinctrl/fsl,imx8mq-pinctrl.txt36
-rw-r--r--dts/Bindings/pinctrl/fsl,imx8mq-pinctrl.yaml82
-rw-r--r--dts/Bindings/pinctrl/qcom,ipq6018-pinctrl.yaml153
-rw-r--r--dts/Bindings/pinctrl/socionext,uniphier-pinctrl.txt27
-rw-r--r--dts/Bindings/pinctrl/socionext,uniphier-pinctrl.yaml42
-rw-r--r--dts/Bindings/pinctrl/st,stm32-pinctrl.yaml2
-rw-r--r--dts/Bindings/power/amlogic,meson-ee-pwrc.yaml2
-rw-r--r--dts/Bindings/power/amlogic,meson-sec-pwrc.yaml40
-rw-r--r--dts/Bindings/power/power-domain.yaml28
-rw-r--r--dts/Bindings/power/renesas,apmu.txt35
-rw-r--r--dts/Bindings/power/renesas,apmu.yaml55
-rw-r--r--dts/Bindings/power/renesas,rcar-sysc.txt62
-rw-r--r--dts/Bindings/power/renesas,rcar-sysc.yaml73
-rw-r--r--dts/Bindings/power/reset/syscon-poweroff.yaml2
-rw-r--r--dts/Bindings/power/reset/syscon-reboot.yaml2
-rw-r--r--dts/Bindings/power/supply/max77650-charger.yaml3
-rw-r--r--dts/Bindings/ptp/ptp-idt82p33.yaml45
-rw-r--r--dts/Bindings/ptp/ptp-idtcm.yaml2
-rw-r--r--dts/Bindings/pwm/google,cros-ec-pwm.txt23
-rw-r--r--dts/Bindings/pwm/google,cros-ec-pwm.yaml40
-rw-r--r--dts/Bindings/pwm/iqs620a-pwm.yaml32
-rw-r--r--dts/Bindings/pwm/nvidia,tegra20-pwm.txt1
-rw-r--r--dts/Bindings/pwm/pwm-mediatek.txt5
-rw-r--r--dts/Bindings/pwm/renesas,tpu-pwm.yaml4
-rw-r--r--dts/Bindings/regulator/max77650-regulator.yaml5
-rw-r--r--dts/Bindings/regulator/mp886x.txt27
-rw-r--r--dts/Bindings/regulator/mps,mp5416.yaml78
-rw-r--r--dts/Bindings/regulator/qcom,smd-rpm-regulator.txt13
-rw-r--r--dts/Bindings/regulator/rohm,bd71837-regulator.txt162
-rw-r--r--dts/Bindings/regulator/rohm,bd71837-regulator.yaml103
-rw-r--r--dts/Bindings/regulator/rohm,bd71847-regulator.yaml97
-rw-r--r--dts/Bindings/regulator/st,stpmic1-regulator.txt64
-rw-r--r--dts/Bindings/regulator/vqmmc-ipq4019-regulator.yaml42
-rw-r--r--dts/Bindings/remoteproc/ti,omap-remoteproc.yaml324
-rw-r--r--dts/Bindings/reset/amlogic,meson-reset.yaml2
-rw-r--r--dts/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml2
-rw-r--r--dts/Bindings/reset/renesas,rst.txt48
-rw-r--r--dts/Bindings/reset/renesas,rst.yaml63
-rw-r--r--dts/Bindings/rng/amlogic,meson-rng.yaml2
-rw-r--r--dts/Bindings/rng/brcm,bcm2835.txt40
-rw-r--r--dts/Bindings/rng/brcm,bcm2835.yaml61
-rw-r--r--dts/Bindings/rtc/ingenic,jz4740-rtc.txt37
-rw-r--r--dts/Bindings/rtc/ingenic,rtc.yaml83
-rw-r--r--dts/Bindings/rtc/renesas,sh-rtc.yaml2
-rw-r--r--dts/Bindings/rtc/rtc-mt2712.txt14
-rw-r--r--dts/Bindings/rtc/st,stm32-rtc.yaml2
-rw-r--r--dts/Bindings/serial/amlogic,meson-uart.yaml2
-rw-r--r--dts/Bindings/serial/fsl-imx-uart.txt6
-rw-r--r--dts/Bindings/serial/fsl-lpuart.txt10
-rw-r--r--dts/Bindings/serial/renesas,hscif.yaml135
-rw-r--r--dts/Bindings/serial/renesas,sci-serial.txt150
-rw-r--r--dts/Bindings/serial/renesas,sci.yaml69
-rw-r--r--dts/Bindings/serial/renesas,scif.yaml172
-rw-r--r--dts/Bindings/serial/renesas,scifa.yaml107
-rw-r--r--dts/Bindings/serial/renesas,scifb.yaml98
-rw-r--r--dts/Bindings/serial/serial.txt56
-rw-r--r--dts/Bindings/serial/serial.yaml131
-rw-r--r--dts/Bindings/serial/slave-device.txt45
-rw-r--r--dts/Bindings/serial/snps-dw-apb-uart.yaml1
-rw-r--r--dts/Bindings/serial/socionext,uniphier-uart.yaml46
-rw-r--r--dts/Bindings/serial/uniphier-uart.txt22
-rw-r--r--dts/Bindings/soc/amlogic/amlogic,canvas.yaml2
-rw-r--r--dts/Bindings/soc/imx/fsl,aips-bus.yaml47
-rw-r--r--dts/Bindings/soc/mediatek/pwrap.txt1
-rw-r--r--dts/Bindings/soc/qcom/qcom,apr.txt50
-rw-r--r--dts/Bindings/sound/adi,adau7118.yaml2
-rw-r--r--dts/Bindings/sound/amlogic,aiu.yaml113
-rw-r--r--dts/Bindings/sound/amlogic,g12a-toacodec.yaml51
-rw-r--r--dts/Bindings/sound/amlogic,gx-sound-card.yaml113
-rw-r--r--dts/Bindings/sound/amlogic,t9015.yaml58
-rw-r--r--dts/Bindings/sound/brcm,bcm63xx-audio.txt29
-rw-r--r--dts/Bindings/sound/cirrus,cs42l51.yaml69
-rw-r--r--dts/Bindings/sound/cs42l51.txt33
-rw-r--r--dts/Bindings/sound/google,cros-ec-codec.txt44
-rw-r--r--dts/Bindings/sound/google,cros-ec-codec.yaml67
-rw-r--r--dts/Bindings/sound/ingenic,aic.yaml92
-rw-r--r--dts/Bindings/sound/ingenic,jz4740-i2s.txt23
-rw-r--r--dts/Bindings/sound/nvidia,tegra-audio-wm8903.txt1
-rw-r--r--dts/Bindings/sound/qcom,wcd934x.yaml2
-rw-r--r--dts/Bindings/sound/renesas,fsi.yaml2
-rw-r--r--dts/Bindings/sound/rockchip,rk3328-codec.txt7
-rw-r--r--dts/Bindings/sound/rockchip-i2s.txt49
-rw-r--r--dts/Bindings/sound/rockchip-i2s.yaml111
-rw-r--r--dts/Bindings/sound/rt5682.txt18
-rw-r--r--dts/Bindings/sound/samsung,odroid.yaml2
-rw-r--r--dts/Bindings/sound/samsung-i2s.yaml2
-rw-r--r--dts/Bindings/sound/st,stm32-i2s.txt62
-rw-r--r--dts/Bindings/sound/st,stm32-i2s.yaml87
-rw-r--r--dts/Bindings/sound/st,stm32-spdifrx.txt56
-rw-r--r--dts/Bindings/sound/st,stm32-spdifrx.yaml80
-rw-r--r--dts/Bindings/sound/tas2562.txt2
-rw-r--r--dts/Bindings/sound/tlv320adcx140.yaml82
-rw-r--r--dts/Bindings/spi/allwinner,sun6i-a31-spi.yaml11
-rw-r--r--dts/Bindings/spi/amlogic,meson-gx-spicc.yaml22
-rw-r--r--dts/Bindings/spi/fsl-imx-cspi.txt5
-rw-r--r--dts/Bindings/spi/qca,ar934x-spi.yaml41
-rw-r--r--dts/Bindings/spi/qcom,spi-qcom-qspi.txt36
-rw-r--r--dts/Bindings/spi/qcom,spi-qcom-qspi.yaml88
-rw-r--r--dts/Bindings/spi/spi-controller.yaml10
-rw-r--r--dts/Bindings/spi/spi-fsl-dspi.txt19
-rw-r--r--dts/Bindings/spi/spi-mtk-nor.txt (renamed from dts/Bindings/mtd/mtk-quadspi.txt)15
-rw-r--r--dts/Bindings/spi/spi-mux.yaml89
-rw-r--r--dts/Bindings/spi/spi-nxp-fspi.txt3
-rw-r--r--dts/Bindings/spi/spi-rockchip.txt58
-rw-r--r--dts/Bindings/spi/spi-rockchip.yaml107
-rw-r--r--dts/Bindings/sram/qcom,ocmem.yaml14
-rw-r--r--dts/Bindings/thermal/amlogic,thermal.yaml4
-rw-r--r--dts/Bindings/thermal/armada-thermal.txt2
-rw-r--r--dts/Bindings/thermal/imx8mm-thermal.txt15
-rw-r--r--dts/Bindings/thermal/qcom-tsens.yaml39
-rw-r--r--dts/Bindings/thermal/rcar-gen3-thermal.txt1
-rw-r--r--dts/Bindings/thermal/rcar-thermal.txt78
-rw-r--r--dts/Bindings/thermal/rcar-thermal.yaml139
-rw-r--r--dts/Bindings/thermal/sprd-thermal.yaml107
-rw-r--r--dts/Bindings/thermal/thermal.txt2
-rw-r--r--dts/Bindings/timer/arm,arch_timer.yaml2
-rw-r--r--dts/Bindings/timer/arm,arch_timer_mmio.yaml4
-rw-r--r--dts/Bindings/timer/arm,global_timer.yaml2
-rw-r--r--dts/Bindings/timer/faraday,fttmr010.txt1
-rw-r--r--dts/Bindings/timer/ingenic,tcu.txt1
-rw-r--r--dts/Bindings/timer/intel,ixp4xx-timer.yaml2
-rw-r--r--dts/Bindings/timer/samsung,exynos4210-mct.yaml2
-rw-r--r--dts/Bindings/trivial-devices.yaml16
-rw-r--r--dts/Bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml23
-rw-r--r--dts/Bindings/usb/aspeed,usb-vhub.yaml77
-rw-r--r--dts/Bindings/usb/dwc2.yaml49
-rw-r--r--dts/Bindings/usb/dwc3.txt7
-rw-r--r--dts/Bindings/usb/exynos-usb.txt9
-rw-r--r--dts/Bindings/usb/fcs,fusb302.txt2
-rw-r--r--dts/Bindings/usb/generic.txt8
-rw-r--r--dts/Bindings/usb/ingenic,jz4740-musb.txt32
-rw-r--r--dts/Bindings/usb/ingenic,jz4770-phy.yaml52
-rw-r--r--dts/Bindings/usb/ingenic,musb.yaml76
-rw-r--r--dts/Bindings/usb/maxim,max3420-udc.yaml69
-rw-r--r--dts/Bindings/usb/mediatek,mtu3.txt2
-rw-r--r--dts/Bindings/usb/mediatek,musb.txt2
-rw-r--r--dts/Bindings/usb/nvidia,tegra-xudc.yaml190
-rw-r--r--dts/Bindings/usb/richtek,rt1711h.txt2
-rw-r--r--dts/Bindings/usb/ti,hd3ss3220.txt2
-rw-r--r--dts/Bindings/usb/typec-tcpci.txt2
-rw-r--r--dts/Bindings/usb/usb-conn-gpio.txt4
-rw-r--r--dts/Bindings/vendor-prefixes.yaml39
-rw-r--r--dts/Bindings/watchdog/st,stpmic1-wdt.txt11
-rw-r--r--dts/Bindings/watchdog/ti,rti-wdt.yaml65
-rw-r--r--dts/include/dt-bindings/arm/coresight-cti-dt.h37
-rw-r--r--dts/include/dt-bindings/bus/ti-sysc.h4
-rw-r--r--dts/include/dt-bindings/clock/dm814.h5
-rw-r--r--dts/include/dt-bindings/clock/g12a-clkc.h2
-rw-r--r--dts/include/dt-bindings/clock/gxbb-clkc.h1
-rw-r--r--dts/include/dt-bindings/clock/imx7d-clock.h3
-rw-r--r--dts/include/dt-bindings/clock/imx8mm-clock.h11
-rw-r--r--dts/include/dt-bindings/clock/imx8mn-clock.h8
-rw-r--r--dts/include/dt-bindings/clock/imx8mp-clock.h5
-rw-r--r--dts/include/dt-bindings/clock/imx8mq-clock.h9
-rw-r--r--dts/include/dt-bindings/clock/k210-clk.h20
-rw-r--r--dts/include/dt-bindings/clock/marvell,mmp2.h13
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-sc7180.h7
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-sm8150.h4
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-sm8250.h271
-rw-r--r--dts/include/dt-bindings/clock/qcom,gpucc-sc7180.h3
-rw-r--r--dts/include/dt-bindings/clock/qcom,mss-sc7180.h12
-rw-r--r--dts/include/dt-bindings/clock/qcom,rpmcc.h4
-rw-r--r--dts/include/dt-bindings/clock/qcom,rpmh.h4
-rw-r--r--dts/include/dt-bindings/clock/sprd,sc9863a-clk.h334
-rw-r--r--dts/include/dt-bindings/clock/sun50i-a64-ccu.h2
-rw-r--r--dts/include/dt-bindings/clock/tegra114-car.h4
-rw-r--r--dts/include/dt-bindings/clock/tegra124-car-common.h4
-rw-r--r--dts/include/dt-bindings/clock/tegra210-car.h4
-rw-r--r--dts/include/dt-bindings/clock/tegra30-car.h4
-rw-r--r--dts/include/dt-bindings/display/sdtv-standards.h76
-rw-r--r--dts/include/dt-bindings/input/linux-event-codes.h2
-rw-r--r--dts/include/dt-bindings/interconnect/qcom,osm-l3.h12
-rw-r--r--dts/include/dt-bindings/interconnect/qcom,sc7180.h161
-rw-r--r--dts/include/dt-bindings/interconnect/qcom,sdm845.h263
-rw-r--r--dts/include/dt-bindings/leds/common.h36
-rw-r--r--dts/include/dt-bindings/media/tvp5150.h2
-rw-r--r--dts/include/dt-bindings/power/meson-a1-power.h32
-rw-r--r--dts/include/dt-bindings/soc/tegra-pmc.h16
-rw-r--r--dts/include/dt-bindings/sound/meson-aiu.h18
-rw-r--r--dts/include/dt-bindings/sound/meson-g12a-toacodec.h10
-rw-r--r--dts/src/arc/axs10x_mb.dtsi1
-rw-r--r--dts/src/arm/am33xx-l4.dtsi21
-rw-r--r--dts/src/arm/am33xx.dtsi133
-rw-r--r--dts/src/arm/am4372.dtsi191
-rw-r--r--dts/src/arm/am437x-l4.dtsi77
-rw-r--r--dts/src/arm/am57-pruss.dtsi50
-rw-r--r--dts/src/arm/am5718.dtsi1
-rw-r--r--dts/src/arm/am5728.dtsi1
-rw-r--r--dts/src/arm/am5748.dtsi1
-rw-r--r--dts/src/arm/arm-realview-pbx.dtsi2
-rw-r--r--dts/src/arm/aspeed-g4.dtsi2
-rw-r--r--dts/src/arm/aspeed-g5.dtsi2
-rw-r--r--dts/src/arm/aspeed-g6-pinctrl.dtsi25
-rw-r--r--dts/src/arm/aspeed-g6.dtsi45
-rw-r--r--dts/src/arm/at91-dvk_su60_somc_lcm.dtsi2
-rw-r--r--dts/src/arm/at91-sam9x60ek.dts5
-rw-r--r--dts/src/arm/at91-sama5d27_wlsom1_ek.dts12
-rw-r--r--dts/src/arm/at91-sama5d2_ptc_ek.dts33
-rw-r--r--dts/src/arm/at91-sama5d2_xplained.dts33
-rw-r--r--dts/src/arm/at91-sama5d4_ma5d4evk.dts2
-rw-r--r--dts/src/arm/at91sam9n12ek.dts2
-rw-r--r--dts/src/arm/at91sam9x5dm.dtsi2
-rw-r--r--dts/src/arm/bcm2711-rpi-4-b.dts74
-rw-r--r--dts/src/arm/bcm2711.dtsi25
-rw-r--r--dts/src/arm/dm814x-clocks.dtsi14
-rw-r--r--dts/src/arm/dm814x.dtsi260
-rw-r--r--dts/src/arm/dm816x.dtsi148
-rw-r--r--dts/src/arm/dra62x.dtsi6
-rw-r--r--dts/src/arm/dra7.dtsi219
-rw-r--r--dts/src/arm/dra72x.dtsi6
-rw-r--r--dts/src/arm/dra74x.dtsi10
-rw-r--r--dts/src/arm/ecx-2000.dts6
-rw-r--r--dts/src/arm/ecx-common.dtsi17
-rw-r--r--dts/src/arm/exynos3250-artik5.dtsi2
-rw-r--r--dts/src/arm/exynos4210-universal_c210.dts4
-rw-r--r--dts/src/arm/exynos4412-odroid-common.dtsi9
-rw-r--r--dts/src/arm/exynos5250-arndale.dts10
-rw-r--r--dts/src/arm/exynos5420-arndale-octa.dts2
-rw-r--r--dts/src/arm/exynos5422-cpus.dtsi8
-rw-r--r--dts/src/arm/exynos5422-odroid-core.dtsi1
-rw-r--r--dts/src/arm/exynos5422-odroidhc1.dts30
-rw-r--r--dts/src/arm/exynos5422-odroidxu3-common.dtsi59
-rw-r--r--dts/src/arm/gemini-dlink-dir-685.dts50
-rw-r--r--dts/src/arm/gemini-dlink-dns-313.dts2
-rw-r--r--dts/src/arm/gemini-nas4220b.dts4
-rw-r--r--dts/src/arm/gemini-sl93512r.dts4
-rw-r--r--dts/src/arm/gemini-sq201.dts2
-rw-r--r--dts/src/arm/gemini.dtsi8
-rw-r--r--dts/src/arm/highbank.dts11
-rw-r--r--dts/src/arm/imx23-olinuxino.dts2
-rw-r--r--dts/src/arm/imx23.dtsi10
-rw-r--r--dts/src/arm/imx25-pinfunc.h8
-rw-r--r--dts/src/arm/imx25.dtsi4
-rw-r--r--dts/src/arm/imx27.dtsi2
-rw-r--r--dts/src/arm/imx28-apx4devkit.dts10
-rw-r--r--dts/src/arm/imx28.dtsi2
-rw-r--r--dts/src/arm/imx31.dtsi4
-rw-r--r--dts/src/arm/imx35.dtsi4
-rw-r--r--dts/src/arm/imx50.dtsi4
-rw-r--r--dts/src/arm/imx51-zii-rdu1.dts5
-rw-r--r--dts/src/arm/imx51.dtsi17
-rw-r--r--dts/src/arm/imx53.dtsi4
-rw-r--r--dts/src/arm/imx6dl-colibri-eval-v3.dts40
-rw-r--r--dts/src/arm/imx6dl-pico-dwarf.dts17
-rw-r--r--dts/src/arm/imx6dl-pico-hobbit.dts17
-rw-r--r--dts/src/arm/imx6dl-pico-nymph.dts17
-rw-r--r--dts/src/arm/imx6dl-pico-pi.dts17
-rw-r--r--dts/src/arm/imx6dl-riotboard.dts16
-rw-r--r--dts/src/arm/imx6dl-yapp4-common.dtsi2
-rw-r--r--dts/src/arm/imx6dl.dtsi8
-rw-r--r--dts/src/arm/imx6q-apalis-eval.dts40
-rw-r--r--dts/src/arm/imx6q-apalis-ixora-v1.1.dts40
-rw-r--r--dts/src/arm/imx6q-apalis-ixora.dts40
-rw-r--r--dts/src/arm/imx6q-marsboard.dts16
-rw-r--r--dts/src/arm/imx6q-novena.dts2
-rw-r--r--dts/src/arm/imx6q-pico-dwarf.dts17
-rw-r--r--dts/src/arm/imx6q-pico-hobbit.dts17
-rw-r--r--dts/src/arm/imx6q-pico-nymph.dts17
-rw-r--r--dts/src/arm/imx6q-pico-pi.dts17
-rw-r--r--dts/src/arm/imx6q.dtsi6
-rw-r--r--dts/src/arm/imx6qdl-apalis.dtsi42
-rw-r--r--dts/src/arm/imx6qdl-colibri.dtsi40
-rw-r--r--dts/src/arm/imx6qdl-gw52xx.dtsi5
-rw-r--r--dts/src/arm/imx6qdl-gw53xx.dtsi5
-rw-r--r--dts/src/arm/imx6qdl-gw54xx.dtsi5
-rw-r--r--dts/src/arm/imx6qdl-gw553x.dtsi31
-rw-r--r--dts/src/arm/imx6qdl-gw5910.dtsi25
-rw-r--r--dts/src/arm/imx6qdl-phytec-phycore-som.dtsi5
-rw-r--r--dts/src/arm/imx6qdl-pico-dwarf.dtsi45
-rw-r--r--dts/src/arm/imx6qdl-pico-hobbit.dtsi37
-rw-r--r--dts/src/arm/imx6qdl-pico-nymph.dtsi54
-rw-r--r--dts/src/arm/imx6qdl-pico-pi.dtsi31
-rw-r--r--dts/src/arm/imx6qdl-pico.dtsi617
-rw-r--r--dts/src/arm/imx6qdl-sr-som-ti.dtsi1
-rw-r--r--dts/src/arm/imx6qdl-zii-rdu2.dtsi7
-rw-r--r--dts/src/arm/imx6qdl.dtsi30
-rw-r--r--dts/src/arm/imx6qp.dtsi2
-rw-r--r--dts/src/arm/imx6sl.dtsi28
-rw-r--r--dts/src/arm/imx6sll.dtsi12
-rw-r--r--dts/src/arm/imx6sx-nitrogen6sx.dts20
-rw-r--r--dts/src/arm/imx6sx-pinfunc.h286
-rw-r--r--dts/src/arm/imx6sx-sabreauto.dts4
-rw-r--r--dts/src/arm/imx6sx-sdb.dtsi12
-rw-r--r--dts/src/arm/imx6sx-softing-vining-2000.dts22
-rw-r--r--dts/src/arm/imx6sx-udoo-neo.dtsi28
-rw-r--r--dts/src/arm/imx6sx.dtsi34
-rw-r--r--dts/src/arm/imx6ul-ccimx6ulsbcpro.dts2
-rw-r--r--dts/src/arm/imx6ul-pico-dwarf.dts52
-rw-r--r--dts/src/arm/imx6ul-pico.dtsi39
-rw-r--r--dts/src/arm/imx6ul.dtsi28
-rw-r--r--dts/src/arm/imx6ull.dtsi2
-rw-r--r--dts/src/arm/imx7-colibri-aster.dtsi169
-rw-r--r--dts/src/arm/imx7-colibri-eval-v3.dtsi46
-rw-r--r--dts/src/arm/imx7-colibri.dtsi230
-rw-r--r--dts/src/arm/imx7d-cl-som-imx7.dts4
-rw-r--r--dts/src/arm/imx7d-colibri-aster.dts20
-rw-r--r--dts/src/arm/imx7d-colibri-emmc-aster.dts20
-rw-r--r--dts/src/arm/imx7d-colibri-emmc.dtsi26
-rw-r--r--dts/src/arm/imx7d-colibri-eval-v3.dts41
-rw-r--r--dts/src/arm/imx7d-colibri.dtsi41
-rw-r--r--dts/src/arm/imx7d-pico-dwarf.dts87
-rw-r--r--dts/src/arm/imx7d-pico-nymph.dts84
-rw-r--r--dts/src/arm/imx7s-colibri-aster.dts15
-rw-r--r--dts/src/arm/imx7s-colibri-eval-v3.dts41
-rw-r--r--dts/src/arm/imx7s-colibri.dtsi41
-rw-r--r--dts/src/arm/imx7s.dtsi38
-rw-r--r--dts/src/arm/imx7ulp-evk.dts3
-rw-r--r--dts/src/arm/imx7ulp.dtsi4
-rw-r--r--dts/src/arm/integratorap.dts1
-rw-r--r--dts/src/arm/mmp2-brownstone.dts332
-rw-r--r--dts/src/arm/mmp2.dtsi16
-rw-r--r--dts/src/arm/mmp3.dtsi16
-rw-r--r--dts/src/arm/mt2701.dtsi2
-rw-r--r--dts/src/arm/mt7623.dtsi2
-rw-r--r--dts/src/arm/mt7629.dtsi16
-rw-r--r--dts/src/arm/omap4-l4.dtsi1
-rw-r--r--dts/src/arm/omap4.dtsi279
-rw-r--r--dts/src/arm/omap5-l4-abe.dtsi16
-rw-r--r--dts/src/arm/omap5.dtsi241
-rw-r--r--dts/src/arm/pxa168-aspenite.dts24
-rw-r--r--dts/src/arm/pxa168.dtsi15
-rw-r--r--dts/src/arm/pxa910-dkb.dts286
-rw-r--r--dts/src/arm/pxa910.dtsi15
-rw-r--r--dts/src/arm/qcom-apq8064.dtsi1
-rw-r--r--dts/src/arm/qcom-apq8084.dtsi1
-rw-r--r--dts/src/arm/qcom-ipq4019.dtsi1
-rw-r--r--dts/src/arm/qcom-ipq8064.dtsi1
-rw-r--r--dts/src/arm/qcom-mdm9615.dtsi1
-rw-r--r--dts/src/arm/qcom-msm8660.dtsi1
-rw-r--r--dts/src/arm/qcom-msm8960.dtsi1
-rw-r--r--dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts71
-rw-r--r--dts/src/arm/qcom-msm8974-sony-xperia-honami.dts25
-rw-r--r--dts/src/arm/qcom-msm8974.dtsi10
-rw-r--r--dts/src/arm/r7s72100-gr-peach.dts3
-rw-r--r--dts/src/arm/r7s72100.dtsi5
-rw-r--r--dts/src/arm/r8a73a4-ape6evm.dts7
-rw-r--r--dts/src/arm/r8a7743.dtsi5
-rw-r--r--dts/src/arm/r8a7744.dtsi5
-rw-r--r--dts/src/arm/r8a7745-iwg22d-sodimm-dbhd-ca.dts6
-rw-r--r--dts/src/arm/r8a7745-iwg22d-sodimm.dts93
-rw-r--r--dts/src/arm/r8a7745.dtsi3
-rw-r--r--dts/src/arm/r8a77470.dtsi5
-rw-r--r--dts/src/arm/r8a7790-lager.dts1
-rw-r--r--dts/src/arm/r8a7790-stout.dts1
-rw-r--r--dts/src/arm/r8a7790.dtsi2
-rw-r--r--dts/src/arm/r8a7791-koelsch.dts1
-rw-r--r--dts/src/arm/r8a7791-porter.dts1
-rw-r--r--dts/src/arm/r8a7791.dtsi5
-rw-r--r--dts/src/arm/r8a7792.dtsi5
-rw-r--r--dts/src/arm/r8a7793-gose.dts1
-rw-r--r--dts/src/arm/r8a7793.dtsi5
-rw-r--r--dts/src/arm/r8a7794-alt.dts1
-rw-r--r--dts/src/arm/r8a7794-silk.dts1
-rw-r--r--dts/src/arm/r8a7794.dtsi2
-rw-r--r--dts/src/arm/rk3036-kylin.dts2
-rw-r--r--dts/src/arm/rk3036.dtsi8
-rw-r--r--dts/src/arm/rk3066a.dtsi18
-rw-r--r--dts/src/arm/rk3188-bqedison2qc.dts29
-rw-r--r--dts/src/arm/rk3188.dtsi10
-rw-r--r--dts/src/arm/rk322x.dtsi17
-rw-r--r--dts/src/arm/rk3288-evb-act8846.dts1
-rw-r--r--dts/src/arm/rk3288-evb-rk808.dts1
-rw-r--r--dts/src/arm/rk3288-firefly-reload.dts1
-rw-r--r--dts/src/arm/rk3288-r89.dts1
-rw-r--r--dts/src/arm/rk3288-tinker.dtsi1
-rw-r--r--dts/src/arm/rk3288-vyasa.dts28
-rw-r--r--dts/src/arm/rk3288.dtsi26
-rw-r--r--dts/src/arm/rk3xxx.dtsi4
-rw-r--r--dts/src/arm/rv1108.dtsi12
-rw-r--r--dts/src/arm/sam9x60.dtsi8
-rw-r--r--dts/src/arm/sama5d2.dtsi2
-rw-r--r--dts/src/arm/sama5d3.dtsi33
-rw-r--r--dts/src/arm/sama5d4.dtsi35
-rw-r--r--dts/src/arm/sh73a0-kzm9g.dts9
-rw-r--r--dts/src/arm/socfpga_arria10.dtsi12
-rw-r--r--dts/src/arm/socfpga_arria10_socdk_nand.dts4
-rw-r--r--dts/src/arm/ste-ab8500.dtsi6
-rw-r--r--dts/src/arm/ste-ab8505.dtsi6
-rw-r--r--dts/src/arm/ste-dbx5x0.dtsi6
-rw-r--r--dts/src/arm/ste-href-stuib.dtsi2
-rw-r--r--dts/src/arm/ste-href-tvk1281618-r2.dtsi2
-rw-r--r--dts/src/arm/ste-href-tvk1281618-r3.dtsi2
-rw-r--r--dts/src/arm/ste-ux500-samsung-skomer.dts581
-rw-r--r--dts/src/arm/stm32746g-eval.dts2
-rw-r--r--dts/src/arm/stm32mp15-pinctrl.dtsi93
-rw-r--r--dts/src/arm/stm32mp151.dtsi16
-rw-r--r--dts/src/arm/stm32mp153.dtsi1
-rw-r--r--dts/src/arm/stm32mp157a-avenger96.dts11
-rw-r--r--dts/src/arm/stm32mp157c-dhcom-pdk2.dts265
-rw-r--r--dts/src/arm/stm32mp157c-dhcom-som.dtsi368
-rw-r--r--dts/src/arm/stm32mp157c-ed1.dts16
-rw-r--r--dts/src/arm/stm32mp157c-ev1.dts13
-rw-r--r--dts/src/arm/stm32mp15xx-dkx.dtsi10
-rw-r--r--dts/src/arm/sun5i-a13-pocketbook-touch-lux-3.dts257
-rw-r--r--dts/src/arm/sun5i.dtsi5
-rw-r--r--dts/src/arm/sun6i-a31.dtsi12
-rw-r--r--dts/src/arm/sun7i-a20-linutronix-testbox-v2.dts47
-rw-r--r--dts/src/arm/sun7i-a20.dtsi25
-rw-r--r--dts/src/arm/sun8i-a23-a33.dtsi3
-rw-r--r--dts/src/arm/sun8i-a33.dtsi2
-rw-r--r--dts/src/arm/sun8i-a83t-tbs-a711.dts1
-rw-r--r--dts/src/arm/sun8i-a83t.dtsi73
-rw-r--r--dts/src/arm/sun8i-h3.dtsi25
-rw-r--r--dts/src/arm/sun8i-r40.dtsi32
-rw-r--r--dts/src/arm/sun8i-v3s.dtsi2
-rw-r--r--dts/src/arm/sunxi-h3-h5.dtsi19
-rw-r--r--dts/src/arm/tango4-common.dtsi2
-rw-r--r--dts/src/arm/tegra114-dalmore.dts8
-rw-r--r--dts/src/arm/tegra114.dtsi4
-rw-r--r--dts/src/arm/tegra124-apalis-v1.2.dtsi8
-rw-r--r--dts/src/arm/tegra124-apalis.dtsi8
-rw-r--r--dts/src/arm/tegra124-jetson-tk1.dts14
-rw-r--r--dts/src/arm/tegra124-nyan.dtsi8
-rw-r--r--dts/src/arm/tegra124-venice2.dts8
-rw-r--r--dts/src/arm/tegra124.dtsi4
-rw-r--r--dts/src/arm/tegra20.dtsi4
-rw-r--r--dts/src/arm/tegra30-apalis-v1.1.dtsi8
-rw-r--r--dts/src/arm/tegra30-apalis.dtsi8
-rw-r--r--dts/src/arm/tegra30-beaver.dts8
-rw-r--r--dts/src/arm/tegra30-cardhu.dtsi8
-rw-r--r--dts/src/arm/tegra30-colibri.dtsi8
-rw-r--r--dts/src/arm/tegra30.dtsi4
-rw-r--r--dts/src/arm/uniphier-ld4.dtsi10
-rw-r--r--dts/src/arm/uniphier-pro4.dtsi12
-rw-r--r--dts/src/arm/uniphier-pro5.dtsi164
-rw-r--r--dts/src/arm/uniphier-pxs2.dtsi14
-rw-r--r--dts/src/arm/uniphier-ref-daughter.dtsi2
-rw-r--r--dts/src/arm/uniphier-sld8.dtsi10
-rw-r--r--dts/src/arm/versatile-ab-ib2.dts2
-rw-r--r--dts/src/arm/vexpress-v2m-rs1.dtsi2
-rw-r--r--dts/src/arm/vexpress-v2m.dtsi2
-rw-r--r--dts/src/arm/vexpress-v2p-ca15-tc1.dts2
-rw-r--r--dts/src/arm/vexpress-v2p-ca15_a7.dts2
-rw-r--r--dts/src/arm/vexpress-v2p-ca5s.dts2
-rw-r--r--dts/src/arm/vexpress-v2p-ca9.dts2
-rw-r--r--dts/src/arm/vf-colibri-eval-v3.dtsi40
-rw-r--r--dts/src/arm/vf-colibri.dtsi39
-rw-r--r--dts/src/arm/vf500-colibri-eval-v3.dts40
-rw-r--r--dts/src/arm/vf500-colibri.dtsi40
-rw-r--r--dts/src/arm/vf500.dtsi4
-rw-r--r--dts/src/arm/vf610-colibri-eval-v3.dts40
-rw-r--r--dts/src/arm/vf610-colibri.dtsi40
-rw-r--r--dts/src/arm/vf610-zii-cfu1.dts8
-rw-r--r--dts/src/arm/vf610-zii-dev.dtsi8
-rw-r--r--dts/src/arm/vf610-zii-spb4.dts8
-rw-r--r--dts/src/arm/vf610-zii-ssmb-dtu.dts8
-rw-r--r--dts/src/arm/vf610-zii-ssmb-spu3.dts8
-rw-r--r--dts/src/arm/vf610m4-colibri.dts39
-rw-r--r--dts/src/arm/vfxxx.dtsi4
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-olinuxino.dts17
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-pinebook.dts170
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-pinephone-1.0.dts11
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-pinephone-1.1.dts11
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-pinephone.dtsi379
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-pinetab.dts460
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64.dtsi44
-rw-r--r--dts/src/arm64/allwinner/sun50i-h5-orangepi-pc2.dts21
-rw-r--r--dts/src/arm64/allwinner/sun50i-h5.dtsi3
-rw-r--r--dts/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts11
-rw-r--r--dts/src/arm64/allwinner/sun50i-h6-orangepi-3.dts20
-rw-r--r--dts/src/arm64/allwinner/sun50i-h6-orangepi-one-plus.dts33
-rw-r--r--dts/src/arm64/allwinner/sun50i-h6-orangepi.dtsi37
-rw-r--r--dts/src/arm64/allwinner/sun50i-h6-pine-h64.dts30
-rw-r--r--dts/src/arm64/allwinner/sun50i-h6.dtsi66
-rw-r--r--dts/src/arm64/altera/socfpga_stratix10_socdk.dts6
-rw-r--r--dts/src/arm64/amlogic/meson-a1.dtsi6
-rw-r--r--dts/src/arm64/amlogic/meson-axg-s400.dts6
-rw-r--r--dts/src/arm64/amlogic/meson-g12-common.dtsi136
-rw-r--r--dts/src/arm64/amlogic/meson-g12.dtsi2
-rw-r--r--dts/src/arm64/amlogic/meson-g12a-sei510.dts4
-rw-r--r--dts/src/arm64/amlogic/meson-g12a-u200.dts2
-rw-r--r--dts/src/arm64/amlogic/meson-g12a-x96-max.dts2
-rw-r--r--dts/src/arm64/amlogic/meson-g12b-khadas-vim3.dtsi4
-rw-r--r--dts/src/arm64/amlogic/meson-g12b-odroid-n2.dts25
-rw-r--r--dts/src/arm64/amlogic/meson-g12b-ugoos-am6.dts2
-rw-r--r--dts/src/arm64/amlogic/meson-gx.dtsi52
-rw-r--r--dts/src/arm64/amlogic/meson-gxbb-kii-pro.dts4
-rw-r--r--dts/src/arm64/amlogic/meson-gxbb-odroidc2.dts1
-rw-r--r--dts/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi3
-rw-r--r--dts/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi9
-rw-r--r--dts/src/arm64/amlogic/meson-gxm-khadas-vim2.dts87
-rw-r--r--dts/src/arm64/amlogic/meson-gxm.dtsi28
-rw-r--r--dts/src/arm64/amlogic/meson-khadas-vim3.dtsi24
-rw-r--r--dts/src/arm64/amlogic/meson-sm1-sei610.dts2
-rw-r--r--dts/src/arm64/amlogic/meson-sm1.dtsi1
-rw-r--r--dts/src/arm64/arm/foundation-v8.dtsi2
-rw-r--r--dts/src/arm64/arm/fvp-base-revc.dts2
-rw-r--r--dts/src/arm64/arm/juno-base.dtsi2
-rw-r--r--dts/src/arm64/arm/juno-motherboard.dtsi2
-rw-r--r--dts/src/arm64/arm/rtsm_ve-aemv8a.dts2
-rw-r--r--dts/src/arm64/arm/rtsm_ve-motherboard-rs2.dtsi2
-rw-r--r--dts/src/arm64/arm/rtsm_ve-motherboard.dtsi2
-rw-r--r--dts/src/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts2
-rw-r--r--dts/src/arm64/arm/vexpress-v2m-rs1.dtsi2
-rw-r--r--dts/src/arm64/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts91
-rw-r--r--dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var2.dts72
-rw-r--r--dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts117
-rw-r--r--dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var4.dts51
-rw-r--r--dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28.dts187
-rw-r--r--dts/src/arm64/freescale/fsl-ls1028a-qds.dts1
-rw-r--r--dts/src/arm64/freescale/fsl-ls1028a-rdb.dts65
-rw-r--r--dts/src/arm64/freescale/fsl-ls1028a.dtsi257
-rw-r--r--dts/src/arm64/freescale/fsl-ls1088a-rdb.dts1
-rw-r--r--dts/src/arm64/freescale/fsl-ls1088a.dtsi4
-rw-r--r--dts/src/arm64/freescale/fsl-ls208xa.dtsi4
-rw-r--r--dts/src/arm64/freescale/fsl-lx2160a-cex7.dtsi37
-rw-r--r--dts/src/arm64/freescale/fsl-lx2160a-qds.dts15
-rw-r--r--dts/src/arm64/freescale/fsl-lx2160a-rdb.dts4
-rw-r--r--dts/src/arm64/freescale/fsl-lx2160a.dtsi168
-rw-r--r--dts/src/arm64/freescale/imx8mm-evk.dts2
-rw-r--r--dts/src/arm64/freescale/imx8mm.dtsi74
-rw-r--r--dts/src/arm64/freescale/imx8mn-evk.dtsi21
-rw-r--r--dts/src/arm64/freescale/imx8mn.dtsi81
-rw-r--r--dts/src/arm64/freescale/imx8mp-evk.dts270
-rw-r--r--dts/src/arm64/freescale/imx8mp-pinfunc.h931
-rw-r--r--dts/src/arm64/freescale/imx8mp.dtsi654
-rw-r--r--dts/src/arm64/freescale/imx8mq-evk.dts2
-rw-r--r--dts/src/arm64/freescale/imx8mq-librem5-devkit.dts148
-rw-r--r--dts/src/arm64/freescale/imx8mq-phanbell.dts104
-rw-r--r--dts/src/arm64/freescale/imx8mq.dtsi18
-rw-r--r--dts/src/arm64/freescale/imx8qxp.dtsi39
-rw-r--r--dts/src/arm64/freescale/s32v234.dtsi4
-rw-r--r--dts/src/arm64/intel/socfpga_agilex_socdk.dts6
-rw-r--r--dts/src/arm64/marvell/armada-3720-espressobin-emmc.dts2
-rw-r--r--dts/src/arm64/marvell/armada-3720-espressobin-v7-emmc.dts2
-rw-r--r--dts/src/arm64/marvell/armada-3720-espressobin-v7.dts2
-rw-r--r--dts/src/arm64/marvell/armada-3720-espressobin.dtsi8
-rw-r--r--dts/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts1
-rw-r--r--dts/src/arm64/marvell/armada-8040-mcbin.dtsi3
-rw-r--r--dts/src/arm64/marvell/armada-ap806-dual.dtsi5
-rw-r--r--dts/src/arm64/marvell/armada-ap807-quad.dtsi8
-rw-r--r--dts/src/arm64/mediatek/mt2712e.dtsi8
-rw-r--r--dts/src/arm64/mediatek/mt6797.dtsi2
-rw-r--r--dts/src/arm64/mediatek/mt7622.dtsi2
-rw-r--r--dts/src/arm64/mediatek/mt8173.dtsi3
-rw-r--r--dts/src/arm64/mediatek/mt8183.dtsi53
-rw-r--r--dts/src/arm64/mediatek/mt8516-pinfunc.h663
-rw-r--r--dts/src/arm64/mediatek/mt8516-pumpkin.dts20
-rw-r--r--dts/src/arm64/mediatek/mt8516.dtsi457
-rw-r--r--dts/src/arm64/mediatek/pumpkin-common.dtsi221
-rw-r--r--dts/src/arm64/nvidia/tegra132.dtsi4
-rw-r--r--dts/src/arm64/nvidia/tegra186-p2771-0000.dts26
-rw-r--r--dts/src/arm64/nvidia/tegra186-p3310.dtsi1
-rw-r--r--dts/src/arm64/nvidia/tegra186.dtsi19
-rw-r--r--dts/src/arm64/nvidia/tegra194-p2888.dtsi36
-rw-r--r--dts/src/arm64/nvidia/tegra194-p2972-0000.dts81
-rw-r--r--dts/src/arm64/nvidia/tegra194.dtsi250
-rw-r--r--dts/src/arm64/nvidia/tegra210-p2180.dtsi3
-rw-r--r--dts/src/arm64/nvidia/tegra210-p2371-2180.dts2
-rw-r--r--dts/src/arm64/nvidia/tegra210-p2597.dtsi45
-rw-r--r--dts/src/arm64/nvidia/tegra210-p3450-0000.dts24
-rw-r--r--dts/src/arm64/nvidia/tegra210-smaug.dts2
-rw-r--r--dts/src/arm64/nvidia/tegra210.dtsi25
-rw-r--r--dts/src/arm64/qcom/apq8016-sbc.dtsi1
-rw-r--r--dts/src/arm64/qcom/apq8096-db820c.dtsi6
-rw-r--r--dts/src/arm64/qcom/ipq6018-cp01-c1.dts64
-rw-r--r--dts/src/arm64/qcom/ipq6018.dtsi443
-rw-r--r--dts/src/arm64/qcom/ipq8074.dtsi1
-rw-r--r--dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi8
-rw-r--r--dts/src/arm64/qcom/msm8916.dtsi21
-rw-r--r--dts/src/arm64/qcom/msm8992.dtsi1
-rw-r--r--dts/src/arm64/qcom/msm8994.dtsi1
-rw-r--r--dts/src/arm64/qcom/msm8996.dtsi33
-rw-r--r--dts/src/arm64/qcom/msm8998-mtp.dtsi8
-rw-r--r--dts/src/arm64/qcom/msm8998.dtsi16
-rw-r--r--dts/src/arm64/qcom/pm6150.dtsi2
-rw-r--r--dts/src/arm64/qcom/pm8998.dtsi2
-rw-r--r--dts/src/arm64/qcom/qcs404-evb.dtsi1
-rw-r--r--dts/src/arm64/qcom/qcs404.dtsi4
-rw-r--r--dts/src/arm64/qcom/sc7180-idp.dts64
-rw-r--r--dts/src/arm64/qcom/sc7180.dtsi605
-rw-r--r--dts/src/arm64/qcom/sdm845-cheza.dtsi15
-rw-r--r--dts/src/arm64/qcom/sdm845-db845c.dts283
-rw-r--r--dts/src/arm64/qcom/sdm845-mtp.dts89
-rw-r--r--dts/src/arm64/qcom/sdm845.dtsi672
-rw-r--r--dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts114
-rw-r--r--dts/src/arm64/qcom/sm8250-mtp.dts29
-rw-r--r--dts/src/arm64/qcom/sm8250.dtsi444
-rw-r--r--dts/src/arm64/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts52
-rw-r--r--dts/src/arm64/renesas/r8a774a1.dtsi7
-rw-r--r--dts/src/arm64/renesas/r8a774b1.dtsi7
-rw-r--r--dts/src/arm64/renesas/r8a774c0.dtsi8
-rw-r--r--dts/src/arm64/renesas/r8a77950.dtsi2
-rw-r--r--dts/src/arm64/renesas/r8a77951.dtsi11
-rw-r--r--dts/src/arm64/renesas/r8a77960.dtsi16
-rw-r--r--dts/src/arm64/renesas/r8a77961-salvator-xs.dts2
-rw-r--r--dts/src/arm64/renesas/r8a77961-ulcb.dts32
-rw-r--r--dts/src/arm64/renesas/r8a77961.dtsi89
-rw-r--r--dts/src/arm64/renesas/r8a77965.dtsi31
-rw-r--r--dts/src/arm64/renesas/r8a77970.dtsi4
-rw-r--r--dts/src/arm64/renesas/r8a77980.dtsi7
-rw-r--r--dts/src/arm64/renesas/r8a77990.dtsi29
-rw-r--r--dts/src/arm64/renesas/r8a77995.dtsi14
-rw-r--r--dts/src/arm64/rockchip/px30.dtsi32
-rw-r--r--dts/src/arm64/rockchip/rk3308.dtsi10
-rw-r--r--dts/src/arm64/rockchip/rk3328-a1.dts1
-rw-r--r--dts/src/arm64/rockchip/rk3328-rock64.dts1
-rw-r--r--dts/src/arm64/rockchip/rk3328.dtsi7
-rw-r--r--dts/src/arm64/rockchip/rk3368-px5-evb.dts1
-rw-r--r--dts/src/arm64/rockchip/rk3368.dtsi3
-rw-r--r--dts/src/arm64/rockchip/rk3399-evb.dts270
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-chromebook.dtsi4
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru.dtsi4
-rw-r--r--dts/src/arm64/rockchip/rk3399-hugsun-x99.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3399-orangepi.dts43
-rw-r--r--dts/src/arm64/rockchip/rk3399-pinebook-pro.dts1096
-rw-r--r--dts/src/arm64/rockchip/rk3399-puma.dtsi2
-rw-r--r--dts/src/arm64/rockchip/rk3399-rock960.dtsi2
-rw-r--r--dts/src/arm64/rockchip/rk3399-sapphire-excavator.dts2
-rw-r--r--dts/src/arm64/rockchip/rk3399.dtsi11
-rw-r--r--dts/src/arm64/rockchip/rk3399pro-rock-pi-n10.dts3
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11.dtsi10
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20.dtsi20
-rw-r--r--dts/src/arm64/socionext/uniphier-pxs3-ref.dts10
-rw-r--r--dts/src/arm64/socionext/uniphier-pxs3.dtsi55
-rw-r--r--dts/src/arm64/ti/k3-am65-main.dtsi4
-rw-r--r--dts/src/arm64/ti/k3-am65-mcu.dtsi61
-rw-r--r--dts/src/arm64/ti/k3-am65.dtsi1
-rw-r--r--dts/src/arm64/ti/k3-am654-base-board.dts42
-rw-r--r--dts/src/arm64/ti/k3-j721e-common-proc-board.dts43
-rw-r--r--dts/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi69
-rw-r--r--dts/src/arm64/ti/k3-j721e.dtsi1
-rw-r--r--dts/src/mips/brcm/bcm7425.dtsi4
-rw-r--r--dts/src/mips/ingenic/ci20.dts19
-rw-r--r--dts/src/mips/loongson/loongson3-package.dtsi64
-rw-r--r--dts/src/mips/loongson/loongson3_4core_rs780e.dts25
-rw-r--r--dts/src/mips/loongson/loongson3_8core_rs780e.dts25
-rw-r--r--dts/src/mips/loongson/rs780e-pch.dtsi26
-rw-r--r--dts/src/nios2/10m50_devboard.dts6
-rw-r--r--dts/src/riscv/kendryte/k210.dts23
-rw-r--r--dts/src/riscv/kendryte/k210.dtsi123
1097 files changed, 39016 insertions, 9456 deletions
diff --git a/dts/Bindings/.gitignore b/dts/Bindings/.gitignore
index ef82fcf..5c6d8ea 100644
--- a/dts/Bindings/.gitignore
+++ b/dts/Bindings/.gitignore
@@ -1,2 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
*.example.dts
-processed-schema.yaml
+processed-schema*.yaml
diff --git a/dts/Bindings/Makefile b/dts/Bindings/Makefile
index 646cb35..1df680d 100644
--- a/dts/Bindings/Makefile
+++ b/dts/Bindings/Makefile
@@ -2,7 +2,6 @@
DT_DOC_CHECKER ?= dt-doc-validate
DT_EXTRACT_EX ?= dt-extract-example
DT_MK_SCHEMA ?= dt-mk-schema
-DT_MK_SCHEMA_FLAGS := $(if $(DT_SCHEMA_FILES), -u)
quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \
@@ -11,26 +10,35 @@ quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
$(obj)/%.example.dts: $(src)/%.yaml FORCE
$(call if_changed,chk_binding)
-DT_TMP_SCHEMA := processed-schema.yaml
+# Use full schemas when checking %.example.dts
+DT_TMP_SCHEMA := $(obj)/processed-schema-examples.yaml
quiet_cmd_mk_schema = SCHEMA $@
cmd_mk_schema = $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) -o $@ $(real-prereqs)
-DT_DOCS = $(shell \
+DT_DOCS = $(addprefix $(src)/, \
+ $(shell \
cd $(srctree)/$(src) && \
find * \( -name '*.yaml' ! \
- -name $(DT_TMP_SCHEMA) ! \
+ -name 'processed-schema*' ! \
-name '*.example.dt.yaml' \) \
- )
+ ))
-DT_SCHEMA_FILES ?= $(addprefix $(src)/,$(DT_DOCS))
+DT_SCHEMA_FILES ?= $(DT_DOCS)
-ifeq ($(CHECK_DTBS),)
-extra-y += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES))
-extra-y += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES))
-endif
+extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES))
+extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES))
+extra-$(CHECK_DT_BINDING) += processed-schema-examples.yaml
-$(obj)/$(DT_TMP_SCHEMA): $(DT_SCHEMA_FILES) FORCE
+override DTC_FLAGS := \
+ -Wno-avoid_unnecessary_addr_size \
+ -Wno-graph_child_address
+
+$(obj)/processed-schema-examples.yaml: $(DT_DOCS) FORCE
+ $(call if_changed,mk_schema)
+
+$(obj)/processed-schema.yaml: DT_MK_SCHEMA_FLAGS := -u
+$(obj)/processed-schema.yaml: $(DT_SCHEMA_FILES) FORCE
$(call if_changed,mk_schema)
-extra-y += $(DT_TMP_SCHEMA)
+extra-y += processed-schema.yaml
diff --git a/dts/Bindings/arm/altera/socfpga-clk-manager.yaml b/dts/Bindings/arm/altera/socfpga-clk-manager.yaml
index e4131fa..5723813 100644
--- a/dts/Bindings/arm/altera/socfpga-clk-manager.yaml
+++ b/dts/Bindings/arm/altera/socfpga-clk-manager.yaml
@@ -21,6 +21,8 @@ properties:
required:
- compatible
+additionalProperties: false
+
examples:
- |
clkmgr@ffd04000 {
diff --git a/dts/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml b/dts/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
index 853d7d2..66213bd 100644
--- a/dts/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
+++ b/dts/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
@@ -43,6 +43,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
ao-secure@140 {
diff --git a/dts/Bindings/arm/arm,integrator.yaml b/dts/Bindings/arm/arm,integrator.yaml
new file mode 100644
index 0000000..192ded4
--- /dev/null
+++ b/dts/Bindings/arm/arm,integrator.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,integrator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Integrator Boards Device Tree Bindings
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |+
+ These were the first ARM platforms officially supported by ARM Ltd.
+ They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
+ so the system is modular and can host a variety of CPU tiles called
+ "core tiles" and referred to in the device tree as "core modules".
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: ARM Integrator Application Platform, this board has a PCI
+ host and several PCI slots, as well as a number of slots for logical
+ expansion modules, it is referred to as an "ASIC Development
+ Motherboard" and is extended with custom FPGA and is intended for
+ rapid prototyping. See ARM DUI 0098B. This board can physically come
+ pre-packaged in a PC Tower form factor called Integrator/PP1 or a
+ special metal fixture called Integrator/PP2, see ARM DUI 0169A.
+ items:
+ - const: arm,integrator-ap
+ - description: ARM Integrator Compact Platform (HBI-0086), this board has
+ a compact form factor and mainly consists of the bare minimum
+ peripherals to make use of the core module. See ARM DUI 0159B.
+ items:
+ - const: arm,integrator-cp
+ - description: ARM Integrator Standard Development Board (SDB) Platform,
+ this board is a PCI-based board conforming to the Microsoft SDB
+ (HARP) specification. See ARM DUI 0099A.
+ items:
+ - const: arm,integrator-sp
+
+ core-module@10000000:
+ type: object
+ description: the root node in the Integrator platforms must contain
+ a core module child node. They are always at physical address
+ 0x10000000 in all the Integrator variants.
+ properties:
+ compatible:
+ items:
+ - const: arm,core-module-integrator
+ - const: syscon
+ - const: simple-mfd
+ reg:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+
+patternProperties:
+ "^syscon@[0-9a-f]+$":
+ description: All Integrator boards must provide a system controller as a
+ node in the root of the device tree.
+ type: object
+ properties:
+ compatible:
+ items:
+ - enum:
+ - arm,integrator-ap-syscon
+ - arm,integrator-cp-syscon
+ - arm,integrator-sp-syscon
+ - const: syscon
+ reg:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+
+
+required:
+ - compatible
+ - core-module@10000000
+
+...
diff --git a/dts/Bindings/arm/arm,realview.yaml b/dts/Bindings/arm/arm,realview.yaml
new file mode 100644
index 0000000..d6e85d1
--- /dev/null
+++ b/dts/Bindings/arm/arm,realview.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,realview.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM RealView Boards Device Tree Bindings
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |+
+ The ARM RealView series of reference designs were built to explore the ARM
+ 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
+ the earlier CPUs such as TrustZone and multicore (MPCore).
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: ARM RealView Emulation Baseboard (HBI-0140) was created
+ as a generic platform to test different FPGA designs, and has
+ pluggable CPU modules, see ARM DUI 0303E.
+ items:
+ - const: arm,realview-eb
+ - description: ARM RealView Platform Baseboard for ARM1176JZF-S
+ (HBI-0147) was created as a development board to test ARM TrustZone,
+ CoreSight and Intelligent Energy Management (IEM) see ARM DUI 0425F.
+ items:
+ - const: arm,realview-pb1176
+ - description: ARM RealView Platform Baseboard for ARM 11 MPCore
+ (HBI-0159, HBI-0175 and HBI-0176) was created to showcase
+ multiprocessing with ARM11 using MPCore using symmetric
+ multiprocessing (SMP). See ARM DUI 0351E.
+ items:
+ - const: arm,realview-pb11mp
+ - description: ARM RealView Platform Baseboard for Cortex-A8 (HBI-0178,
+ HBI-0176 and HBI-0175) was the first reference platform for the
+ Cortex CPU family, including a Cortex-A8 test chip.
+ items:
+ - const: arm,realview-pba8
+ - description: ARM RealView Platform Baseboard Explore for Cortex-A9
+ (HBI-0182 and HBI-0183) was the reference platform for the Cortex-A9
+ CPU.
+ items:
+ - const: arm,realview-pbx
+
+ soc:
+ description: All RealView boards must provide a soc node in the root of the
+ device tree, representing the System-on-Chip since these test chips are
+ rather complex.
+ type: object
+ properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: arm,realview-eb-soc
+ - const: simple-bus
+ - items:
+ - const: arm,realview-pb1176-soc
+ - const: simple-bus
+ - items:
+ - const: arm,realview-pb11mp-soc
+ - const: simple-bus
+ - items:
+ - const: arm,realview-pba8-soc
+ - const: simple-bus
+ - items:
+ - const: arm,realview-pbx-soc
+ - const: simple-bus
+
+ patternProperties:
+ "^.*syscon@[0-9a-f]+$":
+ type: object
+ description: All RealView boards must provide a syscon system controller
+ node inside the soc node.
+ properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: arm,realview-eb11mp-revb-syscon
+ - const: arm,realview-eb-syscon
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - const: arm,realview-eb11mp-revc-syscon
+ - const: arm,realview-eb-syscon
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - const: arm,realview-eb-syscon
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - const: arm,realview-pb1176-syscon
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - const: arm,realview-pb11mp-syscon
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - const: arm,realview-pba8-syscon
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - const: arm,realview-pbx-syscon
+ - const: syscon
+ - const: simple-mfd
+
+ required:
+ - compatible
+ - reg
+
+ required:
+ - compatible
+
+required:
+ - compatible
+ - soc
+
+...
diff --git a/dts/Bindings/arm/arm,versatile.yaml b/dts/Bindings/arm/arm,versatile.yaml
new file mode 100644
index 0000000..06efd2a
--- /dev/null
+++ b/dts/Bindings/arm/arm,versatile.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,versatile.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Versatile Boards Device Tree Bindings
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |+
+ The ARM Versatile boards are two variants of ARM926EJ-S evaluation boards
+ with various pluggable interface boards, in essence the Versatile PB version
+ is a superset of the Versatile AB version.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: The ARM Versatile Application Baseboard (HBI-0118) is an
+ evaluation board specifically for the ARM926EJ-S. It can be connected
+ to an IB1 interface board for a touchscreen-type use case or an IB2
+ for a candybar phone-type use case. See ARM DUI 0225D.
+ items:
+ - const: arm,versatile-ab
+ - description: The ARM Versatile Platform Baseboard (HBI-0117) is an
+ extension of the Versatile Application Baseboard that includes a
+ PCI host controller. Like the sibling board, it is done specifically
+ for ARM926EJ-S. See ARM DUI 0224B.
+ items:
+ - const: arm,versatile-pb
+
+ core-module@10000000:
+ type: object
+ description: the root node in the Versatile platforms must contain
+ a core module child node. They are always at physical address
+ 0x10000000 in all the Versatile variants.
+ properties:
+ compatible:
+ items:
+ - const: arm,core-module-versatile
+ - const: syscon
+ - const: simple-mfd
+ reg:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+
+patternProperties:
+ "^syscon@[0-9a-f]+$":
+ type: object
+ description: When fitted with the IB2 Interface Board, the Versatile
+ AB will present an optional system controller node which controls the
+ extra peripherals on the interface board.
+ properties:
+ compatible:
+ contains:
+ const: arm,versatile-ib2-syscon
+ required:
+ - compatible
+ - reg
+
+required:
+ - compatible
+ - core-module@10000000
+
+...
diff --git a/dts/Bindings/arm/arm,vexpress-juno.yaml b/dts/Bindings/arm/arm,vexpress-juno.yaml
new file mode 100644
index 0000000..8c06a73
--- /dev/null
+++ b/dts/Bindings/arm/arm,vexpress-juno.yaml
@@ -0,0 +1,223 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Versatile Express and Juno Boards Device Tree Bindings
+
+maintainers:
+ - Sudeep Holla <sudeep.holla@arm.com>
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |+
+ ARM's Versatile Express platform were built as reference designs for exploring
+ multicore Cortex-A class systems. The Versatile Express family contains both
+ 32 bit (Aarch32) and 64 bit (Aarch64) systems.
+
+ The board consist of a motherboard and one or more daughterboards (tiles). The
+ motherboard provides a set of peripherals. Processor and RAM "live" on the
+ tiles.
+
+ The motherboard and each core tile should be described by a separate Device
+ Tree source file, with the tile's description including the motherboard file
+ using an include directive. As the motherboard can be initialized in one of
+ two different configurations ("memory maps"), care must be taken to include
+ the correct one.
+
+ When a new generation of boards were introduced under the name "Juno", these
+ shared to many common characteristics with the Versatile Express that the
+ "arm,vexpress" compatible was retained in the root node, and these are
+ included in this binding schema as well.
+
+ The root node indicates the CPU SoC on the core tile, and this
+ is a daughterboard to the main motherboard. The name used in the compatible
+ string shall match the name given in the core tile's technical reference
+ manual, followed by "arm,vexpress" as an additional compatible value. If
+ further subvariants are released of the core tile, even more fine-granular
+ compatible strings with up to three compatible strings are used.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
+ in MPCore configuration in a test chip on the core tile. See ARM
+ DUI 0448I. This was the first Versatile Express platform.
+ items:
+ - const: arm,vexpress,v2p-ca9
+ - const: arm,vexpress
+ - description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
+ in a test chip on the core tile. It is intended to evaluate NEON, FPU
+ and Jazelle support in the Cortex A5 family. See ARM DUI 0541C.
+ items:
+ - const: arm,vexpress,v2p-ca5s
+ - const: arm,vexpress
+ - description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU
+ cores in a MPCore configuration in a test chip on the core tile. See
+ ARM DUI 0604F.
+ items:
+ - const: arm,vexpress,v2p-ca15
+ - const: arm,vexpress
+ - description: CoreTile Express A15x4 (V2P-CA15, HBI-0237A) has 4 Cortex
+ A15 CPU cores in a test chip on the core tile. This is the first test
+ chip called "TC1".
+ items:
+ - const: arm,vexpress,v2p-ca15,tc1
+ - const: arm,vexpress,v2p-ca15
+ - const: arm,vexpress
+ - description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15
+ CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
+ in a test chip on the core tile. See ARM DDI 0503I.
+ items:
+ - const: arm,vexpress,v2p-ca15_a7
+ - const: arm,vexpress
+ - description: LogicTile Express 20MG (V2F-1XV7) has 2 Cortex A53 CPU
+ cores in a test chip on the core tile. See ARM DDI 0498D.
+ items:
+ - const: arm,vexpress,v2f-1xv7,ca53x2
+ - const: arm,vexpress,v2f-1xv7
+ - const: arm,vexpress
+ - description: Arm Versatile Express Juno "r0" (the first Juno board,
+ V2M-Juno) was introduced as a vehicle for evaluating big.LITTLE on
+ AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
+ cores in a big.LITTLE configuration. It also features the MALI T624
+ GPU. See ARM document 100113_0000_07_en.
+ items:
+ - const: arm,juno
+ - const: arm,vexpress
+ - description: Arm Versatile Express Juno r1 Development Platform
+ (V2M-Juno r1) was introduced mainly aimed at development of PCIe
+ based systems. Juno r1 also has support for AXI masters placed on
+ the TLX connectors to join the coherency domain. Otherwise it is the
+ same configuration as Juno r0. See ARM document 100122_0100_06_en.
+ items:
+ - const: arm,juno-r1
+ - const: arm,juno
+ - const: arm,vexpress
+ - description: Arm Versatile Express Juno r2 Development Platform
+ (V2M-Juno r2). It has the same feature set as Juno r0 and r1. See
+ ARM document 100114_0200_04_en.
+ items:
+ - const: arm,juno-r2
+ - const: arm,juno
+ - const: arm,vexpress
+ - description: Arm AEMv8a Versatile Express Real-Time System Model
+ (VE RTSM) is a programmers view of the Versatile Express with Arm
+ v8A hardware. See ARM DUI 0575D.
+ items:
+ - const: arm,rtsm_ve,aemv8a
+ - const: arm,vexpress
+ - description: Arm FVP (Fixed Virtual Platform) base model revision C
+ See ARM Document 100964_1190_00_en.
+ items:
+ - const: arm,fvp-base-revc
+ - const: arm,vexpress
+ - description: Arm Foundation model for Aarch64
+ items:
+ - const: arm,foundation-aarch64
+ - const: arm,vexpress
+
+ arm,hbi:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: This indicates the ARM HBI (Hardware Board ID), this is
+ ARM's unique board model ID, visible on the PCB's silkscreen.
+
+ arm,vexpress,site:
+ description: As Versatile Express can be configured in number of physically
+ different setups, the device tree should describe platform topology.
+ For this reason the root node and main motherboard node must define this
+ property, describing the physical location of the children nodes.
+ 0 means motherboard site, while 1 and 2 are daughterboard sites, and
+ 0xf means "sisterboard" which is the site containing the main CPU tile.
+ allOf:
+ - $ref: '/schemas/types.yaml#/definitions/uint32'
+ - minimum: 0
+ maximum: 15
+
+ arm,vexpress,position:
+ description: When daughterboards are stacked on one site, their position
+ in the stack be be described this attribute.
+ allOf:
+ - $ref: '/schemas/types.yaml#/definitions/uint32'
+ - minimum: 0
+ maximum: 3
+
+ arm,vexpress,dcc:
+ description: When describing tiles consisting of more than one DCC, its
+ number can be specified with this attribute.
+ allOf:
+ - $ref: '/schemas/types.yaml#/definitions/uint32'
+ - minimum: 0
+ maximum: 3
+
+patternProperties:
+ "^bus@[0-9a-f]+$":
+ description: Static Memory Bus (SMB) node, if this exists it describes
+ the connection between the motherboard and any tiles. Sometimes the
+ compatible is placed directly under this node, sometimes it is placed
+ in a subnode named "motherboard". Sometimes the compatible includes
+ "arm,vexpress,v2?-p1" sometimes (on software models) is is just
+ "simple-bus". If the compatible is placed in the "motherboard" node,
+ it is stricter and always has two compatibles.
+ type: object
+ allOf:
+ - $ref: '/schemas/simple-bus.yaml'
+
+ properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - arm,vexpress,v2m-p1
+ - arm,vexpress,v2p-p1
+ - const: simple-bus
+ - const: simple-bus
+ motherboard:
+ type: object
+ description: The motherboard description provides a single "motherboard"
+ node using 2 address cells corresponding to the Static Memory Bus
+ used between the motherboard and the tile. The first cell defines the
+ Chip Select (CS) line number, the second cell address offset within
+ the CS. All interrupt lines between the motherboard and the tile
+ are active high and are described using single cell.
+ properties:
+ "#address-cells":
+ const: 2
+ "#size-cells":
+ const: 1
+ compatible:
+ items:
+ - enum:
+ - arm,vexpress,v2m-p1
+ - arm,vexpress,v2p-p1
+ - const: simple-bus
+ arm,v2m-memory-map:
+ description: This describes the memory map type.
+ allOf:
+ - $ref: '/schemas/types.yaml#/definitions/string'
+ - enum:
+ - rs1
+ - rs2
+ required:
+ - compatible
+ required:
+ - compatible
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - arm,vexpress,v2p-ca9
+ - arm,vexpress,v2p-ca5s
+ - arm,vexpress,v2p-ca15
+ - arm,vexpress,v2p-ca15_a7
+ - arm,vexpress,v2f-1xv7,ca53x2
+ then:
+ required:
+ - arm,hbi
+
+...
diff --git a/dts/Bindings/arm/arm-boards b/dts/Bindings/arm/arm-boards
deleted file mode 100644
index 96b1dad..0000000
--- a/dts/Bindings/arm/arm-boards
+++ /dev/null
@@ -1,237 +0,0 @@
-ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform)
------------------------------------------------------------------------------
-ARM's oldest Linux-supported platform with connectors for different core
-tiles of ARMv4, ARMv5 and ARMv6 type.
-
-Required properties (in root node):
- compatible = "arm,integrator-ap"; /* Application Platform */
- compatible = "arm,integrator-cp"; /* Compact Platform */
-
-FPGA type interrupt controllers, see the versatile-fpga-irq binding doc.
-
-Required nodes:
-
-- core-module: the root node to the Integrator platforms must have
- a core-module with regs and the compatible string
- "arm,core-module-integrator"
-- external-bus-interface: the root node to the Integrator platforms
- must have an external bus interface with regs and the
- compatible-string "arm,external-bus-interface"
-
- Required properties for the core module:
- - regs: the location and size of the core module registers, one
- range of 0x200 bytes.
-
-- syscon: the root node of the Integrator platforms must have a
- system controller node pointing to the control registers,
- with the compatible string
- "arm,integrator-ap-syscon"
- "arm,integrator-cp-syscon"
- respectively.
-
- Required properties for the system controller:
- - regs: the location and size of the system controller registers,
- one range of 0x100 bytes.
-
- Required properties for the AP system controller:
- - interrupts: the AP syscon node must include the logical module
- interrupts, stated in order of module instance <module 0>,
- <module 1>, <module 2> ... for the CP system controller this
- is not required not of any use.
-
-/dts-v1/;
-/include/ "integrator.dtsi"
-
-/ {
- model = "ARM Integrator/AP";
- compatible = "arm,integrator-ap";
-
- core-module@10000000 {
- compatible = "arm,core-module-integrator";
- reg = <0x10000000 0x200>;
- };
-
- ebi@12000000 {
- compatible = "arm,external-bus-interface";
- reg = <0x12000000 0x100>;
- };
-
- syscon {
- compatible = "arm,integrator-ap-syscon";
- reg = <0x11000000 0x100>;
- interrupt-parent = <&pic>;
- /* These are the logic module IRQs */
- interrupts = <9>, <10>, <11>, <12>;
- };
-};
-
-
-ARM Versatile Application and Platform Baseboards
--------------------------------------------------
-ARM's development hardware platform with connectors for customizable
-core tiles. The hardware configuration of the Versatile boards is
-highly customizable.
-
-Required properties (in root node):
- compatible = "arm,versatile-ab"; /* Application baseboard */
- compatible = "arm,versatile-pb"; /* Platform baseboard */
-
-Interrupt controllers:
-- VIC required properties:
- compatible = "arm,versatile-vic";
- interrupt-controller;
- #interrupt-cells = <1>;
-
-- SIC required properties:
- compatible = "arm,versatile-sic";
- interrupt-controller;
- #interrupt-cells = <1>;
-
-Required nodes:
-
-- core-module: the root node to the Versatile platforms must have
- a core-module with regs and the compatible strings
- "arm,core-module-versatile", "syscon"
-
-Optional nodes:
-
-- arm,versatile-ib2-syscon : if the Versatile has an IB2 interface
- board mounted, this has a separate system controller that is
- defined in this node.
- Required properties:
- compatible = "arm,versatile-ib2-syscon", "syscon"
-
-ARM RealView Boards
--------------------
-The RealView boards cover tailored evaluation boards that are used to explore
-the ARM11 and Cortex A-8 and Cortex A-9 processors.
-
-Required properties (in root node):
- /* RealView Emulation Baseboard */
- compatible = "arm,realview-eb";
- /* RealView Platform Baseboard for ARM1176JZF-S */
- compatible = "arm,realview-pb1176";
- /* RealView Platform Baseboard for ARM11 MPCore */
- compatible = "arm,realview-pb11mp";
- /* RealView Platform Baseboard for Cortex A-8 */
- compatible = "arm,realview-pba8";
- /* RealView Platform Baseboard Explore for Cortex A-9 */
- compatible = "arm,realview-pbx";
-
-Required nodes:
-
-- soc: some node of the RealView platforms must be the SoC
- node that contain the SoC-specific devices, with the compatible
- string set to one of these tuples:
- "arm,realview-eb-soc", "simple-bus"
- "arm,realview-pb1176-soc", "simple-bus"
- "arm,realview-pb11mp-soc", "simple-bus"
- "arm,realview-pba8-soc", "simple-bus"
- "arm,realview-pbx-soc", "simple-bus"
-
-- syscon: some subnode of the RealView SoC node must be a
- system controller node pointing to the control registers,
- with the compatible string set to one of these:
- "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon"
- "arm,realview-eb11mp-revc-syscon", "arm,realview-eb-syscon", "syscon"
- "arm,realview-eb-syscon", "syscon"
- "arm,realview-pb1176-syscon", "syscon"
- "arm,realview-pb11mp-syscon", "syscon"
- "arm,realview-pba8-syscon", "syscon"
- "arm,realview-pbx-syscon", "syscon"
-
- Required properties for the system controller:
- - regs: the location and size of the system controller registers,
- one range of 0x1000 bytes.
-
-Example:
-
-/dts-v1/;
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- model = "ARM RealView PB1176 with device tree";
- compatible = "arm,realview-pb1176";
- #address-cells = <1>;
- #size-cells = <1>;
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "arm,realview-pb1176-soc", "simple-bus";
- ranges;
-
- syscon: syscon@10000000 {
- compatible = "arm,realview-syscon", "syscon";
- reg = <0x10000000 0x1000>;
- };
-
- };
-};
-
-ARM Versatile Express Boards
------------------------------
-For details on the device tree bindings for ARM Versatile Express boards
-please consult the vexpress.txt file in the same directory as this file.
-
-ARM Juno Boards
-----------------
-The Juno boards are targeting development for AArch64 systems. The first
-iteration, Juno r0, is a vehicle for evaluating big.LITTLE on AArch64,
-with the second iteration, Juno r1, mainly aimed at development of PCIe
-based systems. Juno r1 also has support for AXI masters placed on the TLX
-connectors to join the coherency domain.
-
-Juno boards are described in a similar way to ARM Versatile Express boards,
-with the motherboard part of the hardware being described in a separate file
-to highlight the fact that is part of the support infrastructure for the SoC.
-Juno device tree bindings also share the Versatile Express bindings as
-described under the RS1 memory mapping.
-
-Required properties (in root node):
- compatible = "arm,juno"; /* For Juno r0 board */
- compatible = "arm,juno-r1"; /* For Juno r1 board */
- compatible = "arm,juno-r2"; /* For Juno r2 board */
-
-Required nodes:
-The description for the board must include:
- - a "psci" node describing the boot method used for the secondary CPUs.
- A detailed description of the bindings used for "psci" nodes is present
- in the psci.yaml file.
- - a "cpus" node describing the available cores and their associated
- "enable-method"s. For more details see cpus.yaml file.
-
-Example:
-
-/dts-v1/;
-/ {
- model = "ARM Juno development board (r0)";
- compatible = "arm,juno", "arm,vexpress";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- A57_0: cpu@0 {
- compatible = "arm,cortex-a57";
- reg = <0x0 0x0>;
- device_type = "cpu";
- enable-method = "psci";
- };
-
- .....
-
- A53_0: cpu@100 {
- compatible = "arm,cortex-a53";
- reg = <0x0 0x100>;
- device_type = "cpu";
- enable-method = "psci";
- };
-
- .....
- };
-
-};
diff --git a/dts/Bindings/arm/bcm/brcm,bcm11351-cpu-method.txt b/dts/Bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
deleted file mode 100644
index e3f9969..0000000
--- a/dts/Bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Broadcom Kona Family CPU Enable Method
---------------------------------------
-This binding defines the enable method used for starting secondary
-CPUs in the following Broadcom SoCs:
- BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
-
-The enable method is specified by defining the following required
-properties in the "cpu" device tree node:
- - enable-method = "brcm,bcm11351-cpu-method";
- - secondary-boot-reg = <...>;
-
-The secondary-boot-reg property is a u32 value that specifies the
-physical address of the register used to request the ROM holding pen
-code release a secondary CPU. The value written to the register is
-formed by encoding the target CPU id into the low bits of the
-physical start address it should jump to.
-
-Example:
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <0x3500417c>;
- };
- };
diff --git a/dts/Bindings/arm/bcm/brcm,bcm11351.txt b/dts/Bindings/arm/bcm/brcm,bcm11351.txt
deleted file mode 100644
index 0ff6560..0000000
--- a/dts/Bindings/arm/bcm/brcm,bcm11351.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-Broadcom BCM11351 device tree bindings
--------------------------------------------
-
-Boards with the bcm281xx SoC family (which includes bcm11130, bcm11140,
-bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties:
-
-Required root node property:
-
-compatible = "brcm,bcm11351";
-DEPRECATED: compatible = "bcm,bcm11351";
diff --git a/dts/Bindings/arm/bcm/brcm,bcm11351.yaml b/dts/Bindings/arm/bcm/brcm,bcm11351.yaml
new file mode 100644
index 0000000..b5ef266
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,bcm11351.yaml
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm11351.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM11351 device tree bindings
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ items:
+ - enum:
+ - brcm,bcm28155-ap
+ - const: brcm,bcm11351
+
+...
diff --git a/dts/Bindings/arm/bcm/brcm,bcm21664.txt b/dts/Bindings/arm/bcm/brcm,bcm21664.txt
deleted file mode 100644
index e077425..0000000
--- a/dts/Bindings/arm/bcm/brcm,bcm21664.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Broadcom BCM21664 device tree bindings
---------------------------------------
-
-This document describes the device tree bindings for boards with the BCM21664
-SoC.
-
-Required root node property:
- - compatible: brcm,bcm21664
-
-Example:
- / {
- model = "BCM21664 SoC";
- compatible = "brcm,bcm21664";
- [...]
- }
diff --git a/dts/Bindings/arm/bcm/brcm,bcm21664.yaml b/dts/Bindings/arm/bcm/brcm,bcm21664.yaml
new file mode 100644
index 0000000..aafbd6a
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,bcm21664.yaml
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm21664.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM21664 device tree bindings
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ items:
+ - enum:
+ - brcm,bcm21664-garnet
+ - const: brcm,bcm21664
+
+...
diff --git a/dts/Bindings/arm/bcm/brcm,bcm23550-cpu-method.txt b/dts/Bindings/arm/bcm/brcm,bcm23550-cpu-method.txt
deleted file mode 100644
index a3af54c..0000000
--- a/dts/Bindings/arm/bcm/brcm,bcm23550-cpu-method.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Broadcom Kona Family CPU Enable Method
---------------------------------------
-This binding defines the enable method used for starting secondary
-CPUs in the following Broadcom SoCs:
- BCM23550
-
-The enable method is specified by defining the following required
-properties in the "cpu" device tree node:
- - enable-method = "brcm,bcm23550";
- - secondary-boot-reg = <...>;
-
-The secondary-boot-reg property is a u32 value that specifies the
-physical address of the register used to request the ROM holding pen
-code release a secondary CPU. The value written to the register is
-formed by encoding the target CPU id into the low bits of the
-physical start address it should jump to.
-
-Example:
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- enable-method = "brcm,bcm23550";
- secondary-boot-reg = <0x3500417c>;
- };
- };
diff --git a/dts/Bindings/arm/bcm/brcm,bcm23550.txt b/dts/Bindings/arm/bcm/brcm,bcm23550.txt
deleted file mode 100644
index 080baad..0000000
--- a/dts/Bindings/arm/bcm/brcm,bcm23550.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Broadcom BCM23550 device tree bindings
---------------------------------------
-
-This document describes the device tree bindings for boards with the BCM23550
-SoC.
-
-Required root node property:
- - compatible: brcm,bcm23550
-
-Example:
- / {
- model = "BCM23550 SoC";
- compatible = "brcm,bcm23550";
- [...]
- }
diff --git a/dts/Bindings/arm/bcm/brcm,bcm23550.yaml b/dts/Bindings/arm/bcm/brcm,bcm23550.yaml
new file mode 100644
index 0000000..c4b4efd
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,bcm23550.yaml
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm23550.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM23550 device tree bindings
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ items:
+ - enum:
+ - brcm,bcm23550-sparrow
+ - const: brcm,bcm23550
+
+...
diff --git a/dts/Bindings/arm/bcm/brcm,bcm4708.txt b/dts/Bindings/arm/bcm/brcm,bcm4708.txt
deleted file mode 100644
index 8608a77..0000000
--- a/dts/Bindings/arm/bcm/brcm,bcm4708.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Broadcom BCM4708 device tree bindings
--------------------------------------------
-
-Boards with the BCM4708 SoC shall have the following properties:
-
-Required root node property:
-
-bcm4708
-compatible = "brcm,bcm4708";
-
-bcm4709
-compatible = "brcm,bcm4709";
-
-bcm53012
-compatible = "brcm,bcm53012";
diff --git a/dts/Bindings/arm/bcm/brcm,bcm4708.yaml b/dts/Bindings/arm/bcm/brcm,bcm4708.yaml
new file mode 100644
index 0000000..d48313c
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,bcm4708.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4708.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM4708 device tree bindings
+
+description:
+ Broadcom BCM4708/47081/4709/47094/53012 Wi-Fi/network SoCs based
+ on the iProc architecture (Northstar).
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+ - Hauke Mehrtens <hauke@hauke-m.de>
+ - Rafal Milecki <zajec5@gmail.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: BCM4708 based boards
+ items:
+ - enum:
+ - asus,rt-ac56u
+ - asus,rt-ac68u
+ - buffalo,wzr-1750dhp
+ - linksys,ea6300-v1
+ - linksys,ea6500-v2
+ - luxul,xap-1510v1
+ - luxul,xwc-1000
+ - netgear,r6250v1
+ - netgear,r6300v2
+ - smartrg,sr400ac
+ - brcm,bcm94708
+ - const: brcm,bcm4708
+
+ - description: BCM47081 based boards
+ items:
+ - enum:
+ - asus,rt-n18u
+ - buffalo,wzr-600dhp2
+ - buffalo,wzr-900dhp
+ - luxul,xap-1410v1
+ - luxul,xwr-1200v1
+ - tplink,archer-c5-v2
+ - const: brcm,bcm47081
+ - const: brcm,bcm4708
+
+ - description: BCM4709 based boards
+ items:
+ - enum:
+ - asus,rt-ac87u
+ - buffalo,wxr-1900dhp
+ - linksys,ea9200
+ - netgear,r7000
+ - netgear,r8000
+ - tplink,archer-c9-v1
+ - brcm,bcm94709
+ - const: brcm,bcm4709
+ - const: brcm,bcm4708
+
+ - description: BCM47094 based boards
+ items:
+ - enum:
+ - dlink,dir-885l
+ - linksys,panamera
+ - luxul,abr-4500-v1
+ - luxul,xap-1610-v1
+ - luxul,xbr-4500-v1
+ - luxul,xwc-2000-v1
+ - luxul,xwr-3100v1
+ - luxul,xwr-3150-v1
+ - netgear,r8500
+ - phicomm,k3
+ - const: brcm,bcm47094
+ - const: brcm,bcm4708
+
+ - description: BCM53012 based boards
+ items:
+ - enum:
+ - brcm,bcm953012er
+ - brcm,bcm953012hr
+ - brcm,bcm953012k
+ - const: brcm,brcm53012
+ - const: brcm,bcm4708
+...
diff --git a/dts/Bindings/arm/bcm/brcm,cygnus.txt b/dts/Bindings/arm/bcm/brcm,cygnus.txt
deleted file mode 100644
index 4c77169..0000000
--- a/dts/Bindings/arm/bcm/brcm,cygnus.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-Broadcom Cygnus device tree bindings
-------------------------------------
-
-
-Boards with Cygnus SoCs shall have the following properties:
-
-Required root node property:
-
-BCM11300
-compatible = "brcm,bcm11300", "brcm,cygnus";
-
-BCM11320
-compatible = "brcm,bcm11320", "brcm,cygnus";
-
-BCM11350
-compatible = "brcm,bcm11350", "brcm,cygnus";
-
-BCM11360
-compatible = "brcm,bcm11360", "brcm,cygnus";
-
-BCM58300
-compatible = "brcm,bcm58300", "brcm,cygnus";
-
-BCM58302
-compatible = "brcm,bcm58302", "brcm,cygnus";
-
-BCM58303
-compatible = "brcm,bcm58303", "brcm,cygnus";
-
-BCM58305
-compatible = "brcm,bcm58305", "brcm,cygnus";
diff --git a/dts/Bindings/arm/bcm/brcm,cygnus.yaml b/dts/Bindings/arm/bcm/brcm,cygnus.yaml
new file mode 100644
index 0000000..fe111e7
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,cygnus.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bcm/brcm,cygnus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Cygnus device tree bindings
+
+maintainers:
+ - Ray Jui <rjui@broadcom.com>
+ - Scott Branden <sbranden@broadcom.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ items:
+ - enum:
+ - brcm,bcm11300
+ - brcm,bcm11320
+ - brcm,bcm11350
+ - brcm,bcm11360
+ - brcm,bcm58300
+ - brcm,bcm58302
+ - brcm,bcm58303
+ - brcm,bcm58305
+ - const: brcm,cygnus
+
+...
diff --git a/dts/Bindings/arm/bcm/brcm,hr2.txt b/dts/Bindings/arm/bcm/brcm,hr2.txt
deleted file mode 100644
index a124c7f..0000000
--- a/dts/Bindings/arm/bcm/brcm,hr2.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-Broadcom Hurricane 2 device tree bindings
----------------------------------------
-
-Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs
-are based on Broadcom's iProc SoC architecture and feature a single core Cortex
-A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
-flash and a PCIe attached integrated switching engine.
-
-Boards with Hurricane SoCs shall have the following properties:
-
-Required root node property:
-
-BCM53342
-compatible = "brcm,bcm53342", "brcm,hr2";
diff --git a/dts/Bindings/arm/bcm/brcm,hr2.yaml b/dts/Bindings/arm/bcm/brcm,hr2.yaml
new file mode 100644
index 0000000..1158f49
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,hr2.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bcm/brcm,hr2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Hurricane 2 device tree bindings
+
+description:
+ Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs
+ are based on Broadcom's iProc SoC architecture and feature a single core Cortex
+ A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
+ flash and a PCIe attached integrated switching engine.
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ items:
+ - enum:
+ - ubnt,unifi-switch8
+ - const: brcm,bcm53342
+ - const: brcm,hr2
+
+...
diff --git a/dts/Bindings/arm/bcm/brcm,ns2.txt b/dts/Bindings/arm/bcm/brcm,ns2.txt
deleted file mode 100644
index 35f056f..0000000
--- a/dts/Bindings/arm/bcm/brcm,ns2.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-Broadcom North Star 2 (NS2) device tree bindings
-------------------------------------------------
-
-Boards with NS2 shall have the following properties:
-
-Required root node property:
-
-NS2 SVK board
-compatible = "brcm,ns2-svk", "brcm,ns2";
diff --git a/dts/Bindings/arm/bcm/brcm,ns2.yaml b/dts/Bindings/arm/bcm/brcm,ns2.yaml
new file mode 100644
index 0000000..2451704
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,ns2.yaml
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bcm/brcm,ns2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom North Star 2 (NS2) device tree bindings
+
+maintainers:
+ - Ray Jui <rjui@broadcom.com>
+ - Scott Branden <sbranden@broadcom.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ items:
+ - enum:
+ - brcm,ns2-svk
+ - brcm,ns2-xmc
+ - const: brcm,ns2
+
+...
diff --git a/dts/Bindings/arm/bcm/brcm,nsp-cpu-method.txt b/dts/Bindings/arm/bcm/brcm,nsp-cpu-method.txt
deleted file mode 100644
index 677ef9d..0000000
--- a/dts/Bindings/arm/bcm/brcm,nsp-cpu-method.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-Broadcom Northstar Plus SoC CPU Enable Method
----------------------------------------------
-This binding defines the enable method used for starting secondary
-CPU in the following Broadcom SoCs:
- BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
-
-The enable method is specified by defining the following required
-properties in the corresponding secondary "cpu" device tree node:
- - enable-method = "brcm,bcm-nsp-smp";
- - secondary-boot-reg = <...>;
-
-The secondary-boot-reg property is a u32 value that specifies the
-physical address of the register which should hold the common
-entry point for a secondary CPU. This entry is cpu node specific
-and should be added per cpu. E.g., in case of NSP (BCM58625) which
-is a dual core CPU SoC, this entry should be added to cpu1 node.
-
-
-Example:
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- next-level-cache = <&L2>;
- reg = <0>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- next-level-cache = <&L2>;
- enable-method = "brcm,bcm-nsp-smp";
- secondary-boot-reg = <0xffff042c>;
- reg = <1>;
- };
- };
diff --git a/dts/Bindings/arm/bcm/brcm,nsp.txt b/dts/Bindings/arm/bcm/brcm,nsp.txt
deleted file mode 100644
index eae53e4..0000000
--- a/dts/Bindings/arm/bcm/brcm,nsp.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Broadcom Northstar Plus device tree bindings
---------------------------------------------
-
-Broadcom Northstar Plus family of SoCs are used for switching control
-and management applications as well as residential router/gateway
-applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
-several peripheral interfaces including multiple Gigabit Ethernet PHYs,
-DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
-SATA and several other IO controllers.
-
-Boards with Northstar Plus SoCs shall have the following properties:
-
-Required root node property:
-
-BCM58522
-compatible = "brcm,bcm58522", "brcm,nsp";
-
-BCM58525
-compatible = "brcm,bcm58525", "brcm,nsp";
-
-BCM58535
-compatible = "brcm,bcm58535", "brcm,nsp";
-
-BCM58622
-compatible = "brcm,bcm58622", "brcm,nsp";
-
-BCM58623
-compatible = "brcm,bcm58623", "brcm,nsp";
-
-BCM58625
-compatible = "brcm,bcm58625", "brcm,nsp";
-
-BCM88312
-compatible = "brcm,bcm88312", "brcm,nsp";
diff --git a/dts/Bindings/arm/bcm/brcm,nsp.yaml b/dts/Bindings/arm/bcm/brcm,nsp.yaml
new file mode 100644
index 0000000..fe364ce
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,nsp.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bcm/brcm,nsp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Northstar Plus device tree bindings
+
+description:
+ Broadcom Northstar Plus family of SoCs are used for switching control
+ and management applications as well as residential router/gateway
+ applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
+ several peripheral interfaces including multiple Gigabit Ethernet PHYs,
+ DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
+ SATA and several other IO controllers.
+
+maintainers:
+ - Ray Jui <rjui@broadcom.com>
+ - Scott Branden <sbranden@broadcom.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ items:
+ - enum:
+ - brcm,bcm58522
+ - brcm,bcm58525
+ - brcm,bcm58535
+ - brcm,bcm58622
+ - brcm,bcm58623
+ - brcm,bcm58625
+ - brcm,bcm88312
+ - const: brcm,nsp
+
+...
diff --git a/dts/Bindings/arm/bcm/brcm,stingray.txt b/dts/Bindings/arm/bcm/brcm,stingray.txt
deleted file mode 100644
index 23a0217..0000000
--- a/dts/Bindings/arm/bcm/brcm,stingray.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-Broadcom Stingray device tree bindings
-------------------------------------------------
-
-Boards with Stingray shall have the following properties:
-
-Required root node property:
-
-Stingray Combo SVK board
-compatible = "brcm,bcm958742k", "brcm,stingray";
-
-Stingray SST100 board
-compatible = "brcm,bcm958742t", "brcm,stingray";
diff --git a/dts/Bindings/arm/bcm/brcm,stingray.yaml b/dts/Bindings/arm/bcm/brcm,stingray.yaml
new file mode 100644
index 0000000..4ad2b21
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,stingray.yaml
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bcm/brcm,stingray.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Stingray device tree bindings
+
+maintainers:
+ - Ray Jui <rjui@broadcom.com>
+ - Scott Branden <sbranden@broadcom.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ items:
+ - enum:
+ - brcm,bcm958742k
+ - brcm,bcm958742t
+ - brcm,bcm958802a802x
+ - const: brcm,stingray
+
+...
diff --git a/dts/Bindings/arm/bcm/brcm,vulcan-soc.txt b/dts/Bindings/arm/bcm/brcm,vulcan-soc.txt
deleted file mode 100644
index 223ed34..0000000
--- a/dts/Bindings/arm/bcm/brcm,vulcan-soc.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-Broadcom Vulcan device tree bindings
-------------------------------------
-
-Boards with Broadcom Vulcan shall have the following root property:
-
-Broadcom Vulcan Evaluation Board:
- compatible = "brcm,vulcan-eval", "brcm,vulcan-soc";
-
-Generic Vulcan board:
- compatible = "brcm,vulcan-soc";
diff --git a/dts/Bindings/arm/bcm/brcm,vulcan-soc.yaml b/dts/Bindings/arm/bcm/brcm,vulcan-soc.yaml
new file mode 100644
index 0000000..c5b6f31
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,vulcan-soc.yaml
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bcm/brcm,vulcan-soc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Vulcan device tree bindings
+
+maintainers:
+ - Robert Richter <rrichter@marvell.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ items:
+ - enum:
+ - brcm,vulcan-eval
+ - cavium,thunderx2-cn9900
+ - const: brcm,vulcan-soc
+
+...
diff --git a/dts/Bindings/arm/coresight-cti.yaml b/dts/Bindings/arm/coresight-cti.yaml
new file mode 100644
index 0000000..3db3642
--- /dev/null
+++ b/dts/Bindings/arm/coresight-cti.yaml
@@ -0,0 +1,336 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+# Copyright 2019 Linaro Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Coresight Cross Trigger Interface (CTI) device.
+
+description: |
+ The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
+ to one or more CoreSight components and/or a CPU, with CTIs interconnected in
+ a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
+ The ECT components are not part of the trace generation data path and are thus
+ not part of the CoreSight graph described in the general CoreSight bindings
+ file coresight.txt.
+
+ The CTI component properties define the connections between the individual
+ CTI and the components it is directly connected to, consisting of input and
+ output hardware trigger signals. CTIs can have a maximum number of input and
+ output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
+ number is defined at design time, the maximum of each defined in the DEVID
+ register.
+
+ CTIs are interconnected in a star topology via the CTM, using a number of
+ programmable channels, usually 4, but again implementation defined and
+ described in the DEVID register. The star topology is not required to be
+ described in the bindings as the actual connections are software
+ programmable.
+
+ In general the connections between CTI and components via the trigger signals
+ are implementation defined, except when the CTI is connected to an ARM v8
+ architecture core and optional ETM.
+
+ In this case the ARM v8 architecture defines the required signal connections
+ between CTI and the CPU core and ETM if present. In the case of a v8
+ architecturally connected CTI an additional compatible string is used to
+ indicate this feature (arm,coresight-cti-v8-arch).
+
+ When CTI trigger connection information is unavailable then a minimal driver
+ binding can be declared with no explicit trigger signals. This will result
+ the driver detecting the maximum available triggers and channels from the
+ DEVID register and make them all available for use as a single default
+ connection. Any user / client application will require additional information
+ on the connections between the CTI and other components for correct operation.
+ This information might be found by enabling the Integration Test registers in
+ the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel
+ configuration). These registers may be used to explore the trigger connections
+ between CTI and other CoreSight components.
+
+ Certain triggers between CoreSight devices and the CTI have specific types
+ and usages. These can be defined along with the signal indexes with the
+ constants defined in <dt-bindings/arm/coresight-cti-dt.h>
+
+ For example a CTI connected to a core will usually have a DBGREQ signal. This
+ is defined in the binding as type PE_EDBGREQ. These types will appear in an
+ optional array alongside the signal indexes. Omitting types will default all
+ signals to GEN_IO.
+
+ Note that some hardware trigger signals can be connected to non-CoreSight
+ components (e.g. UART etc) depending on hardware implementation.
+
+maintainers:
+ - Mike Leach <mike.leach@linaro.org>
+
+allOf:
+ - $ref: /schemas/arm/primecell.yaml#
+
+# Need a custom select here or 'arm,primecell' will match on lots of nodes
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - arm,coresight-cti
+ required:
+ - compatible
+
+properties:
+ $nodename:
+ pattern: "^cti(@[0-9a-f]+)$"
+ compatible:
+ oneOf:
+ - items:
+ - const: arm,coresight-cti
+ - const: arm,primecell
+ - items:
+ - const: arm,coresight-cti-v8-arch
+ - const: arm,coresight-cti
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+
+ cpu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Handle to cpu this device is associated with. This must appear in the
+ base cti node if compatible string arm,coresight-cti-v8-arch is used,
+ or may appear in a trig-conns child node when appropriate.
+
+ arm,cti-ctm-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Defines the CTM this CTI is connected to, in large systems with multiple
+ separate CTI/CTM nets. Typically multi-socket systems where the CTM is
+ propagated between sockets.
+
+ arm,cs-dev-assoc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ defines a phandle reference to an associated CoreSight trace device.
+ When the associated trace device is enabled, then the respective CTI
+ will be enabled. Use in a trig-conns node, or in CTI base node when
+ compatible string arm,coresight-cti-v8-arch used. If the associated
+ device has not been registered then the node name will be stored as
+ the connection name for later resolution. If the associated device is
+ not a CoreSight device or not registered then the node name will remain
+ the connection name and automatic enabling will not occur.
+
+ # size cells and address cells required if trig-conns node present.
+ "#size-cells":
+ const: 0
+
+ "#address-cells":
+ const: 1
+
+patternProperties:
+ '^trig-conns@([0-9]+)$':
+ type: object
+ description:
+ A trigger connections child node which describes the trigger signals
+ between this CTI and another hardware device. This device may be a CPU,
+ CoreSight device, any other hardware device or simple external IO lines.
+ The connection may have both input and output triggers, or only one or the
+ other.
+
+ properties:
+ reg:
+ maxItems: 1
+
+ arm,trig-in-sigs:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 32
+ description:
+ List of CTI trigger in signal numbers in use by a trig-conns node.
+
+ arm,trig-in-types:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 32
+ description:
+ List of constants representing the types for the CTI trigger in
+ signals. Types in this array match to the corresponding signal in the
+ arm,trig-in-sigs array. If the -types array is smaller, or omitted
+ completely, then the types will default to GEN_IO.
+
+ arm,trig-out-sigs:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 32
+ description:
+ List of CTI trigger out signal numbers in use by a trig-conns node.
+
+ arm,trig-out-types:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 32
+ description:
+ List of constants representing the types for the CTI trigger out
+ signals. Types in this array match to the corresponding signal
+ in the arm,trig-out-sigs array. If the "-types" array is smaller,
+ or omitted completely, then the types will default to GEN_IO.
+
+ arm,trig-filters:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 32
+ description:
+ List of CTI trigger out signals that will be blocked from becoming
+ active, unless filtering is disabled on the driver.
+
+ arm,trig-conn-name:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/string
+ description:
+ Defines a connection name that will be displayed, if the cpu or
+ arm,cs-dev-assoc properties are not being used in this connection.
+ Principle use for CTI that are connected to non-CoreSight devices, or
+ external IO.
+
+ anyOf:
+ - required:
+ - arm,trig-in-sigs
+ - required:
+ - arm,trig-out-sigs
+ oneOf:
+ - required:
+ - arm,trig-conn-name
+ - required:
+ - cpu
+ - required:
+ - arm,cs-dev-assoc
+ required:
+ - reg
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: arm,coresight-cti-v8-arch
+
+then:
+ required:
+ - cpu
+
+examples:
+ # minimum CTI definition. DEVID register used to set number of triggers.
+ - |
+ cti@20020000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x20020000 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ };
+ # v8 architecturally defined CTI - CPU + ETM connections generated by the
+ # driver according to the v8 architecture specification.
+ - |
+ cti@859000 {
+ compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+ "arm,primecell";
+ reg = <0x859000 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+
+ cpu = <&CPU1>;
+ arm,cs-dev-assoc = <&etm1>;
+ };
+ # Implementation defined CTI - CPU + ETM connections explicitly defined..
+ # Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h
+ # #size-cells and #address-cells are required if trig-conns@ nodes present.
+ - |
+ #include <dt-bindings/arm/coresight-cti-dt.h>
+
+ cti@858000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x858000 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+
+ arm,cti-ctm-id = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ trig-conns@0 {
+ reg = <0>;
+ arm,trig-in-sigs = <4 5 6 7>;
+ arm,trig-in-types = <ETM_EXTOUT
+ ETM_EXTOUT
+ ETM_EXTOUT
+ ETM_EXTOUT>;
+ arm,trig-out-sigs = <4 5 6 7>;
+ arm,trig-out-types = <ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN>;
+ arm,cs-dev-assoc = <&etm0>;
+ };
+
+ trig-conns@1 {
+ reg = <1>;
+ cpu = <&CPU0>;
+ arm,trig-in-sigs = <0 1>;
+ arm,trig-in-types = <PE_DBGTRIGGER
+ PE_PMUIRQ>;
+ arm,trig-out-sigs=<0 1 2 >;
+ arm,trig-out-types = <PE_EDBGREQ
+ PE_DBGRESTART
+ PE_CTIIRQ>;
+
+ arm,trig-filters = <0>;
+ };
+ };
+ # Implementation defined CTI - non CoreSight component connections.
+ - |
+ cti@20110000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0 0x20110000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ trig-conns@0 {
+ reg = <0>;
+ arm,trig-in-sigs=<0>;
+ arm,trig-in-types=<GEN_INTREQ>;
+ arm,trig-out-sigs=<0>;
+ arm,trig-out-types=<GEN_HALTREQ>;
+ arm,trig-conn-name = "sys_profiler";
+ };
+
+ trig-conns@1 {
+ reg = <1>;
+ arm,trig-out-sigs=<2 3>;
+ arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
+ arm,trig-conn-name = "watchdog";
+ };
+
+ trig-conns@2 {
+ reg = <2>;
+ arm,trig-in-sigs=<1 6>;
+ arm,trig-in-types=<GEN_HALTREQ GEN_RESTARTREQ>;
+ arm,trig-conn-name = "g_counter";
+ };
+ };
+
+...
diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt
index d02c42d..846f6da 100644
--- a/dts/Bindings/arm/coresight.txt
+++ b/dts/Bindings/arm/coresight.txt
@@ -45,6 +45,10 @@ its hardware characteristcs.
- Coresight Address Translation Unit (CATU)
"arm,coresight-catu", "arm,primecell";
+ - Coresight Cross Trigger Interface (CTI):
+ "arm,coresight-cti", "arm,primecell";
+ See coresight-cti.yaml for full CTI definitions.
+
* reg: physical base address and length of the register
set(s) of the component.
@@ -72,6 +76,9 @@ its hardware characteristcs.
* reg-names: the only acceptable values are "stm-base" and
"stm-stimulus-base", each corresponding to the areas defined in "reg".
+* Required properties for Coresight Cross Trigger Interface (CTI)
+ See coresight-cti.yaml for full CTI definitions.
+
* Required properties for devices that don't show up on the AMBA bus, such as
non-configurable replicators and non-configurable funnels:
diff --git a/dts/Bindings/arm/cpus.yaml b/dts/Bindings/arm/cpus.yaml
index 0d5b610..a018147 100644
--- a/dts/Bindings/arm/cpus.yaml
+++ b/dts/Bindings/arm/cpus.yaml
@@ -123,11 +123,18 @@ properties:
- arm,cortex-a12
- arm,cortex-a15
- arm,cortex-a17
+ - arm,cortex-a32
+ - arm,cortex-a34
+ - arm,cortex-a35
- arm,cortex-a53
- arm,cortex-a55
- arm,cortex-a57
+ - arm,cortex-a65
- arm,cortex-a72
- arm,cortex-a73
+ - arm,cortex-a75
+ - arm,cortex-a76
+ - arm,cortex-a77
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
@@ -136,6 +143,8 @@ properties:
- arm,cortex-r4
- arm,cortex-r5
- arm,cortex-r7
+ - arm,neoverse-e1
+ - arm,neoverse-n1
- brcm,brahma-b15
- brcm,brahma-b53
- brcm,vulcan
@@ -155,6 +164,8 @@ properties:
- nvidia,tegra194-carmel
- qcom,krait
- qcom,kryo
+ - qcom,kryo260
+ - qcom,kryo280
- qcom,kryo385
- qcom,kryo485
- qcom,scorpion
@@ -201,6 +212,8 @@ properties:
- rockchip,rk3066-smp
- socionext,milbeaut-m10v-smp
- ste,dbx500-smp
+ - ti,am3352
+ - ti,am4372
cpu-release-addr:
$ref: '/schemas/types.yaml#/definitions/uint64'
@@ -287,6 +300,39 @@ properties:
While optional, it is the preferred way to get access to
the cpu-core power-domains.
+ secondary-boot-reg:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: |
+ Required for systems that have an "enable-method" property value of
+ "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
+
+ This includes the following SoCs: |
+ BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
+ BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+ The secondary-boot-reg property is a u32 value that specifies the
+ physical address of the register used to request the ROM holding pen
+ code release a secondary CPU. The value written to the register is
+ formed by encoding the target CPU id into the low bits of the
+ physical start address it should jump to.
+
+if:
+ # If the enable-method property contains one of those values
+ properties:
+ enable-method:
+ contains:
+ enum:
+ - brcm,bcm11351-cpu-method
+ - brcm,bcm23550
+ - brcm,bcm-nsp-smp
+ # and if enable-method is present
+ required:
+ - enable-method
+
+then:
+ required:
+ - secondary-boot-reg
+
required:
- device_type
- reg
diff --git a/dts/Bindings/arm/freescale/fsl,scu.txt b/dts/Bindings/arm/freescale/fsl,scu.txt
index e07735a..623fedf 100644
--- a/dts/Bindings/arm/freescale/fsl,scu.txt
+++ b/dts/Bindings/arm/freescale/fsl,scu.txt
@@ -164,7 +164,18 @@ Required properties:
- compatible: should be:
"fsl,imx8qxp-sc-key"
followed by "fsl,imx-sc-key";
-- linux,keycodes: See Documentation/devicetree/bindings/input/keys.txt
+- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml
+
+Thermal bindings based on SCU Message Protocol
+------------------------------------------------------------
+
+Required properties:
+- compatible: Should be :
+ "fsl,imx8qxp-sc-thermal"
+ followed by "fsl,imx-sc-thermal";
+
+- #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal.txt
+ for a description.
Example (imx8qxp):
-------------
@@ -238,6 +249,11 @@ firmware {
compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
timeout-sec = <60>;
};
+
+ tsens: thermal-sensor {
+ compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
+ #thermal-sensor-cells = <1>;
+ };
};
};
diff --git a/dts/Bindings/arm/fsl.yaml b/dts/Bindings/arm/fsl.yaml
index 0e17e1f..cd3fbe7 100644
--- a/dts/Bindings/arm/fsl.yaml
+++ b/dts/Bindings/arm/fsl.yaml
@@ -119,6 +119,10 @@ properties:
- fsl,imx6q-sabreauto
- fsl,imx6q-sabrelite
- fsl,imx6q-sabresd
+ - technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf
+ - technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit
+ - technexion,imx6q-pico-nymph # TechNexion i.MX6Q Pico-Nymph
+ - technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi
- technologic,imx6q-ts4900
- technologic,imx6q-ts7970
- toradex,apalis_imx6q # Apalis iMX6 Module
@@ -166,6 +170,10 @@ properties:
- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base
- fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
+ - technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf
+ - technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit
+ - technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph
+ - technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi
- technologic,imx6dl-ts4900
- technologic,imx6dl-ts7970
- toradex,colibri_imx6dl # Colibri iMX6 Module
@@ -225,6 +233,9 @@ properties:
- fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
- kontron,imx6ul-n6310-som # Kontron N6310 SOM
- kontron,imx6ul-n6311-som # Kontron N6311 SOM
+ - technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf
+ - technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL Pico-Hobbit
+ - technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi
- const: fsl,imx6ul
- description: Kontron N6310 S Board
@@ -274,6 +285,7 @@ properties:
items:
- enum:
- toradex,colibri-imx7s # Colibri iMX7 Solo Module
+ - toradex,colibri-imx7s-aster # Colibri iMX7 Solo Module on Aster Carrier Board
- toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3
- tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM
- const: fsl,imx7s
@@ -284,8 +296,14 @@ properties:
- fsl,imx7d-sdb # i.MX7 SabreSD Board
- fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
+ - technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf
+ - technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
+ - technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph
+ - technexion,imx7d-pico-pi # TechNexion i.MX7D Pico-Pi
- toradex,colibri-imx7d # Colibri iMX7 Dual Module
+ - toradex,colibri-imx7d-aster # Colibri iMX7 Dual Module on Aster Carrier Board
- toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module
+ - toradex,colibri-imx7d-emmc-aster # Colibri iMX7 Dual 1GB (eMMC) Module on Aster Carrier Board
- toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on Colibri Evaluation Board V3
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on Colibri Evaluation Board V3
- tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM
@@ -324,6 +342,12 @@ properties:
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
- const: fsl,imx8mn
+ - description: i.MX8MP based Boards
+ items:
+ - enum:
+ - fsl,imx8mp-evk # i.MX8MP EVK Board
+ - const: fsl,imx8mp
+
- description: i.MX8MQ based Boards
items:
- enum:
@@ -395,6 +419,51 @@ properties:
- fsl,ls1021a-twr
- const: fsl,ls1021a
+ - description: LS1028A based Boards
+ items:
+ - enum:
+ - fsl,ls1028a-qds
+ - fsl,ls1028a-rdb
+ - const: fsl,ls1028a
+
+ - description: Kontron KBox A-230-LS
+ items:
+ - const: kontron,kbox-a-230-ls
+ - const: kontron,sl28-var4
+ - const: kontron,sl28
+ - const: fsl,ls1028a
+ - description:
+ Kontron SMARC-sAL28 board on the SMARC Eval Carrier 2.0
+ items:
+ - enum:
+ - kontron,sl28-var2-ads2
+ - kontron,sl28-var3-ads2
+ - kontron,sl28-var4-ads2
+ - enum:
+ - kontron,sl28-var2
+ - kontron,sl28-var3
+ - kontron,sl28-var4
+ - const: kontron,sl28
+ - const: fsl,ls1028a
+
+ - description:
+ Kontron SMARC-sAL28 board (on a generic/undefined carrier)
+ items:
+ - enum:
+ - kontron,sl28-var2
+ - kontron,sl28-var3
+ - kontron,sl28-var4
+ - const: kontron,sl28
+ - const: fsl,ls1028a
+
+ - description:
+ Kontron SMARC-sAL28 board (base). This is used in the base device
+ tree which is compatible with the overlays provided by the
+ vendor.
+ items:
+ - const: kontron,sl28
+ - const: fsl,ls1028a
+
- description: LS1043A based Boards
items:
- enum:
diff --git a/dts/Bindings/arm/l2c2x0.yaml b/dts/Bindings/arm/l2c2x0.yaml
index 913a8cd..5d1d50e 100644
--- a/dts/Bindings/arm/l2c2x0.yaml
+++ b/dts/Bindings/arm/l2c2x0.yaml
@@ -29,27 +29,30 @@ allOf:
properties:
compatible:
- enum:
- - arm,pl310-cache
- - arm,l220-cache
- - arm,l210-cache
- # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
- - bcm,bcm11351-a2-pl310-cache
- # For Broadcom bcm11351 chipset where an
- # offset needs to be added to the address before passing down to the L2
- # cache controller
- - brcm,bcm11351-a2-pl310-cache
- # Marvell Controller designed to be
- # compatible with the ARM one, with system cache mode (meaning
- # maintenance operations on L1 are broadcasted to the L2 and L2
- # performs the same operation).
- - marvell,aurora-system-cache
- # Marvell Controller designed to be
- # compatible with the ARM one with outer cache mode.
- - marvell,aurora-outer-cache
- # Marvell Tauros3 cache controller, compatible
- # with arm,pl310-cache controller.
- - marvell,tauros3-cache
+ oneOf:
+ - enum:
+ - arm,pl310-cache
+ - arm,l220-cache
+ - arm,l210-cache
+ # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+ - bcm,bcm11351-a2-pl310-cache
+ # For Broadcom bcm11351 chipset where an
+ # offset needs to be added to the address before passing down to the L2
+ # cache controller
+ - brcm,bcm11351-a2-pl310-cache
+ # Marvell Controller designed to be
+ # compatible with the ARM one, with system cache mode (meaning
+ # maintenance operations on L1 are broadcasted to the L2 and L2
+ # performs the same operation).
+ - marvell,aurora-system-cache
+ # Marvell Controller designed to be
+ # compatible with the ARM one with outer cache mode.
+ - marvell,aurora-outer-cache
+ - items:
+ # Marvell Tauros3 cache controller, compatible
+ # with arm,pl310-cache controller.
+ - const: marvell,tauros3-cache
+ - const: arm,pl310-cache
cache-level:
const: 2
diff --git a/dts/Bindings/arm/mrvl/mrvl.yaml b/dts/Bindings/arm/mrvl/mrvl.yaml
index 818dfe6..3235ec9 100644
--- a/dts/Bindings/arm/mrvl/mrvl.yaml
+++ b/dts/Bindings/arm/mrvl/mrvl.yaml
@@ -28,8 +28,11 @@ properties:
items:
- enum:
- mrvl,mmp2-brownstone
+ - olpc,xo-1.75
- const: mrvl,mmp2
- description: MMP3 based boards
items:
- - const: mrvl,mmp3
+ - enum:
+ - dell,wyse-ariel
+ - const: marvell,mmp3
...
diff --git a/dts/Bindings/arm/msm/qcom,llcc.yaml b/dts/Bindings/arm/msm/qcom,llcc.yaml
index 79902f4..c3a8604 100644
--- a/dts/Bindings/arm/msm/qcom,llcc.yaml
+++ b/dts/Bindings/arm/msm/qcom,llcc.yaml
@@ -43,6 +43,8 @@ required:
- reg-names
- interrupts
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/Bindings/arm/pmu.yaml b/dts/Bindings/arm/pmu.yaml
index 52ae094..97df36d 100644
--- a/dts/Bindings/arm/pmu.yaml
+++ b/dts/Bindings/arm/pmu.yaml
@@ -20,27 +20,36 @@ properties:
items:
- enum:
- apm,potenza-pmu
- - arm,armv8-pmuv3
- - arm,cortex-a73-pmu
- - arm,cortex-a72-pmu
- - arm,cortex-a57-pmu
- - arm,cortex-a53-pmu
- - arm,cortex-a35-pmu
- - arm,cortex-a17-pmu
- - arm,cortex-a15-pmu
- - arm,cortex-a12-pmu
- - arm,cortex-a9-pmu
- - arm,cortex-a8-pmu
- - arm,cortex-a7-pmu
- - arm,cortex-a5-pmu
- - arm,arm11mpcore-pmu
- - arm,arm1176-pmu
+ - arm,armv8-pmuv3 # Only for s/w models
- arm,arm1136-pmu
+ - arm,arm1176-pmu
+ - arm,arm11mpcore-pmu
+ - arm,cortex-a5-pmu
+ - arm,cortex-a7-pmu
+ - arm,cortex-a8-pmu
+ - arm,cortex-a9-pmu
+ - arm,cortex-a12-pmu
+ - arm,cortex-a15-pmu
+ - arm,cortex-a17-pmu
+ - arm,cortex-a32-pmu
+ - arm,cortex-a34-pmu
+ - arm,cortex-a35-pmu
+ - arm,cortex-a53-pmu
+ - arm,cortex-a55-pmu
+ - arm,cortex-a57-pmu
+ - arm,cortex-a65-pmu
+ - arm,cortex-a72-pmu
+ - arm,cortex-a73-pmu
+ - arm,cortex-a75-pmu
+ - arm,cortex-a76-pmu
+ - arm,cortex-a77-pmu
+ - arm,neoverse-e1-pmu
+ - arm,neoverse-n1-pmu
- brcm,vulcan-pmu
- cavium,thunder-pmu
+ - qcom,krait-pmu
- qcom,scorpion-pmu
- qcom,scorpion-mp-pmu
- - qcom,krait-pmu
interrupts:
# Don't know how many CPUs, so no constraints to specify
diff --git a/dts/Bindings/arm/psci.yaml b/dts/Bindings/arm/psci.yaml
index 5e66934..9247b58 100644
--- a/dts/Bindings/arm/psci.yaml
+++ b/dts/Bindings/arm/psci.yaml
@@ -32,6 +32,9 @@ description: |+
http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
properties:
+ $nodename:
+ const: psci
+
compatible:
oneOf:
- description:
@@ -141,6 +144,8 @@ allOf:
- cpu_off
- cpu_on
+additionalProperties: false
+
examples:
- |+
diff --git a/dts/Bindings/arm/qcom.yaml b/dts/Bindings/arm/qcom.yaml
index 5976c0b..64ddae3 100644
--- a/dts/Bindings/arm/qcom.yaml
+++ b/dts/Bindings/arm/qcom.yaml
@@ -28,6 +28,7 @@ description: |
apq8074
apq8084
apq8096
+ ipq6018
ipq8074
mdm9615
msm8916
@@ -41,6 +42,7 @@ description: |
The 'board' element must be one of the following strings:
cdp
+ cp01-c1
dragonboard
hk01
idp
@@ -150,4 +152,10 @@ properties:
- enum:
- qcom,sc7180-idp
- const: qcom,sc7180
+
+ - items:
+ - enum:
+ - qcom,ipq6018-cp01-c1
+ - const: qcom,ipq6018
+
...
diff --git a/dts/Bindings/arm/renesas,prr.yaml b/dts/Bindings/arm/renesas,prr.yaml
index 7f8d17f..dd08764 100644
--- a/dts/Bindings/arm/renesas,prr.yaml
+++ b/dts/Bindings/arm/renesas,prr.yaml
@@ -27,6 +27,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
prr: chipid@ff000044 {
diff --git a/dts/Bindings/arm/renesas.yaml b/dts/Bindings/arm/renesas.yaml
index 9436124..611094d 100644
--- a/dts/Bindings/arm/renesas.yaml
+++ b/dts/Bindings/arm/renesas.yaml
@@ -208,6 +208,7 @@ properties:
- description: R-Car M3-W+ (R8A77961)
items:
- enum:
+ - renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro, RTP8J77961ASKB0SK0SA05A (M3 ES3.0))
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012SA5A)
- const: renesas,r8a77961
diff --git a/dts/Bindings/arm/rockchip.yaml b/dts/Bindings/arm/rockchip.yaml
index 874b0ea..715586d 100644
--- a/dts/Bindings/arm/rockchip.yaml
+++ b/dts/Bindings/arm/rockchip.yaml
@@ -402,6 +402,11 @@ properties:
- const: phytec,rk3288-phycore-som
- const: rockchip,rk3288
+ - description: Pine64 PinebookPro
+ items:
+ - const: pine64,pinebook-pro
+ - const: rockchip,rk3399
+
- description: Pine64 Rock64
items:
- const: pine64,rock64
@@ -443,7 +448,7 @@ properties:
- description: Rockchip Kylin
items:
- - const: rockchip,kylin-rk3036
+ - const: rockchip,rk3036-kylin
- const: rockchip,rk3036
- description: Rockchip PX3 Evaluation board
@@ -468,6 +473,11 @@ properties:
- const: rockchip,r88
- const: rockchip,rk3368
+ - description: Rockchip RK3036 Evaluation board
+ items:
+ - const: rockchip,rk3036-evb
+ - const: rockchip,rk3036
+
- description: Rockchip RK3228 Evaluation board
items:
- const: rockchip,rk3228-evb
diff --git a/dts/Bindings/arm/samsung/exynos-chipid.yaml b/dts/Bindings/arm/samsung/exynos-chipid.yaml
index afcd708..0425d33 100644
--- a/dts/Bindings/arm/samsung/exynos-chipid.yaml
+++ b/dts/Bindings/arm/samsung/exynos-chipid.yaml
@@ -30,6 +30,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
chipid@10000000 {
diff --git a/dts/Bindings/arm/samsung/pmu.yaml b/dts/Bindings/arm/samsung/pmu.yaml
index 73b56fc..c965189 100644
--- a/dts/Bindings/arm/samsung/pmu.yaml
+++ b/dts/Bindings/arm/samsung/pmu.yaml
@@ -89,6 +89,8 @@ required:
- clock-names
- clocks
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/exynos5250.h>
diff --git a/dts/Bindings/arm/samsung/samsung-secure-firmware.yaml b/dts/Bindings/arm/samsung/samsung-secure-firmware.yaml
index 51d23b6..3d9abad 100644
--- a/dts/Bindings/arm/samsung/samsung-secure-firmware.yaml
+++ b/dts/Bindings/arm/samsung/samsung-secure-firmware.yaml
@@ -23,6 +23,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
firmware@203f000 {
diff --git a/dts/Bindings/arm/socionext/cache-uniphier.txt b/dts/Bindings/arm/socionext/cache-uniphier.txt
deleted file mode 100644
index d27a646..0000000
--- a/dts/Bindings/arm/socionext/cache-uniphier.txt
+++ /dev/null
@@ -1,60 +0,0 @@
-UniPhier outer cache controller
-
-UniPhier SoCs are integrated with a full-custom outer cache controller system.
-All of them have a level 2 cache controller, and some have a level 3 cache
-controller as well.
-
-Required properties:
-- compatible: should be "socionext,uniphier-system-cache"
-- reg: offsets and lengths of the register sets for the device. It should
- contain 3 regions: control register, revision register, operation register,
- in this order.
-- cache-unified: specifies the cache is a unified cache.
-- cache-size: specifies the size in bytes of the cache
-- cache-sets: specifies the number of associativity sets of the cache
-- cache-line-size: specifies the line size in bytes
-- cache-level: specifies the level in the cache hierarchy. The value should
- be 2 for L2 cache, 3 for L3 cache, etc.
-
-Optional properties:
-- next-level-cache: phandle to the next level cache if present. The next level
- cache should be also compatible with "socionext,uniphier-system-cache".
-
-The L2 cache must exist to use the L3 cache; the cache hierarchy must be
-indicated correctly with "next-level-cache" properties.
-
-Example 1 (system with L2):
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
- <0x506c0000 0x400>;
- cache-unified;
- cache-size = <0x80000>;
- cache-sets = <256>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
-Example 2 (system with L2 and L3):
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
- <0x506c0000 0x400>;
- cache-unified;
- cache-size = <0x200000>;
- cache-sets = <512>;
- cache-line-size = <128>;
- cache-level = <2>;
- next-level-cache = <&l3>;
- };
-
- l3: l3-cache@500c8000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
- <0x506c8000 0x400>;
- cache-unified;
- cache-size = <0x400000>;
- cache-sets = <512>;
- cache-line-size = <256>;
- cache-level = <3>;
- };
diff --git a/dts/Bindings/arm/socionext/socionext,uniphier-system-cache.yaml b/dts/Bindings/arm/socionext/socionext,uniphier-system-cache.yaml
new file mode 100644
index 0000000..2e765bb
--- /dev/null
+++ b/dts/Bindings/arm/socionext/socionext,uniphier-system-cache.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier outer cache controller
+
+description: |
+ UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
+ controller system. All of them have a level 2 cache controller, and some
+ have a level 3 cache controller as well.
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ compatible:
+ const: socionext,uniphier-system-cache
+
+ reg:
+ description: |
+ should contain 3 regions: control register, revision register,
+ operation register, in this order.
+ minItems: 3
+ maxItems: 3
+
+ interrupts:
+ description: |
+ Interrupts can be used to notify the completion of cache operations.
+ The number of interrupts should match to the number of CPU cores.
+ The specified interrupts correspond to CPU0, CPU1, ... in this order.
+ minItems: 1
+ maxItems: 4
+
+ cache-unified: true
+
+ cache-size: true
+
+ cache-sets: true
+
+ cache-line-size: true
+
+ cache-level:
+ minimum: 2
+ maximum: 3
+
+ next-level-cache: true
+
+allOf:
+ - $ref: /schemas/cache-controller.yaml#
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - cache-unified
+ - cache-size
+ - cache-sets
+ - cache-line-size
+ - cache-level
+
+examples:
+ - |
+ // System with L2.
+ cache-controller@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <0x140000>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+ - |
+ // System with L2 and L3.
+ // L2 should specify the next level cache by 'next-level-cache'.
+ l2: cache-controller@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
+ interrupts = <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <0x200000>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ next-level-cache = <&l3>;
+ };
+
+ l3: cache-controller@500c8000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <0x200000>;
+ cache-sets = <512>;
+ cache-line-size = <256>;
+ cache-level = <3>;
+ };
diff --git a/dts/Bindings/arm/socionext/uniphier.txt b/dts/Bindings/arm/socionext/uniphier.txt
deleted file mode 100644
index b3ed103..0000000
--- a/dts/Bindings/arm/socionext/uniphier.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-Socionext UniPhier SoC family
------------------------------
-
-Required properties in the root node:
- - compatible: should contain board and SoC compatible strings
-
-SoC and board compatible strings:
- (sorted chronologically)
-
- - LD4 SoC: "socionext,uniphier-ld4"
- - Reference Board: "socionext,uniphier-ld4-ref"
-
- - Pro4 SoC: "socionext,uniphier-pro4"
- - Reference Board: "socionext,uniphier-pro4-ref"
- - Ace Board: "socionext,uniphier-pro4-ace"
- - Sanji Board: "socionext,uniphier-pro4-sanji"
-
- - sLD8 SoC: "socionext,uniphier-sld8"
- - Reference Board: "socionext,uniphier-sld8-ref"
-
- - PXs2 SoC: "socionext,uniphier-pxs2"
- - Gentil Board: "socionext,uniphier-pxs2-gentil"
- - Vodka Board: "socionext,uniphier-pxs2-vodka"
-
- - LD6b SoC: "socionext,uniphier-ld6b"
- - Reference Board: "socionext,uniphier-ld6b-ref"
-
- - LD11 SoC: "socionext,uniphier-ld11"
- - Reference Board: "socionext,uniphier-ld11-ref"
- - Global Board: "socionext,uniphier-ld11-global"
-
- - LD20 SoC: "socionext,uniphier-ld20"
- - Reference Board: "socionext,uniphier-ld20-ref"
- - Global Board: "socionext,uniphier-ld20-global"
-
- - PXs3 SoC: "socionext,uniphier-pxs3"
- - Reference Board: "socionext,uniphier-pxs3-ref"
-
-Example:
-
-/dts-v1/;
-
-/ {
- compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
-
- ...
-};
diff --git a/dts/Bindings/arm/socionext/uniphier.yaml b/dts/Bindings/arm/socionext/uniphier.yaml
new file mode 100644
index 0000000..65ad6d8
--- /dev/null
+++ b/dts/Bindings/arm/socionext/uniphier.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/socionext/uniphier.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier platform device tree bindings
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ $nodename:
+ const: /
+ compatible:
+ oneOf:
+ - description: LD4 SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-ld4-ref
+ - const: socionext,uniphier-ld4
+ - description: Pro4 SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-pro4-ace
+ - socionext,uniphier-pro4-ref
+ - socionext,uniphier-pro4-sanji
+ - const: socionext,uniphier-pro4
+ - description: sLD8 SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-sld8-ref
+ - const: socionext,uniphier-sld8
+ - description: PXs2 SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-pxs2-gentil
+ - socionext,uniphier-pxs2-vodka
+ - const: socionext,uniphier-pxs2
+ - description: LD6b SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-ld6b-ref
+ - const: socionext,uniphier-ld6b
+ - description: LD11 SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-ld11-global
+ - socionext,uniphier-ld11-ref
+ - const: socionext,uniphier-ld11
+ - description: LD20 SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-ld20-global
+ - socionext,uniphier-ld20-ref
+ - const: socionext,uniphier-ld20
+ - description: PXs3 SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-pxs3-ref
+ - const: socionext,uniphier-pxs3
diff --git a/dts/Bindings/arm/stm32/st,stm32-syscon.yaml b/dts/Bindings/arm/stm32/st,stm32-syscon.yaml
index 0dedf94..baff801 100644
--- a/dts/Bindings/arm/stm32/st,stm32-syscon.yaml
+++ b/dts/Bindings/arm/stm32/st,stm32-syscon.yaml
@@ -29,6 +29,8 @@ required:
- reg
- clocks
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/stm32mp1-clks.h>
diff --git a/dts/Bindings/arm/sunxi.yaml b/dts/Bindings/arm/sunxi.yaml
index 327ce67..abf2d97 100644
--- a/dts/Bindings/arm/sunxi.yaml
+++ b/dts/Bindings/arm/sunxi.yaml
@@ -394,6 +394,12 @@ properties:
- const: linksprite,pcduino3-nano
- const: allwinner,sun7i-a20
+ - description: Linutronix Testbox v2
+ items:
+ - const: linutronix,testbox-v2
+ - const: lamobo,lamobo-r1
+ - const: allwinner,sun7i-a20
+
- description: HAOYU Electronics Marsboard A10
items:
- const: haoyu,a10-marsboard
@@ -636,6 +642,21 @@ properties:
- const: pine64,pinebook
- const: allwinner,sun50i-a64
+ - description: Pine64 PinePhone Developer Batch (1.0)
+ items:
+ - const: pine64,pinephone-1.0
+ - const: allwinner,sun50i-a64
+
+ - description: Pine64 PinePhone Braveheart (1.1)
+ items:
+ - const: pine64,pinephone-1.1
+ - const: allwinner,sun50i-a64
+
+ - description: Pine64 PineTab
+ items:
+ - const: pine64,pinetab
+ - const: allwinner,sun50i-a64
+
- description: Pine64 SoPine Baseboard
items:
- const: pine64,sopine-baseboard
@@ -647,6 +668,11 @@ properties:
- const: pineriver,mini-xplus
- const: allwinner,sun4i-a10
+ - description: PocketBook Touch Lux 3
+ items:
+ - const: pocketbook,touch-lux-3
+ - const: allwinner,sun5i-a13
+
- description: Point of View Protab2-IPS9
items:
- const: pov,protab2-ips9
diff --git a/dts/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/dts/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
index 9370e64..aa0738b 100644
--- a/dts/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
+++ b/dts/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
@@ -30,6 +30,7 @@ properties:
enum:
- allwinner,sun5i-a13-mbus
- allwinner,sun8i-h3-mbus
+ - allwinner,sun50i-a64-mbus
reg:
maxItems: 1
diff --git a/dts/Bindings/arm/tegra/nvidia,tegra20-pmc.txt b/dts/Bindings/arm/tegra/nvidia,tegra20-pmc.txt
deleted file mode 100644
index cb12f33..0000000
--- a/dts/Bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ /dev/null
@@ -1,300 +0,0 @@
-NVIDIA Tegra Power Management Controller (PMC)
-
-== Power Management Controller Node ==
-
-The PMC block interacts with an external Power Management Unit. The PMC
-mostly controls the entry and exit of the system from different sleep
-modes. It provides power-gating controllers for SoC and CPU power-islands.
-
-Required properties:
-- name : Should be pmc
-- compatible : Should contain one of the following:
- For Tegra20 must contain "nvidia,tegra20-pmc".
- For Tegra30 must contain "nvidia,tegra30-pmc".
- For Tegra114 must contain "nvidia,tegra114-pmc"
- For Tegra124 must contain "nvidia,tegra124-pmc"
- For Tegra132 must contain "nvidia,tegra124-pmc"
- For Tegra210 must contain "nvidia,tegra210-pmc"
-- reg : Offset and length of the register set for the device
-- clocks : Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names : Must include the following entries:
- "pclk" (The Tegra clock of that name),
- "clk32k_in" (The 32KHz clock input to Tegra).
-
-Optional properties:
-- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
- The PMU is an external Power Management Unit, whose interrupt output
- signal is fed into the PMC. This signal is optionally inverted, and then
- fed into the ARM GIC. The PMC is not involved in the detection or
- handling of this interrupt signal, merely its inversion.
-- nvidia,suspend-mode : The suspend mode that the platform should use.
- Valid values are 0, 1 and 2:
- 0 (LP0): CPU + Core voltage off and DRAM in self-refresh
- 1 (LP1): CPU voltage off and DRAM in self-refresh
- 2 (LP2): CPU voltage off
-- nvidia,core-power-req-active-high : Boolean, core power request active-high
-- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
-- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
-- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
- is enabled.
-
-Required properties when nvidia,suspend-mode is specified:
-- nvidia,cpu-pwr-good-time : CPU power good time in uS.
-- nvidia,cpu-pwr-off-time : CPU power off time in uS.
-- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
- Core power good time in uS.
-- nvidia,core-pwr-off-time : Core power off time in uS.
-
-Required properties when nvidia,suspend-mode=<0>:
-- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
- The LP0 vector contains the warm boot code that is executed by AVP when
- resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
- processor and always being the first boot processor when chip is power on
- or resume from deep sleep mode. When the system is resumed from the deep
- sleep mode, the warm boot code will restore some PLLs, clocks and then
- bring up CPU0 for resuming the system.
-
-Hardware-triggered thermal reset:
-On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,
-hardware-triggered thermal reset will be enabled.
-
-Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
-- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are
- described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the
- Tegra K1 Technical Reference Manual.
-- nvidia,bus-addr : Bus address of the PMU on the I2C bus
-- nvidia,reg-addr : I2C register address to write poweroff command to
-- nvidia,reg-data : Poweroff command to write to PMU
-
-Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
-- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.
- Defaults to 0. Valid values are described in section 12.5.2
- "Pinmux Support" of the Tegra4 Technical Reference Manual.
-
-Optional nodes:
-- powergates : This node contains a hierarchy of power domain nodes, which
- should match the powergates on the Tegra SoC. See "Powergate
- Nodes" below.
-
-Example:
-
-/ SoC dts including file
-pmc@7000f400 {
- compatible = "nvidia,tegra20-pmc";
- reg = <0x7000e400 0x400>;
- clocks = <&tegra_car 110>, <&clk32k_in>;
- clock-names = "pclk", "clk32k_in";
- nvidia,invert-interrupt;
- nvidia,suspend-mode = <1>;
- nvidia,cpu-pwr-good-time = <2000>;
- nvidia,cpu-pwr-off-time = <100>;
- nvidia,core-pwr-good-time = <3845 3845>;
- nvidia,core-pwr-off-time = <458>;
- nvidia,core-power-req-active-high;
- nvidia,sys-clock-req-active-high;
- nvidia,lp0-vec = <0xbdffd000 0x2000>;
-};
-
-/ Tegra board dts file
-{
- ...
- pmc@7000f400 {
- i2c-thermtrip {
- nvidia,i2c-controller-id = <4>;
- nvidia,bus-addr = <0x40>;
- nvidia,reg-addr = <0x36>;
- nvidia,reg-data = <0x2>;
- };
- };
- ...
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock {
- compatible = "fixed-clock";
- reg=<0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
- ...
-};
-
-
-== Powergate Nodes ==
-
-Each of the powergate nodes represents a power-domain on the Tegra SoC
-that can be power-gated by the Tegra PMC. The name of the powergate node
-should be one of the below. Note that not every powergate is applicable
-to all Tegra devices and the following list shows which powergates are
-applicable to which devices. Please refer to the Tegra TRM for more
-details on the various powergates.
-
- Name Description Devices Applicable
- 3d 3D Graphics Tegra20/114/124/210
- 3d0 3D Graphics 0 Tegra30
- 3d1 3D Graphics 1 Tegra30
- aud Audio Tegra210
- dfd Debug Tegra210
- dis Display A Tegra114/124/210
- disb Display B Tegra114/124/210
- heg 2D Graphics Tegra30/114/124/210
- iram Internal RAM Tegra124/210
- mpe MPEG Encode All
- nvdec NVIDIA Video Decode Engine Tegra210
- nvjpg NVIDIA JPEG Engine Tegra210
- pcie PCIE Tegra20/30/124/210
- sata SATA Tegra30/124/210
- sor Display interfaces Tegra124/210
- ve2 Video Encode Engine 2 Tegra210
- venc Video Encode Engine All
- vdec Video Decode Engine Tegra20/30/114/124
- vic Video Imaging Compositor Tegra124/210
- xusba USB Partition A Tegra114/124/210
- xusbb USB Partition B Tegra114/124/210
- xusbc USB Partition C Tegra114/124/210
-
-Required properties:
- - clocks: Must contain an entry for each clock required by the PMC for
- controlling a power-gate. See ../clocks/clock-bindings.txt for details.
- - resets: Must contain an entry for each reset required by the PMC for
- controlling a power-gate. See ../reset/reset.txt for details.
- - #power-domain-cells: Must be 0.
-
-Example:
-
- pmc: pmc@7000e400 {
- compatible = "nvidia,tegra210-pmc";
- reg = <0x0 0x7000e400 0x0 0x400>;
- clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
- clock-names = "pclk", "clk32k_in";
-
- powergates {
- pd_audio: aud {
- clocks = <&tegra_car TEGRA210_CLK_APE>,
- <&tegra_car TEGRA210_CLK_APB2APE>;
- resets = <&tegra_car 198>;
- #power-domain-cells = <0>;
- };
- };
- };
-
-
-== Powergate Clients ==
-
-Hardware blocks belonging to a power domain should contain a "power-domains"
-property that is a phandle pointing to the corresponding powergate node.
-
-Example:
-
- adma: adma@702e2000 {
- ...
- power-domains = <&pd_audio>;
- ...
- };
-
-== Pad Control ==
-
-On Tegra SoCs a pad is a set of pins which are configured as a group.
-The pin grouping is a fixed attribute of the hardware. The PMC can be
-used to set pad power state and signaling voltage. A pad can be either
-in active or power down mode. The support for power state and signaling
-voltage configuration varies depending on the pad in question. 3.3 V and
-1.8 V signaling voltages are supported on pins where software
-controllable signaling voltage switching is available.
-
-The pad configuration state nodes are placed under the pmc node and they
-are referred to by the pinctrl client properties. For more information
-see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
-The pad name should be used as the value of the pins property in pin
-configuration nodes.
-
-The following pads are present on Tegra124 and Tegra132:
-audio bb cam comp
-csia csb cse dsi
-dsib dsic dsid hdmi
-hsic hv lvds mipi-bias
-nand pex-bias pex-clk1 pex-clk2
-pex-cntrl sdmmc1 sdmmc3 sdmmc4
-sys_ddc uart usb0 usb1
-usb2 usb_bias
-
-The following pads are present on Tegra210:
-audio audio-hv cam csia
-csib csic csid csie
-csif dbg debug-nonao dmic
-dp dsi dsib dsic
-dsid emmc emmc2 gpio
-hdmi hsic lvds mipi-bias
-pex-bias pex-clk1 pex-clk2 pex-cntrl
-sdmmc1 sdmmc3 spi spi-hv
-uart usb0 usb1 usb2
-usb3 usb-bias
-
-Required pin configuration properties:
- - pins: Must contain name of the pad(s) to be configured.
-
-Optional pin configuration properties:
- - low-power-enable: Configure the pad into power down mode
- - low-power-disable: Configure the pad into active mode
- - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8
- or TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
- The values are defined in
- include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
-
-Note: The power state can be configured on all of the Tegra124 and
- Tegra132 pads. None of the Tegra124 or Tegra132 pads support
- signaling voltage switching.
-
-Note: All of the listed Tegra210 pads except pex-cntrl support power
- state configuration. Signaling voltage switching is supported on
- following Tegra210 pads: audio, audio-hv, cam, dbg, dmic, gpio,
- pex-cntrl, sdmmc1, sdmmc3, spi, spi-hv, and uart.
-
-Pad configuration state example:
- pmc: pmc@7000e400 {
- compatible = "nvidia,tegra210-pmc";
- reg = <0x0 0x7000e400 0x0 0x400>;
- clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
- clock-names = "pclk", "clk32k_in";
-
- ...
-
- sdmmc1_3v3: sdmmc1-3v3 {
- pins = "sdmmc1";
- power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
- };
-
- sdmmc1_1v8: sdmmc1-1v8 {
- pins = "sdmmc1";
- power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
- };
-
- hdmi_off: hdmi-off {
- pins = "hdmi";
- low-power-enable;
- }
-
- hdmi_on: hdmi-on {
- pins = "hdmi";
- low-power-disable;
- }
- };
-
-Pinctrl client example:
- sdmmc1: sdhci@700b0000 {
- ...
- pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
- pinctrl-0 = <&sdmmc1_3v3>;
- pinctrl-1 = <&sdmmc1_1v8>;
- };
- ...
- sor@54540000 {
- ...
- pinctrl-0 = <&hdmi_off>;
- pinctrl-1 = <&hdmi_on>;
- pinctrl-names = "hdmi-on", "hdmi-off";
- };
diff --git a/dts/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/dts/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
new file mode 100644
index 0000000..f17bb35
--- /dev/null
+++ b/dts/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -0,0 +1,354 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra Power Management Controller (PMC)
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jonathan Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra20-pmc
+ - nvidia,tegra20-pmc
+ - nvidia,tegra30-pmc
+ - nvidia,tegra114-pmc
+ - nvidia,tegra124-pmc
+ - nvidia,tegra210-pmc
+
+ reg:
+ maxItems: 1
+ description:
+ Offset and length of the register set for the device.
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: clk32k_in
+ description:
+ Must includes entries pclk and clk32k_in.
+ pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
+ input to Tegra.
+
+ clocks:
+ maxItems: 2
+ description:
+ Must contain an entry for each entry in clock-names.
+ See ../clocks/clocks-bindings.txt for details.
+
+ '#clock-cells':
+ const: 1
+ description:
+ Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
+ PMC also has blink control which allows 32Khz clock output to
+ Tegra blink pad.
+ Consumer of PMC clock should specify the desired clock by having
+ the clock ID in its "clocks" phandle cell with pmc clock provider.
+ See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
+ clock IDs.
+
+ '#interrupt-cells':
+ const: 2
+ description:
+ Specifies number of cells needed to encode an interrupt source.
+ The value must be 2.
+
+ interrupt-controller: true
+
+ nvidia,invert-interrupt:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Inverts the PMU interrupt signal.
+ The PMU is an external Power Management Unit, whose interrupt output
+ signal is fed into the PMC. This signal is optionally inverted, and
+ then fed into the ARM GIC. The PMC is not involved in the detection
+ or handling of this interrupt signal, merely its inversion.
+
+ nvidia,core-power-req-active-high:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Core power request active-high.
+
+ nvidia,sys-clock-req-active-high:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: System clock request active-high.
+
+ nvidia,combined-power-req:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: combined power request for CPU and Core.
+
+ nvidia,cpu-pwr-good-en:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ CPU power good signal from external PMIC to PMC is enabled.
+
+ nvidia,suspend-mode:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [0, 1, 2]
+ description:
+ The suspend mode that the platform should use.
+ Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
+ Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
+ Mode 2 is for LP2, CPU voltage off
+
+ nvidia,cpu-pwr-good-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: CPU power good time in uSec.
+
+ nvidia,cpu-pwr-off-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: CPU power off time in uSec.
+
+ nvidia,core-pwr-good-time:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ <Oscillator-stable-time Power-stable-time>
+ Core power good time in uSec.
+
+ nvidia,core-pwr-off-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Core power off time in uSec.
+
+ nvidia,lp0-vec:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ <start length> Starting address and length of LP0 vector.
+ The LP0 vector contains the warm boot code that is executed
+ by AVP when resuming from the LP0 state.
+ The AVP (Audio-Video Processor) is an ARM7 processor and
+ always being the first boot processor when chip is power on
+ or resume from deep sleep mode. When the system is resumed
+ from the deep sleep mode, the warm boot code will restore
+ some PLLs, clocks and then brings up CPU0 for resuming the
+ system.
+
+ i2c-thermtrip:
+ type: object
+ description:
+ On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
+ hardware-triggered thermal reset will be enabled.
+
+ properties:
+ nvidia,i2c-controller-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ ID of I2C controller to send poweroff command to PMU.
+ Valid values are described in section 9.2.148
+ "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
+ Manual.
+
+ nvidia,bus-addr:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Bus address of the PMU on the I2C bus.
+
+ nvidia,reg-addr:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: PMU I2C register address to issue poweroff command.
+
+ nvidia,reg-data:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Poweroff command to write to PMU.
+
+ nvidia,pinmux-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Pinmux used by the hardware when issuing Poweroff command.
+ Defaults to 0. Valid values are described in section 12.5.2
+ "Pinmux Support" of the Tegra4 Technical Reference Manual.
+
+ required:
+ - nvidia,i2c-controller-id
+ - nvidia,bus-addr
+ - nvidia,reg-addr
+ - nvidia,reg-data
+
+ additionalProperties: false
+
+ powergates:
+ type: object
+ description: |
+ This node contains a hierarchy of power domain nodes, which should
+ match the powergates on the Tegra SoC. Each powergate node
+ represents a power-domain on the Tegra SoC that can be power-gated
+ by the Tegra PMC.
+ Hardware blocks belonging to a power domain should contain
+ "power-domains" property that is a phandle pointing to corresponding
+ powergate node.
+ The name of the powergate node should be one of the below. Note that
+ not every powergate is applicable to all Tegra devices and the following
+ list shows which powergates are applicable to which devices.
+ Please refer to Tegra TRM for mode details on the powergate nodes to
+ use for each power-gate block inside Tegra.
+ Name Description Devices Applicable
+ 3d 3D Graphics Tegra20/114/124/210
+ 3d0 3D Graphics 0 Tegra30
+ 3d1 3D Graphics 1 Tegra30
+ aud Audio Tegra210
+ dfd Debug Tegra210
+ dis Display A Tegra114/124/210
+ disb Display B Tegra114/124/210
+ heg 2D Graphics Tegra30/114/124/210
+ iram Internal RAM Tegra124/210
+ mpe MPEG Encode All
+ nvdec NVIDIA Video Decode Engine Tegra210
+ nvjpg NVIDIA JPEG Engine Tegra210
+ pcie PCIE Tegra20/30/124/210
+ sata SATA Tegra30/124/210
+ sor Display interfaces Tegra124/210
+ ve2 Video Encode Engine 2 Tegra210
+ venc Video Encode Engine All
+ vdec Video Decode Engine Tegra20/30/114/124
+ vic Video Imaging Compositor Tegra124/210
+ xusba USB Partition A Tegra114/124/210
+ xusbb USB Partition B Tegra114/124/210
+ xusbc USB Partition C Tegra114/124/210
+
+ patternProperties:
+ "^[a-z0-9]+$":
+ type: object
+
+ patternProperties:
+ clocks:
+ minItems: 1
+ maxItems: 8
+ description:
+ Must contain an entry for each clock required by the PMC
+ for controlling a power-gate.
+ See ../clocks/clock-bindings.txt document for more details.
+
+ resets:
+ minItems: 1
+ maxItems: 8
+ description:
+ Must contain an entry for each reset required by the PMC
+ for controlling a power-gate.
+ See ../reset/reset.txt for more details.
+
+ '#power-domain-cells':
+ const: 0
+ description: Must be 0.
+
+ required:
+ - clocks
+ - resets
+ - '#power-domain-cells'
+
+ additionalProperties: false
+
+patternProperties:
+ "^[a-f0-9]+-[a-f0-9]+$":
+ type: object
+ description:
+ This is a Pad configuration node. On Tegra SOCs a pad is a set of
+ pins which are configured as a group. The pin grouping is a fixed
+ attribute of the hardware. The PMC can be used to set pad power state
+ and signaling voltage. A pad can be either in active or power down mode.
+ The support for power state and signaling voltage configuration varies
+ depending on the pad in question. 3.3V and 1.8V signaling voltages
+ are supported on pins where software controllable signaling voltage
+ switching is available.
+
+ The pad configuration state nodes are placed under the pmc node and they
+ are referred to by the pinctrl client properties. For more information
+ see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
+ The pad name should be used as the value of the pins property in pin
+ configuration nodes.
+
+ The following pads are present on Tegra124 and Tegra132
+ audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
+ hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
+ sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
+
+ The following pads are present on Tegra210
+ audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
+ debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
+ hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
+ sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
+
+ properties:
+ pins:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: Must contain name of the pad(s) to be configured.
+
+ low-power-enable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Configure the pad into power down mode.
+
+ low-power-disable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Configure the pad into active mode.
+
+ power-source:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
+ TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
+ The values are defined in
+ include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
+ Power state can be configured on all Tegra124 and Tegra132
+ pads. None of the Tegra124 or Tegra132 pads support signaling
+ voltage switching.
+ All of the listed Tegra210 pads except pex-cntrl support power
+ state configuration. Signaling voltage switching is supported
+ on below Tegra210 pads.
+ audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
+ sdmmc3, spi, spi-hv, and uart.
+
+ required:
+ - pins
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clock-names
+ - clocks
+ - '#clock-cells'
+
+dependencies:
+ "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
+ "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
+ "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
+
+examples:
+ - |
+
+ #include <dt-bindings/clock/tegra210-car.h>
+ #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
+ #include <dt-bindings/soc/tegra-pmc.h>
+
+ tegra_pmc: pmc@7000e400 {
+ compatible = "nvidia,tegra210-pmc";
+ reg = <0x0 0x7000e400 0x0 0x400>;
+ clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
+ clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
+
+ nvidia,invert-interrupt;
+ nvidia,suspend-mode = <0>;
+ nvidia,cpu-pwr-good-time = <0>;
+ nvidia,cpu-pwr-off-time = <0>;
+ nvidia,core-pwr-good-time = <4587 3876>;
+ nvidia,core-pwr-off-time = <39065>;
+ nvidia,core-power-req-active-high;
+ nvidia,sys-clock-req-active-high;
+
+ powergates {
+ pd_audio: aud {
+ clocks = <&tegra_car TEGRA210_CLK_APE>,
+ <&tegra_car TEGRA210_CLK_APB2APE>;
+ resets = <&tegra_car 198>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_xusbss: xusba {
+ clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
+ resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
diff --git a/dts/Bindings/arm/vexpress.txt b/dts/Bindings/arm/vexpress.txt
deleted file mode 100644
index 39844cd..0000000
--- a/dts/Bindings/arm/vexpress.txt
+++ /dev/null
@@ -1,229 +0,0 @@
-ARM Versatile Express boards family
------------------------------------
-
-ARM's Versatile Express platform consists of a motherboard and one
-or more daughterboards (tiles). The motherboard provides a set of
-peripherals. Processor and RAM "live" on the tiles.
-
-The motherboard and each core tile should be described by a separate
-Device Tree source file, with the tile's description including
-the motherboard file using a /include/ directive. As the motherboard
-can be initialized in one of two different configurations ("memory
-maps"), care must be taken to include the correct one.
-
-
-Root node
----------
-
-Required properties in the root node:
-- compatible value:
- compatible = "arm,vexpress,<model>", "arm,vexpress";
- where <model> is the full tile model name (as used in the tile's
- Technical Reference Manual), eg.:
- - for Coretile Express A5x2 (V2P-CA5s):
- compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
- - for Coretile Express A9x4 (V2P-CA9):
- compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
- If a tile comes in several variants or can be used in more then one
- configuration, the compatible value should be:
- compatible = "arm,vexpress,<model>,<variant>", \
- "arm,vexpress,<model>", "arm,vexpress";
- eg:
- - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1:
- compatible = "arm,vexpress,v2p-ca15,tc1", \
- "arm,vexpress,v2p-ca15", "arm,vexpress";
- - LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM:
- compatible = "arm,vexpress,v2f-2xv6,ca7x3", \
- "arm,vexpress,v2f-2xv6", "arm,vexpress";
-
-Optional properties in the root node:
-- tile model name (use name from the tile's Technical Reference
- Manual, eg. "V2P-CA5s")
- model = "<model>";
-- tile's HBI number (unique ARM's board model ID, visible on the
- PCB's silkscreen) in hexadecimal transcription:
- arm,hbi = <0xhbi>
- eg:
- - for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
- arm,hbi = <0x191>;
- - Coretile Express A9x4 (V2P-CA9) HBI-0225:
- arm,hbi = <0x225>;
-
-
-CPU nodes
----------
-
-Top-level standard "cpus" node is required. It must contain a node
-with device_type = "cpu" property for every available core, eg.:
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a5";
- reg = <0>;
- };
- };
-
-
-Configuration infrastructure
-----------------------------
-
-The platform has an elaborated configuration system, consisting of
-microcontrollers residing on the mother- and daughterboards known
-as Motherboard/Daughterboard Configuration Controller (MCC and DCC).
-The controllers are responsible for the platform initialization
-(reset generation, flash programming, FPGA bitfiles loading etc.)
-but also control clock generators, voltage regulators, gather
-environmental data like temperature, power consumption etc. Even
-the video output switch (FPGA) is controlled that way.
-
-The controllers are not mapped into normal memory address space
-and must be accessed through bridges - other devices capable
-of generating transactions on the configuration bus.
-
-The nodes describing configuration controllers must define
-the following properties:
-- compatible value:
- compatible = "arm,vexpress,config-bus";
-- bridge phandle:
- arm,vexpress,config-bridge = <phandle>;
-and children describing available functions.
-
-
-Platform topology
------------------
-
-As Versatile Express can be configured in number of physically
-different setups, the device tree should describe platform topology.
-Root node and main motherboard node must define the following
-property, describing physical location of the children nodes:
-- site number:
- arm,vexpress,site = <number>;
- where 0 means motherboard, 1 or 2 are daugtherboard sites,
- 0xf means "master" site (site containing main CPU tile)
-- when daughterboards are stacked on one site, their position
- in the stack be be described with:
- arm,vexpress,position = <number>;
-- when describing tiles consisting more than one DCC, its number
- can be described with:
- arm,vexpress,dcc = <number>;
-
-Any of the numbers above defaults to zero if not defined in
-the node or any of its parent.
-
-
-Motherboard
------------
-
-The motherboard description file provides a single "motherboard" node
-using 2 address cells corresponding to the Static Memory Bus used
-between the motherboard and the tile. The first cell defines the Chip
-Select (CS) line number, the second cell address offset within the CS.
-All interrupt lines between the motherboard and the tile are active
-high and are described using single cell.
-
-Optional properties of the "motherboard" node:
-- motherboard's memory map variant:
- arm,v2m-memory-map = "<name>";
- where name is one of:
- - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also
- referred to as "ARM Cortex-A Series memory map":
- arm,v2m-memory-map = "rs1";
- When this property is missing, the motherboard is using the original
- memory map (also known as the "Legacy memory map", primarily used
- with the original CoreTile Express A9x4) with peripherals on CS7.
-
-Motherboard .dtsi files provide a set of labelled peripherals that
-can be used to obtain required phandle in the tile's "aliases" node:
-- UARTs, note that the numbers correspond to the physical connectors
- on the motherboard's back panel:
- v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
-- I2C controllers:
- v2m_i2c_dvi and v2m_i2c_pcie
-- SP804 timers:
- v2m_timer01 and v2m_timer23
-
-The tile description should define a "smb" node, describing the
-Static Memory Bus between the tile and motherboard. It must define
-the following properties:
-- "simple-bus" compatible value (to ensure creation of the children)
- compatible = "simple-bus";
-- mapping of the SMB CS/offset addresses into main address space:
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <...>;
-- interrupts mapping:
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 63>;
- interrupt-map = <...>;
-
-
-Example of a VE tile description (simplified)
----------------------------------------------
-
-/dts-v1/;
-
-/ {
- model = "V2P-CA5s";
- arm,hbi = <0x225>;
- arm,vexpress,site = <0xf>;
- compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- chosen { };
-
- aliases {
- serial0 = &v2m_serial0;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a5";
- reg = <0>;
- };
- };
-
- gic: interrupt-controller@2c001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x2c001000 0x1000>,
- <0x2c000100 0x100>;
- };
-
- dcc {
- compatible = "arm,vexpress,config-bus";
- arm,vexpress,config-bridge = <&v2m_sysreg>;
-
- osc@0 {
- compatible = "arm,vexpress-osc";
- };
- };
-
- smb {
- compatible = "simple-bus";
-
- #address-cells = <2>;
- #size-cells = <1>;
- /* CS0 is visible at 0x08000000 */
- ranges = <0 0 0x08000000 0x04000000>;
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 63>;
- /* Active high IRQ 0 is connected to GIC's SPI0 */
- interrupt-map = <0 0 0 &gic 0 0 4>;
-
- /include/ "vexpress-v2m-rs1.dtsi"
- };
-};
-
diff --git a/dts/Bindings/ata/renesas,rcar-sata.yaml b/dts/Bindings/ata/renesas,rcar-sata.yaml
new file mode 100644
index 0000000..7b69831
--- /dev/null
+++ b/dts/Bindings/ata/renesas,rcar-sata.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas R-Car Serial-ATA Interface
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,sata-r8a7779 # R-Car H1
+ - items:
+ - enum:
+ - renesas,sata-r8a7790-es1 # R-Car H2 ES1
+ - renesas,sata-r8a7790 # R-Car H2 other than ES1
+ - renesas,sata-r8a7791 # R-Car M2-W
+ - renesas,sata-r8a7793 # R-Car M2-N
+ - const: renesas,rcar-gen2-sata # generic R-Car Gen2
+ - items:
+ - enum:
+ - renesas,sata-r8a774b1 # RZ/G2N
+ - renesas,sata-r8a7795 # R-Car H3
+ - renesas,sata-r8a77965 # R-Car M3-N
+ - const: renesas,rcar-gen3-sata # generic R-Car Gen3 or RZ/G2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7791-sysc.h>
+
+ sata@ee300000 {
+ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
+ reg = <0xee300000 0x200000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 815>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 815>;
+ };
diff --git a/dts/Bindings/ata/sata_rcar.txt b/dts/Bindings/ata/sata_rcar.txt
deleted file mode 100644
index a2fbdc9..0000000
--- a/dts/Bindings/ata/sata_rcar.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-* Renesas R-Car SATA
-
-Required properties:
-- compatible : should contain one or more of the following:
- - "renesas,sata-r8a774b1" for RZ/G2N
- - "renesas,sata-r8a7779" for R-Car H1
- - "renesas,sata-r8a7790-es1" for R-Car H2 ES1
- - "renesas,sata-r8a7790" for R-Car H2 other than ES1
- - "renesas,sata-r8a7791" for R-Car M2-W
- - "renesas,sata-r8a7793" for R-Car M2-N
- - "renesas,sata-r8a7795" for R-Car H3
- - "renesas,sata-r8a77965" for R-Car M3-N
- - "renesas,rcar-gen2-sata" for a generic R-Car Gen2
- compatible device
- - "renesas,rcar-gen3-sata" for a generic R-Car Gen3 or
- RZ/G2 compatible device
- - "renesas,rcar-sata" is deprecated
-
- When compatible with the generic version nodes
- must list the SoC-specific version corresponding
- to the platform first followed by the generic
- version.
-
-- reg : address and length of the SATA registers;
-- interrupts : must consist of one interrupt specifier.
-- clocks : must contain a reference to the functional clock.
-
-Example:
-
-sata0: sata@ee300000 {
- compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
- reg = <0 0xee300000 0 0x2000>;
- interrupt-parent = <&gic>;
- interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
-};
diff --git a/dts/Bindings/bus/socionext,uniphier-system-bus.yaml b/dts/Bindings/bus/socionext,uniphier-system-bus.yaml
new file mode 100644
index 0000000..c4c9119
--- /dev/null
+++ b/dts/Bindings/bus/socionext,uniphier-system-bus.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier System Bus
+
+description: |
+ The UniPhier System Bus is an external bus that connects on-board devices to
+ the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
+ some control signals. It supports up to 8 banks (chip selects).
+
+ Before any access to the bus, the bus controller must be configured; the bus
+ controller registers provide the control for the translation from the offset
+ within each bank to the CPU-viewed address. The needed setup includes the
+ base address, the size of each bank. Optionally, some timing parameters can
+ be optimized for faster bus access.
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ compatible:
+ const: socionext,uniphier-system-bus
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ description: |
+ The first cell is the bank number (chip select).
+ The second cell is the address offset within the bank.
+ const: 2
+
+ "#size-cells":
+ const: 1
+
+ ranges:
+ description: |
+ Provide address translation from the System Bus to the parent bus.
+
+ Note:
+ The address region(s) that can be assigned for the System Bus is
+ implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
+ 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
+ There might be additional limitations depending on SoCs and the boot mode.
+ The address translation is arbitrary as long as the banks are assigned in
+ the supported address space with the required alignment and they do not
+ overlap one another.
+
+ For example, it is possible to map:
+ bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
+ It is also possible to map:
+ bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
+ There is no reason to stick to a particular translation mapping, but the
+ "ranges" property should provide a "reasonable" default that is known to
+ work. The software should initialize the bus controller according to it.
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+examples:
+ - |
+ // In this example,
+ // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
+ // mapped to 0x43f00000 of the parent bus.
+ // - the UART device is connected at the offset 0x00200000 of CS5 and
+ // mapped to 0x46200000 of the parent bus.
+
+ system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0x00000000 0x42000000 0x02000000>,
+ <5 0x00000000 0x46000000 0x01000000>;
+
+ ethernet@1,01f00000 {
+ compatible = "smsc,lan9115";
+ reg = <1 0x01f00000 0x1000>;
+ interrupts = <0 48 4>;
+ phy-mode = "mii";
+ };
+
+ uart@5,00200000 {
+ compatible = "ns16550a";
+ reg = <5 0x00200000 0x20>;
+ interrupts = <0 49 4>;
+ clock-frequency = <12288000>;
+ };
+ };
diff --git a/dts/Bindings/bus/ti-sysc.txt b/dts/Bindings/bus/ti-sysc.txt
index 233eb82..c984143 100644
--- a/dts/Bindings/bus/ti-sysc.txt
+++ b/dts/Bindings/bus/ti-sysc.txt
@@ -38,6 +38,7 @@ Required standard properties:
"ti,sysc-dra7-mcasp"
"ti,sysc-usb-host-fs"
"ti,sysc-dra7-mcan"
+ "ti,sysc-pruss"
- reg shall have register areas implemented for the interconnect
target module in question such as revision, sysc and syss
diff --git a/dts/Bindings/bus/uniphier-system-bus.txt b/dts/Bindings/bus/uniphier-system-bus.txt
deleted file mode 100644
index 68ef80a..0000000
--- a/dts/Bindings/bus/uniphier-system-bus.txt
+++ /dev/null
@@ -1,66 +0,0 @@
-UniPhier System Bus
-
-The UniPhier System Bus is an external bus that connects on-board devices to
-the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
-some control signals. It supports up to 8 banks (chip selects).
-
-Before any access to the bus, the bus controller must be configured; the bus
-controller registers provide the control for the translation from the offset
-within each bank to the CPU-viewed address. The needed setup includes the base
-address, the size of each bank. Optionally, some timing parameters can be
-optimized for faster bus access.
-
-Required properties:
-- compatible: should be "socionext,uniphier-system-bus".
-- reg: offset and length of the register set for the bus controller device.
-- #address-cells: should be 2. The first cell is the bank number (chip select).
- The second cell is the address offset within the bank.
-- #size-cells: should be 1.
-- ranges: should provide a proper address translation from the System Bus to
- the parent bus.
-
-Note:
-The address region(s) that can be assigned for the System Bus is implementation
-defined. Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff,
-while other SoCs can only use 0x40000000-0x4fffffff. There might be additional
-limitations depending on SoCs and the boot mode. The address translation is
-arbitrary as long as the banks are assigned in the supported address space with
-the required alignment and they do not overlap one another.
-For example, it is possible to map:
- bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
-It is also possible to map:
- bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
-There is no reason to stick to a particular translation mapping, but the
-"ranges" property should provide a "reasonable" default that is known to work.
-The software should initialize the bus controller according to it.
-
-Example:
-
- system-bus {
- compatible = "socionext,uniphier-system-bus";
- reg = <0x58c00000 0x400>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <1 0x00000000 0x42000000 0x02000000
- 5 0x00000000 0x46000000 0x01000000>;
-
- ethernet@1,01f00000 {
- compatible = "smsc,lan9115";
- reg = <1 0x01f00000 0x1000>;
- interrupts = <0 48 4>
- phy-mode = "mii";
- };
-
- uart@5,00200000 {
- compatible = "ns16550a";
- reg = <5 0x00200000 0x20>;
- interrupts = <0 49 4>
- clock-frequency = <12288000>;
- };
- };
-
-In this example,
- - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
- mapped to 0x43f00000 of the parent bus.
- - the UART device is connected at the offset 0x00200000 of CS5 and
- mapped to 0x46200000 of the parent bus.
diff --git a/dts/Bindings/chrome/google,cros-ec-typec.yaml b/dts/Bindings/chrome/google,cros-ec-typec.yaml
new file mode 100644
index 0000000..6d7396a
--- /dev/null
+++ b/dts/Bindings/chrome/google,cros-ec-typec.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Chrome OS EC(Embedded Controller) Type C port driver.
+
+maintainers:
+ - Benson Leung <bleung@chromium.org>
+ - Prashant Malani <pmalani@chromium.org>
+
+description:
+ Chrome OS devices have an Embedded Controller(EC) which has access to
+ Type C port state. This node is intended to allow the host to read and
+ control the Type C ports. The node for this device should be under a
+ cros-ec node like google,cros-ec-spi.
+
+properties:
+ compatible:
+ const: google,cros-ec-typec
+
+ connector:
+ $ref: /schemas/connector/usb-connector.yaml#
+
+required:
+ - compatible
+
+examples:
+ - |+
+ spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cros_ec: ec@0 {
+ compatible = "google,cros-ec-spi";
+ reg = <0>;
+
+ typec {
+ compatible = "google,cros-ec-typec";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "source";
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/clock/arm,syscon-icst.yaml b/dts/Bindings/clock/arm,syscon-icst.yaml
new file mode 100644
index 0000000..de9a465
--- /dev/null
+++ b/dts/Bindings/clock/arm,syscon-icst.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM System Controller ICST Clocks
+
+maintainers:
+ - Linus Walleij <linusw@kernel.org>
+
+description: |
+ The ICS525 and ICS307 oscillators are produced by Integrated
+ Devices Technology (IDT). ARM integrated these oscillators deeply into their
+ reference designs by adding special control registers that manage such
+ oscillators to their system controllers.
+
+ The various ARM system controllers contain logic to serialize and initialize
+ an ICST clock request after a write to the 32 bit register at an offset
+ into the system controller. Furthermore, to even be able to alter one of
+ these frequencies, the system controller must first be unlocked by
+ writing a special token to another offset in the system controller.
+
+ Some ARM hardware contain special versions of the serial interface that only
+ connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to
+ different values and sometimes also hard-wires the output divider. They
+ therefore have special compatible strings as per this table (the OD value is
+ the value on the pins, not the resulting output divider).
+
+ In the core modules and logic tiles, the ICST is a configurable clock fed
+ from a 24 MHz clock on the motherboard (usually the main crystal) used for
+ generating e.g. video clocks. It is located on the core module and there is
+ only one of these. This clock node must be a subnode of the core module.
+
+ Hardware variant RDW OD VDW
+
+ Integrator/AP 22 1 Bit 8 0, rest variable
+ integratorap-cm
+
+ Integrator/AP 46 3 Bit 8 0, rest variable
+ integratorap-sys
+
+ Integrator/AP 22 or 1 17 or (33 or 25 MHz)
+ integratorap-pci 14 1 14
+
+ Integrator/CP 22 variable Bit 8 0, rest variable
+ integratorcp-cm-core
+
+ Integrator/CP 22 variable Bit 8 0, rest variable
+ integratorcp-cm-mem
+
+ The ICST oscillator must be provided inside a system controller node.
+
+properties:
+ "#clock-cells":
+ const: 0
+
+ compatible:
+ enum:
+ - arm,syscon-icst525
+ - arm,syscon-icst307
+ - arm,syscon-icst525-integratorap-cm
+ - arm,syscon-icst525-integratorap-sys
+ - arm,syscon-icst525-integratorap-pci
+ - arm,syscon-icst525-integratorcp-cm-core
+ - arm,syscon-icst525-integratorcp-cm-mem
+ - arm,integrator-cm-auxosc
+ - arm,versatile-cm-auxosc
+ - arm,impd-vco1
+ - arm,impd-vco2
+
+ clocks:
+ description: Parent clock for the ICST VCO
+ maxItems: 1
+
+ clock-output-names:
+ maxItems: 1
+
+ lock-offset:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: Offset to the unlocking register for the oscillator
+
+ vco-offset:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: Offset to the VCO register for the oscillator
+
+required:
+ - "#clock-cells"
+ - compatible
+ - clocks
+
+examples:
+ - |
+ vco1: clock@00 {
+ compatible = "arm,impd1-vco1";
+ #clock-cells = <0>;
+ lock-offset = <0x08>;
+ vco-offset = <0x00>;
+ clocks = <&sysclk>;
+ clock-output-names = "IM-PD1-VCO1";
+ };
+
+...
diff --git a/dts/Bindings/clock/arm-integrator.txt b/dts/Bindings/clock/arm-integrator.txt
deleted file mode 100644
index 11f5f95..0000000
--- a/dts/Bindings/clock/arm-integrator.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Clock bindings for ARM Integrator and Versatile Core Module clocks
-
-Auxiliary Oscillator Clock
-
-This is a configurable clock fed from a 24 MHz chrystal,
-used for generating e.g. video clocks. It is located on the
-core module and there is only one of these.
-
-This clock node *must* be a subnode of the core module, since
-it obtains the base address for it's address range from its
-parent node.
-
-
-Required properties:
-- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc"
-- #clock-cells: must be <0>
-
-Optional properties:
-- clocks: parent clock(s)
-
-Example:
-
-core-module@10000000 {
- xtal24mhz: xtal24mhz@24M {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
- auxosc: cm_aux_osc@25M {
- #clock-cells = <0>;
- compatible = "arm,integrator-cm-auxosc";
- clocks = <&xtal24mhz>;
- };
-};
diff --git a/dts/Bindings/clock/arm-syscon-icst.txt b/dts/Bindings/clock/arm-syscon-icst.txt
deleted file mode 100644
index 4cd8174..0000000
--- a/dts/Bindings/clock/arm-syscon-icst.txt
+++ /dev/null
@@ -1,70 +0,0 @@
-ARM System Controller ICST clocks
-
-The ICS525 and ICS307 oscillators are produced by Integrated Devices
-Technology (IDT). ARM integrated these oscillators deeply into their
-reference designs by adding special control registers that manage such
-oscillators to their system controllers.
-
-The various ARM system controllers contain logic to serialize and initialize
-an ICST clock request after a write to the 32 bit register at an offset
-into the system controller. Furthermore, to even be able to alter one of
-these frequencies, the system controller must first be unlocked by
-writing a special token to another offset in the system controller.
-
-Some ARM hardware contain special versions of the serial interface that only
-connects the low 8 bits of the VDW (missing one bit), hardwires RDW to
-different values and sometimes also hardwire the output divider. They
-therefore have special compatible strings as per this table (the OD value is
-the value on the pins, not the resulting output divider):
-
-Hardware variant: RDW OD VDW
-
-Integrator/AP 22 1 Bit 8 0, rest variable
-integratorap-cm
-
-Integrator/AP 46 3 Bit 8 0, rest variable
-integratorap-sys
-
-Integrator/AP 22 or 1 17 or (33 or 25 MHz)
-integratorap-pci 14 1 14
-
-Integrator/CP 22 variable Bit 8 0, rest variable
-integratorcp-cm-core
-
-Integrator/CP 22 variable Bit 8 0, rest variable
-integratorcp-cm-mem
-
-The ICST oscillator must be provided inside a system controller node.
-
-Required properties:
-- compatible: must be one of
- "arm,syscon-icst525"
- "arm,syscon-icst307"
- "arm,syscon-icst525-integratorap-cm"
- "arm,syscon-icst525-integratorap-sys"
- "arm,syscon-icst525-integratorap-pci"
- "arm,syscon-icst525-integratorcp-cm-core"
- "arm,syscon-icst525-integratorcp-cm-mem"
-- lock-offset: the offset address into the system controller where the
- unlocking register is located
-- vco-offset: the offset address into the system controller where the
- ICST control register is located (even 32 bit address)
-- #clock-cells: must be <0>
-- clocks: parent clock, since the ICST needs a parent clock to derive its
- frequency from, this attribute is compulsory.
-
-Example:
-
-syscon: syscon@10000000 {
- compatible = "syscon";
- reg = <0x10000000 0x1000>;
-
- oscclk0: osc0@c {
- compatible = "arm,syscon-icst307";
- #clock-cells = <0>;
- lock-offset = <0x20>;
- vco-offset = <0x0c>;
- clocks = <&xtal24mhz>;
- };
- (...)
-};
diff --git a/dts/Bindings/clock/clock-bindings.txt b/dts/Bindings/clock/clock-bindings.txt
index b646bbc..8a55fdc 100644
--- a/dts/Bindings/clock/clock-bindings.txt
+++ b/dts/Bindings/clock/clock-bindings.txt
@@ -94,7 +94,7 @@ clock is connected to output 0 of the &ref.
/* external oscillator */
osc: oscillator {
compatible = "fixed-clock";
- #clock-cells = <1>;
+ #clock-cells = <0>;
clock-frequency = <32678>;
clock-output-names = "osc";
};
diff --git a/dts/Bindings/clock/fsl,plldig.yaml b/dts/Bindings/clock/fsl,plldig.yaml
index c835003..a203d5d 100644
--- a/dts/Bindings/clock/fsl,plldig.yaml
+++ b/dts/Bindings/clock/fsl,plldig.yaml
@@ -21,6 +21,9 @@ properties:
reg:
maxItems: 1
+ clocks:
+ maxItems: 1
+
'#clock-cells':
const: 0
@@ -41,6 +44,8 @@ required:
- clocks
- '#clock-cells'
+additionalProperties: false
+
examples:
# Display PIXEL Clock node:
- |
diff --git a/dts/Bindings/clock/imx8mm-clock.txt b/dts/Bindings/clock/imx8mm-clock.txt
deleted file mode 100644
index 8e4ab9e..0000000
--- a/dts/Bindings/clock/imx8mm-clock.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-* Clock bindings for NXP i.MX8M Mini
-
-Required properties:
-- compatible: Should be "fsl,imx8mm-ccm"
-- reg: Address and length of the register set
-- #clock-cells: Should be <1>
-- clocks: list of clock specifiers, must contain an entry for each required
- entry in clock-names
-- clock-names: should include the following entries:
- - "osc_32k"
- - "osc_24m"
- - "clk_ext1"
- - "clk_ext2"
- - "clk_ext3"
- - "clk_ext4"
-
-clk: clock-controller@30380000 {
- compatible = "fsl,imx8mm-ccm";
- reg = <0x0 0x30380000 0x0 0x10000>;
- #clock-cells = <1>;
- clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
- <&clk_ext3>, <&clk_ext4>;
- clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4";
-};
-
-The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h
-for the full list of i.MX8M Mini clock IDs.
diff --git a/dts/Bindings/clock/imx8mm-clock.yaml b/dts/Bindings/clock/imx8mm-clock.yaml
new file mode 100644
index 0000000..ec830db
--- /dev/null
+++ b/dts/Bindings/clock/imx8mm-clock.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx8mm-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8M Mini Clock Control Module Binding
+
+maintainers:
+ - Anson Huang <Anson.Huang@nxp.com>
+
+description: |
+ NXP i.MX8M Mini clock control module is an integrated clock controller, which
+ generates and supplies to all modules.
+
+properties:
+ compatible:
+ const: fsl,imx8mm-ccm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: 32k osc
+ - description: 24m osc
+ - description: ext1 clock input
+ - description: ext2 clock input
+ - description: ext3 clock input
+ - description: ext4 clock input
+
+ clock-names:
+ items:
+ - const: osc_32k
+ - const: osc_24m
+ - const: clk_ext1
+ - const: clk_ext2
+ - const: clk_ext3
+ - const: clk_ext4
+
+ '#clock-cells':
+ const: 1
+ description:
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h
+ for the full list of i.MX8M Mini clock IDs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+examples:
+ # Clock Control Module node:
+ - |
+ clk: clock-controller@30380000 {
+ compatible = "fsl,imx8mm-ccm";
+ reg = <0x30380000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
+ <&clk_ext3>, <&clk_ext4>;
+ clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4";
+ };
+
+...
diff --git a/dts/Bindings/clock/imx8mn-clock.yaml b/dts/Bindings/clock/imx8mn-clock.yaml
index cd0b8a3..bdaa296 100644
--- a/dts/Bindings/clock/imx8mn-clock.yaml
+++ b/dts/Bindings/clock/imx8mn-clock.yaml
@@ -40,7 +40,7 @@ properties:
'#clock-cells':
const: 1
- description: |
+ description:
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
for the full list of i.MX8M Nano clock IDs.
@@ -52,12 +52,14 @@ required:
- clock-names
- '#clock-cells'
+additionalProperties: false
+
examples:
# Clock Control Module node:
- |
clk: clock-controller@30380000 {
compatible = "fsl,imx8mn-ccm";
- reg = <0x0 0x30380000 0x0 0x10000>;
+ reg = <0x30380000 0x10000>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
<&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
@@ -65,48 +67,4 @@ examples:
"clk_ext2", "clk_ext3", "clk_ext4";
};
- # Required external clocks for Clock Control Module node:
- - |
- osc_32k: clock-osc-32k {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "osc_32k";
- };
-
- osc_24m: clock-osc-24m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "osc_24m";
- };
-
- clk_ext1: clock-ext1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <133000000>;
- clock-output-names = "clk_ext1";
- };
-
- clk_ext2: clock-ext2 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <133000000>;
- clock-output-names = "clk_ext2";
- };
-
- clk_ext3: clock-ext3 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <133000000>;
- clock-output-names = "clk_ext3";
- };
-
- clk_ext4: clock-ext4 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency= <133000000>;
- clock-output-names = "clk_ext4";
- };
-
...
diff --git a/dts/Bindings/clock/imx8mp-clock.yaml b/dts/Bindings/clock/imx8mp-clock.yaml
index 89aee63..4351a1d 100644
--- a/dts/Bindings/clock/imx8mp-clock.yaml
+++ b/dts/Bindings/clock/imx8mp-clock.yaml
@@ -52,6 +52,8 @@ required:
- clock-names
- '#clock-cells'
+additionalProperties: false
+
examples:
# Clock Control Module node:
- |
diff --git a/dts/Bindings/clock/imx8mq-clock.txt b/dts/Bindings/clock/imx8mq-clock.txt
deleted file mode 100644
index 52de826..0000000
--- a/dts/Bindings/clock/imx8mq-clock.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* Clock bindings for NXP i.MX8M Quad
-
-Required properties:
-- compatible: Should be "fsl,imx8mq-ccm"
-- reg: Address and length of the register set
-- #clock-cells: Should be <1>
-- clocks: list of clock specifiers, must contain an entry for each required
- entry in clock-names
-- clock-names: should include the following entries:
- - "ckil"
- - "osc_25m"
- - "osc_27m"
- - "clk_ext1"
- - "clk_ext2"
- - "clk_ext3"
- - "clk_ext4"
-
-The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
-for the full list of i.MX8M Quad clock IDs.
diff --git a/dts/Bindings/clock/imx8mq-clock.yaml b/dts/Bindings/clock/imx8mq-clock.yaml
new file mode 100644
index 0000000..05d7d14
--- /dev/null
+++ b/dts/Bindings/clock/imx8mq-clock.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx8mq-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8M Quad Clock Control Module Binding
+
+maintainers:
+ - Anson Huang <Anson.Huang@nxp.com>
+
+description: |
+ NXP i.MX8M Quad clock control module is an integrated clock controller, which
+ generates and supplies to all modules.
+
+properties:
+ compatible:
+ const: fsl,imx8mq-ccm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: 32k osc
+ - description: 25m osc
+ - description: 27m osc
+ - description: ext1 clock input
+ - description: ext2 clock input
+ - description: ext3 clock input
+ - description: ext4 clock input
+
+ clock-names:
+ items:
+ - const: ckil
+ - const: osc_25m
+ - const: osc_27m
+ - const: clk_ext1
+ - const: clk_ext2
+ - const: clk_ext3
+ - const: clk_ext4
+
+ '#clock-cells':
+ const: 1
+ description:
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
+ for the full list of i.MX8M Quad clock IDs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+examples:
+ # Clock Control Module node:
+ - |
+ clk: clock-controller@30380000 {
+ compatible = "fsl,imx8mq-ccm";
+ reg = <0x30380000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
+ <&clk_ext1>, <&clk_ext2>,
+ <&clk_ext3>, <&clk_ext4>;
+ clock-names = "ckil", "osc_25m", "osc_27m",
+ "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4";
+ };
+
+...
diff --git a/dts/Bindings/clock/marvell,mmp2-clock.yaml b/dts/Bindings/clock/marvell,mmp2-clock.yaml
new file mode 100644
index 0000000..e2b6ac9
--- /dev/null
+++ b/dts/Bindings/clock/marvell,mmp2-clock.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MMP2 and MMP3 Clock Controller
+
+maintainers:
+ - Lubomir Rintel <lkundrak@v3.sk>
+
+description: |
+ The clock subsystem on MMP2 or MMP3 generates and supplies clock to various
+ controllers within the SoC.
+
+ Each clock is assigned an identifier and client nodes use this identifier
+ to specify the clock which they consume.
+
+ All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>.
+
+properties:
+ compatible:
+ enum:
+ - marvell,mmp2-clock # controller compatible with MMP2 SoC
+ - marvell,mmp3-clock # controller compatible with MMP3 SoC
+
+ reg:
+ items:
+ - description: MPMU register region
+ - description: APMU register region
+ - description: APBC register region
+
+ reg-names:
+ items:
+ - const: mpmu
+ - const: apmu
+ - const: apbc
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@d4050000 {
+ compatible = "marvell,mmp2-clock";
+ reg = <0xd4050000 0x1000>,
+ <0xd4282800 0x400>,
+ <0xd4015000 0x1000>;
+ reg-names = "mpmu", "apmu", "apbc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/marvell,mmp2.txt b/dts/Bindings/clock/marvell,mmp2.txt
deleted file mode 100644
index 23b52dc..0000000
--- a/dts/Bindings/clock/marvell,mmp2.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* Marvell MMP2 Clock Controller
-
-The MMP2 clock subsystem generates and supplies clock to various
-controllers within the MMP2 SoC.
-
-Required Properties:
-
-- compatible: should be one of the following.
- - "marvell,mmp2-clock" - controller compatible with MMP2 SoC.
-
-- reg: physical base address of the clock subsystem and length of memory mapped
- region. There are 3 places in SOC has clock control logic:
- "mpmu", "apmu", "apbc". So three reg spaces need to be defined.
-
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Each clock is assigned an identifier and client nodes use this identifier
-to specify the clock which they consume.
-
-All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>.
diff --git a/dts/Bindings/clock/milbeaut-clock.yaml b/dts/Bindings/clock/milbeaut-clock.yaml
index f0b804a..0e8b077 100644
--- a/dts/Bindings/clock/milbeaut-clock.yaml
+++ b/dts/Bindings/clock/milbeaut-clock.yaml
@@ -35,6 +35,8 @@ required:
- clocks
- '#clock-cells'
+additionalProperties: false
+
examples:
# Clock controller node:
- |
diff --git a/dts/Bindings/clock/qcom,gcc-apq8064.yaml b/dts/Bindings/clock/qcom,gcc-apq8064.yaml
index 3647007..eacccc8 100644
--- a/dts/Bindings/clock/qcom,gcc-apq8064.yaml
+++ b/dts/Bindings/clock/qcom,gcc-apq8064.yaml
@@ -68,6 +68,8 @@ required:
- nvmem-cell-names
- '#thermal-sensor-cells'
+additionalProperties: false
+
examples:
- |
clock-controller@900000 {
diff --git a/dts/Bindings/clock/qcom,gcc-ipq8074.yaml b/dts/Bindings/clock/qcom,gcc-ipq8074.yaml
index 89c6e07..98572b4 100644
--- a/dts/Bindings/clock/qcom,gcc-ipq8074.yaml
+++ b/dts/Bindings/clock/qcom,gcc-ipq8074.yaml
@@ -40,6 +40,8 @@ required:
- '#clock-cells'
- '#reset-cells'
+additionalProperties: false
+
examples:
- |
clock-controller@1800000 {
diff --git a/dts/Bindings/clock/qcom,gcc-msm8996.yaml b/dts/Bindings/clock/qcom,gcc-msm8996.yaml
index 18e4e77..5a5b221 100644
--- a/dts/Bindings/clock/qcom,gcc-msm8996.yaml
+++ b/dts/Bindings/clock/qcom,gcc-msm8996.yaml
@@ -56,6 +56,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
clock-controller@300000 {
diff --git a/dts/Bindings/clock/qcom,gcc-msm8998.yaml b/dts/Bindings/clock/qcom,gcc-msm8998.yaml
index 1d3cae9..a0bb713 100644
--- a/dts/Bindings/clock/qcom,gcc-msm8998.yaml
+++ b/dts/Bindings/clock/qcom,gcc-msm8998.yaml
@@ -66,6 +66,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
diff --git a/dts/Bindings/clock/qcom,gcc-qcs404.yaml b/dts/Bindings/clock/qcom,gcc-qcs404.yaml
index 8cdece3..ce06f3f 100644
--- a/dts/Bindings/clock/qcom,gcc-qcs404.yaml
+++ b/dts/Bindings/clock/qcom,gcc-qcs404.yaml
@@ -40,6 +40,8 @@ required:
- '#clock-cells'
- '#reset-cells'
+additionalProperties: false
+
examples:
- |
clock-controller@1800000 {
diff --git a/dts/Bindings/clock/qcom,gcc-sc7180.yaml b/dts/Bindings/clock/qcom,gcc-sc7180.yaml
index ee4f968..a345320 100644
--- a/dts/Bindings/clock/qcom,gcc-sc7180.yaml
+++ b/dts/Bindings/clock/qcom,gcc-sc7180.yaml
@@ -58,6 +58,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
diff --git a/dts/Bindings/clock/qcom,gcc-sm8150.yaml b/dts/Bindings/clock/qcom,gcc-sm8150.yaml
index 888e9a7..36f3b36 100644
--- a/dts/Bindings/clock/qcom,gcc-sm8150.yaml
+++ b/dts/Bindings/clock/qcom,gcc-sm8150.yaml
@@ -56,6 +56,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
diff --git a/dts/Bindings/clock/qcom,gcc-sm8250.yaml b/dts/Bindings/clock/qcom,gcc-sm8250.yaml
new file mode 100644
index 0000000..2c40a8a
--- /dev/null
+++ b/dts/Bindings/clock/qcom,gcc-sm8250.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for SM8250
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+ - Taniya Das <tdas@codeaurora.org>
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains on SM8250.
+
+ See also:
+ - dt-bindings/clock/qcom,gcc-sm8250.h
+
+properties:
+ compatible:
+ const: qcom,gcc-sm8250
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: sleep_clk
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ protected-clocks:
+ description:
+ Protected clock specifier list as per common clock binding.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - reg
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,gcc-sm8250";
+ reg = <0 0x00100000 0 0x1f0000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>;
+ clock-names = "bi_tcxo", "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/clock/qcom,gcc.yaml b/dts/Bindings/clock/qcom,gcc.yaml
index d18f8ab..e533bb0 100644
--- a/dts/Bindings/clock/qcom,gcc.yaml
+++ b/dts/Bindings/clock/qcom,gcc.yaml
@@ -74,6 +74,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
# Example for GCC for MSM8960:
- |
diff --git a/dts/Bindings/clock/qcom,mmcc.yaml b/dts/Bindings/clock/qcom,mmcc.yaml
index 8551849..f684fe6 100644
--- a/dts/Bindings/clock/qcom,mmcc.yaml
+++ b/dts/Bindings/clock/qcom,mmcc.yaml
@@ -74,6 +74,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
if:
properties:
compatible:
diff --git a/dts/Bindings/clock/qcom,msm8998-gpucc.yaml b/dts/Bindings/clock/qcom,msm8998-gpucc.yaml
index 7d853c1..d747bb5 100644
--- a/dts/Bindings/clock/qcom,msm8998-gpucc.yaml
+++ b/dts/Bindings/clock/qcom,msm8998-gpucc.yaml
@@ -50,6 +50,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
diff --git a/dts/Bindings/clock/qcom,rpmcc.txt b/dts/Bindings/clock/qcom,rpmcc.txt
index 944719b..90a1349 100644
--- a/dts/Bindings/clock/qcom,rpmcc.txt
+++ b/dts/Bindings/clock/qcom,rpmcc.txt
@@ -14,7 +14,9 @@ Required properties :
"qcom,rpmcc-apq8060", "qcom,rpmcc"
"qcom,rpmcc-msm8916", "qcom,rpmcc"
"qcom,rpmcc-msm8974", "qcom,rpmcc"
+ "qcom,rpmcc-msm8976", "qcom,rpmcc"
"qcom,rpmcc-apq8064", "qcom,rpmcc"
+ "qcom,rpmcc-ipq806x", "qcom,rpmcc"
"qcom,rpmcc-msm8996", "qcom,rpmcc"
"qcom,rpmcc-msm8998", "qcom,rpmcc"
"qcom,rpmcc-qcs404", "qcom,rpmcc"
diff --git a/dts/Bindings/clock/qcom,rpmhcc.yaml b/dts/Bindings/clock/qcom,rpmhcc.yaml
index 2cd158f..a46a3a7 100644
--- a/dts/Bindings/clock/qcom,rpmhcc.yaml
+++ b/dts/Bindings/clock/qcom,rpmhcc.yaml
@@ -20,6 +20,7 @@ properties:
- qcom,sc7180-rpmh-clk
- qcom,sdm845-rpmh-clk
- qcom,sm8150-rpmh-clk
+ - qcom,sm8250-rpmh-clk
clocks:
maxItems: 1
@@ -35,6 +36,8 @@ required:
- compatible
- '#clock-cells'
+additionalProperties: false
+
examples:
# Example for GCC for SDM845: The below node should be defined inside
# &apps_rsc node.
diff --git a/dts/Bindings/clock/qcom,sc7180-dispcc.yaml b/dts/Bindings/clock/qcom,sc7180-dispcc.yaml
index 0429062..58cdfd5 100644
--- a/dts/Bindings/clock/qcom,sc7180-dispcc.yaml
+++ b/dts/Bindings/clock/qcom,sc7180-dispcc.yaml
@@ -58,6 +58,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
diff --git a/dts/Bindings/clock/qcom,sc7180-gpucc.yaml b/dts/Bindings/clock/qcom,sc7180-gpucc.yaml
index 5785192..8635e35 100644
--- a/dts/Bindings/clock/qcom,sc7180-gpucc.yaml
+++ b/dts/Bindings/clock/qcom,sc7180-gpucc.yaml
@@ -52,6 +52,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
diff --git a/dts/Bindings/clock/qcom,sc7180-mss.yaml b/dts/Bindings/clock/qcom,sc7180-mss.yaml
new file mode 100644
index 0000000..0dd5d25
--- /dev/null
+++ b/dts/Bindings/clock/qcom,sc7180-mss.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Modem Clock Controller Binding for SC7180
+
+maintainers:
+ - Taniya Das <tdas@codeaurora.org>
+
+description: |
+ Qualcomm modem clock control module which supports the clocks on SC7180.
+
+ See also:
+ - dt-bindings/clock/qcom,mss-sc7180.h
+
+properties:
+ compatible:
+ const: qcom,sc7180-mss
+
+ clocks:
+ items:
+ - description: gcc_mss_mfab_axi clock from GCC
+ - description: gcc_mss_nav_axi clock from GCC
+ - description: gcc_mss_cfg_ahb clock from GCC
+
+ clock-names:
+ items:
+ - const: gcc_mss_mfab_axis
+ - const: gcc_mss_nav_axi
+ - const: cfg_ahb
+
+ '#clock-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sc7180.h>
+ clock-controller@41a8000 {
+ compatible = "qcom,sc7180-mss";
+ reg = <0 0x041a8000 0 0x8000>;
+ clocks = <&gcc GCC_MSS_MFAB_AXIS_CLK>,
+ <&gcc GCC_MSS_NAV_AXI_CLK>,
+ <&gcc GCC_MSS_CFG_AHB_CLK>;
+ clock-names = "gcc_mss_mfab_axis",
+ "gcc_mss_nav_axi",
+ "cfg_ahb";
+ #clock-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/clock/qcom,sc7180-videocc.yaml b/dts/Bindings/clock/qcom,sc7180-videocc.yaml
index 31df901..0071b97 100644
--- a/dts/Bindings/clock/qcom,sc7180-videocc.yaml
+++ b/dts/Bindings/clock/qcom,sc7180-videocc.yaml
@@ -48,6 +48,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
diff --git a/dts/Bindings/clock/qcom,sdm845-dispcc.yaml b/dts/Bindings/clock/qcom,sdm845-dispcc.yaml
index 89269dd..ad47d74 100644
--- a/dts/Bindings/clock/qcom,sdm845-dispcc.yaml
+++ b/dts/Bindings/clock/qcom,sdm845-dispcc.yaml
@@ -67,6 +67,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
diff --git a/dts/Bindings/clock/qcom,sdm845-gpucc.yaml b/dts/Bindings/clock/qcom,sdm845-gpucc.yaml
index bac04f1..7a052ac 100644
--- a/dts/Bindings/clock/qcom,sdm845-gpucc.yaml
+++ b/dts/Bindings/clock/qcom,sdm845-gpucc.yaml
@@ -52,6 +52,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
diff --git a/dts/Bindings/clock/qcom,sdm845-videocc.yaml b/dts/Bindings/clock/qcom,sdm845-videocc.yaml
index 9d216c0..2a6a81a 100644
--- a/dts/Bindings/clock/qcom,sdm845-videocc.yaml
+++ b/dts/Bindings/clock/qcom,sdm845-videocc.yaml
@@ -48,6 +48,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.txt b/dts/Bindings/clock/renesas,cpg-mssr.txt
deleted file mode 100644
index f4d153f..0000000
--- a/dts/Bindings/clock/renesas,cpg-mssr.txt
+++ /dev/null
@@ -1,100 +0,0 @@
-* Renesas Clock Pulse Generator / Module Standby and Software Reset
-
-On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
-and MSSR (Module Standby and Software Reset) blocks are intimately connected,
-and share the same register block.
-
-They provide the following functionalities:
- - The CPG block generates various core clocks,
- - The MSSR block provides two functions:
- 1. Module Standby, providing a Clock Domain to control the clock supply
- to individual SoC devices,
- 2. Reset Control, to perform a software reset of individual SoC devices.
-
-Required Properties:
- - compatible: Must be one of:
- - "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2)
- - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
- - "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N)
- - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
- - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
- - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)
- - "renesas,r8a774b1-cpg-mssr" for the r8a774b1 SoC (RZ/G2N)
- - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)
- - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
- - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
- - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
- - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
- - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- - "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W)
- - "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+)
- - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
- - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
- - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
- - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)
- - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
-
- - reg: Base address and length of the memory resource used by the CPG/MSSR
- block
-
- - clocks: References to external parent clocks, one entry for each entry in
- clock-names
- - clock-names: List of external parent clock names. Valid names are:
- - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,
- r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793,
- r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970,
- r8a77980, r8a77990, r8a77995)
- - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965,
- r8a77970, r8a77980)
- - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,
- r8a7793, r8a7794)
-
- - #clock-cells: Must be 2
- - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
- and a core clock reference, as defined in
- <dt-bindings/clock/*-cpg-mssr.h>.
- - For module clocks, the two clock specifier cells must be "CPG_MOD" and
- a module number, as defined in the datasheet.
-
- - #power-domain-cells: Must be 0
- - SoC devices that are part of the CPG/MSSR Clock Domain and can be
- power-managed through Module Standby should refer to the CPG device
- node in their "power-domains" property, as documented by the generic PM
- Domain bindings in
- Documentation/devicetree/bindings/power/power-domain.yaml.
-
- - #reset-cells: Must be 1
- - The single reset specifier cell must be the module number, as defined
- in the datasheet.
-
-
-Examples
---------
-
- - CPG device node:
-
- cpg: clock-controller@e6150000 {
- compatible = "renesas,r8a7795-cpg-mssr";
- reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk>, <&extalr_clk>;
- clock-names = "extal", "extalr";
- #clock-cells = <2>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
- };
-
-
- - CPG/MSSR Clock Domain member device node:
-
- scif2: serial@e6e88000 {
- compatible = "renesas,scif-r8a7795", "renesas,scif";
- reg = <0 0xe6e88000 0 64>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 310>;
- clock-names = "fck";
- dmas = <&dmac1 0x13>, <&dmac1 0x12>;
- dma-names = "tx", "rx";
- power-domains = <&cpg>;
- resets = <&cpg 310>;
- };
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.yaml b/dts/Bindings/clock/renesas,cpg-mssr.yaml
new file mode 100644
index 0000000..9cd102e
--- /dev/null
+++ b/dts/Bindings/clock/renesas,cpg-mssr.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas Clock Pulse Generator / Module Standby and Software Reset
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description: |
+ On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
+ and MSSR (Module Standby and Software Reset) blocks are intimately connected,
+ and share the same register block.
+
+ They provide the following functionalities:
+ - The CPG block generates various core clocks,
+ - The MSSR block provides two functions:
+ 1. Module Standby, providing a Clock Domain to control the clock supply
+ to individual SoC devices,
+ 2. Reset Control, to perform a software reset of individual SoC devices.
+
+properties:
+ compatible:
+ enum:
+ - renesas,r7s9210-cpg-mssr # RZ/A2
+ - renesas,r8a7743-cpg-mssr # RZ/G1M
+ - renesas,r8a7744-cpg-mssr # RZ/G1N
+ - renesas,r8a7745-cpg-mssr # RZ/G1E
+ - renesas,r8a77470-cpg-mssr # RZ/G1C
+ - renesas,r8a774a1-cpg-mssr # RZ/G2M
+ - renesas,r8a774b1-cpg-mssr # RZ/G2N
+ - renesas,r8a774c0-cpg-mssr # RZ/G2E
+ - renesas,r8a7790-cpg-mssr # R-Car H2
+ - renesas,r8a7791-cpg-mssr # R-Car M2-W
+ - renesas,r8a7792-cpg-mssr # R-Car V2H
+ - renesas,r8a7793-cpg-mssr # R-Car M2-N
+ - renesas,r8a7794-cpg-mssr # R-Car E2
+ - renesas,r8a7795-cpg-mssr # R-Car H3
+ - renesas,r8a7796-cpg-mssr # R-Car M3-W
+ - renesas,r8a77961-cpg-mssr # R-Car M3-W+
+ - renesas,r8a77965-cpg-mssr # R-Car M3-N
+ - renesas,r8a77970-cpg-mssr # R-Car V3M
+ - renesas,r8a77980-cpg-mssr # R-Car V3H
+ - renesas,r8a77990-cpg-mssr # R-Car E3
+ - renesas,r8a77995-cpg-mssr # R-Car D3
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ enum:
+ - extal # All
+ - extalr # Most R-Car Gen3 and RZ/G2
+ - usb_extal # Most R-Car Gen2 and RZ/G1
+
+ '#clock-cells':
+ description: |
+ - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
+ and a core clock reference, as defined in
+ <dt-bindings/clock/*-cpg-mssr.h>
+ - For module clocks, the two clock specifier cells must be "CPG_MOD" and
+ a module number, as defined in the datasheet.
+ const: 2
+
+ '#power-domain-cells':
+ description:
+ SoC devices that are part of the CPG/MSSR Clock Domain and can be
+ power-managed through Module Standby should refer to the CPG device node
+ in their "power-domains" property, as documented by the generic PM Domain
+ bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
+ const: 0
+
+ '#reset-cells':
+ description:
+ The single reset specifier cell must be the module number, as defined in
+ the datasheet.
+ const: 1
+
+if:
+ not:
+ properties:
+ compatible:
+ items:
+ enum:
+ - renesas,r7s9210-cpg-mssr
+then:
+ required:
+ - '#reset-cells'
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7795-cpg-mssr";
+ reg = <0xe6150000 0x1000>;
+ clocks = <&extal_clk>, <&extalr_clk>;
+ clock-names = "extal", "extalr";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt b/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt
index 83f6c6a..4bf6f53 100644
--- a/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt
+++ b/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt
@@ -38,10 +38,17 @@ Required properties:
- reg: offset and length of the USB 2.0 clock selector register block.
- clocks: A list of phandles and specifier pairs.
- clock-names: Name of the clocks.
- - The functional clock must be "ehci_ohci"
+ - The functional clock of USB 2.0 host side must be "ehci_ohci"
+ - The functional clock of HS-USB side must be "hs-usb-if"
- The USB_EXTAL clock pin must be "usb_extal"
- The USB_XTAL clock pin must be "usb_xtal"
- #clock-cells: Must be 0
+- power-domains: A phandle and symbolic PM domain specifier.
+ See power/renesas,rcar-sysc.yaml.
+- resets: A list of phandles and specifier pairs.
+- reset-names: Name of the resets.
+ - The reset of USB 2.0 host side must be "ehci_ohci"
+ - The reset of HS-USB side must be "hs-usb-if"
Example (R-Car H3):
@@ -49,7 +56,11 @@ Example (R-Car H3):
compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
"renesas,rcar-gen3-usb2-clock-sel";
reg = <0 0xe6590630 0 0x02>;
- clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
- clock-names = "ehci_ohci", "usb_extal", "usb_xtal";
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
+ <&usb_extal>, <&usb_xtal>;
+ clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal";
#clock-cells = <0>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 703>, <&cpg 704>;
+ reset-names = "ehci_ohci", "hs-usb-if";
};
diff --git a/dts/Bindings/clock/socionext,uniphier-clock.yaml b/dts/Bindings/clock/socionext,uniphier-clock.yaml
new file mode 100644
index 0000000..c3930ed
--- /dev/null
+++ b/dts/Bindings/clock/socionext,uniphier-clock.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/socionext,uniphier-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier clock controller
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ compatible:
+ oneOf:
+ - description: System clock
+ enum:
+ - socionext,uniphier-ld4-clock
+ - socionext,uniphier-pro4-clock
+ - socionext,uniphier-sld8-clock
+ - socionext,uniphier-pro5-clock
+ - socionext,uniphier-pxs2-clock
+ - socionext,uniphier-ld6b-clock
+ - socionext,uniphier-ld11-clock
+ - socionext,uniphier-ld20-clock
+ - socionext,uniphier-pxs3-clock
+ - description: Media I/O (MIO) clock, SD clock
+ enum:
+ - socionext,uniphier-ld4-mio-clock
+ - socionext,uniphier-pro4-mio-clock
+ - socionext,uniphier-sld8-mio-clock
+ - socionext,uniphier-pro5-sd-clock
+ - socionext,uniphier-pxs2-sd-clock
+ - socionext,uniphier-ld11-mio-clock
+ - socionext,uniphier-ld20-sd-clock
+ - socionext,uniphier-pxs3-sd-clock
+ - description: Peripheral clock
+ enum:
+ - socionext,uniphier-ld4-peri-clock
+ - socionext,uniphier-pro4-peri-clock
+ - socionext,uniphier-sld8-peri-clock
+ - socionext,uniphier-pro5-peri-clock
+ - socionext,uniphier-pxs2-peri-clock
+ - socionext,uniphier-ld11-peri-clock
+ - socionext,uniphier-ld20-peri-clock
+ - socionext,uniphier-pxs3-peri-clock
+
+ "#clock-cells":
+ const: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - "#clock-cells"
+
+examples:
+ - |
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon";
+ reg = <0x61840000 0x4000>;
+
+ clock {
+ compatible = "socionext,uniphier-ld11-clock";
+ #clock-cells = <1>;
+ };
+
+ // other nodes ...
+ };
+
+ - |
+ mioctrl@59810000 {
+ compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+
+ clock {
+ compatible = "socionext,uniphier-ld11-mio-clock";
+ #clock-cells = <1>;
+ };
+
+ // other nodes ...
+ };
+
+ - |
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ clock {
+ compatible = "socionext,uniphier-ld11-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ // other nodes ...
+ };
diff --git a/dts/Bindings/clock/sprd.txt b/dts/Bindings/clock/sprd,sc9860-clk.txt
index e9d179e..aaaf02c 100644
--- a/dts/Bindings/clock/sprd.txt
+++ b/dts/Bindings/clock/sprd,sc9860-clk.txt
@@ -1,4 +1,4 @@
-Spreadtrum Clock Binding
+Spreadtrum SC9860 Clock Binding
------------------------
Required properties:
diff --git a/dts/Bindings/clock/sprd,sc9863a-clk.yaml b/dts/Bindings/clock/sprd,sc9863a-clk.yaml
new file mode 100644
index 0000000..bb3a78d
--- /dev/null
+++ b/dts/Bindings/clock/sprd,sc9863a-clk.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2019 Unisoc Inc.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: SC9863A Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Orson Zhai <orsonzhai@gmail.com>
+ - Baolin Wang <baolin.wang7@gmail.com>
+ - Chunyan Zhang <zhang.lyra@gmail.com>
+
+properties:
+ "#clock-cells":
+ const: 1
+
+ compatible :
+ enum:
+ - sprd,sc9863a-ap-clk
+ - sprd,sc9863a-aon-clk
+ - sprd,sc9863a-apahb-gate
+ - sprd,sc9863a-pmu-gate
+ - sprd,sc9863a-aonapb-gate
+ - sprd,sc9863a-pll
+ - sprd,sc9863a-mpll
+ - sprd,sc9863a-rpll
+ - sprd,sc9863a-dpll
+ - sprd,sc9863a-mm-gate
+ - sprd,sc9863a-apapb-gate
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+ description: |
+ The input parent clock(s) phandle for this clock, only list fixed
+ clocks which are declared in devicetree.
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+ items:
+ - const: ext-26m
+ - const: ext-32k
+ - const: ext-4m
+ - const: rco-100m
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - '#clock-cells'
+
+if:
+ properties:
+ compatible:
+ enum:
+ - sprd,sc9863a-ap-clk
+ - sprd,sc9863a-aon-clk
+then:
+ required:
+ - reg
+
+else:
+ description: |
+ Other SC9863a clock nodes should be the child of a syscon node in
+ which compatible string shoule be:
+ "sprd,sc9863a-glbregs", "syscon", "simple-mfd"
+
+ The 'reg' property for the clock node is also required if there is a sub
+ range of registers for the clocks.
+
+examples:
+ - |
+ ap_clk: clock-controller@21500000 {
+ compatible = "sprd,sc9863a-ap-clk";
+ reg = <0 0x21500000 0 0x1000>;
+ clocks = <&ext_26m>, <&ext_32k>;
+ clock-names = "ext-26m", "ext-32k";
+ #clock-cells = <1>;
+ };
+
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ap_ahb_regs: syscon@20e00000 {
+ compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
+ reg = <0 0x20e00000 0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x20e00000 0x4000>;
+
+ apahb_gate: apahb-gate@0 {
+ compatible = "sprd,sc9863a-apahb-gate";
+ reg = <0x0 0x1020>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml b/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
new file mode 100644
index 0000000..869b18a
--- /dev/null
+++ b/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti,am654-ehrpwm-tbclk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI EHRPWM Time Base Clock
+
+maintainers:
+ - Vignesh Raghavendra <vigneshr@ti.com>
+
+properties:
+ compatible:
+ items:
+ - const: ti,am654-ehrpwm-tbclk
+ - const: syscon
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+
+examples:
+ - |
+ ehrpwm_tbclk: syscon@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk", "syscon";
+ reg = <0x4140 0x18>;
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/uniphier-clock.txt b/dts/Bindings/clock/uniphier-clock.txt
deleted file mode 100644
index 7b5f602..0000000
--- a/dts/Bindings/clock/uniphier-clock.txt
+++ /dev/null
@@ -1,132 +0,0 @@
-UniPhier clock controller
-
-
-System clock
-------------
-
-Required properties:
-- compatible: should be one of the following:
- "socionext,uniphier-ld4-clock" - for LD4 SoC.
- "socionext,uniphier-pro4-clock" - for Pro4 SoC.
- "socionext,uniphier-sld8-clock" - for sLD8 SoC.
- "socionext,uniphier-pro5-clock" - for Pro5 SoC.
- "socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
- "socionext,uniphier-ld11-clock" - for LD11 SoC.
- "socionext,uniphier-ld20-clock" - for LD20 SoC.
- "socionext,uniphier-pxs3-clock" - for PXs3 SoC
-- #clock-cells: should be 1.
-
-Example:
-
- sysctrl@61840000 {
- compatible = "socionext,uniphier-sysctrl",
- "simple-mfd", "syscon";
- reg = <0x61840000 0x4000>;
-
- clock {
- compatible = "socionext,uniphier-ld11-clock";
- #clock-cells = <1>;
- };
-
- other nodes ...
- };
-
-Provided clocks:
-
- 8: ST DMAC
-12: GIO (Giga bit stream I/O)
-14: USB3 ch0 host
-15: USB3 ch1 host
-16: USB3 ch0 PHY0
-17: USB3 ch0 PHY1
-20: USB3 ch1 PHY0
-21: USB3 ch1 PHY1
-
-
-Media I/O (MIO) clock, SD clock
--------------------------------
-
-Required properties:
-- compatible: should be one of the following:
- "socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
- "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
- "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
- "socionext,uniphier-pro5-sd-clock" - for Pro5 SoC.
- "socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
- "socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
- "socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
- "socionext,uniphier-pxs3-sd-clock" - for PXs3 SoC
-- #clock-cells: should be 1.
-
-Example:
-
- mioctrl@59810000 {
- compatible = "socionext,uniphier-mioctrl",
- "simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
-
- clock {
- compatible = "socionext,uniphier-ld11-mio-clock";
- #clock-cells = <1>;
- };
-
- other nodes ...
- };
-
-Provided clocks:
-
- 0: SD ch0 host
- 1: eMMC host
- 2: SD ch1 host
- 7: MIO DMAC
- 8: USB2 ch0 host
- 9: USB2 ch1 host
-10: USB2 ch2 host
-12: USB2 ch0 PHY
-13: USB2 ch1 PHY
-14: USB2 ch2 PHY
-
-
-Peripheral clock
-----------------
-
-Required properties:
-- compatible: should be one of the following:
- "socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
- "socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
- "socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
- "socionext,uniphier-pro5-peri-clock" - for Pro5 SoC.
- "socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
- "socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
- "socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
- "socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC
-- #clock-cells: should be 1.
-
-Example:
-
- perictrl@59820000 {
- compatible = "socionext,uniphier-perictrl",
- "simple-mfd", "syscon";
- reg = <0x59820000 0x200>;
-
- clock {
- compatible = "socionext,uniphier-ld11-peri-clock";
- #clock-cells = <1>;
- };
-
- other nodes ...
- };
-
-Provided clocks:
-
- 0: UART ch0
- 1: UART ch1
- 2: UART ch2
- 3: UART ch3
- 4: I2C ch0
- 5: I2C ch1
- 6: I2C ch2
- 7: I2C ch3
- 8: I2C ch4
- 9: I2C ch5
-10: I2C ch6
diff --git a/dts/Bindings/connector/samsung,usb-connector-11pin.txt b/dts/Bindings/connector/samsung,usb-connector-11pin.txt
index 22256e2..3dd8961 100644
--- a/dts/Bindings/connector/samsung,usb-connector-11pin.txt
+++ b/dts/Bindings/connector/samsung,usb-connector-11pin.txt
@@ -19,7 +19,7 @@ Required nodes:
0: High Speed (HS),
3: Mobile High-Definition Link (MHL), specific to 11-pin Samsung micro-USB.
-[1]: bindings/connector/usb-connector.txt
+[1]: bindings/connector/usb-connector.yaml
Example
-------
diff --git a/dts/Bindings/connector/usb-connector.txt b/dts/Bindings/connector/usb-connector.txt
deleted file mode 100644
index 88578ac..0000000
--- a/dts/Bindings/connector/usb-connector.txt
+++ /dev/null
@@ -1,135 +0,0 @@
-USB Connector
-=============
-
-A USB connector node represents a physical USB connector. It should be
-a child of a USB interface controller.
-
-Required properties:
-- compatible: describes type of the connector, must be one of:
- "usb-a-connector",
- "usb-b-connector",
- "usb-c-connector".
-
-Optional properties:
-- label: symbolic name for the connector,
-- type: size of the connector, should be specified in case of USB-A, USB-B
- non-fullsize connectors: "mini", "micro".
-- self-powered: Set this property if the usb device that has its own power
- source.
-
-Optional properties for usb-b-connector:
-- id-gpios: an input gpio for USB ID pin.
-- vbus-gpios: an input gpio for USB VBUS pin, used to detect presence of
- VBUS 5V.
- see gpio/gpio.txt.
-- vbus-supply: a phandle to the regulator for USB VBUS if needed when host
- mode or dual role mode is supported.
- Particularly, if use an output GPIO to control a VBUS regulator, should
- model it as a regulator.
- see regulator/fixed-regulator.yaml
-- pinctrl-names : a pinctrl state named "default" is optional
-- pinctrl-0 : pin control group
- see pinctrl/pinctrl-bindings.txt
-
-Optional properties for usb-c-connector:
-- power-role: should be one of "source", "sink" or "dual"(DRP) if typec
- connector has power support.
-- try-power-role: preferred power role if "dual"(DRP) can support Try.SNK
- or Try.SRC, should be "sink" for Try.SNK or "source" for Try.SRC.
-- data-role: should be one of "host", "device", "dual"(DRD) if typec
- connector supports USB data.
-
-Required properties for usb-c-connector with power delivery support:
-- source-pdos: An array of u32 with each entry providing supported power
- source data object(PDO), the detailed bit definitions of PDO can be found
- in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2
- Source_Capabilities Message, the order of each entry(PDO) should follow
- the PD spec chapter 6.4.1. Required for power source and power dual role.
- User can specify the source PDO array via PDO_FIXED/BATT/VAR/PPS_APDO()
- defined in dt-bindings/usb/pd.h.
-- sink-pdos: An array of u32 with each entry providing supported power
- sink data object(PDO), the detailed bit definitions of PDO can be found
- in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
- Sink Capabilities Message, the order of each entry(PDO) should follow
- the PD spec chapter 6.4.1. Required for power sink and power dual role.
- User can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined
- in dt-bindings/usb/pd.h.
-- op-sink-microwatt: Sink required operating power in microwatt, if source
- can't offer the power, Capability Mismatch is set. Required for power
- sink and power dual role.
-
-Required nodes:
-- any data bus to the connector should be modeled using the OF graph bindings
- specified in bindings/graph.txt, unless the bus is between parent node and
- the connector. Since single connector can have multiple data buses every bus
- has assigned OF graph port number as follows:
- 0: High Speed (HS), present in all connectors,
- 1: Super Speed (SS), present in SS capable connectors,
- 2: Sideband use (SBU), present in USB-C.
-
-Examples
---------
-
-1. Micro-USB connector with HS lines routed via controller (MUIC):
-
-muic-max77843@66 {
- ...
- usb_con: connector {
- compatible = "usb-b-connector";
- label = "micro-USB";
- type = "micro";
- };
-};
-
-2. USB-C connector attached to CC controller (s2mm005), HS lines routed
-to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort.
-DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
-
-ccic: s2mm005@33 {
- ...
- usb_con: connector {
- compatible = "usb-c-connector";
- label = "USB-C";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- usb_con_hs: endpoint {
- remote-endpoint = <&max77865_usbc_hs>;
- };
- };
- port@1 {
- reg = <1>;
- usb_con_ss: endpoint {
- remote-endpoint = <&usbdrd_phy_ss>;
- };
- };
- port@2 {
- reg = <2>;
- usb_con_sbu: endpoint {
- remote-endpoint = <&dp_aux>;
- };
- };
- };
- };
-};
-
-3. USB-C connector attached to a typec port controller(ptn5110), which has
-power delivery support and enables drp.
-
-typec: ptn5110@50 {
- ...
- usb_con: connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- power-role = "dual";
- try-power-role = "sink";
- source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
- PDO_VAR(5000, 12000, 2000)>;
- op-sink-microwatt = <10000000>;
- };
-};
diff --git a/dts/Bindings/connector/usb-connector.yaml b/dts/Bindings/connector/usb-connector.yaml
new file mode 100644
index 0000000..4638d7a
--- /dev/null
+++ b/dts/Bindings/connector/usb-connector.yaml
@@ -0,0 +1,206 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/connector/usb-connector.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: USB Connector
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description:
+ A USB connector node represents a physical USB connector. It should be a child
+ of a USB interface controller.
+
+properties:
+ compatible:
+ enum:
+ - usb-a-connector
+ - usb-b-connector
+ - usb-c-connector
+
+ label:
+ description: Symbolic name for the connector.
+
+ type:
+ description: Size of the connector, should be specified in case of
+ non-fullsize 'usb-a-connector' or 'usb-b-connector' compatible
+ connectors.
+ allOf:
+ - $ref: /schemas/types.yaml#definitions/string
+ enum:
+ - mini
+ - micro
+
+ self-powered:
+ description: Set this property if the USB device has its own power source.
+ type: boolean
+
+ # The following are optional properties for "usb-b-connector".
+ id-gpios:
+ description: An input gpio for USB ID pin.
+ maxItems: 1
+
+ vbus-gpios:
+ description: An input gpio for USB VBus pin, used to detect presence of
+ VBUS 5V.
+ maxItems: 1
+
+ vbus-supply:
+ description: A phandle to the regulator for USB VBUS if needed when host
+ mode or dual role mode is supported.
+ Particularly, if use an output GPIO to control a VBUS regulator, should
+ model it as a regulator. See bindings/regulator/fixed-regulator.yaml
+
+ # The following are optional properties for "usb-c-connector".
+ power-role:
+ description: Determines the power role that the Type C connector will
+ support. "dual" refers to Dual Role Port (DRP).
+ allOf:
+ - $ref: /schemas/types.yaml#definitions/string
+ enum:
+ - source
+ - sink
+ - dual
+
+ try-power-role:
+ description: Preferred power role.
+ allOf:
+ - $ref: /schemas/types.yaml#definitions/string
+ enum:
+ - source
+ - sink
+ - dual
+
+ data-role:
+ description: Data role if Type C connector supports USB data. "dual" refers
+ Dual Role Device (DRD).
+ allOf:
+ - $ref: /schemas/types.yaml#definitions/string
+ enum:
+ - host
+ - device
+ - dual
+
+ # The following are optional properties for "usb-c-connector" with power
+ # delivery support.
+ source-pdos:
+ description: An array of u32 with each entry providing supported power
+ source data object(PDO), the detailed bit definitions of PDO can be found
+ in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2
+ Source_Capabilities Message, the order of each entry(PDO) should follow
+ the PD spec chapter 6.4.1. Required for power source and power dual role.
+ User can specify the source PDO array via PDO_FIXED/BATT/VAR/PPS_APDO()
+ defined in dt-bindings/usb/pd.h.
+ minItems: 1
+ maxItems: 7
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ sink-pdos:
+ description: An array of u32 with each entry providing supported power sink
+ data object(PDO), the detailed bit definitions of PDO can be found in
+ "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
+ Sink Capabilities Message, the order of each entry(PDO) should follow the
+ PD spec chapter 6.4.1. Required for power sink and power dual role. User
+ can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined
+ in dt-bindings/usb/pd.h.
+ minItems: 1
+ maxItems: 7
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ op-sink-microwatt:
+ description: Sink required operating power in microwatt, if source can't
+ offer the power, Capability Mismatch is set. Required for power sink and
+ power dual role.
+
+ ports:
+ description: OF graph bindings (specified in bindings/graph.txt) that model
+ any data bus to the connector unless the bus is between parent node and
+ the connector. Since a single connector can have multiple data buses every
+ bus has an assigned OF graph port number as described below.
+ type: object
+ properties:
+ port@0:
+ type: object
+ description: High Speed (HS), present in all connectors.
+
+ port@1:
+ type: object
+ description: Super Speed (SS), present in SS capable connectors.
+
+ port@2:
+ type: object
+ description: Sideband Use (SBU), present in USB-C. This describes the
+ alternate mode connection of which SBU is a part.
+
+ required:
+ - port@0
+
+required:
+ - compatible
+
+examples:
+ # Micro-USB connector with HS lines routed via controller (MUIC).
+ - |+
+ muic-max77843 {
+ usb_con1: connector {
+ compatible = "usb-b-connector";
+ label = "micro-USB";
+ type = "micro";
+ };
+ };
+
+ # USB-C connector attached to CC controller (s2mm005), HS lines routed
+ # to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort.
+ # DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
+ - |+
+ ccic: s2mm005 {
+ usb_con2: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usb_con_hs: endpoint {
+ remote-endpoint = <&max77865_usbc_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ usb_con_ss: endpoint {
+ remote-endpoint = <&usbdrd_phy_ss>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ usb_con_sbu: endpoint {
+ remote-endpoint = <&dp_aux>;
+ };
+ };
+ };
+ };
+ };
+
+ # USB-C connector attached to a typec port controller(ptn5110), which has
+ # power delivery support and enables drp.
+ - |+
+ #include <dt-bindings/usb/pd.h>
+ typec: ptn5110 {
+ usb_con3: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 12000, 2000)>;
+ op-sink-microwatt = <10000000>;
+ };
+ };
diff --git a/dts/Bindings/crypto/fsl-dcp.txt b/dts/Bindings/crypto/fsl-dcp.txt
index 4e4d387..513499f 100644
--- a/dts/Bindings/crypto/fsl-dcp.txt
+++ b/dts/Bindings/crypto/fsl-dcp.txt
@@ -11,7 +11,7 @@ Required properties:
Example:
-dcp@80028000 {
+dcp: crypto@80028000 {
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
interrupts = <52 53>;
diff --git a/dts/Bindings/crypto/fsl-imx-sahara.txt b/dts/Bindings/crypto/fsl-imx-sahara.txt
index e8a35c7..db690b1 100644
--- a/dts/Bindings/crypto/fsl-imx-sahara.txt
+++ b/dts/Bindings/crypto/fsl-imx-sahara.txt
@@ -8,7 +8,7 @@ Required properties:
Example:
-sah@10025000 {
+sah: crypto@10025000 {
compatible = "fsl,imx27-sahara";
reg = < 0x10025000 0x800>;
interrupts = <75>;
diff --git a/dts/Bindings/crypto/fsl-sec4.txt b/dts/Bindings/crypto/fsl-sec4.txt
index 2fe245c..8f359f4 100644
--- a/dts/Bindings/crypto/fsl-sec4.txt
+++ b/dts/Bindings/crypto/fsl-sec4.txt
@@ -138,7 +138,7 @@ iMX6QDL/SX requires four clocks
iMX6UL does only require three clocks
- crypto: caam@2140000 {
+ crypto: crypto@2140000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/Bindings/crypto/xlnx,zynqmp-aes.yaml b/dts/Bindings/crypto/xlnx,zynqmp-aes.yaml
new file mode 100644
index 0000000..55dd6e3
--- /dev/null
+++ b/dts/Bindings/crypto/xlnx,zynqmp-aes.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx ZynqMP AES-GCM Hardware Accelerator Device Tree Bindings
+
+maintainers:
+ - Kalyani Akula <kalyani.akula@xilinx.com>
+ - Michal Simek <michal.simek@xilinx.com>
+
+description: |
+ The ZynqMP AES-GCM hardened cryptographic accelerator is used to
+ encrypt or decrypt the data with provided key and initialization vector.
+
+properties:
+ compatible:
+ const: xlnx,zynqmp-aes
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+ xlnx_aes: zynqmp-aes {
+ compatible = "xlnx,zynqmp-aes";
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml b/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml
index 5ff9cf2..e5344c4 100644
--- a/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml
+++ b/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml
@@ -36,6 +36,12 @@ properties:
- items:
- enum:
+ - allwinner,sun7i-a20-tcon0
+ - allwinner,sun7i-a20-tcon1
+ - const: allwinner,sun7i-a20-tcon
+
+ - items:
+ - enum:
- allwinner,sun50i-a64-tcon-lcd
- const: allwinner,sun8i-a83t-tcon-lcd
diff --git a/dts/Bindings/display/amlogic,meson-vpu.yaml b/dts/Bindings/display/amlogic,meson-vpu.yaml
index d1205a6..a8d202c 100644
--- a/dts/Bindings/display/amlogic,meson-vpu.yaml
+++ b/dts/Bindings/display/amlogic,meson-vpu.yaml
@@ -71,9 +71,9 @@ properties:
maxItems: 2
reg-names:
- items:
- - const: vpu
- - const: hhi
+ items:
+ - const: vpu
+ - const: hhi
interrupts:
maxItems: 1
@@ -107,6 +107,8 @@ required:
- "#address-cells"
- "#size-cells"
+additionalProperties: false
+
examples:
- |
vpu: vpu@d0100000 {
diff --git a/dts/Bindings/display/bridge/adi,adv7511.txt b/dts/Bindings/display/bridge/adi,adv7511.txt
index 2c88753..e8ddec5 100644
--- a/dts/Bindings/display/bridge/adi,adv7511.txt
+++ b/dts/Bindings/display/bridge/adi,adv7511.txt
@@ -1,10 +1,10 @@
-Analog Device ADV7511(W)/13/33 HDMI Encoders
+Analog Device ADV7511(W)/13/33/35 HDMI Encoders
-----------------------------------------
-The ADV7511, ADV7511W, ADV7513 and ADV7533 are HDMI audio and video transmitters
-compatible with HDMI 1.4 and DVI 1.0. They support color space conversion,
-S/PDIF, CEC and HDCP. ADV7533 supports the DSI interface for input pixels, while
-the others support RGB interface.
+The ADV7511, ADV7511W, ADV7513, ADV7533 and ADV7535 are HDMI audio and video
+transmitters compatible with HDMI 1.4 and DVI 1.0. They support color space
+conversion, S/PDIF, CEC and HDCP. ADV7533/5 supports the DSI interface for input
+pixels, while the others support RGB interface.
Required properties:
@@ -13,6 +13,7 @@ Required properties:
"adi,adv7511w"
"adi,adv7513"
"adi,adv7533"
+ "adi,adv7535"
- reg: I2C slave addresses
The ADV7511 internal registers are split into four pages exposed through
@@ -52,14 +53,14 @@ The following input format properties are required except in "rgb 1x" and
- bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is
needed only for ADV7511.
-The following properties are required for ADV7533:
+The following properties are required for ADV7533 and ADV7535:
- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should
be one of 1, 2, 3 or 4.
- a2vdd-supply: 1.8V supply that powers up the A2VDD pin on the chip.
- v3p3-supply: A 3.3V supply that powers up the V3P3 pin on the chip.
- v1p2-supply: A supply that powers up the V1P2 pin on the chip. It can be
- either 1.2V or 1.8V.
+ either 1.2V or 1.8V for ADV7533 but only 1.8V for ADV7535.
Optional properties:
@@ -71,9 +72,9 @@ Optional properties:
- adi,embedded-sync: The input uses synchronization signals embedded in the
data stream (similar to BT.656). Defaults to separate H/V synchronization
signals.
-- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing
- generator. The chip will rely on the sync signals in the DSI data lanes,
- rather than generate its own timings for HDMI output.
+- adi,disable-timing-generator: Only for ADV7533 and ADV7535. Disables the
+ internal timing generator. The chip will rely on the sync signals in the
+ DSI data lanes, rather than generate its own timings for HDMI output.
- clocks: from common clock binding: reference to the CEC clock.
- clock-names: from common clock binding: must be "cec".
- reg-names : Names of maps with programmable addresses.
@@ -85,7 +86,7 @@ Required nodes:
The ADV7511 has two video ports. Their connections are modelled using the OF
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
-- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533, the
+- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533/5, the
remote endpoint phandle should be a reference to a valid mipi_dsi_host device
node.
- Video port 1 for the HDMI output
diff --git a/dts/Bindings/display/bridge/ps8640.yaml b/dts/Bindings/display/bridge/ps8640.yaml
new file mode 100644
index 0000000..5dff936
--- /dev/null
+++ b/dts/Bindings/display/bridge/ps8640.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ps8640.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPI DSI to eDP Video Format Converter Device Tree Bindings
+
+maintainers:
+ - Nicolas Boichat <drinkcat@chromium.org>
+ - Enric Balletbo i Serra <enric.balletbo@collabora.com>
+
+description: |
+ The PS8640 is a low power MIPI-to-eDP video format converter supporting
+ mobile devices with embedded panel resolutions up to 2048 x 1536. The
+ device accepts a single channel of MIPI DSI v1.1, with up to four lanes
+ plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
+ device outputs eDP v1.4, one or two lanes, at a link rate of up to
+ 3.24Gbit/sec per lane.
+
+properties:
+ compatible:
+ const: parade,ps8640
+
+ reg:
+ maxItems: 1
+ description: Base I2C address of the device.
+
+ powerdown-gpios:
+ maxItems: 1
+ description: GPIO connected to active low powerdown.
+
+ reset-gpios:
+ maxItems: 1
+ description: GPIO connected to active low reset.
+
+ vdd12-supply:
+ maxItems: 1
+ description: Regulator for 1.2V digital core power.
+
+ vdd33-supply:
+ maxItems: 1
+ description: Regulator for 3.3V digital core power.
+
+ ports:
+ type: object
+ description:
+ A node containing DSI input & output port nodes with endpoint
+ definitions as documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+ Documentation/devicetree/bindings/graph.txt
+ properties:
+ port@0:
+ type: object
+ description: |
+ Video port for DSI input
+
+ port@1:
+ type: object
+ description: |
+ Video port for eDP output (panel or connector).
+
+ required:
+ - port@0
+
+required:
+ - compatible
+ - reg
+ - powerdown-gpios
+ - reset-gpios
+ - vdd12-supply
+ - vdd33-supply
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ps8640: edp-bridge@18 {
+ compatible = "parade,ps8640";
+ reg = <0x18>;
+ powerdown-gpios = <&pio 116 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
+ vdd12-supply = <&ps8640_fixed_1v2>;
+ vdd33-supply = <&mt6397_vgp2_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ ps8640_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ps8640_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+ };
+
diff --git a/dts/Bindings/display/bridge/toshiba,tc358768.yaml b/dts/Bindings/display/bridge/toshiba,tc358768.yaml
new file mode 100644
index 0000000..c036a75
--- /dev/null
+++ b/dts/Bindings/display/bridge/toshiba,tc358768.yaml
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358768.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toschiba TC358768/TC358778 Parallel RGB to MIPI DSI bridge
+
+maintainers:
+ - Peter Ujfalusi <peter.ujfalusi@ti.com>
+
+description: |
+ The TC358768/TC358778 is bridge device which converts RGB to DSI.
+
+properties:
+ compatible:
+ enum:
+ - toshiba,tc358768
+ - toshiba,tc358778
+
+ reg:
+ maxItems: 1
+ description: base I2C address of the device
+
+ reset-gpios:
+ maxItems: 1
+ description: GPIO connected to active low RESX pin
+
+ vddc-supply:
+ description: Regulator for 1.2V internal core power.
+
+ vddmipi-supply:
+ description: Regulator for 1.2V for the MIPI.
+
+ vddio-supply:
+ description: Regulator for 1.8V - 3.3V IO power.
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: refclk
+
+ ports:
+ type: object
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ port@0:
+ type: object
+ additionalProperties: false
+
+ description: |
+ Video port for RGB input
+
+ properties:
+ reg:
+ const: 0
+
+ patternProperties:
+ endpoint:
+ type: object
+ additionalProperties: false
+
+ properties:
+ data-lines:
+ enum: [ 16, 18, 24 ]
+
+ remote-endpoint: true
+
+ required:
+ - reg
+
+ port@1:
+ type: object
+ additionalProperties: false
+
+ description: |
+ Video port for DSI output (panel or connector).
+
+ properties:
+ reg:
+ const: 1
+
+ patternProperties:
+ endpoint:
+ type: object
+ additionalProperties: false
+
+ properties:
+ remote-endpoint: true
+
+ required:
+ - reg
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - vddc-supply
+ - vddmipi-supply
+ - vddio-supply
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi_bridge: dsi-bridge@e {
+ compatible = "toshiba,tc358768";
+ reg = <0xe>;
+
+ clocks = <&tc358768_refclk>;
+ clock-names = "refclk";
+
+ reset-gpios = <&pcf_display_board 0 GPIO_ACTIVE_LOW>;
+
+ vddc-supply = <&v1_2d>;
+ vddmipi-supply = <&v1_2d>;
+ vddio-supply = <&v3_3d>;
+
+ dsi_bridge_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ rgb_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ data-lines = <24>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&lcd_in>;
+ };
+ };
+ };
+ };
+ };
+
diff --git a/dts/Bindings/display/connector/analog-tv-connector.txt b/dts/Bindings/display/connector/analog-tv-connector.txt
index 0c0970c..883bcb2 100644
--- a/dts/Bindings/display/connector/analog-tv-connector.txt
+++ b/dts/Bindings/display/connector/analog-tv-connector.txt
@@ -6,16 +6,22 @@ Required properties:
Optional properties:
- label: a symbolic name for the connector
+- sdtv-standards: limit the supported TV standards on a connector to the given
+ ones. If not specified all TV standards are allowed.
+ Possible TV standards are defined in
+ include/dt-bindings/display/sdtv-standards.h.
Required nodes:
- Video port for TV input
Example
-------
+#include <dt-bindings/display/sdtv-standards.h>
tv: connector {
compatible = "composite-video-connector";
label = "tv";
+ sdtv-standards = <(SDTV_STD_PAL | SDTV_STD_NTSC)>;
port {
tv_connector_in: endpoint {
diff --git a/dts/Bindings/display/etnaviv/etnaviv-drm.txt b/dts/Bindings/display/etnaviv/etnaviv-drm.txt
deleted file mode 100644
index 8def11b..0000000
--- a/dts/Bindings/display/etnaviv/etnaviv-drm.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Vivante GPU core devices
-========================
-
-Required properties:
-- compatible: Should be "vivante,gc"
- A more specific compatible is not needed, as the cores contain chip
- identification registers at fixed locations, which provide all the
- necessary information to the driver.
-- reg: should be register base and length as documented in the
- datasheet
-- interrupts: Should contain the cores interrupt line
-- clocks: should contain one clock for entry in clock-names
- see Documentation/devicetree/bindings/clock/clock-bindings.txt
-- clock-names:
- - "bus": AXI/master interface clock
- - "reg": AHB/slave interface clock
- (only required if GPU can gate slave interface independently)
- - "core": GPU core clock
- - "shader": Shader clock (only required if GPU has feature PIPE_3D)
-
-Optional properties:
-- power-domains: a power domain consumer specifier according to
- Documentation/devicetree/bindings/power/power_domain.txt
-
-example:
-
-gpu_3d: gpu@130000 {
- compatible = "vivante,gc";
- reg = <0x00130000 0x4000>;
- interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
- <&clks IMX6QDL_CLK_GPU3D_CORE>,
- <&clks IMX6QDL_CLK_GPU3D_SHADER>;
- clock-names = "bus", "core", "shader";
- power-domains = <&gpc 1>;
-};
diff --git a/dts/Bindings/display/ilitek,ili9486.yaml b/dts/Bindings/display/ilitek,ili9486.yaml
new file mode 100644
index 0000000..66e93e5
--- /dev/null
+++ b/dts/Bindings/display/ilitek,ili9486.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/ilitek,ili9486.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek ILI9486 display panels device tree bindings
+
+maintainers:
+ - Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com>
+
+description:
+ This binding is for display panels using an Ilitek ILI9486 controller in SPI
+ mode.
+
+allOf:
+ - $ref: panel/panel-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ # Waveshare 3.5" 320x480 Color TFT LCD
+ - waveshare,rpi-lcd-35
+ # Ozzmaker 3.5" 320x480 Color TFT LCD
+ - ozzmaker,piscreen
+ - const: ilitek,ili9486
+
+ spi-max-frequency:
+ maximum: 32000000
+
+ dc-gpios:
+ maxItems: 1
+ description: Display data/command selection (D/CX)
+
+ backlight: true
+ reg: true
+ reset-gpios: true
+ rotation: true
+
+required:
+ - compatible
+ - reg
+ - dc-gpios
+ - reset-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ backlight: backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ };
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+
+ display@0{
+ compatible = "waveshare,rpi-lcd-35", "ilitek,ili9486";
+ reg = <0>;
+ spi-max-frequency = <32000000>;
+ dc-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+ rotation = <180>;
+ backlight = <&backlight>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/mediatek/mediatek,dpi.txt b/dts/Bindings/display/mediatek/mediatek,dpi.txt
index b6a7e73..58914cf 100644
--- a/dts/Bindings/display/mediatek/mediatek,dpi.txt
+++ b/dts/Bindings/display/mediatek/mediatek,dpi.txt
@@ -7,6 +7,7 @@ output bus.
Required properties:
- compatible: "mediatek,<chip>-dpi"
+ the supported chips are mt2701 , mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
diff --git a/dts/Bindings/display/msm/gmu.txt b/dts/Bindings/display/msm/gmu.txt
deleted file mode 100644
index bf9c7a2..0000000
--- a/dts/Bindings/display/msm/gmu.txt
+++ /dev/null
@@ -1,116 +0,0 @@
-Qualcomm adreno/snapdragon GMU (Graphics management unit)
-
-The GMU is a programmable power controller for the GPU. the CPU controls the
-GMU which in turn handles power controls for the GPU.
-
-Required properties:
-- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
- for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
- Note that you need to list the less specific "qcom,adreno-gmu"
- for generic matches and the more specific identifier to identify
- the specific device.
-- reg: Physical base address and length of the GMU registers.
-- reg-names: Matching names for the register regions
- * "gmu"
- * "gmu_pdc"
- * "gmu_pdc_seg"
-- interrupts: The interrupt signals from the GMU.
-- interrupt-names: Matching names for the interrupts
- * "hfi"
- * "gmu"
-- clocks: phandles to the device clocks
-- clock-names: Matching names for the clocks
- * "gmu"
- * "cxo"
- * "axi"
- * "mnoc"
-- power-domains: should be:
- <&clock_gpucc GPU_CX_GDSC>
- <&clock_gpucc GPU_GX_GDSC>
-- power-domain-names: Matching names for the power domains
-- iommus: phandle to the adreno iommu
-- operating-points-v2: phandle to the OPP operating points
-
-Optional properties:
-- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
- SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
-
-Example:
-
-/ {
- ...
-
- gmu: gmu@506a000 {
- compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
-
- reg = <0x506a000 0x30000>,
- <0xb280000 0x10000>,
- <0xb480000 0x10000>;
- reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
-
- interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hfi", "gmu";
-
- clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
- <&gpucc GPU_CC_CXO_CLK>,
- <&gcc GCC_DDRSS_GPU_AXI_CLK>,
- <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
- clock-names = "gmu", "cxo", "axi", "memnoc";
-
- power-domains = <&gpucc GPU_CX_GDSC>,
- <&gpucc GPU_GX_GDSC>;
- power-domain-names = "cx", "gx";
-
- iommus = <&adreno_smmu 5>;
-
- operating-points-v2 = <&gmu_opp_table>;
- };
-};
-
-a3xx example with OCMEM support:
-
-/ {
- ...
-
- gpu: adreno@fdb00000 {
- compatible = "qcom,adreno-330.2",
- "qcom,adreno";
- reg = <0xfdb00000 0x10000>;
- reg-names = "kgsl_3d0_reg_memory";
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "kgsl_3d0_irq";
- clock-names = "core",
- "iface",
- "mem_iface";
- clocks = <&mmcc OXILI_GFX3D_CLK>,
- <&mmcc OXILICX_AHB_CLK>,
- <&mmcc OXILICX_AXI_CLK>;
- sram = <&gmu_sram>;
- power-domains = <&mmcc OXILICX_GDSC>;
- operating-points-v2 = <&gpu_opp_table>;
- iommus = <&gpu_iommu 0>;
- };
-
- ocmem@fdd00000 {
- compatible = "qcom,msm8974-ocmem";
-
- reg = <0xfdd00000 0x2000>,
- <0xfec00000 0x180000>;
- reg-names = "ctrl",
- "mem";
-
- clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
- <&mmcc OCMEMCX_OCMEMNOC_CLK>;
- clock-names = "core",
- "iface";
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- gmu_sram: gmu-sram@0 {
- reg = <0x0 0x100000>;
- ranges = <0 0 0xfec00000 0x100000>;
- };
- };
-};
diff --git a/dts/Bindings/display/msm/gmu.yaml b/dts/Bindings/display/msm/gmu.yaml
new file mode 100644
index 0000000..0b8736a
--- /dev/null
+++ b/dts/Bindings/display/msm/gmu.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
+%YAML 1.2
+---
+
+$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Devicetree bindings for the GMU attached to certain Adreno GPUs
+
+maintainers:
+ - Rob Clark <robdclark@gmail.com>
+
+description: |
+ These bindings describe the Graphics Management Unit (GMU) that is attached
+ to members of the Adreno A6xx GPU family. The GMU provides on-device power
+ management and support to improve power efficiency and reduce the load on
+ the CPU.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,adreno-gmu-630.2
+ - const: qcom,adreno-gmu
+
+ reg:
+ items:
+ - description: Core GMU registers
+ - description: GMU PDC registers
+ - description: GMU PDC sequence registers
+
+ reg-names:
+ items:
+ - const: gmu
+ - const: gmu_pdc
+ - const: gmu_pdc_seq
+
+ clocks:
+ items:
+ - description: GMU clock
+ - description: GPU CX clock
+ - description: GPU AXI clock
+ - description: GPU MEMNOC clock
+
+ clock-names:
+ items:
+ - const: gmu
+ - const: cxo
+ - const: axi
+ - const: memnoc
+
+ interrupts:
+ items:
+ - description: GMU HFI interrupt
+ - description: GMU interrupt
+
+
+ interrupt-names:
+ items:
+ - const: hfi
+ - const: gmu
+
+ power-domains:
+ items:
+ - description: CX power domain
+ - description: GX power domain
+
+ power-domain-names:
+ items:
+ - const: cx
+ - const: gx
+
+ iommus:
+ maxItems: 1
+
+ operating-points-v2: true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - power-domains
+ - power-domain-names
+ - iommus
+ - operating-points-v2
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ gmu: gmu@506a000 {
+ compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
+
+ reg = <0x506a000 0x30000>,
+ <0xb280000 0x10000>,
+ <0xb480000 0x10000>;
+ reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ clock-names = "gmu", "cxo", "axi", "memnoc";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ power-domains = <&gpucc GPU_CX_GDSC>,
+ <&gpucc GPU_GX_GDSC>;
+ power-domain-names = "cx", "gx";
+
+ iommus = <&adreno_smmu 5>;
+ operating-points-v2 = <&gmu_opp_table>;
+ };
diff --git a/dts/Bindings/display/msm/gpu.txt b/dts/Bindings/display/msm/gpu.txt
index 7edc298..fd779cd 100644
--- a/dts/Bindings/display/msm/gpu.txt
+++ b/dts/Bindings/display/msm/gpu.txt
@@ -35,25 +35,54 @@ Required properties:
bring the GPU out of secure mode.
- firmware-name: optional property of the 'zap-shader' node, listing the
relative path of the device specific zap firmware.
+- sram: phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
+ a4xx Snapdragon SoCs. See
+ Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
-Example 3xx/4xx/a5xx:
+Example 3xx/4xx:
/ {
...
- gpu: qcom,kgsl-3d0@4300000 {
- compatible = "qcom,adreno-320.2", "qcom,adreno";
- reg = <0x04300000 0x20000>;
+ gpu: adreno@fdb00000 {
+ compatible = "qcom,adreno-330.2",
+ "qcom,adreno";
+ reg = <0xfdb00000 0x10000>;
reg-names = "kgsl_3d0_reg_memory";
- interrupts = <GIC_SPI 80 0>;
- clock-names =
- "core",
- "iface",
- "mem_iface";
- clocks =
- <&mmcc GFX3D_CLK>,
- <&mmcc GFX3D_AHB_CLK>,
- <&mmcc MMSS_IMEM_AHB_CLK>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+ clock-names = "core",
+ "iface",
+ "mem_iface";
+ clocks = <&mmcc OXILI_GFX3D_CLK>,
+ <&mmcc OXILICX_AHB_CLK>,
+ <&mmcc OXILICX_AXI_CLK>;
+ sram = <&gpu_sram>;
+ power-domains = <&mmcc OXILICX_GDSC>;
+ operating-points-v2 = <&gpu_opp_table>;
+ iommus = <&gpu_iommu 0>;
+ };
+
+ gpu_sram: ocmem@fdd00000 {
+ compatible = "qcom,msm8974-ocmem";
+
+ reg = <0xfdd00000 0x2000>,
+ <0xfec00000 0x180000>;
+ reg-names = "ctrl",
+ "mem";
+
+ clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
+ <&mmcc OCMEMCX_OCMEMNOC_CLK>;
+ clock-names = "core",
+ "iface";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpu_sram: gpu-sram@0 {
+ reg = <0x0 0x100000>;
+ ranges = <0 0 0xfec00000 0x100000>;
+ };
};
};
diff --git a/dts/Bindings/display/panel/advantech,idk-1110wr.yaml b/dts/Bindings/display/panel/advantech,idk-1110wr.yaml
new file mode 100644
index 0000000..93878c2
--- /dev/null
+++ b/dts/Bindings/display/panel/advantech,idk-1110wr.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/advantech,idk-1110wr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Advantech IDK-1110WR 10.1" WSVGA LVDS Display Panel
+
+maintainers:
+ - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+allOf:
+ - $ref: lvds.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: advantech,idk-1110wr
+ - {} # panel-lvds, but not listed here to avoid false select
+
+ data-mapping:
+ const: jeida-24
+
+ width-mm:
+ const: 223
+
+ height-mm:
+ const: 125
+
+ panel-timing: true
+ port: true
+
+additionalProperties: false
+
+required:
+ - compatible
+
+examples:
+ - |+
+ panel {
+ compatible = "advantech,idk-1110wr", "panel-lvds";
+
+ width-mm = <223>;
+ height-mm = <125>;
+
+ data-mapping = "jeida-24";
+
+ panel-timing {
+ /* 1024x600 @60Hz */
+ clock-frequency = <51200000>;
+ hactive = <1024>;
+ vactive = <600>;
+ hsync-len = <240>;
+ hfront-porch = <40>;
+ hback-porch = <40>;
+ vsync-len = <10>;
+ vfront-porch = <15>;
+ vback-porch = <10>;
+ };
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds_encoder>;
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/panel/advantech,idk-2121wr.yaml b/dts/Bindings/display/panel/advantech,idk-2121wr.yaml
new file mode 100644
index 0000000..6b7fddc
--- /dev/null
+++ b/dts/Bindings/display/panel/advantech,idk-2121wr.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/advantech,idk-2121wr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Advantech IDK-2121WR 21.5" Full-HD dual-LVDS panel
+
+maintainers:
+ - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+description: |
+ The IDK-2121WR from Advantech is a Full-HD dual-LVDS panel.
+ A dual-LVDS interface is a dual-link connection with even pixels traveling
+ on one link, and with odd pixels traveling on the other link.
+
+ The panel expects odd pixels on the first port, and even pixels on the
+ second port, therefore the ports must be marked accordingly (with either
+ dual-lvds-odd-pixels or dual-lvds-even-pixels).
+
+properties:
+ compatible:
+ items:
+ - const: advantech,idk-2121wr
+ - {} # panel-lvds, but not listed here to avoid false select
+
+ width-mm:
+ const: 476
+
+ height-mm:
+ const: 268
+
+ data-mapping:
+ const: vesa-24
+
+ panel-timing: true
+
+ ports:
+ type: object
+ properties:
+ port@0:
+ type: object
+ description: The sink for odd pixels.
+ properties:
+ reg:
+ const: 0
+
+ dual-lvds-odd-pixels: true
+
+ required:
+ - reg
+ - dual-lvds-odd-pixels
+
+ port@1:
+ type: object
+ description: The sink for even pixels.
+ properties:
+ reg:
+ const: 1
+
+ dual-lvds-even-pixels: true
+
+ required:
+ - reg
+ - dual-lvds-even-pixels
+
+additionalProperties: false
+
+required:
+ - compatible
+ - width-mm
+ - height-mm
+ - data-mapping
+ - panel-timing
+ - ports
+
+examples:
+ - |+
+ panel-lvds {
+ compatible = "advantech,idk-2121wr", "panel-lvds";
+
+ width-mm = <476>;
+ height-mm = <268>;
+
+ data-mapping = "vesa-24";
+
+ panel-timing {
+ clock-frequency = <148500000>;
+ hactive = <1920>;
+ vactive = <1080>;
+ hsync-len = <44>;
+ hfront-porch = <88>;
+ hback-porch = <148>;
+ vfront-porch = <4>;
+ vback-porch = <36>;
+ vsync-len = <5>;
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dual-lvds-odd-pixels;
+ panel_in0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dual-lvds-even-pixels;
+ panel_in1: endpoint {
+ remote-endpoint = <&lvds1_out>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/panel/auo,b080uan01.txt b/dts/Bindings/display/panel/auo,b080uan01.txt
deleted file mode 100644
index bae0e2b..0000000
--- a/dts/Bindings/display/panel/auo,b080uan01.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-AU Optronics Corporation 8.0" WUXGA TFT LCD panel
-
-Required properties:
-- compatible: should be "auo,b101ean01"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/auo,b101aw03.txt b/dts/Bindings/display/panel/auo,b101aw03.txt
deleted file mode 100644
index 72e088a..0000000
--- a/dts/Bindings/display/panel/auo,b101aw03.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-AU Optronics Corporation 10.1" WSVGA TFT LCD panel
-
-Required properties:
-- compatible: should be "auo,b101aw03"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/auo,b101ean01.txt b/dts/Bindings/display/panel/auo,b101ean01.txt
deleted file mode 100644
index 3590b07..0000000
--- a/dts/Bindings/display/panel/auo,b101ean01.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-AU Optronics Corporation 10.1" WSVGA TFT LCD panel
-
-Required properties:
-- compatible: should be "auo,b101ean01"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/auo,b101xtn01.txt b/dts/Bindings/display/panel/auo,b101xtn01.txt
deleted file mode 100644
index 889d511..0000000
--- a/dts/Bindings/display/panel/auo,b101xtn01.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-AU Optronics Corporation 10.1" WXGA TFT LCD panel
-
-Required properties:
-- compatible: should be "auo,b101xtn01"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/auo,b116xw03.txt b/dts/Bindings/display/panel/auo,b116xw03.txt
deleted file mode 100644
index 690d0a5..0000000
--- a/dts/Bindings/display/panel/auo,b116xw03.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-AU Optronics Corporation 11.6" HD (1366x768) color TFT-LCD panel
-
-Required properties:
-- compatible: should be "auo,b116xw03"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/auo,b133htn01.txt b/dts/Bindings/display/panel/auo,b133htn01.txt
deleted file mode 100644
index 302226b..0000000
--- a/dts/Bindings/display/panel/auo,b133htn01.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel
-
-Required properties:
-- compatible: should be "auo,b133htn01"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/auo,b133xtn01.txt b/dts/Bindings/display/panel/auo,b133xtn01.txt
deleted file mode 100644
index 7443b7c..0000000
--- a/dts/Bindings/display/panel/auo,b133xtn01.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-AU Optronics Corporation 13.3" WXGA (1366x768) TFT LCD panel
-
-Required properties:
-- compatible: should be "auo,b133xtn01"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/auo,g070vvn01.txt b/dts/Bindings/display/panel/auo,g070vvn01.txt
deleted file mode 100644
index 49e4105..0000000
--- a/dts/Bindings/display/panel/auo,g070vvn01.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-AU Optronics Corporation 7.0" FHD (800 x 480) TFT LCD panel
-
-Required properties:
-- compatible: should be "auo,g070vvn01"
-- backlight: phandle of the backlight device attached to the panel
-- power-supply: single regulator to provide the supply voltage
-
-Required nodes:
-- port: Parallel port mapping to connect this display
-
-This panel needs single power supply voltage. Its backlight is conntrolled
-via PWM signal.
-
-Example:
---------
-
-Example device-tree definition when connected to iMX6Q based board
-
- lcd_panel: lcd-panel {
- compatible = "auo,g070vvn01";
- backlight = <&backlight_lcd>;
- power-supply = <&reg_display>;
-
- port {
- lcd_panel_in: endpoint {
- remote-endpoint = <&lcd_display_out>;
- };
- };
- };
diff --git a/dts/Bindings/display/panel/auo,g101evn010.txt b/dts/Bindings/display/panel/auo,g101evn010.txt
deleted file mode 100644
index bc6a0c8..0000000
--- a/dts/Bindings/display/panel/auo,g101evn010.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-AU Optronics Corporation 10.1" (1280x800) color TFT LCD panel
-
-Required properties:
-- compatible: should be "auo,g101evn010"
-- power-supply: as specified in the base binding
-
-Optional properties:
-- backlight: as specified in the base binding
-- enable-gpios: as specified in the base binding
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/auo,g104sn02.txt b/dts/Bindings/display/panel/auo,g104sn02.txt
deleted file mode 100644
index 85626ed..0000000
--- a/dts/Bindings/display/panel/auo,g104sn02.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-AU Optronics Corporation 10.4" (800x600) color TFT LCD panel
-
-Required properties:
-- compatible: should be "auo,g104sn02"
-- power-supply: as specified in the base binding
-
-Optional properties:
-- backlight: as specified in the base binding
-- enable-gpios: as specified in the base binding
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/auo,g133han01.txt b/dts/Bindings/display/panel/auo,g133han01.txt
deleted file mode 100644
index 3afc767..0000000
--- a/dts/Bindings/display/panel/auo,g133han01.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-AU Optronics Corporation 13.3" FHD (1920x1080) TFT LCD panel
-
-Required properties:
-- compatible: should be "auo,g133han01"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/auo,g185han01.txt b/dts/Bindings/display/panel/auo,g185han01.txt
deleted file mode 100644
index ed657c2..0000000
--- a/dts/Bindings/display/panel/auo,g185han01.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-AU Optronics Corporation 18.5" FHD (1920x1080) TFT LCD panel
-
-Required properties:
-- compatible: should be "auo,g185han01"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/auo,p320hvn03.txt b/dts/Bindings/display/panel/auo,p320hvn03.txt
deleted file mode 100644
index 59bb6cd..0000000
--- a/dts/Bindings/display/panel/auo,p320hvn03.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-AU Optronics Corporation 31.5" FHD (1920x1080) TFT LCD panel
-
-Required properties:
-- compatible: should be "auo,p320hvn03"
-- power-supply: as specified in the base binding
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/auo,t215hvn01.txt b/dts/Bindings/display/panel/auo,t215hvn01.txt
deleted file mode 100644
index cbd9da3..0000000
--- a/dts/Bindings/display/panel/auo,t215hvn01.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-AU Optronics Corporation 21.5" FHD (1920x1080) color TFT LCD panel
-
-Required properties:
-- compatible: should be "auo,t215hvn01"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/avic,tm070ddh03.txt b/dts/Bindings/display/panel/avic,tm070ddh03.txt
deleted file mode 100644
index b6f2f3e..0000000
--- a/dts/Bindings/display/panel/avic,tm070ddh03.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel
-
-Required properties:
-- compatible: should be "avic,tm070ddh03"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/boe,hv070wsa-100.txt b/dts/Bindings/display/panel/boe,hv070wsa-100.txt
deleted file mode 100644
index 55183d3..0000000
--- a/dts/Bindings/display/panel/boe,hv070wsa-100.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-BOE HV070WSA-100 7.01" WSVGA TFT LCD panel
-
-Required properties:
-- compatible: should be "boe,hv070wsa-100"
-- power-supply: regulator to provide the VCC supply voltage (3.3 volts)
-- enable-gpios: GPIO pin to enable and disable panel (active high)
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
-
-The device node can contain one 'port' child node with one child
-'endpoint' node, according to the bindings defined in [1]. This
-node should describe panel's video bus.
-
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
-
-Example:
-
- panel: panel {
- compatible = "boe,hv070wsa-100";
- power-supply = <&vcc_3v3_reg>;
- enable-gpios = <&gpd1 3 GPIO_ACTIVE_HIGH>;
- port {
- panel_ep: endpoint {
- remote-endpoint = <&bridge_out_ep>;
- };
- };
- };
diff --git a/dts/Bindings/display/panel/boe,nv101wxmn51.txt b/dts/Bindings/display/panel/boe,nv101wxmn51.txt
deleted file mode 100644
index b258d6a..0000000
--- a/dts/Bindings/display/panel/boe,nv101wxmn51.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel
-
-Required properties:
-- compatible: should be "boe,nv101wxmn51"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/boe,tv080wum-nl0.txt b/dts/Bindings/display/panel/boe,tv080wum-nl0.txt
deleted file mode 100644
index 50be5e2..0000000
--- a/dts/Bindings/display/panel/boe,tv080wum-nl0.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Boe Corporation 8.0" WUXGA TFT LCD panel
-
-Required properties:
-- compatible: should be "boe,tv080wum-nl0"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/boe,tv101wum-nl6.yaml b/dts/Bindings/display/panel/boe,tv101wum-nl6.yaml
new file mode 100644
index 0000000..7402134
--- /dev/null
+++ b/dts/Bindings/display/panel/boe,tv101wum-nl6.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/boe,tv101wum-nl6.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: BOE TV101WUM-NL6 DSI Display Panel
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Sam Ravnborg <sam@ravnborg.org>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ # BOE TV101WUM-NL6 10.1" WUXGA TFT LCD panel
+ - boe,tv101wum-nl6
+ # AUO KD101N80-45NA 10.1" WUXGA TFT LCD panel
+ - auo,kd101n80-45na
+ # BOE TV101WUM-N53 10.1" WUXGA TFT LCD panel
+ - boe,tv101wum-n53
+ # AUO B101UAN08.3 10.1" WUXGA TFT LCD panel
+ - auo,b101uan08.3
+
+ reg:
+ description: the virtual channel number of a DSI peripheral
+
+ enable-gpios:
+ description: a GPIO spec for the enable pin
+
+ pp1800-supply:
+ description: core voltage supply
+
+ avdd-supply:
+ description: phandle of the regulator that provides positive voltage
+
+ avee-supply:
+ description: phandle of the regulator that provides negative voltage
+
+ backlight:
+ description: phandle of the backlight device attached to the panel
+
+ port: true
+
+required:
+ - compatible
+ - reg
+ - enable-gpios
+ - pp1800-supply
+ - avdd-supply
+ - avee-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "boe,tv101wum-nl6";
+ reg = <0>;
+ enable-gpios = <&pio 45 0>;
+ avdd-supply = <&ppvarn_lcd>;
+ avee-supply = <&ppvarp_lcd>;
+ pp1800-supply = <&pp1800_lcd>;
+ backlight = <&backlight_lcd0>;
+ status = "okay";
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/panel/cdtech,s043wq26h-ct7.txt b/dts/Bindings/display/panel/cdtech,s043wq26h-ct7.txt
deleted file mode 100644
index 057f7f3..0000000
--- a/dts/Bindings/display/panel/cdtech,s043wq26h-ct7.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-CDTech(H.K.) Electronics Limited 4.3" 480x272 color TFT-LCD panel
-
-Required properties:
-- compatible: should be "cdtech,s043wq26h-ct7"
-- power-supply: as specified in the base binding
-
-Optional properties:
-- backlight: as specified in the base binding
-- enable-gpios: as specified in the base binding
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/cdtech,s070wv95-ct16.txt b/dts/Bindings/display/panel/cdtech,s070wv95-ct16.txt
deleted file mode 100644
index 505615d..0000000
--- a/dts/Bindings/display/panel/cdtech,s070wv95-ct16.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-CDTech(H.K.) Electronics Limited 7" 800x480 color TFT-LCD panel
-
-Required properties:
-- compatible: should be "cdtech,s070wv95-ct16"
-- power-supply: as specified in the base binding
-
-Optional properties:
-- backlight: as specified in the base binding
-- enable-gpios: as specified in the base binding
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/chunghwa,claa070wp03xg.txt b/dts/Bindings/display/panel/chunghwa,claa070wp03xg.txt
deleted file mode 100644
index dd22685d..0000000
--- a/dts/Bindings/display/panel/chunghwa,claa070wp03xg.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Chunghwa Picture Tubes Ltd. 7" WXGA TFT LCD panel
-
-Required properties:
-- compatible: should be "chunghwa,claa070wp03xg"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/chunghwa,claa101wa01a.txt b/dts/Bindings/display/panel/chunghwa,claa101wa01a.txt
deleted file mode 100644
index f24614e..0000000
--- a/dts/Bindings/display/panel/chunghwa,claa101wa01a.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel
-
-Required properties:
-- compatible: should be "chunghwa,claa101wa01a"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/chunghwa,claa101wb03.txt b/dts/Bindings/display/panel/chunghwa,claa101wb03.txt
deleted file mode 100644
index 0ab2c05..0000000
--- a/dts/Bindings/display/panel/chunghwa,claa101wb03.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel
-
-Required properties:
-- compatible: should be "chunghwa,claa101wb03"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/dataimage,scf0700c48ggu18.txt b/dts/Bindings/display/panel/dataimage,scf0700c48ggu18.txt
deleted file mode 100644
index 897085e..0000000
--- a/dts/Bindings/display/panel/dataimage,scf0700c48ggu18.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface.
-
-Required properties:
-- compatible: should be "dataimage,scf0700c48ggu18"
-- power-supply: as specified in the base binding
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/display-timing.txt b/dts/Bindings/display/panel/display-timing.txt
index 78222ce..7f55ad4 100644
--- a/dts/Bindings/display/panel/display-timing.txt
+++ b/dts/Bindings/display/panel/display-timing.txt
@@ -1,123 +1 @@
-display-timing bindings
-=======================
-
-display-timings node
---------------------
-
-required properties:
- - none
-
-optional properties:
- - native-mode: The native mode for the display, in case multiple modes are
- provided. When omitted, assume the first node is the native.
-
-timing subnode
---------------
-
-required properties:
- - hactive, vactive: display resolution
- - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters
- in pixels
- vfront-porch, vback-porch, vsync-len: vertical display timing parameters in
- lines
- - clock-frequency: display clock in Hz
-
-optional properties:
- - hsync-active: hsync pulse is active low/high/ignored
- - vsync-active: vsync pulse is active low/high/ignored
- - de-active: data-enable pulse is active low/high/ignored
- - pixelclk-active: with
- - active high = drive pixel data on rising edge/
- sample data on falling edge
- - active low = drive pixel data on falling edge/
- sample data on rising edge
- - ignored = ignored
- - syncclk-active: with
- - active high = drive sync on rising edge/
- sample sync on falling edge of pixel
- clock
- - active low = drive sync on falling edge/
- sample sync on rising edge of pixel
- clock
- - omitted = same configuration as pixelclk-active
- - interlaced (bool): boolean to enable interlaced mode
- - doublescan (bool): boolean to enable doublescan mode
- - doubleclk (bool): boolean to enable doubleclock mode
-
-All the optional properties that are not bool follow the following logic:
- <1>: high active
- <0>: low active
- omitted: not used on hardware
-
-There are different ways of describing the capabilities of a display. The
-devicetree representation corresponds to the one commonly found in datasheets
-for displays. If a display supports multiple signal timings, the native-mode
-can be specified.
-
-The parameters are defined as:
-
- +----------+-------------------------------------+----------+-------+
- | | ^ | | |
- | | |vback_porch | | |
- | | v | | |
- +----------#######################################----------+-------+
- | # ^ # | |
- | # | # | |
- | hback # | # hfront | hsync |
- | porch # | hactive # porch | len |
- |<-------->#<-------+--------------------------->#<-------->|<----->|
- | # | # | |
- | # |vactive # | |
- | # | # | |
- | # v # | |
- +----------#######################################----------+-------+
- | | ^ | | |
- | | |vfront_porch | | |
- | | v | | |
- +----------+-------------------------------------+----------+-------+
- | | ^ | | |
- | | |vsync_len | | |
- | | v | | |
- +----------+-------------------------------------+----------+-------+
-
-Note: In addition to being used as subnode(s) of display-timings, the timing
- subnode may also be used on its own. This is appropriate if only one mode
- need be conveyed. In this case, the node should be named 'panel-timing'.
-
-
-Example:
-
- display-timings {
- native-mode = <&timing0>;
- timing0: 1080p24 {
- /* 1920x1080p24 */
- clock-frequency = <52000000>;
- hactive = <1920>;
- vactive = <1080>;
- hfront-porch = <25>;
- hback-porch = <25>;
- hsync-len = <25>;
- vback-porch = <2>;
- vfront-porch = <2>;
- vsync-len = <2>;
- hsync-active = <1>;
- };
- };
-
-Every required property also supports the use of ranges, so the commonly used
-datasheet description with minimum, typical and maximum values can be used.
-
-Example:
-
- timing1: timing {
- /* 1920x1080p24 */
- clock-frequency = <148500000>;
- hactive = <1920>;
- vactive = <1080>;
- hsync-len = <0 44 60>;
- hfront-porch = <80 88 95>;
- hback-porch = <100 148 160>;
- vfront-porch = <0 4 6>;
- vback-porch = <0 36 50>;
- vsync-len = <0 5 6>;
- };
+See display-timings.yaml in this directory.
diff --git a/dts/Bindings/display/panel/display-timings.yaml b/dts/Bindings/display/panel/display-timings.yaml
new file mode 100644
index 0000000..c8c0c9c
--- /dev/null
+++ b/dts/Bindings/display/panel/display-timings.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/display-timings.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: display timing bindings
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+ - Sam Ravnborg <sam@ravnborg.org>
+
+description: |
+ A display panel may be able to handle several display timings,
+ with different resolutions.
+ The display-timings node makes it possible to specify the timing
+ and to specify the timing that is native for the display.
+
+properties:
+ $nodename:
+ const: display-timings
+
+ native-mode:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ The default display timing is the one specified as native-mode.
+ If no native-mode is specified then the first node is assumed the
+ native mode.
+
+patternProperties:
+ "^timing":
+ type: object
+ allOf:
+ - $ref: panel-timing.yaml#
+
+additionalProperties: false
+
+examples:
+ - |+
+
+ /*
+ * Example that specifies panel timing using minimum, typical,
+ * maximum values as commonly used in datasheet description.
+ * timing1 is the native-mode.
+ */
+ display-timings {
+ native-mode = <&timing1>;
+ timing0 {
+ /* 1920x1080p24 */
+ clock-frequency = <148500000>;
+ hactive = <1920>;
+ vactive = <1080>;
+ hsync-len = <0 44 60>;
+ hfront-porch = <80 88 95>;
+ hback-porch = <100 148 160>;
+ vfront-porch = <0 4 6>;
+ vback-porch = <0 36 50>;
+ vsync-len = <0 5 6>;
+ };
+ timing1 {
+ /* 1920x1080p24 */
+ clock-frequency = <52000000>;
+ hactive = <1920>;
+ vactive = <1080>;
+ hfront-porch = <25>;
+ hback-porch = <25>;
+ hsync-len = <0 25 25>;
+ vback-porch = <2>;
+ vfront-porch = <2>;
+ vsync-len = <2>;
+ hsync-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/panel/dlc,dlc1010gig.txt b/dts/Bindings/display/panel/dlc,dlc1010gig.txt
deleted file mode 100644
index fbf5dcd..0000000
--- a/dts/Bindings/display/panel/dlc,dlc1010gig.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel
-
-Required properties:
-- compatible: should be "dlc,dlc1010gig"
-- power-supply: See simple-panel.txt
-
-Optional properties:
-- enable-gpios: See simple-panel.txt
-- backlight: See simple-panel.txt
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/edt,et-series.txt b/dts/Bindings/display/panel/edt,et-series.txt
deleted file mode 100644
index b7ac1c7..0000000
--- a/dts/Bindings/display/panel/edt,et-series.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-Emerging Display Technology Corp. Displays
-==========================================
-
-
-Display bindings for EDT Display Technology Corp. Displays which are
-compatible with the simple-panel binding, which is specified in
-simple-panel.txt
-
-3,5" QVGA TFT Panels
---------------------
-+-----------------+---------------------+-------------------------------------+
-| Identifier | compatbile | description |
-+=================+=====================+=====================================+
-| ET035012DM6 | edt,et035012dm6 | 3.5" QVGA TFT LCD panel |
-+-----------------+---------------------+-------------------------------------+
-
-4,3" WVGA TFT Panels
---------------------
-
-+-----------------+---------------------+-------------------------------------+
-| Identifier | compatbile | description |
-+=================+=====================+=====================================+
-| ETM0430G0DH6 | edt,etm0430g0dh6 | 480x272 TFT Display |
-+-----------------+---------------------+-------------------------------------+
-
-5,7" WVGA TFT Panels
---------------------
-
-+-----------------+---------------------+-------------------------------------+
-| Identifier | compatbile | description |
-+=================+=====================+=====================================+
-| ET057090DHU | edt,et057090dhu | 5.7" VGA TFT LCD panel |
-+-----------------+---------------------+-------------------------------------+
-
-
-7,0" WVGA TFT Panels
---------------------
-
-+-----------------+---------------------+-------------------------------------+
-| Identifier | compatbile | description |
-+=================+=====================+=====================================+
-| ETM0700G0DH6 | edt,etm070080dh6 | WVGA TFT Display with capacitive |
-| | edt,etm0700g0dh6 | Touchscreen |
-+-----------------+---------------------+-------------------------------------+
-| ETM0700G0BDH6 | edt,etm070080bdh6 | Same as ETM0700G0DH6 but with |
-| | | inverted pixel clock. |
-+-----------------+---------------------+-------------------------------------+
-| ETM0700G0EDH6 | edt,etm070080edh6 | Same display as the ETM0700G0BDH6, |
-| | | but with changed Hardware for the |
-| | | backlight and the touch interface |
-+-----------------+---------------------+-------------------------------------+
-| ET070080DH6 | edt,etm070080dh6 | Same timings as the ETM0700G0DH6, |
-| | | but with resistive touch. |
-+-----------------+---------------------+-------------------------------------+
-
diff --git a/dts/Bindings/display/panel/elida,kd35t133.yaml b/dts/Bindings/display/panel/elida,kd35t133.yaml
new file mode 100644
index 0000000..aa761f6
--- /dev/null
+++ b/dts/Bindings/display/panel/elida,kd35t133.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/elida,kd35t133.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Elida KD35T133 3.5in 320x480 DSI panel
+
+maintainers:
+ - Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ const: elida,kd35t133
+ reg: true
+ backlight: true
+ reset-gpios: true
+ iovcc-supply:
+ description: regulator that supplies the iovcc voltage
+ vdd-supply:
+ description: regulator that supplies the vdd voltage
+
+required:
+ - compatible
+ - reg
+ - backlight
+ - iovcc-supply
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "elida,kd35t133";
+ reg = <0>;
+ backlight = <&backlight>;
+ iovcc-supply = <&vcc_1v8>;
+ vdd-supply = <&vcc3v3_lcd>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/panel/evervision,vgg804821.txt b/dts/Bindings/display/panel/evervision,vgg804821.txt
deleted file mode 100644
index 82d22e1..0000000
--- a/dts/Bindings/display/panel/evervision,vgg804821.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-Evervision Electronics Co. Ltd. VGG804821 5.0" WVGA TFT LCD Panel
-
-Required properties:
-- compatible: should be "evervision,vgg804821"
-- power-supply: See simple-panel.txt
-
-Optional properties:
-- backlight: See simple-panel.txt
-- enable-gpios: See simple-panel.txt
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/feixin,k101-im2ba02.yaml b/dts/Bindings/display/panel/feixin,k101-im2ba02.yaml
new file mode 100644
index 0000000..927f1ee
--- /dev/null
+++ b/dts/Bindings/display/panel/feixin,k101-im2ba02.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/feixin,k101-im2ba02.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Feixin K101 IM2BA02 10.1" MIPI-DSI LCD panel
+
+maintainers:
+ - Icenowy Zheng <icenowy@aosc.io>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ const: feixin,k101-im2ba02
+ reg: true
+ backlight: true
+ reset-gpios: true
+ avdd-supply:
+ description: regulator that supplies the AVDD voltage
+ dvdd-supply:
+ description: regulator that supplies the DVDD voltage
+ cvdd-supply:
+ description: regulator that supplies the CVDD voltage
+
+required:
+ - compatible
+ - reg
+ - avdd-supply
+ - dvdd-supply
+ - cvdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "feixin,k101-im2ba02";
+ reg = <0>;
+ avdd-supply = <&reg_dc1sw>;
+ dvdd-supply = <&reg_dc1sw>;
+ cvdd-supply = <&reg_ldo_io1>;
+ reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>;
+ backlight = <&backlight>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/panel/foxlink,fl500wvr00-a0t.txt b/dts/Bindings/display/panel/foxlink,fl500wvr00-a0t.txt
deleted file mode 100644
index b47f9d8..0000000
--- a/dts/Bindings/display/panel/foxlink,fl500wvr00-a0t.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Foxlink Group 5" WVGA TFT LCD panel
-
-Required properties:
-- compatible: should be "foxlink,fl500wvr00-a0t"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/friendlyarm,hd702e.txt b/dts/Bindings/display/panel/friendlyarm,hd702e.txt
deleted file mode 100644
index 6c9156f..0000000
--- a/dts/Bindings/display/panel/friendlyarm,hd702e.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-FriendlyELEC HD702E 800x1280 LCD panel
-
-HD702E lcd is FriendlyELEC developed eDP LCD panel with 800x1280
-resolution. It has built in Goodix, GT9271 captive touchscreen
-with backlight adjustable via PWM.
-
-Required properties:
-- compatible: should be "friendlyarm,hd702e"
-- power-supply: regulator to provide the supply voltage
-
-Optional properties:
-- backlight: phandle of the backlight device attached to the panel
-
-Optional nodes:
-- Video port for LCD panel input.
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
-
-Example:
-
- panel {
- compatible ="friendlyarm,hd702e", "simple-panel";
- backlight = <&backlight>;
- power-supply = <&vcc3v3_sys>;
-
- port {
- panel_in_edp: endpoint {
- remote-endpoint = <&edp_out_panel>;
- };
- };
- };
diff --git a/dts/Bindings/display/panel/giantplus,gpg482739qs5.txt b/dts/Bindings/display/panel/giantplus,gpg482739qs5.txt
deleted file mode 100644
index 24b0b62..0000000
--- a/dts/Bindings/display/panel/giantplus,gpg482739qs5.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-GiantPlus GPG48273QS5 4.3" (480x272) WQVGA TFT LCD panel
-
-Required properties:
-- compatible: should be "giantplus,gpg48273qs5"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/hannstar,hsd070pww1.txt b/dts/Bindings/display/panel/hannstar,hsd070pww1.txt
deleted file mode 100644
index 7da1d5c..0000000
--- a/dts/Bindings/display/panel/hannstar,hsd070pww1.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-HannStar Display Corp. HSD070PWW1 7.0" WXGA TFT LCD panel
-
-Required properties:
-- compatible: should be "hannstar,hsd070pww1"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/hannstar,hsd100pxn1.txt b/dts/Bindings/display/panel/hannstar,hsd100pxn1.txt
deleted file mode 100644
index 8270319..0000000
--- a/dts/Bindings/display/panel/hannstar,hsd100pxn1.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel
-
-Required properties:
-- compatible: should be "hannstar,hsd100pxn1"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/hit,tx23d38vm0caa.txt b/dts/Bindings/display/panel/hit,tx23d38vm0caa.txt
deleted file mode 100644
index 04caaae..0000000
--- a/dts/Bindings/display/panel/hit,tx23d38vm0caa.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel
-
-Required properties:
-- compatible: should be "hit,tx23d38vm0caa"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/innolux,at043tn24.txt b/dts/Bindings/display/panel/innolux,at043tn24.txt
deleted file mode 100644
index 4104226..0000000
--- a/dts/Bindings/display/panel/innolux,at043tn24.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Innolux AT043TN24 4.3" WQVGA TFT LCD panel
-
-Required properties:
-- compatible: should be "innolux,at043tn24"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/innolux,at070tn92.txt b/dts/Bindings/display/panel/innolux,at070tn92.txt
deleted file mode 100644
index 3e10cd7..0000000
--- a/dts/Bindings/display/panel/innolux,at070tn92.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Innolux AT070TN92 7.0" WQVGA TFT LCD panel
-
-Required properties:
-- compatible: should be "innolux,at070tn92"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/innolux,g070y2-l01.txt b/dts/Bindings/display/panel/innolux,g070y2-l01.txt
deleted file mode 100644
index 7c234cf..0000000
--- a/dts/Bindings/display/panel/innolux,g070y2-l01.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-Innolux G070Y2-L01 7" WVGA (800x480) TFT LCD panel
-
-Required properties:
-- compatible: should be "innolux,g070y2-l01"
-- power-supply: as specified in the base binding
-
-Optional properties:
-- backlight: as specified in the base binding
-- enable-gpios: as specified in the base binding
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/innolux,g101ice-l01.txt b/dts/Bindings/display/panel/innolux,g101ice-l01.txt
deleted file mode 100644
index 9e75904..0000000
--- a/dts/Bindings/display/panel/innolux,g101ice-l01.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Innolux Corporation 10.1" G101ICE-L01 WXGA (1280x800) LVDS panel
-
-Required properties:
-- compatible: should be "innolux,g101ice-l01"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/innolux,g121i1-l01.txt b/dts/Bindings/display/panel/innolux,g121i1-l01.txt
deleted file mode 100644
index 2743b07..0000000
--- a/dts/Bindings/display/panel/innolux,g121i1-l01.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Innolux Corporation 12.1" WXGA (1280x800) TFT LCD panel
-
-Required properties:
-- compatible: should be "innolux,g121i1-l01"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/innolux,g121x1-l03.txt b/dts/Bindings/display/panel/innolux,g121x1-l03.txt
deleted file mode 100644
index 6497446..0000000
--- a/dts/Bindings/display/panel/innolux,g121x1-l03.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Innolux Corporation 12.1" G121X1-L03 XGA (1024x768) TFT LCD panel
-
-Required properties:
-- compatible: should be "innolux,g121x1-l03"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/innolux,n116bge.txt b/dts/Bindings/display/panel/innolux,n116bge.txt
deleted file mode 100644
index 081bb93..0000000
--- a/dts/Bindings/display/panel/innolux,n116bge.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
-
-Required properties:
-- compatible: should be "innolux,n116bge"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/innolux,n156bge-l21.txt b/dts/Bindings/display/panel/innolux,n156bge-l21.txt
deleted file mode 100644
index 7825844..0000000
--- a/dts/Bindings/display/panel/innolux,n156bge-l21.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-InnoLux 15.6" WXGA TFT LCD panel
-
-Required properties:
-- compatible: should be "innolux,n156bge-l21"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/innolux,zj070na-01p.txt b/dts/Bindings/display/panel/innolux,zj070na-01p.txt
deleted file mode 100644
index 824f87f..0000000
--- a/dts/Bindings/display/panel/innolux,zj070na-01p.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel
-
-Required properties:
-- compatible: should be "innolux,zj070na-01p"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/koe,tx14d24vm1bpa.txt b/dts/Bindings/display/panel/koe,tx14d24vm1bpa.txt
deleted file mode 100644
index be7ac66..0000000
--- a/dts/Bindings/display/panel/koe,tx14d24vm1bpa.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel
-
-Required properties:
-- compatible: should be "koe,tx14d24vm1bpa"
-- backlight: phandle of the backlight device attached to the panel
-- power-supply: single regulator to provide the supply voltage
-
-Required nodes:
-- port: Parallel port mapping to connect this display
-
-This panel needs single power supply voltage. Its backlight is conntrolled
-via PWM signal.
-
-Example:
---------
-
-Example device-tree definition when connected to iMX53 based board
-
- lcd_panel: lcd-panel {
- compatible = "koe,tx14d24vm1bpa";
- backlight = <&backlight_lcd>;
- power-supply = <&reg_3v3>;
-
- port {
- lcd_panel_in: endpoint {
- remote-endpoint = <&lcd_display_out>;
- };
- };
- };
-
-Then one needs to extend the dispX node:
-
- lcd_display: disp1 {
-
- port@1 {
- reg = <1>;
-
- lcd_display_out: endpoint {
- remote-endpoint = <&lcd_panel_in>;
- };
- };
- };
diff --git a/dts/Bindings/display/panel/koe,tx31d200vm0baa.txt b/dts/Bindings/display/panel/koe,tx31d200vm0baa.txt
deleted file mode 100644
index 6a036ed..0000000
--- a/dts/Bindings/display/panel/koe,tx31d200vm0baa.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
-
-Required properties:
-- compatible: should be "koe,tx31d200vm0baa"
-
-Optional properties:
-- backlight: phandle of the backlight device attached to the panel
-
-Optional nodes:
-- Video port for LVDS panel input.
-
-Example:
- panel {
- compatible = "koe,tx31d200vm0baa";
- backlight = <&backlight_lvds>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&lvds0_out>;
- };
- };
- };
diff --git a/dts/Bindings/display/panel/kyo,tcg121xglp.txt b/dts/Bindings/display/panel/kyo,tcg121xglp.txt
deleted file mode 100644
index a8e940f..0000000
--- a/dts/Bindings/display/panel/kyo,tcg121xglp.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Kyocera Corporation 12.1" XGA (1024x768) TFT LCD panel
-
-Required properties:
-- compatible: should be "kyo,tcg121xglp"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/leadtek,ltk500hd1829.yaml b/dts/Bindings/display/panel/leadtek,ltk500hd1829.yaml
index a614644..fd931b2 100644
--- a/dts/Bindings/display/panel/leadtek,ltk500hd1829.yaml
+++ b/dts/Bindings/display/panel/leadtek,ltk500hd1829.yaml
@@ -34,7 +34,7 @@ additionalProperties: false
examples:
- |
- dsi@ff450000 {
+ dsi {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xff450000 0x1000>;
diff --git a/dts/Bindings/display/panel/lemaker,bl035-rgb-002.txt b/dts/Bindings/display/panel/lemaker,bl035-rgb-002.txt
deleted file mode 100644
index 74ee7ea..0000000
--- a/dts/Bindings/display/panel/lemaker,bl035-rgb-002.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-LeMaker BL035-RGB-002 3.5" QVGA TFT LCD panel
-
-Required properties:
-- compatible: should be "lemaker,bl035-rgb-002"
-- power-supply: as specified in the base binding
-
-Optional properties:
-- backlight: as specified in the base binding
-- enable-gpios: as specified in the base binding
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/lg,lb070wv8.txt b/dts/Bindings/display/panel/lg,lb070wv8.txt
deleted file mode 100644
index a7588e5..0000000
--- a/dts/Bindings/display/panel/lg,lb070wv8.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-LG 7" (800x480 pixels) TFT LCD panel
-
-Required properties:
-- compatible: should be "lg,lb070wv8"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/lg,lp079qx1-sp0v.txt b/dts/Bindings/display/panel/lg,lp079qx1-sp0v.txt
deleted file mode 100644
index b9877ac..0000000
--- a/dts/Bindings/display/panel/lg,lp079qx1-sp0v.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel
-
-Required properties:
-- compatible: should be "lg,lp079qx1-sp0v"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/lg,lp097qx1-spa1.txt b/dts/Bindings/display/panel/lg,lp097qx1-spa1.txt
deleted file mode 100644
index 4214151..0000000
--- a/dts/Bindings/display/panel/lg,lp097qx1-spa1.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-LG 9.7" (2048x1536 pixels) TFT LCD panel
-
-Required properties:
-- compatible: should be "lg,lp097qx1-spa1"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/lg,lp120up1.txt b/dts/Bindings/display/panel/lg,lp120up1.txt
deleted file mode 100644
index 8c5de69..0000000
--- a/dts/Bindings/display/panel/lg,lp120up1.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-LG 12.0" (1920x1280 pixels) TFT LCD panel
-
-Required properties:
-- compatible: should be "lg,lp120up1"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/lg,lp129qe.txt b/dts/Bindings/display/panel/lg,lp129qe.txt
deleted file mode 100644
index 9f262e0..0000000
--- a/dts/Bindings/display/panel/lg,lp129qe.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-LG 12.9" (2560x1700 pixels) TFT LCD panel
-
-Required properties:
-- compatible: should be "lg,lp129qe"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/mitsubishi,aa070mc01.txt b/dts/Bindings/display/panel/mitsubishi,aa070mc01.txt
deleted file mode 100644
index 7d8f6ee..0000000
--- a/dts/Bindings/display/panel/mitsubishi,aa070mc01.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Mitsubishi "AA070MC01 7.0" WVGA TFT LCD panel
-
-Required properties:
-- compatible: should be "mitsubishi,aa070mc01-ca1"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/nec,nl12880b20-05.txt b/dts/Bindings/display/panel/nec,nl12880b20-05.txt
deleted file mode 100644
index 71cbc49..0000000
--- a/dts/Bindings/display/panel/nec,nl12880b20-05.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel
-
-Required properties:
-- compatible: should be "nec,nl12880bc20-05"
-- power-supply: as specified in the base binding
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/nec,nl4827hc19-05b.txt b/dts/Bindings/display/panel/nec,nl4827hc19-05b.txt
deleted file mode 100644
index 8e1914d..0000000
--- a/dts/Bindings/display/panel/nec,nl4827hc19-05b.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-NEC LCD Technologies,Ltd. WQVGA TFT LCD panel
-
-Required properties:
-- compatible: should be "nec,nl4827hc19-05b"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/netron-dy,e231732.txt b/dts/Bindings/display/panel/netron-dy,e231732.txt
deleted file mode 100644
index c6d06b5..0000000
--- a/dts/Bindings/display/panel/netron-dy,e231732.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Netron-DY E231732 7.0" WSVGA TFT LCD panel
-
-Required properties:
-- compatible: should be "netron-dy,e231732"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/newhaven,nhd-4.3-480272ef-atxl.txt b/dts/Bindings/display/panel/newhaven,nhd-4.3-480272ef-atxl.txt
deleted file mode 100644
index e78292b..0000000
--- a/dts/Bindings/display/panel/newhaven,nhd-4.3-480272ef-atxl.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Newhaven Display International 480 x 272 TFT LCD panel
-
-Required properties:
-- compatible: should be "newhaven,nhd-4.3-480272ef-atxl"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/nlt,nl192108ac18-02d.txt b/dts/Bindings/display/panel/nlt,nl192108ac18-02d.txt
deleted file mode 100644
index 1a639fd..0000000
--- a/dts/Bindings/display/panel/nlt,nl192108ac18-02d.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel
-
-Required properties:
-- compatible: should be "nlt,nl192108ac18-02d"
-- power-supply: as specified in the base binding
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/novatek,nt35510.yaml b/dts/Bindings/display/panel/novatek,nt35510.yaml
new file mode 100644
index 0000000..73d2ff3
--- /dev/null
+++ b/dts/Bindings/display/panel/novatek,nt35510.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/novatek,nt35510.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Novatek NT35510-based display panels
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: hydis,hva40wv1
+ - const: novatek,nt35510
+ description: This indicates the panel manufacturer of the panel
+ that is in turn using the NT35510 panel driver. The compatible
+ string determines how the NT35510 panel driver shall be configured
+ to work with the indicated panel. The novatek,nt35510 compatible shall
+ always be provided as a fallback.
+ reg: true
+ reset-gpios: true
+ vdd-supply:
+ description: regulator that supplies the vdd voltage
+ vddi-supply:
+ description: regulator that supplies the vddi voltage
+ backlight: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "hydis,hva40wv1", "novatek,nt35510";
+ reg = <0>;
+ vdd-supply = <&ab8500_ldo_aux4_reg>;
+ vddi-supply = <&ab8500_ldo_aux6_reg>;
+ reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ backlight = <&gpio_bl>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/panel/nvd,9128.txt b/dts/Bindings/display/panel/nvd,9128.txt
deleted file mode 100644
index 17bcd01..0000000
--- a/dts/Bindings/display/panel/nvd,9128.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-New Vision Display 7.0" 800 RGB x 480 TFT LCD panel
-
-Required properties:
-- compatible: should be "nvd,9128"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/okaya,rs800480t-7x0gp.txt b/dts/Bindings/display/panel/okaya,rs800480t-7x0gp.txt
deleted file mode 100644
index ddf8e21..0000000
--- a/dts/Bindings/display/panel/okaya,rs800480t-7x0gp.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-OKAYA Electric America, Inc. RS800480T-7X0GP 7" WVGA LCD panel
-
-Required properties:
-- compatible: should be "okaya,rs800480t-7x0gp"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt b/dts/Bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt
deleted file mode 100644
index 74540a0..0000000
--- a/dts/Bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Olimex 4.3" TFT LCD panel
-
-Required properties:
-- compatible: should be "olimex,lcd-olinuxino-43-ts"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/ontat,yx700wv03.txt b/dts/Bindings/display/panel/ontat,yx700wv03.txt
deleted file mode 100644
index 3d8a5e0..0000000
--- a/dts/Bindings/display/panel/ontat,yx700wv03.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-On Tat Industrial Company 7" DPI TFT panel.
-
-Required properties:
-- compatible: should be "ontat,yx700wv03"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/orisetech,otm8009a.txt b/dts/Bindings/display/panel/orisetech,otm8009a.txt
deleted file mode 100644
index 203b03e..0000000
--- a/dts/Bindings/display/panel/orisetech,otm8009a.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode)
-
-The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using
-a MIPI-DSI video interface. Its backlight is managed through the DSI link.
-
-Required properties:
- - compatible: "orisetech,otm8009a"
- - reg: the virtual channel number of a DSI peripheral
-
-Optional properties:
- - reset-gpios: a GPIO spec for the reset pin (active low).
- - power-supply: phandle of the regulator that provides the supply voltage.
-
-Example:
-&dsi {
- ...
- panel@0 {
- compatible = "orisetech,otm8009a";
- reg = <0>;
- reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
- power-supply = <&v1v8>;
- };
-};
diff --git a/dts/Bindings/display/panel/orisetech,otm8009a.yaml b/dts/Bindings/display/panel/orisetech,otm8009a.yaml
new file mode 100644
index 0000000..4b6dda6
--- /dev/null
+++ b/dts/Bindings/display/panel/orisetech,otm8009a.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/orisetech,otm8009a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode)
+
+maintainers:
+ - Philippe CORNU <philippe.cornu@st.com>
+
+description: |
+ The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using
+ a MIPI-DSI video interface. Its backlight is managed through the DSI link.
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+
+ compatible:
+ const: orisetech,otm8009a
+
+ reg:
+ maxItems: 1
+ description: DSI virtual channel
+
+ enable-gpios: true
+ port: true
+ power-supply: true
+
+ reset-gpios:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "orisetech,otm8009a";
+ reg = <0>;
+ reset-gpios = <&gpiof 15 0>;
+ power-supply = <&v1v8>;
+ };
+ };
+...
+
diff --git a/dts/Bindings/display/panel/ortustech,com37h3m05dtc.txt b/dts/Bindings/display/panel/ortustech,com37h3m05dtc.txt
deleted file mode 100644
index c16907c..0000000
--- a/dts/Bindings/display/panel/ortustech,com37h3m05dtc.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-OrtusTech COM37H3M05DTC Blanview 3.7" VGA portrait TFT-LCD panel
-
-Required properties:
-- compatible: should be "ortustech,com37h3m05dtc"
-
-Optional properties:
-- enable-gpios: GPIO pin to enable or disable the panel
-- backlight: phandle of the backlight device attached to the panel
-- power-supply: phandle of the regulator that provides the supply voltage
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/ortustech,com37h3m99dtc.txt b/dts/Bindings/display/panel/ortustech,com37h3m99dtc.txt
deleted file mode 100644
index 06a73c3..0000000
--- a/dts/Bindings/display/panel/ortustech,com37h3m99dtc.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-OrtusTech COM37H3M99DTC Blanview 3.7" VGA portrait TFT-LCD panel
-
-Required properties:
-- compatible: should be "ortustech,com37h3m99dtc"
-
-Optional properties:
-- enable-gpios: GPIO pin to enable or disable the panel
-- backlight: phandle of the backlight device attached to the panel
-- power-supply: phandle of the regulator that provides the supply voltage
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/ortustech,com43h4m85ulc.txt b/dts/Bindings/display/panel/ortustech,com43h4m85ulc.txt
deleted file mode 100644
index de19e93..0000000
--- a/dts/Bindings/display/panel/ortustech,com43h4m85ulc.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-OrtusTech COM43H4M85ULC Blanview 3.7" TFT-LCD panel
-
-Required properties:
-- compatible: should be "ortustech,com43h4m85ulc"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/osddisplays,osd070t1718-19ts.txt b/dts/Bindings/display/panel/osddisplays,osd070t1718-19ts.txt
deleted file mode 100644
index e57883c..0000000
--- a/dts/Bindings/display/panel/osddisplays,osd070t1718-19ts.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-OSD Displays OSD070T1718-19TS 7" WVGA TFT LCD panel
-
-Required properties:
-- compatible: shall be "osddisplays,osd070t1718-19ts"
-- power-supply: see simple-panel.txt
-
-Optional properties:
-- backlight: see simple-panel.txt
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory. No other simple-panel properties than
-the ones specified herein are valid.
diff --git a/dts/Bindings/display/panel/osddisplays,osd101t2045-53ts.txt b/dts/Bindings/display/panel/osddisplays,osd101t2045-53ts.txt
deleted file mode 100644
index 85c0b2c..0000000
--- a/dts/Bindings/display/panel/osddisplays,osd101t2045-53ts.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-One Stop Displays OSD101T2045-53TS 10.1" 1920x1200 panel
-
-Required properties:
-- compatible: should be "osddisplays,osd101t2045-53ts"
-- power-supply: as specified in the base binding
-
-Optional properties:
-- backlight: as specified in the base binding
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/panasonic,vvx10f004b00.txt b/dts/Bindings/display/panel/panasonic,vvx10f004b00.txt
deleted file mode 100644
index d328b03..0000000
--- a/dts/Bindings/display/panel/panasonic,vvx10f004b00.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Panasonic Corporation 10.1" WUXGA TFT LCD panel
-
-Required properties:
-- compatible: should be "panasonic,vvx10f004b00"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/panasonic,vvx10f034n00.txt b/dts/Bindings/display/panel/panasonic,vvx10f034n00.txt
deleted file mode 100644
index 37dedf6..0000000
--- a/dts/Bindings/display/panel/panasonic,vvx10f034n00.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Panasonic 10" WUXGA TFT LCD panel
-
-Required properties:
-- compatible: should be "panasonic,vvx10f034n00"
-- reg: DSI virtual channel of the peripheral
-- power-supply: phandle of the regulator that provides the supply voltage
-
-Optional properties:
-- backlight: phandle of the backlight device attached to the panel
-
-Example:
-
- mdss_dsi@fd922800 {
- panel@0 {
- compatible = "panasonic,vvx10f034n00";
- reg = <0>;
- power-supply = <&vreg_vsp>;
- backlight = <&lp8566_wled>;
- };
- };
diff --git a/dts/Bindings/display/panel/panel-common.yaml b/dts/Bindings/display/panel/panel-common.yaml
index ef8d8cd..ed051ba 100644
--- a/dts/Bindings/display/panel/panel-common.yaml
+++ b/dts/Bindings/display/panel/panel-common.yaml
@@ -54,13 +54,20 @@ properties:
# Display Timings
panel-timing:
- type: object
description:
Most display panels are restricted to a single resolution and
require specific display timings. The panel-timing subnode expresses those
- timings as specified in the timing subnode section of the display timing
- bindings defined in
- Documentation/devicetree/bindings/display/panel/display-timing.txt.
+ timings.
+ allOf:
+ - $ref: panel-timing.yaml#
+
+ display-timings:
+ description:
+ Some display panels supports several resolutions with different timing.
+ The display-timings bindings supports specifying several timings and
+ optional specify which is the native mode.
+ allOf:
+ - $ref: display-timings.yaml#
# Connectivity
port:
diff --git a/dts/Bindings/display/panel/panel-dpi.txt b/dts/Bindings/display/panel/panel-dpi.txt
deleted file mode 100644
index 6b203bc..0000000
--- a/dts/Bindings/display/panel/panel-dpi.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-Generic MIPI DPI Panel
-======================
-
-Required properties:
-- compatible: "panel-dpi"
-
-Optional properties:
-- label: a symbolic name for the panel
-- enable-gpios: panel enable gpio
-- reset-gpios: GPIO to control the RESET pin
-- vcc-supply: phandle of regulator that will be used to enable power to the display
-- backlight: phandle of the backlight device
-
-Required nodes:
-- "panel-timing" containing video timings
- (Documentation/devicetree/bindings/display/panel/display-timing.txt)
-- Video port for DPI input
-
-Example
--------
-
-lcd0: display@0 {
- compatible = "samsung,lte430wq-f0c", "panel-dpi";
- label = "lcd";
-
- backlight = <&backlight>;
-
- port {
- lcd_in: endpoint {
- remote-endpoint = <&dpi_out>;
- };
- };
-
- panel-timing {
- clock-frequency = <9200000>;
- hactive = <480>;
- vactive = <272>;
- hfront-porch = <8>;
- hback-porch = <4>;
- hsync-len = <41>;
- vback-porch = <2>;
- vfront-porch = <4>;
- vsync-len = <10>;
-
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
-};
diff --git a/dts/Bindings/display/panel/panel-dpi.yaml b/dts/Bindings/display/panel/panel-dpi.yaml
new file mode 100644
index 0000000..0cd74c8
--- /dev/null
+++ b/dts/Bindings/display/panel/panel-dpi.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/panel-dpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic MIPI DPI Panel
+
+maintainers:
+ - Sam Ravnborg <sam@ravnborg.org>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ description:
+ Shall contain a panel specific compatible and "panel-dpi"
+ in that order.
+ items:
+ - {}
+ - const: panel-dpi
+
+ backlight: true
+ enable-gpios: true
+ height-mm: true
+ label: true
+ panel-timing: true
+ port: true
+ power-supply: true
+ reset-gpios: true
+ width-mm: true
+
+required:
+ - panel-timing
+ - power-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ panel {
+ compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
+ label = "osddisplay";
+ power-supply = <&vcc_supply>;
+ backlight = <&backlight>;
+
+ port {
+ lcd_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+ panel-timing {
+ clock-frequency = <9200000>;
+ hactive = <800>;
+ vactive = <480>;
+ hfront-porch = <8>;
+ hback-porch = <4>;
+ hsync-len = <41>;
+ vback-porch = <2>;
+ vfront-porch = <4>;
+ vsync-len = <10>;
+
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/panel/panel-simple-dsi.yaml b/dts/Bindings/display/panel/panel-simple-dsi.yaml
new file mode 100644
index 0000000..b2e8742
--- /dev/null
+++ b/dts/Bindings/display/panel/panel-simple-dsi.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/panel-simple-dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Simple DSI panels with a single power-supply
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Sam Ravnborg <sam@ravnborg.org>
+
+description: |
+ This binding file is a collection of the DSI panels that
+ requires only a single power-supply.
+ There are optionally a backlight and an enable GPIO.
+ The panel may use an OF graph binding for the association to the display,
+ or it may be a direct child node of the display.
+
+ If the panel is more advanced a dedicated binding file is required.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+
+ compatible:
+ enum:
+ # compatible must be listed in alphabetical order, ordered by compatible.
+ # The description in the comment is mandatory for each compatible.
+
+ # Panasonic 10" WUXGA TFT LCD panel
+ - panasonic,vvx10f034n00
+
+ reg:
+ maxItems: 1
+ description: DSI virtual channel
+
+ backlight: true
+ enable-gpios: true
+ port: true
+ power-supply: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - power-supply
+ - reg
+
+examples:
+ - |
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "panasonic,vvx10f034n00";
+ reg = <0>;
+ power-supply = <&vcc_lcd_reg>;
+
+ port {
+ panel: endpoint {
+ remote-endpoint = <&ltdc_out>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/panel/panel-simple.yaml b/dts/Bindings/display/panel/panel-simple.yaml
index 8fe60ee..393ffc6 100644
--- a/dts/Bindings/display/panel/panel-simple.yaml
+++ b/dts/Bindings/display/panel/panel-simple.yaml
@@ -33,16 +33,225 @@ properties:
- ampire,am-480272h3tmqw-t01h
# Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel
- ampire,am800480r3tmqwa1h
+ # AU Optronics Corporation 8.0" WUXGA TFT LCD panel
+ - auo,b080uan01
+ # AU Optronics Corporation 10.1" WSVGA TFT LCD panel
+ - auo,b101aw03
+ # AU Optronics Corporation 10.1" WSVGA TFT LCD panel
+ - auo,b101ean01
+ # AU Optronics Corporation 10.1" WXGA TFT LCD panel
+ - auo,b101xtn01
# AUO B116XAK01 eDP TFT LCD panel
- auo,b116xa01
+ # AU Optronics Corporation 11.6" HD (1366x768) color TFT-LCD panel
+ - auo,b116xw03
+ # AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel
+ - auo,b133htn01
+ # AU Optronics Corporation 13.3" WXGA (1366x768) TFT LCD panel
+ - auo,b133xtn01
+ # AU Optronics Corporation 7.0" FHD (800 x 480) TFT LCD panel
+ - auo,g070vvn01
+ # AU Optronics Corporation 10.1" (1280x800) color TFT LCD panel
+ - auo,g101evn010
+ # AU Optronics Corporation 10.4" (800x600) color TFT LCD panel
+ - auo,g104sn02
+ # AU Optronics Corporation 13.3" FHD (1920x1080) TFT LCD panel
+ - auo,g133han01
+ # AU Optronics Corporation 18.5" FHD (1920x1080) TFT LCD panel
+ - auo,g185han01
+ # AU Optronics Corporation 31.5" FHD (1920x1080) TFT LCD panel
+ - auo,p320hvn03
+ # AU Optronics Corporation 21.5" FHD (1920x1080) color TFT LCD panel
+ - auo,t215hvn01
+ # Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel
+ - avic,tm070ddh03
+ # BOE HV070WSA-100 7.01" WSVGA TFT LCD panel
+ - boe,hv070wsa-100
+ # BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel
+ - boe,nv101wxmn51
# BOE NV140FHM-N49 14.0" FHD a-Si FT panel
- boe,nv140fhmn49
+ # Boe Corporation 8.0" WUXGA TFT LCD panel
+ - boe,tv080wum-nl0
+ # CDTech(H.K.) Electronics Limited 4.3" 480x272 color TFT-LCD panel
+ - cdtech,s043wq26h-ct7
+ # CDTech(H.K.) Electronics Limited 7" 800x480 color TFT-LCD panel
+ - cdtech,s070wv95-ct16
+ # Chunghwa Picture Tubes Ltd. 7" WXGA TFT LCD panel
+ - chunghwa,claa070wp03xg
+ # Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel
+ - chunghwa,claa101wa01a
+ # Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel
+ - chunghwa,claa101wb03
+ # DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface.
+ - dataimage,scf0700c48ggu18
+ # DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel
+ - dlc,dlc1010gig
+ # Emerging Display Technology Corp. 3.5" QVGA TFT LCD panel
+ - edt,et035012dm6
+ # Emerging Display Technology Corp. 480x272 TFT Display with capacitive touch
+ - edt,etm043080dh6gp
+ # Emerging Display Technology Corp. 480x272 TFT Display
+ - edt,etm0430g0dh6
+ # Emerging Display Technology Corp. 5.7" VGA TFT LCD panel
+ - edt,et057090dhu
+ # Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
+ - edt,etm070080dh6
+ # Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
+ - edt,etm0700g0dh6
+ # Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
+ # Same as ETM0700G0DH6 but with inverted pixel clock.
+ - edt,etm070080bdh6
+ # Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
+ # Same display as the ETM0700G0BDH6, but with changed hardware for the
+ # backlight and the touch interface.
+ - edt,etm070080edh6
+ # Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
+ # Same timings as the ETM0700G0DH6, but with resistive touch.
+ - edt,etm070080dh6
+ # Evervision Electronics Co. Ltd. VGG804821 5.0" WVGA TFT LCD Panel
+ - evervision,vgg804821
+ # Foxlink Group 5" WVGA TFT LCD panel
+ - foxlink,fl500wvr00-a0t
+ # Frida FRD350H54004 3.5" QVGA TFT LCD panel
+ - frida,frd350h54004
+ # FriendlyELEC HD702E 800x1280 LCD panel
+ - friendlyarm,hd702e
+ # GiantPlus GPG48273QS5 4.3" (480x272) WQVGA TFT LCD panel
+ - giantplus,gpg48273qs5
# GiantPlus GPM940B0 3.0" QVGA TFT LCD panel
- giantplus,gpm940b0
+ # HannStar Display Corp. HSD070PWW1 7.0" WXGA TFT LCD panel
+ - hannstar,hsd070pww1
+ # HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel
+ - hannstar,hsd100pxn1
+ # Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel
+ - hit,tx23d38vm0caa
+ # Innolux AT043TN24 4.3" WQVGA TFT LCD panel
+ - innolux,at043tn24
+ # Innolux AT070TN92 7.0" WQVGA TFT LCD panel
+ - innolux,at070tn92
+ # Innolux G070Y2-L01 7" WVGA (800x480) TFT LCD panel
+ - innolux,g070y2-l01
+ # Innolux Corporation 10.1" G101ICE-L01 WXGA (1280x800) LVDS panel
+ - innolux,g101ice-l01
+ # Innolux Corporation 12.1" WXGA (1280x800) TFT LCD panel
+ - innolux,g121i1-l01
+ # Innolux Corporation 12.1" G121X1-L03 XGA (1024x768) TFT LCD panel
+ - innolux,g121x1-l03
+ # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
+ - innolux,n116bge
+ # InnoLux 15.6" WXGA TFT LCD panel
+ - innolux,n156bge-l21
+ # Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel
+ - innolux,zj070na-01p
+ # Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel
+ - koe,tx14d24vm1bpa
+ # Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel
+ - koe,tx31d200vm0baa
+ # Kyocera Corporation 12.1" XGA (1024x768) TFT LCD panel
+ - kyo,tcg121xglp
+ # LeMaker BL035-RGB-002 3.5" QVGA TFT LCD panel
+ - lemaker,bl035-rgb-002
+ # LG 7" (800x480 pixels) TFT LCD panel
+ - lg,lb070wv8
+ # LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel
+ - lg,lp079qx1-sp0v
+ # LG 9.7" (2048x1536 pixels) TFT LCD panel
+ - lg,lp097qx1-spa1
+ # LG 12.0" (1920x1280 pixels) TFT LCD panel
+ - lg,lp120up1
+ # LG 12.9" (2560x1700 pixels) TFT LCD panel
+ - lg,lp129qe
+ # Logic Technologies LT161010-2NHC 7" WVGA TFT Cap Touch Module
+ - logictechno,lt161010-2nhc
+ # Logic Technologies LT161010-2NHR 7" WVGA TFT Resistive Touch Module
+ - logictechno,lt161010-2nhr
+ # Logic Technologies LT170410-2WHC 10.1" 1280x800 IPS TFT Cap Touch Mod.
+ - logictechno,lt170410-2whc
+ # Mitsubishi "AA070MC01 7.0" WVGA TFT LCD panel
+ - mitsubishi,aa070mc01-ca1
+ # NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel
+ - nec,nl12880bc20-05
+ # NEC LCD Technologies,Ltd. WQVGA TFT LCD panel
+ - nec,nl4827hc19-05b
+ # Netron-DY E231732 7.0" WSVGA TFT LCD panel
+ - netron-dy,e231732
+ # NewEast Optoelectronics CO., LTD WJFH116008A eDP TFT LCD panel
+ - neweast,wjfh116008a
+ # Newhaven Display International 480 x 272 TFT LCD panel
+ - newhaven,nhd-4.3-480272ef-atxl
+ # NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel
+ - nlt,nl192108ac18-02d
+ # New Vision Display 7.0" 800 RGB x 480 TFT LCD panel
+ - nvd,9128
+ # OKAYA Electric America, Inc. RS800480T-7X0GP 7" WVGA LCD panel
+ - okaya,rs800480t-7x0gp
+ # Olimex 4.3" TFT LCD panel
+ - olimex,lcd-olinuxino-43-ts
+ # On Tat Industrial Company 7" DPI TFT panel.
+ - ontat,yx700wv03
+ # OrtusTech COM37H3M05DTC Blanview 3.7" VGA portrait TFT-LCD panel
+ - ortustech,com37h3m05dtc
+ # OrtusTech COM37H3M99DTC Blanview 3.7" VGA portrait TFT-LCD panel
+ - ortustech,com37h3m99dtc
+ # OrtusTech COM43H4M85ULC Blanview 3.7" TFT-LCD panel
+ - ortustech,com43h4m85ulc
+ # OSD Displays OSD070T1718-19TS 7" WVGA TFT LCD panel
+ - osddisplays,osd070t1718-19ts
+ # One Stop Displays OSD101T2045-53TS 10.1" 1920x1200 panel
+ - osddisplays,osd101t2045-53ts
+ # QiaoDian XianShi Corporation 4"3 TFT LCD panel
+ - qiaodian,qd43003c0-40
+ # Rocktech Displays Ltd. RK101II01D-CT 10.1" TFT 1280x800
+ - rocktech,rk101ii01d-ct
+ # Rocktech Display Ltd. RK070ER9427 800(RGB)x480 TFT LCD panel
+ - rocktech,rk070er9427
+ # Samsung 12.2" (2560x1600 pixels) TFT LCD panel
+ - samsung,lsn122dl01-c01
+ # Samsung Electronics 10.1" WSVGA TFT LCD panel
+ - samsung,ltn101nt05
+ # Samsung Electronics 14" WXGA (1366x768) TFT LCD panel
+ - samsung,ltn140at29-301
# Satoz SAT050AT40H12R2 5.0" WVGA TFT LCD panel
- satoz,sat050at40h12r2
+ # Sharp LQ035Q7DB03 3.5" QVGA TFT LCD panel
+ - sharp,lq035q7db03
+ # Sharp LQ070Y3DG3B 7.0" WVGA landscape TFT LCD panel
+ - sharp,lq070y3dg3b
+ # Sharp Display Corp. LQ101K1LY04 10.07" WXGA TFT LCD panel
+ - sharp,lq101k1ly04
+ # Sharp 12.3" (2400x1600 pixels) TFT LCD panel
+ - sharp,lq123p1jx31
# Sharp LS020B1DD01D 2.0" HQVGA TFT LCD panel
- sharp,ls020b1dd01d
+ # Shelly SCA07010-BFN-LNN 7.0" WVGA TFT LCD panel
+ - shelly,sca07010-bfn-lnn
+ # Starry 12.2" (1920x1200 pixels) TFT LCD panel
+ - starry,kr122ea0sra
+ # Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel
+ - tianma,tm070jdhg30
+ # Tianma Micro-electronics TM070RVHG71 7.0" WXGA TFT LCD panel
+ - tianma,tm070rvhg71
+ # Toshiba 8.9" WXGA (1280x768) TFT LCD panel
+ - toshiba,lt089ac29000
+ # TPK U.S.A. LLC Fusion 7" 800 x 480 (WVGA) LCD panel with capacitive touch
+ - tpk,f07a-0102
+ # TPK U.S.A. LLC Fusion 10.1" 1024 x 600 (WSVGA) LCD panel with capacitive touch
+ - tpk,f10a-0102
+ # United Radiant Technology UMSH-8596MD-xT 7.0" WVGA TFT LCD panel
+ # Supported are LVDS versions (-11T, -19T) and parallel ones
+ # (-T, -1T, -7T, -20T).
+ - urt,umsh-8596md-t
+ - urt,umsh-8596md-1t
+ - urt,umsh-8596md-7t
+ - urt,umsh-8596md-11t
+ - urt,umsh-8596md-19t
+ - urt,umsh-8596md-20t
+ # VXT 800x480 color TFT LCD panel
+ - vxt,vl050-8048nt-c01
+ # Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel
+ - winstar,wf35ltiacd
backlight: true
enable-gpios: true
diff --git a/dts/Bindings/display/panel/panel-timing.yaml b/dts/Bindings/display/panel/panel-timing.yaml
new file mode 100644
index 0000000..bd558ad
--- /dev/null
+++ b/dts/Bindings/display/panel/panel-timing.yaml
@@ -0,0 +1,227 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: panel timing bindings
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Sam Ravnborg <sam@ravnborg.org>
+
+description: |
+ There are different ways of describing the timing data of a panel. The
+ devicetree representation corresponds to the one commonly found in datasheets
+ for panels.
+
+ The parameters are defined as seen in the following illustration.
+
+ +----------+-------------------------------------+----------+-------+
+ | | ^ | | |
+ | | |vback_porch | | |
+ | | v | | |
+ +----------#######################################----------+-------+
+ | # ^ # | |
+ | # | # | |
+ | hback # | # hfront | hsync |
+ | porch # | hactive # porch | len |
+ |<-------->#<-------+--------------------------->#<-------->|<----->|
+ | # | # | |
+ | # |vactive # | |
+ | # | # | |
+ | # v # | |
+ +----------#######################################----------+-------+
+ | | ^ | | |
+ | | |vfront_porch | | |
+ | | v | | |
+ +----------+-------------------------------------+----------+-------+
+ | | ^ | | |
+ | | |vsync_len | | |
+ | | v | | |
+ +----------+-------------------------------------+----------+-------+
+
+
+ The following is the panel timings shown with time on the x-axis.
+ This matches the timing diagrams often found in data sheets.
+
+ Active Front Sync Back
+ Region Porch Porch
+ <-----------------------><----------------><-------------><-------------->
+ //////////////////////|
+ ////////////////////// |
+ ////////////////////// |.................. ................
+ _______________
+
+ Timing can be specified either as a typical value or as a tuple
+ of min, typ, max values.
+
+properties:
+
+ clock-frequency:
+ description: Panel clock in Hz
+
+ hactive:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Horizontal panel resolution in pixels
+
+ vactive:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Vertical panel resolution in pixels
+
+ hfront-porch:
+ description: Horizontal front porch panel timing
+ oneOf:
+ - allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - maxItems: 1
+ items:
+ description: typical number of pixels
+ - allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - minItems: 3
+ maxItems: 3
+ items:
+ description: min, typ, max number of pixels
+
+ hback-porch:
+ description: Horizontal back porch timing
+ oneOf:
+ - allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - maxItems: 1
+ items:
+ description: typical number of pixels
+ - allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - minItems: 3
+ maxItems: 3
+ items:
+ description: min, typ, max number of pixels
+
+ hsync-len:
+ description: Horizontal sync length panel timing
+ oneOf:
+ - allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - maxItems: 1
+ items:
+ description: typical number of pixels
+ - allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - minItems: 3
+ maxItems: 3
+ items:
+ description: min, typ, max number of pixels
+
+ vfront-porch:
+ description: Vertical front porch panel timing
+ oneOf:
+ - allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - maxItems: 1
+ items:
+ description: typical number of lines
+ - allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - minItems: 3
+ maxItems: 3
+ items:
+ description: min, typ, max number of lines
+
+ vback-porch:
+ description: Vertical back porch panel timing
+ oneOf:
+ - allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - maxItems: 1
+ items:
+ description: typical number of lines
+ - allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - minItems: 3
+ maxItems: 3
+ items:
+ description: min, typ, max number of lines
+
+ vsync-len:
+ description: Vertical sync length panel timing
+ oneOf:
+ - allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - maxItems: 1
+ items:
+ description: typical number of lines
+ - allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - minItems: 3
+ maxItems: 3
+ items:
+ description: min, typ, max number of lines
+
+ hsync-active:
+ description: |
+ Horizontal sync pulse.
+ 0 selects active low, 1 selects active high.
+ If omitted then it is not used by the hardware
+ enum: [0, 1]
+
+ vsync-active:
+ description: |
+ Vertical sync pulse.
+ 0 selects active low, 1 selects active high.
+ If omitted then it is not used by the hardware
+ enum: [0, 1]
+
+ de-active:
+ description: |
+ Data enable.
+ 0 selects active low, 1 selects active high.
+ If omitted then it is not used by the hardware
+ enum: [0, 1]
+
+ pixelclk-active:
+ description: |
+ Data driving on rising or falling edge.
+ Use 0 to drive pixel data on falling edge and
+ sample data on rising edge.
+ Use 1 to drive pixel data on rising edge and
+ sample data on falling edge
+ enum: [0, 1]
+
+ syncclk-active:
+ description: |
+ Drive sync on rising or sample sync on falling edge.
+ If not specified then the setup is as specified by pixelclk-active.
+ Use 0 to drive sync on falling edge and
+ sample sync on rising edge of pixel clock.
+ Use 1 to drive sync on rising edge and
+ sample sync on falling edge of pixel clock
+ enum: [0, 1]
+
+ interlaced:
+ type: boolean
+ description: Enable interlaced mode
+
+ doublescan:
+ type: boolean
+ description: Enable double scan mode
+
+ doubleclk:
+ type: boolean
+ description: Enable double clock mode
+
+required:
+ - clock-frequency
+ - hactive
+ - vactive
+ - hfront-porch
+ - hback-porch
+ - hsync-len
+ - vfront-porch
+ - vback-porch
+ - vsync-len
+
+additionalProperties: false
+
+...
diff --git a/dts/Bindings/display/panel/qiaodian,qd43003c0-40.txt b/dts/Bindings/display/panel/qiaodian,qd43003c0-40.txt
deleted file mode 100644
index 0fbdab8..0000000
--- a/dts/Bindings/display/panel/qiaodian,qd43003c0-40.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-QiaoDian XianShi Corporation 4"3 TFT LCD panel
-
-Required properties:
-- compatible: should be "qiaodian,qd43003c0-40"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/raydium,rm68200.txt b/dts/Bindings/display/panel/raydium,rm68200.txt
deleted file mode 100644
index cbb79ef..0000000
--- a/dts/Bindings/display/panel/raydium,rm68200.txt
+++