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-rw-r--r--arch/arm/boards/protonic-stm32mp1/board.c2
-rw-r--r--arch/arm/dts/stm32mp151-prtt1c.dts124
-rw-r--r--drivers/phy/phy-stm32-usbphyc.c9
-rw-r--r--drivers/usb/dwc2/dwc2.c51
4 files changed, 181 insertions, 5 deletions
diff --git a/arch/arm/boards/protonic-stm32mp1/board.c b/arch/arm/boards/protonic-stm32mp1/board.c
index 84a3d8eabc..174454ed27 100644
--- a/arch/arm/boards/protonic-stm32mp1/board.c
+++ b/arch/arm/boards/protonic-stm32mp1/board.c
@@ -7,6 +7,7 @@
#include <init.h>
#include <mach/bbu.h>
#include <of_device.h>
+#include <deep-probe.h>
/* board specific flags */
#define PRT_STM32_BOOTSRC_SD BIT(2)
@@ -118,6 +119,7 @@ static const struct of_device_id prt_stm32_of_match[] = {
{ .compatible = "prt,prtt1s", .data = &prt_stm32_prtt1a },
{ /* sentinel */ },
};
+BAREBOX_DEEP_PROBE_ENABLE(prt_stm32_of_match);
static struct driver_d prt_stm32_board_driver = {
.name = "board-protonic-stm32",
diff --git a/arch/arm/dts/stm32mp151-prtt1c.dts b/arch/arm/dts/stm32mp151-prtt1c.dts
index fc411f9719..4eaf6712a5 100644
--- a/arch/arm/dts/stm32mp151-prtt1c.dts
+++ b/arch/arm/dts/stm32mp151-prtt1c.dts
@@ -22,13 +22,131 @@
status = "disabled";
};
};
+
+ aliases {
+ mdio-gpio0 = &mdio0;
+ };
+
+ clock_ksz9031: clock-ksz9031 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ mdio0: mdio {
+ compatible = "virtual,mdio-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
+ &gpioa 2 GPIO_ACTIVE_HIGH>;
+
+ t1l0_phy: ethernet-phy@6 {
+ compatible = "ethernet-phy-id2000.0181";
+ reg = <6>;
+ interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
+ };
+
+ t1l1_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-id2000.0181";
+ reg = <7>;
+ interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>;
+ };
+
+ t1l2_phy: ethernet-phy@10 {
+ compatible = "ethernet-phy-id2000.0181";
+ reg = <10>;
+ interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>;
+ };
+
+ rj45_phy: ethernet-phy@2 {
+ reg = <2>;
+ interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <1000>;
+
+ clocks = <&clock_ksz9031>;
+ };
+ };
+
+ spi-gpio-0 {
+ compatible = "spi-gpio";
+ gpio-sck = <&gpioa 5 GPIO_ACTIVE_HIGH>;
+ gpio-mosi = <&gpiob 5 GPIO_ACTIVE_HIGH>;
+ gpio-miso = <&gpioa 6 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
+ num-chipselects = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch@0 {
+ compatible = "nxp,sja1105q";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ spi-rx-delay-us = <1>;
+ spi-tx-delay-us = <1>;
+ spi-cpha;
+
+ reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "t1l0";
+ phy-mode = "rmii";
+ phy-handle = <&t1l0_phy>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "t1l1";
+ phy-mode = "rmii";
+ phy-handle = <&t1l1_phy>;
+ };
+
+ port@2 {
+ reg = <2>;
+ phy-mode = "rmii";
+ label = "t1l2";
+ phy-handle = <&t1l2_phy>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "rj45";
+ phy-handle = <&rj45_phy>;
+ phy-mode = "rgmii-id";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "cpu";
+ ethernet = <&ethernet0>;
+ phy-mode = "rmii";
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
+
+
};
&ethernet0 {
pinctrl-0 = <&ethernet0_rmii_pins_a>;
pinctrl-names = "default";
phy-mode = "rmii";
- phy-reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
status = "okay";
fixed-link {
@@ -57,9 +175,7 @@
pins1 {
pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('B', 13, AF11)>, /* ETH1_RMII_TXD1 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
+ <STM32_PINMUX('B', 11, AF11)>; /* ETH1_RMII_TX_EN */
};
pins2 {
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c
index 4c1d7bfa48..2fa1f0fd01 100644
--- a/drivers/phy/phy-stm32-usbphyc.c
+++ b/drivers/phy/phy-stm32-usbphyc.c
@@ -423,10 +423,17 @@ static int stm32_usbphyc_probe(struct device_d *dev)
for_each_child_of_node(np, child) {
struct stm32_usbphyc_phy *usbphyc_phy;
+ struct device_d *phydev;
struct phy *phy;
u32 index;
- phy = phy_create(dev, child, &stm32_usbphyc_phy_ops);
+ phydev = of_platform_device_create(child, dev);
+ if (!phydev)
+ continue;
+
+ of_platform_device_dummy_drv(phydev);
+
+ phy = phy_create(phydev, child, &stm32_usbphyc_phy_ops);
if (IS_ERR(phy)) {
ret = PTR_ERR(phy);
if (ret != -EPROBE_DEFER)
diff --git a/drivers/usb/dwc2/dwc2.c b/drivers/usb/dwc2/dwc2.c
index 1b5981c2d5..8cb99446e4 100644
--- a/drivers/usb/dwc2/dwc2.c
+++ b/drivers/usb/dwc2/dwc2.c
@@ -13,9 +13,49 @@
#include <driver.h>
#include <linux/clk.h>
#include <linux/reset.h>
+#include <of_device.h>
#include "dwc2.h"
+static void dwc2_set_stm32mp15_fsotg_params(struct dwc2 *dwc2)
+{
+ struct dwc2_core_params *p = &dwc2->params;
+
+ p->otg_cap &= ~(DWC2_CAP_PARAM_HNP_SRP_CAPABLE
+ | DWC2_CAP_PARAM_SRP_ONLY_CAPABLE);
+ p->otg_cap |= DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
+ p->speed = DWC2_SPEED_PARAM_FULL;
+ p->host_rx_fifo_size = 128;
+ p->host_nperio_tx_fifo_size = 96;
+ p->host_perio_tx_fifo_size = 96;
+ p->max_packet_count = 256;
+ p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
+ p->i2c_enable = false;
+ p->activate_stm_fs_transceiver = true;
+ p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
+ p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+ p->host_support_fs_ls_low_power = true;
+ p->host_ls_low_power_phy_clk = true;
+}
+
+static void dwc2_set_stm32mp15_hsotg_params(struct dwc2 *dwc2)
+{
+ struct dwc2_core_params *p = &dwc2->params;
+
+ p->otg_cap &= ~(DWC2_CAP_PARAM_HNP_SRP_CAPABLE
+ | DWC2_CAP_PARAM_SRP_ONLY_CAPABLE);
+ p->otg_cap |= DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
+ p->host_rx_fifo_size = 440;
+ p->host_nperio_tx_fifo_size = 256;
+ p->host_perio_tx_fifo_size = 256;
+ p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
+ p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+ p->lpm = false;
+ p->lpm_clock_gating = false;
+ p->besl = false;
+ p->hird_threshold_en = false;
+}
+
static int dwc2_set_mode(void *ctx, enum usb_dr_mode mode)
{
struct dwc2 *dwc2 = ctx;
@@ -43,10 +83,13 @@ static int dwc2_set_mode(void *ctx, enum usb_dr_mode mode)
return ret;
}
+typedef void (*set_params_cb)(struct dwc2 *dwc2);
+
static int dwc2_probe(struct device_d *dev)
{
struct resource *iores;
struct dwc2 *dwc2;
+ set_params_cb set_params;
int ret;
dwc2 = xzalloc(sizeof(*dwc2));
@@ -107,6 +150,10 @@ static int dwc2_probe(struct device_d *dev)
dwc2_set_default_params(dwc2);
+ set_params = of_device_get_match_data(dev);
+ if (set_params)
+ set_params(dwc2);
+
dma_set_mask(dev, DMA_BIT_MASK(32));
dev->priv = dwc2;
@@ -148,6 +195,10 @@ static const struct of_device_id dwc2_platform_dt_ids[] = {
{ .compatible = "brcm,bcm2835-usb", },
{ .compatible = "brcm,bcm2708-usb", },
{ .compatible = "snps,dwc2", },
+ { .compatible = "st,stm32mp15-fsotg",
+ .data = dwc2_set_stm32mp15_fsotg_params },
+ { .compatible = "st,stm32mp15-hsotg",
+ .data = dwc2_set_stm32mp15_hsotg_params },
{ }
};
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-20 02:44:18 +0000