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-rw-r--r--arch/arm/boards/at91rm9200ek/lowlevel.c40
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam926x_board_init.h22
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h8
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_sdramc.h4
-rw-r--r--arch/arm/mach-at91/include/mach/debug_ll.h6
-rw-r--r--arch/arm/mach-at91/include/mach/gpio.h57
-rw-r--r--arch/arm/mach-at91/sam9_smc.c58
-rw-r--r--arch/arm/mach-at91/setup.c4
-rw-r--r--drivers/clocksource/timer-atmel-pit.c4
-rw-r--r--drivers/mci/atmel-mci-regs.h4
-rw-r--r--drivers/net/at91_ether.h4
-rw-r--r--drivers/net/macb.h8
-rw-r--r--drivers/pinctrl/pinctrl-at91.c28
-rw-r--r--drivers/spi/atmel_spi.h4
-rw-r--r--drivers/usb/gadget/at91_udc.c86
-rw-r--r--drivers/video/atmel_lcdfb.h4
16 files changed, 168 insertions, 173 deletions
diff --git a/arch/arm/boards/at91rm9200ek/lowlevel.c b/arch/arm/boards/at91rm9200ek/lowlevel.c
index 030c3dbf04..b132ccc084 100644
--- a/arch/arm/boards/at91rm9200ek/lowlevel.c
+++ b/arch/arm/boards/at91rm9200ek/lowlevel.c
@@ -33,28 +33,28 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint
/*
* PMC Check if the PLL is already initialized
*/
- r = __raw_readl(pmc + AT91_PMC_MCKR);
+ r = readl(pmc + AT91_PMC_MCKR);
if (r & AT91_PMC_CSS)
goto end;
/*
* Enable the Main Oscillator
*/
- __raw_writel(CONFIG_SYS_MOR_VAL, pmc + AT91_CKGR_MOR);
+ writel(CONFIG_SYS_MOR_VAL, pmc + AT91_CKGR_MOR);
do {
- r = __raw_readl(pmc + AT91_PMC_SR);
+ r = readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_MOSCS));
/*
* EBI_CFGR
*/
- __raw_writel(CONFIG_SYS_EBI_CFGR_VAL, mc + AT91RM9200_EBI_CFGR);
+ writel(CONFIG_SYS_EBI_CFGR_VAL, mc + AT91RM9200_EBI_CFGR);
/*
* SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
*/
- __raw_writel(CONFIG_SYS_SMC_CSR0_VAL, mc + AT91RM9200_SMC_CSR(0));
+ writel(CONFIG_SYS_SMC_CSR0_VAL, mc + AT91RM9200_SMC_CSR(0));
/*
* Init Clocks
@@ -63,24 +63,24 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint
/*
* PLLAR: x MHz for PCK
*/
- __raw_writel(CONFIG_SYS_PLLAR_VAL, pmc + AT91_CKGR_PLLAR);
+ writel(CONFIG_SYS_PLLAR_VAL, pmc + AT91_CKGR_PLLAR);
do {
- r = __raw_readl(pmc + AT91_PMC_SR);
+ r = readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_LOCKA));
/*
* PCK/x = MCK Master Clock from SLOW
*/
- __raw_writel(CONFIG_SYS_MCKR2_VAL1, pmc + AT91_PMC_MCKR);
+ writel(CONFIG_SYS_MCKR2_VAL1, pmc + AT91_PMC_MCKR);
/*
* PCK/x = MCK Master Clock from PLLA
*/
- __raw_writel(CONFIG_SYS_MCKR2_VAL2, pmc + AT91_PMC_MCKR);
+ writel(CONFIG_SYS_MCKR2_VAL2, pmc + AT91_PMC_MCKR);
do {
- r = __raw_readl(pmc + AT91_PMC_SR);
+ r = readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_MCKRDY));
/*
@@ -88,38 +88,38 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint
*/
/* PIOC_ASR: Configure PIOC as peripheral (D16/D31) */
- __raw_writel(CONFIG_SYS_PIOC_ASR_VAL, AT91RM9200_BASE_PIOC + PIO_ASR);
+ writel(CONFIG_SYS_PIOC_ASR_VAL, AT91RM9200_BASE_PIOC + PIO_ASR);
/* PIOC_BSR */
- __raw_writel(CONFIG_SYS_PIOC_BSR_VAL, AT91RM9200_BASE_PIOC + PIO_BSR);
+ writel(CONFIG_SYS_PIOC_BSR_VAL, AT91RM9200_BASE_PIOC + PIO_BSR);
/* PIOC_PDR */
- __raw_writel(CONFIG_SYS_PIOC_PDR_VAL, AT91RM9200_BASE_PIOC + PIO_PDR);
+ writel(CONFIG_SYS_PIOC_PDR_VAL, AT91RM9200_BASE_PIOC + PIO_PDR);
/* EBI_CSA : CS1=SDRAM */
- __raw_writel(CONFIG_SYS_EBI_CSA_VAL, mc + AT91RM9200_EBI_CSA);
+ writel(CONFIG_SYS_EBI_CSA_VAL, mc + AT91RM9200_EBI_CSA);
/* SDRC_CR */
- __raw_writel(CONFIG_SYS_SDRC_CR_VAL, mc + AT91RM9200_SDRAMC_CR);
+ writel(CONFIG_SYS_SDRC_CR_VAL, mc + AT91RM9200_SDRAMC_CR);
/* SDRC_MR : Precharge All */
- __raw_writel(AT91RM9200_SDRAMC_MODE_PRECHARGE, mc + AT91RM9200_SDRAMC_MR);
+ writel(AT91RM9200_SDRAMC_MODE_PRECHARGE, mc + AT91RM9200_SDRAMC_MR);
/* access SDRAM */
access_sdram();
/* SDRC_MR : refresh */
- __raw_writel(AT91RM9200_SDRAMC_MODE_REFRESH, mc + AT91RM9200_SDRAMC_MR);
+ writel(AT91RM9200_SDRAMC_MODE_REFRESH, mc + AT91RM9200_SDRAMC_MR);
/* access SDRAM 8 times */
for (i = 0; i < 8; i++)
access_sdram();
/* SDRC_MR : Load Mode Register */
- __raw_writel(AT91RM9200_SDRAMC_MODE_LMR, mc + AT91RM9200_SDRAMC_MR);
+ writel(AT91RM9200_SDRAMC_MODE_LMR, mc + AT91RM9200_SDRAMC_MR);
/* access SDRAM */
access_sdram();
/* SDRC_TR : Write refresh rate */
- __raw_writel(CONFIG_SYS_SDRC_TR_VAL, mc + AT91RM9200_SDRAMC_TR);
+ writel(CONFIG_SYS_SDRC_TR_VAL, mc + AT91RM9200_SDRAMC_TR);
/* access SDRAM */
access_sdram();
/* SDRC_MR : Normal Mode */
- __raw_writel(AT91RM9200_SDRAMC_MODE_NORMAL, mc + AT91RM9200_SDRAMC_MR);
+ writel(AT91RM9200_SDRAMC_MODE_NORMAL, mc + AT91RM9200_SDRAMC_MR);
/* access SDRAM */
access_sdram();
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
index 9ab0eef728..d52a29e5ef 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
@@ -78,43 +78,43 @@ static void __always_inline at91sam926x_sdramc_init(struct at91sam926x_board_cfg
int in_sram = running_in_sram();
/* SDRAMC Check if Refresh Timer Counter is already initialized */
- r = __raw_readl(cfg->sdramc + AT91_SDRAMC_TR);
+ r = readl(cfg->sdramc + AT91_SDRAMC_TR);
if (r && !in_sram)
return;
/* SDRAMC_MR : Normal Mode */
- __raw_writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR);
+ writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR);
/* SDRAMC_TR - Refresh Timer register */
- __raw_writel(cfg->sdrc_tr1, cfg->sdramc + AT91_SDRAMC_TR);
+ writel(cfg->sdrc_tr1, cfg->sdramc + AT91_SDRAMC_TR);
/* SDRAMC_CR - Configuration register*/
- __raw_writel(cfg->sdrc_cr, cfg->sdramc + AT91_SDRAMC_CR);
+ writel(cfg->sdrc_cr, cfg->sdramc + AT91_SDRAMC_CR);
/* Memory Device Type */
- __raw_writel(cfg->sdrc_mdr, cfg->sdramc + AT91_SDRAMC_MDR);
+ writel(cfg->sdrc_mdr, cfg->sdramc + AT91_SDRAMC_MDR);
/* SDRAMC_MR : Precharge All */
- __raw_writel(AT91_SDRAMC_MODE_PRECHARGE, cfg->sdramc + AT91_SDRAMC_MR);
+ writel(AT91_SDRAMC_MODE_PRECHARGE, cfg->sdramc + AT91_SDRAMC_MR);
access_sdram();
/* SDRAMC_MR : refresh */
- __raw_writel(AT91_SDRAMC_MODE_REFRESH, cfg->sdramc + AT91_SDRAMC_MR);
+ writel(AT91_SDRAMC_MODE_REFRESH, cfg->sdramc + AT91_SDRAMC_MR);
/* access SDRAM 8 times */
for (i = 0; i < 8; i++)
access_sdram();
/* SDRAMC_MR : Load Mode Register */
- __raw_writel(AT91_SDRAMC_MODE_LMR, cfg->sdramc + AT91_SDRAMC_MR);
+ writel(AT91_SDRAMC_MODE_LMR, cfg->sdramc + AT91_SDRAMC_MR);
access_sdram();
/* SDRAMC_MR : Normal Mode */
- __raw_writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR);
+ writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR);
access_sdram();
/* SDRAMC_TR : Refresh Timer Counter */
- __raw_writel(cfg->sdrc_tr2, cfg->sdramc + AT91_SDRAMC_TR);
+ writel(cfg->sdrc_tr2, cfg->sdramc + AT91_SDRAMC_TR);
access_sdram();
}
@@ -127,7 +127,7 @@ static void __always_inline at91sam926x_board_init(void __iomem *smcbase,
if (!IS_ENABLED(CONFIG_AT91SAM926X_BOARD_INIT))
return;
- __raw_writel(cfg->wdt_mr, AT91SAM926X_BASE_WDT + AT91_WDT_MR);
+ writel(cfg->wdt_mr, AT91SAM926X_BASE_WDT + AT91_WDT_MR);
/* configure PIOx as EBI0 D[16-31] */
at91_mux_gpio_disable(cfg->pio, cfg->ebi_pio_pdr);
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index 1c4d313eb4..b0c003cd1e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -145,8 +145,8 @@ static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb)
u32 size;
bool is_sdram;
- cr = __raw_readl(base + AT91_DDRSDRC_CR);
- mdr = __raw_readl(base + AT91_DDRSDRC_MDR);
+ cr = readl(base + AT91_DDRSDRC_CR);
+ mdr = readl(base + AT91_DDRSDRC_MDR);
is_sdram = (mdr & AT91_DDRSDRC_MD) <= AT91_DDRSDRC_MD_LOW_POWER_SDR;
@@ -230,8 +230,8 @@ static inline u32 at91sama5_get_ddram_size(void)
u32 size;
void * __iomem base = IOMEM(SAMA5D3_BASE_MPDDRC);
- cr = __raw_readl(base + AT91_DDRSDRC_CR);
- mdr = __raw_readl(base + AT91_DDRSDRC_MDR);
+ cr = readl(base + AT91_DDRSDRC_CR);
+ mdr = readl(base + AT91_DDRSDRC_MDR);
/* Formula:
* size = bank << (col + row + 1);
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 8595f9cd5c..7bd887c8cb 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -90,7 +90,7 @@ static inline u32 at91_get_sdram_size(void *base)
u32 val;
u32 size;
- val = __raw_readl(base + AT91_SDRAMC_CR);
+ val = readl(base + AT91_SDRAMC_CR);
/* Formula:
* size = bank << (col + row + 1);
@@ -114,7 +114,7 @@ static inline u32 at91_get_sdram_size(void *base)
static inline bool at91_is_low_power_sdram(void *base)
{
- return __raw_readl(base + AT91_SDRAMC_MDR) & AT91_SDRAMC_MD_LOW_POWER_SDRAM;
+ return readl(base + AT91_SDRAMC_MDR) & AT91_SDRAMC_MD_LOW_POWER_SDRAM;
}
#ifdef CONFIG_SOC_AT91SAM9260
diff --git a/arch/arm/mach-at91/include/mach/debug_ll.h b/arch/arm/mach-at91/include/mach/debug_ll.h
index 42728a4b27..fd26cae21e 100644
--- a/arch/arm/mach-at91/include/mach/debug_ll.h
+++ b/arch/arm/mach-at91/include/mach/debug_ll.h
@@ -31,11 +31,11 @@
*/
static inline void PUTC_LL(char c)
{
- while (!(__raw_readl(UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXRDY))
+ while (!(readl(UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXRDY))
barrier();
- __raw_writel(c, UART_BASE + ATMEL_US_THR);
+ writel(c, UART_BASE + ATMEL_US_THR);
- while (!(__raw_readl(UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
+ while (!(readl(UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
barrier();
}
#endif
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index bdc0cb6879..f5ab47c064 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -26,67 +26,62 @@ static inline unsigned pin_to_mask(unsigned pin)
static inline void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
{
- __raw_writel(mask, pio + PIO_IDR);
+ writel(mask, pio + PIO_IDR);
}
static inline void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
{
- __raw_writel(mask, pio + (on ? PIO_PUER : PIO_PUDR));
+ writel(mask, pio + (on ? PIO_PUER : PIO_PUDR));
}
static inline void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
{
- __raw_writel(mask, pio + (on ? PIO_MDER : PIO_MDDR));
+ writel(mask, pio + (on ? PIO_MDER : PIO_MDDR));
}
static inline void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
{
- __raw_writel(mask, pio + PIO_ASR);
+ writel(mask, pio + PIO_ASR);
}
static inline void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
{
- __raw_writel(mask, pio + PIO_BSR);
+ writel(mask, pio + PIO_BSR);
}
static inline void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
{
-
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
- pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
- pio + PIO_ABCDSR2);
+ writel(readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
+ writel(readl(pio + PIO_ABCDSR2) & ~mask, pio + PIO_ABCDSR2);
}
static inline void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
{
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
- pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
- pio + PIO_ABCDSR2);
+ writel(readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
+ writel(readl(pio + PIO_ABCDSR2) & ~mask, pio + PIO_ABCDSR2);
}
static inline void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
{
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+ writel(readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
+ writel(readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
}
static inline void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
{
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+ writel(readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
+ writel(readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
}
static inline void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
{
- __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
+ writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
}
static inline void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
{
if (is_on)
- __raw_writel(mask, pio + PIO_IFSCDR);
+ writel(mask, pio + PIO_IFSCDR);
at91_mux_set_deglitch(pio, mask, is_on);
}
@@ -94,50 +89,50 @@ static inline void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
bool is_on, u32 div)
{
if (is_on) {
- __raw_writel(mask, pio + PIO_IFSCER);
- __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
- __raw_writel(mask, pio + PIO_IFER);
+ writel(mask, pio + PIO_IFSCER);
+ writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
+ writel(mask, pio + PIO_IFER);
} else {
- __raw_writel(mask, pio + PIO_IFDR);
+ writel(mask, pio + PIO_IFDR);
}
}
static inline void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
{
- __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
+ writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
}
static inline void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
{
- __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
+ writel(readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
}
static inline void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
{
- __raw_writel(mask, pio + PIO_PDR);
+ writel(mask, pio + PIO_PDR);
}
static inline void at91_mux_gpio_enable(void __iomem *pio, unsigned mask)
{
- __raw_writel(mask, pio + PIO_PER);
+ writel(mask, pio + PIO_PER);
}
static inline void at91_mux_gpio_input(void __iomem *pio, unsigned mask, bool input)
{
- __raw_writel(mask, pio + (input ? PIO_ODR : PIO_OER));
+ writel(mask, pio + (input ? PIO_ODR : PIO_OER));
}
static inline void at91_mux_gpio_set(void __iomem *pio, unsigned mask,
int value)
{
- __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
+ writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
}
static inline int at91_mux_gpio_get(void __iomem *pio, unsigned mask)
{
u32 pdsr;
- pdsr = __raw_readl(pio + PIO_PDSR);
+ pdsr = readl(pio + PIO_PDSR);
return (pdsr & mask) != 0;
}
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index dc1f2edf41..a4d441f023 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -41,23 +41,23 @@ static void sam9_smc_cs_write_mode(void __iomem *base,
break;
}
- __raw_writel(config->mode
- | AT91_SMC_TDF_(config->tdf_cycles),
- mode_reg);
+ writel(config->mode
+ | AT91_SMC_TDF_(config->tdf_cycles),
+ mode_reg);
}
static void sam9_smc_cs_write_timings(void __iomem *base,
struct sam9_smc_config *config)
{
- __raw_writel(AT91_SMC_TCLR_(config->tclr)
- | AT91_SMC_TADL_(config->tadl)
- | AT91_SMC_TAR_(config->tar)
- | AT91_SMC_OCMS_(config->ocms)
- | AT91_SMC_TRR_(config->trr)
- | AT91_SMC_TWB_(config->twb)
- | AT91_SMC_RBNSEL_(config->rbnsel)
- | AT91_SMC_NFSEL_(config->nfsel),
- base + AT91_SAMA5_SMC_TIMINGS);
+ writel(AT91_SMC_TCLR_(config->tclr)
+ | AT91_SMC_TADL_(config->tadl)
+ | AT91_SMC_TAR_(config->tar)
+ | AT91_SMC_OCMS_(config->ocms)
+ | AT91_SMC_TRR_(config->trr)
+ | AT91_SMC_TWB_(config->twb)
+ | AT91_SMC_RBNSEL_(config->rbnsel)
+ | AT91_SMC_NFSEL_(config->nfsel),
+ base + AT91_SAMA5_SMC_TIMINGS);
}
void sam9_smc_write_mode(int id, int cs,
@@ -71,23 +71,23 @@ static void sam9_smc_cs_configure(void __iomem *base,
{
/* Setup register */
- __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)
- | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
- | AT91_SMC_NRDSETUP_(config->nrd_setup)
- | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
- base + AT91_SMC_SETUP);
+ writel(AT91_SMC_NWESETUP_(config->nwe_setup)
+ | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
+ | AT91_SMC_NRDSETUP_(config->nrd_setup)
+ | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
+ base + AT91_SMC_SETUP);
/* Pulse register */
- __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
- | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
- | AT91_SMC_NRDPULSE_(config->nrd_pulse)
- | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
- base + AT91_SMC_PULSE);
+ writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
+ | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
+ | AT91_SMC_NRDPULSE_(config->nrd_pulse)
+ | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
+ base + AT91_SMC_PULSE);
/* Cycle register */
- __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)
- | AT91_SMC_NRDCYCLE_(config->read_cycle),
- base + AT91_SMC_CYCLE);
+ writel(AT91_SMC_NWECYCLE_(config->write_cycle)
+ | AT91_SMC_NRDCYCLE_(config->read_cycle),
+ base + AT91_SMC_CYCLE);
/* Mode register */
sam9_smc_cs_write_mode(base, config);
@@ -115,7 +115,7 @@ static void sam9_smc_cs_read_mode(void __iomem *base,
break;
}
- val = __raw_readl(mode_reg);
+ val = readl(mode_reg);
config->mode = (val & ~AT91_SMC_NWECYCLE);
config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
@@ -133,7 +133,7 @@ static void sam9_smc_cs_read(void __iomem *base,
u32 val;
/* Setup register */
- val = __raw_readl(base + AT91_SMC_SETUP);
+ val = readl(base + AT91_SMC_SETUP);
config->nwe_setup = val & AT91_SMC_NWESETUP;
config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
@@ -141,7 +141,7 @@ static void sam9_smc_cs_read(void __iomem *base,
config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
/* Pulse register */
- val = __raw_readl(base + AT91_SMC_PULSE);
+ val = readl(base + AT91_SMC_PULSE);
config->nwe_setup = val & AT91_SMC_NWEPULSE;
config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
@@ -149,7 +149,7 @@ static void sam9_smc_cs_read(void __iomem *base,
config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
/* Cycle register */
- val = __raw_readl(base + AT91_SMC_CYCLE);
+ val = readl(base + AT91_SMC_CYCLE);
config->write_cycle = val & AT91_SMC_NWECYCLE;
config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index cb79eb26b8..4e30c78de7 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -29,11 +29,11 @@ static void __init soc_detect(u32 dbgu_base)
{
u32 cidr, socid;
- cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
+ cidr = readl(dbgu_base + AT91_DBGU_CIDR);
socid = cidr & ~AT91_CIDR_VERSION;
/* sub version of soc */
- at91_soc_initdata.exid = __raw_readl(dbgu_base + AT91_DBGU_EXID);
+ at91_soc_initdata.exid = readl(dbgu_base + AT91_DBGU_EXID);
switch (socid) {
case ARCH_ID_AT91RM9200:
diff --git a/drivers/clocksource/timer-atmel-pit.c b/drivers/clocksource/timer-atmel-pit.c
index e23f1e5ec4..6e86653480 100644
--- a/drivers/clocksource/timer-atmel-pit.c
+++ b/drivers/clocksource/timer-atmel-pit.c
@@ -35,8 +35,8 @@
#include <linux/err.h>
#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
-#define pit_write(reg, val) __raw_writel(val, pit_base + reg)
-#define pit_read(reg) __raw_readl(pit_base + reg)
+#define pit_write(reg, val) writel(val, pit_base + reg)
+#define pit_read(reg) readl(pit_base + reg)
static __iomem void *pit_base;
diff --git a/drivers/mci/atmel-mci-regs.h b/drivers/mci/atmel-mci-regs.h
index af1dba00f9..2866e3eb77 100644
--- a/drivers/mci/atmel-mci-regs.h
+++ b/drivers/mci/atmel-mci-regs.h
@@ -138,9 +138,9 @@
/* Register access macros */
#define atmci_readl(port,reg) \
- __raw_readl((port)->regs + reg)
+ readl((port)->regs + reg)
#define atmci_writel(port,reg,value) \
- __raw_writel((value), (port)->regs + reg)
+ writel((value), (port)->regs + reg)
/* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
#ifdef CONFIG_AVR32
diff --git a/drivers/net/at91_ether.h b/drivers/net/at91_ether.h
index 08df6f161c..21c2ae94da 100644
--- a/drivers/net/at91_ether.h
+++ b/drivers/net/at91_ether.h
@@ -33,7 +33,7 @@ struct rbf_t
*/
static inline unsigned long at91_emac_read(unsigned int reg)
{
- return __raw_readl(AT91_VA_BASE_EMAC + reg);
+ return readl(AT91_VA_BASE_EMAC + reg);
}
/*
@@ -41,6 +41,6 @@ static inline unsigned long at91_emac_read(unsigned int reg)
*/
static inline void at91_emac_write(unsigned int reg, unsigned long value)
{
- __raw_writel(value, AT91_VA_BASE_EMAC + reg);
+ writel(value, AT91_VA_BASE_EMAC + reg);
}
#endif
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index 979f53cb71..fda4d08663 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -334,13 +334,13 @@
/* Register access macros */
#define macb_readl(port,reg) \
- __raw_readl((port)->regs + MACB_##reg)
+ readl((port)->regs + MACB_##reg)
#define macb_writel(port,reg,value) \
- __raw_writel((value), (port)->regs + MACB_##reg)
+ writel((value), (port)->regs + MACB_##reg)
#define gem_readl(port, reg) \
- __raw_readl((port)->regs + GEM_##reg)
+ readl((port)->regs + GEM_##reg)
#define gem_writel(port, reg, value) \
- __raw_writel((value), (port)->regs + GEM_##reg)
+ writel((value), (port)->regs + GEM_##reg)
/*
* Conditional GEM/MACB macros. These perform the operation to the correct
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 11e00833c5..9b366e4812 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -303,11 +303,11 @@ static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
{
unsigned select;
- if (__raw_readl(pio + PIO_PSR) & mask)
+ if (readl(pio + PIO_PSR) & mask)
return AT91_MUX_GPIO;
- select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
- select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
+ select = !!(readl(pio + PIO_ABCDSR1) & mask);
+ select |= (!!(readl(pio + PIO_ABCDSR2) & mask) << 1);
return select + 1;
}
@@ -316,34 +316,34 @@ static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
{
unsigned select;
- if (__raw_readl(pio + PIO_PSR) & mask)
+ if (readl(pio + PIO_PSR) & mask)
return AT91_MUX_GPIO;
- select = __raw_readl(pio + PIO_ABSR) & mask;
+ select = readl(pio + PIO_ABSR) & mask;
return select + 1;
}
static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
{
- return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1;
+ return (readl(pio + PIO_IFSR) >> pin) & 0x1;
}
static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
{
- *div = __raw_readl(pio + PIO_SCDR);
+ *div = readl(pio + PIO_SCDR);
- return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1;
+ return (readl(pio + PIO_IFSCSR) >> pin) & 0x1;
}
static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
{
- return (__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1;
+ return (readl(pio + PIO_PPDSR) >> pin) & 0x1;
}
static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
{
- return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
+ return (readl(pio + PIO_SCHMITT) >> pin) & 0x1;
}
static struct at91_pinctrl_mux_ops at91rm9200_ops = {
@@ -559,7 +559,7 @@ static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
unsigned mask = 1 << offset;
at91_mux_gpio_set(pio, mask, value);
- __raw_writel(mask, pio + PIO_OER);
+ writel(mask, pio + PIO_OER);
return 0;
}
@@ -571,8 +571,8 @@ static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
unsigned mask = 1 << offset;
u32 osr;
- if (mask & __raw_readl(pio + PIO_PSR)) {
- osr = __raw_readl(pio + PIO_OSR);
+ if (mask & readl(pio + PIO_PSR)) {
+ osr = readl(pio + PIO_OSR);
return !(osr & mask);
} else {
return -EBUSY;
@@ -585,7 +585,7 @@ static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << offset;
- __raw_writel(mask, pio + PIO_ODR);
+ writel(mask, pio + PIO_ODR);
return 0;
}
diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h
index 3f4d7ba124..7c4806981f 100644
--- a/drivers/spi/atmel_spi.h
+++ b/drivers/spi/atmel_spi.h
@@ -161,8 +161,8 @@
/* Register access macros */
#define spi_readl(port, reg) \
- __raw_readl((port)->regs + SPI_##reg)
+ readl((port)->regs + SPI_##reg)
#define spi_writel(port, reg, value) \
- __raw_writel((value), (port)->regs + SPI_##reg)
+ writel((value), (port)->regs + SPI_##reg)
#endif /* __ATMEL_SPI_H__ */
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 243656d443..efbc574c23 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -65,9 +65,9 @@
static const char ep0name[] = "ep0";
#define at91_udp_read(udc, reg) \
- __raw_readl((udc)->udp_baseaddr + (reg))
+ readl((udc)->udp_baseaddr + (reg))
#define at91_udp_write(udc, reg, val) \
- __raw_writel((val), (udc)->udp_baseaddr + (reg))
+ writel((val), (udc)->udp_baseaddr + (reg))
/*-------------------------------------------------------------------------*/
@@ -136,7 +136,7 @@ static int read_fifo (struct at91_ep *ep, struct at91_request *req)
* or if we already emptied both pingpong buffers
*/
rescan:
- csr = __raw_readl(creg);
+ csr = readl(creg);
if ((csr & RX_DATA_READY) == 0)
return 0;
@@ -162,7 +162,7 @@ rescan:
}
} else
csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0);
- __raw_writel(csr, creg);
+ writel(csr, creg);
req->req.actual += count;
is_done = (count < ep->ep.maxpacket);
@@ -184,7 +184,7 @@ rescan:
* CSR returns bad RXCOUNT when read too soon after updating
* RX_DATA_BK flags.
*/
- csr = __raw_readl(creg);
+ csr = readl(creg);
bufferspace -= count;
buf += count;
@@ -198,7 +198,7 @@ rescan:
static int write_fifo(struct at91_ep *ep, struct at91_request *req)
{
u32 __iomem *creg = ep->creg;
- u32 csr = __raw_readl(creg);
+ u32 csr = readl(creg);
u8 __iomem *dreg = ep->creg + (AT91_UDP_FDR(0) - AT91_UDP_CSR(0));
unsigned total, count, is_last;
u8 *buf;
@@ -219,8 +219,8 @@ static int write_fifo(struct at91_ep *ep, struct at91_request *req)
if (csr & AT91_UDP_TXCOMP) {
csr |= CLR_FX;
csr &= ~(SET_FX | AT91_UDP_TXCOMP);
- __raw_writel(csr, creg);
- csr = __raw_readl(creg);
+ writel(csr, creg);
+ csr = readl(creg);
}
if (csr & AT91_UDP_TXPKTRDY)
return 0;
@@ -340,7 +340,7 @@ ok:
tmp |= 0x04;
tmp <<= 8;
tmp |= AT91_UDP_EPEDS;
- __raw_writel(tmp, ep->creg);
+ writel(tmp, ep->creg);
ep->desc = desc;
ep->ep.maxpacket = maxpacket;
@@ -373,7 +373,7 @@ static int at91_ep_disable (struct usb_ep * _ep)
if (ep->udc->clocked) {
at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask);
at91_udp_write(udc, AT91_UDP_RST_EP, 0);
- __raw_writel(0, ep->creg);
+ writel(0, ep->creg);
}
return 0;
@@ -471,10 +471,10 @@ static int at91_ep_queue(struct usb_ep *_ep,
ep0_in_status:
PACKET("ep0 in/status\n");
status = 0;
- tmp = __raw_readl(ep->creg);
+ tmp = readl(ep->creg);
tmp &= ~SET_FX;
tmp |= CLR_FX | AT91_UDP_TXPKTRDY;
- __raw_writel(tmp, ep->creg);
+ writel(tmp, ep->creg);
udc->req_pending = 0;
goto done;
}
@@ -534,7 +534,7 @@ static int at91_ep_set_halt(struct usb_ep *_ep, int value)
creg = ep->creg;
- csr = __raw_readl(creg);
+ csr = readl(creg);
/*
* fail with still-busy IN endpoints, ensuring correct sequencing
@@ -554,7 +554,7 @@ static int at91_ep_set_halt(struct usb_ep *_ep, int value)
at91_udp_write(udc, AT91_UDP_RST_EP, 0);
csr &= ~AT91_UDP_FORCESTALL;
}
- __raw_writel(csr, creg);
+ writel(csr, creg);
}
return status;
@@ -760,7 +760,7 @@ static int handle_ep(struct at91_ep *ep)
{
struct at91_request *req;
u32 __iomem *creg = ep->creg;
- u32 csr = __raw_readl(creg);
+ u32 csr = readl(creg);
if (!list_empty(&ep->queue))
req = list_entry(ep->queue.next,
@@ -772,7 +772,7 @@ static int handle_ep(struct at91_ep *ep)
if (csr & (AT91_UDP_STALLSENT | AT91_UDP_TXCOMP)) {
csr |= CLR_FX;
csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP);
- __raw_writel(csr, creg);
+ writel(csr, creg);
}
if (req)
return write_fifo(ep, req);
@@ -784,8 +784,8 @@ static int handle_ep(struct at91_ep *ep)
req->req.status = -EILSEQ;
csr |= CLR_FX;
csr &= ~(SET_FX | AT91_UDP_STALLSENT);
- __raw_writel(csr, creg);
- csr = __raw_readl(creg);
+ writel(csr, creg);
+ csr = readl(creg);
}
if (req && (csr & RX_DATA_READY))
return read_fifo(ep, req);
@@ -811,7 +811,7 @@ static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr)
rxcount = (csr & AT91_UDP_RXBYTECNT) >> 16;
if (likely(rxcount == 8)) {
while (rxcount--)
- pkt.raw[i++] = __raw_readb(dreg);
+ pkt.raw[i++] = readb(dreg);
if (pkt.r.bRequestType & USB_DIR_IN) {
csr |= AT91_UDP_DIR;
ep->is_in = 1;
@@ -826,7 +826,7 @@ static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr)
}
csr |= CLR_FX;
csr &= ~(SET_FX | AT91_UDP_RXSETUP);
- __raw_writel(csr, creg);
+ writel(csr, creg);
udc->wait_for_addr_ack = 0;
udc->wait_for_config_ack = 0;
ep->stopped = 0;
@@ -846,14 +846,14 @@ static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr)
* hardware ... notably for device and endpoint features.
*/
udc->req_pending = 1;
- csr = __raw_readl(creg);
+ csr = readl(creg);
csr |= CLR_FX;
csr &= ~SET_FX;
switch ((pkt.r.bRequestType << 8) | pkt.r.bRequest) {
case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8)
| USB_REQ_SET_ADDRESS:
- __raw_writel(csr | AT91_UDP_TXPKTRDY, creg);
+ writel(csr | AT91_UDP_TXPKTRDY, creg);
udc->addr = w_value;
udc->wait_for_addr_ack = 1;
udc->req_pending = 0;
@@ -882,8 +882,8 @@ static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr)
if (at91_udp_read(udc, AT91_UDP_GLB_STAT) & AT91_UDP_ESR)
tmp |= (1 << USB_DEVICE_REMOTE_WAKEUP);
PACKET("get device status\n");
- __raw_writeb(tmp, dreg);
- __raw_writeb(0, dreg);
+ writeb(tmp, dreg);
+ writeb(0, dreg);
goto write_in;
/* then STATUS starts later, automatically */
case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8)
@@ -910,8 +910,8 @@ static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr)
case ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_INTERFACE) << 8)
| USB_REQ_GET_STATUS:
PACKET("get interface status\n");
- __raw_writeb(0, dreg);
- __raw_writeb(0, dreg);
+ writeb(0, dreg);
+ writeb(0, dreg);
goto write_in;
/* then STATUS starts later, automatically */
case ((USB_TYPE_STANDARD|USB_RECIP_INTERFACE) << 8)
@@ -939,12 +939,12 @@ static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr)
goto stall;
}
PACKET("get %s status\n", ep->ep.name);
- if (__raw_readl(ep->creg) & AT91_UDP_FORCESTALL)
+ if (readl(ep->creg) & AT91_UDP_FORCESTALL)
tmp = (1 << USB_ENDPOINT_HALT);
else
tmp = 0;
- __raw_writeb(tmp, dreg);
- __raw_writeb(0, dreg);
+ writeb(tmp, dreg);
+ writeb(0, dreg);
goto write_in;
/* then STATUS starts later, automatically */
case ((USB_TYPE_STANDARD|USB_RECIP_ENDPOINT) << 8)
@@ -961,10 +961,10 @@ static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr)
} else if (ep->is_in)
goto stall;
- tmp = __raw_readl(ep->creg);
+ tmp = readl(ep->creg);
tmp &= ~SET_FX;
tmp |= CLR_FX | AT91_UDP_FORCESTALL;
- __raw_writel(tmp, ep->creg);
+ writel(tmp, ep->creg);
goto succeed;
case ((USB_TYPE_STANDARD|USB_RECIP_ENDPOINT) << 8)
| USB_REQ_CLEAR_FEATURE:
@@ -984,10 +984,10 @@ static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr)
at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask);
at91_udp_write(udc, AT91_UDP_RST_EP, 0);
- tmp = __raw_readl(ep->creg);
+ tmp = readl(ep->creg);
tmp |= CLR_FX;
tmp &= ~(SET_FX | AT91_UDP_FORCESTALL);
- __raw_writel(tmp, ep->creg);
+ writel(tmp, ep->creg);
if (!list_empty(&ep->queue))
handle_ep(ep);
goto succeed;
@@ -1008,7 +1008,7 @@ stall:
VDBG(udc, "req %02x.%02x protocol STALL; stat %d\n",
pkt.r.bRequestType, pkt.r.bRequest, status);
csr |= AT91_UDP_FORCESTALL;
- __raw_writel(csr, creg);
+ writel(csr, creg);
udc->req_pending = 0;
}
return;
@@ -1018,7 +1018,7 @@ succeed:
PACKET("ep0 in/status\n");
write_in:
csr |= AT91_UDP_TXPKTRDY;
- __raw_writel(csr, creg);
+ writel(csr, creg);
udc->req_pending = 0;
}
@@ -1026,7 +1026,7 @@ static void handle_ep0(struct at91_udc *udc)
{
struct at91_ep *ep0 = &udc->ep[0];
u32 __iomem *creg = ep0->creg;
- u32 csr = __raw_readl(creg);
+ u32 csr = readl(creg);
struct at91_request *req;
if (unlikely(csr & AT91_UDP_STALLSENT)) {
@@ -1034,9 +1034,9 @@ static void handle_ep0(struct at91_udc *udc)
udc->req_pending = 0;
csr |= CLR_FX;
csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_FORCESTALL);
- __raw_writel(csr, creg);
+ writel(csr, creg);
VDBG(udc, "ep0 stalled\n");
- csr = __raw_readl(creg);
+ csr = readl(creg);
}
if (csr & AT91_UDP_RXSETUP) {
nuke(ep0, 0);
@@ -1070,7 +1070,7 @@ static void handle_ep0(struct at91_udc *udc)
*/
} else {
udc->req_pending = 0;
- __raw_writel(csr, creg);
+ writel(csr, creg);
/*
* SET_ADDRESS takes effect only after the STATUS
@@ -1104,10 +1104,10 @@ static void handle_ep0(struct at91_udc *udc)
if (handle_ep(ep0)) {
/* send IN/STATUS */
PACKET("ep0 in/status\n");
- csr = __raw_readl(creg);
+ csr = readl(creg);
csr &= ~SET_FX;
csr |= CLR_FX | AT91_UDP_TXPKTRDY;
- __raw_writel(csr, creg);
+ writel(csr, creg);
udc->req_pending = 0;
}
} else if (udc->req_pending) {
@@ -1129,14 +1129,14 @@ static void handle_ep0(struct at91_udc *udc)
* that gadget drivers not use this mode.
*/
DBG(udc, "no control-OUT deferred responses!\n");
- __raw_writel(csr | AT91_UDP_FORCESTALL, creg);
+ writel(csr | AT91_UDP_FORCESTALL, creg);
udc->req_pending = 0;
}
/* STATUS stage for control-IN; ack. */
} else {
PACKET("ep0 out/status ACK\n");
- __raw_writel(csr, creg);
+ writel(csr, creg);
/* "early" status stage */
if (req)
diff --git a/drivers/video/atmel_lcdfb.h b/drivers/video/atmel_lcdfb.h
index b8458924ba..76c0e739e8 100644
--- a/drivers/video/atmel_lcdfb.h
+++ b/drivers/video/atmel_lcdfb.h
@@ -43,8 +43,8 @@ struct atmel_lcdfb_info {
void *dma_desc;
};
-#define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg))
-#define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg))
+#define lcdc_readl(sinfo, reg) readl((sinfo)->mmio+(reg))
+#define lcdc_writel(sinfo, reg, val) writel((val), (sinfo)->mmio+(reg))
#define ATMEL_LCDC_STOP_NOWAIT (1 << 0)
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-23 22:17:18 +0000