diff options
353 files changed, 9779 insertions, 994 deletions
diff --git a/Documentation/devicetree/index.rst b/Documentation/devicetree/index.rst index abb9088e91..c5992c0fc9 100644 --- a/Documentation/devicetree/index.rst +++ b/Documentation/devicetree/index.rst @@ -11,3 +11,4 @@ Contents: bindings/barebox/* bindings/leds/* bindings/misc/* + bindings/mtd/* diff --git a/Documentation/filesystems/fat.rst b/Documentation/filesystems/fat.rst index 2138328d18..e39e34a0e9 100644 --- a/Documentation/filesystems/fat.rst +++ b/Documentation/filesystems/fat.rst @@ -7,9 +7,8 @@ barebox supports FAT filesystems in both read and write modes with optional support for long filenames. A FAT filesystem can be mounted using the :ref:`command_mount` command:: - mkdir /mnt - mount /dev/disk0.0 fat /mnt - ls /mnt + barebox:/ mkdir /mnt + barebox:/ mount /dev/disk0.0 fat /mnt + barebox:/ ls /mnt zImage barebox.bin - umount /mnt - + barebox:/ umount /mnt diff --git a/Documentation/filesystems/nfs.rst b/Documentation/filesystems/nfs.rst index 4469ac1dff..ab51241549 100644 --- a/Documentation/filesystems/nfs.rst +++ b/Documentation/filesystems/nfs.rst @@ -9,7 +9,7 @@ barebox has readonly support for NFSv3 in UDP mode. Example:: - mount -t nfs 192.168.23.4:/home/user/nfsroot /mnt/nfs + barebox:/ mount -t nfs 192.168.23.4:/home/user/nfsroot /mnt/nfs The barebox NFS driver adds a ``linux.bootargs`` device parameter to the NFS device. This parameter holds a Linux kernel commandline snippet containing a suitable root= @@ -17,7 +17,7 @@ option for booting from exactly that NFS share. Example:: - devinfo nfs0 + barebox:/ devinfo nfs0 ... linux.bootargs: root=/dev/nfs nfsroot=192.168.23.4:/home/sha/nfsroot/generic-v7,v3,tcp diff --git a/Documentation/filesystems/pstore.rst b/Documentation/filesystems/pstore.rst index 74acd87ca0..0f3a2239e3 100644 --- a/Documentation/filesystems/pstore.rst +++ b/Documentation/filesystems/pstore.rst @@ -12,6 +12,7 @@ messages are stored by the kernel in a specified RAM area which is never overwritten by any user. This data can be accessed after a reboot through /pstore in Barebox or the kernel. The pstore filesystem is automatically mounted at boot:: + none on / type ramfs none on /dev type devfs none on /pstore type pstore @@ -40,7 +41,7 @@ and RAM backend support. The kernel receives the parameters describing the layout over the kernel command line. These parameters are automatically generated by Barebox. You can change these parameters in Barebox menuconfig. The RAMOOPS parameters for the Kernel are stored in the variable -global.linux.bootargs.ramoops:: +global.linux.bootargs.ramoops. To see where the RAMOOPS area is located, you can execute iomem in Barebox. The RAMOOPS area is listed as 'persistent ram':: diff --git a/Documentation/filesystems/ramfs.rst b/Documentation/filesystems/ramfs.rst index b7ece1a9d8..d27f88561f 100644 --- a/Documentation/filesystems/ramfs.rst +++ b/Documentation/filesystems/ramfs.rst @@ -9,4 +9,4 @@ is ``ramfs``. Example:: - mount none ramfs /somedir + barebox:/ mount none ramfs /somedir diff --git a/Documentation/filesystems/smhfs.rst b/Documentation/filesystems/smhfs.rst index 28de14677d..9e9993cb28 100644 --- a/Documentation/filesystems/smhfs.rst +++ b/Documentation/filesystems/smhfs.rst @@ -20,7 +20,7 @@ directory. Nevertheless, the files are there. Example:: - mount -t smhfs /dev/null /mnt/smhfs + barebox:/ mount -t smhfs /dev/null /mnt/smhfs Host Side Setup diff --git a/Documentation/filesystems/tftp.rst b/Documentation/filesystems/tftp.rst index e0a1159264..eeb3fcb688 100644 --- a/Documentation/filesystems/tftp.rst +++ b/Documentation/filesystems/tftp.rst @@ -2,15 +2,19 @@ .. _filesystems_tftp: -TFTP support -============ +TFTP filesystem +=============== -barebox has read/write support for the Trivial File Transfer Protocol. +barebox has read/write support for the Trivial File Transfer Protocol (TFTP, +`RFC1350 <https://tools.ietf.org/html/rfc1350>`_). TFTP is not designed as a filesystem. It does not have support for listing -directories. This means a :ref:`command_ls` to a TFTP-mounted path will show an empty -directory. Nevertheless, the files are there. +directories. This means a :ref:`ls <command_ls>` to a TFTP-mounted path will +show an empty directory. Nevertheless, the files are there. Example:: - mount -t tftp 192.168.23.4 /mnt/tftp + barebox:/ mount -t tftp 192.168.23.4 /mnt/tftp + +In addition to the TFTP filesystem implementation, barebox does also have a +:ref:`tftp command <command_tftp>`. diff --git a/Documentation/user/barebox.rst b/Documentation/user/barebox.rst index 00ceabb925..530693d743 100644 --- a/Documentation/user/barebox.rst +++ b/Documentation/user/barebox.rst @@ -113,9 +113,9 @@ with the most popular being ``menuconfig``:: make menuconfig -barebox uses the same (Kbuild) configuration system as Linux, so you can use -all the kernel config targets you already know, e.g. ``make xconfig``, -``make allyesconfig`` etc. +barebox uses the same configuration and build system as Linux (Kconfig, +Kbuild), so you can use all the kernel config targets you already know, e.g. +``make xconfig``, ``make allyesconfig`` etc. Configuring and compiling "out-of-tree" ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -186,7 +186,9 @@ with U-Boot's 'go' command:: U-Boot: tftp $load_addr barebox.bin U-Boot: go $load_addr -With barebox already running on your board, this can be used to chainload another barebox:: +With barebox already running on your board, this can be used to chainload +another barebox. For instance, if you mounted a TFTP server to ``/mnt/tftp`` +(see :ref:`filesystems_tftp` for how to do that), chainload barebox with:: bootm /mnt/tftp/barebox.bin diff --git a/Documentation/user/booting-linux.rst b/Documentation/user/booting-linux.rst index 5b021f0662..98628faf9d 100644 --- a/Documentation/user/booting-linux.rst +++ b/Documentation/user/booting-linux.rst @@ -6,7 +6,7 @@ Booting Linux Introduction ------------ -The basic boot command in barebox is :ref:`command_bootm`. This command +The lowlevel boot command in barebox is :ref:`command_bootm`. This command can be used directly, but there is also a :ref:`command_boot` command which offers additional features like a boot sequence which tries to boot different entries until one succeeds. @@ -14,7 +14,7 @@ boot different entries until one succeeds. The bootm command ----------------- -The :ref:`command_bootm` command is the basic boot command. Depending on the +The :ref:`command_bootm` command is the lowlevel boot command. Depending on the architecture the bootm command handles different image types. On ARM the following images are supported: diff --git a/Documentation/user/networking.rst b/Documentation/user/networking.rst index 6eeb93dd88..8afb433837 100644 --- a/Documentation/user/networking.rst +++ b/Documentation/user/networking.rst @@ -1,26 +1,25 @@ Networking ========== -barebox has IPv4 networking support. Several protocols such as -:ref:`command_dhcp`, :ref:`filesystems_nfs`, :ref:`command_tftp` are -supported. +barebox has IPv4 networking support. Several protocols such as :ref:`DHCP +<command_dhcp>`, NFS and TFTP are supported. Network configuration --------------------- The first step for networking is configuring the network device. The network device is usually ``eth0``. The current configuration can be viewed with the -:ref:`command_devinfo` command: +:ref:`devinfo <command_devinfo>` command: .. code-block:: sh barebox:/ devinfo eth0 Parameters: - ipaddr: 192.168.23.197 - serverip: 192.168.23.1 + ethaddr: 00:1c:49:01:03:4b gateway: 192.168.23.1 + ipaddr: 192.168.23.197 netmask: 255.255.0.0 - ethaddr: 00:1c:49:01:03:4b + serverip: 192.168.23.1 The configuration can be changed on the command line with: @@ -28,19 +27,21 @@ The configuration can be changed on the command line with: eth0.ipaddr=172.0.0.10 -The :ref:`command_dhcp` command will change the settings based on the answer +The :ref:`dhcp command <command_dhcp>` will change the settings based on the answer from the DHCP server. This low-level configuration of the network interface is often not necessary. Normally the network settings should be edited in ``/env/network/eth0``, then the network interface -can be brought up using the :ref:`command_ifup` command. +can be brought up using the :ref:`ifup command <command_ifup>`. Network filesystems ------------------- -barebox supports NFS and TFTP as filesystem implementations. See :ref:`filesystems_nfs` -and :ref:`filesystems_tftp` for more information. After the network device has been -brought up a network filesystem can be mounted with: +barebox supports NFS and TFTP both with commands (:ref:`nfs <command_nfs>` and +:ref:`tftp <command_tftp>`) and as filesystem implementations; see +:ref:`filesystems_nfs` and :ref:`filesystems_tftp` for more information. After +the network device has been brought up, a network filesystem can be mounted +with: .. code-block:: sh @@ -52,8 +53,9 @@ or mount -t nfs 192.168.2.1:/export none /mnt -**NOTE:** this can often be hidden behind the :ref:`command_automount` command to make -mounting transparent to the user. +**NOTE:** The execution of the mount command can often be hidden behind the +:ref:`automount command <command_automount>`, to make mounting transparent to +the user. Network console --------------- @@ -71,11 +73,19 @@ risks. It can be enabled using: netconsole.ip=192.168.23.2 netconsole.active=ioe -This will send UDP packets to 192.168.23.2 on port 6666. On 192.168.23.2 the -scripts/netconsole script can be used to control barebox: +This will send UDP packets to a PC with IP address 192.168.23.2 and port 6666. + +The ``netconsole.active`` parameter consists of the fields "input" (i), +"output" (o) and "error" (e); if the fields are set, the respective channel is +activated on the network console. + +On the PC side, the ``scripts/netconsole`` script can be used to remote control +barebox: .. code-block:: sh scripts/netconsole <board IP> 6666 -The netconsole can be used just like any other console. +The netconsole can be used just like any other console. Note, however, that the +simple console protocol is UDP based, so there is no guarantee about packet +loss. diff --git a/Documentation/user/usb.rst b/Documentation/user/usb.rst index 99158a2676..8602a8f7fe 100644 --- a/Documentation/user/usb.rst +++ b/Documentation/user/usb.rst @@ -110,8 +110,10 @@ The Fastboot gadget supports the following commands: - fastboot boot - fastboot reboot -**NOTE** ``fastboot erase`` is not yet implemented. This means flashing MTD partitions -does not yet work. +``fastboot flash`` additionally supports image types UBI and Barebox. For UBI +Images and a MTD device as target, ubiformat is called. For a Barebox image +with an available barebox update handler for the fastboot exported device, the +barebox_update is called. The barebox Fastboot gadget supports the following non standard extensions: @@ -126,6 +128,53 @@ The barebox Fastboot gadget supports the following non standard extensions: command returns successfully when the barebox command was successful and it fails when the barebox command fails. +**Example booting kernel/devicetree/initrd with fastboot** + +In Barebox start the fastboot gadget: + +.. code-block:: sh + + usbgadget -A /kernel(kernel)c,/initrd(initrd)c,/devicetree(devicetree)c + +On the host you can use this script to start a kernel with kernel, devicetree +and initrd: + +.. code-block:: sh + + #!/bin/bash + + set -e + set -v + + if [ "$#" -lt 3 ] + then + echo "USAGE: $0 <KERNEL> <DT> <INITRD> [<ARGS>]" + exit 0 + fi + + kernel=$1 + dt=$2 + initrd=$3 + + shift 3 + + fastboot -i 7531 flash kernel $kernel + fastboot -i 7531 flash devicetree $dt + fastboot -i 7531 flash initrd $initrd + + + fastboot -i 7531 oem exec 'global linux.bootargs.fa'$ct'=rdinit=/sbin/init' + if [ $# -gt 0 ] + then + ct=1 + for i in $* + do + fastboot -i 7531 oem exec 'global linux.bootargs.fa'$ct'='"\"$i\"" + ct=$(($ct + 1)) + done + fi + timeout -k 5 3 fastboot -i 7531 oem exec -- bootm -o /devicetree -r /initrd /kernel + USB Composite Multifunction Gadget ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/Documentation/user/user-manual.rst b/Documentation/user/user-manual.rst index 0d6daee70e..be44f0d645 100644 --- a/Documentation/user/user-manual.rst +++ b/Documentation/user/user-manual.rst @@ -27,6 +27,7 @@ Contents: usb ubi booting-linux + remote-control system-setup reset-reason system-reset @@ -1,5 +1,5 @@ VERSION = 2016 -PATCHLEVEL = 02 +PATCHLEVEL = 03 SUBLEVEL = 0 EXTRAVERSION = NAME = None @@ -965,7 +965,7 @@ CLEAN_FILES += barebox System.map include/generated/barebox_default_env.h \ barebox.efi barebox.canon-a1100.bin # Directories & files removed with 'make mrproper' -MRPROPER_DIRS += include/config usr/include include/generated +MRPROPER_DIRS += include/config usr/include include/generated Documentation/commands MRPROPER_FILES += .config .config.old .version .old_version \ include/config.h \ Module.symvers tags TAGS cscope* diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 5a755c9636..9241b664c9 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -107,6 +107,7 @@ obj-$(CONFIG_MACH_SAMA5D4EK) += sama5d4ek/ obj-$(CONFIG_MACH_SCB9328) += scb9328/ obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += altera-socdk/ obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/ +obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox/ obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += solidrun-microsom/ diff --git a/arch/arm/boards/afi-gf/lowlevel.c b/arch/arm/boards/afi-gf/lowlevel.c index efe15ec99f..91b4b68c6d 100644 --- a/arch/arm/boards/afi-gf/lowlevel.c +++ b/arch/arm/boards/afi-gf/lowlevel.c @@ -196,7 +196,7 @@ static const struct module_pin_mux board_can_pin_mux[] = { {-1}, }; -extern char __dtb_am335x_afi_gf_start[]; +extern char __dtb_z_am335x_afi_gf_start[]; /** * @brief The basic entry point for board initialization. @@ -211,7 +211,7 @@ static noinline int gf_sram_init(void) { void *fdt; - fdt = __dtb_am335x_afi_gf_start; + fdt = __dtb_z_am335x_afi_gf_start; /* WDT1 is already running when the bootloader gets control * Disable it to avoid "random" resets @@ -258,7 +258,7 @@ ENTRY_FUNCTION(start_am33xx_afi_gf_sdram, r0, r1, r2) { void *fdt; - fdt = __dtb_am335x_afi_gf_start - get_runtime_offset(); + fdt = __dtb_z_am335x_afi_gf_start - get_runtime_offset(); putc_ll('>'); diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c index 79d598561c..100f64fdd9 100644 --- a/arch/arm/boards/beaglebone/lowlevel.c +++ b/arch/arm/boards/beaglebone/lowlevel.c @@ -103,9 +103,9 @@ static const struct am33xx_emif_regs ddr3_regs = { .sdram_ref_ctrl = 0xC30, }; -extern char __dtb_am335x_boneblack_start[]; -extern char __dtb_am335x_bone_common_start[]; -extern char __dtb_am335x_bone_start[]; +extern char __dtb_z_am335x_boneblack_start[]; +extern char __dtb_z_am335x_bone_common_start[]; +extern char __dtb_z_am335x_bone_start[]; /** * @brief The basic entry point for board initialization. @@ -121,7 +121,7 @@ static noinline int beaglebone_sram_init(void) uint32_t sdram_size; void *fdt; - fdt = __dtb_am335x_bone_common_start; + fdt = __dtb_z_am335x_bone_common_start; if (is_beaglebone_black()) sdram_size = SZ_512M; @@ -176,10 +176,10 @@ ENTRY_FUNCTION(start_am33xx_beaglebone_sdram, r0, r1, r2) if (is_beaglebone_black()) { sdram_size = SZ_512M; - fdt = __dtb_am335x_boneblack_start; + fdt = __dtb_z_am335x_boneblack_start; } else { sdram_size = SZ_256M; - fdt = __dtb_am335x_bone_start; + fdt = __dtb_z_am335x_bone_start; } fdt -= get_runtime_offset(); diff --git a/arch/arm/boards/edb93xx/edb93xx.c b/arch/arm/boards/edb93xx/edb93xx.c index c314320d21..0fb93d23dc 100644 --- a/arch/arm/boards/edb93xx/edb93xx.c +++ b/arch/arm/boards/edb93xx/edb93xx.c @@ -27,10 +27,16 @@ #include <malloc.h> #include <generated/mach-types.h> #include <mach/ep93xx-regs.h> +#include <net/ep93xx_eth.h> #include "edb93xx.h" #define DEVCFG_U1EN (1 << 18) +static struct ep93xx_eth_platform_data ep93xx_eth_info = { + .xcv_type = PHY_INTERFACE_MODE_MII, + .phy_addr = 1, +}; + static int ep93xx_mem_init(void) { arm_add_mem_device("ram0", CONFIG_EP93XX_SDRAM_BANK0_BASE, @@ -70,7 +76,7 @@ static int ep93xx_devices_init(void) * CS line 6, data width is 16 bit */ add_generic_device("ep93xx_eth", DEVICE_ID_DYNAMIC, NULL, 0, 0, IORESOURCE_MEM, - NULL); + &ep93xx_eth_info); armlinux_set_architecture(MACH_TYPE); diff --git a/arch/arm/boards/karo-tx6x/Makefile b/arch/arm/boards/karo-tx6x/Makefile index 01c7a259e9..51b7c2d449 100644 --- a/arch/arm/boards/karo-tx6x/Makefile +++ b/arch/arm/boards/karo-tx6x/Makefile @@ -1,2 +1,3 @@ obj-y += board.o lwl-y += lowlevel.o +obj-y += pmic-ltc3676.o pmic-rn5t567.o pmic-rn5t618.o diff --git a/arch/arm/boards/karo-tx6x/board.c b/arch/arm/boards/karo-tx6x/board.c index a921541bfc..31c1c3a9ff 100644 --- a/arch/arm/boards/karo-tx6x/board.c +++ b/arch/arm/boards/karo-tx6x/board.c @@ -16,6 +16,8 @@ * GNU General Public License for more details. */ +#define pr_fmt(fmt) "Karo-tx6: " fmt + #include <common.h> #include <gpio.h> #include <init.h> @@ -26,122 +28,40 @@ #include <mach/bbu.h> #include <mach/imx6.h> #include <mfd/imx6q-iomuxc-gpr.h> +#include "pmic.h" #define ETH_PHY_RST IMX_GPIO_NR(7, 6) #define ETH_PHY_PWR IMX_GPIO_NR(3, 20) #define ETH_PHY_INT IMX_GPIO_NR(7, 1) -#define DIV_ROUND(n,d) (((n) + ((d)/2)) / (d)) - -#define LTC3676_BUCK1 0x01 -#define LTC3676_BUCK2 0x02 -#define LTC3676_BUCK3 0x03 -#define LTC3676_BUCK4 0x04 -#define LTC3676_DVB1A 0x0A -#define LTC3676_DVB1B 0x0B -#define LTC3676_DVB2A 0x0C -#define LTC3676_DVB2B 0x0D -#define LTC3676_DVB3A 0x0E -#define LTC3676_DVB3B 0x0F -#define LTC3676_DVB4A 0x10 -#define LTC3676_DVB4B 0x11 -#define LTC3676_MSKPG 0x13 -#define LTC3676_CLIRQ 0x1f - -#define LTC3676_BUCK_DVDT_FAST (1 << 0) -#define LTC3676_BUCK_KEEP_ALIVE (1 << 1) -#define LTC3676_BUCK_CLK_RATE_LOW (1 << 2) -#define LTC3676_BUCK_PHASE_SEL (1 << 3) -#define LTC3676_BUCK_ENABLE_300 (1 << 4) -#define LTC3676_BUCK_PULSE_SKIP (0 << 5) -#define LTC3676_BUCK_BURST_MODE (1 << 5) -#define LTC3676_BUCK_CONTINUOUS (2 << 5) -#define LTC3676_BUCK_ENABLE (1 << 7) - -#define LTC3676_PGOOD_MASK (1 << 5) - -#define LTC3676_MSKPG_BUCK1 (1 << 0) -#define LTC3676_MSKPG_BUCK2 (1 << 1) -#define LTC3676_MSKPG_BUCK3 (1 << 2) -#define LTC3676_MSKPG_BUCK4 (1 << 3) -#define LTC3676_MSKPG_LDO2 (1 << 5) -#define LTC3676_MSKPG_LDO3 (1 << 6) -#define LTC3676_MSKPG_LDO4 (1 << 7) - -#define VDD_IO_VAL mV_to_regval(vout_to_vref(3300 * 10, 5)) -#define VDD_IO_VAL_LP mV_to_regval(vout_to_vref(3100 * 10, 5)) -#define VDD_IO_VAL_2 mV_to_regval(vout_to_vref(3300 * 10, 5_2)) -#define VDD_IO_VAL_2_LP mV_to_regval(vout_to_vref(3100 * 10, 5_2)) -#define VDD_SOC_VAL mV_to_regval(vout_to_vref(1425 * 10, 6)) -#define VDD_SOC_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 6)) -#define VDD_DDR_VAL mV_to_regval(vout_to_vref(1500 * 10, 7)) -#define VDD_DDR_VAL_LP mV_to_regval(vout_to_vref(1500 * 10, 7)) -#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1425 * 10, 8)) -#define VDD_CORE_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 8)) - -/* LDO1 */ -#define R1_1 470 -#define R2_1 150 -/* LDO4 */ -#define R1_4 470 -#define R2_4 150 -/* Buck1 */ -#define R1_5 390 -#define R2_5 110 -#define R1_5_2 470 -#define R2_5_2 150 -/* Buck2 (SOC) */ -#define R1_6 150 -#define R2_6 180 -/* Buck3 (DDR) */ -#define R1_7 150 -#define R2_7 140 -/* Buck4 (CORE) */ -#define R1_8 150 -#define R2_8 180 - -/* calculate voltages in 10mV */ -#define R1(idx) R1_##idx -#define R2(idx) R2_##idx - -#define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx))) -#define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx)) - -#define mV_to_regval(mV) DIV_ROUND(((((mV) < 4125) ? 4125 : (mV)) - 4125), 125) -#define regval_to_mV(v) (((v) * 125 + 4125)) - -static struct ltc3673_regs { - u8 addr; - u8 val; - u8 mask; -} ltc3676_regs[] = { - { LTC3676_MSKPG, ~LTC3676_MSKPG_BUCK1, }, - { LTC3676_DVB2B, VDD_SOC_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, }, - { LTC3676_DVB3B, VDD_DDR_VAL_LP, ~0x3f, }, - { LTC3676_DVB4B, VDD_CORE_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, }, - { LTC3676_DVB2A, VDD_SOC_VAL, ~0x3f, }, - { LTC3676_DVB3A, VDD_DDR_VAL, ~0x3f, }, - { LTC3676_DVB4A, VDD_CORE_VAL, ~0x3f, }, - { LTC3676_BUCK1, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, }, - { LTC3676_BUCK2, LTC3676_BUCK_BURST_MODE, }, - { LTC3676_BUCK3, LTC3676_BUCK_BURST_MODE, }, - { LTC3676_BUCK4, LTC3676_BUCK_BURST_MODE, }, - { LTC3676_CLIRQ, 0, }, /* clear interrupt status */ -}; -static struct ltc3673_regs ltc3676_regs_2[] = { - { LTC3676_DVB1B, VDD_IO_VAL_2_LP | LTC3676_PGOOD_MASK, ~0x3f, }, - { LTC3676_DVB1A, VDD_IO_VAL_2, ~0x3f, }, -}; +static void eth_init(void) +{ + void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR; + uint32_t val; + + val = readl(iomux + IOMUXC_GPR1); + val |= IMX6Q_GPR1_ENET_CLK_SEL_ANATOP; + writel(val, iomux + IOMUXC_GPR1); +} +static struct { + unsigned char addr; + int (*init)(struct i2c_client *client); + const char *name; +} i2c_addrs[] = { + { 0x3c, ltc3676_pmic_setup, "ltc3676" }, + { 0x32, rn5t618_pmic_setup, "rn5t618" }, + { 0x33, rn5t567_pmic_setup, "rn5t567" }, +}; -static int setup_pmic_voltages(void) +int setup_pmic_voltages(void) { - struct i2c_adapter *adapter = NULL; + struct i2c_adapter *adapter; struct i2c_client client; - int addr = 0x3c; - int bus = 0; + int ret = -ENODEV; int i; - struct ltc3673_regs *r; + int bus = 0; + uint8_t reg; adapter = i2c_get_adapter(bus); if (!adapter) { @@ -150,52 +70,65 @@ static int setup_pmic_voltages(void) } client.adapter = adapter; - client.addr = addr; - - r = ltc3676_regs; - for (i = 0; i < ARRAY_SIZE(ltc3676_regs); i++, r++) { - if (i2c_write_reg(&client, r->addr, &r->val, 1) != 1) { - pr_err("i2c write error\n"); - return -EIO; - } - } + for (i = 0; i < ARRAY_SIZE(i2c_addrs); i++) { + client.addr = i2c_addrs[i].addr; - r = ltc3676_regs_2; + pr_debug("Probing for I2C dev 0x%02x\n", client.addr); - for (i = 0; i < ARRAY_SIZE(ltc3676_regs_2); i++, r++) { - if (i2c_write_reg(&client, r->addr, &r->val, 1) != 1) { - pr_err("i2c write error\n"); - return -EIO; + ret = i2c_write_reg(&client, 0x00, ®, 0); + if (ret == 0) { + pr_info("Detected %s PMIC\n", i2c_addrs[i].name); + ret = i2c_addrs[i].init(&client); + goto out; } } - return 0; -} - -static void eth_init(void) -{ - void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR; - uint32_t val; + pr_err("No PMIC found\n"); +out: + if (ret) + pr_err("PMIC setup failed with %s\n", strerror(-ret)); - val = readl(iomux + IOMUXC_GPR1); - val |= IMX6Q_GPR1_ENET_CLK_SEL_ANATOP; - writel(val, iomux + IOMUXC_GPR1); + return ret; } +#define IMX6_SRC_SBMR1 0x04 + static int tx6x_devices_init(void) { + void __iomem *src_base = IOMEM(MX6_SRC_BASE_ADDR); + uint32_t sbmr1; + if (!of_machine_is_compatible("karo,imx6dl-tx6dl") && !of_machine_is_compatible("karo,imx6q-tx6q")) return 0; - barebox_set_hostname("tx6u"); + barebox_set_hostname("tx6"); eth_init(); setup_pmic_voltages(); - imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); + sbmr1 = readl(src_base + IMX6_SRC_SBMR1); + + /* + * Check if this board is booted from eMMC or NAND to enable the + * corresponding device. We can't use the regular bootsource + * function here as it might return that we are in serial + * downloader mode. Even if we are SBMR1[7] indicates whether + * this board has eMMC or NAND. + */ + if (sbmr1 & (1 << 7)) { + imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); + of_device_enable_and_register_by_name("environment-nand"); + of_device_enable_and_register_by_name("gpmi-nand@00112000"); + } else { + imx6_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc3.boot0", + BBU_HANDLER_FLAG_DEFAULT); + of_device_enable_and_register_by_name("environment-emmc"); + of_device_enable_and_register_by_name("usdhc@0219c000"); + } + return 0; } diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg new file mode 100644 index 0000000000..be4efe3c70 --- /dev/null +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg @@ -0,0 +1,174 @@ +soc imx6 +loadaddr 0x20000000 +dcdofs 0x400 + +wm 32 0x020e00a4 0x00000016 +wm 32 0x020e00c4 0x00000011 +wm 32 0x020e03b8 0x0000f079 +wm 32 0x020e03d8 0x0000f079 +wm 32 0x020e0898 0x00000000 +wm 32 0x020e089c 0x00000000 +wm 32 0x020e0248 0x00000012 +wm 32 0x020e02c8 0x00000015 +wm 32 0x020e06b0 0x000030b0 +wm 32 0x020e00a0 0x00000015 +wm 32 0x020e03b4 0x000030b0 +wm 32 0x020e024c 0x00000005 +wm 32 0x020e061c 0x000030b0 +wm 32 0x020c402c 0x006336c1 +wm 32 0x020c4034 0x00012093 +wm 32 0x020c4038 0x00012090 +wm 32 0x020c80e0 0x00002001 +wm 32 0x020c80a0 0x80082029 +wm 32 0x020c80b0 0x00065b9a +wm 32 0x020c80c0 0x000f4240 +wm 32 0x020e0004 0x48640005 +wm 32 0x020e02a8 0x00000001 +wm 32 0x020e02ac 0x00000001 +wm 32 0x020e0920 0x00000003 +wm 32 0x020e02c0 0x00000001 +wm 32 0x020e02c4 0x00000001 +wm 32 0x020e091c 0x00000003 +wm 32 0x020e02ec 0x00000000 +wm 32 0x020e05ac 0x00020030 +wm 32 0x020e05b4 0x00020030 +wm 32 0x020e0528 0x00020030 +wm 32 0x020e0520 0x00020030 +wm 32 0x020e0514 0x00020030 +wm 32 0x020e0510 0x00020030 +wm 32 0x020e05bc 0x00020030 +wm 32 0x020e05c4 0x00020030 +wm 32 0x020e052c 0x00020200 +wm 32 0x020e0530 0x00020200 +wm 32 0x020e0534 0x00020200 +wm 32 0x020e0538 0x00020200 +wm 32 0x020e053c 0x00020200 +wm 32 0x020e0540 0x00020200 +wm 32 0x020e0544 0x00020200 +wm 32 0x020e0548 0x00020200 +wm 32 0x020e054c 0x00020200 +wm 32 0x020e0550 0x00020200 +wm 32 0x020e0554 0x00020200 +wm 32 0x020e0558 0x00020200 +wm 32 0x020e055c 0x00020200 +wm 32 0x020e0560 0x00020200 +wm 32 0x020e0564 0x00020200 +wm 32 0x020e0568 0x00020200 +wm 32 0x020e056c 0x00020030 +wm 32 0x020e0578 0x00020030 +wm 32 0x020e0588 0x00020030 +wm 32 0x020e0594 0x00020030 +wm 32 0x020e057c 0x00020030 +wm 32 0x020e0590 0x00003000 +wm 32 0x020e0598 0x00003000 +wm 32 0x020e0580 0x00000000 +wm 32 0x020e0584 0x00000000 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00003030 +wm 32 0x020e05a0 0x00003030 +wm 32 0x020e0784 0x00000030 +wm 32 0x020e0788 0x00000030 +wm 32 0x020e0794 0x00000030 +wm 32 0x020e079c 0x00000030 +wm 32 0x020e07a0 0x00000030 +wm 32 0x020e07a4 0x00000030 +wm 32 0x020e07a8 0x00000030 +wm 32 0x020e0748 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0774 0x00020000 +wm 32 0x020e078c 0x00000030 +wm 32 0x020e0798 0x000c0000 +wm 32 0x020e0768 0x00002000 +wm 32 0x020e0770 0x00000000 +wm 32 0x020e0754 0x00000200 +wm 32 0x020e075c 0x00000200 +wm 32 0x020e0760 0x00000200 +wm 32 0x020e0764 0x00000200 +wm 32 0x020e076c 0x00000200 +wm 32 0x020e0778 0x00000200 +wm 32 0x020e077c 0x00000200 +wm 32 0x020e0780 0x00000200 +wm 32 0x021b001c 0x04008010 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b0800 0xa1390001 +wm 32 0x021b080c 0x001e001e +wm 32 0x021b0810 0x001e001e +wm 32 0x021b480c 0x001e001e +wm 32 0x021b4810 0x001e001e +wm 32 0x021b083c 0x43430349 +wm 32 0x021b0840 0x03330334 +wm 32 0x021b483c 0x434b0351 +wm 32 0x021b4840 0x033d030e +wm 32 0x021b0848 0x40404040 +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4848 0x40404040 +wm 32 0x021b4850 0x40404040 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b0018 0x00000742 +check 32 while_all_bits_clear 0x021b0018 0x00000002 +wm 32 0x021b001c 0x00008000 +check 32 while_any_bit_clear 0x021b001c 0x00004000 +wm 32 0x021b0000 0x831a0000 +check 32 while_any_bit_clear 0x021b0018 0x40000000 +wm 32 0x021b000c 0x545a79a4 +wm 32 0x021b0010 0xff538e64 +wm 32 0x021b0014 0x01ff00dd +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x005a1023 +wm 32 0x021b0008 0x24444040 +wm 32 0x021b0004 0x00020076 +wm 32 0x021b0040 0x00000027 +wm 32 0x021b001c 0x09308030 +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x00488032 +wm 32 0x021b001c 0x00008033 +wm 32 0x021b0020 0x0000c000 +wm 32 0x021b001c 0x00008020 +wm 32 0x021b0818 0x00022222 +wm 32 0x021b4818 0x00022222 +wm 32 0x021b0890 0x00000003 +wm 32 0x021b0404 0x00000001 +wm 32 0x021b001c 0x04008010 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b0800 0xa1390001 +check 32 while_all_bits_clear 0x021b0800 0x00010000 +wm 32 0x021b0800 0xa1380000 +wm 32 0x021b001c 0x00048033 +wm 32 0x020e05a8 0x00000030 +wm 32 0x020e05b0 0x00000030 +wm 32 0x020e0524 0x00000030 +wm 32 0x020e051c 0x00000030 +wm 32 0x020e0518 0x00000030 +wm 32 0x020e050c 0x00000030 +wm 32 0x020e05b8 0x00000030 +wm 32 0x020e05c0 0x00000030 +wm 32 0x021b001c 0x04008050 +wm 32 0x021b0860 0x00000030 +wm 32 0x021b4860 0x00000030 +check 32 while_all_bits_clear 0x021b0860 0x0000001f +check 32 while_all_bits_clear 0x021b4860 0x0000001f +wm 32 0x021b001c 0x04008050 +wm 32 0x021b0864 0x00000030 +check 32 while_all_bits_clear 0x021b0864 0x0000001f +wm 32 0x021b001c 0x04008050 +wm 32 0x021b4864 0x00000030 +check 32 while_all_bits_clear 0x021b4864 0x0000001f +wm 32 0x021b001c 0x00008033 +wm 32 0x021b0800 0xa138002b +wm 32 0x021b0020 0x00001800 +wm 32 0x021b0404 0x00001000 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b001c 0x00000000 +check 32 while_all_bits_clear 0x021b001c 0x00004000 + diff --git a/arch/arm/boards/karo-tx6x/lowlevel.c b/arch/arm/boards/karo-tx6x/lowlevel.c index 1e44b1b38d..1aa24c5842 100644 --- a/arch/arm/boards/karo-tx6x/lowlevel.c +++ b/arch/arm/boards/karo-tx6x/lowlevel.c @@ -18,6 +18,7 @@ #include <asm/barebox-arm.h> #include <image-metadata.h> #include <mach/generic.h> +#include <mach/esdctl.h> #include <linux/sizes.h> static inline void setup_uart(void) @@ -35,7 +36,7 @@ static inline void setup_uart(void) putc_ll('>'); } -extern char __dtb_imx6dl_tx6u_801x_start[]; +extern char __dtb_imx6dl_tx6u_start[]; BAREBOX_IMD_TAG_STRING(tx6x_mx6_memsize_1G, IMD_TYPE_PARAMETER, "memsize=1024", 0); @@ -52,7 +53,27 @@ ENTRY_FUNCTION(start_imx6dl_tx6x_1g, r0, r1, r2) if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); - fdt = __dtb_imx6dl_tx6u_801x_start - get_runtime_offset(); + fdt = __dtb_imx6dl_tx6u_start - get_runtime_offset(); barebox_arm_entry(0x10000000, SZ_1G, fdt); } + +extern char __dtb_imx6q_tx6q_start[]; + +ENTRY_FUNCTION(start_imx6q_tx6x_1g, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + arm_setup_stack(0x00920000 - 8); + + IMD_USED(tx6x_mx6_memsize_1G); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = __dtb_imx6q_tx6q_start - get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} diff --git a/arch/arm/boards/karo-tx6x/pmic-ltc3676.c b/arch/arm/boards/karo-tx6x/pmic-ltc3676.c new file mode 100644 index 0000000000..0cddb929fc --- /dev/null +++ b/arch/arm/boards/karo-tx6x/pmic-ltc3676.c @@ -0,0 +1,149 @@ +/* + * Copyright (C) 2014 Lothar Waßmann <LW@KARO-electronics.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <i2c/i2c.h> +#include "pmic.h" + +#define LTC3676_BUCK1 0x01 +#define LTC3676_BUCK2 0x02 +#define LTC3676_BUCK3 0x03 +#define LTC3676_BUCK4 0x04 +#define LTC3676_DVB1A 0x0A +#define LTC3676_DVB1B 0x0B +#define LTC3676_DVB2A 0x0C +#define LTC3676_DVB2B 0x0D +#define LTC3676_DVB3A 0x0E +#define LTC3676_DVB3B 0x0F +#define LTC3676_DVB4A 0x10 +#define LTC3676_DVB4B 0x11 +#define LTC3676_MSKPG 0x13 +#define LTC3676_CLIRQ 0x1f + +#define LTC3676_BUCK_DVDT_FAST (1 << 0) +#define LTC3676_BUCK_KEEP_ALIVE (1 << 1) +#define LTC3676_BUCK_CLK_RATE_LOW (1 << 2) +#define LTC3676_BUCK_PHASE_SEL (1 << 3) +#define LTC3676_BUCK_ENABLE_300 (1 << 4) +#define LTC3676_BUCK_PULSE_SKIP (0 << 5) +#define LTC3676_BUCK_BURST_MODE (1 << 5) +#define LTC3676_BUCK_CONTINUOUS (2 << 5) +#define LTC3676_BUCK_ENABLE (1 << 7) + +#define LTC3676_PGOOD_MASK (1 << 5) + +#define LTC3676_MSKPG_BUCK1 (1 << 0) +#define LTC3676_MSKPG_BUCK2 (1 << 1) +#define LTC3676_MSKPG_BUCK3 (1 << 2) +#define LTC3676_MSKPG_BUCK4 (1 << 3) +#define LTC3676_MSKPG_LDO2 (1 << 5) +#define LTC3676_MSKPG_LDO3 (1 << 6) +#define LTC3676_MSKPG_LDO4 (1 << 7) + +#define VDD_IO_VAL mV_to_regval(vout_to_vref(3300 * 10, 5)) +#define VDD_IO_VAL_LP mV_to_regval(vout_to_vref(3100 * 10, 5)) +#define VDD_IO_VAL_2 mV_to_regval(vout_to_vref(3300 * 10, 5_2)) +#define VDD_IO_VAL_2_LP mV_to_regval(vout_to_vref(3100 * 10, 5_2)) +#define VDD_SOC_VAL mV_to_regval(vout_to_vref(1425 * 10, 6)) +#define VDD_SOC_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 6)) +#define VDD_DDR_VAL mV_to_regval(vout_to_vref(1500 * 10, 7)) +#define VDD_DDR_VAL_LP mV_to_regval(vout_to_vref(1500 * 10, 7)) +#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1425 * 10, 8)) +#define VDD_CORE_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 8)) + +/* LDO1 */ +#define R1_1 470 +#define R2_1 150 +/* LDO4 */ +#define R1_4 470 +#define R2_4 150 +/* Buck1 */ +#define R1_5 390 +#define R2_5 110 +#define R1_5_2 470 +#define R2_5_2 150 +/* Buck2 (SOC) */ +#define R1_6 150 +#define R2_6 180 +/* Buck3 (DDR) */ +#define R1_7 150 +#define R2_7 140 +/* Buck4 (CORE) */ +#define R1_8 150 +#define R2_8 180 + +/* calculate voltages in 10mV */ +#define R1(idx) R1_##idx +#define R2(idx) R2_##idx + +#define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx))) +#define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx)) + +#define mV_to_regval(mV) DIV_ROUND(((((mV) < 4125) ? 4125 : (mV)) - 4125), 125) +#define regval_to_mV(v) (((v) * 125 + 4125)) + +static struct ltc3673_regs { + u8 addr; + u8 val; + u8 mask; +} ltc3676_regs[] = { + { LTC3676_MSKPG, ~LTC3676_MSKPG_BUCK1, }, + { LTC3676_DVB2B, VDD_SOC_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, }, + { LTC3676_DVB3B, VDD_DDR_VAL_LP, ~0x3f, }, + { LTC3676_DVB4B, VDD_CORE_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, }, + { LTC3676_DVB2A, VDD_SOC_VAL, ~0x3f, }, + { LTC3676_DVB3A, VDD_DDR_VAL, ~0x3f, }, + { LTC3676_DVB4A, VDD_CORE_VAL, ~0x3f, }, + { LTC3676_BUCK1, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, }, + { LTC3676_BUCK2, LTC3676_BUCK_BURST_MODE, }, + { LTC3676_BUCK3, LTC3676_BUCK_BURST_MODE, }, + { LTC3676_BUCK4, LTC3676_BUCK_BURST_MODE, }, + { LTC3676_CLIRQ, 0, }, /* clear interrupt status */ +}; + +static struct ltc3673_regs ltc3676_regs_2[] = { + { LTC3676_DVB1B, VDD_IO_VAL_2_LP | LTC3676_PGOOD_MASK, ~0x3f, }, + { LTC3676_DVB1A, VDD_IO_VAL_2, ~0x3f, }, +}; + + +int ltc3676_pmic_setup(struct i2c_client *client) +{ + int i; + struct ltc3673_regs *r; + + r = ltc3676_regs; + + for (i = 0; i < ARRAY_SIZE(ltc3676_regs); i++, r++) { + if (i2c_write_reg(client, r->addr, &r->val, 1) != 1) { + pr_err("i2c write error\n"); + return -EIO; + } + } + + r = ltc3676_regs_2; + + for (i = 0; i < ARRAY_SIZE(ltc3676_regs_2); i++, r++) { + if (i2c_write_reg(client, r->addr, &r->val, 1) != 1) { + pr_err("i2c write error\n"); + return -EIO; + } + } + + return 0; +} + diff --git a/arch/arm/boards/karo-tx6x/pmic-rn5t567.c b/arch/arm/boards/karo-tx6x/pmic-rn5t567.c new file mode 100644 index 0000000000..5397592c3c --- /dev/null +++ b/arch/arm/boards/karo-tx6x/pmic-rn5t567.c @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2014 Lothar Waßmann <LW@KARO-electronics.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <i2c/i2c.h> +#include "pmic.h" + +#define RN5T567_NOETIMSET 0x11 +#define RN5T567_LDORTC1_SLOT 0x2a +#define RN5T567_DC1CTL 0x2c +#define RN5T567_DC1CTL2 0x2d +#define RN5T567_DC2CTL 0x2e +#define RN5T567_DC2CTL2 0x2f +#define RN5T567_DC3CTL 0x30 +#define RN5T567_DC3CTL2 0x31 +#define RN5T567_DC1DAC 0x36 /* CORE */ +#define RN5T567_DC2DAC 0x37 /* SOC */ +#define RN5T567_DC3DAC 0x38 /* DDR */ +#define RN5T567_DC1DAC_SLP 0x3b +#define RN5T567_DC2DAC_SLP 0x3c +#define RN5T567_DC3DAC_SLP 0x3d +#define RN5T567_LDOEN1 0x44 +#define RN5T567_LDODIS 0x46 +#define RN5T567_LDOEN2 0x48 +#define RN5T567_LDO3DAC 0x4e /* IO */ +#define RN5T567_LDORTC1DAC 0x56 /* VBACKUP */ + +#define NOETIMSET_DIS_OFF_NOE_TIM (1 << 3) + +#define VDD_RTC_VAL mV_to_regval_rtc(3000) +#define VDD_HIGH_VAL mV_to_regval3(3000) +#define VDD_HIGH_VAL_LP mV_to_regval3(3000) +#define VDD_CORE_VAL mV_to_regval(1350) /* DCDC1 */ +#define VDD_CORE_VAL_LP mV_to_regval(900) +#define VDD_SOC_VAL mV_to_regval(1350) /* DCDC2 */ +#define VDD_SOC_VAL_LP mV_to_regval(900) +#define VDD_DDR_VAL mV_to_regval(1350) /* DCDC3 */ +#define VDD_DDR_VAL_LP mV_to_regval(1350) + +/* calculate voltages in 10mV */ +#define v2r(v,n,m) DIV_ROUND(((((v) < (n)) ? (n) : (v)) - (n)), (m)) +#define r2v(r,n,m) (((r) * (m) + (n)) / 10) + +/* DCDC1-3 */ +#define mV_to_regval(mV) v2r((mV) * 10, 6000, 125) +#define regval_to_mV(r) r2v(r, 6000, 125) + +/* LDO1-2 */ +#define mV_to_regval2(mV) v2r((mV) * 10, 9000, 250) +#define regval2_to_mV(r) r2v(r, 9000, 250) + +/* LDO3 */ +#define mV_to_regval3(mV) v2r((mV) * 10, 6000, 250) +#define regval3_to_mV(r) r2v(r, 6000, 250) + +/* LDORTC */ +#define mV_to_regval_rtc(mV) v2r((mV) * 10, 17000, 250) +#define regval_rtc_to_mV(r) r2v(r, 17000, 250) + +static struct rn5t567_regs { + u8 addr; + u8 val; + u8 mask; +} rn5t567_regs[] = { + { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, }, + { RN5T567_DC1DAC, VDD_CORE_VAL, }, + { RN5T567_DC2DAC, VDD_SOC_VAL, }, + { RN5T567_DC3DAC, VDD_DDR_VAL, }, + { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, }, + { RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, }, + { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, }, + { RN5T567_LDOEN1, 0x01f, ~0x1f, }, + { RN5T567_LDOEN2, 0x10, ~0x30, }, + { RN5T567_LDODIS, 0x00, }, + { RN5T567_LDO3DAC, VDD_HIGH_VAL, }, + { RN5T567_LDORTC1DAC, VDD_RTC_VAL, }, + { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, }, +}; + +static int rn5t567_setup_regs(struct i2c_client *client, struct rn5t567_regs *r, + size_t count) +{ + int ret; + int i; + + for (i = 0; i < count; i++, r++) { +#ifdef DEBUG + unsigned char value; + + ret = i2c_read_reg(client, r->addr, &value, 1); + if ((value & ~r->mask) != r->val) { + pr_debug("Changing PMIC reg %02x from %02x to %02x\n", + r->addr, value, r->val); + } + if (ret != 1) { + pr_debug("%s: failed to read PMIC register %02x: %d\n", + __func__, r->addr, ret); + return ret; + } +#endif + ret = i2c_write_reg(client, r->addr, &r->val, 1); + if (ret != 1) { + pr_err("%s: failed to write PMIC register %02x: %d\n", + __func__, r->addr, ret); + return ret; + } + } + return 0; +} + +int rn5t567_pmic_setup(struct i2c_client *client) +{ + int ret; + unsigned char value; + + ret = i2c_read_reg(client, 0x11, &value, 1); + if (ret != 1) { + pr_err("i2c read error\n"); + return ret; + } + + ret = rn5t567_setup_regs(client, rn5t567_regs, + ARRAY_SIZE(rn5t567_regs)); + if (ret) + return ret; + + ret = i2c_read_reg(client, RN5T567_DC1DAC, &value, 1); + if (ret == 1) { + pr_debug("VDDCORE set to %umV\n", regval_to_mV(value)); + } else { + pr_err("i2c read error\n"); + return ret; + } + + ret = i2c_read_reg(client, RN5T567_DC2DAC, &value, 1); + if (ret == 1) { + pr_debug("VDDSOC set to %umV\n", regval_to_mV(value)); + } else { + pr_err("i2c read error\n"); + return ret; + } + + return 0; +} diff --git a/arch/arm/boards/karo-tx6x/pmic-rn5t618.c b/arch/arm/boards/karo-tx6x/pmic-rn5t618.c new file mode 100644 index 0000000000..d5806d27ff --- /dev/null +++ b/arch/arm/boards/karo-tx6x/pmic-rn5t618.c @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2014 Lothar Waßmann <LW@KARO-electronics.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <i2c/i2c.h> +#include "pmic.h" + +#define RN5T618_NOETIMSET 0x11 +#define RN5T618_LDORTC1_SLOT 0x2a +#define RN5T618_DC1CTL 0x2c +#define RN5T618_DC1CTL2 0x2d +#define RN5T618_DC2CTL 0x2e +#define RN5T618_DC2CTL2 0x2f +#define RN5T618_DC3CTL 0x30 +#define RN5T618_DC3CTL2 0x31 +#define RN5T618_DC1DAC 0x36 /* CORE */ +#define RN5T618_DC2DAC 0x37 /* SOC */ +#define RN5T618_DC3DAC 0x38 /* DDR */ +#define RN5T618_DC1DAC_SLP 0x3b +#define RN5T618_DC2DAC_SLP 0x3c +#define RN5T618_DC3DAC_SLP 0x3d +#define RN5T618_LDOEN1 0x44 +#define RN5T618_LDODIS 0x46 +#define RN5T618_LDOEN2 0x48 +#define RN5T618_LDO3DAC 0x4e /* IO */ +#define RN5T618_LDORTCDAC 0x56 /* VBACKUP */ + +#define VDD_RTC_VAL mV_to_regval_rtc(3000) +#define VDD_HIGH_VAL mV_to_regval3(3000) +#define VDD_HIGH_VAL_LP mV_to_regval3(3000) +#define VDD_CORE_VAL mV_to_regval(1425) /* DCDC1 */ +#define VDD_CORE_VAL_LP mV_to_regval(900) +#define VDD_SOC_VAL mV_to_regval(1425) /* DCDC2 */ +#define VDD_SOC_VAL_LP mV_to_regval(900) +#define VDD_DDR_VAL mV_to_regval(1500) /* DCDC3 */ +#define VDD_DDR_VAL_LP mV_to_regval(1500) + +/* calculate voltages in 10mV */ +#define v2r(v,n,m) DIV_ROUND(((((v) < (n)) ? (n) : (v)) - (n)), (m)) +#define r2v(r,n,m) (((r) * (m) + (n)) / 10) + +/* DCDC1-3 */ +#define mV_to_regval(mV) v2r((mV) * 10, 6000, 125) +#define regval_to_mV(r) r2v(r, 6000, 125) + +/* LDO1-2 */ +#define mV_to_regval2(mV) v2r((mV) * 10, 9000, 250) +#define regval2_to_mV(r) r2v(r, 9000, 250) + +/* LDO3 */ +#define mV_to_regval3(mV) v2r((mV) * 10, 6000, 250) +#define regval3_to_mV(r) r2v(r, 6000, 250) + +/* LDORTC */ +#define mV_to_regval_rtc(mV) v2r((mV) * 10, 17000, 250) +#define regval_rtc_to_mV(r) r2v(r, 17000, 250) + +static struct rn5t618_regs { + u8 addr; + u8 val; + u8 mask; +} rn5t618_regs[] = { + { RN5T618_NOETIMSET, 0, }, + { RN5T618_DC1DAC, VDD_CORE_VAL, }, + { RN5T618_DC2DAC, VDD_SOC_VAL, }, + { RN5T618_DC3DAC, VDD_DDR_VAL, }, + { RN5T618_DC1DAC_SLP, VDD_CORE_VAL_LP, }, + { RN5T618_DC2DAC_SLP, VDD_SOC_VAL_LP, }, + { RN5T618_DC3DAC_SLP, VDD_DDR_VAL_LP, }, + { RN5T618_LDOEN1, 0x01f, ~0x1f, }, + { RN5T618_LDOEN2, 0x10, ~0x30, }, + { RN5T618_LDODIS, 0x00, }, + { RN5T618_LDO3DAC, VDD_HIGH_VAL, }, + { RN5T618_LDORTCDAC, VDD_RTC_VAL, }, + { RN5T618_LDORTC1_SLOT, 0x0f, ~0x3f, }, +}; + +static int rn5t618_setup_regs(struct i2c_client *client, struct rn5t618_regs *r, + size_t count) +{ + int ret; + int i; + + for (i = 0; i < count; i++, r++) { +#ifdef DEBUG + unsigned char value; + + ret = i2c_read_reg(client, r->addr, &value, 1); + if ((value & ~r->mask) != r->val) { + pr_debug("Changing PMIC reg %02x from %02x to %02x\n", + r->addr, value, r->val); + } + if (ret != 1) { + pr_debug("%s: failed to read PMIC register %02x: %d\n", + __func__, r->addr, ret); + return ret; + } +#endif + ret = i2c_write_reg(client, r->addr, &r->val, 1); + if (ret != 1) { + pr_err("%s: failed to write PMIC register %02x: %d\n", + __func__, r->addr, ret); + return ret; + } + } + return 0; +} + +int rn5t618_pmic_setup(struct i2c_client *client) +{ + int ret; + unsigned char value; + + ret = i2c_read_reg(client, 0x11, &value, 1); + if (ret) { + pr_err("i2c read error\n"); + return ret; + } + + ret = rn5t618_setup_regs(client, rn5t618_regs, + ARRAY_SIZE(rn5t618_regs)); + if (ret) + return ret; + + ret = i2c_read_reg(client, RN5T618_DC1DAC, &value, 1); + if (ret == 1) { + pr_debug("VDDCORE set to %umV\n", regval_to_mV(value)); + } else { + pr_err("i2c read error\n"); + return ret; + } + + ret = i2c_read_reg(client, RN5T618_DC2DAC, &value, 1); + if (ret == 1) { + pr_debug("VDDSOC set to %umV\n", regval_to_mV(value)); + } else { + pr_err("i2c read error\n"); + return ret; + } + + return 0; +} diff --git a/arch/arm/boards/karo-tx6x/pmic.h b/arch/arm/boards/karo-tx6x/pmic.h new file mode 100644 index 0000000000..2427a52e50 --- /dev/null +++ b/arch/arm/boards/karo-tx6x/pmic.h @@ -0,0 +1,8 @@ + +#include <i2c/i2c.h> + +#define DIV_ROUND(n,d) (((n) + ((d)/2)) / (d)) + +int ltc3676_pmic_setup(struct i2c_client *client); +int rn5t567_pmic_setup(struct i2c_client *client); +int rn5t618_pmic_setup(struct i2c_client *client); diff --git a/arch/arm/boards/phytec-som-am335x/lowlevel.c b/arch/arm/boards/phytec-som-am335x/lowlevel.c index d7afbb6af3..73e75eb491 100644 --- a/arch/arm/boards/phytec-som-am335x/lowlevel.c +++ b/arch/arm/boards/phytec-som-am335x/lowlevel.c @@ -102,8 +102,8 @@ static noinline void physom_board_entry(unsigned long bootinfo, int sdram, void #define PHYTEC_ENTRY_MLO(name, fdt_name, sdram) \ ENTRY_FUNCTION(name, bootinfo, r1, r2) \ { \ - extern char __dtb_##fdt_name##_start[]; \ - void *fdt =__dtb_##fdt_name##_start - \ + extern char __dtb_z_##fdt_name##_start[]; \ + void *fdt = __dtb_z_##fdt_name##_start - \ get_runtime_offset(); \ physom_board_entry(bootinfo, sdram, fdt); \ } @@ -111,8 +111,8 @@ static noinline void physom_board_entry(unsigned long bootinfo, int sdram, void #define PHYTEC_ENTRY(name, fdt_name) \ ENTRY_FUNCTION(name, r0, r1, r2) \ { \ - extern char __dtb_##fdt_name##_start[]; \ - void *fdt =__dtb_##fdt_name##_start - \ + extern char __dtb_z_##fdt_name##_start[]; \ + void *fdt = __dtb_z_##fdt_name##_start - \ get_runtime_offset(); \ am335x_barebox_entry(fdt); \ } @@ -123,6 +123,8 @@ PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_256mb, am335x_phytec_phycore_s PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J256M16HA15EIT_512MB); PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_2x512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J512M8125IT_2x512MB); PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_1024mb, am335x_phytec_phycore_som_mlo, PHYCORE_IM8G16D3FBBG15EI_1024MB); +PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_r2_sram_512mb, am335x_phytec_phycore_som_mlo, PHYCORE_R2_MT41K256M16TW107IT_512MB); +PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_r2_sram_256mb, am335x_phytec_phycore_som_mlo, PHYCORE_R2_MT41K128M16JT_256MB); PHYTEC_ENTRY(start_am33xx_phytec_phycore_sdram, am335x_phytec_phycore_som); PHYTEC_ENTRY(start_am33xx_phytec_phycore_no_spi_sdram, am335x_phytec_phycore_som_no_spi); PHYTEC_ENTRY(start_am33xx_phytec_phycore_no_eeprom_sdram, am335x_phytec_phycore_som_no_eeprom); diff --git a/arch/arm/boards/phytec-som-am335x/ram-timings.h b/arch/arm/boards/phytec-som-am335x/ram-timings.h index 698b0732b0..884874caf7 100644 --- a/arch/arm/boards/phytec-som-am335x/ram-timings.h +++ b/arch/arm/boards/phytec-som-am335x/ram-timings.h @@ -30,6 +30,8 @@ enum { PHYCORE_MT41J256M16HA15EIT_512MB, PHYCORE_MT41J512M8125IT_2x512MB, PHYCORE_IM8G16D3FBBG15EI_1024MB, + PHYCORE_R2_MT41K256M16TW107IT_512MB, + PHYCORE_R2_MT41K128M16JT_256MB, PHYCARD_NT5CB128M16BP_256MB, }; @@ -192,6 +194,44 @@ struct am335x_sdram_timings physom_timings[] = { .dll_lock_diff0 = 0x0, }, }, + + /* 512MB R2 */ + [PHYCORE_R2_MT41K256M16TW107IT_512MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAD4DB, + .emif_tim2 = 0x266B7FDA, + .emif_tim3 = 0x501F867F, + .sdram_config = 0x61C05332, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30, + }, + .data = { + .rd_slave_ratio0 = 0x37, + .wr_dqs_slave_ratio0 = 0x38, + .fifo_we_slave_ratio0 = 0x92, + .wr_slave_ratio0 = 0x72, + }, + }, + + /* 256MB R2 */ + [PHYCORE_R2_MT41K128M16JT_256MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAD4DB, + .emif_tim2 = 0x26437FDA, + .emif_tim3 = 0x501F83FF, + .sdram_config = 0x61C052B2, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30, + }, + .data = { + .rd_slave_ratio0 = 0x36, + .wr_dqs_slave_ratio0 = 0x38, + .fifo_we_slave_ratio0 = 0x99, + .wr_slave_ratio0 = 0x73, + }, + }, }; #endif diff --git a/arch/arm/boards/terasic-de0-nano-soc/Makefile b/arch/arm/boards/terasic-de0-nano-soc/Makefile new file mode 100644 index 0000000000..8c927fe291 --- /dev/null +++ b/arch/arm/boards/terasic-de0-nano-soc/Makefile @@ -0,0 +1,2 @@ +obj-y += lowlevel.o board.o +pbl-y += lowlevel.o diff --git a/arch/arm/boards/terasic-de0-nano-soc/board.c b/arch/arm/boards/terasic-de0-nano-soc/board.c new file mode 100644 index 0000000000..919bfc8c54 --- /dev/null +++ b/arch/arm/boards/terasic-de0-nano-soc/board.c @@ -0,0 +1,35 @@ +#include <common.h> +#include <types.h> +#include <driver.h> +#include <init.h> +#include <asm/armlinux.h> +#include <linux/micrel_phy.h> +#include <linux/phy.h> +#include <linux/sizes.h> +#include <fcntl.h> +#include <fs.h> +#include <mach/socfpga-regs.h> + +static int phy_fixup(struct phy_device *dev) +{ + /* + * min rx data delay, max rx/tx clock delay, + * min rx/tx control delay + */ + phy_write_mmd_indirect(dev, 4, 2, 0); + phy_write_mmd_indirect(dev, 5, 2, 0); + phy_write_mmd_indirect(dev, 8, 2, 0x003ff); + return 0; +} + +static int socfpga_init(void) +{ + if (!of_machine_is_compatible("terasic,de0-nano-soc")) + return 0; + + if (IS_ENABLED(CONFIG_PHYLIB)) + phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, phy_fixup); + + return 0; +} +console_initcall(socfpga_init); diff --git a/arch/arm/boards/terasic-de0-nano-soc/config.h b/arch/arm/boards/terasic-de0-nano-soc/config.h new file mode 100644 index 0000000000..da84fa5f6b --- /dev/null +++ b/arch/arm/boards/terasic-de0-nano-soc/config.h @@ -0,0 +1 @@ +/* nothing */ diff --git a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c new file mode 100644 index 0000000000..4e9ac7fb77 --- /dev/null +++ b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c @@ -0,0 +1,674 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <mach/scan-manager.h> + +static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00020080, + 0x18060000, + 0x08000000, + 0x00018020, + 0x00000000, + 0x00004000, + 0x00010040, + 0x04010000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x00020000, + 0x02008000, + 0x02000000, + 0x00000008, + 0x00002008, + 0x00001000, +}; + +static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { + 0x00100000, + 0x10040000, + 0x100000C0, + 0x00000040, + 0x00010040, + 0x00008000, + 0x00060180, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x00010040, + 0x10000000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x00020000, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x00010000, + 0x04000000, + 0x00000000, + 0x00000010, + 0x00004000, + 0x00000800, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000008, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00401000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00600802, + 0x00000000, + 0x80200000, + 0x80000600, + 0x00000200, + 0x00000100, + 0x00300401, + 0xC0100400, + 0x40100000, + 0x40000300, + 0x000C0100, + 0x00000080, +}; + +static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { + 0x300C0300, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C0300C0, + 0x00008000, + 0x00080000, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00020000, + 0x00004000, + 0x200300C0, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x00002000, + 0x10018060, + 0x06018000, + 0x06000000, + 0x00010018, + 0x00006018, + 0x00001000, + 0x00010000, + 0x00000000, + 0x03000000, + 0x0000800C, + 0x00C01004, + 0x00000800, +}; + +static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { + 0x0C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x4D034071, + 0x1A681A03, + 0x806180D0, + 0x34071C06, + 0x01A034D0, + 0x380D0000, + 0x0820680E, + 0x034D0340, + 0xD000001A, + 0x0680E380, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x4D034071, + 0x1A681A03, + 0x806180D0, + 0x34071C06, + 0x01A00040, + 0x180D0002, + 0x71C06806, + 0x034D0340, + 0xD01A681A, + 0x06806180, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xD32CA3D6, + 0xF551451E, + 0x034CD348, + 0x821A0000, + 0x0000D000, + 0x030C0680, + 0xD659647A, + 0x1ED32CA3, + 0x48F55145, + 0x00034CD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x59647A03, + 0x932CA3DE, + 0xF651451E, + 0x035CD348, + 0x821A0041, + 0x0000D000, + 0x00000680, + 0xDE59647A, + 0x1ED32CA3, + 0x48F55145, + 0x00035492, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x59647A03, + 0xD32CA3DE, + 0xF551451E, + 0x035CB2C8, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDE59647A, + 0x1ED2AAA3, + 0xC8F55965, + 0x00035CB2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xD32CA3DE, + 0xF551451E, + 0x035CD348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDE59647A, + 0x1ED32CA3, + 0x48F55145, + 0x00035CD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; diff --git a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c new file mode 100644 index 0000000000..6d937abda5 --- /dev/null +++ b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c @@ -0,0 +1,76 @@ +#include <common.h> +#include <linux/sizes.h> +#include <io.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/generic.h> +#include <debug_ll.h> +#include <asm/cache.h> +#include "sdram_config.h" +#include <mach/sdram_config.h> +#include "pinmux_config.c" +#include "pll_config.h" +#include <mach/pll_config.h> +#include "sequencer_defines.h" +#include "sequencer_auto.h" +#include <mach/sequencer.c> +#include "sequencer_auto_inst_init.c" +#include "sequencer_auto_ac_init.c" +#include "iocsr_config_cyclone5.c" + +extern char __dtb_socfpga_cyclone5_de0_nano_soc_start[]; + +ENTRY_FUNCTION(start_socfpga_de0_nano_soc, r0, r1, r2) +{ + void *fdt; + + arm_cpu_lowlevel_init(); + + fdt = __dtb_socfpga_cyclone5_de0_nano_soc_start - get_runtime_offset(); + + barebox_arm_entry(0x0, SZ_1G, fdt); +} + +static noinline void de0_nano_soc_entry(void) +{ + struct socfpga_io_config io_config; + int ret; + + arm_early_mmu_cache_invalidate(); + + relocate_to_current_adr(); + setup_c(); + + io_config.pinmux = sys_mgr_init_table; + io_config.num_pin = ARRAY_SIZE(sys_mgr_init_table); + io_config.iocsr_emac_mixed2 = iocsr_scan_chain0_table; + io_config.iocsr_mixed1_flash = iocsr_scan_chain1_table; + io_config.iocsr_general = iocsr_scan_chain2_table; + io_config.iocsr_ddr = iocsr_scan_chain3_table; + + socfpga_lowlevel_init(&cm_default_cfg, &io_config); + + puts_ll("lowlevel init done\n"); + puts_ll("SDRAM setup...\n"); + + socfpga_sdram_mmr_init(); + + puts_ll("SDRAM calibration...\n"); + + ret = socfpga_mem_calibration(); + if (!ret) + hang(); + + puts_ll("done\n"); + + barebox_arm_entry(0x0, SZ_1G, NULL); +} + +ENTRY_FUNCTION(start_socfpga_de0_nano_soc_xload, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + + arm_setup_stack(0xffff0000 + SZ_64K - SZ_4K - 16); + + de0_nano_soc_entry(); +} diff --git a/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c b/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c new file mode 100644 index 0000000000..fd37608acb --- /dev/null +++ b/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c @@ -0,0 +1,240 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <common.h> + +unsigned long sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 1, /* GENERALIO15 */ + 1, /* GENERALIO16 */ + 1, /* GENERALIO17 */ + 1, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 0, /* MIXED1IO15 */ + 0, /* MIXED1IO16 */ + 0, /* MIXED1IO17 */ + 0, /* MIXED1IO18 */ + 0, /* MIXED1IO19 */ + 0, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; diff --git a/arch/arm/boards/terasic-de0-nano-soc/pll_config.h b/arch/arm/boards/terasic-de0-nano-soc/pll_config.h new file mode 100644 index 0000000000..bb2f0eab0e --- /dev/null +++ b/arch/arm/boards/terasic-de0-nano-soc/pll_config.h @@ -0,0 +1,107 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PRELOADER_PLL_CONFIG_H_ +#define _PRELOADER_PLL_CONFIG_H_ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 (1) + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (73) +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511) +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511) +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (18) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39) +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (19) +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (4) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (4) +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) +#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) + +#define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_OSC2_HZ (25000000) +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0) +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0) +#define CONFIG_HPS_CLK_MAINVCO_HZ (1850000000) +#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) +#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000) +#define CONFIG_HPS_CLK_EMAC0_HZ (1953125) +#define CONFIG_HPS_CLK_EMAC1_HZ (250000000) +#define CONFIG_HPS_CLK_USBCLK_HZ (200000000) +#define CONFIG_HPS_CLK_NAND_HZ (50000000) +#define CONFIG_HPS_CLK_SDMMC_HZ (200000000) +#define CONFIG_HPS_CLK_QSPI_HZ (3613281) +#define CONFIG_HPS_CLK_SPIM_HZ (200000000) +#define CONFIG_HPS_CLK_CAN0_HZ (12500000) +#define CONFIG_HPS_CLK_CAN1_HZ (12500000) +#define CONFIG_HPS_CLK_GPIODB_HZ (32000) +#define CONFIG_HPS_CLK_L4_MP_HZ (100000000) +#define CONFIG_HPS_CLK_L4_SP_HZ (100000000) + +#define CONFIG_HPS_ALTERAGRP_MPUCLK (1) +#define CONFIG_HPS_ALTERAGRP_MAINCLK (4) +#define CONFIG_HPS_ALTERAGRP_DBGATCLK (4) + +#endif /* _PRELOADER_PLL_CONFIG_H_ */ diff --git a/arch/arm/boards/terasic-de0-nano-soc/sdram_config.h b/arch/arm/boards/terasic-de0-nano-soc/sdram_config.h new file mode 100644 index 0000000000..292ff6d4d7 --- /dev/null +++ b/arch/arm/boards/terasic-de0-nano-soc/sdram_config.h @@ -0,0 +1,108 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SDRAM_CONFIG_H +#define __SDRAM_CONFIG_H + +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE (2) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL (8) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN (1) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT (10) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS (0) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL (7) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL (0) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL (7) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD (3) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW (15) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC (120) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI (3120) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD (6) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP (6) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR (6) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR (4) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP (3) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS (14) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC (20) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD (4) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD (4) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT (512) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT (3) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES (0) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES (8) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS (10) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS (15) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS (3) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS (1) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH (32) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH (8) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN (0) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK (3) +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL (2) +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH (2) +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN (0) +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE (0) +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC (0) +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY (0x3FFD1088) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 (0x21084210) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 (0x1EF84) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 (0x2020) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 (0xF800) +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 (0x200) + +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH (0x44555) +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP (0x2C011000) +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP (0xB00088) +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP (0x760210) +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP (0x980543) +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR (0x5A56A) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 (0x20820820) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 (0x8208208) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 (0) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 (0x41041041) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 (0x410410) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \ +(0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \ +(0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \ +(0x0101) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0x1) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0x1) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0x3) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST (0x311) + +#endif /*#ifndef__SDRAM_CONFIG_H*/ diff --git a/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto.h b/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto.h new file mode 100644 index 0000000000..3797a2584f --- /dev/null +++ b/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto.h @@ -0,0 +1,227 @@ +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#define __RW_MGR_ac_mrs1 0x04 +#define __RW_MGR_ac_mrs3 0x06 +#define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C +#define __RW_MGR_ac_act_1 0x11 +#define __RW_MGR_ac_write_postdata 0x1A +#define __RW_MGR_ac_act_0 0x10 +#define __RW_MGR_ac_des 0x0D +#define __RW_MGR_ac_init_reset_1_cke_0 0x01 +#define __RW_MGR_ac_write_data 0x19 +#define __RW_MGR_ac_init_reset_0_cke_0 0x00 +#define __RW_MGR_ac_read_bank_0_1_norden 0x22 +#define __RW_MGR_ac_pre_all 0x12 +#define __RW_MGR_ac_mrs0_user 0x02 +#define __RW_MGR_ac_mrs0_dll_reset 0x03 +#define __RW_MGR_ac_read_bank_0_0 0x1D +#define __RW_MGR_ac_write_bank_0_col_1 0x16 +#define __RW_MGR_ac_read_bank_0_1 0x1F +#define __RW_MGR_ac_write_bank_1_col_0 0x15 +#define __RW_MGR_ac_write_bank_1_col_1 0x17 +#define __RW_MGR_ac_write_bank_0_col_0 0x14 +#define __RW_MGR_ac_read_bank_1_0 0x1E +#define __RW_MGR_ac_mrs1_mirr 0x0A +#define __RW_MGR_ac_read_bank_1_1 0x20 +#define __RW_MGR_ac_des_odt_1 0x0E +#define __RW_MGR_ac_mrs0_dll_reset_mirr 0x09 +#define __RW_MGR_ac_zqcl 0x07 +#define __RW_MGR_ac_write_predata 0x18 +#define __RW_MGR_ac_mrs0_user_mirr 0x08 +#define __RW_MGR_ac_ref 0x13 +#define __RW_MGR_ac_nop 0x0F +#define __RW_MGR_ac_rdimm 0x23 +#define __RW_MGR_ac_mrs2_mirr 0x0B +#define __RW_MGR_ac_write_bank_0_col_0_nodata 0x1B +#define __RW_MGR_ac_read_en 0x21 +#define __RW_MGR_ac_mrs3_mirr 0x0C +#define __RW_MGR_ac_mrs2 0x05 +#define __RW_MGR_CONTENT_ac_mrs1 0x10090006 +#define __RW_MGR_CONTENT_ac_mrs3 0x100B0000 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata_wl_1 0x18980000 +#define __RW_MGR_CONTENT_ac_act_1 0x106B0000 +#define __RW_MGR_CONTENT_ac_write_postdata 0x38780000 +#define __RW_MGR_CONTENT_ac_act_0 0x10680000 +#define __RW_MGR_CONTENT_ac_des 0x30780000 +#define __RW_MGR_CONTENT_ac_init_reset_1_cke_0 0x20780000 +#define __RW_MGR_CONTENT_ac_write_data 0x3CF80000 +#define __RW_MGR_CONTENT_ac_init_reset_0_cke_0 0x20700000 +#define __RW_MGR_CONTENT_ac_read_bank_0_1_norden 0x10580008 +#define __RW_MGR_CONTENT_ac_pre_all 0x10280400 +#define __RW_MGR_CONTENT_ac_mrs0_user 0x10080471 +#define __RW_MGR_CONTENT_ac_mrs0_dll_reset 0x10080570 +#define __RW_MGR_CONTENT_ac_read_bank_0_0 0x13580000 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_1 0x1C980008 +#define __RW_MGR_CONTENT_ac_read_bank_0_1 0x13580008 +#define __RW_MGR_CONTENT_ac_write_bank_1_col_0 0x1C9B0000 +#define __RW_MGR_CONTENT_ac_write_bank_1_col_1 0x1C9B0008 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_0 0x1C980000 +#define __RW_MGR_CONTENT_ac_read_bank_1_0 0x135B0000 +#define __RW_MGR_CONTENT_ac_mrs1_mirr 0x100A0006 +#define __RW_MGR_CONTENT_ac_read_bank_1_1 0x135B0008 +#define __RW_MGR_CONTENT_ac_des_odt_1 0x38780000 +#define __RW_MGR_CONTENT_ac_mrs0_dll_reset_mirr 0x100804E8 +#define __RW_MGR_CONTENT_ac_zqcl 0x10380400 +#define __RW_MGR_CONTENT_ac_write_predata 0x38F80000 +#define __RW_MGR_CONTENT_ac_mrs0_user_mirr 0x10080469 +#define __RW_MGR_CONTENT_ac_ref 0x10480000 +#define __RW_MGR_CONTENT_ac_nop 0x30780000 +#define __RW_MGR_CONTENT_ac_rdimm 0x10780000 +#define __RW_MGR_CONTENT_ac_mrs2_mirr 0x10090218 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata 0x18180000 +#define __RW_MGR_CONTENT_ac_read_en 0x33780000 +#define __RW_MGR_CONTENT_ac_mrs3_mirr 0x100B0000 +#define __RW_MGR_CONTENT_ac_mrs2 0x100A0218 + +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#define __RW_MGR_READ_B2B_WAIT2 0x6B +#define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define __RW_MGR_REFRESH_ALL 0x14 +#define __RW_MGR_ZQCL 0x06 +#define __RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define __RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define __RW_MGR_ACTIVATE_0_AND_1 0x0D +#define __RW_MGR_MRS2_MIRR 0x0A +#define __RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define __RW_MGR_ACTIVATE_1 0x0F +#define __RW_MGR_MRS2 0x04 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define __RW_MGR_MRS1 0x03 +#define __RW_MGR_IDLE_LOOP1 0x7B +#define __RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define __RW_MGR_MRS3 0x05 +#define __RW_MGR_IDLE_LOOP2 0x7A +#define __RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define __RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define __RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define __RW_MGR_RDIMM_CMD 0x79 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define __RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define __RW_MGR_GUARANTEED_READ_CONT 0x54 +#define __RW_MGR_REFRESH_DELAY 0x15 +#define __RW_MGR_MRS3_MIRR 0x0B +#define __RW_MGR_IDLE 0x00 +#define __RW_MGR_READ_B2B 0x59 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define __RW_MGR_GUARANTEED_WRITE 0x18 +#define __RW_MGR_PRECHARGE_ALL 0x12 +#define __RW_MGR_SGLE_READ 0x7D +#define __RW_MGR_MRS0_USER_MIRR 0x0C +#define __RW_MGR_RETURN 0x01 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define __RW_MGR_MRS0_USER 0x07 +#define __RW_MGR_GUARANTEED_READ 0x4C +#define __RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define __RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define __RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define __RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define __RW_MGR_MRS0_DLL_RESET 0x02 +#define __RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define __RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define __RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define __RW_MGR_MRS1_MIRR 0x09 +#define __RW_MGR_READ_B2B_WAIT1 0x61 +#define __RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680 +#define __RW_MGR_CONTENT_REFRESH_ALL 0x000980 +#define __RW_MGR_CONTENT_ZQCL 0x008380 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00 +#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800 +#define __RW_MGR_CONTENT_MRS2_MIRR 0x008580 +#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680 +#define __RW_MGR_CONTENT_ACTIVATE_1 0x000880 +#define __RW_MGR_CONTENT_MRS2 0x008280 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00 +#define __RW_MGR_CONTENT_MRS1 0x008200 +#define __RW_MGR_CONTENT_IDLE_LOOP1 0x00A680 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8 +#define __RW_MGR_CONTENT_MRS3 0x008300 +#define __RW_MGR_CONTENT_IDLE_LOOP2 0x008680 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88 +#define __RW_MGR_CONTENT_RDIMM_CMD 0x009180 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0 +#define __RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168 +#define __RW_MGR_CONTENT_REFRESH_DELAY 0x00A680 +#define __RW_MGR_CONTENT_MRS3_MIRR 0x008600 +#define __RW_MGR_CONTENT_IDLE 0x080000 +#define __RW_MGR_CONTENT_READ_B2B 0x040E88 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68 +#define __RW_MGR_CONTENT_PRECHARGE_ALL 0x000900 +#define __RW_MGR_CONTENT_SGLE_READ 0x040F08 +#define __RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400 +#define __RW_MGR_CONTENT_RETURN 0x080680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80 +#define __RW_MGR_CONTENT_MRS0_USER 0x008100 +#define __RW_MGR_CONTENT_GUARANTEED_READ 0x001168 +#define __RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480 +#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080 +#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00 +#define __RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180 +#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80 +#define __RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158 +#define __RW_MGR_CONTENT_MRS1_MIRR 0x008500 +#define __RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680 diff --git a/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c new file mode 100644 index 0000000000..fe0764b0ce --- /dev/null +++ b/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c @@ -0,0 +1,69 @@ +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +static const uint32_t ac_rom_init_size = 36; +static const uint32_t ac_rom_init[36] = +{ + 0x20700000, + 0x20780000, + 0x10080471, + 0x10080570, + 0x10090006, + 0x100a0218, + 0x100b0000, + 0x10380400, + 0x10080469, + 0x100804e8, + 0x100a0006, + 0x10090218, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; diff --git a/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_inst_init.c b/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_inst_init.c new file mode 100644 index 0000000000..09bdc582d1 --- /dev/null +++ b/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_inst_init.c @@ -0,0 +1,161 @@ +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include <common.h> +static const uint32_t inst_rom_init_size = 127; +static const uint32_t inst_rom_init[127] = +{ + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; diff --git a/arch/arm/boards/terasic-de0-nano-soc/sequencer_defines.h b/arch/arm/boards/terasic-de0-nano-soc/sequencer_defines.h new file mode 100644 index 0000000000..f4d43951c8 --- /dev/null +++ b/arch/arm/boards/terasic-de0-nano-soc/sequencer_defines.h @@ -0,0 +1,160 @@ +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#ifndef _SEQUENCER_DEFINES_H_ +#define _SEQUENCER_DEFINES_H_ + +#define AC_ROM_MR1_MIRR 0000000000110 +#define AC_ROM_MR1_OCD_ENABLE +#define AC_ROM_MR2_MIRR 0001000011000 +#define AC_ROM_MR3_MIRR 0000000000000 +#define AC_ROM_MR0_CALIB +#define AC_ROM_MR0_DLL_RESET_MIRR 0010011101000 +#define AC_ROM_MR0_DLL_RESET 0010101110000 +#define AC_ROM_MR0_MIRR 0010001101001 +#define AC_ROM_MR0 0010001110001 +#define AC_ROM_MR1 0000000000110 +#define AC_ROM_MR2 0001000011000 +#define AC_ROM_MR3 0000000000000 +#define AFI_CLK_FREQ 401 +#define AFI_RATE_RATIO 1 +#define ARRIAVGZ 0 +#define ARRIAV 0 +#define AVL_CLK_FREQ 67 +#define BFM_MODE 0 +#define BURST2 0 +#define CALIBRATE_BIT_SLIPS 0 +#define CALIB_LFIFO_OFFSET 12 +#define CALIB_VFIFO_OFFSET 10 +#define CYCLONEV 1 +#define DDR2 0 +#define DDR3 1 +#define DDRX 1 +#define DM_PINS_ENABLED 1 +#define ENABLE_ASSERT 0 +#define ENABLE_BRINGUP_DEBUGGING 0 +#define ENABLE_DELAY_CHAIN_WRITE 0 +#define ENABLE_DQS_IN_CENTERING 1 +#define ENABLE_DQS_OUT_CENTERING 0 +#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0 +#define ENABLE_INST_ROM_WRITE 1 +#define ENABLE_MARGIN_REPORT_GEN 0 +#define ENABLE_NON_DESTRUCTIVE_CALIB 0 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define ENABLE_TCL_DEBUG 0 +#define FAKE_CAL_FAIL 0 +#define FULL_RATE 1 +#define GUARANTEED_READ_BRINGUP_TEST 0 +#define HALF_RATE 0 +#define HARD_PHY 1 +#define HARD_VFIFO 1 +#define HCX_COMPAT_MODE 0 +#define HHP_HPS_SIMULATION 0 +#define HHP_HPS_VERIFICATION 0 +#define HHP_HPS 1 +#define HPS_HW 1 +#define HR_DDIO_OUT_HAS_THREE_REGS 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DM_OUT_RESERVE 0 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_DQ_OUT_RESERVE 0 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define LPDDR1 0 +#define LPDDR2 0 +#define LRDIMM 0 +#define M10_DQ_WIDTH_8 0 +#define M10_DQ_WIDTH_16 0 +#define M10_DQ_WIDTH_24 0 +#define MARGIN_VARIATION_TEST 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define MEM_ADDR_WIDTH 13 +#define MRS_MIRROR_PING_PONG_ATSO 0 +#define MULTIPLE_AFI_WLAT 0 +#define NUM_SHADOW_REGS 1 +#define QDRII 0 +#define QUARTER_RATE 0 +#define RDIMM 0 +#define READ_AFTER_WRITE_CALIBRATION 1 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c +#define RLDRAM3 0 +#define RLDRAMII 0 +#define RLDRAMX 0 +#define RUNTIME_CAL_REPORT 0 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_ADDRESS_WIDTH 15 +#define RW_MGR_MEM_BANK_WIDTH 3 +#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1 +#define RW_MGR_MEM_CLK_EN_WIDTH 1 +#define RW_MGR_MEM_CONTROL_WIDTH 1 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_ODT_WIDTH 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_MR0_BL 1 +#define RW_MGR_MR0_CAS_LATENCY 7 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_WRITE_TO_DEBUG_READ 1.0 +#define SKEW_CALIBRATION 0 +#define STATIC_FULL_CALIBRATION 1 +#define STATIC_SIM_FILESET 0 +#define STATIC_SKIP_MEM_INIT 0 +#define STRATIXV 0 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TINIT_CNTR0_VAL 99 +#define TRACKING_ERROR_TEST 0 +#define TRACKING_WATCH_TEST 0 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 +#define TRESET_CNTR0_VAL 99 +#define TW0_CAPTURE_CLOCKS 0 +#define USE_DQS_TRACKING 1 +#define USE_SHADOW_REGS 0 +#define USE_USER_RDIMM_VALUE 0 + +#endif /* _SEQUENCER_DEFINES_H_ */ diff --git a/arch/arm/boards/terasic-sockit/pinmux_config.c b/arch/arm/boards/terasic-sockit/pinmux_config.c index 3a7cd2bc62..bcf27dbe1e 100644 --- a/arch/arm/boards/terasic-sockit/pinmux_config.c +++ b/arch/arm/boards/terasic-sockit/pinmux_config.c @@ -29,7 +29,7 @@ #include <common.h> -unsigned long sys_mgr_init_table[] = { +static unsigned long sys_mgr_init_table[] = { 0, /* EMACIO0 */ 2, /* EMACIO1 */ 2, /* EMACIO2 */ diff --git a/arch/arm/configs/am335x_defconfig b/arch/arm/configs/am335x_defconfig index 9563865065..9196fb8b36 100644 --- a/arch/arm/configs/am335x_defconfig +++ b/arch/arm/configs/am335x_defconfig @@ -75,13 +75,16 @@ CONFIG_CMD_FLASH=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_LED=y +CONFIG_CMD_NANDTEST=y CONFIG_CMD_SPI=y CONFIG_CMD_LED_TRIGGER=y CONFIG_CMD_USBGADGET=y +CONFIG_CMD_WD=y CONFIG_CMD_BAREBOX_UPDATE=y CONFIG_CMD_OF_NODE=y CONFIG_CMD_OF_PROPERTY=y CONFIG_CMD_OF_DISPLAY_TIMINGS=y +CONFIG_CMD_OF_FIXUP_STATUS=y CONFIG_CMD_OFTREE=y CONFIG_CMD_TIME=y CONFIG_NET=y @@ -123,6 +126,8 @@ CONFIG_LED_GPIO=y CONFIG_LED_GPIO_OF=y CONFIG_LED_TRIGGERS=y CONFIG_EEPROM_AT24=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_OMAP=y CONFIG_GPIO_GENERIC_PLATFORM=y CONFIG_PINCTRL_SINGLE=y CONFIG_BUS_OMAP_GPMC=y diff --git a/arch/arm/configs/socfpga-xload-2_defconfig b/arch/arm/configs/socfpga-xload-2_defconfig new file mode 100644 index 0000000000..97997cf752 --- /dev/null +++ b/arch/arm/configs/socfpga-xload-2_defconfig @@ -0,0 +1,28 @@ +CONFIG_ARCH_SOCFPGA=y +CONFIG_ARCH_SOCFPGA_XLOAD=y +CONFIG_MACH_SOCFPGA_ALTERA_SOCDK=y +CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC=y +CONFIG_THUMB2_BAREBOX=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +# CONFIG_ARM_EXCEPTIONS is not set +# CONFIG_MEMINFO is not set +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_DUMMY=y +CONFIG_RELOCATABLE=y +CONFIG_SHELL_NONE=y +# CONFIG_ERRNO_MESSAGES is not set +# CONFIG_TIMESTAMP is not set +# CONFIG_DEFAULT_ENVIRONMENT is not set +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +# CONFIG_MCI_WRITE is not set +CONFIG_MCI_DW=y +CONFIG_MFD_MC13XXX=y +CONFIG_EEPROM_AT25=y +# CONFIG_FS_RAMFS is not set +# CONFIG_FS_DEVFS is not set +CONFIG_FS_FAT=y +CONFIG_BOOTSTRAP=y +CONFIG_BOOTSTRAP_DISK=y diff --git a/arch/arm/configs/socfpga-xload_defconfig b/arch/arm/configs/socfpga-xload_defconfig index 9f64adfd74..521f3f1c1f 100644 --- a/arch/arm/configs/socfpga-xload_defconfig +++ b/arch/arm/configs/socfpga-xload_defconfig @@ -3,12 +3,10 @@ CONFIG_ARCH_SOCFPGA_XLOAD=y CONFIG_MACH_SOCFPGA_EBV_SOCRATES=y CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT=y CONFIG_THUMB2_BAREBOX=y -# CONFIG_CMD_ARM_CPUINFO is not set CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y # CONFIG_ARM_EXCEPTIONS is not set # CONFIG_MEMINFO is not set CONFIG_MMU=y -CONFIG_TEXT_BASE=0x0 CONFIG_MALLOC_SIZE=0x0 CONFIG_MALLOC_DUMMY=y CONFIG_RELOCATABLE=y diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig index 7fbe045e27..6cbc28ea42 100644 --- a/arch/arm/configs/socfpga_defconfig +++ b/arch/arm/configs/socfpga_defconfig @@ -1,6 +1,7 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_MACH_SOCFPGA_EBV_SOCRATES=y CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT=y +CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC=y CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y diff --git a/arch/arm/configs/tegra_v7_defconfig b/arch/arm/configs/tegra_v7_defconfig index c7b59ac1d0..ff92c392cb 100644 --- a/arch/arm/configs/tegra_v7_defconfig +++ b/arch/arm/configs/tegra_v7_defconfig @@ -8,7 +8,7 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y CONFIG_MMU=y CONFIG_STACK_SIZE=0x10000 -CONFIG_MALLOC_SIZE=0x4000000 +CONFIG_MALLOC_SIZE=0x0 CONFIG_KALLSYMS=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S index b76222d8f3..e5baa12346 100644 --- a/arch/arm/cpu/lowlevel.S +++ b/arch/arm/cpu/lowlevel.S @@ -4,6 +4,8 @@ .section ".text_bare_init_","ax" ENTRY(arm_cpu_lowlevel_init) + /* save lr, since it may be banked away with a processor mode change */ + mov r2, lr /* set the cpu to SVC32 mode, mask irq and fiq */ mrs r12, cpsr bic r12, r12, #0x1f @@ -54,5 +56,5 @@ ENTRY(arm_cpu_lowlevel_init) mcr p15, 0, r12, c1, c0, 0 /* SCTLR */ - mov pc, lr + mov pc, r2 ENDPROC(arm_cpu_lowlevel_init) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d85c23768e..b83c1109ef 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -58,6 +58,7 @@ pbl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o pbl-dtb-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o pbl-dtb-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o +pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o pbl-dtb-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o @@ -67,7 +68,8 @@ pbl-dtb-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o pbl-dtb-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o pbl-dtb-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o pbl-dtb-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o -pbl-dtb-$(CONFIG_MACH_TX6X) += imx6dl-tx6u-801x.dtb.o +pbl-dtb-$(CONFIG_MACH_TX6X) += imx6dl-tx6u.dtb.o +pbl-dtb-$(CONFIG_MACH_TX6X) += imx6q-tx6q.dtb.o pbl-dtb-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o pbl-dtb-$(CONFIG_MACH_USI_TOPKICK) += kirkwood-topkick-bb.dtb.o pbl-dtb-$(CONFIG_MACH_VARISCITE_MX6) += imx6q-var-custom.dtb.o diff --git a/arch/arm/dts/am335x-bone-common.dts b/arch/arm/dts/am335x-bone-common.dts index 91745d3f62..0488cbe1fc 100644 --- a/arch/arm/dts/am335x-bone-common.dts +++ b/arch/arm/dts/am335x-bone-common.dts @@ -9,6 +9,7 @@ #include "am33xx.dtsi" #include "am33xx-strip.dtsi" +#include "am33xx-clocks-strip.dtsi" #include "am335x-bone-common.dtsi" / { diff --git a/arch/arm/dts/am335x-phytec-phycard-som.dtsi b/arch/arm/dts/am335x-phytec-phycard-som.dtsi index c0b2456636..d1dfa86bca 100644 --- a/arch/arm/dts/am335x-phytec-phycard-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phycard-som.dtsi @@ -92,7 +92,7 @@ status = "okay"; clock-frequency = <400000>; - eeprom: 24c32@52 { + eeprom: eeprom@54 { status = "disabled"; compatible = "atmel,24c32"; pagesize = <32>; diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dtsi b/arch/arm/dts/am335x-phytec-phycore-som.dtsi index ba0589cdc5..f3a1d4d45a 100644 --- a/arch/arm/dts/am335x-phytec-phycore-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phycore-som.dtsi @@ -143,7 +143,7 @@ status = "okay"; clock-frequency = <400000>; - eeprom: 24c32@52 { + eeprom: eeprom@52 { status = "disabled"; compatible = "atmel,24c32"; pagesize = <32>; diff --git a/arch/arm/dts/imx6dl-tx6u.dts b/arch/arm/dts/imx6dl-tx6u.dts new file mode 100644 index 0000000000..77fda6203f --- /dev/null +++ b/arch/arm/dts/imx6dl-tx6u.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include <arm/imx6q.dtsi> +#include <arm/imx6qdl-tx6.dtsi> +#include "imx6qdl.dtsi" +#include "imx6qdl-tx6x.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-801x Module"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; +}; + diff --git a/arch/arm/dts/imx6q-tx6q.dts b/arch/arm/dts/imx6q-tx6q.dts new file mode 100644 index 0000000000..6063dd4fe5 --- /dev/null +++ b/arch/arm/dts/imx6q-tx6q.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include <arm/imx6q.dtsi> +#include <arm/imx6qdl-tx6.dtsi> +#include "imx6q.dtsi" +#include "imx6qdl-tx6x.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q Module"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; +}; + diff --git a/arch/arm/dts/imx6dl-tx6u-801x.dts b/arch/arm/dts/imx6qdl-tx6x.dtsi index a480408f50..9c5d676a74 100644 --- a/arch/arm/dts/imx6dl-tx6u-801x.dts +++ b/arch/arm/dts/imx6qdl-tx6x.dtsi @@ -1,21 +1,32 @@ -#include <arm/imx6dl-tx6u-801x.dts> -#include "imx6qdl.dtsi" - / { - model = "Ka-Ro electronics TX6U-801x Module"; - compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; - chosen { linux,stdout-path = &uart1; - environment@0 { + environment-nand { + status = "disabled"; compatible = "barebox,environment"; device-path = &gpmi, "partname:barebox-environment"; }; + + environment-emmc { + status = "disabled"; + compatible = "barebox,environment"; + device-path = &usdhc4, "partname:boot1"; + }; }; + + gpio-keys { + status = "disabled"; + }; +}; + +&fec { + phy-reset-duration = <22>; }; &gpmi { + status = "disabled"; + partition@0 { label = "barebox"; reg = <0x0 0x400000>; @@ -53,13 +64,31 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 >; }; - }; -}; -&fec { - phy-reset-duration = <22>; + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; + }; }; &ocotp { barebox,provide-mac-address = <&fec 0x620>; }; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + non-removable; + no-1-8-v; + fsl,wp-controller; + status = "disabled"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file mode 100644 index 0000000000..087fc71e60 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <arm/socfpga_cyclone5_de0_sockit.dts> +#include "socfpga.dtsi" + +/ { + model = "Terasic DE0-Nano-SoC/Atlas-SoC Kit"; + compatible = "terasic,de0-nano-soc","altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path = &uart0; + }; + + leds: gpio-leds { + }; + + buttons: gpio-keys { + }; +}; diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts index 91e1354448..3e7f879d68 100644 --- a/arch/arm/dts/tegra30-beaver.dts +++ b/arch/arm/dts/tegra30-beaver.dts @@ -10,6 +10,7 @@ aliases { rtc0 = "/i2c@7000d000/tps65911@2d"; rtc1 = "/rtc@7000e000"; + serial0 = &uarta; }; chosen { diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index 6346bb440c..d2b075e3e8 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c @@ -173,6 +173,7 @@ void sama5_smc_configure(int id, int cs, struct sam9_smc_config *config) static int at91sam9_smc_probe(struct device_d *dev) { + struct resource *iores; int id = dev->id; if (id < 0) { @@ -182,11 +183,12 @@ static int at91sam9_smc_probe(struct device_d *dev) return -EIO; } - smc_base_addr[id] = dev_request_mem_region(dev, 0); - if (IS_ERR(smc_base_addr[id])) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "Impossible to request smc.%d\n", id); - return PTR_ERR(smc_base_addr[id]); + return PTR_ERR(iores); } + smc_base_addr[id] = IOMEM(iores->start); return 0; } diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index c631c33cf3..33ae145193 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -698,8 +698,8 @@ config IMX_OCOTP_WRITE MAC to 12:34:56:78:9A:BC (2 words with address 0x22 (OCOTP_MAC0) and address 0x23 (OCOTP_MAC1)). To calculate the file offset multiply the value of the address by 4. - mw -l -d /dev/imx-ocotp 0x8C 0x00001234 - mw -l -d /dev/imx-ocotp 0x88 0x56789ABC + mw -l -d /dev/imx-ocotp 0x8C 0x00001234 + mw -l -d /dev/imx-ocotp 0x88 0x56789ABC config HAB bool diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c index bb1318f3bf..5f600a9da3 100644 --- a/arch/arm/mach-imx/clk-imx1.c +++ b/arch/arm/mach-imx/clk-imx1.c @@ -87,11 +87,13 @@ int __init mx1_clocks_init(void __iomem *regs, unsigned long fref) static int imx1_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *regs; - regs = dev_request_mem_region(dev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + regs = IOMEM(iores->start); mx1_clocks_init(regs, 32000); diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c index b48bb8ccd3..546461b8ee 100644 --- a/arch/arm/mach-imx/clk-imx21.c +++ b/arch/arm/mach-imx/clk-imx21.c @@ -107,13 +107,15 @@ static const char *spll_sel_clks[] = { static int imx21_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *base; unsigned long lref = 32768; unsigned long href = 26000000; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); writel(PCCR0_UART1_EN | PCCR0_UART2_EN | PCCR0_UART3_EN | PCCR0_UART4_EN | PCCR0_CSPI1_EN | PCCR0_CSPI2_EN | PCCR0_SDHC1_EN | diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index 7d10078376..fccea7fafe 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -85,11 +85,13 @@ static const char *per_sel_clks[] = { static int imx25_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *base; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); writel((1 << 3) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 15) | (1 << 19) | (1 << 21) | (1 << 22) | diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index bd1753ab8a..4b63244211 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -156,11 +156,13 @@ static const char *clko_sel_clks[] = { static int imx27_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *base; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); writel(PCCR0_SDHC3_EN | PCCR0_SDHC2_EN | PCCR0_SDHC1_EN | PCCR0_PWM_EN | PCCR0_KPP_EN | PCCR0_IIM_EN | diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c index eb9bb095e0..8d135c9a1f 100644 --- a/arch/arm/mach-imx/clk-imx31.c +++ b/arch/arm/mach-imx/clk-imx31.c @@ -80,11 +80,13 @@ static const char *per_sel[] = { static int imx31_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *base; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); writel(0xffffffff, base + CCM_CGR0); writel(0xffffffff, base + CCM_CGR1); diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c index dde23395a1..2433d73cb6 100644 --- a/arch/arm/mach-imx/clk-imx35.c +++ b/arch/arm/mach-imx/clk-imx35.c @@ -90,14 +90,16 @@ static const char *ipg_per_sel[] = { static int imx35_ccm_probe(struct device_d *dev) { + struct resource *iores; u32 pdr0, consumer_sel, hsp_sel; struct arm_ahb_div *aad; unsigned char *hsp_div; void __iomem *base; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); writel(0xffffffff, base + CCM_CGR0); writel(0xffffffff, base + CCM_CGR1); diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c index 70db31c18e..51a6460c9e 100644 --- a/arch/arm/mach-imx/clk-imx5.c +++ b/arch/arm/mach-imx/clk-imx5.c @@ -304,11 +304,13 @@ int __init mx51_clocks_init(struct device_d *dev, void __iomem *regs) static int imx51_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *regs; - regs = dev_request_mem_region(dev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + regs = IOMEM(iores->start); mx51_clocks_init(dev, regs); @@ -392,9 +394,13 @@ int __init mx53_clocks_init(struct device_d *dev, void __iomem *regs) static int imx53_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *regs; - regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + regs = IOMEM(iores->start); mx53_clocks_init(dev, regs); diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c index 597e502050..daa58018a6 100644 --- a/arch/arm/mach-imx/clk-imx6.c +++ b/arch/arm/mach-imx/clk-imx6.c @@ -337,12 +337,14 @@ static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb) static int imx6_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *base, *anatop_base, *ccm_base; anatop_base = (void *)MX6_ANATOP_BASE_ADDR; - ccm_base = dev_request_mem_region(dev, 0); - if (IS_ERR(ccm_base)) - return PTR_ERR(ccm_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ccm_base = IOMEM(iores->start); base = anatop_base; @@ -443,6 +445,9 @@ static int imx6_ccm_probe(struct device_d *dev) /* name parent_name reg shift */ clks[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); + clks[IMX6QDL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); + clks[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); + clks[IMX6QDL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); clks[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); clks[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); clks[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); @@ -477,6 +482,7 @@ static int imx6_ccm_probe(struct device_d *dev) clks[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); clks[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); clks[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); + clks[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10); clks[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); clks[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index e88e240202..d758957d4d 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -118,15 +118,17 @@ static struct clk_div_table video_div_table[] = { static int imx6sx_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *base, *anatop_base, *ccm_base; struct device_node *ccm_node = dev->device_node; clks[IMX6SX_CLK_DUMMY] = clk_fixed("dummy", 0); anatop_base = (void *)MX6_ANATOP_BASE_ADDR; - ccm_base = dev_request_mem_region(dev, 0); - if (IS_ERR(ccm_base)) - return PTR_ERR(ccm_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ccm_base = IOMEM(iores->start); base = anatop_base; diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c index 8766e39b0e..66dcea4cfb 100644 --- a/arch/arm/mach-imx/clocksource.c +++ b/arch/arm/mach-imx/clocksource.c @@ -91,6 +91,7 @@ static struct notifier_block imx_clock_notifier = { static int imx_gpt_probe(struct device_d *dev) { + struct resource *iores; int i; int ret; unsigned long rate; @@ -103,9 +104,10 @@ static int imx_gpt_probe(struct device_d *dev) if (ret) return ret; - timer_base = dev_request_mem_region(dev, 0); - if (IS_ERR(timer_base)) - return PTR_ERR(timer_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + timer_base = IOMEM(iores->start); /* setup GP Timer 1 */ writel(TCTL_SWR, timer_base + GPT_TCTL); diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index 2f9f5e971e..e633b62993 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -308,6 +308,7 @@ static void imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) static int imx_esdctl_probe(struct device_d *dev) { + struct resource *iores; struct imx_esdctl_data *data; int ret; void *base; @@ -316,9 +317,10 @@ static int imx_esdctl_probe(struct device_d *dev) if (ret) return ret; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); if (imx_esdctl_disabled) return 0; diff --git a/arch/arm/mach-imx/iim.c b/arch/arm/mach-imx/iim.c index c16a6c6879..dbd8ccf054 100644 --- a/arch/arm/mach-imx/iim.c +++ b/arch/arm/mach-imx/iim.c @@ -389,6 +389,7 @@ static inline void imx_iim_init_dt(struct device_d *dev, struct iim_priv *iim) static int imx_iim_probe(struct device_d *dev) { + struct resource *iores; struct iim_priv *iim; int i, ret; struct imx_iim_drvdata *drvdata = NULL; @@ -414,9 +415,10 @@ static int imx_iim_probe(struct device_d *dev) iim->fuse_supply = ERR_PTR(-ENODEV); - iim->base = dev_request_mem_region(dev, 0); - if (IS_ERR(iim->base)) - return PTR_ERR(iim->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + iim->base = IOMEM(iores->start); for (i = 0; i < IIM_NUM_BANKS; i++) { ret = imx_iim_add_bank(iim, i); diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c index ac90c53bb7..821ce660f5 100644 --- a/arch/arm/mach-imx/imx-bbu-internal.c +++ b/arch/arm/mach-imx/imx-bbu-internal.c @@ -132,6 +132,9 @@ static int imx_bbu_check_prereq(struct bbu_data *data) if (ret) return ret; + if (!strncmp(data->devicefile, "/dev/", 5)) + device_detect_by_name(data->devicefile + 5); + return 0; } diff --git a/arch/arm/mach-imx/ocotp.c b/arch/arm/mach-imx/ocotp.c index e2f10e12a0..1dc9108a2b 100644 --- a/arch/arm/mach-imx/ocotp.c +++ b/arch/arm/mach-imx/ocotp.c @@ -371,6 +371,7 @@ static struct regmap_bus imx_ocotp_regmap_bus = { static int imx_ocotp_probe(struct device_d *dev) { + struct resource *iores; void __iomem *base; struct ocotp_priv *priv; int ret = 0; @@ -380,9 +381,10 @@ static int imx_ocotp_probe(struct device_d *dev) if (ret) return ret; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); imx_ocotp_init_dt(dev, base); diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c index 00758450cc..72f3e8240b 100644 --- a/arch/arm/mach-mxs/ocotp.c +++ b/arch/arm/mach-mxs/ocotp.c @@ -179,12 +179,14 @@ static struct file_operations mxs_ocotp_ops = { static int mxs_ocotp_probe(struct device_d *dev) { + struct resource *iores; int err; struct ocotp_priv *priv = xzalloc(sizeof (*priv)); - priv->base = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->base = IOMEM(iores->start); priv->clk = clk_get(dev, NULL); if (IS_ERR(priv->clk)) diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig index 5c68062365..d7c863ca12 100644 --- a/arch/arm/mach-omap/Kconfig +++ b/arch/arm/mach-omap/Kconfig @@ -44,6 +44,7 @@ config ARCH_AM33XX select GENERIC_GPIO select OFTREE select OMAP_CLOCK_SOURCE_DMTIMER + select ARM_USE_COMPRESSED_DTB help Say Y here if you are using Texas Instrument's AM33xx based platform diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 73b26efd20..94689e3ecd 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -20,6 +20,10 @@ config MACH_SOCFPGA_EBV_SOCRATES select HAVE_DEFAULT_ENVIRONMENT_NEW bool "EBV Socrates" +config MACH_SOCFPGA_TERASIC_DE0_NANO_SOC + select HAVE_DEFAULT_ENVIRONMENT_NEW + bool "Terasic DE0-NANO-SoC aka Atlas" + config MACH_SOCFPGA_TERASIC_SOCKIT select HAVE_DEFAULT_ENVIRONMENT_NEW bool "Terasic SoCKit" diff --git a/arch/arm/mach-tegra/tegra20-pmc.c b/arch/arm/mach-tegra/tegra20-pmc.c index 02f0bf7499..f7c7ac918f 100644 --- a/arch/arm/mach-tegra/tegra20-pmc.c +++ b/arch/arm/mach-tegra/tegra20-pmc.c @@ -202,11 +202,13 @@ static void tegra20_pmc_detect_reset_cause(void) static int tegra20_pmc_probe(struct device_d *dev) { - pmc_base = dev_request_mem_region(dev, 0); - if (IS_ERR(pmc_base)) { + struct resource *iores; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(pmc_base); + return PTR_ERR(iores); } + pmc_base = IOMEM(iores->start); tegra_powergate_init(); diff --git a/arch/arm/mach-tegra/tegra20-timer.c b/arch/arm/mach-tegra/tegra20-timer.c index a8e4d7b53d..2ba58bd65e 100644 --- a/arch/arm/mach-tegra/tegra20-timer.c +++ b/arch/arm/mach-tegra/tegra20-timer.c @@ -45,17 +45,19 @@ static struct clocksource cs = { static int tegra20_timer_probe(struct device_d *dev) { + struct resource *iores; u32 reg; /* use only one timer */ if (timer_base) return -EBUSY; - timer_base = dev_request_mem_region(dev, 0); - if (IS_ERR(timer_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(timer_base); + return PTR_ERR(iores); } + timer_base = IOMEM(iores->start); /* * calibrate timer to run at 1MHz diff --git a/arch/arm/mach-zynq/clk-zynq7000.c b/arch/arm/mach-zynq/clk-zynq7000.c index 2b9260ba1d..cd49d8478f 100644 --- a/arch/arm/mach-zynq/clk-zynq7000.c +++ b/arch/arm/mach-zynq/clk-zynq7000.c @@ -359,12 +359,14 @@ static struct clk *zynq_cpu_subclk(const char *name, static int zynq_clock_probe(struct device_d *dev) { + struct resource *iores; void __iomem *slcr_base; unsigned long ps_clk_rate = 33333330; - slcr_base = dev_request_mem_region(dev, 0); - if (IS_ERR(slcr_base)) - return PTR_ERR(slcr_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + slcr_base = IOMEM(iores->start); clks[ps_clk] = clk_fixed("ps_clk", ps_clk_rate); diff --git a/arch/efi/efi/efi-device.c b/arch/efi/efi/efi-device.c index 7db8e48f7b..678a28399d 100644 --- a/arch/efi/efi/efi-device.c +++ b/arch/efi/efi/efi-device.c @@ -168,8 +168,10 @@ static struct efi_device *efi_add_device(efi_handle_t *handle, efi_guid_t **guid efiret = BS->open_protocol(handle, &efi_device_path_protocol_guid, &devpath, NULL, NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL); - if (EFI_ERROR(efiret)) + if (EFI_ERROR(efiret)) { + free(guidarr); return ERR_PTR(-EINVAL); + } efidev = xzalloc(sizeof(*efidev)); diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index fdf62e8608..06a516d70f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -6,6 +6,7 @@ config MIPS select HAS_KALLSYMS select HAVE_CONFIGURABLE_MEMORY_LAYOUT select HAVE_CONFIGURABLE_TEXT_BASE + select HAS_DMA default y config SYS_SUPPORTS_BIG_ENDIAN diff --git a/arch/mips/boards/black-swift/include/board/board_pbl_start.h b/arch/mips/boards/black-swift/include/board/board_pbl_start.h index 7394092838..ee21a85ac9 100644 --- a/arch/mips/boards/black-swift/include/board/board_pbl_start.h +++ b/arch/mips/boards/black-swift/include/board/board_pbl_start.h @@ -26,18 +26,32 @@ mips_barebox_10h - mips_disable_interrupts + hornet_mips24k_cp0_setup pbl_blt 0xbf000000 skip_pll_ram_config t8 + hornet_1_1_war + pbl_ar9331_pll pbl_ar9331_ddr2_config + /* Initialize caches... */ + mips_cache_reset + + /* ... and enable them */ + dcache_enable + skip_pll_ram_config: pbl_ar9331_uart_enable debug_ll_ar9331_init mips_nmon + /* + * It is amazing but we have to enable MDIO on GPIO + * to use GPIO27 for LED1. + */ + pbl_ar9331_mdio_gpio_enable + copy_to_link_location pbl_start .set pop diff --git a/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h b/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h index d25f5aa337..ef0d36dc38 100644 --- a/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h +++ b/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h @@ -26,18 +26,32 @@ mips_barebox_10h - mips_disable_interrupts + hornet_mips24k_cp0_setup pbl_blt 0xbf000000 skip_pll_ram_config t8 + hornet_1_1_war + pbl_ar9331_pll pbl_ar9331_ddr1_config + /* Initialize caches... */ + mips_cache_reset + + /* ... and enable them */ + dcache_enable + skip_pll_ram_config: pbl_ar9331_uart_enable debug_ll_ar9331_init mips_nmon + /* + * It is amazing but we have to enable MDIO on GPIO + * to use GPIO26 for the "WPS" LED and GPIO27 for the "3G" LED. + */ + pbl_ar9331_mdio_gpio_enable + copy_to_link_location pbl_start .set pop diff --git a/arch/mips/boot/dtb.c b/arch/mips/boot/dtb.c index 23d8979ad5..977c837887 100644 --- a/arch/mips/boot/dtb.c +++ b/arch/mips/boot/dtb.c @@ -28,11 +28,13 @@ void of_add_memory_bank(struct device_node *node, bool dump, int r, { static char str[12]; - sprintf(str, "kseg0_ram%d", r); - barebox_add_memory_bank(str, KSEG0 | base, size); - - sprintf(str, "kseg1_ram%d", r); - barebox_add_memory_bank(str, KSEG1 | base, size); + if (IS_ENABLED(CONFIG_MMU)) { + sprintf(str, "kseg0_ram%d", r); + barebox_add_memory_bank(str, KSEG0 | base, size); + } else { + sprintf(str, "kseg1_ram%d", r); + barebox_add_memory_bank(str, KSEG1 | base, size); + } if (dump) pr_info("%s: %s: 0x%llx@0x%llx\n", node->name, str, size, base); diff --git a/arch/mips/configs/black-swift_defconfig b/arch/mips/configs/black-swift_defconfig index 74449687ab..1a72cfbd77 100644 --- a/arch/mips/configs/black-swift_defconfig +++ b/arch/mips/configs/black-swift_defconfig @@ -9,6 +9,8 @@ CONFIG_NMON_USER_START_DELAY=0x5 CONFIG_NMON_HELP=y CONFIG_PBL_IMAGE=y CONFIG_IMAGE_COMPRESSION_XZKERN=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x82000000 CONFIG_MALLOC_TLSF=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y @@ -32,6 +34,8 @@ CONFIG_CMD_EDIT=y CONFIG_CMD_MM=y CONFIG_CMD_CLK=y CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_LED=y CONFIG_CMD_SPI=y CONFIG_CMD_OF_NODE=y CONFIG_CMD_OF_PROPERTY=y @@ -42,5 +46,9 @@ CONFIG_DRIVER_SPI_ATH79=y CONFIG_MTD=y # CONFIG_MTD_OOB_DEVICE is not set CONFIG_MTD_M25P80=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y +CONFIG_KEYBOARD_GPIO=y CONFIG_DIGEST_SHA224_GENERIC=y CONFIG_DIGEST_SHA256_GENERIC=y diff --git a/arch/mips/configs/tplink-mr3020_defconfig b/arch/mips/configs/tplink-mr3020_defconfig index f2ba2da167..93fb10ddd2 100644 --- a/arch/mips/configs/tplink-mr3020_defconfig +++ b/arch/mips/configs/tplink-mr3020_defconfig @@ -3,6 +3,8 @@ CONFIG_BUILTIN_DTB_NAME="tplink-mr3020" CONFIG_MACH_MIPS_ATH79=y CONFIG_PBL_IMAGE=y CONFIG_IMAGE_COMPRESSION_XZKERN=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x81000000 CONFIG_MALLOC_TLSF=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y diff --git a/arch/mips/dts/ar9331.dtsi b/arch/mips/dts/ar9331.dtsi index 99ede9e920..efc0531c93 100644 --- a/arch/mips/dts/ar9331.dtsi +++ b/arch/mips/dts/ar9331.dtsi @@ -33,7 +33,7 @@ #clock-cells = <1>; }; - spi: spi@1f000000{ + spi: spi@1f000000 { #address-cells = <1>; #size-cells = <0>; compatible = "qca,ath79-spi"; diff --git a/arch/mips/dts/black-swift.dts b/arch/mips/dts/black-swift.dts index 270374d530..d19c381df9 100644 --- a/arch/mips/dts/black-swift.dts +++ b/arch/mips/dts/black-swift.dts @@ -1,6 +1,8 @@ /dts-v1/; #include "ar9331.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> / { model = "Black Swift"; @@ -13,12 +15,36 @@ aliases { spiflash = &spiflash; }; + + buttons { + compatible = "gpio-keys"; + + s1 { + label = "S1"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + }; + }; + + leds { + compatible = "gpio-leds"; + + s1 { + label = "LED1"; + gpios = <&gpio 27 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; }; &serial0 { status = "okay"; }; +&gpio { + status = "okay"; +}; + &spi { num-chipselects = <1>; status = "okay"; diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h new file mode 100644 index 0000000000..cceba0acc0 --- /dev/null +++ b/arch/mips/include/asm/cache.h @@ -0,0 +1,6 @@ +#ifndef _ASM_MIPS_CACHE_H +#define _ASM_MIPS_CACHE_H + +void flush_cache_all(void); + +#endif /* _ASM_MIPS_CACHE_H */ diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h new file mode 100644 index 0000000000..3bc585259f --- /dev/null +++ b/arch/mips/include/asm/cacheops.h @@ -0,0 +1,36 @@ +/* + * Cache operations for the cache instruction. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle + * (C) Copyright 1999 Silicon Graphics, Inc. + */ +#ifndef __ASM_CACHEOPS_H +#define __ASM_CACHEOPS_H + +/* + * Most cache ops are split into a 2 bit field identifying the cache, and a 3 + * bit field identifying the cache operation. + */ +#define Cache_I 0x00 +#define Cache_D 0x01 + +#define Index_Writeback_Inv 0x00 +#define Index_Store_Tag 0x08 +#define Hit_Invalidate 0x10 +#define Hit_Writeback_Inv 0x14 /* not with Cache_I though */ + +/* + * Cache Operations available on all MIPS processors with R4000-style caches + */ +#define Index_Invalidate_I (Cache_I | Index_Writeback_Inv) +#define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv) +#define Index_Store_Tag_I (Cache_I | Index_Store_Tag) +#define Index_Store_Tag_D (Cache_D | Index_Store_Tag) +#define Hit_Invalidate_D (Cache_D | Hit_Invalidate) +#define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv) + +#endif /* __ASM_CACHEOPS_H */ diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h index 639511226d..c71a087038 100644 --- a/arch/mips/include/asm/dma-mapping.h +++ b/arch/mips/include/asm/dma-mapping.h @@ -1,10 +1,12 @@ #ifndef _ASM_DMA_MAPPING_H #define _ASM_DMA_MAPPING_H +#include <common.h> #include <xfuncs.h> #include <asm/addrspace.h> #include <asm/types.h> #include <malloc.h> +#include <asm/io.h> static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle) { @@ -12,16 +14,23 @@ static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle) ret = xmemalign(PAGE_SIZE, size); + memset(ret, 0, size); + if (dma_handle) *dma_handle = CPHYSADDR(ret); + dma_flush_range((unsigned long)ret, (unsigned long)(ret + size)); + return (void *)CKSEG1ADDR(ret); } static inline void dma_free_coherent(void *vaddr, dma_addr_t dma_handle, size_t size) { - free(vaddr); + if (IS_ENABLED(CONFIG_MMU)) + free((void *)CKSEG0ADDR(vaddr)); + else + free(vaddr); } #endif /* _ASM_DMA_MAPPING_H */ diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 4832be6d09..4bee5913a5 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -14,6 +14,9 @@ #include <asm/types.h> #include <asm/byteorder.h> +void dma_flush_range(unsigned long, unsigned long); +void dma_inv_range(unsigned long, unsigned long); + #define IO_SPACE_LIMIT 0 /*****************************************************************************/ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index f9238607ab..30262e6e1e 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -409,6 +409,14 @@ #define MIPS_CONF1_PC (_ULCAST_(1) << 4) #define MIPS_CONF1_MD (_ULCAST_(1) << 5) #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) +#define MIPS_CONF1_DA_SHF 7 +#define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_DL_SHF 10 +#define MIPS_CONF1_DL (_ULCAST_(7) << 10) +#define MIPS_CONF1_DS_SHF 13 +#define MIPS_CONF1_DS (_ULCAST_(7) << 13) +#define MIPS_CONF1_IA_SHF 16 + #define MIPS_CONF1_DA (_ULCAST_(7) << 7) #define MIPS_CONF1_DL (_ULCAST_(7) << 10) #define MIPS_CONF1_DS (_ULCAST_(7) << 13) diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h index dbe3410632..37b150ac2b 100644 --- a/arch/mips/include/asm/pbl_macros.h +++ b/arch/mips/include/asm/pbl_macros.h @@ -27,6 +27,8 @@ #include <asm-generic/memory_layout.h> #include <generated/compile.h> #include <generated/utsrelease.h> +#include <asm/addrspace.h> +#include <asm/cacheops.h> .macro pbl_reg_writel val addr .set push @@ -212,4 +214,135 @@ copy_loop_exit: .set pop .endm +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + +#define INDEX_BASE CKSEG0 + + .macro f_fill64 dst, offset, val + LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) +#if LONGSIZE == 4 + LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) +#endif + .endm + + .macro cache_loop curr, end, line_sz, op +10: cache \op, 0(\curr) + PTR_ADDU \curr, \curr, \line_sz + bne \curr, \end, 10b + .endm + + .macro l1_info sz, line_sz, off + .set push + .set noat + + mfc0 $1, CP0_CONFIG, 1 + + /* detect line size */ + srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF + andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF) + move \sz, zero + beqz \line_sz, 10f + li \sz, 2 + sllv \line_sz, \sz, \line_sz + + /* detect associativity */ + srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF + andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF) + addi \sz, \sz, 1 + + /* sz *= line_sz */ + mul \sz, \sz, \line_sz + + /* detect log32(sets) */ + srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF + andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF) + addiu $1, $1, 1 + andi $1, $1, 0x7 + + /* sz <<= log32(sets) */ + sllv \sz, \sz, $1 + + /* sz *= 32 */ + li $1, 32 + mul \sz, \sz, $1 +10: + .set pop + .endm + +/* + * mips_cache_reset - low level initialisation of the primary caches + * + * This routine initialises the primary caches to ensure that they have good + * parity. It must be called by the ROM before any cached locations are used + * to prevent the possibility of data with bad parity being written to memory. + * + * To initialise the instruction cache it is essential that a source of data + * with good parity is available. This routine will initialise an area of + * memory starting at location zero to be used as a source of parity. + * + */ + .macro mips_cache_reset + + l1_info t2, t8, MIPS_CONF1_IA_SHF + l1_info t3, t9, MIPS_CONF1_DA_SHF + + /* + * The TagLo registers used depend upon the CPU implementation, but the + * architecture requires that it is safe for software to write to both + * TagLo selects 0 & 2 covering supported cases. + */ + mtc0 zero, CP0_TAGLO + mtc0 zero, CP0_TAGLO, 2 + + /* + * The caches are probably in an indeterminate state, so we force good + * parity into them by doing an invalidate for each line. + */ + + /* + * Initialize the I-cache first, + */ + blez t2, 1f + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, t2 + /* clear tag to invalidate */ + cache_loop t0, t1, t8, Index_Store_Tag_I + + /* + * then initialize D-cache. + */ +1: blez t3, 3f + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, t3 + /* clear all tags */ + cache_loop t0, t1, t9, Index_Store_Tag_D + +3: nop + + .endm + + .macro dcache_enable + mfc0 t0, CP0_CONFIG + ori t0, CONF_CM_CMASK + xori t0, CONF_CM_CMASK + ori t0, CONFIG_SYS_MIPS_CACHE_MODE + mtc0 t0, CP0_CONFIG + .endm + #endif /* __ASM_PBL_MACROS_H */ diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 02ee1893f8..d25d0969fc 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -6,6 +6,8 @@ obj-y += ashrdi3.o obj-y += cpu-probe.o obj-y += traps.o obj-y += genex.o +obj-y += shutdown.o +obj-y += dma-default.o obj-$(CONFIG_MIPS_OPTIMIZED_STRING_FUNCTIONS) += memcpy.o obj-$(CONFIG_MIPS_OPTIMIZED_STRING_FUNCTIONS) += memset.o diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c index 0a9dd0eb9a..150205840d 100644 --- a/arch/mips/lib/c-r4k.c +++ b/arch/mips/lib/c-r4k.c @@ -10,10 +10,81 @@ #include <common.h> #include <asm/io.h> #include <asm/mipsregs.h> +#include <asm/cache.h> +#include <asm/cacheops.h> #include <asm/cpu.h> #include <asm/cpu-info.h> #include <asm/bitops.h> +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop) \ +static inline void blast_##pfx##cache##_range(unsigned long start, \ + unsigned long end) \ +{ \ + unsigned long lsize = current_cpu_data.desc.linesz; \ + unsigned long addr = start & ~(lsize - 1); \ + unsigned long aend = (end - 1) & ~(lsize - 1); \ + \ + if (current_cpu_data.desc.flags & MIPS_CACHE_NOT_PRESENT) \ + return; \ + \ + while (1) { \ + cache_op(hitop, addr); \ + if (addr == aend) \ + break; \ + addr += lsize; \ + } \ +} + +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D) +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D) + +void flush_cache_all(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned long lsize; + unsigned long addr; + unsigned long aend; + unsigned int icache_size, dcache_size; + + dcache_size = c->dcache.waysize * c->dcache.ways; + lsize = c->dcache.linesz; + aend = (KSEG0 + dcache_size - 1) & ~(lsize - 1); + for (addr = KSEG0; addr <= aend; addr += lsize) + cache_op(Index_Writeback_Inv_D, addr); + + icache_size = c->icache.waysize * c->icache.ways; + lsize = c->icache.linesz; + aend = (KSEG0 + icache_size - 1) & ~(lsize - 1); + for (addr = KSEG0; addr <= aend; addr += lsize) + cache_op(Index_Invalidate_I, addr); + + /* secondatory cache skipped */ +} + +void dma_flush_range(unsigned long start, unsigned long end) +{ + blast_dcache_range(start, end); + + /* secondatory cache skipped */ +} + +void dma_inv_range(unsigned long start, unsigned long end) +{ + blast_inv_dcache_range(start, end); + + /* secondatory cache skipped */ +} + void r4k_cache_init(void); static void probe_pcache(void) @@ -91,7 +162,6 @@ static void probe_pcache(void) } } -#define CONFIG_M (1 << 31) #define CONFIG2_SS_OFFSET 8 #define CONFIG2_SL_OFFSET 4 #define CONFIG2_SA_OFFSET 0 @@ -101,10 +171,10 @@ static void probe_scache(void) unsigned int config2, config1, config = read_c0_config(); unsigned int ss, sl, sa; - if ((config & CONFIG_M) == 0) + if ((config & MIPS_CONF_M) == 0) goto noscache; config1 = read_c0_config1(); - if ((config1 & CONFIG_M) == 0) + if ((config1 & MIPS_CONF_M) == 0) goto noscache; config2 = read_c0_config2(); ss = 0xf & (config2 >> CONFIG2_SS_OFFSET); diff --git a/arch/mips/lib/dma-default.c b/arch/mips/lib/dma-default.c new file mode 100644 index 0000000000..9b2fe7d410 --- /dev/null +++ b/arch/mips/lib/dma-default.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2015, 2016 Peter Mamonov <pmamonov@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <dma.h> +#include <asm/io.h> + +#if defined(CONFIG_CPU_MIPS32) || \ + defined(CONFIG_CPU_MIPS64) +static inline void __dma_sync_mips(unsigned long addr, size_t size, + enum dma_data_direction direction) +{ + switch (direction) { + case DMA_TO_DEVICE: + dma_flush_range(addr, addr + size); + break; + + case DMA_FROM_DEVICE: + dma_inv_range(addr, addr + size); + break; + + case DMA_BIDIRECTIONAL: + dma_flush_range(addr, addr + size); + break; + + default: + BUG(); + } +} +#else +static inline void __dma_sync_mips(void *addr, size_t size, + enum dma_data_direction direction) +{ +} +#endif + +void dma_sync_single_for_cpu(unsigned long address, size_t size, + enum dma_data_direction dir) +{ + __dma_sync_mips(address, size, dir); +} + +void dma_sync_single_for_device(unsigned long address, size_t size, + enum dma_data_direction dir) +{ + __dma_sync_mips(address, size, dir); +} diff --git a/arch/mips/lib/shutdown.c b/arch/mips/lib/shutdown.c new file mode 100644 index 0000000000..973cd23c71 --- /dev/null +++ b/arch/mips/lib/shutdown.c @@ -0,0 +1,12 @@ +/** + * This function is called by shutdown_barebox to get a clean + * memory/cache state. + */ +#include <init.h> +#include <asm/cache.h> + +static void arch_shutdown(void) +{ + flush_cache_all(); +} +archshutdown_exitcall(arch_shutdown); diff --git a/arch/mips/mach-ar231x/ar231x_reset.c b/arch/mips/mach-ar231x/ar231x_reset.c index 318f772108..7c322d87b6 100644 --- a/arch/mips/mach-ar231x/ar231x_reset.c +++ b/arch/mips/mach-ar231x/ar231x_reset.c @@ -54,11 +54,13 @@ EXPORT_SYMBOL(ar231x_reset_bit); static int ar231x_reset_probe(struct device_d *dev) { - reset_base = dev_request_mem_region(dev, 0); - if (IS_ERR(reset_base)) { + struct resource *iores; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(reset_base); + return PTR_ERR(iores); } + reset_base = IOMEM(iores->start); return 0; } diff --git a/arch/mips/mach-ath79/include/mach/pbl_macros.h b/arch/mips/mach-ath79/include/mach/pbl_macros.h index c00dd28f5a..8f4d09aec4 100644 --- a/arch/mips/mach-ath79/include/mach/pbl_macros.h +++ b/arch/mips/mach-ath79/include/mach/pbl_macros.h @@ -179,4 +179,99 @@ | AR933X_GPIO_FUNC_RSRV15, GPIO_FUNC .endm +#define RESET_REG_BOOTSTRAP ((KSEG1 | AR71XX_RESET_BASE) \ + | AR933X_RESET_REG_BOOTSTRAP) + +.macro pbl_ar9331_mdio_gpio_enable + /* Bit 18 enables MDC and MDIO function on GPIO26 and GPIO28 */ + pbl_reg_set (1 << 18), RESET_REG_BOOTSTRAP +.endm + +.macro hornet_mips24k_cp0_setup + .set push + .set noreorder + + /* + * Clearing CP0 registers - This is generally required for the MIPS-24k + * core used by Atheros. + */ + mtc0 zero, CP0_INDEX + mtc0 zero, CP0_ENTRYLO0 + mtc0 zero, CP0_ENTRYLO1 + mtc0 zero, CP0_CONTEXT + mtc0 zero, CP0_PAGEMASK + mtc0 zero, CP0_WIRED + mtc0 zero, CP0_INFO + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_ENTRYHI + mtc0 zero, CP0_COMPARE + + li t0, ST0_CU0 | ST0_ERL + mtc0 t0, CP0_STATUS + + mtc0 zero, CP0_CAUSE + mtc0 zero, CP0_EPC + + li t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG + + mtc0 zero, CP0_LLADDR + mtc0 zero, CP0_WATCHLO + mtc0 zero, CP0_WATCHHI + mtc0 zero, CP0_XCONTEXT + mtc0 zero, CP0_FRAMEMASK + mtc0 zero, CP0_DIAGNOSTIC + mtc0 zero, CP0_DEBUG + mtc0 zero, CP0_DEPC + mtc0 zero, CP0_PERFORMANCE + mtc0 zero, CP0_ECC + mtc0 zero, CP0_CACHEERR + mtc0 zero, CP0_TAGLO + + .set pop +.endm + +.macro hornet_1_1_war + .set push + .set noreorder + +/* + * WAR: Hornet 1.1 currently need a reset once we boot to let the resetb has + * enough time to stable, so that trigger reset at 1st boot, system team + * is investigaing the issue, will remove in short + */ + + li t7, 0xbd000000 + lw t8, 0(t7) + li t9, 0x12345678 + + /* if value of 0xbd000000 != 0x12345678, go to do_reset */ + bne t8, t9, do_reset + nop + + li t9, 0xffffffff + sw t9, 0(t7) + b normal_path + nop + +do_reset: + /* put 0x12345678 into 0xbd000000 */ + sw t9, 0(t7) + + /* reset register 0x1806001c */ + li t7, 0xb806001c + lw t8, 0(t7) + /* bit24, fullchip reset */ + li t9, 0x1000000 + or t8, t8, t9 + sw t8, 0(t7) + +do_reset_loop: + b do_reset_loop + nop + +normal_path: + .set pop +.endm + #endif /* __ASM_MACH_ATH79_PBL_MACROS_H */ diff --git a/commands/Kconfig b/commands/Kconfig index b4fdc866a7..9519a44cfc 100644 --- a/commands/Kconfig +++ b/commands/Kconfig @@ -2114,6 +2114,22 @@ config CMD_OF_DISPLAY_TIMINGS -s path select display-timings and register oftree fixup -f dtb work on dtb. Has no effect on -s option +config CMD_OF_FIXUP_STATUS + tristate + select OFTREE + prompt "of_fixup_status" + help + Register a fixup to enable or disable node + + Usage: of_fixup_node [-d] path + + Options: + -d disable node + path Node path or alias + + Register a fixup to enable or disable a device tree node. + Nodes are enabled on default. Disabled with -d. + config CMD_OFTREE tristate select OFTREE diff --git a/commands/Makefile b/commands/Makefile index d98534119d..8975d4bd40 100644 --- a/commands/Makefile +++ b/commands/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_CMD_OF_PROPERTY) += of_property.o obj-$(CONFIG_CMD_OF_NODE) += of_node.o obj-$(CONFIG_CMD_OF_DUMP) += of_dump.o obj-$(CONFIG_CMD_OF_DISPLAY_TIMINGS) += of_display_timings.o +obj-$(CONFIG_CMD_OF_FIXUP_STATUS) += of_fixup_status.o obj-$(CONFIG_CMD_MAGICVAR) += magicvar.o obj-$(CONFIG_CMD_IOMEM) += iomemport.o obj-$(CONFIG_CMD_LINUX_EXEC) += linux_exec.o diff --git a/commands/magicvar.c b/commands/magicvar.c index 6737eb533d..8740784ed2 100644 --- a/commands/magicvar.c +++ b/commands/magicvar.c @@ -24,7 +24,7 @@ static void magicvar_print_one(struct magicvar_dyn *md, int verbose) } } -struct magicvar_dyn *magicvar_find(const char *name) +static struct magicvar_dyn *magicvar_find(const char *name) { struct magicvar_dyn *md; diff --git a/commands/nand.c b/commands/nand.c index ad1c8c9b3d..c330ad1dc4 100644 --- a/commands/nand.c +++ b/commands/nand.c @@ -90,8 +90,13 @@ static int do_nand(int argc, char *argv[]) } ret = ioctl(fd, MEMSETBADBLOCK, &badblock); - if (ret) - perror("ioctl"); + if (ret) { + if (ret == -EINVAL) + printf("Maybe offset %lld is out of range.\n", + badblock); + else + perror("ioctl"); + } close(fd); return ret; diff --git a/commands/of_fixup_status.c b/commands/of_fixup_status.c new file mode 100644 index 0000000000..9a4a619195 --- /dev/null +++ b/commands/of_fixup_status.c @@ -0,0 +1,74 @@ +/* + * of_fixup_status.c - Register a fixup to enable or disable nodes in the + * device tree + * + * Copyright (c) 2014-2016 PHYTEC Messtechnik GmbH + * Author: + * Teresa Remmet + * Wadim Egorov + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <of.h> +#include <command.h> +#include <malloc.h> +#include <complete.h> +#include <asm/byteorder.h> +#include <linux/err.h> +#include <getopt.h> +#include <string.h> + +static int do_of_fixup_status(int argc, char *argv[]) +{ + int opt; + bool status = 1; + char *node = NULL; + + while ((opt = getopt(argc, argv, "d")) > 0) { + switch (opt) { + case 'd': + status = 0; + break; + default: + return COMMAND_ERROR_USAGE; + } + } + + if (optind == argc) + return COMMAND_ERROR_USAGE; + + node = xstrdup(argv[optind]); + + of_register_set_status_fixup(node, status); + + return 0; +} + +BAREBOX_CMD_HELP_START(of_fixup_status) +BAREBOX_CMD_HELP_TEXT("Options:") +BAREBOX_CMD_HELP_OPT("-d", "disable node") +BAREBOX_CMD_HELP_OPT("path", "Node path\n") +BAREBOX_CMD_HELP_TEXT("Register a fixup to enable or disable a device tree node.") +BAREBOX_CMD_HELP_TEXT("Nodes are enabled on default. Disabled with -d.") +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(of_fixup_status) + .cmd = do_of_fixup_status, + BAREBOX_CMD_DESC("register a fixup to enable or disable node") + BAREBOX_CMD_OPTS("[-d] path") + BAREBOX_CMD_GROUP(CMD_GRP_MISC) + BAREBOX_CMD_COMPLETE(devicetree_file_complete) + BAREBOX_CMD_HELP(cmd_of_fixup_status_help) +BAREBOX_CMD_END diff --git a/common/bbu.c b/common/bbu.c index 4d71fa4a87..68812a733d 100644 --- a/common/bbu.c +++ b/common/bbu.c @@ -97,6 +97,34 @@ static struct bbu_handler *bbu_find_handler(const char *name) return NULL; } +static struct bbu_handler *bbu_find_handler_by_device(const char *devicepath) +{ + struct bbu_handler *handler; + + if (!devicepath) + return NULL; + + list_for_each_entry(handler, &bbu_image_handlers, list) + if (!strcmp(handler->devicefile, devicepath)) + return handler; + + return NULL; +} + +bool barebox_update_handler_exists(struct bbu_data *data) +{ + struct bbu_handler *handler; + + handler = bbu_find_handler_by_device(data->devicefile); + if (handler) + return true; + + if (!data->handler_name) + return false; + + return !bbu_find_handler(data->handler_name); +} + /* * do a barebox update with data from *data */ @@ -105,7 +133,11 @@ int barebox_update(struct bbu_data *data) struct bbu_handler *handler; int ret; - handler = bbu_find_handler(data->handler_name); + handler = bbu_find_handler_by_device(data->devicefile); + + if (!handler) + handler = bbu_find_handler(data->handler_name); + if (!handler) return -ENODEV; @@ -187,7 +219,7 @@ static int bbu_std_file_handler(struct bbu_handler *handler, oflags |= O_CREAT; } else { if (!S_ISREG(s.st_mode) && s.st_size < data->len) { - printf("Image (%lld) is too big for device (%d)\n", + printf("Image (%lld) is too big for device (%zd)\n", s.st_size, data->len); } } diff --git a/common/filetype.c b/common/filetype.c index 8cfae88aeb..74baf51446 100644 --- a/common/filetype.c +++ b/common/filetype.c @@ -369,3 +369,16 @@ err_out: cdev_close(cdev); return type; } + +bool filetype_is_barebox_image(enum filetype ft) +{ + switch (ft) { + case filetype_arm_barebox: + case filetype_mips_barebox: + case filetype_ch_image: + case filetype_ch_image_be: + return true; + default: + return false; + } +} diff --git a/common/imx-bbu-nand-fcb.c b/common/imx-bbu-nand-fcb.c index 22031f5b7f..3eb9e9b169 100644 --- a/common/imx-bbu-nand-fcb.c +++ b/common/imx-bbu-nand-fcb.c @@ -337,14 +337,14 @@ static int imx_bbu_write_firmware(struct mtd_info *mtd, unsigned block, return block; } -static int dbbt_data_create(struct mtd_info *mtd, void *buf, int block_last) +static int dbbt_data_create(struct mtd_info *mtd, void *buf, int num_blocks) { int n; int n_bad_blocks = 0; uint32_t *bb = buf + 0x8; uint32_t *n_bad_blocksp = buf + 0x4; - for (n = 0; n <= block_last; n++) { + for (n = 0; n < num_blocks; n++) { loff_t offset = n * mtd->erasesize; if (mtd_block_isbad(mtd, offset)) { n_bad_blocks++; @@ -461,10 +461,6 @@ static int imx_bbu_nand_update(struct bbu_handler *handler, struct bbu_data *dat */ memset(fcb_raw_page + mtd->writesize, 0xFF, 2); - ret = raw_write_page(mtd, fcb_raw_page, mtd->erasesize); - if (ret) - goto out; - dbbt->Checksum = 0; dbbt->FingerPrint = 0x54424244; dbbt->Version = 0x01000000; diff --git a/common/oftree.c b/common/oftree.c index d408f14e66..e98b908738 100644 --- a/common/oftree.c +++ b/common/oftree.c @@ -139,6 +139,42 @@ static int of_register_bootargs_fixup(void) } late_initcall(of_register_bootargs_fixup); +struct of_fixup_status_data { + const char *path; + bool status; +}; + +static int of_fixup_status(struct device_node *root, void *context) +{ + const struct of_fixup_status_data *data = context; + struct device_node *node; + + node = of_find_node_by_path_or_alias(root, data->path); + if (!node) + return -ENODEV; + + if (data->status) + return of_device_enable(node); + else + return of_device_disable(node); +} + +/** + * of_register_set_status_fixup - register fix up to set status of nodes + * Register a fixup to enable or disable a node in the devicet tree by + * passing the path or alias. + */ +int of_register_set_status_fixup(const char *path, bool status) +{ + struct of_fixup_status_data *data; + + data = xzalloc(sizeof(*data)); + data->path = path; + data->status = status; + + return of_register_fixup(of_fixup_status, (void *)data); +} + struct of_fixup { int (*fixup)(struct device_node *, void *); void *context; diff --git a/common/ratp.c b/common/ratp.c index 2fef3cc0fe..e879e2b3c1 100644 --- a/common/ratp.c +++ b/common/ratp.c @@ -398,20 +398,6 @@ out: ratp_console_unregister(ctx); } -static int do_ratp_close(int argc, char *argv[]) -{ - if (ratp_command_ctx && ratp_command_ctx->cdev) - ratp_console_unregister(ratp_command_ctx); - else - printf("ratp is not active\n"); - - return 0; -} - -BAREBOX_CMD_START(ratp_close) - .cmd = do_ratp_close, -}; - int barebox_ratp_fs_call(struct ratp_bb_pkt *tx, struct ratp_bb_pkt **rx) { struct ratp_ctx *ctx = ratp_command_ctx; @@ -508,4 +494,4 @@ static void barebox_ratp_close(void) if (ratp_command_ctx && ratp_command_ctx->cdev) ratp_console_unregister(ratp_command_ctx); } -predevshutdown_exitcall(barebox_ratp_close);
\ No newline at end of file +predevshutdown_exitcall(barebox_ratp_close); diff --git a/common/state.c b/common/state.c index 3e95efd911..b55b1503bd 100644 --- a/common/state.c +++ b/common/state.c @@ -999,6 +999,7 @@ static int of_state_fixup(struct device_node *root, void *ctx) return 0; out: + dev_err(&state->dev, "error fixing up device tree with boot state\n"); of_delete_node(new_node); return ret; } diff --git a/drivers/Kconfig b/drivers/Kconfig index 5984ccca2c..3236696564 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -31,5 +31,6 @@ source "drivers/pci/Kconfig" source "drivers/rtc/Kconfig" source "drivers/firmware/Kconfig" source "drivers/phy/Kconfig" +source "drivers/crypto/Kconfig" endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 8a8c8c44bd..a4467a0e79 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -31,3 +31,4 @@ obj-y += rtc/ obj-$(CONFIG_FIRMWARE) += firmware/ obj-$(CONFIG_GENERIC_PHY) += phy/ obj-$(CONFIG_HAB) += hab/ +obj-$(CONFIG_CRYPTO_HW) += crypto/ diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 4e42180d9e..c31b337ba2 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -659,15 +659,17 @@ int ahci_add_host(struct ahci_device *ahci) static int ahci_probe(struct device_d *dev) { + struct resource *iores; struct ahci_device *ahci; void __iomem *regs; int ret; ahci = xzalloc(sizeof(*ahci)); - regs = dev_request_mem_region(dev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + regs = IOMEM(iores->start); ahci->dev = dev; ahci->mmio_base = regs; diff --git a/drivers/ata/intf_platform_ide.c b/drivers/ata/intf_platform_ide.c index d0f7984a2c..6e74bfb089 100644 --- a/drivers/ata/intf_platform_ide.c +++ b/drivers/ata/intf_platform_ide.c @@ -80,6 +80,7 @@ static void platform_ide_setup_port(void *reg_base, void *alt_base, static int platform_ide_probe(struct device_d *dev) { + struct resource *iores; int rc; struct ide_port_info *pdata = dev->platform_data; struct ide_port *ide; @@ -102,11 +103,17 @@ static int platform_ide_probe(struct device_d *dev) return -EINVAL; } - reg_base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + reg_base = IOMEM(iores->start); if (!IS_ERR(reg_base)) { mmio = 1; - alt_base = dev_request_mem_region(dev, 1); + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + alt_base = IOMEM(iores->start); if (IS_ERR(alt_base)) alt_base = NULL; } else { diff --git a/drivers/ata/pata-imx.c b/drivers/ata/pata-imx.c index d8deba1461..842957331e 100644 --- a/drivers/ata/pata-imx.c +++ b/drivers/ata/pata-imx.c @@ -153,6 +153,7 @@ static int pata_imx_detect(struct device_d *dev) static int imx_pata_probe(struct device_d *dev) { + struct resource *iores; struct ide_port *ide; struct clk *clk; void __iomem *base; @@ -160,9 +161,10 @@ static int imx_pata_probe(struct device_d *dev) const char *devname = NULL; ide = xzalloc(sizeof(*ide)); - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); clk = clk_get(dev, NULL); if (IS_ERR(clk)) { diff --git a/drivers/ata/sata-imx.c b/drivers/ata/sata-imx.c index 612762e229..6a601956db 100644 --- a/drivers/ata/sata-imx.c +++ b/drivers/ata/sata-imx.c @@ -84,6 +84,7 @@ static int imx_sata_init_1ms(struct imx_ahci *imx_ahci) static int imx_sata_probe(struct device_d *dev) { + struct resource *iores; struct imx_ahci *imx_ahci; struct imx_sata_data *data; int ret; @@ -100,9 +101,10 @@ static int imx_sata_probe(struct device_d *dev) goto err_free; } - imx_ahci->ahci.mmio_base = dev_request_mem_region(dev, 0); - if (IS_ERR(imx_ahci->ahci.mmio_base)) - return PTR_ERR(imx_ahci->ahci.mmio_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + imx_ahci->ahci.mmio_base = IOMEM(iores->start); data->init(imx_ahci); diff --git a/drivers/base/driver.c b/drivers/base/driver.c index c529296fc6..5867fe45d0 100644 --- a/drivers/base/driver.c +++ b/drivers/base/driver.c @@ -404,7 +404,7 @@ void __iomem *dev_request_mem_region_err_null(struct device_d *dev, int num) } EXPORT_SYMBOL(dev_request_mem_region_err_null); -void __iomem *dev_request_mem_region(struct device_d *dev, int num) +struct resource *dev_request_mem_resource(struct device_d *dev, int num) { struct resource *res; @@ -412,7 +412,14 @@ void __iomem *dev_request_mem_region(struct device_d *dev, int num) if (IS_ERR(res)) return ERR_CAST(res); - res = request_iomem_region(dev_name(dev), res->start, res->end); + return request_iomem_region(dev_name(dev), res->start, res->end); +} + +void __iomem *dev_request_mem_region(struct device_d *dev, int num) +{ + struct resource *res; + + res = dev_request_mem_resource(dev, num); if (IS_ERR(res)) return ERR_CAST(res); diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c index bc090cf191..c62e948f5b 100644 --- a/drivers/bus/imx-weim.c +++ b/drivers/bus/imx-weim.c @@ -130,6 +130,7 @@ static int weim_parse_dt(struct imx_weim *weim) static int weim_probe(struct device_d *dev) { + struct resource *iores; struct imx_weim_devtype *devtype; struct imx_weim *weim; int ret; @@ -144,11 +145,12 @@ static int weim_probe(struct device_d *dev) weim->devtype = devtype; /* get the resource */ - weim->base = dev_request_mem_region(dev, 0); - if (IS_ERR(weim->base)) { - ret = PTR_ERR(weim->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto weim_err; } + weim->base = IOMEM(iores->start); /* parse the device node */ ret = weim_parse_dt(weim); diff --git a/drivers/clk/clk-ar933x.c b/drivers/clk/clk-ar933x.c index 79b257133c..373f8cc085 100644 --- a/drivers/clk/clk-ar933x.c +++ b/drivers/clk/clk-ar933x.c @@ -137,11 +137,13 @@ static void ar933x_pll_init(void __iomem *base) static int ar933x_clk_probe(struct device_d *dev) { + struct resource *iores; void __iomem *base; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); ar933x_ref_clk_init(base); ar933x_pll_init(base); diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c index c4774979bd..a06b29f4e7 100644 --- a/drivers/clk/mvebu/common.c +++ b/drivers/clk/mvebu/common.c @@ -42,6 +42,7 @@ static struct of_device_id mvebu_coreclk_ids[] = { int mvebu_coreclk_probe(struct device_d *dev) { + struct resource *iores; struct device_node *np = dev->device_node; const struct of_device_id *match; const struct coreclk_soc_desc *desc; @@ -57,9 +58,10 @@ int mvebu_coreclk_probe(struct device_d *dev) desc = (const struct coreclk_soc_desc *)match->data; /* Get SAR base address */ - base = dev_request_mem_region(dev, 0); - if (!base) - return -EINVAL; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ clk_data.clk_num = 2 + desc->num_ratios; @@ -151,6 +153,7 @@ static struct of_device_id mvebu_clk_gating_ids[] = { int mvebu_clk_gating_probe(struct device_d *dev) { + struct resource *iores; struct device_node *np = dev->device_node; const struct of_device_id *match; const struct clk_gating_soc_desc *desc; @@ -166,9 +169,10 @@ int mvebu_clk_gating_probe(struct device_d *dev) return -EINVAL; desc = (const struct clk_gating_soc_desc *)match->data; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); clk = of_clk_get(np, 0); if (IS_ERR(clk)) diff --git a/drivers/clk/mvebu/corediv.c b/drivers/clk/mvebu/corediv.c index 55f6e6ad62..87b1f8bd7c 100644 --- a/drivers/clk/mvebu/corediv.c +++ b/drivers/clk/mvebu/corediv.c @@ -199,6 +199,7 @@ static struct of_device_id mvebu_corediv_clk_ids[] = { static int mvebu_corediv_clk_probe(struct device_d *dev) { + struct resource *iores; struct device_node *np = dev->device_node; const struct of_device_id *match; const struct clk_corediv_soc_desc *soc_desc; @@ -212,9 +213,10 @@ static int mvebu_corediv_clk_probe(struct device_d *dev) return -EINVAL; soc_desc = (const struct clk_corediv_soc_desc *)match->data; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); parent = of_clk_get(np, 0); if (IS_ERR(parent)) diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c index 8bf27c1c07..e28dae12f1 100644 --- a/drivers/clk/mxs/clk-imx23.c +++ b/drivers/clk/mxs/clk-imx23.c @@ -126,11 +126,13 @@ int __init mx23_clocks_init(void __iomem *regs) static int imx23_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *regs; - regs = dev_request_mem_region(dev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + regs = IOMEM(iores->start); mx23_clocks_init(regs); diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index a408044264..ffe03c8668 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c @@ -167,11 +167,13 @@ int __init mx28_clocks_init(void __iomem *regs) static int imx28_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *regs; - regs = dev_request_mem_region(dev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + regs = IOMEM(iores->start); mx28_clocks_init(regs); diff --git a/drivers/clk/socfpga.c b/drivers/clk/socfpga.c index 5952efb336..37ed038be8 100644 --- a/drivers/clk/socfpga.c +++ b/drivers/clk/socfpga.c @@ -374,12 +374,14 @@ static void socfpga_register_clocks(struct device_d *dev, struct device_node *no static int socfpga_ccm_probe(struct device_d *dev) { + struct resource *iores; void __iomem *regs; struct device_node *clknode; - regs = dev_request_mem_region(dev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + regs = IOMEM(iores->start); clk_mgr_base_addr = regs; diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 7a2f7c081f..cec7b5f803 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -335,9 +335,11 @@ static struct tegra_clk_init_table init_table[] = { static int tegra124_car_probe(struct device_d *dev) { - car_base = dev_request_mem_region(dev, 0); - if (IS_ERR(car_base)) - return PTR_ERR(car_base); + struct resource *iores; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + car_base = IOMEM(iores->start); tegra124_osc_clk_init(); tegra124_pll_init(); diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 2ff42d8bdb..2f843bb9ac 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -338,9 +338,11 @@ static struct tegra_clk_init_table init_table[] = { static int tegra20_car_probe(struct device_d *dev) { - car_base = dev_request_mem_region(dev, 0); - if (IS_ERR(car_base)) - return PTR_ERR(car_base); + struct resource *iores; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + car_base = IOMEM(iores->start); tegra20_osc_clk_init(); tegra20_pll_init(); diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 46fd6dddea..77f31d213e 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -366,9 +366,11 @@ static struct tegra_clk_init_table init_table[] = { static int tegra30_car_probe(struct device_d *dev) { - car_base = dev_request_mem_region(dev, 0); - if (IS_ERR(car_base)) - return PTR_ERR(car_base); + struct resource *iores; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + car_base = IOMEM(iores->start); tegra30_osc_clk_init(); tegra30_pll_init(); diff --git a/drivers/clocksource/arm_smp_twd.c b/drivers/clocksource/arm_smp_twd.c index c0296cdfd8..226150aa42 100644 --- a/drivers/clocksource/arm_smp_twd.c +++ b/drivers/clocksource/arm_smp_twd.c @@ -42,6 +42,7 @@ static struct clocksource smp_twd_clksrc = { static int smp_twd_probe(struct device_d *dev) { + struct resource *iores; u32 tick_rate; u32 val; int ret; @@ -61,9 +62,10 @@ static int smp_twd_probe(struct device_d *dev) return ret; } - twd_base = dev_request_mem_region(dev, 0); - if (IS_ERR(twd_base)) - return PTR_ERR(twd_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + twd_base = IOMEM(iores->start); tick_rate = clk_get_rate(twd_clk); if (tick_rate > SMP_TWD_MAX_FREQ) { diff --git a/drivers/clocksource/bcm2835.c b/drivers/clocksource/bcm2835.c index 0cb8e57993..b5831d5f10 100644 --- a/drivers/clocksource/bcm2835.c +++ b/drivers/clocksource/bcm2835.c @@ -42,6 +42,7 @@ static struct clocksource bcm2835_stc = { static int bcm2835_cs_probe(struct device_d *dev) { + struct resource *iores; static struct clk *stc_clk; u32 rate; int ret; @@ -61,9 +62,10 @@ static int bcm2835_cs_probe(struct device_d *dev) } rate = clk_get_rate(stc_clk); - stc_base = dev_request_mem_region(dev, 0); - if (IS_ERR(stc_base)) - return PTR_ERR(stc_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + stc_base = IOMEM(iores->start); clocks_calc_mult_shift(&bcm2835_stc.mult, &bcm2835_stc.shift, rate, NSEC_PER_SEC, 60); diff --git a/drivers/clocksource/clps711x.c b/drivers/clocksource/clps711x.c index a49853f2b5..f6399e9300 100644 --- a/drivers/clocksource/clps711x.c +++ b/drivers/clocksource/clps711x.c @@ -29,6 +29,7 @@ static struct clocksource clps711x_cs = { static int clps711x_cs_probe(struct device_d *dev) { + struct resource *iores; u32 rate; struct clk *timer_clk; @@ -37,11 +38,12 @@ static int clps711x_cs_probe(struct device_d *dev) return PTR_ERR(timer_clk); rate = clk_get_rate(timer_clk); - clps711x_timer_base = dev_request_mem_region(dev, 0); - if (IS_ERR(clps711x_timer_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { clk_put(timer_clk); - return PTR_ERR(clps711x_timer_base); + return PTR_ERR(iores); } + clps711x_timer_base = IOMEM(iores->start); clocks_calc_mult_shift(&clps711x_cs.mult, &clps711x_cs.shift, rate, NSEC_PER_SEC, 10); diff --git a/drivers/clocksource/digic.c b/drivers/clocksource/digic.c index 277bb02b63..1ecd839160 100644 --- a/drivers/clocksource/digic.c +++ b/drivers/clocksource/digic.c @@ -40,15 +40,17 @@ static struct clocksource digic_cs = { static int digic_timer_probe(struct device_d *dev) { + struct resource *iores; /* use only one timer */ if (timer_base) return -EBUSY; - timer_base = dev_request_mem_region(dev, 0); - if (IS_ERR(timer_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(timer_base); + return PTR_ERR(iores); } + timer_base = IOMEM(iores->start); clocks_calc_mult_shift(&digic_cs.mult, &digic_cs.shift, DIGIC_TIMER_CLOCK, NSEC_PER_SEC, 1); diff --git a/drivers/clocksource/mvebu.c b/drivers/clocksource/mvebu.c index 88db0b06c3..cf80571263 100644 --- a/drivers/clocksource/mvebu.c +++ b/drivers/clocksource/mvebu.c @@ -56,12 +56,14 @@ static struct clocksource cs = { static int mvebu_timer_probe(struct device_d *dev) { + struct resource *iores; struct clk *clk; u32 rate, div, val; - timer_base = dev_request_mem_region(dev, 0); - if (IS_ERR(timer_base)) - return PTR_ERR(timer_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + timer_base = IOMEM(iores->start); val = __raw_readl(timer_base + TIMER_CTRL_OFF); val &= ~(TIMER0_25MHZ | TIMER0_DIV_MASK); diff --git a/drivers/clocksource/nomadik.c b/drivers/clocksource/nomadik.c index 48f4715c8f..9b20cbc946 100644 --- a/drivers/clocksource/nomadik.c +++ b/drivers/clocksource/nomadik.c @@ -94,6 +94,7 @@ static void nmdk_timer_reset(void) static int nmdk_mtu_probe(struct device_d *dev) { + struct resource *iores; static struct clk *mtu_clk; u32 rate; int ret; @@ -123,9 +124,10 @@ static int nmdk_mtu_probe(struct device_d *dev) nmdk_cycle = (rate + 1000 / 2) / 1000; /* Save global pointer to mtu, used by functions above */ - mtu_base = dev_request_mem_region(dev, 0); - if (IS_ERR(mtu_base)) - return PTR_ERR(mtu_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mtu_base = IOMEM(iores->start); /* Init the timer and register clocksource */ nmdk_timer_reset(); diff --git a/drivers/clocksource/orion.c b/drivers/clocksource/orion.c index 2e40b49ee7..97008dabab 100644 --- a/drivers/clocksource/orion.c +++ b/drivers/clocksource/orion.c @@ -45,12 +45,14 @@ static struct clocksource clksrc = { static int orion_timer_probe(struct device_d *dev) { + struct resource *iores; struct clk *tclk; uint32_t val; - timer_base = dev_request_mem_region(dev, 0); - if (IS_ERR(timer_base)) - return PTR_ERR(timer_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + timer_base = IOMEM(iores->start); tclk = clk_get(dev, NULL); diff --git a/drivers/clocksource/uemd.c b/drivers/clocksource/uemd.c index d4291dd736..b80908f3b0 100644 --- a/drivers/clocksource/uemd.c +++ b/drivers/clocksource/uemd.c @@ -66,6 +66,7 @@ static struct clocksource uemd_cs = { static int uemd_timer_probe(struct device_d *dev) { + struct resource *iores; int mode; struct clk *timer_clk; @@ -73,11 +74,12 @@ static int uemd_timer_probe(struct device_d *dev) if (timer_base) return -EBUSY; - timer_base = dev_request_mem_region(dev, 0); - if (IS_ERR(timer_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(timer_base); + return PTR_ERR(iores); } + timer_base = IOMEM(iores->start); timer_clk = clk_get(dev, NULL); if (IS_ERR(timer_clk)) { diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig new file mode 100644 index 0000000000..9f02c17c26 --- /dev/null +++ b/drivers/crypto/Kconfig @@ -0,0 +1,10 @@ + +menuconfig CRYPTO_HW + bool "Hardware crypto devices" + help + +if CRYPTO_HW + +source drivers/crypto/caam/Kconfig + +endif diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile new file mode 100644 index 0000000000..67f968f76c --- /dev/null +++ b/drivers/crypto/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam/ diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig new file mode 100644 index 0000000000..cf05d1c077 --- /dev/null +++ b/drivers/crypto/caam/Kconfig @@ -0,0 +1,34 @@ +config CRYPTO_DEV_FSL_CAAM + bool "Freescale CAAM-Multicore driver backend" + depends on ARCH_IMX6 + help + Enables the driver module for Freescale's Cryptographic Accelerator + and Assurance Module (CAAM), also known as the SEC version 4 (SEC4). + This module creates job ring devices, and configures h/w + to operate as a DPAA component automatically, depending + on h/w feature availability. + +config CRYPTO_DEV_FSL_CAAM_RINGSIZE + int "Job Ring size" + depends on CRYPTO_DEV_FSL_CAAM + range 2 9 + default "9" + help + Select size of Job Rings as a power of 2, within the + range 2-9 (ring size 4-512). + Examples: + 2 => 4 + 3 => 8 + 4 => 16 + 5 => 32 + 6 => 64 + 7 => 128 + 8 => 256 + 9 => 512 + +config CRYPTO_DEV_FSL_CAAM_RNG + bool "Register caam RNG device" + depends on CRYPTO_DEV_FSL_CAAM + default y + help + Selecting this will register the SEC4 hardware rng. diff --git a/drivers/crypto/caam/Makefile b/drivers/crypto/caam/Makefile new file mode 100644 index 0000000000..74d32da00e --- /dev/null +++ b/drivers/crypto/caam/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the CAAM backend and dependent components +# +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += ctrl.o error.o jr.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG) += caamrng.o diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c new file mode 100644 index 0000000000..0fef171a2b --- /dev/null +++ b/drivers/crypto/caam/caamrng.c @@ -0,0 +1,291 @@ +/* + * caam - Freescale FSL CAAM support for hw_random + * + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. + * + * Based on caamalg.c crypto API driver. + * + * relationship between job descriptors to shared descriptors: + * + * --------------- -------------- + * | JobDesc #0 |-------------------->| ShareDesc | + * | *(buffer 0) | |------------->| (generate) | + * --------------- | | (move) | + * | | (store) | + * --------------- | -------------- + * | JobDesc #1 |------| + * | *(buffer 1) | + * --------------- + * + * A job desc looks like this: + * + * --------------------- + * | Header | + * | ShareDesc Pointer | + * | SEQ_OUT_PTR | + * | (output buffer) | + * --------------------- + * + * The SharedDesc never changes, and each job descriptor points to one of two + * buffers for each device, from which the data will be copied into the + * requested destination + */ +#include <common.h> +#include <dma.h> +#include <driver.h> +#include <init.h> +#include <linux/spinlock.h> + +#include "regs.h" +#include "intern.h" +#include "desc_constr.h" +#include "jr.h" +#include "error.h" + +/* + * Maximum buffer size: maximum number of random, cache-aligned bytes that + * will be generated and moved to seq out ptr (extlen not allowed) + */ +#define RN_BUF_SIZE 32767 + +/* length of descriptors */ +#define DESC_JOB_O_LEN (CAAM_CMD_SZ * 2 + CAAM_PTR_SZ * 2) +#define DESC_RNG_LEN (10 * CAAM_CMD_SZ) + +/* Buffer, its dma address and lock */ +struct buf_data { + u8 buf[RN_BUF_SIZE]; + dma_addr_t addr; + u32 hw_desc[DESC_JOB_O_LEN]; +#define BUF_NOT_EMPTY 0 +#define BUF_EMPTY 1 +#define BUF_PENDING 2 /* Empty, but with job pending --don't submit another */ + int empty; +}; + +/* rng per-device context */ +struct caam_rng_ctx { + struct device_d *jrdev; + dma_addr_t sh_desc_dma; + u32 sh_desc[DESC_RNG_LEN]; + unsigned int cur_buf_idx; + int current_buf; + struct buf_data bufs[2]; + struct cdev cdev; +}; + +static struct caam_rng_ctx *rng_ctx; + +static void rng_done(struct device_d *jrdev, u32 *desc, u32 err, void *context) +{ + struct buf_data *bd; + + bd = (struct buf_data *)((char *)desc - + offsetof(struct buf_data, hw_desc)); + + if (err) + caam_jr_strstatus(jrdev, err); + + bd->empty = BUF_NOT_EMPTY; + + /* Buffer refilled, invalidate cache */ + dma_sync_single_for_cpu(bd->addr, RN_BUF_SIZE, DMA_FROM_DEVICE); + +#ifdef DEBUG + print_hex_dump(KERN_ERR, "rng refreshed buf@: ", + DUMP_PREFIX_OFFSET, 16, 4, bd->buf, RN_BUF_SIZE, 1); +#endif +} + +static inline int submit_job(struct caam_rng_ctx *ctx, int to_current) +{ + struct buf_data *bd = &ctx->bufs[!(to_current ^ ctx->current_buf)]; + struct device_d *jrdev = ctx->jrdev; + u32 *desc = bd->hw_desc; + int err; + + dev_dbg(jrdev, "submitting job %d\n", !(to_current ^ ctx->current_buf)); + + dma_sync_single_for_device((unsigned long)desc, desc_bytes(desc), + DMA_TO_DEVICE); + + err = caam_jr_enqueue(jrdev, desc, rng_done, ctx); + if (!err) + bd->empty += 1; /* note if pending */ + + return err; +} + +static int caam_read(struct caam_rng_ctx *ctx, void *data, size_t max, bool wait) +{ + struct buf_data *bd = &ctx->bufs[ctx->current_buf]; + int next_buf_idx, copied_idx; + int err; + + if (bd->empty) { + /* try to submit job if there wasn't one */ + if (bd->empty == BUF_EMPTY) { + err = submit_job(ctx, 1); + /* if can't submit job, can't even wait */ + if (err) + return 0; + } + /* no immediate data, so exit if not waiting */ + if (!wait) + return 0; + } + + next_buf_idx = ctx->cur_buf_idx + max; + dev_dbg(ctx->jrdev, "%s: start reading at buffer %d, idx %d\n", + __func__, ctx->current_buf, ctx->cur_buf_idx); + + /* if enough data in current buffer */ + if (next_buf_idx < RN_BUF_SIZE) { + memcpy(data, bd->buf + ctx->cur_buf_idx, max); + ctx->cur_buf_idx = next_buf_idx; + return max; + } + + /* else, copy what's left... */ + copied_idx = RN_BUF_SIZE - ctx->cur_buf_idx; + memcpy(data, bd->buf + ctx->cur_buf_idx, copied_idx); + ctx->cur_buf_idx = 0; + bd->empty = BUF_EMPTY; + + /* ...refill... */ + err = submit_job(ctx, 1); + if (err) + return err; + + /* and use next buffer */ + ctx->current_buf = !ctx->current_buf; + dev_dbg(ctx->jrdev, "switched to buffer %d\n", ctx->current_buf); + + /* since there already is some data read, don't wait */ + return copied_idx + caam_read(ctx, data + copied_idx, + max - copied_idx, false); +} + +static inline int rng_create_sh_desc(struct caam_rng_ctx *ctx) +{ + u32 *desc = ctx->sh_desc; + + init_sh_desc(desc, HDR_SHARE_SERIAL); + + /* Propagate errors from shared to job descriptor */ + append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD); + + /* Generate random bytes */ + append_operation(desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG); + + /* Store bytes */ + append_seq_fifo_store(desc, RN_BUF_SIZE, FIFOST_TYPE_RNGSTORE); + + ctx->sh_desc_dma = (dma_addr_t)desc; + + dma_sync_single_for_device((unsigned long)desc, desc_bytes(desc), + DMA_TO_DEVICE); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "rng shdesc@: ", DUMP_PREFIX_OFFSET, 16, 4, + desc, desc_bytes(desc), 1); +#endif + return 0; +} + +static inline int rng_create_job_desc(struct caam_rng_ctx *ctx, int buf_id) +{ + struct buf_data *bd = &ctx->bufs[buf_id]; + u32 *desc = bd->hw_desc; + int sh_len = desc_len(ctx->sh_desc); + + init_job_desc_shared(desc, ctx->sh_desc_dma, sh_len, HDR_SHARE_DEFER | + HDR_REVERSE); + + bd->addr = (dma_addr_t)bd->buf; + + append_seq_out_ptr_intlen(desc, bd->addr, RN_BUF_SIZE, 0); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "rng job desc@: ", DUMP_PREFIX_OFFSET, 16, 4, + desc, desc_bytes(desc), 1); +#endif + return 0; +} + +static int caam_init_buf(struct caam_rng_ctx *ctx, int buf_id) +{ + struct buf_data *bd = &ctx->bufs[buf_id]; + int err; + + err = rng_create_job_desc(ctx, buf_id); + if (err) + return err; + + bd->empty = BUF_EMPTY; + return submit_job(ctx, buf_id == ctx->current_buf); +} + +static int caam_init_rng(struct caam_rng_ctx *ctx, struct device_d *jrdev) +{ + int err; + + ctx->jrdev = jrdev; + + err = rng_create_sh_desc(ctx); + if (err) + return err; + + ctx->current_buf = 0; + ctx->cur_buf_idx = 0; + + err = caam_init_buf(ctx, 0); + if (err) + return err; + + err = caam_init_buf(ctx, 1); + if (err) + return err; + + return 0; +} + +static ssize_t random_read(struct cdev *cdev, void *buf, size_t count, + loff_t offset, ulong flags) +{ + struct caam_rng_ctx *ctx = container_of(cdev, struct caam_rng_ctx, cdev); + + return caam_read(ctx, buf, count, true); +} + +static struct file_operations randomops = { + .read = random_read, + .lseek = dev_lseek_default, +}; + +static int caam_init_devrandom(struct caam_rng_ctx *ctx, struct device_d *dev) +{ + ctx->cdev.name = "hwrng"; + ctx->cdev.flags = DEVFS_IS_CHARACTER_DEV; + ctx->cdev.ops = &randomops; + ctx->cdev.dev = dev; + + return devfs_create(&ctx->cdev); +} + +int caam_rng_probe(struct device_d *dev, struct device_d *jrdev) +{ + int err; + + rng_ctx = xzalloc(sizeof(*rng_ctx)); + + err = caam_init_rng(rng_ctx, jrdev); + if (err) + return err; + + err = caam_init_devrandom(rng_ctx, dev); + if (err) + return err; + + dev_info(dev, "registering rng-caam\n"); + + return 0; +} diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c new file mode 100644 index 0000000000..4deed8a195 --- /dev/null +++ b/drivers/crypto/caam/ctrl.c @@ -0,0 +1,601 @@ +/* + * CAAM control-plane driver backend + * Controller-level driver, kernel property detection, initialization + * + * Copyright 2008-2012 Freescale Semiconductor, Inc. + */ + +#include <common.h> +#include <clock.h> +#include <driver.h> +#include <init.h> +#include <linux/barebox-wrapper.h> +#include <linux/spinlock.h> +#include <linux/clk.h> + +#include "regs.h" +#include "intern.h" +#include "jr.h" +#include "desc_constr.h" +#include "error.h" +#include "ctrl.h" + +/* + * Descriptor to instantiate RNG State Handle 0 in normal mode and + * load the JDKEK, TDKEK and TDSK registers + */ +static void build_instantiation_desc(u32 *desc, int handle, int do_sk) +{ + u32 *jump_cmd, op_flags; + + init_job_desc(desc, 0); + + op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | + (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT; + + /* INIT RNG in non-test mode */ + append_operation(desc, op_flags); + + if (!handle && do_sk) { + /* + * For SH0, Secure Keys must be generated as well + */ + + /* wait for done */ + jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); + set_jump_tgt_here(desc, jump_cmd); + + /* + * load 1 to clear written reg: + * resets the done interrrupt and returns the RNG to idle. + */ + append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); + + /* Initialize State Handle */ + append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | + OP_ALG_AAI_RNG4_SK); + } + + append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); +} + +/* + * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of + * the software (no JR/QI used). + * @ctrldev - pointer to device + * @status - descriptor status, after being run + * + * Return: - 0 if no error occurred + * - -ENODEV if the DECO couldn't be acquired + * - -EAGAIN if an error occurred while executing the descriptor + */ +static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc, + u32 *status) +{ + struct caam_drv_private *ctrlpriv = ctrldev->priv; + struct caam_ctrl __iomem *ctrl; + struct caam_deco __iomem *deco; + u32 deco_dbg_reg, flags; + uint64_t start; + int i; + + ctrl = ctrlpriv->ctrl; + deco = ctrlpriv->deco; + + if (ctrlpriv->virt_en == 1) { + setbits32(&ctrl->deco_rsr, DECORSR_JR0); + + start = get_time_ns(); + while (!(readl(&ctrl->deco_rsr) & DECORSR_VALID)) { + if (is_timeout(start, 100 * MSECOND)) { + dev_err(ctrldev, "DECO timed out\n"); + return -ETIMEDOUT; + } + } + } + + setbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); + + start = get_time_ns(); + while (!(readl(&ctrl->deco_rq) & DECORR_DEN0)) { + if (is_timeout(start, 100 * MSECOND)) { + dev_err(ctrldev, "failed to acquire DECO 0\n"); + clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); + return -ETIMEDOUT; + } + } + + for (i = 0; i < desc_len(desc); i++) + writel(*(desc + i), &deco->descbuf[i]); + + flags = DECO_JQCR_WHL; + /* + * If the descriptor length is longer than 4 words, then the + * FOUR bit in JRCTRL register must be set. + */ + if (desc_len(desc) >= 4) + flags |= DECO_JQCR_FOUR; + + /* Instruct the DECO to execute it */ + writel(flags, &deco->jr_ctl_hi); + + start = get_time_ns(); + while ((deco_dbg_reg = readl(&deco->desc_dbg)) & + DESC_DBG_DECO_STAT_VALID) { + /* + * If an error occured in the descriptor, then + * the DECO status field will be set to 0x0D + */ + if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) == + DESC_DBG_DECO_STAT_HOST_ERR) + break; + } + + *status = readl(&deco->op_status_hi) & + DECO_OP_STATUS_HI_ERR_MASK; + + if (ctrlpriv->virt_en == 1) + clrbits32(&ctrl->deco_rsr, DECORSR_JR0); + + /* Mark the DECO as free */ + clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); + + if (is_timeout(start, 100 * MSECOND)) + return -EAGAIN; + + return 0; +} + +/* + * instantiate_rng - builds and executes a descriptor on DECO0, + * which initializes the RNG block. + * @ctrldev - pointer to device + * @state_handle_mask - bitmask containing the instantiation status + * for the RNG4 state handles which exist in + * the RNG4 block: 1 if it's been instantiated + * by an external entry, 0 otherwise. + * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK; + * Caution: this can be done only once; if the keys need to be + * regenerated, a POR is required + * + * Return: - 0 if no error occurred + * - -ENOMEM if there isn't enough memory to allocate the descriptor + * - -ENODEV if DECO0 couldn't be acquired + * - -EAGAIN if an error occurred when executing the descriptor + * f.i. there was a RNG hardware error due to not "good enough" + * entropy being aquired. + */ +static int instantiate_rng(struct device_d *ctrldev, int state_handle_mask, + int gen_sk) +{ + struct caam_drv_private *ctrlpriv = ctrldev->priv; + struct caam_ctrl __iomem *ctrl; + u32 *desc, status, rdsta_val; + int ret = 0, sh_idx; + + ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; + desc = xzalloc(CAAM_CMD_SZ * 7); + + for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { + /* + * If the corresponding bit is set, this state handle + * was initialized by somebody else, so it's left alone. + */ + if ((1 << sh_idx) & state_handle_mask) + continue; + + /* Create the descriptor for instantiating RNG State Handle */ + build_instantiation_desc(desc, sh_idx, gen_sk); + + /* Try to run it through DECO0 */ + ret = run_descriptor_deco0(ctrldev, desc, &status); + + /* + * If ret is not 0, or descriptor status is not 0, then + * something went wrong. No need to try the next state + * handle (if available), bail out here. + * Also, if for some reason, the State Handle didn't get + * instantiated although the descriptor has finished + * without any error (HW optimizations for later + * CAAM eras), then try again. + */ + rdsta_val = readl(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; + if (status || !(rdsta_val & (1 << sh_idx))) + ret = -EAGAIN; + if (ret) + break; + dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx); + /* Clear the contents before recreating the descriptor */ + memset(desc, 0x00, CAAM_CMD_SZ * 7); + } + + return ret; +} + +static void caam_remove(struct device_d *dev) +{ + struct caam_drv_private *ctrlpriv = dev->priv; + + /* shut clocks off before finalizing shutdown */ + clk_disable(ctrlpriv->caam_ipg); + clk_disable(ctrlpriv->caam_mem); + clk_disable(ctrlpriv->caam_aclk); + clk_disable(ctrlpriv->caam_emi_slow); +} + +/* + * kick_trng - sets the various parameters for enabling the initialization + * of the RNG4 block in CAAM + * @pdev - pointer to the platform device + * @ent_delay - Defines the length (in system clocks) of each entropy sample. + */ +static void kick_trng(struct device_d *ctrldev, int ent_delay) +{ + struct caam_drv_private *ctrlpriv = ctrldev->priv; + struct caam_ctrl __iomem *ctrl; + struct rng4tst __iomem *r4tst; + u32 val; + + ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; + r4tst = &ctrl->r4tst[0]; + + /* put RNG4 into program mode */ + setbits32(&r4tst->rtmctl, RTMCTL_PRGM); + + /* + * Performance-wise, it does not make sense to + * set the delay to a value that is lower + * than the last one that worked (i.e. the state handles + * were instantiated properly. Thus, instead of wasting + * time trying to set the values controlling the sample + * frequency, the function simply returns. + */ + val = (readl(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) + >> RTSDCTL_ENT_DLY_SHIFT; + if (ent_delay <= val) { + /* put RNG4 into run mode */ + clrbits32(&r4tst->rtmctl, RTMCTL_PRGM); + return; + } + + val = readl(&r4tst->rtsdctl); + val = (val & ~RTSDCTL_ENT_DLY_MASK) | + (ent_delay << RTSDCTL_ENT_DLY_SHIFT); + writel(val, &r4tst->rtsdctl); + /* min. freq. count, equal to 1/4 of the entropy sample length */ + writel(ent_delay >> 2, &r4tst->rtfrqmin); + /* disable maximum frequency count */ + writel(RTFRQMAX_DISABLE, &r4tst->rtfrqmax); + /* read the control register */ + val = readl(&r4tst->rtmctl); + /* + * select raw sampling in both entropy shifter + * and statistical checker + */ + setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC); + /* put RNG4 into run mode */ + clrbits32(&val, RTMCTL_PRGM); + /* write back the control register */ + writel(val, &r4tst->rtmctl); +} + +/** + * caam_get_era() - Return the ERA of the SEC on SoC, based + * on "sec-era" propery in the DTS. This property is updated by u-boot. + **/ +int caam_get_era(void) +{ + struct device_node *caam_node; + int ret; + u32 prop; + + caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); + ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop); + + return IS_ERR_VALUE(ret) ? -ENOTSUPP : prop; +} +EXPORT_SYMBOL(caam_get_era); + +/* Probe routine for CAAM top (controller) level */ +static int caam_probe(struct device_d *dev) +{ + int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; + u64 caam_id; + struct device_node *nprop, *np; + struct caam_ctrl __iomem *ctrl; + struct caam_drv_private *ctrlpriv; + u32 scfgr, comp_params; + u32 cha_vid_ls; + int pg_size; + int BLOCK_OFFSET = 0; + + ctrlpriv = xzalloc(sizeof(struct caam_drv_private)); + + dev->priv = ctrlpriv; + ctrlpriv->pdev = dev; + nprop = dev->device_node; + + ctrlpriv->caam_ipg = clk_get(dev, "ipg"); + if (IS_ERR(ctrlpriv->caam_ipg)) { + ret = PTR_ERR(ctrlpriv->caam_ipg); + dev_err(dev, "can't identify CAAM ipg clk: %d\n", ret); + return -ENODEV; + } + + ctrlpriv->caam_mem = clk_get(dev, "mem"); + if (IS_ERR(ctrlpriv->caam_mem)) { + ret = PTR_ERR(ctrlpriv->caam_mem); + dev_err(dev, "can't identify CAAM secure mem clk: %d\n", ret); + return -ENODEV; + } + + ctrlpriv->caam_aclk = clk_get(dev, "aclk"); + if (IS_ERR(ctrlpriv->caam_aclk)) { + ret = PTR_ERR(ctrlpriv->caam_aclk); + dev_err(dev, + "can't identify CAAM aclk clk: %d\n", ret); + return -ENODEV; + } + + ctrlpriv->caam_emi_slow = clk_get(dev, "emi_slow"); + if (IS_ERR(ctrlpriv->caam_emi_slow)) { + ret = PTR_ERR(ctrlpriv->caam_emi_slow); + dev_err(dev, + "can't identify CAAM emi slow clk: %d\n", ret); + return -ENODEV; + } + + ret = clk_enable(ctrlpriv->caam_ipg); + if (ret < 0) { + dev_err(dev, "can't enable CAAM ipg clock: %d\n", ret); + return -ENODEV; + } + + ret = clk_enable(ctrlpriv->caam_mem); + if (ret < 0) { + dev_err(dev, "can't enable CAAM secure mem clock: %d\n", + ret); + return -ENODEV; + } + + ret = clk_enable(ctrlpriv->caam_aclk); + if (ret < 0) { + dev_err(dev, "can't enable CAAM aclk clock: %d\n", ret); + return -ENODEV; + } + + ret = clk_enable(ctrlpriv->caam_emi_slow); + if (ret < 0) { + dev_err(dev, "can't enable CAAM emi slow clock: %d\n", + ret); + return -ENODEV; + } + + /* Get configuration properties from device tree */ + /* First, get register page */ + ctrl = dev_request_mem_region(dev, 0); + if (ctrl == NULL) { + dev_err(dev, "caam: of_iomap() failed\n"); + return -ENOMEM; + } + /* Finding the page size for using the CTPR_MS register */ + comp_params = readl(&ctrl->perfmon.comp_parms_ms); + pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT; + + /* Allocating the BLOCK_OFFSET based on the supported page size on + * the platform + */ + if (pg_size == 0) + BLOCK_OFFSET = PG_SIZE_4K; + else + BLOCK_OFFSET = PG_SIZE_64K; + + ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl; + ctrlpriv->assure = (struct caam_assurance __force *) + ((uint8_t *)ctrl + + BLOCK_OFFSET * ASSURE_BLOCK_NUMBER); + ctrlpriv->deco = (struct caam_deco __force *) + ((uint8_t *)ctrl + + BLOCK_OFFSET * DECO_BLOCK_NUMBER); + + /* + * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, + * long pointers in master configuration register + */ + clrsetbits_be32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_ARCACHE_MASK, + MCFGR_AWCACHE_CACH | MCFGR_ARCACHE_MASK | + MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ? + MCFGR_LONG_PTR : 0)); + + /* + * Read the Compile Time paramters and SCFGR to determine + * if Virtualization is enabled for this platform + */ + scfgr = readl(&ctrl->scfgr); + + ctrlpriv->virt_en = 0; + if (comp_params & CTPR_MS_VIRT_EN_INCL) { + /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or + * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1 + */ + if ((comp_params & CTPR_MS_VIRT_EN_POR) || + (!(comp_params & CTPR_MS_VIRT_EN_POR) && + (scfgr & SCFGR_VIRT_EN))) + ctrlpriv->virt_en = 1; + } else { + /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ + if (comp_params & CTPR_MS_VIRT_EN_POR) + ctrlpriv->virt_en = 1; + } + + if (ctrlpriv->virt_en == 1) + setbits32(&ctrl->jrstart, JRSTART_JR0_START | + JRSTART_JR1_START | JRSTART_JR2_START | + JRSTART_JR3_START); + + /* + * ERRATA: mx6 devices have an issue wherein AXI bus transactions + * may not occur in the correct order. This isn't a problem running + * single descriptors, but can be if running multiple concurrent + * descriptors. Reworking the driver to throttle to single requests + * is impractical, thus the workaround is to limit the AXI pipeline + * to a depth of 1 (from it's default of 4) to preclude this situation + * from occurring. + */ + writel((readl(&ctrl->mcr) & ~(MCFGR_AXIPIPE_MASK)) | + ((1 << MCFGR_AXIPIPE_SHIFT) & MCFGR_AXIPIPE_MASK), &ctrl->mcr); + + /* + * Detect and enable JobRs + * First, find out how many ring spec'ed, allocate references + * for all, then go probe each one. + */ + rspec = 0; + for_each_available_child_of_node(nprop, np) + if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || + of_device_is_compatible(np, "fsl,sec4.0-job-ring")) + rspec++; + + ctrlpriv->jrpdev = xzalloc(sizeof(struct device_d *) * rspec); + + ring = 0; + ctrlpriv->total_jobrs = 0; + for_each_available_child_of_node(nprop, np) { + if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || + of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { + struct device_d *jrdev; + + jrdev = of_platform_device_create(np, dev); + if (!jrdev) + continue; + + ret = caam_jr_probe(jrdev); + if (ret) { + dev_err(dev, "Could not add jobring %d\n", ring); + return ret; + } + + ctrlpriv->jrpdev[ring] = jrdev; + ctrlpriv->jr[ring] = (struct caam_job_ring __force *) + ((uint8_t *)ctrl + + (ring + JR_BLOCK_NUMBER) * + BLOCK_OFFSET); + ctrlpriv->total_jobrs++; + ring++; + } + } + + /* Check to see if QI present. If so, enable */ + ctrlpriv->qi_present = + !!(readl(&ctrl->perfmon.comp_parms_ms) & + CTPR_MS_QI_MASK); + if (ctrlpriv->qi_present) { + ctrlpriv->qi = (struct caam_queue_if __force *) + ((uint8_t *)ctrl + + BLOCK_OFFSET * QI_BLOCK_NUMBER); + /* This is all that's required to physically enable QI */ + writel(QICTL_DQEN, &ctrlpriv->qi->qi_control_lo); + } + + /* If no QI and no rings specified, quit and go home */ + if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { + dev_err(dev, "no queues configured, terminating\n"); + caam_remove(dev); + return -ENOMEM; + } + + cha_vid_ls = readl(&ctrl->perfmon.cha_id_ls); + + /* + * If SEC has RNG version >= 4 and RNG state handle has not been + * already instantiated, do RNG instantiation + */ + if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) { + ctrlpriv->rng4_sh_init = + readl(&ctrl->r4tst[0].rdsta); + /* + * If the secure keys (TDKEK, JDKEK, TDSK), were already + * generated, signal this to the function that is instantiating + * the state handles. An error would occur if RNG4 attempts + * to regenerate these keys before the next POR. + */ + gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; + ctrlpriv->rng4_sh_init &= RDSTA_IFMASK; + do { + int inst_handles = + readl(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; + /* + * If either SH were instantiated by somebody else + * (e.g. u-boot) then it is assumed that the entropy + * parameters are properly set and thus the function + * setting these (kick_trng(...)) is skipped. + * Also, if a handle was instantiated, do not change + * the TRNG parameters. + */ + if (!(ctrlpriv->rng4_sh_init || inst_handles)) { + dev_dbg(dev, "Entropy delay = %u\n", ent_delay); + kick_trng(dev, ent_delay); + ent_delay += 400; + } + /* + * if instantiate_rng(...) fails, the loop will rerun + * and the kick_trng(...) function will modfiy the + * upper and lower limits of the entropy sampling + * interval, leading to a sucessful initialization of + * the RNG. + */ + ret = instantiate_rng(dev, inst_handles, gen_sk); + } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); + + if (ret) { + dev_err(dev, "failed to instantiate RNG"); + caam_remove(dev); + return ret; + } + /* + * Set handles init'ed by this module as the complement of the + * already initialized ones + */ + ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK; + + /* Enable RDB bit so that RNG works faster */ + setbits32(&ctrl->scfgr, SCFGR_RDBENABLE); + } + + if (IS_ENABLED(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG)) { + ret = caam_rng_probe(dev, ctrlpriv->jrpdev[0]); + if (ret) { + dev_err(dev, "failed to instantiate RNG device"); + caam_remove(dev); + return ret; + } + } + + /* NOTE: RTIC detection ought to go here, around Si time */ + caam_id = (u64)readl(&ctrl->perfmon.caam_id_ms) << 32 | + (u64)readl(&ctrl->perfmon.caam_id_ls); + + /* Report "alive" for developer to see */ + dev_dbg(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, + caam_get_era()); + dev_dbg(dev, "job rings = %d, qi = %d\n", + ctrlpriv->total_jobrs, ctrlpriv->qi_present); + + return 0; +} + +static __maybe_unused struct of_device_id caam_match[] = { + { + .compatible = "fsl,sec-v4.0", + }, { + .compatible = "fsl,sec4.0", + }, + {}, +}; + +static struct driver_d caam_driver = { + .name = "caam", + .probe = caam_probe, + .of_compatible = DRV_OF_COMPAT(caam_match), +}; +device_platform_driver(caam_driver); diff --git a/drivers/crypto/caam/ctrl.h b/drivers/crypto/caam/ctrl.h new file mode 100644 index 0000000000..cac5402a46 --- /dev/null +++ b/drivers/crypto/caam/ctrl.h @@ -0,0 +1,13 @@ +/* + * CAAM control-plane driver backend public-level include definitions + * + * Copyright 2012 Freescale Semiconductor, Inc. + */ + +#ifndef CTRL_H +#define CTRL_H + +/* Prototypes for backend-level services exposed to APIs */ +int caam_get_era(void); + +#endif /* CTRL_H */ diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h new file mode 100644 index 0000000000..a12eb86037 --- /dev/null +++ b/drivers/crypto/caam/desc.h @@ -0,0 +1,1665 @@ +/* + * CAAM descriptor composition header + * Definitions to support CAAM descriptor instruction generation + * + * Copyright (C) 2008-2015 Freescale Semiconductor, Inc. + */ + +#ifndef DESC_H +#define DESC_H + +/* + * 16-byte hardware scatter/gather table + * An 8-byte table exists in the hardware spec, but has never been + * implemented to date. The 8/16 option is selected at RTL-compile-time. + * and this selection is visible in the Compile Time Parameters Register + */ + +#define SEC4_SG_LEN_EXT 0x80000000 /* Entry points to table */ +#define SEC4_SG_LEN_FIN 0x40000000 /* Last ent in table */ +#define SEC4_SG_BPID_MASK 0x000000ff +#define SEC4_SG_BPID_SHIFT 16 +#define SEC4_SG_LEN_MASK 0x3fffffff /* Excludes EXT and FINAL */ +#define SEC4_SG_OFFS_MASK 0x00001fff + +struct sec4_sg_entry { +#ifdef CONFIG_64BIT + u64 ptr; +#else + u32 reserved; + u32 ptr; +#endif + u32 len; + u16 buf_pool_id; + u16 offset; +}; + +/* Max size of any CAAM descriptor in 32-bit words, inclusive of header */ +#define MAX_CAAM_DESCSIZE 64 + +/* Block size of any entity covered/uncovered with a KEK/TKEK */ +#define KEK_BLOCKSIZE 16 + +/* + * Supported descriptor command types as they show up + * inside a descriptor command word. + */ +#define CMD_SHIFT 27 +#define CMD_MASK 0xf8000000 + +#define CMD_KEY (0x00 << CMD_SHIFT) +#define CMD_SEQ_KEY (0x01 << CMD_SHIFT) +#define CMD_LOAD (0x02 << CMD_SHIFT) +#define CMD_SEQ_LOAD (0x03 << CMD_SHIFT) +#define CMD_FIFO_LOAD (0x04 << CMD_SHIFT) +#define CMD_SEQ_FIFO_LOAD (0x05 << CMD_SHIFT) +#define CMD_STORE (0x0a << CMD_SHIFT) +#define CMD_SEQ_STORE (0x0b << CMD_SHIFT) +#define CMD_FIFO_STORE (0x0c << CMD_SHIFT) +#define CMD_SEQ_FIFO_STORE (0x0d << CMD_SHIFT) +#define CMD_MOVE_LEN (0x0e << CMD_SHIFT) +#define CMD_MOVE (0x0f << CMD_SHIFT) +#define CMD_OPERATION (0x10 << CMD_SHIFT) +#define CMD_SIGNATURE (0x12 << CMD_SHIFT) +#define CMD_JUMP (0x14 << CMD_SHIFT) +#define CMD_MATH (0x15 << CMD_SHIFT) +#define CMD_DESC_HDR (0x16 << CMD_SHIFT) +#define CMD_SHARED_DESC_HDR (0x17 << CMD_SHIFT) +#define CMD_SEQ_IN_PTR (0x1e << CMD_SHIFT) +#define CMD_SEQ_OUT_PTR (0x1f << CMD_SHIFT) + +/* General-purpose class selector for all commands */ +#define CLASS_SHIFT 25 +#define CLASS_MASK (0x03 << CLASS_SHIFT) + +#define CLASS_NONE (0x00 << CLASS_SHIFT) +#define CLASS_1 (0x01 << CLASS_SHIFT) +#define CLASS_2 (0x02 << CLASS_SHIFT) +#define CLASS_BOTH (0x03 << CLASS_SHIFT) + +/* + * Descriptor header command constructs + * Covers shared, job, and trusted descriptor headers + */ + +/* + * Do Not Run - marks a descriptor inexecutable if there was + * a preceding error somewhere + */ +#define HDR_DNR 0x01000000 + +/* + * ONE - should always be set. Combination of ONE (always + * set) and ZRO (always clear) forms an endianness sanity check + */ +#define HDR_ONE 0x00800000 +#define HDR_ZRO 0x00008000 + +/* Start Index or SharedDesc Length */ +#define HDR_START_IDX_MASK 0x3f +#define HDR_START_IDX_SHIFT 16 + +/* If shared descriptor header, 6-bit length */ +#define HDR_DESCLEN_SHR_MASK 0x3f + +/* If non-shared header, 7-bit length */ +#define HDR_DESCLEN_MASK 0x7f + +/* This is a TrustedDesc (if not SharedDesc) */ +#define HDR_TRUSTED 0x00004000 + +/* Make into TrustedDesc (if not SharedDesc) */ +#define HDR_MAKE_TRUSTED 0x00002000 + +/* Save context if self-shared (if SharedDesc) */ +#define HDR_SAVECTX 0x00001000 + +/* Next item points to SharedDesc */ +#define HDR_SHARED 0x00001000 + +/* + * Reverse Execution Order - execute JobDesc first, then + * execute SharedDesc (normally SharedDesc goes first). + */ +#define HDR_REVERSE 0x00000800 + +/* Propogate DNR property to SharedDesc */ +#define HDR_PROP_DNR 0x00000800 + +/* JobDesc/SharedDesc share property */ +#define HDR_SD_SHARE_MASK 0x03 +#define HDR_SD_SHARE_SHIFT 8 +#define HDR_JD_SHARE_MASK 0x07 +#define HDR_JD_SHARE_SHIFT 8 + +#define HDR_SHARE_NEVER (0x00 << HDR_SD_SHARE_SHIFT) +#define HDR_SHARE_WAIT (0x01 << HDR_SD_SHARE_SHIFT) +#define HDR_SHARE_SERIAL (0x02 << HDR_SD_SHARE_SHIFT) +#define HDR_SHARE_ALWAYS (0x03 << HDR_SD_SHARE_SHIFT) +#define HDR_SHARE_DEFER (0x04 << HDR_SD_SHARE_SHIFT) + +/* JobDesc/SharedDesc descriptor length */ +#define HDR_JD_LENGTH_MASK 0x7f +#define HDR_SD_LENGTH_MASK 0x3f + +/* + * KEY/SEQ_KEY Command Constructs + */ + +/* Key Destination Class: 01 = Class 1, 02 - Class 2 */ +#define KEY_DEST_CLASS_SHIFT 25 /* use CLASS_1 or CLASS_2 */ +#define KEY_DEST_CLASS_MASK (0x03 << KEY_DEST_CLASS_SHIFT) + +/* Scatter-Gather Table/Variable Length Field */ +#define KEY_SGF 0x01000000 +#define KEY_VLF 0x01000000 + +/* Immediate - Key follows command in the descriptor */ +#define KEY_IMM 0x00800000 + +/* + * Encrypted - Key is encrypted either with the KEK, or + * with the TDKEK if TK is set + */ +#define KEY_ENC 0x00400000 + +/* + * No Write Back - Do not allow key to be FIFO STOREd + */ +#define KEY_NWB 0x00200000 + +/* + * Enhanced Encryption of Key + */ +#define KEY_EKT 0x00100000 + +/* + * Encrypted with Trusted Key + */ +#define KEY_TK 0x00008000 + +/* + * KDEST - Key Destination: 0 - class key register, + * 1 - PKHA 'e', 2 - AFHA Sbox, 3 - MDHA split-key + */ +#define KEY_DEST_SHIFT 16 +#define KEY_DEST_MASK (0x03 << KEY_DEST_SHIFT) + +#define KEY_DEST_CLASS_REG (0x00 << KEY_DEST_SHIFT) +#define KEY_DEST_PKHA_E (0x01 << KEY_DEST_SHIFT) +#define KEY_DEST_AFHA_SBOX (0x02 << KEY_DEST_SHIFT) +#define KEY_DEST_MDHA_SPLIT (0x03 << KEY_DEST_SHIFT) + +/* Length in bytes */ +#define KEY_LENGTH_MASK 0x000003ff + +/* + * LOAD/SEQ_LOAD/STORE/SEQ_STORE Command Constructs + */ + +/* + * Load/Store Destination: 0 = class independent CCB, + * 1 = class 1 CCB, 2 = class 2 CCB, 3 = DECO + */ +#define LDST_CLASS_SHIFT 25 +#define LDST_CLASS_MASK (0x03 << LDST_CLASS_SHIFT) +#define LDST_CLASS_IND_CCB (0x00 << LDST_CLASS_SHIFT) +#define LDST_CLASS_1_CCB (0x01 << LDST_CLASS_SHIFT) +#define LDST_CLASS_2_CCB (0x02 << LDST_CLASS_SHIFT) +#define LDST_CLASS_DECO (0x03 << LDST_CLASS_SHIFT) + +/* Scatter-Gather Table/Variable Length Field */ +#define LDST_SGF 0x01000000 +#define LDST_VLF LDST_SGF + +/* Immediate - Key follows this command in descriptor */ +#define LDST_IMM_MASK 1 +#define LDST_IMM_SHIFT 23 +#define LDST_IMM (LDST_IMM_MASK << LDST_IMM_SHIFT) + +/* SRC/DST - Destination for LOAD, Source for STORE */ +#define LDST_SRCDST_SHIFT 16 +#define LDST_SRCDST_MASK (0x7f << LDST_SRCDST_SHIFT) + +#define LDST_SRCDST_BYTE_CONTEXT (0x20 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_BYTE_KEY (0x40 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_BYTE_INFIFO (0x7c << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_BYTE_OUTFIFO (0x7e << LDST_SRCDST_SHIFT) + +#define LDST_SRCDST_WORD_MODE_REG (0x00 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_KEYSZ_REG (0x01 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DATASZ_REG (0x02 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_ICVSZ_REG (0x03 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_CHACTRL (0x06 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECOCTRL (0x06 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_IRQCTRL (0x07 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_PCLOVRD (0x07 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_CLRW (0x08 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_MATH0 (0x08 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_STAT (0x09 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_MATH1 (0x09 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_MATH2 (0x0a << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_AAD_SZ (0x0b << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DECO_MATH3 (0x0b << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_CLASS1_ICV_SZ (0x0c << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_ALTDS_CLASS1 (0x0f << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_PKHA_A_SZ (0x10 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_PKHA_B_SZ (0x11 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_PKHA_N_SZ (0x12 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_PKHA_E_SZ (0x13 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_CLASS_CTX (0x20 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF (0x40 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF_JOB (0x41 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF_SHARED (0x42 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF_JOB_WE (0x45 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_DESCBUF_SHARED_WE (0x46 << LDST_SRCDST_SHIFT) +#define LDST_SRCDST_WORD_INFO_FIFO (0x7a << LDST_SRCDST_SHIFT) + +/* Offset in source/destination */ +#define LDST_OFFSET_SHIFT 8 +#define LDST_OFFSET_MASK (0xff << LDST_OFFSET_SHIFT) + +/* LDOFF definitions used when DST = LDST_SRCDST_WORD_DECOCTRL */ +/* These could also be shifted by LDST_OFFSET_SHIFT - this reads better */ +#define LDOFF_CHG_SHARE_SHIFT 0 +#define LDOFF_CHG_SHARE_MASK (0x3 << LDOFF_CHG_SHARE_SHIFT) +#define LDOFF_CHG_SHARE_NEVER (0x1 << LDOFF_CHG_SHARE_SHIFT) +#define LDOFF_CHG_SHARE_OK_PROP (0x2 << LDOFF_CHG_SHARE_SHIFT) +#define LDOFF_CHG_SHARE_OK_NO_PROP (0x3 << LDOFF_CHG_SHARE_SHIFT) + +#define LDOFF_ENABLE_AUTO_NFIFO (1 << 2) +#define LDOFF_DISABLE_AUTO_NFIFO (1 << 3) + +#define LDOFF_CHG_NONSEQLIODN_SHIFT 4 +#define LDOFF_CHG_NONSEQLIODN_MASK (0x3 << LDOFF_CHG_NONSEQLIODN_SHIFT) +#define LDOFF_CHG_NONSEQLIODN_SEQ (0x1 << LDOFF_CHG_NONSEQLIODN_SHIFT) +#define LDOFF_CHG_NONSEQLIODN_NON_SEQ (0x2 << LDOFF_CHG_NONSEQLIODN_SHIFT) +#define LDOFF_CHG_NONSEQLIODN_TRUSTED (0x3 << LDOFF_CHG_NONSEQLIODN_SHIFT) + +#define LDOFF_CHG_SEQLIODN_SHIFT 6 +#define LDOFF_CHG_SEQLIODN_MASK (0x3 << LDOFF_CHG_SEQLIODN_SHIFT) +#define LDOFF_CHG_SEQLIODN_SEQ (0x1 << LDOFF_CHG_SEQLIODN_SHIFT) +#define LDOFF_CHG_SEQLIODN_NON_SEQ (0x2 << LDOFF_CHG_SEQLIODN_SHIFT) +#define LDOFF_CHG_SEQLIODN_TRUSTED (0x3 << LDOFF_CHG_SEQLIODN_SHIFT) + +/* Data length in bytes */ +#define LDST_LEN_SHIFT 0 +#define LDST_LEN_MASK (0xff << LDST_LEN_SHIFT) + +/* Special Length definitions when dst=deco-ctrl */ +#define LDLEN_ENABLE_OSL_COUNT (1 << 7) +#define LDLEN_RST_CHA_OFIFO_PTR (1 << 6) +#define LDLEN_RST_OFIFO (1 << 5) +#define LDLEN_SET_OFIFO_OFF_VALID (1 << 4) +#define LDLEN_SET_OFIFO_OFF_RSVD (1 << 3) +#define LDLEN_SET_OFIFO_OFFSET_SHIFT 0 +#define LDLEN_SET_OFIFO_OFFSET_MASK (3 << LDLEN_SET_OFIFO_OFFSET_SHIFT) + +/* + * FIFO_LOAD/FIFO_STORE/SEQ_FIFO_LOAD/SEQ_FIFO_STORE + * Command Constructs + */ + +/* + * Load Destination: 0 = skip (SEQ_FIFO_LOAD only), + * 1 = Load for Class1, 2 = Load for Class2, 3 = Load both + * Store Source: 0 = normal, 1 = Class1key, 2 = Class2key + */ +#define FIFOLD_CLASS_SHIFT 25 +#define FIFOLD_CLASS_MASK (0x03 << FIFOLD_CLASS_SHIFT) +#define FIFOLD_CLASS_SKIP (0x00 << FIFOLD_CLASS_SHIFT) +#define FIFOLD_CLASS_CLASS1 (0x01 << FIFOLD_CLASS_SHIFT) +#define FIFOLD_CLASS_CLASS2 (0x02 << FIFOLD_CLASS_SHIFT) +#define FIFOLD_CLASS_BOTH (0x03 << FIFOLD_CLASS_SHIFT) + +#define FIFOST_CLASS_SHIFT 25 +#define FIFOST_CLASS_MASK (0x03 << FIFOST_CLASS_SHIFT) +#define FIFOST_CLASS_NORMAL (0x00 << FIFOST_CLASS_SHIFT) +#define FIFOST_CLASS_CLASS1KEY (0x01 << FIFOST_CLASS_SHIFT) +#define FIFOST_CLASS_CLASS2KEY (0x02 << FIFOST_CLASS_SHIFT) + +/* + * Scatter-Gather Table/Variable Length Field + * If set for FIFO_LOAD, refers to a SG table. Within + * SEQ_FIFO_LOAD, is variable input sequence + */ +#define FIFOLDST_SGF_SHIFT 24 +#define FIFOLDST_SGF_MASK (1 << FIFOLDST_SGF_SHIFT) +#define FIFOLDST_VLF_MASK (1 << FIFOLDST_SGF_SHIFT) +#define FIFOLDST_SGF (1 << FIFOLDST_SGF_SHIFT) +#define FIFOLDST_VLF (1 << FIFOLDST_SGF_SHIFT) + +/* Immediate - Data follows command in descriptor */ +#define FIFOLD_IMM_SHIFT 23 +#define FIFOLD_IMM_MASK (1 << FIFOLD_IMM_SHIFT) +#define FIFOLD_IMM (1 << FIFOLD_IMM_SHIFT) + +/* Continue - Not the last FIFO store to come */ +#define FIFOST_CONT_SHIFT 23 +#define FIFOST_CONT_MASK (1 << FIFOST_CONT_SHIFT) + +/* + * Extended Length - use 32-bit extended length that + * follows the pointer field. Illegal with IMM set + */ +#define FIFOLDST_EXT_SHIFT 22 +#define FIFOLDST_EXT_MASK (1 << FIFOLDST_EXT_SHIFT) +#define FIFOLDST_EXT (1 << FIFOLDST_EXT_SHIFT) + +/* Input data type.*/ +#define FIFOLD_TYPE_SHIFT 16 +#define FIFOLD_CONT_TYPE_SHIFT 19 /* shift past last-flush bits */ +#define FIFOLD_TYPE_MASK (0x3f << FIFOLD_TYPE_SHIFT) + +/* PK types */ +#define FIFOLD_TYPE_PK (0x00 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_MASK (0x30 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_TYPEMASK (0x0f << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A0 (0x00 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A1 (0x01 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A2 (0x02 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A3 (0x03 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B0 (0x04 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B1 (0x05 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B2 (0x06 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B3 (0x07 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_N (0x08 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_A (0x0c << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_PK_B (0x0d << FIFOLD_TYPE_SHIFT) + +/* Other types. Need to OR in last/flush bits as desired */ +#define FIFOLD_TYPE_MSG_MASK (0x38 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_MSG (0x10 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_MSG1OUT2 (0x18 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_IV (0x20 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_BITDATA (0x28 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_AAD (0x30 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_ICV (0x38 << FIFOLD_TYPE_SHIFT) + +/* Last/Flush bits for use with "other" types above */ +#define FIFOLD_TYPE_ACT_MASK (0x07 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_NOACTION (0x00 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_FLUSH1 (0x01 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LAST1 (0x02 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LAST2FLUSH (0x03 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LAST2 (0x04 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LAST2FLUSH1 (0x05 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LASTBOTH (0x06 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_LASTBOTHFL (0x07 << FIFOLD_TYPE_SHIFT) +#define FIFOLD_TYPE_NOINFOFIFO (0x0F << FIFOLD_TYPE_SHIFT) + +#define FIFOLDST_LEN_MASK 0xffff +#define FIFOLDST_EXT_LEN_MASK 0xffffffff + +/* Output data types */ +#define FIFOST_TYPE_SHIFT 16 +#define FIFOST_TYPE_MASK (0x3f << FIFOST_TYPE_SHIFT) + +#define FIFOST_TYPE_PKHA_A0 (0x00 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_A1 (0x01 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_A2 (0x02 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_A3 (0x03 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B0 (0x04 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B1 (0x05 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B2 (0x06 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B3 (0x07 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_N (0x08 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_A (0x0c << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_B (0x0d << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_AF_SBOX_CCM_JKEK (0x10 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_AF_SBOX_CCM_TKEK (0x11 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_CCM_JKEK (0x14 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_CCM_TKEK (0x15 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_E_JKEK (0x22 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_PKHA_E_TKEK (0x23 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_KEK (0x24 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_KEY_TKEK (0x25 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_SPLIT_KEK (0x26 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_SPLIT_TKEK (0x27 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_OUTFIFO_KEK (0x28 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_OUTFIFO_TKEK (0x29 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_MESSAGE_DATA (0x30 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_RNGSTORE (0x34 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_RNGFIFO (0x35 << FIFOST_TYPE_SHIFT) +#define FIFOST_TYPE_SKIP (0x3f << FIFOST_TYPE_SHIFT) + +/* + * OPERATION Command Constructs + */ + +/* Operation type selectors - OP TYPE */ +#define OP_TYPE_SHIFT 24 +#define OP_TYPE_MASK (0x07 << OP_TYPE_SHIFT) + +#define OP_TYPE_UNI_PROTOCOL (0x00 << OP_TYPE_SHIFT) +#define OP_TYPE_PK (0x01 << OP_TYPE_SHIFT) +#define OP_TYPE_CLASS1_ALG (0x02 << OP_TYPE_SHIFT) +#define OP_TYPE_CLASS2_ALG (0x04 << OP_TYPE_SHIFT) +#define OP_TYPE_DECAP_PROTOCOL (0x06 << OP_TYPE_SHIFT) +#define OP_TYPE_ENCAP_PROTOCOL (0x07 << OP_TYPE_SHIFT) + +/* ProtocolID selectors - PROTID */ +#define OP_PCLID_SHIFT 16 +#define OP_PCLID_MASK (0xff << 16) + +/* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */ +#define OP_PCLID_IKEV1_PRF (0x01 << OP_PCLID_SHIFT) +#define OP_PCLID_IKEV2_PRF (0x02 << OP_PCLID_SHIFT) +#define OP_PCLID_SSL30_PRF (0x08 << OP_PCLID_SHIFT) +#define OP_PCLID_TLS10_PRF (0x09 << OP_PCLID_SHIFT) +#define OP_PCLID_TLS11_PRF (0x0a << OP_PCLID_SHIFT) +#define OP_PCLID_DTLS10_PRF (0x0c << OP_PCLID_SHIFT) +#define OP_PCLID_PRF (0x06 << OP_PCLID_SHIFT) +#define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT) +#define OP_PCLID_SECRETKEY (0x11 << OP_PCLID_SHIFT) +#define OP_PCLID_PUBLICKEYPAIR (0x14 << OP_PCLID_SHIFT) +#define OP_PCLID_DSASIGN (0x15 << OP_PCLID_SHIFT) +#define OP_PCLID_DSAVERIFY (0x16 << OP_PCLID_SHIFT) + +/* Assuming OP_TYPE = OP_TYPE_DECAP_PROTOCOL/ENCAP_PROTOCOL */ +#define OP_PCLID_IPSEC (0x01 << OP_PCLID_SHIFT) +#define OP_PCLID_SRTP (0x02 << OP_PCLID_SHIFT) +#define OP_PCLID_MACSEC (0x03 << OP_PCLID_SHIFT) +#define OP_PCLID_WIFI (0x04 << OP_PCLID_SHIFT) +#define OP_PCLID_WIMAX (0x05 << OP_PCLID_SHIFT) +#define OP_PCLID_SSL30 (0x08 << OP_PCLID_SHIFT) +#define OP_PCLID_TLS10 (0x09 << OP_PCLID_SHIFT) +#define OP_PCLID_TLS11 (0x0a << OP_PCLID_SHIFT) +#define OP_PCLID_TLS12 (0x0b << OP_PCLID_SHIFT) +#define OP_PCLID_DTLS (0x0c << OP_PCLID_SHIFT) + +/* + * ProtocolInfo selectors + */ +#define OP_PCLINFO_MASK 0xffff + +/* for OP_PCLID_IPSEC */ +#define OP_PCL_IPSEC_CIPHER_MASK 0xff00 +#define OP_PCL_IPSEC_AUTH_MASK 0x00ff + +#define OP_PCL_IPSEC_DES_IV64 0x0100 +#define OP_PCL_IPSEC_DES 0x0200 +#define OP_PCL_IPSEC_3DES 0x0300 +#define OP_PCL_IPSEC_AES_CBC 0x0c00 +#define OP_PCL_IPSEC_AES_CTR 0x0d00 +#define OP_PCL_IPSEC_AES_XTS 0x1600 +#define OP_PCL_IPSEC_AES_CCM8 0x0e00 +#define OP_PCL_IPSEC_AES_CCM12 0x0f00 +#define OP_PCL_IPSEC_AES_CCM16 0x1000 +#define OP_PCL_IPSEC_AES_GCM8 0x1200 +#define OP_PCL_IPSEC_AES_GCM12 0x1300 +#define OP_PCL_IPSEC_AES_GCM16 0x1400 + +#define OP_PCL_IPSEC_HMAC_NULL 0x0000 +#define OP_PCL_IPSEC_HMAC_MD5_96 0x0001 +#define OP_PCL_IPSEC_HMAC_SHA1_96 0x0002 +#define OP_PCL_IPSEC_AES_XCBC_MAC_96 0x0005 +#define OP_PCL_IPSEC_HMAC_MD5_128 0x0006 +#define OP_PCL_IPSEC_HMAC_SHA1_160 0x0007 +#define OP_PCL_IPSEC_HMAC_SHA2_256_128 0x000c +#define OP_PCL_IPSEC_HMAC_SHA2_384_192 0x000d +#define OP_PCL_IPSEC_HMAC_SHA2_512_256 0x000e + +/* For SRTP - OP_PCLID_SRTP */ +#define OP_PCL_SRTP_CIPHER_MASK 0xff00 +#define OP_PCL_SRTP_AUTH_MASK 0x00ff + +#define OP_PCL_SRTP_AES_CTR 0x0d00 + +#define OP_PCL_SRTP_HMAC_SHA1_160 0x0007 + +/* For SSL 3.0 - OP_PCLID_SSL30 */ +#define OP_PCL_SSL30_AES_128_CBC_SHA 0x002f +#define OP_PCL_SSL30_AES_128_CBC_SHA_2 0x0030 +#define OP_PCL_SSL30_AES_128_CBC_SHA_3 0x0031 +#define OP_PCL_SSL30_AES_128_CBC_SHA_4 0x0032 +#define OP_PCL_SSL30_AES_128_CBC_SHA_5 0x0033 +#define OP_PCL_SSL30_AES_128_CBC_SHA_6 0x0034 +#define OP_PCL_SSL30_AES_128_CBC_SHA_7 0x008c +#define OP_PCL_SSL30_AES_128_CBC_SHA_8 0x0090 +#define OP_PCL_SSL30_AES_128_CBC_SHA_9 0x0094 +#define OP_PCL_SSL30_AES_128_CBC_SHA_10 0xc004 +#define OP_PCL_SSL30_AES_128_CBC_SHA_11 0xc009 +#define OP_PCL_SSL30_AES_128_CBC_SHA_12 0xc00e +#define OP_PCL_SSL30_AES_128_CBC_SHA_13 0xc013 +#define OP_PCL_SSL30_AES_128_CBC_SHA_14 0xc018 +#define OP_PCL_SSL30_AES_128_CBC_SHA_15 0xc01d +#define OP_PCL_SSL30_AES_128_CBC_SHA_16 0xc01e +#define OP_PCL_SSL30_AES_128_CBC_SHA_17 0xc01f + +#define OP_PCL_SSL30_AES_256_CBC_SHA 0x0035 +#define OP_PCL_SSL30_AES_256_CBC_SHA_2 0x0036 +#define OP_PCL_SSL30_AES_256_CBC_SHA_3 0x0037 +#define OP_PCL_SSL30_AES_256_CBC_SHA_4 0x0038 +#define OP_PCL_SSL30_AES_256_CBC_SHA_5 0x0039 +#define OP_PCL_SSL30_AES_256_CBC_SHA_6 0x003a +#define OP_PCL_SSL30_AES_256_CBC_SHA_7 0x008d +#define OP_PCL_SSL30_AES_256_CBC_SHA_8 0x0091 +#define OP_PCL_SSL30_AES_256_CBC_SHA_9 0x0095 +#define OP_PCL_SSL30_AES_256_CBC_SHA_10 0xc005 +#define OP_PCL_SSL30_AES_256_CBC_SHA_11 0xc00a +#define OP_PCL_SSL30_AES_256_CBC_SHA_12 0xc00f +#define OP_PCL_SSL30_AES_256_CBC_SHA_13 0xc014 +#define OP_PCL_SSL30_AES_256_CBC_SHA_14 0xc019 +#define OP_PCL_SSL30_AES_256_CBC_SHA_15 0xc020 +#define OP_PCL_SSL30_AES_256_CBC_SHA_16 0xc021 +#define OP_PCL_SSL30_AES_256_CBC_SHA_17 0xc022 + +#define OP_PCL_SSL30_3DES_EDE_CBC_MD5 0x0023 + +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA 0x001f +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_2 0x008b +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_3 0x008f +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_4 0x0093 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_5 0x000a +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_6 0x000d +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_7 0x0010 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_8 0x0013 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_9 0x0016 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_10 0x001b +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_11 0xc003 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_12 0xc008 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_13 0xc00d +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_14 0xc012 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_15 0xc017 +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_16 0xc01a +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_17 0xc01b +#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_18 0xc01c + +#define OP_PCL_SSL30_DES40_CBC_MD5 0x0029 + +#define OP_PCL_SSL30_DES_CBC_MD5 0x0022 + +#define OP_PCL_SSL30_DES40_CBC_SHA 0x0008 +#define OP_PCL_SSL30_DES40_CBC_SHA_2 0x000b +#define OP_PCL_SSL30_DES40_CBC_SHA_3 0x000e +#define OP_PCL_SSL30_DES40_CBC_SHA_4 0x0011 +#define OP_PCL_SSL30_DES40_CBC_SHA_5 0x0014 +#define OP_PCL_SSL30_DES40_CBC_SHA_6 0x0019 +#define OP_PCL_SSL30_DES40_CBC_SHA_7 0x0026 + +#define OP_PCL_SSL30_DES_CBC_SHA 0x001e +#define OP_PCL_SSL30_DES_CBC_SHA_2 0x0009 +#define OP_PCL_SSL30_DES_CBC_SHA_3 0x000c +#define OP_PCL_SSL30_DES_CBC_SHA_4 0x000f +#define OP_PCL_SSL30_DES_CBC_SHA_5 0x0012 +#define OP_PCL_SSL30_DES_CBC_SHA_6 0x0015 +#define OP_PCL_SSL30_DES_CBC_SHA_7 0x001a + +#define OP_PCL_SSL30_RC4_128_MD5 0x0024 +#define OP_PCL_SSL30_RC4_128_MD5_2 0x0004 +#define OP_PCL_SSL30_RC4_128_MD5_3 0x0018 + +#define OP_PCL_SSL30_RC4_40_MD5 0x002b +#define OP_PCL_SSL30_RC4_40_MD5_2 0x0003 +#define OP_PCL_SSL30_RC4_40_MD5_3 0x0017 + +#define OP_PCL_SSL30_RC4_128_SHA 0x0020 +#define OP_PCL_SSL30_RC4_128_SHA_2 0x008a +#define OP_PCL_SSL30_RC4_128_SHA_3 0x008e +#define OP_PCL_SSL30_RC4_128_SHA_4 0x0092 +#define OP_PCL_SSL30_RC4_128_SHA_5 0x0005 +#define OP_PCL_SSL30_RC4_128_SHA_6 0xc002 +#define OP_PCL_SSL30_RC4_128_SHA_7 0xc007 +#define OP_PCL_SSL30_RC4_128_SHA_8 0xc00c +#define OP_PCL_SSL30_RC4_128_SHA_9 0xc011 +#define OP_PCL_SSL30_RC4_128_SHA_10 0xc016 + +#define OP_PCL_SSL30_RC4_40_SHA 0x0028 + + +/* For TLS 1.0 - OP_PCLID_TLS10 */ +#define OP_PCL_TLS10_AES_128_CBC_SHA 0x002f +#define OP_PCL_TLS10_AES_128_CBC_SHA_2 0x0030 +#define OP_PCL_TLS10_AES_128_CBC_SHA_3 0x0031 +#define OP_PCL_TLS10_AES_128_CBC_SHA_4 0x0032 +#define OP_PCL_TLS10_AES_128_CBC_SHA_5 0x0033 +#define OP_PCL_TLS10_AES_128_CBC_SHA_6 0x0034 +#define OP_PCL_TLS10_AES_128_CBC_SHA_7 0x008c +#define OP_PCL_TLS10_AES_128_CBC_SHA_8 0x0090 +#define OP_PCL_TLS10_AES_128_CBC_SHA_9 0x0094 +#define OP_PCL_TLS10_AES_128_CBC_SHA_10 0xc004 +#define OP_PCL_TLS10_AES_128_CBC_SHA_11 0xc009 +#define OP_PCL_TLS10_AES_128_CBC_SHA_12 0xc00e +#define OP_PCL_TLS10_AES_128_CBC_SHA_13 0xc013 +#define OP_PCL_TLS10_AES_128_CBC_SHA_14 0xc018 +#define OP_PCL_TLS10_AES_128_CBC_SHA_15 0xc01d +#define OP_PCL_TLS10_AES_128_CBC_SHA_16 0xc01e +#define OP_PCL_TLS10_AES_128_CBC_SHA_17 0xc01f + +#define OP_PCL_TLS10_AES_256_CBC_SHA 0x0035 +#define OP_PCL_TLS10_AES_256_CBC_SHA_2 0x0036 +#define OP_PCL_TLS10_AES_256_CBC_SHA_3 0x0037 +#define OP_PCL_TLS10_AES_256_CBC_SHA_4 0x0038 +#define OP_PCL_TLS10_AES_256_CBC_SHA_5 0x0039 +#define OP_PCL_TLS10_AES_256_CBC_SHA_6 0x003a +#define OP_PCL_TLS10_AES_256_CBC_SHA_7 0x008d +#define OP_PCL_TLS10_AES_256_CBC_SHA_8 0x0091 +#define OP_PCL_TLS10_AES_256_CBC_SHA_9 0x0095 +#define OP_PCL_TLS10_AES_256_CBC_SHA_10 0xc005 +#define OP_PCL_TLS10_AES_256_CBC_SHA_11 0xc00a +#define OP_PCL_TLS10_AES_256_CBC_SHA_12 0xc00f +#define OP_PCL_TLS10_AES_256_CBC_SHA_13 0xc014 +#define OP_PCL_TLS10_AES_256_CBC_SHA_14 0xc019 +#define OP_PCL_TLS10_AES_256_CBC_SHA_15 0xc020 +#define OP_PCL_TLS10_AES_256_CBC_SHA_16 0xc021 +#define OP_PCL_TLS10_AES_256_CBC_SHA_17 0xc022 + +/* #define OP_PCL_TLS10_3DES_EDE_CBC_MD5 0x0023 */ + +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA 0x001f +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_2 0x008b +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_3 0x008f +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_4 0x0093 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_5 0x000a +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_6 0x000d +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_7 0x0010 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_8 0x0013 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_9 0x0016 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_10 0x001b +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_11 0xc003 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_12 0xc008 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_13 0xc00d +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_14 0xc012 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_15 0xc017 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_16 0xc01a +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_17 0xc01b +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_18 0xc01c + +#define OP_PCL_TLS10_DES40_CBC_MD5 0x0029 + +#define OP_PCL_TLS10_DES_CBC_MD5 0x0022 + +#define OP_PCL_TLS10_DES40_CBC_SHA 0x0008 +#define OP_PCL_TLS10_DES40_CBC_SHA_2 0x000b +#define OP_PCL_TLS10_DES40_CBC_SHA_3 0x000e +#define OP_PCL_TLS10_DES40_CBC_SHA_4 0x0011 +#define OP_PCL_TLS10_DES40_CBC_SHA_5 0x0014 +#define OP_PCL_TLS10_DES40_CBC_SHA_6 0x0019 +#define OP_PCL_TLS10_DES40_CBC_SHA_7 0x0026 + + +#define OP_PCL_TLS10_DES_CBC_SHA 0x001e +#define OP_PCL_TLS10_DES_CBC_SHA_2 0x0009 +#define OP_PCL_TLS10_DES_CBC_SHA_3 0x000c +#define OP_PCL_TLS10_DES_CBC_SHA_4 0x000f +#define OP_PCL_TLS10_DES_CBC_SHA_5 0x0012 +#define OP_PCL_TLS10_DES_CBC_SHA_6 0x0015 +#define OP_PCL_TLS10_DES_CBC_SHA_7 0x001a + +#define OP_PCL_TLS10_RC4_128_MD5 0x0024 +#define OP_PCL_TLS10_RC4_128_MD5_2 0x0004 +#define OP_PCL_TLS10_RC4_128_MD5_3 0x0018 + +#define OP_PCL_TLS10_RC4_40_MD5 0x002b +#define OP_PCL_TLS10_RC4_40_MD5_2 0x0003 +#define OP_PCL_TLS10_RC4_40_MD5_3 0x0017 + +#define OP_PCL_TLS10_RC4_128_SHA 0x0020 +#define OP_PCL_TLS10_RC4_128_SHA_2 0x008a +#define OP_PCL_TLS10_RC4_128_SHA_3 0x008e +#define OP_PCL_TLS10_RC4_128_SHA_4 0x0092 +#define OP_PCL_TLS10_RC4_128_SHA_5 0x0005 +#define OP_PCL_TLS10_RC4_128_SHA_6 0xc002 +#define OP_PCL_TLS10_RC4_128_SHA_7 0xc007 +#define OP_PCL_TLS10_RC4_128_SHA_8 0xc00c +#define OP_PCL_TLS10_RC4_128_SHA_9 0xc011 +#define OP_PCL_TLS10_RC4_128_SHA_10 0xc016 + +#define OP_PCL_TLS10_RC4_40_SHA 0x0028 + +#define OP_PCL_TLS10_3DES_EDE_CBC_MD5 0xff23 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA160 0xff30 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA224 0xff34 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA256 0xff36 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA384 0xff33 +#define OP_PCL_TLS10_3DES_EDE_CBC_SHA512 0xff35 +#define OP_PCL_TLS10_AES_128_CBC_SHA160 0xff80 +#define OP_PCL_TLS10_AES_128_CBC_SHA224 0xff84 +#define OP_PCL_TLS10_AES_128_CBC_SHA256 0xff86 +#define OP_PCL_TLS10_AES_128_CBC_SHA384 0xff83 +#define OP_PCL_TLS10_AES_128_CBC_SHA512 0xff85 +#define OP_PCL_TLS10_AES_192_CBC_SHA160 0xff20 +#define OP_PCL_TLS10_AES_192_CBC_SHA224 0xff24 +#define OP_PCL_TLS10_AES_192_CBC_SHA256 0xff26 +#define OP_PCL_TLS10_AES_192_CBC_SHA384 0xff23 +#define OP_PCL_TLS10_AES_192_CBC_SHA512 0xff25 +#define OP_PCL_TLS10_AES_256_CBC_SHA160 0xff60 +#define OP_PCL_TLS10_AES_256_CBC_SHA224 0xff64 +#define OP_PCL_TLS10_AES_256_CBC_SHA256 0xff66 +#define OP_PCL_TLS10_AES_256_CBC_SHA384 0xff63 +#define OP_PCL_TLS10_AES_256_CBC_SHA512 0xff65 + + + +/* For TLS 1.1 - OP_PCLID_TLS11 */ +#define OP_PCL_TLS11_AES_128_CBC_SHA 0x002f +#define OP_PCL_TLS11_AES_128_CBC_SHA_2 0x0030 +#define OP_PCL_TLS11_AES_128_CBC_SHA_3 0x0031 +#define OP_PCL_TLS11_AES_128_CBC_SHA_4 0x0032 +#define OP_PCL_TLS11_AES_128_CBC_SHA_5 0x0033 +#define OP_PCL_TLS11_AES_128_CBC_SHA_6 0x0034 +#define OP_PCL_TLS11_AES_128_CBC_SHA_7 0x008c +#define OP_PCL_TLS11_AES_128_CBC_SHA_8 0x0090 +#define OP_PCL_TLS11_AES_128_CBC_SHA_9 0x0094 +#define OP_PCL_TLS11_AES_128_CBC_SHA_10 0xc004 +#define OP_PCL_TLS11_AES_128_CBC_SHA_11 0xc009 +#define OP_PCL_TLS11_AES_128_CBC_SHA_12 0xc00e +#define OP_PCL_TLS11_AES_128_CBC_SHA_13 0xc013 +#define OP_PCL_TLS11_AES_128_CBC_SHA_14 0xc018 +#define OP_PCL_TLS11_AES_128_CBC_SHA_15 0xc01d +#define OP_PCL_TLS11_AES_128_CBC_SHA_16 0xc01e +#define OP_PCL_TLS11_AES_128_CBC_SHA_17 0xc01f + +#define OP_PCL_TLS11_AES_256_CBC_SHA 0x0035 +#define OP_PCL_TLS11_AES_256_CBC_SHA_2 0x0036 +#define OP_PCL_TLS11_AES_256_CBC_SHA_3 0x0037 +#define OP_PCL_TLS11_AES_256_CBC_SHA_4 0x0038 +#define OP_PCL_TLS11_AES_256_CBC_SHA_5 0x0039 +#define OP_PCL_TLS11_AES_256_CBC_SHA_6 0x003a +#define OP_PCL_TLS11_AES_256_CBC_SHA_7 0x008d +#define OP_PCL_TLS11_AES_256_CBC_SHA_8 0x0091 +#define OP_PCL_TLS11_AES_256_CBC_SHA_9 0x0095 +#define OP_PCL_TLS11_AES_256_CBC_SHA_10 0xc005 +#define OP_PCL_TLS11_AES_256_CBC_SHA_11 0xc00a +#define OP_PCL_TLS11_AES_256_CBC_SHA_12 0xc00f +#define OP_PCL_TLS11_AES_256_CBC_SHA_13 0xc014 +#define OP_PCL_TLS11_AES_256_CBC_SHA_14 0xc019 +#define OP_PCL_TLS11_AES_256_CBC_SHA_15 0xc020 +#define OP_PCL_TLS11_AES_256_CBC_SHA_16 0xc021 +#define OP_PCL_TLS11_AES_256_CBC_SHA_17 0xc022 + +/* #define OP_PCL_TLS11_3DES_EDE_CBC_MD5 0x0023 */ + +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA 0x001f +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_2 0x008b +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_3 0x008f +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_4 0x0093 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_5 0x000a +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_6 0x000d +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_7 0x0010 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_8 0x0013 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_9 0x0016 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_10 0x001b +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_11 0xc003 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_12 0xc008 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_13 0xc00d +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_14 0xc012 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_15 0xc017 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_16 0xc01a +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_17 0xc01b +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_18 0xc01c + +#define OP_PCL_TLS11_DES40_CBC_MD5 0x0029 + +#define OP_PCL_TLS11_DES_CBC_MD5 0x0022 + +#define OP_PCL_TLS11_DES40_CBC_SHA 0x0008 +#define OP_PCL_TLS11_DES40_CBC_SHA_2 0x000b +#define OP_PCL_TLS11_DES40_CBC_SHA_3 0x000e +#define OP_PCL_TLS11_DES40_CBC_SHA_4 0x0011 +#define OP_PCL_TLS11_DES40_CBC_SHA_5 0x0014 +#define OP_PCL_TLS11_DES40_CBC_SHA_6 0x0019 +#define OP_PCL_TLS11_DES40_CBC_SHA_7 0x0026 + +#define OP_PCL_TLS11_DES_CBC_SHA 0x001e +#define OP_PCL_TLS11_DES_CBC_SHA_2 0x0009 +#define OP_PCL_TLS11_DES_CBC_SHA_3 0x000c +#define OP_PCL_TLS11_DES_CBC_SHA_4 0x000f +#define OP_PCL_TLS11_DES_CBC_SHA_5 0x0012 +#define OP_PCL_TLS11_DES_CBC_SHA_6 0x0015 +#define OP_PCL_TLS11_DES_CBC_SHA_7 0x001a + +#define OP_PCL_TLS11_RC4_128_MD5 0x0024 +#define OP_PCL_TLS11_RC4_128_MD5_2 0x0004 +#define OP_PCL_TLS11_RC4_128_MD5_3 0x0018 + +#define OP_PCL_TLS11_RC4_40_MD5 0x002b +#define OP_PCL_TLS11_RC4_40_MD5_2 0x0003 +#define OP_PCL_TLS11_RC4_40_MD5_3 0x0017 + +#define OP_PCL_TLS11_RC4_128_SHA 0x0020 +#define OP_PCL_TLS11_RC4_128_SHA_2 0x008a +#define OP_PCL_TLS11_RC4_128_SHA_3 0x008e +#define OP_PCL_TLS11_RC4_128_SHA_4 0x0092 +#define OP_PCL_TLS11_RC4_128_SHA_5 0x0005 +#define OP_PCL_TLS11_RC4_128_SHA_6 0xc002 +#define OP_PCL_TLS11_RC4_128_SHA_7 0xc007 +#define OP_PCL_TLS11_RC4_128_SHA_8 0xc00c +#define OP_PCL_TLS11_RC4_128_SHA_9 0xc011 +#define OP_PCL_TLS11_RC4_128_SHA_10 0xc016 + +#define OP_PCL_TLS11_RC4_40_SHA 0x0028 + +#define OP_PCL_TLS11_3DES_EDE_CBC_MD5 0xff23 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA160 0xff30 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA224 0xff34 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA256 0xff36 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA384 0xff33 +#define OP_PCL_TLS11_3DES_EDE_CBC_SHA512 0xff35 +#define OP_PCL_TLS11_AES_128_CBC_SHA160 0xff80 +#define OP_PCL_TLS11_AES_128_CBC_SHA224 0xff84 +#define OP_PCL_TLS11_AES_128_CBC_SHA256 0xff86 +#define OP_PCL_TLS11_AES_128_CBC_SHA384 0xff83 +#define OP_PCL_TLS11_AES_128_CBC_SHA512 0xff85 +#define OP_PCL_TLS11_AES_192_CBC_SHA160 0xff20 +#define OP_PCL_TLS11_AES_192_CBC_SHA224 0xff24 +#define OP_PCL_TLS11_AES_192_CBC_SHA256 0xff26 +#define OP_PCL_TLS11_AES_192_CBC_SHA384 0xff23 +#define OP_PCL_TLS11_AES_192_CBC_SHA512 0xff25 +#define OP_PCL_TLS11_AES_256_CBC_SHA160 0xff60 +#define OP_PCL_TLS11_AES_256_CBC_SHA224 0xff64 +#define OP_PCL_TLS11_AES_256_CBC_SHA256 0xff66 +#define OP_PCL_TLS11_AES_256_CBC_SHA384 0xff63 +#define OP_PCL_TLS11_AES_256_CBC_SHA512 0xff65 + + +/* For TLS 1.2 - OP_PCLID_TLS12 */ +#define OP_PCL_TLS12_AES_128_CBC_SHA 0x002f +#define OP_PCL_TLS12_AES_128_CBC_SHA_2 0x0030 +#define OP_PCL_TLS12_AES_128_CBC_SHA_3 0x0031 +#define OP_PCL_TLS12_AES_128_CBC_SHA_4 0x0032 +#define OP_PCL_TLS12_AES_128_CBC_SHA_5 0x0033 +#define OP_PCL_TLS12_AES_128_CBC_SHA_6 0x0034 +#define OP_PCL_TLS12_AES_128_CBC_SHA_7 0x008c +#define OP_PCL_TLS12_AES_128_CBC_SHA_8 0x0090 +#define OP_PCL_TLS12_AES_128_CBC_SHA_9 0x0094 +#define OP_PCL_TLS12_AES_128_CBC_SHA_10 0xc004 +#define OP_PCL_TLS12_AES_128_CBC_SHA_11 0xc009 +#define OP_PCL_TLS12_AES_128_CBC_SHA_12 0xc00e +#define OP_PCL_TLS12_AES_128_CBC_SHA_13 0xc013 +#define OP_PCL_TLS12_AES_128_CBC_SHA_14 0xc018 +#define OP_PCL_TLS12_AES_128_CBC_SHA_15 0xc01d +#define OP_PCL_TLS12_AES_128_CBC_SHA_16 0xc01e +#define OP_PCL_TLS12_AES_128_CBC_SHA_17 0xc01f + +#define OP_PCL_TLS12_AES_256_CBC_SHA 0x0035 +#define OP_PCL_TLS12_AES_256_CBC_SHA_2 0x0036 +#define OP_PCL_TLS12_AES_256_CBC_SHA_3 0x0037 +#define OP_PCL_TLS12_AES_256_CBC_SHA_4 0x0038 +#define OP_PCL_TLS12_AES_256_CBC_SHA_5 0x0039 +#define OP_PCL_TLS12_AES_256_CBC_SHA_6 0x003a +#define OP_PCL_TLS12_AES_256_CBC_SHA_7 0x008d +#define OP_PCL_TLS12_AES_256_CBC_SHA_8 0x0091 +#define OP_PCL_TLS12_AES_256_CBC_SHA_9 0x0095 +#define OP_PCL_TLS12_AES_256_CBC_SHA_10 0xc005 +#define OP_PCL_TLS12_AES_256_CBC_SHA_11 0xc00a +#define OP_PCL_TLS12_AES_256_CBC_SHA_12 0xc00f +#define OP_PCL_TLS12_AES_256_CBC_SHA_13 0xc014 +#define OP_PCL_TLS12_AES_256_CBC_SHA_14 0xc019 +#define OP_PCL_TLS12_AES_256_CBC_SHA_15 0xc020 +#define OP_PCL_TLS12_AES_256_CBC_SHA_16 0xc021 +#define OP_PCL_TLS12_AES_256_CBC_SHA_17 0xc022 + +/* #define OP_PCL_TLS12_3DES_EDE_CBC_MD5 0x0023 */ + +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA 0x001f +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_2 0x008b +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_3 0x008f +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_4 0x0093 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_5 0x000a +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_6 0x000d +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_7 0x0010 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_8 0x0013 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_9 0x0016 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_10 0x001b +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_11 0xc003 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_12 0xc008 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_13 0xc00d +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_14 0xc012 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_15 0xc017 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_16 0xc01a +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_17 0xc01b +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_18 0xc01c + +#define OP_PCL_TLS12_DES40_CBC_MD5 0x0029 + +#define OP_PCL_TLS12_DES_CBC_MD5 0x0022 + +#define OP_PCL_TLS12_DES40_CBC_SHA 0x0008 +#define OP_PCL_TLS12_DES40_CBC_SHA_2 0x000b +#define OP_PCL_TLS12_DES40_CBC_SHA_3 0x000e +#define OP_PCL_TLS12_DES40_CBC_SHA_4 0x0011 +#define OP_PCL_TLS12_DES40_CBC_SHA_5 0x0014 +#define OP_PCL_TLS12_DES40_CBC_SHA_6 0x0019 +#define OP_PCL_TLS12_DES40_CBC_SHA_7 0x0026 + +#define OP_PCL_TLS12_DES_CBC_SHA 0x001e +#define OP_PCL_TLS12_DES_CBC_SHA_2 0x0009 +#define OP_PCL_TLS12_DES_CBC_SHA_3 0x000c +#define OP_PCL_TLS12_DES_CBC_SHA_4 0x000f +#define OP_PCL_TLS12_DES_CBC_SHA_5 0x0012 +#define OP_PCL_TLS12_DES_CBC_SHA_6 0x0015 +#define OP_PCL_TLS12_DES_CBC_SHA_7 0x001a + +#define OP_PCL_TLS12_RC4_128_MD5 0x0024 +#define OP_PCL_TLS12_RC4_128_MD5_2 0x0004 +#define OP_PCL_TLS12_RC4_128_MD5_3 0x0018 + +#define OP_PCL_TLS12_RC4_40_MD5 0x002b +#define OP_PCL_TLS12_RC4_40_MD5_2 0x0003 +#define OP_PCL_TLS12_RC4_40_MD5_3 0x0017 + +#define OP_PCL_TLS12_RC4_128_SHA 0x0020 +#define OP_PCL_TLS12_RC4_128_SHA_2 0x008a +#define OP_PCL_TLS12_RC4_128_SHA_3 0x008e +#define OP_PCL_TLS12_RC4_128_SHA_4 0x0092 +#define OP_PCL_TLS12_RC4_128_SHA_5 0x0005 +#define OP_PCL_TLS12_RC4_128_SHA_6 0xc002 +#define OP_PCL_TLS12_RC4_128_SHA_7 0xc007 +#define OP_PCL_TLS12_RC4_128_SHA_8 0xc00c +#define OP_PCL_TLS12_RC4_128_SHA_9 0xc011 +#define OP_PCL_TLS12_RC4_128_SHA_10 0xc016 + +#define OP_PCL_TLS12_RC4_40_SHA 0x0028 + +/* #define OP_PCL_TLS12_AES_128_CBC_SHA256 0x003c */ +#define OP_PCL_TLS12_AES_128_CBC_SHA256_2 0x003e +#define OP_PCL_TLS12_AES_128_CBC_SHA256_3 0x003f +#define OP_PCL_TLS12_AES_128_CBC_SHA256_4 0x0040 +#define OP_PCL_TLS12_AES_128_CBC_SHA256_5 0x0067 +#define OP_PCL_TLS12_AES_128_CBC_SHA256_6 0x006c + +/* #define OP_PCL_TLS12_AES_256_CBC_SHA256 0x003d */ +#define OP_PCL_TLS12_AES_256_CBC_SHA256_2 0x0068 +#define OP_PCL_TLS12_AES_256_CBC_SHA256_3 0x0069 +#define OP_PCL_TLS12_AES_256_CBC_SHA256_4 0x006a +#define OP_PCL_TLS12_AES_256_CBC_SHA256_5 0x006b +#define OP_PCL_TLS12_AES_256_CBC_SHA256_6 0x006d + +/* AEAD_AES_xxx_CCM/GCM remain to be defined... */ + +#define OP_PCL_TLS12_3DES_EDE_CBC_MD5 0xff23 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA160 0xff30 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA224 0xff34 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA256 0xff36 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA384 0xff33 +#define OP_PCL_TLS12_3DES_EDE_CBC_SHA512 0xff35 +#define OP_PCL_TLS12_AES_128_CBC_SHA160 0xff80 +#define OP_PCL_TLS12_AES_128_CBC_SHA224 0xff84 +#define OP_PCL_TLS12_AES_128_CBC_SHA256 0xff86 +#define OP_PCL_TLS12_AES_128_CBC_SHA384 0xff83 +#define OP_PCL_TLS12_AES_128_CBC_SHA512 0xff85 +#define OP_PCL_TLS12_AES_192_CBC_SHA160 0xff20 +#define OP_PCL_TLS12_AES_192_CBC_SHA224 0xff24 +#define OP_PCL_TLS12_AES_192_CBC_SHA256 0xff26 +#define OP_PCL_TLS12_AES_192_CBC_SHA384 0xff23 +#define OP_PCL_TLS12_AES_192_CBC_SHA512 0xff25 +#define OP_PCL_TLS12_AES_256_CBC_SHA160 0xff60 +#define OP_PCL_TLS12_AES_256_CBC_SHA224 0xff64 +#define OP_PCL_TLS12_AES_256_CBC_SHA256 0xff66 +#define OP_PCL_TLS12_AES_256_CBC_SHA384 0xff63 +#define OP_PCL_TLS12_AES_256_CBC_SHA512 0xff65 + +/* For DTLS - OP_PCLID_DTLS */ + +#define OP_PCL_DTLS_AES_128_CBC_SHA 0x002f +#define OP_PCL_DTLS_AES_128_CBC_SHA_2 0x0030 +#define OP_PCL_DTLS_AES_128_CBC_SHA_3 0x0031 +#define OP_PCL_DTLS_AES_128_CBC_SHA_4 0x0032 +#define OP_PCL_DTLS_AES_128_CBC_SHA_5 0x0033 +#define OP_PCL_DTLS_AES_128_CBC_SHA_6 0x0034 +#define OP_PCL_DTLS_AES_128_CBC_SHA_7 0x008c +#define OP_PCL_DTLS_AES_128_CBC_SHA_8 0x0090 +#define OP_PCL_DTLS_AES_128_CBC_SHA_9 0x0094 +#define OP_PCL_DTLS_AES_128_CBC_SHA_10 0xc004 +#define OP_PCL_DTLS_AES_128_CBC_SHA_11 0xc009 +#define OP_PCL_DTLS_AES_128_CBC_SHA_12 0xc00e +#define OP_PCL_DTLS_AES_128_CBC_SHA_13 0xc013 +#define OP_PCL_DTLS_AES_128_CBC_SHA_14 0xc018 +#define OP_PCL_DTLS_AES_128_CBC_SHA_15 0xc01d +#define OP_PCL_DTLS_AES_128_CBC_SHA_16 0xc01e +#define OP_PCL_DTLS_AES_128_CBC_SHA_17 0xc01f + +#define OP_PCL_DTLS_AES_256_CBC_SHA 0x0035 +#define OP_PCL_DTLS_AES_256_CBC_SHA_2 0x0036 +#define OP_PCL_DTLS_AES_256_CBC_SHA_3 0x0037 +#define OP_PCL_DTLS_AES_256_CBC_SHA_4 0x0038 +#define OP_PCL_DTLS_AES_256_CBC_SHA_5 0x0039 +#define OP_PCL_DTLS_AES_256_CBC_SHA_6 0x003a +#define OP_PCL_DTLS_AES_256_CBC_SHA_7 0x008d +#define OP_PCL_DTLS_AES_256_CBC_SHA_8 0x0091 +#define OP_PCL_DTLS_AES_256_CBC_SHA_9 0x0095 +#define OP_PCL_DTLS_AES_256_CBC_SHA_10 0xc005 +#define OP_PCL_DTLS_AES_256_CBC_SHA_11 0xc00a +#define OP_PCL_DTLS_AES_256_CBC_SHA_12 0xc00f +#define OP_PCL_DTLS_AES_256_CBC_SHA_13 0xc014 +#define OP_PCL_DTLS_AES_256_CBC_SHA_14 0xc019 +#define OP_PCL_DTLS_AES_256_CBC_SHA_15 0xc020 +#define OP_PCL_DTLS_AES_256_CBC_SHA_16 0xc021 +#define OP_PCL_DTLS_AES_256_CBC_SHA_17 0xc022 + +/* #define OP_PCL_DTLS_3DES_EDE_CBC_MD5 0x0023 */ + +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA 0x001f +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_2 0x008b +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_3 0x008f +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_4 0x0093 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_5 0x000a +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_6 0x000d +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_7 0x0010 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_8 0x0013 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_9 0x0016 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_10 0x001b +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_11 0xc003 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_12 0xc008 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_13 0xc00d +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_14 0xc012 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_15 0xc017 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_16 0xc01a +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_17 0xc01b +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_18 0xc01c + +#define OP_PCL_DTLS_DES40_CBC_MD5 0x0029 + +#define OP_PCL_DTLS_DES_CBC_MD5 0x0022 + +#define OP_PCL_DTLS_DES40_CBC_SHA 0x0008 +#define OP_PCL_DTLS_DES40_CBC_SHA_2 0x000b +#define OP_PCL_DTLS_DES40_CBC_SHA_3 0x000e +#define OP_PCL_DTLS_DES40_CBC_SHA_4 0x0011 +#define OP_PCL_DTLS_DES40_CBC_SHA_5 0x0014 +#define OP_PCL_DTLS_DES40_CBC_SHA_6 0x0019 +#define OP_PCL_DTLS_DES40_CBC_SHA_7 0x0026 + + +#define OP_PCL_DTLS_DES_CBC_SHA 0x001e +#define OP_PCL_DTLS_DES_CBC_SHA_2 0x0009 +#define OP_PCL_DTLS_DES_CBC_SHA_3 0x000c +#define OP_PCL_DTLS_DES_CBC_SHA_4 0x000f +#define OP_PCL_DTLS_DES_CBC_SHA_5 0x0012 +#define OP_PCL_DTLS_DES_CBC_SHA_6 0x0015 +#define OP_PCL_DTLS_DES_CBC_SHA_7 0x001a + + +#define OP_PCL_DTLS_3DES_EDE_CBC_MD5 0xff23 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA160 0xff30 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA224 0xff34 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA256 0xff36 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA384 0xff33 +#define OP_PCL_DTLS_3DES_EDE_CBC_SHA512 0xff35 +#define OP_PCL_DTLS_AES_128_CBC_SHA160 0xff80 +#define OP_PCL_DTLS_AES_128_CBC_SHA224 0xff84 +#define OP_PCL_DTLS_AES_128_CBC_SHA256 0xff86 +#define OP_PCL_DTLS_AES_128_CBC_SHA384 0xff83 +#define OP_PCL_DTLS_AES_128_CBC_SHA512 0xff85 +#define OP_PCL_DTLS_AES_192_CBC_SHA160 0xff20 +#define OP_PCL_DTLS_AES_192_CBC_SHA224 0xff24 +#define OP_PCL_DTLS_AES_192_CBC_SHA256 0xff26 +#define OP_PCL_DTLS_AES_192_CBC_SHA384 0xff23 +#define OP_PCL_DTLS_AES_192_CBC_SHA512 0xff25 +#define OP_PCL_DTLS_AES_256_CBC_SHA160 0xff60 +#define OP_PCL_DTLS_AES_256_CBC_SHA224 0xff64 +#define OP_PCL_DTLS_AES_256_CBC_SHA256 0xff66 +#define OP_PCL_DTLS_AES_256_CBC_SHA384 0xff63 +#define OP_PCL_DTLS_AES_256_CBC_SHA512 0xff65 + +/* 802.16 WiMAX protinfos */ +#define OP_PCL_WIMAX_OFDM 0x0201 +#define OP_PCL_WIMAX_OFDMA 0x0231 + +/* 802.11 WiFi protinfos */ +#define OP_PCL_WIFI 0xac04 + +/* MacSec protinfos */ +#define OP_PCL_MACSEC 0x0001 + +/* PKI unidirectional protocol protinfo bits */ +#define OP_PCL_PKPROT_TEST 0x0008 +#define OP_PCL_PKPROT_DECRYPT 0x0004 +#define OP_PCL_PKPROT_ECC 0x0002 +#define OP_PCL_PKPROT_F2M 0x0001 + +/* Blob protocol protinfo bits */ +#define OP_PCL_BLOB_TK 0x0200 +#define OP_PCL_BLOB_EKT 0x0100 + +#define OP_PCL_BLOB_K2KR_MEM 0x0000 +#define OP_PCL_BLOB_K2KR_C1KR 0x0010 +#define OP_PCL_BLOB_K2KR_C2KR 0x0030 +#define OP_PCL_BLOB_K2KR_AFHAS 0x0050 +#define OP_PCL_BLOB_K2KR_C2KR_SPLIT 0x0070 + +#define OP_PCL_BLOB_PTXT_SECMEM 0x0008 +#define OP_PCL_BLOB_BLACK 0x0004 + +#define OP_PCL_BLOB_FMT_NORMAL 0x0000 +#define OP_PCL_BLOB_FMT_MSTR 0x0002 +#define OP_PCL_BLOB_FMT_TEST 0x0003 + +/* For non-protocol/alg-only op commands */ +#define OP_ALG_TYPE_SHIFT 24 +#define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT) +#define OP_ALG_TYPE_CLASS1 2 +#define OP_ALG_TYPE_CLASS2 4 + +#define OP_ALG_ALGSEL_SHIFT 16 +#define OP_ALG_ALGSEL_MASK (0xff << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SUBMASK (0x0f << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_AES (0x10 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_DES (0x20 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_3DES (0x21 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_ARC4 (0x30 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_MD5 (0x40 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA1 (0x41 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA224 (0x42 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA256 (0x43 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA384 (0x44 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SHA512 (0x45 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_RNG (0x50 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SNOW (0x60 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SNOW_F8 (0x60 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_KASUMI (0x70 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_CRC (0x90 << OP_ALG_ALGSEL_SHIFT) +#define OP_ALG_ALGSEL_SNOW_F9 (0xA0 << OP_ALG_ALGSEL_SHIFT) + +#define OP_ALG_AAI_SHIFT 4 +#define OP_ALG_AAI_MASK (0x1ff << OP_ALG_AAI_SHIFT) + +/* blockcipher AAI set */ +#define OP_ALG_AAI_CTR_MOD128 (0x00 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD8 (0x01 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD16 (0x02 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD24 (0x03 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD32 (0x04 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD40 (0x05 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD48 (0x06 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD56 (0x07 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD64 (0x08 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD72 (0x09 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD80 (0x0a << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD88 (0x0b << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD96 (0x0c << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD104 (0x0d << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD112 (0x0e << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_MOD120 (0x0f << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CBC (0x10 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_ECB (0x20 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CFB (0x30 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_OFB (0x40 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_XTS (0x50 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CMAC (0x60 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_XCBC_MAC (0x70 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CCM (0x80 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_GCM (0x90 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CBC_XCBCMAC (0xa0 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CTR_XCBCMAC (0xb0 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CHECKODD (0x80 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_DK (0x100 << OP_ALG_AAI_SHIFT) + +/* randomizer AAI set */ +#define OP_ALG_AAI_RNG (0x00 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG_NZB (0x10 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG_OBP (0x20 << OP_ALG_AAI_SHIFT) + +/* RNG4 AAI set */ +#define OP_ALG_AAI_RNG4_SH_0 (0x00 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG4_SH_1 (0x01 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG4_PS (0x40 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG4_AI (0x80 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_RNG4_SK (0x100 << OP_ALG_AAI_SHIFT) + +/* hmac/smac AAI set */ +#define OP_ALG_AAI_HASH (0x00 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_HMAC (0x01 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_SMAC (0x02 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_HMAC_PRECOMP (0x04 << OP_ALG_AAI_SHIFT) + +/* CRC AAI set*/ +#define OP_ALG_AAI_802 (0x01 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_3385 (0x02 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_CUST_POLY (0x04 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_DIS (0x10 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_DOS (0x20 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_DOC (0x40 << OP_ALG_AAI_SHIFT) + +/* Kasumi/SNOW AAI set */ +#define OP_ALG_AAI_F8 (0xc0 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_F9 (0xc8 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_GSM (0x10 << OP_ALG_AAI_SHIFT) +#define OP_ALG_AAI_EDGE (0x20 << OP_ALG_AAI_SHIFT) + +#define OP_ALG_AS_SHIFT 2 +#define OP_ALG_AS_MASK (0x3 << OP_ALG_AS_SHIFT) +#define OP_ALG_AS_UPDATE (0 << OP_ALG_AS_SHIFT) +#define OP_ALG_AS_INIT (1 << OP_ALG_AS_SHIFT) +#define OP_ALG_AS_FINALIZE (2 << OP_ALG_AS_SHIFT) +#define OP_ALG_AS_INITFINAL (3 << OP_ALG_AS_SHIFT) + +#define OP_ALG_ICV_SHIFT 1 +#define OP_ALG_ICV_MASK (1 << OP_ALG_ICV_SHIFT) +#define OP_ALG_ICV_OFF (0 << OP_ALG_ICV_SHIFT) +#define OP_ALG_ICV_ON (1 << OP_ALG_ICV_SHIFT) + +#define OP_ALG_DIR_SHIFT 0 +#define OP_ALG_DIR_MASK 1 +#define OP_ALG_DECRYPT 0 +#define OP_ALG_ENCRYPT 1 + +/* PKHA algorithm type set */ +#define OP_ALG_PK 0x00800000 +#define OP_ALG_PK_FUN_MASK 0x3f /* clrmem, modmath, or cpymem */ + +/* PKHA mode clear memory functions */ +#define OP_ALG_PKMODE_A_RAM 0x80000 +#define OP_ALG_PKMODE_B_RAM 0x40000 +#define OP_ALG_PKMODE_E_RAM 0x20000 +#define OP_ALG_PKMODE_N_RAM 0x10000 +#define OP_ALG_PKMODE_CLEARMEM 0x00001 + +/* PKHA mode modular-arithmetic functions */ +#define OP_ALG_PKMODE_MOD_IN_MONTY 0x80000 +#define OP_ALG_PKMODE_MOD_OUT_MONTY 0x40000 +#define OP_ALG_PKMODE_MOD_F2M 0x20000 +#define OP_ALG_PKMODE_MOD_R2_IN 0x10000 +#define OP_ALG_PKMODE_PRJECTV 0x00800 +#define OP_ALG_PKMODE_TIME_EQ 0x400 +#define OP_ALG_PKMODE_OUT_B 0x000 +#define OP_ALG_PKMODE_OUT_A 0x100 +#define OP_ALG_PKMODE_MOD_ADD 0x002 +#define OP_ALG_PKMODE_MOD_SUB_AB 0x003 +#define OP_ALG_PKMODE_MOD_SUB_BA 0x004 +#define OP_ALG_PKMODE_MOD_MULT 0x005 +#define OP_ALG_PKMODE_MOD_EXPO 0x006 +#define OP_ALG_PKMODE_MOD_REDUCT 0x007 +#define OP_ALG_PKMODE_MOD_INV 0x008 +#define OP_ALG_PKMODE_MOD_ECC_ADD 0x009 +#define OP_ALG_PKMODE_MOD_ECC_DBL 0x00a +#define OP_ALG_PKMODE_MOD_ECC_MULT 0x00b +#define OP_ALG_PKMODE_MOD_MONT_CNST 0x00c +#define OP_ALG_PKMODE_MOD_CRT_CNST 0x00d +#define OP_ALG_PKMODE_MOD_GCD 0x00e +#define OP_ALG_PKMODE_MOD_PRIMALITY 0x00f + +/* PKHA mode copy-memory functions */ +#define OP_ALG_PKMODE_SRC_REG_SHIFT 13 +#define OP_ALG_PKMODE_SRC_REG_MASK (7 << OP_ALG_PKMODE_SRC_REG_SHIFT) +#define OP_ALG_PKMODE_DST_REG_SHIFT 10 +#define OP_ALG_PKMODE_DST_REG_MASK (7 << OP_ALG_PKMODE_DST_REG_SHIFT) +#define OP_ALG_PKMODE_SRC_SEG_SHIFT 8 +#define OP_ALG_PKMODE_SRC_SEG_MASK (3 << OP_ALG_PKMODE_SRC_SEG_SHIFT) +#define OP_ALG_PKMODE_DST_SEG_SHIFT 6 +#define OP_ALG_PKMODE_DST_SEG_MASK (3 << OP_ALG_PKMODE_DST_SEG_SHIFT) + +#define OP_ALG_PKMODE_SRC_REG_A (0 << OP_ALG_PKMODE_SRC_REG_SHIFT) +#define OP_ALG_PKMODE_SRC_REG_B (1 << OP_ALG_PKMODE_SRC_REG_SHIFT) +#define OP_ALG_PKMODE_SRC_REG_N (3 << OP_ALG_PKMODE_SRC_REG_SHIFT) +#define OP_ALG_PKMODE_DST_REG_A (0 << OP_ALG_PKMODE_DST_REG_SHIFT) +#define OP_ALG_PKMODE_DST_REG_B (1 << OP_ALG_PKMODE_DST_REG_SHIFT) +#define OP_ALG_PKMODE_DST_REG_E (2 << OP_ALG_PKMODE_DST_REG_SHIFT) +#define OP_ALG_PKMODE_DST_REG_N (3 << OP_ALG_PKMODE_DST_REG_SHIFT) +#define OP_ALG_PKMODE_SRC_SEG_0 (0 << OP_ALG_PKMODE_SRC_SEG_SHIFT) +#define OP_ALG_PKMODE_SRC_SEG_1 (1 << OP_ALG_PKMODE_SRC_SEG_SHIFT) +#define OP_ALG_PKMODE_SRC_SEG_2 (2 << OP_ALG_PKMODE_SRC_SEG_SHIFT) +#define OP_ALG_PKMODE_SRC_SEG_3 (3 << OP_ALG_PKMODE_SRC_SEG_SHIFT) +#define OP_ALG_PKMODE_DST_SEG_0 (0 << OP_ALG_PKMODE_DST_SEG_SHIFT) +#define OP_ALG_PKMODE_DST_SEG_1 (1 << OP_ALG_PKMODE_DST_SEG_SHIFT) +#define OP_ALG_PKMODE_DST_SEG_2 (2 << OP_ALG_PKMODE_DST_SEG_SHIFT) +#define OP_ALG_PKMODE_DST_SEG_3 (3 << OP_ALG_PKMODE_DST_SEG_SHIFT) +#define OP_ALG_PKMODE_CPYMEM_N_SZ 0x80 +#define OP_ALG_PKMODE_CPYMEM_SRC_SZ 0x81 + +/* + * SEQ_IN_PTR Command Constructs + */ + +/* Release Buffers */ +#define SQIN_RBS 0x04000000 + +/* Sequence pointer is really a descriptor */ +#define SQIN_INL 0x02000000 + +/* Sequence pointer is a scatter-gather table */ +#define SQIN_SGF 0x01000000 + +/* Appends to a previous pointer */ +#define SQIN_PRE 0x00800000 + +/* Use extended length following pointer */ +#define SQIN_EXT 0x00400000 + +/* Restore sequence with pointer/length */ +#define SQIN_RTO 0x00200000 + +/* Replace job descriptor */ +#define SQIN_RJD 0x00100000 + +#define SQIN_LEN_SHIFT 0 +#define SQIN_LEN_MASK (0xffff << SQIN_LEN_SHIFT) + +/* + * SEQ_OUT_PTR Command Constructs + */ + +/* Sequence pointer is a scatter-gather table */ +#define SQOUT_SGF 0x01000000 + +/* Appends to a previous pointer */ +#define SQOUT_PRE SQIN_PRE + +/* Restore sequence with pointer/length */ +#define SQOUT_RTO SQIN_RTO + +/* Use extended length following pointer */ +#define SQOUT_EXT 0x00400000 + +#define SQOUT_LEN_SHIFT 0 +#define SQOUT_LEN_MASK (0xffff << SQOUT_LEN_SHIFT) + + +/* + * SIGNATURE Command Constructs + */ + +/* TYPE field is all that's relevant */ +#define SIGN_TYPE_SHIFT 16 +#define SIGN_TYPE_MASK (0x0f << SIGN_TYPE_SHIFT) + +#define SIGN_TYPE_FINAL (0x00 << SIGN_TYPE_SHIFT) +#define SIGN_TYPE_FINAL_RESTORE (0x01 << SIGN_TYPE_SHIFT) +#define SIGN_TYPE_FINAL_NONZERO (0x02 << SIGN_TYPE_SHIFT) +#define SIGN_TYPE_IMM_2 (0x0a << SIGN_TYPE_SHIFT) +#define SIGN_TYPE_IMM_3 (0x0b << SIGN_TYPE_SHIFT) +#define SIGN_TYPE_IMM_4 (0x0c << SIGN_TYPE_SHIFT) + +/* + * MOVE Command Constructs + */ + +#define MOVE_AUX_SHIFT 25 +#define MOVE_AUX_MASK (3 << MOVE_AUX_SHIFT) +#define MOVE_AUX_MS (2 << MOVE_AUX_SHIFT) +#define MOVE_AUX_LS (1 << MOVE_AUX_SHIFT) + +#define MOVE_WAITCOMP_SHIFT 24 +#define MOVE_WAITCOMP_MASK (1 << MOVE_WAITCOMP_SHIFT) +#define MOVE_WAITCOMP (1 << MOVE_WAITCOMP_SHIFT) + +#define MOVE_SRC_SHIFT 20 +#define MOVE_SRC_MASK (0x0f << MOVE_SRC_SHIFT) +#define MOVE_SRC_CLASS1CTX (0x00 << MOVE_SRC_SHIFT) +#define MOVE_SRC_CLASS2CTX (0x01 << MOVE_SRC_SHIFT) +#define MOVE_SRC_OUTFIFO (0x02 << MOVE_SRC_SHIFT) +#define MOVE_SRC_DESCBUF (0x03 << MOVE_SRC_SHIFT) +#define MOVE_SRC_MATH0 (0x04 << MOVE_SRC_SHIFT) +#define MOVE_SRC_MATH1 (0x05 << MOVE_SRC_SHIFT) +#define MOVE_SRC_MATH2 (0x06 << MOVE_SRC_SHIFT) +#define MOVE_SRC_MATH3 (0x07 << MOVE_SRC_SHIFT) +#define MOVE_SRC_INFIFO (0x08 << MOVE_SRC_SHIFT) +#define MOVE_SRC_INFIFO_CL (0x09 << MOVE_SRC_SHIFT) + +#define MOVE_DEST_SHIFT 16 +#define MOVE_DEST_MASK (0x0f << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS1CTX (0x00 << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS2CTX (0x01 << MOVE_DEST_SHIFT) +#define MOVE_DEST_OUTFIFO (0x02 << MOVE_DEST_SHIFT) +#define MOVE_DEST_DESCBUF (0x03 << MOVE_DEST_SHIFT) +#define MOVE_DEST_MATH0 (0x04 << MOVE_DEST_SHIFT) +#define MOVE_DEST_MATH1 (0x05 << MOVE_DEST_SHIFT) +#define MOVE_DEST_MATH2 (0x06 << MOVE_DEST_SHIFT) +#define MOVE_DEST_MATH3 (0x07 << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS1INFIFO (0x08 << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS2INFIFO (0x09 << MOVE_DEST_SHIFT) +#define MOVE_DEST_INFIFO_NOINFO (0x0a << MOVE_DEST_SHIFT) +#define MOVE_DEST_PK_A (0x0c << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS1KEY (0x0d << MOVE_DEST_SHIFT) +#define MOVE_DEST_CLASS2KEY (0x0e << MOVE_DEST_SHIFT) + +#define MOVE_OFFSET_SHIFT 8 +#define MOVE_OFFSET_MASK (0xff << MOVE_OFFSET_SHIFT) + +#define MOVE_LEN_SHIFT 0 +#define MOVE_LEN_MASK (0xff << MOVE_LEN_SHIFT) + +#define MOVELEN_MRSEL_SHIFT 0 +#define MOVELEN_MRSEL_MASK (0x3 << MOVE_LEN_SHIFT) + +/* + * MATH Command Constructs + */ + +#define MATH_IFB_SHIFT 26 +#define MATH_IFB_MASK (1 << MATH_IFB_SHIFT) +#define MATH_IFB (1 << MATH_IFB_SHIFT) + +#define MATH_NFU_SHIFT 25 +#define MATH_NFU_MASK (1 << MATH_NFU_SHIFT) +#define MATH_NFU (1 << MATH_NFU_SHIFT) + +#define MATH_STL_SHIFT 24 +#define MATH_STL_MASK (1 << MATH_STL_SHIFT) +#define MATH_STL (1 << MATH_STL_SHIFT) + +/* Function selectors */ +#define MATH_FUN_SHIFT 20 +#define MATH_FUN_MASK (0x0f << MATH_FUN_SHIFT) +#define MATH_FUN_ADD (0x00 << MATH_FUN_SHIFT) +#define MATH_FUN_ADDC (0x01 << MATH_FUN_SHIFT) +#define MATH_FUN_SUB (0x02 << MATH_FUN_SHIFT) +#define MATH_FUN_SUBB (0x03 << MATH_FUN_SHIFT) +#define MATH_FUN_OR (0x04 << MATH_FUN_SHIFT) +#define MATH_FUN_AND (0x05 << MATH_FUN_SHIFT) +#define MATH_FUN_XOR (0x06 << MATH_FUN_SHIFT) +#define MATH_FUN_LSHIFT (0x07 << MATH_FUN_SHIFT) +#define MATH_FUN_RSHIFT (0x08 << MATH_FUN_SHIFT) +#define MATH_FUN_SHLD (0x09 << MATH_FUN_SHIFT) +#define MATH_FUN_ZBYT (0x0a << MATH_FUN_SHIFT) + +/* Source 0 selectors */ +#define MATH_SRC0_SHIFT 16 +#define MATH_SRC0_MASK (0x0f << MATH_SRC0_SHIFT) +#define MATH_SRC0_REG0 (0x00 << MATH_SRC0_SHIFT) +#define MATH_SRC0_REG1 (0x01 << MATH_SRC0_SHIFT) +#define MATH_SRC0_REG2 (0x02 << MATH_SRC0_SHIFT) +#define MATH_SRC0_REG3 (0x03 << MATH_SRC0_SHIFT) +#define MATH_SRC0_IMM (0x04 << MATH_SRC0_SHIFT) +#define MATH_SRC0_DPOVRD (0x07 << MATH_SRC0_SHIFT) +#define MATH_SRC0_SEQINLEN (0x08 << MATH_SRC0_SHIFT) +#define MATH_SRC0_SEQOUTLEN (0x09 << MATH_SRC0_SHIFT) +#define MATH_SRC0_VARSEQINLEN (0x0a << MATH_SRC0_SHIFT) +#define MATH_SRC0_VARSEQOUTLEN (0x0b << MATH_SRC0_SHIFT) +#define MATH_SRC0_ZERO (0x0c << MATH_SRC0_SHIFT) + +/* Source 1 selectors */ +#define MATH_SRC1_SHIFT 12 +#define MATH_SRC1_MASK (0x0f << MATH_SRC1_SHIFT) +#define MATH_SRC1_REG0 (0x00 << MATH_SRC1_SHIFT) +#define MATH_SRC1_REG1 (0x01 << MATH_SRC1_SHIFT) +#define MATH_SRC1_REG2 (0x02 << MATH_SRC1_SHIFT) +#define MATH_SRC1_REG3 (0x03 << MATH_SRC1_SHIFT) +#define MATH_SRC1_IMM (0x04 << MATH_SRC1_SHIFT) +#define MATH_SRC1_DPOVRD (0x07 << MATH_SRC0_SHIFT) +#define MATH_SRC1_INFIFO (0x0a << MATH_SRC1_SHIFT) +#define MATH_SRC1_OUTFIFO (0x0b << MATH_SRC1_SHIFT) +#define MATH_SRC1_ONE (0x0c << MATH_SRC1_SHIFT) + +/* Destination selectors */ +#define MATH_DEST_SHIFT 8 +#define MATH_DEST_MASK (0x0f << MATH_DEST_SHIFT) +#define MATH_DEST_REG0 (0x00 << MATH_DEST_SHIFT) +#define MATH_DEST_REG1 (0x01 << MATH_DEST_SHIFT) +#define MATH_DEST_REG2 (0x02 << MATH_DEST_SHIFT) +#define MATH_DEST_REG3 (0x03 << MATH_DEST_SHIFT) +#define MATH_DEST_SEQINLEN (0x08 << MATH_DEST_SHIFT) +#define MATH_DEST_SEQOUTLEN (0x09 << MATH_DEST_SHIFT) +#define MATH_DEST_VARSEQINLEN (0x0a << MATH_DEST_SHIFT) +#define MATH_DEST_VARSEQOUTLEN (0x0b << MATH_DEST_SHIFT) +#define MATH_DEST_NONE (0x0f << MATH_DEST_SHIFT) + +/* Length selectors */ +#define MATH_LEN_SHIFT 0 +#define MATH_LEN_MASK (0x0f << MATH_LEN_SHIFT) +#define MATH_LEN_1BYTE 0x01 +#define MATH_LEN_2BYTE 0x02 +#define MATH_LEN_4BYTE 0x04 +#define MATH_LEN_8BYTE 0x08 + +/* + * JUMP Command Constructs + */ + +#define JUMP_CLASS_SHIFT 25 +#define JUMP_CLASS_MASK (3 << JUMP_CLASS_SHIFT) +#define JUMP_CLASS_NONE 0 +#define JUMP_CLASS_CLASS1 (1 << JUMP_CLASS_SHIFT) +#define JUMP_CLASS_CLASS2 (2 << JUMP_CLASS_SHIFT) +#define JUMP_CLASS_BOTH (3 << JUMP_CLASS_SHIFT) + +#define JUMP_JSL_SHIFT 24 +#define JUMP_JSL_MASK (1 << JUMP_JSL_SHIFT) +#define JUMP_JSL (1 << JUMP_JSL_SHIFT) + +#define JUMP_TYPE_SHIFT 22 +#define JUMP_TYPE_MASK (0x03 << JUMP_TYPE_SHIFT) +#define JUMP_TYPE_LOCAL (0x00 << JUMP_TYPE_SHIFT) +#define JUMP_TYPE_NONLOCAL (0x01 << JUMP_TYPE_SHIFT) +#define JUMP_TYPE_HALT (0x02 << JUMP_TYPE_SHIFT) +#define JUMP_TYPE_HALT_USER (0x03 << JUMP_TYPE_SHIFT) + +#define JUMP_TEST_SHIFT 16 +#define JUMP_TEST_MASK (0x03 << JUMP_TEST_SHIFT) +#define JUMP_TEST_ALL (0x00 << JUMP_TEST_SHIFT) +#define JUMP_TEST_INVALL (0x01 << JUMP_TEST_SHIFT) +#define JUMP_TEST_ANY (0x02 << JUMP_TEST_SHIFT) +#define JUMP_TEST_INVANY (0x03 << JUMP_TEST_SHIFT) + +/* Condition codes. JSL bit is factored in */ +#define JUMP_COND_SHIFT 8 +#define JUMP_COND_MASK (0x100ff << JUMP_COND_SHIFT) +#define JUMP_COND_PK_0 (0x80 << JUMP_COND_SHIFT) +#define JUMP_COND_PK_GCD_1 (0x40 << JUMP_COND_SHIFT) +#define JUMP_COND_PK_PRIME (0x20 << JUMP_COND_SHIFT) +#define JUMP_COND_MATH_N (0x08 << JUMP_COND_SHIFT) +#define JUMP_COND_MATH_Z (0x04 << JUMP_COND_SHIFT) +#define JUMP_COND_MATH_C (0x02 << JUMP_COND_SHIFT) +#define JUMP_COND_MATH_NV (0x01 << JUMP_COND_SHIFT) + +#define JUMP_COND_JRP ((0x80 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_SHRD ((0x40 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_SELF ((0x20 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_CALM ((0x10 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_NIP ((0x08 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_NIFP ((0x04 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_NOP ((0x02 << JUMP_COND_SHIFT) | JUMP_JSL) +#define JUMP_COND_NCP ((0x01 << JUMP_COND_SHIFT) | JUMP_JSL) + +#define JUMP_OFFSET_SHIFT 0 +#define JUMP_OFFSET_MASK (0xff << JUMP_OFFSET_SHIFT) + +/* + * NFIFO ENTRY + * Data Constructs + * + */ +#define NFIFOENTRY_DEST_SHIFT 30 +#define NFIFOENTRY_DEST_MASK (3 << NFIFOENTRY_DEST_SHIFT) +#define NFIFOENTRY_DEST_DECO (0 << NFIFOENTRY_DEST_SHIFT) +#define NFIFOENTRY_DEST_CLASS1 (1 << NFIFOENTRY_DEST_SHIFT) +#define NFIFOENTRY_DEST_CLASS2 (2 << NFIFOENTRY_DEST_SHIFT) +#define NFIFOENTRY_DEST_BOTH (3 << NFIFOENTRY_DEST_SHIFT) + +#define NFIFOENTRY_LC2_SHIFT 29 +#define NFIFOENTRY_LC2_MASK (1 << NFIFOENTRY_LC2_SHIFT) +#define NFIFOENTRY_LC2 (1 << NFIFOENTRY_LC2_SHIFT) + +#define NFIFOENTRY_LC1_SHIFT 28 +#define NFIFOENTRY_LC1_MASK (1 << NFIFOENTRY_LC1_SHIFT) +#define NFIFOENTRY_LC1 (1 << NFIFOENTRY_LC1_SHIFT) + +#define NFIFOENTRY_FC2_SHIFT 27 +#define NFIFOENTRY_FC2_MASK (1 << NFIFOENTRY_FC2_SHIFT) +#define NFIFOENTRY_FC2 (1 << NFIFOENTRY_FC2_SHIFT) + +#define NFIFOENTRY_FC1_SHIFT 26 +#define NFIFOENTRY_FC1_MASK (1 << NFIFOENTRY_FC1_SHIFT) +#define NFIFOENTRY_FC1 (1 << NFIFOENTRY_FC1_SHIFT) + +#define NFIFOENTRY_STYPE_SHIFT 24 +#define NFIFOENTRY_STYPE_MASK (3 << NFIFOENTRY_STYPE_SHIFT) +#define NFIFOENTRY_STYPE_DFIFO (0 << NFIFOENTRY_STYPE_SHIFT) +#define NFIFOENTRY_STYPE_OFIFO (1 << NFIFOENTRY_STYPE_SHIFT) +#define NFIFOENTRY_STYPE_PAD (2 << NFIFOENTRY_STYPE_SHIFT) +#define NFIFOENTRY_STYPE_SNOOP (3 << NFIFOENTRY_STYPE_SHIFT) + +#define NFIFOENTRY_DTYPE_SHIFT 20 +#define NFIFOENTRY_DTYPE_MASK (0xF << NFIFOENTRY_DTYPE_SHIFT) + +#define NFIFOENTRY_DTYPE_SBOX (0x0 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_AAD (0x1 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_IV (0x2 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_SAD (0x3 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_ICV (0xA << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_SKIP (0xE << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_MSG (0xF << NFIFOENTRY_DTYPE_SHIFT) + +#define NFIFOENTRY_DTYPE_PK_A0 (0x0 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_A1 (0x1 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_A2 (0x2 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_A3 (0x3 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_B0 (0x4 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_B1 (0x5 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_B2 (0x6 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_B3 (0x7 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_N (0x8 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_E (0x9 << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_A (0xC << NFIFOENTRY_DTYPE_SHIFT) +#define NFIFOENTRY_DTYPE_PK_B (0xD << NFIFOENTRY_DTYPE_SHIFT) + + +#define NFIFOENTRY_BND_SHIFT 19 +#define NFIFOENTRY_BND_MASK (1 << NFIFOENTRY_BND_SHIFT) +#define NFIFOENTRY_BND (1 << NFIFOENTRY_BND_SHIFT) + +#define NFIFOENTRY_PTYPE_SHIFT 16 +#define NFIFOENTRY_PTYPE_MASK (0x7 << NFIFOENTRY_PTYPE_SHIFT) + +#define NFIFOENTRY_PTYPE_ZEROS (0x0 << NFIFOENTRY_PTYPE_SHIFT) +#define NFIFOENTRY_PTYPE_RND_NOZEROS (0x1 << NFIFOENTRY_PTYPE_SHIFT) +#define NFIFOENTRY_PTYPE_INCREMENT (0x2 << NFIFOENTRY_PTYPE_SHIFT) +#define NFIFOENTRY_PTYPE_RND (0x3 << NFIFOENTRY_PTYPE_SHIFT) +#define NFIFOENTRY_PTYPE_ZEROS_NZ (0x4 << NFIFOENTRY_PTYPE_SHIFT) +#define NFIFOENTRY_PTYPE_RND_NZ_LZ (0x5 << NFIFOENTRY_PTYPE_SHIFT) +#define NFIFOENTRY_PTYPE_N (0x6 << NFIFOENTRY_PTYPE_SHIFT) +#define NFIFOENTRY_PTYPE_RND_NZ_N (0x7 << NFIFOENTRY_PTYPE_SHIFT) + +#define NFIFOENTRY_OC_SHIFT 15 +#define NFIFOENTRY_OC_MASK (1 << NFIFOENTRY_OC_SHIFT) +#define NFIFOENTRY_OC (1 << NFIFOENTRY_OC_SHIFT) + +#define NFIFOENTRY_AST_SHIFT 14 +#define NFIFOENTRY_AST_MASK (1 << NFIFOENTRY_OC_SHIFT) +#define NFIFOENTRY_AST (1 << NFIFOENTRY_OC_SHIFT) + +#define NFIFOENTRY_BM_SHIFT 11 +#define NFIFOENTRY_BM_MASK (1 << NFIFOENTRY_BM_SHIFT) +#define NFIFOENTRY_BM (1 << NFIFOENTRY_BM_SHIFT) + +#define NFIFOENTRY_PS_SHIFT 10 +#define NFIFOENTRY_PS_MASK (1 << NFIFOENTRY_PS_SHIFT) +#define NFIFOENTRY_PS (1 << NFIFOENTRY_PS_SHIFT) + +#define NFIFOENTRY_DLEN_SHIFT 0 +#define NFIFOENTRY_DLEN_MASK (0xFFF << NFIFOENTRY_DLEN_SHIFT) + +#define NFIFOENTRY_PLEN_SHIFT 0 +#define NFIFOENTRY_PLEN_MASK (0xFF << NFIFOENTRY_PLEN_SHIFT) + +/* Append Load Immediate Command */ +#define FD_CMD_APPEND_LOAD_IMMEDIATE 0x80000000 + +/* Set SEQ LIODN equal to the Non-SEQ LIODN for the job */ +#define FD_CMD_SET_SEQ_LIODN_EQUAL_NONSEQ_LIODN 0x40000000 + +/* Frame Descriptor Command for Replacement Job Descriptor */ +#define FD_CMD_REPLACE_JOB_DESC 0x20000000 + +#define ARC4_BLOCK_SIZE 1 +#define ARC4_MAX_KEY_SIZE 256 +#define ARC4_MIN_KEY_SIZE 1 + +#define XCBC_MAC_DIGEST_SIZE 16 +#define XCBC_MAC_BLOCK_WORDS 16 + + +#endif /* DESC_H */ diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h new file mode 100644 index 0000000000..9f79fd7bd4 --- /dev/null +++ b/drivers/crypto/caam/desc_constr.h @@ -0,0 +1,390 @@ +/* + * caam descriptor construction helper functions + * + * Copyright 2008-2012 Freescale Semiconductor, Inc. + */ + +#include "desc.h" + +#define IMMEDIATE (1 << 23) +#define CAAM_CMD_SZ sizeof(u32) +#define CAAM_PTR_SZ sizeof(dma_addr_t) +#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE) +#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3) + +#ifdef DEBUG +#define PRINT_POS do { printk(KERN_DEBUG "%02d: %s\n", desc_len(desc),\ + &__func__[sizeof("append")]); } while (0) +#else +#define PRINT_POS +#endif + +#define SET_OK_NO_PROP_ERRORS (IMMEDIATE | LDST_CLASS_DECO | \ + LDST_SRCDST_WORD_DECOCTRL | \ + (LDOFF_CHG_SHARE_OK_NO_PROP << \ + LDST_OFFSET_SHIFT)) +#define DISABLE_AUTO_INFO_FIFO (IMMEDIATE | LDST_CLASS_DECO | \ + LDST_SRCDST_WORD_DECOCTRL | \ + (LDOFF_DISABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT)) +#define ENABLE_AUTO_INFO_FIFO (IMMEDIATE | LDST_CLASS_DECO | \ + LDST_SRCDST_WORD_DECOCTRL | \ + (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT)) + +static inline int desc_len(u32 *desc) +{ + return *desc & HDR_DESCLEN_MASK; +} + +static inline int desc_bytes(void *desc) +{ + return desc_len(desc) * CAAM_CMD_SZ; +} + +static inline u32 *desc_end(u32 *desc) +{ + return desc + desc_len(desc); +} + +static inline void *sh_desc_pdb(u32 *desc) +{ + return desc + 1; +} + +static inline void init_desc(u32 *desc, u32 options) +{ + *desc = (options | HDR_ONE) + 1; +} + +static inline void init_sh_desc(u32 *desc, u32 options) +{ + PRINT_POS; + init_desc(desc, CMD_SHARED_DESC_HDR | options); +} + +static inline void init_sh_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes) +{ + u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ; + + init_sh_desc(desc, (((pdb_len + 1) << HDR_START_IDX_SHIFT) + pdb_len) | + options); +} + +static inline void init_job_desc(u32 *desc, u32 options) +{ + init_desc(desc, CMD_DESC_HDR | options); +} + +static inline void append_ptr(u32 *desc, dma_addr_t ptr) +{ + dma_addr_t *offset = (dma_addr_t *)desc_end(desc); + + *offset = ptr; + + (*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ; +} + +static inline void init_job_desc_shared(u32 *desc, dma_addr_t ptr, int len, + u32 options) +{ + PRINT_POS; + init_job_desc(desc, HDR_SHARED | options | + (len << HDR_START_IDX_SHIFT)); + append_ptr(desc, ptr); +} + +static inline void append_data(u32 *desc, void *data, int len) +{ + u32 *offset = desc_end(desc); + + if (len) /* avoid sparse warning: memcpy with byte count of 0 */ + memcpy(offset, data, len); + + (*desc) += (len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ; +} + +static inline void append_cmd(u32 *desc, u32 command) +{ + u32 *cmd = desc_end(desc); + + *cmd = command; + + (*desc)++; +} + +#define append_u32 append_cmd + +static inline void append_u64(u32 *desc, u64 data) +{ + u32 *offset = desc_end(desc); + + *offset = upper_32_bits(data); + *(++offset) = lower_32_bits(data); + + (*desc) += 2; +} + +/* Write command without affecting header, and return pointer to next word */ +static inline u32 *write_cmd(u32 *desc, u32 command) +{ + *desc = command; + + return desc + 1; +} + +static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len, + u32 command) +{ + append_cmd(desc, command | len); + append_ptr(desc, ptr); +} + +/* Write length after pointer, rather than inside command */ +static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr, + unsigned int len, u32 command) +{ + append_cmd(desc, command); + if (!(command & (SQIN_RTO | SQIN_PRE))) + append_ptr(desc, ptr); + append_cmd(desc, len); +} + +static inline void append_cmd_data(u32 *desc, void *data, int len, + u32 command) +{ + append_cmd(desc, command | IMMEDIATE | len); + append_data(desc, data, len); +} + +#define APPEND_CMD_RET(cmd, op) \ +static inline u32 *append_##cmd(u32 *desc, u32 options) \ +{ \ + u32 *cmd = desc_end(desc); \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | options); \ + return cmd; \ +} +APPEND_CMD_RET(jump, JUMP) +APPEND_CMD_RET(move, MOVE) + +static inline void set_jump_tgt_here(u32 *desc, u32 *jump_cmd) +{ + *jump_cmd = *jump_cmd | (desc_len(desc) - (jump_cmd - desc)); +} + +static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd) +{ + *move_cmd &= ~MOVE_OFFSET_MASK; + *move_cmd = *move_cmd | ((desc_len(desc) << (MOVE_OFFSET_SHIFT + 2)) & + MOVE_OFFSET_MASK); +} + +#define APPEND_CMD(cmd, op) \ +static inline void append_##cmd(u32 *desc, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | options); \ +} +APPEND_CMD(operation, OPERATION) + +#define APPEND_CMD_LEN(cmd, op) \ +static inline void append_##cmd(u32 *desc, unsigned int len, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | len | options); \ +} + +APPEND_CMD_LEN(seq_load, SEQ_LOAD) +APPEND_CMD_LEN(seq_store, SEQ_STORE) +APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD) +APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE) + +#define APPEND_CMD_PTR(cmd, op) \ +static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \ + u32 options) \ +{ \ + PRINT_POS; \ + append_cmd_ptr(desc, ptr, len, CMD_##op | options); \ +} +APPEND_CMD_PTR(key, KEY) +APPEND_CMD_PTR(load, LOAD) +APPEND_CMD_PTR(fifo_load, FIFO_LOAD) +APPEND_CMD_PTR(fifo_store, FIFO_STORE) + +static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len, + u32 options) +{ + u32 cmd_src; + + cmd_src = options & LDST_SRCDST_MASK; + + append_cmd(desc, CMD_STORE | options | len); + + /* The following options do not require pointer */ + if (!(cmd_src == LDST_SRCDST_WORD_DESCBUF_SHARED || + cmd_src == LDST_SRCDST_WORD_DESCBUF_JOB || + cmd_src == LDST_SRCDST_WORD_DESCBUF_JOB_WE || + cmd_src == LDST_SRCDST_WORD_DESCBUF_SHARED_WE)) + append_ptr(desc, ptr); +} + +#define APPEND_SEQ_PTR_INTLEN(cmd, op) \ +static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \ + unsigned int len, \ + u32 options) \ +{ \ + PRINT_POS; \ + if (options & (SQIN_RTO | SQIN_PRE)) \ + append_cmd(desc, CMD_SEQ_##op##_PTR | len | options); \ + else \ + append_cmd_ptr(desc, ptr, len, CMD_SEQ_##op##_PTR | options); \ +} +APPEND_SEQ_PTR_INTLEN(in, IN) +APPEND_SEQ_PTR_INTLEN(out, OUT) + +#define APPEND_CMD_PTR_TO_IMM(cmd, op) \ +static inline void append_##cmd##_as_imm(u32 *desc, void *data, \ + unsigned int len, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd_data(desc, data, len, CMD_##op | options); \ +} +APPEND_CMD_PTR_TO_IMM(load, LOAD); +APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD); + +#define APPEND_CMD_PTR_EXTLEN(cmd, op) \ +static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \ + unsigned int len, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd_ptr_extlen(desc, ptr, len, CMD_##op | SQIN_EXT | options); \ +} +APPEND_CMD_PTR_EXTLEN(seq_in_ptr, SEQ_IN_PTR) +APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR) + +/* + * Determine whether to store length internally or externally depending on + * the size of its type + */ +#define APPEND_CMD_PTR_LEN(cmd, op, type) \ +static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \ + type len, u32 options) \ +{ \ + PRINT_POS; \ + if (sizeof(type) > sizeof(u16)) \ + append_##cmd##_extlen(desc, ptr, len, options); \ + else \ + append_##cmd##_intlen(desc, ptr, len, options); \ +} +APPEND_CMD_PTR_LEN(seq_in_ptr, SEQ_IN_PTR, u32) +APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_PTR, u32) + +/* + * 2nd variant for commands whose specified immediate length differs + * from length of immediate data provided, e.g., split keys + */ +#define APPEND_CMD_PTR_TO_IMM2(cmd, op) \ +static inline void append_##cmd##_as_imm(u32 *desc, void *data, \ + unsigned int data_len, \ + unsigned int len, u32 options) \ +{ \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | IMMEDIATE | len | options); \ + append_data(desc, data, data_len); \ +} +APPEND_CMD_PTR_TO_IMM2(key, KEY); + +#define APPEND_CMD_RAW_IMM(cmd, op, type) \ +static inline void append_##cmd##_imm_##type(u32 *desc, type immediate, \ + u32 options) \ +{ \ + PRINT_POS; \ + append_cmd(desc, CMD_##op | IMMEDIATE | options | sizeof(type)); \ + append_cmd(desc, immediate); \ +} +APPEND_CMD_RAW_IMM(load, LOAD, u32); + +/* + * Append math command. Only the last part of destination and source need to + * be specified + */ +#define APPEND_MATH(op, desc, dest, src_0, src_1, len) \ +append_cmd(desc, CMD_MATH | MATH_FUN_##op | MATH_DEST_##dest | \ + MATH_SRC0_##src_0 | MATH_SRC1_##src_1 | (u32)len); + +#define append_math_add(desc, dest, src0, src1, len) \ + APPEND_MATH(ADD, desc, dest, src0, src1, len) +#define append_math_sub(desc, dest, src0, src1, len) \ + APPEND_MATH(SUB, desc, dest, src0, src1, len) +#define append_math_add_c(desc, dest, src0, src1, len) \ + APPEND_MATH(ADDC, desc, dest, src0, src1, len) +#define append_math_sub_b(desc, dest, src0, src1, len) \ + APPEND_MATH(SUBB, desc, dest, src0, src1, len) +#define append_math_and(desc, dest, src0, src1, len) \ + APPEND_MATH(AND, desc, dest, src0, src1, len) +#define append_math_or(desc, dest, src0, src1, len) \ + APPEND_MATH(OR, desc, dest, src0, src1, len) +#define append_math_xor(desc, dest, src0, src1, len) \ + APPEND_MATH(XOR, desc, dest, src0, src1, len) +#define append_math_lshift(desc, dest, src0, src1, len) \ + APPEND_MATH(LSHIFT, desc, dest, src0, src1, len) +#define append_math_rshift(desc, dest, src0, src1, len) \ + APPEND_MATH(RSHIFT, desc, dest, src0, src1, len) +#define append_math_ldshift(desc, dest, src0, src1, len) \ + APPEND_MATH(SHLD, desc, dest, src0, src1, len) + +/* Exactly one source is IMM. Data is passed in as u32 value */ +#define APPEND_MATH_IMM_u32(op, desc, dest, src_0, src_1, data) \ +do { \ + APPEND_MATH(op, desc, dest, src_0, src_1, CAAM_CMD_SZ); \ + append_cmd(desc, data); \ +} while (0) + +#define append_math_add_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(ADD, desc, dest, src0, src1, data) +#define append_math_sub_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(SUB, desc, dest, src0, src1, data) +#define append_math_add_c_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(ADDC, desc, dest, src0, src1, data) +#define append_math_sub_b_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(SUBB, desc, dest, src0, src1, data) +#define append_math_and_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(AND, desc, dest, src0, src1, data) +#define append_math_or_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(OR, desc, dest, src0, src1, data) +#define append_math_xor_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(XOR, desc, dest, src0, src1, data) +#define append_math_lshift_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(LSHIFT, desc, dest, src0, src1, data) +#define append_math_rshift_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(RSHIFT, desc, dest, src0, src1, data) + +/* Exactly one source is IMM. Data is passed in as u64 value */ +#define APPEND_MATH_IMM_u64(op, desc, dest, src_0, src_1, data) \ +do { \ + u32 upper = (data >> 16) >> 16; \ + APPEND_MATH(op, desc, dest, src_0, src_1, CAAM_CMD_SZ * 2 | \ + (upper ? 0 : MATH_IFB)); \ + if (upper) \ + append_u64(desc, data); \ + else \ + append_u32(desc, data); \ +} while (0) + +#define append_math_add_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(ADD, desc, dest, src0, src1, data) +#define append_math_sub_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(SUB, desc, dest, src0, src1, data) +#define append_math_add_c_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(ADDC, desc, dest, src0, src1, data) +#define append_math_sub_b_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(SUBB, desc, dest, src0, src1, data) +#define append_math_and_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(AND, desc, dest, src0, src1, data) +#define append_math_or_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(OR, desc, dest, src0, src1, data) +#define append_math_xor_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(XOR, desc, dest, src0, src1, data) +#define append_math_lshift_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(LSHIFT, desc, dest, src0, src1, data) +#define append_math_rshift_imm_u64(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u64(RSHIFT, desc, dest, src0, src1, data) diff --git a/drivers/crypto/caam/error.c b/drivers/crypto/caam/error.c new file mode 100644 index 0000000000..9c875375df --- /dev/null +++ b/drivers/crypto/caam/error.c @@ -0,0 +1,257 @@ +/* + * CAAM Error Reporting + * + * Copyright 2009-2011 Freescale Semiconductor, Inc. + */ + +#include <common.h> +#include "regs.h" +#include "error.h" + +static const struct { + u8 value; + const char *error_text; +} desc_error_list[] = { + { 0x00, "No error." }, + { 0x01, "SGT Length Error. The descriptor is trying to read more data than is contained in the SGT table." }, + { 0x02, "SGT Null Entry Error." }, + { 0x03, "Job Ring Control Error. There is a bad value in the Job Ring Control register." }, + { 0x04, "Invalid Descriptor Command. The Descriptor Command field is invalid." }, + { 0x05, "Reserved." }, + { 0x06, "Invalid KEY Command" }, + { 0x07, "Invalid LOAD Command" }, + { 0x08, "Invalid STORE Command" }, + { 0x09, "Invalid OPERATION Command" }, + { 0x0A, "Invalid FIFO LOAD Command" }, + { 0x0B, "Invalid FIFO STORE Command" }, + { 0x0C, "Invalid MOVE/MOVE_LEN Command" }, + { 0x0D, "Invalid JUMP Command. A nonlocal JUMP Command is invalid because the target is not a Job Header Command, or the jump is from a Trusted Descriptor to a Job Descriptor, or because the target Descriptor contains a Shared Descriptor." }, + { 0x0E, "Invalid MATH Command" }, + { 0x0F, "Invalid SIGNATURE Command" }, + { 0x10, "Invalid Sequence Command. A SEQ IN PTR OR SEQ OUT PTR Command is invalid or a SEQ KEY, SEQ LOAD, SEQ FIFO LOAD, or SEQ FIFO STORE decremented the input or output sequence length below 0. This error may result if a built-in PROTOCOL Command has encountered a malformed PDU." }, + { 0x11, "Skip data type invalid. The type must be 0xE or 0xF."}, + { 0x12, "Shared Descriptor Header Error" }, + { 0x13, "Header Error. Invalid length or parity, or certain other problems." }, + { 0x14, "Burster Error. Burster has gotten to an illegal state" }, + { 0x15, "Context Register Length Error. The descriptor is trying to read or write past the end of the Context Register. A SEQ LOAD or SEQ STORE with the VLF bit set was executed with too large a length in the variable length register (VSOL for SEQ STORE or VSIL for SEQ LOAD)." }, + { 0x16, "DMA Error" }, + { 0x17, "Reserved." }, + { 0x1A, "Job failed due to JR reset" }, + { 0x1B, "Job failed due to Fail Mode" }, + { 0x1C, "DECO Watchdog timer timeout error" }, + { 0x1D, "DECO tried to copy a key from another DECO but the other DECO's Key Registers were locked" }, + { 0x1E, "DECO attempted to copy data from a DECO that had an unmasked Descriptor error" }, + { 0x1F, "LIODN error. DECO was trying to share from itself or from another DECO but the two Non-SEQ LIODN values didn't match or the 'shared from' DECO's Descriptor required that the SEQ LIODNs be the same and they aren't." }, + { 0x20, "DECO has completed a reset initiated via the DRR register" }, + { 0x21, "Nonce error. When using EKT (CCM) key encryption option in the FIFO STORE Command, the Nonce counter reached its maximum value and this encryption mode can no longer be used." }, + { 0x22, "Meta data is too large (> 511 bytes) for TLS decap (input frame; block ciphers) and IPsec decap (output frame, when doing the next header byte update) and DCRC (output frame)." }, + { 0x23, "Read Input Frame error" }, + { 0x24, "JDKEK, TDKEK or TDSK not loaded error" }, + { 0x80, "DNR (do not run) error" }, + { 0x81, "undefined protocol command" }, + { 0x82, "invalid setting in PDB" }, + { 0x83, "Anti-replay LATE error" }, + { 0x84, "Anti-replay REPLAY error" }, + { 0x85, "Sequence number overflow" }, + { 0x86, "Sigver invalid signature" }, + { 0x87, "DSA Sign Illegal test descriptor" }, + { 0x88, "Protocol Format Error - A protocol has seen an error in the format of data received. When running RSA, this means that formatting with random padding was used, and did not follow the form: 0x00, 0x02, 8-to-N bytes of non-zero pad, 0x00, F data." }, + { 0x89, "Protocol Size Error - A protocol has seen an error in size. When running RSA, pdb size N < (size of F) when no formatting is used; or pdb size N < (F + 11) when formatting is used." }, + { 0xC1, "Blob Command error: Undefined mode" }, + { 0xC2, "Blob Command error: Secure Memory Blob mode error" }, + { 0xC4, "Blob Command error: Black Blob key or input size error" }, + { 0xC5, "Blob Command error: Invalid key destination" }, + { 0xC8, "Blob Command error: Trusted/Secure mode error" }, + { 0xF0, "IPsec TTL or hop limit field either came in as 0, or was decremented to 0" }, + { 0xF1, "3GPP HFN matches or exceeds the Threshold" }, +}; + +static const char * const cha_id_list[] = { + "", + "AES", + "DES", + "ARC4", + "MDHA", + "RNG", + "SNOW f8", + "Kasumi f8/9", + "PKHA", + "CRCA", + "SNOW f9", + "ZUCE", + "ZUCA", +}; + +static const char * const err_id_list[] = { + "No error.", + "Mode error.", + "Data size error.", + "Key size error.", + "PKHA A memory size error.", + "PKHA B memory size error.", + "Data arrived out of sequence error.", + "PKHA divide-by-zero error.", + "PKHA modulus even error.", + "DES key parity error.", + "ICV check failed.", + "Hardware error.", + "Unsupported CCM AAD size.", + "Class 1 CHA is not reset", + "Invalid CHA combination was selected", + "Invalid CHA selected.", +}; + +static const char * const rng_err_id_list[] = { + "", + "", + "", + "Instantiate", + "Not instantiated", + "Test instantiate", + "Prediction resistance", + "Prediction resistance and test request", + "Uninstantiate", + "Secure key generation", +}; + +static void report_invalid_status(struct device_d *jrdev, const u32 status, + const char *error) +{ + dev_err(jrdev, "%08x: %s: %s() not implemented\n", + status, error, __func__); +} + +static void report_ccb_status(struct device_d *jrdev, const u32 status, + const char *error) +{ + u8 cha_id = (status & JRSTA_CCBERR_CHAID_MASK) >> + JRSTA_CCBERR_CHAID_SHIFT; + u8 err_id = status & JRSTA_CCBERR_ERRID_MASK; + u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >> + JRSTA_DECOERR_INDEX_SHIFT; + char *idx_str; + const char *cha_str = "unidentified cha_id value 0x"; + char cha_err_code[3] = { 0 }; + const char *err_str = "unidentified err_id value 0x"; + char err_err_code[3] = { 0 }; + + if (status & JRSTA_DECOERR_JUMP) + idx_str = "jump tgt desc idx"; + else + idx_str = "desc idx"; + + if (cha_id < ARRAY_SIZE(cha_id_list)) + cha_str = cha_id_list[cha_id]; + else + snprintf(cha_err_code, sizeof(cha_err_code), "%02x", cha_id); + + if ((cha_id << JRSTA_CCBERR_CHAID_SHIFT) == JRSTA_CCBERR_CHAID_RNG && + err_id < ARRAY_SIZE(rng_err_id_list) && + strlen(rng_err_id_list[err_id])) { + /* RNG-only error */ + err_str = rng_err_id_list[err_id]; + } else if (err_id < ARRAY_SIZE(err_id_list)) + err_str = err_id_list[err_id]; + else + snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id); + + /* + * CCB ICV check failures are part of normal operation life; + * we leave the upper layers to do what they want with them. + */ + if (err_id != JRSTA_CCBERR_ERRID_ICVCHK) + dev_err(jrdev, "%08x: %s: %s %d: %s%s: %s%s\n", + status, error, idx_str, idx, + cha_str, cha_err_code, + err_str, err_err_code); +} + +static void report_jump_status(struct device_d *jrdev, const u32 status, + const char *error) +{ + dev_err(jrdev, "%08x: %s: %s() not implemented\n", + status, error, __func__); +} + +static void report_deco_status(struct device_d *jrdev, const u32 status, + const char *error) +{ + u8 err_id = status & JRSTA_DECOERR_ERROR_MASK; + u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >> + JRSTA_DECOERR_INDEX_SHIFT; + char *idx_str; + const char *err_str = "unidentified error value 0x"; + char err_err_code[3] = { 0 }; + int i; + + if (status & JRSTA_DECOERR_JUMP) + idx_str = "jump tgt desc idx"; + else + idx_str = "desc idx"; + + for (i = 0; i < ARRAY_SIZE(desc_error_list); i++) + if (desc_error_list[i].value == err_id) + break; + + if (i != ARRAY_SIZE(desc_error_list) && desc_error_list[i].error_text) + err_str = desc_error_list[i].error_text; + else + snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id); + + dev_err(jrdev, "%08x: %s: %s %d: %s%s\n", + status, error, idx_str, idx, err_str, err_err_code); +} + +static void report_jr_status(struct device_d *jrdev, const u32 status, + const char *error) +{ + dev_err(jrdev, "%08x: %s: %s() not implemented\n", + status, error, __func__); +} + +static void report_cond_code_status(struct device_d *jrdev, const u32 status, + const char *error) +{ + dev_err(jrdev, "%08x: %s: %s() not implemented\n", + status, error, __func__); +} + +void caam_jr_strstatus(struct device_d *jrdev, u32 status) +{ + static const struct stat_src { + void (*report_ssed)(struct device_d *jrdev, const u32 status, + const char *error); + const char *error; + } status_src[16] = { + { NULL, "No error" }, + { report_invalid_status, "invalid 0x0001" }, + { report_ccb_status, "CCB" }, + { report_jump_status, "Jump" }, + { report_deco_status, "DECO" }, + { NULL, "Queue Manager Interface" }, + { report_jr_status, "Job Ring" }, + { report_cond_code_status, "Condition Code" }, + { report_invalid_status, "invalid 0x1000" }, + { report_invalid_status, "invalid 0x1001" }, + { report_invalid_status, "invalid 0x1010" }, + { report_invalid_status, "invalid 0x1011" }, + { report_invalid_status, "invalid 0x1100" }, + { report_invalid_status, "invalid 0x1101" }, + { report_invalid_status, "invalid 0x1110" }, + { report_invalid_status, "invalid 0x1111" }, + }; + u32 ssrc = status >> JRSTA_SSRC_SHIFT; + const char *error = status_src[ssrc].error; + + /* + * If there is an error handling function, call it to report the error. + * Otherwise print the error source name. + */ + if (status_src[ssrc].report_ssed) + status_src[ssrc].report_ssed(jrdev, status, error); + else if (error) + dev_err(jrdev, "%d: %s\n", ssrc, error); + else + dev_err(jrdev, "%d: unknown error source\n", ssrc); +} +EXPORT_SYMBOL(caam_jr_strstatus); diff --git a/drivers/crypto/caam/error.h b/drivers/crypto/caam/error.h new file mode 100644 index 0000000000..4ea908977e --- /dev/null +++ b/drivers/crypto/caam/error.h @@ -0,0 +1,11 @@ +/* + * CAAM Error Reporting code header + * + * Copyright 2009-2011 Freescale Semiconductor, Inc. + */ + +#ifndef CAAM_ERROR_H +#define CAAM_ERROR_H +#define CAAM_ERROR_STR_MAX 302 +void caam_jr_strstatus(struct device_d *jrdev, u32 status); +#endif /* CAAM_ERROR_H */ diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h new file mode 100644 index 0000000000..fe19a2c8d2 --- /dev/null +++ b/drivers/crypto/caam/intern.h @@ -0,0 +1,97 @@ +/* + * CAAM/SEC 4.x driver backend + * Private/internal definitions between modules + * + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + */ + +#ifndef INTERN_H +#define INTERN_H + +/* Currently comes from Kconfig param as a ^2 (driver-required) */ +#define JOBR_DEPTH (1 << CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE) + +/* + * Storage for tracking each in-process entry moving across a ring + * Each entry on an output ring needs one of these + */ +struct caam_jrentry_info { + void (*callbk)(struct device_d *dev, u32 *desc, u32 status, void *arg); + void *cbkarg; /* Argument per ring entry */ + u32 *desc_addr_virt; /* Stored virt addr for postprocessing */ + dma_addr_t desc_addr_dma; /* Stored bus addr for done matching */ + u32 desc_size; /* Stored size for postprocessing, header derived */ +}; + +/* Private sub-storage for a single JobR */ +struct caam_drv_private_jr { + struct list_head list_node; /* Job Ring device list */ + struct device_d *dev; + int ridx; + struct caam_job_ring __iomem *rregs; /* JobR's register space */ + int irq; /* One per queue */ + + /* Number of scatterlist crypt transforms active on the JobR */ + int tfm_count; + + /* Job ring info */ + int ringsize; /* Size of rings (assume input = output) */ + struct caam_jrentry_info *entinfo; /* Alloc'ed 1 per ring entry */ + spinlock_t inplock; /* Input ring index lock */ + int inp_ring_write_index; /* Input index "tail" */ + int head; /* entinfo (s/w ring) head index */ + dma_addr_t *inpring; /* Base of input ring, alloc DMA-safe */ + spinlock_t outlock; /* Output ring index lock */ + int out_ring_read_index; /* Output index "tail" */ + int tail; /* entinfo (s/w ring) tail index */ + struct jr_outentry *outring; /* Base of output ring, DMA-safe */ +}; + +/* + * Driver-private storage for a single CAAM block instance + */ +struct caam_drv_private { + + struct device *dev; + struct device *smdev; + struct device_d **jrpdev; /* Alloc'ed array per sub-device */ + struct device_d *pdev; + + /* Physical-presence section */ + struct caam_ctrl __iomem *ctrl; /* controller region */ + struct caam_deco __iomem *deco; /* DECO/CCB views */ + struct caam_assurance __iomem *assure; + struct caam_queue_if __iomem *qi; /* QI control region */ + struct caam_job_ring __iomem *jr[4]; /* JobR's register space */ + struct snvs_full __iomem *snvs; /* SNVS HP+LP register space */ + dma_addr_t __iomem *sm_base; /* Secure memory storage base */ + u32 sm_size; + + /* + * Detected geometry block. Filled in from device tree if powerpc, + * or from register-based version detection code + */ + u8 total_jobrs; /* Total Job Rings in device */ + u8 qi_present; /* Nonzero if QI present in device */ + int secvio_irq; /* Security violation interrupt number */ + int virt_en; /* Virtualization enabled in CAAM */ + +#define RNG4_MAX_HANDLES 2 + /* RNG4 block */ + u32 rng4_sh_init; /* This bitmap shows which of the State + Handles of the RNG4 block are initialized + by this driver */ + + struct clk *caam_ipg; + struct clk *caam_mem; + struct clk *caam_aclk; + struct clk *caam_emi_slow; +}; + +void caam_jr_algapi_init(struct device *dev); +void caam_jr_algapi_remove(struct device *dev); + +int caam_rng_probe(struct device_d *dev, struct device_d *jrdev); +int caam_jr_probe(struct device_d *dev); +#endif /* INTERN_H */ diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c new file mode 100644 index 0000000000..8f169d4060 --- /dev/null +++ b/drivers/crypto/caam/jr.c @@ -0,0 +1,348 @@ +/* +* CAAM/SEC 4.x transport/backend driver +* JobR backend functionality + * + * Copyright 2008-2015 Freescale Semiconductor, Inc. + */ + +#include <common.h> +#include <clock.h> +#include <dma.h> +#include <driver.h> +#include <init.h> +#include <linux/barebox-wrapper.h> +#include <linux/spinlock.h> +#include <linux/circ_buf.h> +#include <linux/compiler.h> +#include <linux/err.h> + +#include "regs.h" +#include "jr.h" +#include "desc.h" +#include "intern.h" + +/* + * The DMA address registers in the JR are a pair of 32-bit registers. + * The layout is: + * + * base + 0x0000 : most-significant 32 bits + * base + 0x0004 : least-significant 32 bits + * + * The 32-bit version of this core therefore has to write to base + 0x0004 + * to set the 32-bit wide DMA address. This seems to be independent of the + * endianness of the written/read data. + */ + +#define REG64_MS32(reg) ((u32 __iomem *)(reg)) +#define REG64_LS32(reg) ((u32 __iomem *)(reg) + 1) + +static inline void wr_reg64(u64 __iomem *reg, u64 data) +{ + writel(data >> 32, REG64_MS32(reg)); + writel(data, REG64_LS32(reg)); +} + +static inline u64 rd_reg64(u64 __iomem *reg) +{ + return ((u64)readl(REG64_MS32(reg)) << 32 | + (u64)readl(REG64_LS32(reg))); +} + +static int caam_reset_hw_jr(struct device_d *dev) +{ + struct caam_drv_private_jr *jrp = dev->priv; + uint64_t start; + + /* initiate flush (required prior to reset) */ + writel(JRCR_RESET, &jrp->rregs->jrcommand); + + start = get_time_ns(); + while ((readl(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) == + JRINT_ERR_HALT_INPROGRESS) { + if (is_timeout(start, 100 * MSECOND)) { + dev_err(dev, "job ring %d timed out on flush\n", + jrp->ridx); + return -ETIMEDOUT; + } + } + + /* initiate reset */ + writel(JRCR_RESET, &jrp->rregs->jrcommand); + + start = get_time_ns(); + while (readl(&jrp->rregs->jrcommand) & JRCR_RESET) { + if (is_timeout(start, 100 * MSECOND)) { + dev_err(dev, "job ring %d timed out on reset\n", + jrp->ridx); + return -ETIMEDOUT; + } + } + + return 0; +} + +/* Deferred service handler, run as interrupt-fired tasklet */ +static int caam_jr_dequeue(struct caam_drv_private_jr *jrp) +{ + int hw_idx, sw_idx, i, head, tail; + void (*usercall)(struct device_d *dev, u32 *desc, u32 status, void *arg); + u32 *userdesc, userstatus; + void *userarg; + int found; + + while (readl(&jrp->rregs->outring_used)) { + head = jrp->head; + + sw_idx = tail = jrp->tail; + hw_idx = jrp->out_ring_read_index; + + found = 0; + + for (i = 0; CIRC_CNT(head, tail + i, JOBR_DEPTH) >= 1; i++) { + sw_idx = (tail + i) & (JOBR_DEPTH - 1); + + if (jrp->outring[hw_idx].desc == + jrp->entinfo[sw_idx].desc_addr_dma) { + found = 1; + break; /* found */ + } + } + + if (!found) + return -ENOENT; + + barrier(); + + /* mark completed, avoid matching on a recycled desc addr */ + jrp->entinfo[sw_idx].desc_addr_dma = 0; + + /* Stash callback params for use outside of lock */ + usercall = jrp->entinfo[sw_idx].callbk; + userarg = jrp->entinfo[sw_idx].cbkarg; + userdesc = jrp->entinfo[sw_idx].desc_addr_virt; + userstatus = jrp->outring[hw_idx].jrstatus; + + barrier(); + + /* set done */ + writel(1, &jrp->rregs->outring_rmvd); + + jrp->out_ring_read_index = (jrp->out_ring_read_index + 1) & + (JOBR_DEPTH - 1); + + /* + * if this job completed out-of-order, do not increment + * the tail. Otherwise, increment tail by 1 plus the + * number of subsequent jobs already completed out-of-order + */ + if (sw_idx == tail) { + do { + tail = (tail + 1) & (JOBR_DEPTH - 1); + } while (CIRC_CNT(head, tail, JOBR_DEPTH) >= 1 && + jrp->entinfo[tail].desc_addr_dma == 0); + + jrp->tail = tail; + } + + /* Finally, execute user's callback */ + usercall(jrp->dev, userdesc, userstatus, userarg); + } + + return 0; +} + +/* Main per-ring interrupt handler */ +static int caam_jr_interrupt(struct caam_drv_private_jr *jrp) +{ + uint64_t start; + u32 irqstate; + + start = get_time_ns(); + while (!(irqstate = readl(&jrp->rregs->jrintstatus))) { + if (is_timeout(start, 100 * MSECOND)) { + dev_err(jrp->dev, "timeout waiting for interrupt\n"); + return -ETIMEDOUT; + } + } + + /* + * If JobR error, we got more development work to do + * Flag a bug now, but we really need to shut down and + * restart the queue (and fix code). + */ + if (irqstate & JRINT_JR_ERROR) { + dev_err(jrp->dev, "job ring error: irqstate: %08x\n", irqstate); + BUG(); + } + + /* Have valid interrupt at this point, just ACK and trigger */ + writel(irqstate, &jrp->rregs->jrintstatus); + + return caam_jr_dequeue(jrp); +} + + +/** + * caam_jr_enqueue() - Enqueue a job descriptor head. Returns 0 if OK, + * -EBUSY if the queue is full, -EIO if it cannot map the caller's + * descriptor. + * @dev: device of the job ring to be used. + * @desc: points to a job descriptor that execute our request. All + * descriptors (and all referenced data) must be in a DMAable + * region, and all data references must be physical addresses + * accessible to CAAM (i.e. within a PAMU window granted + * to it). + * @cbk: pointer to a callback function to be invoked upon completion + * of this request. This has the form: + * callback(struct device *dev, u32 *desc, u32 stat, void *arg) + * where: + * @dev: contains the job ring device that processed this + * response. + * @desc: descriptor that initiated the request, same as + * "desc" being argued to caam_jr_enqueue(). + * @status: untranslated status received from CAAM. See the + * reference manual for a detailed description of + * error meaning, or see the JRSTA definitions in the + * register header file + * @areq: optional pointer to an argument passed with the + * original request + * @areq: optional pointer to a user argument for use at callback + * time. + **/ +int caam_jr_enqueue(struct device_d *dev, u32 *desc, + void (*cbk)(struct device_d *dev, u32 *desc, + u32 status, void *areq), + void *areq) +{ + struct caam_drv_private_jr *jrp; + struct caam_jrentry_info *head_entry; + int head, tail, desc_size; + + desc_size = (*desc & HDR_JD_LENGTH_MASK) * sizeof(u32); + + if (!dev->priv) + return -ENODEV; + + jrp = dev->priv; + + head = jrp->head; + tail = jrp->tail; + if (!readl(&jrp->rregs->inpring_avail) || + CIRC_SPACE(head, tail, JOBR_DEPTH) <= 0) { + return -EBUSY; + } + + head_entry = &jrp->entinfo[head]; + head_entry->desc_addr_virt = phys_to_virt((u32) desc); + head_entry->desc_size = desc_size; + head_entry->callbk = (void *)cbk; + head_entry->cbkarg = areq; + head_entry->desc_addr_dma = (dma_addr_t)desc; + + if (!jrp->inpring) + return -EIO; + + jrp->inpring[jrp->inp_ring_write_index] = (dma_addr_t)desc; + + barrier(); + + jrp->inp_ring_write_index = (jrp->inp_ring_write_index + 1) & + (JOBR_DEPTH - 1); + jrp->head = (head + 1) & (JOBR_DEPTH - 1); + + barrier(); + writel(1, &jrp->rregs->inpring_jobadd); + + clrbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK); + + return caam_jr_interrupt(jrp); +} +EXPORT_SYMBOL(caam_jr_enqueue); + +/* + * Init JobR independent of platform property detection + */ +static int caam_jr_init(struct device_d *dev) +{ + struct caam_drv_private_jr *jrp; + dma_addr_t dma_inpring; + dma_addr_t dma_outring; + int i, error; + + jrp = dev->priv; + + error = caam_reset_hw_jr(dev); + if (error) + return error; + + jrp->inpring = dma_alloc_coherent(sizeof(*jrp->inpring) * JOBR_DEPTH, + &dma_inpring); + if (!jrp->inpring) + return -ENOMEM; + + jrp->outring = dma_alloc_coherent(sizeof(*jrp->outring) * + JOBR_DEPTH, &dma_outring); + if (!jrp->outring) { + dma_free_coherent(jrp->inpring, 0, sizeof(dma_addr_t) * JOBR_DEPTH); + dev_err(dev, "can't allocate job rings for %d\n", jrp->ridx); + return -ENOMEM; + } + + jrp->entinfo = xzalloc(sizeof(*jrp->entinfo) * JOBR_DEPTH); + + for (i = 0; i < JOBR_DEPTH; i++) + jrp->entinfo[i].desc_addr_dma = !0; + + /* Setup rings */ + jrp->inp_ring_write_index = 0; + jrp->out_ring_read_index = 0; + jrp->head = 0; + jrp->tail = 0; + + wr_reg64(&jrp->rregs->inpring_base, dma_inpring); + wr_reg64(&jrp->rregs->outring_base, dma_outring); + writel(JOBR_DEPTH, &jrp->rregs->inpring_size); + writel(JOBR_DEPTH, &jrp->rregs->outring_size); + + jrp->ringsize = JOBR_DEPTH; + + return 0; +} + +/* + * Probe routine for each detected JobR subsystem. + */ +int caam_jr_probe(struct device_d *dev) +{ + struct device_node *nprop; + struct caam_job_ring __iomem *ctrl; + struct caam_drv_private_jr *jrpriv; + static int total_jobrs; + int error; + + jrpriv = xzalloc(sizeof(*jrpriv)); + + dev->priv = jrpriv; + jrpriv->dev = dev; + + /* save ring identity relative to detection */ + jrpriv->ridx = total_jobrs++; + + nprop = dev->device_node; + /* Get configuration properties from device tree */ + /* First, get register page */ + ctrl = dev_get_mem_region(dev, 0); + if (IS_ERR(ctrl)) + return PTR_ERR(ctrl); + + jrpriv->rregs = (struct caam_job_ring __force *)ctrl; + + /* Now do the platform independent part */ + error = caam_jr_init(dev); /* now turn on hardware */ + if (error) + return error; + + jrpriv->tfm_count = 0; + + return 0; +} diff --git a/drivers/crypto/caam/jr.h b/drivers/crypto/caam/jr.h new file mode 100644 index 0000000000..e0e53c0f6c --- /dev/null +++ b/drivers/crypto/caam/jr.h @@ -0,0 +1,18 @@ +/* + * CAAM public-level include definitions for the JobR backend + * + * Copyright 2008-2011 Freescale Semiconductor, Inc. + */ + +#ifndef JR_H +#define JR_H + +/* Prototypes for backend-level services exposed to APIs */ +struct device *caam_jr_alloc(void); +void caam_jr_free(struct device *rdev); +int caam_jr_enqueue(struct device_d *dev, u32 *desc, + void (*cbk)(struct device_d *dev, u32 *desc, u32 status, + void *areq), + void *areq); + +#endif /* JR_H */ diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h new file mode 100644 index 0000000000..b8ca5e396a --- /dev/null +++ b/drivers/crypto/caam/regs.h @@ -0,0 +1,895 @@ +/* + * CAAM hardware register-level view + * + * Copyright 2008-2015 Freescale Semiconductor, Inc. + */ + +#ifndef REGS_H +#define REGS_H + +#include <linux/types.h> +#include <io.h> + +/* These are common macros for Power, put here for ARMs */ +#define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr)) +#define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr)) + +/* + * jr_outentry + * Represents each entry in a JobR output ring + */ +struct jr_outentry { + dma_addr_t desc;/* Pointer to completed descriptor */ + u32 jrstatus; /* Status for completed descriptor */ +} __packed; + +/* + * CHA version ID / instantiation bitfields + * Defined for use within cha_id in perfmon + * Note that the same shift/mask selectors can be used to pull out number + * of instantiated blocks within cha_num in perfmon, the locations are + * the same. + */ + +/* Number of DECOs */ +#define CHA_NUM_MS_DECONUM_SHIFT 24 +#define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT) + +/* CHA Version IDs */ +#define CHA_ID_LS_AES_SHIFT 0 +#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT) + +#define CHA_ID_LS_DES_SHIFT 4 +#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT) + +#define CHA_ID_LS_ARC4_SHIFT 8 +#define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT) + +#define CHA_ID_LS_MD_SHIFT 12 +#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT) + +#define CHA_ID_LS_RNG_SHIFT 16 +#define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT) + +#define CHA_ID_LS_SNW8_SHIFT 20 +#define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT) + +#define CHA_ID_LS_KAS_SHIFT 24 +#define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT) + +#define CHA_ID_LS_PK_SHIFT 28 +#define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT) + +#define CHA_ID_MS_CRC_SHIFT 0 +#define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT) + +#define CHA_ID_MS_SNW9_SHIFT 4 +#define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT) + +#define CHA_ID_MS_DECO_SHIFT 24 +#define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT) + +#define CHA_ID_MS_JR_SHIFT 28 +#define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT) + +/* ZUC-Authentication */ +#define CHA_ID_MS_ZA_SHIFT 12 +#define CHA_ID_MS_ZA_MASK (0xfull << CHA_ID_MS_ZA_SHIFT) + +/* ZUC-Encryption */ +#define CHA_ID_MS_ZE_SHIFT 8 +#define CHA_ID_MS_ZE_MASK (0xfull << CHA_ID_MS_ZE_SHIFT) + +/* SNOW f9 */ +#define CHA_ID_MS_SNW9_SHIFT 4 +#define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT) + +/* CRC */ +#define CHA_ID_MS_CRC_SHIFT 0 +#define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT) + +/* Public Key */ +#define CHA_ID_LS_PK_SHIFT 28 +#define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT) + +/* Kasumi */ +#define CHA_ID_LS_KAS_SHIFT 24 +#define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT) + +/* SNOW f8 */ +#define CHA_ID_LS_SNW8_SHIFT 20 +#define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT) + +/* + * Random Generator + * RNG4 = FIPS-verification-compliant, requires init kickstart for use + */ +#define CHA_ID_LS_RNG_SHIFT 16 +#define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT) +#define CHA_ID_LS_RNG_A (0x1ull << CHA_ID_LS_RNG_SHIFT) +#define CHA_ID_LS_RNG_B (0x2ull << CHA_ID_LS_RNG_SHIFT) +#define CHA_ID_LS_RNG_C (0x3ull << CHA_ID_LS_RNG_SHIFT) +#define CHA_ID_LS_RNG_4 (0x4ull << CHA_ID_LS_RNG_SHIFT) + +/* + * Message Digest + * LP256 = Low Power (MD5/SHA1/SHA224/SHA256 + HMAC) + * LP512 = Low Power (LP256 + SHA384/SHA512) + * HP = High Power (LP512 + SMAC) + */ +#define CHA_ID_LS_MD_SHIFT 12 +#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT) +#define CHA_ID_LS_MD_LP256 (0x0ull << CHA_ID_LS_MD_SHIFT) +#define CHA_ID_LS_MD_LP512 (0x1ull << CHA_ID_LS_MD_SHIFT) +#define CHA_ID_LS_MD_HP (0x2ull << CHA_ID_LS_MD_SHIFT) + +/* ARC4 Streamcipher */ +#define CHA_ID_LS_ARC4_SHIFT 8 +#define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT) +#define CHA_ID_LS_ARC4_LP (0x0ull << CHA_ID_LS_ARC4_SHIFT) +#define CHA_ID_LS_ARC4_HP (0x1ull << CHA_ID_LS_ARC4_SHIFT) + +/* DES Blockcipher Accelerator */ +#define CHA_ID_LS_DES_SHIFT 4 +#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT) + +/* + * AES Blockcipher + Combo Mode Accelerator + * LP = Low Power (includes ECB/CBC/CFB128/OFB/CTR/CCM/CMAC/XCBC-MAC) + * HP = High Power (LP + CBCXCBC/CTRXCBC/XTS/GCM) + * DIFFPWR = ORed in if differential-power-analysis resistance implemented + */ +#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT) +#define CHA_ID_LS_AES_LP (0x3ull << CHA_ID_LS_AES_SHIFT) +#define CHA_ID_LS_AES_HP (0x4ull << CHA_ID_LS_AES_SHIFT) +#define CHA_ID_LS_AES_DIFFPWR (0x1ull << CHA_ID_LS_AES_SHIFT) + +/* + * caam_perfmon - Performance Monitor/Secure Memory Status/ + * CAAM Global Status/Component Version IDs + * + * Spans f00-fff wherever instantiated + */ + +struct sec_vid { + u16 ip_id; + u8 maj_rev; + u8 min_rev; +}; + +struct caam_perfmon { + /* Performance Monitor Registers f00-f9f */ + u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */ + u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */ + u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */ + u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */ + u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */ + u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */ + u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */ + u64 rsvd[13]; + + /* CAAM Hardware Instantiation Parameters fa0-fbf */ + u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/ + u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/ +#define CTPR_MS_QI_SHIFT 25 +#define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT) +#define CTPR_MS_VIRT_EN_INCL 0x00000001 +#define CTPR_MS_VIRT_EN_POR 0x00000002 +#define CTPR_MS_PG_SZ_MASK 0x10 +#define CTPR_MS_PG_SZ_SHIFT 4 + u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ + u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ + /* Secure Memory State Visibility */ + u32 rsvd1; + u32 smstatus; /* Secure memory status */ + u32 rsvd2; + u32 smpartown; /* Secure memory partition owner */ + + /* CAAM Global Status fc0-fdf */ + u64 faultaddr; /* FAR - Fault Address */ + u32 faultliodn; /* FALR - Fault Address LIODN */ + u32 faultdetail; /* FADR - Fault Addr Detail */ + u32 rsvd3; + u32 status; /* CSTA - CAAM Status */ + u32 smpart; /* Secure Memory Partition Parameters */ + u32 smvid; /* Secure Memory Version ID */ + + /* Component Instantiation Parameters fe0-fff */ + u32 rtic_id; /* RVID - RTIC Version ID */ + u32 ccb_id; /* CCBVID - CCB Version ID */ + u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/ + u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/ + u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */ + u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/ + u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */ + u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */ +}; + +#define SMSTATUS_PART_SHIFT 28 +#define SMSTATUS_PART_MASK (0xf << SMSTATUS_PART_SHIFT) +#define SMSTATUS_PAGE_SHIFT 16 +#define SMSTATUS_PAGE_MASK (0x7ff << SMSTATUS_PAGE_SHIFT) +#define SMSTATUS_MID_SHIFT 8 +#define SMSTATUS_MID_MASK (0x3f << SMSTATUS_MID_SHIFT) +#define SMSTATUS_ACCERR_SHIFT 4 +#define SMSTATUS_ACCERR_MASK (0xf << SMSTATUS_ACCERR_SHIFT) +#define SMSTATUS_ACCERR_NONE 0 +#define SMSTATUS_ACCERR_ALLOC 1 /* Page not allocated */ +#define SMSTATUS_ACCESS_ID 2 /* Not granted by ID */ +#define SMSTATUS_ACCESS_WRITE 3 /* Writes not allowed */ +#define SMSTATUS_ACCESS_READ 4 /* Reads not allowed */ +#define SMSTATUS_ACCESS_NONKEY 6 /* Non-key reads not allowed */ +#define SMSTATUS_ACCESS_BLOB 9 /* Blob access not allowed */ +#define SMSTATUS_ACCESS_DESCB 10 /* Descriptor Blob access spans pages */ +#define SMSTATUS_ACCESS_NON_SM 11 /* Outside Secure Memory range */ +#define SMSTATUS_ACCESS_XPAGE 12 /* Access crosses pages */ +#define SMSTATUS_ACCESS_INITPG 13 /* Page still initializing */ +#define SMSTATUS_STATE_SHIFT 0 +#define SMSTATUS_STATE_MASK (0xf << SMSTATUS_STATE_SHIFT) +#define SMSTATUS_STATE_RESET 0 +#define SMSTATUS_STATE_INIT 1 +#define SMSTATUS_STATE_NORMAL 2 +#define SMSTATUS_STATE_FAIL 3 + +/* up to 15 rings, 2 bits shifted by ring number */ +#define SMPARTOWN_RING_SHIFT 2 +#define SMPARTOWN_RING_MASK 3 +#define SMPARTOWN_AVAILABLE 0 +#define SMPARTOWN_NOEXIST 1 +#define SMPARTOWN_UNAVAILABLE 2 +#define SMPARTOWN_OURS 3 + +/* Maximum number of pages possible */ +#define SMPART_MAX_NUMPG_SHIFT 16 +#define SMPART_MAX_NUMPG_MASK (0x3f << SMPART_MAX_NUMPG_SHIFT) + +/* Maximum partition number */ +#define SMPART_MAX_PNUM_SHIFT 12 +#define SMPART_MAX_PNUM_MASK (0xf << SMPART_MAX_PNUM_SHIFT) + +/* Highest possible page number */ +#define SMPART_MAX_PG_SHIFT 0 +#define SMPART_MAX_PG_MASK (0x3f << SMPART_MAX_PG_SHIFT) + +/* Max size of a page */ +#define SMVID_PG_SIZE_SHIFT 16 +#define SMVID_PG_SIZE_MASK (0x7 << SMVID_PG_SIZE_SHIFT) + +/* Major/Minor Version ID */ +#define SMVID_MAJ_VERS_SHIFT 8 +#define SMVID_MAJ_VERS (0xf << SMVID_MAJ_VERS_SHIFT) +#define SMVID_MIN_VERS_SHIFT 0 +#define SMVID_MIN_VERS (0xf << SMVID_MIN_VERS_SHIFT) + +/* LIODN programming for DMA configuration */ +#define MSTRID_LOCK_LIODN 0x80000000 +#define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */ + +#define MSTRID_LIODN_MASK 0x0fff +struct masterid { + u32 liodn_ms; /* lock and make-trusted control bits */ + u32 liodn_ls; /* LIODN for non-sequence and seq access */ +}; + +/* Partition ID for DMA configuration */ +struct partid { + u32 rsvd1; + u32 pidr; /* partition ID, DECO */ +}; + +/* RNGB test mode (replicated twice in some configurations) */ +/* Padded out to 0x100 */ +struct rngtst { + u32 mode; /* RTSTMODEx - Test mode */ + u32 rsvd1[3]; + u32 reset; /* RTSTRESETx - Test reset control */ + u32 rsvd2[3]; + u32 status; /* RTSTSSTATUSx - Test status */ + u32 rsvd3; + u32 errstat; /* RTSTERRSTATx - Test error status */ + u32 rsvd4; + u32 errctl; /* RTSTERRCTLx - Test error control */ + u32 rsvd5; + u32 entropy; /* RTSTENTROPYx - Test entropy */ + u32 rsvd6[15]; + u32 verifctl; /* RTSTVERIFCTLx - Test verification control */ + u32 rsvd7; + u32 verifstat; /* RTSTVERIFSTATx - Test verification status */ + u32 rsvd8; + u32 verifdata; /* RTSTVERIFDx - Test verification data */ + u32 rsvd9; + u32 xkey; /* RTSTXKEYx - Test XKEY */ + u32 rsvd10; + u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */ + u32 rsvd11; + u32 oscct; /* RTSTOSCCTx - Test oscillator counter */ + u32 rsvd12; + u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */ + u32 rsvd13[2]; + u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */ + u32 rsvd14[15]; +}; + +/* RNG4 TRNG test registers */ +struct rng4tst { +#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ +#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in + both entropy shifter and + statistical checker */ +#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both + entropy shifter and + statistical checker */ +#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in + entropy shifter, raw data + in statistical checker */ +#define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */ + u32 rtmctl; /* misc. control register */ + u32 rtscmisc; /* statistical check misc. register */ + u32 rtpkrrng; /* poker range register */ + union { + u32 rtpkrmax; /* PRGM=1: poker max. limit register */ + u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ + }; +#define RTSDCTL_ENT_DLY_SHIFT 16 +#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) +#define RTSDCTL_ENT_DLY_MIN 3200 +#define RTSDCTL_ENT_DLY_MAX 12800 + u32 rtsdctl; /* seed control register */ + union { + u32 rtsblim; /* PRGM=1: sparse bit limit register */ + u32 rttotsam; /* PRGM=0: total samples register */ + }; + u32 rtfrqmin; /* frequency count min. limit register */ +#define RTFRQMAX_DISABLE (1 << 20) + union { + u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */ + u32 rtfrqcnt; /* PRGM=0: freq. count register */ + }; + u32 rsvd1[40]; +#define RDSTA_SKVT 0x80000000 +#define RDSTA_SKVN 0x40000000 +#define RDSTA_IF0 0x00000001 +#define RDSTA_IF1 0x00000002 +#define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0) + u32 rdsta; + u32 rsvd2[15]; +}; + +/* + * caam_ctrl - basic core configuration + * starts base + 0x0000 padded out to 0x1000 + */ + +#define KEK_KEY_SIZE 8 +#define TKEK_KEY_SIZE 8 +#define TDSK_KEY_SIZE 8 + +#define DECO_RESET 1 /* Use with DECO reset/availability regs */ +#define DECO_RESET_0 (DECO_RESET << 0) +#define DECO_RESET_1 (DECO_RESET << 1) +#define DECO_RESET_2 (DECO_RESET << 2) +#define DECO_RESET_3 (DECO_RESET << 3) +#define DECO_RESET_4 (DECO_RESET << 4) + +struct caam_ctrl { + /* Basic Configuration Section 000-01f */ + /* Read/Writable */ + u32 rsvd1; + u32 mcr; /* MCFG Master Config Register */ + u32 rsvd2; + u32 scfgr; /* SCFGR, Security Config Register */ + + /* Bus Access Configuration Section 010-11f */ + /* Read/Writable */ + struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */ + u32 rsvd3[11]; + u32 jrstart; /* JRSTART - Job Ring Start Register */ + struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */ + u32 rsvd4[5]; + u32 deco_rsr; /* DECORSR - Deco Request Source */ + u32 rsvd11; + u32 deco_rq; /* DECORR - DECO Request */ + struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */ + u32 rsvd5[22]; + + /* DECO Availability/Reset Section 120-3ff */ + u32 deco_avail; /* DAR - DECO availability */ + u32 deco_reset; /* DRR - DECO reset */ + u32 rsvd6[182]; + + /* Key Encryption/Decryption Configuration 400-5ff */ + /* Read/Writable only while in Non-secure mode */ + u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */ + u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */ + u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */ + u32 rsvd7[32]; + u64 sknonce; /* SKNR - Secure Key Nonce */ + u32 rsvd8[70]; + + /* RNG Test/Verification/Debug Access 600-7ff */ + /* (Useful in Test/Debug modes only...) */ + union { + struct rngtst rtst[2]; + struct rng4tst r4tst[2]; + }; + + u32 rsvd9[448]; + + /* Performance Monitor f00-fff */ + struct caam_perfmon perfmon; +}; + +/* + * Controller master config register defs + */ +#define MCFGR_SWRESET 0x80000000 /* software reset */ +#define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */ +#define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */ +#define MCFGR_DMA_RESET 0x10000000 +#define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */ +#define SCFGR_RDBENABLE 0x00000400 +#define SCFGR_VIRT_EN 0x00008000 +#define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */ +#define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */ +#define DECORSR_VALID 0x80000000 +#define DECORR_DEN0 0x00010000 /* DECO0 available for access*/ + +/* AXI read cache control */ +#define MCFGR_ARCACHE_SHIFT 12 +#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) +#define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT) +#define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT) +#define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT) + +/* AXI write cache control */ +#define MCFGR_AWCACHE_SHIFT 8 +#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) +#define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT) +#define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT) +#define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT) + +/* AXI pipeline depth */ +#define MCFGR_AXIPIPE_SHIFT 4 +#define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT) + +#define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */ +#define MCFGR_BURST_64 0x00000001 /* Max burst size */ + +/* JRSTART register offsets */ +#define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */ +#define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */ +#define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */ +#define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */ + +/* + * caam_job_ring - direct job ring setup + * 1-4 possible per instantiation, base + 1000/2000/3000/4000 + * Padded out to 0x1000 + */ +struct caam_job_ring { + /* Input ring */ + u64 inpring_base; /* IRBAx - Input desc ring baseaddr */ + u32 rsvd1; + u32 inpring_size; /* IRSx - Input ring size */ + u32 rsvd2; + u32 inpring_avail; /* IRSAx - Input ring room remaining */ + u32 rsvd3; + u32 inpring_jobadd; /* IRJAx - Input ring jobs added */ + + /* Output Ring */ + u64 outring_base; /* ORBAx - Output status ring base addr */ + u32 rsvd4; + u32 outring_size; /* ORSx - Output ring size */ + u32 rsvd5; + u32 outring_rmvd; /* ORJRx - Output ring jobs removed */ + u32 rsvd6; + u32 outring_used; /* ORSFx - Output ring slots full */ + + /* Status/Configuration */ + u32 rsvd7; + u32 jroutstatus; /* JRSTAx - JobR output status */ + u32 rsvd8; + u32 jrintstatus; /* JRINTx - JobR interrupt status */ + u32 rconfig_hi; /* JRxCFG - Ring configuration */ + u32 rconfig_lo; + + /* Indices. CAAM maintains as "heads" of each queue */ + u32 rsvd9; + u32 inp_rdidx; /* IRRIx - Input ring read index */ + u32 rsvd10; + u32 out_wtidx; /* ORWIx - Output ring write index */ + + /* Command/control */ + u32 rsvd11; + u32 jrcommand; /* JRCRx - JobR command */ + + u32 rsvd12[33]; + + /* Secure Memory Configuration - if you have it */ + u32 sm_cmd; /* SMCJRx - Secure memory command */ + u32 rsvd13; + u32 sm_status; /* SMCSJRx - Secure memory status */ + u32 rsvd14; + u32 sm_perm; /* SMAPJRx - Secure memory access perms */ + u32 sm_group2; /* SMAP2JRx - Secure memory access group 2 */ + u32 sm_group1; /* SMAP1JRx - Secure memory access group 1 */ + + u32 rsvd15[891]; + + /* Performance Monitor f00-fff */ + struct caam_perfmon perfmon; +}; + +#define JR_RINGSIZE_MASK 0x03ff +/* + * jrstatus - Job Ring Output Status + * All values in lo word + * Also note, same values written out as status through QI + * in the command/status field of a frame descriptor + */ +#define JRSTA_SSRC_SHIFT 28 +#define JRSTA_SSRC_MASK 0xf0000000 + +#define JRSTA_SSRC_NONE 0x00000000 +#define JRSTA_SSRC_CCB_ERROR 0x20000000 +#define JRSTA_SSRC_JUMP_HALT_USER 0x30000000 +#define JRSTA_SSRC_DECO 0x40000000 +#define JRSTA_SSRC_JRERROR 0x60000000 +#define JRSTA_SSRC_JUMP_HALT_CC 0x70000000 + +#define JRSTA_DECOERR_JUMP 0x08000000 +#define JRSTA_DECOERR_INDEX_SHIFT 8 +#define JRSTA_DECOERR_INDEX_MASK 0xff00 +#define JRSTA_DECOERR_ERROR_MASK 0x00ff + +#define JRSTA_DECOERR_NONE 0x00 +#define JRSTA_DECOERR_LINKLEN 0x01 +#define JRSTA_DECOERR_LINKPTR 0x02 +#define JRSTA_DECOERR_JRCTRL 0x03 +#define JRSTA_DECOERR_DESCCMD 0x04 +#define JRSTA_DECOERR_ORDER 0x05 +#define JRSTA_DECOERR_KEYCMD 0x06 +#define JRSTA_DECOERR_LOADCMD 0x07 +#define JRSTA_DECOERR_STORECMD 0x08 +#define JRSTA_DECOERR_OPCMD 0x09 +#define JRSTA_DECOERR_FIFOLDCMD 0x0a +#define JRSTA_DECOERR_FIFOSTCMD 0x0b +#define JRSTA_DECOERR_MOVECMD 0x0c +#define JRSTA_DECOERR_JUMPCMD 0x0d +#define JRSTA_DECOERR_MATHCMD 0x0e +#define JRSTA_DECOERR_SHASHCMD 0x0f +#define JRSTA_DECOERR_SEQCMD 0x10 +#define JRSTA_DECOERR_DECOINTERNAL 0x11 +#define JRSTA_DECOERR_SHDESCHDR 0x12 +#define JRSTA_DECOERR_HDRLEN 0x13 +#define JRSTA_DECOERR_BURSTER 0x14 +#define JRSTA_DECOERR_DESCSIGNATURE 0x15 +#define JRSTA_DECOERR_DMA 0x16 +#define JRSTA_DECOERR_BURSTFIFO 0x17 +#define JRSTA_DECOERR_JRRESET 0x1a +#define JRSTA_DECOERR_JOBFAIL 0x1b +#define JRSTA_DECOERR_DNRERR 0x80 +#define JRSTA_DECOERR_UNDEFPCL 0x81 +#define JRSTA_DECOERR_PDBERR 0x82 +#define JRSTA_DECOERR_ANRPLY_LATE 0x83 +#define JRSTA_DECOERR_ANRPLY_REPLAY 0x84 +#define JRSTA_DECOERR_SEQOVF 0x85 +#define JRSTA_DECOERR_INVSIGN 0x86 +#define JRSTA_DECOERR_DSASIGN 0x87 + +#define JRSTA_CCBERR_JUMP 0x08000000 +#define JRSTA_CCBERR_INDEX_MASK 0xff00 +#define JRSTA_CCBERR_INDEX_SHIFT 8 +#define JRSTA_CCBERR_CHAID_MASK 0x00f0 +#define JRSTA_CCBERR_CHAID_SHIFT 4 +#define JRSTA_CCBERR_ERRID_MASK 0x000f + +#define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT) +#define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT) + +#define JRSTA_CCBERR_ERRID_NONE 0x00 +#define JRSTA_CCBERR_ERRID_MODE 0x01 +#define JRSTA_CCBERR_ERRID_DATASIZ 0x02 +#define JRSTA_CCBERR_ERRID_KEYSIZ 0x03 +#define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04 +#define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05 +#define JRSTA_CCBERR_ERRID_SEQUENCE 0x06 +#define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07 +#define JRSTA_CCBERR_ERRID_PKMODEVN 0x08 +#define JRSTA_CCBERR_ERRID_KEYPARIT 0x09 +#define JRSTA_CCBERR_ERRID_ICVCHK 0x0a +#define JRSTA_CCBERR_ERRID_HARDWARE 0x0b +#define JRSTA_CCBERR_ERRID_CCMAAD 0x0c +#define JRSTA_CCBERR_ERRID_INVCHA 0x0f + +#define JRINT_ERR_INDEX_MASK 0x3fff0000 +#define JRINT_ERR_INDEX_SHIFT 16 +#define JRINT_ERR_TYPE_MASK 0xf00 +#define JRINT_ERR_TYPE_SHIFT 8 +#define JRINT_ERR_HALT_MASK 0xc +#define JRINT_ERR_HALT_SHIFT 2 +#define JRINT_ERR_HALT_INPROGRESS 0x4 +#define JRINT_ERR_HALT_COMPLETE 0x8 +#define JRINT_JR_ERROR 0x02 +#define JRINT_JR_INT 0x01 + +#define JRINT_ERR_TYPE_WRITE 1 +#define JRINT_ERR_TYPE_BAD_INPADDR 3 +#define JRINT_ERR_TYPE_BAD_OUTADDR 4 +#define JRINT_ERR_TYPE_INV_INPWRT 5 +#define JRINT_ERR_TYPE_INV_OUTWRT 6 +#define JRINT_ERR_TYPE_RESET 7 +#define JRINT_ERR_TYPE_REMOVE_OFL 8 +#define JRINT_ERR_TYPE_ADD_OFL 9 + +#define JRCFG_SOE 0x04 +#define JRCFG_ICEN 0x02 +#define JRCFG_IMSK 0x01 +#define JRCFG_ICDCT_SHIFT 8 +#define JRCFG_ICTT_SHIFT 16 + +#define JRCR_RESET 0x01 + +/* secure memory command */ +#define SMC_PAGE_SHIFT 16 +#define SMC_PAGE_MASK (0xffff << SMC_PAGE_SHIFT) +#define SMC_PART_SHIFT 8 +#define SMC_PART_MASK (0x0f << SMC_PART_SHIFT) +#define SMC_CMD_SHIFT 0 +#define SMC_CMD_MASK (0x0f << SMC_CMD_SHIFT) + +#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */ +#define SMC_CMD_DEALLOC_PAGE 0x02 /* deallocate page from partition */ +#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */ +#define SMC_CMD_PAGE_INQUIRY 0x05 /* find partition associate with page */ + +/* secure memory (command) status */ +#define SMCS_PAGE_SHIFT 16 +#define SMCS_PAGE_MASK (0x0fff << SMCS_PAGE_SHIFT) +#define SMCS_CMDERR_SHIFT 14 +#define SMCS_CMDERR_MASK (3 << SMCS_CMDERR_SHIFT) +#define SMCS_ALCERR_SHIFT 12 +#define SMCS_ALCERR_MASK (3 << SMCS_ALCERR_SHIFT) +#define SMCS_PGOWN_SHIFT 6 +#define SMCS_PGWON_MASK (3 << SMCS_PGOWN_SHIFT) +#define SMCS_PART_SHIFT 0 +#define SMCS_PART_MASK (0xf << SMCS_PART_SHIFT) + +#define SMCS_CMDERR_NONE 0 +#define SMCS_CMDERR_INCOMP 1 /* Command not yet complete */ +#define SMCS_CMDERR_SECFAIL 2 /* Security failure occurred */ +#define SMCS_CMDERR_OVERFLOW 3 /* Command overflow */ + +#define SMCS_ALCERR_NONE 0 +#define SMCS_ALCERR_PSPERR 1 /* Partion marked PSP (dealloc only) */ +#define SMCS_ALCERR_PAGEAVAIL 2 /* Page not available */ +#define SMCS_ALCERR_PARTOWN 3 /* Partition ownership error */ + +#define SMCS_PGOWN_AVAIL 0 /* Page is available */ +#define SMCS_PGOWN_NOEXIST 1 /* Page initializing or nonexistent */ +#define SMCS_PGOWN_NOOWN 2 /* Page owned by another processor */ +#define SMCS_PGOWN_OWNED 3 /* Page belongs to this processor */ + +/* secure memory access permissions */ +#define SMCS_PERM_KEYMOD_SHIFT 16 +#define SMCA_PERM_KEYMOD_MASK (0xff << SMCS_PERM_KEYMOD_SHIFT) +#define SMCA_PERM_CSP_ZERO 0x8000 /* Zero when deallocated or released */ +#define SMCA_PERM_PSP_LOCK 0x4000 /* Part./pages can't be deallocated */ +#define SMCA_PERM_PERM_LOCK 0x2000 /* Lock permissions */ +#define SMCA_PERM_GRP_LOCK 0x1000 /* Lock access groups */ +#define SMCA_PERM_RINGID_SHIFT 10 +#define SMCA_PERM_RINGID_MASK (3 << SMCA_PERM_RINGID_SHIFT) +#define SMCA_PERM_G2_BLOB 0x0080 /* Group 2 blob import/export */ +#define SMCA_PERM_G2_WRITE 0x0020 /* Group 2 write */ +#define SMCA_PERM_G2_READ 0x0010 /* Group 2 read */ +#define SMCA_PERM_G1_BLOB 0x0008 /* Group 1... */ +#define SMCA_PERM_G1_WRITE 0x0002 +#define SMCA_PERM_G1_READ 0x0001 + +/* + * caam_assurance - Assurance Controller View + * base + 0x6000 padded out to 0x1000 + */ + +struct rtic_element { + u64 address; + u32 rsvd; + u32 length; +}; + +struct rtic_block { + struct rtic_element element[2]; +}; + +struct rtic_memhash { + u32 memhash_be[32]; + u32 memhash_le[32]; +}; + +struct caam_assurance { + /* Status/Command/Watchdog */ + u32 rsvd1; + u32 status; /* RSTA - Status */ + u32 rsvd2; + u32 cmd; /* RCMD - Command */ + u32 rsvd3; + u32 ctrl; /* RCTL - Control */ + u32 rsvd4; + u32 throttle; /* RTHR - Throttle */ + u32 rsvd5[2]; + u64 watchdog; /* RWDOG - Watchdog Timer */ + u32 rsvd6; + u32 rend; /* REND - Endian corrections */ + u32 rsvd7[50]; + + /* Block access/configuration @ 100/110/120/130 */ + struct rtic_block memblk[4]; /* Memory Blocks A-D */ + u32 rsvd8[32]; + + /* Block hashes @ 200/300/400/500 */ + struct rtic_memhash hash[4]; /* Block hash values A-D */ + u32 rsvd_3[640]; +}; + +/* + * caam_queue_if - QI configuration and control + * starts base + 0x7000, padded out to 0x1000 long + */ + +struct caam_queue_if { + u32 qi_control_hi; /* QICTL - QI Control */ + u32 qi_control_lo; + u32 rsvd1; + u32 qi_status; /* QISTA - QI Status */ + u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */ + u32 qi_deq_cfg_lo; + u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */ + u32 qi_enq_cfg_lo; + u32 rsvd2[1016]; +}; + +/* QI control bits - low word */ +#define QICTL_DQEN 0x01 /* Enable frame pop */ +#define QICTL_STOP 0x02 /* Stop dequeue/enqueue */ +#define QICTL_SOE 0x04 /* Stop on error */ + +/* QI control bits - high word */ +#define QICTL_MBSI 0x01 +#define QICTL_MHWSI 0x02 +#define QICTL_MWSI 0x04 +#define QICTL_MDWSI 0x08 +#define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */ +#define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */ +#define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */ +#define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */ +#define QICTL_MBSO 0x0100 +#define QICTL_MHWSO 0x0200 +#define QICTL_MWSO 0x0400 +#define QICTL_MDWSO 0x0800 +#define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */ +#define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */ +#define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */ +#define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */ +#define QICTL_DMBS 0x010000 +#define QICTL_EPO 0x020000 + +/* QI status bits */ +#define QISTA_PHRDERR 0x01 /* PreHeader Read Error */ +#define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */ +#define QISTA_OFWRERR 0x04 /* Output Frame Read Error */ +#define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */ +#define QISTA_BTSERR 0x10 /* Buffer Undersize */ +#define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */ +#define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */ + +/* deco_sg_table - DECO view of scatter/gather table */ +struct deco_sg_table { + u64 addr; /* Segment Address */ + u32 elen; /* E, F bits + 30-bit length */ + u32 bpid_offset; /* Buffer Pool ID + 16-bit length */ +}; + +/* + * caam_deco - descriptor controller - CHA cluster block + * + * Only accessible when direct DECO access is turned on + * (done in DECORR, via MID programmed in DECOxMID + * + * 5 typical, base + 0x8000/9000/a000/b000 + * Padded out to 0x1000 long + */ +struct caam_deco { + u32 rsvd1; + u32 cls1_mode; /* CxC1MR - Class 1 Mode */ + u32 rsvd2; + u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */ + u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */ + u32 cls1_datasize_lo; + u32 rsvd3; + u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */ + u32 rsvd4[5]; + u32 cha_ctrl; /* CCTLR - CHA control */ + u32 rsvd5; + u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */ + u32 rsvd6; + u32 clr_written; /* CxCWR - Clear-Written */ + u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */ + u32 ccb_status_lo; + u32 rsvd7[3]; + u32 aad_size; /* CxAADSZR - Current AAD Size */ + u32 rsvd8; + u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */ + u32 rsvd9[7]; + u32 pkha_a_size; /* PKASZRx - Size of PKHA A */ + u32 rsvd10; + u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */ + u32 rsvd11; + u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */ + u32 rsvd12; + u32 pkha_e_size; /* PKESZRx - Size of PKHA E */ + u32 rsvd13[24]; + u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */ + u32 rsvd14[48]; + u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */ + u32 rsvd15[121]; + u32 cls2_mode; /* CxC2MR - Class 2 Mode */ + u32 rsvd16; + u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */ + u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */ + u32 cls2_datasize_lo; + u32 rsvd17; + u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */ + u32 rsvd18[56]; + u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */ + u32 rsvd19[46]; + u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */ + u32 rsvd20[84]; + u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */ + u32 inp_infofifo_lo; + u32 rsvd21[2]; + u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */ + u32 rsvd22[2]; + u64 out_datafifo; /* CxOFIFO - Output Data FIFO */ + u32 rsvd23[2]; + u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */ + u32 jr_ctl_lo; + u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */ +#define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF + u32 op_status_hi; /* DxOPSTA - DECO Operation Status */ + u32 op_status_lo; + u32 rsvd24[2]; + u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */ + u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */ + u32 rsvd26[6]; + u64 math[4]; /* DxMTH - Math register */ + u32 rsvd27[8]; + struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */ + u32 rsvd28[16]; + struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */ + u32 rsvd29[48]; + u32 descbuf[64]; /* DxDESB - Descriptor buffer */ + u32 rscvd30[193]; +#define DESC_DBG_DECO_STAT_HOST_ERR 0x00D00000 +#define DESC_DBG_DECO_STAT_VALID 0x80000000 +#define DESC_DBG_DECO_STAT_MASK 0x00F00000 + u32 desc_dbg; /* DxDDR - DECO Debug Register */ + u32 rsvd31[126]; +}; + +#define DECO_JQCR_WHL 0x20000000 +#define DECO_JQCR_FOUR 0x10000000 + +#define JR_BLOCK_NUMBER 1 +#define ASSURE_BLOCK_NUMBER 6 +#define QI_BLOCK_NUMBER 7 +#define DECO_BLOCK_NUMBER 8 +#define PG_SIZE_4K 0x1000 +#define PG_SIZE_64K 0x10000 +#endif /* REGS_H */ diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index bd0017b6c1..64f4326514 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -588,6 +588,7 @@ int mxs_dma_go(int chan) */ static int apbh_dma_probe(struct device_d *dev) { + struct resource *iores; struct apbh_dma *apbh; struct mxs_dma_chan *pchan; enum mxs_dma_id id; @@ -598,9 +599,10 @@ static int apbh_dma_probe(struct device_d *dev) return ret; apbh_dma = apbh = xzalloc(sizeof(*apbh)); - apbh->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(apbh->regs)) - return PTR_ERR(apbh->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + apbh->regs = IOMEM(iores->start); apbh->id = id; diff --git a/drivers/eeprom/at25.c b/drivers/eeprom/at25.c index 3e75b56519..9f054d00b4 100644 --- a/drivers/eeprom/at25.c +++ b/drivers/eeprom/at25.c @@ -356,6 +356,7 @@ static int at25_probe(struct device_d *dev) dev_dbg(dev, "%s probed\n", at25->cdev.name); devfs_create(&at25->cdev); + of_parse_partitions(&at25->cdev, dev->device_node); return 0; fail: diff --git a/drivers/firmware/socfpga.c b/drivers/firmware/socfpga.c index 159644bbfb..a0cd2011cb 100644 --- a/drivers/firmware/socfpga.c +++ b/drivers/firmware/socfpga.c @@ -395,6 +395,7 @@ static int programmed_get(struct param_d *p, void *priv) static int fpgamgr_probe(struct device_d *dev) { + struct resource *iores; struct fpgamgr *mgr; struct firmware_handler *fh; const char *alias = of_alias_get(dev->device_node); @@ -407,17 +408,19 @@ static int fpgamgr_probe(struct device_d *dev) mgr = xzalloc(sizeof(*mgr)); fh = &mgr->fh; - mgr->regs = dev_request_mem_region(dev, 0); - if (!mgr->regs) { - ret = -EBUSY; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto out; } + mgr->regs = IOMEM(iores->start); - mgr->regs_data = dev_request_mem_region(dev, 1); - if (!mgr->regs_data) { - ret = -EBUSY; + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto out; } + mgr->regs_data = IOMEM(iores->start); if (alias) fh->id = xstrdup(alias); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d839d7a426..ab919c95f5 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -87,17 +87,17 @@ config GPIO_PCA953X SMBus I/O expanders, made mostly by NXP or TI. Compatible models include: - 4 bits: pca9536, pca9537 + 4 bits: pca9536, pca9537 - 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554, - pca9556, pca9557, pca9574, tca6408, xra1202 + 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554, + pca9556, pca9557, pca9574, tca6408, xra1202 - 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575, - tca6416 + 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575, + tca6416 - 24 bits: tca6424 + 24 bits: tca6424 - 40 bits: pca9505, pca9698 + 40 bits: pca9505, pca9698 config GPIO_PL061 bool "PrimeCell PL061 GPIO support" diff --git a/drivers/gpio/gpio-ath79.c b/drivers/gpio/gpio-ath79.c index a1e42c417d..d08d743b54 100644 --- a/drivers/gpio/gpio-ath79.c +++ b/drivers/gpio/gpio-ath79.c @@ -107,6 +107,7 @@ static const struct of_device_id ath79_gpio_of_match[] = { static int ath79_gpio_probe(struct device_d *dev) { + struct resource *iores; struct device_node *np = dev->device_node; int err; @@ -125,11 +126,12 @@ static int ath79_gpio_probe(struct device_d *dev) return -EINVAL; } - ath79_gpio_base = dev_request_mem_region(dev, 0); - if (IS_ERR(ath79_gpio_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(ath79_gpio_base); + return PTR_ERR(iores); } + ath79_gpio_base = IOMEM(iores->start); ath79_gpio_chip.dev = dev; ath79_gpio_chip.ngpio = ath79_gpio_count; diff --git a/drivers/gpio/gpio-bcm2835.c b/drivers/gpio/gpio-bcm2835.c index cec15c98b1..1802ab7ccb 100644 --- a/drivers/gpio/gpio-bcm2835.c +++ b/drivers/gpio/gpio-bcm2835.c @@ -112,11 +112,15 @@ static struct gpio_ops bcm2835_gpio_ops = { static int bcm2835_gpio_probe(struct device_d *dev) { + struct resource *iores; struct bcm2835_gpio_chip *bcmgpio; int ret; bcmgpio = xzalloc(sizeof(*bcmgpio)); - bcmgpio->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + bcmgpio->base = IOMEM(iores->start); bcmgpio->chip.ops = &bcm2835_gpio_ops; bcmgpio->chip.base = 0; bcmgpio->chip.ngpio = 54; diff --git a/drivers/gpio/gpio-clps711x.c b/drivers/gpio/gpio-clps711x.c index 43268b6bbf..d71c606690 100644 --- a/drivers/gpio/gpio-clps711x.c +++ b/drivers/gpio/gpio-clps711x.c @@ -15,6 +15,7 @@ static int clps711x_gpio_probe(struct device_d *dev) { + struct resource *iores; int err, id = dev->id; void __iomem *dat, *dir = NULL, *dir_inv = NULL; struct bgpio_chip *bgc; @@ -25,20 +26,23 @@ static int clps711x_gpio_probe(struct device_d *dev) if (id < 0 || id > 4) return -ENODEV; - dat = dev_request_mem_region(dev, 0); - if (IS_ERR(dat)) - return PTR_ERR(dat); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + dat = IOMEM(iores->start); switch (id) { case 3: - dir_inv = dev_request_mem_region(dev, 1); - if (IS_ERR(dir_inv)) - return PTR_ERR(dir_inv); + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + dir_inv = IOMEM(iores->start); break; default: - dir = dev_request_mem_region(dev, 1); - if (IS_ERR(dir)) - return PTR_ERR(dir); + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + dir = IOMEM(iores->start); break; } diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index 61c6e7e68c..7c060a09b1 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -142,6 +142,7 @@ static struct gpio_ops davinci_gpio_ops = { static int davinci_gpio_probe(struct device_d *dev) { + struct resource *iores; void __iomem *gpio_base; int ret; u32 val; @@ -162,11 +163,12 @@ static int davinci_gpio_probe(struct device_d *dev) chips = xzalloc((ngpio / 32 + 1) * sizeof(*chips)); - gpio_base = dev_request_mem_region(dev, 0); - if (IS_ERR(gpio_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(gpio_base); + return PTR_ERR(iores); } + gpio_base = IOMEM(iores->start); for (i = 0, base = 0; base < ngpio; i++, base += 32) { struct davinci_gpio_regs __iomem *regs; diff --git a/drivers/gpio/gpio-digic.c b/drivers/gpio/gpio-digic.c index 468aaa79ab..714e3b4a1d 100644 --- a/drivers/gpio/gpio-digic.c +++ b/drivers/gpio/gpio-digic.c @@ -122,6 +122,7 @@ static struct gpio_ops digic_gpio_ops = { static int digic_gpio_probe(struct device_d *dev) { + struct resource *iores; struct digic_gpio_chip *chip; struct resource *res; resource_size_t rsize; @@ -136,7 +137,10 @@ static int digic_gpio_probe(struct device_d *dev) rsize = resource_size(res); chip->gc.ngpio = rsize / sizeof(int32_t); - chip->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + chip->base = IOMEM(iores->start); chip->gc.ops = &digic_gpio_ops; chip->gc.base = 0; diff --git a/drivers/gpio/gpio-dw.c b/drivers/gpio/gpio-dw.c index 258e43b84e..f145c01232 100644 --- a/drivers/gpio/gpio-dw.c +++ b/drivers/gpio/gpio-dw.c @@ -164,14 +164,16 @@ static int dw_gpio_add_port(struct device_d *dev, struct device_node *node, static int dw_gpio_probe(struct device_d *dev) { + struct resource *iores; struct dw_gpio *gpio; struct device_node *node; gpio = xzalloc(sizeof(*gpio)); - gpio->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(gpio->regs)) - return PTR_ERR(gpio->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + gpio->regs = IOMEM(iores->start); for_each_child_of_node(dev->device_node, node) dw_gpio_add_port(dev, node, gpio); diff --git a/drivers/gpio/gpio-imx.c b/drivers/gpio/gpio-imx.c index 6311db22fe..bfb0119c84 100644 --- a/drivers/gpio/gpio-imx.c +++ b/drivers/gpio/gpio-imx.c @@ -132,6 +132,7 @@ static struct gpio_ops imx_gpio_ops = { static int imx_gpio_probe(struct device_d *dev) { + struct resource *iores; struct imx_gpio_chip *imxgpio; struct imx_gpio_regs *regs; int ret; @@ -141,7 +142,10 @@ static int imx_gpio_probe(struct device_d *dev) return ret; imxgpio = xzalloc(sizeof(*imxgpio)); - imxgpio->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + imxgpio->base = IOMEM(iores->start); imxgpio->chip.ops = &imx_gpio_ops; if (dev->id < 0) { imxgpio->chip.base = of_alias_get_id(dev->device_node, "gpio"); diff --git a/drivers/gpio/gpio-jz4740.c b/drivers/gpio/gpio-jz4740.c index f7e6781dc1..87e0716b06 100644 --- a/drivers/gpio/gpio-jz4740.c +++ b/drivers/gpio/gpio-jz4740.c @@ -90,15 +90,17 @@ static struct gpio_ops jz4740_gpio_ops = { static int jz4740_gpio_probe(struct device_d *dev) { + struct resource *iores; void __iomem *base; struct jz4740_gpio_chip *jz4740_gpio; int ret; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(base); + return PTR_ERR(iores); } + base = IOMEM(iores->start); jz4740_gpio = xzalloc(sizeof(*jz4740_gpio)); jz4740_gpio->base = base; diff --git a/drivers/gpio/gpio-malta-fpga-i2c.c b/drivers/gpio/gpio-malta-fpga-i2c.c index ff77b8c7ef..0188e51af2 100644 --- a/drivers/gpio/gpio-malta-fpga-i2c.c +++ b/drivers/gpio/gpio-malta-fpga-i2c.c @@ -133,15 +133,17 @@ static struct gpio_ops malta_i2c_gpio_ops = { static int malta_i2c_gpio_probe(struct device_d *dev) { + struct resource *iores; void __iomem *gpio_base; struct malta_i2c_gpio *sc; int ret; - gpio_base = dev_request_mem_region(dev, 0); - if (IS_ERR(gpio_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(gpio_base); + return PTR_ERR(iores); } + gpio_base = IOMEM(iores->start); sc = xzalloc(sizeof(*sc)); sc->base = gpio_base; diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 43449df45b..b00766a6aa 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -141,15 +141,17 @@ static struct gpio_ops omap_gpio_ops = { static int omap_gpio_probe(struct device_d *dev) { + struct resource *iores; struct omap_gpio_chip *omapgpio; struct omap_gpio_drvdata *drvdata = NULL; dev_get_drvdata(dev, (const void **)&drvdata); omapgpio = xzalloc(sizeof(*omapgpio)); - omapgpio->base = dev_request_mem_region(dev, 0); - if (IS_ERR(omapgpio->base)) - return PTR_ERR(omapgpio->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + omapgpio->base = IOMEM(iores->start); if (drvdata) omapgpio->base += drvdata->regofs; diff --git a/drivers/gpio/gpio-orion.c b/drivers/gpio/gpio-orion.c index 3deeac126f..63ef966edf 100644 --- a/drivers/gpio/gpio-orion.c +++ b/drivers/gpio/gpio-orion.c @@ -89,6 +89,7 @@ static struct gpio_ops orion_gpio_ops = { static int orion_gpio_probe(struct device_d *dev) { + struct resource *iores; struct orion_gpio_chip *gpio; dev->id = of_alias_get_id(dev->device_node, "gpio"); @@ -96,11 +97,12 @@ static int orion_gpio_probe(struct device_d *dev) return dev->id; gpio = xzalloc(sizeof(*gpio)); - gpio->regs = dev_request_mem_region(dev, 0); - if (!gpio->regs) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { free(gpio); - return -EINVAL; + return PTR_ERR(iores); } + gpio->regs = IOMEM(iores->start); gpio->chip.dev = dev; gpio->chip.ops = &orion_gpio_ops; gpio->chip.base = dev->id * 32; diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c index e2cc3f4a8c..56808b57e4 100644 --- a/drivers/gpio/gpio-tegra.c +++ b/drivers/gpio/gpio-tegra.c @@ -140,6 +140,7 @@ static struct gpio_chip tegra_gpio_chip = { static int tegra_gpio_probe(struct device_d *dev) { + struct resource *iores; int i, j, ret; ret = dev_get_drvdata(dev, (const void **)&config); @@ -148,11 +149,12 @@ static int tegra_gpio_probe(struct device_d *dev) return ret; } - gpio_base = dev_request_mem_region(dev, 0); - if (IS_ERR(gpio_base)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return PTR_ERR(gpio_base); + return PTR_ERR(iores); } + gpio_base = IOMEM(iores->start); for (i = 0; i < config->bank_count; i++) { for (j = 0; j < 4; j++) { diff --git a/drivers/hab/habv3.c b/drivers/hab/habv3.c index 70f31a3c4d..82ae245f8a 100644 --- a/drivers/hab/habv3.c +++ b/drivers/hab/habv3.c @@ -20,35 +20,39 @@ struct hab_status { }; static struct hab_status hab_status[] = { - { 0x8d, "data specified is out of bounds" }, - { 0x55, "error during assert verification" }, - { 0x36, "hash verification failed" }, - { 0x33, "certificate parsing failed or the certificate contained an unsupported key" }, - { 0x35, "signature verification failed" }, - { 0x4B, "CSF command sequence contains unsupported command identifier" }, - { 0x4e, "absence of expected CSF header" }, - { 0x4d, "CSF length is unsupported" }, - { 0x2e, "CSF TYPE does not match processor TYPE" }, - { 0x2d, "CSF UID does not match either processor UID or generic UID" }, - { 0x3a, "CSF customer/product code does not match processor customer/product code" }, - { 0x87, "key indexis either unsupported, or an attempt is made to overwrite the SRK from a CSF command" }, + { 0x12, "Download code can't be executed, please check the HAB type" }, { 0x17, "SCC unexpectedly not in secure state" }, - { 0x1e, "secureRAM secret key invalid" }, - { 0x1d, "secureRAM initialization failure" }, { 0x1b, "secureRAM self test failure" }, - { 0x2b, "secureRAM internal failure" }, + { 0x1d, "secureRAM initialization failure" }, + { 0x1e, "secureRAM secret key invalid" }, { 0x27, "secureRAM secrect key unexpectedly in use" }, - { 0x8b, "an attempt is made to read a key from the list of subordinate public keys at a location " - "where no key is installed" }, - { 0x8e, "algorithm type is either invalid or ortherwise unsupported" }, - { 0x66, "write operation to register failed" }, + { 0x2b, "secureRAM internal failure" }, + { 0x2d, "CSF UID does not match either processor UID or generic UID" }, + { 0x2e, "CSF TYPE does not match processor TYPE" }, + { 0x33, "certificate parsing failed or the certificate contained an unsupported key" }, + { 0x35, "signature verification failed" }, + { 0x36, "hash verification failed" }, + { 0x39, "Failure not matching any other description" }, + { 0x3a, "CSF customer/product code does not match processor customer/product code" }, + { 0x47, "installation or comparison of SRKs failed" }, + { 0x4b, "CSF command sequence contains unsupported command identifier" }, + { 0x4d, "CSF length is unsupported" }, + { 0x4e, "absence of expected CSF header" }, + { 0x55, "error during assert verification" }, + { 0x56, "Download code can't be executed, please check the HAB type" }, { 0x63, "DCD invalid" }, - { 0x6f, "RAM application pointer is NULL or ERASED_FLASH" }, + { 0x66, "write operation to register failed" }, + { 0x67, "INT_BOOT fuse is blown but BOOT pins are set for external boot" }, { 0x69, "CSF missing when HAB TYPE is not HAB-disabled" }, { 0x6a, "NANDFC boot buffer load failed" }, { 0x6c, "Exception has occured" }, - { 0x67, "INT_BOOT fuse is blown but BOOT pins are set for external boot" }, + { 0x6f, "RAM application pointer is NULL or ERASED_FLASH" }, + { 0x87, "key indexis either unsupported, or an attempt is made to overwrite the SRK from a CSF command" }, { 0x88, "Successful download completion" }, + { 0x8b, "an attempt is made to read a key from the list of subordinate public keys at a location " + "where no key is installed" }, + { 0x8d, "data specified is out of bounds" }, + { 0x8e, "algorithm type is either invalid or ortherwise unsupported" }, }; int imx_habv3_get_status(uint32_t status) @@ -75,4 +79,4 @@ int imx_habv3_get_status(uint32_t status) int imx25_hab_get_status(void) { return imx_habv3_get_status(readl(IOMEM(0x780018d4))); -}
\ No newline at end of file +} diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c index 622c56d97b..76bb51bf30 100644 --- a/drivers/i2c/busses/i2c-at91.c +++ b/drivers/i2c/busses/i2c-at91.c @@ -410,6 +410,7 @@ static struct of_device_id at91_twi_dt_ids[] = { static int at91_twi_probe(struct device_d *dev) { + struct resource *iores; struct at91_twi_dev *i2c_at91; struct at91_twi_pdata *i2c_data; int rc = 0; @@ -425,10 +426,13 @@ static int at91_twi_probe(struct device_d *dev) i2c_at91->pdata = i2c_data; - i2c_at91->base = dev_request_mem_region(dev, 0); - if (!i2c_at91->base) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + i2c_at91->base = IOMEM(iores->start); + if (IS_ERR(i2c_at91->base)) { dev_err(dev, "could not get memory region\n"); - rc = -ENODEV; + rc = PTR_ERR(i2c_at91->base); goto out_free; } diff --git a/drivers/i2c/busses/i2c-designware.c b/drivers/i2c/busses/i2c-designware.c index a51439f2d5..0b022afd30 100644 --- a/drivers/i2c/busses/i2c-designware.c +++ b/drivers/i2c/busses/i2c-designware.c @@ -472,6 +472,7 @@ static int i2c_dw_xfer(struct i2c_adapter *adapter, static int i2c_dw_probe(struct device_d *pdev) { + struct resource *iores; struct dw_i2c_dev *dw; struct i2c_platform_data *pdata; int ret, bitrate; @@ -494,11 +495,12 @@ static int i2c_dw_probe(struct device_d *pdev) dw->adapter.dev.parent = pdev; dw->adapter.dev.device_node = pdev->device_node; - dw->base = dev_request_mem_region(pdev, 0); - if (IS_ERR(dw->base)) { - ret = PTR_ERR(dw->base); + iores = dev_request_mem_resource(pdev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto fail; } + dw->base = IOMEM(iores->start); ic_comp_type_value = readl(dw->base + DW_IC_COMP_TYPE); if (ic_comp_type_value != DW_IC_COMP_TYPE_VALUE) { diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index affc277164..e407896394 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c @@ -584,6 +584,7 @@ static void i2c_fsl_init_recovery(struct fsl_i2c_struct *i2c_fsl, struct device_ static int __init i2c_fsl_probe(struct device_d *pdev) { + struct resource *iores; struct fsl_i2c_struct *i2c_fsl; struct i2c_platform_data *pdata; int ret; @@ -604,11 +605,12 @@ static int __init i2c_fsl_probe(struct device_d *pdev) i2c_fsl->adapter.nr = pdev->id; i2c_fsl->adapter.dev.parent = pdev; i2c_fsl->adapter.dev.device_node = pdev->device_node; - i2c_fsl->base = dev_request_mem_region(pdev, 0); - if (IS_ERR(i2c_fsl->base)) { - ret = PTR_ERR(i2c_fsl->base); + iores = dev_request_mem_resource(pdev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto fail; } + i2c_fsl->base = IOMEM(iores->start); i2c_fsl_init_recovery(i2c_fsl, pdev); diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c index 0c38e64145..9b9e6c953f 100644 --- a/drivers/i2c/busses/i2c-mv64xxx.c +++ b/drivers/i2c/busses/i2c-mv64xxx.c @@ -595,6 +595,7 @@ out: static int mv64xxx_i2c_probe(struct device_d *pd) { + struct resource *iores; struct mv64xxx_i2c_data *drv_data; int rc; @@ -603,9 +604,10 @@ mv64xxx_i2c_probe(struct device_d *pd) drv_data = xzalloc(sizeof(*drv_data)); - drv_data->reg_base = dev_request_mem_region(pd, 0); - if (IS_ERR(drv_data->reg_base)) - return PTR_ERR(drv_data->reg_base); + iores = dev_request_mem_resource(pd, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + drv_data->reg_base = IOMEM(iores->start); drv_data->clk = clk_get(pd, NULL); if (IS_ERR(drv_data->clk)) diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 48c55daeda..bdb34ca1b4 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -1070,6 +1070,7 @@ static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = { static int __init i2c_omap_probe(struct device_d *pdev) { + struct resource *iores; struct omap_i2c_struct *i2c_omap; struct omap_i2c_driver_data *i2c_data; int r; @@ -1109,9 +1110,10 @@ i2c_omap_probe(struct device_d *pdev) speed = 100; /* Default speed */ i2c_omap->speed = speed; - i2c_omap->base = dev_request_mem_region(pdev, 0); - if (IS_ERR(i2c_omap->base)) - return PTR_ERR(i2c_omap->base); + iores = dev_request_mem_resource(pdev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + i2c_omap->base = IOMEM(iores->start); /* * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2. diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index f6a4b227f4..d56c0def65 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -605,16 +605,18 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { static int tegra_i2c_probe(struct device_d *dev) { + struct resource *iores; struct tegra_i2c_dev *i2c_dev; struct clk *div_clk, *fast_clk; void __iomem *base; int ret = 0; - base = dev_request_mem_region(dev, 0); - if (!base) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get iomem region\n"); - return -ENODEV; + return PTR_ERR(iores); } + base = IOMEM(iores->start); div_clk = clk_get(dev, "div-clk"); if (IS_ERR(div_clk)) { diff --git a/drivers/i2c/busses/i2c-versatile.c b/drivers/i2c/busses/i2c-versatile.c index bfabc78312..6a00c2a2eb 100644 --- a/drivers/i2c/busses/i2c-versatile.c +++ b/drivers/i2c/busses/i2c-versatile.c @@ -66,6 +66,7 @@ static struct i2c_algo_bit_data i2c_versatile_algo = { static int i2c_versatile_probe(struct device_d *dev) { + struct resource *iores; struct i2c_versatile *i2c; int ret; @@ -75,11 +76,12 @@ static int i2c_versatile_probe(struct device_d *dev) goto err_release; } - i2c->base = dev_request_mem_region(dev, 0); - if (IS_ERR(i2c->base)) { - ret = PTR_ERR(i2c->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto err_free; } + i2c->base = IOMEM(iores->start); writel(SCL | SDA, i2c->base + I2C_CONTROLS); diff --git a/drivers/input/imx_keypad.c b/drivers/input/imx_keypad.c index 000e17626b..44ff9b7856 100644 --- a/drivers/input/imx_keypad.c +++ b/drivers/input/imx_keypad.c @@ -364,6 +364,7 @@ static void imx_keypad_inhibit(struct imx_keypad *keypad) static int __init imx_keypad_probe(struct device_d *dev) { + struct resource *iores; struct imx_keypad *keypad; const struct matrix_keymap_data *keymap_data = dev->platform_data; int i, ret, row, col; @@ -371,9 +372,10 @@ static int __init imx_keypad_probe(struct device_d *dev) keypad = xzalloc(sizeof(struct imx_keypad)); keypad->dev = dev; - keypad->mmio_base = dev_request_mem_region(dev, 0); - if (IS_ERR(keypad->mmio_base)) - return PTR_ERR(keypad->mmio_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + keypad->mmio_base = IOMEM(iores->start); ret = matrix_keypad_build_keymap(dev, keymap_data, MATRIX_ROW_SHIFT, keypad->keycodes); diff --git a/drivers/input/usb_kbd.c b/drivers/input/usb_kbd.c index 74bc11f3bb..2acc95d9fd 100644 --- a/drivers/input/usb_kbd.c +++ b/drivers/input/usb_kbd.c @@ -46,13 +46,10 @@ struct usb_kbd_pdata; struct usb_kbd_pdata { - uint64_t last_report; uint8_t *new; uint8_t old[USB_KBD_BOOT_REPORT_SIZE]; - uint8_t flags; - struct poller_struct poller; + struct poller_async poller; struct usb_device *usbdev; - int lock; unsigned long intpipe; int intpktsize; int intinterval; @@ -94,23 +91,17 @@ static const unsigned char usb_kbd_keycode[256] = { 150,158,159,128,136,177,178,176,142,152,173,140 }; -static void usb_kbd_poll(struct poller_struct *poller) +static void usb_kbd_poll(void *arg) { - struct usb_kbd_pdata *data = container_of(poller, - struct usb_kbd_pdata, poller); + struct usb_kbd_pdata *data = arg; struct usb_device *usbdev = data->usbdev; int ret, i; - if (data->lock) - return; - - data->lock = 1; - ret = data->do_poll(data); if (ret == -EAGAIN) goto exit; if (ret < 0) { - /* exit and lock forever */ + /* exit with noreturn */ dev_err(&usbdev->dev, "usb_submit_int_msg() failed. Keyboard disconnect?\n"); return; @@ -125,7 +116,6 @@ static void usb_kbd_poll(struct poller_struct *poller) input_report_key_event(&data->input, usb_kbd_keycode[i + 224], (data->new[0] >> i) & 1); for (i = 2; i < 8; i++) { - if (data->old[i] > 3 && memscan(data->new + 2, data->old[i], 6) == data->new + 8) { if (usb_kbd_keycode[data->old[i]]) input_report_key_event(&data->input, usb_kbd_keycode[data->old[i]], 0); @@ -145,10 +135,10 @@ static void usb_kbd_poll(struct poller_struct *poller) } } - memcpy(data->old, data->new, 8); + memcpy(data->old, data->new, USB_KBD_BOOT_REPORT_SIZE); exit: - data->lock = 0; + poller_call_async(&data->poller, data->intinterval * MSECOND, usb_kbd_poll, data); } static int usb_kbd_probe(struct usb_device *usbdev, @@ -173,7 +163,6 @@ static int usb_kbd_probe(struct usb_device *usbdev, data->new = dma_alloc(USB_KBD_BOOT_REPORT_SIZE); data->usbdev = usbdev; - data->last_report = get_time_ns(); data->ep = &iface->ep_desc[0]; data->intpipe = usb_rcvintpipe(usbdev, data->ep->bEndpointAddress); @@ -199,18 +188,28 @@ static int usb_kbd_probe(struct usb_device *usbdev, } else dev_dbg(&usbdev->dev, "poll keyboard via int ep\n"); - input_device_register(&data->input); + ret = input_device_register(&data->input); + if (ret) { + dev_err(&usbdev->dev, "can't register input\n"); + return ret; + } + + ret = poller_async_register(&data->poller); + if (ret) { + dev_err(&usbdev->dev, "can't setup poller\n"); + return ret; + } - data->poller.func = usb_kbd_poll; + poller_call_async(&data->poller, data->intinterval * MSECOND, usb_kbd_poll, data); - return poller_register(&data->poller); + return 0; } static void usb_kbd_disconnect(struct usb_device *usbdev) { struct usb_kbd_pdata *data = usbdev->drv_data; - poller_unregister(&data->poller); + poller_async_unregister(&data->poller); input_device_unregister(&data->input); dma_free(data->new); free(data); diff --git a/drivers/mci/atmel_mci.c b/drivers/mci/atmel_mci.c index 10e769ea13..2a0ddb052b 100644 --- a/drivers/mci/atmel_mci.c +++ b/drivers/mci/atmel_mci.c @@ -533,6 +533,7 @@ static void atmci_get_cap(struct atmel_mci *host) static int atmci_probe(struct device_d *hw_dev) { + struct resource *iores; struct atmel_mci *host; struct atmel_mci_platform_data *pd = hw_dev->platform_data; int ret; @@ -572,9 +573,10 @@ static int atmci_probe(struct device_d *hw_dev) host->mci.host_caps |= MMC_CAP_8_BIT_DATA; host->slot_b = pd->slot_b; - host->regs = dev_request_mem_region(hw_dev, 0); - if (IS_ERR(host->regs)) - return PTR_ERR(host->regs); + iores = dev_request_mem_resource(hw_dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->regs = IOMEM(iores->start); host->hw_dev = hw_dev; hw_dev->priv = host; host->clk = clk_get(hw_dev, "mci_clk"); diff --git a/drivers/mci/dw_mmc.c b/drivers/mci/dw_mmc.c index cbd3f00646..0e004abe31 100644 --- a/drivers/mci/dw_mmc.c +++ b/drivers/mci/dw_mmc.c @@ -675,6 +675,7 @@ static int dw_mmc_detect(struct device_d *dev) static int dw_mmc_probe(struct device_d *dev) { + struct resource *iores; struct dwmci_host *host; struct dw_mmc_platform_data *pdata = dev->platform_data; @@ -692,9 +693,10 @@ static int dw_mmc_probe(struct device_d *dev) clk_enable(host->clk_ciu); host->dev = dev; - host->ioaddr = dev_request_mem_region(dev, 0); - if (IS_ERR(host->ioaddr)) - return PTR_ERR(host->ioaddr); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->ioaddr = IOMEM(iores->start); host->idmac = dma_alloc_coherent(sizeof(*host->idmac) * DW_MMC_NUM_IDMACS, DMA_ADDRESS_BROKEN); diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c index 6caf165616..282887ba78 100644 --- a/drivers/mci/imx-esdhc.c +++ b/drivers/mci/imx-esdhc.c @@ -545,6 +545,7 @@ static int fsl_esdhc_detect(struct device_d *dev) static int fsl_esdhc_probe(struct device_d *dev) { + struct resource *iores; struct fsl_esdhc_host *host; struct mci_host *mci; u32 caps; @@ -560,9 +561,10 @@ static int fsl_esdhc_probe(struct device_d *dev) return PTR_ERR(host->clk); host->dev = dev; - host->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(host->regs)) - return PTR_ERR(host->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->regs = IOMEM(iores->start); /* First reset the eSDHC controller */ ret = esdhc_reset(host); diff --git a/drivers/mci/imx.c b/drivers/mci/imx.c index 9c8c1b1e27..2788fb9d9d 100644 --- a/drivers/mci/imx.c +++ b/drivers/mci/imx.c @@ -492,6 +492,7 @@ static int mxcmci_init(struct mci_host *mci, struct device_d *dev) static int mxcmci_probe(struct device_d *dev) { + struct resource *iores; struct mxcmci_host *host; unsigned long rate; @@ -507,9 +508,10 @@ static int mxcmci_probe(struct device_d *dev) host->mci.host_caps = MMC_CAP_4_BIT_DATA; host->mci.hw_dev = dev; - host->base = dev_request_mem_region(dev, 0); - if (IS_ERR(host->base)) - return PTR_ERR(host->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->base = IOMEM(iores->start); host->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; diff --git a/drivers/mci/mci-bcm2835.c b/drivers/mci/mci-bcm2835.c index 59c667f5c9..c7a8cf972a 100644 --- a/drivers/mci/mci-bcm2835.c +++ b/drivers/mci/mci-bcm2835.c @@ -480,6 +480,7 @@ static int bcm2835_mci_detect(struct device_d *dev) static int bcm2835_mci_probe(struct device_d *hw_dev) { + struct resource *iores; struct bcm2835_mci_host *host; static struct clk *clk; int ret; @@ -505,11 +506,12 @@ static int bcm2835_mci_probe(struct device_d *hw_dev) host->mci.hw_dev = hw_dev; host->hw_dev = hw_dev; host->max_clock = clk_get_rate(clk); - host->regs = dev_request_mem_region(hw_dev, 0); - if (IS_ERR(host->regs)) { + iores = dev_request_mem_resource(hw_dev, 0); + if (IS_ERR(iores)) { dev_err(host->hw_dev, "Failed request mem region, aborting...\n"); - return PTR_ERR(host->regs); + return PTR_ERR(iores); } + host->regs = IOMEM(iores->start); host->mci.host_caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; diff --git a/drivers/mci/mxs.c b/drivers/mci/mxs.c index b36fb13254..2355651022 100644 --- a/drivers/mci/mxs.c +++ b/drivers/mci/mxs.c @@ -544,6 +544,7 @@ static void mxs_mci_info(struct device_d *hw_dev) static int mxs_mci_probe(struct device_d *hw_dev) { + struct resource *iores; struct mxs_mci_platform_data *pd = hw_dev->platform_data; struct mxs_mci_host *mxs_mci; struct mci_host *host; @@ -557,9 +558,10 @@ static int mxs_mci_probe(struct device_d *hw_dev) host->send_cmd = mxs_mci_request; host->set_ios = mxs_mci_set_ios; host->init = mxs_mci_initialize; - mxs_mci->regs = dev_request_mem_region(hw_dev, 0); - if (IS_ERR(mxs_mci->regs)) - return PTR_ERR(mxs_mci->regs); + iores = dev_request_mem_resource(hw_dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mxs_mci->regs = IOMEM(iores->start); /* feed forward the platform specific values */ if (pd) { diff --git a/drivers/mci/omap_hsmmc.c b/drivers/mci/omap_hsmmc.c index 752787aa43..180afb16c9 100644 --- a/drivers/mci/omap_hsmmc.c +++ b/drivers/mci/omap_hsmmc.c @@ -584,6 +584,7 @@ static int omap_mmc_detect(struct device_d *dev) static int omap_mmc_probe(struct device_d *dev) { + struct resource *iores; struct omap_hsmmc *hsmmc; struct omap_hsmmc_platform_data *pdata; struct omap_mmc_driver_data *drvdata; @@ -604,9 +605,10 @@ static int omap_mmc_probe(struct device_d *dev) MMC_CAP_MMC_HIGHSPEED | MMC_CAP_8_BIT_DATA; hsmmc->mci.hw_dev = dev; - hsmmc->iobase = dev_request_mem_region(dev, 0); - if (IS_ERR(hsmmc->iobase)) - return PTR_ERR(hsmmc->iobase); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + hsmmc->iobase = IOMEM(iores->start); hsmmc->base = hsmmc->iobase + reg_ofs; hsmmc->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; diff --git a/drivers/mci/pxamci.c b/drivers/mci/pxamci.c index 6b14aba509..1a33661d0f 100644 --- a/drivers/mci/pxamci.c +++ b/drivers/mci/pxamci.c @@ -334,14 +334,16 @@ static int pxamci_init(struct mci_host *mci, struct device_d *dev) static int pxamci_probe(struct device_d *dev) { + struct resource *iores; struct pxamci_host *host; int gpio_power = -1; clk_enable(); host = xzalloc(sizeof(*host)); - host->base = dev_request_mem_region(dev, 0); - if (IS_ERR(host->base)) - return PTR_ERR(host->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->base = IOMEM(iores->start); host->mci.init = pxamci_init; host->mci.send_cmd = pxamci_request; diff --git a/drivers/mci/s3c.c b/drivers/mci/s3c.c index 3afd61e491..86a83b63fa 100644 --- a/drivers/mci/s3c.c +++ b/drivers/mci/s3c.c @@ -723,6 +723,7 @@ static void s3c_info(struct device_d *hw_dev) static int s3c_mci_probe(struct device_d *hw_dev) { + struct resource *iores; struct s3c_mci_host *s3c_host; struct s3c_mci_platform_data *pd = hw_dev->platform_data; @@ -741,9 +742,10 @@ static int s3c_mci_probe(struct device_d *hw_dev) } hw_dev->priv = s3c_host; - s3c_host->base = dev_request_mem_region(hw_dev, 0); - if (IS_ERR(s3c_host->base)) - return PTR_ERR(s3c_host->base); + iores = dev_request_mem_resource(hw_dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + s3c_host->base = IOMEM(iores->start); s3c_host->host.hw_dev = hw_dev; diff --git a/drivers/mci/tegra-sdmmc.c b/drivers/mci/tegra-sdmmc.c index 14c230483f..e465d891a2 100644 --- a/drivers/mci/tegra-sdmmc.c +++ b/drivers/mci/tegra-sdmmc.c @@ -422,6 +422,7 @@ static void tegra_sdmmc_parse_dt(struct tegra_sdmmc_host *host) static int tegra_sdmmc_probe(struct device_d *dev) { + struct resource *iores; struct tegra_sdmmc_host *host; struct mci_host *mci; int ret; @@ -437,11 +438,12 @@ static int tegra_sdmmc_probe(struct device_d *dev) if (IS_ERR(host->reset)) return PTR_ERR(host->reset); - host->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(host->regs)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get iomem region\n"); - return PTR_ERR(host->regs); + return PTR_ERR(iores); } + host->regs = IOMEM(iores->start); mci->hw_dev = dev; mci->f_max = 48000000; diff --git a/drivers/misc/sram.c b/drivers/misc/sram.c index 9769325338..58b574157a 100644 --- a/drivers/misc/sram.c +++ b/drivers/misc/sram.c @@ -34,14 +34,16 @@ static struct file_operations memops = { static int sram_probe(struct device_d *dev) { + struct resource *iores; struct sram *sram; struct resource *res; void __iomem *base; int ret; - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); sram = xzalloc(sizeof(*sram)); diff --git a/drivers/mtd/core.c b/drivers/mtd/core.c index 62307db709..161c6ad874 100644 --- a/drivers/mtd/core.c +++ b/drivers/mtd/core.c @@ -67,14 +67,13 @@ int mtd_all_ff(const void *buf, unsigned int len) } static ssize_t mtd_op_read(struct cdev *cdev, void* buf, size_t count, - loff_t _offset, ulong flags) + loff_t offset, ulong flags) { struct mtd_info *mtd = cdev->priv; size_t retlen; int ret; - unsigned long offset = _offset; - dev_dbg(cdev->dev, "read ofs: 0x%08lx count: 0x%08zx\n", + dev_dbg(cdev->dev, "read ofs: 0x%08llx count: 0x%08zx\n", offset, count); ret = mtd_read(mtd, offset, count, &retlen, buf); @@ -115,13 +114,13 @@ static struct mtd_erase_region_info *mtd_find_erase_region(struct mtd_info *mtd, return NULL; } -static int mtd_erase_align(struct mtd_info *mtd, size_t *count, loff_t *offset) +static int mtd_erase_align(struct mtd_info *mtd, loff_t *count, loff_t *offset) { struct mtd_erase_region_info *e; loff_t ofs; if (mtd->numeraseregions == 0) { - ofs = *offset & ~(mtd->erasesize - 1); + ofs = *offset & ~(loff_t)(mtd->erasesize - 1); *count += (*offset - ofs); *count = ALIGN(*count, mtd->erasesize); *offset = ofs; @@ -145,11 +144,11 @@ static int mtd_erase_align(struct mtd_info *mtd, size_t *count, loff_t *offset) return 0; } -static int mtd_op_erase(struct cdev *cdev, size_t count, loff_t offset) +static int mtd_op_erase(struct cdev *cdev, loff_t count, loff_t offset) { struct mtd_info *mtd = cdev->priv; struct erase_info erase; - uint32_t addr; + loff_t addr; int ret; ret = mtd_erase_align(mtd, &count, &offset); @@ -169,7 +168,7 @@ static int mtd_op_erase(struct cdev *cdev, size_t count, loff_t offset) erase.len = mtd->erasesize; while (count > 0) { - dev_dbg(cdev->dev, "erase %d %d\n", addr, erase.len); + dev_dbg(cdev->dev, "erase 0x%08llx len: 0x%08llx\n", addr, erase.len); if (mtd->allow_erasebad || (mtd->master && mtd->master->allow_erasebad)) ret = 0; @@ -179,7 +178,7 @@ static int mtd_op_erase(struct cdev *cdev, size_t count, loff_t offset) erase.addr = addr; if (ret > 0) { - printf("Skipping bad block at 0x%08x\n", addr); + printf("Skipping bad block at 0x%08llx\n", addr); } else { ret = mtd_erase(mtd, &erase); if (ret) @@ -310,6 +309,9 @@ int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs) { int ret; + if (ofs < 0 || ofs >= mtd->size) + return -EINVAL; + if (mtd->block_markbad) ret = mtd->block_markbad(mtd, ofs); else @@ -324,6 +326,11 @@ int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, int ret_code; *retlen = 0; + if (from < 0 || from >= mtd->size || len > mtd->size - from) + return -EINVAL; + if (!len) + return 0; + /* * In the absence of an error, drivers return a non-negative integer * representing the maximum number of bitflips that were corrected on @@ -342,11 +349,28 @@ int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, { *retlen = 0; + if (to < 0 || to >= mtd->size || len > mtd->size - to) + return -EINVAL; + if (!mtd->write || !(mtd->flags & MTD_WRITEABLE)) + return -EROFS; + if (!len) + return 0; + return mtd->write(mtd, to, len, retlen, buf); } int mtd_erase(struct mtd_info *mtd, struct erase_info *instr) { + if (instr->addr >= mtd->size || instr->len > mtd->size - instr->addr) + return -EINVAL; + if (!(mtd->flags & MTD_WRITEABLE)) + return -EROFS; + instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN; + if (!instr->len) { + instr->state = MTD_ERASE_DONE; + mtd_erase_callback(instr); + return 0; + } return mtd->erase(mtd, instr); } diff --git a/drivers/mtd/devices/docg3.c b/drivers/mtd/devices/docg3.c index 9ae606b3d8..3ff7ddfb09 100644 --- a/drivers/mtd/devices/docg3.c +++ b/drivers/mtd/devices/docg3.c @@ -1146,11 +1146,15 @@ nomem1: static int __init docg3_probe(struct device_d *dev) { + struct resource *iores; struct mtd_info *mtd; void __iomem *base; int ret, floor, found = 0; - base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); ret = -ENOMEM; docg3_bch = init_bch(DOC_ECC_BCH_M, DOC_ECC_BCH_T, diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index d627690080..656a7f5ef0 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -298,6 +298,8 @@ static __maybe_unused struct of_device_id m25p80_dt_ids[] = { { .compatible = "m25p80", }, { + .compatible = "jedec,spi-nor", + }, { /* sentinel */ } }; diff --git a/drivers/mtd/devices/mtdram.c b/drivers/mtd/devices/mtdram.c index d1eaafdab5..acaf002258 100644 --- a/drivers/mtd/devices/mtdram.c +++ b/drivers/mtd/devices/mtdram.c @@ -49,6 +49,7 @@ static int ram_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retle static int mtdram_probe(struct device_d *dev) { + struct resource *iores; void __iomem *base; int device_id; struct mtd_info *mtd; @@ -70,11 +71,12 @@ static int mtdram_probe(struct device_d *dev) mtd->name = "mtdram"; } - base = dev_request_mem_region(dev, 0); - if (!base) { - ret = -EBUSY; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto nobase; } + base = IOMEM(iores->start); res = dev_get_resource(dev, IORESOURCE_MEM, 0); size = (unsigned long) resource_size(res); diff --git a/drivers/mtd/mtdoob.c b/drivers/mtd/mtdoob.c index 6160ddba08..4dcf2f5915 100644 --- a/drivers/mtd/mtdoob.c +++ b/drivers/mtd/mtdoob.c @@ -79,7 +79,7 @@ static int add_mtdoob_device(struct mtd_info *mtd, const char *devname, void **p mtdoob = xzalloc(sizeof(*mtdoob)); mtdoob->cdev.ops = &mtd_ops_oob; mtdoob->cdev.size = mtd_div_by_wb(mtd->size, mtd) * mtd->oobsize; - mtdoob->cdev.name = asprintf("%s_oob%d", devname, mtd->class_dev.id); + mtdoob->cdev.name = asprintf("%s.oob", mtd->cdev.name); mtdoob->cdev.priv = mtdoob; mtdoob->cdev.dev = &mtd->class_dev; mtdoob->mtd = mtd; diff --git a/drivers/mtd/mtdraw.c b/drivers/mtd/mtdraw.c index ae4bec2a4c..4d6ac72bd9 100644 --- a/drivers/mtd/mtdraw.c +++ b/drivers/mtd/mtdraw.c @@ -83,6 +83,20 @@ static struct mtd_info *to_mtd(struct cdev *cdev) return mtdraw->mtd; } +static unsigned int mtdraw_offset_to_block(struct mtd_info *mtd, loff_t offset) +{ + u64 ofs64 = offset; + + do_div(ofs64, mtd->writesize + mtd->oobsize); + + return ofs64; +} + +static loff_t mtdraw_raw_to_mtd_offset(struct mtd_info *mtd, loff_t offset) +{ + return (loff_t)mtdraw_offset_to_block(mtd, offset) * mtd->writesize; +} + static ssize_t mtdraw_read_unaligned(struct mtd_info *mtd, void *dst, size_t count, int skip, ulong offset) { @@ -117,22 +131,21 @@ err: } static ssize_t mtdraw_read(struct cdev *cdev, void *buf, size_t count, - loff_t _offset, ulong flags) + loff_t offset, ulong flags) { struct mtd_info *mtd = to_mtd(cdev); ssize_t retlen = 0, ret = 1, toread; - ulong numpage; + ulong numblock; int skip; - unsigned long offset = _offset; - numpage = offset / (mtd->writesize + mtd->oobsize); - skip = offset % (mtd->writesize + mtd->oobsize); + numblock = mtdraw_offset_to_block(mtd, offset); + skip = offset - numblock * (mtd->writesize + mtd->oobsize); while (ret > 0 && count > 0) { toread = min_t(int, count, mtd->writesize + mtd->oobsize - skip); ret = mtdraw_read_unaligned(mtd, buf, toread, - skip, numpage++ * mtd->writesize); + skip, numblock++ * mtd->writesize); buf += ret; skip = 0; count -= ret; @@ -171,20 +184,21 @@ static void mtdraw_fillbuf(struct mtdraw *mtdraw, const void *src, int nbbytes) } static ssize_t mtdraw_write(struct cdev *cdev, const void *buf, size_t count, - loff_t _offset, ulong flags) + loff_t offset, ulong flags) { struct mtdraw *mtdraw = to_mtdraw(cdev); struct mtd_info *mtd = to_mtd(cdev); int bsz = mtd->writesize + mtd->oobsize; - ulong numpage; + ulong numblock; size_t retlen = 0, tofill; - unsigned long offset = _offset; int ret = 0; + numblock = mtdraw_offset_to_block(mtd, offset); + if (mtdraw->write_fill && mtdraw->write_ofs + mtdraw->write_fill != offset) return -EINVAL; - if (mtdraw->write_fill == 0 && offset % bsz) + if (mtdraw->write_fill == 0 && offset - numblock * mtd->writesize != 0) return -EINVAL; if (mtdraw->write_fill) { @@ -196,16 +210,16 @@ static ssize_t mtdraw_write(struct cdev *cdev, const void *buf, size_t count, } if (mtdraw->write_fill == bsz) { - numpage = mtdraw->write_ofs / (mtd->writesize + mtd->oobsize); + numblock = mtdraw_offset_to_block(mtd, mtdraw->write_ofs); ret = mtdraw_blkwrite(mtd, mtdraw->writebuf, - mtd->writesize * numpage); + mtd->writesize * numblock); mtdraw->write_fill = 0; } - numpage = offset / (mtd->writesize + mtd->oobsize); + numblock = mtdraw_offset_to_block(mtd, offset); while (ret >= 0 && count >= bsz) { ret = mtdraw_blkwrite(mtd, buf + retlen, - mtd->writesize * numpage++); + mtd->writesize * numblock++); count -= ret; retlen += ret; offset += ret; @@ -225,15 +239,14 @@ static ssize_t mtdraw_write(struct cdev *cdev, const void *buf, size_t count, } } -static int mtdraw_erase(struct cdev *cdev, size_t count, loff_t _offset) +static int mtdraw_erase(struct cdev *cdev, loff_t count, loff_t offset) { struct mtd_info *mtd = to_mtd(cdev); struct erase_info erase; - unsigned long offset = _offset; int ret; - offset = offset / (mtd->writesize + mtd->oobsize) * mtd->writesize; - count = count / (mtd->writesize + mtd->oobsize) * mtd->writesize; + offset = mtdraw_raw_to_mtd_offset(mtd, offset); + count = mtdraw_raw_to_mtd_offset(mtd, count); memset(&erase, 0, sizeof(erase)); erase.mtd = mtd; @@ -241,7 +254,7 @@ static int mtdraw_erase(struct cdev *cdev, size_t count, loff_t _offset) erase.len = mtd->erasesize; while (count > 0) { - debug("erase %d %d\n", erase.addr, erase.len); + debug("erase 0x%08llx len: 0x%08llx\n", erase.addr, erase.len); if (!mtd->allow_erasebad) ret = mtd_block_isbad(mtd, erase.addr); @@ -249,7 +262,7 @@ static int mtdraw_erase(struct cdev *cdev, size_t count, loff_t _offset) ret = 0; if (ret > 0) { - printf("Skipping bad block at 0x%08x\n", erase.addr); + printf("Skipping bad block at 0x%08llx\n", erase.addr); } else { ret = mtd_erase(mtd, &erase); if (ret) diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 4ddabda572..299cc15c3d 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -862,6 +862,7 @@ static int pmecc_build_galois_table(unsigned int mm, int16_t *index_of, static int __init atmel_pmecc_nand_init_params(struct device_d *dev, struct atmel_nand_host *host) { + struct resource *iores; struct mtd_info *mtd = &host->mtd; struct nand_chip *nand_chip = &host->nand_chip; int cap, sector_size, err_no; @@ -872,21 +873,28 @@ static int __init atmel_pmecc_nand_init_params(struct device_d *dev, dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n", cap, sector_size); - host->ecc = dev_request_mem_region(dev, 1); - if (host->ecc == NULL) { + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->ecc = IOMEM(iores->start); + if (IS_ERR(host->ecc)) { dev_err(host->dev, "ioremap failed\n"); return -EIO; } - host->pmerrloc_base = dev_request_mem_region(dev, 2); - if (!host->pmerrloc_base) { + iores = dev_request_mem_resource(dev, 2); + if (IS_ERR(iores)) { dev_err(host->dev, "Can not get I/O resource for PMECC ERRLOC controller!\n"); - return -EIO; + return PTR_ERR(iores); } + host->pmerrloc_base = IOMEM(iores->start); - host->pmecc_rom_base = dev_request_mem_region(dev, 3); - if (!host->pmecc_rom_base) { + iores = dev_request_mem_resource(dev, 3); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->pmecc_rom_base = IOMEM(iores->start); + if (IS_ERR(host->pmecc_rom_base)) { /* Set pmecc_rom_base as the begin of gf table */ int size = sector_size == 512 ? 0x2000 : 0x4000; pmecc_galois_table = xzalloc(2 * size * sizeof(uint16_t)); @@ -1245,11 +1253,15 @@ static int atmel_nand_of_init(struct atmel_nand_host *host, struct device_node * static int atmel_hw_nand_init_params(struct device_d *dev, struct atmel_nand_host *host) { + struct resource *iores; struct mtd_info *mtd = &host->mtd; struct nand_chip *nand_chip = &host->nand_chip; - host->ecc = dev_request_mem_region(dev, 1); - if (host->ecc == NULL) { + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->ecc = IOMEM(iores->start); + if (IS_ERR(host->ecc)) { dev_err(host->dev, "ioremap failed\n"); return -EIO; } @@ -1297,6 +1309,7 @@ static int atmel_hw_nand_init_params(struct device_d *dev, */ static int __init atmel_nand_probe(struct device_d *dev) { + struct resource *iores; struct atmel_nand_data *pdata = NULL; struct atmel_nand_host *host; struct mtd_info *mtd; @@ -1312,9 +1325,10 @@ static int __init atmel_nand_probe(struct device_d *dev) if (!pdata) return -ENOMEM; - host->io_base = dev_request_mem_region(dev, 0); - if (IS_ERR(host->io_base)) - return PTR_ERR(host->io_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->io_base = IOMEM(iores->start); mtd = &host->mtd; nand_chip = &host->nand_chip; diff --git a/drivers/mtd/nand/nand-bb.c b/drivers/mtd/nand/nand-bb.c index 8e4600ab03..e6d42772b3 100644 --- a/drivers/mtd/nand/nand-bb.c +++ b/drivers/mtd/nand/nand-bb.c @@ -88,7 +88,7 @@ static ssize_t nand_bb_read(struct cdev *cdev, void *buf, size_t count, } /* Must be a multiple of the largest NAND page size */ -#define BB_WRITEBUF_SIZE 4096 +#define BB_WRITEBUF_SIZE 8192 #ifdef CONFIG_MTD_WRITE static int nand_bb_write_buf(struct nand_bb *bb, size_t count) @@ -157,7 +157,7 @@ static ssize_t nand_bb_write(struct cdev *cdev, const void *buf, size_t count, return bytes; } -static int nand_bb_erase(struct cdev *cdev, size_t count, loff_t offset) +static int nand_bb_erase(struct cdev *cdev, loff_t count, loff_t offset) { struct nand_bb *bb = cdev->priv; struct erase_info erase = {}; diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 554d3d2f96..ec5a8b757c 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -3718,7 +3718,7 @@ int nand_scan_tail(struct mtd_info *mtd) * properly set. */ if (!mtd->bitflip_threshold) - mtd->bitflip_threshold = mtd->ecc_strength; + mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); /* Check, if we should skip the bad block table scan */ if (chip->options & NAND_SKIP_BBTSCAN) diff --git a/drivers/mtd/nand/nand_denali_dt.c b/drivers/mtd/nand/nand_denali_dt.c index 6a3aee1415..2c6b188094 100644 --- a/drivers/mtd/nand/nand_denali_dt.c +++ b/drivers/mtd/nand/nand_denali_dt.c @@ -36,6 +36,7 @@ struct denali_dt { static int denali_dt_probe(struct device_d *ofdev) { + struct resource *iores; struct denali_dt *dt; struct denali_nand_info *denali; int ret; @@ -51,12 +52,15 @@ static int denali_dt_probe(struct device_d *ofdev) denali->platform = DT; denali->dev = ofdev; - denali->flash_mem = dev_request_mem_region(ofdev, 0); - if (IS_ERR(denali->flash_mem)) - return PTR_ERR(denali->flash_mem); - denali->flash_reg = dev_request_mem_region(ofdev, 1); - if (IS_ERR(denali->flash_reg)) - return PTR_ERR(denali->flash_reg); + iores = dev_request_mem_resource(ofdev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + denali->flash_mem = IOMEM(iores->start); + + iores = dev_request_mem_resource(ofdev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + denali->flash_reg = IOMEM(iores->start); dt->clk = clk_get(ofdev, NULL); if (IS_ERR(dt->clk)) { diff --git a/drivers/mtd/nand/nand_imx.c b/drivers/mtd/nand/nand_imx.c index 00c05d00af..6ea82a110d 100644 --- a/drivers/mtd/nand/nand_imx.c +++ b/drivers/mtd/nand/nand_imx.c @@ -1105,6 +1105,7 @@ static int __init mxcnd_probe_dt(struct imx_nand_host *host) static int __init imxnd_probe(struct device_d *dev) { + struct resource *iores; struct nand_chip *this; struct mtd_info *mtd; struct imx_nand_host *host; @@ -1146,7 +1147,10 @@ static int __init imxnd_probe(struct device_d *dev) } if (nfc_is_v21()) { - host->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->base = IOMEM(iores->start); host->main_area0 = host->base; host->regs = host->base + 0x1e00; host->spare0 = host->base + 0x1000; @@ -1155,7 +1159,10 @@ static int __init imxnd_probe(struct device_d *dev) oob_largepage = &nandv2_hw_eccoob_largepage; oob_4kpage = &nandv2_hw_eccoob_4k; /* FIXME : to check */ } else if (nfc_is_v1()) { - host->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->base = IOMEM(iores->start); host->main_area0 = host->base; host->regs = host->base + 0xe00; host->spare0 = host->base + 0x800; @@ -1164,13 +1171,20 @@ static int __init imxnd_probe(struct device_d *dev) oob_largepage = &nandv1_hw_eccoob_largepage; oob_4kpage = &nandv1_hw_eccoob_smallpage; /* FIXME : to check */ } else if (nfc_is_v3_2()) { - host->regs_ip = dev_request_mem_region(dev, 0); - host->base = dev_request_mem_region(dev, 1); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->regs_ip = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->base = IOMEM(iores->start); host->main_area0 = host->base; - if (!host->regs_ip) { + if (IS_ERR(host->regs_ip)) { dev_err(dev, "no second mem region\n"); - err = -ENODEV; + err = PTR_ERR(host->regs_ip); goto escan; } diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c index f160d15ab5..578790da26 100644 --- a/drivers/mtd/nand/nand_mrvl_nfc.c +++ b/drivers/mtd/nand/nand_mrvl_nfc.c @@ -1105,6 +1105,7 @@ static int mrvl_nand_scan(struct mtd_info *mtd) static struct mrvl_nand_host *alloc_nand_resource(struct device_d *dev) { + struct resource *iores; struct mrvl_nand_platform_data *pdata; struct mrvl_nand_host *host; struct nand_chip *chip = NULL; @@ -1135,7 +1136,10 @@ static struct mrvl_nand_host *alloc_nand_resource(struct device_d *dev) chip->chip_delay = CHIP_DELAY_TIMEOUT_US; host->dev = dev; - host->mmio_base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->mmio_base = IOMEM(iores->start); if (IS_ERR(host->mmio_base)) { free(host); return host->mmio_base; diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c index 7635e2a418..20bda14b62 100644 --- a/drivers/mtd/nand/nand_mxs.c +++ b/drivers/mtd/nand/nand_mxs.c @@ -1274,6 +1274,7 @@ static void mxs_nand_probe_dt(struct device_d *dev, struct mxs_nand_info *nand_i static int mxs_nand_probe(struct device_d *dev) { + struct resource *iores; struct mxs_nand_info *nand_info; struct nand_chip *nand; struct mtd_info *mtd; @@ -1293,13 +1294,15 @@ static int mxs_nand_probe(struct device_d *dev) mxs_nand_probe_dt(dev, nand_info); nand_info->type = type; - nand_info->io_base = dev_request_mem_region(dev, 0); - if (IS_ERR(nand_info->io_base)) - return PTR_ERR(nand_info->io_base); - - nand_info->bch_base = dev_request_mem_region(dev, 1); - if (IS_ERR(nand_info->bch_base)) - return PTR_ERR(nand_info->bch_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + nand_info->io_base = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + nand_info->bch_base = IOMEM(iores->start); nand_info->clk = clk_get(dev, NULL); if (IS_ERR(nand_info->clk)) diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c index 9d9d27e964..a920522939 100644 --- a/drivers/mtd/nand/nand_omap_gpmc.c +++ b/drivers/mtd/nand/nand_omap_gpmc.c @@ -846,6 +846,7 @@ static int gpmc_set_buswidth(struct nand_chip *chip, int buswidth) */ static int gpmc_nand_probe(struct device_d *pdev) { + struct resource *iores; struct gpmc_nand_info *oinfo; struct gpmc_nand_platform_data *pdata; struct nand_chip *nand; @@ -881,7 +882,10 @@ static int gpmc_nand_probe(struct device_d *pdev) } /* Setup register specific data */ oinfo->gpmc_cs = pdata->cs; - oinfo->gpmc_base = dev_request_mem_region(pdev, 0); + iores = dev_request_mem_resource(pdev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + oinfo->gpmc_base = IOMEM(iores->start); cs_base = oinfo->gpmc_base + GPMC_CONFIG1_0 + (pdata->cs * GPMC_CONFIG_CS_SIZE); oinfo->gpmc_command = (void *)(cs_base + GPMC_CS_NAND_COMMAND); diff --git a/drivers/mtd/nand/nand_orion.c b/drivers/mtd/nand/nand_orion.c index fe06ef7912..881ffeec05 100644 --- a/drivers/mtd/nand/nand_orion.c +++ b/drivers/mtd/nand/nand_orion.c @@ -80,6 +80,7 @@ static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) static int orion_nand_probe(struct device_d *dev) { + struct resource *iores; struct device_node *dev_node = dev->device_node; struct orion_nand *priv; struct mtd_info *mtd; @@ -93,9 +94,10 @@ static int orion_nand_probe(struct device_d *dev) mtd = &priv->mtd; chip = &priv->chip; - io_base = dev_request_mem_region(dev, 0); - if (IS_ERR(io_base)) - return PTR_ERR(io_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + io_base = IOMEM(iores->start); if (!of_property_read_u32(dev_node, "cle", &val)) priv->cle = (u8)val; diff --git a/drivers/mtd/nand/nand_s3c24xx.c b/drivers/mtd/nand/nand_s3c24xx.c index 37bba39260..83d45172b1 100644 --- a/drivers/mtd/nand/nand_s3c24xx.c +++ b/drivers/mtd/nand/nand_s3c24xx.c @@ -408,6 +408,7 @@ static int s3c24x0_nand_inithw(struct s3c24x0_nand_host *host) static int s3c24x0_nand_probe(struct device_d *dev) { + struct resource *iores; struct nand_chip *chip; struct s3c24x0_nand_platform_data *pdata = dev->platform_data; struct mtd_info *mtd; @@ -420,7 +421,10 @@ static int s3c24x0_nand_probe(struct device_d *dev) return -ENOMEM; host->dev = dev; - host->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + host->base = IOMEM(iores->start); /* structures must be linked */ chip = &host->nand; diff --git a/drivers/mtd/nor/cfi_flash.c b/drivers/mtd/nor/cfi_flash.c index feffbd04ac..e50f0e667f 100644 --- a/drivers/mtd/nor/cfi_flash.c +++ b/drivers/mtd/nor/cfi_flash.c @@ -966,13 +966,15 @@ static void cfi_init_mtd(struct flash_info *info) static int cfi_probe_one(struct flash_info *info, int num) { + struct resource *iores; int ret; info->flash_id = FLASH_UNKNOWN; info->cmd_reset = FLASH_CMD_RESET; - info->base = dev_request_mem_region(info->dev, num); - if (IS_ERR(info->base)) - return PTR_ERR(info->base); + iores = dev_request_mem_resource(info->dev, num); + if (IS_ERR(iores)) + return PTR_ERR(iores); + info->base = IOMEM(iores->start); ret = flash_detect_size(info); if (ret) { diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index ff7bb7a5d8..680f30f707 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -1109,6 +1109,7 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) static int cqspi_probe(struct device_d *dev) { + struct resource *iores; struct device_node *np = dev->device_node; struct cqspi_st *cqspi; struct cadence_qspi_platform_data *pdata = dev->platform_data; @@ -1142,14 +1143,20 @@ static int cqspi_probe(struct device_d *dev) clk_enable(cqspi->qspi_clk); - cqspi->iobase = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + cqspi->iobase = IOMEM(iores->start); if (IS_ERR(cqspi->iobase)) { dev_err(dev, "dev_request_mem_region 0 failed\n"); ret = PTR_ERR(cqspi->iobase); goto probe_failed; } - cqspi->ahb_base = dev_request_mem_region(dev, 1); + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + cqspi->ahb_base = IOMEM(iores->start); if (IS_ERR(cqspi->ahb_base)) { dev_err(dev, "dev_request_mem_region 0 failed\n"); ret = PTR_ERR(cqspi->ahb_base); diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 908aacb6a2..4b55b0c3d8 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -571,6 +571,7 @@ static const struct spi_device_id spi_nor_ids[] = { { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) }, { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, + { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K) }, { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, 0) }, { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K) }, diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c index a1863655fa..1e67c7a8e7 100644 --- a/drivers/net/altera_tse.c +++ b/drivers/net/altera_tse.c @@ -492,6 +492,7 @@ static int tse_init_dev(struct eth_device *edev) static int tse_probe(struct device_d *dev) { + struct resource *iores; struct altera_tse_priv *priv; struct mii_bus *miibus; struct eth_device *edev; @@ -516,9 +517,10 @@ static int tse_probe(struct device_d *dev) edev->parent = dev; #ifdef CONFIG_TSE_USE_DEDICATED_DESC_MEM - tx_desc = dev_request_mem_region(dev, 3); - if (IS_ERR(tx_desc)) - return PTR_ERR(tx_desc); + iores = dev_request_mem_resource(dev, 3); + if (IS_ERR(iores)) + return PTR_ERR(iores); + tx_desc = IOMEM(iores->start); rx_desc = tx_desc + 2; #else tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX), (dma_addr_t *)&dma_handle); @@ -534,15 +536,19 @@ static int tse_probe(struct device_d *dev) memset(rx_desc, 0, (sizeof *rx_desc) * (PKTBUFSRX + 1)); memset(tx_desc, 0, (sizeof *tx_desc) * 2); - priv->tse_regs = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->tse_regs)) - return PTR_ERR(priv->tse_regs); - priv->sgdma_rx_regs = dev_request_mem_region(dev, 1); - if (IS_ERR(priv->sgdma_rx_regs)) - return PTR_ERR(priv->sgdma_rx_regs); - priv->sgdma_tx_regs = dev_request_mem_region(dev, 2); - if (IS_ERR(priv->sgdma_tx_regs)) - return PTR_ERR(priv->sgdma_tx_regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->tse_regs = IOMEM(iores->start); + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->sgdma_rx_regs = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 2); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->sgdma_tx_regs = IOMEM(iores->start); priv->rx_desc = rx_desc; priv->tx_desc = tx_desc; diff --git a/drivers/net/ar231x.c b/drivers/net/ar231x.c index 7447c4484d..1ef9ce8154 100644 --- a/drivers/net/ar231x.c +++ b/drivers/net/ar231x.c @@ -363,6 +363,7 @@ static int ar231x_mdiibus_reset(struct mii_bus *bus) static int ar231x_eth_probe(struct device_d *dev) { + struct resource *iores; struct ar231x_eth_priv *priv; struct eth_device *edev; struct mii_bus *miibus; @@ -384,20 +385,22 @@ static int ar231x_eth_probe(struct device_d *dev) priv->mac = pdata->mac; priv->reset_bit = pdata->reset_bit; - priv->eth_regs = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->eth_regs)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "No eth_regs!!\n"); - return PTR_ERR(priv->eth_regs); + return PTR_ERR(iores); } + priv->eth_regs = IOMEM(iores->start); /* we have 0x100000 for eth, part of it are dma regs. * So they are already requested */ priv->dma_regs = (void *)(priv->eth_regs + 0x1000); - priv->phy_regs = dev_request_mem_region(dev, 1); - if (IS_ERR(priv->phy_regs)) { + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) { dev_err(dev, "No phy_regs!!\n"); - return PTR_ERR(priv->phy_regs); + return PTR_ERR(iores); } + priv->phy_regs = IOMEM(iores->start); priv->cfg = pdata; edev->init = ar231x_eth_init; diff --git a/drivers/net/arc_emac.c b/drivers/net/arc_emac.c index 3dc54cd22b..2155349e21 100644 --- a/drivers/net/arc_emac.c +++ b/drivers/net/arc_emac.c @@ -391,6 +391,7 @@ static int arc_emac_mdio_write(struct mii_bus *bus, int phy_addr, int reg_num, static int arc_emac_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct arc_emac_priv *priv; unsigned long clock_frequency; @@ -406,9 +407,10 @@ static int arc_emac_probe(struct device_d *dev) miibus = xzalloc(sizeof(struct mii_bus)); priv = edev->priv; - priv->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->regs)) - return PTR_ERR(priv->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); priv->bus = miibus; priv->clk = clk_get(dev, "hclk"); diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 4d6b7b2e78..d11ca33f70 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -1126,6 +1126,7 @@ static int cpsw_probe_dt(struct cpsw_priv *priv) int cpsw_probe(struct device_d *dev) { + struct resource *iores; struct cpsw_platform_data *data = (struct cpsw_platform_data *)dev->platform_data; struct cpsw_priv *priv; void __iomem *regs; @@ -1136,9 +1137,10 @@ int cpsw_probe(struct device_d *dev) dev_dbg(dev, "* %s\n", __func__); - regs = dev_request_mem_region(dev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + regs = IOMEM(iores->start); priv = xzalloc(sizeof(*priv)); priv->dev = dev; diff --git a/drivers/net/cs8900.c b/drivers/net/cs8900.c index a4a5dcaf7f..1be49e86fe 100644 --- a/drivers/net/cs8900.c +++ b/drivers/net/cs8900.c @@ -435,13 +435,17 @@ static int cs8900_check_id(struct cs8900_priv *priv) static int cs8900_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct cs8900_priv *priv; debug("cs8900_init()\n"); priv = (struct cs8900_priv *)xmalloc(sizeof(*priv)); - priv->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); if (cs8900_check_id(priv)) { free(priv); return -1; diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 9f8f0e1fa7..3dc4b16b67 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -516,6 +516,7 @@ out: static int davinci_emac_probe(struct device_d *dev) { + struct resource *iores; struct davinci_emac_platform_data *pdata; struct davinci_emac_priv *priv; uint64_t start; @@ -534,10 +535,25 @@ static int davinci_emac_probe(struct device_d *dev) priv->dev = dev; - priv->adap_emac = dev_request_mem_region(dev, 0); - priv->adap_ewrap = dev_request_mem_region(dev, 1); - priv->adap_mdio = dev_request_mem_region(dev, 2); - priv->emac_desc_base = dev_request_mem_region(dev, 3); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->adap_emac = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->adap_ewrap = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 2); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->adap_mdio = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 3); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->emac_desc_base = IOMEM(iores->start); /* EMAC descriptors */ priv->emac_rx_desc = priv->emac_desc_base + EMAC_RX_DESC_BASE; diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 966f64f7b6..3b21244478 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -445,6 +445,7 @@ static int dwc_probe_dt(struct device_d *dev, struct dw_eth_dev *priv) static int dwc_ether_probe(struct device_d *dev) { + struct resource *iores; struct dw_eth_dev *priv; struct eth_device *edev; struct mii_bus *miibus; @@ -471,9 +472,10 @@ static int dwc_ether_probe(struct device_d *dev) return ret; } - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); priv->mac_regs_p = base; dwc_version(dev, readl(&priv->mac_regs_p->version)); diff --git a/drivers/net/dm9k.c b/drivers/net/dm9k.c index 1f1938d977..ad402e3efc 100644 --- a/drivers/net/dm9k.c +++ b/drivers/net/dm9k.c @@ -785,6 +785,7 @@ static int dm9000_parse_pdata(struct device_d *dev, struct dm9k *priv) static int dm9k_probe(struct device_d *dev) { + struct resource *iores; unsigned io_mode; struct eth_device *edev; struct dm9k *priv; @@ -808,17 +809,19 @@ static int dm9k_probe(struct device_d *dev) if (ret) goto err; - priv->iodata = dev_request_mem_region(dev, 1); - if (!priv->iodata) { - ret = -EBUSY; + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto err; } + priv->iodata = IOMEM(iores->start); - priv->iobase = dev_request_mem_region(dev, 0); - if (!priv->iobase) { - ret = -EBUSY; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto err; } + priv->iobase = IOMEM(iores->start); edev->init = dm9k_init_dev; edev->open = dm9k_eth_open; diff --git a/drivers/net/efi-snp.c b/drivers/net/efi-snp.c index 5b96fbf462..963d539db3 100644 --- a/drivers/net/efi-snp.c +++ b/drivers/net/efi-snp.c @@ -238,7 +238,7 @@ static int efi_snp_get_ethaddr(struct eth_device *edev, unsigned char *adr) return 0; } -static int efi_snp_set_ethaddr(struct eth_device *edev, unsigned char *adr) +static int efi_snp_set_ethaddr(struct eth_device *edev, const unsigned char *adr) { return 0; } diff --git a/drivers/net/ep93xx.c b/drivers/net/ep93xx.c index 90c12fce75..0acb9b692f 100644 --- a/drivers/net/ep93xx.c +++ b/drivers/net/ep93xx.c @@ -38,6 +38,7 @@ #include <linux/types.h> #include <mach/ep93xx-regs.h> #include <linux/phy.h> +#include <net/ep93xx_eth.h> #include "ep93xx.h" #define EP93XX_MAX_PKT_SIZE 1536 @@ -203,8 +204,8 @@ static int ep93xx_eth_open(struct eth_device *edev) pr_debug("+ep93xx_eth_open\n"); - ret = phy_device_connect(edev, &priv->miibus, 0, NULL, - 0, PHY_INTERFACE_MODE_NA); + ret = phy_device_connect(edev, &priv->miibus, priv->phy_addr, NULL, + 0, priv->interface); if (ret) return ret; @@ -482,6 +483,7 @@ static int ep93xx_eth_set_ethaddr(struct eth_device *edev, static int ep93xx_eth_probe(struct device_d *dev) { + struct ep93xx_eth_platform_data *pdata = (struct ep93xx_eth_platform_data *)dev->platform_data; struct eth_device *edev; struct ep93xx_eth_priv *priv; int ret = -1; @@ -504,6 +506,14 @@ static int ep93xx_eth_probe(struct device_d *dev) edev->set_ethaddr = ep93xx_eth_set_ethaddr; edev->parent = dev; + if (pdata) { + priv->interface = pdata->xcv_type; + priv->phy_addr = pdata->phy_addr; + } else { + priv->interface = PHY_INTERFACE_MODE_NA; + priv->phy_addr = 0; + } + priv->miibus.read = ep93xx_phy_read; priv->miibus.write = ep93xx_phy_write; priv->miibus.parent = dev; @@ -589,14 +599,12 @@ static int ep93xx_phy_read(struct mii_bus *bus, int phy_addr, int phy_reg) pr_debug("+ep93xx_phy_read\n"); /* - * Save the current SelfCTL register value. Set MAC to suppress + * Save the current SelfCTL register value. Set MAC to send * preamble bits. Wait for any previous MII command to complete * before issuing the new command. */ self_ctl = readl(®s->selfctl); -#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) /* TODO */ writel(self_ctl & ~(1 << 8), ®s->selfctl); -#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ while (readl(®s->miists) & MIISTS_BUSY) ; /* noop */ @@ -632,14 +640,12 @@ static int ep93xx_phy_write(struct mii_bus *bus, int phy_addr, pr_debug("+ep93xx_phy_write\n"); /* - * Save the current SelfCTL register value. Set MAC to suppress + * Save the current SelfCTL register value. Set MAC to send * preamble bits. Wait for any previous MII command to complete * before issuing the new command. */ self_ctl = readl(®s->selfctl); -#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) /* TODO */ writel(self_ctl & ~(1 << 8), ®s->selfctl); -#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ while (readl(®s->miists) & MIISTS_BUSY) ; /* noop */ diff --git a/drivers/net/ep93xx.h b/drivers/net/ep93xx.h index 89451b8a5f..32ae57f9f2 100644 --- a/drivers/net/ep93xx.h +++ b/drivers/net/ep93xx.h @@ -137,6 +137,8 @@ struct ep93xx_eth_priv { struct tx_descriptor_queue tx_dq; struct tx_status_queue tx_sq; + int phy_addr; + phy_interface_t interface; struct mii_bus miibus; }; diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index 6bae7d68a6..1cb9fc2859 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -534,6 +534,7 @@ static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) static int ethoc_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct ethoc *priv; @@ -542,9 +543,10 @@ static int ethoc_probe(struct device_d *dev) edev->priv = (struct ethoc *)(edev + 1); priv = edev->priv; - priv->iobase = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->iobase)) - return PTR_ERR(priv->iobase); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->iobase = IOMEM(iores->start); priv->miibus.read = ethoc_mdio_read; priv->miibus.write = ethoc_mdio_write; diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c index 5418034129..de31ec48bd 100644 --- a/drivers/net/fec_imx.c +++ b/drivers/net/fec_imx.c @@ -647,6 +647,7 @@ static int fec_probe_dt(struct device_d *dev, struct fec_priv *fec) #endif static int fec_probe(struct device_d *dev) { + struct resource *iores; struct fec_platform_data *pdata = (struct fec_platform_data *)dev->platform_data; struct eth_device *edev; struct fec_priv *fec; @@ -681,7 +682,10 @@ static int fec_probe(struct device_d *dev) clk_enable(fec->clk); - fec->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + fec->regs = IOMEM(iores->start); phy_reset = of_get_named_gpio(dev->device_node, "phy-reset-gpios", 0); if (gpio_is_valid(phy_reset)) { diff --git a/drivers/net/fec_mpc5200.c b/drivers/net/fec_mpc5200.c index 30be8f77dc..bb57c34502 100644 --- a/drivers/net/fec_mpc5200.c +++ b/drivers/net/fec_mpc5200.c @@ -638,6 +638,7 @@ static int mpc5xxx_fec_recv(struct eth_device *dev) int mpc5xxx_fec_probe(struct device_d *dev) { + struct resource *iores; struct fec_platform_data *pdata = dev->platform_data; struct eth_device *edev; mpc5xxx_fec_priv *fec; @@ -655,9 +656,10 @@ int mpc5xxx_fec_probe(struct device_d *dev) edev->set_ethaddr = mpc5xxx_fec_set_ethaddr; edev->parent = dev; - fec->eth = dev_request_mem_region(dev, 0); - if (IS_ERR(fec->eth)) - return PTR_ERR(fec->eth); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + fec->eth = IOMEM(iores->start); fec->tbdBase = (FEC_TBD *)FEC_BD_BASE; fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD)); diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c index 854a666bfc..39e1654ca6 100644 --- a/drivers/net/ks8851_mll.c +++ b/drivers/net/ks8851_mll.c @@ -809,6 +809,7 @@ static void ks8851_eth_halt(struct eth_device *edev) static int ks8851_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct ks_net *ks; u16 id; @@ -823,13 +824,16 @@ static int ks8851_probe(struct device_d *dev) return -ENODEV; } - ks->hw_addr = dev_request_mem_region(dev, 0); - if (IS_ERR(ks->hw_addr)) - return PTR_ERR(ks->hw_addr); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ks->hw_addr = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ks->hw_addr_cmd = IOMEM(iores->start); - ks->hw_addr_cmd = dev_request_mem_region(dev, 1); - if (IS_ERR(ks->hw_addr_cmd)) - return PTR_ERR(ks->hw_addr_cmd); ks->bus_width = dev->resource[0].flags & IORESOURCE_MEM_TYPE_MASK; edev->init = ks8851_init_dev; diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 6d4973fa2f..5f2e5e5131 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -612,6 +612,7 @@ static void macb_init_rx_buffer_size(struct macb_device *bp, size_t size) static int macb_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct macb_device *macb; u32 ncfgr; @@ -649,9 +650,10 @@ static int macb_probe(struct device_d *dev) macb->phy_flags = pdata->phy_flags; - macb->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(macb->regs)) - return PTR_ERR(macb->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + macb->regs = IOMEM(iores->start); /* * Do some basic initialization so that we at least can talk diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c index 1199b372b6..b7055910eb 100644 --- a/drivers/net/smc91111.c +++ b/drivers/net/smc91111.c @@ -1444,6 +1444,7 @@ static int smc91c111_init_dev(struct eth_device *edev) static int smc91c111_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct smc91c111_priv *priv; @@ -1481,9 +1482,10 @@ static int smc91c111_probe(struct device_d *dev) priv->miibus.write = smc91c111_phy_write; priv->miibus.priv = priv; priv->miibus.parent = dev; - priv->base = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->base = IOMEM(iores->start); smc91c111_reset(edev); diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 60cf36ea4a..9b1a38ae21 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -494,6 +494,7 @@ static int smc911x_init_dev(struct eth_device *edev) static int smc911x_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct smc911x_priv *priv; uint32_t val; @@ -506,7 +507,10 @@ static int smc911x_probe(struct device_d *dev) is_32bit = 1; else is_32bit = is_32bit == IORESOURCE_MEM_32BIT; - priv->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->base = IOMEM(iores->start); if (pdata) { priv->shift = pdata->shift; diff --git a/drivers/net/xgmac.c b/drivers/net/xgmac.c index 7cc4d4888f..47ab6e72eb 100644 --- a/drivers/net/xgmac.c +++ b/drivers/net/xgmac.c @@ -689,11 +689,15 @@ static int xgmac_set_ethaddr(struct eth_device *dev, const unsigned char *addr) static int hb_xgmac_probe(struct device_d *dev) { + struct resource *iores; struct eth_device *edev; struct xgmac_priv *priv; void __iomem *base; - base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); /* check hardware version */ if (readl(base + XGMAC_VERSION) != 0x1012) diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c index d32bd2b4ce..46483b4cc8 100644 --- a/drivers/pci/pci-imx6.c +++ b/drivers/pci/pci-imx6.c @@ -555,6 +555,7 @@ static int __init imx6_add_pcie_port(struct pcie_port *pp, static int __init imx6_pcie_probe(struct device_d *dev) { + struct resource *iores; struct imx6_pcie *imx6_pcie; struct pcie_port *pp; struct device_node *np = dev->device_node; @@ -567,9 +568,10 @@ static int __init imx6_pcie_probe(struct device_d *dev) pp = &imx6_pcie->pp; pp->dev = dev; - pp->dbi_base = dev_request_mem_region(dev, 0); - if (IS_ERR(pp->dbi_base)) - return PTR_ERR(pp->dbi_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + pp->dbi_base = IOMEM(iores->start); /* Fetch GPIOs */ imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); diff --git a/drivers/pinctrl/imx-iomux-v2.c b/drivers/pinctrl/imx-iomux-v2.c index 1e0e8e9fd6..0c985a69d3 100644 --- a/drivers/pinctrl/imx-iomux-v2.c +++ b/drivers/pinctrl/imx-iomux-v2.c @@ -118,9 +118,11 @@ int imx_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count) static int imx_iomux_probe(struct device_d *dev) { - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + struct resource *iores; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); return 0; } diff --git a/drivers/pinctrl/imx-iomux-v3.c b/drivers/pinctrl/imx-iomux-v3.c index 62a352ba50..66443b7e7b 100644 --- a/drivers/pinctrl/imx-iomux-v3.c +++ b/drivers/pinctrl/imx-iomux-v3.c @@ -171,12 +171,16 @@ static int imx_pinctrl_dt(struct device_d *dev, void __iomem *base) static int imx_iomux_v3_probe(struct device_d *dev) { + struct resource *iores; int ret = 0; if (iomuxv3_base) return -EBUSY; - iomuxv3_base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + iomuxv3_base = IOMEM(iores->start); iomuxv3_dev = dev; if (IS_ENABLED(CONFIG_PINCTRL) && dev->device_node) diff --git a/drivers/pinctrl/mvebu/armada-370.c b/drivers/pinctrl/mvebu/armada-370.c index b7901f8c6d..1c79bd62af 100644 --- a/drivers/pinctrl/mvebu/armada-370.c +++ b/drivers/pinctrl/mvebu/armada-370.c @@ -391,14 +391,16 @@ static struct of_device_id armada_370_pinctrl_of_match[] = { static int armada_370_pinctrl_probe(struct device_d *dev) { + struct resource *iores; const struct of_device_id *match = of_match_node(armada_370_pinctrl_of_match, dev->device_node); struct mvebu_pinctrl_soc_info *soc = (struct mvebu_pinctrl_soc_info *)match->data; - mpp_base = dev_request_mem_region(dev, 0); - if (!mpp_base) - return -EBUSY; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mpp_base = IOMEM(iores->start); return mvebu_pinctrl_probe(dev, soc); } diff --git a/drivers/pinctrl/mvebu/armada-xp.c b/drivers/pinctrl/mvebu/armada-xp.c index 51db35d068..f1bc8b498a 100644 --- a/drivers/pinctrl/mvebu/armada-xp.c +++ b/drivers/pinctrl/mvebu/armada-xp.c @@ -370,13 +370,15 @@ static struct of_device_id armada_xp_pinctrl_of_match[] = { static int armada_xp_pinctrl_probe(struct device_d *dev) { + struct resource *iores; const struct of_device_id *match = of_match_node(armada_xp_pinctrl_of_match, dev->device_node); struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info; - mpp_base = dev_request_mem_region(dev, 0); - if (IS_ERR(mpp_base)) - return PTR_ERR(mpp_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mpp_base = IOMEM(iores->start); soc->variant = (enum armada_xp_variant)match->data; diff --git a/drivers/pinctrl/mvebu/dove.c b/drivers/pinctrl/mvebu/dove.c index d1848a79d3..8de01e74d6 100644 --- a/drivers/pinctrl/mvebu/dove.c +++ b/drivers/pinctrl/mvebu/dove.c @@ -696,6 +696,7 @@ static struct of_device_id dove_pinctrl_of_match[] = { static int dove_pinctrl_probe(struct device_d *dev) { + struct resource *iores; const struct of_device_id *match = of_match_node(dove_pinctrl_of_match, dev->device_node); struct mvebu_pinctrl_soc_info *soc = @@ -706,10 +707,15 @@ static int dove_pinctrl_probe(struct device_d *dev) clk = clk_get(dev, NULL); clk_enable(clk); - mpp_base = dev_request_mem_region(dev, 0); - mpp4_base = dev_request_mem_region(dev, 1); - if (!mpp_base || !mpp4_base) - return -EBUSY; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mpp_base = IOMEM(iores->start); + + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mpp4_base = IOMEM(iores->start); /* * Dove PMU does not have a stable binding, yet. diff --git a/drivers/pinctrl/mvebu/kirkwood.c b/drivers/pinctrl/mvebu/kirkwood.c index e2ac559668..4b2618cd2e 100644 --- a/drivers/pinctrl/mvebu/kirkwood.c +++ b/drivers/pinctrl/mvebu/kirkwood.c @@ -432,14 +432,16 @@ static struct of_device_id kirkwood_pinctrl_of_match[] = { static int kirkwood_pinctrl_probe(struct device_d *dev) { + struct resource *iores; const struct of_device_id *match = of_match_node(kirkwood_pinctrl_of_match, dev->device_node); struct mvebu_pinctrl_soc_info *soc = (struct mvebu_pinctrl_soc_info *)match->data; - mpp_base = dev_request_mem_region(dev, 0); - if (IS_ERR(mpp_base)) - return PTR_ERR(mpp_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mpp_base = IOMEM(iores->start); return mvebu_pinctrl_probe(dev, soc); } diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 5c60c70b17..15b74cc1df 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -98,12 +98,16 @@ static struct pinctrl_ops pcs_ops = { static int pcs_probe(struct device_d *dev) { + struct resource *iores; struct pinctrl_single *pcs; struct device_node *np = dev->device_node; int ret = 0; pcs = xzalloc(sizeof(*pcs)); - pcs->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + pcs->base = IOMEM(iores->start); pcs->pinctrl.dev = dev; pcs->pinctrl.ops = &pcs_ops; diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c index d567754fd7..a7a75bb9c5 100644 --- a/drivers/pinctrl/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/pinctrl-tegra-xusb.c @@ -378,6 +378,7 @@ static struct pinctrl_ops pinctrl_tegra_xusb_ops = { static int pinctrl_tegra_xusb_probe(struct device_d *dev) { + struct resource *iores; struct tegra_xusb_padctl *padctl; struct phy *phy; int err; @@ -389,11 +390,12 @@ static int pinctrl_tegra_xusb_probe(struct device_d *dev) dev_get_drvdata(dev, (const void **)&padctl->soc); - padctl->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(padctl->regs)) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "Could not get iomem region\n"); - return PTR_ERR(padctl->regs); + return PTR_ERR(iores); } + padctl->regs = IOMEM(iores->start); padctl->rst = reset_control_get(dev, NULL); if (IS_ERR(padctl->rst)) diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c index be9d8a996d..eaaba9e7a7 100644 --- a/drivers/pinctrl/pinctrl-tegra20.c +++ b/drivers/pinctrl/pinctrl-tegra20.c @@ -295,6 +295,7 @@ static struct pinctrl_ops pinctrl_tegra20_ops = { static int pinctrl_tegra20_probe(struct device_d *dev) { + struct resource *iores; struct pinctrl_tegra20 *ctrl; int i, ret; u32 **regs; @@ -309,11 +310,12 @@ static int pinctrl_tegra20_probe(struct device_d *dev) */ regs = (u32 **)&ctrl->regs; for (i = 0; i <= 2; i++) { - regs[i] = dev_request_mem_region(dev, i); - if (IS_ERR(regs[i])) { + iores = dev_request_mem_resource(dev, i); + if (IS_ERR(iores)) { dev_err(dev, "Could not get iomem region %d\n", i); - return PTR_ERR(regs[i]); + return PTR_ERR(iores); } + regs[i] = IOMEM(iores->start); } ctrl->pinctrl.dev = dev; diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c index 145a1a821e..4b271dd0b6 100644 --- a/drivers/pinctrl/pinctrl-tegra30.c +++ b/drivers/pinctrl/pinctrl-tegra30.c @@ -870,6 +870,7 @@ static struct pinctrl_ops pinctrl_tegra30_ops = { static int pinctrl_tegra30_probe(struct device_d *dev) { + struct resource *iores; struct pinctrl_tegra30 *ctrl; int i, ret; u32 **regs; @@ -884,11 +885,12 @@ static int pinctrl_tegra30_probe(struct device_d *dev) */ regs = (u32 **)&ctrl->regs; for (i = 0; i <= 1; i++) { - regs[i] = dev_request_mem_region(dev, i); - if (IS_ERR(regs[i])) { + iores = dev_request_mem_resource(dev, i); + if (IS_ERR(iores)) { dev_err(dev, "Could not get iomem region %d\n", i); - return PTR_ERR(regs[i]); + return PTR_ERR(iores); } + regs[i] = IOMEM(iores->start); } dev_get_drvdata(dev, (const void **)&ctrl->drvdata); diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index bd99cf3198..0845c234fe 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -212,6 +212,7 @@ static struct of_device_id imx_pwm_dt_ids[] = { static int imx_pwm_probe(struct device_d *dev) { + struct resource *iores; const struct imx_pwm_data *data; struct imx_chip *imx; int ret = 0; @@ -226,9 +227,10 @@ static int imx_pwm_probe(struct device_d *dev) if (IS_ERR(imx->clk_per)) return PTR_ERR(imx->clk_per); - imx->mmio_base = dev_request_mem_region(dev, 0); - if (IS_ERR(imx->mmio_base)) - return PTR_ERR(imx->mmio_base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + imx->mmio_base = IOMEM(iores->start); imx->chip.ops = &imx_pwm_ops; if (dev->device_node) { diff --git a/drivers/pwm/pwm-mxs.c b/drivers/pwm/pwm-mxs.c index e66744288b..011d9002ba 100644 --- a/drivers/pwm/pwm-mxs.c +++ b/drivers/pwm/pwm-mxs.c @@ -110,6 +110,7 @@ static struct pwm_ops mxs_pwm_ops = { static int mxs_pwm_probe(struct device_d *dev) { + struct resource *iores; struct device_node *np = dev->device_node; struct mxs_pwm *mxs; int ret, i; @@ -117,9 +118,10 @@ static int mxs_pwm_probe(struct device_d *dev) mxs = xzalloc(sizeof(*mxs)); - mxs->base = dev_request_mem_region(dev, 0); - if (IS_ERR(mxs->base)) - return PTR_ERR(mxs->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mxs->base = IOMEM(iores->start); mxs->clk = clk_get(dev, NULL); if (IS_ERR(mxs->clk)) diff --git a/drivers/pwm/pxa_pwm.c b/drivers/pwm/pxa_pwm.c index 8b2ebe4f6f..e399d03efd 100644 --- a/drivers/pwm/pxa_pwm.c +++ b/drivers/pwm/pxa_pwm.c @@ -130,12 +130,16 @@ static struct pwm_ops pxa_pwm_ops = { static int pxa_pwm_probe(struct device_d *dev) { + struct resource *iores; struct pxa_pwm_chip *chip; chip = xzalloc(sizeof(*chip)); chip->chip.devname = asprintf("pwm%d", dev->id); chip->chip.ops = &pxa_pwm_ops; - chip->iobase = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + chip->iobase = IOMEM(iores->start); chip->id = dev->id; dev->priv = chip; diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c index 8194050e7f..95885357d9 100644 --- a/drivers/rtc/rtc-jz4740.c +++ b/drivers/rtc/rtc-jz4740.c @@ -113,16 +113,18 @@ static struct rtc_class_ops jz4740_rtc_ops = { static int jz4740_rtc_probe(struct device_d *dev) { + struct resource *iores; int ret; struct jz4740_rtc *rtc; uint32_t scratchpad; void __iomem *base; - base = dev_request_mem_region(dev, 0); - if (!base) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return -ENODEV; + return PTR_ERR(iores); } + base = IOMEM(iores->start); rtc = xzalloc(sizeof(*rtc)); diff --git a/drivers/serial/serial_altera.c b/drivers/serial/serial_altera.c index d519a87928..10d1506bca 100644 --- a/drivers/serial/serial_altera.c +++ b/drivers/serial/serial_altera.c @@ -78,13 +78,17 @@ static int altera_serial_getc(struct console_device *cdev) static int altera_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; struct altera_serial_priv *priv; priv = xzalloc(sizeof(*priv)); cdev = &priv->cdev; - priv->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = altera_serial_tstc; cdev->putc = altera_serial_putc; diff --git a/drivers/serial/serial_altera_jtag.c b/drivers/serial/serial_altera_jtag.c index 4219a4bbb9..0164ea5eff 100644 --- a/drivers/serial/serial_altera_jtag.c +++ b/drivers/serial/serial_altera_jtag.c @@ -82,6 +82,7 @@ static int altera_serial_jtag_getc(struct console_device *cdev) } static int altera_serial_jtag_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; struct altera_serial_jtag_priv *priv; @@ -89,7 +90,10 @@ static int altera_serial_jtag_probe(struct device_d *dev) { priv = xzalloc(sizeof(*priv)); cdev = &priv->cdev; - priv->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = altera_serial_jtag_tstc; cdev->putc = altera_serial_jtag_putc; diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c index 59bb5b2ecf..676b9fadf8 100644 --- a/drivers/serial/serial_ar933x.c +++ b/drivers/serial/serial_ar933x.c @@ -156,15 +156,17 @@ static int ar933x_serial_getc(struct console_device *cdev) static int ar933x_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; struct ar933x_uart_priv *priv; u32 uart_cs; cdev = xzalloc(sizeof(struct console_device)); priv = xzalloc(sizeof(struct ar933x_uart_priv)); - priv->base = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->base = IOMEM(iores->start); dev->priv = priv; diff --git a/drivers/serial/serial_auart.c b/drivers/serial/serial_auart.c index 87b2e33ca3..9bef576cd7 100644 --- a/drivers/serial/serial_auart.c +++ b/drivers/serial/serial_auart.c @@ -180,6 +180,7 @@ static void auart_serial_init_port(struct auart_priv *priv) static int auart_serial_probe(struct device_d *dev) { + struct resource *iores; struct auart_priv *priv; struct console_device *cdev; @@ -194,9 +195,10 @@ static int auart_serial_probe(struct device_d *dev) cdev->dev = dev; dev->priv = priv; - priv->base = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->base = IOMEM(iores->start); priv->clk = clk_get(dev, NULL); if (IS_ERR(priv->clk)) return PTR_ERR(priv->clk); diff --git a/drivers/serial/serial_cadence.c b/drivers/serial/serial_cadence.c index 6b48a48d1f..36dfa20841 100644 --- a/drivers/serial/serial_cadence.c +++ b/drivers/serial/serial_cadence.c @@ -216,6 +216,7 @@ static int cadence_clocksource_clock_change(struct notifier_block *nb, static int cadence_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; struct cadence_serial_priv *priv; struct cadence_serial_devtype_data *devtype; @@ -239,11 +240,12 @@ static int cadence_serial_probe(struct device_d *dev) if (devtype->mode & CADENCE_MODE_CLK_REF_DIV) clk_set_rate(priv->clk, clk_get_rate(priv->clk) / 8); - priv->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->regs)) { - ret = PTR_ERR(priv->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto err_free; } + priv->regs = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = cadence_serial_tstc; diff --git a/drivers/serial/serial_digic.c b/drivers/serial/serial_digic.c index 235ea0ff47..06b6e15e0c 100644 --- a/drivers/serial/serial_digic.c +++ b/drivers/serial/serial_digic.c @@ -101,10 +101,14 @@ static int digic_serial_tstc(struct console_device *cdev) static int digic_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; cdev = xzalloc(sizeof(struct console_device)); - dev->priv = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + dev->priv = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = &digic_serial_tstc; cdev->putc = &digic_serial_putc; diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c index 68b438b0bb..f140310fdc 100644 --- a/drivers/serial/serial_imx.c +++ b/drivers/serial/serial_imx.c @@ -55,6 +55,7 @@ static struct imx_serial_devtype_data imx21_data = { struct imx_serial_priv { struct console_device cdev; int baudrate; + int dte_mode; struct notifier_block notify; void __iomem *regs; struct clk *clk; @@ -93,9 +94,12 @@ static int imx_serial_init_port(struct console_device *cdev) writel(0, regs + UBMR); writel(0, regs + priv->devtype->uts); - /* Configure FIFOs */ - writel(0xa81, regs + UFCR); + val = 0xa81; + if (priv->dte_mode) + val |= UFCR_DCEDTE; + + writel(val, regs + UFCR); if (priv->devtype->onems) @@ -202,6 +206,7 @@ static int imx_clocksource_clock_change(struct notifier_block *nb, static int imx_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; struct imx_serial_priv *priv; uint32_t val; @@ -224,7 +229,10 @@ static int imx_serial_probe(struct device_d *dev) goto err_free; } - priv->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = imx_serial_tstc; cdev->putc = imx_serial_putc; @@ -240,6 +248,9 @@ static int imx_serial_probe(struct device_d *dev) } } + if (of_property_read_bool(dev->device_node, "fsl,dte-mode")) + priv->dte_mode = 1; + imx_serial_init_port(cdev); /* Enable UART */ diff --git a/drivers/serial/serial_mpc5xxx.c b/drivers/serial/serial_mpc5xxx.c index 711163cefd..cc63a84c68 100644 --- a/drivers/serial/serial_mpc5xxx.c +++ b/drivers/serial/serial_mpc5xxx.c @@ -145,12 +145,14 @@ static int mpc5xxx_serial_tstc (struct console_device *cdev) static int mpc5xxx_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; cdev = xzalloc(sizeof(struct console_device)); - dev->priv = dev_request_mem_region(dev, 0); - if (IS_ERR(dev->priv)) - return PTR_ERR(dev->priv); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + dev->priv = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = mpc5xxx_serial_tstc; cdev->putc = mpc5xxx_serial_putc; diff --git a/drivers/serial/serial_netx.c b/drivers/serial/serial_netx.c index c659cfaaf3..55ed89bf92 100644 --- a/drivers/serial/serial_netx.c +++ b/drivers/serial/serial_netx.c @@ -133,10 +133,14 @@ static int netx_serial_tstc(struct console_device *cdev) static int netx_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; cdev = xzalloc(sizeof(struct console_device)); - dev->priv = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + dev->priv = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = netx_serial_tstc; cdev->putc = netx_serial_putc; diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index 1af226a76a..4ad52ea79c 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -321,6 +321,7 @@ static __maybe_unused struct ns16550_drvdata tegra_drvdata = { static int ns16550_init_iomem(struct device_d *dev, struct ns16550_priv *priv) { + struct resource *iores; struct resource *res; int width; @@ -328,9 +329,10 @@ static int ns16550_init_iomem(struct device_d *dev, struct ns16550_priv *priv) if (IS_ERR(res)) return PTR_ERR(res); - priv->mmiobase = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->mmiobase)) - return PTR_ERR(priv->mmiobase); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->mmiobase = IOMEM(iores->start); width = res->flags & IORESOURCE_MEM_TYPE_MASK; switch (width) { diff --git a/drivers/serial/serial_pl010.c b/drivers/serial/serial_pl010.c index 81cea776a6..06f9d2dcdc 100644 --- a/drivers/serial/serial_pl010.c +++ b/drivers/serial/serial_pl010.c @@ -135,10 +135,14 @@ static int pl010_tstc(struct console_device *cdev) static int pl010_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; cdev = xzalloc(sizeof(struct console_device)); - dev->priv = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + dev->priv = IOMEM(iores->start); cdev->dev = dev; cdev->tstc = pl010_tstc; cdev->putc = pl010_putc; diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c index 20ac4beb96..1a4d7b4303 100644 --- a/drivers/serial/serial_pxa.c +++ b/drivers/serial/serial_pxa.c @@ -161,12 +161,16 @@ static int pxa_serial_setbaudrate(struct console_device *cdev, int baudrate) static int pxa_serial_probe(struct device_d *dev) { + struct resource *iores; struct console_device *cdev; struct pxa_serial_priv *priv; priv = xzalloc(sizeof(*priv)); cdev = &priv->cdev; - priv->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); dev->priv = priv; cdev->dev = dev; diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c index 038193dcf4..0a6e22d971 100644 --- a/drivers/serial/serial_s3c.c +++ b/drivers/serial/serial_s3c.c @@ -176,12 +176,16 @@ static void s3c_serial_flush(struct console_device *cdev) static int s3c_serial_probe(struct device_d *dev) { + struct resource *iores; struct s3c_uart *priv; struct console_device *cdev; priv = xzalloc(sizeof(struct s3c_uart)); cdev = &priv->cdev; - priv->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); dev->priv = priv; cdev->dev = dev; cdev->tstc = s3c_serial_tstc; diff --git a/drivers/serial/stm-serial.c b/drivers/serial/stm-serial.c index 8bb242b14d..83328f4550 100644 --- a/drivers/serial/stm-serial.c +++ b/drivers/serial/stm-serial.c @@ -145,6 +145,7 @@ static int stm_serial_init_port(struct stm_priv *priv) static int stm_serial_probe(struct device_d *dev) { + struct resource *iores; struct stm_priv *priv; struct console_device *cdev; @@ -160,9 +161,10 @@ static int stm_serial_probe(struct device_d *dev) cdev->dev = dev; dev->priv = priv; - priv->base = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->base = IOMEM(iores->start); priv->clk = clk_get(dev, NULL); if (IS_ERR(priv->clk)) return PTR_ERR(priv->clk); diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index bf1add81fe..4506e2741d 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -206,6 +206,7 @@ static int altera_spi_transfer(struct spi_device *spi, struct spi_message *mesg) static int altera_spi_probe(struct device_d *dev) { + struct resource *iores; struct spi_master *master; struct altera_spi *altera_spi; struct spi_altera_master *pdata = dev->platform_data; @@ -221,9 +222,10 @@ static int altera_spi_probe(struct device_d *dev) master->num_chipselect = pdata->num_chipselect; master->bus_num = pdata->bus_num; - altera_spi->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(altera_spi->regs)) - return PTR_ERR(altera_spi->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + altera_spi->regs = IOMEM(iores->start); altera_spi->databits = pdata->databits; altera_spi->speed = pdata->speed; diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c index bdb39ef0cb..68b4c7c48e 100644 --- a/drivers/spi/ath79_spi.c +++ b/drivers/spi/ath79_spi.c @@ -233,6 +233,7 @@ static void ath79_spi_disable(struct ath79_spi *sp) static int ath79_spi_probe(struct device_d *dev) { + struct resource *iores; struct spi_master *master; struct ath79_spi *ath79_spi; @@ -263,7 +264,10 @@ static int ath79_spi_probe(struct device_d *dev) master->num_chipselect = num_cs; } - ath79_spi->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ath79_spi->regs = IOMEM(iores->start); /* enable gpio mode */ ath79_spi_enable(ath79_spi); diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index 0bf9d08b83..3f2c527d14 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -371,6 +371,7 @@ err: static int atmel_spi_probe(struct device_d *dev) { + struct resource *iores; int ret = 0; int i; struct spi_master *master; @@ -399,7 +400,10 @@ static int atmel_spi_probe(struct device_d *dev) master->transfer = atmel_spi_transfer; master->num_chipselect = pdata->num_chipselect; as->cs_pins = pdata->chipselect; - as->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + as->regs = IOMEM(iores->start); for (i = 0; i < master->num_chipselect; i++) { ret = gpio_request(as->cs_pins[i], dev_name(dev)); diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c index 2e489674d8..5bd1845fbb 100644 --- a/drivers/spi/imx_spi.c +++ b/drivers/spi/imx_spi.c @@ -538,6 +538,7 @@ static int imx_spi_dt_probe(struct imx_spi *imx) static int imx_spi_probe(struct device_d *dev) { + struct resource *iores; struct spi_master *master; struct imx_spi *imx; struct spi_imx_master *pdata = dev->platform_data; @@ -574,7 +575,10 @@ static int imx_spi_probe(struct device_d *dev) imx->chipselect = devdata->chipselect; imx->xchg_single = devdata->xchg_single; imx->do_transfer = devdata->do_transfer; - imx->regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + imx->regs = IOMEM(iores->start); if (devdata->init) devdata->init(imx); diff --git a/drivers/spi/mvebu_spi.c b/drivers/spi/mvebu_spi.c index bc0655f6a0..c679e64c42 100644 --- a/drivers/spi/mvebu_spi.c +++ b/drivers/spi/mvebu_spi.c @@ -332,6 +332,7 @@ static struct of_device_id mvebu_spi_dt_ids[] = { static int mvebu_spi_probe(struct device_d *dev) { + struct resource *iores; struct spi_master *master; struct mvebu_spi *priv; const struct of_device_id *match; @@ -342,11 +343,12 @@ static int mvebu_spi_probe(struct device_d *dev) return -EINVAL; priv = xzalloc(sizeof(*priv)); - priv->base = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->base)) { - ret = PTR_ERR(priv->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto err_free; } + priv->base = IOMEM(iores->start); priv->set_baudrate = (void *)match->data; priv->clk = clk_get(dev, NULL); if (IS_ERR(priv->clk)) { diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 9fe2fd4eaf..420d122b55 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -250,6 +250,7 @@ static int mxs_spi_transfer(struct spi_device *spi, struct spi_message *mesg) static int mxs_spi_probe(struct device_d *dev) { + struct resource *iores; struct spi_master *master; struct mxs_spi *mxs; @@ -264,9 +265,10 @@ static int mxs_spi_probe(struct device_d *dev) master->num_chipselect = 3; mxs->mode = SPI_CPOL | SPI_CPHA; - mxs->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(mxs->regs)) - return PTR_ERR(mxs->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + mxs->regs = IOMEM(iores->start); mxs->clk = clk_get(dev, NULL); if (IS_ERR(mxs->clk)) diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 8e29fde0bb..f63039718f 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -358,6 +358,7 @@ static int omap3_spi_probe_dt(struct device_d *dev, struct omap3_spi_master *oma static int omap3_spi_probe(struct device_d *dev) { + struct resource *iores; struct spi_master *master; struct omap3_spi_master *omap3_master; struct omap_spi_drvdata *devtype; @@ -399,7 +400,10 @@ static int omap3_spi_probe(struct device_d *dev) master->setup = omap3_spi_setup; master->transfer = omap3_spi_transfer; - omap3_master->base = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + omap3_master->base = IOMEM(iores->start); omap3_master->regs = omap3_master->base; omap3_master->regs += devtype->register_offset; diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c index b36ef19c8a..5f6bebc733 100644 --- a/drivers/usb/gadget/at91_udc.c +++ b/drivers/usb/gadget/at91_udc.c @@ -1379,6 +1379,7 @@ static void at91_udc_gadget_poll(struct usb_gadget *gadget) static int __init at91udc_probe(struct device_d *dev) { + struct resource *iores; struct at91_udc *udc = &controller; int retval; @@ -1422,7 +1423,10 @@ static int __init at91udc_probe(struct device_d *dev) udc->ep[3].maxpacket = 64; } - udc->udp_baseaddr = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + udc->udp_baseaddr = IOMEM(iores->start); if (IS_ERR(udc->udp_baseaddr)) { retval = PTR_ERR(udc->udp_baseaddr); goto fail0a; diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index bf28f7c22a..0df08c9a2b 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -23,6 +23,7 @@ #include <clock.h> #include <ioctl.h> #include <libbb.h> +#include <bbu.h> #include <boot.h> #include <dma.h> #include <fs.h> @@ -686,7 +687,21 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req, const char *cmd } if (filetype == filetype_ubi) { - char *cmd = asprintf("ubiformat -y -f %s %s", FASTBOOT_TMPFILE, filename); + char *cmd; + int fd; + struct mtd_info_user meminfo; + + fd = open(filename, O_RDONLY); + if (fd < 0) + goto copy; + + ret = ioctl(fd, MEMGETINFO, &meminfo); + close(fd); + /* Not a MTD device, ubiformat is not a valid operation */ + if (ret) + goto copy; + + cmd = asprintf("ubiformat -y -f %s %s", FASTBOOT_TMPFILE, filename); fastboot_tx_print(f_fb, "INFOThis is an UBI image..."); @@ -702,6 +717,37 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req, const char *cmd goto out; } + if (IS_ENABLED(CONFIG_BAREBOX_UPDATE) && filetype_is_barebox_image(filetype)) { + struct bbu_data data = { + .devicefile = filename, + .imagefile = FASTBOOT_TMPFILE, + .flags = BBU_FLAG_YES, + }; + + if (!barebox_update_handler_exists(&data)) + goto copy; + + fastboot_tx_print(f_fb, "INFOThis is a barebox image..."); + + data.image = read_file(data.imagefile, &data.len); + if (!data.image) { + fastboot_tx_print(f_fb, "FAILreading barebox"); + return; + } + + ret = barebox_update(&data); + + free(data.image); + + if (ret) { + fastboot_tx_print(f_fb, "FAILupdate barebox: %s", strerror(-ret)); + return; + } + + goto out; + } + +copy: ret = copy_file(FASTBOOT_TMPFILE, filename, 1); if (ret) { fastboot_tx_print(f_fb, "FAILwrite partition: %s", strerror(-ret)); diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c index 3db3480cad..372c07b418 100644 --- a/drivers/usb/gadget/pxa27x_udc.c +++ b/drivers/usb/gadget/pxa27x_udc.c @@ -1449,12 +1449,14 @@ static struct pxa_udc memory = { static int __init pxa_udc_probe(struct device_d *dev) { + struct resource *iores; struct pxa_udc *udc = &memory; int gpio, ret; - udc->regs = dev_request_mem_region(dev, 0); - if (!udc->regs) - return -ENXIO; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + udc->regs = IOMEM(iores->start); udc->dev = dev; udc->mach = dev->platform_data; diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c index 11b1a894e1..cc9636c4b7 100644 --- a/drivers/usb/host/ehci-atmel.c +++ b/drivers/usb/host/ehci-atmel.c @@ -46,6 +46,7 @@ static void atmel_stop_clock(void) static int atmel_ehci_probe(struct device_d *dev) { + struct resource *iores; struct ehci_data data; iclk = clk_get(dev, "ehci_clk"); @@ -67,7 +68,10 @@ static int atmel_ehci_probe(struct device_d *dev) data.flags = 0; - data.hccr = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + data.hccr = IOMEM(iores->start); ehci_register(dev, &data); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 91c6d73c30..b0bf9225ec 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1005,7 +1005,7 @@ static struct int_queue *ehci_create_int_queue(struct usb_device *dev, struct usb_host *host = dev->host; struct ehci_priv *ehci = to_ehci(host); struct int_queue *result = NULL; - uint32_t i, toggle; + uint32_t i; struct QH *list = ehci->periodic_queue; /* @@ -1057,8 +1057,6 @@ static struct int_queue *ehci_create_int_queue(struct usb_device *dev, memset(result->first, 0, sizeof(struct QH) * queuesize); memset(result->tds, 0, sizeof(struct qTD) * queuesize); - toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); - for (i = 0; i < queuesize; i++) { struct QH *qh = result->first + i; struct qTD *td = result->tds + i; @@ -1073,7 +1071,6 @@ static struct int_queue *ehci_create_int_queue(struct usb_device *dev, qh->qh_endpt1 = cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */ (usb_maxpacket(dev, pipe) << 16) | /* MPS */ - (1 << 14) | QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */ (usb_pipedevice(pipe) << 0)); @@ -1092,7 +1089,6 @@ static struct int_queue *ehci_create_int_queue(struct usb_device *dev, "communication direction is '%s'\n", usb_pipein(pipe) ? "in" : "out"); td->qt_token = cpu_to_hc32( - QT_TOKEN_DT(toggle) | (elementsize << 16) | ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */ 0x80); /* active */ @@ -1108,7 +1104,6 @@ static struct int_queue *ehci_create_int_queue(struct usb_device *dev, cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff); *buf = buffer + i * elementsize; - toggle ^= 1; } if (ehci->periodic_schedules > 0) { @@ -1144,8 +1139,7 @@ static void *ehci_poll_int_queue(struct usb_device *dev, { struct QH *cur = queue->current; struct qTD *cur_td; - uint32_t token, toggle; - unsigned long pipe = queue->pipe; + uint32_t token; /* depleted queue */ if (cur == NULL) { @@ -1162,9 +1156,6 @@ static void *ehci_poll_int_queue(struct usb_device *dev, return NULL; } - toggle = QT_TOKEN_GET_DT(token); - usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle); - if (!(cur->qh_link & QH_LINK_TERMINATE)) queue->current++; else @@ -1183,7 +1174,6 @@ static int ehci_destroy_int_queue(struct usb_device *dev, struct usb_host *host = dev->host; struct ehci_priv *ehci = to_ehci(host); struct QH *cur = ehci->periodic_queue; - uint64_t start; if (disable_periodic(ehci) < 0) { dev_err(&dev->dev, @@ -1192,7 +1182,6 @@ static int ehci_destroy_int_queue(struct usb_device *dev, } ehci->periodic_schedules--; - start = get_time_ns(); while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) { dev_dbg(&dev->dev, "considering %p, with qh_link %x\n", @@ -1205,12 +1194,6 @@ static int ehci_destroy_int_queue(struct usb_device *dev, break; } cur = NEXT_QH(cur); - if (is_timeout_non_interruptible(start, 500 * MSECOND)) { - dev_err(&dev->dev, - "Timeout destroying interrupt endpoint queue\n"); - result = -ETIMEDOUT; - goto out; - } } if (ehci->periodic_schedules > 0) { @@ -1334,6 +1317,7 @@ int ehci_register(struct device_d *dev, struct ehci_data *data) static int ehci_probe(struct device_d *dev) { + struct resource *iores; struct ehci_data data = {}; struct ehci_platform_data *pdata = dev->platform_data; struct device_node *dn = dev->device_node; @@ -1350,12 +1334,17 @@ static int ehci_probe(struct device_d *dev) */ data.flags = EHCI_HAS_TT; - data.hccr = dev_request_mem_region(dev, 0); - if (IS_ERR(data.hccr)) - return PTR_ERR(data.hccr); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + data.hccr = IOMEM(iores->start); - if (dev->num_resources > 1) - data.hcor = dev_request_mem_region(dev, 1); + if (dev->num_resources > 1) { + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + data.hcor = IOMEM(iores->start); + } else data.hcor = NULL; diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 1d511b7563..612c3a1033 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1793,6 +1793,7 @@ static int ohci_init(struct usb_host *host) static int ohci_probe(struct device_d *dev) { + struct resource *iores; struct usb_host *host; struct ohci *ohci; @@ -1818,9 +1819,10 @@ static int ohci_probe(struct device_d *dev) usb_register_host(host); - ohci->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(ohci->regs)) - return PTR_ERR(ohci->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ohci->regs = IOMEM(iores->start); return 0; } diff --git a/drivers/usb/host/xhci-hcd.c b/drivers/usb/host/xhci-hcd.c index a44a1a4dff..2b808cc875 100644 --- a/drivers/usb/host/xhci-hcd.c +++ b/drivers/usb/host/xhci-hcd.c @@ -1509,9 +1509,13 @@ int xhci_register(struct device_d *dev, struct xhci_data *data) static int xhci_probe(struct device_d *dev) { + struct resource *iores; struct xhci_data data = {}; - data.regs = dev_request_mem_region(dev, 0); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + data.regs = IOMEM(iores->start); return xhci_register(dev, &data); } diff --git a/drivers/usb/imx/chipidea-imx.c b/drivers/usb/imx/chipidea-imx.c index a1c36cf644..a799abe4ee 100644 --- a/drivers/usb/imx/chipidea-imx.c +++ b/drivers/usb/imx/chipidea-imx.c @@ -216,6 +216,7 @@ static int ci_register_otg_device(struct imx_chipidea *ci) static int imx_chipidea_probe(struct device_d *dev) { + struct resource *iores; struct imxusb_platformdata *pdata = dev->platform_data; int ret; void __iomem *base; @@ -245,9 +246,10 @@ static int imx_chipidea_probe(struct device_d *dev) if (!IS_ERR(ci->vbus)) regulator_enable(ci->vbus); - base = dev_request_mem_region(dev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); ci->base = base; diff --git a/drivers/usb/imx/imx-usb-misc.c b/drivers/usb/imx/imx-usb-misc.c index af1a32110c..d938a2cd87 100644 --- a/drivers/usb/imx/imx-usb-misc.c +++ b/drivers/usb/imx/imx-usb-misc.c @@ -545,6 +545,7 @@ int imx_usbmisc_port_post_init(int port, unsigned flags) static int imx_usbmisc_probe(struct device_d *dev) { + struct resource *iores; struct imx_usb_misc_data *devtype; int ret; @@ -552,9 +553,10 @@ static int imx_usbmisc_probe(struct device_d *dev) if (ret) return ret; - usbmisc_base = dev_request_mem_region(dev, 0); - if (!usbmisc_base) - return -ENOMEM; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + usbmisc_base = IOMEM(iores->start); imxusbmisc_data = devtype; diff --git a/drivers/usb/imx/imx-usb-phy.c b/drivers/usb/imx/imx-usb-phy.c index 837c1b5176..1aa12be29d 100644 --- a/drivers/usb/imx/imx-usb-phy.c +++ b/drivers/usb/imx/imx-usb-phy.c @@ -65,20 +65,23 @@ static int imx_usbphy_enable(struct imx_usbphy *imxphy) static int imx_usbphy_probe(struct device_d *dev) { + struct resource *iores; int ret; struct imx_usbphy *imxphy; imxphy = xzalloc(sizeof(*imxphy)); - imxphy->base = dev_request_mem_region(dev, 0); - if (!imxphy->base) { - ret = -ENODEV; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto err_free; } + imxphy->base = IOMEM(iores->start); imxphy->clk = clk_get(dev, NULL); if (IS_ERR(imxphy->clk)) { dev_err(dev, "could not get clk: %s\n", strerrorp(imxphy->clk)); + ret = PTR_ERR(imxphy->clk); goto err_clk; } diff --git a/drivers/usb/musb/musb_dsps.c b/drivers/usb/musb/musb_dsps.c index 958aeec685..431b97ea9b 100644 --- a/drivers/usb/musb/musb_dsps.c +++ b/drivers/usb/musb/musb_dsps.c @@ -349,6 +349,7 @@ static int dsps_register_otg_device(struct dsps_glue *glue) static int dsps_probe(struct device_d *dev) { + struct resource *iores; struct musb_hdrc_platform_data *pdata; struct musb_hdrc_config *config; struct device_node *dn = dev->device_node; @@ -378,13 +379,15 @@ static int dsps_probe(struct device_d *dev) pdata = &glue->pdata; - glue->musb.mregs = dev_request_mem_region(dev, 0); - if (IS_ERR(glue->musb.mregs)) - return PTR_ERR(glue->musb.mregs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + glue->musb.mregs = IOMEM(iores->start); - glue->musb.ctrl_base = dev_request_mem_region(dev, 1); - if (IS_ERR(glue->musb.ctrl_base)) - return PTR_ERR(glue->musb.ctrl_base); + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + glue->musb.ctrl_base = IOMEM(iores->start); glue->musb.controller = dev; diff --git a/drivers/usb/musb/phy-am335x-control.c b/drivers/usb/musb/phy-am335x-control.c index 809c5182c0..5fd8802b3a 100644 --- a/drivers/usb/musb/phy-am335x-control.c +++ b/drivers/usb/musb/phy-am335x-control.c @@ -129,6 +129,7 @@ EXPORT_SYMBOL(am335x_get_phy_control); static int am335x_control_usb_probe(struct device_d *dev) { + struct resource *iores; /*struct resource *res;*/ struct am335x_control_usb *ctrl_usb; const struct phy_control *phy_ctrl; @@ -146,13 +147,15 @@ static int am335x_control_usb_probe(struct device_d *dev) ctrl_usb->dev = dev; - ctrl_usb->phy_reg = dev_request_mem_region(dev, 0); - if (IS_ERR(ctrl_usb->phy_reg)) - return PTR_ERR(ctrl_usb->phy_reg); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ctrl_usb->phy_reg = IOMEM(iores->start); - ctrl_usb->wkup = dev_request_mem_region(dev, 1); - if (IS_ERR(ctrl_usb->wkup)) - return PTR_ERR(ctrl_usb->wkup); + iores = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ctrl_usb->wkup = IOMEM(iores->start); spin_lock_init(&ctrl_usb->lock); ctrl_usb->phy_ctrl = *phy_ctrl; diff --git a/drivers/usb/musb/phy-am335x.c b/drivers/usb/musb/phy-am335x.c index 2d58bbedb4..204e51054d 100644 --- a/drivers/usb/musb/phy-am335x.c +++ b/drivers/usb/musb/phy-am335x.c @@ -30,17 +30,19 @@ static int am335x_init(struct usb_phy *phy) static int am335x_phy_probe(struct device_d *dev) { + struct resource *iores; int ret; am_usbphy = xzalloc(sizeof(*am_usbphy)); if (!am_usbphy) return -ENOMEM; - am_usbphy->base = dev_request_mem_region(dev, 0); - if (!am_usbphy->base) { - ret = -ENODEV; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto err_free; } + am_usbphy->base = IOMEM(iores->start); am_usbphy->phy_ctrl = am335x_get_phy_control(dev); if (!am_usbphy->phy_ctrl) diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c index 76116af1da..555799ea4b 100644 --- a/drivers/video/atmel_lcdfb_core.c +++ b/drivers/video/atmel_lcdfb_core.c @@ -245,6 +245,7 @@ static struct fb_ops atmel_lcdc_ops = { int atmel_lcdc_register(struct device_d *dev, struct atmel_lcdfb_devdata *data) { + struct resource *iores; struct atmel_lcdfb_info *sinfo; struct atmel_lcdfb_platform_data *pdata = dev->platform_data; int ret = 0; @@ -257,9 +258,10 @@ int atmel_lcdc_register(struct device_d *dev, struct atmel_lcdfb_devdata *data) sinfo = xzalloc(sizeof(*sinfo)); sinfo->pdata = pdata; - sinfo->mmio = dev_request_mem_region(dev, 0); - if (IS_ERR(sinfo->mmio)) - return PTR_ERR(sinfo->mmio); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + sinfo->mmio = IOMEM(iores->start); sinfo->dev_data = data; diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c index 03d191a331..7c3a800149 100644 --- a/drivers/video/imx-ipu-fb.c +++ b/drivers/video/imx-ipu-fb.c @@ -988,6 +988,7 @@ static int sdc_fb_register_overlay(struct ipu_fb_info *fbi, void *fb) static int imxfb_probe(struct device_d *dev) { + struct resource *iores; struct ipu_fb_info *fbi; struct fb_info *info; const struct imx_ipu_fb_platform_data *pdata = dev->platform_data; @@ -1003,9 +1004,10 @@ static int imxfb_probe(struct device_d *dev) if (IS_ERR(fbi->clk)) return PTR_ERR(fbi->clk); - fbi->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(fbi->regs)) - return PTR_ERR(fbi->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + fbi->regs = IOMEM(iores->start); fbi->dev = dev; fbi->enable = pdata->enable; fbi->disp_data_fmt = pdata->disp_data_fmt; diff --git a/drivers/video/imx-ipu-v3/imx-hdmi.c b/drivers/video/imx-ipu-v3/imx-hdmi.c index 25fcb0c739..8b251a52ea 100644 --- a/drivers/video/imx-ipu-v3/imx-hdmi.c +++ b/drivers/video/imx-ipu-v3/imx-hdmi.c @@ -1271,6 +1271,7 @@ static int dw_hdmi_ioctl(struct vpl *vpl, unsigned int port, static int dw_hdmi_probe(struct device_d *dev) { + struct resource *iores; struct device_node *np = dev->device_node; struct dw_hdmi *hdmi; int ret; @@ -1293,9 +1294,10 @@ static int dw_hdmi_probe(struct device_d *dev) hdmi->ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); - hdmi->regs = dev_request_mem_region(dev, 0); - if (!hdmi->regs) - return -EBUSY; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + hdmi->regs = IOMEM(iores->start); hdmi->isfr_clk = clk_get(hdmi->dev, "isfr"); if (IS_ERR(hdmi->isfr_clk)) { diff --git a/drivers/video/imx-ipu-v3/ipu-common.c b/drivers/video/imx-ipu-v3/ipu-common.c index 70bb0e59b6..1811e50227 100644 --- a/drivers/video/imx-ipu-v3/ipu-common.c +++ b/drivers/video/imx-ipu-v3/ipu-common.c @@ -751,6 +751,7 @@ err_register: static int ipu_probe(struct device_d *dev) { + struct resource *iores; struct ipu_soc *ipu; void __iomem *ipu_base; int i, ret; @@ -760,9 +761,10 @@ static int ipu_probe(struct device_d *dev) if (ret) return ret; - ipu_base = dev_request_mem_region(dev, 0); - if (!ipu_base) - return -EBUSY; + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + ipu_base = IOMEM(iores->start); ipu = xzalloc(sizeof(*ipu)); diff --git a/drivers/video/imx.c b/drivers/video/imx.c index 11d49c6cfb..78cb5c0ca2 100644 --- a/drivers/video/imx.c +++ b/drivers/video/imx.c @@ -539,6 +539,7 @@ static int imxfb_register_overlay(struct imxfb_info *fbi, void *fb) static int imxfb_probe(struct device_d *dev) { + struct resource *iores; struct imxfb_info *fbi; struct fb_info *info; struct imx_fb_platform_data *pdata = dev->platform_data; @@ -573,9 +574,10 @@ static int imxfb_probe(struct device_d *dev) return PTR_ERR(fbi->ipg_clk); fbi->mode = pdata->mode; - fbi->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(fbi->regs)) - return PTR_ERR(fbi->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + fbi->regs = IOMEM(iores->start); fbi->pcr = pdata->mode->pcr; fbi->pwmr = pdata->pwmr; diff --git a/drivers/video/pxa.c b/drivers/video/pxa.c index e76404d9c9..d444e0981f 100644 --- a/drivers/video/pxa.c +++ b/drivers/video/pxa.c @@ -487,6 +487,7 @@ static struct fb_ops pxafb_ops = { static int pxafb_probe(struct device_d *dev) { + struct resource *iores; struct pxafb_platform_data *pdata = dev->platform_data; struct pxafb_info *fbi; struct fb_info *info; @@ -499,9 +500,10 @@ static int pxafb_probe(struct device_d *dev) info = &fbi->info; fbi->mode = pdata->mode; - fbi->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(fbi->regs)) - return PTR_ERR(fbi->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + fbi->regs = IOMEM(iores->start); fbi->dev = dev; fbi->lcd_power = pdata->lcd_power; diff --git a/drivers/video/s3c24xx.c b/drivers/video/s3c24xx.c index b1883e232c..84ed0aee39 100644 --- a/drivers/video/s3c24xx.c +++ b/drivers/video/s3c24xx.c @@ -358,13 +358,17 @@ static struct s3cfb_info fbi = { static int s3cfb_probe(struct device_d *hw_dev) { + struct resource *iores; struct s3c_fb_platform_data *pdata = hw_dev->platform_data; int ret; if (! pdata) return -ENODEV; - fbi.base = dev_request_mem_region(hw_dev, 0); + iores = dev_request_mem_resource(hw_dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + fbi.base = IOMEM(iores->start); writel(0, fbi.base + LCDCON1); writel(0, fbi.base + LCDCON5); /* FIXME not 0 for some displays */ diff --git a/drivers/video/stm.c b/drivers/video/stm.c index e5c1ef3974..0c190d36ae 100644 --- a/drivers/video/stm.c +++ b/drivers/video/stm.c @@ -505,6 +505,7 @@ static struct imxfb_info fbi = { static int stmfb_probe(struct device_d *hw_dev) { + struct resource *iores; struct imx_fb_platformdata *pdata = hw_dev->platform_data; int ret; @@ -513,7 +514,10 @@ static int stmfb_probe(struct device_d *hw_dev) /* add runtime hardware info */ fbi.hw_dev = hw_dev; - fbi.base = dev_request_mem_region(hw_dev, 0); + iores = dev_request_mem_resource(hw_dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + fbi.base = IOMEM(iores->start); fbi.clk = clk_get(hw_dev, NULL); if (IS_ERR(fbi.clk)) return PTR_ERR(fbi.clk); diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c index dfabee230c..03dc83408e 100644 --- a/drivers/watchdog/davinci_wdt.c +++ b/drivers/watchdog/davinci_wdt.c @@ -131,14 +131,16 @@ static int davinci_wdt_set_timeout(struct watchdog *wd, unsigned timeout) static int davinci_wdt_probe(struct device_d *dev) { + struct resource *iores; int ret = 0; struct davinci_wdt *davinci_wdt; davinci_wdt = xzalloc(sizeof(*davinci_wdt)); - davinci_wdt->base = dev_request_mem_region(dev, 0); - if (IS_ERR(davinci_wdt->base)) - return PTR_ERR(davinci_wdt->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + davinci_wdt->base = IOMEM(iores->start); davinci_wdt->clk = clk_get(dev, NULL); if (WARN_ON(IS_ERR(davinci_wdt->clk))) diff --git a/drivers/watchdog/im28wd.c b/drivers/watchdog/im28wd.c index 3510776a3a..1956fdb73d 100644 --- a/drivers/watchdog/im28wd.c +++ b/drivers/watchdog/im28wd.c @@ -189,13 +189,15 @@ static void __maybe_unused imx28_detect_reset_source(const struct imx28_wd *p) static int imx28_wd_probe(struct device_d *dev) { + struct resource *iores; struct imx28_wd *priv; int rc; priv = xzalloc(sizeof(struct imx28_wd)); - priv->regs = dev_request_mem_region(dev, 0); - if (IS_ERR(priv->regs)) - return PTR_ERR(priv->regs); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + priv->regs = IOMEM(iores->start); priv->wd.set_timeout = imx28_watchdog_set_timeout; priv->wd.dev = dev; diff --git a/drivers/watchdog/imxwd.c b/drivers/watchdog/imxwd.c index 1952548fa7..03e116ea20 100644 --- a/drivers/watchdog/imxwd.c +++ b/drivers/watchdog/imxwd.c @@ -173,6 +173,7 @@ static int imx21_wd_init(struct imx_wd *priv) static int imx_wd_probe(struct device_d *dev) { + struct resource *iores; struct imx_wd *priv; void *ops; int ret; @@ -182,11 +183,12 @@ static int imx_wd_probe(struct device_d *dev) return ret; priv = xzalloc(sizeof(struct imx_wd)); - priv->base = dev_request_mem_region(dev, 0); - if (!priv->base) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return -ENODEV; + return PTR_ERR(iores); } + priv->base = IOMEM(iores->start); priv->ops = ops; priv->wd.set_timeout = imx_watchdog_set_timeout; priv->wd.dev = dev; diff --git a/drivers/watchdog/jz4740.c b/drivers/watchdog/jz4740.c index 3d45b46ee2..f28bb9177a 100644 --- a/drivers/watchdog/jz4740.c +++ b/drivers/watchdog/jz4740.c @@ -67,14 +67,16 @@ static void __noreturn jz4740_reset_soc(struct restart_handler *rst) static int jz4740_wdt_probe(struct device_d *dev) { + struct resource *iores; struct jz4740_wdt_drvdata *priv; priv = xzalloc(sizeof(struct jz4740_wdt_drvdata)); - priv->base = dev_request_mem_region(dev, 0); - if (!priv->base) { + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { dev_err(dev, "could not get memory region\n"); - return -ENODEV; + return PTR_ERR(iores); } + priv->base = IOMEM(iores->start); dev->priv = priv; diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 06301b3b9e..27fdfd13a0 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -154,6 +154,7 @@ static int omap_wdt_set_timeout(struct watchdog *wdog, static int omap_wdt_probe(struct device_d *dev) { + struct resource *iores; struct omap_wdt_dev *wdev; int ret; @@ -162,11 +163,12 @@ static int omap_wdt_probe(struct device_d *dev) wdev->wdt_trgr_pattern = 0x1234; /* reserve static register mappings */ - wdev->base = dev_request_mem_region(dev, 0); - if (IS_ERR(wdev->base)) { - ret = PTR_ERR(wdev->base); + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); goto error; } + wdev->base = IOMEM(iores->start); wdev->timeout = TIMER_MARGIN_DEFAULT; diff --git a/dts/Bindings/clock/rockchip,rk3036-cru.txt b/dts/Bindings/clock/rockchip,rk3036-cru.txt index ace05992a2..20df350b9e 100644 --- a/dts/Bindings/clock/rockchip,rk3036-cru.txt +++ b/dts/Bindings/clock/rockchip,rk3036-cru.txt @@ -30,7 +30,7 @@ that they are defined using standard clock bindings with following clock-output-names: - "xin24m" - crystal input - required, - "ext_i2s" - external I2S clock - optional, - - "ext_gmac" - external GMAC clock - optional + - "rmii_clkin" - external EMAC clock - optional Example: Clock controller node: diff --git a/dts/Bindings/interrupt-controller/arm,gic-v3.txt b/dts/Bindings/interrupt-controller/arm,gic-v3.txt index 7803e77d85..007a5b4625 100644 --- a/dts/Bindings/interrupt-controller/arm,gic-v3.txt +++ b/dts/Bindings/interrupt-controller/arm,gic-v3.txt @@ -24,9 +24,8 @@ Main node required properties: 1 = edge triggered 4 = level triggered - Cells 4 and beyond are reserved for future use. When the 1st cell - has a value of 0 or 1, cells 4 and beyond act as padding, and may be - ignored. It is recommended that padding cells have a value of 0. + Cells 4 and beyond are reserved for future use and must have a value + of 0 if present. - reg : Specifies base physical address(s) and size of the GIC registers, in the following order: diff --git a/dts/Bindings/net/brcm,bcmgenet.txt b/dts/Bindings/net/brcm,bcmgenet.txt index 451fef26b4..10587bdadb 100644 --- a/dts/Bindings/net/brcm,bcmgenet.txt +++ b/dts/Bindings/net/brcm,bcmgenet.txt @@ -68,7 +68,7 @@ ethernet@f0b60000 { phy1: ethernet-phy@1 { max-speed = <1000>; reg = <0x1>; - compatible = "brcm,28nm-gphy", "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-ieee802.3-c22"; }; }; }; @@ -115,7 +115,7 @@ ethernet@f0ba0000 { phy0: ethernet-phy@0 { max-speed = <1000>; reg = <0x0>; - compatible = "brcm,bcm53125", "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-ieee802.3-c22"; }; }; }; diff --git a/dts/Bindings/net/hisilicon-hns-dsaf.txt b/dts/Bindings/net/hisilicon-hns-dsaf.txt index 80411b2f04..ecacfa44b1 100644 --- a/dts/Bindings/net/hisilicon-hns-dsaf.txt +++ b/dts/Bindings/net/hisilicon-hns-dsaf.txt @@ -4,8 +4,6 @@ Required properties: - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2". "hisilicon,hns-dsaf-v1" is for hip05. "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612. -- dsa-name: dsa fabric name who provide this interface. - should be "dsafX", X is the dsaf id. - mode: dsa fabric mode string. only support one of dsaf modes like these: "2port-64vf", "6port-16rss", @@ -26,9 +24,8 @@ Required properties: Example: -dsa: dsa@c7000000 { +dsaf0: dsa@c7000000 { compatible = "hisilicon,hns-dsaf-v1"; - dsa_name = "dsaf0"; mode = "6port-16rss"; interrupt-parent = <&mbigen_dsa>; reg = <0x0 0xC0000000 0x0 0x420000 diff --git a/dts/Bindings/net/hisilicon-hns-nic.txt b/dts/Bindings/net/hisilicon-hns-nic.txt index 41d19be701..e6a9d1c308 100644 --- a/dts/Bindings/net/hisilicon-hns-nic.txt +++ b/dts/Bindings/net/hisilicon-hns-nic.txt @@ -4,8 +4,9 @@ Required properties: - compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2". "hisilicon,hns-nic-v1" is for hip05. "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612. -- ae-name: accelerator name who provides this interface, - is simply a name referring to the name of name in the accelerator node. +- ae-handle: accelerator engine handle for hns, + specifies a reference to the associating hardware driver node. + see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt - port-id: is the index of port provided by DSAF (the accelerator). DSAF can connect to 8 PHYs. Port 0 to 1 are both used for adminstration purpose. They are called debug ports. @@ -41,7 +42,7 @@ Example: ethernet@0{ compatible = "hisilicon,hns-nic-v1"; - ae-name = "dsaf0"; + ae-handle = <&dsaf0>; port-id = <0>; local-mac-address = [a2 14 e4 4b 56 76]; }; diff --git a/dts/Bindings/net/marvell-armada-370-neta.txt b/dts/Bindings/net/marvell-armada-370-neta.txt index aeea50c84e..d0cb869396 100644 --- a/dts/Bindings/net/marvell-armada-370-neta.txt +++ b/dts/Bindings/net/marvell-armada-370-neta.txt @@ -6,12 +6,17 @@ Required properties: - interrupts: interrupt for the device - phy: See ethernet.txt file in the same directory. - phy-mode: See ethernet.txt file in the same directory -- clocks: a pointer to the reference clock for this device. +- clocks: List of clocks for this device. At least one clock is + mandatory for the core clock. If several clocks are given, then the + clock-names property must be used to identify them. Optional properties: - tx-csum-limit: maximum mtu supported by port that allow TX checksum. Value is presented in bytes. If not used, by default 1600B is set for "marvell,armada-370-neta" and 9800B for others. +- clock-names: List of names corresponding to clocks property; shall be + "core" for core clock and "bus" for the optional bus clock. + Example: diff --git a/dts/Bindings/net/mdio-mux-gpio.txt b/dts/Bindings/net/mdio-mux-gpio.txt index 79384113c2..694987d3c1 100644 --- a/dts/Bindings/net/mdio-mux-gpio.txt +++ b/dts/Bindings/net/mdio-mux-gpio.txt @@ -38,7 +38,6 @@ Example : phy11: ethernet-phy@1 { reg = <1>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, @@ -48,7 +47,6 @@ Example : }; phy12: ethernet-phy@2 { reg = <2>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, @@ -58,7 +56,6 @@ Example : }; phy13: ethernet-phy@3 { reg = <3>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, @@ -68,7 +65,6 @@ Example : }; phy14: ethernet-phy@4 { reg = <4>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, @@ -85,7 +81,6 @@ Example : phy21: ethernet-phy@1 { reg = <1>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, @@ -95,7 +90,6 @@ Example : }; phy22: ethernet-phy@2 { reg = <2>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, @@ -105,7 +99,6 @@ Example : }; phy23: ethernet-phy@3 { reg = <3>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, @@ -115,7 +108,6 @@ Example : }; phy24: ethernet-phy@4 { reg = <4>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, diff --git a/dts/Bindings/net/mdio-mux.txt b/dts/Bindings/net/mdio-mux.txt index f65606f8d6..491f5bd552 100644 --- a/dts/Bindings/net/mdio-mux.txt +++ b/dts/Bindings/net/mdio-mux.txt @@ -47,7 +47,6 @@ Example : phy11: ethernet-phy@1 { reg = <1>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, @@ -57,7 +56,6 @@ Example : }; phy12: ethernet-phy@2 { reg = <2>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, @@ -67,7 +65,6 @@ Example : }; phy13: ethernet-phy@3 { reg = <3>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, @@ -77,7 +74,6 @@ Example : }; phy14: ethernet-phy@4 { reg = <4>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, @@ -94,7 +90,6 @@ Example : phy21: ethernet-phy@1 { reg = <1>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, @@ -104,7 +99,6 @@ Example : }; phy22: ethernet-phy@2 { reg = <2>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, @@ -114,7 +108,6 @@ Example : }; phy23: ethernet-phy@3 { reg = <3>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, @@ -124,7 +117,6 @@ Example : }; phy24: ethernet-phy@4 { reg = <4>; - compatible = "marvell,88e1149r"; marvell,reg-init = <3 0x10 0 0x5777>, <3 0x11 0 0x00aa>, <3 0x12 0 0x4105>, diff --git a/dts/Bindings/net/phy.txt b/dts/Bindings/net/phy.txt index 525e1658f2..bc1c3c8bf8 100644 --- a/dts/Bindings/net/phy.txt +++ b/dts/Bindings/net/phy.txt @@ -17,8 +17,7 @@ Optional Properties: "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45 specifications. If neither of these are specified, the default is to - assume clause 22. The compatible list may also contain other - elements. + assume clause 22. If the phy's identifier is known then the list may contain an entry of the form: "ethernet-phy-idAAAA.BBBB" where @@ -28,6 +27,9 @@ Optional Properties: 4 hex digits. This is the chip vendor OUI bits 19:24, followed by 10 bits of a vendor specific ID. + The compatible list should not contain other values than those + listed here. + - max-speed: Maximum PHY supported speed (10, 100, 1000...) - broken-turn-around: If set, indicates the PHY device does not correctly diff --git a/dts/Bindings/pci/pci-rcar-gen2.txt b/dts/Bindings/pci/pci-rcar-gen2.txt index 4e8b90e43d..07a75094c5 100644 --- a/dts/Bindings/pci/pci-rcar-gen2.txt +++ b/dts/Bindings/pci/pci-rcar-gen2.txt @@ -8,6 +8,7 @@ OHCI and EHCI controllers. Required properties: - compatible: "renesas,pci-r8a7790" for the R8A7790 SoC; "renesas,pci-r8a7791" for the R8A7791 SoC; + "renesas,pci-r8a7793" for the R8A7793 SoC; "renesas,pci-r8a7794" for the R8A7794 SoC; "renesas,pci-rcar-gen2" for a generic R-Car Gen2 compatible device diff --git a/dts/Bindings/pci/rcar-pci.txt b/dts/Bindings/pci/rcar-pci.txt index 558fe528ae..6cf99690ee 100644 --- a/dts/Bindings/pci/rcar-pci.txt +++ b/dts/Bindings/pci/rcar-pci.txt @@ -4,6 +4,7 @@ Required properties: compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC; "renesas,pcie-r8a7790" for the R8A7790 SoC; "renesas,pcie-r8a7791" for the R8A7791 SoC; + "renesas,pcie-r8a7793" for the R8A7793 SoC; "renesas,pcie-r8a7795" for the R8A7795 SoC; "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device. diff --git a/dts/Bindings/rtc/s3c-rtc.txt b/dts/Bindings/rtc/s3c-rtc.txt index ac2fcd6ff4..1068ffce9f 100644 --- a/dts/Bindings/rtc/s3c-rtc.txt +++ b/dts/Bindings/rtc/s3c-rtc.txt @@ -14,6 +14,10 @@ Required properties: interrupt number is the rtc alarm interrupt and second interrupt number is the rtc tick interrupt. The number of cells representing a interrupt depends on the parent interrupt controller. +- clocks: Must contain a list of phandle and clock specifier for the rtc + and source clocks. +- clock-names: Must contain "rtc" and "rtc_src" entries sorted in the + same order as the clocks property. Example: @@ -21,4 +25,6 @@ Example: compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupts = <44 0 45 0>; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; }; diff --git a/dts/Bindings/serial/fsl-imx-uart.txt b/dts/Bindings/serial/fsl-imx-uart.txt index 35ae1fb353..ed94c217c9 100644 --- a/dts/Bindings/serial/fsl-imx-uart.txt +++ b/dts/Bindings/serial/fsl-imx-uart.txt @@ -9,7 +9,7 @@ Optional properties: - fsl,uart-has-rtscts : Indicate the uart has rts and cts - fsl,irda-mode : Indicate the uart supports irda mode - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works - is DCE mode by default. + in DCE mode by default. Note: Each uart controller should have an alias correctly numbered in "aliases" node. diff --git a/dts/Bindings/sound/fsl-asoc-card.txt b/dts/Bindings/sound/fsl-asoc-card.txt index ce55c0a6f7..4da41bf188 100644 --- a/dts/Bindings/sound/fsl-asoc-card.txt +++ b/dts/Bindings/sound/fsl-asoc-card.txt @@ -30,6 +30,8 @@ The compatible list for this generic sound card currently: "fsl,imx-audio-sgtl5000" (compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt) + "fsl,imx-audio-wm8960" + Required properties: - compatible : Contains one of entries in the compatible list. diff --git a/dts/Bindings/thermal/rcar-thermal.txt b/dts/Bindings/thermal/rcar-thermal.txt index 332e625f6e..e5ee3f1598 100644 --- a/dts/Bindings/thermal/rcar-thermal.txt +++ b/dts/Bindings/thermal/rcar-thermal.txt @@ -1,8 +1,9 @@ * Renesas R-Car Thermal Required properties: -- compatible : "renesas,thermal-<soctype>", "renesas,rcar-thermal" - as fallback. +- compatible : "renesas,thermal-<soctype>", + "renesas,rcar-gen2-thermal" (with thermal-zone) or + "renesas,rcar-thermal" (without thermal-zone) as fallback. Examples with soctypes are: - "renesas,thermal-r8a73a4" (R-Mobile APE6) - "renesas,thermal-r8a7779" (R-Car H1) @@ -36,3 +37,35 @@ thermal@e61f0000 { 0xe61f0300 0x38>; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; }; + +Example (with thermal-zone): + +thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + }; + }; +}; + +thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7790", + "renesas,rcar-gen2-thermal", + "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; + power-domains = <&cpg_clocks>; + #thermal-sensor-cells = <0>; +}; diff --git a/dts/include/dt-bindings/clock/tegra210-car.h b/dts/include/dt-bindings/clock/tegra210-car.h index 6f45aea49e..0a05b0d36a 100644 --- a/dts/include/dt-bindings/clock/tegra210-car.h +++ b/dts/include/dt-bindings/clock/tegra210-car.h @@ -126,7 +126,7 @@ /* 104 */ /* 105 */ #define TEGRA210_CLK_D_AUDIO 106 -/* 107 ( affects abp -> ape) */ +#define TEGRA210_CLK_APB2APE 107 /* 108 */ /* 109 */ /* 110 */ diff --git a/dts/src/arm/am33xx.dtsi b/dts/src/arm/am33xx.dtsi index 04885f9f95..1fafaad516 100644 --- a/dts/src/arm/am33xx.dtsi +++ b/dts/src/arm/am33xx.dtsi @@ -439,6 +439,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; mbox_wkupm3: wkup_m3 { + ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; }; diff --git a/dts/src/arm/am4372.dtsi b/dts/src/arm/am4372.dtsi index df955ba4dc..92068fbf8b 100644 --- a/dts/src/arm/am4372.dtsi +++ b/dts/src/arm/am4372.dtsi @@ -73,7 +73,7 @@ global_timer: timer@48240200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x48240200 0x100>; - interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; interrupt-parent = <&gic>; clocks = <&mpu_periphclk>; }; @@ -81,7 +81,7 @@ local_timer: timer@48240600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x48240600 0x100>; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>; interrupt-parent = <&gic>; clocks = <&mpu_periphclk>; }; @@ -290,6 +290,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; mbox_wkupm3: wkup_m3 { + ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; }; diff --git a/dts/src/arm/am437x-gp-evm.dts b/dts/src/arm/am437x-gp-evm.dts index 64d43325bc..ecd09ab6d5 100644 --- a/dts/src/arm/am437x-gp-evm.dts +++ b/dts/src/arm/am437x-gp-evm.dts @@ -590,8 +590,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pixcir_ts_pins>; reg = <0x5c>; - interrupt-parent = <&gpio3>; - interrupts = <22 0>; attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; @@ -599,7 +597,7 @@ * 0x264 represents the offset of padconf register of * gpio3_22 from am43xx_pinmux base. */ - interrupts-extended = <&gpio3 22 IRQ_TYPE_NONE>, + interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>, <&am43xx_pinmux 0x264>; interrupt-names = "tsc", "wakeup"; diff --git a/dts/src/arm/am43x-epos-evm.dts b/dts/src/arm/am43x-epos-evm.dts index 746fd2b179..d580e2b70f 100644 --- a/dts/src/arm/am43x-epos-evm.dts +++ b/dts/src/arm/am43x-epos-evm.dts @@ -491,7 +491,7 @@ pinctrl-0 = <&pixcir_ts_pins>; reg = <0x5c>; interrupt-parent = <&gpio1>; - interrupts = <17 0>; + interrupts = <17 IRQ_TYPE_EDGE_FALLING>; attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; diff --git a/dts/src/arm/am57xx-cl-som-am57x.dts b/dts/src/arm/am57xx-cl-som-am57x.dts index c53882643a..8d93882dc8 100644 --- a/dts/src/arm/am57xx-cl-som-am57x.dts +++ b/dts/src/arm/am57xx-cl-som-am57x.dts @@ -167,7 +167,7 @@ DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLUP | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ + DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ >; }; @@ -492,14 +492,14 @@ pinctrl-names = "default"; pinctrl-0 = <&qspi1_pins>; - spi-max-frequency = <20000000>; + spi-max-frequency = <48000000>; spi_flash: spi_flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spansion,m25p80", "jedec,spi-nor"; reg = <0>; /* CS0 */ - spi-max-frequency = <20000000>; + spi-max-frequency = <48000000>; partition@0 { label = "uboot"; @@ -559,13 +559,13 @@ &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii"; + phy-mode = "rgmii-txid"; dual_emac_res_vlan = <0>; }; &cpsw_emac1 { phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-txid"; dual_emac_res_vlan = <1>; }; @@ -588,7 +588,7 @@ }; &usb2 { - dr_mode = "peripheral"; + dr_mode = "host"; }; &mcasp3 { diff --git a/dts/src/arm/am57xx-sbc-am57x.dts b/dts/src/arm/am57xx-sbc-am57x.dts index 77bb8e1740..988e99632d 100644 --- a/dts/src/arm/am57xx-sbc-am57x.dts +++ b/dts/src/arm/am57xx-sbc-am57x.dts @@ -25,8 +25,8 @@ &dra7_pmx_core { uart3_pins_default: uart3_pins_default { pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */ + DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ + DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ >; }; @@ -108,9 +108,9 @@ pinctrl-0 = <&i2c5_pins_default>; clock-frequency = <400000>; - eeprom_base: atmel@50 { + eeprom_base: atmel@54 { compatible = "atmel,24c08"; - reg = <0x50>; + reg = <0x54>; pagesize = <16>; }; diff --git a/dts/src/arm/armada-xp-lenovo-ix4-300d.dts b/dts/src/arm/armada-xp-lenovo-ix4-300d.dts index 13cf69a8d0..fb9e1bbf23 100644 --- a/dts/src/arm/armada-xp-lenovo-ix4-300d.dts +++ b/dts/src/arm/armada-xp-lenovo-ix4-300d.dts @@ -152,6 +152,7 @@ nand-on-flash-bbt; partitions { + compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/src/arm/at91-sama5d2_xplained.dts b/dts/src/arm/at91-sama5d2_xplained.dts index 77ddff0364..e683856c50 100644 --- a/dts/src/arm/at91-sama5d2_xplained.dts +++ b/dts/src/arm/at91-sama5d2_xplained.dts @@ -114,9 +114,15 @@ macb0: ethernet@f8008000 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_default>; + pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; phy-mode = "rmii"; status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioA>; + interrupts = <73 IRQ_TYPE_LEVEL_LOW>; + }; }; pdmic@f8018000 { @@ -300,6 +306,10 @@ bias-disable; }; + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PC9__GPIO>; + }; + pinctrl_pdmic_default: pdmic_default { pinmux = <PIN_PB26__PDMIC_DAT>, <PIN_PB27__PDMIC_CLK>; diff --git a/dts/src/arm/at91-sama5d4_xplained.dts b/dts/src/arm/at91-sama5d4_xplained.dts index 131614f28e..569026e8f9 100644 --- a/dts/src/arm/at91-sama5d4_xplained.dts +++ b/dts/src/arm/at91-sama5d4_xplained.dts @@ -86,10 +86,12 @@ macb0: ethernet@f8020000 { phy-mode = "rmii"; status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; phy0: ethernet-phy@1 { interrupt-parent = <&pioE>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; reg = <1>; }; }; @@ -152,6 +154,10 @@ atmel,pins = <AT91_PIOE 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; }; + pinctrl_macb0_phy_irq: macb0_phy_irq_0 { + atmel,pins = + <AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; }; }; }; diff --git a/dts/src/arm/at91-sama5d4ek.dts b/dts/src/arm/at91-sama5d4ek.dts index 2d4a33100a..4e98cda974 100644 --- a/dts/src/arm/at91-sama5d4ek.dts +++ b/dts/src/arm/at91-sama5d4ek.dts @@ -160,8 +160,15 @@ }; macb0: ethernet@f8020000 { + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; phy-mode = "rmii"; status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioE>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; }; mmc1: mmc@fc000000 { @@ -193,6 +200,10 @@ pinctrl@fc06a000 { board { + pinctrl_macb0_phy_irq: macb0_phy_irq { + atmel,pins = + <AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; pinctrl_mmc0_cd: mmc0_cd { atmel,pins = <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; diff --git a/dts/src/arm/at91sam9n12ek.dts b/dts/src/arm/at91sam9n12ek.dts index ca4ddf8681..626c67d666 100644 --- a/dts/src/arm/at91sam9n12ek.dts +++ b/dts/src/arm/at91sam9n12ek.dts @@ -215,7 +215,7 @@ }; panel: panel { - compatible = "qd,qd43003c0-40", "simple-panel"; + compatible = "qiaodian,qd43003c0-40", "simple-panel"; backlight = <&backlight>; power-supply = <&panel_reg>; #address-cells = <1>; diff --git a/dts/src/arm/kirkwood-lswvl.dts b/dts/src/arm/kirkwood-lswvl.dts index 09eed3cea0..36eec7392a 100644 --- a/dts/src/arm/kirkwood-lswvl.dts +++ b/dts/src/arm/kirkwood-lswvl.dts @@ -1,7 +1,8 @@ /* * Device Tree file for Buffalo Linkstation LS-WVL/VL * - * Copyright (C) 2015, rogershimizu@gmail.com + * Copyright (C) 2015, 2016 + * Roger Shimizu <rogershimizu@gmail.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -156,21 +157,21 @@ button@1 { label = "Function Button"; linux,code = <KEY_OPTION>; - gpios = <&gpio0 45 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; }; button@2 { label = "Power-on Switch"; linux,code = <KEY_RESERVED>; linux,input-type = <5>; - gpios = <&gpio0 46 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; button@3 { label = "Power-auto Switch"; linux,code = <KEY_ESC>; linux,input-type = <5>; - gpios = <&gpio0 47 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; }; @@ -185,38 +186,38 @@ led@1 { label = "lswvl:red:alarm"; - gpios = <&gpio0 36 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; led@2 { label = "lswvl:red:func"; - gpios = <&gpio0 37 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; }; led@3 { label = "lswvl:amber:info"; - gpios = <&gpio0 38 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; }; led@4 { label = "lswvl:blue:func"; - gpios = <&gpio0 39 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; led@5 { label = "lswvl:blue:power"; - gpios = <&gpio0 40 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; default-state = "keep"; }; led@6 { label = "lswvl:red:hdderr0"; - gpios = <&gpio0 34 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; }; led@7 { label = "lswvl:red:hdderr1"; - gpios = <&gpio0 35 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; }; }; @@ -233,7 +234,7 @@ 3250 1 5000 0>; - alarm-gpios = <&gpio0 43 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; restart_poweroff { diff --git a/dts/src/arm/kirkwood-lswxl.dts b/dts/src/arm/kirkwood-lswxl.dts index f5db16a085..b13ec20a70 100644 --- a/dts/src/arm/kirkwood-lswxl.dts +++ b/dts/src/arm/kirkwood-lswxl.dts @@ -1,7 +1,8 @@ /* * Device Tree file for Buffalo Linkstation LS-WXL/WSXL * - * Copyright (C) 2015, rogershimizu@gmail.com + * Copyright (C) 2015, 2016 + * Roger Shimizu <rogershimizu@gmail.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -156,21 +157,21 @@ button@1 { label = "Function Button"; linux,code = <KEY_OPTION>; - gpios = <&gpio1 41 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; }; button@2 { label = "Power-on Switch"; linux,code = <KEY_RESERVED>; linux,input-type = <5>; - gpios = <&gpio1 42 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; button@3 { label = "Power-auto Switch"; linux,code = <KEY_ESC>; linux,input-type = <5>; - gpios = <&gpio1 43 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; }; @@ -185,12 +186,12 @@ led@1 { label = "lswxl:blue:func"; - gpios = <&gpio1 36 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; }; led@2 { label = "lswxl:red:alarm"; - gpios = <&gpio1 49 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; led@3 { @@ -200,23 +201,23 @@ led@4 { label = "lswxl:blue:power"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + default-state = "keep"; }; led@5 { label = "lswxl:red:func"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - default-state = "keep"; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; }; led@6 { label = "lswxl:red:hdderr0"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; }; led@7 { label = "lswxl:red:hdderr1"; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; }; @@ -225,15 +226,15 @@ pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; pinctrl-names = "default"; - gpios = <&gpio0 47 GPIO_ACTIVE_LOW - &gpio0 48 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW + &gpio1 15 GPIO_ACTIVE_LOW>; gpio-fan,speed-map = <0 3 1500 2 3250 1 5000 0>; - alarm-gpios = <&gpio1 49 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; restart_poweroff { @@ -256,7 +257,7 @@ enable-active-high; regulator-always-on; regulator-boot-on; - gpio = <&gpio0 37 GPIO_ACTIVE_HIGH>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; }; hdd_power0: regulator@2 { compatible = "regulator-fixed"; diff --git a/dts/src/arm/kirkwood-pogoplug-series-4.dts b/dts/src/arm/kirkwood-pogoplug-series-4.dts index 1db6f2c506..8082d64266 100644 --- a/dts/src/arm/kirkwood-pogoplug-series-4.dts +++ b/dts/src/arm/kirkwood-pogoplug-series-4.dts @@ -131,6 +131,7 @@ chip-delay = <40>; status = "okay"; partitions { + compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/src/arm/logicpd-torpedo-som.dtsi b/dts/src/arm/logicpd-torpedo-som.dtsi index 7fed0bd4f3..0080532236 100644 --- a/dts/src/arm/logicpd-torpedo-som.dtsi +++ b/dts/src/arm/logicpd-torpedo-som.dtsi @@ -112,14 +112,6 @@ clock-frequency = <400000>; }; -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; -}; - /* * Only found on the wireless SOM. For the SOM without wireless, the pins for * MMC3 can be routed with jumpers to the second MMC slot on the devkit and @@ -143,6 +135,7 @@ interrupt-parent = <&gpio5>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */ ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; }; }; diff --git a/dts/src/arm/omap5-board-common.dtsi b/dts/src/arm/omap5-board-common.dtsi index 888412c63f..902657d671 100644 --- a/dts/src/arm/omap5-board-common.dtsi +++ b/dts/src/arm/omap5-board-common.dtsi @@ -130,6 +130,16 @@ }; }; +&gpio8 { + /* TI trees use GPIO instead of msecure, see also muxing */ + p234 { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "gpio8_234/msecure"; + }; +}; + &omap5_pmx_core { pinctrl-names = "default"; pinctrl-0 = < @@ -213,6 +223,13 @@ >; }; + /* TI trees use GPIO mode; msecure mode does not work reliably? */ + palmas_msecure_pins: palmas_msecure_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */ + >; + }; + usbhost_pins: pinmux_usbhost_pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ @@ -278,6 +295,12 @@ &usbhost_wkup_pins >; + palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1 */ + >; + }; + usbhost_wkup_pins: pinmux_usbhost_wkup_pins { pinctrl-single,pins = < OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ @@ -345,6 +368,8 @@ interrupt-controller; #interrupt-cells = <2>; ti,system-power-controller; + pinctrl-names = "default"; + pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>; extcon_usb3: palmas_usb { compatible = "ti,palmas-usb-vid"; @@ -358,6 +383,14 @@ #clock-cells = <0>; }; + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 IRQ_TYPE_NONE>; + ti,backup-battery-chargeable; + ti,backup-battery-charge-high-current; + }; + palmas_pmic { compatible = "ti,palmas-pmic"; interrupt-parent = <&palmas>; diff --git a/dts/src/arm/orion5x-linkstation-lswtgl.dts b/dts/src/arm/orion5x-linkstation-lswtgl.dts index 3daec912b4..420788229e 100644 --- a/dts/src/arm/orion5x-linkstation-lswtgl.dts +++ b/dts/src/arm/orion5x-linkstation-lswtgl.dts @@ -1,7 +1,8 @@ /* * Device Tree file for Buffalo Linkstation LS-WTGL * - * Copyright (C) 2015, Roger Shimizu <rogershimizu@gmail.com> + * Copyright (C) 2015, 2016 + * Roger Shimizu <rogershimizu@gmail.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -69,8 +70,6 @@ internal-regs { pinctrl: pinctrl@10000 { - pinctrl-0 = <&pmx_usb_power &pmx_power_hdd - &pmx_fan_low &pmx_fan_high &pmx_fan_lock>; pinctrl-names = "default"; pmx_led_power: pmx-leds { @@ -162,6 +161,7 @@ led@1 { label = "lswtgl:blue:power"; gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + default-state = "keep"; }; led@2 { @@ -188,7 +188,7 @@ 3250 1 5000 0>; - alarm-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; }; restart_poweroff { diff --git a/dts/src/arm/sama5d4.dtsi b/dts/src/arm/sama5d4.dtsi index b8032bca46..db1151c184 100644 --- a/dts/src/arm/sama5d4.dtsi +++ b/dts/src/arm/sama5d4.dtsi @@ -1342,7 +1342,7 @@ dbgu: serial@fc069000 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfc069000 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; clocks = <&dbgu_clk>; diff --git a/dts/src/arm/ste-nomadik-stn8815.dtsi b/dts/src/arm/ste-nomadik-stn8815.dtsi index d0c7438533..27a333eb89 100644 --- a/dts/src/arm/ste-nomadik-stn8815.dtsi +++ b/dts/src/arm/ste-nomadik-stn8815.dtsi @@ -127,22 +127,14 @@ }; mmcsd_default_mode: mmcsd_default { mmcsd_default_cfg1 { - /* MCCLK */ - pins = "GPIO8_B10"; - ste,output = <0>; - }; - mmcsd_default_cfg2 { - /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 */ - pins = "GPIO10_C11", "GPIO15_A12", - "GPIO16_C13", "GPIO23_D15"; - ste,output = <1>; - }; - mmcsd_default_cfg3 { - /* MCCMD, MCDAT3-0, MCMSFBCLK */ - pins = "GPIO9_A10", "GPIO11_B11", - "GPIO12_A11", "GPIO13_C12", - "GPIO14_B12", "GPIO24_C15"; - ste,input = <1>; + /* + * MCCLK, MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 + * MCCMD, MCDAT3-0, MCMSFBCLK + */ + pins = "GPIO8_B10", "GPIO9_A10", "GPIO10_C11", "GPIO11_B11", + "GPIO12_A11", "GPIO13_C12", "GPIO14_B12", "GPIO15_A12", + "GPIO16_C13", "GPIO23_D15", "GPIO24_C15"; + ste,output = <2>; }; }; }; @@ -802,10 +794,21 @@ clock-names = "mclk", "apb_pclk"; interrupt-parent = <&vica>; interrupts = <22>; - max-frequency = <48000000>; + max-frequency = <400000>; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + full-pwr-cycle; + /* + * The STw4811 circuit used with the Nomadik strictly + * requires that all of these signal direction pins be + * routed and used for its 4-bit levelshifter. + */ + st,sig-dir-dat0; + st,sig-dir-dat2; + st,sig-dir-dat31; + st,sig-dir-cmd; + st,sig-pin-fbclk; pinctrl-names = "default"; pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; vmmc-supply = <&vmmc_regulator>; diff --git a/dts/src/arm64/arm/juno-base.dtsi b/dts/src/arm64/arm/juno-base.dtsi index dd5158eb58..e5b59ca9de 100644 --- a/dts/src/arm64/arm/juno-base.dtsi +++ b/dts/src/arm64/arm/juno-base.dtsi @@ -115,6 +115,7 @@ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/src/arm64/hisilicon/hip05_hns.dtsi b/dts/src/arm64/hisilicon/hip05_hns.dtsi index da7b6e6132..933cba3599 100644 --- a/dts/src/arm64/hisilicon/hip05_hns.dtsi +++ b/dts/src/arm64/hisilicon/hip05_hns.dtsi @@ -23,9 +23,8 @@ soc0: soc@000000000 { }; }; - dsa: dsa@c7000000 { + dsaf0: dsa@c7000000 { compatible = "hisilicon,hns-dsaf-v1"; - dsa_name = "dsaf0"; mode = "6port-16rss"; interrupt-parent = <&mbigen_dsa>; @@ -127,7 +126,7 @@ soc0: soc@000000000 { eth0: ethernet@0{ compatible = "hisilicon,hns-nic-v1"; - ae-name = "dsaf0"; + ae-handle = <&dsaf0>; port-id = <0>; local-mac-address = [00 00 00 01 00 58]; status = "disabled"; @@ -135,14 +134,14 @@ soc0: soc@000000000 { }; eth1: ethernet@1{ compatible = "hisilicon,hns-nic-v1"; - ae-name = "dsaf0"; + ae-handle = <&dsaf0>; port-id = <1>; status = "disabled"; dma-coherent; }; eth2: ethernet@2{ compatible = "hisilicon,hns-nic-v1"; - ae-name = "dsaf0"; + ae-handle = <&dsaf0>; port-id = <2>; local-mac-address = [00 00 00 01 00 5a]; status = "disabled"; @@ -150,7 +149,7 @@ soc0: soc@000000000 { }; eth3: ethernet@3{ compatible = "hisilicon,hns-nic-v1"; - ae-name = "dsaf0"; + ae-handle = <&dsaf0>; port-id = <3>; local-mac-address = [00 00 00 01 00 5b]; status = "disabled"; @@ -158,7 +157,7 @@ soc0: soc@000000000 { }; eth4: ethernet@4{ compatible = "hisilicon,hns-nic-v1"; - ae-name = "dsaf0"; + ae-handle = <&dsaf0>; port-id = <4>; local-mac-address = [00 00 00 01 00 5c]; status = "disabled"; @@ -166,7 +165,7 @@ soc0: soc@000000000 { }; eth5: ethernet@5{ compatible = "hisilicon,hns-nic-v1"; - ae-name = "dsaf0"; + ae-handle = <&dsaf0>; port-id = <5>; local-mac-address = [00 00 00 01 00 5d]; status = "disabled"; @@ -174,7 +173,7 @@ soc0: soc@000000000 { }; eth6: ethernet@6{ compatible = "hisilicon,hns-nic-v1"; - ae-name = "dsaf0"; + ae-handle = <&dsaf0>; port-id = <6>; local-mac-address = [00 00 00 01 00 5e]; status = "disabled"; @@ -182,7 +181,7 @@ soc0: soc@000000000 { }; eth7: ethernet@7{ compatible = "hisilicon,hns-nic-v1"; - ae-name = "dsaf0"; + ae-handle = <&dsaf0>; port-id = <7>; local-mac-address = [00 00 00 01 00 5f]; status = "disabled"; diff --git a/dts/src/arm64/nvidia/tegra132-norrin.dts b/dts/src/arm64/nvidia/tegra132-norrin.dts index 7dfe1c0859..62f33fc84e 100644 --- a/dts/src/arm64/nvidia/tegra132-norrin.dts +++ b/dts/src/arm64/nvidia/tegra132-norrin.dts @@ -12,6 +12,8 @@ rtc1 = "/rtc@0,7000e000"; }; + chosen { }; + memory { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x80000000>; diff --git a/dts/src/mips/brcm/bcm6328.dtsi b/dts/src/mips/brcm/bcm6328.dtsi index 459b9b252c..d61b1616b6 100644 --- a/dts/src/mips/brcm/bcm6328.dtsi +++ b/dts/src/mips/brcm/bcm6328.dtsi @@ -74,6 +74,7 @@ timer: timer@10000040 { compatible = "syscon"; reg = <0x10000040 0x2c>; + little-endian; }; reboot { diff --git a/dts/src/mips/brcm/bcm7125.dtsi b/dts/src/mips/brcm/bcm7125.dtsi index 4fc7ecee27..1a7efa883c 100644 --- a/dts/src/mips/brcm/bcm7125.dtsi +++ b/dts/src/mips/brcm/bcm7125.dtsi @@ -98,6 +98,7 @@ sun_top_ctrl: syscon@404000 { compatible = "brcm,bcm7125-sun-top-ctrl", "syscon"; reg = <0x404000 0x60c>; + little-endian; }; reboot { diff --git a/dts/src/mips/brcm/bcm7346.dtsi b/dts/src/mips/brcm/bcm7346.dtsi index a3039bb534..d4bf52cfcf 100644 --- a/dts/src/mips/brcm/bcm7346.dtsi +++ b/dts/src/mips/brcm/bcm7346.dtsi @@ -118,6 +118,7 @@ sun_top_ctrl: syscon@404000 { compatible = "brcm,bcm7346-sun-top-ctrl", "syscon"; reg = <0x404000 0x51c>; + little-endian; }; reboot { diff --git a/dts/src/mips/brcm/bcm7358.dtsi b/dts/src/mips/brcm/bcm7358.dtsi index 4274ff41ec..8e2501694d 100644 --- a/dts/src/mips/brcm/bcm7358.dtsi +++ b/dts/src/mips/brcm/bcm7358.dtsi @@ -112,6 +112,7 @@ sun_top_ctrl: syscon@404000 { compatible = "brcm,bcm7358-sun-top-ctrl", "syscon"; reg = <0x404000 0x51c>; + little-endian; }; reboot { diff --git a/dts/src/mips/brcm/bcm7360.dtsi b/dts/src/mips/brcm/bcm7360.dtsi index 0dcc9163c2..7e5f76040f 100644 --- a/dts/src/mips/brcm/bcm7360.dtsi +++ b/dts/src/mips/brcm/bcm7360.dtsi @@ -112,6 +112,7 @@ sun_top_ctrl: syscon@404000 { compatible = "brcm,bcm7360-sun-top-ctrl", "syscon"; reg = <0x404000 0x51c>; + little-endian; }; reboot { diff --git a/dts/src/mips/brcm/bcm7362.dtsi b/dts/src/mips/brcm/bcm7362.dtsi index 2f3f9fc2c4..c739ea77ac 100644 --- a/dts/src/mips/brcm/bcm7362.dtsi +++ b/dts/src/mips/brcm/bcm7362.dtsi @@ -118,6 +118,7 @@ sun_top_ctrl: syscon@404000 { compatible = "brcm,bcm7362-sun-top-ctrl", "syscon"; reg = <0x404000 0x51c>; + little-endian; }; reboot { diff --git a/dts/src/mips/brcm/bcm7420.dtsi b/dts/src/mips/brcm/bcm7420.dtsi index bee221b3b5..5f55d0a50a 100644 --- a/dts/src/mips/brcm/bcm7420.dtsi +++ b/dts/src/mips/brcm/bcm7420.dtsi @@ -99,6 +99,7 @@ sun_top_ctrl: syscon@404000 { compatible = "brcm,bcm7420-sun-top-ctrl", "syscon"; reg = <0x404000 0x60c>; + little-endian; }; reboot { diff --git a/dts/src/mips/brcm/bcm7425.dtsi b/dts/src/mips/brcm/bcm7425.dtsi index 571f30f52e..e24d41ab4e 100644 --- a/dts/src/mips/brcm/bcm7425.dtsi +++ b/dts/src/mips/brcm/bcm7425.dtsi @@ -100,6 +100,7 @@ sun_top_ctrl: syscon@404000 { compatible = "brcm,bcm7425-sun-top-ctrl", "syscon"; reg = <0x404000 0x51c>; + little-endian; }; reboot { diff --git a/dts/src/mips/brcm/bcm7435.dtsi b/dts/src/mips/brcm/bcm7435.dtsi index 614ee211f7..8b9432cc06 100644 --- a/dts/src/mips/brcm/bcm7435.dtsi +++ b/dts/src/mips/brcm/bcm7435.dtsi @@ -114,6 +114,7 @@ sun_top_ctrl: syscon@404000 { compatible = "brcm,bcm7425-sun-top-ctrl", "syscon"; reg = <0x404000 0x51c>; + little-endian; }; reboot { diff --git a/fs/devfs-core.c b/fs/devfs-core.c index 88a7e3a1d6..deacaaad3f 100644 --- a/fs/devfs-core.c +++ b/fs/devfs-core.c @@ -259,7 +259,7 @@ int cdev_ioctl(struct cdev *cdev, int request, void *buf) return cdev->ops->ioctl(cdev, request, buf); } -int cdev_erase(struct cdev *cdev, size_t count, loff_t offset) +int cdev_erase(struct cdev *cdev, loff_t count, loff_t offset) { if (!cdev->ops->erase) return -ENOSYS; diff --git a/fs/devfs.c b/fs/devfs.c index 0b8d4fd246..6fabcf8ffa 100644 --- a/fs/devfs.c +++ b/fs/devfs.c @@ -66,7 +66,7 @@ static loff_t devfs_lseek(struct device_d *_dev, FILE *f, loff_t pos) return ret - cdev->offset; } -static int devfs_erase(struct device_d *_dev, FILE *f, size_t count, loff_t offset) +static int devfs_erase(struct device_d *_dev, FILE *f, loff_t count, loff_t offset) { struct cdev *cdev = f->priv; @@ -527,7 +527,7 @@ int efi_fs_probe(struct efi_device *efidev) BS->handle_protocol(efi_loaded_image->device_handle, &efi_simple_file_system_protocol_guid, (void*)&volume); - if (efidev->protocol == volume) + if (efi_loaded_image && efidev->protocol == volume) path = xstrdup("/boot"); else path = asprintf("/efi%d", index); diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index 590f54d5d8..1ecbb8dfb7 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -127,7 +127,8 @@ int ext4fs_read_inode(struct ext2_data *data, int ino, struct ext2_inode *inode) return 0; } -int ext4fs_get_indir_block(struct ext2fs_node *node, struct ext4fs_indir_block *indir, int blkno) +static int ext4fs_get_indir_block(struct ext2fs_node *node, + struct ext4fs_indir_block *indir, int blkno) { struct ext_filesystem *fs = node->data->fs; int blksz; diff --git a/fs/fat/fat.c b/fs/fat/fat.c index ece937d443..49cd78ff92 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -1,7 +1,7 @@ /* - * ramfs.c - a malloc based filesystem + * fat.c - FAT filesystem barebox driver * - * Copyright (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * Copyright (c) 2011 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix * * See file CREDITS for list of people who contributed to this * project. @@ -924,7 +924,7 @@ out: } EXPORT_SYMBOL(lseek); -int erase(int fd, size_t count, loff_t offset) +int erase(int fd, loff_t count, loff_t offset) { struct fs_driver_d *fsdrv; FILE *f; diff --git a/images/Makefile.am33xx b/images/Makefile.am33xx index 375ff9094f..6c7e81a9dc 100644 --- a/images/Makefile.am33xx +++ b/images/Makefile.am33xx @@ -47,6 +47,12 @@ FILE_barebox-am33xx-phytec-phycore-mlo-256mb.spi.img = start_am33xx_phytec_phyco am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-mlo-256mb.img am33xx-mlospi-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-mlo-256mb.spi.img +pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycore_r2_sram_256mb +FILE_barebox-am33xx-phytec-phycore-r2-mlo-256mb.img = start_am33xx_phytec_phycore_r2_sram_256mb.pblx.mlo +FILE_barebox-am33xx-phytec-phycore-r2-mlo-256mb.spi.img = start_am33xx_phytec_phycore_r2_sram_256mb.pblx.mlospi +am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-r2-mlo-256mb.img +am33xx-mlospi-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-r2-mlo-256mb.spi.img + pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycore_sram_128mb FILE_barebox-am33xx-phytec-phycore-mlo-128mb.img = start_am33xx_phytec_phycore_sram_128mb.pblx.mlo FILE_barebox-am33xx-phytec-phycore-mlo-128mb.spi.img = start_am33xx_phytec_phycore_sram_128mb.pblx.mlospi @@ -59,6 +65,12 @@ FILE_barebox-am33xx-phytec-phycore-mlo-512mb.spi.img = start_am33xx_phytec_phyco am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-mlo-512mb.img am33xx-mlospi-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-mlo-512mb.spi.img +pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycore_r2_sram_512mb +FILE_barebox-am33xx-phytec-phycore-r2-mlo-512mb.img = start_am33xx_phytec_phycore_r2_sram_512mb.pblx.mlo +FILE_barebox-am33xx-phytec-phycore-r2-mlo-512mb.spi.img = start_am33xx_phytec_phycore_r2_sram_512mb.pblx.mlospi +am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-r2-mlo-512mb.img +am33xx-mlospi-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-r2-mlo-512mb.spi.img + pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycore_sram_2x512mb FILE_barebox-am33xx-phytec-phycore-mlo-2x512mb.img = start_am33xx_phytec_phycore_sram_2x512mb.pblx.mlo FILE_barebox-am33xx-phytec-phycore-mlo-2x512mb.spi.img = start_am33xx_phytec_phycore_sram_2x512mb.pblx.mlospi diff --git a/images/Makefile.imx b/images/Makefile.imx index 4ab2dcb57f..6870bce4ca 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -288,6 +288,11 @@ CFG_start_imx6dl_tx6x_1g.pblx.imximg = $(board)/karo-tx6x/flash-header-tx6dl-1g. FILE_barebox-karo-imx6dl-tx6x-1g.img = start_imx6dl_tx6x_1g.pblx.imximg image-$(CONFIG_MACH_TX6X) += barebox-karo-imx6dl-tx6x-1g.img +pblx-$(CONFIG_MACH_TX6X) += start_imx6q_tx6x_1g +CFG_start_imx6q_tx6x_1g.pblx.imximg = $(board)/karo-tx6x/flash-header-tx6q-1g.imxcfg +FILE_barebox-karo-imx6q-tx6x-1g.img = start_imx6q_tx6x_1g.pblx.imximg +image-$(CONFIG_MACH_TX6X) += barebox-karo-imx6q-tx6x-1g.img + pblx-$(CONFIG_MACH_UDOO) += start_imx6_udoo CFG_start_imx6_udoo.pblx.imximg = $(board)/udoo/flash-header-mx6-udoo.imxcfg FILE_barebox-udoo-imx6q.img = start_imx6_udoo.pblx.imximg diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga index f295c673ad..d52b909ff3 100644 --- a/images/Makefile.socfpga +++ b/images/Makefile.socfpga @@ -11,7 +11,7 @@ $(obj)/%.socfpgaimg: $(obj)/% FORCE $(call if_changed,socfpga_image) # ----------------------- Cyclone5 based boards --------------------------- -pblx-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCKDK) += start_socfpga_socdk_xload +pblx-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += start_socfpga_socdk_xload FILE_barebox-socfpga-socdk-xload.img = start_socfpga_socdk_xload.pblx.socfpgaimg socfpga-xload-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += barebox-socfpga-socdk-xload.img @@ -19,6 +19,14 @@ pblx-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += start_socfpga_socdk FILE_barebox-socfpga-socdk.img = start_socfpga_socdk.pblx socfpga-barebox-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += barebox-socfpga-socdk.img +pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += start_socfpga_de0_nano_soc_xload +FILE_barebox-socfpga-de0_nano_soc-xload.img = start_socfpga_de0_nano_soc_xload.pblx.socfpgaimg +socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += barebox-socfpga-de0_nano_soc-xload.img + +pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += start_socfpga_de0_nano_soc +FILE_barebox-socfpga-de0_nano_soc.img = start_socfpga_de0_nano_soc.pblx +socfpga-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += barebox-socfpga-de0_nano_soc.img + pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += start_socfpga_sockit_xload FILE_barebox-socfpga-sockit-xload.img = start_socfpga_sockit_xload.pblx.socfpgaimg socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit-xload.img diff --git a/include/bbu.h b/include/bbu.h index 7277911718..0fe7a1a9bc 100644 --- a/include/bbu.h +++ b/include/bbu.h @@ -36,6 +36,8 @@ int bbu_confirm(struct bbu_data *); int barebox_update(struct bbu_data *); +bool barebox_update_handler_exists(struct bbu_data *); + void bbu_handlers_list(void); #ifdef CONFIG_BAREBOX_UPDATE diff --git a/include/driver.h b/include/driver.h index 31c673452f..80aa8d821c 100644 --- a/include/driver.h +++ b/include/driver.h @@ -203,10 +203,16 @@ void *dev_get_mem_region(struct device_d *dev, int num); /* * exlusively request register base 'num' for a device + * deprecated, use dev_request_mem_resource instead */ void __iomem *dev_request_mem_region(struct device_d *dev, int num); /* + * exlusively request resource 'num' for a device + */ +struct resource *dev_request_mem_resource(struct device_d *dev, int num); + +/* * exlusively request register base 'num' for a device * will return NULL on error * only used on platform like at91 where the Ressource address collision with @@ -425,7 +431,7 @@ struct file_operations { int (*open)(struct cdev*, unsigned long flags); int (*close)(struct cdev*); int (*flush)(struct cdev*); - int (*erase)(struct cdev*, size_t count, loff_t offset); + int (*erase)(struct cdev*, loff_t count, loff_t offset); int (*protect)(struct cdev*, size_t count, loff_t offset, int prot); int (*memmap)(struct cdev*, void **map, int flags); }; @@ -470,7 +476,7 @@ int cdev_flush(struct cdev *cdev); ssize_t cdev_read(struct cdev *cdev, void *buf, size_t count, loff_t offset, ulong flags); ssize_t cdev_write(struct cdev *cdev, const void *buf, size_t count, loff_t offset, ulong flags); int cdev_ioctl(struct cdev *cdev, int cmd, void *buf); -int cdev_erase(struct cdev *cdev, size_t count, loff_t offset); +int cdev_erase(struct cdev *cdev, loff_t count, loff_t offset); #define DEVFS_PARTITION_FIXED (1U << 0) #define DEVFS_PARTITION_READONLY (1U << 1) diff --git a/include/filetype.h b/include/filetype.h index cde543e5b0..e87ca174a8 100644 --- a/include/filetype.h +++ b/include/filetype.h @@ -2,6 +2,7 @@ #define __FILE_TYPE_H #include <linux/string.h> +#include <linux/types.h> /* * List of file types we know @@ -48,6 +49,7 @@ enum filetype file_name_detect_type(const char *filename); enum filetype cdev_detect_type(const char *name); enum filetype is_fat_or_mbr(const unsigned char *sector, unsigned long *bootsec); int is_fat_boot_sector(const void *_buf); +bool filetype_is_barebox_image(enum filetype ft); #define ARM_HEAD_SIZE 0x30 #define ARM_HEAD_MAGICWORD_OFFSET 0x20 diff --git a/include/fs.h b/include/fs.h index 23156eadae..9f4164ed77 100644 --- a/include/fs.h +++ b/include/fs.h @@ -70,7 +70,7 @@ struct fs_driver_d { int (*stat)(struct device_d *dev, const char *file, struct stat *stat); int (*ioctl)(struct device_d *dev, FILE *f, int request, void *buf); - int (*erase)(struct device_d *dev, FILE *f, size_t count, + int (*erase)(struct device_d *dev, FILE *f, loff_t count, loff_t offset); int (*protect)(struct device_d *dev, FILE *f, size_t count, loff_t offset, int prot); @@ -145,7 +145,7 @@ int mount (const char *device, const char *fsname, const char *path, int umount(const char *pathname); /* not-so-standard functions */ -int erase(int fd, size_t count, loff_t offset); +int erase(int fd, loff_t count, loff_t offset); int protect(int fd, size_t count, loff_t offset, int prot); int protect_file(const char *file, int prot); void *memmap(int fd, int flags); diff --git a/include/linux/circ_buf.h b/include/linux/circ_buf.h new file mode 100644 index 0000000000..90f2471dc6 --- /dev/null +++ b/include/linux/circ_buf.h @@ -0,0 +1,36 @@ +/* + * See Documentation/circular-buffers.txt for more information. + */ + +#ifndef _LINUX_CIRC_BUF_H +#define _LINUX_CIRC_BUF_H 1 + +struct circ_buf { + char *buf; + int head; + int tail; +}; + +/* Return count in buffer. */ +#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1)) + +/* Return space available, 0..size-1. We always leave one free char + as a completely full buffer has head == tail, which is the same as + empty. */ +#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size)) + +/* Return count up to the end of the buffer. Carefully avoid + accessing head and tail more than once, so they can change + underneath us without returning inconsistent results. */ +#define CIRC_CNT_TO_END(head,tail,size) \ + ({int end = (size) - (tail); \ + int n = ((head) + end) & ((size)-1); \ + n < end ? n : end;}) + +/* Return space available up to the end of the buffer. */ +#define CIRC_SPACE_TO_END(head,tail,size) \ + ({int end = (size) - 1 - (head); \ + int n = (end + (tail)) & ((size)-1); \ + n <= end ? n : end+1;}) + +#endif /* _LINUX_CIRC_BUF_H */ diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h index c46605d5e3..8e778df173 100644 --- a/include/linux/mtd/mtd-abi.h +++ b/include/linux/mtd/mtd-abi.h @@ -10,13 +10,13 @@ #include <asm-generic/div64.h> struct erase_info_user { - uint32_t start; - uint32_t length; + uint64_t start; + uint64_t length; }; struct mtd_oob_buf { - uint32_t start; - uint32_t length; + uint64_t start; + uint64_t length; unsigned char *ptr; }; diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 7e828bc98f..421a941aad 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -26,14 +26,16 @@ #define MTD_ERASE_DONE 0x08 #define MTD_ERASE_FAILED 0x10 +#define MTD_FAIL_ADDR_UNKNOWN -1LL + /* If the erase fails, fail_addr might indicate exactly which block failed. If fail_addr = 0xffffffff, the failure was not at the device level or was not specific to any particular block. */ struct erase_info { struct mtd_info *mtd; - u_int32_t addr; - u_int32_t len; - u_int32_t fail_addr; + u_int64_t addr; + u_int64_t len; + u_int64_t fail_addr; u_long time; u_long retries; u_int dev; @@ -45,7 +47,7 @@ struct erase_info { }; struct mtd_erase_region_info { - u_int32_t offset; /* At which this region starts, from the beginning of the MTD */ + u_int64_t offset; /* At which this region starts, from the beginning of the MTD */ u_int32_t erasesize; /* For this region */ u_int32_t numblocks; /* Number of blocks of erasesize in this region */ unsigned long *lockmap; /* If keeping bitmap of locks */ diff --git a/include/net/ep93xx_eth.h b/include/net/ep93xx_eth.h new file mode 100644 index 0000000000..0fb11d0acd --- /dev/null +++ b/include/net/ep93xx_eth.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Alexander Kurz <akurz@blala.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __NET_EP93XX_ETH_H +#define __NET_EP93XX_ETH_H + +#include <linux/phy.h> + +struct ep93xx_eth_platform_data { + phy_interface_t xcv_type; + int phy_addr; +}; + +#endif /* __NET_EP93XX_ETH_H */ diff --git a/include/of.h b/include/of.h index 75cc3c11c1..8c8f57a7cc 100644 --- a/include/of.h +++ b/include/of.h @@ -249,6 +249,7 @@ int of_find_path(struct device_node *node, const char *propname, char **outpath, int of_find_path_by_node(struct device_node *node, char **outpath, unsigned flags); int of_register_fixup(int (*fixup)(struct device_node *, void *), void *context); int of_unregister_fixup(int (*fixup)(struct device_node *, void *), void *context); +int of_register_set_status_fixup(const char *node, bool status); struct device_node *of_find_node_by_alias(struct device_node *root, const char *alias); struct device_node *of_find_node_by_path_or_alias(struct device_node *root, diff --git a/include/serial/imx-uart.h b/include/serial/imx-uart.h index 8faa12f24b..29b117c51f 100644 --- a/include/serial/imx-uart.h +++ b/include/serial/imx-uart.h @@ -84,6 +84,7 @@ #define UFCR_RFDIV2 (0b100<<7) /* Reference freq divider mask */ #define UFCR_RFDIV1 (0b101<<7) /* Reference freq divider mask */ #define UFCR_RFDIV7 (0b110<<7) /* Reference freq divider mask */ +#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ #define USR1_RTSS (1<<14) /* RTS pin status */ diff --git a/lib/process_escape_sequence.c b/lib/process_escape_sequence.c index 1bfd0702f5..3747da11fd 100644 --- a/lib/process_escape_sequence.c +++ b/lib/process_escape_sequence.c @@ -18,6 +18,7 @@ */ #include <common.h> #include <fs.h> +#include <globalvar.h> #include <libbb.h> #include <shell.h> @@ -57,6 +58,11 @@ int process_escape_sequence(const char *source, char *dest, int destlen) case 'h': i += snprintf(dest + i, destlen - i, "%s", barebox_get_model()); break; + case 'u': + if (IS_ENABLED(CONFIG_GLOBALVAR)) + i += snprintf(dest + i, destlen - i, "%s", + dev_get_param(&global_device, "user")); + break; case 'w': i += snprintf(dest + i, destlen - i, "%s", getcwd()); break; |