diff options
| -rw-r--r-- | dts/Bindings/clock/clock-bindings.txt | 16 | ||||
| -rw-r--r-- | dts/Bindings/input/input-reset.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/media/rockchip-vpu.txt | 29 | ||||
| -rw-r--r-- | dts/src/arc/hsdk.dts | 15 | ||||
| -rw-r--r-- | dts/src/arm64/qcom/sdm845-mtp.dts | 6 |
5 files changed, 38 insertions, 30 deletions
diff --git a/dts/Bindings/clock/clock-bindings.txt b/dts/Bindings/clock/clock-bindings.txt index 2ec489eebe..b646bbcf7f 100644 --- a/dts/Bindings/clock/clock-bindings.txt +++ b/dts/Bindings/clock/clock-bindings.txt @@ -168,3 +168,19 @@ a shared clock is forbidden. Configuration of common clocks, which affect multiple consumer devices can be similarly specified in the clock provider node. + +==Protected clocks== + +Some platforms or firmwares may not fully expose all the clocks to the OS, such +as in situations where those clks are used by drivers running in ARM secure +execution levels. Such a configuration can be specified in device tree with the +protected-clocks property in the form of a clock specifier list. This property should +only be specified in the node that is providing the clocks being protected: + + clock-controller@a000f000 { + compatible = "vendor,clk95; + reg = <0xa000f000 0x1000> + #clocks-cells = <1>; + ... + protected-clocks = <UART3_CLK>, <SPI5_CLK>; + }; diff --git a/dts/Bindings/input/input-reset.txt b/dts/Bindings/input/input-reset.txt index 2bb2626fdb..1ca6cc5ebf 100644 --- a/dts/Bindings/input/input-reset.txt +++ b/dts/Bindings/input/input-reset.txt @@ -12,7 +12,7 @@ The /chosen node should contain a 'linux,sysrq-reset-seq' child node to define a set of keys. Required property: -sysrq-reset-seq: array of Linux keycodes, one keycode per cell. +keyset: array of Linux keycodes, one keycode per cell. Optional property: timeout-ms: duration keys must be pressed together in milliseconds before diff --git a/dts/Bindings/media/rockchip-vpu.txt b/dts/Bindings/media/rockchip-vpu.txt deleted file mode 100644 index 35dc464ad7..0000000000 --- a/dts/Bindings/media/rockchip-vpu.txt +++ /dev/null @@ -1,29 +0,0 @@ -device-tree bindings for rockchip VPU codec - -Rockchip (Video Processing Unit) present in various Rockchip platforms, -such as RK3288 and RK3399. - -Required properties: -- compatible: value should be one of the following - "rockchip,rk3288-vpu"; - "rockchip,rk3399-vpu"; -- interrupts: encoding and decoding interrupt specifiers -- interrupt-names: should be "vepu" and "vdpu" -- clocks: phandle to VPU aclk, hclk clocks -- clock-names: should be "aclk" and "hclk" -- power-domains: phandle to power domain node -- iommus: phandle to a iommu node - -Example: -SoC-specific DT entry: - vpu: video-codec@ff9a0000 { - compatible = "rockchip,rk3288-vpu"; - reg = <0x0 0xff9a0000 0x0 0x800>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "hclk"; - power-domains = <&power RK3288_PD_VIDEO>; - iommus = <&vpu_mmu>; - }; diff --git a/dts/src/arc/hsdk.dts b/dts/src/arc/hsdk.dts index ef149f5992..43f17b51ee 100644 --- a/dts/src/arc/hsdk.dts +++ b/dts/src/arc/hsdk.dts @@ -222,6 +222,21 @@ bus-width = <4>; dma-coherent; }; + + gpio: gpio@3000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x3000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_port_a: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + }; + }; }; memory@80000000 { diff --git a/dts/src/arm64/qcom/sdm845-mtp.dts b/dts/src/arm64/qcom/sdm845-mtp.dts index d667eee4e6..b3def03581 100644 --- a/dts/src/arm64/qcom/sdm845-mtp.dts +++ b/dts/src/arm64/qcom/sdm845-mtp.dts @@ -343,6 +343,12 @@ }; }; +&gcc { + protected-clocks = <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>; +}; + &i2c10 { status = "okay"; clock-frequency = <400000>; |