diff options
153 files changed, 2109 insertions, 745 deletions
diff --git a/Documentation/boards/stm32mp.rst b/Documentation/boards/stm32mp.rst index 6f4b14049a..0c9615b290 100644 --- a/Documentation/boards/stm32mp.rst +++ b/Documentation/boards/stm32mp.rst @@ -28,7 +28,9 @@ Building barebox There's a single ``stm32mp_defconfig`` for all STM32MP boards:: - make ARCH=arm stm32mp_defconfig + export ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- + make stm32mp_defconfig + make The resulting images will be placed under ``images/``:: diff --git a/Documentation/user/remote-control.rst b/Documentation/user/remote-control.rst index c8b7442f17..43f1fb3118 100644 --- a/Documentation/user/remote-control.rst +++ b/Documentation/user/remote-control.rst @@ -54,7 +54,7 @@ account via: .. code-block:: sh - pip install --user crcmod enum enum34 + python2 -m pip install --user crcmod enum enum34 configuring bbremote ^^^^^^^^^^^^^^^^^^^^ @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 2022 -PATCHLEVEL = 04 +PATCHLEVEL = 05 SUBLEVEL = 0 EXTRAVERSION = NAME = None diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 75e15cbda4..d303999614 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -77,6 +77,7 @@ obj-$(CONFIG_MACH_MB7707) += module-mb7707/ obj-$(CONFIG_MACH_MIOA701) += mioa701/ obj-$(CONFIG_MACH_MX23EVK) += freescale-mx23-evk/ obj-$(CONFIG_MACH_MX28EVK) += freescale-mx28-evk/ +obj-$(CONFIG_MACH_MYIRTECH_X335X) += myirtech-x335x/ obj-$(CONFIG_MACH_NESO) += guf-neso/ obj-$(CONFIG_MACH_NETGEAR_RN104) += netgear-rn104/ obj-$(CONFIG_MACH_NETGEAR_RN2120) += netgear-rn2120/ diff --git a/arch/arm/boards/archosg9/board.c b/arch/arm/boards/archosg9/board.c index 3289cfda3d..597830432b 100644 --- a/arch/arm/boards/archosg9/board.c +++ b/arch/arm/boards/archosg9/board.c @@ -5,10 +5,10 @@ #include <init.h> #include <asm/armlinux.h> #include <generated/mach-types.h> +#include <mach/devices.h> #include <mach/omap4-silicon.h> #include <mach/omap4-devices.h> #include <mach/omap4_rom_usb.h> -#include <mach/omap-fb.h> #include <linux/sizes.h> #include <i2c/i2c.h> #include <gpio.h> diff --git a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg index f11387b023..bd869ec29e 100644 --- a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg +++ b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg @@ -2,13 +2,13 @@ /* MDMISC mirroring interleaved (row/bank/col) */ wm 32 MX6_MMDC_P0_MDMISC 0x00000742 -check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002 +check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 -check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 wm 32 MX6_MMDC_P0_MDCTL 0x831a0000 -check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333 wm 32 MX6_MMDC_P0_MDCFG1 0x926e8a63 @@ -36,7 +36,7 @@ wm 32 MX6_MMDC_P0_MDSCR 0x04008010 wm 32 MX6_MMDC_P0_MDSCR 0x04008040 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390001 -check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1380000 wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001e001e @@ -64,11 +64,11 @@ wm 32 MX6_MMDC_P1_MPWRDLCTL 0x40404040 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000 -check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x80000000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000 wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000 -check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x80000000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000 wm 32 MX6_MMDC_P0_MPDGCTRL0 0x50800000 -check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x10001000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x10001000 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 @@ -83,16 +83,16 @@ wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f -check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x00008033 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b wm 32 MX6_MMDC_P0_MDREF 0x00001800 @@ -100,4 +100,4 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00001006 wm 32 MX6_MMDC_P0_MDPDC 0x0002556d wm 32 MX6_MMDC_P1_MDPDC 0x0002556d wm 32 MX6_MMDC_P0_MDSCR 0x00000000 -check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg index c327b5f0c1..51f600d490 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg @@ -94,11 +94,10 @@ wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 wm 32 MX6_MMDC_P0_MDMISC 0x00000742 -check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002 +check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000 wm 32 MX6_MMDC_P0_MDCTL 0x83190000 -check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000 wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333 wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8a63 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db @@ -119,7 +118,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001 wm 32 MX6_MMDC_P0_MDSCR 0x04008010 wm 32 MX6_MMDC_P0_MDSCR 0x04008040 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 -check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000 wm 32 MX6_MMDC_P0_MDSCR 0x00048033 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 @@ -128,14 +127,14 @@ wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x00008033 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b wm 32 MX6_MMDC_P0_MDREF 0x00001800 wm 32 MX6_MMDC_P0_MAPSR 0x00001000 wm 32 MX6_MMDC_P0_MDPDC 0x0002556d wm 32 MX6_MMDC_P0_MDSCR 0x00000000 -check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg index 9c8196d4da..697ce45480 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg @@ -121,11 +121,11 @@ wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 wm 32 MX6_MMDC_P0_MDMISC 0x00000742 -check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002 +check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 -check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 wm 32 MX6_MMDC_P0_MDCTL 0x831a0000 -check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 wm 32 MX6_MMDC_P0_MDCFG0 0x545a79a4 wm 32 MX6_MMDC_P0_MDCFG1 0xff538e64 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00dd @@ -147,7 +147,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001 wm 32 MX6_MMDC_P0_MDSCR 0x04008010 wm 32 MX6_MMDC_P0_MDSCR 0x04008040 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 -check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000 wm 32 MX6_MMDC_P0_MDSCR 0x00048033 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 @@ -161,19 +161,19 @@ wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f -check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x00008033 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b wm 32 MX6_MMDC_P0_MDREF 0x00001800 wm 32 MX6_MMDC_P0_MAPSR 0x00001000 wm 32 MX6_MMDC_P0_MDPDC 0x00025576 wm 32 MX6_MMDC_P0_MDSCR 0x00000000 -check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg index c242193a62..8756e8dfb5 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg @@ -130,11 +130,11 @@ wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 wm 32 MX6_MMDC_P0_MDMISC 0x00000742 -check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002 +check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 -check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 wm 32 MX6_MMDC_P0_MDCTL 0x841a0000 -check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 wm 32 MX6_MMDC_P0_MDCFG0 0x898f78f4 wm 32 MX6_MMDC_P0_MDCFG1 0xff328e64 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db @@ -157,7 +157,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001 wm 32 MX6_MMDC_P0_MDSCR 0x04008010 wm 32 MX6_MMDC_P0_MDSCR 0x04008040 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 -check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000 wm 32 MX6_MMDC_P0_MDSCR 0x00048033 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 @@ -171,18 +171,18 @@ wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f -check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x00008033 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b wm 32 MX6_MMDC_P0_MDREF 0x00001800 wm 32 MX6_MMDC_P0_MAPSR 0x00001000 wm 32 MX6_MMDC_P0_MDPDC 0x00025576 wm 32 MX6_MMDC_P0_MDSCR 0x00000000 -check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/myirtech-x335x/Makefile b/arch/arm/boards/myirtech-x335x/Makefile new file mode 100644 index 0000000000..05d9fc7bc3 --- /dev/null +++ b/arch/arm/boards/myirtech-x335x/Makefile @@ -0,0 +1,3 @@ +lwl-y += lowlevel.o +obj-y += board.o +bbenv-$(CONFIG_DEFAULT_ENVIRONMENT) += defaultenv-myirtech-x335x diff --git a/arch/arm/boards/myirtech-x335x/board.c b/arch/arm/boards/myirtech-x335x/board.c new file mode 100644 index 0000000000..c6d808284e --- /dev/null +++ b/arch/arm/boards/myirtech-x335x/board.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> */ + +#include <bootsource.h> +#include <common.h> +#include <driver.h> +#include <envfs.h> +#include <init.h> +#include <linux/sizes.h> +#include <mach/am33xx-generic.h> + +static struct omap_barebox_part myir_barebox_part = { + .nand_offset = SZ_128K * 4, + .nand_size = SZ_1M, +}; + +static __init int myir_devices_init(void) +{ + if (!of_machine_is_compatible("myir,myc-am335x")) + return 0; + + am33xx_register_ethaddr(0, 0); + am33xx_register_ethaddr(1, 1); + + switch (bootsource_get()) { + case BOOTSOURCE_MMC: + omap_set_bootmmc_devname("mmc0"); + break; + case BOOTSOURCE_NAND: + omap_set_barebox_part(&myir_barebox_part); + break; + default: + break; + } + + if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT)) + defaultenv_append_directory(defaultenv_myirtech_x335x); + + if (IS_ENABLED(CONFIG_SHELL_NONE)) + return am33xx_of_register_bootdevice(); + + return 0; +} +coredevice_initcall(myir_devices_init); diff --git a/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/boot/nand b/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/boot/nand new file mode 100644 index 0000000000..c000041095 --- /dev/null +++ b/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/boot/nand @@ -0,0 +1,4 @@ +#!/bin/sh + +global.bootm.image="/dev/nand0.system.ubi.kernel" +global.linux.bootargs.dyn.root="ubi.mtd=system ubi.block=0,root root=fe00 ro" diff --git a/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/nv/boot.default b/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/nv/boot.default new file mode 100644 index 0000000000..026a25cc7e --- /dev/null +++ b/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/nv/boot.default @@ -0,0 +1 @@ +nand diff --git a/arch/arm/boards/myirtech-x335x/lowlevel.c b/arch/arm/boards/myirtech-x335x/lowlevel.c new file mode 100644 index 0000000000..e867a0be7d --- /dev/null +++ b/arch/arm/boards/myirtech-x335x/lowlevel.c @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> */ + +#include <io.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <debug_ll.h> +#include <init.h> +#include <linux/sizes.h> +#include <mach/am33xx-clock.h> +#include <mach/am33xx-generic.h> +#include <mach/am33xx-mux.h> +#include <mach/generic.h> +#include <mach/sdrc.h> +#include <mach/sys_info.h> +#include <mach/wdt.h> + +#define AM335X_ZCZ_1000 0x1c2f + +static const struct am33xx_ddr_data ddr3_data = { + .rd_slave_ratio0 = 0x38, + .wr_dqs_slave_ratio0 = 0x44, + .fifo_we_slave_ratio0 = 0x94, + .wr_slave_ratio0 = 0x7d, + .use_rank0_delay = 0x01, + .dll_lock_diff0 = 0x00, +}; + +static const struct am33xx_cmd_control ddr3_cmd_ctrl = { + .slave_ratio0 = 0x80, + .dll_lock_diff0 = 0x01, + .invert_clkout0 = 0x00, + .slave_ratio1 = 0x80, + .dll_lock_diff1 = 0x01, + .invert_clkout1 = 0x00, + .slave_ratio2 = 0x80, + .dll_lock_diff2 = 0x01, + .invert_clkout2 = 0x00, +}; + +/* CPU module contains 512MB (2*256MB) DDR3 SDRAM (2*128MB compatible), + * so we configure EMIF for 512MB then detect real size of memory. + */ +static const struct am33xx_emif_regs ddr3_regs = { + .emif_read_latency = 0x00100007, + .emif_tim1 = 0x0aaad4db, + .emif_tim2 = 0x266b7fda, + .emif_tim3 = 0x501f867f, + .zq_config = 0x50074be4, + .sdram_config = 0x61c05332, + .sdram_config2 = 0x00, + .sdram_ref_ctrl = 0xc30, +}; + +extern char __dtb_z_am335x_myirtech_myd_start[]; + +ENTRY_FUNCTION(start_am33xx_myirtech_sram, bootinfo, r1, r2) +{ + int mpupll; + void *fdt; + + am33xx_save_bootinfo((void *)bootinfo); + + arm_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + fdt = __dtb_z_am335x_myirtech_myd_start; + + /* WDT1 is already running when the bootloader gets control + * Disable it to avoid "random" resets + */ + __raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); + while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); + __raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); + while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); + + mpupll = MPUPLL_M_800; + if (am33xx_get_cpu_rev() == AM335X_ES2_1) { + u32 deviceid = readl(AM33XX_EFUSE_SMA) & 0x1fff; + if (deviceid == AM335X_ZCZ_1000) + mpupll = MPUPLL_M_1000; + } + + am33xx_pll_init(mpupll, DDRPLL_M_400); + + am335x_sdram_init(0x18b, &ddr3_cmd_ctrl, &ddr3_regs, &ddr3_data); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) { + am33xx_uart_soft_reset(IOMEM(AM33XX_UART0_BASE)); + am33xx_enable_uart0_pin_mux(); + omap_uart_lowlevel_init(IOMEM(AM33XX_UART0_BASE)); + putc_ll('>'); + } + + barebox_arm_entry(AM33XX_DRAM_ADDR_SPACE_START, SZ_256M, fdt); +} + +ENTRY_FUNCTION(start_am33xx_myirtech_sdram, r0, r1, r2) +{ + void *fdt; + u32 sdram_size; + + fdt = __dtb_z_am335x_myirtech_myd_start; + + fdt += get_runtime_offset(); + + /* Detect 256M/512M module variant */ + __raw_writel(SZ_512M, AM33XX_DRAM_ADDR_SPACE_START + SZ_256M); + __raw_writel(SZ_256M, AM33XX_DRAM_ADDR_SPACE_START + 0); + sdram_size = __raw_readl(AM33XX_DRAM_ADDR_SPACE_START + SZ_256M); + + barebox_arm_entry(AM33XX_DRAM_ADDR_SPACE_START, sdram_size, fdt); +} diff --git a/arch/arm/boards/phytec-phycore-omap4460/board.c b/arch/arm/boards/phytec-phycore-omap4460/board.c index 9e8b9e56a7..e25ff5eb31 100644 --- a/arch/arm/boards/phytec-phycore-omap4460/board.c +++ b/arch/arm/boards/phytec-phycore-omap4460/board.c @@ -10,10 +10,10 @@ #include <envfs.h> #include <asm/armlinux.h> #include <generated/mach-types.h> +#include <mach/devices.h> #include <mach/omap4-silicon.h> #include <mach/omap4-devices.h> #include <mach/omap4-clock.h> -#include <mach/omap-fb.h> #include <mach/sdrc.h> #include <mach/sys_info.h> #include <mach/syslib.h> @@ -292,8 +292,7 @@ static int pcm049_devices_init(void) armlinux_set_architecture(MACH_TYPE_PCM049); - if (IS_ENABLED(CONFIG_DRIVER_VIDEO_OMAP)) - omap_add_display(&pcm049_fb_data); + omap_add_display(&pcm049_fb_data); if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) defaultenv_append_directory(defaultenv_phytec_phycore_omap4460); diff --git a/arch/arm/boards/protonic-imx6/board.c b/arch/arm/boards/protonic-imx6/board.c index 52cf39917a..cdbb8debe6 100644 --- a/arch/arm/boards/protonic-imx6/board.c +++ b/arch/arm/boards/protonic-imx6/board.c @@ -126,6 +126,22 @@ static const struct gpio prt_imx6_kvg_gpios[] = { }, }; +static int prt_of_fixup_hwrev(struct prt_imx6_priv *priv) +{ + const char *compat; + char *buf; + + compat = of_device_get_match_compatible(priv->dev); + + buf = xasprintf("%s-m%u-r%u", compat, priv->hw_id, + priv->hw_rev); + barebox_set_of_machine_compatible(buf); + + free(buf); + + return 0; +} + static int prt_imx6_read_rfid(struct prt_imx6_priv *priv, void *buf, size_t size) { @@ -196,30 +212,12 @@ static int prt_imx6_set_mac(struct prt_imx6_priv *priv, return 0; } -static int prt_of_fixup_serial(struct device_node *dstroot, void *arg) -{ - struct device_node *srcroot = arg; - const char *ser; - int len; - - ser = of_get_property(srcroot, "serial-number", &len); - return of_set_property(dstroot, "serial-number", ser, len, 1); -} - -static void prt_oftree_fixup_serial(const char *serial) -{ - struct device_node *root = of_get_root_node(); - - of_set_property(root, "serial-number", serial, strlen(serial) + 1, 1); - of_register_fixup(prt_of_fixup_serial, root); -} - static int prt_imx6_set_serial(struct prt_imx6_priv *priv, struct prti6q_rfid_contents *rfid) { rfid->serial[9] = 0; /* Failsafe */ dev_info(priv->dev, "Serial number: %s\n", rfid->serial); - prt_oftree_fixup_serial(rfid->serial); + barebox_set_serial_number(rfid->serial); return 0; } @@ -815,7 +813,6 @@ exit_get_dcfg: static int prt_imx6_probe(struct device_d *dev) { struct prt_imx6_priv *priv; - const char *name, *ptr; struct param_d *p; int ret; @@ -824,9 +821,7 @@ static int prt_imx6_probe(struct device_d *dev) return -ENOMEM; priv->dev = dev; - name = of_device_get_match_compatible(priv->dev); - ptr = strchr(name, ','); - priv->name = ptr ? ptr + 1 : name; + priv->name = of_get_machine_compatible(); pr_info("Detected machine type: %s\n", priv->name); @@ -836,6 +831,7 @@ static int prt_imx6_probe(struct device_d *dev) pr_info(" HW type: %d\n", priv->hw_id); pr_info(" HW revision: %d\n", priv->hw_rev); + prt_of_fixup_hwrev(priv); ret = prt_imx6_get_dcfg(priv); if (ret) diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c index 82da4d6464..41ef7d1677 100644 --- a/arch/arm/boards/raspberry-pi/rpi-common.c +++ b/arch/arm/boards/raspberry-pi/rpi-common.c @@ -350,8 +350,10 @@ static const struct rpi_machine_data *rpi_get_dcfg(struct rpi_priv *priv) const struct rpi_machine_data *dcfg; dcfg = of_device_get_match_data(priv->dev); - if (!dcfg) - return ERR_PTR(-EINVAL); + if (!dcfg) { + dev_err(priv->dev, "Unknown board. Not applying fixups\n"); + return NULL; + } for (; dcfg->hw_id != U8_MAX; dcfg++) { if (priv->hw_id & 0x800000) { @@ -367,7 +369,7 @@ static const struct rpi_machine_data *rpi_get_dcfg(struct rpi_priv *priv) return dcfg; } - dev_err(priv->dev, "Failed to get dcfg for board_id: 0x%x.\n", + dev_err(priv->dev, "dcfg 0x%x for board_id doesn't match DT compatible\n", priv->hw_id); return ERR_PTR(-ENODEV); } @@ -405,7 +407,7 @@ static int rpi_devices_probe(struct device_d *dev) rpi_env_init(); rpi_vc_fdt(); - if (dcfg->init) + if (dcfg && dcfg->init) dcfg->init(priv); reg = regulator_get_name("bcm2835_usb"); @@ -584,6 +586,24 @@ static const struct rpi_machine_data rpi_3_model_b_plus[] = { }, }; +static const struct rpi_machine_data rpi_compute_module_3[] = { + { + .hw_id = BCM2837_BOARD_REV_CM3, + }, { + .hw_id = BCM2837B0_BOARD_REV_CM3_PLUS, + }, { + .hw_id = U8_MAX + }, +}; + +static const struct rpi_machine_data rpi_model_zero_2_w[] = { + { + .hw_id = BCM2837B0_BOARD_REV_ZERO_2, + }, { + .hw_id = U8_MAX + }, +}; + static const struct of_device_id rpi_of_match[] = { /* BCM2835 based Boards */ { .compatible = "raspberrypi,model-a", .data = rpi_model_a }, @@ -604,6 +624,10 @@ static const struct of_device_id rpi_of_match[] = { { .compatible = "raspberrypi,3-model-a-plus", .data = rpi_3_model_a_plus }, { .compatible = "raspberrypi,3-model-b", .data = rpi_3_model_b }, { .compatible = "raspberrypi,3-model-b-plus", .data = rpi_3_model_b_plus }, + { .compatible = "raspberrypi,model-zero-2-w", .data = rpi_model_zero_2_w }, + { .compatible = "raspberrypi,3-compute-module", .data = rpi_compute_module_3 }, + { .compatible = "raspberrypi,3-compute-module-lite", .data = rpi_compute_module_3 }, + { /* sentinel */ }, }; BAREBOX_DEEP_PROBE_ENABLE(rpi_of_match); diff --git a/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c index 9f039c6048..f79f975080 100644 --- a/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c +++ b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c @@ -16,10 +16,13 @@ static noinline void rk3568_start(void) void *fdt; /* - * Enable vccio4 1.8V and vccio6 1.8V - * Needed for GMAC to work. + * set iodomain vccio6 to 1.8V needed for GMAC1 to work. + * vccio4 (gmac0/switch) needs to stay at 3v3 (default) */ - writel(RK_SETBITS(0x50), 0xfdc20140); + //set bit 6 in PMU_GRF_IO_VSEL0 for vccio6 1v8 + writel(RK_SETBITS(BIT(6)), PMU_GRF_IO_VSEL0); + //clear bit 6 for 3v3 as it was set to 1v8 + writel(RK_CLRBITS(BIT(6)), PMU_GRF_IO_VSEL1); fdt = __dtb_rk3568_bpi_r2_pro_start; diff --git a/arch/arm/boards/skov-imx6/board.c b/arch/arm/boards/skov-imx6/board.c index 2702bc1de9..bceb215a01 100644 --- a/arch/arm/boards/skov-imx6/board.c +++ b/arch/arm/boards/skov-imx6/board.c @@ -312,55 +312,21 @@ static int skov_board_no = -1; static bool skov_have_switch = true; static const char *no_switch_suffix = "-noswitch"; -static void fixup_machine_compatible(const char *compat, - struct device_node *root) -{ - int cclen = 0, clen = strlen(compat) + 1; - const char *curcompat; - void *buf; - - if (!root) { - root = of_get_root_node(); - if (!root) - return; - } - - curcompat = of_get_property(root, "compatible", &cclen); - - buf = xzalloc(cclen + clen); - - memcpy(buf, compat, clen); - memcpy(buf + clen, curcompat, cclen); - - /* - * Prepend the compatible from board entry to the machine compatible. - * Used to match bootspec entries against it. - */ - of_set_property(root, "compatible", buf, cclen + clen, true); - - free(buf); -} - static void fixup_noswitch_machine_compatible(struct device_node *root) { const char *compat = imx6_variants[skov_board_no].dts_compatible; const char *generic = "skov,imx6"; - size_t size, size_generic; char *buf; - size = strlen(compat) + strlen(no_switch_suffix) + 1; - size_generic = strlen(generic) + strlen(no_switch_suffix) + 1; - size = max(size, size_generic); - /* add generic compatible, so systemd&co can make right decisions */ buf = xasprintf("%s%s", generic, no_switch_suffix); - fixup_machine_compatible(buf, root); + of_prepend_machine_compatible(root, buf); /* add specific compatible as fallback, in case this board has new * challenges. */ buf = xasprintf("%s%s", compat, no_switch_suffix); - fixup_machine_compatible(buf, root); + of_prepend_machine_compatible(root, buf); free(buf); } @@ -648,7 +614,7 @@ static int skov_imx6_probe(struct device_d *dev) globalvar_add_simple("board.dts", variant->dts_compatible); globalvar_add_simple("board.display", variant->display ?: NULL); - fixup_machine_compatible(variant->dts_compatible, NULL); + of_prepend_machine_compatible(NULL, variant->dts_compatible); skov_init_board(variant); diff --git a/arch/arm/configs/am335x_mlo_defconfig b/arch/arm/configs/am335x_mlo_defconfig index 51d238db3e..83bb20e4b5 100644 --- a/arch/arm/configs/am335x_mlo_defconfig +++ b/arch/arm/configs/am335x_mlo_defconfig @@ -5,6 +5,7 @@ CONFIG_OMAP_SERIALBOOT=y CONFIG_OMAP_MULTI_BOARDS=y CONFIG_MACH_AFI_GF=y CONFIG_MACH_BEAGLEBONE=y +CONFIG_MACH_MYIRTECH_X335X=y CONFIG_MACH_PHYTEC_SOM_AM335X=y CONFIG_THUMB2_BAREBOX=y # CONFIG_MEMINFO is not set diff --git a/arch/arm/configs/omap_defconfig b/arch/arm/configs/omap_defconfig index 59892cb231..ae4d1a67da 100644 --- a/arch/arm/configs/omap_defconfig +++ b/arch/arm/configs/omap_defconfig @@ -6,6 +6,7 @@ CONFIG_OMAP_MULTI_BOARDS=y CONFIG_MACH_AFI_GF=y CONFIG_MACH_BEAGLE=y CONFIG_MACH_BEAGLEBONE=y +CONFIG_MACH_MYIRTECH_X335X=y CONFIG_MACH_PHYTEC_SOM_AM335X=y CONFIG_MACH_VSCOM_BALTOS=y CONFIG_MACH_WAGO_PFC_AM35XX=y @@ -46,6 +47,7 @@ CONFIG_CMD_GO=y CONFIG_CMD_LOADB=y CONFIG_CMD_RESET=y CONFIG_CMD_UIMAGE=y +CONFIG_CMD_BOOTCHOOSER=y CONFIG_CMD_PARTITION=y CONFIG_CMD_UBIFORMAT=y CONFIG_CMD_EXPORT=y @@ -93,7 +95,6 @@ CONFIG_CMD_OF_FIXUP_STATUS=y CONFIG_CMD_OFTREE=y CONFIG_CMD_TIME=y CONFIG_CMD_STATE=y -CONFIG_CMD_BOOTCHOOSER=y CONFIG_NET=y CONFIG_NET_NFS=y CONFIG_NET_NETCONSOLE=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e0177d84e4..46e5e67672 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -40,6 +40,7 @@ lwl-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o lwl-$(CONFIG_MACH_MARVELL_ARMADA_XP_DB) += armada-xp-db-bb.dtb.o lwl-$(CONFIG_MACH_MB7707) += module-mb7707.dtb.o lwl-$(CONFIG_MACH_MX28EVK) += imx28-evk.dtb.o +lwl-$(CONFIG_MACH_MYIRTECH_X335X) += am335x-myirtech-myd.dtb.o lwl-$(CONFIG_MACH_NETGEAR_RN104) += armada-370-rn104-bb.dtb.o lwl-$(CONFIG_MACH_NETGEAR_RN2120) += armada-xp-rn2120-bb.dtb.o lwl-$(CONFIG_MACH_NITROGEN6) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o imx6qp-nitrogen6_max.dtb.o diff --git a/arch/arm/dts/am335x-myirtech-myd.dts b/arch/arm/dts/am335x-myirtech-myd.dts new file mode 100644 index 0000000000..6ec65e533d --- /dev/null +++ b/arch/arm/dts/am335x-myirtech-myd.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */ + +/dts-v1/; + +#include <arm/am335x-myirtech-myd.dts> + +/ { + chosen { + environment { + compatible = "barebox,environment"; + device-path = &nand_environment; + }; + }; + +}; + +&nand0 { + /delete-node/ partition@0; + /delete-node/ partition@20000; + + nand_parts: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "MLO"; + reg = <0x00000 0x20000>; + }; + + partition@80000 { + label = "boot"; + reg = <0x80000 0x100000>; + }; + + nand_environment: partition@180000 { + label = "env"; + reg = <0x180000 0x40000>; + }; + + partition@1c0000 { + label = "system"; + reg = <0x1c0000 0>; + }; + }; +}; diff --git a/arch/arm/dts/rk3568-bpi-r2-pro.dts b/arch/arm/dts/rk3568-bpi-r2-pro.dts index db13f00cd0..da76ab64c1 100644 --- a/arch/arm/dts/rk3568-bpi-r2-pro.dts +++ b/arch/arm/dts/rk3568-bpi-r2-pro.dts @@ -560,16 +560,13 @@ status = "okay"; }; -&usbdrd_dwc3 { +&usb_host0_xhci { dr_mode = "host"; extcon = <&usb2phy0>; -}; - -&usbdrd30 { status = "okay"; }; -&usbhost30 { +&usb_host1_xhci { status = "okay"; }; diff --git a/arch/arm/dts/rk3568-evb1-v10.dts b/arch/arm/dts/rk3568-evb1-v10.dts index 4ded9b1735..df5633978d 100644 --- a/arch/arm/dts/rk3568-evb1-v10.dts +++ b/arch/arm/dts/rk3568-evb1-v10.dts @@ -547,24 +547,20 @@ status = "okay"; }; -&usb_host1_ehci { +&usb_host0_xhci { + extcon = <&usb2phy0>; status = "okay"; }; -&usb_host1_ohci { +&usb_host1_ehci { status = "okay"; }; -&usbdrd_dwc3 { - dr_mode = "otg"; - extcon = <&usb2phy0>; -}; - -&usbdrd30 { +&usb_host1_ohci { status = "okay"; }; -&usbhost30 { +&usb_host1_xhci { status = "okay"; }; diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi index 0f19d3f0c0..3c458754af 100644 --- a/arch/arm/dts/rk3568.dtsi +++ b/arch/arm/dts/rk3568.dtsi @@ -198,62 +198,38 @@ }; }; - usbdrd30: usbdrd { - compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; + usb_host0_xhci: usb@fcc00000 { + compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfcc00000 0x0 0x400000>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>; + <&cru ACLK_USB3OTG0>; clock-names = "ref_clk", "suspend_clk", - "bus_clk", "pipe_clk"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_USB3OTG0>; + snps,dis_u2_susphy_quirk; status = "disabled"; - - usbdrd_dwc3: dwc3@fcc00000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfcc00000 0x0 0x400000>; - interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - resets = <&cru SRST_USB3OTG0>; - reset-names = "usb3-otg"; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,xhci-trb-ent-quirk; - }; }; - usbhost30: usbhost { - compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; + usb_host1_xhci: usb@fd000000 { + compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfd000000 0x0 0x400000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>; + <&cru ACLK_USB3OTG1>; clock-names = "ref_clk", "suspend_clk", - "bus_clk", "pipe_clk"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + "bus_clk"; + dr_mode = "host"; + phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_USB3OTG1>; + snps,dis_u2_susphy_quirk; status = "disabled"; - - usbhost_dwc3: dwc3@fd000000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfd000000 0x0 0x400000>; - interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - resets = <&cru SRST_USB3OTG1>; - reset-names = "usb3-host"; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,xhci-trb-ent-quirk; - }; }; gic: interrupt-controller@fd400000 { @@ -367,11 +343,10 @@ #phy-cells = <1>; clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, <&cru PCLK_PIPE>; - clock-names = "refclk", "apbclk", "pipe_clk"; + clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; assigned-clock-rates = <24000000>; - resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; - reset-names = "combphy-apb", "combphy"; + resets = <&cru SRST_PIPEPHY0>; rockchip,pipe-grf = <&pipegrf>; rockchip,pipe-phy-grf = <&pipe_phy_grf0>; status = "disabled"; @@ -383,11 +358,10 @@ #phy-cells = <1>; clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, <&cru PCLK_PIPE>; - clock-names = "refclk", "apbclk", "pipe_clk"; + clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; assigned-clock-rates = <24000000>; - resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; - reset-names = "combphy-apb", "combphy"; + resets = <&cru SRST_PIPEPHY1>; rockchip,pipe-grf = <&pipegrf>; rockchip,pipe-phy-grf = <&pipe_phy_grf1>; status = "disabled"; diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index f10f5bc148..a9f06512bc 100644 --- a/arch/arm/mach-bcm283x/include/mach/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -171,6 +171,7 @@ struct bcm2835_mbox_tag_hdr { #define BCM2837B0_BOARD_REV_3B_PLUS 0x0d #define BCM2837B0_BOARD_REV_3A_PLUS 0x0e #define BCM2837B0_BOARD_REV_CM3_PLUS 0x10 +#define BCM2837B0_BOARD_REV_ZERO_2 0x12 struct bcm2835_mbox_tag_get_board_rev { struct bcm2835_mbox_tag_hdr tag_hdr; diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index d3dbfff423..8dd0ddbbc9 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -350,6 +350,8 @@ static int vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) #define DDRC_ADDRMAP8_BG_B1 GENMASK(13, 8) #define DDRC_ADDRMAP8_BG_B0 GENMASK(4, 0) +#define DDRC_ADDRMAP_LENGTH 9 + static unsigned int imx_ddrc_count_bits(unsigned int bits, const u8 config[], unsigned int config_num) @@ -365,7 +367,7 @@ imx_ddrc_count_bits(unsigned int bits, const u8 config[], } static resource_size_t -imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[], +imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[DDRC_ADDRMAP_LENGTH], u8 col_max, const u8 col_b[], unsigned int col_b_num, u8 row_max, const u8 row_b[], unsigned int row_b_num, bool reduced_adress_space, bool is_imx8) @@ -392,7 +394,7 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[], } /* Bus width in bytes, 0 means half byte or 4-bit mode */ - if (is_imx8) + if (is_imx8 && !(mstr & DDRC_MSTR_LPDDR4)) width = (1 << FIELD_GET(DDRC_MSTR_DEVICE_CONFIG, mstr)) >> 1; else width = 4; @@ -446,7 +448,7 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[], static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc) { - const u32 addrmap[] = { + const u32 addrmap[DDRC_ADDRMAP_LENGTH] = { readl(ddrc + DDRC_ADDRMAP(0)), readl(ddrc + DDRC_ADDRMAP(1)), readl(ddrc + DDRC_ADDRMAP(2)), @@ -498,7 +500,7 @@ static int imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc) { - const u32 addrmap[] = { + const u32 addrmap[DDRC_ADDRMAP_LENGTH] = { readl(ddrc + DDRC_ADDRMAP(0)), readl(ddrc + DDRC_ADDRMAP(1)), readl(ddrc + DDRC_ADDRMAP(2)), diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig index 220b635167..f0e035e31e 100644 --- a/arch/arm/mach-omap/Kconfig +++ b/arch/arm/mach-omap/Kconfig @@ -168,6 +168,12 @@ config MACH_BEAGLEBONE help Say Y here if you are using Beagle Bone +config MACH_MYIRTECH_X335X + bool "MYIR Tech Limited SOMs" + select ARCH_AM33XX + help + Say Y here if you are using a TI AM335X based MYIR SOM + config MACH_PHYTEC_SOM_AM335X bool "Phytec AM335X SOMs" select ARCH_AM33XX diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile index 36b2aa090e..e81284ec3b 100644 --- a/arch/arm/mach-omap/Makefile +++ b/arch/arm/mach-omap/Makefile @@ -15,7 +15,7 @@ # GNU General Public License for more details. # # -obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o omap_fb.o +obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o pbl-$(CONFIG_ARCH_OMAP) += syslib.o obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h index 3c2143d600..b0293db990 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-clock.h +++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h @@ -25,6 +25,7 @@ #define MPUPLL_M_600 600 /* 125 * n */ #define MPUPLL_M_720 720 /* 125 * n */ #define MPUPLL_M_800 800 +#define MPUPLL_M_1000 1000 #define MPUPLL_M2 1 diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h index 0729369255..0467dac03b 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h +++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h @@ -201,6 +201,8 @@ #define AM33XX_MAC_ID1_HI (AM33XX_CTRL_BASE + 0x63c) #define AM33XX_MAC_MII_SEL (AM33XX_CTRL_BASE + 0x650) +#define AM33XX_EFUSE_SMA (AM33XX_CTRL_BASE + 0x7fc) + struct am33xx_cmd_control { u32 slave_ratio0; u32 dll_lock_diff0; diff --git a/arch/arm/mach-omap/include/mach/devices.h b/arch/arm/mach-omap/include/mach/devices.h index 0f9fdf1ca5..06fd2a8dd3 100644 --- a/arch/arm/mach-omap/include/mach/devices.h +++ b/arch/arm/mach-omap/include/mach/devices.h @@ -4,6 +4,7 @@ #define __MACH_OMAP_DEVICES_H #include <mach/omap_hsmmc.h> +#include <video/omap-fb.h> void omap_add_ram0(resource_size_t size); @@ -11,4 +12,6 @@ void omap_add_sram0(resource_size_t base, resource_size_t size); struct device_d *omap_add_uart(int id, unsigned long base); +struct device_d *omap_add_display(struct omapfb_platform_data *o_pdata); + #endif /* __MACH_OMAP_DEVICES_H */ diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c index c9a89c57b7..406b686318 100644 --- a/arch/arm/mach-omap/omap4_generic.c +++ b/arch/arm/mach-omap/omap4_generic.c @@ -433,38 +433,29 @@ unsigned int omap4_revision(void) return OMAP4430_ES1_0; case MIDR_CORTEX_A9_R1P2: switch (readl(CONTROL_ID_CODE)) { - case OMAP4_CONTROL_ID_CODE_ES2_0: - return OMAP4430_ES2_0; - break; case OMAP4_CONTROL_ID_CODE_ES2_1: return OMAP4430_ES2_1; - break; case OMAP4_CONTROL_ID_CODE_ES2_2: return OMAP4430_ES2_2; - break; default: - return OMAP4430_ES2_0; break; } - break; + return OMAP4430_ES2_0; case MIDR_CORTEX_A9_R1P3: return OMAP4430_ES2_3; - break; case MIDR_CORTEX_A9_R2P10: switch (readl(CONTROL_ID_CODE)) { case OMAP4460_CONTROL_ID_CODE_ES1_1: return OMAP4460_ES1_1; - break; - case OMAP4460_CONTROL_ID_CODE_ES1_0: default: - return OMAP4460_ES1_0; break; } - break; + return OMAP4460_ES1_0; default: - return OMAP4430_SILICON_ID_INVALID; break; } + + return OMAP4430_SILICON_ID_INVALID; } /* diff --git a/arch/arm/mach-omap/omap_devices.c b/arch/arm/mach-omap/omap_devices.c index 7c36b8819d..beae59f74d 100644 --- a/arch/arm/mach-omap/omap_devices.c +++ b/arch/arm/mach-omap/omap_devices.c @@ -26,3 +26,32 @@ struct device_d *omap_add_uart(int id, unsigned long base) return add_generic_device("omap-uart", id, NULL, base, 1024, IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat); } + +#if defined(CONFIG_DRIVER_VIDEO_OMAP) +static struct resource omapfb_resources[] = { + { + .name = "omap4_dss", + .start = 0x48040000, + .end = 0x48040000 + 512 - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, + }, { + .name = "omap4_dispc", + .start = 0x48041000, + .end = 0x48041000 + 3072 - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, + }, +}; + +struct device_d *omap_add_display(struct omapfb_platform_data *o_pdata) +{ + return add_generic_device_res("omap_fb", -1, + omapfb_resources, + ARRAY_SIZE(omapfb_resources), + o_pdata); +} +#else +struct device_d *omap_add_display(struct omapfb_platform_data *o_pdata) +{ + return NULL; +} +#endif diff --git a/arch/arm/mach-omap/omap_fb.c b/arch/arm/mach-omap/omap_fb.c deleted file mode 100644 index 0bd51c5f55..0000000000 --- a/arch/arm/mach-omap/omap_fb.c +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <driver.h> -#include <common.h> -#include <linux/ioport.h> -#include <mach/omap-fb.h> - -#if defined(CONFIG_DRIVER_VIDEO_OMAP) -static struct resource omapfb_resources[] = { - { - .name = "omap4_dss", - .start = 0x48040000, - .end = 0x48040000 + 512 - 1, - .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, - }, { - .name = "omap4_dispc", - .start = 0x48041000, - .end = 0x48041000 + 3072 - 1, - .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, - }, -}; - -struct device_d *omap_add_display(struct omapfb_platform_data *o_pdata) -{ - return add_generic_device_res("omap_fb", -1, - omapfb_resources, - ARRAY_SIZE(omapfb_resources), - o_pdata); -} -#else -struct device_d *omap_add_display(struct omapfb_platform_data *o_pdata) -{ - return NULL; -} -#endif -EXPORT_SYMBOL(omap_add_display); diff --git a/arch/arm/mach-rockchip/include/mach/rockchip.h b/arch/arm/mach-rockchip/include/mach/rockchip.h index f24db36f01..ff8b1109f8 100644 --- a/arch/arm/mach-rockchip/include/mach/rockchip.h +++ b/arch/arm/mach-rockchip/include/mach/rockchip.h @@ -23,6 +23,9 @@ static inline int rk3288_init(void) #ifdef CONFIG_ARCH_RK3568 int rk3568_init(void); +#define PMU_GRF 0xfdc20000 +#define PMU_GRF_IO_VSEL0 (PMU_GRF + 0x140) +#define PMU_GRF_IO_VSEL1 (PMU_GRF + 0x144) #else static inline int rk3568_init(void) { diff --git a/arch/riscv/configs/sifive_defconfig b/arch/riscv/configs/sifive_defconfig index 59cfebf194..6ebe6eaf37 100644 --- a/arch/riscv/configs/sifive_defconfig +++ b/arch/riscv/configs/sifive_defconfig @@ -13,13 +13,10 @@ CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y -CONFIG_IMD_TARGET=y CONFIG_CONSOLE_ALLOW_COLOR=y CONFIG_PBL_CONSOLE=y CONFIG_PARTITION_DISK_EFI=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_BAREBOXENV_TARGET=y -CONFIG_BAREBOXCRC32_TARGET=y CONFIG_STATE=y CONFIG_STATE_CRYPTO=y CONFIG_BOOTCHOOSER=y @@ -85,20 +82,21 @@ CONFIG_VIRTIO_CONSOLE=y CONFIG_SERIAL_SIFIVE=y CONFIG_DRIVER_NET_MACB=y CONFIG_DRIVER_SPI_GPIO=y +CONFIG_SPI_SIFIVE=y CONFIG_I2C=y CONFIG_I2C_GPIO=y CONFIG_MTD=y -# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_RAW_DEVICE=y CONFIG_MTD_CONCAT=y CONFIG_MTD_M25P80=y CONFIG_DRIVER_CFI=y CONFIG_DRIVER_CFI_BANK_WIDTH_8=y -CONFIG_DISK=y -CONFIG_DISK_WRITE=y CONFIG_VIRTIO_BLK=y CONFIG_VIDEO=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_DRIVER_VIDEO_SIMPLEFB_CLIENT=y +CONFIG_MCI=y +CONFIG_MCI_SPI=y CONFIG_CLOCKSOURCE_DUMMY_RATE=60000 CONFIG_EEPROM_AT24=y CONFIG_HWRNG=y @@ -126,3 +124,6 @@ CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DECOMPRESS=y CONFIG_BASE64=y CONFIG_DIGEST_CRC32_GENERIC=y +CONFIG_IMD_TARGET=y +CONFIG_BAREBOXENV_TARGET=y +CONFIG_BAREBOXCRC32_TARGET=y diff --git a/common/misc.c b/common/misc.c index 226635f0d4..0f6de3e9e5 100644 --- a/common/misc.c +++ b/common/misc.c @@ -149,6 +149,8 @@ EXPORT_SYMBOL(barebox_get_model); BAREBOX_MAGICVAR(global.model, "Product name of this hardware"); static char *hostname; +static char *serial_number; +static char *of_machine_compatible; /* * The hostname is supposed to be the shortname of a board. It should @@ -179,6 +181,43 @@ EXPORT_SYMBOL(barebox_set_hostname_no_overwrite); BAREBOX_MAGICVAR(global.hostname, "shortname of the board. Also used as hostname for DHCP requests"); +void barebox_set_serial_number(const char *__serial_number) +{ + globalvar_add_simple_string("serial_number", &serial_number); + + free(serial_number); + serial_number = xstrdup(__serial_number); +} + +const char *barebox_get_serial_number(void) +{ + return serial_number; +} + +BAREBOX_MAGICVAR(global.serial_number, "Board serial number"); + +void barebox_set_of_machine_compatible(const char *__compatible) +{ + free(of_machine_compatible); + of_machine_compatible = xstrdup(__compatible); +} + +const char *barebox_get_of_machine_compatible(void) +{ + return of_machine_compatible; +} + +static int of_kernel_init(void) +{ + globalvar_add_simple_string("of.kernel.add_machine_compatible", + &of_machine_compatible); + + return 0; +} +device_initcall(of_kernel_init); + +BAREBOX_MAGICVAR(global.of.kernel.add_machine_compatible, "Additional machine/board compatible"); + void __noreturn panic(const char *fmt, ...) { va_list args; diff --git a/common/oftree.c b/common/oftree.c index bce0ff09d6..91b3fcc9fa 100644 --- a/common/oftree.c +++ b/common/oftree.c @@ -206,6 +206,16 @@ static int of_fixup_bootargs(struct device_node *root, void *unused) int err; int instance = reset_source_get_instance(); struct device_d *dev; + const char *serialno; + const char *compat; + + serialno = barebox_get_serial_number(); + if (serialno) + of_property_write_string(root, "serial-number", serialno); + + compat = barebox_get_of_machine_compatible(); + if (compat) + of_prepend_machine_compatible(root, compat); node = of_create_node(root, "/chosen"); if (!node) @@ -478,3 +488,34 @@ int of_autoenable_i2c_by_component(char *path) return ret; } + +int of_prepend_machine_compatible(struct device_node *root, const char *compat) +{ + int cclen = 0, clen = strlen(compat) + 1; + const char *curcompat; + void *buf; + + if (!root) { + root = of_get_root_node(); + if (!root) + return -ENODEV; + } + + if (of_device_is_compatible(root, compat)) + return 0; + + curcompat = of_get_property(root, "compatible", &cclen); + + buf = xzalloc(cclen + clen); + + memcpy(buf, compat, clen); + + if (curcompat) + memcpy(buf + clen, curcompat, cclen); + + of_set_property(root, "compatible", buf, cclen + clen, true); + + free(buf); + + return 0; +} diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 3c0b0a5450..eb9e1bd133 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -101,7 +101,7 @@ static inline void __iomem *ahci_port_base(void __iomem *base, int port) static int ahci_link_ok(struct ahci_port *ahci_port, int verbose) { - u32 val = ahci_port_read(ahci_port, PORT_SCR_STAT) & 0xf; + u32 val = ahci_port_read(ahci_port, PORT_SCR_STAT) & PORT_SCR_STAT_DET; if (val == 0x3) return true; @@ -117,11 +117,13 @@ static void ahci_fill_cmd_slot(struct ahci_port *ahci_port, u32 opts) ahci_port->cmd_slot->opts = cpu_to_le32(opts); ahci_port->cmd_slot->status = 0; ahci_port->cmd_slot->tbl_addr = - cpu_to_le32((unsigned long)ahci_port->cmd_tbl & 0xffffffff); - ahci_port->cmd_slot->tbl_addr_hi = 0; + cpu_to_le32(lower_32_bits(ahci_port->cmd_tbl_dma)); + if (ahci_port->ahci->cap & HOST_CAP_64) + ahci_port->cmd_slot->tbl_addr_hi = + cpu_to_le32(upper_32_bits(ahci_port->cmd_tbl_dma)); } -static int ahci_fill_sg(struct ahci_port *ahci_port, const void *buf, int buf_len) +static int ahci_fill_sg(struct ahci_port *ahci_port, dma_addr_t buf_dma, int buf_len) { struct ahci_sg *ahci_sg = ahci_port->cmd_tbl_sg; u32 sg_count; @@ -133,12 +135,14 @@ static int ahci_fill_sg(struct ahci_port *ahci_port, const void *buf, int buf_le while (buf_len) { unsigned int now = min(AHCI_MAX_DATA_BYTE_COUNT, buf_len); - ahci_sg->addr = cpu_to_le32((u32)buf); - ahci_sg->addr_hi = 0; + ahci_sg->addr = cpu_to_le32(lower_32_bits(buf_dma)); + if (ahci_port->ahci->cap & HOST_CAP_64) + ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(buf_dma)); ahci_sg->flags_size = cpu_to_le32(now - 1); buf_len -= now; - buf += now; + buf_dma += now; + ahci_sg++; } return sg_count; @@ -150,40 +154,39 @@ static int ahci_io(struct ahci_port *ahci_port, u8 *fis, int fis_len, void *rbuf u32 opts; int sg_count; int ret; + void *buf; + dma_addr_t buf_dma; + enum dma_data_direction dma_dir; if (!ahci_link_ok(ahci_port, 1)) return -EIO; - if (wbuf) - dma_sync_single_for_device((unsigned long)wbuf, buf_len, - DMA_TO_DEVICE); - if (rbuf) - dma_sync_single_for_device((unsigned long)rbuf, buf_len, - DMA_FROM_DEVICE); + if (wbuf) { + buf = (void *)wbuf; + dma_dir = DMA_TO_DEVICE; + } else { + buf = rbuf; + dma_dir = DMA_FROM_DEVICE; + } + + buf_dma = dma_map_single(ahci_port->ahci->dev, buf, buf_len, dma_dir); - memcpy((unsigned char *)ahci_port->cmd_tbl, fis, fis_len); + memcpy(ahci_port->cmd_tbl, fis, fis_len); - sg_count = ahci_fill_sg(ahci_port, rbuf ? rbuf : wbuf, buf_len); + sg_count = ahci_fill_sg(ahci_port, buf_dma, buf_len); opts = (fis_len >> 2) | (sg_count << 16); if (wbuf) - opts |= 1 << 6; + opts |= CMD_LIST_OPTS_WRITE; ahci_fill_cmd_slot(ahci_port, opts); ahci_port_write_f(ahci_port, PORT_CMD_ISSUE, 1); ret = wait_on_timeout(WAIT_DATAIO, - (readl(ahci_port->port_mmio + PORT_CMD_ISSUE) & 0x1) == 0); - if (ret) - return -ETIMEDOUT; + (ahci_port_read(ahci_port, PORT_CMD_ISSUE) & 0x1) == 0); - if (wbuf) - dma_sync_single_for_cpu((unsigned long)wbuf, buf_len, - DMA_TO_DEVICE); - if (rbuf) - dma_sync_single_for_cpu((unsigned long)rbuf, buf_len, - DMA_FROM_DEVICE); + dma_unmap_single(ahci_port->ahci->dev, buf_dma, buf_len, dma_dir); - return 0; + return ret; } /* @@ -192,14 +195,12 @@ static int ahci_io(struct ahci_port *ahci_port, u8 *fis, int fis_len, void *rbuf static int ahci_read_id(struct ata_port *ata, void *buf) { struct ahci_port *ahci = container_of(ata, struct ahci_port, ata); - u8 fis[20]; - - memset(fis, 0, sizeof(fis)); - /* Construct the FIS */ - fis[0] = 0x27; /* Host to device FIS. */ - fis[1] = 1 << 7; /* Command FIS. */ - fis[2] = ATA_CMD_ID_ATA; /* Command byte. */ + u8 fis[20] = { + 0x27, /* Host to device FIS. */ + 1 << 7, /* Command FIS. */ + ATA_CMD_ID_ATA /* Command byte. */ + }; return ahci_io(ahci, fis, sizeof(fis), buf, NULL, SECTOR_SIZE); } @@ -208,16 +209,13 @@ static int ahci_rw(struct ata_port *ata, void *rbuf, const void *wbuf, sector_t block, blkcnt_t num_blocks) { struct ahci_port *ahci = container_of(ata, struct ahci_port, ata); - u8 fis[20]; + u8 fis[20] = { + 0x27, /* Host to device FIS. */ + 1 << 7 /* Command FIS. */ + }; int ret; int lba48 = ata_id_has_lba48(ata->id); - memset(fis, 0, sizeof(fis)); - - /* Construct the FIS */ - fis[0] = 0x27; /* Host to device FIS. */ - fis[1] = 1 << 7; /* Command FIS. */ - /* Command byte. */ if (lba48) fis[2] = wbuf ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; @@ -274,12 +272,11 @@ static int ahci_write(struct ata_port *ata, const void *buf, sector_t block, static int ahci_init_port(struct ahci_port *ahci_port) { - void __iomem *port_mmio; u32 val, cmd; + void *mem; + dma_addr_t mem_dma; int ret; - port_mmio = ahci_port->port_mmio; - /* make sure port is not active */ val = ahci_port_read(ahci_port, PORT_CMD); if (val & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | PORT_CMD_FIS_RX | PORT_CMD_START)) { @@ -295,46 +292,45 @@ static int ahci_init_port(struct ahci_port *ahci_port) mdelay(500); } + mem = dma_alloc_coherent(AHCI_PORT_PRIV_DMA_SZ, &mem_dma); + if (!mem) { + return -ENOMEM; + } + /* - * First item in chunk of DMA memory: 32-slot command table, + * First item in chunk of DMA memory: 32-slot command list, * 32 bytes each in size */ - ahci_port->cmd_slot = dma_alloc_coherent(AHCI_CMD_SLOT_SZ * 32, - DMA_ADDRESS_BROKEN); - if (!ahci_port->cmd_slot) { - ret = -ENOMEM; - goto err_alloc; - } + ahci_port->cmd_slot = mem; + ahci_port->cmd_slot_dma = mem_dma; - ahci_port_debug(ahci_port, "cmd_slot = 0x%x\n", (unsigned)ahci_port->cmd_slot); + ahci_port_debug(ahci_port, "cmd_slot = 0x%p (0x%pa)\n", + ahci_port->cmd_slot, ahci_port->cmd_slot_dma); /* * Second item: Received-FIS area */ - ahci_port->rx_fis = (unsigned long)dma_alloc_coherent(AHCI_RX_FIS_SZ, - DMA_ADDRESS_BROKEN); - if (!ahci_port->rx_fis) { - ret = -ENOMEM; - goto err_alloc1; - } + ahci_port->rx_fis = mem + AHCI_CMD_LIST_SZ; + ahci_port->rx_fis_dma = mem_dma + AHCI_CMD_LIST_SZ; /* * Third item: data area for storing a single command * and its scatter-gather table */ - ahci_port->cmd_tbl = dma_alloc_coherent(AHCI_CMD_TBL_SZ, - DMA_ADDRESS_BROKEN); - if (!ahci_port->cmd_tbl) { - ret = -ENOMEM; - goto err_alloc2; - } + ahci_port->cmd_tbl = mem + AHCI_CMD_LIST_SZ + AHCI_RX_FIS_SZ; + ahci_port->cmd_tbl_dma = mem_dma + AHCI_CMD_LIST_SZ + AHCI_RX_FIS_SZ; - ahci_port_debug(ahci_port, "cmd_tbl_dma = 0x%p\n", ahci_port->cmd_tbl); + ahci_port_debug(ahci_port, "cmd_tbl = 0x%p (0x%pa)\n", + ahci_port->cmd_tbl, ahci_port->cmd_tbl_dma); ahci_port->cmd_tbl_sg = ahci_port->cmd_tbl + AHCI_CMD_TBL_HDR_SZ; - ahci_port_write_f(ahci_port, PORT_LST_ADDR, (u32)ahci_port->cmd_slot); - ahci_port_write_f(ahci_port, PORT_FIS_ADDR, ahci_port->rx_fis); + ahci_port_write_f(ahci_port, PORT_LST_ADDR, lower_32_bits(ahci_port->cmd_slot_dma)); + if (ahci_port->ahci->cap & HOST_CAP_64) + ahci_port_write_f(ahci_port, PORT_LST_ADDR_HI, upper_32_bits(ahci_port->cmd_slot_dma)); + ahci_port_write_f(ahci_port, PORT_FIS_ADDR, lower_32_bits(ahci_port->rx_fis_dma)); + if (ahci_port->ahci->cap & HOST_CAP_64) + ahci_port_write_f(ahci_port, PORT_FIS_ADDR_HI, upper_32_bits(ahci_port->rx_fis_dma)); /* * Add the spinup command to whatever mode bits may @@ -358,7 +354,7 @@ static int ahci_init_port(struct ahci_port *ahci_port) * rarely has it taken between 1-2 ms. Never seen it above 2 ms. */ ret = wait_on_timeout(WAIT_LINKUP, - (ahci_port_read(ahci_port, PORT_SCR_STAT) & 0xf) == 0x3); + (ahci_port_read(ahci_port, PORT_SCR_STAT) & PORT_SCR_STAT_DET) == 0x3); if (ret) { ahci_port_info(ahci_port, "SATA link timeout\n"); ret = -ETIMEDOUT; @@ -375,16 +371,17 @@ static int ahci_init_port(struct ahci_port *ahci_port) ahci_port_info(ahci_port, "Spinning up device...\n"); ret = wait_on_timeout(WAIT_SPINUP, - ((readl(port_mmio + PORT_TFDATA) & - (ATA_STATUS_BUSY | ATA_STATUS_DRQ)) == 0) - || ((readl(port_mmio + PORT_SCR_STAT) & 0xf) == 1)); + ((ahci_port_read(ahci_port, PORT_TFDATA) & + (ATA_STATUS_BUSY | ATA_STATUS_DRQ)) == 0) || + ((ahci_port_read(ahci_port, PORT_SCR_STAT) & + PORT_SCR_STAT_DET) == 1)); if (ret) { ahci_port_info(ahci_port, "timeout.\n"); ret = -ENODEV; goto err_init; } - if ((readl(port_mmio + PORT_SCR_STAT) & 0xf) == 1) { + if ((ahci_port_read(ahci_port, PORT_SCR_STAT) & PORT_SCR_STAT_DET) == 1) { ahci_port_info(ahci_port, "down.\n"); ret = -ENODEV; goto err_init; @@ -411,18 +408,13 @@ static int ahci_init_port(struct ahci_port *ahci_port) ahci_port_debug(ahci_port, "status: 0x%08x\n", val); - if ((val & 0xf) == 0x03) + if ((val & PORT_SCR_STAT_DET) == 0x3) return 0; ret = -ENODEV; err_init: - dma_free_coherent(ahci_port->cmd_tbl, 0, AHCI_CMD_TBL_SZ); -err_alloc2: - dma_free_coherent((void *)ahci_port->rx_fis, 0, AHCI_RX_FIS_SZ); -err_alloc1: - dma_free_coherent(ahci_port->cmd_slot, 0, AHCI_CMD_SLOT_SZ * 32); -err_alloc: + dma_free_coherent(mem, mem_dma, AHCI_PORT_PRIV_DMA_SZ); return ret; } @@ -501,7 +493,7 @@ void ahci_print_info(struct ahci_device *ahci) cap2 = ahci_ioread(ahci, HOST_CAP2); impl = ahci->port_map; - speed = (cap >> 20) & 0xf; + speed = (cap & HOST_CAP_ISS) >> 20; if (speed == 1) speed_s = "1.5"; else if (speed == 2) @@ -519,32 +511,34 @@ void ahci_print_info(struct ahci_device *ahci) (vers >> 16) & 0xff, (vers >> 8) & 0xff, vers & 0xff, - ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); + ((cap & HOST_CAP_NCS) >> 8) + 1, + (cap & HOST_CAP_NP) + 1, speed_s, impl, scc_s); printf("flags: " "%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s" "%s%s%s%s%s%s\n", - cap & (1 << 31) ? "64bit " : "", - cap & (1 << 30) ? "ncq " : "", - cap & (1 << 28) ? "ilck " : "", - cap & (1 << 27) ? "stag " : "", - cap & (1 << 26) ? "pm " : "", - cap & (1 << 25) ? "led " : "", - cap & (1 << 24) ? "clo " : "", - cap & (1 << 19) ? "nz " : "", - cap & (1 << 18) ? "only " : "", - cap & (1 << 17) ? "pmp " : "", - cap & (1 << 16) ? "fbss " : "", - cap & (1 << 15) ? "pio " : "", - cap & (1 << 14) ? "slum " : "", - cap & (1 << 13) ? "part " : "", - cap & (1 << 7) ? "ccc " : "", - cap & (1 << 6) ? "ems " : "", - cap & (1 << 5) ? "sxs " : "", - cap2 & (1 << 2) ? "apst " : "", - cap2 & (1 << 1) ? "nvmp " : "", - cap2 & (1 << 0) ? "boh " : ""); + cap & HOST_CAP_64 ? "64bit " : "", + cap & HOST_CAP_NCQ ? "ncq " : "", + cap & HOST_CAP_SNTF ? "sntf " : "", + cap & HOST_CAP_SMPS ? "ilck " : "", + cap & HOST_CAP_SSS ? "stag " : "", + cap & HOST_CAP_ALPM ? "pm " : "", + cap & HOST_CAP_LED ? "led " : "", + cap & HOST_CAP_CLO ? "clo " : "", + cap & HOST_CAP_RESERVED ? "nz " : "", + cap & HOST_CAP_ONLY ? "only " : "", + cap & HOST_CAP_SPM ? "pmp " : "", + cap & HOST_CAP_FBS ? "fbss " : "", + cap & HOST_CAP_PIO_MULTI ? "pio " : "", + cap & HOST_CAP_SSC ? "slum " : "", + cap & HOST_CAP_PART ? "part " : "", + cap & HOST_CAP_CCC ? "ccc " : "", + cap & HOST_CAP_EMS ? "ems " : "", + cap & HOST_CAP_SXS ? "sxs " : "", + cap2 & HOST_CAP2_APST ? "apst " : "", + cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", + cap2 & HOST_CAP2_BOH ? "boh " : ""); } void ahci_info(struct device_d *dev) @@ -557,11 +551,15 @@ void ahci_info(struct device_d *dev) static int ahci_detect(struct device_d *dev) { struct ahci_device *ahci = dev->priv; + int n_ports = max_t(int, ahci->n_ports, fls(ahci->port_map)); int i; - for (i = 0; i < ahci->n_ports; i++) { + for (i = 0; i < n_ports; i++) { struct ahci_port *ahci_port = &ahci->ports[i]; + if (!(ahci->port_map & (1 << i))) + continue; + ata_port_detect(&ahci_port->ata); } @@ -570,9 +568,8 @@ static int ahci_detect(struct device_d *dev) int ahci_add_host(struct ahci_device *ahci) { - u8 *mmio = (u8 *)ahci->mmio_base; u32 tmp, cap_save; - int i, ret; + int n_ports, i, ret; ahci->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY @@ -584,9 +581,9 @@ int ahci_add_host(struct ahci_device *ahci) ahci_debug(ahci, "ahci_host_init: start\n"); - cap_save = readl(mmio + HOST_CAP); - cap_save &= ((1 << 28) | (1 << 17)); - cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ + cap_save = ahci_ioread(ahci, HOST_CAP); + cap_save &= (HOST_CAP_SMPS | HOST_CAP_SPM); + cap_save |= HOST_CAP_SSS; /* Staggered Spin-up. Not needed. */ /* global controller reset */ tmp = ahci_ioread(ahci, HOST_CTL); @@ -597,9 +594,9 @@ int ahci_add_host(struct ahci_device *ahci) * reset must complete within 1 second, or * the hardware should be considered fried. */ - ret = wait_on_timeout(SECOND, (readl(mmio + HOST_CTL) & HOST_RESET) == 0); + ret = wait_on_timeout(SECOND, (ahci_ioread(ahci, HOST_CTL) & HOST_RESET) == 0); if (ret) { - ahci_debug(ahci,"controller reset failed (0x%x)\n", tmp); + ahci_debug(ahci, "controller reset failed (0x%x)\n", tmp); return -ENODEV; } @@ -609,18 +606,23 @@ int ahci_add_host(struct ahci_device *ahci) ahci->cap = ahci_ioread(ahci, HOST_CAP); ahci->port_map = ahci_ioread(ahci, HOST_PORTS_IMPL); - ahci->n_ports = (ahci->cap & 0x1f) + 1; + ahci->n_ports = (ahci->cap & HOST_CAP_NP) + 1; ahci_debug(ahci, "cap 0x%x port_map 0x%x n_ports %d\n", ahci->cap, ahci->port_map, ahci->n_ports); - for (i = 0; i < ahci->n_ports; i++) { + n_ports = max_t(int, ahci->n_ports, fls(ahci->port_map)); + + for (i = 0; i < n_ports; i++) { struct ahci_port *ahci_port = &ahci->ports[i]; + if (!(ahci->port_map & (1 << i))) + continue; + ahci_port->num = i; ahci_port->ahci = ahci; ahci_port->ata.dev = ahci->dev; - ahci_port->port_mmio = ahci_port_base(mmio, i); + ahci_port->port_mmio = ahci_port_base(ahci->mmio_base, i); ahci_port->ata.ops = &ahci_ops; ata_port_register(&ahci_port->ata); } diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index 7fed43045a..77196592ed 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -10,13 +10,15 @@ #define AHCI_PCI_BAR 0x24 #define AHCI_MAX_SG 56 /* hardware max is 64K */ #define AHCI_CMD_SLOT_SZ 32 -#define AHCI_MAX_CMD_SLOT 32 +#define AHCI_MAX_CMDS 32 +#define AHCI_CMD_LIST_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMDS) #define AHCI_RX_FIS_SZ 256 #define AHCI_CMD_TBL_HDR_SZ 0x80 #define AHCI_CMD_TBL_CDB 0x40 -#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 32) -#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \ - AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ) +#define AHCI_CMD_TBL_ITM_SZ 16 +#define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * AHCI_CMD_TBL_ITM_SZ)) +#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_LIST_SZ + AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ) + #define AHCI_CMD_ATAPI (1 << 5) #define AHCI_CMD_WRITE (1 << 6) #define AHCI_CMD_PREFETCH (1 << 7) @@ -33,6 +35,34 @@ #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ #define HOST_CAP2 0x24 /* host capabilities, extended */ +/* HOST_CAP bits */ +#define HOST_CAP_64 (1 << 31) /* PCI DAC (64-bit DMA) support */ +#define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */ +#define HOST_CAP_SNTF (1 << 29) /* SNotification register */ +#define HOST_CAP_SMPS (1 << 28) /* Supports mechanical presence switch */ +#define HOST_CAP_SSS (1 << 27) /* Supports staggered spin-up */ +#define HOST_CAP_ALPM (1 << 26) /* Aggressive Link PM support */ +#define HOST_CAP_LED (1 << 25) /* Supports activity LED */ +#define HOST_CAP_CLO (1 << 24) /* Command List Override support */ +#define HOST_CAP_ISS (0xf << 20) /* Interface Speed Support */ +#define HOST_CAP_RESERVED (1 << 19) /* Reserved bit */ +#define HOST_CAP_ONLY (1 << 18) /* Supports AHCI mode only */ +#define HOST_CAP_SPM (1 << 17) /* Supports port multiplier */ +#define HOST_CAP_FBS (1 << 16) /* FIS-based switching support */ +#define HOST_CAP_PIO_MULTI (1 << 15) /* PIO multiple DRQ support */ +#define HOST_CAP_SSC (1 << 14) /* Slumber state capable */ +#define HOST_CAP_PART (1 << 13) /* Partial state capable */ +#define HOST_CAP_NCS (0x1f << 8) /* Number of Command Slots */ +#define HOST_CAP_CCC (1 << 7) /* Command Completion Coalescing */ +#define HOST_CAP_EMS (1 << 6) /* Enclosure Management support */ +#define HOST_CAP_SXS (1 << 5) /* Supports External SATA */ +#define HOST_CAP_NP (0x1f << 0) /* Number of ports */ + +/* HOST_CAP2 bits */ +#define HOST_CAP2_APST (1 << 2) /* Automatic partial to slumber */ +#define HOST_CAP2_NVMHCI (1 << 1) /* NVMHCI supported */ +#define HOST_CAP2_BOH (1 << 0) /* BIOS/OS handoff supported */ + /* HOST_CTL bits */ #define HOST_RESET (1 << 0) /* reset controller; self-clear */ #define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ @@ -98,6 +128,9 @@ #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ +/* PORT_SCR_STAT bits */ +#define PORT_SCR_STAT_DET (0xf << 0) /* device detection */ + #define AHCI_MAX_PORTS 32 /* SETFEATURES stuff */ @@ -130,6 +163,9 @@ #define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */ #define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */ +/* Command list entry DW0 bits */ +#define CMD_LIST_OPTS_WRITE (1 << 6) /* the direction is a device write */ + struct ahci_device; struct ahci_port { @@ -139,9 +175,12 @@ struct ahci_port { unsigned flags; void __iomem *port_mmio; struct ahci_cmd_hdr *cmd_slot; + dma_addr_t cmd_slot_dma; struct ahci_sg *cmd_tbl_sg; void *cmd_tbl; - u32 rx_fis; + dma_addr_t cmd_tbl_dma; + void *rx_fis; + dma_addr_t rx_fis_dma; }; struct ahci_device { diff --git a/drivers/ata/disk_ata_drive.c b/drivers/ata/disk_ata_drive.c index f36e06328c..7df0879b19 100644 --- a/drivers/ata/disk_ata_drive.c +++ b/drivers/ata/disk_ata_drive.c @@ -80,9 +80,9 @@ static void __maybe_unused ata_dump_id(uint16_t *id) ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); printf("Product model number: %s\n\r", product); - /* Total sectors of device */ + /* Total sectors of device */ n_sectors = ata_id_n_sectors(id); - printf("Capablity: %lld sectors\n\r", n_sectors); + printf("Capacity: %lld sectors\n\r", n_sectors); printf ("id[49]: capabilities = 0x%04x\n" "id[53]: field valid = 0x%04x\n" @@ -95,12 +95,14 @@ static void __maybe_unused ata_dump_id(uint16_t *id) id[ATA_ID_PIO_MODES], id[ATA_ID_QUEUE_DEPTH]); - printf ("id[76]: sata capablity = 0x%04x\n" + printf ("id[76]: sata capabilities 1 = 0x%04x\n" + "id[77]: sata capabilities 2 = 0x%04x\n" "id[78]: sata features supported = 0x%04x\n" - "id[79]: sata features enable = 0x%04x\n", - id[76], /* FIXME */ - id[78], /* FIXME */ - id[79]); /* FIXME */ + "id[79]: sata features enabled = 0x%04x\n", + id[ATA_ID_SATA_CAPAB_1], + id[ATA_ID_SATA_CAPAB_2], + id[ATA_ID_SATA_FEAT_SUPP], + id[ATA_ID_SATA_FEAT_ENABLE]); printf ("id[80]: major version = 0x%04x\n" "id[81]: minor version = 0x%04x\n" @@ -108,12 +110,13 @@ static void __maybe_unused ata_dump_id(uint16_t *id) "id[83]: command set supported 2 = 0x%04x\n" "id[84]: command set extension = 0x%04x\n", id[ATA_ID_MAJOR_VER], - id[81], /* FIXME */ + id[ATA_ID_MINOR_VER], id[ATA_ID_COMMAND_SET_1], id[ATA_ID_COMMAND_SET_2], id[ATA_ID_CFSSE]); - printf ("id[85]: command set enable 1 = 0x%04x\n" - "id[86]: command set enable 2 = 0x%04x\n" + + printf ("id[85]: command set enabled 1 = 0x%04x\n" + "id[86]: command set enabled 2 = 0x%04x\n" "id[87]: command set default = 0x%04x\n" "id[88]: udma = 0x%04x\n" "id[93]: hardware reset result = 0x%04x\n", diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 8e317b4b05..52e309e877 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -232,6 +232,9 @@ int clk_set_parent(struct clk *clk, struct clk *newparent) int i, ret; struct clk *curparent = clk_get_parent(clk); + if (!clk || !newparent) + return 0; + if (IS_ERR(clk)) return PTR_ERR(clk); if (IS_ERR(newparent)) @@ -287,7 +290,7 @@ struct clk *clk_get_parent(struct clk *clk) struct clk_hw *hw; int idx; - if (IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return clk; if (!clk->num_parents) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index c9b33bcd6c..f845a57394 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -431,7 +431,7 @@ static int gpiochip_find_base(int ngpio) } } else { spare = 0; - i += chip->ngpio - 1; + i -= chip->ngpio - 1; } } @@ -609,7 +609,7 @@ int gpiod_get(struct device_d *dev, const char *_con_id, enum gpiod_flags flags) int gpiochip_add(struct gpio_chip *chip) { - int base, i; + int i; if (chip->base >= 0) { for (i = 0; i < chip->ngpio; i++) { diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index d4e74552b7..58f8656067 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -70,4 +70,12 @@ config I2C_RK3X Say Y here to include support for the I2C adapter in Rockchip RK3xxx SoCs. +config I2C_CADENCE + bool "Cadence I2C adapter" + depends on HAVE_CLK + depends on ARCH_ZYNQMP || COMPILE_TEST + help + Say Y here to include support for the Cadence I2C host controller found + in Zynq UltraScale+ MPSoCs. + endmenu diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index d6273f3d86..a8661f605e 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o obj-$(CONFIG_I2C_DESIGNWARE) += i2c-designware.o obj-$(CONFIG_I2C_STM32) += i2c-stm32.o obj-$(CONFIG_I2C_RK3X) += i2c-rockchip.o +obj-$(CONFIG_I2C_CADENCE) += i2c-cadence.o diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c new file mode 100644 index 0000000000..5537efff23 --- /dev/null +++ b/drivers/i2c/busses/i2c-cadence.c @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * I2C bus driver for the Cadence I2C host controller (master only). + * + * Partly based on the driver in the Linux kernel + * Copyright (C) 2009 - 2014 Xilinx, Inc. + * + * Copyright (C) 2022 Matthias Fend <matthias.fend@emfend.at> + */ + +#include <common.h> +#include <i2c/i2c.h> +#include <linux/iopoll.h> +#include <errno.h> +#include <linux/err.h> +#include <driver.h> +#include <io.h> +#include <linux/clk.h> +#include <regmap.h> + +struct __packed i2c_regs { + u32 control; + u32 status; + u32 address; + u32 data; + u32 interrupt_status; + u32 transfer_size; + u32 slave_mon_pause; + u32 time_out; + u32 interrupt_mask; + u32 interrupt_enable; + u32 interrupt_disable; + u32 glitch_filter; +}; + +/* Control register fields */ +#define CDNS_I2C_CONTROL_RW BIT(0) +#define CDNS_I2C_CONTROL_MS BIT(1) +#define CDNS_I2C_CONTROL_NEA BIT(2) +#define CDNS_I2C_CONTROL_ACKEN BIT(3) +#define CDNS_I2C_CONTROL_HOLD BIT(4) +#define CDNS_I2C_CONTROL_SLVMON BIT(5) +#define CDNS_I2C_CONTROL_CLR_FIFO BIT(6) +#define CDNS_I2C_CONTROL_DIV_B_SHIFT 8 +#define CDNS_I2C_CONTROL_DIV_B_MASK (0x3F << CDNS_I2C_CONTROL_DIV_B_SHIFT) +#define CDNS_I2C_CONTROL_DIV_A_SHIFT 14 +#define CDNS_I2C_CONTROL_DIV_A_MASK (0x03 << CDNS_I2C_CONTROL_DIV_A_SHIFT) + +#define CDNS_I2C_CONTROL_DIV_B_MAX 64 +#define CDNS_I2C_CONTROL_DIV_A_MAX 4 + +/* Status register fields */ +#define CDNS_I2C_STATUS_RXRW BIT(3) +#define CDNS_I2C_STATUS_RXDV BIT(5) +#define CDNS_I2C_STATUS_TXDV BIT(6) +#define CDNS_I2C_STATUS_RXOVF BIT(7) +#define CDNS_I2C_STATUS_BA BIT(8) + +/* Address register fields */ +#define CDNS_I2C_ADDRESS_MASK 0x3FF + +/* Interrupt register fields */ +#define CDNS_I2C_INTERRUPT_COMP BIT(0) +#define CDNS_I2C_INTERRUPT_DATA BIT(1) +#define CDNS_I2C_INTERRUPT_NACK BIT(2) +#define CDNS_I2C_INTERRUPT_TO BIT(3) +#define CDNS_I2C_INTERRUPT_SLVRDY BIT(4) +#define CDNS_I2C_INTERRUPT_RXOVF BIT(5) +#define CDNS_I2C_INTERRUPT_TXOVF BIT(6) +#define CDNS_I2C_INTERRUPT_RXUNF BIT(7) +#define CDNS_I2C_INTERRUPT_ARBLOST BIT(9) + +#define CDNS_I2C_INTERRUPTS_MASK_MASTER (CDNS_I2C_INTERRUPT_COMP | \ + CDNS_I2C_INTERRUPT_DATA | \ + CDNS_I2C_INTERRUPT_NACK | \ + CDNS_I2C_INTERRUPT_RXOVF | \ + CDNS_I2C_INTERRUPT_TXOVF | \ + CDNS_I2C_INTERRUPT_RXUNF | \ + CDNS_I2C_INTERRUPT_ARBLOST) + +#define CDNS_I2C_INTERRUPTS_MASK_ALL (CDNS_I2C_INTERRUPT_COMP | \ + CDNS_I2C_INTERRUPT_DATA | \ + CDNS_I2C_INTERRUPT_NACK | \ + CDNS_I2C_INTERRUPT_TO | \ + CDNS_I2C_INTERRUPT_SLVRDY | \ + CDNS_I2C_INTERRUPT_RXOVF | \ + CDNS_I2C_INTERRUPT_TXOVF | \ + CDNS_I2C_INTERRUPT_RXUNF | \ + CDNS_I2C_INTERRUPT_ARBLOST) + +#define CDNS_I2C_FIFO_DEPTH 16 +#define CDNS_I2C_TRANSFER_SIZE_MAX 255 +#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3) + +#define I2C_TIMEOUT_US (100 * USEC_PER_MSEC) + +struct cdns_i2c { + struct i2c_adapter adapter; + struct clk *clk; + struct i2c_regs *regs; + bool bus_hold_flag; +}; + +static void cdns_i2c_reset_hardware(struct cdns_i2c *i2c) +{ + struct i2c_regs *regs = i2c->regs; + u32 regval; + + writel(CDNS_I2C_INTERRUPTS_MASK_ALL, ®s->interrupt_disable); + + regval = readl(®s->control); + regval &= ~CDNS_I2C_CONTROL_HOLD; + regval |= CDNS_I2C_CONTROL_CLR_FIFO; + writel(regval, ®s->control); + + writel(0xFF, ®s->time_out); + + writel(0, ®s->transfer_size); + + regval = readl(®s->interrupt_status); + writel(regval, ®s->interrupt_status); + + regval = readl(®s->status); + writel(regval, ®s->status); + + writel(0, ®s->control); +} + +static void cdns_i2c_setup_master(struct cdns_i2c *i2c) +{ + u32 control; + + control = readl(&i2c->regs->control); + control |= CDNS_I2C_CONTROL_MS | CDNS_I2C_CONTROL_ACKEN | + CDNS_I2C_CONTROL_NEA; + writel(control, &i2c->regs->control); + + writel(CDNS_I2C_INTERRUPTS_MASK_MASTER, &i2c->regs->interrupt_enable); +} + +static void cdns_i2c_clear_hold_flag(struct cdns_i2c *i2c) +{ + u32 control; + + control = readl(&i2c->regs->control); + if (control & CDNS_I2C_CONTROL_HOLD) + writel(control & ~CDNS_I2C_CONTROL_HOLD, &i2c->regs->control); +} + +static bool cdns_i2c_is_busy(struct cdns_i2c *i2c) +{ + return readl(&i2c->regs->status) & CDNS_I2C_STATUS_BA; +} + +static int cdns_i2c_hw_error(struct cdns_i2c *i2c) +{ + u32 isr_status; + + isr_status = readl(&i2c->regs->interrupt_status); + + if (isr_status & CDNS_I2C_INTERRUPT_NACK) + return -EREMOTEIO; + + if (isr_status & + (CDNS_I2C_INTERRUPT_ARBLOST | CDNS_I2C_INTERRUPT_RXOVF)) + return -EAGAIN; + + return 0; +} + +static int cdns_i2c_wait_for_completion(struct cdns_i2c *i2c) +{ + int err; + u32 isr_status; + const u32 isr_mask = + (CDNS_I2C_INTERRUPT_COMP | CDNS_I2C_INTERRUPT_NACK | + CDNS_I2C_INTERRUPT_ARBLOST); + + err = readl_poll_timeout(&i2c->regs->interrupt_status, isr_status, + isr_status & isr_mask, I2C_TIMEOUT_US); + + if (err) + return -ETIMEDOUT; + + return cdns_i2c_hw_error(i2c); +} + +/* + * Find best clock divisors + * + * f = finput / (22 x (div_a + 1) x (div_b + 1)) + */ +static int cdns_i2c_calc_divs(u32 *f, u32 input_clk, u32 *a, u32 *b) +{ + ulong fscl = *f, best_fscl = *f, actual_fscl, temp; + uint div_a, div_b, calc_div_a = 0, calc_div_b = 0; + uint last_error, current_error; + + temp = input_clk / (22 * fscl); + + if (!temp || + (temp > (CDNS_I2C_CONTROL_DIV_A_MAX * CDNS_I2C_CONTROL_DIV_B_MAX))) + return -EINVAL; + + last_error = -1; + for (div_a = 0; div_a < CDNS_I2C_CONTROL_DIV_A_MAX; div_a++) { + div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); + + if ((div_b < 1) || (div_b > CDNS_I2C_CONTROL_DIV_B_MAX)) + continue; + div_b--; + + actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); + + if (actual_fscl > fscl) + continue; + + current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) : + (fscl - actual_fscl)); + + if (last_error > current_error) { + calc_div_a = div_a; + calc_div_b = div_b; + best_fscl = actual_fscl; + last_error = current_error; + } + } + + *a = calc_div_a; + *b = calc_div_b; + *f = best_fscl; + + return 0; +} + +static int cdns_i2c_set_clk(struct cdns_i2c *i2c, u32 scl_rate) +{ + u32 i2c_rate; + u32 control; + u32 div_a, div_b; + int err; + + i2c_rate = clk_get_rate(i2c->clk); + + err = cdns_i2c_calc_divs(&scl_rate, i2c_rate, &div_a, &div_b); + if (err) + return err; + + control = readl(&i2c->regs->control); + control &= ~(CDNS_I2C_CONTROL_DIV_B_MASK | CDNS_I2C_CONTROL_DIV_A_MASK); + control |= (div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) | + (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT); + writel(control, &i2c->regs->control); + + return err; +} + +static int cdns_i2c_read(struct cdns_i2c *i2c, uchar chip, uchar *buf, + uint buf_len) +{ + struct i2c_regs *regs = i2c->regs; + u32 control; + int err; + + control = readl(®s->control); + control |= CDNS_I2C_CONTROL_RW | CDNS_I2C_CONTROL_CLR_FIFO; + if (i2c->bus_hold_flag || (buf_len > CDNS_I2C_FIFO_DEPTH)) + control |= CDNS_I2C_CONTROL_HOLD; + writel(control, ®s->control); + + do { + uint bytes_to_receive; + u32 isr_status; + u64 start_time; + + isr_status = readl(®s->interrupt_status); + writel(isr_status, ®s->interrupt_status); + + if (buf_len > CDNS_I2C_TRANSFER_SIZE) + bytes_to_receive = CDNS_I2C_TRANSFER_SIZE; + else + bytes_to_receive = buf_len; + + buf_len -= bytes_to_receive; + + writel(bytes_to_receive, ®s->transfer_size); + writel(chip & CDNS_I2C_ADDRESS_MASK, ®s->address); + + start_time = get_time_ns(); + while (bytes_to_receive) { + err = cdns_i2c_hw_error(i2c); + if (err) + goto i2c_exit; + + if (is_timeout(start_time, + (I2C_TIMEOUT_US * USECOND))) { + err = -ETIMEDOUT; + goto i2c_exit; + } + + if (readl(®s->status) & CDNS_I2C_STATUS_RXDV) { + *buf++ = readl(®s->data); + bytes_to_receive--; + } + } + + } while (buf_len); + + err = cdns_i2c_wait_for_completion(i2c); + +i2c_exit: + if (!i2c->bus_hold_flag) + cdns_i2c_clear_hold_flag(i2c); + + return err; +} + +static int cdns_i2c_write(struct cdns_i2c *i2c, uchar chip, uchar *buf, + uint buf_len) +{ + struct i2c_regs *regs = i2c->regs; + u32 control; + u32 isr_status; + bool start_transfer; + int err; + + control = readl(®s->control); + control &= ~CDNS_I2C_CONTROL_RW; + control |= CDNS_I2C_CONTROL_CLR_FIFO; + if (i2c->bus_hold_flag || (buf_len > CDNS_I2C_FIFO_DEPTH)) + control |= CDNS_I2C_CONTROL_HOLD; + writel(control, ®s->control); + + isr_status = readl(®s->interrupt_status); + writel(isr_status, ®s->interrupt_status); + + start_transfer = true; + do { + uint bytes_to_send; + + bytes_to_send = + CDNS_I2C_FIFO_DEPTH - readl(®s->transfer_size); + + if (buf_len < bytes_to_send) + bytes_to_send = buf_len; + + buf_len -= bytes_to_send; + + while (bytes_to_send--) + writel(*buf++, ®s->data); + + if (start_transfer) { + writel(chip & CDNS_I2C_ADDRESS_MASK, ®s->address); + start_transfer = false; + } + + err = cdns_i2c_wait_for_completion(i2c); + if (err) + goto i2c_exit; + + } while (buf_len); + +i2c_exit: + if (!i2c->bus_hold_flag) + cdns_i2c_clear_hold_flag(i2c); + + return err; +} + +static int cdns_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msg, + int nmsgs) +{ + struct cdns_i2c *i2c = container_of(adapter, struct cdns_i2c, adapter); + int i; + int err; + + if (cdns_i2c_is_busy(i2c)) + return -EBUSY; + + for (i = 0; i < nmsgs; i++) { + i2c->bus_hold_flag = i < (nmsgs - 1); + + if (msg->flags & I2C_M_RD) { + err = cdns_i2c_read(i2c, msg->addr, msg->buf, msg->len); + } else { + err = cdns_i2c_write(i2c, msg->addr, msg->buf, + msg->len); + } + + if (err) + return err; + + msg++; + } + + return nmsgs; +} + +static int cdns_i2c_probe(struct device_d *dev) +{ + struct device_node *np = dev->device_node; + struct resource *iores; + struct cdns_i2c *i2c; + u32 bitrate; + int err; + + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + + i2c = xzalloc(sizeof(*i2c)); + + dev->priv = i2c; + i2c->regs = IOMEM(iores->start); + + i2c->clk = clk_get(dev, NULL); + if (IS_ERR(i2c->clk)) + return PTR_ERR(i2c->clk); + + err = clk_enable(i2c->clk); + if (err) + return err; + + i2c->adapter.master_xfer = cdns_i2c_xfer; + i2c->adapter.nr = dev->id; + i2c->adapter.dev.parent = dev; + i2c->adapter.dev.device_node = np; + + cdns_i2c_reset_hardware(i2c); + + bitrate = 100000; + of_property_read_u32(np, "clock-frequency", &bitrate); + + err = cdns_i2c_set_clk(i2c, bitrate); + if (err) + return err; + + cdns_i2c_setup_master(i2c); + + return i2c_add_numbered_adapter(&i2c->adapter); +} + +static const struct of_device_id cdns_i2c_match[] = { + { .compatible = "cdns,i2c-r1p14" }, + {}, +}; + +static struct driver_d cdns_i2c_driver = { + .name = "cdns-i2c", + .of_compatible = cdns_i2c_match, + .probe = cdns_i2c_probe, +}; +coredevice_platform_driver(cdns_i2c_driver); diff --git a/drivers/i2c/busses/i2c-rockchip.c b/drivers/i2c/busses/i2c-rockchip.c index 4990735a4b..ca33905335 100644 --- a/drivers/i2c/busses/i2c-rockchip.c +++ b/drivers/i2c/busses/i2c-rockchip.c @@ -375,15 +375,17 @@ i2c_exit: return err; } -static int rockchip_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msg, +static int rockchip_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int nmsgs) { struct rk_i2c *i2c = to_rk_i2c(adapter); struct device_d *dev = &adapter->dev; - int ret; + int i, ret = 0; dev_dbg(dev, "i2c_xfer: %d messages\n", nmsgs); - for (; nmsgs > 0; nmsgs--, msg++) { + for (i = 0; i < nmsgs; i++) { + struct i2c_msg *msg = &msgs[i]; + dev_dbg(dev, "i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); if (msg->flags & I2C_M_RD) { ret = rk_i2c_read(i2c, msg->addr, 0, 0, msg->buf, @@ -395,14 +397,15 @@ static int rockchip_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msg, if (ret) { dev_dbg(dev, "i2c_write: error sending: %pe\n", ERR_PTR(ret)); - return -EREMOTEIO; + ret = -EREMOTEIO; + break; } } rk_i2c_send_stop_bit(i2c); rk_i2c_disable(i2c); - return 0; + return ret < 0 ? ret : nmsgs; } static int rk_i2c_probe(struct device_d *dev) diff --git a/drivers/mci/stm32_sdmmc2.c b/drivers/mci/stm32_sdmmc2.c index 0c620427ee..40ffc17908 100644 --- a/drivers/mci/stm32_sdmmc2.c +++ b/drivers/mci/stm32_sdmmc2.c @@ -643,6 +643,11 @@ static struct amba_id stm32_sdmmc2_ids[] = { .id = 0x00253180, .mask = 0xf0ffffff, }, + /* ST Micro STM32MP13 */ + { + .id = 0x20253180, + .mask = 0xf0ffffff, + }, { 0, 0 }, }; diff --git a/drivers/net/dsa.c b/drivers/net/dsa.c index f2420d306f..d9e629cefc 100644 --- a/drivers/net/dsa.c +++ b/drivers/net/dsa.c @@ -111,6 +111,10 @@ static int dsa_port_start(struct eth_device *edev) dsa_port_set_ethaddr(edev); + ret = phy_wait_aneg_done(dp->edev.phydev); + if (ret) + return ret; + if (ops->port_enable) { ret = ops->port_enable(dp, dp->index, dp->edev.phydev); if (ret) diff --git a/drivers/of/address.c b/drivers/of/address.c index 67e8062f5d..4eafce376d 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -301,10 +301,13 @@ static int of_translate_one(struct device_node *parent, struct of_bus *bus, * * As far as we know, this damage only exists on Apple machines, so * This code is only enabled on powerpc. --gcl + * + * This quirk also applies for 'dma-ranges' which frequently exist in + * child nodes without 'dma-ranges' in the parent nodes. --RobH */ ranges = of_get_property(parent, rprop, &rlen); #if !defined(CONFIG_PPC) - if (ranges == NULL) { + if (ranges == NULL && strcmp(rprop, "dma-ranges")) { pr_vdebug("OF: no ranges; cannot translate\n"); return 1; } diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 445703ecd8..2d86d86334 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -83,7 +83,6 @@ struct rockchip_combphy_priv { struct regmap *pipe_grf; struct regmap *phy_grf; struct phy *phy; - struct reset_control *apb_rst; struct reset_control *phy_rst; const struct rockchip_combphy_cfg *cfg; }; @@ -317,17 +316,7 @@ static int rockchip_combphy_parse_dt(struct device_d *dev, param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, true); - priv->apb_rst = reset_control_get(dev, "combphy-apb"); - if (IS_ERR(priv->apb_rst)) { - ret = PTR_ERR(priv->apb_rst); - - if (ret != -EPROBE_DEFER) - dev_warn(dev, "failed to get apb reset\n"); - - return ret; - } - - priv->phy_rst = reset_control_get(dev, "combphy"); + priv->phy_rst = reset_control_get(dev, NULL); if (IS_ERR(priv->phy_rst)) { ret = PTR_ERR(priv->phy_rst); @@ -579,9 +568,9 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { }; static const struct clk_bulk_data rk3568_clks[] = { - { .id = "refclk" }, - { .id = "apbclk" }, - { .id = "pipe_clk" }, + { .id = "ref" }, + { .id = "apb" }, + { .id = "pipe" }, }; static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index 464ae1aebc..f93a89ab95 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -366,11 +366,6 @@ static __maybe_unused struct ns16550_drvdata jz_drvdata = { .init_port = ns16550_jz_init_port, }; -static __maybe_unused struct ns16550_drvdata tegra_drvdata = { - .init_port = ns16550_serial_init_port, - .linux_console_name = "ttyS", -}; - static __maybe_unused struct ns16550_drvdata rpi_drvdata = { .init_port = rpi_init_port, .linux_console_name = "ttyS", @@ -528,6 +523,9 @@ static struct of_device_id ns16550_serial_dt_ids[] = { }, { .compatible = "marvell,armada-38x-uart", .data = &ns16550_drvdata, + }, { + .compatible = "nvidia,tegra20-uart", + .data = &ns16550_drvdata, }, #if IS_ENABLED(CONFIG_ARCH_OMAP) { @@ -541,12 +539,6 @@ static struct of_device_id ns16550_serial_dt_ids[] = { .data = &omap_drvdata, }, #endif -#if IS_ENABLED(CONFIG_ARCH_TEGRA) - { - .compatible = "nvidia,tegra20-uart", - .data = &tegra_drvdata, - }, -#endif #if IS_ENABLED(CONFIG_MACH_MIPS_XBURST) { .compatible = "ingenic,jz4740-uart", diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7df7561718..8935feb97b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -124,6 +124,12 @@ config SPI_NXP_FLEXSPI This controller does not support generic SPI messages and only supports the high-level SPI memory interface. +config SPI_SIFIVE + tristate "SiFive SPI controller" + depends on SOC_SIFIVE || COMPILE_TEST + help + This exposes the SPI controller IP from SiFive. + endif endmenu diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 64c8e2645a..3455eea869 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_DRIVER_SPI_DSPI) += dspi_spi.o obj-$(CONFIG_SPI_ZYNQ_QSPI) += zynq_qspi.o obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o obj-$(CONFIG_DRIVER_SPI_STM32) += stm32_spi.o +obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c new file mode 100644 index 0000000000..713bcc0c3b --- /dev/null +++ b/drivers/spi/spi-sifive.c @@ -0,0 +1,521 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 SiFive, Inc. + * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com> + * + * SiFive SPI controller driver (master mode only) + */ + +#include <common.h> +#include <linux/clk.h> +#include <driver.h> +#include <init.h> +#include <errno.h> +#include <linux/reset.h> +#include <spi/spi.h> +#include <linux/spi/spi-mem.h> +#include <linux/bitops.h> +#include <clock.h> +#include <gpio.h> +#include <of_gpio.h> +#include <linux/bitfield.h> +#include <linux/iopoll.h> +#include <linux/log2.h> + +#define SIFIVE_SPI_MAX_CS 32 + +#define SIFIVE_SPI_DEFAULT_DEPTH 8 +#define SIFIVE_SPI_DEFAULT_BITS 8 + +/* register offsets */ +#define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */ +#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */ +#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */ +#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */ +#define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */ +#define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */ +#define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */ +#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */ +#define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */ +#define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */ +#define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */ +#define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */ +#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */ +#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */ +#define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */ +#define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */ + +/* sckdiv bits */ +#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU + +/* sckmode bits */ +#define SIFIVE_SPI_SCKMODE_PHA BIT(0) +#define SIFIVE_SPI_SCKMODE_POL BIT(1) +#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \ + SIFIVE_SPI_SCKMODE_POL) + +/* csmode bits */ +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U + +/* delay0 bits */ +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16) +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16) + +/* delay1 bits */ +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU +#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16) +#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16) + +/* fmt bits */ +#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U +#define SIFIVE_SPI_FMT_PROTO_DUAL 1U +#define SIFIVE_SPI_FMT_PROTO_QUAD 2U +#define SIFIVE_SPI_FMT_PROTO_MASK 3U +#define SIFIVE_SPI_FMT_ENDIAN BIT(2) +#define SIFIVE_SPI_FMT_DIR BIT(3) +#define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16) +#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16) + +/* txdata bits */ +#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU +#define SIFIVE_SPI_TXDATA_FULL BIT(31) + +/* rxdata bits */ +#define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU +#define SIFIVE_SPI_RXDATA_EMPTY BIT(31) + +/* ie and ip bits */ +#define SIFIVE_SPI_IP_TXWM BIT(0) +#define SIFIVE_SPI_IP_RXWM BIT(1) + +/* format protocol */ +#define SIFIVE_SPI_PROTO_QUAD 4 /* 4 lines I/O protocol transfer */ +#define SIFIVE_SPI_PROTO_DUAL 2 /* 2 lines I/O protocol transfer */ +#define SIFIVE_SPI_PROTO_SINGLE 1 /* 1 line I/O protocol transfer */ + +#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ +#define SPI_XFER_END 0x02 /* Deassert CS after transfer */ + +struct sifive_spi { + struct spi_controller ctlr; + void __iomem *regs; /* base address of the registers */ + u32 fifo_depth; + u32 bits_per_word; + u32 cs_inactive; /* Level of the CS pins when inactive*/ + u32 freq; + u8 fmt_proto; +}; + +static inline struct sifive_spi *to_sifive_spi(struct spi_controller *ctlr) +{ + return container_of(ctlr, struct sifive_spi, ctlr); +} + +static void sifive_spi_prep_device(struct sifive_spi *spi, + struct spi_device *spi_dev) +{ + /* Update the chip select polarity */ + if (spi_dev->mode & SPI_CS_HIGH) + spi->cs_inactive &= ~BIT(spi_dev->chip_select); + else + spi->cs_inactive |= BIT(spi_dev->chip_select); + writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF); + + /* Select the correct device */ + writel(spi_dev->chip_select, spi->regs + SIFIVE_SPI_REG_CSID); +} + +static void sifive_spi_set_cs(struct sifive_spi *spi, + struct spi_device *spi_dev) +{ + u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD; + + if (spi_dev->mode & SPI_CS_HIGH) + cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO; + + writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE); +} + +static void sifive_spi_clear_cs(struct sifive_spi *spi) +{ + writel(SIFIVE_SPI_CSMODE_MODE_AUTO, spi->regs + SIFIVE_SPI_REG_CSMODE); +} + +static void sifive_spi_prep_transfer(struct sifive_spi *spi, + struct spi_device *spi_dev, + u8 *rx_ptr) +{ + u32 cr; + + /* Modify the SPI protocol mode */ + cr = readl(spi->regs + SIFIVE_SPI_REG_FMT); + + /* Bits per word ? */ + cr &= ~SIFIVE_SPI_FMT_LEN_MASK; + cr |= SIFIVE_SPI_FMT_LEN(spi->bits_per_word); + + /* LSB first? */ + cr &= ~SIFIVE_SPI_FMT_ENDIAN; + if (spi_dev->mode & SPI_LSB_FIRST) + cr |= SIFIVE_SPI_FMT_ENDIAN; + + /* Number of wires ? */ + cr &= ~SIFIVE_SPI_FMT_PROTO_MASK; + switch (spi->fmt_proto) { + case SIFIVE_SPI_PROTO_QUAD: + cr |= SIFIVE_SPI_FMT_PROTO_QUAD; + break; + case SIFIVE_SPI_PROTO_DUAL: + cr |= SIFIVE_SPI_FMT_PROTO_DUAL; + break; + default: + cr |= SIFIVE_SPI_FMT_PROTO_SINGLE; + break; + } + + /* SPI direction in/out ? */ + cr &= ~SIFIVE_SPI_FMT_DIR; + if (!rx_ptr) + cr |= SIFIVE_SPI_FMT_DIR; + + writel(cr, spi->regs + SIFIVE_SPI_REG_FMT); +} + +static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr) +{ + u32 data; + + do { + data = readl(spi->regs + SIFIVE_SPI_REG_RXDATA); + } while (data & SIFIVE_SPI_RXDATA_EMPTY); + + if (rx_ptr) + *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK; +} + +static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr) +{ + u32 data; + u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK : + SIFIVE_SPI_TXDATA_DATA_MASK; + + do { + data = readl(spi->regs + SIFIVE_SPI_REG_TXDATA); + } while (data & SIFIVE_SPI_TXDATA_FULL); + + writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA); +} + +static int sifive_spi_wait(struct sifive_spi *spi, u32 mask) +{ + u32 val; + + return readl_poll_timeout(spi->regs + SIFIVE_SPI_REG_IP, val, + (val & mask) == mask, 100 * USEC_PER_MSEC); +} + +static int sifive_spi_transfer_one(struct spi_device *spi_dev, unsigned int nbytes, + const void *dout, void *din) +{ + struct sifive_spi *spi = to_sifive_spi(spi_dev->controller); + const u8 *tx_ptr = dout; + u8 *rx_ptr = din; + int ret; + + sifive_spi_prep_transfer(spi, spi_dev, rx_ptr); + + while (nbytes) { + unsigned int n_words = min(nbytes, spi->fifo_depth); + unsigned int tx_words, rx_words; + + /* Enqueue n_words for transmission */ + for (tx_words = 0; tx_words < n_words; tx_words++) { + if (!tx_ptr) + sifive_spi_tx(spi, NULL); + else + sifive_spi_tx(spi, tx_ptr++); + } + + if (rx_ptr) { + /* Wait for transmission + reception to complete */ + writel(n_words - 1, spi->regs + SIFIVE_SPI_REG_RXMARK); + ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM); + if (ret) + return ret; + + /* Read out all the data from the RX FIFO */ + for (rx_words = 0; rx_words < n_words; rx_words++) + sifive_spi_rx(spi, rx_ptr++); + } else { + /* Wait for transmission to complete */ + ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM); + if (ret) + return ret; + } + + nbytes -= n_words; + } + + return 0; +} + +static int sifive_spi_transfer(struct spi_device *spi_dev, struct spi_message *msg) +{ + struct spi_controller *ctlr = spi_dev->controller; + struct sifive_spi *spi = to_sifive_spi(ctlr); + struct spi_transfer *t; + int ret = 0; + + if (list_empty(&msg->transfers)) + return 0; + + msg->actual_length = 0; + + sifive_spi_prep_device(spi, spi_dev); + sifive_spi_set_cs(spi, spi_dev); + + dev_dbg(ctlr->dev, "transfer start actual_length=%i\n", msg->actual_length); + list_for_each_entry(t, &msg->transfers, transfer_list) { + dev_dbg(ctlr->dev, " xfer %p: len %u tx %p rx %p\n", + t, t->len, t->tx_buf, t->rx_buf); + + ret = sifive_spi_transfer_one(spi_dev, t->len, + t->tx_buf, t->rx_buf); + if (ret < 0) + goto out; + msg->actual_length += t->len; + } + dev_dbg(ctlr->dev, "transfer done actual_length=%i\n", msg->actual_length); + +out: + sifive_spi_clear_cs(spi); + return ret; +} + +static int sifive_spi_exec_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct spi_device *spi_dev = mem->spi; + struct device_d *dev = &spi_dev->dev; + struct sifive_spi *spi = spi_controller_get_devdata(spi_dev->controller); + u8 opcode = op->cmd.opcode; + int ret; + + spi->fmt_proto = op->cmd.buswidth; + + sifive_spi_prep_device(spi, spi_dev); + sifive_spi_set_cs(spi, spi_dev); + + /* send the opcode */ + ret = sifive_spi_transfer_one(spi_dev, 1, &opcode, NULL); + if (ret < 0) { + dev_err(dev, "failed to xfer opcode\n"); + goto out; + } + + if (!op->addr.nbytes && !op->data.nbytes) + goto out; + + /* send the addr + dummy */ + if (op->addr.nbytes) { + int i, op_len = op->addr.nbytes + op->dummy.nbytes; + u8 *op_buf; + + op_buf = malloc(op_len); + if (!op_buf) { + ret = -ENOMEM; + goto out; + } + + /* fill address */ + for (i = 0; i < op->addr.nbytes; i++) + op_buf[i] = op->addr.val >> + (8 * (op->addr.nbytes - i - 1)); + + /* fill dummy */ + memset(op_buf + op->addr.nbytes, 0xff, op->dummy.nbytes); + + spi->fmt_proto = op->addr.buswidth; + + ret = sifive_spi_transfer_one(spi_dev, op_len, op_buf, NULL); + free(op_buf); + if (ret < 0) { + dev_err(dev, "failed to xfer addr + dummy\n"); + goto out; + } + } + + /* send/received the data */ + if (op->data.nbytes) { + const void *tx_buf = NULL; + void *rx_buf = NULL; + + if (op->data.dir == SPI_MEM_DATA_IN) + rx_buf = op->data.buf.in; + else + tx_buf = op->data.buf.out; + + spi->fmt_proto = op->data.buswidth; + + ret = sifive_spi_transfer_one(spi_dev, op->data.nbytes, + tx_buf, rx_buf); + if (ret) { + dev_err(dev, "failed to xfer data\n"); + goto out; + } + } + +out: + sifive_spi_clear_cs(spi); + return ret; +} + +static void sifive_spi_set_speed(struct sifive_spi *spi, uint speed) +{ + u32 scale; + + if (speed > spi->freq) + speed = spi->freq; + + /* Cofigure max speed */ + scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1) + & SIFIVE_SPI_SCKDIV_DIV_MASK; + writel(scale, spi->regs + SIFIVE_SPI_REG_SCKDIV); +} + +static void sifive_spi_set_mode(struct sifive_spi *spi, uint mode) +{ + u32 cr; + + /* Switch clock mode bits */ + cr = readl(spi->regs + SIFIVE_SPI_REG_SCKMODE) & + ~SIFIVE_SPI_SCKMODE_MODE_MASK; + if (mode & SPI_CPHA) + cr |= SIFIVE_SPI_SCKMODE_PHA; + if (mode & SPI_CPOL) + cr |= SIFIVE_SPI_SCKMODE_POL; + + writel(cr, spi->regs + SIFIVE_SPI_REG_SCKMODE); +} + +static int sifive_spi_setup(struct spi_device *spi_dev) +{ + struct sifive_spi *spi = to_sifive_spi(spi_dev->controller); + + sifive_spi_set_mode(spi, spi_dev->mode); + sifive_spi_set_speed(spi, spi_dev->max_speed_hz); + + return 0; +} + +static void sifive_spi_init_hw(struct sifive_spi *spi) +{ + struct device_d *dev = spi->ctlr.dev; + u32 cs_bits; + + /* probe the number of CS lines */ + spi->cs_inactive = readl(spi->regs + SIFIVE_SPI_REG_CSDEF); + writel(0xffffffffU, spi->regs + SIFIVE_SPI_REG_CSDEF); + cs_bits = readl(spi->regs + SIFIVE_SPI_REG_CSDEF); + writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF); + if (!cs_bits) { + dev_warn(dev, "Could not auto probe CS lines\n"); + return; + } + + spi->ctlr.num_chipselect = ilog2(cs_bits) + 1; + if (spi->ctlr.num_chipselect > SIFIVE_SPI_MAX_CS) { + dev_warn(dev, "Invalid number of spi slaves\n"); + return; + } + + /* Watermark interrupts are disabled by default */ + writel(0, spi->regs + SIFIVE_SPI_REG_IE); + + /* Default watermark FIFO threshold values */ + writel(1, spi->regs + SIFIVE_SPI_REG_TXMARK); + writel(0, spi->regs + SIFIVE_SPI_REG_RXMARK); + + /* Set CS/SCK Delays and Inactive Time to defaults */ + writel(SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1), + spi->regs + SIFIVE_SPI_REG_DELAY0); + writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), + spi->regs + SIFIVE_SPI_REG_DELAY1); + + /* Exit specialized memory-mapped SPI flash mode */ + writel(0, spi->regs + SIFIVE_SPI_REG_FCTRL); +} + +static const struct spi_controller_mem_ops sifive_spi_mem_ops = { + .exec_op = sifive_spi_exec_op, +}; + +static void sifive_spi_dt_probe(struct sifive_spi *spi) +{ + struct device_node *node = spi->ctlr.dev->device_node; + + spi->fifo_depth = SIFIVE_SPI_DEFAULT_DEPTH; + of_property_read_u32(node, "sifive,fifo-depth", &spi->fifo_depth); + + spi->bits_per_word = SIFIVE_SPI_DEFAULT_BITS; + of_property_read_u32(node, "sifive,max-bits-per-word", &spi->bits_per_word); +} + +static int sifive_spi_probe(struct device_d *dev) +{ + struct sifive_spi *spi; + struct resource *iores; + struct spi_controller *ctlr; + struct clk *clkdev; + + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + + spi = xzalloc(sizeof(*spi)); + + spi->regs = IOMEM(iores->start); + if (!spi->regs) + return -ENODEV; + + ctlr = &spi->ctlr; + ctlr->dev = dev; + + ctlr->setup = sifive_spi_setup; + ctlr->transfer = sifive_spi_transfer; + ctlr->mem_ops = &sifive_spi_mem_ops; + + ctlr->bus_num = -1; + + spi_controller_set_devdata(ctlr, spi); + + sifive_spi_dt_probe(spi); + + clkdev = clk_get(dev, NULL); + if (IS_ERR(clkdev)) + return PTR_ERR(clkdev); + + spi->freq = clk_get_rate(clkdev); + + /* init the sifive spi hw */ + sifive_spi_init_hw(spi); + + return spi_register_master(ctlr); +} + +static const struct of_device_id sifive_spi_ids[] = { + { .compatible = "sifive,spi0" }, + { /* sentinel */ } +}; + +static struct driver_d sifive_spi_driver = { + .name = "sifive_spi", + .probe = sifive_spi_probe, + .of_compatible = sifive_spi_ids, +}; +coredevice_platform_driver(sifive_spi_driver); diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index fd0ec754e0..30aaef90ac 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -23,6 +23,11 @@ #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ +struct dwc3_match_data { + const struct clk_bulk_data *clks; + const int num_clks; +}; + /** * dwc3_get_dr_mode - Validates and sets dr_mode * @dwc: pointer to our context structure @@ -326,12 +331,6 @@ err0: return ret; } -static const struct clk_bulk_data dwc3_core_clks[] = { - { .id = "ref" }, - { .id = "bus_early" }, - { .id = "suspend" }, -}; - /* * dwc3_frame_length_adjustment - Adjusts frame length if required * @dwc3: Pointer to our controller context structure @@ -1098,20 +1097,23 @@ static void dwc3_coresoft_reset(struct dwc3 *dwc) static int dwc3_probe(struct device_d *dev) { + const struct dwc3_match_data *match; struct dwc3 *dwc; int ret; dwc = xzalloc(sizeof(*dwc)); dev->priv = dwc; - dwc->clks = xmemdup(dwc3_core_clks, sizeof(dwc3_core_clks)); + match = device_get_match_data(dev); + dwc->clks = xmemdup(match->clks, match->num_clks * + sizeof(struct clk_bulk_data)); dwc->dev = dev; dwc->regs = dev_get_mem_region(dwc->dev, 0) + DWC3_GLOBALS_REGS_START; dwc3_get_properties(dwc); if (dev->device_node) { - dwc->num_clks = ARRAY_SIZE(dwc3_core_clks); + dwc->num_clks = match->num_clks; if (of_find_property(dev->device_node, "clocks", NULL)) { ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks); @@ -1176,12 +1178,40 @@ static void dwc3_remove(struct device_d *dev) clk_bulk_put(dwc->num_clks, dwc->clks); } +static const struct clk_bulk_data dwc3_core_clks[] = { + { .id = "ref" }, + { .id = "bus_early" }, + { .id = "suspend" }, +}; + +static const struct dwc3_match_data dwc3_default = { + .clks = dwc3_core_clks, + .num_clks = ARRAY_SIZE(dwc3_core_clks), +}; + +static const struct clk_bulk_data dwc3_core_clks_rk3568[] = { + { .id = "ref_clk" }, + { .id = "bus_clk" }, + { .id = "suspend_clk" }, +}; + +static const struct dwc3_match_data dwc3_rk3568 = { + .clks = dwc3_core_clks_rk3568, + .num_clks = ARRAY_SIZE(dwc3_core_clks_rk3568), +}; + static const struct of_device_id of_dwc3_match[] = { { - .compatible = "snps,dwc3" + .compatible = "snps,dwc3", + .data = &dwc3_default, + }, + { + .compatible = "synopsys,dwc3", + .data = &dwc3_default, }, { - .compatible = "synopsys,dwc3" + .compatible = "rockchip,rk3568-dwc3", + .data = &dwc3_rk3568, }, { }, }; diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index dcdc6c2135..a20b7bbee9 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -75,7 +75,7 @@ config DRIVER_VIDEO_S3C24XX config DRIVER_VIDEO_OMAP bool "OMAP framebuffer driver" - depends on ARCH_OMAP4 + depends on ARCH_OMAP4 || COMPILE_TEST help Add support for OMAP Display Controller. Currently this driver only supports OMAP4 SoCs in DISPC parallel mode on diff --git a/drivers/video/omap.c b/drivers/video/omap.c index 62c51a1dfc..ca41ab36fc 100644 --- a/drivers/video/omap.c +++ b/drivers/video/omap.c @@ -20,8 +20,7 @@ #include <clock.h> #include <linux/err.h> -#include <mach/omap4-silicon.h> -#include <mach/omap-fb.h> +#include <video/omap-fb.h> #include <mmu.h> diff --git a/dts/Bindings/clock/imx8m-clock.yaml b/dts/Bindings/clock/imx8m-clock.yaml index 625f573a7b..458c7645ee 100644 --- a/dts/Bindings/clock/imx8m-clock.yaml +++ b/dts/Bindings/clock/imx8m-clock.yaml @@ -55,8 +55,6 @@ allOf: then: properties: clocks: - minItems: 7 - maxItems: 7 items: - description: 32k osc - description: 25m osc @@ -66,8 +64,6 @@ allOf: - description: ext3 clock input - description: ext4 clock input clock-names: - minItems: 7 - maxItems: 7 items: - const: ckil - const: osc_25m diff --git a/dts/Bindings/clock/microchip,mpfs.yaml b/dts/Bindings/clock/microchip,mpfs.yaml index 0c15afa221..016a4f378b 100644 --- a/dts/Bindings/clock/microchip,mpfs.yaml +++ b/dts/Bindings/clock/microchip,mpfs.yaml @@ -22,7 +22,16 @@ properties: const: microchip,mpfs-clkcfg reg: - maxItems: 1 + items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for the, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable and reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss + pll clocks: maxItems: 1 @@ -51,7 +60,7 @@ examples: #size-cells = <2>; clkcfg: clock-controller@20002000 { compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>; + reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; clocks = <&ref>; #clock-cells = <1>; }; diff --git a/dts/Bindings/display/bridge/renesas,lvds.yaml b/dts/Bindings/display/bridge/renesas,lvds.yaml index a51baf8a4c..bb9dbfb9be 100644 --- a/dts/Bindings/display/bridge/renesas,lvds.yaml +++ b/dts/Bindings/display/bridge/renesas,lvds.yaml @@ -95,7 +95,6 @@ then: properties: clocks: minItems: 1 - maxItems: 4 items: - description: Functional clock - description: EXTAL input clock @@ -104,7 +103,6 @@ then: clock-names: minItems: 1 - maxItems: 4 items: - const: fck # The LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks. @@ -128,12 +126,10 @@ then: else: properties: clocks: - maxItems: 1 items: - description: Functional clock clock-names: - maxItems: 1 items: - const: fck diff --git a/dts/Bindings/display/renesas,du.yaml b/dts/Bindings/display/renesas,du.yaml index 56cedcd6d5..b3e5880220 100644 --- a/dts/Bindings/display/renesas,du.yaml +++ b/dts/Bindings/display/renesas,du.yaml @@ -109,7 +109,6 @@ allOf: properties: clocks: minItems: 1 - maxItems: 3 items: - description: Functional clock - description: DU_DOTCLKIN0 input clock @@ -117,7 +116,6 @@ allOf: clock-names: minItems: 1 - maxItems: 3 items: - const: du.0 - pattern: '^dclkin\.[01]$' @@ -159,7 +157,6 @@ allOf: properties: clocks: minItems: 2 - maxItems: 4 items: - description: Functional clock for DU0 - description: Functional clock for DU1 @@ -168,7 +165,6 @@ allOf: clock-names: minItems: 2 - maxItems: 4 items: - const: du.0 - const: du.1 @@ -216,7 +212,6 @@ allOf: properties: clocks: minItems: 2 - maxItems: 4 items: - description: Functional clock for DU0 - description: Functional clock for DU1 @@ -225,7 +220,6 @@ allOf: clock-names: minItems: 2 - maxItems: 4 items: - const: du.0 - const: du.1 @@ -271,7 +265,6 @@ allOf: properties: clocks: minItems: 2 - maxItems: 4 items: - description: Functional clock for DU0 - description: Functional clock for DU1 @@ -280,7 +273,6 @@ allOf: clock-names: minItems: 2 - maxItems: 4 items: - const: du.0 - const: du.1 @@ -327,7 +319,6 @@ allOf: properties: clocks: minItems: 2 - maxItems: 4 items: - description: Functional clock for DU0 - description: Functional clock for DU1 @@ -336,7 +327,6 @@ allOf: clock-names: minItems: 2 - maxItems: 4 items: - const: du.0 - const: du.1 @@ -386,7 +376,6 @@ allOf: properties: clocks: minItems: 3 - maxItems: 6 items: - description: Functional clock for DU0 - description: Functional clock for DU1 @@ -397,7 +386,6 @@ allOf: clock-names: minItems: 3 - maxItems: 6 items: - const: du.0 - const: du.1 @@ -448,7 +436,6 @@ allOf: properties: clocks: minItems: 4 - maxItems: 8 items: - description: Functional clock for DU0 - description: Functional clock for DU1 @@ -461,7 +448,6 @@ allOf: clock-names: minItems: 4 - maxItems: 8 items: - const: du.0 - const: du.1 @@ -525,7 +511,6 @@ allOf: properties: clocks: minItems: 3 - maxItems: 6 items: - description: Functional clock for DU0 - description: Functional clock for DU1 @@ -536,7 +521,6 @@ allOf: clock-names: minItems: 3 - maxItems: 6 items: - const: du.0 - const: du.1 @@ -596,7 +580,6 @@ allOf: properties: clocks: minItems: 3 - maxItems: 6 items: - description: Functional clock for DU0 - description: Functional clock for DU1 @@ -607,7 +590,6 @@ allOf: clock-names: minItems: 3 - maxItems: 6 items: - const: du.0 - const: du.1 @@ -666,14 +648,12 @@ allOf: properties: clocks: minItems: 1 - maxItems: 2 items: - description: Functional clock for DU0 - description: DU_DOTCLKIN0 input clock clock-names: minItems: 1 - maxItems: 2 items: - const: du.0 - const: dclkin.0 @@ -723,7 +703,6 @@ allOf: properties: clocks: minItems: 2 - maxItems: 4 items: - description: Functional clock for DU0 - description: Functional clock for DU1 @@ -732,7 +711,6 @@ allOf: clock-names: minItems: 2 - maxItems: 4 items: - const: du.0 - const: du.1 @@ -791,7 +769,6 @@ allOf: - description: Functional clock clock-names: - maxItems: 1 items: - const: du.0 diff --git a/dts/Bindings/dma/qcom,gpi.yaml b/dts/Bindings/dma/qcom,gpi.yaml index e614fe3187..d09d79d740 100644 --- a/dts/Bindings/dma/qcom,gpi.yaml +++ b/dts/Bindings/dma/qcom,gpi.yaml @@ -29,6 +29,7 @@ properties: interrupts: description: Interrupt lines for each GPI instance + minItems: 1 maxItems: 13 "#dma-cells": diff --git a/dts/Bindings/hwmon/ti,tmp421.yaml b/dts/Bindings/hwmon/ti,tmp421.yaml index 36f649938f..a6f1fa75a6 100644 --- a/dts/Bindings/hwmon/ti,tmp421.yaml +++ b/dts/Bindings/hwmon/ti,tmp421.yaml @@ -58,10 +58,9 @@ patternProperties: description: | The value (two's complement) to be programmed in the channel specific N correction register. For remote channels only. - $ref: /schemas/types.yaml#/definitions/uint32 - items: - minimum: 0 - maximum: 255 + $ref: /schemas/types.yaml#/definitions/int32 + minimum: -128 + maximum: 127 required: - reg diff --git a/dts/Bindings/iio/adc/st,stm32-adc.yaml b/dts/Bindings/iio/adc/st,stm32-adc.yaml index 4d6074518b..fa8da42cb1 100644 --- a/dts/Bindings/iio/adc/st,stm32-adc.yaml +++ b/dts/Bindings/iio/adc/st,stm32-adc.yaml @@ -138,7 +138,6 @@ allOf: - const: bus - const: adc minItems: 1 - maxItems: 2 interrupts: items: @@ -170,7 +169,6 @@ allOf: - const: bus - const: adc minItems: 1 - maxItems: 2 interrupts: items: diff --git a/dts/Bindings/leds/leds-mt6360.yaml b/dts/Bindings/leds/leds-mt6360.yaml index b2fe6eb893..10f95bf1d6 100644 --- a/dts/Bindings/leds/leds-mt6360.yaml +++ b/dts/Bindings/leds/leds-mt6360.yaml @@ -43,8 +43,6 @@ patternProperties: - 4 # LED output FLASH1 - 5 # LED output FLASH2 -unevaluatedProperties: false - required: - compatible - "#address-cells" diff --git a/dts/Bindings/mfd/atmel-flexcom.txt b/dts/Bindings/mfd/atmel-flexcom.txt index 692300117c..9d83753563 100644 --- a/dts/Bindings/mfd/atmel-flexcom.txt +++ b/dts/Bindings/mfd/atmel-flexcom.txt @@ -54,7 +54,7 @@ flexcom@f8034000 { clock-names = "spi_clk"; atmel,fifo-size = <32>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at25f512b"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/dts/Bindings/mmc/nvidia,tegra20-sdhci.yaml b/dts/Bindings/mmc/nvidia,tegra20-sdhci.yaml index f3f4d5b027..fe02702076 100644 --- a/dts/Bindings/mmc/nvidia,tegra20-sdhci.yaml +++ b/dts/Bindings/mmc/nvidia,tegra20-sdhci.yaml @@ -202,22 +202,17 @@ allOf: clocks: items: - description: module clock - minItems: 1 - maxItems: 1 else: properties: clocks: items: - description: module clock - description: timeout clock - minItems: 2 - maxItems: 2 + clock-names: items: - const: sdhci - const: tmclk - minItems: 2 - maxItems: 2 required: - clock-names diff --git a/dts/Bindings/mtd/gpmi-nand.yaml b/dts/Bindings/mtd/gpmi-nand.yaml index 9d764e654e..849aeae319 100644 --- a/dts/Bindings/mtd/gpmi-nand.yaml +++ b/dts/Bindings/mtd/gpmi-nand.yaml @@ -147,8 +147,6 @@ allOf: - description: SoC gpmi io clock - description: SoC gpmi bch apb clock clock-names: - minItems: 2 - maxItems: 2 items: - const: gpmi_io - const: gpmi_bch_apb diff --git a/dts/Bindings/net/can/bosch,c_can.yaml b/dts/Bindings/net/can/bosch,c_can.yaml index 8bad328b18..51aa89ac7e 100644 --- a/dts/Bindings/net/can/bosch,c_can.yaml +++ b/dts/Bindings/net/can/bosch,c_can.yaml @@ -80,8 +80,6 @@ if: then: properties: interrupts: - minItems: 4 - maxItems: 4 items: - description: Error and status IRQ - description: Message object IRQ @@ -91,7 +89,6 @@ then: else: properties: interrupts: - maxItems: 1 items: - description: Error and status IRQ diff --git a/dts/Bindings/net/dsa/realtek.yaml b/dts/Bindings/net/dsa/realtek.yaml index 8756060895..99ee4b5b93 100644 --- a/dts/Bindings/net/dsa/realtek.yaml +++ b/dts/Bindings/net/dsa/realtek.yaml @@ -27,32 +27,25 @@ description: The realtek-mdio driver is an MDIO driver and it must be inserted inside an MDIO node. + The compatible string is only used to identify which (silicon) family the + switch belongs to. Roughly speaking, a family is any set of Realtek switches + whose chip identification register(s) have a common location and semantics. + The different models in a given family can be automatically disambiguated by + parsing the chip identification register(s) according to the given family, + avoiding the need for a unique compatible string for each model. + properties: compatible: enum: - realtek,rtl8365mb - - realtek,rtl8366 - realtek,rtl8366rb - - realtek,rtl8366s - - realtek,rtl8367 - - realtek,rtl8367b - - realtek,rtl8367rb - - realtek,rtl8367s - - realtek,rtl8368s - - realtek,rtl8369 - - realtek,rtl8370 description: | - realtek,rtl8365mb: 4+1 ports - realtek,rtl8366: 5+1 ports - realtek,rtl8366rb: 5+1 ports - realtek,rtl8366s: 5+1 ports - realtek,rtl8367: - realtek,rtl8367b: - realtek,rtl8367rb: 5+2 ports - realtek,rtl8367s: 5+2 ports - realtek,rtl8368s: 8 ports - realtek,rtl8369: 8+1 ports - realtek,rtl8370: 8+2 ports + realtek,rtl8365mb: + Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB, + RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S, + RTL8367SB, RTL8370MB, RTL8310SR + realtek,rtl8366rb: + Use with models RTL8366RB, RTL8366S mdc-gpios: description: GPIO line for the MDC clock line. @@ -335,7 +328,7 @@ examples: #size-cells = <0>; switch@29 { - compatible = "realtek,rtl8367s"; + compatible = "realtek,rtl8365mb"; reg = <29>; reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; diff --git a/dts/Bindings/pci/apple,pcie.yaml b/dts/Bindings/pci/apple,pcie.yaml index 7f01e15fc8..daf602ac0d 100644 --- a/dts/Bindings/pci/apple,pcie.yaml +++ b/dts/Bindings/pci/apple,pcie.yaml @@ -142,7 +142,6 @@ examples: device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; reset-gpios = <&pinctrl_ap 152 0>; - max-link-speed = <2>; #address-cells = <3>; #size-cells = <2>; @@ -153,7 +152,6 @@ examples: device_type = "pci"; reg = <0x800 0x0 0x0 0x0 0x0>; reset-gpios = <&pinctrl_ap 153 0>; - max-link-speed = <2>; #address-cells = <3>; #size-cells = <2>; @@ -164,7 +162,6 @@ examples: device_type = "pci"; reg = <0x1000 0x0 0x0 0x0 0x0>; reset-gpios = <&pinctrl_ap 33 0>; - max-link-speed = <1>; #address-cells = <3>; #size-cells = <2>; diff --git a/dts/Bindings/phy/brcm,sata-phy.yaml b/dts/Bindings/phy/brcm,sata-phy.yaml index cb1aa32533..435b971dfd 100644 --- a/dts/Bindings/phy/brcm,sata-phy.yaml +++ b/dts/Bindings/phy/brcm,sata-phy.yaml @@ -102,19 +102,17 @@ if: then: properties: reg: - maxItems: 2 + minItems: 2 + reg-names: - items: - - const: "phy" - - const: "phy-ctrl" + minItems: 2 else: properties: reg: maxItems: 1 + reg-names: maxItems: 1 - items: - - const: "phy" required: - compatible diff --git a/dts/Bindings/pinctrl/pincfg-node.yaml b/dts/Bindings/pinctrl/pincfg-node.yaml index 4b22a9e3a4..f5a121311f 100644 --- a/dts/Bindings/pinctrl/pincfg-node.yaml +++ b/dts/Bindings/pinctrl/pincfg-node.yaml @@ -52,11 +52,19 @@ properties: hardware supporting it the pull strength in Ohm. drive-push-pull: - type: boolean + oneOf: + - type: boolean + - $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + deprecated: true description: drive actively high and low drive-open-drain: - type: boolean + oneOf: + - type: boolean + - $ref: /schemas/types.yaml#/definitions/uint32 + const: 1 # No known cases of 0 + deprecated: true description: drive with open drain drive-open-source: diff --git a/dts/Bindings/regulator/richtek,rt5190a-regulator.yaml b/dts/Bindings/regulator/richtek,rt5190a-regulator.yaml index 28725c5467..edb411be03 100644 --- a/dts/Bindings/regulator/richtek,rt5190a-regulator.yaml +++ b/dts/Bindings/regulator/richtek,rt5190a-regulator.yaml @@ -58,7 +58,7 @@ properties: type: object $ref: regulator.yaml# description: | - regulator description for buck1 and buck4. + regulator description for buck1 to buck4, and ldo. properties: regulator-allowed-modes: diff --git a/dts/Bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/dts/Bindings/rtc/allwinner,sun6i-a31-rtc.yaml index 0b767fec39..6b38bd7eb3 100644 --- a/dts/Bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/dts/Bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -71,7 +71,6 @@ allOf: then: properties: clock-output-names: - minItems: 1 maxItems: 1 - if: @@ -102,7 +101,6 @@ allOf: properties: clock-output-names: minItems: 3 - maxItems: 3 - if: properties: @@ -113,16 +111,12 @@ allOf: then: properties: clocks: - minItems: 3 - maxItems: 3 items: - description: Bus clock for register access - description: 24 MHz oscillator - description: 32 kHz clock from the CCU clock-names: - minItems: 3 - maxItems: 3 items: - const: bus - const: hosc @@ -142,7 +136,6 @@ allOf: properties: clocks: minItems: 3 - maxItems: 4 items: - description: Bus clock for register access - description: 24 MHz oscillator @@ -151,7 +144,6 @@ allOf: clock-names: minItems: 3 - maxItems: 4 items: - const: bus - const: hosc @@ -174,14 +166,12 @@ allOf: then: properties: interrupts: - minItems: 1 maxItems: 1 else: properties: interrupts: minItems: 2 - maxItems: 2 required: - "#clock-cells" diff --git a/dts/Bindings/rtc/microchip,mfps-rtc.yaml b/dts/Bindings/rtc/microchip,mfps-rtc.yaml index a2e984ea35..500c62becd 100644 --- a/dts/Bindings/rtc/microchip,mfps-rtc.yaml +++ b/dts/Bindings/rtc/microchip,mfps-rtc.yaml @@ -31,11 +31,19 @@ properties: to that of the RTC's count register. clocks: - maxItems: 1 + items: + - description: | + AHB clock + - description: | + Reference clock: divided by the prescaler to create a time-based + strobe (typically 1 Hz) for the calendar counter. By default, the rtc + on the PolarFire SoC shares it's reference with MTIMER so this will + be a 1 MHz clock. clock-names: items: - const: rtc + - const: rtcref required: - compatible @@ -48,11 +56,12 @@ additionalProperties: false examples: - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" rtc@20124000 { compatible = "microchip,mpfs-rtc"; reg = <0x20124000 0x1000>; - clocks = <&clkcfg 21>; - clock-names = "rtc"; + clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; + clock-names = "rtc", "rtcref"; interrupts = <80>, <81>; }; ... diff --git a/dts/Bindings/serial/samsung_uart.yaml b/dts/Bindings/serial/samsung_uart.yaml index d4688e317f..901c1e2cea 100644 --- a/dts/Bindings/serial/samsung_uart.yaml +++ b/dts/Bindings/serial/samsung_uart.yaml @@ -100,7 +100,6 @@ allOf: maxItems: 3 clock-names: minItems: 2 - maxItems: 3 items: - const: uart - pattern: '^clk_uart_baud[0-1]$' @@ -118,11 +117,8 @@ allOf: then: properties: clocks: - minItems: 2 maxItems: 2 clock-names: - minItems: 2 - maxItems: 2 items: - const: uart - const: clk_uart_baud0 diff --git a/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml b/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml index c21c807b66..34f6ee9de3 100644 --- a/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -89,7 +89,6 @@ allOf: properties: dmas: minItems: 1 - maxItems: 2 items: - description: RX DMA Channel - description: TX DMA Channel diff --git a/dts/Bindings/sound/ti,j721e-cpb-audio.yaml b/dts/Bindings/sound/ti,j721e-cpb-audio.yaml index 6806f53a4a..20ea5883b7 100644 --- a/dts/Bindings/sound/ti,j721e-cpb-audio.yaml +++ b/dts/Bindings/sound/ti,j721e-cpb-audio.yaml @@ -80,7 +80,6 @@ allOf: then: properties: clocks: - minItems: 6 items: - description: AUXCLK clock for McASP used by CPB audio - description: Parent for CPB_McASP auxclk (for 48KHz) @@ -107,7 +106,6 @@ allOf: then: properties: clocks: - maxItems: 4 items: - description: AUXCLK clock for McASP used by CPB audio - description: Parent for CPB_McASP auxclk (for 48KHz) diff --git a/dts/Bindings/thermal/rcar-gen3-thermal.yaml b/dts/Bindings/thermal/rcar-gen3-thermal.yaml index f963204e0b..1368d90da0 100644 --- a/dts/Bindings/thermal/rcar-gen3-thermal.yaml +++ b/dts/Bindings/thermal/rcar-gen3-thermal.yaml @@ -67,7 +67,6 @@ then: properties: reg: minItems: 2 - maxItems: 3 items: - description: TSC1 registers - description: TSC2 registers diff --git a/dts/Bindings/ufs/cdns,ufshc.yaml b/dts/Bindings/ufs/cdns,ufshc.yaml index d227dea368..fb45f66d64 100644 --- a/dts/Bindings/ufs/cdns,ufshc.yaml +++ b/dts/Bindings/ufs/cdns,ufshc.yaml @@ -43,6 +43,9 @@ properties: - const: phy_clk - const: ref_clk + power-domains: + maxItems: 1 + reg: maxItems: 1 diff --git a/dts/Bindings/usb/samsung,exynos-usb2.yaml b/dts/Bindings/usb/samsung,exynos-usb2.yaml index 340dff8d19..9c92defbba 100644 --- a/dts/Bindings/usb/samsung,exynos-usb2.yaml +++ b/dts/Bindings/usb/samsung,exynos-usb2.yaml @@ -62,6 +62,7 @@ required: - interrupts - phys - phy-names + - reg allOf: - if: diff --git a/dts/include/dt-bindings/clock/microchip,mpfs-clock.h b/dts/include/dt-bindings/clock/microchip,mpfs-clock.h index 73f2a93248..4048669bf7 100644 --- a/dts/include/dt-bindings/clock/microchip,mpfs-clock.h +++ b/dts/include/dt-bindings/clock/microchip,mpfs-clock.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Daire McNamara,<daire.mcnamara@microchip.com> - * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. + * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ @@ -42,4 +42,7 @@ #define CLK_ATHENA 31 #define CLK_CFM 32 +#define CLK_RTCREF 33 +#define CLK_MSSPLL 34 + #endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ diff --git a/dts/include/dt-bindings/input/linux-event-codes.h b/dts/include/dt-bindings/input/linux-event-codes.h index 7989d9483e..dff8e7f170 100644 --- a/dts/include/dt-bindings/input/linux-event-codes.h +++ b/dts/include/dt-bindings/input/linux-event-codes.h @@ -662,6 +662,27 @@ /* Select an area of screen to be copied */ #define KEY_SELECTIVE_SCREENSHOT 0x27a +/* Move the focus to the next or previous user controllable element within a UI container */ +#define KEY_NEXT_ELEMENT 0x27b +#define KEY_PREVIOUS_ELEMENT 0x27c + +/* Toggle Autopilot engagement */ +#define KEY_AUTOPILOT_ENGAGE_TOGGLE 0x27d + +/* Shortcut Keys */ +#define KEY_MARK_WAYPOINT 0x27e +#define KEY_SOS 0x27f +#define KEY_NAV_CHART 0x280 +#define KEY_FISHING_CHART 0x281 +#define KEY_SINGLE_RANGE_RADAR 0x282 +#define KEY_DUAL_RANGE_RADAR 0x283 +#define KEY_RADAR_OVERLAY 0x284 +#define KEY_TRADITIONAL_SONAR 0x285 +#define KEY_CLEARVU_SONAR 0x286 +#define KEY_SIDEVU_SONAR 0x287 +#define KEY_NAV_INFO 0x288 +#define KEY_BRIGHTNESS_MENU 0x289 + /* * Some keyboards have keys which do not have a defined meaning, these keys * are intended to be programmed / bound to macros by the user. For most diff --git a/dts/src/arc/hsdk.dts b/dts/src/arc/hsdk.dts index dcaa44e408..f48ba03e9b 100644 --- a/dts/src/arc/hsdk.dts +++ b/dts/src/arc/hsdk.dts @@ -275,7 +275,7 @@ cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>, <&creg_gpio 1 GPIO_ACTIVE_LOW>; - spi-flash@0 { + flash@0 { compatible = "sst26wf016b", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; diff --git a/dts/src/arm/am33xx-l4.dtsi b/dts/src/arm/am33xx-l4.dtsi index c9629cb5cc..7da42a5b95 100644 --- a/dts/src/arm/am33xx-l4.dtsi +++ b/dts/src/arm/am33xx-l4.dtsi @@ -263,6 +263,8 @@ compatible = "ti,am3359-tscadc"; reg = <0x0 0x1000>; interrupts = <16>; + clocks = <&adc_tsc_fck>; + clock-names = "fck"; status = "disabled"; dmas = <&edma 53 0>, <&edma 57 0>; dma-names = "fifo0", "fifo1"; diff --git a/dts/src/arm/am3517-evm.dts b/dts/src/arm/am3517-evm.dts index 0d2fac98ce..c8b80f156e 100644 --- a/dts/src/arm/am3517-evm.dts +++ b/dts/src/arm/am3517-evm.dts @@ -161,6 +161,8 @@ /* HS USB Host PHY on PORT 1 */ hsusb1_phy: hsusb1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_rst_pins>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */ #phy-cells = <0>; @@ -168,7 +170,9 @@ }; &davinci_emac { - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins>; + status = "okay"; }; &davinci_mdio { @@ -193,6 +197,8 @@ }; &i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; clock-frequency = <400000>; /* User DIP swithes [1:8] / User LEDS [1:2] */ tca6416: gpio@21 { @@ -205,6 +211,8 @@ }; &i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; clock-frequency = <400000>; }; @@ -223,6 +231,8 @@ }; &usbhshost { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_pins>; port1-mode = "ehci-phy"; }; @@ -231,8 +241,35 @@ }; &omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_rst_pins>; + + ethernet_pins: pinmux_ethernet_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT | MUX_MODE0) /* rmii_mdio_data */ + OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /* rmii_mdio_clk */ + OMAP3_CORE1_IOPAD(0x2202, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd0 */ + OMAP3_CORE1_IOPAD(0x2204, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd1 */ + OMAP3_CORE1_IOPAD(0x2206, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_crs_dv */ + OMAP3_CORE1_IOPAD(0x2208, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_rxer */ + OMAP3_CORE1_IOPAD(0x220a, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd0 */ + OMAP3_CORE1_IOPAD(0x220c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd1 */ + OMAP3_CORE1_IOPAD(0x220e, PIN_OUTPUT_PULLDOWN |MUX_MODE0) /* rmii_txen */ + OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + >; + }; leds_pins: pinmux_leds_pins { pinctrl-single,pins = < @@ -300,8 +337,6 @@ }; &omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_pins>; hsusb1_pins: pinmux_hsusb1_pins { pinctrl-single,pins = < diff --git a/dts/src/arm/am3517-som.dtsi b/dts/src/arm/am3517-som.dtsi index 8b669e2eaf..f7b680f6c4 100644 --- a/dts/src/arm/am3517-som.dtsi +++ b/dts/src/arm/am3517-som.dtsi @@ -69,6 +69,8 @@ }; &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>; s35390a: s35390a@30 { @@ -179,6 +181,13 @@ &omap3_pmx_core { + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */ diff --git a/dts/src/arm/at91-dvk_su60_somc.dtsi b/dts/src/arm/at91-dvk_su60_somc.dtsi index c1c8650daf..3542ad8a24 100644 --- a/dts/src/arm/at91-dvk_su60_somc.dtsi +++ b/dts/src/arm/at91-dvk_su60_somc.dtsi @@ -44,7 +44,7 @@ status = "okay"; /* spi0.0: 4M Flash Macronix MX25R4035FM1IL0 */ - spi-flash@0 { + flash@0 { compatible = "mxicy,mx25u4035", "jedec,spi-nor"; spi-max-frequency = <33000000>; reg = <0>; diff --git a/dts/src/arm/at91-kizbox3-hs.dts b/dts/src/arm/at91-kizbox3-hs.dts index f7d90cf1bb..2799b2a1f4 100644 --- a/dts/src/arm/at91-kizbox3-hs.dts +++ b/dts/src/arm/at91-kizbox3-hs.dts @@ -225,7 +225,7 @@ pinctrl_pio_io_reset: gpio_io_reset { pinmux = <PIN_PB30__GPIO>; bias-disable; - drive-open-drain; + drive-open-drain = <1>; output-low; }; pinctrl_pio_input: gpio_input { diff --git a/dts/src/arm/at91-kizbox3_common.dtsi b/dts/src/arm/at91-kizbox3_common.dtsi index 4656646284..abe27adfa4 100644 --- a/dts/src/arm/at91-kizbox3_common.dtsi +++ b/dts/src/arm/at91-kizbox3_common.dtsi @@ -211,7 +211,7 @@ pinmux = <PIN_PD12__FLEXCOM4_IO0>, //DATA <PIN_PD13__FLEXCOM4_IO1>; //CLK bias-disable; - drive-open-drain; + drive-open-drain = <1>; }; pinctrl_pwm0 { diff --git a/dts/src/arm/at91-q5xr5.dts b/dts/src/arm/at91-q5xr5.dts index 47a00062f0..9cf60b6f69 100644 --- a/dts/src/arm/at91-q5xr5.dts +++ b/dts/src/arm/at91-q5xr5.dts @@ -125,7 +125,7 @@ cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>; status = "okay"; - m25p80@0 { + flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/dts/src/arm/at91-sama5d27_wlsom1.dtsi b/dts/src/arm/at91-sama5d27_wlsom1.dtsi index 21c86171e4..ba621783ac 100644 --- a/dts/src/arm/at91-sama5d27_wlsom1.dtsi +++ b/dts/src/arm/at91-sama5d27_wlsom1.dtsi @@ -214,7 +214,7 @@ pinctrl-0 = <&pinctrl_qspi1_default>; status = "disabled"; - qspi1_flash: spi_flash@0 { + qspi1_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/dts/src/arm/at91-sama5d27_wlsom1_ek.dts b/dts/src/arm/at91-sama5d27_wlsom1_ek.dts index c145c4e5ef..5e8755f227 100644 --- a/dts/src/arm/at91-sama5d27_wlsom1_ek.dts +++ b/dts/src/arm/at91-sama5d27_wlsom1_ek.dts @@ -191,7 +191,7 @@ &qspi1 { status = "okay"; - qspi1_flash: spi_flash@0 { + qspi1_flash: flash@0 { status = "okay"; }; }; diff --git a/dts/src/arm/at91-sama5d2_xplained.dts b/dts/src/arm/at91-sama5d2_xplained.dts index 9bf2ec0ba3..cdfe891f9a 100644 --- a/dts/src/arm/at91-sama5d2_xplained.dts +++ b/dts/src/arm/at91-sama5d2_xplained.dts @@ -137,7 +137,7 @@ pinctrl-0 = <&pinctrl_spi0_default>; status = "okay"; - m25p80@0 { + flash@0 { compatible = "atmel,at25df321a"; reg = <0>; spi-max-frequency = <50000000>; diff --git a/dts/src/arm/at91-sama5d3_xplained.dts b/dts/src/arm/at91-sama5d3_xplained.dts index d72c042f28..a49c2966b4 100644 --- a/dts/src/arm/at91-sama5d3_xplained.dts +++ b/dts/src/arm/at91-sama5d3_xplained.dts @@ -57,8 +57,8 @@ }; spi0: spi@f0004000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_cs>; + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi0_cs>; cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; status = "okay"; }; @@ -171,8 +171,8 @@ }; spi1: spi@f8008000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_cs>; + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi1_cs>; cs-gpios = <&pioC 25 0>; status = "okay"; }; diff --git a/dts/src/arm/at91-sama5d4_ma5d4.dtsi b/dts/src/arm/at91-sama5d4_ma5d4.dtsi index 710cb72bda..fd1086f52b 100644 --- a/dts/src/arm/at91-sama5d4_ma5d4.dtsi +++ b/dts/src/arm/at91-sama5d4_ma5d4.dtsi @@ -49,7 +49,7 @@ cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; status = "okay"; - m25p80@0 { + flash@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/dts/src/arm/at91-sama5d4_xplained.dts b/dts/src/arm/at91-sama5d4_xplained.dts index d241c24f0d..e519d27479 100644 --- a/dts/src/arm/at91-sama5d4_xplained.dts +++ b/dts/src/arm/at91-sama5d4_xplained.dts @@ -81,8 +81,8 @@ }; spi1: spi@fc018000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_cs>; + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi1_cs>; cs-gpios = <&pioB 21 0>; status = "okay"; }; @@ -140,7 +140,7 @@ atmel,pins = <AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; }; - pinctrl_spi0_cs: spi0_cs_default { + pinctrl_spi1_cs: spi1_cs_default { atmel,pins = <AT91_PIOB 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; }; diff --git a/dts/src/arm/at91-sama5d4ek.dts b/dts/src/arm/at91-sama5d4ek.dts index fe432b6b7e..7017f626f3 100644 --- a/dts/src/arm/at91-sama5d4ek.dts +++ b/dts/src/arm/at91-sama5d4ek.dts @@ -65,7 +65,7 @@ spi0: spi@f8010000 { cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; status = "okay"; - m25p80@0 { + flash@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/dts/src/arm/at91-sama7g5ek.dts b/dts/src/arm/at91-sama7g5ek.dts index 08685a10ed..d83f76a6cd 100644 --- a/dts/src/arm/at91-sama7g5ek.dts +++ b/dts/src/arm/at91-sama7g5ek.dts @@ -495,7 +495,7 @@ pinctrl_flx3_default: flx3_default { pinmux = <PIN_PD16__FLEXCOM3_IO0>, <PIN_PD17__FLEXCOM3_IO1>; - bias-disable; + bias-pull-up; }; pinctrl_flx4_default: flx4_default { @@ -655,7 +655,7 @@ <PIN_PB21__QSPI0_INT>; bias-disable; slew-rate = <0>; - atmel,drive-strength = <ATMEL_PIO_DRVSTR_HI>; + atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>; }; pinctrl_sdmmc0_default: sdmmc0_default { diff --git a/dts/src/arm/at91-vinco.dts b/dts/src/arm/at91-vinco.dts index a51a3372af..ebeaa6ab50 100644 --- a/dts/src/arm/at91-vinco.dts +++ b/dts/src/arm/at91-vinco.dts @@ -59,7 +59,7 @@ spi0: spi@f8010000 { cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; status = "okay"; - m25p80@0 { + flash@0 { compatible = "n25q32b", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/dts/src/arm/at91rm9200ek.dts b/dts/src/arm/at91rm9200ek.dts index e1ef4e44e6..4624a6f076 100644 --- a/dts/src/arm/at91rm9200ek.dts +++ b/dts/src/arm/at91rm9200ek.dts @@ -73,7 +73,7 @@ spi0: spi@fffe0000 { status = "okay"; cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <15000000>; reg = <0>; @@ -94,7 +94,7 @@ status = "okay"; }; - nor_flash@10000000 { + flash@10000000 { compatible = "cfi-flash"; reg = <0x10000000 0x800000>; linux,mtd-name = "physmap-flash.0"; diff --git a/dts/src/arm/at91sam9260ek.dts b/dts/src/arm/at91sam9260ek.dts index ce96345d28..6381088ba2 100644 --- a/dts/src/arm/at91sam9260ek.dts +++ b/dts/src/arm/at91sam9260ek.dts @@ -92,7 +92,7 @@ spi0: spi@fffc8000 { cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; - mtd_dataflash@1 { + flash@1 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <50000000>; reg = <1>; diff --git a/dts/src/arm/at91sam9261ek.dts b/dts/src/arm/at91sam9261ek.dts index beed819609..8f11c0b7d7 100644 --- a/dts/src/arm/at91sam9261ek.dts +++ b/dts/src/arm/at91sam9261ek.dts @@ -145,7 +145,7 @@ cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>; status = "okay"; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; reg = <0>; spi-max-frequency = <15000000>; diff --git a/dts/src/arm/at91sam9263ek.dts b/dts/src/arm/at91sam9263ek.dts index 71f6057676..42e7340202 100644 --- a/dts/src/arm/at91sam9263ek.dts +++ b/dts/src/arm/at91sam9263ek.dts @@ -95,7 +95,7 @@ spi0: spi@fffa4000 { status = "okay"; cs-gpios = <&pioA 5 0>, <0>, <0>, <0>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/dts/src/arm/at91sam9g20ek_common.dtsi b/dts/src/arm/at91sam9g20ek_common.dtsi index 87bb39060e..85c17dd1c8 100644 --- a/dts/src/arm/at91sam9g20ek_common.dtsi +++ b/dts/src/arm/at91sam9g20ek_common.dtsi @@ -110,7 +110,7 @@ spi0: spi@fffc8000 { cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; - mtd_dataflash@1 { + flash@1 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <50000000>; reg = <1>; @@ -214,11 +214,23 @@ 24c512@50 { compatible = "atmel,24c512"; reg = <0x50>; + vcc-supply = <®_3v3>; }; wm8731: wm8731@1b { compatible = "wm8731"; reg = <0x1b>; + + /* PCK0 at 12MHz */ + clocks = <&pmc PMC_TYPE_SYSTEM 8>; + clock-names = "mclk"; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>; + assigned-clock-rates = <12000000>; + + HPVDD-supply = <&vcc_dac>; + AVDD-supply = <&vcc_dac>; + DCVDD-supply = <®_3v3>; + DBVDD-supply = <®_3v3>; }; }; @@ -254,4 +266,35 @@ atmel,ssc-controller = <&ssc0>; atmel,audio-codec = <&wm8731>; }; + + reg_5v: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_3v3: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + vin-supply = <®_5v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_1v: fixedregulator2 { + compatible = "regulator-fixed"; + regulator-name = "1V"; + vin-supply = <®_5v>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vcc_dac: fixedregulator3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_DAC"; + vin-supply = <®_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; diff --git a/dts/src/arm/at91sam9m10g45ek.dts b/dts/src/arm/at91sam9m10g45ek.dts index b6256a20fb..e5db198a87 100644 --- a/dts/src/arm/at91sam9m10g45ek.dts +++ b/dts/src/arm/at91sam9m10g45ek.dts @@ -167,7 +167,7 @@ spi0: spi@fffa4000{ status = "okay"; cs-gpios = <&pioB 3 0>, <0>, <0>, <0>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <13000000>; reg = <0>; diff --git a/dts/src/arm/at91sam9n12ek.dts b/dts/src/arm/at91sam9n12ek.dts index 2bc4e6e0a9..c905d7bfc7 100644 --- a/dts/src/arm/at91sam9n12ek.dts +++ b/dts/src/arm/at91sam9n12ek.dts @@ -119,7 +119,7 @@ spi0: spi@f0000000 { status = "okay"; cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; - m25p80@0 { + flash@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/dts/src/arm/at91sam9rlek.dts b/dts/src/arm/at91sam9rlek.dts index 62981b39c8..d74b8d9d84 100644 --- a/dts/src/arm/at91sam9rlek.dts +++ b/dts/src/arm/at91sam9rlek.dts @@ -180,7 +180,7 @@ spi0: spi@fffcc000 { status = "okay"; cs-gpios = <&pioA 28 0>, <0>, <0>, <0>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <15000000>; reg = <0>; diff --git a/dts/src/arm/at91sam9x5ek.dtsi b/dts/src/arm/at91sam9x5ek.dtsi index 6d1264de60..5f4eaa618a 100644 --- a/dts/src/arm/at91sam9x5ek.dtsi +++ b/dts/src/arm/at91sam9x5ek.dtsi @@ -125,7 +125,7 @@ cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; status = "disabled"; /* conflicts with mmc1 */ - m25p80@0 { + flash@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/dts/src/arm/dra7-l4.dtsi b/dts/src/arm/dra7-l4.dtsi index 0a11bacffc..5733e3a4ea 100644 --- a/dts/src/arm/dra7-l4.dtsi +++ b/dts/src/arm/dra7-l4.dtsi @@ -4188,11 +4188,11 @@ reg = <0x1d0010 0x4>; reg-names = "sysc"; ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; + <SYSC_IDLE_NO>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; + power-domains = <&prm_vpe>; clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; diff --git a/dts/src/arm/imx6qdl-apalis.dtsi b/dts/src/arm/imx6qdl-apalis.dtsi index ed2739e390..bd763bae59 100644 --- a/dts/src/arm/imx6qdl-apalis.dtsi +++ b/dts/src/arm/imx6qdl-apalis.dtsi @@ -286,6 +286,8 @@ codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_module_3v3_audio>; VDDIO-supply = <®_module_3v3>; @@ -517,8 +519,6 @@ MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 >; }; @@ -811,6 +811,12 @@ >; }; + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 + >; + }; + pinctrl_spdif: spdifgrp { fsl,pins = < MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 diff --git a/dts/src/arm/imx6ull-colibri.dtsi b/dts/src/arm/imx6ull-colibri.dtsi index 7f35a06dff..951a2a6c5a 100644 --- a/dts/src/arm/imx6ull-colibri.dtsi +++ b/dts/src/arm/imx6ull-colibri.dtsi @@ -37,7 +37,7 @@ reg_sd1_vmmc: regulator-sd1-vmmc { compatible = "regulator-gpio"; - gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_snvs_reg_sd>; regulator-always-on; diff --git a/dts/src/arm/logicpd-som-lv-35xx-devkit.dts b/dts/src/arm/logicpd-som-lv-35xx-devkit.dts index 2a0a98fe67..3240c67e0c 100644 --- a/dts/src/arm/logicpd-som-lv-35xx-devkit.dts +++ b/dts/src/arm/logicpd-som-lv-35xx-devkit.dts @@ -11,3 +11,18 @@ model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit"; compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3"; }; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_2_pins>; + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; +}; diff --git a/dts/src/arm/logicpd-som-lv-37xx-devkit.dts b/dts/src/arm/logicpd-som-lv-37xx-devkit.dts index a604d92221..c757f0d778 100644 --- a/dts/src/arm/logicpd-som-lv-37xx-devkit.dts +++ b/dts/src/arm/logicpd-som-lv-37xx-devkit.dts @@ -11,3 +11,18 @@ model = "LogicPD Zoom DM3730 SOM-LV Development Kit"; compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"; }; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_2_pins>; + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; +}; diff --git a/dts/src/arm/logicpd-som-lv.dtsi b/dts/src/arm/logicpd-som-lv.dtsi index b56524cc7f..55b619c99e 100644 --- a/dts/src/arm/logicpd-som-lv.dtsi +++ b/dts/src/arm/logicpd-som-lv.dtsi @@ -265,21 +265,6 @@ }; }; -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; - &uart2 { interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; pinctrl-names = "default"; diff --git a/dts/src/arm/omap3-gta04.dtsi b/dts/src/arm/omap3-gta04.dtsi index 7e3d8147e2..0365f06165 100644 --- a/dts/src/arm/omap3-gta04.dtsi +++ b/dts/src/arm/omap3-gta04.dtsi @@ -31,6 +31,8 @@ aliases { display0 = &lcd; display1 = &tv0; + /delete-property/ mmc2; + /delete-property/ mmc3; }; ldo_3v3: fixedregulator { diff --git a/dts/src/arm/sama5d3xmb.dtsi b/dts/src/arm/sama5d3xmb.dtsi index a499de8a7a..3652c9e241 100644 --- a/dts/src/arm/sama5d3xmb.dtsi +++ b/dts/src/arm/sama5d3xmb.dtsi @@ -26,7 +26,7 @@ spi0: spi@f0004000 { dmas = <0>, <0>; /* Do not use DMA for spi0 */ - m25p80@0 { + flash@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/dts/src/arm/sama5d3xmb_cmp.dtsi b/dts/src/arm/sama5d3xmb_cmp.dtsi index fa9e5e2a74..5d9e97fecf 100644 --- a/dts/src/arm/sama5d3xmb_cmp.dtsi +++ b/dts/src/arm/sama5d3xmb_cmp.dtsi @@ -25,7 +25,7 @@ spi0: spi@f0004000 { dmas = <0>, <0>; /* Do not use DMA for spi0 */ - m25p80@0 { + flash@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/dts/src/arm/sama7g5.dtsi b/dts/src/arm/sama7g5.dtsi index 4decd3a91a..f691c8f08d 100644 --- a/dts/src/arm/sama7g5.dtsi +++ b/dts/src/arm/sama7g5.dtsi @@ -601,9 +601,9 @@ #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, - <&dma0 AT91_XDMAC_DT_PERID(8)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, + <&dma0 AT91_XDMAC_DT_PERID(7)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; @@ -786,9 +786,9 @@ #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>, - <&dma0 AT91_XDMAC_DT_PERID(22)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, + <&dma0 AT91_XDMAC_DT_PERID(21)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; @@ -810,9 +810,9 @@ #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>, - <&dma0 AT91_XDMAC_DT_PERID(24)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; diff --git a/dts/src/arm/usb_a9263.dts b/dts/src/arm/usb_a9263.dts index 8a0cfbfd0c..b6cb9cdf81 100644 --- a/dts/src/arm/usb_a9263.dts +++ b/dts/src/arm/usb_a9263.dts @@ -60,7 +60,7 @@ spi0: spi@fffa4000 { cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>; status = "okay"; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; reg = <0>; spi-max-frequency = <15000000>; diff --git a/dts/src/arm64/amlogic/meson-g12b-a311d.dtsi b/dts/src/arm64/amlogic/meson-g12b-a311d.dtsi index d61f43052a..8e9ad1e51d 100644 --- a/dts/src/arm64/amlogic/meson-g12b-a311d.dtsi +++ b/dts/src/arm64/amlogic/meson-g12b-a311d.dtsi @@ -11,26 +11,6 @@ compatible = "operating-points-v2"; opp-shared; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <761000>; @@ -71,26 +51,6 @@ compatible = "operating-points-v2"; opp-shared; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <731000>; diff --git a/dts/src/arm64/amlogic/meson-g12b-s922x.dtsi b/dts/src/arm64/amlogic/meson-g12b-s922x.dtsi index 1e5d0ee5d5..44c23c9840 100644 --- a/dts/src/arm64/amlogic/meson-g12b-s922x.dtsi +++ b/dts/src/arm64/amlogic/meson-g12b-s922x.dtsi @@ -11,26 +11,6 @@ compatible = "operating-points-v2"; opp-shared; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <731000>; @@ -76,26 +56,6 @@ compatible = "operating-points-v2"; opp-shared; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <751000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <751000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <751000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <751000>; - }; - opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <771000>; diff --git a/dts/src/arm64/amlogic/meson-s4.dtsi b/dts/src/arm64/amlogic/meson-s4.dtsi index bf9ae1e101..480afa2cc6 100644 --- a/dts/src/arm64/amlogic/meson-s4.dtsi +++ b/dts/src/arm64/amlogic/meson-s4.dtsi @@ -13,28 +13,28 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a35","arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; }; cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a35","arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; }; cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a35","arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x2>; enable-method = "psci"; }; cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a35","arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x3>; enable-method = "psci"; }; diff --git a/dts/src/arm64/amlogic/meson-sm1-bananapi-m5.dts b/dts/src/arm64/amlogic/meson-sm1-bananapi-m5.dts index 5751c48620..cadba194b1 100644 --- a/dts/src/arm64/amlogic/meson-sm1-bananapi-m5.dts +++ b/dts/src/arm64/amlogic/meson-sm1-bananapi-m5.dts @@ -437,6 +437,7 @@ "", "eMMC_RST#", /* BOOT_12 */ "eMMC_DS", /* BOOT_13 */ + "", "", /* GPIOC */ "SD_D0_B", /* GPIOC_0 */ "SD_D1_B", /* GPIOC_1 */ diff --git a/dts/src/arm64/amlogic/meson-sm1.dtsi b/dts/src/arm64/amlogic/meson-sm1.dtsi index 3c07a89bfd..80737731af 100644 --- a/dts/src/arm64/amlogic/meson-sm1.dtsi +++ b/dts/src/arm64/amlogic/meson-sm1.dtsi @@ -95,26 +95,6 @@ compatible = "operating-points-v2"; opp-shared; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <730000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <730000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <730000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <666666666>; - opp-microvolt = <750000>; - }; - opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <770000>; diff --git a/dts/src/arm64/freescale/imx8mm-venice-gw71xx.dtsi b/dts/src/arm64/freescale/imx8mm-venice-gw71xx.dtsi index 73addc0b8e..cce55c3c5d 100644 --- a/dts/src/arm64/freescale/imx8mm-venice-gw71xx.dtsi +++ b/dts/src/arm64/freescale/imx8mm-venice-gw71xx.dtsi @@ -146,12 +146,14 @@ &usbotg1 { dr_mode = "otg"; + over-current-active-low; vbus-supply = <®_usb_otg1_vbus>; status = "okay"; }; &usbotg2 { dr_mode = "host"; + disable-over-current; status = "okay"; }; @@ -215,7 +217,7 @@ fsl,pins = < MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 >; }; diff --git a/dts/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi b/dts/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi index 1e7badb2a8..f61e4847fa 100644 --- a/dts/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi +++ b/dts/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi @@ -211,12 +211,14 @@ &usbotg1 { dr_mode = "otg"; + over-current-active-low; vbus-supply = <®_usb_otg1_vbus>; status = "okay"; }; &usbotg2 { dr_mode = "host"; + disable-over-current; vbus-supply = <®_usb_otg2_vbus>; status = "okay"; }; @@ -309,7 +311,7 @@ fsl,pins = < MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 >; }; diff --git a/dts/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi b/dts/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi index 426483ec1f..0236196489 100644 --- a/dts/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi +++ b/dts/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi @@ -238,12 +238,14 @@ &usbotg1 { dr_mode = "otg"; + over-current-active-low; vbus-supply = <®_usb_otg1_vbus>; status = "okay"; }; &usbotg2 { dr_mode = "host"; + disable-over-current; vbus-supply = <®_usb_otg2_vbus>; status = "okay"; }; @@ -358,7 +360,7 @@ fsl,pins = < MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 >; }; diff --git a/dts/src/arm64/freescale/imx8mn-ddr4-evk.dts b/dts/src/arm64/freescale/imx8mn-ddr4-evk.dts index 7dfee715a2..d8ce217c60 100644 --- a/dts/src/arm64/freescale/imx8mn-ddr4-evk.dts +++ b/dts/src/arm64/freescale/imx8mn-ddr4-evk.dts @@ -59,6 +59,10 @@ interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + regulators { buck1_reg: BUCK1 { regulator-name = "buck1"; diff --git a/dts/src/arm64/freescale/imx8mn.dtsi b/dts/src/arm64/freescale/imx8mn.dtsi index 99f0f50266..5c0ca24905 100644 --- a/dts/src/arm64/freescale/imx8mn.dtsi +++ b/dts/src/arm64/freescale/imx8mn.dtsi @@ -293,7 +293,7 @@ ranges; sai2: sai@30020000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI2_IPG>, @@ -307,7 +307,7 @@ }; sai3: sai@30030000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30030000 0x10000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI3_IPG>, @@ -321,7 +321,7 @@ }; sai5: sai@30050000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI5_IPG>, @@ -337,7 +337,7 @@ }; sai6: sai@30060000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI6_IPG>, @@ -394,7 +394,7 @@ }; sai7: sai@300b0000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x300b0000 0x10000>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI7_IPG>, diff --git a/dts/src/arm64/freescale/imx8mq-tqma8mq.dtsi b/dts/src/arm64/freescale/imx8mq-tqma8mq.dtsi index 38ffcd145b..899e8e7dbc 100644 --- a/dts/src/arm64/freescale/imx8mq-tqma8mq.dtsi +++ b/dts/src/arm64/freescale/imx8mq-tqma8mq.dtsi @@ -253,7 +253,7 @@ #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <84000000>; - spi-tx-bus-width = <4>; + spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; }; }; diff --git a/dts/src/arm64/freescale/imx8qm.dtsi b/dts/src/arm64/freescale/imx8qm.dtsi index be8c76a055..4f767012f1 100644 --- a/dts/src/arm64/freescale/imx8qm.dtsi +++ b/dts/src/arm64/freescale/imx8qm.dtsi @@ -196,7 +196,7 @@ }; clk: clock-controller { - compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; + compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; #clock-cells = <2>; }; diff --git a/dts/src/arm64/nvidia/tegra186-p3310.dtsi b/dts/src/arm64/nvidia/tegra186-p3310.dtsi index 1df8433592..aff857df25 100644 --- a/dts/src/arm64/nvidia/tegra186-p3310.dtsi +++ b/dts/src/arm64/nvidia/tegra186-p3310.dtsi @@ -262,25 +262,25 @@ gpio4 { pins = "gpio4"; function = "32k-out1"; - drive-push-pull; + drive-push-pull = <1>; }; gpio5 { pins = "gpio5"; function = "gpio"; - drive-push-pull; + drive-push-pull = <0>; }; gpio6 { pins = "gpio6"; function = "gpio"; - drive-push-pull; + drive-push-pull = <1>; }; gpio7 { pins = "gpio7"; function = "gpio"; - drive-push-pull; + drive-push-pull = <0>; }; }; diff --git a/dts/src/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts b/dts/src/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts index 1ab132c152..4631504c3c 100644 --- a/dts/src/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/dts/src/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -462,25 +462,25 @@ gpio4 { pins = "gpio4"; function = "32k-out1"; - drive-push-pull; + drive-push-pull = <1>; }; gpio5 { pins = "gpio5"; function = "gpio"; - drive-push-pull; + drive-push-pull = <0>; }; gpio6 { pins = "gpio6"; function = "gpio"; - drive-push-pull; + drive-push-pull = <1>; }; gpio7 { pins = "gpio7"; function = "gpio"; - drive-push-pull; + drive-push-pull = <1>; }; }; diff --git a/dts/src/arm64/nvidia/tegra194-p2888.dtsi b/dts/src/arm64/nvidia/tegra194-p2888.dtsi index 634d0f493c..a7d7cfd663 100644 --- a/dts/src/arm64/nvidia/tegra194-p2888.dtsi +++ b/dts/src/arm64/nvidia/tegra194-p2888.dtsi @@ -174,19 +174,19 @@ gpio4 { pins = "gpio4"; function = "32k-out1"; - drive-push-pull; + drive-push-pull = <1>; }; gpio6 { pins = "gpio6"; function = "gpio"; - drive-push-pull; + drive-push-pull = <1>; }; gpio7 { pins = "gpio7"; function = "gpio"; - drive-push-pull; + drive-push-pull = <0>; }; }; diff --git a/dts/src/arm64/nvidia/tegra194-p3668.dtsi b/dts/src/arm64/nvidia/tegra194-p3668.dtsi index 0b219e7276..0bd66f9c62 100644 --- a/dts/src/arm64/nvidia/tegra194-p3668.dtsi +++ b/dts/src/arm64/nvidia/tegra194-p3668.dtsi @@ -148,19 +148,19 @@ gpio4 { pins = "gpio4"; function = "32k-out1"; - drive-push-pull; + drive-push-pull = <1>; }; gpio6 { pins = "gpio6"; function = "gpio"; - drive-push-pull; + drive-push-pull = <1>; }; gpio7 { pins = "gpio7"; function = "gpio"; - drive-push-pull; + drive-push-pull = <0>; }; }; diff --git a/dts/src/arm64/nvidia/tegra210-p2180.dtsi b/dts/src/arm64/nvidia/tegra210-p2180.dtsi index 0fe772b04b..75eb743a72 100644 --- a/dts/src/arm64/nvidia/tegra210-p2180.dtsi +++ b/dts/src/arm64/nvidia/tegra210-p2180.dtsi @@ -59,7 +59,7 @@ gpio1 { pins = "gpio1"; function = "fps-out"; - drive-push-pull; + drive-push-pull = <1>; maxim,active-fps-source = <MAX77620_FPS_SRC_0>; maxim,active-fps-power-up-slot = <7>; maxim,active-fps-power-down-slot = <0>; @@ -68,7 +68,7 @@ gpio2_3 { pins = "gpio2", "gpio3"; function = "fps-out"; - drive-open-drain; + drive-open-drain = <1>; maxim,active-fps-source = <MAX77620_FPS_SRC_0>; }; @@ -80,7 +80,7 @@ gpio5_6_7 { pins = "gpio5", "gpio6", "gpio7"; function = "gpio"; - drive-push-pull; + drive-push-pull = <1>; }; }; diff --git a/dts/src/arm64/nvidia/tegra210-p2894.dtsi b/dts/src/arm64/nvidia/tegra210-p2894.dtsi index 936a309e28..10347b6e6e 100644 --- a/dts/src/arm64/nvidia/tegra210-p2894.dtsi +++ b/dts/src/arm64/nvidia/tegra210-p2894.dtsi @@ -1351,7 +1351,7 @@ gpio1 { pins = "gpio1"; function = "fps-out"; - drive-push-pull; + drive-push-pull = <1>; maxim,active-fps-source = <MAX77620_FPS_SRC_0>; maxim,active-fps-power-up-slot = <7>; maxim,active-fps-power-down-slot = <0>; @@ -1360,14 +1360,14 @@ gpio2 { pins = "gpio2"; function = "fps-out"; - drive-open-drain; + drive-open-drain = <1>; maxim,active-fps-source = <MAX77620_FPS_SRC_0>; }; gpio3 { pins = "gpio3"; function = "fps-out"; - drive-open-drain; + drive-open-drain = <1>; maxim,active-fps-source = <MAX77620_FPS_SRC_0>; }; @@ -1379,7 +1379,7 @@ gpio5_6_7 { pins = "gpio5", "gpio6", "gpio7"; function = "gpio"; - drive-push-pull; + drive-push-pull = <1>; }; }; diff --git a/dts/src/arm64/nvidia/tegra210-p3450-0000.dts b/dts/src/arm64/nvidia/tegra210-p3450-0000.dts index f6446120c2..72c2dc3c14 100644 --- a/dts/src/arm64/nvidia/tegra210-p3450-0000.dts +++ b/dts/src/arm64/nvidia/tegra210-p3450-0000.dts @@ -195,7 +195,7 @@ gpio1 { pins = "gpio1"; function = "fps-out"; - drive-push-pull; + drive-push-pull = <1>; maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; maxim,active-fps-power-up-slot = <0>; maxim,active-fps-power-down-slot = <7>; @@ -204,7 +204,7 @@ gpio2 { pins = "gpio2"; function = "fps-out"; - drive-open-drain; + drive-open-drain = <1>; maxim,active-fps-source = <MAX77620_FPS_SRC_0>; maxim,active-fps-power-up-slot = <0>; maxim,active-fps-power-down-slot = <7>; @@ -213,7 +213,7 @@ gpio3 { pins = "gpio3"; function = "fps-out"; - drive-open-drain; + drive-open-drain = <1>; maxim,active-fps-source = <MAX77620_FPS_SRC_0>; maxim,active-fps-power-up-slot = <4>; maxim,active-fps-power-down-slot = <3>; @@ -227,7 +227,7 @@ gpio5_6_7 { pins = "gpio5", "gpio6", "gpio7"; function = "gpio"; - drive-push-pull; + drive-push-pull = <1>; }; }; diff --git a/dts/src/arm64/nvidia/tegra210-smaug.dts b/dts/src/arm64/nvidia/tegra210-smaug.dts index e42384f097..a263d51882 100644 --- a/dts/src/arm64/nvidia/tegra210-smaug.dts +++ b/dts/src/arm64/nvidia/tegra210-smaug.dts @@ -1386,7 +1386,7 @@ gpio3 { pins = "gpio3"; function = "fps-out"; - drive-open-drain; + drive-open-drain = <1>; maxim,active-fps-source = <MAX77620_FPS_SRC_0>; maxim,active-fps-power-up-slot = <4>; maxim,active-fps-power-down-slot = <2>; @@ -1395,7 +1395,7 @@ gpio5_6 { pins = "gpio5", "gpio6"; function = "gpio"; - drive-push-pull; + drive-push-pull = <1>; }; gpio4 { diff --git a/dts/src/riscv/microchip/microchip-mpfs-fabric.dtsi b/dts/src/riscv/microchip/microchip-mpfs-fabric.dtsi index 854320e17b..ccaac3371c 100644 --- a/dts/src/riscv/microchip/microchip-mpfs-fabric.dtsi +++ b/dts/src/riscv/microchip/microchip-mpfs-fabric.dtsi @@ -7,7 +7,7 @@ reg = <0x0 0x41000000 0x0 0xF0>; microchip,sync-update-mask = /bits/ 32 <0>; #pwm-cells = <2>; - clocks = <&clkcfg CLK_FIC3>; + clocks = <&fabric_clk3>; status = "disabled"; }; @@ -16,10 +16,22 @@ reg = <0x0 0x44000000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clkcfg CLK_FIC3>; + clocks = <&fabric_clk3>; interrupt-parent = <&plic>; interrupts = <122>; clock-frequency = <100000>; status = "disabled"; }; + + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; }; diff --git a/dts/src/riscv/microchip/microchip-mpfs-icicle-kit.dts b/dts/src/riscv/microchip/microchip-mpfs-icicle-kit.dts index cd2fe80fa8..3392153dd0 100644 --- a/dts/src/riscv/microchip/microchip-mpfs-icicle-kit.dts +++ b/dts/src/riscv/microchip/microchip-mpfs-icicle-kit.dts @@ -45,7 +45,7 @@ }; &refclk { - clock-frequency = <600000000>; + clock-frequency = <125000000>; }; &mmuart1 { diff --git a/dts/src/riscv/microchip/microchip-mpfs.dtsi b/dts/src/riscv/microchip/microchip-mpfs.dtsi index c5c9d1360d..746c4d4e76 100644 --- a/dts/src/riscv/microchip/microchip-mpfs.dtsi +++ b/dts/src/riscv/microchip/microchip-mpfs.dtsi @@ -141,7 +141,7 @@ }; }; - refclk: msspllclk { + refclk: mssrefclk { compatible = "fixed-clock"; #clock-cells = <0>; }; @@ -190,7 +190,7 @@ clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>; + reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; clocks = <&refclk>; #clock-cells = <1>; }; @@ -393,8 +393,8 @@ reg = <0x0 0x20124000 0x0 0x1000>; interrupt-parent = <&plic>; interrupts = <80>, <81>; - clocks = <&clkcfg CLK_RTC>; - clock-names = "rtc"; + clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; + clock-names = "rtc", "rtcref"; status = "disabled"; }; @@ -424,7 +424,7 @@ <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; interrupt-map-mask = <0 0 0 7>; - clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>; + clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; clock-names = "fic0", "fic1", "fic3"; ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; msi-parent = <&pcie>; diff --git a/images/Makefile.am33xx b/images/Makefile.am33xx index add676117c..a63def771e 100644 --- a/images/Makefile.am33xx +++ b/images/Makefile.am33xx @@ -26,6 +26,14 @@ FILE_barebox-am33xx-afi-gf-mlo.spi.img = start_am33xx_afi_gf_sram.pblb.mlospi am33xx-mlo-$(CONFIG_MACH_AFI_GF) += barebox-am33xx-afi-gf-mlo.img am33xx-mlospi-$(CONFIG_MACH_AFI_GF) += barebox-am33xx-afi-gf-mlo.spi.img +pblb-$(CONFIG_MACH_MYIRTECH_X335X) += start_am33xx_myirtech_sdram +FILE_barebox-am33xx-myirtech.img = start_am33xx_myirtech_sdram.pblb +am33xx-barebox-$(CONFIG_MACH_MYIRTECH_X335X) += barebox-am33xx-myirtech.img + +pblb-$(CONFIG_MACH_MYIRTECH_X335X) += start_am33xx_myirtech_sram +FILE_barebox-am33xx-myirtech-mlo.img = start_am33xx_myirtech_sram.pblb.mlo +am33xx-mlo-$(CONFIG_MACH_MYIRTECH_X335X) += barebox-am33xx-myirtech-mlo.img + pblb-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycore_nand_sdram FILE_barebox-am33xx-phytec-phycore.img = start_am33xx_phytec_phycore_nand_sdram.pblb am33xx-barebox-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore.img diff --git a/include/ata_drive.h b/include/ata_drive.h index 6b8915c9cb..e11172ba39 100644 --- a/include/ata_drive.h +++ b/include/ata_drive.h @@ -67,7 +67,12 @@ enum { ATA_ID_MWDMA_MODES = 63, ATA_ID_PIO_MODES = 64, ATA_ID_QUEUE_DEPTH = 75, + ATA_ID_SATA_CAPAB_1 = 76, + ATA_ID_SATA_CAPAB_2 = 77, + ATA_ID_SATA_FEAT_SUPP = 78, + ATA_ID_SATA_FEAT_ENABLE = 79, ATA_ID_MAJOR_VER = 80, + ATA_ID_MINOR_VER = 81, ATA_ID_COMMAND_SET_1 = 82, ATA_ID_COMMAND_SET_2 = 83, ATA_ID_CFSSE = 84, diff --git a/include/common.h b/include/common.h index 4167d4676e..bd12035688 100644 --- a/include/common.h +++ b/include/common.h @@ -126,4 +126,10 @@ const char *barebox_get_hostname(void); void barebox_set_hostname(const char *); void barebox_set_hostname_no_overwrite(const char *); +const char *barebox_get_serial_number(void); +void barebox_set_serial_number(const char *); + +void barebox_set_of_machine_compatible(const char *); +const char *barebox_get_of_machine_compatible(void); + #endif /* __COMMON_H_ */ diff --git a/include/of.h b/include/of.h index cf9950e9b3..3a8e32f69c 100644 --- a/include/of.h +++ b/include/of.h @@ -316,6 +316,7 @@ struct device_node *of_find_node_by_path_or_alias(struct device_node *root, const char *str); int of_autoenable_device_by_path(char *path); int of_autoenable_i2c_by_component(char *path); +int of_prepend_machine_compatible(struct device_node *root, const char *compat); #else static inline bool of_node_name_eq(const struct device_node *np, const char *name) { @@ -834,6 +835,11 @@ static inline int of_autoenable_i2c_by_component(char *path) return -ENODEV; } +static int of_prepend_machine_compatible(struct device_node *root, + const char *compat) +{ + return -ENODEV; +} #endif diff --git a/arch/arm/mach-omap/include/mach/omap-fb.h b/include/video/omap-fb.h index f727164434..519460f0d5 100644 --- a/arch/arm/mach-omap/include/mach/omap-fb.h +++ b/include/video/omap-fb.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H -#define H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H +#ifndef OMAP_FB_H +#define OMAP_FB_H #include <fb.h> @@ -42,8 +42,4 @@ struct omapfb_platform_data { void (*enable)(int p); }; -struct device_d; -struct device_d *omap_add_display(struct omapfb_platform_data *o_pdata); - - -#endif /* H_BAREBOX_ARCH_ARM_MACH_OMAP_MACH_FB4_H */ +#endif /* OMAP_FB_H */ @@ -58,6 +58,7 @@ struct header { static struct net_connection *dns_con; static uint64_t dns_timer_start; +static uint16_t dns_req_id; static int dns_state; static IPaddr_t dns_ip; @@ -70,9 +71,12 @@ static int dns_send(const char *name) unsigned char *p, *s, *fullname, *dotptr; const unsigned char *domain; + /* generate "difficult" to predict transaction id */ + dns_req_id = dns_timer_start + (dns_timer_start >> 16); + /* Prepare DNS packet header */ header = (struct header *)packet; - header->tid = 1; + header->tid = htons(dns_req_id); header->flags = htons(0x100); /* standard query */ header->nqueries = htons(1); /* Just one query */ header->nanswers = 0; @@ -127,6 +131,12 @@ static void dns_recv(struct header *header, unsigned len) pr_debug("%s\n", __func__); + /* Only accept responses with the expected request id */ + if (ntohs(header->tid) != dns_req_id) { + pr_debug("DNS response with incorrect id\n"); + return; + } + /* We sent 1 query. We want to see more that 1 answer. */ if (ntohs(header->nqueries) != 1) return; |