diff options
| -rw-r--r-- | arch/arm/boards/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/boards/enclustra-aa1/Makefile | 4 | ||||
| -rw-r--r-- | arch/arm/boards/enclustra-aa1/board.c | 48 | ||||
| -rw-r--r-- | arch/arm/boards/enclustra-aa1/lowlevel.c | 120 | ||||
| -rw-r--r-- | arch/arm/boards/enclustra-aa1/pinmux-config-arria10.c | 104 | ||||
| -rw-r--r-- | arch/arm/boards/enclustra-aa1/pll-config-arria10.c | 56 | ||||
| -rw-r--r-- | arch/arm/boards/reflex-achilles/board.c | 3 | ||||
| -rw-r--r-- | arch/arm/boards/reflex-achilles/lowlevel.c | 32 | ||||
| -rw-r--r-- | arch/arm/configs/socfpga-arria10_defconfig | 1 | ||||
| -rw-r--r-- | arch/arm/dts/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/dts/socfpga_arria10_mercury_aa1.dts | 85 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/Kconfig | 5 | ||||
| -rw-r--r-- | images/Makefile.socfpga | 12 | ||||
| -rwxr-xr-x | scripts/socfpga_xml_to_config.sh | 8 |
14 files changed, 460 insertions, 20 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 96f81a32d6..5a11c52831 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -135,6 +135,7 @@ obj-$(CONFIG_MACH_SCB9328) += scb9328/ obj-$(CONFIG_MACH_SEEED_ODYSSEY) += seeed-odyssey/ obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += altera-socdk/ obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/ +obj-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += enclustra-aa1/ obj-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += reflex-achilles/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += terasic-de10-nano/ diff --git a/arch/arm/boards/enclustra-aa1/Makefile b/arch/arm/boards/enclustra-aa1/Makefile new file mode 100644 index 0000000000..5678718188 --- /dev/null +++ b/arch/arm/boards/enclustra-aa1/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/enclustra-aa1/board.c b/arch/arm/boards/enclustra-aa1/board.c new file mode 100644 index 0000000000..6261eb4b83 --- /dev/null +++ b/arch/arm/boards/enclustra-aa1/board.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <init.h> +#include <io.h> +#include <bbu.h> +#include <mach/arria10-system-manager.h> + +static int aa1_init(void) +{ + int pbl_index = 0; + uint32_t flag_barebox1 = 0; + uint32_t flag_barebox2 = 0; + + if (!of_machine_is_compatible("enclustra,mercury-aa1")) + return 0; + + pbl_index = readl(ARRIA10_SYSMGR_ROM_INITSWLASTLD); + + pr_debug("Current barebox instance %d\n", pbl_index); + + switch (pbl_index) { + case 0: + flag_barebox1 |= BBU_HANDLER_FLAG_DEFAULT; + break; + case 1: + flag_barebox2 |= BBU_HANDLER_FLAG_DEFAULT; + break; + }; + + bbu_register_std_file_update("emmc-barebox1-xload", flag_barebox1, + "/dev/mmc0.barebox1-xload", + filetype_socfpga_xload); + + bbu_register_std_file_update("emmc-barebox1", 0, + "/dev/mmc0.barebox1", + filetype_arm_barebox); + + bbu_register_std_file_update("emmc-barebox2-xload", flag_barebox2, + "/dev/mmc0.barebox2-xload", + filetype_socfpga_xload); + + bbu_register_std_file_update("emmc-barebox2", 0, + "/dev/mmc0.barebox2", + filetype_arm_barebox); + return 0; +} +postcore_initcall(aa1_init); diff --git a/arch/arm/boards/enclustra-aa1/lowlevel.c b/arch/arm/boards/enclustra-aa1/lowlevel.c new file mode 100644 index 0000000000..9f2d66a6bc --- /dev/null +++ b/arch/arm/boards/enclustra-aa1/lowlevel.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <linux/sizes.h> +#include <io.h> +#include <memory.h> +#include <asm/barebox-arm.h> +#include <asm/cache.h> +#include <asm/sections.h> +#include <asm/unaligned.h> +#include <debug_ll.h> +#include <pbl.h> +#include <mach/arria10-sdram.h> +#include <mach/arria10-regs.h> +#include <mach/arria10-reset-manager.h> +#include <mach/arria10-clock-manager.h> +#include <mach/arria10-pinmux.h> +#include <mach/arria10-fpga.h> +#include "pll-config-arria10.c" +#include "pinmux-config-arria10.c" +#include <mach/generic.h> + +#define BAREBOX_PART 0 +// the bitstream is located in the second partition in the partition table +#define BITSTREAM_PART 1 +#define BAREBOX1_OFFSET SZ_1M +#define BAREBOX2_OFFSET (BAREBOX1_OFFSET + SZ_1M) +// Offset from the start of the second partition on the eMMC. +#define BITSTREAM1_OFFSET 0x0 +#define BITSTREAM2_OFFSET (BITSTREAM1_OFFSET + SZ_32M) + +extern char __dtb_z_socfpga_arria10_mercury_aa1_start[]; + +#define ARRIA10_STACKTOP (ARRIA10_OCRAM_ADDR + SZ_256K) + +ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_xload, ARRIA10_STACKTOP, r0, r1, r2) +{ + int pbl_index = 0; + int barebox = 0; + int bitstream = 0; + + arm_cpu_lowlevel_init(); + + relocate_to_current_adr(); + + setup_c(); + + arria10_init(&mainpll_cfg, &perpll_cfg, pinmux); + + arria10_prepare_mmc(BAREBOX_PART, BITSTREAM_PART); + + pbl_index = readl(ARRIA10_SYSMGR_ROM_INITSWLASTLD); + + /* Allow booting from both PBL0 and PBL1 to allow atomic updates. + * Bitstreams redundant too and expected to reside in the second + * partition. + * There is a fixed relation between the PBL/barebox instance and its + * bitstream location (offset) that requires to update them together */ + switch (pbl_index) { + case 0: + barebox = BAREBOX1_OFFSET; + bitstream = BITSTREAM1_OFFSET; + break; + case 1: + barebox = BAREBOX2_OFFSET; + bitstream = BITSTREAM2_OFFSET; + break; + case 2: + case 3: + /* Left blank for future extension */ + break; + default: + /* If we get an undefined pbl index, use the first and hope for the best. + * We could bail out, but user wouldn't see anything on the console + * and wouldn't know what happend anyway. */ + barebox = BAREBOX1_OFFSET; + bitstream = BITSTREAM1_OFFSET; + break; + } + + arria10_load_fpga(bitstream, SZ_32M); + + arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux); + + arria10_ddr_calibration_sequence(); + + arria10_start_image(barebox); +} + +ENTRY_FUNCTION(start_socfpga_aa1, r0, r1, r2) +{ + void *fdt; + + fdt = __dtb_z_socfpga_arria10_mercury_aa1_start + get_runtime_offset(); + + barebox_arm_entry(0x0, SZ_2G, fdt); +} + +ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_bringup, ARRIA10_STACKTOP, r0, r1, r2) +{ + void *fdt; + + arm_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + arria10_init(&mainpll_cfg, &perpll_cfg, pinmux); + + /* wait for fpga_usermode */ + a10_wait_for_usermode(0x1000000); + + arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux); + + arria10_ddr_calibration_sequence(); + + fdt = __dtb_z_socfpga_arria10_mercury_aa1_start + get_runtime_offset(); + + barebox_arm_entry(0x0, SZ_2G, fdt); +} diff --git a/arch/arm/boards/enclustra-aa1/pinmux-config-arria10.c b/arch/arm/boards/enclustra-aa1/pinmux-config-arria10.c new file mode 100644 index 0000000000..3e250dbf6f --- /dev/null +++ b/arch/arm/boards/enclustra-aa1/pinmux-config-arria10.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <mach/arria10-pinmux.h> + +static uint32_t pinmux[] = { +[arria10_pinmux_shared_io_q3_7] = 0, +[arria10_pinmux_shared_io_q3_6] = 15, +[arria10_pinmux_shared_io_q3_5] = 15, +[arria10_pinmux_shared_io_q3_4] = 15, +[arria10_pinmux_shared_io_q3_3] = 15, +[arria10_pinmux_shared_io_q3_2] = 15, +[arria10_pinmux_shared_io_q3_1] = 15, +[arria10_pinmux_shared_io_q2_12] = 4, +[arria10_pinmux_shared_io_q2_11] = 4, +[arria10_pinmux_shared_io_q2_10] = 4, +[arria10_pinmux_shared_io_q2_8] = 4, +[arria10_pinmux_shared_io_q2_9] = 4, +[arria10_pinmux_shared_io_q2_7] = 4, +[arria10_pinmux_shared_io_q2_6] = 4, +[arria10_pinmux_shared_io_q2_5] = 4, +[arria10_pinmux_shared_io_q2_4] = 4, +[arria10_pinmux_shared_io_q2_3] = 4, +[arria10_pinmux_shared_io_q2_2] = 4, +[arria10_pinmux_shared_io_q2_1] = 4, +[arria10_pinmux_shared_io_q1_12] = 8, +[arria10_pinmux_shared_io_q1_10] = 8, +[arria10_pinmux_shared_io_q1_11] = 8, +[arria10_pinmux_shared_io_q1_9] = 8, +[arria10_pinmux_shared_io_q1_8] = 8, +[arria10_pinmux_shared_io_q1_7] = 8, +[arria10_pinmux_shared_io_q1_6] = 8, +[arria10_pinmux_shared_io_q1_5] = 8, +[arria10_pinmux_shared_io_q1_4] = 8, +[arria10_pinmux_shared_io_q1_3] = 8, +[arria10_pinmux_shared_io_q1_2] = 8, +[arria10_pinmux_shared_io_q1_1] = 8, +[arria10_pinmux_shared_io_q4_12] = 15, +[arria10_pinmux_shared_io_q4_11] = 15, +[arria10_pinmux_shared_io_q4_10] = 3, +[arria10_pinmux_shared_io_q4_9] = 3, +[arria10_pinmux_shared_io_q4_8] = 3, +[arria10_pinmux_shared_io_q4_7] = 3, +[arria10_pinmux_shared_io_q4_6] = 10, +[arria10_pinmux_shared_io_q4_4] = 10, +[arria10_pinmux_shared_io_q4_5] = 10, +[arria10_pinmux_shared_io_q4_3] = 10, +[arria10_pinmux_shared_io_q4_2] = 10, +[arria10_pinmux_shared_io_q4_1] = 10, +[arria10_pinmux_shared_io_q3_12] = 1, +[arria10_pinmux_shared_io_q3_11] = 1, +[arria10_pinmux_shared_io_q3_10] = 15, +[arria10_pinmux_shared_io_q3_9] = 15, +[arria10_pinmux_shared_io_q3_8] = 0, +[arria10_pinmux_dedicated_io_7] = 8, +[arria10_pinmux_dedicated_io_8] = 8, +[arria10_pinmux_dedicated_io_9] = 8, +[arria10_pinmux_dedicated_io_10] = 15, +[arria10_pinmux_dedicated_io_11] = 15, +[arria10_pinmux_dedicated_io_12] = 8, +[arria10_pinmux_dedicated_io_13] = 8, +[arria10_pinmux_dedicated_io_14] = 8, +[arria10_pinmux_dedicated_io_15] = 8, +[arria10_pinmux_dedicated_io_16] = 13, +[arria10_pinmux_dedicated_io_17] = 13, +[arria10_pinmux_dedicated_io_4] = 8, +[arria10_pinmux_dedicated_io_5] = 8, +[arria10_pinmux_dedicated_io_6] = 8, +[arria10_pincfg_dedicated_io_bank] = 0x101, +[arria10_pincfg_dedicated_io_1] = 0xb080a, +[arria10_pincfg_dedicated_io_2] = 0xb080a, +[arria10_pincfg_dedicated_io_3] = 0xb080a, +[arria10_pincfg_dedicated_io_4] = 0xa282a, +[arria10_pincfg_dedicated_io_5] = 0xa282a, +[arria10_pincfg_dedicated_io_6] = 0x8282a, +[arria10_pincfg_dedicated_io_7] = 0xa282a, +[arria10_pincfg_dedicated_io_8] = 0xa282a, +[arria10_pincfg_dedicated_io_9] = 0xa282a, +[arria10_pincfg_dedicated_io_10] = 0xa280a, +[arria10_pincfg_dedicated_io_11] = 0xa280a, +[arria10_pincfg_dedicated_io_12] = 0xa280a, +[arria10_pincfg_dedicated_io_13] = 0xa280a, +[arria10_pincfg_dedicated_io_14] = 0xa280a, +[arria10_pincfg_dedicated_io_15] = 0xa280a, +[arria10_pincfg_dedicated_io_16] = 0x8282a, +[arria10_pincfg_dedicated_io_17] = 0xa280a, +[arria10_pinmux_rgmii0_usefpga] = 0, +[arria10_pinmux_rgmii1_usefpga] = 0, +[arria10_pinmux_rgmii2_usefpga] = 0, +[arria10_pinmux_nand_usefpga] = 0, +[arria10_pinmux_qspi_usefpga] = 0, +[arria10_pinmux_sdmmc_usefpga] = 0, +[arria10_pinmux_spim0_usefpga] = 0, +[arria10_pinmux_spim1_usefpga] = 0, +[arria10_pinmux_spis0_usefpga] = 0, +[arria10_pinmux_spis1_usefpga] = 0, +[arria10_pinmux_uart0_usefpga] = 0, +[arria10_pinmux_uart1_usefpga] = 0, +[arria10_pinmux_i2c0_usefpga] = 0, +[arria10_pinmux_i2c1_usefpga] = 0, +[arria10_pinmux_i2cemac0_usefpga] = 0, +[arria10_pinmux_i2cemac1_usefpga] = 0, +[arria10_pinmux_i2cemac2_usefpga] = 0, +}; + diff --git a/arch/arm/boards/enclustra-aa1/pll-config-arria10.c b/arch/arm/boards/enclustra-aa1/pll-config-arria10.c new file mode 100644 index 0000000000..41aad354bc --- /dev/null +++ b/arch/arm/boards/enclustra-aa1/pll-config-arria10.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <mach/arria10-clock-manager.h> + +static struct arria10_mainpll_cfg mainpll_cfg = { + .cntr15clk_cnt = 900, + .cntr2clk_cnt = 900, + .cntr3clk_cnt = 900, + .cntr4clk_cnt = 900, + .cntr5clk_cnt = 900, + .cntr6clk_cnt = 7, + .cntr7clk_cnt = 15, + .cntr7clk_src = 0, + .cntr8clk_cnt = 7, + .cntr9clk_cnt = 900, + .cntr9clk_src = 0, + .mpuclk_cnt = 0, + .mpuclk_src = 0, + .nocclk_cnt = 0, + .nocclk_src = 0, + .nocdiv_csatclk = 0, + .nocdiv_cspdbgclk = 1, + .nocdiv_cstraceclk = 0, + .nocdiv_l4mainclk = 0, + .nocdiv_l4mpclk = 1, + .nocdiv_l4spclk = 2, + .vco0_psrc = 0, + .vco1_denom = 32, + .vco1_numer = 1584, + .mpuclk = 0x3840001, + .nocclk = 0x3840007, +}; + +static struct arria10_perpll_cfg perpll_cfg = { + .cntr2clk_cnt = 5, + .cntr2clk_src = 1, + .cntr3clk_cnt = 900, + .cntr3clk_src = 1, + .cntr4clk_cnt = 14, + .cntr4clk_src = 1, + .cntr5clk_cnt = 374, + .cntr5clk_src = 1, + .cntr6clk_cnt = 900, + .cntr6clk_src = 0, + .cntr7clk_cnt = 900, + .cntr8clk_cnt = 900, + .cntr8clk_src = 0, + .cntr9clk_cnt = 900, + .emacctl_emac0sel = 0, + .emacctl_emac1sel = 0, + .emacctl_emac2sel = 0, + .gpiodiv_gpiodbclk = 32000, + .vco0_psrc = 0, + .vco1_denom = 32, + .vco1_numer = 1485, +}; diff --git a/arch/arm/boards/reflex-achilles/board.c b/arch/arm/boards/reflex-achilles/board.c index 43e3a69be7..0fbb967ff9 100644 --- a/arch/arm/boards/reflex-achilles/board.c +++ b/arch/arm/boards/reflex-achilles/board.c @@ -4,6 +4,7 @@ #include <init.h> #include <io.h> #include <bbu.h> +#include <mach/arria10-system-manager.h> static int achilles_init(void) { @@ -14,7 +15,7 @@ static int achilles_init(void) if (!of_machine_is_compatible("reflex,achilles")) return 0; - pbl_index = readl(0xFFD06210); + pbl_index = readl(ARRIA10_SYSMGR_ROM_INITSWLASTLD); pr_debug("Current barebox instance %d\n", pbl_index); diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c index e8d1a9cee4..ec8c126c2a 100644 --- a/arch/arm/boards/reflex-achilles/lowlevel.c +++ b/arch/arm/boards/reflex-achilles/lowlevel.c @@ -23,21 +23,24 @@ #define BAREBOX_PART 0 #define BITSTREAM_PART 1 #define BAREBOX1_OFFSET SZ_1M -#define BAREBOX2_OFFSET BAREBOX1_OFFSET + SZ_512K -#define BAREBOX3_OFFSET BAREBOX2_OFFSET + SZ_512K -#define BAREBOX4_OFFSET BAREBOX3_OFFSET + SZ_512K +#define BAREBOX2_OFFSET (BAREBOX1_OFFSET + SZ_512K) +#define BAREBOX3_OFFSET (BAREBOX2_OFFSET + SZ_512K) +#define BAREBOX4_OFFSET (BAREBOX3_OFFSET + SZ_512K) +// Offset from the start of the second partition on the eMMC. #define BITSTREAM1_OFFSET 0x0 -#define BITSTREAM2_OFFSET BITSTREAM1_OFFSET + SZ_32M +#define BITSTREAM2_OFFSET (BITSTREAM1_OFFSET + SZ_32M) -extern char __dtb_socfpga_arria10_achilles_start[]; +extern char __dtb_z_socfpga_arria10_achilles_start[]; -static noinline void achilles_start(void) +#define ARRIA10_STACKTOP (ARRIA10_OCRAM_ADDR + SZ_256K) + +ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_xload, ARRIA10_STACKTOP, r0, r1, r2) { int pbl_index = 0; int barebox = 0; int bitstream = 0; - arm_early_mmu_cache_invalidate(); + arm_cpu_lowlevel_init(); relocate_to_current_adr(); setup_c(); @@ -76,23 +79,16 @@ static noinline void achilles_start(void) arria10_start_image(barebox); } -ENTRY_FUNCTION(start_socfpga_achilles_xload, r0, r1, r2) -{ - arm_cpu_lowlevel_init(); - arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K); - achilles_start(); -} - ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2) { void *fdt; - fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset(); + fdt = __dtb_z_socfpga_arria10_achilles_start + get_runtime_offset(); barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt); } -ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2) +ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_bringup, ARRIA10_STACKTOP, r0, r1, r2) { void *fdt; @@ -100,8 +96,6 @@ ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2) arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K); - arm_early_mmu_cache_invalidate(); - relocate_to_current_adr(); setup_c(); @@ -114,7 +108,7 @@ ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2) arria10_ddr_calibration_sequence(); - fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset(); + fdt = __dtb_z_socfpga_arria10_achilles_start + get_runtime_offset(); barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt); } diff --git a/arch/arm/configs/socfpga-arria10_defconfig b/arch/arm/configs/socfpga-arria10_defconfig index a37bae6217..5ac2198d41 100644 --- a/arch/arm/configs/socfpga-arria10_defconfig +++ b/arch/arm/configs/socfpga-arria10_defconfig @@ -1,4 +1,5 @@ CONFIG_ARCH_SOCFPGA=y +CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1=y CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES=y CONFIG_AEABI=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4e935a7632..97374edc4c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -121,6 +121,7 @@ lwl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o imx6qp-sabresd.dtb.o lwl-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o lwl-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o lwl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o +lwl-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += socfpga_arria10_mercury_aa1.dtb.o lwl-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += socfpga_arria10_achilles.dtb.o lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += socfpga_cyclone5_de10_nano.dtb.o diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/dts/socfpga_arria10_mercury_aa1.dts new file mode 100644 index 0000000000..3f551755cb --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_mercury_aa1.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <arm/socfpga_arria10_mercury_aa1.dts> + +/ { + aliases { + mmc0 = &mmc; + }; + + chosen { + stdout-path = &uart1; + + environment { + compatible = "barebox,environment"; + device-path = &environment_mmc; + }; + }; +}; + +// provide reset-names until fixed in the upstream dts. Binding prescribes this property. +&{/soc/dwmmc0@ff808000} { + reset-names = "reset"; +}; + +// This clock is unused, but fixed-clocks need to have a clock-frequency set +&{/soc/clkmgr@ffd04000/clocks/cb_intosc_hs_div2_clk} { + clock-frequency = <0>; +}; + +&{/soc/clkmgr@ffd04000/clocks/cb_intosc_ls_clk} { + clock-frequency = <60000000>; +}; + +&{/soc/clkmgr@ffd04000/clocks/f2s_free_clk} { + clock-frequency = <200000000>; +}; + +&mmc { + bus-width = <8>; + non-removable; + disable-wp; + no-sd; + + partitions { + compatible = "fixed-partitions"; + #size-cells = <1>; + #address-cells = <1>; + + // This must be marked as an "A2" partition in the partition table + barebox1_xload: partition@100000 { + label = "barebox1-xload"; + reg = <0x100000 0x40000>; + }; + + barebox2_xload: partition@140000 { + label = "barebox2-xload"; + reg = <0x140000 0x40000>; + }; + + barebox1: partition@200000 { + label = "barebox1"; + reg = <0x200000 0x100000>; + }; + + barebox2: partition@300000 { + label = "barebox2"; + reg = <0x300000 0x100000>; + }; + + environment_mmc: partition@400000 { + label = "environment"; + reg = <0x400000 0x8000>; + }; + + // This is actually the second partition on the mmc. It has no filesystem. + bitstream1: partition@700000 { + label = "bitstream1"; + reg = <0x700000 0x2000000>; + }; + + bitstream2: partition@2700000 { + label = "bitstream2"; + reg = <0x2700000 0x2000000>; + }; + }; +}; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 80344315e3..b23a41d3f9 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -23,6 +23,7 @@ config ARCH_SOCFPGA_CYCLONE5 config ARCH_SOCFPGA_ARRIA10 bool select CPU_V7 + select ARM_USE_COMPRESSED_DTB select RESET_CONTROLLER select HAVE_PBL_MULTI_IMAGES select OFDEVICE @@ -36,6 +37,10 @@ config MACH_SOCFPGA_EBV_SOCRATES select ARCH_SOCFPGA_CYCLONE5 bool "EBV Socrates" +config MACH_SOCFPGA_ENCLUSTRA_AA1 + select ARCH_SOCFPGA_ARRIA10 + bool "Enclustra AA1" + config MACH_SOCFPGA_REFLEX_ACHILLES select ARCH_SOCFPGA_ARRIA10 bool "Reflex Achilles" diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga index 90e3c066dc..7f95bed032 100644 --- a/images/Makefile.socfpga +++ b/images/Makefile.socfpga @@ -39,6 +39,18 @@ pblb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += start_socfpga_de10_nano FILE_barebox-socfpga-de10_nano.img = start_socfpga_de10_nano.pblb socfpga-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += barebox-socfpga-de10_nano.img +pblb-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += start_socfpga_aa1_xload +FILE_barebox-socfpga-aa1-xload.img = start_socfpga_aa1_xload.pblb.socfpgaimg +socfpga-barebox-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += barebox-socfpga-aa1-xload.img + +pblb-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += start_socfpga_aa1 +FILE_barebox-socfpga-aa1.img = start_socfpga_aa1.pblb +socfpga-barebox-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += barebox-socfpga-aa1.img + +pblb-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += start_socfpga_aa1_bringup +FILE_barebox-socfpga-aa1-bringup.img = start_socfpga_aa1_bringup.pblb +socfpga-barebox-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += barebox-socfpga-aa1-bringup.img + pblb-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += start_socfpga_achilles_xload FILE_barebox-socfpga-achilles-xload.img = start_socfpga_achilles_xload.pblb.socfpgaimg socfpga-barebox-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += barebox-socfpga-achilles-xload.img diff --git a/scripts/socfpga_xml_to_config.sh b/scripts/socfpga_xml_to_config.sh index 3bb0dd283b..1e6056cfb4 100755 --- a/scripts/socfpga_xml_to_config.sh +++ b/scripts/socfpga_xml_to_config.sh @@ -74,6 +74,14 @@ pinmux_config() { # FIXME: Either find solution how to parse these values too or replace # script with something that goes more in the direction of a programming # language + # 21:19 RTRIM + # 18:17 INPUT_BUF_EN + # 16 WK_PU_EN + # 13 PU_SLW_RT + # 12:8 PU_DRV_STRG + # 5 PD_SLW_RT + # 4:0 PD_DRV_STRG + DEDICATED_FIXME="[arria10_pincfg_dedicated_io_bank] = FIXME, [arria10_pincfg_dedicated_io_1] = FIXME, [arria10_pincfg_dedicated_io_2] = FIXME, |