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-rw-r--r--Makefile2
-rw-r--r--arch/arm/boards/phytec-phycore-omap4460/lowlevel.c26
-rw-r--r--arch/arm/dts/imx6qdl-tqma6x.dtsi12
-rw-r--r--arch/arm/mach-omap/omap_generic.c4
-rw-r--r--arch/arm/mach-socfpga/arria10-generic.c8
-rw-r--r--drivers/clk/clkdev.c2
-rw-r--r--drivers/clk/imx/clk-pllv3.c26
-rw-r--r--drivers/clk/imx/clk-vf610.c28
-rw-r--r--drivers/clk/imx/clk.h4
-rw-r--r--drivers/pci/pci-mvebu.c2
-rw-r--r--drivers/pinctrl/pinctrl-at91.c3
-rw-r--r--scripts/kwbimage.c6
12 files changed, 52 insertions, 71 deletions
diff --git a/Makefile b/Makefile
index 42948fafa3..35158319a6 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
VERSION = 2017
-PATCHLEVEL = 06
+PATCHLEVEL = 07
SUBLEVEL = 0
EXTRAVERSION =
NAME = None
diff --git a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
index 71ab793354..02297adb95 100644
--- a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
@@ -96,19 +96,19 @@ static void noinline pcm049_init_lowlevel(void)
set_muxconf_regs();
-#ifdef CONFIG_1024MB_DDR2RAM
- omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
- writel(EMIF_SDRAM_CONFIG, OMAP44XX_EMIF1_BASE +
- EMIF_LPDDR2_MODE_REG_CONFIG);
- density = (readl(OMAP44XX_EMIF1_BASE + EMIF_LPDDR2_MODE_REG_DATA) &
- LPDDR2_DENSITY_MASK) >> LPDDR2_DENSITY_SHIFT;
- if (density == LPDDR2_2G)
- omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core);
- else if (density == LPDDR2_4G)
- omap4_ddr_init(&ddr_regs_mt42L128M64D2LL_25_400_mhz, &core);
-#else
- omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
-#endif
+ if (IS_ENABLED(CONFIG_1024MB_DDR2RAM)) {
+ omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
+ writel(EMIF_SDRAM_CONFIG, OMAP44XX_EMIF1_BASE +
+ EMIF_LPDDR2_MODE_REG_CONFIG);
+ density = (readl(OMAP44XX_EMIF1_BASE + EMIF_LPDDR2_MODE_REG_DATA) &
+ LPDDR2_DENSITY_MASK) >> LPDDR2_DENSITY_SHIFT;
+ if (density == LPDDR2_2G)
+ omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core);
+ else if (density == LPDDR2_4G)
+ omap4_ddr_init(&ddr_regs_mt42L128M64D2LL_25_400_mhz, &core);
+ } else {
+ omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
+ }
/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
if (rev < OMAP4460_ES1_0)
diff --git a/arch/arm/dts/imx6qdl-tqma6x.dtsi b/arch/arm/dts/imx6qdl-tqma6x.dtsi
index f0b1a0db75..82f9ec368f 100644
--- a/arch/arm/dts/imx6qdl-tqma6x.dtsi
+++ b/arch/arm/dts/imx6qdl-tqma6x.dtsi
@@ -76,12 +76,12 @@
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
diff --git a/arch/arm/mach-omap/omap_generic.c b/arch/arm/mach-omap/omap_generic.c
index 694c951037..a1c0aeb595 100644
--- a/arch/arm/mach-omap/omap_generic.c
+++ b/arch/arm/mach-omap/omap_generic.c
@@ -141,8 +141,8 @@ static int omap_env_init(void)
rootpath = cdev_mount_default(cdev, NULL);
if (IS_ERR(rootpath)) {
- pr_err("Failed to load environment: mount %s failed (%d)\n",
- cdev->name, IS_ERR(rootpath));
+ pr_err("Failed to load environment: mount %s failed (%ld)\n",
+ cdev->name, PTR_ERR(rootpath));
goto out;
}
ret = symlink(rootpath, "/boot");
diff --git a/arch/arm/mach-socfpga/arria10-generic.c b/arch/arm/mach-socfpga/arria10-generic.c
index b8129eaf23..6a10c19d14 100644
--- a/arch/arm/mach-socfpga/arria10-generic.c
+++ b/arch/arm/mach-socfpga/arria10-generic.c
@@ -37,14 +37,6 @@ static void arria10_init_emac(void)
val |= ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
writel(val, ARRIA10_SYSMGR_EMAC2);
- val = readl(ARRIA10_SYSMGR_FPGAINTF_EN_3);
- val &= ~(ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0 |
- ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0_SW |
- ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1 |
- ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1_SW |
- ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2 |
- ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2_SW);
-
rst = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST);
rst &= ~(ARRIA10_RSTMGR_PER0MODRST_EMAC0 |
ARRIA10_RSTMGR_PER0MODRST_EMAC1 |
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 7f9f8f2adc..6b16663551 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -181,7 +181,7 @@ struct clk *clk_get(struct device_d *dev, const char *con_id)
if (dev) {
clk = of_clk_get_by_name(dev->device_node, con_id);
- if (!IS_ERR(clk))
+ if (!IS_ERR(clk) || PTR_ERR(clk) != -ENODEV)
return clk;
}
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 6d4399b9b3..0e55a63e92 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -41,8 +41,6 @@ struct clk_pllv3 {
u32 div_mask;
u32 div_shift;
const char *parent;
- void __iomem *lock_reg;
- u32 lock_mask;
u32 ref_clock;
u32 power_bit;
};
@@ -56,7 +54,6 @@ static int clk_pllv3_enable(struct clk *clk)
int timeout = 10000;
val = readl(pll->base);
- val &= ~BM_PLL_BYPASS;
if (pll->powerup_set)
val |= pll->power_bit;
else
@@ -88,7 +85,6 @@ static void clk_pllv3_disable(struct clk *clk)
val &= ~BM_PLL_ENABLE;
writel(val, pll->base);
- val |= BM_PLL_BYPASS;
if (pll->powerup_set)
val &= ~pll->power_bit;
else
@@ -356,9 +352,6 @@ static int clk_pllv3_sys_vf610_set_rate(struct clk *clk, unsigned long rate,
writel(mfn, pll->base + SYS_VF610_PLL_OFFSET + PLL_NUM_OFFSET);
writel(mfd, pll->base + SYS_VF610_PLL_OFFSET + PLL_DENOM_OFFSET);
- while (!(readl(pll->lock_reg) & pll->lock_mask))
- ;
-
return 0;
}
@@ -429,22 +422,3 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
return &pll->clk;
}
-
-struct clk *imx_clk_pllv3_locked(enum imx_pllv3_type type, const char *name,
- const char *parent, void __iomem *base,
- u32 div_mask, void __iomem *lock_reg, u32 lock_mask)
-{
- struct clk *clk;
- struct clk_pllv3 *pll;
-
- clk = imx_clk_pllv3(type, name, parent, base, div_mask);
- if (IS_ERR(clk))
- return clk;
-
- pll = to_clk_pllv3(clk);
-
- pll->lock_reg = lock_reg;
- pll->lock_mask = lock_mask;
-
- return clk;
-}
diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index 41fa3e92b4..49d66fb592 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -181,8 +181,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
CCSR_PLL1_PFDn_EN(4);
writel(ccsr, CCM_CCSR);
- clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels));
- clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels));
+ clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux2("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels));
+ clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux2("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels));
clk[VF610_CLK_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", PLL1_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[VF610_CLK_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", PLL2_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
@@ -192,8 +192,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", PLL6_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[VF610_CLK_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", PLL7_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
- clk[VF610_CLK_PLL1] = imx_clk_pllv3_locked(IMX_PLLV3_SYS_VF610, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1, PLL_LOCK, BIT(6));
- clk[VF610_CLK_PLL2] = imx_clk_pllv3_locked(IMX_PLLV3_SYS_VF610, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1, PLL_LOCK, BIT(5));
+ clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS_VF610, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1);
+ clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_SYS_VF610, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1);
clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x2);
clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f);
@@ -243,10 +243,10 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", PFD_PLL3_BASE, 2);
clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_usb_otg", PFD_PLL3_BASE, 3);
- clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
- clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
- clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
- clk[VF610_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels));
+ clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux2("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
+ clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux2("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
+ clk[VF610_CLK_SYS_SEL] = imx_clk_mux2("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
+ clk[VF610_CLK_DDR_SEL] = imx_clk_mux2("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels));
clk[VF610_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3);
clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
@@ -478,6 +478,18 @@ static int vf610_switch_cpu_clock_to_500mhz(void)
return -EINVAL;
}
+ /*
+ * Code below alters the frequency of PLL1, and doing so would
+ * require us to wait for PLL1 lock before proceeding to
+ * select it as a clock source again.
+ *
+ * We achive this by relying on PLL1 being disabled implicitly
+ * by selecting different source for "sys_sel", and then
+ * consecutively enabled (which would result in busy waiting
+ * on 'lock' bit) as a part of setting "pll1_pfd_sel" as a
+ * source for "sys_sel".
+ *
+ */
ret = clk_set_parent(clk[VF610_CLK_SYS_SEL], clk[VF610_CLK_PLL2_BUS]);
if (ret < 0) {
pr_crit("Unable to re-parent '%s'\n",
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 8da806403f..c46c2614d9 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -126,10 +126,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent, void __iomem *base,
u32 div_mask);
-struct clk *imx_clk_pllv3_locked(enum imx_pllv3_type type, const char *name,
- const char *parent, void __iomem *base,
- u32 div_mask, void __iomem *lock_reg, u32 lock_mask);
-
struct clk *imx_clk_pfd(const char *name, const char *parent,
void __iomem *reg, u8 idx);
diff --git a/drivers/pci/pci-mvebu.c b/drivers/pci/pci-mvebu.c
index 907bda0f96..91e8ca870b 100644
--- a/drivers/pci/pci-mvebu.c
+++ b/drivers/pci/pci-mvebu.c
@@ -342,7 +342,7 @@ static struct mvebu_pcie *mvebu_pcie_port_probe(struct device_d *dev,
if (mvebu_mbus_add_window_remap_by_id(mem_target, mem_attr,
(resource_size_t)pcie->membase, resource_size(&pcie->mem),
(u32)pcie->mem.start)) {
- dev_err(dev, "PCIe%d.%d unable to add mbus window for mem at %08x+%08x",
+ dev_err(dev, "PCIe%d.%d unable to add mbus window for mem at %08x+%08x\n",
port, lane, (u32)pcie->mem.start, resource_size(&pcie->mem));
free(pcie);
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 021c1e5a2e..d52c184e44 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -449,6 +449,9 @@ static int at91_pinctrl_set_state(struct pinctrl_device *pdev, struct device_nod
info = to_at91_pinctrl(pdev);
list = of_get_property(np, "atmel,pins", &size);
+ if (!list)
+ return -EINVAL;
+
size /= sizeof(*list);
if (!size || size % 4) {
diff --git a/scripts/kwbimage.c b/scripts/kwbimage.c
index 5b84db3f7a..2a052a7ff3 100644
--- a/scripts/kwbimage.c
+++ b/scripts/kwbimage.c
@@ -967,7 +967,11 @@ static void *image_create_v1(struct image_cfg_element *image_cfg,
cur += (binarye->binary.nargs + 1) * sizeof(unsigned int);
- ret = fread(cur, s.st_size, 1, bin);
+ if (s.st_size)
+ ret = fread(cur, s.st_size, 1, bin);
+ else
+ ret = 1;
+
if (ret != 1) {
fprintf(stderr,
"Could not read binary image %s\n",
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-19 19:59:18 +0000