diff options
285 files changed, 12949 insertions, 3972 deletions
diff --git a/Documentation/boards/imx/protonic-prt8mm.rst b/Documentation/boards/imx/protonic-prt8mm.rst new file mode 100644 index 0000000000..f8c8b2c88d --- /dev/null +++ b/Documentation/boards/imx/protonic-prt8mm.rst @@ -0,0 +1,10 @@ +Protonic Holland PRT8MM board +============================= + +This board is a low-cost 7inch touchscreen virtual terminal for agricultural applications. +HW specs: + +* SoC: i.MX8M mini +* RAM: 1GiB LPDDR4 +* eMMC: 16GiB +* Display: 7inch 800x480 with capacitive touchscreen. diff --git a/Documentation/boards/riscv.rst b/Documentation/boards/riscv.rst index 59cdc00a99..387b86c588 100644 --- a/Documentation/boards/riscv.rst +++ b/Documentation/boards/riscv.rst @@ -122,7 +122,7 @@ Run barebox:: Running on DE0-Nano FPGA board ------------------------------- +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ See https://github.com/open-design/riscv-soc-cores/ for instructions on DE0-Nano bitstream generation and loading. @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 2021 -PATCHLEVEL = 05 +PATCHLEVEL = 06 SUBLEVEL = 0 EXTRAVERSION = NAME = None @@ -352,9 +352,6 @@ KCONFIG_CONFIG ?= .config export KCONFIG_CONFIG -# Default file for 'make defconfig'. This may be overridden by arch-Makefile. -export KBUILD_DEFCONFIG := defconfig - # SHELL used by kbuild CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ else if [ -x /bin/bash ]; then echo /bin/bash; \ @@ -596,8 +593,11 @@ $(KCONFIG_CONFIG): # This exploits the 'multi-target pattern rule' trick. # The syncconfig should be executed only once to make all the targets. # (Note: use the grouped target '&:' when we bump to GNU Make 4.3) -%/auto.conf %/auto.conf.cmd: $(KCONFIG_CONFIG) - $(Q)$(MAKE) -f $(srctree)/Makefile syncconfig +quiet_cmd_syncconfig = SYNC $@ + cmd_syncconfig = $(MAKE) -f $(srctree)/Makefile syncconfig + +%/config/auto.conf %/config/auto.conf.cmd %/generated/autoconf.h: $(KCONFIG_CONFIG) + +$(call cmd,syncconfig) else # !may-sync-config # External modules and some install targets need include/generated/autoconf.h # and include/config/auto.conf but do not care if they are up-to-date. @@ -941,7 +941,8 @@ scripts: scripts_basic PHONY += prepare archprepare prepare0 archprepare: outputmakefile scripts_basic include/config/kernel.release \ - $(version_h) include/generated/utsrelease.h include/config.h + $(version_h) include/generated/utsrelease.h include/config.h \ + include/generated/autoconf.h prepare0: archprepare FORCE ifneq ($(KBUILD_MODULES),) diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 40b0af8d30..b3415eb4a2 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -105,6 +105,7 @@ obj-$(CONFIG_MACH_PM9261) += pm9261/ obj-$(CONFIG_MACH_PM9263) += pm9263/ obj-$(CONFIG_MACH_PM9G45) += pm9g45/ obj-$(CONFIG_MACH_PROTONIC_IMX6) += protonic-imx6/ +obj-$(CONFIG_MACH_PROTONIC_IMX8M) += protonic-imx8m/ obj-$(CONFIG_MACH_QIL_A9260) += qil-a926x/ obj-$(CONFIG_MACH_QIL_A9G20) += qil-a926x/ obj-$(CONFIG_MACH_RADXA_ROCK) += radxa-rock/ @@ -129,6 +130,7 @@ obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += altera-socdk/ obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/ obj-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += reflex-achilles/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/ +obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += terasic-de10-nano/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox/ obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += solidrun-microsom/ diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c index 91d143e415..31211448f5 100644 --- a/arch/arm/boards/beaglebone/lowlevel.c +++ b/arch/arm/boards/beaglebone/lowlevel.c @@ -126,7 +126,7 @@ static noinline int beaglebone_sram_init(void) /* Setup the PLLs and the clocks for the peripherals */ if (is_beaglebone_black()) { - am33xx_pll_init(MPUPLL_M_500, DDRPLL_M_400); + am33xx_pll_init(MPUPLL_M_800, DDRPLL_M_400); am335x_sdram_init(0x18B, &ddr3_cmd_ctrl, &ddr3_regs, &ddr3_data); } else { diff --git a/arch/arm/boards/freescale-mx6-sabresd/board.c b/arch/arm/boards/freescale-mx6-sabresd/board.c index b710c05a47..82da8bb1dd 100644 --- a/arch/arm/boards/freescale-mx6-sabresd/board.c +++ b/arch/arm/boards/freescale-mx6-sabresd/board.c @@ -55,7 +55,8 @@ static int ar8031_phy_fixup(struct phy_device *dev) static int sabresd_devices_init(void) { - if (!of_machine_is_compatible("fsl,imx6q-sabresd")) + if (!of_machine_is_compatible("fsl,imx6q-sabresd") && + !of_machine_is_compatible("fsl,imx6qp-sabresd")) return 0; armlinux_set_architecture(3980); @@ -67,7 +68,8 @@ device_initcall(sabresd_devices_init); static int sabresd_coredevices_init(void) { - if (!of_machine_is_compatible("fsl,imx6q-sabresd")) + if (!of_machine_is_compatible("fsl,imx6q-sabresd") && + !of_machine_is_compatible("fsl,imx6qp-sabresd")) return 0; phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, diff --git a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6q-sabresd.imxcfg index 133f499ab9..d0a0b40189 100644 --- a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg +++ b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6q-sabresd.imxcfg @@ -1,128 +1,90 @@ loadaddr 0x10000000 soc imx6 ivtofs 0x400 +wm 32 0x20e056c 0x00020030 +wm 32 0x20e0578 0x00020030 +wm 32 0x20e0588 0x00020030 +wm 32 0x20e0594 0x00020030 +wm 32 0x20e0798 0x000C0000 +wm 32 0x20e0758 0x00000000 +wm 32 0x20e0588 0x00000030 +wm 32 0x20e0594 0x00000030 +wm 32 0x20e056c 0x00000030 +wm 32 0x20e0578 0x00000030 +wm 32 0x20e074c 0x00000030 +wm 32 0x20e057c 0x00000030 +wm 32 0x20e058c 0x00000000 +wm 32 0x20e059c 0x00000030 +wm 32 0x20e05a0 0x00000030 +wm 32 0x20e078c 0x00000030 +wm 32 0x20e0750 0x00020000 wm 32 0x20e05a8 0x00000030 wm 32 0x20e05b0 0x00000030 wm 32 0x20e0524 0x00000030 wm 32 0x20e051c 0x00000030 - wm 32 0x20e0518 0x00000030 wm 32 0x20e050c 0x00000030 wm 32 0x20e05b8 0x00000030 wm 32 0x20e05c0 0x00000030 - -wm 32 0x20e05ac 0x00020030 -wm 32 0x20e05b4 0x00020030 -wm 32 0x20e0528 0x00020030 -wm 32 0x20e0520 0x00020030 - -wm 32 0x20e0514 0x00020030 -wm 32 0x20e0510 0x00020030 -wm 32 0x20e05bc 0x00020030 -wm 32 0x20e05c4 0x00020030 - -wm 32 0x20e056c 0x00020030 -wm 32 0x20e0578 0x00020030 -wm 32 0x20e0588 0x00020030 -wm 32 0x20e0594 0x00020030 - -wm 32 0x20e057c 0x00020030 -wm 32 0x20e0590 0x00003000 -wm 32 0x20e0598 0x00003000 -wm 32 0x20e058c 0x00000000 - -wm 32 0x20e059c 0x00003030 -wm 32 0x20e05a0 0x00003030 +wm 32 0x20e0774 0x00020000 wm 32 0x20e0784 0x00000030 wm 32 0x20e0788 0x00000030 - wm 32 0x20e0794 0x00000030 wm 32 0x20e079c 0x00000030 wm 32 0x20e07a0 0x00000030 wm 32 0x20e07a4 0x00000030 - wm 32 0x20e07a8 0x00000030 wm 32 0x20e0748 0x00000030 -wm 32 0x20e074c 0x00000030 -wm 32 0x20e0750 0x00020000 - -wm 32 0x20e0758 0x00000000 -wm 32 0x20e0774 0x00020000 -wm 32 0x20e078c 0x00000030 -wm 32 0x20e0798 0x000C0000 - +wm 32 0x20e05ac 0x00000030 +wm 32 0x20e05b4 0x00000030 +wm 32 0x20e0528 0x00000030 +wm 32 0x20e0520 0x00000030 +wm 32 0x20e0514 0x00000030 +wm 32 0x20e0510 0x00000030 +wm 32 0x20e05bc 0x00000030 +wm 32 0x20e05c4 0x00000030 +wm 32 0x21b0800 0xa1390003 +wm 32 0x21b080c 0x001F001F +wm 32 0x21b0810 0x001F001F +wm 32 0x21b480c 0x001F001F +wm 32 0x21b4810 0x001F001F +wm 32 0x21b083c 0x43270338 +wm 32 0x21b0840 0x03200314 +wm 32 0x21b483c 0x431A032F +wm 32 0x21b4840 0x03200263 +wm 32 0x21b0848 0x4B434748 +wm 32 0x21b4848 0x4445404C +wm 32 0x21b0850 0x38444542 +wm 32 0x21b4850 0x4935493A wm 32 0x21b081c 0x33333333 wm 32 0x21b0820 0x33333333 wm 32 0x21b0824 0x33333333 wm 32 0x21b0828 0x33333333 - wm 32 0x21b481c 0x33333333 wm 32 0x21b4820 0x33333333 wm 32 0x21b4824 0x33333333 wm 32 0x21b4828 0x33333333 - -wm 32 0x21b0018 0x00081740 - -wm 32 0x21b001c 0x00008000 +wm 32 0x21b08b8 0x00000800 +wm 32 0x21b48b8 0x00000800 +wm 32 0x21b0004 0x00020036 +wm 32 0x21b0008 0x09444040 wm 32 0x21b000c 0x555A7975 -wm 32 0x21b0010 0xFF538E64 +wm 32 0x21b0010 0xFF538F64 wm 32 0x21b0014 0x01FF00DB -wm 32 0x21b002c 0x000026D2 - -wm 32 0x21b0030 0x005B0E21 -wm 32 0x21b0008 0x09444040 -wm 32 0x21b0004 0x00025576 +wm 32 0x21b0018 0x00001740 +wm 32 0x21b001c 0x00008000 +wm 32 0x21b002c 0x000026d2 +wm 32 0x21b0030 0x005A1023 wm 32 0x21b0040 0x00000027 wm 32 0x21b0000 0x831A0000 - wm 32 0x21b001c 0x04088032 -wm 32 0x21b001c 0x0408803A wm 32 0x21b001c 0x00008033 -wm 32 0x21b001c 0x0000803B -wm 32 0x21b001c 0x00428031 -wm 32 0x21b001c 0x00428039 +wm 32 0x21b001c 0x00048031 wm 32 0x21b001c 0x09408030 -wm 32 0x21b001c 0x09408038 - wm 32 0x21b001c 0x04008040 -wm 32 0x21b001c 0x04008048 -wm 32 0x21b0800 0xA1380003 -wm 32 0x21b4800 0xA1380003 wm 32 0x21b0020 0x00005800 -wm 32 0x21b0818 0x00022227 -wm 32 0x21b4818 0x00022227 - -wm 32 0x21b083c 0x434B0350 -wm 32 0x21b0840 0x034C0359 -wm 32 0x21b483c 0x434B0350 -wm 32 0x21b4840 0x03650348 -wm 32 0x21b0848 0x4436383B -wm 32 0x21b4848 0x39393341 -wm 32 0x21b0850 0x35373933 -wm 32 0x21b4850 0x48254A36 - -wm 32 0x21b080c 0x001F001F -wm 32 0x21b0810 0x001F001F - -wm 32 0x21b480c 0x00440044 -wm 32 0x21b4810 0x00440044 - -wm 32 0x21b08b8 0x00000800 -wm 32 0x21b48b8 0x00000800 - -wm 32 0x21b001c 0x00000000 +wm 32 0x21b0818 0x00011117 +wm 32 0x21b4818 0x00011117 +wm 32 0x21b0004 0x00025576 wm 32 0x21b0404 0x00011006 - -wm 32 0x020c4068 0x00c03f3f -wm 32 0x020c406c 0x0030fc03 -wm 32 0x020c4070 0x0fffc000 -wm 32 0x020c4074 0x3ff00000 -wm 32 0x020c4078 0x00fff300 -wm 32 0x020c407c 0x0f0000c3 -wm 32 0x020c4080 0x000003ff - -# enable AXI cache for VDOA/VPU/IPU -wm 32 0x20e0010 0xf00000cf -# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 -wm 32 0x20e0018 0x007f007f -wm 32 0x20e001c 0x007f007f +wm 32 0x21b001c 0x00000000 diff --git a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6qp-sabresd.imxcfg b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6qp-sabresd.imxcfg new file mode 100644 index 0000000000..aa52776afb --- /dev/null +++ b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6qp-sabresd.imxcfg @@ -0,0 +1,96 @@ +loadaddr 0x10000000 +soc imx6 +ivtofs 0x400 +wm 32 0x20e0798 0x000c0000 +wm 32 0x20e0758 0x00000000 +wm 32 0x20e0588 0x00000030 +wm 32 0x20e0594 0x00000030 +wm 32 0x20e056c 0x00000030 +wm 32 0x20e0578 0x00000030 +wm 32 0x20e074c 0x00000030 +wm 32 0x20e057c 0x00000030 +wm 32 0x20e058c 0x00000000 +wm 32 0x20e059c 0x00000030 +wm 32 0x20e05a0 0x00000030 +wm 32 0x20e078c 0x00000030 +wm 32 0x20e0750 0x00020000 +wm 32 0x20e05a8 0x00000030 +wm 32 0x20e05b0 0x00000030 +wm 32 0x20e0524 0x00000030 +wm 32 0x20e051c 0x00000030 +wm 32 0x20e0518 0x00000030 +wm 32 0x20e050c 0x00000030 +wm 32 0x20e05b8 0x00000030 +wm 32 0x20e05c0 0x00000030 +wm 32 0x20e0774 0x00020000 +wm 32 0x20e0784 0x00000030 +wm 32 0x20e0788 0x00000030 +wm 32 0x20e0794 0x00000030 +wm 32 0x20e079c 0x00000030 +wm 32 0x20e07a0 0x00000030 +wm 32 0x20e07a4 0x00000030 +wm 32 0x20e07a8 0x00000030 +wm 32 0x20e0748 0x00000030 +wm 32 0x20e05ac 0x00000030 +wm 32 0x20e05b4 0x00000030 +wm 32 0x20e0528 0x00000030 +wm 32 0x20e0520 0x00000030 +wm 32 0x20e0514 0x00000030 +wm 32 0x20e0510 0x00000030 +wm 32 0x20e05bc 0x00000030 +wm 32 0x20e05c4 0x00000030 +wm 32 0x21b0800 0xa1390003 +wm 32 0x21b080c 0x001b001e +wm 32 0x21b0810 0x002e0029 +wm 32 0x21b480c 0x001b002a +wm 32 0x21b4810 0x0019002c +wm 32 0x21b083c 0x43240334 +wm 32 0x21b0840 0x0324031a +wm 32 0x21b483c 0x43340344 +wm 32 0x21b4840 0x03280276 +wm 32 0x21b0848 0x44383A3E +wm 32 0x21b4848 0x3C3C3846 +wm 32 0x21b0850 0x2e303230 +wm 32 0x21b4850 0x38283E34 +wm 32 0x21b081c 0x33333333 +wm 32 0x21b0820 0x33333333 +wm 32 0x21b0824 0x33333333 +wm 32 0x21b0828 0x33333333 +wm 32 0x21b481c 0x33333333 +wm 32 0x21b4820 0x33333333 +wm 32 0x21b4824 0x33333333 +wm 32 0x21b4828 0x33333333 +wm 32 0x21b08c0 0x24912249 +wm 32 0x21b48c0 0x24914289 +wm 32 0x21b08b8 0x00000800 +wm 32 0x21b48b8 0x00000800 +wm 32 0x21b0004 0x00020036 +wm 32 0x21b0008 0x24444040 +wm 32 0x21b000c 0x555A7955 +wm 32 0x21b0010 0xFF320F64 +wm 32 0x21b0014 0x01ff00db +wm 32 0x21b0018 0x00001740 +wm 32 0x21b001c 0x00008000 +wm 32 0x21b002c 0x000026d2 +wm 32 0x21b0030 0x005A1023 +wm 32 0x21b0040 0x00000027 +wm 32 0x21b0400 0x14420000 +wm 32 0x21b0000 0x831A0000 +wm 32 0x21b0890 0x00400C58 +wm 32 0x0bb0008 0x00000000 +wm 32 0x0bb000c 0x2891E41A +wm 32 0x0bb0038 0x00000564 +wm 32 0x0bb0014 0x00000040 +wm 32 0x0bb0028 0x00000020 +wm 32 0x0bb002c 0x00000020 +wm 32 0x21b001c 0x04088032 +wm 32 0x21b001c 0x00008033 +wm 32 0x21b001c 0x00048031 +wm 32 0x21b001c 0x09408030 +wm 32 0x21b001c 0x04008040 +wm 32 0x21b0020 0x00005800 +wm 32 0x21b0818 0x00011117 +wm 32 0x21b4818 0x00011117 +wm 32 0x21b0004 0x00025576 +wm 32 0x21b0404 0x00011006 +wm 32 0x21b001c 0x00000000 diff --git a/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c b/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c index ae847feaa6..7f83366e7a 100644 --- a/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c +++ b/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c @@ -35,3 +35,19 @@ ENTRY_FUNCTION(start_imx6q_sabresd, r0, r1, r2) barebox_arm_entry(0x10000000, SZ_1G, fdt); } + +extern char __dtb_imx6qp_sabresd_start[]; + +ENTRY_FUNCTION(start_imx6qp_sabresd, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = __dtb_imx6qp_sabresd_start + get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} diff --git a/arch/arm/boards/friendlyarm-tiny210/tiny210.c b/arch/arm/boards/friendlyarm-tiny210/tiny210.c index c96aa83059..c47f488207 100644 --- a/arch/arm/boards/friendlyarm-tiny210/tiny210.c +++ b/arch/arm/boards/friendlyarm-tiny210/tiny210.c @@ -31,11 +31,6 @@ #include <mach/s3c-clocks.h> #include <mach/s3c-generic.h> - -static const unsigned pin_usage[] = { - /* TODO */ -}; - static struct gpio_led leds[] = { { .gpio = GPJ20, @@ -91,8 +86,6 @@ console_initcall(tiny210_console_init); static int tiny210_devices_init(void) { int i; - for (i = 0; i < ARRAY_SIZE(pin_usage); i++) - s3c_gpio_mode(pin_usage[i]); for (i = 0; i < ARRAY_SIZE(leds); i++) { leds[i].active_low = 1; diff --git a/arch/arm/boards/phytec-phycard-omap3/lowlevel.c b/arch/arm/boards/phytec-phycard-omap3/lowlevel.c index 54d8eaaddf..546fa78735 100644 --- a/arch/arm/boards/phytec-phycard-omap3/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-omap3/lowlevel.c @@ -98,7 +98,7 @@ static void config_sdram_ddr(u8 cs, u8 cfg) static void pcaal1_sdrc_init(void) { u32 test0, test1; - char cfg; + signed char cfg; init_sdram_ddr(); diff --git a/arch/arm/boards/protonic-imx8m/Makefile b/arch/arm/boards/protonic-imx8m/Makefile new file mode 100644 index 0000000000..51a27f0c2d --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/Makefile @@ -0,0 +1,3 @@ +obj-y += board.o +lwl-y += lowlevel-prt8mm.o lpddr4-timing-prt8mm.o +bbenv-y += defaultenv-prt8m diff --git a/arch/arm/boards/protonic-imx8m/board.c b/arch/arm/boards/protonic-imx8m/board.c new file mode 100644 index 0000000000..87264f0c97 --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/board.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2020 David Jander, Protonic Holland + +#include <bootsource.h> +#include <common.h> +#include <envfs.h> +#include <environment.h> +#include <i2c/i2c.h> +#include <init.h> +#include <mach/bbu.h> + +static int prt_prt8mm_init_power(void) +{ + struct i2c_adapter *adapter = NULL; + struct i2c_client client; + int ret; + char buf[2]; + + client.addr = 0x60; + adapter = i2c_get_adapter(1); + if (!adapter) { + printf("i2c bus not found\n"); + return -ENODEV; + } + client.adapter = adapter; + + buf[0] = 0xe3; + ret = i2c_write_reg(&client, 0x00, buf, 1); // VSEL0 = 0.95V, force PWM + if (ret < 0) { + printf("i2c write error\n"); + return -ENODEV; + } + buf[0] = 0xe0; + ret = i2c_write_reg(&client, 0x01, buf, 1); // VSEL1 = 0.92V, force PWM + if (ret < 0) { + printf("i2c write error\n"); + return -ENODEV; + } + return 0; +} + +static int prt_prt8mm_probe(struct device_d *dev) +{ + int emmc_bbu_flag = 0; + int sd_bbu_flag = 0; + + prt_prt8mm_init_power(); + + barebox_set_hostname("prt8mm"); + + if (bootsource_get() == BOOTSOURCE_MMC) { + if (bootsource_get_instance() == 2) { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + of_device_enable_path("/chosen/environment-sd"); + sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + } else { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", + sd_bbu_flag); + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", + emmc_bbu_flag); + + defaultenv_append_directory(defaultenv_prt8m); + + return 0; +} + +static const struct of_device_id prt_imx8mm_of_match[] = { + { .compatible = "prt,prt8mm", }, + { /* sentinel */ }, +}; + +static struct driver_d prt_prt8mm_board_driver = { + .name = "board-protonic-imx8mm", + .probe = prt_prt8mm_probe, + .of_compatible = DRV_OF_COMPAT(prt_imx8mm_of_match), +}; +device_platform_driver(prt_prt8mm_board_driver); diff --git a/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/boot/prt8mm-default b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/boot/prt8mm-default new file mode 100644 index 0000000000..ca8bef306d --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/boot/prt8mm-default @@ -0,0 +1,7 @@ +#!/bin/sh + +if [ "$bootsource_instance" = "2" ]; then + boot mmc2 +else + boot mmc3 +fi diff --git a/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/network/eth0-discover b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/network/eth0-discover new file mode 100644 index 0000000000..18f2446387 --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/network/eth0-discover @@ -0,0 +1,4 @@ +#!/bin/sh + +# PRT8M doesn't have a ETH port, but may have USB network attached +usb diff --git a/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/nv/boot.default b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/nv/boot.default new file mode 100644 index 0000000000..ba8938923a --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/nv/boot.default @@ -0,0 +1 @@ +prt8mm-default diff --git a/arch/arm/boards/protonic-imx8m/flash-header-prt8mm.imxcfg b/arch/arm/boards/protonic-imx8m/flash-header-prt8mm.imxcfg new file mode 100644 index 0000000000..b013173113 --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/flash-header-prt8mm.imxcfg @@ -0,0 +1,5 @@ +soc imx8mm + +loadaddr 0x007e1000 +max_load_size 0x3f000 +ivtofs 0x400 diff --git a/arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c b/arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c new file mode 100644 index 0000000000..3b8b53b36e --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <asm/barebox-arm.h> +#include <common.h> +#include <debug_ll.h> +#include <firmware.h> +#include <mach/atf.h> +#include <mach/esdctl.h> +#include <mach/generic.h> +#include <mach/imx8m-ccm-regs.h> +#include <mach/imx8mm-regs.h> +#include <mach/iomux-mx8mm.h> +#include <mach/xload.h> +#include <soc/fsl/fsl_udc.h> +#include <soc/imx8m/ddr.h> + +extern char __dtb_imx8mm_prt8mm_start[]; + +#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM) + +static void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART4_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mm_setup_pad(IMX8MM_PAD_UART4_TXD_UART4_TX | UART_PAD_CTRL); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +extern struct dram_timing_info prt8mm_dram_timing; + +static void start_atf(void) +{ + size_t bl31_size; + const u8 *bl31; + enum bootsource src; + int instance; + + /* + * If we are in EL3 we are running for the first time and need to + * initialize the DRAM and run TF-A (BL31). The TF-A will then jump + * to DRAM in EL2. + */ + if (current_el() != 3) + return; + + imx8mm_early_clock_init(); + + imx8mm_ddr_init(&prt8mm_dram_timing); + + imx8mm_get_boot_source(&src, &instance); + switch (src) { + case BOOTSOURCE_MMC: + imx8m_esdhc_load_image(instance, false); + break; + case BOOTSOURCE_SERIAL: + imx8mm_barebox_load_usb((void *)MX8M_ATF_BL33_BASE_ADDR); + break; + default: + printf("Unhandled bootsource BOOTSOURCE_%d\n", src); + hang(); + } + + /* + * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR + * in EL2. Copy the image there, but replace the PBL part of + * that image with ourselves. On a high assurance boot only the + * currently running code is validated and contains the checksum + * for the piggy data, so we need to ensure that we are running + * the same code in DRAM. + */ + memcpy((void *)MX8MM_ATF_BL33_BASE_ADDR, + __image_start, barebox_pbl_size); + + get_builtin_firmware(imx8mm_bl31_bin, &bl31, &bl31_size); + imx8mm_atf_load_bl31(bl31, bl31_size); + + /* not reached */ +} + +/* + * Power-on execution flow of start_prt_prt8mm() might not be + * obvious for a very first read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time. At entry the exception level is EL3. + * + * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL + * part is copied from OCRAM to the TF-A return address in DRAM. + * + * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us + * from EL3 to EL2. + * + * 4. Standard barebox boot flow continues + */ +static __noreturn noinline void prt_prt8mm_start(void) +{ + setup_uart(); + + start_atf(); + + /* + * Standard entry we hit once we initialized both DDR and ATF + */ + imx8mm_barebox_entry(__dtb_imx8mm_prt8mm_start); +} + +ENTRY_FUNCTION(start_prt_prt8mm, r0, r1, r2) +{ + imx8mm_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + prt_prt8mm_start(); +} diff --git a/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c b/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c new file mode 100644 index 0000000000..2c55e7d451 --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c @@ -0,0 +1,1994 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> + +#define DDR_ONE_RANK +#include <soc/imx8m/lpddr4_define.h> + +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + { DDRC_DBG1(0), 0x00000001 }, + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa1080020 }, + { DDRC_RFSHTMG(0), 0x005b0087 }, + { DDRC_INIT0(0), 0xc00305ba }, + { DDRC_INIT1(0), 0x00940000 }, + { DDRC_INIT3(0), 0x00D4002D }, + { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, + { DDRC_INIT6(0), 0x0066004d }, + { DDRC_INIT7(0), 0x0016004d }, + + { DDRC_DRAMTMG0(0), 0x191e1920 }, + { DDRC_DRAMTMG1(0), 0x00060630 }, + { DDRC_DRAMTMG3(0), 0x00B0B000 }, + { DDRC_DRAMTMG4(0), 0x0e04080e }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0c100002 }, + { DDRC_DRAMTMG14(0), 0x0000008d }, + { DDRC_DRAMTMG17(0), 0x0090004b }, + + //{ DDRC_DERATEEN(0), 0x00000203 }, + //{ DDRC_DERATEINT(0), 0x0003a980 }, + + { DDRC_ZQCTL0(0), 0x02ee0017 }, + { DDRC_ZQCTL1(0), 0x02605b8e }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG2(0), 0x0000170A }, + { DDRC_DRAMTMG2(0), 0x070e1617 }, + { DDRC_DBICTL(0), 0x00000001 }, + + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + + { DDRC_DFIPHYMSTR(0), 0x00000000 }, + { DDRC_RANKCTL(0), 0x00000c99 }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), 0x0000001f }, + { DDRC_ADDRMAP1(0), 0x00080808 }, + { DDRC_ADDRMAP2(0), 0x00000000 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + { DDRC_ADDRMAP4(0), 0x00001f1f }, + { DDRC_ADDRMAP5(0), 0x07070707 }, + { DDRC_ADDRMAP6(0), 0x0F070707 }, + { DDRC_ADDRMAP7(0), 0x00000f0f }, + + /* performance setting */ + { DDRC_SCHED(0), 0x29001701 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x04000030 }, + { DDRC_PERFLPR1(0), 0x900093e7 }, + { DDRC_PERFWR1(0), 0x02005574 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCFGQOS0_0(0), 0x02100e07 }, + { DDRC_PCFGQOS1_0(0), 0x00620096 }, + { DDRC_PCFGWQOS0_0(0), 0x01100e07 }, + { DDRC_PCFGWQOS1_0(0), 0x00c8012c }, + + /* frequency P1&P2 */ + /* Frequency 1: 400MHz */ + { DDRC_FREQ1_DRAMTMG0(0), 0x0c080609 }, + { DDRC_FREQ1_DRAMTMG1(0), 0x0003040d }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505000 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x04040204 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x02030303 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x01010004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x00000301 }, + //{ DDRC_FREQ1_DRAMTMG12(0), 0x00020300 }, + //{ DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 }, + { DDRC_FREQ1_DRAMTMG14(0), 0x00000026 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x00280014 }, + //{ DDRC_FREQ1_DERATEEN(0), 0x00000001 }, + { DDRC_FREQ1_DERATEINT(0), 0x00007a00 }, + //{ DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 }, + //{ DDRC_FREQ1_ZQCTL0(0), 0x00c80006 }, + { DDRC_FREQ1_DFITMG0(0), 0x03858202 }, + //{ DDRC_FREQ1_DFITMG1(0), 0x00080303 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000502 }, + { DDRC_FREQ1_RFSHTMG(0), 0x00180024 }, + { DDRC_FREQ1_INIT3(0), 0x00940009 }, + { DDRC_FREQ1_INIT4(0), 0x00310000 }, + { DDRC_FREQ1_INIT6(0), 0x0066004d }, + { DDRC_FREQ1_INIT7(0), 0x0016004d }, + // { DDRC_FREQ1_RANKCTL(0), 0x00000c99 }, + + /* Frequency 2: 100MHz */ + { DDRC_FREQ2_DRAMTMG0(0), 0x0a020103 }, + { DDRC_FREQ2_DRAMTMG1(0), 0x00030405 }, + { DDRC_FREQ2_DRAMTMG2(0), 0x0203060b }, + { DDRC_FREQ2_DRAMTMG3(0), 0x00505000 }, + { DDRC_FREQ2_DRAMTMG4(0), 0x02040202 }, + { DDRC_FREQ2_DRAMTMG5(0), 0x02030202 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x01010004 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x00000301 }, + //{ DDRC_FREQ2_DRAMTMG12(0), 0x00020300 }, + //{ DDRC_FREQ2_DRAMTMG13(0), 0x0a100002 }, + { DDRC_FREQ2_DRAMTMG14(0), 0x0000000a }, + { DDRC_FREQ2_DRAMTMG17(0), 0x000a0005 }, + //{ DDRC_FREQ2_DERATEEN(0), 0x00000001 }, + { DDRC_FREQ2_DERATEINT(0), 0x00003e80 }, + //{ DDRC_FREQ2_RFSHCTL0(0), 0x0020d040 }, + //{ DDRC_FREQ2_ZQCTL0(0), 0x00320004 }, + { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, + //{ DDRC_FREQ2_DFITMG1(0), 0x00080303 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000100 }, + { DDRC_FREQ2_RFSHTMG(0), 0x00060009 }, + { DDRC_FREQ2_INIT3(0), 0x00840000 }, + { DDRC_FREQ2_INIT4(0), 0x00310008 }, + //{ DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, + { DDRC_FREQ2_INIT6(0), 0x0066004d }, + { DDRC_FREQ2_INIT7(0), 0x0016004d }, + // { DDRC_FREQ2_RANKCTL(0), 0x00000c99 }, + + /* boot start point */ + { DDRC_MSTR2(0), 0x0 }, //DDRC_MSTR2 +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + + { 0x20024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x120024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x220024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + + { 0x200b2, 0x1d4 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + + { 0x20025, 0x0 }, + { 0x2002d, LPDDR4_PHY_DMIPinPresent }, + { 0x12002d, LPDDR4_PHY_DMIPinPresent }, + { 0x22002d, LPDDR4_PHY_DMIPinPresent }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x2200c7, 0x21 }, + { 0x2200ca, 0x24 }, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xbb8 }, // 3000 + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, // LPDDR4_HDT_CTL_3200_1D + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0xd400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */ + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0x8400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0x8400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0xd400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x5d }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, { + /* P1 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info prt8mm_dram_timing = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), +}; diff --git a/arch/arm/boards/terasic-de10-nano/Makefile b/arch/arm/boards/terasic-de10-nano/Makefile new file mode 100644 index 0000000000..8c927fe291 --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/Makefile @@ -0,0 +1,2 @@ +obj-y += lowlevel.o board.o +pbl-y += lowlevel.o diff --git a/arch/arm/boards/terasic-de10-nano/board.c b/arch/arm/boards/terasic-de10-nano/board.c new file mode 100644 index 0000000000..dc0e8967de --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/board.c @@ -0,0 +1,35 @@ +#include <common.h> +#include <types.h> +#include <driver.h> +#include <init.h> +#include <asm/armlinux.h> +#include <linux/micrel_phy.h> +#include <linux/phy.h> +#include <linux/sizes.h> +#include <fcntl.h> +#include <fs.h> +#include <mach/cyclone5-regs.h> + +static int phy_fixup(struct phy_device *dev) +{ + /* + * min rx data delay, max rx/tx clock delay, + * min rx/tx control delay + */ + phy_write_mmd_indirect(dev, 4, 2, 0); + phy_write_mmd_indirect(dev, 5, 2, 0); + phy_write_mmd_indirect(dev, 8, 2, 0x003ff); + return 0; +} + +static int socfpga_init(void) +{ + if (!of_machine_is_compatible("terasic,de10-nano")) + return 0; + + if (IS_ENABLED(CONFIG_PHYLIB)) + phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, phy_fixup); + + return 0; +} +console_initcall(socfpga_init); diff --git a/arch/arm/boards/terasic-de10-nano/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-de10-nano/iocsr_config_cyclone5.c new file mode 100644 index 0000000000..c1291dea40 --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/iocsr_config_cyclone5.c @@ -0,0 +1,678 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <mach/cyclone5-scan-manager.h> + +static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] + = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00000000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00020000, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, +}; + +static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] + = { + 0x00100000, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x00008000, + 0x00060180, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x000300C0, + 0x10000000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00020000, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x00010000, + 0x04000000, + 0x00000000, + 0x00000010, + 0x00004000, + 0x00000800, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000008, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] + = { + 0x300C0300, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x000300C0, + 0x00008000, + 0x00080000, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00020000, + 0x00004000, + 0x200300C0, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x00002000, + 0x10018060, + 0x06018000, + 0x06000000, + 0x00010018, + 0x00006018, + 0x00001000, + 0x00010000, + 0x00000000, + 0x03000000, + 0x0000800C, + 0x00C0300C, + 0x00000800, +}; + +static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] + = { + 0x0C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x45034071, + 0x0A281A01, + 0x806180D0, + 0x34071C06, + 0x01A034D0, + 0x180D0000, + 0x71C06806, + 0x01450340, + 0xD000001A, + 0x0680E380, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x45034071, + 0x0A281A01, + 0x806180D0, + 0x34071C06, + 0x01A00040, + 0x180D0002, + 0x71C06806, + 0x01450340, + 0xD00A281A, + 0x06806180, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x79E47A03, + 0xCAAAA3DD, + 0xF6D5551E, + 0x0352D348, + 0x821A0000, + 0x0000D000, + 0x030C0680, + 0xD559647A, + 0x1ECAAAA3, + 0xC8F6D965, + 0x00034AB2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x79E47A03, + 0x8B2CA3DD, + 0xF6D9651E, + 0x034AB2C8, + 0x821A0041, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1E8B2CA3, + 0xC8F6D965, + 0x00034AB2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0x8AAAA3D5, + 0xF6D9651E, + 0x034AB2C8, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1E8B2CA3, + 0xC8F6D965, + 0x00034AB2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0x8B2CA3D5, + 0xF6D9651E, + 0x0352D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1E8B2CA3, + 0x48F6D965, + 0x000352D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; diff --git a/arch/arm/boards/terasic-de10-nano/lowlevel.c b/arch/arm/boards/terasic-de10-nano/lowlevel.c new file mode 100644 index 0000000000..d80cea6f20 --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/lowlevel.c @@ -0,0 +1,13 @@ +#include "sdram_config.h" +#include "pinmux_config.c" +#include "pll_config.h" +#include "sequencer_defines.h" +#include "sequencer_auto.h" +#include "sequencer_auto_inst_init.c" +#include "sequencer_auto_ac_init.c" +#include "iocsr_config_cyclone5.c" + +#include <mach/lowlevel.h> + +SOCFPGA_C5_ENTRY(start_socfpga_de10_nano, socfpga_cyclone5_de10_nano, SZ_1G); +SOCFPGA_C5_XLOAD_ENTRY(start_socfpga_de10_nano_xload, SZ_1G); diff --git a/arch/arm/boards/terasic-de10-nano/pinmux_config.c b/arch/arm/boards/terasic-de10-nano/pinmux_config.c new file mode 100644 index 0000000000..7dbe1c1d1f --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/pinmux_config.c @@ -0,0 +1,241 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <common.h> + +/* pin MUX configuration data */ +static unsigned long sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 1, /* GENERALIO15 */ + 1, /* GENERALIO16 */ + 1, /* GENERALIO17 */ + 1, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 0, /* MIXED1IO15 */ + 0, /* MIXED1IO16 */ + 0, /* MIXED1IO17 */ + 0, /* MIXED1IO18 */ + 0, /* MIXED1IO19 */ + 0, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; diff --git a/arch/arm/boards/terasic-de10-nano/pll_config.h b/arch/arm/boards/terasic-de10-nano/pll_config.h new file mode 100644 index 0000000000..d78eaae98a --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/pll_config.h @@ -0,0 +1,107 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PRELOADER_PLL_CONFIG_H_ +#define _PRELOADER_PLL_CONFIG_H_ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 (1) + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511) +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511) +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39) +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (4) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (4) +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) +#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (4) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) + +#define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_OSC2_HZ (25000000) +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0) +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0) +#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) +#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) +#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000) +#define CONFIG_HPS_CLK_EMAC0_HZ (1953125) +#define CONFIG_HPS_CLK_EMAC1_HZ (250000000) +#define CONFIG_HPS_CLK_USBCLK_HZ (200000000) +#define CONFIG_HPS_CLK_NAND_HZ (50000000) +#define CONFIG_HPS_CLK_SDMMC_HZ (200000000) +#define CONFIG_HPS_CLK_QSPI_HZ (3125000) +#define CONFIG_HPS_CLK_SPIM_HZ (200000000) +#define CONFIG_HPS_CLK_CAN0_HZ (12500000) +#define CONFIG_HPS_CLK_CAN1_HZ (12500000) +#define CONFIG_HPS_CLK_GPIODB_HZ (32000) +#define CONFIG_HPS_CLK_L4_MP_HZ (100000000) +#define CONFIG_HPS_CLK_L4_SP_HZ (100000000) + +#define CONFIG_HPS_ALTERAGRP_MPUCLK (1) +#define CONFIG_HPS_ALTERAGRP_MAINCLK (3) +#define CONFIG_HPS_ALTERAGRP_DBGATCLK (3) + +#endif /* _PRELOADER_PLL_CONFIG_H_ */ diff --git a/arch/arm/boards/terasic-de10-nano/sdram_config.h b/arch/arm/boards/terasic-de10-nano/sdram_config.h new file mode 100644 index 0000000000..8f084021d5 --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/sdram_config.h @@ -0,0 +1,112 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SDRAM_CONFIG_H +#define __SDRAM_CONFIG_H + +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE (2) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL (8) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN (1) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT (10) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS (0) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL (7) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL (0) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL (7) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD (3) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW (15) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC (120) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI (3120) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD (6) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP (6) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR (6) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR (4) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP (3) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS (14) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC (20) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD (4) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD (4) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT (512) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT (3) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES (0) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES (8) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS (10) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS (15) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS (3) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS (1) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH (32) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH (8) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN (0) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK (3) +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL (2) +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH (2) +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN (0) +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE (0) +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC (0) +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 (0x21084210) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 (0x10441) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 (0x78) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 (0x200) + +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH (0x44555) +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP (0x2C011000) +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP (0xB00088) +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP (0x760210) +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP (0x980543) +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR (0x5A56A) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 (0x20820820) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 (0x8208208) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 (0) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 (0x41041041) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 (0x410410) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \ +(0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \ +(0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \ +(0x0101) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0xF) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0xF) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0x1) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST (0x1FF) + +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR (2) +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC (2) +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2) + +#endif /*#ifndef__SDRAM_CONFIG_H */ diff --git a/arch/arm/boards/terasic-de10-nano/sequencer_auto.h b/arch/arm/boards/terasic-de10-nano/sequencer_auto.h new file mode 100644 index 0000000000..34dc3108aa --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/sequencer_auto.h @@ -0,0 +1,225 @@ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Intel Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#define __RW_MGR_ac_mrs1 0x04 +#define __RW_MGR_ac_mrs3 0x06 +#define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C +#define __RW_MGR_ac_act_1 0x11 +#define __RW_MGR_ac_write_postdata 0x1A +#define __RW_MGR_ac_act_0 0x10 +#define __RW_MGR_ac_des 0x0D +#define __RW_MGR_ac_init_reset_1_cke_0 0x01 +#define __RW_MGR_ac_write_data 0x19 +#define __RW_MGR_ac_init_reset_0_cke_0 0x00 +#define __RW_MGR_ac_read_bank_0_1_norden 0x22 +#define __RW_MGR_ac_pre_all 0x12 +#define __RW_MGR_ac_mrs0_user 0x02 +#define __RW_MGR_ac_mrs0_dll_reset 0x03 +#define __RW_MGR_ac_read_bank_0_0 0x1D +#define __RW_MGR_ac_write_bank_0_col_1 0x16 +#define __RW_MGR_ac_read_bank_0_1 0x1F +#define __RW_MGR_ac_write_bank_1_col_0 0x15 +#define __RW_MGR_ac_write_bank_1_col_1 0x17 +#define __RW_MGR_ac_write_bank_0_col_0 0x14 +#define __RW_MGR_ac_read_bank_1_0 0x1E +#define __RW_MGR_ac_mrs1_mirr 0x0A +#define __RW_MGR_ac_read_bank_1_1 0x20 +#define __RW_MGR_ac_des_odt_1 0x0E +#define __RW_MGR_ac_mrs0_dll_reset_mirr 0x09 +#define __RW_MGR_ac_zqcl 0x07 +#define __RW_MGR_ac_write_predata 0x18 +#define __RW_MGR_ac_mrs0_user_mirr 0x08 +#define __RW_MGR_ac_ref 0x13 +#define __RW_MGR_ac_nop 0x0F +#define __RW_MGR_ac_rdimm 0x23 +#define __RW_MGR_ac_mrs2_mirr 0x0B +#define __RW_MGR_ac_write_bank_0_col_0_nodata 0x1B +#define __RW_MGR_ac_read_en 0x21 +#define __RW_MGR_ac_mrs3_mirr 0x0C +#define __RW_MGR_ac_mrs2 0x05 +#define __RW_MGR_CONTENT_ac_mrs1 0x10090044 +#define __RW_MGR_CONTENT_ac_mrs3 0x100B0000 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata_wl_1 0x18980000 +#define __RW_MGR_CONTENT_ac_act_1 0x106B0000 +#define __RW_MGR_CONTENT_ac_write_postdata 0x38780000 +#define __RW_MGR_CONTENT_ac_act_0 0x10680000 +#define __RW_MGR_CONTENT_ac_des 0x30780000 +#define __RW_MGR_CONTENT_ac_init_reset_1_cke_0 0x20780000 +#define __RW_MGR_CONTENT_ac_write_data 0x3CF80000 +#define __RW_MGR_CONTENT_ac_init_reset_0_cke_0 0x20700000 +#define __RW_MGR_CONTENT_ac_read_bank_0_1_norden 0x10580008 +#define __RW_MGR_CONTENT_ac_pre_all 0x10280400 +#define __RW_MGR_CONTENT_ac_mrs0_user 0x10080431 +#define __RW_MGR_CONTENT_ac_mrs0_dll_reset 0x10080530 +#define __RW_MGR_CONTENT_ac_read_bank_0_0 0x13580000 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_1 0x1C980008 +#define __RW_MGR_CONTENT_ac_read_bank_0_1 0x13580008 +#define __RW_MGR_CONTENT_ac_write_bank_1_col_0 0x1C9B0000 +#define __RW_MGR_CONTENT_ac_write_bank_1_col_1 0x1C9B0008 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_0 0x1C980000 +#define __RW_MGR_CONTENT_ac_read_bank_1_0 0x135B0000 +#define __RW_MGR_CONTENT_ac_mrs1_mirr 0x100A0024 +#define __RW_MGR_CONTENT_ac_read_bank_1_1 0x135B0008 +#define __RW_MGR_CONTENT_ac_des_odt_1 0x38780000 +#define __RW_MGR_CONTENT_ac_mrs0_dll_reset_mirr 0x100804C8 +#define __RW_MGR_CONTENT_ac_zqcl 0x10380400 +#define __RW_MGR_CONTENT_ac_write_predata 0x38F80000 +#define __RW_MGR_CONTENT_ac_mrs0_user_mirr 0x10080449 +#define __RW_MGR_CONTENT_ac_ref 0x10480000 +#define __RW_MGR_CONTENT_ac_nop 0x30780000 +#define __RW_MGR_CONTENT_ac_rdimm 0x10780000 +#define __RW_MGR_CONTENT_ac_mrs2_mirr 0x10090008 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata 0x18180000 +#define __RW_MGR_CONTENT_ac_read_en 0x33780000 +#define __RW_MGR_CONTENT_ac_mrs3_mirr 0x100B0000 +#define __RW_MGR_CONTENT_ac_mrs2 0x100A0010 + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Intel Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#define __RW_MGR_READ_B2B_WAIT2 0x6B +#define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define __RW_MGR_REFRESH_ALL 0x14 +#define __RW_MGR_ZQCL 0x06 +#define __RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define __RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define __RW_MGR_ACTIVATE_0_AND_1 0x0D +#define __RW_MGR_MRS2_MIRR 0x0A +#define __RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define __RW_MGR_ACTIVATE_1 0x0F +#define __RW_MGR_MRS2 0x04 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define __RW_MGR_MRS1 0x03 +#define __RW_MGR_IDLE_LOOP1 0x7B +#define __RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define __RW_MGR_MRS3 0x05 +#define __RW_MGR_IDLE_LOOP2 0x7A +#define __RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define __RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define __RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define __RW_MGR_RDIMM_CMD 0x79 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define __RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define __RW_MGR_GUARANTEED_READ_CONT 0x54 +#define __RW_MGR_REFRESH_DELAY 0x15 +#define __RW_MGR_MRS3_MIRR 0x0B +#define __RW_MGR_IDLE 0x00 +#define __RW_MGR_READ_B2B 0x59 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define __RW_MGR_GUARANTEED_WRITE 0x18 +#define __RW_MGR_PRECHARGE_ALL 0x12 +#define __RW_MGR_SGLE_READ 0x7D +#define __RW_MGR_MRS0_USER_MIRR 0x0C +#define __RW_MGR_RETURN 0x01 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define __RW_MGR_MRS0_USER 0x07 +#define __RW_MGR_GUARANTEED_READ 0x4C +#define __RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define __RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define __RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define __RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define __RW_MGR_MRS0_DLL_RESET 0x02 +#define __RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define __RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define __RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define __RW_MGR_MRS1_MIRR 0x09 +#define __RW_MGR_READ_B2B_WAIT1 0x61 +#define __RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680 +#define __RW_MGR_CONTENT_REFRESH_ALL 0x000980 +#define __RW_MGR_CONTENT_ZQCL 0x008380 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00 +#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800 +#define __RW_MGR_CONTENT_MRS2_MIRR 0x008580 +#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680 +#define __RW_MGR_CONTENT_ACTIVATE_1 0x000880 +#define __RW_MGR_CONTENT_MRS2 0x008280 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00 +#define __RW_MGR_CONTENT_MRS1 0x008200 +#define __RW_MGR_CONTENT_IDLE_LOOP1 0x00A680 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8 +#define __RW_MGR_CONTENT_MRS3 0x008300 +#define __RW_MGR_CONTENT_IDLE_LOOP2 0x008680 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88 +#define __RW_MGR_CONTENT_RDIMM_CMD 0x009180 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0 +#define __RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168 +#define __RW_MGR_CONTENT_REFRESH_DELAY 0x00A680 +#define __RW_MGR_CONTENT_MRS3_MIRR 0x008600 +#define __RW_MGR_CONTENT_IDLE 0x080000 +#define __RW_MGR_CONTENT_READ_B2B 0x040E88 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68 +#define __RW_MGR_CONTENT_PRECHARGE_ALL 0x000900 +#define __RW_MGR_CONTENT_SGLE_READ 0x040F08 +#define __RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400 +#define __RW_MGR_CONTENT_RETURN 0x080680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80 +#define __RW_MGR_CONTENT_MRS0_USER 0x008100 +#define __RW_MGR_CONTENT_GUARANTEED_READ 0x001168 +#define __RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480 +#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080 +#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00 +#define __RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180 +#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80 +#define __RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158 +#define __RW_MGR_CONTENT_MRS1_MIRR 0x008500 +#define __RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680 diff --git a/arch/arm/boards/terasic-de10-nano/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-de10-nano/sequencer_auto_ac_init.c new file mode 100644 index 0000000000..05f1609674 --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/sequencer_auto_ac_init.c @@ -0,0 +1,67 @@ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Intel Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +static const uint32_t ac_rom_init_size = 36; +static const uint32_t ac_rom_init[36] = { + 0x20700000, + 0x20780000, + 0x10080431, + 0x10080530, + 0x10090044, + 0x100a0010, + 0x100b0000, + 0x10380400, + 0x10080449, + 0x100804c8, + 0x100a0024, + 0x10090008, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; diff --git a/arch/arm/boards/terasic-de10-nano/sequencer_auto_inst_init.c b/arch/arm/boards/terasic-de10-nano/sequencer_auto_inst_init.c new file mode 100644 index 0000000000..2ca79c65a5 --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/sequencer_auto_inst_init.c @@ -0,0 +1,158 @@ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Intel Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +static const uint32_t inst_rom_init_size = 127; +static const uint32_t inst_rom_init[127] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; diff --git a/arch/arm/boards/terasic-de10-nano/sequencer_defines.h b/arch/arm/boards/terasic-de10-nano/sequencer_defines.h new file mode 100644 index 0000000000..98d0475cbd --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/sequencer_defines.h @@ -0,0 +1,165 @@ +/* +Copyright (C) 2016 Intel Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#ifndef _SEQUENCER_DEFINES_H_ +#define _SEQUENCER_DEFINES_H_ + +#define AC_ROM_MR1_MIRR 0000000100100 +#define AC_ROM_MR1_OCD_ENABLE +#define AC_ROM_MR2_MIRR 0000000001000 +#define AC_ROM_MR3_MIRR 0000000000000 +#define AC_ROM_MR0_CALIB +#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000 +#define AC_ROM_MR0_DLL_RESET 0010100110000 +#define AC_ROM_MR0_MIRR 0010001001001 +#define AC_ROM_MR0 0010000110001 +#define AC_ROM_MR1 0000001000100 +#define AC_ROM_MR2 0000000010000 +#define AC_ROM_MR3 0000000000000 +#define AC_ROM_USER_ADD_0 0_0000_0000_0000 +#define AC_ROM_USER_ADD_1 0_0000_0000_1000 +#define AFI_CLK_FREQ 401 +#define AFI_RATE_RATIO 1 +#define AP_MODE 0 +#define ARRIAVGZ 0 +#define ARRIAV 0 +#define AVL_CLK_FREQ 67 +#define BFM_MODE 0 +#define BURST2 0 +#define CALIBRATE_BIT_SLIPS 0 +#define CALIB_LFIFO_OFFSET 8 +#define CALIB_VFIFO_OFFSET 6 +#define CYCLONEV 1 +#define DDR2 0 +#define DDR3 1 +#define DDRX 1 +#define DM_PINS_ENABLED 1 +#define ENABLE_ASSERT 0 +#define ENABLE_BRINGUP_DEBUGGING 0 +#define ENABLE_DELAY_CHAIN_WRITE 0 +#define ENABLE_DQS_IN_CENTERING 1 +#define ENABLE_DQS_OUT_CENTERING 0 +#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0 +#define ENABLE_INST_ROM_WRITE 1 +#define ENABLE_MARGIN_REPORT_GEN 0 +#define ENABLE_NON_DESTRUCTIVE_CALIB 0 +#define ENABLE_NON_DES_CAL_TEST 0 +#define ENABLE_NON_DES_CAL 0 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define ENABLE_TCL_DEBUG 0 +#define FAKE_CAL_FAIL 0 +#define FIX_READ_LATENCY 8 +#define FULL_RATE 1 +#define GUARANTEED_READ_BRINGUP_TEST 0 +#define HALF_RATE 0 +#define HARD_PHY 1 +#define HARD_VFIFO 1 +#define HCX_COMPAT_MODE 0 +#define HHP_HPS_SIMULATION 0 +#define HHP_HPS_VERIFICATION 0 +#define HHP_HPS 1 +#define HPS_HW 1 +#define HR_DDIO_OUT_HAS_THREE_REGS 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DM_OUT_RESERVE 0 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_DQ_OUT_RESERVE 0 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define LPDDR1 0 +#define LPDDR2 0 +#define LRDIMM 0 +#define MARGIN_VARIATION_TEST 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define MEM_ADDR_WIDTH 13 +#define MRS_MIRROR_PING_PONG_ATSO 0 +#define MULTIPLE_AFI_WLAT 0 +#define NON_DES_CAL 0 +#define NUM_SHADOW_REGS 1 +#define QDRII 0 +#define QUARTER_RATE 0 +#define RDIMM 0 +#define READ_AFTER_WRITE_CALIBRATION 1 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504c9 +#define RLDRAM3 0 +#define RLDRAMII 0 +#define RLDRAMX 0 +#define RUNTIME_CAL_REPORT 0 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_ADDRESS_WIDTH 15 +#define RW_MGR_MEM_BANK_WIDTH 3 +#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1 +#define RW_MGR_MEM_CLK_EN_WIDTH 1 +#define RW_MGR_MEM_CONTROL_WIDTH 1 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_ODT_WIDTH 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_MR0_BL 1 +#define RW_MGR_MR0_CAS_LATENCY 3 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_WRITE_TO_DEBUG_READ 1.0 +#define SET_FIX_READ_LATENCY_ENABLE 0 +#define SKEW_CALIBRATION 0 +#define SKIP_PTAP_0_DQS_EN_CAL 1 +#define STATIC_FULL_CALIBRATION 1 +#define STATIC_SIM_FILESET 0 +#define STATIC_SKIP_MEM_INIT 0 +#define STRATIXV 0 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TINIT_CNTR0_VAL 99 +#define TRACKING_ERROR_TEST 0 +#define TRACKING_WATCH_TEST 0 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 +#define TRESET_CNTR0_VAL 99 +#define USE_DQS_TRACKING 1 +#define USE_SHADOW_REGS 0 +#define USE_USER_RDIMM_VALUE 0 + +#endif /* _SEQUENCER_DEFINES_H_ */ diff --git a/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2.imxcfg b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-256.imxcfg index ea327b2630..ea327b2630 100644 --- a/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2.imxcfg +++ b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-256.imxcfg diff --git a/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-512.imxcfg b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-512.imxcfg new file mode 100644 index 0000000000..d438a665f1 --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-512.imxcfg @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +loadaddr 0x80000000 +soc imx6 +ivtofs 0x400 + +/* Enable all clocks */ +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff + +/* IOMUX */ +/* DDR IO type */ +wm 32 0x020E04B4 0x000C0000 +wm 32 0x020E04AC 0x00000000 +/* Clock */ +wm 32 0x020E027C 0x00000028 +/* Control */ +wm 32 0x020E0250 0x00000028 +wm 32 0x020E024C 0x00000028 +wm 32 0x020E0490 0x00000028 +wm 32 0x020E0288 0x00000028 +wm 32 0x020E0270 0x00000000 +wm 32 0x020E0260 0x00000028 +wm 32 0x020E0264 0x00000028 +wm 32 0x020E04A0 0x00000028 +/* Data strobe */ +wm 32 0x020E0494 0x00020000 +wm 32 0x020E0280 0x00000028 +wm 32 0x020E0284 0x00000028 +/* Data */ +wm 32 0x020E04B0 0x00020000 +wm 32 0x020E0498 0x00000028 +wm 32 0x020E04A4 0x00000028 +wm 32 0x020E0244 0x00000028 +wm 32 0x020E0248 0x00000028 + +/* DDR Controller registers */ +wm 32 0x021B001C 0x00008000 +wm 32 0x021B0800 0xA1390003 +/* Calibration values */ +wm 32 0x021B080C 0x00090000 +wm 32 0x021B083C 0x01580158 +wm 32 0x021B0848 0x40405050 +wm 32 0x021B0850 0x4040524C +wm 32 0x021B081C 0x33333333 +wm 32 0x021B0820 0x33333333 +wm 32 0x021B082C 0xf3333333 +wm 32 0x021B0830 0xf3333333 +/* END of calibration values */ +wm 32 0x021B08C0 0x00921012 +wm 32 0x021B08b8 0x00000800 + +/* MMDC init */ +wm 32 0x021B0004 0x0002002D +wm 32 0x021B0008 0x1b333030 +wm 32 0x021B000C 0x676B52F3 +wm 32 0x021B0010 0xB66D0B63 +wm 32 0x021B0014 0x01FF00DB +/* Consider reducing RALAT (currently set to 5) */ +wm 32 0x021B0018 0x00211740 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B002C 0x000026D2 +wm 32 0x021B0030 0x006B1023 +wm 32 0x021B0040 0x0000004F +wm 32 0x021B0000 0x84180000 + +/* Mode registers writes for CS0 */ +wm 32 0x021B001C 0x02008032 +wm 32 0x021B001C 0x00008033 +wm 32 0x021B001C 0x00048031 +wm 32 0x021B001C 0x15208030 +wm 32 0x021B001C 0x04008040 + +/* Final DDR setup */ +wm 32 0x021B0020 0x00007800 +wm 32 0x021B0818 0x00000227 +wm 32 0x021B0004 0x0002556D +wm 32 0x021B0404 0x00011006 +wm 32 0x021B001C 0x00000000 + +/* Disable TZASC bypass */ +wm 32 0x020E4024 0x00000001 + +#include <mach/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/webasto-ccbv2/lowlevel.c b/arch/arm/boards/webasto-ccbv2/lowlevel.c index 8529ea3735..32117b0a77 100644 --- a/arch/arm/boards/webasto-ccbv2/lowlevel.c +++ b/arch/arm/boards/webasto-ccbv2/lowlevel.c @@ -48,7 +48,7 @@ static void noinline start_ccbv2(u32 r0) */ if(IS_ENABLED(CONFIG_FIRMWARE_CCBV2_OPTEE) && !(r0 > MX6_MMDC_P0_BASE_ADDR - && r0 < MX6_MMDC_P0_BASE_ADDR + SZ_256M)) { + && r0 < MX6_MMDC_P0_BASE_ADDR + SZ_512M)) { get_builtin_firmware(ccbv2_optee_bin, &tee, &tee_size); memset((void *)OPTEE_OVERLAY_LOCATION, 0, 0x1000); @@ -59,7 +59,21 @@ static void noinline start_ccbv2(u32 r0) imx6ul_barebox_entry(__dtb_z_imx6ul_webasto_ccbv2_start); } -ENTRY_FUNCTION(start_imx6ul_ccbv2, r0, r1, r2) +ENTRY_FUNCTION(start_imx6ul_ccbv2_256m, r0, r1, r2) +{ + + imx6ul_cpu_lowlevel_init(); + + arm_setup_stack(0x00910000); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + start_ccbv2(r0); +} + +ENTRY_FUNCTION(start_imx6ul_ccbv2_512m, r0, r1, r2) { imx6ul_cpu_lowlevel_init(); diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig index 06d79f594d..e1e7b0f91e 100644 --- a/arch/arm/configs/imx_v8_defconfig +++ b/arch/arm/configs/imx_v8_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_IMX=y CONFIG_IMX_MULTI_BOARDS=y +CONFIG_MACH_PROTONIC_IMX8M=y CONFIG_MACH_ZII_IMX8MQ_DEV=y CONFIG_MACH_NXP_IMX8MM_EVK=y CONFIG_MACH_NXP_IMX8MP_EVK=y @@ -104,6 +105,7 @@ CONFIG_MTD_DATAFLASH=y CONFIG_MTD_M25P80=y CONFIG_USB_HOST=y CONFIG_USB_IMX_CHIPIDEA=y +CONFIG_USB_EHCI=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_SERIAL=y diff --git a/arch/arm/configs/socfpga-xload-2_defconfig b/arch/arm/configs/socfpga-xload-2_defconfig index 66cc777a7d..78b07aae5b 100644 --- a/arch/arm/configs/socfpga-xload-2_defconfig +++ b/arch/arm/configs/socfpga-xload-2_defconfig @@ -2,6 +2,7 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA_XLOAD=y CONFIG_MACH_SOCFPGA_ALTERA_SOCDK=y CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC=y +CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO=y CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y # CONFIG_ARM_EXCEPTIONS is not set diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig index 2509ad0b42..9f39285a9c 100644 --- a/arch/arm/configs/socfpga_defconfig +++ b/arch/arm/configs/socfpga_defconfig @@ -1,6 +1,7 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_MACH_SOCFPGA_EBV_SOCRATES=y CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC=y +CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO=y CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT=y CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a637869fb6..a07a3bf33f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -92,6 +92,7 @@ lwl-$(CONFIG_MACH_PROTONIC_IMX6) += \ imx6qp-prtwd3.dtb.o \ imx6qp-vicutp.dtb.o \ imx6ul-prti6g.dtb.o +lwl-$(CONFIG_MACH_PROTONIC_IMX8M) += imx8mm-prt8mm.dtb.o lwl-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o lwl-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o lwl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o @@ -100,12 +101,13 @@ lwl-$(CONFIG_MACH_RPI2) += bcm2836-rpi-2.dtb.o lwl-$(CONFIG_MACH_RPI3) += bcm2837-rpi-3.dtb.o lwl-$(CONFIG_MACH_RPI_CM3) += bcm2837-rpi-cm3.dtb.o lwl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o -lwl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o +lwl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o imx6qp-sabresd.dtb.o lwl-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o lwl-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o lwl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o lwl-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += socfpga_arria10_achilles.dtb.o lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o +lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += socfpga_cyclone5_de10_nano.dtb.o lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o lwl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o lwl-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o \ diff --git a/arch/arm/dts/imx6q-nitrogen6x.dts b/arch/arm/dts/imx6q-nitrogen6x.dts index e4a6a6c29e..14f7ba2190 100644 --- a/arch/arm/dts/imx6q-nitrogen6x.dts +++ b/arch/arm/dts/imx6q-nitrogen6x.dts @@ -14,3 +14,5 @@ #include <arm/imx6q-nitrogen6x.dts> #include "imx6q.dtsi" #include "imx6qdl-nitrogen6x.dtsi" + +/delete-node/ &{/memory@10000000}; diff --git a/arch/arm/dts/imx6qdl-prti6q-emmc.dtsi b/arch/arm/dts/imx6qdl-prti6q-emmc.dtsi index 4fc7bd6473..094b0b09d7 100644 --- a/arch/arm/dts/imx6qdl-prti6q-emmc.dtsi +++ b/arch/arm/dts/imx6qdl-prti6q-emmc.dtsi @@ -1,6 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT / { + aliases { + state = &state_emmc; + }; + chosen { stdout-path = &uart4; @@ -10,6 +14,70 @@ }; }; + state_emmc: state { + magic = <0x292D3A3C>; + compatible = "barebox,state"; + backend-type = "raw"; + backend = <&state_backend_emmc>; + backend-stridesize = <0x400>; + #address-cells = <1>; + #size-cells = <1>; + + bootstate { + #address-cells = <1>; + #size-cells = <1>; + + system0 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts { + reg = <0x0 0x4>; + type = "uint32"; + default = <3>; + }; + + priority { + reg = <0x4 0x4>; + type = "uint32"; + default = <21>; + }; + }; + + system1 { + #address-cells = <1>; + #size-cells = <1>; + + remaining_attempts { + reg = <0x10 0x4>; + type = "uint32"; + default = <3>; + }; + + priority { + reg = <0x14 0x4>; + type = "uint32"; + default = <20>; + }; + }; + + last_chosen { + reg = <0x20 0x4>; + type = "uint32"; + }; + }; + + blobs { + #address-cells = <1>; + #size-cells = <1>; + + data_partitions { + reg = <0x26 0x100>; + type = "string"; + }; + }; + }; + reserved-memory { #address-cells = <1>; #size-cells = <1>; @@ -42,7 +110,7 @@ reg = <0x40000 0x80000>; }; - partition@c0000 { + state_backend_emmc: partition@c0000 { label = "state"; reg = <0xc0000 0x40000>; }; diff --git a/arch/arm/dts/imx6qp-sabresd.dts b/arch/arm/dts/imx6qp-sabresd.dts new file mode 100644 index 0000000000..1fb20cb0b4 --- /dev/null +++ b/arch/arm/dts/imx6qp-sabresd.dts @@ -0,0 +1,42 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <arm/imx6qp-sabresd.dts> + +/ { + model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board"; + compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp"; + + chosen { + stdout-path = &uart1; + + environment { + compatible = "barebox,environment"; + device-path = &environment_usdhc3; + }; + }; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + environment_usdhc3: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; diff --git a/arch/arm/dts/imx8mm-prt8mm.dts b/arch/arm/dts/imx8mm-prt8mm.dts new file mode 100644 index 0000000000..bdcdd08062 --- /dev/null +++ b/arch/arm/dts/imx8mm-prt8mm.dts @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Protonic Holland + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include <arm64/freescale/imx8mm.dtsi> + +/ { + model = "Protonic PRT8MM"; + compatible = "prt,prt8mm", "fsl,imx8mm"; + + chosen { + stdout-path = &uart4; + + environment-sd { + compatible = "barebox,environment"; + device-path = &part_env_sd; + status = "disabled"; + }; + environment-emmc { + compatible = "barebox,environment"; + device-path = &part_env_emmc; + status = "disabled"; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + dr_mode = "host"; + power-active-high; + over-current-active-low; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <100000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + part_env_sd: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + part_env_emmc: partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c3 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0d4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x000 + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x000 + >; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts new file mode 100644 index 0000000000..da6da02381 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/* + * socfpga_cyclone5_de10_nano.dts - Device Tree File for Terasic DE10-Nano + * Copyright (C) 2021 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com> + */ + +#include <arm/socfpga_cyclone5.dtsi> +#include "socfpga.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Terasic DE10-Nano"; + compatible = "terasic,de10-nano", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = &uart0; + + environment { + compatible = "barebox,environment"; + device-path = &mmc, "partname:1"; + file-path = "barebox.env"; + }; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + ethernet0 = &gmac1; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + hps_hkey0 { + label = "HPS_KEY"; + gpios = <&portb 25 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 24 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + + max-frame-size = <3800>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + adxl345: adxl345@53 { + compatible = "adi,adxl345"; + reg = <0x53>; + + interrupt-parent = <&portc>; + interrupts = <3 2>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/lib32/module.c b/arch/arm/lib32/module.c index 5073675180..7214e3c73c 100644 --- a/arch/arm/lib32/module.c +++ b/arch/arm/lib32/module.c @@ -38,7 +38,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, sym = ((Elf32_Sym *)symsec->sh_addr) + offset; - if (rel->r_offset < 0 || rel->r_offset > dstsec->sh_size - sizeof(u32)) { + if (rel->r_offset > dstsec->sh_size - sizeof(u32)) { printf("%s: out of bounds relocation, " "section %u reloc %u offset %d size %d\n", module->name, relindex, i, rel->r_offset, diff --git a/arch/arm/mach-at91/xload-mmc.c b/arch/arm/mach-at91/xload-mmc.c index 8d4f653d1e..1b641f3a47 100644 --- a/arch/arm/mach-at91/xload-mmc.c +++ b/arch/arm/mach-at91/xload-mmc.c @@ -116,7 +116,7 @@ void __noreturn sama5d3_atmci_start_image(u32 boot_src, unsigned int clock, instance = &sama5d3_atmci_instances[boot_src]; - sama5d3_pmc_enable_periph_clock(SAMA5D2_ID_PIOD); + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_PIOD); for (pin = instance->pins; *pin >= 0; pin++) { at91_mux_pio3_pin(IOMEM(SAMA5D3_BASE_PIOD), pin_to_mask(*pin), instance->periph, 0); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 5f5b762ce5..fa373f9a7c 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -345,6 +345,16 @@ config MACH_PROTONIC_IMX6 select ARCH_IMX6UL select ARM_USE_COMPRESSED_DTB +config MACH_PROTONIC_IMX8M + bool "Protonic-Holland i.MX8Mx based boards" + select ARCH_IMX8MM + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MM_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select IMX8M_DRAM + select USB_GADGET_DRIVER_ARC_PBL + config MACH_KONTRON_SAMX6I bool "Kontron sAMX6i" select ARCH_IMX6 diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c index e9b5a49443..2b66bbf71e 100644 --- a/arch/arm/mach-imx/boot.c +++ b/arch/arm/mach-imx/boot.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <bootsource.h> diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c index 9d86353e22..a034b5a9a5 100644 --- a/arch/arm/mach-imx/cpu_init.c +++ b/arch/arm/mach-imx/cpu_init.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2014 Lucas Stach, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Lucas Stach, Pengutronix #include <common.h> #include <asm/barebox-arm-head.h> diff --git a/arch/arm/mach-imx/esdctl-v4.c b/arch/arm/mach-imx/esdctl-v4.c index d9f6e919a1..14a967d521 100644 --- a/arch/arm/mach-imx/esdctl-v4.c +++ b/arch/arm/mach-imx/esdctl-v4.c @@ -1,17 +1,7 @@ -/* - * esdctl-v4.c - i.MX sdram controller functions for i.MX53 - * - * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + +/* esdctl-v4.c - i.MX sdram controller functions for i.MX53 */ #include <common.h> #include <io.h> diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index 135a16d111..f297cd35d5 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -1,17 +1,7 @@ -/* - * esdctl.c - i.MX sdram controller functions - * - * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + +/* esdctl.c - i.MX sdram controller functions */ #include <common.h> #include <io.h> diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c index 893bfdb77f..92dcaeaaf8 100644 --- a/arch/arm/mach-imx/external-nand-boot.c +++ b/arch/arm/mach-imx/external-nand-boot.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <init.h> diff --git a/arch/arm/mach-imx/iim.c b/arch/arm/mach-imx/iim.c index b60c5de7e1..40b9b00cec 100644 --- a/arch/arm/mach-imx/iim.c +++ b/arch/arm/mach-imx/iim.c @@ -1,19 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2010 Baruch Siach <baruch@tkos.co.il>, Orex Computed Radiography + /* * iim.c - i.MX IIM fusebox driver * * Provide an interface for programming and sensing the information that are * stored in on-chip fuse elements. This functionality is part of the IC * Identification Module (IIM), which is present on some i.MX CPUs. - * - * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>, - * Orex Computed Radiography - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <common.h> diff --git a/arch/arm/mach-imx/imx-bbu-external-nand.c b/arch/arm/mach-imx/imx-bbu-external-nand.c index 8aa4f152a1..392497e434 100644 --- a/arch/arm/mach-imx/imx-bbu-external-nand.c +++ b/arch/arm/mach-imx/imx-bbu-external-nand.c @@ -1,17 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + /* * imx-bbu-external-nand.c - i.MX specific update functions for external * nand boot - * - * Copyright (c) 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> @@ -39,7 +31,7 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_ uint32_t num_bb = 0, bbt = 0; loff_t offset = 0; int block = 0, len, now, blocksize; - void *image = data->image; + void *image = NULL; ret = stat(data->devicefile, &s); if (ret) @@ -55,6 +47,12 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_ if (ret) goto out; + image = memdup(data->image, data->len); + if (!image) { + ret = -ENOMEM; + goto out; + } + blocksize = meminfo.erasesize; size_need = data->len; @@ -172,6 +170,7 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_ out: close(fd); + free(image); return ret; } diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c index c6d427a46c..880f8b2496 100644 --- a/arch/arm/mach-imx/imx-bbu-internal.c +++ b/arch/arm/mach-imx/imx-bbu-internal.c @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + /* * imx-bbu-internal.c - i.MX specific update functions for internal boot - * - * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c index bd7e9ac423..0d2a5b2063 100644 --- a/arch/arm/mach-imx/imx.c +++ b/arch/arm/mach-imx/imx.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <of.h> diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c index 6a09b276c8..6cf95667c9 100644 --- a/arch/arm/mach-imx/imx1.c +++ b/arch/arm/mach-imx/imx1.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <init.h> diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c index 7a19ed3986..223a390c9c 100644 --- a/arch/arm/mach-imx/imx21.c +++ b/arch/arm/mach-imx/imx21.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <init.h> diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c index d27680e428..a855ff0714 100644 --- a/arch/arm/mach-imx/imx25.c +++ b/arch/arm/mach-imx/imx25.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <init.h> diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c index d4949babeb..97e6792d87 100644 --- a/arch/arm/mach-imx/imx27.c +++ b/arch/arm/mach-imx/imx27.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <mach/imx27-regs.h> diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c index 137c77a923..b524d0105e 100644 --- a/arch/arm/mach-imx/imx31.c +++ b/arch/arm/mach-imx/imx31.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <init.h> diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c index d37bdfda7b..c6ded7407d 100644 --- a/arch/arm/mach-imx/imx35.c +++ b/arch/arm/mach-imx/imx35.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/mach-imx/imx50.c b/arch/arm/mach-imx/imx50.c index b76e3794e3..20670a7446 100644 --- a/arch/arm/mach-imx/imx50.c +++ b/arch/arm/mach-imx/imx50.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <init.h> #include <common.h> diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c index 7404254bee..214a4031ec 100644 --- a/arch/arm/mach-imx/imx51.c +++ b/arch/arm/mach-imx/imx51.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <init.h> #include <common.h> diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c index f8e34a39da..3906a48917 100644 --- a/arch/arm/mach-imx/imx53.c +++ b/arch/arm/mach-imx/imx53.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <init.h> #include <common.h> diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c index 8f661e3dfe..00b8d30d69 100644 --- a/arch/arm/mach-imx/imx6-mmdc.c +++ b/arch/arm/mach-imx/imx6-mmdc.c @@ -1,19 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de + /* * i.MX6 DDR controller calibration functions * Based on Freescale code - * - * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> #include <io.h> diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index 6a9ea23c71..9ccb391384 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <abort.h> #include <init.h> diff --git a/arch/arm/mach-imx/imx7.c b/arch/arm/mach-imx/imx7.c index d875bf44f1..8f9d5034ab 100644 --- a/arch/arm/mach-imx/imx7.c +++ b/arch/arm/mach-imx/imx7.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <init.h> #include <common.h> diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index 350d203539..8672d5fe39 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <init.h> #include <common.h> diff --git a/arch/arm/mach-imx/nand.c b/arch/arm/mach-imx/nand.c index 7574fe80b2..718cada052 100644 --- a/arch/arm/mach-imx/nand.c +++ b/arch/arm/mach-imx/nand.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <mach/generic.h> diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index 73350d15e1..8272d5b720 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -1,11 +1,5 @@ -/* - * Copyright 2016 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2016 Sascha Hauer <s.hauer@pengutronix.de> #include <common.h> #include <init.h> diff --git a/arch/arm/mach-imx/vf610.c b/arch/arm/mach-imx/vf610.c index 2fbd6393ea..ccef9d48d9 100644 --- a/arch/arm/mach-imx/vf610.c +++ b/arch/arm/mach-imx/vf610.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <init.h> #include <common.h> diff --git a/arch/arm/mach-imx/xload-gpmi-nand.c b/arch/arm/mach-imx/xload-gpmi-nand.c index b3fd479cb4..3a4f331ce6 100644 --- a/arch/arm/mach-imx/xload-gpmi-nand.c +++ b/arch/arm/mach-imx/xload-gpmi-nand.c @@ -1,13 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only #define pr_fmt(fmt) "xload-gpmi-nand: " fmt @@ -111,14 +102,15 @@ static int mxs_dma_enable(struct mxs_dma_chan *pchan, struct apbh_dma *apbh = pchan->apbh; int channel_bit; int channel = pchan->channel; + unsigned long pdesc32 = (unsigned long)pdesc; if (apbh_dma_is_imx23(apbh)) { - writel((uint32_t)pdesc, + writel(pdesc32, apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX23(channel)); writel(1, apbh->regs + HW_APBHX_CHn_SEMA_MX23(channel)); channel_bit = channel + BP_APBH_CTRL0_CLKGATE_CHANNEL; } else { - writel((uint32_t)pdesc, + writel(pdesc32, apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX28(channel)); writel(1, apbh->regs + HW_APBHX_CHn_SEMA_MX28(channel)); channel_bit = channel; @@ -174,7 +166,7 @@ static int mxs_dma_run(struct mxs_dma_chan *pchan, struct mxs_dma_cmd *pdesc, /* chain descriptors */ for (i = 0; i < num - 1; i++) { - pdesc[i].next = (uint32_t)(&pdesc[i + 1]); + pdesc[i].next = (unsigned long)(&pdesc[i + 1]); pdesc[i].data |= DMACMD_CHAIN; } diff --git a/arch/arm/mach-imx/xload-imx-nand.c b/arch/arm/mach-imx/xload-imx-nand.c index ff54941a0c..3838d9164d 100644 --- a/arch/arm/mach-imx/xload-imx-nand.c +++ b/arch/arm/mach-imx/xload-imx-nand.c @@ -1,15 +1,5 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later + #define pr_fmt(fmt) "imx-nand-boot: " fmt #include <common.h> diff --git a/arch/arm/mach-layerscape/icid.c b/arch/arm/mach-layerscape/icid.c index aec57f4b3f..644401b181 100644 --- a/arch/arm/mach-layerscape/icid.c +++ b/arch/arm/mach-layerscape/icid.c @@ -305,8 +305,8 @@ static void fdt_fixup_fman_port_icid_by_compat(struct device_node *root, const char *compat) { struct device_node *np; - int ret; - u32 cell_index, icid; + int ret, icid; + u32 cell_index; for_each_compatible_node_from(np, root, NULL, compat) { ret = of_property_read_u32(np, "cell-index", &cell_index); diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h index e71ecbcd24..3c2143d600 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-clock.h +++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h @@ -24,6 +24,7 @@ #define MPUPLL_M_550 550 /* 125 * n */ #define MPUPLL_M_600 600 /* 125 * n */ #define MPUPLL_M_720 720 /* 125 * n */ +#define MPUPLL_M_800 800 #define MPUPLL_M2 1 diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 2da875cef0..ea2abebaa2 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -42,6 +42,10 @@ config MACH_SOCFPGA_TERASIC_DE0_NANO_SOC select ARCH_SOCFPGA_CYCLONE5 bool "Terasic DE0-NANO-SoC aka Atlas" +config MACH_SOCFPGA_TERASIC_DE10_NANO + select ARCH_SOCFPGA_CYCLONE5 + bool "Terasic DE10-NANO" + config MACH_SOCFPGA_TERASIC_SOCKIT select ARCH_SOCFPGA_CYCLONE5 bool "Terasic SoCKit" diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c index 6f137e300e..e52fd1ed87 100644 --- a/arch/arm/mach-socfpga/arria10-xload.c +++ b/arch/arm/mach-socfpga/arria10-xload.c @@ -136,7 +136,7 @@ static int a10_fpga_init(void *buf) { uint32_t stat, mask; uint32_t val; - uint32_t timeout; + int timeout; val = CFGWDTH_32 << A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SHIFT; a10_update_bits(A10_FPGAMGR_IMGCFG_CTL_02_OFST, diff --git a/arch/powerpc/mach-mpc85xx/fsl_law.c b/arch/powerpc/mach-mpc85xx/fsl_law.c index 2254c92544..e3c765f30f 100644 --- a/arch/powerpc/mach-mpc85xx/fsl_law.c +++ b/arch/powerpc/mach-mpc85xx/fsl_law.c @@ -81,7 +81,7 @@ static void fsl_set_next_law(phys_addr_t addr, enum law_size sz, static void fsl_set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { - u32 idx; + int idx; for (idx = (FSL_HW_NUM_LAWS - 1); idx >= 0; idx--) { if (fsl_is_free_law(idx)) { diff --git a/commands/clk.c b/commands/clk.c index 649a0a7cb2..2e21e9df58 100644 --- a/commands/clk.c +++ b/commands/clk.c @@ -82,6 +82,38 @@ BAREBOX_CMD_START(clk_set_rate) BAREBOX_CMD_COMPLETE(clk_name_complete) BAREBOX_CMD_END +static int do_clk_round_rate(int argc, char *argv[]) +{ + struct clk *clk; + unsigned long rate; + + if (argc != 3) + return COMMAND_ERROR_USAGE; + + clk = clk_lookup(argv[1]); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + rate = simple_strtoul(argv[2], NULL, 0); + + printf("%ld\n", clk_round_rate(clk, rate)); + + return 0; +} + +BAREBOX_CMD_HELP_START(clk_round_rate) +BAREBOX_CMD_HELP_TEXT("Set clock CLK to RATE") +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(clk_round_rate) + .cmd = do_clk_round_rate, + BAREBOX_CMD_DESC("set a clocks rate") + BAREBOX_CMD_OPTS("CLK HZ") + BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP) + BAREBOX_CMD_HELP(cmd_clk_round_rate_help) + BAREBOX_CMD_COMPLETE(clk_name_complete) +BAREBOX_CMD_END + static int do_clk_get_rate(int argc, char *argv[]) { int opt; diff --git a/common/Kconfig b/common/Kconfig index db7cc6713a..b18975850d 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1,8 +1,3 @@ -config DEFCONFIG_LIST - string - option defconfig_list - default "arch/$(SRCARCH)/configs/$(KBUILD_DEFCONFIG)" - config GREGORIAN_CALENDER bool @@ -333,7 +328,7 @@ config MODULES depends on HAS_MODULES depends on EXPERIMENTAL bool "module support" - option modules + modules help This option enables support for loadable modules via insmod. Module support is quite experimental at the moment. There is no convenient diff --git a/common/imx-bbu-nand-fcb.c b/common/imx-bbu-nand-fcb.c index 4e680a0a51..3b07d539ee 100644 --- a/common/imx-bbu-nand-fcb.c +++ b/common/imx-bbu-nand-fcb.c @@ -1263,16 +1263,17 @@ static int imx_bbu_nand_update(struct bbu_handler *handler, struct bbu_data *dat free(fcb); fcb = xzalloc(sizeof(*fcb)); - fcb->Firmware1_startingPage = imx_bbu_firmware_fcb_start_page(mtd, !used); - if (fcb->Firmware1_startingPage < 0) { - ret = fcb->Firmware1_startingPage; + + ret = imx_bbu_firmware_fcb_start_page(mtd, !used); + if (ret < 0) goto out; - } - fcb->Firmware2_startingPage = imx_bbu_firmware_fcb_start_page(mtd, used); - if (fcb->Firmware2_startingPage < 0) { - ret = fcb->Firmware2_startingPage; + fcb->Firmware1_startingPage = ret; + + ret = imx_bbu_firmware_fcb_start_page(mtd, used); + if (ret < 0) goto out; - } + fcb->Firmware2_startingPage = ret; + fcb->PagesInFirmware1 = fw_size / mtd->writesize; fcb->PagesInFirmware2 = fcb->PagesInFirmware1; diff --git a/drivers/aiodev/lm75.c b/drivers/aiodev/lm75.c index 8e5948f468..1900636555 100644 --- a/drivers/aiodev/lm75.c +++ b/drivers/aiodev/lm75.c @@ -182,6 +182,8 @@ static int lm75_probe(struct device_d *dev) clr_mask |= 1 << 5; /* not one-shot mode */ data->resolution = 12; break; + default: + return -EINVAL; } /* configure as specified */ diff --git a/drivers/base/regmap/Makefile b/drivers/base/regmap/Makefile index ab2387037d..b12b695311 100644 --- a/drivers/base/regmap/Makefile +++ b/drivers/base/regmap/Makefile @@ -1,2 +1,3 @@ obj-y += regmap.o obj-y += regmap-mmio.o +obj-$(CONFIG_I2C) += regmap-i2c.o diff --git a/drivers/base/regmap/regmap-i2c.c b/drivers/base/regmap/regmap-i2c.c new file mode 100644 index 0000000000..88b24ae6a8 --- /dev/null +++ b/drivers/base/regmap/regmap-i2c.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021, Ahmad Fatoum, Pengutronix + */ + +#include <i2c/i2c.h> +#include <regmap.h> + + +static int regmap_i2c_reg_read(void *client, unsigned int reg, unsigned int *val) +{ + u8 buf[1]; + int ret; + + ret = i2c_read_reg(client, reg, buf, 1); + if (ret != 1) + return ret; + + *val = buf[0]; + return 0; +} + +static int regmap_i2c_reg_write(void *client, unsigned int reg, unsigned int val) +{ + u8 buf[] = { val & 0xff }; + int ret; + + ret = i2c_write_reg(client, reg, buf, 1); + if (ret != 1) + return ret; + + return 0; +} + +static const struct regmap_bus regmap_regmap_i2c_bus = { + .reg_write = regmap_i2c_reg_write, + .reg_read = regmap_i2c_reg_read, +}; + +struct regmap *regmap_init_i2c(struct i2c_client *client, + const struct regmap_config *config) +{ + return regmap_init(&client->dev, ®map_regmap_i2c_bus, client, config); +} diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index 6613670263..1af0c15a7b 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -132,6 +132,11 @@ struct regmap *dev_get_regmap(struct device_d *dev, const char *name) return ERR_PTR(-ENOENT); } +struct device_d *regmap_get_device(struct regmap *map) +{ + return map->dev; +} + /* * regmap_write - write a register in a map * diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c index 47bff32fe8..e9a30b0516 100644 --- a/drivers/clk/at91/clk-audio-pll.c +++ b/drivers/clk/at91/clk-audio-pll.c @@ -57,7 +57,7 @@ #define AUDIO_PLL_FOUT_MAX 700000000UL struct clk_audio_frac { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; u32 fracr; u8 nd; @@ -65,7 +65,7 @@ struct clk_audio_frac { }; struct clk_audio_pad { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; u8 qdaudio; u8 div; @@ -73,19 +73,19 @@ struct clk_audio_pad { }; struct clk_audio_pmc { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; u8 qdpmc; const char *parent_name; }; -#define to_clk_audio_frac(clk) container_of(clk, struct clk_audio_frac, clk) -#define to_clk_audio_pad(clk) container_of(clk, struct clk_audio_pad, clk) -#define to_clk_audio_pmc(clk) container_of(clk, struct clk_audio_pmc, clk) +#define to_clk_audio_frac(_hw) container_of(_hw, struct clk_audio_frac, hw) +#define to_clk_audio_pad(_hw) container_of(_hw, struct clk_audio_pad, hw) +#define to_clk_audio_pmc(_hw) container_of(_hw, struct clk_audio_pmc, hw) -static int clk_audio_pll_frac_enable(struct clk *clk) +static int clk_audio_pll_frac_enable(struct clk_hw *hw) { - struct clk_audio_frac *frac = to_clk_audio_frac(clk); + struct clk_audio_frac *frac = to_clk_audio_frac(hw); regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, AT91_PMC_AUDIO_PLL_RESETN, 0); @@ -108,9 +108,9 @@ static int clk_audio_pll_frac_enable(struct clk *clk) return 0; } -static int clk_audio_pll_pad_enable(struct clk *clk) +static int clk_audio_pll_pad_enable(struct clk_hw *hw) { - struct clk_audio_pad *apad_ck = to_clk_audio_pad(clk); + struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL1, AT91_PMC_AUDIO_PLL_QDPAD_MASK, @@ -121,9 +121,9 @@ static int clk_audio_pll_pad_enable(struct clk *clk) return 0; } -static int clk_audio_pll_pmc_enable(struct clk *clk) +static int clk_audio_pll_pmc_enable(struct clk_hw *hw) { - struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(clk); + struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0, AT91_PMC_AUDIO_PLL_PMCEN | @@ -133,9 +133,9 @@ static int clk_audio_pll_pmc_enable(struct clk *clk) return 0; } -static void clk_audio_pll_frac_disable(struct clk *clk) +static void clk_audio_pll_frac_disable(struct clk_hw *hw) { - struct clk_audio_frac *frac = to_clk_audio_frac(clk); + struct clk_audio_frac *frac = to_clk_audio_frac(hw); regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, AT91_PMC_AUDIO_PLL_PLLEN, 0); @@ -144,17 +144,17 @@ static void clk_audio_pll_frac_disable(struct clk *clk) AT91_PMC_AUDIO_PLL_RESETN, 0); } -static void clk_audio_pll_pad_disable(struct clk *clk) +static void clk_audio_pll_pad_disable(struct clk_hw *hw) { - struct clk_audio_pad *apad_ck = to_clk_audio_pad(clk); + struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0, AT91_PMC_AUDIO_PLL_PADEN, 0); } -static void clk_audio_pll_pmc_disable(struct clk *clk) +static void clk_audio_pll_pmc_disable(struct clk_hw *hw) { - struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(clk); + struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0, AT91_PMC_AUDIO_PLL_PMCEN, 0); @@ -174,10 +174,10 @@ static unsigned long clk_audio_pll_fout(unsigned long parent_rate, return parent_rate * (nd + 1) + fr; } -static unsigned long clk_audio_pll_frac_recalc_rate(struct clk *clk, +static unsigned long clk_audio_pll_frac_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_audio_frac *frac = to_clk_audio_frac(clk); + struct clk_audio_frac *frac = to_clk_audio_frac(hw); unsigned long fout; fout = clk_audio_pll_fout(parent_rate, frac->nd, frac->fracr); @@ -188,10 +188,10 @@ static unsigned long clk_audio_pll_frac_recalc_rate(struct clk *clk, return fout; } -static unsigned long clk_audio_pll_pad_recalc_rate(struct clk *clk, +static unsigned long clk_audio_pll_pad_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_audio_pad *apad_ck = to_clk_audio_pad(clk); + struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); unsigned long apad_rate = 0; if (apad_ck->qdaudio && apad_ck->div) @@ -203,10 +203,10 @@ static unsigned long clk_audio_pll_pad_recalc_rate(struct clk *clk, return apad_rate; } -static unsigned long clk_audio_pll_pmc_recalc_rate(struct clk *clk, +static unsigned long clk_audio_pll_pmc_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(clk); + struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); unsigned long apmc_rate = 0; apmc_rate = parent_rate / (apmc_ck->qdpmc + 1); @@ -245,10 +245,10 @@ static int clk_audio_pll_frac_compute_frac(unsigned long rate, return 0; } -static long clk_audio_pll_pad_round_rate(struct clk *clk, unsigned long rate, +static long clk_audio_pll_pad_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - struct clk *pclk = clk_get_parent(clk); + struct clk *pclk = clk_get_parent(clk_hw_to_clk(hw)); long best_rate = -EINVAL; unsigned long best_parent_rate; unsigned long tmp_qd; @@ -296,9 +296,10 @@ static long clk_audio_pll_pad_round_rate(struct clk *clk, unsigned long rate, return best_rate; } -static long clk_audio_pll_pmc_round_rate(struct clk *clk, unsigned long rate, +static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { + struct clk *clk = clk_hw_to_clk(hw); struct clk *pclk = clk_get_parent(clk); long best_rate = -EINVAL; unsigned long best_parent_rate = 0; @@ -336,10 +337,10 @@ static long clk_audio_pll_pmc_round_rate(struct clk *clk, unsigned long rate, return best_rate; } -static int clk_audio_pll_frac_set_rate(struct clk *clk, unsigned long rate, +static int clk_audio_pll_frac_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_audio_frac *frac = to_clk_audio_frac(clk); + struct clk_audio_frac *frac = to_clk_audio_frac(hw); unsigned long fracr, nd; int ret; @@ -359,10 +360,10 @@ static int clk_audio_pll_frac_set_rate(struct clk *clk, unsigned long rate, return 0; } -static int clk_audio_pll_pad_set_rate(struct clk *clk, unsigned long rate, +static int clk_audio_pll_pad_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_audio_pad *apad_ck = to_clk_audio_pad(clk); + struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); u8 tmp_div; pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__, @@ -383,10 +384,10 @@ static int clk_audio_pll_pad_set_rate(struct clk *clk, unsigned long rate, return 0; } -static int clk_audio_pll_pmc_set_rate(struct clk *clk, unsigned long rate, +static int clk_audio_pll_pmc_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(clk); + struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); if (!rate) return -EINVAL; @@ -433,22 +434,22 @@ at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name, if (!frac_ck) return ERR_PTR(-ENOMEM); - frac_ck->clk.name = name; - frac_ck->clk.ops = &audio_pll_frac_ops; + frac_ck->hw.clk.name = name; + frac_ck->hw.clk.ops = &audio_pll_frac_ops; frac_ck->parent_name = parent_name; - frac_ck->clk.parent_names = &frac_ck->parent_name; - frac_ck->clk.num_parents = 1; + frac_ck->hw.clk.parent_names = &frac_ck->parent_name; + frac_ck->hw.clk.num_parents = 1; /* frac_ck->clk.flags = CLK_SET_RATE_GATE; */ frac_ck->regmap = regmap; - ret = clk_register(&frac_ck->clk); + ret = bclk_register(&frac_ck->hw.clk); if (ret) { kfree(frac_ck); return ERR_PTR(ret); } - return &frac_ck->clk; + return &frac_ck->hw.clk; } struct clk * __init @@ -462,23 +463,23 @@ at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name, if (!apad_ck) return ERR_PTR(-ENOMEM); - apad_ck->clk.name = name; - apad_ck->clk.ops = &audio_pll_pad_ops; + apad_ck->hw.clk.name = name; + apad_ck->hw.clk.ops = &audio_pll_pad_ops; apad_ck->parent_name = parent_name; - apad_ck->clk.parent_names = &apad_ck->parent_name; - apad_ck->clk.num_parents = 1; + apad_ck->hw.clk.parent_names = &apad_ck->parent_name; + apad_ck->hw.clk.num_parents = 1; /* apad_ck->clk.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT; */ apad_ck->regmap = regmap; - ret = clk_register(&apad_ck->clk); + ret = bclk_register(&apad_ck->hw.clk); if (ret) { kfree(apad_ck); return ERR_PTR(ret); } - return &apad_ck->clk; + return &apad_ck->hw.clk; } struct clk * __init @@ -492,21 +493,21 @@ at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name, if (!apmc_ck) return ERR_PTR(-ENOMEM); - apmc_ck->clk.name = name; - apmc_ck->clk.ops = &audio_pll_pmc_ops; + apmc_ck->hw.clk.name = name; + apmc_ck->hw.clk.ops = &audio_pll_pmc_ops; apmc_ck->parent_name = parent_name; - apmc_ck->clk.parent_names = &apmc_ck->parent_name; - apmc_ck->clk.num_parents = 1; + apmc_ck->hw.clk.parent_names = &apmc_ck->parent_name; + apmc_ck->hw.clk.num_parents = 1; /* apmc_ck.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT; */ apmc_ck->regmap = regmap; - ret = clk_register(&apmc_ck->clk); + ret = bclk_register(&apmc_ck->hw.clk); if (ret) { kfree(apmc_ck); return ERR_PTR(ret); } - return &apmc_ck->clk; + return &apmc_ck->hw.clk; } diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index 56b800facb..628ff407d9 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -23,7 +23,7 @@ #define GCK_INDEX_DT_AUDIO_PLL 5 struct clk_generated { - struct clk hw; + struct clk_hw hw; struct regmap *regmap; struct clk_range range; u32 id; @@ -33,10 +33,10 @@ struct clk_generated { bool audio_pll_allowed; }; -#define to_clk_generated(hw) \ - container_of(hw, struct clk_generated, hw) +#define to_clk_generated(_hw) \ + container_of(_hw, struct clk_generated, hw) -static int clk_generated_enable(struct clk *hw) +static int clk_generated_enable(struct clk_hw *hw) { struct clk_generated *gck = to_clk_generated(hw); @@ -55,7 +55,7 @@ static int clk_generated_enable(struct clk *hw) return 0; } -static void clk_generated_disable(struct clk *hw) +static void clk_generated_disable(struct clk_hw *hw) { struct clk_generated *gck = to_clk_generated(hw); @@ -66,7 +66,7 @@ static void clk_generated_disable(struct clk *hw) gck->layout->cmd); } -static int clk_generated_is_enabled(struct clk *hw) +static int clk_generated_is_enabled(struct clk_hw *hw) { struct clk_generated *gck = to_clk_generated(hw); unsigned int status; @@ -79,7 +79,7 @@ static int clk_generated_is_enabled(struct clk *hw) } static unsigned long -clk_generated_recalc_rate(struct clk *hw, +clk_generated_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_generated *gck = to_clk_generated(hw); @@ -88,18 +88,18 @@ clk_generated_recalc_rate(struct clk *hw, } /* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */ -static int clk_generated_set_parent(struct clk *hw, u8 index) +static int clk_generated_set_parent(struct clk_hw *hw, u8 index) { struct clk_generated *gck = to_clk_generated(hw); - if (index >= clk_get_num_parents(hw)) + if (index >= clk_get_num_parents(clk_hw_to_clk(hw))) return -EINVAL; gck->parent_id = index; return 0; } -static int clk_generated_get_parent(struct clk *hw) +static int clk_generated_get_parent(struct clk_hw *hw) { struct clk_generated *gck = to_clk_generated(hw); @@ -107,7 +107,7 @@ static int clk_generated_get_parent(struct clk *hw) } /* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */ -static int clk_generated_set_rate(struct clk *hw, +static int clk_generated_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -168,7 +168,7 @@ at91_clk_register_generated(struct regmap *regmap, { size_t parents_array_size; struct clk_generated *gck; - struct clk *hw; + struct clk *clk; int ret; gck = kzalloc(sizeof(*gck), GFP_KERNEL); @@ -176,12 +176,12 @@ at91_clk_register_generated(struct regmap *regmap, return ERR_PTR(-ENOMEM); gck->id = id; - gck->hw.name = name; - gck->hw.ops = &generated_ops; + gck->hw.clk.name = name; + gck->hw.clk.ops = &generated_ops; - parents_array_size = num_parents * sizeof(gck->hw.parent_names[0]); - gck->hw.parent_names = xmemdup(parent_names, parents_array_size); - gck->hw.num_parents = num_parents; + parents_array_size = num_parents * sizeof(gck->hw.clk.parent_names[0]); + gck->hw.clk.parent_names = xmemdup(parent_names, parents_array_size); + gck->hw.clk.num_parents = num_parents; /* gck->hw.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_PARENT; */ gck->regmap = regmap; @@ -190,14 +190,14 @@ at91_clk_register_generated(struct regmap *regmap, gck->layout = layout; clk_generated_startup(gck); - hw = &gck->hw; - ret = clk_register(&gck->hw); + clk = &gck->hw.clk; + ret = bclk_register(&gck->hw.clk); if (ret) { kfree(gck); - hw = ERR_PTR(ret); + clk = ERR_PTR(ret); } else { pmc_register_id(id); } - return hw; + return clk; } diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c index 6052886cca..b2c5007cf7 100644 --- a/drivers/clk/at91/clk-h32mx.c +++ b/drivers/clk/at91/clk-h32mx.c @@ -20,14 +20,14 @@ #define H32MX_MAX_FREQ 90000000 struct clk_sama5d4_h32mx { - struct clk hw; + struct clk_hw hw; struct regmap *regmap; const char *parent; }; -#define to_clk_sama5d4_h32mx(hw) container_of(hw, struct clk_sama5d4_h32mx, hw) +#define to_clk_sama5d4_h32mx(_hw) container_of(_hw, struct clk_sama5d4_h32mx, hw) -static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk *hw, +static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw); @@ -42,7 +42,7 @@ static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk *hw, return parent_rate; } -static long clk_sama5d4_h32mx_round_rate(struct clk *hw, unsigned long rate, +static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { unsigned long div; @@ -59,7 +59,7 @@ static long clk_sama5d4_h32mx_round_rate(struct clk *hw, unsigned long rate, return *parent_rate; } -static int clk_sama5d4_h32mx_set_rate(struct clk *hw, unsigned long rate, +static int clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw); @@ -95,19 +95,19 @@ at91_clk_register_h32mx(struct regmap *regmap, const char *name, return ERR_PTR(-ENOMEM); h32mxclk->parent = parent_name; - h32mxclk->hw.name = name; - h32mxclk->hw.ops = &h32mx_ops; - h32mxclk->hw.parent_names = &h32mxclk->parent; - h32mxclk->hw.num_parents = 1; + h32mxclk->hw.clk.name = name; + h32mxclk->hw.clk.ops = &h32mx_ops; + h32mxclk->hw.clk.parent_names = &h32mxclk->parent; + h32mxclk->hw.clk.num_parents = 1; /* h32mxclk.hw.flags = CLK_SET_RATE_GATE; */ h32mxclk->regmap = regmap; - ret = clk_register(&h32mxclk->hw); + ret = bclk_register(&h32mxclk->hw.clk); if (ret) { kfree(h32mxclk); return ERR_PTR(ret); } - return &h32mxclk->hw; + return &h32mxclk->hw.clk; } diff --git a/drivers/clk/at91/clk-i2s-mux.c b/drivers/clk/at91/clk-i2s-mux.c index f906007ed5..510ea24bbc 100644 --- a/drivers/clk/at91/clk-i2s-mux.c +++ b/drivers/clk/at91/clk-i2s-mux.c @@ -21,17 +21,17 @@ #include "pmc.h" struct clk_i2s_mux { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; u8 bus_id; const char *parent_names[]; }; -#define to_clk_i2s_mux(clk) container_of(clk, struct clk_i2s_mux, clk) +#define to_clk_i2s_mux(_hw) container_of(_hw, struct clk_i2s_mux, hw) -static int clk_i2s_mux_get_parent(struct clk *clk) +static int clk_i2s_mux_get_parent(struct clk_hw *hw) { - struct clk_i2s_mux *mux = to_clk_i2s_mux(clk); + struct clk_i2s_mux *mux = to_clk_i2s_mux(hw); u32 val; regmap_read(mux->regmap, AT91_SFR_I2SCLKSEL, &val); @@ -39,9 +39,9 @@ static int clk_i2s_mux_get_parent(struct clk *clk) return (val & BIT(mux->bus_id)) >> mux->bus_id; } -static int clk_i2s_mux_set_parent(struct clk *clk, u8 index) +static int clk_i2s_mux_set_parent(struct clk_hw *hw, u8 index) { - struct clk_i2s_mux *mux = to_clk_i2s_mux(clk); + struct clk_i2s_mux *mux = to_clk_i2s_mux(hw); return regmap_update_bits(mux->regmap, AT91_SFR_I2SCLKSEL, BIT(mux->bus_id), index << mux->bus_id); @@ -66,21 +66,21 @@ at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, if (!i2s_ck) return ERR_PTR(-ENOMEM); - i2s_ck->clk.name = name; - i2s_ck->clk.ops = &clk_i2s_mux_ops; + i2s_ck->hw.clk.name = name; + i2s_ck->hw.clk.ops = &clk_i2s_mux_ops; memcpy(i2s_ck->parent_names, parent_names, num_parents * sizeof(i2s_ck->parent_names[0])); - i2s_ck->clk.parent_names = &i2s_ck->parent_names[0]; - i2s_ck->clk.num_parents = num_parents; + i2s_ck->hw.clk.parent_names = &i2s_ck->parent_names[0]; + i2s_ck->hw.clk.num_parents = num_parents; i2s_ck->bus_id = bus_id; i2s_ck->regmap = regmap; - ret = clk_register(&i2s_ck->clk); + ret = bclk_register(&i2s_ck->hw.clk); if (ret) { kfree(i2s_ck); return ERR_PTR(ret); } - return &i2s_ck->clk; + return &i2s_ck->hw.clk; } diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index 08abb1673b..38e72d6538 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -26,36 +26,36 @@ AT91_PMC_OSCBYPASS)) ? 1 : 0) struct clk_main_osc { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; const char *parent; }; -#define to_clk_main_osc(clk) container_of(clk, struct clk_main_osc, clk) +#define to_clk_main_osc(_hw) container_of(_hw, struct clk_main_osc, hw) struct clk_main_rc_osc { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; unsigned long frequency; }; -#define to_clk_main_rc_osc(clk) container_of(clk, struct clk_main_rc_osc, clk) +#define to_clk_main_rc_osc(_hw) container_of(_hw, struct clk_main_rc_osc, hw) struct clk_rm9200_main { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; const char *parent; }; -#define to_clk_rm9200_main(clk) container_of(clk, struct clk_rm9200_main, clk) +#define to_clk_rm9200_main(_hw) container_of(_hw, struct clk_rm9200_main, hw) struct clk_sam9x5_main { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; u8 parent; }; -#define to_clk_sam9x5_main(clk) container_of(clk, struct clk_sam9x5_main, clk) +#define to_clk_sam9x5_main(_hw) container_of(_hw, struct clk_sam9x5_main, hw) static inline bool clk_main_osc_ready(struct regmap *regmap) { @@ -66,9 +66,9 @@ static inline bool clk_main_osc_ready(struct regmap *regmap) return status & AT91_PMC_MOSCS; } -static int clk_main_osc_enable(struct clk *clk) +static int clk_main_osc_enable(struct clk_hw *hw) { - struct clk_main_osc *osc = to_clk_main_osc(clk); + struct clk_main_osc *osc = to_clk_main_osc(hw); struct regmap *regmap = osc->regmap; u32 tmp; @@ -89,9 +89,9 @@ static int clk_main_osc_enable(struct clk *clk) return 0; } -static void clk_main_osc_disable(struct clk *clk) +static void clk_main_osc_disable(struct clk_hw *hw) { - struct clk_main_osc *osc = to_clk_main_osc(clk); + struct clk_main_osc *osc = to_clk_main_osc(hw); struct regmap *regmap = osc->regmap; u32 tmp; @@ -106,9 +106,9 @@ static void clk_main_osc_disable(struct clk *clk) regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_KEY); } -static int clk_main_osc_is_enabled(struct clk *clk) +static int clk_main_osc_is_enabled(struct clk_hw *hw) { - struct clk_main_osc *osc = to_clk_main_osc(clk); + struct clk_main_osc *osc = to_clk_main_osc(hw); struct regmap *regmap = osc->regmap; u32 tmp, status; @@ -142,10 +142,10 @@ at91_clk_register_main_osc(struct regmap *regmap, osc = xzalloc(sizeof(*osc)); osc->parent = parent_name; - osc->clk.name = name; - osc->clk.ops = &main_osc_ops; - osc->clk.parent_names = &osc->parent; - osc->clk.num_parents = 1; + osc->hw.clk.name = name; + osc->hw.clk.ops = &main_osc_ops; + osc->hw.clk.parent_names = &osc->parent; + osc->hw.clk.num_parents = 1; osc->regmap = regmap; if (bypass) @@ -154,13 +154,13 @@ at91_clk_register_main_osc(struct regmap *regmap, AT91_PMC_MOSCEN, AT91_PMC_OSCBYPASS | AT91_PMC_KEY); - ret = clk_register(&osc->clk); + ret = bclk_register(&osc->hw.clk); if (ret) { free(osc); return ERR_PTR(ret); } - return &osc->clk; + return &osc->hw.clk; } static bool clk_main_rc_osc_ready(struct regmap *regmap) @@ -172,9 +172,9 @@ static bool clk_main_rc_osc_ready(struct regmap *regmap) return status & AT91_PMC_MOSCRCS; } -static int clk_main_rc_osc_enable(struct clk *clk) +static int clk_main_rc_osc_enable(struct clk_hw *hw) { - struct clk_main_rc_osc *osc = to_clk_main_rc_osc(clk); + struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); struct regmap *regmap = osc->regmap; unsigned int mor; @@ -191,9 +191,9 @@ static int clk_main_rc_osc_enable(struct clk *clk) return 0; } -static void clk_main_rc_osc_disable(struct clk *clk) +static void clk_main_rc_osc_disable(struct clk_hw *hw) { - struct clk_main_rc_osc *osc = to_clk_main_rc_osc(clk); + struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); struct regmap *regmap = osc->regmap; unsigned int mor; @@ -206,9 +206,9 @@ static void clk_main_rc_osc_disable(struct clk *clk) MOR_KEY_MASK | AT91_PMC_MOSCRCEN, AT91_PMC_KEY); } -static int clk_main_rc_osc_is_enabled(struct clk *clk) +static int clk_main_rc_osc_is_enabled(struct clk_hw *hw) { - struct clk_main_rc_osc *osc = to_clk_main_rc_osc(clk); + struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); struct regmap *regmap = osc->regmap; unsigned int mor, status; @@ -218,10 +218,10 @@ static int clk_main_rc_osc_is_enabled(struct clk *clk) return (mor & AT91_PMC_MOSCRCEN) && (status & AT91_PMC_MOSCRCS); } -static unsigned long clk_main_rc_osc_recalc_rate(struct clk *clk, +static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_main_rc_osc *osc = to_clk_main_rc_osc(clk); + struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); return osc->frequency; } @@ -246,21 +246,21 @@ at91_clk_register_main_rc_osc(struct regmap *regmap, osc = xzalloc(sizeof(*osc)); - osc->clk.name = name; - osc->clk.ops = &main_rc_osc_ops; - osc->clk.parent_names = NULL; - osc->clk.num_parents = 0; + osc->hw.clk.name = name; + osc->hw.clk.ops = &main_rc_osc_ops; + osc->hw.clk.parent_names = NULL; + osc->hw.clk.num_parents = 0; osc->regmap = regmap; osc->frequency = frequency; - ret = clk_register(&osc->clk); + ret = bclk_register(&osc->hw.clk); if (ret) { kfree(osc); return ERR_PTR(ret); } - return &osc->clk; + return &osc->hw.clk; } static int clk_main_probe_frequency(struct regmap *regmap) @@ -293,16 +293,16 @@ static unsigned long clk_main_recalc_rate(struct regmap *regmap, return ((mcfr & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV; } -static int clk_rm9200_main_enable(struct clk *clk) +static int clk_rm9200_main_enable(struct clk_hw *hw) { - struct clk_rm9200_main *clkmain = to_clk_rm9200_main(clk); + struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); return clk_main_probe_frequency(clkmain->regmap); } -static int clk_rm9200_main_is_enabled(struct clk *clk) +static int clk_rm9200_main_is_enabled(struct clk_hw *hw) { - struct clk_rm9200_main *clkmain = to_clk_rm9200_main(clk); + struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); unsigned int status; regmap_read(clkmain->regmap, AT91_CKGR_MCFR, &status); @@ -310,10 +310,10 @@ static int clk_rm9200_main_is_enabled(struct clk *clk) return status & AT91_PMC_MAINRDY ? 1 : 0; } -static unsigned long clk_rm9200_main_recalc_rate(struct clk *clk, +static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_rm9200_main *clkmain = to_clk_rm9200_main(clk); + struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); return clk_main_recalc_rate(clkmain->regmap, parent_rate); } @@ -341,19 +341,19 @@ at91_clk_register_rm9200_main(struct regmap *regmap, clkmain = xzalloc(sizeof(*clkmain)); clkmain->parent = parent_name; - clkmain->clk.name = name; - clkmain->clk.ops = &rm9200_main_ops; - clkmain->clk.parent_names = &clkmain->parent; - clkmain->clk.num_parents = 1; + clkmain->hw.clk.name = name; + clkmain->hw.clk.ops = &rm9200_main_ops; + clkmain->hw.clk.parent_names = &clkmain->parent; + clkmain->hw.clk.num_parents = 1; clkmain->regmap = regmap; - ret = clk_register(&clkmain->clk); + ret = bclk_register(&clkmain->hw.clk); if (ret) { kfree(clkmain); return ERR_PTR(ret); } - return &clkmain->clk; + return &clkmain->hw.clk; } static inline bool clk_sam9x5_main_ready(struct regmap *regmap) @@ -365,9 +365,9 @@ static inline bool clk_sam9x5_main_ready(struct regmap *regmap) return status & AT91_PMC_MOSCSELS ? 1 : 0; } -static int clk_sam9x5_main_enable(struct clk *clk) +static int clk_sam9x5_main_enable(struct clk_hw *hw) { - struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(clk); + struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); struct regmap *regmap = clkmain->regmap; while (!clk_sam9x5_main_ready(regmap)) @@ -376,24 +376,24 @@ static int clk_sam9x5_main_enable(struct clk *clk) return clk_main_probe_frequency(regmap); } -static int clk_sam9x5_main_is_enabled(struct clk *clk) +static int clk_sam9x5_main_is_enabled(struct clk_hw *hw) { - struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(clk); + struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); return clk_sam9x5_main_ready(clkmain->regmap); } -static unsigned long clk_sam9x5_main_recalc_rate(struct clk *clk, +static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(clk); + struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); return clk_main_recalc_rate(clkmain->regmap, parent_rate); } -static int clk_sam9x5_main_set_parent(struct clk *clk, u8 index) +static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index) { - struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(clk); + struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); struct regmap *regmap = clkmain->regmap; unsigned int tmp; @@ -414,9 +414,9 @@ static int clk_sam9x5_main_set_parent(struct clk *clk, u8 index) return 0; } -static int clk_sam9x5_main_get_parent(struct clk *clk) +static int clk_sam9x5_main_get_parent(struct clk_hw *hw) { - struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(clk); + struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); unsigned int status; regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status); @@ -451,11 +451,11 @@ at91_clk_register_sam9x5_main(struct regmap *regmap, clkmain = xzalloc(sizeof(*clkmain)); - clkmain->clk.name = name; - clkmain->clk.ops = &sam9x5_main_ops; - parents_array_size = num_parents * sizeof (clkmain->clk.parent_names[0]); - clkmain->clk.parent_names = xmemdup(parent_names, parents_array_size); - clkmain->clk.num_parents = num_parents; + clkmain->hw.clk.name = name; + clkmain->hw.clk.ops = &sam9x5_main_ops; + parents_array_size = num_parents * sizeof (clkmain->hw.clk.parent_names[0]); + clkmain->hw.clk.parent_names = xmemdup(parent_names, parents_array_size); + clkmain->hw.clk.num_parents = num_parents; /* init.flags = CLK_SET_PARENT_GATE; */ @@ -463,11 +463,11 @@ at91_clk_register_sam9x5_main(struct regmap *regmap, regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status); clkmain->parent = clk_main_parent_select(status); - ret = clk_register(&clkmain->clk); + ret = bclk_register(&clkmain->hw.clk); if (ret) { kfree(clkmain); return ERR_PTR(ret); } - return &clkmain->clk; + return &clkmain->hw.clk; } diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index da5e316988..3e4836b667 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -18,10 +18,10 @@ #define MASTER_DIV_SHIFT 8 #define MASTER_DIV_MASK 0x3 -#define to_clk_master(clk) container_of(clk, struct clk_master, clk) +#define to_clk_master(_hw) container_of(_hw, struct clk_master, hw) struct clk_master { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; const struct clk_master_layout *layout; const struct clk_master_characteristics *characteristics; @@ -38,9 +38,9 @@ static inline bool clk_master_ready(struct regmap *regmap) return status & AT91_PMC_MCKRDY ? 1 : 0; } -static int clk_master_enable(struct clk *clk) +static int clk_master_enable(struct clk_hw *hw) { - struct clk_master *master = to_clk_master(clk); + struct clk_master *master = to_clk_master(hw); while (!clk_master_ready(master->regmap)) barrier(); @@ -48,20 +48,20 @@ static int clk_master_enable(struct clk *clk) return 0; } -static int clk_master_is_enabled(struct clk *clk) +static int clk_master_is_enabled(struct clk_hw *hw) { - struct clk_master *master = to_clk_master(clk); + struct clk_master *master = to_clk_master(hw); return clk_master_ready(master->regmap); } -static unsigned long clk_master_recalc_rate(struct clk *clk, +static unsigned long clk_master_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { u8 pres; u8 div; unsigned long rate = parent_rate; - struct clk_master *master = to_clk_master(clk); + struct clk_master *master = to_clk_master(hw); const struct clk_master_layout *layout = master->layout; const struct clk_master_characteristics *characteristics = master->characteristics; @@ -88,9 +88,9 @@ static unsigned long clk_master_recalc_rate(struct clk *clk, return rate; } -static int clk_master_get_parent(struct clk *clk) +static int clk_master_get_parent(struct clk_hw *hw) { - struct clk_master *master = to_clk_master(clk); + struct clk_master *master = to_clk_master(hw); unsigned int mckr; regmap_read(master->regmap, master->layout->offset, &mckr); @@ -121,23 +121,23 @@ at91_clk_register_master(struct regmap *regmap, master = xzalloc(struct_size(master, parents, num_parents)); - master->clk.name = name; - master->clk.ops = &master_ops; + master->hw.clk.name = name; + master->hw.clk.ops = &master_ops; memcpy(master->parents, parent_names, parent_names_size); - master->clk.parent_names = master->parents; - master->clk.num_parents = num_parents; + master->hw.clk.parent_names = master->parents; + master->hw.clk.num_parents = num_parents; master->layout = layout; master->characteristics = characteristics; master->regmap = regmap; - ret = clk_register(&master->clk); + ret = bclk_register(&master->hw.clk); if (ret) { kfree(master); return ERR_PTR(ret); } - return &master->clk; + return &master->hw.clk; } diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c index 2b9008eb2c..c768947647 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -23,16 +23,16 @@ #define PERIPHERAL_MAX_SHIFT 3 struct clk_peripheral { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; u32 id; const char *parent; }; -#define to_clk_peripheral(clk) container_of(clk, struct clk_peripheral, clk) +#define to_clk_peripheral(_hw) container_of(_hw, struct clk_peripheral, hw) struct clk_sam9x5_peripheral { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; struct clk_range range; u32 id; @@ -42,12 +42,12 @@ struct clk_sam9x5_peripheral { const char *parent; }; -#define to_clk_sam9x5_peripheral(clk) \ - container_of(clk, struct clk_sam9x5_peripheral, clk) +#define to_clk_sam9x5_peripheral(_hw) \ + container_of(_hw, struct clk_sam9x5_peripheral, hw) -static int clk_peripheral_enable(struct clk *clk) +static int clk_peripheral_enable(struct clk_hw *hw) { - struct clk_peripheral *periph = to_clk_peripheral(clk); + struct clk_peripheral *periph = to_clk_peripheral(hw); int offset = AT91_PMC_PCER; u32 id = periph->id; @@ -60,9 +60,9 @@ static int clk_peripheral_enable(struct clk *clk) return 0; } -static void clk_peripheral_disable(struct clk *clk) +static void clk_peripheral_disable(struct clk_hw *hw) { - struct clk_peripheral *periph = to_clk_peripheral(clk); + struct clk_peripheral *periph = to_clk_peripheral(hw); int offset = AT91_PMC_PCDR; u32 id = periph->id; @@ -73,9 +73,9 @@ static void clk_peripheral_disable(struct clk *clk) regmap_write(periph->regmap, offset, PERIPHERAL_MASK(id)); } -static int clk_peripheral_is_enabled(struct clk *clk) +static int clk_peripheral_is_enabled(struct clk_hw *hw) { - struct clk_peripheral *periph = to_clk_peripheral(clk); + struct clk_peripheral *periph = to_clk_peripheral(hw); int offset = AT91_PMC_PCSR; unsigned int status; u32 id = periph->id; @@ -107,25 +107,25 @@ at91_clk_register_peripheral(struct regmap *regmap, const char *name, periph = xzalloc(sizeof(*periph)); - periph->clk.name = name; - periph->clk.ops = &peripheral_ops; + periph->hw.clk.name = name; + periph->hw.clk.ops = &peripheral_ops; if (parent_name) { periph->parent = parent_name; - periph->clk.parent_names = &periph->parent; - periph->clk.num_parents = 1; + periph->hw.clk.parent_names = &periph->parent; + periph->hw.clk.num_parents = 1; } periph->id = id; periph->regmap = regmap; - ret = clk_register(&periph->clk); + ret = bclk_register(&periph->hw.clk); if (ret) { kfree(periph); return ERR_PTR(ret); } - return &periph->clk; + return &periph->hw.clk; } static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph) @@ -138,7 +138,7 @@ static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph) return; if (periph->range.max) { - parent = clk_get_parent(&periph->clk); + parent = clk_get_parent(&periph->hw.clk); parent_rate = clk_get_rate(parent); if (!parent_rate) return; @@ -153,9 +153,9 @@ static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph) periph->div = shift; } -static int clk_sam9x5_peripheral_enable(struct clk *clk) +static int clk_sam9x5_peripheral_enable(struct clk_hw *hw) { - struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk); + struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); if (periph->id < PERIPHERAL_ID_MIN) return 0; @@ -172,9 +172,9 @@ static int clk_sam9x5_peripheral_enable(struct clk *clk) return 0; } -static void clk_sam9x5_peripheral_disable(struct clk *clk) +static void clk_sam9x5_peripheral_disable(struct clk_hw *hw) { - struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk); + struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); if (periph->id < PERIPHERAL_ID_MIN) return; @@ -186,9 +186,9 @@ static void clk_sam9x5_peripheral_disable(struct clk *clk) periph->layout->cmd); } -static int clk_sam9x5_peripheral_is_enabled(struct clk *clk) +static int clk_sam9x5_peripheral_is_enabled(struct clk_hw *hw) { - struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk); + struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); unsigned int status; if (periph->id < PERIPHERAL_ID_MIN) @@ -202,10 +202,10 @@ static int clk_sam9x5_peripheral_is_enabled(struct clk *clk) } static unsigned long -clk_sam9x5_peripheral_recalc_rate(struct clk *clk, +clk_sam9x5_peripheral_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk); + struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); unsigned int status; if (periph->id < PERIPHERAL_ID_MIN) @@ -225,7 +225,7 @@ clk_sam9x5_peripheral_recalc_rate(struct clk *clk, return parent_rate >> periph->div; } -static long clk_sam9x5_peripheral_round_rate(struct clk *clk, +static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { @@ -234,7 +234,7 @@ static long clk_sam9x5_peripheral_round_rate(struct clk *clk, unsigned long best_diff; unsigned long cur_rate = *parent_rate; unsigned long cur_diff; - struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk); + struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) return *parent_rate; @@ -271,12 +271,12 @@ static long clk_sam9x5_peripheral_round_rate(struct clk *clk, return best_rate; } -static int clk_sam9x5_peripheral_set_rate(struct clk *clk, +static int clk_sam9x5_peripheral_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { int shift; - struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk); + struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) { if (parent_rate == rate) return 0; @@ -321,13 +321,13 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regmap, periph = xzalloc(sizeof(*periph)); - periph->clk.name = name; - periph->clk.ops = &sam9x5_peripheral_ops; + periph->hw.clk.name = name; + periph->hw.clk.ops = &sam9x5_peripheral_ops; if (parent_name) { periph->parent = parent_name; - periph->clk.parent_names = &periph->parent; - periph->clk.num_parents = 1; + periph->hw.clk.parent_names = &periph->parent; + periph->hw.clk.num_parents = 1; } periph->id = id; @@ -338,7 +338,7 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regmap, periph->layout = layout; periph->range = *range; - ret = clk_register(&periph->clk); + ret = bclk_register(&periph->hw.clk); if (ret) { kfree(periph); return ERR_PTR(ret); @@ -347,5 +347,5 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regmap, clk_sam9x5_peripheral_autodiv(periph); pmc_register_id(id); - return &periph->clk; + return &periph->hw.clk; } diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c index 5cb156e784..d8ea566f49 100644 --- a/drivers/clk/at91/clk-pll.c +++ b/drivers/clk/at91/clk-pll.c @@ -31,10 +31,10 @@ #define PLL_OUT_SHIFT 14 #define PLL_MAX_ID 1 -#define to_clk_pll(clk) container_of(clk, struct clk_pll, clk) +#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) struct clk_pll { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; u8 id; u8 div; @@ -54,9 +54,9 @@ static inline bool clk_pll_ready(struct regmap *regmap, int id) return status & PLL_STATUS_MASK(id) ? 1 : 0; } -static int clk_pll_enable(struct clk *clk) +static int clk_pll_enable(struct clk_hw *hw) { - struct clk_pll *pll = to_clk_pll(clk); + struct clk_pll *pll = to_clk_pll(hw); struct regmap *regmap = pll->regmap; const struct clk_pll_layout *layout = pll->layout; const struct clk_pll_characteristics *characteristics = @@ -97,25 +97,25 @@ static int clk_pll_enable(struct clk *clk) return 0; } -static int clk_pll_is_enabled(struct clk *clk) +static int clk_pll_is_enabled(struct clk_hw *hw) { - struct clk_pll *pll = to_clk_pll(clk); + struct clk_pll *pll = to_clk_pll(hw); return clk_pll_ready(pll->regmap, pll->id); } -static void clk_pll_disable(struct clk *clk) +static void clk_pll_disable(struct clk_hw *hw) { - struct clk_pll *pll = to_clk_pll(clk); + struct clk_pll *pll = to_clk_pll(hw); unsigned int mask = pll->layout->pllr_mask; regmap_write_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask); } -static unsigned long clk_pll_recalc_rate(struct clk *clk, +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_pll *pll = to_clk_pll(clk); + struct clk_pll *pll = to_clk_pll(hw); if (!pll->div || !pll->mul) return 0; @@ -233,19 +233,19 @@ static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate, return bestrate; } -static long clk_pll_round_rate(struct clk *clk, unsigned long rate, +static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - struct clk_pll *pll = to_clk_pll(clk); + struct clk_pll *pll = to_clk_pll(hw); return clk_pll_get_best_div_mul(pll, rate, *parent_rate, NULL, NULL, NULL); } -static int clk_pll_set_rate(struct clk *clk, unsigned long rate, +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_pll *pll = to_clk_pll(clk); + struct clk_pll *pll = to_clk_pll(hw); long ret; u32 div; u32 mul; @@ -289,10 +289,10 @@ at91_clk_register_pll(struct regmap *regmap, const char *name, pll = xzalloc(sizeof(*pll)); pll->parent = parent_name; - pll->clk.name = name; - pll->clk.ops = &pll_ops; - pll->clk.parent_names = &pll->parent; - pll->clk.num_parents = 1; + pll->hw.clk.name = name; + pll->hw.clk.ops = &pll_ops; + pll->hw.clk.parent_names = &pll->parent; + pll->hw.clk.num_parents = 1; /* init.flags = CLK_SET_RATE_GATE; */ @@ -304,13 +304,13 @@ at91_clk_register_pll(struct regmap *regmap, const char *name, pll->div = PLL_DIV(pllr); pll->mul = PLL_MUL(pllr, layout); - ret = clk_register(&pll->clk); + ret = bclk_register(&pll->hw.clk); if (ret) { kfree(pll); return ERR_PTR(ret); } - return &pll->clk; + return &pll->hw.clk; } diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c index 1cbb61bb2c..2830b16722 100644 --- a/drivers/clk/at91/clk-plldiv.c +++ b/drivers/clk/at91/clk-plldiv.c @@ -14,18 +14,18 @@ #include "pmc.h" -#define to_clk_plldiv(hw) container_of(clk, struct clk_plldiv, clk) +#define to_clk_plldiv(_hw) container_of(_hw, struct clk_plldiv, hw) struct clk_plldiv { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; const char *parent; }; -static unsigned long clk_plldiv_recalc_rate(struct clk *clk, +static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_plldiv *plldiv = to_clk_plldiv(clk); + struct clk_plldiv *plldiv = to_clk_plldiv(hw); unsigned int mckr; regmap_read(plldiv->regmap, AT91_PMC_MCKR, &mckr); @@ -36,7 +36,7 @@ static unsigned long clk_plldiv_recalc_rate(struct clk *clk, return parent_rate; } -static long clk_plldiv_round_rate(struct clk *clk, unsigned long rate, +static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { unsigned long div; @@ -53,10 +53,10 @@ static long clk_plldiv_round_rate(struct clk *clk, unsigned long rate, return *parent_rate; } -static int clk_plldiv_set_rate(struct clk *clk, unsigned long rate, +static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_plldiv *plldiv = to_clk_plldiv(clk); + struct clk_plldiv *plldiv = to_clk_plldiv(hw); if ((parent_rate != rate) && (parent_rate / 2 != rate)) return -EINVAL; @@ -82,24 +82,24 @@ at91_clk_register_plldiv(struct regmap *regmap, const char *name, plldiv = xzalloc(sizeof(*plldiv)); - plldiv->clk.name = name; - plldiv->clk.ops = &plldiv_ops; + plldiv->hw.clk.name = name; + plldiv->hw.clk.ops = &plldiv_ops; if (parent_name) { plldiv->parent = parent_name; - plldiv->clk.parent_names = &plldiv->parent; - plldiv->clk.num_parents = 1; + plldiv->hw.clk.parent_names = &plldiv->parent; + plldiv->hw.clk.num_parents = 1; } /* init.flags = CLK_SET_RATE_GATE; */ plldiv->regmap = regmap; - ret = clk_register(&plldiv->clk); + ret = bclk_register(&plldiv->hw.clk); if (ret) { kfree(plldiv); return ERR_PTR(ret); } - return &plldiv->clk; + return &plldiv->hw.clk; } diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c index 99a0fa29a3..ec53f1addd 100644 --- a/drivers/clk/at91/clk-programmable.c +++ b/drivers/clk/at91/clk-programmable.c @@ -22,19 +22,19 @@ #define PROG_MAX_RM9200_CSS 3 struct clk_programmable { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; u8 id; const struct clk_programmable_layout *layout; const char *parent_names[]; }; -#define to_clk_programmable(clk) container_of(clk, struct clk_programmable, clk) +#define to_clk_programmable(_hw) container_of(_hw, struct clk_programmable, hw) -static unsigned long clk_programmable_recalc_rate(struct clk *clk, +static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_programmable *prog = to_clk_programmable(clk); + struct clk_programmable *prog = to_clk_programmable(hw); const struct clk_programmable_layout *layout = prog->layout; unsigned int pckr; unsigned long rate; @@ -49,9 +49,9 @@ static unsigned long clk_programmable_recalc_rate(struct clk *clk, return rate; } -static int clk_programmable_set_parent(struct clk *clk, u8 index) +static int clk_programmable_set_parent(struct clk_hw *hw, u8 index) { - struct clk_programmable *prog = to_clk_programmable(clk); + struct clk_programmable *prog = to_clk_programmable(hw); const struct clk_programmable_layout *layout = prog->layout; unsigned int mask = layout->css_mask; unsigned int pckr = index; @@ -71,9 +71,9 @@ static int clk_programmable_set_parent(struct clk *clk, u8 index) return 0; } -static int clk_programmable_get_parent(struct clk *clk) +static int clk_programmable_get_parent(struct clk_hw *hw) { - struct clk_programmable *prog = to_clk_programmable(clk); + struct clk_programmable *prog = to_clk_programmable(hw); const struct clk_programmable_layout *layout = prog->layout; unsigned int pckr; u8 ret; @@ -88,10 +88,10 @@ static int clk_programmable_get_parent(struct clk *clk) return ret; } -static int clk_programmable_set_rate(struct clk *clk, unsigned long rate, +static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_programmable *prog = to_clk_programmable(clk); + struct clk_programmable *prog = to_clk_programmable(hw); const struct clk_programmable_layout *layout = prog->layout; unsigned long div = parent_rate / rate; int shift = 0; @@ -144,19 +144,19 @@ at91_clk_register_programmable(struct regmap *regmap, if (!prog) return ERR_PTR(-ENOMEM); - prog->clk.name = name; - prog->clk.ops = &programmable_ops; + prog->hw.clk.name = name; + prog->hw.clk.ops = &programmable_ops; memcpy(prog->parent_names, parent_names, num_parents * sizeof(prog->parent_names[0])); - prog->clk.parent_names = &prog->parent_names[0]; - prog->clk.num_parents = num_parents; + prog->hw.clk.parent_names = &prog->parent_names[0]; + prog->hw.clk.num_parents = num_parents; /* init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; */ prog->id = id; prog->layout = layout; prog->regmap = regmap; - ret = clk_register(&prog->clk); + ret = bclk_register(&prog->hw.clk); if (ret) { kfree(prog); return ERR_PTR(ret); @@ -164,7 +164,7 @@ at91_clk_register_programmable(struct regmap *regmap, pmc_register_pck(id); - return &prog->clk; + return &prog->hw.clk; } const struct clk_programmable_layout at91rm9200_programmable_layout = { diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index 9ca77f8722..744c3833bb 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -55,7 +55,7 @@ struct sam9x60_pll { const char *parent_name; }; -#define to_sam9x60_pll(clk) container_of(clk, struct sam9x60_pll, clk) +#define to_sam9x60_pll(_hw) container_of(_hw->clk, struct sam9x60_pll, clk) static inline bool sam9x60_pll_ready(struct regmap *regmap, int id) { @@ -66,9 +66,9 @@ static inline bool sam9x60_pll_ready(struct regmap *regmap, int id) return !!(status & BIT(id)); } -static int sam9x60_pll_enable(struct clk *clk) +static int sam9x60_pll_enable(struct clk_hw *hw) { - struct sam9x60_pll *pll = to_sam9x60_pll(clk); + struct sam9x60_pll *pll = to_sam9x60_pll(hw); struct regmap *regmap = pll->regmap; u8 div; u16 mul; @@ -127,16 +127,16 @@ static int sam9x60_pll_enable(struct clk *clk) return 0; } -static int sam9x60_pll_is_enabled(struct clk *clk) +static int sam9x60_pll_is_enabled(struct clk_hw *hw) { - struct sam9x60_pll *pll = to_sam9x60_pll(clk); + struct sam9x60_pll *pll = to_sam9x60_pll(hw); return sam9x60_pll_ready(pll->regmap, pll->id); } -static void sam9x60_pll_disable(struct clk *clk) +static void sam9x60_pll_disable(struct clk_hw *hw) { - struct sam9x60_pll *pll = to_sam9x60_pll(clk); + struct sam9x60_pll *pll = to_sam9x60_pll(hw); regmap_write(pll->regmap, PMC_PLL_UPDT, pll->id); @@ -156,10 +156,10 @@ static void sam9x60_pll_disable(struct clk *clk) PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE); } -static unsigned long sam9x60_pll_recalc_rate(struct clk *clk, +static unsigned long sam9x60_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct sam9x60_pll *pll = to_sam9x60_pll(clk); + struct sam9x60_pll *pll = to_sam9x60_pll(hw); return (parent_rate * (pll->mul + 1)) / (pll->div + 1); } @@ -253,18 +253,18 @@ static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll, return bestrate; } -static long sam9x60_pll_round_rate(struct clk *clk, unsigned long rate, +static long sam9x60_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - struct sam9x60_pll *pll = to_sam9x60_pll(clk); + struct sam9x60_pll *pll = to_sam9x60_pll(hw); return sam9x60_pll_get_best_div_mul(pll, rate, *parent_rate, false); } -static int sam9x60_pll_set_rate(struct clk *clk, unsigned long rate, +static int sam9x60_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct sam9x60_pll *pll = to_sam9x60_pll(clk); + struct sam9x60_pll *pll = to_sam9x60_pll(hw); return sam9x60_pll_get_best_div_mul(pll, rate, parent_rate, true); } @@ -311,7 +311,7 @@ sam9x60_clk_register_pll(struct regmap *regmap, regmap_read(regmap, PMC_PLL_CTRL1, &pllr); pll->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, pllr); - ret = clk_register(&pll->clk); + ret = bclk_register(&pll->clk); if (ret) { kfree(pll); return ERR_PTR(ret); diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c index bcce810fa5..bc4285e4bf 100644 --- a/drivers/clk/at91/clk-slow.c +++ b/drivers/clk/at91/clk-slow.c @@ -18,16 +18,16 @@ #include "pmc.h" struct clk_sam9260_slow { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; const char *parent_names[]; }; -#define to_clk_sam9260_slow(clk) container_of(clk, struct clk_sam9260_slow, clk) +#define to_clk_sam9260_slow(_hw) container_of(_hw, struct clk_sam9260_slow, hw) -static int clk_sam9260_slow_get_parent(struct clk *clk) +static int clk_sam9260_slow_get_parent(struct clk_hw *hw) { - struct clk_sam9260_slow *slowck = to_clk_sam9260_slow(clk); + struct clk_sam9260_slow *slowck = to_clk_sam9260_slow(hw); unsigned int status; regmap_read(slowck->regmap, AT91_PMC_SR, &status); @@ -55,19 +55,19 @@ at91_clk_register_sam9260_slow(struct regmap *regmap, return ERR_PTR(-EINVAL); slowck = xzalloc(struct_size(slowck, parent_names, num_parents)); - slowck->clk.name = name; - slowck->clk.ops = &sam9260_slow_ops; + slowck->hw.clk.name = name; + slowck->hw.clk.ops = &sam9260_slow_ops; memcpy(slowck->parent_names, parent_names, num_parents * sizeof(slowck->parent_names[0])); - slowck->clk.parent_names = slowck->parent_names; - slowck->clk.num_parents = num_parents; + slowck->hw.clk.parent_names = slowck->parent_names; + slowck->hw.clk.num_parents = num_parents; slowck->regmap = regmap; - ret = clk_register(&slowck->clk); + ret = bclk_register(&slowck->hw.clk); if (ret) { kfree(slowck); return ERR_PTR(ret); } - return &slowck->clk; + return &slowck->hw.clk; } diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c index 366f2eaad5..6df698637c 100644 --- a/drivers/clk/at91/clk-smd.c +++ b/drivers/clk/at91/clk-smd.c @@ -21,18 +21,18 @@ #define SMD_MAX_DIV 0xf struct at91sam9x5_clk_smd { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; const char *parent_names[]; }; -#define to_at91sam9x5_clk_smd(clk) \ - container_of(clk, struct at91sam9x5_clk_smd, clk) +#define to_at91sam9x5_clk_smd(_hw) \ + container_of(_hw, struct at91sam9x5_clk_smd, hw) -static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk *clk, +static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(clk); + struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); unsigned int smdr; u8 smddiv; @@ -42,7 +42,7 @@ static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk *clk, return parent_rate / (smddiv + 1); } -static long at91sam9x5_clk_smd_round_rate(struct clk *clk, unsigned long rate, +static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { unsigned long div; @@ -64,9 +64,9 @@ static long at91sam9x5_clk_smd_round_rate(struct clk *clk, unsigned long rate, return bestrate; } -static int at91sam9x5_clk_smd_set_parent(struct clk *clk, u8 index) +static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index) { - struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(clk); + struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); if (index > 1) return -EINVAL; @@ -77,9 +77,9 @@ static int at91sam9x5_clk_smd_set_parent(struct clk *clk, u8 index) return 0; } -static int at91sam9x5_clk_smd_get_parent(struct clk *clk) +static int at91sam9x5_clk_smd_get_parent(struct clk_hw *hw) { - struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(clk); + struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); unsigned int smdr; regmap_read(smd->regmap, AT91_PMC_SMD, &smdr); @@ -87,10 +87,10 @@ static int at91sam9x5_clk_smd_get_parent(struct clk *clk) return smdr & AT91_PMC_SMDS; } -static int at91sam9x5_clk_smd_set_rate(struct clk *clk, unsigned long rate, +static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(clk); + struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); unsigned long div = parent_rate / rate; if (parent_rate % rate || div < 1 || div > (SMD_MAX_DIV + 1)) @@ -118,20 +118,20 @@ at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name, int ret; smd = xzalloc(struct_size(smd, parent_names, num_parents)); - smd->clk.name = name; - smd->clk.ops = &at91sam9x5_smd_ops; + smd->hw.clk.name = name; + smd->hw.clk.ops = &at91sam9x5_smd_ops; memcpy(smd->parent_names, parent_names, num_parents * sizeof(smd->parent_names[0])); - smd->clk.parent_names = smd->parent_names; - smd->clk.num_parents = num_parents; + smd->hw.clk.parent_names = smd->parent_names; + smd->hw.clk.num_parents = num_parents; /* init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; */ smd->regmap = regmap; - ret = clk_register(&smd->clk); + ret = bclk_register(&smd->hw.clk); if (ret) { kfree(smd); return ERR_PTR(ret); } - return &smd->clk; + return &smd->hw.clk; } diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c index 77f0dff98b..9a15d5b04a 100644 --- a/drivers/clk/at91/clk-system.c +++ b/drivers/clk/at91/clk-system.c @@ -17,9 +17,9 @@ #define SYSTEM_MAX_NAME_SZ 32 -#define to_clk_system(clk) container_of(clk, struct clk_system, clk) +#define to_clk_system(_hw) container_of(_hw, struct clk_system, hw) struct clk_system { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; u8 id; const char *parent_name; @@ -39,9 +39,9 @@ static inline bool clk_system_ready(struct regmap *regmap, int id) return status & (1 << id) ? 1 : 0; } -static int clk_system_enable(struct clk *clk) +static int clk_system_enable(struct clk_hw *hw) { - struct clk_system *sys = to_clk_system(clk); + struct clk_system *sys = to_clk_system(hw); regmap_write(sys->regmap, AT91_PMC_SCER, 1 << sys->id); @@ -54,16 +54,16 @@ static int clk_system_enable(struct clk *clk) return 0; } -static void clk_system_disable(struct clk *clk) +static void clk_system_disable(struct clk_hw *hw) { - struct clk_system *sys = to_clk_system(clk); + struct clk_system *sys = to_clk_system(hw); regmap_write(sys->regmap, AT91_PMC_SCDR, 1 << sys->id); } -static int clk_system_is_enabled(struct clk *clk) +static int clk_system_is_enabled(struct clk_hw *hw) { - struct clk_system *sys = to_clk_system(clk); + struct clk_system *sys = to_clk_system(hw); unsigned int status; regmap_read(sys->regmap, AT91_PMC_SCSR, &status); @@ -96,20 +96,20 @@ at91_clk_register_system(struct regmap *regmap, const char *name, return ERR_PTR(-EINVAL); sys = xzalloc(sizeof(*sys)); - sys->clk.name = name; - sys->clk.ops = &system_ops; + sys->hw.clk.name = name; + sys->hw.clk.ops = &system_ops; sys->parent_name = parent_name; - sys->clk.parent_names = &sys->parent_name; - sys->clk.num_parents = 1; + sys->hw.clk.parent_names = &sys->parent_name; + sys->hw.clk.num_parents = 1; /* init.flags = CLK_SET_RATE_PARENT; */ sys->id = id; sys->regmap = regmap; - ret = clk_register(&sys->clk); + ret = bclk_register(&sys->hw.clk); if (ret) { kfree(sys); return ERR_PTR(ret); } - return &sys->clk; + return &sys->hw.clk; } diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c index 4ca076e777..148befc8ac 100644 --- a/drivers/clk/at91/clk-usb.c +++ b/drivers/clk/at91/clk-usb.c @@ -27,30 +27,30 @@ #define SAM9X60_USBS_MASK GENMASK(1, 0) struct at91sam9x5_clk_usb { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; u32 usbs_mask; u8 num_parents; const char *parent_names[]; }; -#define to_at91sam9x5_clk_usb(clk) \ - container_of(clk, struct at91sam9x5_clk_usb, clk) +#define to_at91sam9x5_clk_usb(_hw) \ + container_of(_hw, struct at91sam9x5_clk_usb, hw) struct at91rm9200_clk_usb { - struct clk clk; + struct clk_hw hw; struct regmap *regmap; u32 divisors[4]; const char *parent_name; }; -#define to_at91rm9200_clk_usb(clk) \ - container_of(clk, struct at91rm9200_clk_usb, clk) +#define to_at91rm9200_clk_usb(_hw) \ + container_of(_hw, struct at91rm9200_clk_usb, hw) -static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk *clk, +static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(clk); + struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); unsigned int usbr; u8 usbdiv; @@ -60,9 +60,9 @@ static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk *clk, return DIV_ROUND_CLOSEST(parent_rate, (usbdiv + 1)); } -static int at91sam9x5_clk_usb_set_parent(struct clk *clk, u8 index) +static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index) { - struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(clk); + struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); if (index >= usb->num_parents) return -EINVAL; @@ -72,9 +72,9 @@ static int at91sam9x5_clk_usb_set_parent(struct clk *clk, u8 index) return 0; } -static int at91sam9x5_clk_usb_get_parent(struct clk *clk) +static int at91sam9x5_clk_usb_get_parent(struct clk_hw *hw) { - struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(clk); + struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); unsigned int usbr; regmap_read(usb->regmap, AT91_PMC_USB, &usbr); @@ -82,10 +82,10 @@ static int at91sam9x5_clk_usb_get_parent(struct clk *clk) return usbr & usb->usbs_mask; } -static int at91sam9x5_clk_usb_set_rate(struct clk *clk, unsigned long rate, +static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(clk); + struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); unsigned long div; if (!rate) @@ -108,9 +108,9 @@ static const struct clk_ops at91sam9x5_usb_ops = { .set_rate = at91sam9x5_clk_usb_set_rate, }; -static int at91sam9n12_clk_usb_enable(struct clk *clk) +static int at91sam9n12_clk_usb_enable(struct clk_hw *hw) { - struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(clk); + struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); regmap_write_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_USBS, AT91_PMC_USBS); @@ -118,16 +118,16 @@ static int at91sam9n12_clk_usb_enable(struct clk *clk) return 0; } -static void at91sam9n12_clk_usb_disable(struct clk *clk) +static void at91sam9n12_clk_usb_disable(struct clk_hw *hw) { - struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(clk); + struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); regmap_write_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_USBS, 0); } -static int at91sam9n12_clk_usb_is_enabled(struct clk *clk) +static int at91sam9n12_clk_usb_is_enabled(struct clk_hw *hw) { - struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(clk); + struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); unsigned int usbr; regmap_read(usb->regmap, AT91_PMC_USB, &usbr); @@ -152,26 +152,26 @@ _at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, int ret; usb = kzalloc(struct_size(usb, parent_names, num_parents), GFP_KERNEL); - usb->clk.name = name; - usb->clk.ops = &at91sam9x5_usb_ops; + usb->hw.clk.name = name; + usb->hw.clk.ops = &at91sam9x5_usb_ops; memcpy(usb->parent_names, parent_names, num_parents * sizeof(usb->parent_names[0])); - usb->clk.parent_names = usb->parent_names; - usb->clk.num_parents = num_parents; - usb->clk.flags = CLK_SET_RATE_PARENT; + usb->hw.clk.parent_names = usb->parent_names; + usb->hw.clk.num_parents = num_parents; + usb->hw.clk.flags = CLK_SET_RATE_PARENT; /* init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | */ /* CLK_SET_RATE_PARENT; */ usb->regmap = regmap; usb->usbs_mask = usbs_mask; usb->num_parents = num_parents; - ret = clk_register(&usb->clk); + ret = bclk_register(&usb->hw.clk); if (ret) { kfree(usb); return ERR_PTR(ret); } - return &usb->clk; + return &usb->hw.clk; } struct clk * __init @@ -198,27 +198,27 @@ at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name, int ret; usb = xzalloc(sizeof(*usb)); - usb->clk.name = name; - usb->clk.ops = &at91sam9n12_usb_ops; + usb->hw.clk.name = name; + usb->hw.clk.ops = &at91sam9n12_usb_ops; usb->parent_names[0] = parent_name; - usb->clk.parent_names = &usb->parent_names[0]; - usb->clk.num_parents = 1; + usb->hw.clk.parent_names = &usb->parent_names[0]; + usb->hw.clk.num_parents = 1; /* init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT; */ usb->regmap = regmap; - ret = clk_register(&usb->clk); + ret = bclk_register(&usb->hw.clk); if (ret) { kfree(usb); return ERR_PTR(ret); } - return &usb->clk; + return &usb->hw.clk; } -static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk *clk, +static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(clk); + struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw); unsigned int pllbr; u8 usbdiv; @@ -231,11 +231,11 @@ static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk *clk, return 0; } -static long at91rm9200_clk_usb_round_rate(struct clk *clk, unsigned long rate, +static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(clk); - struct clk *parent = clk_get_parent(clk); + struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw); + struct clk *parent = clk_get_parent(clk_hw_to_clk(hw)); unsigned long bestrate = 0; int bestdiff = -1; unsigned long tmprate; @@ -272,11 +272,11 @@ static long at91rm9200_clk_usb_round_rate(struct clk *clk, unsigned long rate, return bestrate; } -static int at91rm9200_clk_usb_set_rate(struct clk *clk, unsigned long rate, +static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { int i; - struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(clk); + struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw); unsigned long div; if (!rate) @@ -311,21 +311,21 @@ at91rm9200_clk_register_usb(struct regmap *regmap, const char *name, int ret; usb = xzalloc(sizeof(*usb)); - usb->clk.name = name; - usb->clk.ops = &at91rm9200_usb_ops; + usb->hw.clk.name = name; + usb->hw.clk.ops = &at91rm9200_usb_ops; usb->parent_name = parent_name; - usb->clk.parent_names = &usb->parent_name; - usb->clk.num_parents = 1; + usb->hw.clk.parent_names = &usb->parent_name; + usb->hw.clk.num_parents = 1; /* init.flags = CLK_SET_RATE_PARENT; */ usb->regmap = regmap; memcpy(usb->divisors, divisors, sizeof(usb->divisors)); - ret = clk_register(&usb->clk); + ret = bclk_register(&usb->hw.clk); if (ret) { kfree(usb); return ERR_PTR(ret); } - return &usb->clk; + return &usb->hw.clk; } diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index 3d71cd615f..1389983bde 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -22,13 +22,13 @@ #define UTMI_RATE 480000000 struct clk_utmi { - struct clk clk; + struct clk_hw hw; const char *parent; struct regmap *regmap_pmc; struct regmap *regmap_sfr; }; -#define to_clk_utmi(clk) container_of(clk, struct clk_utmi, clk) +#define to_clk_utmi(_hw) container_of(_hw, struct clk_utmi, hw) static inline bool clk_utmi_ready(struct regmap *regmap) { @@ -39,10 +39,10 @@ static inline bool clk_utmi_ready(struct regmap *regmap) return status & AT91_PMC_LOCKU; } -static int clk_utmi_enable(struct clk *clk) +static int clk_utmi_enable(struct clk_hw *hw) { struct clk *hw_parent; - struct clk_utmi *utmi = to_clk_utmi(clk); + struct clk_utmi *utmi = to_clk_utmi(hw); unsigned int uckr = AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT | AT91_PMC_BIASEN; unsigned int utmi_ref_clk_freq; @@ -53,7 +53,7 @@ static int clk_utmi_enable(struct clk *clk) * FREQ field of the SFR_UTMICKTRIM register to generate properly * the utmi clock. */ - hw_parent = clk_get_parent(clk); + hw_parent = clk_get_parent(clk_hw_to_clk(hw)); parent_rate = clk_get_rate(hw_parent); switch (parent_rate) { @@ -95,22 +95,22 @@ static int clk_utmi_enable(struct clk *clk) return 0; } -static int clk_utmi_is_enabled(struct clk *clk) +static int clk_utmi_is_enabled(struct clk_hw *hw) { - struct clk_utmi *utmi = to_clk_utmi(clk); + struct clk_utmi *utmi = to_clk_utmi(hw); return clk_utmi_ready(utmi->regmap_pmc); } -static void clk_utmi_disable(struct clk *clk) +static void clk_utmi_disable(struct clk_hw *hw) { - struct clk_utmi *utmi = to_clk_utmi(clk); + struct clk_utmi *utmi = to_clk_utmi(hw); regmap_write_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, AT91_PMC_UPLLEN, 0); } -static unsigned long clk_utmi_recalc_rate(struct clk *clk, +static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { /* UTMI clk rate is fixed */ @@ -133,13 +133,13 @@ at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr, utmi = xzalloc(sizeof(*utmi)); - utmi->clk.name = name; - utmi->clk.ops = &utmi_ops; + utmi->hw.clk.name = name; + utmi->hw.clk.ops = &utmi_ops; if (parent_name) { utmi->parent = parent_name; - utmi->clk.parent_names = &utmi->parent; - utmi->clk.num_parents = 1; + utmi->hw.clk.parent_names = &utmi->parent; + utmi->hw.clk.num_parents = 1; } /* utmi->clk.flags = CLK_SET_RATE_GATE; */ @@ -147,11 +147,11 @@ at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr, utmi->regmap_pmc = regmap_pmc; utmi->regmap_sfr = regmap_sfr; - ret = clk_register(&utmi->clk); + ret = bclk_register(&utmi->hw.clk); if (ret) { kfree(utmi); return ERR_PTR(ret); } - return &utmi->clk; + return &utmi->hw.clk; } diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index d9898f718c..579fbf2479 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -34,17 +34,17 @@ struct clk_slow_bits { }; struct clk_slow_osc { - struct clk clk; + struct clk_hw hw; void __iomem *sckcr; const struct clk_slow_bits *bits; unsigned long startup_usec; const char *parent_name; }; -#define to_clk_slow_osc(clk) container_of(clk, struct clk_slow_osc, clk) +#define to_clk_slow_osc(_hw) container_of(_hw, struct clk_slow_osc, hw) struct clk_sama5d4_slow_osc { - struct clk clk; + struct clk_hw hw; void __iomem *sckcr; const struct clk_slow_bits *bits; unsigned long startup_usec; @@ -52,10 +52,10 @@ struct clk_sama5d4_slow_osc { const char *parent_name; }; -#define to_clk_sama5d4_slow_osc(clk) container_of(clk, struct clk_sama5d4_slow_osc, clk) +#define to_clk_sama5d4_slow_osc(_hw) container_of(_hw, struct clk_sama5d4_slow_osc, hw) struct clk_slow_rc_osc { - struct clk clk; + struct clk_hw hw; void __iomem *sckcr; const struct clk_slow_bits *bits; unsigned long frequency; @@ -63,21 +63,21 @@ struct clk_slow_rc_osc { const char *parent_name; }; -#define to_clk_slow_rc_osc(clk) container_of(clk, struct clk_slow_rc_osc, clk) +#define to_clk_slow_rc_osc(_hw) container_of(_hw, struct clk_slow_rc_osc, hw) struct clk_sam9x5_slow { - struct clk clk; + struct clk_hw hw; void __iomem *sckcr; const struct clk_slow_bits *bits; u8 parent; const char *parent_names[]; }; -#define to_clk_sam9x5_slow(clk) container_of(clk, struct clk_sam9x5_slow, clk) +#define to_clk_sam9x5_slow(_hw) container_of(_hw, struct clk_sam9x5_slow, hw) -static int clk_slow_osc_enable(struct clk *clk) +static int clk_slow_osc_enable(struct clk_hw *hw) { - struct clk_slow_osc *osc = to_clk_slow_osc(clk); + struct clk_slow_osc *osc = to_clk_slow_osc(hw); void __iomem *sckcr = osc->sckcr; u32 tmp = readl(sckcr); @@ -91,9 +91,9 @@ static int clk_slow_osc_enable(struct clk *clk) return 0; } -static void clk_slow_osc_disable(struct clk *clk) +static void clk_slow_osc_disable(struct clk_hw *hw) { - struct clk_slow_osc *osc = to_clk_slow_osc(clk); + struct clk_slow_osc *osc = to_clk_slow_osc(hw); void __iomem *sckcr = osc->sckcr; u32 tmp = readl(sckcr); @@ -103,9 +103,9 @@ static void clk_slow_osc_disable(struct clk *clk) writel(tmp & ~osc->bits->cr_osc32en, sckcr); } -static int clk_slow_osc_is_enabled(struct clk *clk) +static int clk_slow_osc_is_enabled(struct clk_hw *hw) { - struct clk_slow_osc *osc = to_clk_slow_osc(clk); + struct clk_slow_osc *osc = to_clk_slow_osc(hw); void __iomem *sckcr = osc->sckcr; u32 tmp = readl(sckcr); @@ -137,11 +137,11 @@ at91_clk_register_slow_osc(void __iomem *sckcr, osc = xzalloc(sizeof(*osc)); - osc->clk.name = name; - osc->clk.ops = &slow_osc_ops; + osc->hw.clk.name = name; + osc->hw.clk.ops = &slow_osc_ops; osc->parent_name = parent_name; - osc->clk.parent_names = &osc->parent_name; - osc->clk.num_parents = 1; + osc->hw.clk.parent_names = &osc->parent_name; + osc->hw.clk.num_parents = 1; /* osc->clk.flags = CLK_IGNORE_UNUSED; */ osc->sckcr = sckcr; @@ -152,34 +152,34 @@ at91_clk_register_slow_osc(void __iomem *sckcr, writel((readl(sckcr) & ~osc->bits->cr_osc32en) | osc->bits->cr_osc32byp, sckcr); - ret = clk_register(&osc->clk); + ret = bclk_register(&osc->hw.clk); if (ret) { kfree(osc); return ERR_PTR(ret); } - return &osc->clk; + return &osc->hw.clk; } static void at91_clk_unregister_slow_osc(struct clk *clk) { - struct clk_slow_osc *osc = to_clk_slow_osc(clk); + struct clk_slow_osc *osc = to_clk_slow_osc(clk_to_clk_hw(clk)); clk_unregister(clk); kfree(osc); } -static unsigned long clk_slow_rc_osc_recalc_rate(struct clk *clk, +static unsigned long clk_slow_rc_osc_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(clk); + struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw); return osc->frequency; } -static int clk_slow_rc_osc_enable(struct clk *clk) +static int clk_slow_rc_osc_enable(struct clk_hw *hw) { - struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(clk); + struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw); void __iomem *sckcr = osc->sckcr; writel(readl(sckcr) | osc->bits->cr_rcen, sckcr); @@ -189,17 +189,17 @@ static int clk_slow_rc_osc_enable(struct clk *clk) return 0; } -static void clk_slow_rc_osc_disable(struct clk *clk) +static void clk_slow_rc_osc_disable(struct clk_hw *hw) { - struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(clk); + struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw); void __iomem *sckcr = osc->sckcr; writel(readl(sckcr) & ~osc->bits->cr_rcen, sckcr); } -static int clk_slow_rc_osc_is_enabled(struct clk *clk) +static int clk_slow_rc_osc_is_enabled(struct clk_hw *hw) { - struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(clk); + struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw); return !!(readl(osc->sckcr) & osc->bits->cr_rcen); } @@ -226,10 +226,10 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, return ERR_PTR(-EINVAL); osc = xzalloc(sizeof(*osc)); - osc->clk.name = name; - osc->clk.ops = &slow_rc_osc_ops; - osc->clk.parent_names = NULL; - osc->clk.num_parents = 0; + osc->hw.clk.name = name; + osc->hw.clk.ops = &slow_rc_osc_ops; + osc->hw.clk.parent_names = NULL; + osc->hw.clk.num_parents = 0; /* init.flags = CLK_IGNORE_UNUSED; */ osc->sckcr = sckcr; @@ -237,26 +237,26 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, osc->frequency = frequency; osc->startup_usec = startup; - ret = clk_register(&osc->clk); + ret = bclk_register(&osc->hw.clk); if (ret) { kfree(osc); return ERR_PTR(ret); } - return &osc->clk; + return &osc->hw.clk; } static void at91_clk_unregister_slow_rc_osc(struct clk *clk) { - struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(clk); + struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(clk_to_clk_hw(clk)); clk_unregister(clk); kfree(osc); } -static int clk_sam9x5_slow_set_parent(struct clk *clk, u8 index) +static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index) { - struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(clk); + struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw); void __iomem *sckcr = slowck->sckcr; u32 tmp; @@ -281,9 +281,9 @@ static int clk_sam9x5_slow_set_parent(struct clk *clk, u8 index) return 0; } -static int clk_sam9x5_slow_get_parent(struct clk *clk) +static int clk_sam9x5_slow_get_parent(struct clk_hw *hw) { - struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(clk); + struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw); return !!(readl(slowck->sckcr) & slowck->bits->cr_oscsel); } @@ -307,29 +307,29 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr, return ERR_PTR(-EINVAL); slowck = xzalloc(struct_size(slowck, parent_names, num_parents)); - slowck->clk.name = name; - slowck->clk.ops = &sam9x5_slow_ops; + slowck->hw.clk.name = name; + slowck->hw.clk.ops = &sam9x5_slow_ops; memcpy(slowck->parent_names, parent_names, num_parents * sizeof(slowck->parent_names[0])); - slowck->clk.parent_names = slowck->parent_names; - slowck->clk.num_parents = num_parents; + slowck->hw.clk.parent_names = slowck->parent_names; + slowck->hw.clk.num_parents = num_parents; slowck->sckcr = sckcr; slowck->bits = bits; slowck->parent = !!(readl(sckcr) & slowck->bits->cr_oscsel); - ret = clk_register(&slowck->clk); + ret = bclk_register(&slowck->hw.clk); if (ret) { kfree(slowck); return ERR_PTR(ret); } - return &slowck->clk; + return &slowck->hw.clk; } static void at91_clk_unregister_sam9x5_slow(struct clk *clk) { - struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(clk); + struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(clk_to_clk_hw(clk)); clk_unregister(clk); kfree(slowck); @@ -505,9 +505,9 @@ unregister_slow_rc: CLK_OF_DECLARE(sam9x60_clk_sckc, "microchip,sam9x60-sckc", of_sam9x60_sckc_setup); -static int clk_sama5d4_slow_osc_enable(struct clk *clk) +static int clk_sama5d4_slow_osc_enable(struct clk_hw *hw) { - struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(clk); + struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw); if (osc->prepared) return 0; @@ -527,9 +527,9 @@ static int clk_sama5d4_slow_osc_enable(struct clk *clk) return 0; } -static int clk_sama5d4_slow_osc_is_enabled(struct clk *clk) +static int clk_sama5d4_slow_osc_is_enabled(struct clk_hw *hw) { - struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(clk); + struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw); return osc->prepared; } @@ -560,10 +560,10 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np) osc = xzalloc(sizeof(*osc)); osc->parent_name = of_clk_get_parent_name(np, 0); - osc->clk.name = parent_names[1]; - osc->clk.ops = &sama5d4_slow_osc_ops; - osc->clk.parent_names = &osc->parent_name; - osc->clk.num_parents = 1; + osc->hw.clk.name = parent_names[1]; + osc->hw.clk.ops = &sama5d4_slow_osc_ops; + osc->hw.clk.parent_names = &osc->parent_name; + osc->hw.clk.num_parents = 1; /* osc->clk.flags = CLK_IGNORE_UNUSED; */ @@ -571,7 +571,7 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np) osc->startup_usec = 1200000; osc->bits = &at91sama5d4_bits; - ret = clk_register(&osc->clk); + ret = bclk_register(&osc->hw.clk); if (ret) goto free_slow_osc_data; @@ -590,7 +590,7 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np) unregister_slowck: at91_clk_unregister_sam9x5_slow(slowck); unregister_slow_osc: - clk_unregister(&osc->clk); + clk_unregister(&osc->hw.clk); free_slow_osc_data: kfree(osc); clk_unregister(slow_rc); diff --git a/drivers/clk/clk-ar933x.c b/drivers/clk/clk-ar933x.c index 0e7f2d6a67..c5e57f41ec 100644 --- a/drivers/clk/clk-ar933x.c +++ b/drivers/clk/clk-ar933x.c @@ -19,17 +19,17 @@ static struct clk *clks[ATH79_CLK_END]; static struct clk_onecell_data clk_data; struct clk_ar933x { - struct clk clk; + struct clk_hw hw; void __iomem *base; u32 div_shift; u32 div_mask; const char *parent; }; -static unsigned long clk_ar933x_recalc_rate(struct clk *clk, +static unsigned long clk_ar933x_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_ar933x *f = container_of(clk, struct clk_ar933x, clk); + struct clk_ar933x *f = container_of(hw, struct clk_ar933x, hw); unsigned long rate; unsigned long freq; u32 clock_ctrl; @@ -79,14 +79,14 @@ static struct clk *clk_ar933x(const char *name, const char *parent, f->div_shift = div_shift; f->div_mask = div_mask; - f->clk.ops = &clk_ar933x_ops; - f->clk.name = name; - f->clk.parent_names = &f->parent; - f->clk.num_parents = 1; + f->hw.clk.ops = &clk_ar933x_ops; + f->hw.clk.name = name; + f->hw.clk.parent_names = &f->parent; + f->hw.clk.num_parents = 1; - clk_register(&f->clk); + bclk_register(&f->hw.clk); - return &f->clk; + return &f->hw.clk; } static void ar933x_pll_init(void __iomem *base) diff --git a/drivers/clk/clk-ar9344.c b/drivers/clk/clk-ar9344.c index 829d4b1f91..d2f63f2608 100644 --- a/drivers/clk/clk-ar9344.c +++ b/drivers/clk/clk-ar9344.c @@ -35,17 +35,17 @@ static struct clk *clks[ATH79_CLK_END]; static struct clk_onecell_data clk_data; struct clk_ar9344 { - struct clk clk; + struct clk_hw hw; void __iomem *base; u32 div_shift; u32 div_mask; const char *parent; }; -static unsigned long clk_ar9344_recalc_rate(struct clk *clk, +static unsigned long clk_ar9344_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_ar9344 *f = container_of(clk, struct clk_ar9344, clk); + struct clk_ar9344 *f = container_of(hw, struct clk_ar9344, hw); int outdiv, refdiv, nint, nfrac; int cpu_post_div; u32 clock_ctrl; @@ -84,14 +84,14 @@ static struct clk *clk_ar9344(const char *name, const char *parent, f->div_shift = 0; f->div_mask = 0; - f->clk.ops = &clk_ar9344_ops; - f->clk.name = name; - f->clk.parent_names = &f->parent; - f->clk.num_parents = 1; + f->hw.clk.ops = &clk_ar9344_ops; + f->hw.clk.name = name; + f->hw.clk.parent_names = &f->parent; + f->hw.clk.num_parents = 1; - clk_register(&f->clk); + bclk_register(&f->hw.clk); - return &f->clk; + return &f->hw.clk; } static void ar9344_pll_init(void __iomem *base) diff --git a/drivers/clk/clk-bulk.c b/drivers/clk/clk-bulk.c index b8db60dcbc..0a0d0f2cb2 100644 --- a/drivers/clk/clk-bulk.c +++ b/drivers/clk/clk-bulk.c @@ -23,8 +23,9 @@ void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) } EXPORT_SYMBOL_GPL(clk_bulk_put); -int __must_check clk_bulk_get(struct device_d *dev, int num_clks, - struct clk_bulk_data *clks) +static int __clk_bulk_get(struct device_d *dev, int num_clks, + struct clk_bulk_data *clks, + bool optional) { int ret; int i; @@ -36,10 +37,15 @@ int __must_check clk_bulk_get(struct device_d *dev, int num_clks, clks[i].clk = clk_get(dev, clks[i].id); if (IS_ERR(clks[i].clk)) { ret = PTR_ERR(clks[i].clk); + clks[i].clk = NULL; + + if (ret == -ENOENT && optional) + continue; + if (ret != -EPROBE_DEFER) dev_err(dev, "Failed to get clk '%s': %d\n", clks[i].id, ret); - clks[i].clk = NULL; + goto err; } } @@ -51,8 +57,21 @@ err: return ret; } + +int __must_check clk_bulk_get(struct device_d *dev, int num_clks, + struct clk_bulk_data *clks) +{ + return __clk_bulk_get(dev, num_clks, clks, false); +} EXPORT_SYMBOL(clk_bulk_get); +int __must_check clk_bulk_get_optional(struct device_d *dev, int num_clks, + struct clk_bulk_data *clks) +{ + return __clk_bulk_get(dev, num_clks, clks, true); +} +EXPORT_SYMBOL(clk_bulk_get_optional); + static int __must_check of_clk_bulk_get(struct device_node *np, int num_clks, struct clk_bulk_data *clks) { diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index e0f543bc1c..479ac5e8ef 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -12,85 +12,115 @@ #include <linux/err.h> struct clk_composite { - struct clk clk; + struct clk_hw hw; struct clk *mux_clk; struct clk *rate_clk; struct clk *gate_clk; }; -#define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk) +#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) -static int clk_composite_get_parent(struct clk *clk) +static int clk_composite_get_parent(struct clk_hw *hw) { - struct clk_composite *composite = to_clk_composite(clk); + struct clk_composite *composite = to_clk_composite(hw); struct clk *mux_clk = composite->mux_clk; + struct clk_hw *mux_hw = clk_to_clk_hw(mux_clk); - return mux_clk ? mux_clk->ops->get_parent(mux_clk) : 0; + return mux_clk ? mux_clk->ops->get_parent(mux_hw) : 0; } -static int clk_composite_set_parent(struct clk *clk, u8 index) +static int clk_composite_set_parent(struct clk_hw *hw, u8 index) { - struct clk_composite *composite = to_clk_composite(clk); + struct clk_composite *composite = to_clk_composite(hw); struct clk *mux_clk = composite->mux_clk; + struct clk_hw *mux_hw = clk_to_clk_hw(mux_clk); - return mux_clk ? mux_clk->ops->set_parent(mux_clk, index) : 0; + return mux_clk ? mux_clk->ops->set_parent(mux_hw, index) : 0; } -static unsigned long clk_composite_recalc_rate(struct clk *clk, +static unsigned long clk_composite_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_composite *composite = to_clk_composite(clk); + struct clk_composite *composite = to_clk_composite(hw); struct clk *rate_clk = composite->rate_clk; + struct clk_hw *rate_hw = clk_to_clk_hw(rate_clk); if (rate_clk) - return rate_clk->ops->recalc_rate(rate_clk, parent_rate); + return rate_clk->ops->recalc_rate(rate_hw, parent_rate); return parent_rate; } -static long clk_composite_round_rate(struct clk *clk, unsigned long rate, +static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { - struct clk_composite *composite = to_clk_composite(clk); + struct clk_composite *composite = to_clk_composite(hw); struct clk *rate_clk = composite->rate_clk; + struct clk *mux_clk = composite->mux_clk; + struct clk_hw *rate_hw = clk_to_clk_hw(rate_clk); + + if (rate_clk) + return rate_clk->ops->round_rate(rate_hw, rate, prate); - return rate_clk ? rate_clk->ops->round_rate(rate_clk, rate, prate) : 0; + if (!(hw->clk.flags & CLK_SET_RATE_NO_REPARENT) && + mux_clk && + mux_clk->ops->set_rate) + return mux_clk->ops->round_rate(clk_to_clk_hw(mux_clk), rate, prate); + + return *prate; } -static int clk_composite_set_rate(struct clk *clk, unsigned long rate, +static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_composite *composite = to_clk_composite(clk); + struct clk_composite *composite = to_clk_composite(hw); struct clk *rate_clk = composite->rate_clk; + struct clk *mux_clk = composite->mux_clk; + struct clk_hw *rate_hw = clk_to_clk_hw(rate_clk); - return rate_clk ? - rate_clk->ops->set_rate(rate_clk, rate, parent_rate) : 0; + /* + * When the rate clock is present use that to set the rate, + * otherwise try the mux clock. We currently do not support + * to find the best rate using a combination of both. + */ + if (rate_clk) + return rate_clk->ops->set_rate(rate_hw, rate, parent_rate); + + if (!(hw->clk.flags & CLK_SET_RATE_NO_REPARENT) && + mux_clk && + mux_clk->ops->set_rate) + return mux_clk->ops->set_rate(clk_to_clk_hw(mux_clk), rate, parent_rate); + + return 0; } -static int clk_composite_is_enabled(struct clk *clk) +static int clk_composite_is_enabled(struct clk_hw *hw) { - struct clk_composite *composite = to_clk_composite(clk); + struct clk_composite *composite = to_clk_composite(hw); struct clk *gate_clk = composite->gate_clk; + struct clk_hw *gate_hw = clk_to_clk_hw(gate_clk); - return gate_clk ? gate_clk->ops->is_enabled(gate_clk) : 0; + return gate_clk ? gate_clk->ops->is_enabled(gate_hw) : 0; } -static int clk_composite_enable(struct clk *clk) +static int clk_composite_enable(struct clk_hw *hw) { - struct clk_composite *composite = to_clk_composite(clk); + struct clk_composite *composite = to_clk_composite(hw); struct clk *gate_clk = composite->gate_clk; + struct clk_hw *gate_hw = clk_to_clk_hw(gate_clk); - return gate_clk ? gate_clk->ops->enable(gate_clk) : 0; + return gate_clk ? gate_clk->ops->enable(gate_hw) : 0; } -static void clk_composite_disable(struct clk *clk) +static void clk_composite_disable(struct clk_hw *hw) { - struct clk_composite *composite = to_clk_composite(clk); + struct clk_composite *composite = to_clk_composite(hw); struct clk *gate_clk = composite->gate_clk; + struct clk_hw *gate_hw = clk_to_clk_hw(gate_clk); if (gate_clk) - gate_clk->ops->disable(gate_clk); + gate_clk->ops->disable(gate_hw); } static struct clk_ops clk_composite_ops = { @@ -116,20 +146,26 @@ struct clk *clk_register_composite(const char *name, composite = xzalloc(sizeof(*composite)); - composite->clk.name = name; - composite->clk.ops = &clk_composite_ops; - composite->clk.flags = flags; - composite->clk.parent_names = parent_names; - composite->clk.num_parents = num_parents; + composite->hw.clk.name = name; + composite->hw.clk.ops = &clk_composite_ops; + composite->hw.clk.flags = flags; + composite->hw.clk.parent_names = parent_names; + composite->hw.clk.num_parents = num_parents; composite->mux_clk = mux_clk; composite->rate_clk = rate_clk; composite->gate_clk = gate_clk; - ret = clk_register(&composite->clk); + ret = bclk_register(&composite->hw.clk); if (ret) goto err; - return &composite->clk; + if (composite->mux_clk) { + composite->mux_clk->parents = composite->hw.clk.parents; + composite->mux_clk->parent_names = composite->hw.clk.parent_names; + composite->mux_clk->num_parents = composite->hw.clk.num_parents; + } + + return &composite->hw.clk; err: kfree(composite); diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 7119dd4e59..856b8a0648 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -92,10 +92,11 @@ unsigned long divider_recalc_rate(struct clk *clk, unsigned long parent_rate, return DIV_ROUND_UP_ULL((u64)parent_rate, div); } -static unsigned long clk_divider_recalc_rate(struct clk *clk, +static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_divider *divider = container_of(clk, struct clk_divider, clk); + struct clk *clk = clk_hw_to_clk(hw); + struct clk_divider *divider = container_of(hw, struct clk_divider, hw); unsigned int val; val = readl(divider->reg) >> divider->shift; @@ -233,13 +234,14 @@ long divider_round_rate(struct clk *clk, unsigned long rate, return DIV_ROUND_UP(*prate, div); } -static long clk_divider_round_rate(struct clk *clk, unsigned long rate, +static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { - struct clk_divider *divider = container_of(clk, struct clk_divider, clk); + struct clk *clk = clk_hw_to_clk(hw); + struct clk_divider *divider = to_clk_divider(hw); if (divider->flags & CLK_DIVIDER_READ_ONLY) - return clk_divider_recalc_rate(clk, *prate); + return clk_divider_recalc_rate(hw, *prate); return divider_round_rate(clk, rate, prate, divider->table, divider->width, divider->flags); @@ -261,10 +263,11 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate, return min_t(unsigned int, value, clk_div_mask(width)); } -static int clk_divider_set_rate(struct clk *clk, unsigned long rate, +static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_divider *divider = container_of(clk, struct clk_divider, clk); + struct clk *clk = clk_hw_to_clk(hw); + struct clk_divider *divider = to_clk_divider(hw); unsigned int value; u32 val; @@ -293,12 +296,16 @@ static int clk_divider_set_rate(struct clk *clk, unsigned long rate, return 0; } -struct clk_ops clk_divider_ops = { +const struct clk_ops clk_divider_ops = { .set_rate = clk_divider_set_rate, .recalc_rate = clk_divider_recalc_rate, .round_rate = clk_divider_round_rate, }; +const struct clk_ops clk_divider_ro_ops = { + .recalc_rate = clk_divider_recalc_rate, +}; + struct clk *clk_divider_alloc(const char *name, const char *parent, unsigned clk_flags, void __iomem *reg, u8 shift, u8 width, unsigned div_flags) @@ -310,18 +317,19 @@ struct clk *clk_divider_alloc(const char *name, const char *parent, div->width = width; div->parent = parent; div->flags = div_flags; - div->clk.ops = &clk_divider_ops; - div->clk.name = name; - div->clk.flags = clk_flags; - div->clk.parent_names = &div->parent; - div->clk.num_parents = 1; + div->hw.clk.ops = &clk_divider_ops; + div->hw.clk.name = name; + div->hw.clk.flags = clk_flags; + div->hw.clk.parent_names = &div->parent; + div->hw.clk.num_parents = 1; - return &div->clk; + return &div->hw.clk; } void clk_divider_free(struct clk *clk) { - struct clk_divider *d = container_of(clk, struct clk_divider, clk); + struct clk_hw *hw = clk_to_clk_hw(clk); + struct clk_divider *d = to_clk_divider(hw); free(d); } @@ -335,7 +343,7 @@ struct clk *clk_divider(const char *name, const char *parent, unsigned clk_flags d = clk_divider_alloc(name , parent, clk_flags, reg, shift, width, div_flags); - ret = clk_register(d); + ret = bclk_register(d); if (ret) { clk_divider_free(d); return ERR_PTR(ret); @@ -350,12 +358,15 @@ struct clk *clk_divider_one_based(const char *name, const char *parent, { struct clk_divider *div; struct clk *clk; + struct clk_hw *hw; clk = clk_divider(name, parent, clk_flags, reg, shift, width, div_flags); if (IS_ERR(clk)) return clk; - div = container_of(clk, struct clk_divider, clk); + hw = clk_to_clk_hw(clk); + div = to_clk_divider(hw); + div->flags |= CLK_DIVIDER_ONE_BASED; return clk; @@ -375,11 +386,11 @@ struct clk *clk_divider_table(const char *name, const char *parent, div->width = width; div->parent = parent; div->flags = div_flags; - div->clk.ops = &clk_divider_ops; - div->clk.name = name; - div->clk.flags = clk_flags; - div->clk.parent_names = &div->parent; - div->clk.num_parents = 1; + div->hw.clk.ops = &clk_divider_ops; + div->hw.clk.name = name; + div->hw.clk.flags = clk_flags; + div->hw.clk.parent_names = &div->parent; + div->hw.clk.num_parents = 1; div->table = table; for (clkt = div->table; clkt->div; clkt++) { @@ -390,11 +401,30 @@ struct clk *clk_divider_table(const char *name, const char *parent, div->table_size++; } - ret = clk_register(&div->clk); + ret = bclk_register(&div->hw.clk); if (ret) { free(div); return ERR_PTR(ret); } - return &div->clk; + return &div->hw.clk; +} + +struct clk *clk_register_divider_table(struct device_d *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock) +{ + return clk_divider_table(name, parent_name, flags, reg, shift, width, + table, clk_divider_flags); +} + +struct clk *clk_register_divider(struct device_d *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, spinlock_t *lock) +{ + return clk_divider(name, parent_name, flags, reg, shift, width, + clk_divider_flags); } diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index e7738775f8..fd4a3805f1 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -10,25 +10,19 @@ #include <linux/clk.h> #include <linux/err.h> -struct clk_fixed_factor { - struct clk clk; - int mult; - int div; - const char *parent; -}; - -static unsigned long clk_fixed_factor_recalc_rate(struct clk *clk, +static unsigned long clk_fixed_factor_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_fixed_factor *f = container_of(clk, struct clk_fixed_factor, clk); + struct clk_fixed_factor *f = to_clk_fixed_factor(hw); return (parent_rate / f->div) * f->mult; } -static long clk_factor_round_rate(struct clk *clk, unsigned long rate, +static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { - struct clk_fixed_factor *fix = container_of(clk, struct clk_fixed_factor, clk); + struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); + struct clk *clk = clk_hw_to_clk(hw); if (clk->flags & CLK_SET_RATE_PARENT) { unsigned long best_parent; @@ -40,10 +34,11 @@ static long clk_factor_round_rate(struct clk *clk, unsigned long rate, return (*prate / fix->div) * fix->mult; } -static int clk_factor_set_rate(struct clk *clk, unsigned long rate, +static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_fixed_factor *fix = container_of(clk, struct clk_fixed_factor, clk); + struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); + struct clk *clk = clk_hw_to_clk(hw); if (clk->flags & CLK_SET_RATE_PARENT) { return clk_set_rate(clk_get_parent(clk), rate * fix->div / fix->mult); @@ -52,7 +47,7 @@ static int clk_factor_set_rate(struct clk *clk, unsigned long rate, return 0; } -static struct clk_ops clk_fixed_factor_ops = { +struct clk_ops clk_fixed_factor_ops = { .set_rate = clk_factor_set_rate, .round_rate = clk_factor_round_rate, .recalc_rate = clk_fixed_factor_recalc_rate, @@ -67,19 +62,26 @@ struct clk *clk_fixed_factor(const char *name, f->mult = mult; f->div = div; f->parent = parent; - f->clk.ops = &clk_fixed_factor_ops; - f->clk.name = name; - f->clk.flags = flags; - f->clk.parent_names = &f->parent; - f->clk.num_parents = 1; + f->hw.clk.ops = &clk_fixed_factor_ops; + f->hw.clk.name = name; + f->hw.clk.flags = flags; + f->hw.clk.parent_names = &f->parent; + f->hw.clk.num_parents = 1; - ret = clk_register(&f->clk); + ret = bclk_register(&f->hw.clk); if (ret) { free(f); return ERR_PTR(ret); } - return &f->clk; + return &f->hw.clk; +} + +struct clk *clk_register_fixed_factor(struct device_d *dev, const char *name, + const char *parent_name, unsigned long flags, + unsigned int mult, unsigned int div) +{ + return clk_fixed_factor(name, parent_name, mult, div, flags); } /** diff --git a/drivers/clk/clk-fixed.c b/drivers/clk/clk-fixed.c index d7ac59c4d4..b961c382ec 100644 --- a/drivers/clk/clk-fixed.c +++ b/drivers/clk/clk-fixed.c @@ -10,14 +10,14 @@ #include <linux/err.h> struct clk_fixed { - struct clk clk; + struct clk_hw hw; unsigned long rate; }; -static unsigned long clk_fixed_recalc_rate(struct clk *clk, +static unsigned long clk_fixed_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_fixed *fix = container_of(clk, struct clk_fixed, clk); + struct clk_fixed *fix = container_of(hw, struct clk_fixed, hw); return fix->rate; } @@ -36,27 +36,27 @@ struct clk *clk_register_fixed_rate(const char *name, int ret; fix->rate = rate; - fix->clk.ops = &clk_fixed_ops; - fix->clk.name = name; - fix->clk.flags = flags; + fix->hw.clk.ops = &clk_fixed_ops; + fix->hw.clk.name = name; + fix->hw.clk.flags = flags; if (parent_name) { parent_names = kzalloc(sizeof(const char *), GFP_KERNEL); if (!parent_names) return ERR_PTR(-ENOMEM); - fix->clk.parent_names = parent_names; - fix->clk.num_parents = 1; + fix->hw.clk.parent_names = parent_names; + fix->hw.clk.num_parents = 1; } - ret = clk_register(&fix->clk); + ret = bclk_register(&fix->hw.clk); if (ret) { free(parent_names); free(fix); return ERR_PTR(ret); } - return &fix->clk; + return &fix->hw.clk; } /** diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index 6f0763b05f..3d96360025 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -1,86 +1,129 @@ -// SPDX-License-Identifier: GPL-2.0-only +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2014 Intel Corporation * * Adjustable fractional divider clock implementation. * Output rate = (m / n) * parent_rate. + * Uses rational best approximation algorithm. */ #include <common.h> #include <io.h> #include <malloc.h> #include <linux/clk.h> +#include <linux/spinlock.h> #include <linux/err.h> #include <linux/gcd.h> #include <linux/math64.h> +#include <linux/rational.h> #include <linux/barebox-wrapper.h> -#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, clk) +static inline u32 clk_fd_readl(struct clk_fractional_divider *fd) +{ + if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN) + return ioread32be(fd->reg); -struct clk_fractional_divider { - struct clk clk; - void __iomem *reg; - u8 mshift; - u32 mmask; - u8 nshift; - u32 nmask; - u8 flags; -}; + return readl(fd->reg); +} + +static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val) +{ + if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN) + iowrite32be(val, fd->reg); + else + writel(val, fd->reg); +} -static unsigned long clk_fd_recalc_rate(struct clk *hw, +static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_fractional_divider *fd = to_clk_fd(hw); - u32 val, m, n; + unsigned long m, n; + u32 val; u64 ret; - val = readl(fd->reg); + val = clk_fd_readl(fd); m = (val & fd->mmask) >> fd->mshift; n = (val & fd->nmask) >> fd->nshift; + if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) { + m++; + n++; + } + + if (!n || !m) + return parent_rate; + ret = (u64)parent_rate * m; do_div(ret, n); return ret; } -static long clk_fd_round_rate(struct clk *hw, unsigned long rate, - unsigned long *prate) +static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate, + unsigned long *m, unsigned long *n) { struct clk_fractional_divider *fd = to_clk_fd(hw); - unsigned maxn = (fd->nmask >> fd->nshift) + 1; - unsigned div; + unsigned long scale; + + /* + * Get rate closer to *parent_rate to guarantee there is no overflow + * for m and n. In the result it will be the nearest rate left shifted + * by (scale - fd->nwidth) bits. + */ + scale = fls_long(*parent_rate / rate - 1); + if (scale > fd->nwidth) + rate <<= scale - fd->nwidth; + + rational_best_approximation(rate, *parent_rate, + GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), + m, n); +} - if (!rate || rate >= *prate) - return *prate; +static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct clk *clk = clk_hw_to_clk(hw); + struct clk_fractional_divider *fd = to_clk_fd(hw); + unsigned long m, n; + u64 ret; - div = gcd(*prate, rate); + if (!rate || (!(clk->flags & CLK_SET_RATE_PARENT) && rate >= *parent_rate)) + return *parent_rate; - while ((*prate / div) > maxn) { - div <<= 1; - rate <<= 1; - } + if (fd->approximation) + fd->approximation(hw, rate, parent_rate, &m, &n); + else + clk_fd_general_approximation(hw, rate, parent_rate, &m, &n); - return rate; + ret = (u64)*parent_rate * m; + do_div(ret, n); + + return ret; } -static int clk_fd_set_rate(struct clk *hw, unsigned long rate, +static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_fractional_divider *fd = to_clk_fd(hw); - unsigned long div; - unsigned n, m; + unsigned long m, n; u32 val; - div = gcd(parent_rate, rate); - m = rate / div; - n = parent_rate / div; + rational_best_approximation(rate, parent_rate, + GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), + &m, &n); + + if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) { + m--; + n--; + } - val = readl(fd->reg); + val = clk_fd_readl(fd); val &= ~(fd->mmask | fd->nmask); val |= (m << fd->mshift) | (n << fd->nshift); - writel(val, fd->reg); + clk_fd_writel(fd, val); return 0; } @@ -103,22 +146,24 @@ struct clk *clk_fractional_divider_alloc( fd->reg = reg; fd->mshift = mshift; - fd->mmask = (BIT(mwidth) - 1) << mshift; + fd->mwidth = mwidth; + fd->mmask = GENMASK(mwidth - 1, 0) << mshift; fd->nshift = nshift; - fd->nmask = (BIT(nwidth) - 1) << nshift; + fd->nwidth = nwidth; + fd->nmask = GENMASK(nwidth - 1, 0) << nshift; fd->flags = clk_divider_flags; - fd->clk.name = name; - fd->clk.ops = &clk_fractional_divider_ops; - fd->clk.flags = flags; - fd->clk.parent_names = parent_name ? &parent_name : NULL; - fd->clk.num_parents = parent_name ? 1 : 0; + fd->hw.clk.name = name; + fd->hw.clk.ops = &clk_fractional_divider_ops; + fd->hw.clk.flags = flags; + fd->hw.clk.parent_names = parent_name ? &parent_name : NULL; + fd->hw.clk.num_parents = parent_name ? 1 : 0; - return &fd->clk; + return &fd->hw.clk; } void clk_fractional_divider_free(struct clk *clk_fd) { - struct clk_fractional_divider *fd = to_clk_fd(clk_fd); + struct clk_fractional_divider *fd = to_clk_fd(clk_to_clk_hw(clk_fd)); free(fd); } @@ -138,7 +183,7 @@ struct clk *clk_fractional_divider( if (IS_ERR(fd)) return fd; - ret = clk_register(fd); + ret = bclk_register(fd); if (ret) { clk_fractional_divider_free(fd); return ERR_PTR(ret); diff --git a/drivers/clk/clk-gate-shared.c b/drivers/clk/clk-gate-shared.c index 54c002e836..069f6975b1 100644 --- a/drivers/clk/clk-gate-shared.c +++ b/drivers/clk/clk-gate-shared.c @@ -11,13 +11,13 @@ #include <linux/err.h> struct clk_gate_shared { - struct clk clk; + struct clk_hw hw; const char *parent; const char *companion_gate; struct clk *companion_clk; }; -#define to_clk_gate_shared(_clk) container_of(_clk, struct clk_gate_shared, clk) +#define to_clk_gate_shared(_hw) container_of(_hw, struct clk_gate_shared, hw) static struct clk *lookup_companion(struct clk_gate_shared *g) { @@ -30,23 +30,23 @@ static struct clk *lookup_companion(struct clk_gate_shared *g) return g->companion_clk; } -static int clk_gate_shared_enable(struct clk *clk) +static int clk_gate_shared_enable(struct clk_hw *hw) { - struct clk_gate_shared *g = to_clk_gate_shared(clk); + struct clk_gate_shared *g = to_clk_gate_shared(hw); return clk_enable(lookup_companion(g)); } -static void clk_gate_shared_disable(struct clk *clk) +static void clk_gate_shared_disable(struct clk_hw *hw) { - struct clk_gate_shared *g = to_clk_gate_shared(clk); + struct clk_gate_shared *g = to_clk_gate_shared(hw); clk_disable(lookup_companion(g)); } -static int clk_gate_shared_is_enabled(struct clk *clk) +static int clk_gate_shared_is_enabled(struct clk_hw *hw) { - struct clk_gate_shared *g = to_clk_gate_shared(clk); + struct clk_gate_shared *g = to_clk_gate_shared(hw); return clk_is_enabled(lookup_companion(g)); } @@ -67,18 +67,19 @@ static struct clk *clk_gate_shared_alloc(const char *name, const char *parent, g->parent = parent; g->companion_gate = companion; g->companion_clk = ERR_PTR(-EINVAL); - g->clk.ops = &clk_gate_shared_ops; - g->clk.name = name; - g->clk.flags = flags; - g->clk.parent_names = &g->parent; - g->clk.num_parents = 1; + g->hw.clk.ops = &clk_gate_shared_ops; + g->hw.clk.name = name; + g->hw.clk.flags = flags; + g->hw.clk.parent_names = &g->parent; + g->hw.clk.num_parents = 1; - return &g->clk; + return &g->hw.clk; } static void clk_gate_shared_free(struct clk *clk) { - struct clk_gate_shared *g = to_clk_gate_shared(clk); + struct clk_hw *hw = clk_to_clk_hw(clk); + struct clk_gate_shared *g = to_clk_gate_shared(hw); free(g); } @@ -103,7 +104,7 @@ struct clk *clk_gate_shared(const char *name, const char *parent, const char *co clk = clk_gate_shared_alloc(name , parent, companion, flags); - ret = clk_register(clk); + ret = bclk_register(clk); if (ret) { clk_gate_shared_free(clk); return ERR_PTR(ret); diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 59dd643b99..3cfd707238 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -10,10 +10,10 @@ #include <linux/clk.h> #include <linux/err.h> -static void clk_gate_endisable(struct clk *clk, int enable) +static void clk_gate_endisable(struct clk_hw *hw, int enable) { - struct clk_gate *gate = container_of(clk, struct clk_gate, clk); - int set = gate->flags & CLK_GATE_INVERTED ? 1 : 0; + struct clk_gate *gate = container_of(hw, struct clk_gate, hw); + int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; u32 val; set ^= enable; @@ -34,29 +34,29 @@ static void clk_gate_endisable(struct clk *clk, int enable) writel(val, gate->reg); } -static int clk_gate_enable(struct clk *clk) +static int clk_gate_enable(struct clk_hw *hw) { - clk_gate_endisable(clk, 1); + clk_gate_endisable(hw, 1); return 0; } -static void clk_gate_disable(struct clk *clk) +static void clk_gate_disable(struct clk_hw *hw) { - clk_gate_endisable(clk, 0); + clk_gate_endisable(hw, 0); } -int clk_gate_is_enabled(struct clk *clk) +int clk_gate_is_enabled(struct clk_hw *hw) { - struct clk_gate *g = container_of(clk, struct clk_gate, clk); + struct clk_gate *g = container_of(hw, struct clk_gate, hw); u32 val; val = readl(g->reg); if (val & (1 << g->shift)) - return g->flags & CLK_GATE_INVERTED ? 0 : 1; + return g->flags & CLK_GATE_SET_TO_DISABLE ? 0 : 1; else - return g->flags & CLK_GATE_INVERTED ? 1 : 0; + return g->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; } struct clk_ops clk_gate_ops = { @@ -75,19 +75,20 @@ struct clk *clk_gate_alloc(const char *name, const char *parent, g->parent = parent; g->reg = reg; g->shift = shift; - g->clk.ops = &clk_gate_ops; - g->clk.name = name; - g->clk.flags = flags; - g->clk.parent_names = &g->parent; - g->clk.num_parents = 1; + g->hw.clk.ops = &clk_gate_ops; + g->hw.clk.name = name; + g->hw.clk.flags = flags; + g->hw.clk.parent_names = &g->parent; + g->hw.clk.num_parents = 1; g->flags = clk_gate_flags; - return &g->clk; + return &g->hw.clk; } void clk_gate_free(struct clk *clk_gate) { - struct clk_gate *g = to_clk_gate(clk_gate); + struct clk_hw *hw = clk_to_clk_hw(clk_gate); + struct clk_gate *g = to_clk_gate(hw); free(g); } @@ -100,9 +101,10 @@ struct clk *clk_gate(const char *name, const char *parent, void __iomem *reg, g = clk_gate_alloc(name , parent, reg, shift, flags, clk_gate_flags); - ret = clk_register(g); + ret = bclk_register(g); if (ret) { - free(to_clk_gate(g)); + struct clk_hw *hw = clk_to_clk_hw(g); + free(to_clk_gate(hw)); return ERR_PTR(ret); } @@ -112,5 +114,13 @@ struct clk *clk_gate(const char *name, const char *parent, void __iomem *reg, struct clk *clk_gate_inverted(const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned flags) { - return clk_gate(name, parent, reg, shift, flags, CLK_GATE_INVERTED); + return clk_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE); +} + +struct clk *clk_register_gate(struct device_d *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + return clk_gate(name, parent_name, reg, bit_idx, flags, clk_gate_flags); } diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c index 1345fbc9ea..6ac2e820fa 100644 --- a/drivers/clk/clk-gpio.c +++ b/drivers/clk/clk-gpio.c @@ -14,30 +14,30 @@ #include <init.h> struct clk_gpio { - struct clk clk; + struct clk_hw hw; const char *parent; int gpio; }; -#define to_clk_gpio(_clk) container_of(_clk, struct clk_gpio, clk) +#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) -static int clk_gpio_enable(struct clk *clk) +static int clk_gpio_enable(struct clk_hw *hw) { - struct clk_gpio *clk_gpio = to_clk_gpio(clk); + struct clk_gpio *clk_gpio = to_clk_gpio(hw); gpio_set_active(clk_gpio->gpio, true); return 0; } -static void clk_gpio_disable(struct clk *clk) +static void clk_gpio_disable(struct clk_hw *hw) { - struct clk_gpio *clk_gpio = to_clk_gpio(clk); + struct clk_gpio *clk_gpio = to_clk_gpio(hw); gpio_set_active(clk_gpio->gpio, false); } -static int clk_gpio_is_enabled(struct clk *clk) +static int clk_gpio_is_enabled(struct clk_hw *hw) { - struct clk_gpio *clk_gpio = to_clk_gpio(clk); + struct clk_gpio *clk_gpio = to_clk_gpio(hw); return gpio_is_active(clk_gpio->gpio); } @@ -67,13 +67,13 @@ static int of_gpio_clk_setup(struct device_node *node) goto no_parent; } - clk_gpio->clk.ops = &clk_gpio_ops; - clk_gpio->clk.parent_names = &clk_gpio->parent; - clk_gpio->clk.num_parents = 1; + clk_gpio->hw.clk.ops = &clk_gpio_ops; + clk_gpio->hw.clk.parent_names = &clk_gpio->parent; + clk_gpio->hw.clk.num_parents = 1; - clk_gpio->clk.name = node->name; + clk_gpio->hw.clk.name = node->name; of_property_read_string(node, "clock-output-names", - &clk_gpio->clk.name); + &clk_gpio->hw.clk.name); ret = of_get_named_gpio_flags(node, "enable-gpios", 0, &of_flags); @@ -86,15 +86,15 @@ static int of_gpio_clk_setup(struct device_node *node) flags = GPIOF_OUT_INIT_ACTIVE; if (of_flags & OF_GPIO_ACTIVE_LOW) flags |= GPIOF_ACTIVE_LOW; - ret = gpio_request_one(clk_gpio->gpio, flags, clk_gpio->clk.name); + ret = gpio_request_one(clk_gpio->gpio, flags, clk_gpio->hw.clk.name); if (ret) goto no_request; - ret = clk_register(&clk_gpio->clk); + ret = bclk_register(&clk_gpio->hw.clk); if (ret) goto no_register; - return of_clk_add_provider(node, of_clk_src_simple_get, &clk_gpio->clk); + return of_clk_add_provider(node, of_clk_src_simple_get, &clk_gpio->hw.clk); no_register: gpio_free(clk_gpio->gpio); diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index a4743c51b0..d8c09e4a75 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -10,21 +10,21 @@ #include <linux/clk.h> #include <linux/err.h> -static int clk_mux_get_parent(struct clk *clk) +static int clk_mux_get_parent(struct clk_hw *hw) { - struct clk_mux *m = container_of(clk, struct clk_mux, clk); + struct clk_mux *m = to_clk_mux(hw); int idx = readl(m->reg) >> m->shift & ((1 << m->width) - 1); return idx; } -static int clk_mux_set_parent(struct clk *clk, u8 idx) +static int clk_mux_set_parent(struct clk_hw *hw, u8 idx) { - struct clk_mux *m = container_of(clk, struct clk_mux, clk); + struct clk_mux *m = to_clk_mux(hw); u32 val; if (m->flags & CLK_MUX_READ_ONLY) { - if (clk_mux_get_parent(clk) != idx) + if (clk_mux_get_parent(hw) != idx) return -EPERM; else return 0; @@ -34,20 +34,102 @@ static int clk_mux_set_parent(struct clk *clk, u8 idx) val &= ~(((1 << m->width) - 1) << m->shift); val |= idx << m->shift; - if (clk->flags & CLK_MUX_HIWORD_MASK) + if (m->flags & CLK_MUX_HIWORD_MASK) val |= ((1 << m->width) - 1) << (m->shift + 16); writel(val, m->reg); return 0; } -struct clk_ops clk_mux_ops = { - .set_rate = clk_parent_set_rate, - .round_rate = clk_parent_round_rate, +static struct clk *clk_get_parent_index(struct clk *clk, int num) +{ + if (num >= clk->num_parents) + return NULL; + + if (clk->parents[num]) + return clk->parents[num]; + + clk->parents[num] = clk_lookup(clk->parent_names[num]); + + return clk->parents[num]; +} + +static struct clk *clk_mux_best_parent(struct clk *mux, unsigned long rate, + unsigned long *rrate) +{ + struct clk *bestparent = NULL; + long bestrate = LONG_MAX; + int i; + + for (i = 0; i < mux->num_parents; i++) { + struct clk *parent = clk_get_parent_index(mux, i); + unsigned long r; + + if (IS_ERR_OR_NULL(parent)) + continue; + + if (mux->flags & CLK_SET_RATE_PARENT) + r = clk_round_rate(parent, rate); + else + r = clk_get_rate(parent); + + if (abs((long)rate - r) < abs((long)rate - bestrate)) { + bestrate = r; + bestparent = parent; + } + } + + *rrate = bestrate; + + return bestparent; +} + +static long clk_mux_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk *clk = clk_hw_to_clk(hw); + unsigned long rrate; + struct clk *bestparent; + + if (clk->flags & CLK_SET_RATE_NO_REPARENT) + return *prate; + + bestparent = clk_mux_best_parent(clk, rate, &rrate); + + return rrate; +} + +static int clk_mux_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk *clk = clk_hw_to_clk(hw); + struct clk *parent; + unsigned long rrate; + int ret; + + if (clk->flags & CLK_SET_RATE_NO_REPARENT) + return 0; + + parent = clk_mux_best_parent(clk, rate, &rrate); + + ret = clk_set_parent(clk, parent); + if (ret) + return ret; + + return clk_set_rate(parent, rate); +} + +const struct clk_ops clk_mux_ops = { + .set_rate = clk_mux_set_rate, + .round_rate = clk_mux_round_rate, .get_parent = clk_mux_get_parent, .set_parent = clk_mux_set_parent, }; +const struct clk_ops clk_mux_ro_ops = { + .get_parent = clk_mux_get_parent, +}; + struct clk *clk_mux_alloc(const char *name, unsigned clk_flags, void __iomem *reg, u8 shift, u8 width, const char * const *parents, u8 num_parents, unsigned mux_flags) @@ -58,18 +140,19 @@ struct clk *clk_mux_alloc(const char *name, unsigned clk_flags, void __iomem *re m->shift = shift; m->width = width; m->flags = mux_flags; - m->clk.ops = &clk_mux_ops; - m->clk.name = name; - m->clk.flags = clk_flags; - m->clk.parent_names = parents; - m->clk.num_parents = num_parents; + m->hw.clk.ops = &clk_mux_ops; + m->hw.clk.name = name; + m->hw.clk.flags = clk_flags; + m->hw.clk.parent_names = parents; + m->hw.clk.num_parents = num_parents; - return &m->clk; + return &m->hw.clk; } void clk_mux_free(struct clk *clk_mux) { - struct clk_mux *m = to_clk_mux(clk_mux); + struct clk_hw *hw = clk_to_clk_hw(clk_mux); + struct clk_mux *m = to_clk_mux(hw); free(m); } @@ -84,11 +167,22 @@ struct clk *clk_mux(const char *name, unsigned clk_flags, void __iomem *reg, m = clk_mux_alloc(name, clk_flags, reg, shift, width, parents, num_parents, mux_flags); - ret = clk_register(m); + ret = bclk_register(m); if (ret) { - free(to_clk_mux(m)); + struct clk_hw *hw = clk_to_clk_hw(m); + free(to_clk_mux(hw)); return ERR_PTR(ret); } return m; } + +struct clk *clk_register_mux(struct device_d *dev, const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_mux_flags, spinlock_t *lock) +{ + return clk_mux(name, flags, reg, shift, width, parent_names, + num_parents, clk_mux_flags); +} diff --git a/drivers/clk/clk-qoric.c b/drivers/clk/clk-qoric.c index 5bf677d94e..f7dbf7230d 100644 --- a/drivers/clk/clk-qoric.c +++ b/drivers/clk/clk-qoric.c @@ -29,7 +29,7 @@ #define CGB_PLL2 5 struct clockgen_pll_div { - struct clk *clk; + struct clk_hw *hw; char name[32]; }; @@ -254,20 +254,20 @@ static const struct clockgen_chipinfo chipinfo_ls2080a = { }; struct mux_hwclock { - struct clk clk; + struct clk_hw hw; struct clockgen *cg; const struct clockgen_muxinfo *info; u32 __iomem *reg; int num_parents; }; -#define to_mux_hwclock(p) container_of(p, struct mux_hwclock, clk) +#define to_mux_hwclock(p) container_of(p, struct mux_hwclock, hw) #define CLKSEL_MASK 0x78000000 #define CLKSEL_SHIFT 27 -static int mux_set_parent(struct clk *clk, u8 idx) +static int mux_set_parent(struct clk_hw *hw, u8 idx) { - struct mux_hwclock *hwc = to_mux_hwclock(clk); + struct mux_hwclock *hwc = to_mux_hwclock(hw); if (idx >= hwc->num_parents) return -EINVAL; @@ -277,9 +277,9 @@ static int mux_set_parent(struct clk *clk, u8 idx) return 0; } -static int mux_get_parent(struct clk *clk) +static int mux_get_parent(struct clk_hw *hw) { - struct mux_hwclock *hwc = to_mux_hwclock(clk); + struct mux_hwclock *hwc = to_mux_hwclock(hw); return (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; } @@ -318,7 +318,7 @@ static struct clk * __init create_mux_common(struct clockgen *cg, const struct clk_ops *ops, const char *fmt, int idx) { - struct clk *clk = &hwc->clk; + struct clk_hw *hw = &hwc->hw; const struct clockgen_pll_div *div; const char **parent_names; int i, ret; @@ -333,20 +333,20 @@ static struct clk * __init create_mux_common(struct clockgen *cg, parent_names[i] = div->name; } - clk->name = xasprintf(fmt, idx);; - clk->ops = ops; - clk->parent_names = parent_names; - clk->num_parents = hwc->num_parents = i; + hw->clk.name = xasprintf(fmt, idx);; + hw->clk.ops = ops; + hw->clk.parent_names = parent_names; + hw->clk.num_parents = hwc->num_parents = i; hwc->cg = cg; - ret = clk_register(clk); + ret = bclk_register(&hw->clk); if (ret) { - pr_err("%s: Couldn't register %s: %d\n", __func__, clk->name, ret); + pr_err("%s: Couldn't register %s: %d\n", __func__, clk_hw_get_name(hw), ret); kfree(hwc); return NULL; } - return clk; + return &hw->clk; } static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) @@ -499,7 +499,7 @@ static void __init create_one_pll(struct clockgen *cg, int idx) continue; } - pll->div[i].clk = clk; + pll->div[i].hw = clk_to_clk_hw(clk); } } @@ -551,7 +551,7 @@ static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data) pll = &cg->pll[PLATFORM_PLL]; if (idx >= ARRAY_SIZE(pll->div)) goto bad_args; - clk = pll->div[idx].clk; + clk = clk_hw_to_clk(pll->div[idx].hw); break; case 5: if (idx != 0) diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index 2380bd0c21..7ba71b4592 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -285,7 +285,7 @@ static const struct clk_div_table ck_trace_div_table[] = { struct stm32_mmux { u8 nbr_clk; - struct clk *hws[MAX_MUX_CLK]; + struct clk_hw *hws[MAX_MUX_CLK]; }; struct stm32_clk_mmux { @@ -419,19 +419,19 @@ _clk_hw_register_mux(void __iomem *base, /* MP1 Gate clock with set & clear registers */ -static int mp1_gate_clk_enable(struct clk *clk) +static int mp1_gate_clk_enable(struct clk_hw *hw) { - if (!clk_gate_ops.is_enabled(clk)) - clk_gate_ops.enable(clk); + if (!clk_gate_ops.is_enabled(hw)) + clk_gate_ops.enable(hw); return 0; } -static void mp1_gate_clk_disable(struct clk *clk) +static void mp1_gate_clk_disable(struct clk_hw *hw) { - struct clk_gate *gate = to_clk_gate(clk); + struct clk_gate *gate = to_clk_gate(hw); - if (clk_gate_ops.is_enabled(clk)) { + if (clk_gate_ops.is_enabled(hw)) { writel(BIT(gate->shift), gate->reg + RCC_CLR); } } @@ -442,12 +442,12 @@ static const struct clk_ops mp1_gate_clk_ops = { .is_enabled = clk_gate_is_enabled, }; -static struct clk *_get_stm32_mux(void __iomem *base, +static struct clk_hw *_get_stm32_mux(void __iomem *base, const struct stm32_mux_cfg *cfg) { struct stm32_clk_mmux *mmux; struct clk_mux *mux; - struct clk *mux_hw; + struct clk_hw *mux_hw; if (cfg->mmux) { mmux = kzalloc(sizeof(*mmux), GFP_KERNEL); @@ -458,7 +458,7 @@ static struct clk *_get_stm32_mux(void __iomem *base, mmux->mux.shift = cfg->mux->shift; mmux->mux.width = cfg->mux->width; mmux->mmux = cfg->mmux; - mux_hw = &mmux->mux.clk; + mux_hw = &mmux->mux.hw; cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw; mux = &mmux->mux; } else { @@ -469,18 +469,18 @@ static struct clk *_get_stm32_mux(void __iomem *base, mux->reg = cfg->mux->reg_off + base; mux->shift = cfg->mux->shift; mux->width = cfg->mux->width; - mux_hw = &mux->clk; + mux_hw = &mux->hw; } if (cfg->ops) - mux->clk.ops = cfg->ops; + mux->hw.clk.ops = cfg->ops; else - mux->clk.ops = &clk_mux_ops; + mux->hw.clk.ops = &clk_mux_ops; return mux_hw; } -static struct clk *_get_stm32_div(void __iomem *base, +static struct clk_hw *_get_stm32_div(void __iomem *base, const struct stm32_div_cfg *cfg) { struct clk_divider *div; @@ -496,11 +496,11 @@ static struct clk *_get_stm32_div(void __iomem *base, div->table = cfg->div->table; if (cfg->ops) - div->clk.ops = cfg->ops; + div->hw.clk.ops = cfg->ops; else - div->clk.ops = &clk_divider_ops; + div->hw.clk.ops = &clk_divider_ops; - return &div->clk; + return &div->hw; } static struct clk_gate * @@ -535,9 +535,9 @@ _get_stm32_gate(void __iomem *base, } if (cfg->ops) - gate->clk.ops = cfg->ops; + gate->hw.clk.ops = cfg->ops; else - gate->clk.ops = &clk_gate_ops; + gate->hw.clk.ops = &clk_gate_ops; return gate; } @@ -558,13 +558,13 @@ clk_stm32_register_gate_ops(const char *name, return ERR_PTR(-ENOMEM); gate->parent = parent_name; - clk = &gate->clk; + clk = &gate->hw.clk; clk->name = name; clk->parent_names = &gate->parent; clk->num_parents = 1; clk->flags = flags; - ret = clk_register(clk); + ret = bclk_register(clk); if (ret) clk = ERR_PTR(ret); @@ -577,7 +577,7 @@ clk_stm32_register_composite(const char *name, const char * const *parent_names, const struct stm32_composite_cfg *cfg, unsigned long flags) { - struct clk *mux_hw, *div_hw, *gate_hw; + struct clk_hw *mux_hw, *div_hw, *gate_hw; struct clk_gate *gate; mux_hw = NULL; @@ -592,36 +592,36 @@ clk_stm32_register_composite(const char *name, const char * const *parent_names, if (cfg->gate) { gate = _get_stm32_gate(base, cfg->gate); - gate_hw = &gate->clk; + gate_hw = &gate->hw; } return clk_register_composite(name, parent_names, num_parents, - mux_hw, div_hw, gate_hw, flags); + &mux_hw->clk, &div_hw->clk, &gate_hw->clk, flags); } #define to_clk_mgate(_gate) container_of(_gate, struct stm32_clk_mgate, gate) -static int mp1_mgate_clk_enable(struct clk *clk) +static int mp1_mgate_clk_enable(struct clk_hw *hw) { - struct clk_gate *gate = to_clk_gate(clk); + struct clk_gate *gate = to_clk_gate(hw); struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate); clk_mgate->mgate->flag |= clk_mgate->mask; - mp1_gate_clk_enable(clk); + mp1_gate_clk_enable(hw); return 0; } -static void mp1_mgate_clk_disable(struct clk *clk) +static void mp1_mgate_clk_disable(struct clk_hw *hw) { - struct clk_gate *gate = to_clk_gate(clk); + struct clk_gate *gate = to_clk_gate(hw); struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate); clk_mgate->mgate->flag &= ~clk_mgate->mask; if (clk_mgate->mgate->flag == 0) - mp1_gate_clk_disable(clk); + mp1_gate_clk_disable(hw); } static const struct clk_ops mp1_mgate_clk_ops = { @@ -633,26 +633,26 @@ static const struct clk_ops mp1_mgate_clk_ops = { #define to_clk_mmux(_mux) container_of(_mux, struct stm32_clk_mmux, mux) -static int clk_mmux_get_parent(struct clk *clk) +static int clk_mmux_get_parent(struct clk_hw *hw) { - return clk_mux_ops.get_parent(clk); + return clk_mux_ops.get_parent(hw); } -static int clk_mmux_set_parent(struct clk *clk, u8 index) +static int clk_mmux_set_parent(struct clk_hw *hw, u8 index) { - struct clk_mux *mux = to_clk_mux(clk); + struct clk_mux *mux = to_clk_mux(hw); struct stm32_clk_mmux *clk_mmux = to_clk_mmux(mux); - struct clk *parent; + struct clk_hw *hwp; int ret, n; - ret = clk_mux_ops.set_parent(clk, index); + ret = clk_mux_ops.set_parent(hw, index); if (ret) return ret; - parent = clk_get_parent(clk); + hwp = clk_hw_get_parent(hw); for (n = 0; n < clk_mmux->mmux->nbr_clk; n++) - clk_set_parent(clk_mmux->mmux->hws[n], parent); + clk_hw_set_parent(clk_mmux->mmux->hws[n], hw); return 0; } @@ -691,8 +691,9 @@ static int __pll_is_enabled(struct clk *clk) #define TIMEOUT 5 -static int pll_enable(struct clk *clk) +static int pll_enable(struct clk_hw *hw) { + struct clk *clk = clk_hw_to_clk(hw); struct stm32_pll_obj *clk_elem = to_pll(clk); u32 reg; unsigned int timeout = TIMEOUT; @@ -722,8 +723,9 @@ unlock: return bit_status; } -static void pll_disable(struct clk *clk) +static void pll_disable(struct clk_hw *hw) { + struct clk *clk = clk_hw_to_clk(hw); struct stm32_pll_obj *clk_elem = to_pll(clk); u32 reg; @@ -744,9 +746,10 @@ static u32 pll_frac_val(struct clk *clk) return frac; } -static unsigned long pll_recalc_rate(struct clk *clk, +static unsigned long pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { + struct clk *clk = clk_hw_to_clk(hw); struct stm32_pll_obj *clk_elem = to_pll(clk); u32 reg; u32 frac, divm, divn; @@ -769,8 +772,9 @@ static unsigned long pll_recalc_rate(struct clk *clk, return rate + rate_frac; } -static int pll_is_enabled(struct clk *clk) +static int pll_is_enabled(struct clk_hw *hw) { + struct clk *clk = clk_hw_to_clk(hw); int ret; ret = __pll_is_enabled(clk); @@ -810,7 +814,7 @@ static struct clk *clk_register_pll(const char *name, element->reg = reg; - err = clk_register(clk); + err = bclk_register(clk); if (err) { kfree(element); @@ -852,17 +856,19 @@ static unsigned long __bestmult(struct clk *clk, unsigned long rate, return mult; } -static long timer_ker_round_rate(struct clk *clk, unsigned long rate, +static long timer_ker_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { + struct clk *clk = clk_hw_to_clk(hw); unsigned long factor = __bestmult(clk, rate, *parent_rate); return *parent_rate * factor; } -static int timer_ker_set_rate(struct clk *clk, unsigned long rate, +static int timer_ker_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { + struct clk *clk = clk_hw_to_clk(hw); struct timer_cker *tim_ker = to_timer_cker(clk); unsigned long factor = __bestmult(clk, rate, parent_rate); int ret = 0; @@ -883,10 +889,11 @@ static int timer_ker_set_rate(struct clk *clk, unsigned long rate, return ret; } -static unsigned long timer_ker_recalc_rate(struct clk *hw, +static unsigned long timer_ker_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct timer_cker *tim_ker = to_timer_cker(hw); + struct clk *clk = clk_hw_to_clk(hw); + struct timer_cker *tim_ker = to_timer_cker(clk); u32 prescaler, timpre; u32 mul; @@ -934,7 +941,7 @@ static struct clk *clk_register_cktim(const char *name, tim_ker->apbdiv = apbdiv; tim_ker->timpre = timpre; - err = clk_register(clk); + err = bclk_register(clk); if (err) { kfree(tim_ker); return ERR_PTR(err); diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index b04d44593b..ba726c342c 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -36,6 +36,7 @@ static void clk_parent_disable(struct clk *clk) int clk_enable(struct clk *clk) { + struct clk_hw *hw; int ret; if (!clk) @@ -44,13 +45,15 @@ int clk_enable(struct clk *clk) if (IS_ERR(clk)) return PTR_ERR(clk); + hw = clk_to_clk_hw(clk); + if (!clk->enable_count) { ret = clk_parent_enable(clk); if (ret) return ret; if (clk->ops->enable) { - ret = clk->ops->enable(clk); + ret = clk->ops->enable(hw); if (ret) { clk_parent_disable(clk); return ret; @@ -65,6 +68,8 @@ int clk_enable(struct clk *clk) void clk_disable(struct clk *clk) { + struct clk_hw *hw; + if (!clk) return; @@ -81,9 +86,11 @@ void clk_disable(struct clk *clk) clk->enable_count--; + hw = clk_to_clk_hw(clk); + if (!clk->enable_count) { if (clk->ops->disable) - clk->ops->disable(clk); + clk->ops->disable(hw); clk_parent_disable(clk); } @@ -91,6 +98,7 @@ void clk_disable(struct clk *clk) unsigned long clk_get_rate(struct clk *clk) { + struct clk_hw *hw; struct clk *parent; unsigned long parent_rate = 0; @@ -106,14 +114,22 @@ unsigned long clk_get_rate(struct clk *clk) if (!IS_ERR_OR_NULL(parent)) parent_rate = clk_get_rate(parent); + hw = clk_to_clk_hw(clk); + if (clk->ops->recalc_rate) - return clk->ops->recalc_rate(clk, parent_rate); + return clk->ops->recalc_rate(hw, parent_rate); return parent_rate; } +unsigned long clk_hw_get_rate(struct clk_hw *hw) +{ + return clk_get_rate(clk_hw_to_clk(hw)); +} + long clk_round_rate(struct clk *clk, unsigned long rate) { + struct clk_hw *hw; unsigned long parent_rate = 0; struct clk *parent; @@ -127,14 +143,22 @@ long clk_round_rate(struct clk *clk, unsigned long rate) if (parent) parent_rate = clk_get_rate(parent); + hw = clk_to_clk_hw(clk); + if (clk->ops->round_rate) - return clk->ops->round_rate(clk, rate, &parent_rate); + return clk->ops->round_rate(hw, rate, &parent_rate); return clk_get_rate(clk); } +long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate) +{ + return clk_round_rate(&hw->clk, rate); +} + int clk_set_rate(struct clk *clk, unsigned long rate) { + struct clk_hw *hw; struct clk *parent; unsigned long parent_rate = 0; int ret; @@ -145,9 +169,18 @@ int clk_set_rate(struct clk *clk, unsigned long rate) if (IS_ERR(clk)) return PTR_ERR(clk); + if (clk_get_rate(clk) == clk_round_rate(clk, rate)) + return 0; + if (!clk->ops->set_rate) return -ENOSYS; + if (clk->flags & CLK_SET_RATE_UNGATE) { + ret = clk_enable(clk); + if (ret) + return ret; + } + parent = clk_get_parent(clk); if (parent) { parent_rate = clk_get_rate(parent); @@ -155,18 +188,29 @@ int clk_set_rate(struct clk *clk, unsigned long rate) if (clk->flags & CLK_OPS_PARENT_ENABLE) { ret = clk_enable(parent); if (ret) - return ret; + goto out; } } - ret = clk->ops->set_rate(clk, rate, parent_rate); + hw = clk_to_clk_hw(clk); + + ret = clk->ops->set_rate(hw, rate, parent_rate); if (parent && clk->flags & CLK_OPS_PARENT_ENABLE) clk_disable(parent); +out: + if (clk->flags & CLK_SET_RATE_UNGATE) + clk_disable(clk); + return ret; } +int clk_hw_set_rate(struct clk_hw *hw, unsigned long rate) +{ + return clk_set_rate(&hw->clk, rate); +} + struct clk *clk_lookup(const char *name) { struct clk *c; @@ -184,6 +228,7 @@ struct clk *clk_lookup(const char *name) int clk_set_parent(struct clk *clk, struct clk *newparent) { + struct clk_hw *hw; int i, ret; struct clk *curparent = clk_get_parent(clk); @@ -217,7 +262,9 @@ int clk_set_parent(struct clk *clk, struct clk *newparent) clk_enable(newparent); } - ret = clk->ops->set_parent(clk, i); + hw = clk_to_clk_hw(clk); + + ret = clk->ops->set_parent(hw, i); if (clk->flags & CLK_OPS_PARENT_ENABLE) { clk_disable(curparent); @@ -230,8 +277,14 @@ int clk_set_parent(struct clk *clk, struct clk *newparent) return ret; } +int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *newparent) +{ + return clk_set_parent(&hw->clk, &newparent->clk); +} + struct clk *clk_get_parent(struct clk *clk) { + struct clk_hw *hw; int idx; if (IS_ERR(clk)) @@ -240,11 +293,13 @@ struct clk *clk_get_parent(struct clk *clk) if (!clk->num_parents) return ERR_PTR(-ENODEV); + hw = clk_to_clk_hw(clk); + if (clk->num_parents != 1) { if (!clk->ops->get_parent) return ERR_PTR(-EINVAL); - idx = clk->ops->get_parent(clk); + idx = clk->ops->get_parent(hw); if (idx >= clk->num_parents) return ERR_PTR(-ENODEV); @@ -258,9 +313,76 @@ struct clk *clk_get_parent(struct clk *clk) return clk->parents[idx]; } -int clk_register(struct clk *clk) +struct clk_hw *clk_hw_get_parent(struct clk_hw *hw) +{ + struct clk *clk = clk_get_parent(clk_hw_to_clk(hw)); + + if (IS_ERR(clk)) + return ERR_CAST(clk); + + return clk_to_clk_hw(clk); +} + +/** + * clk_set_phase - adjust the phase shift of a clock signal + * @clk: clock signal source + * @degrees: number of degrees the signal is shifted + * + * Shifts the phase of a clock signal by the specified + * degrees. Returns 0 on success, -EERROR otherwise. + * + * This function makes no distinction about the input or reference + * signal that we adjust the clock signal phase against. For example + * phase locked-loop clock signal generators we may shift phase with + * respect to feedback clock signal input, but for other cases the + * clock phase may be shifted with respect to some other, unspecified + * signal. + * + * Additionally the concept of phase shift does not propagate through + * the clock tree hierarchy, which sets it apart from clock rates and + * clock accuracy. A parent clock phase attribute does not have an + * impact on the phase attribute of a child clock. + */ +int clk_set_phase(struct clk *clk, int degrees) { + if (!clk) + return 0; + + /* sanity check degrees */ + degrees %= 360; + if (degrees < 0) + degrees += 360; + + if (!clk->ops->set_phase) + return -EINVAL; + + return clk->ops->set_phase(clk_to_clk_hw(clk), degrees); +} + +/** + * clk_get_phase - return the phase shift of a clock signal + * @clk: clock signal source + * + * Returns the phase shift of a clock node in degrees, otherwise returns + * -EERROR. + */ +int clk_get_phase(struct clk *clk) +{ + int ret; + + if (!clk->ops->get_phase) + return 0; + + ret = clk->ops->get_phase(clk_to_clk_hw(clk)); + + return ret; +} + +int bclk_register(struct clk *clk) +{ + struct clk_hw *hw = clk_to_clk_hw(clk); struct clk *c; + int ret; list_for_each_entry(c, &clks, list) { if (!strcmp(c->name, clk->name)) { @@ -274,15 +396,64 @@ int clk_register(struct clk *clk) list_add_tail(&clk->list, &clks); + if (clk->ops->init) { + ret = clk->ops->init(hw); + if (ret) + goto out; + } + if (clk->flags & CLK_IS_CRITICAL) clk_enable(clk); return 0; +out: + list_del(&clk->list); + free(clk->parents); + + return ret; +} + +struct clk *clk_register(struct device_d *dev, struct clk_hw *hw) +{ + struct clk *clk; + const struct clk_init_data *init = hw->init; + char **parent_names; + int i, ret; + + if (!hw->init) + return ERR_PTR(-EINVAL); + + clk = clk_hw_to_clk(hw); + + memset(clk, 0, sizeof(*clk)); + + clk->name = xstrdup(init->name); + clk->ops = init->ops; + clk->num_parents = init->num_parents; + parent_names = xzalloc(init->num_parents * sizeof(char *)); + + for (i = 0; i < init->num_parents; i++) + parent_names[i] = xstrdup(init->parent_names[i]); + + clk->parent_names = (const char *const*)parent_names; + + clk->flags = init->flags; + + ret = bclk_register(clk); + if (ret) { + for (i = 0; i < init->num_parents; i++) + free(parent_names[i]); + free(parent_names); + return ERR_PTR(ret); + } + + return clk; } int clk_is_enabled(struct clk *clk) { int enabled; + struct clk_hw *hw = clk_to_clk_hw(clk); if (IS_ERR(clk)) return 0; @@ -291,7 +462,7 @@ int clk_is_enabled(struct clk *clk) /* * If we can ask a clk, do it */ - enabled = clk->ops->is_enabled(clk); + enabled = clk->ops->is_enabled(hw); } else { if (clk->ops->enable) { /* @@ -320,26 +491,35 @@ int clk_is_enabled(struct clk *clk) return clk_is_enabled(clk); } +int clk_hw_is_enabled(struct clk_hw *hw) +{ + return clk_is_enabled(&hw->clk); +} + /* * Generic struct clk_ops callbacks */ -int clk_is_enabled_always(struct clk *clk) +int clk_is_enabled_always(struct clk_hw *hw) { return 1; } -long clk_parent_round_rate(struct clk *clk, unsigned long rate, +long clk_parent_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { + struct clk *clk = clk_hw_to_clk(hw); + if (!(clk->flags & CLK_SET_RATE_PARENT)) return *prate; return clk_round_rate(clk_get_parent(clk), rate); } -int clk_parent_set_rate(struct clk *clk, unsigned long rate, +int clk_parent_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { + struct clk *clk = clk_hw_to_clk(hw); + if (!(clk->flags & CLK_SET_RATE_PARENT)) return 0; return clk_set_rate(clk_get_parent(clk), rate); @@ -663,8 +843,10 @@ int of_clk_init(struct device_node *root, const struct of_device_id *matches) static const char *clk_hw_stat(struct clk *clk) { + struct clk_hw *hw = clk_to_clk_hw(clk); + if (clk->ops->is_enabled) { - if (clk->ops->is_enabled(clk)) + if (clk->ops->is_enabled(hw)) return "enabled"; else return "disabled"; diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index 6c7f10a2c9..96fccc51d8 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -26,10 +26,11 @@ #define clk_div_mask(width) ((1 << (width)) - 1) -static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk *clk, +static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_divider *divider = container_of(clk, struct clk_divider, clk); + struct clk_divider *divider = container_of(hw, struct clk_divider, hw); + struct clk *clk = clk_hw_to_clk(hw); unsigned long prediv_rate; unsigned int prediv_value; unsigned int div_value; @@ -74,7 +75,7 @@ static int imx8m_clk_composite_compute_dividers(unsigned long rate, return ret; } -static long imx8m_clk_composite_divider_round_rate(struct clk *clk, +static long imx8m_clk_composite_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { @@ -89,11 +90,11 @@ static long imx8m_clk_composite_divider_round_rate(struct clk *clk, } -static int imx8m_clk_composite_divider_set_rate(struct clk *clk, +static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_divider *divider = container_of(clk, struct clk_divider, clk); + struct clk_divider *divider = container_of(hw, struct clk_divider, hw); int prediv_value; int div_value; int ret; @@ -114,14 +115,14 @@ static int imx8m_clk_composite_divider_set_rate(struct clk *clk, return ret; } -static int imx8m_clk_composite_mux_get_parent(struct clk *clk) +static int imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) { - return clk_mux_ops.get_parent(clk); + return clk_mux_ops.get_parent(hw); } -static int imx8m_clk_composite_mux_set_parent(struct clk *clk, u8 index) +static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index) { - struct clk_mux *m = container_of(clk, struct clk_mux, clk); + struct clk_mux *m = container_of(hw, struct clk_mux, hw); u32 val; val = readl(m->reg); @@ -161,7 +162,6 @@ struct clk *imx8m_clk_composite_flags(const char *name, struct clk_divider *div = NULL; struct clk_gate *gate = NULL; struct clk_mux *mux = NULL; - const struct clk_ops *divider_ops; const struct clk_ops *mux_ops; mux = kzalloc(sizeof(*mux), GFP_KERNEL); @@ -171,7 +171,7 @@ struct clk *imx8m_clk_composite_flags(const char *name, mux->reg = reg; mux->shift = PCG_PCS_SHIFT; mux->width = PCG_PCS_WIDTH; - mux->clk.ops = &clk_mux_ops; + mux->hw.clk.ops = &clk_mux_ops; div = kzalloc(sizeof(*div), GFP_KERNEL); if (!div) @@ -181,20 +181,19 @@ struct clk *imx8m_clk_composite_flags(const char *name, if (composite_flags & IMX_COMPOSITE_CORE) { div->shift = PCG_DIV_SHIFT; div->width = PCG_CORE_DIV_WIDTH; - divider_ops = &clk_divider_ops; + div->hw.clk.ops = &clk_divider_ops; mux_ops = &imx8m_clk_composite_mux_ops; } else if (composite_flags & IMX_COMPOSITE_BUS) { div->shift = PCG_PREDIV_SHIFT; div->width = PCG_PREDIV_WIDTH; - divider_ops = &imx8m_clk_composite_divider_ops; + div->hw.clk.ops = &imx8m_clk_composite_divider_ops; mux_ops = &imx8m_clk_composite_mux_ops; } else { div->shift = PCG_PREDIV_SHIFT; div->width = PCG_PREDIV_WIDTH; - divider_ops = &imx8m_clk_composite_divider_ops; + div->hw.clk.ops = &imx8m_clk_composite_divider_ops; mux_ops = &clk_mux_ops; } - div->clk.ops = divider_ops; gate = kzalloc(sizeof(*gate), GFP_KERNEL); if (!gate) @@ -202,10 +201,10 @@ struct clk *imx8m_clk_composite_flags(const char *name, gate->reg = reg; gate->shift = PCG_CGC_SHIFT; - gate->clk.ops = &clk_gate_ops; + gate->hw.clk.ops = &clk_gate_ops; comp = clk_register_composite(name, parent_names, num_parents, - &mux->clk, &div->clk, &gate->clk, flags); + &mux->hw.clk, &div->hw.clk, &gate->hw.clk, flags); if (IS_ERR(comp)) goto fail; diff --git a/drivers/clk/imx/clk-cpu.c b/drivers/clk/imx/clk-cpu.c index f8d54ddba3..0ca5dd63c5 100644 --- a/drivers/clk/imx/clk-cpu.c +++ b/drivers/clk/imx/clk-cpu.c @@ -16,38 +16,38 @@ #include "clk.h" struct clk_cpu { - struct clk clk; + struct clk_hw hw; struct clk *div; struct clk *mux; struct clk *pll; struct clk *step; }; -static inline struct clk_cpu *to_clk_cpu(struct clk *clk) +static inline struct clk_cpu *to_clk_cpu(struct clk_hw *hw) { - return container_of(clk, struct clk_cpu, clk); + return container_of(hw, struct clk_cpu, hw); } -static unsigned long clk_cpu_recalc_rate(struct clk *clk, +static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_cpu *cpu = to_clk_cpu(clk); + struct clk_cpu *cpu = to_clk_cpu(hw); return clk_get_rate(cpu->div); } -static long clk_cpu_round_rate(struct clk *clk, unsigned long rate, +static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { - struct clk_cpu *cpu = to_clk_cpu(clk); + struct clk_cpu *cpu = to_clk_cpu(hw); return clk_round_rate(cpu->pll, rate); } -static int clk_cpu_set_rate(struct clk *clk, unsigned long rate, +static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_cpu *cpu = to_clk_cpu(clk); + struct clk_cpu *cpu = to_clk_cpu(hw); int ret; /* switch to PLL bypass clock */ @@ -98,17 +98,17 @@ struct clk *imx_clk_cpu(const char *name, const char *parent_name, cpu->pll = pll; cpu->step = step; - cpu->clk.name = name; - cpu->clk.ops = &clk_cpu_ops; - cpu->clk.flags = CLK_IS_CRITICAL; - cpu->clk.parent_names = &icpu->parent_name; - cpu->clk.num_parents = 1; + cpu->hw.clk.name = name; + cpu->hw.clk.ops = &clk_cpu_ops; + cpu->hw.clk.flags = CLK_IS_CRITICAL; + cpu->hw.clk.parent_names = &icpu->parent_name; + cpu->hw.clk.num_parents = 1; - ret = clk_register(&cpu->clk); + ret = bclk_register(&cpu->hw.clk); if (ret) { free(cpu); return NULL; } - return &cpu->clk; + return &cpu->hw.clk; } diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c index 48866eadf0..d3fc760717 100644 --- a/drivers/clk/imx/clk-frac-pll.c +++ b/drivers/clk/imx/clk-frac-pll.c @@ -26,12 +26,12 @@ #define PLL_FRAC_DENOM 0x1000000 struct clk_frac_pll { - struct clk clk; + struct clk_hw hw; void __iomem *base; const char *parent; }; -#define to_clk_frac_pll(_clk) container_of(_clk, struct clk_frac_pll, clk) +#define to_clk_frac_pll(_hw) container_of(_hw, struct clk_frac_pll, hw) static int clk_wait_lock(struct clk_frac_pll *pll) { @@ -63,9 +63,9 @@ static int clk_wait_ack(struct clk_frac_pll *pll) return readl(pll->base) & PLL_NEWDIV_ACK ? 0 : ETIMEDOUT; } -static int clk_pll_enable(struct clk *clk) +static int clk_pll_enable(struct clk_hw *hw) { - struct clk_frac_pll *pll = to_clk_frac_pll(clk); + struct clk_frac_pll *pll = to_clk_frac_pll(hw); u32 val; val = readl(pll->base + PLL_CFG0); @@ -75,9 +75,9 @@ static int clk_pll_enable(struct clk *clk) return clk_wait_lock(pll); } -static void clk_pll_disable(struct clk *clk) +static void clk_pll_disable(struct clk_hw *hw) { - struct clk_frac_pll *pll = to_clk_frac_pll(clk); + struct clk_frac_pll *pll = to_clk_frac_pll(hw); u32 val; val = readl(pll->base + PLL_CFG0); @@ -85,19 +85,19 @@ static void clk_pll_disable(struct clk *clk) writel(val, pll->base + PLL_CFG0); } -static int clk_pll_is_enabled(struct clk *clk) +static int clk_pll_is_enabled(struct clk_hw *hw) { - struct clk_frac_pll *pll = to_clk_frac_pll(clk); + struct clk_frac_pll *pll = to_clk_frac_pll(hw); u32 val; val = readl(pll->base + PLL_CFG0); return (val & (1 << PLL_PD)) ? 0 : 1; } -static unsigned long clk_pll_recalc_rate(struct clk *clk, +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_frac_pll *pll = to_clk_frac_pll(clk); + struct clk_frac_pll *pll = to_clk_frac_pll(hw); u32 val, divff, divfi, divq; u64 temp64; @@ -115,7 +115,7 @@ static unsigned long clk_pll_recalc_rate(struct clk *clk, return parent_rate * 8 * (divfi + 1) / divq + (unsigned long)temp64; } -static long clk_pll_round_rate(struct clk *clk, unsigned long rate, +static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { u32 divff, divfi; @@ -144,10 +144,10 @@ static long clk_pll_round_rate(struct clk *clk, unsigned long rate, * pllout = parent_rate * 8 / 2 * DIVF_VAL; * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24. */ -static int clk_pll_set_rate(struct clk *clk, unsigned long rate, +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_frac_pll *pll = to_clk_frac_pll(clk); + struct clk_frac_pll *pll = to_clk_frac_pll(hw); u32 val, divfi, divff; u64 temp64; int ret; @@ -205,16 +205,16 @@ struct clk *imx_clk_frac_pll(const char *name, const char *parent, pll->base = base; pll->parent = parent; - pll->clk.ops = &clk_frac_pll_ops; - pll->clk.name = name; - pll->clk.parent_names = &pll->parent; - pll->clk.num_parents = 1; + pll->hw.clk.ops = &clk_frac_pll_ops; + pll->hw.clk.name = name; + pll->hw.clk.parent_names = &pll->parent; + pll->hw.clk.num_parents = 1; - ret = clk_register(&pll->clk); + ret = bclk_register(&pll->hw.clk); if (ret) { free(pll); return ERR_PTR(ret); } - return &pll->clk; + return &pll->hw.clk; } diff --git a/drivers/clk/imx/clk-gate-exclusive.c b/drivers/clk/imx/clk-gate-exclusive.c index 4bf4de8bd3..473249a356 100644 --- a/drivers/clk/imx/clk-gate-exclusive.c +++ b/drivers/clk/imx/clk-gate-exclusive.c @@ -24,17 +24,21 @@ * register is mutually exclusive to this gate clock. */ struct clk_gate_exclusive { - struct clk clk; + struct clk_hw hw; void __iomem *reg; int shift; const char *parent; u32 exclusive_mask; }; -static int clk_gate_exclusive_enable(struct clk *clk) +static inline struct clk_gate_exclusive *to_clk_gate_exclusive(struct clk_hw *hw) { - struct clk_gate_exclusive *exgate = container_of(clk, - struct clk_gate_exclusive, clk); + return container_of(hw, struct clk_gate_exclusive, hw); +} + +static int clk_gate_exclusive_enable(struct clk_hw *hw) +{ + struct clk_gate_exclusive *exgate = to_clk_gate_exclusive(hw); u32 val = readl(exgate->reg); if (val & exgate->exclusive_mask) @@ -47,10 +51,9 @@ static int clk_gate_exclusive_enable(struct clk *clk) return 0; } -static void clk_gate_exclusive_disable(struct clk *clk) +static void clk_gate_exclusive_disable(struct clk_hw *hw) { - struct clk_gate_exclusive *exgate = container_of(clk, - struct clk_gate_exclusive, clk); + struct clk_gate_exclusive *exgate = to_clk_gate_exclusive(hw); u32 val = readl(exgate->reg); val &= ~(1 << exgate->shift); @@ -58,10 +61,9 @@ static void clk_gate_exclusive_disable(struct clk *clk) writel(val, exgate->reg); } -static int clk_gate_exclusive_is_enabled(struct clk *clk) +static int clk_gate_exclusive_is_enabled(struct clk_hw *hw) { - struct clk_gate_exclusive *exgate = container_of(clk, - struct clk_gate_exclusive, clk); + struct clk_gate_exclusive *exgate = to_clk_gate_exclusive(hw); return readl(exgate->reg) & (1 << exgate->shift); } @@ -80,21 +82,21 @@ struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, exgate = xzalloc(sizeof(*exgate)); exgate->parent = parent; - exgate->clk.name = name; - exgate->clk.ops = &clk_gate_exclusive_ops; - exgate->clk.flags = CLK_SET_RATE_PARENT; - exgate->clk.parent_names = &exgate->parent; - exgate->clk.num_parents = 1; + exgate->hw.clk.name = name; + exgate->hw.clk.ops = &clk_gate_exclusive_ops; + exgate->hw.clk.flags = CLK_SET_RATE_PARENT; + exgate->hw.clk.parent_names = &exgate->parent; + exgate->hw.clk.num_parents = 1; exgate->reg = reg; exgate->shift = shift; exgate->exclusive_mask = exclusive_mask; - ret = clk_register(&exgate->clk); + ret = bclk_register(&exgate->hw.clk); if (ret) { free(exgate); return ERR_PTR(ret); } - return &exgate->clk; + return &exgate->hw.clk; } diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index 88eaae8db3..af83e93b12 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -13,25 +13,27 @@ struct clk_gate2 { - struct clk clk; + struct clk_hw hw; void __iomem *reg; int shift; u8 cgr_val; const char *parent; -#define CLK_GATE_INVERTED (1 << 0) unsigned flags; }; -#define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk) +static inline struct clk_gate2 *to_clk_gate2(struct clk_hw *hw) +{ + return container_of(hw, struct clk_gate2, hw); +} -static int clk_gate2_enable(struct clk *clk) +static int clk_gate2_enable(struct clk_hw *hw) { - struct clk_gate2 *g = to_clk_gate2(clk); + struct clk_gate2 *g = to_clk_gate2(hw); u32 val; val = readl(g->reg); - if (g->flags & CLK_GATE_INVERTED) + if (g->flags & CLK_GATE_SET_TO_DISABLE) val &= ~(3 << g->shift); else val |= g->cgr_val << g->shift; @@ -41,14 +43,14 @@ static int clk_gate2_enable(struct clk *clk) return 0; } -static void clk_gate2_disable(struct clk *clk) +static void clk_gate2_disable(struct clk_hw *hw) { - struct clk_gate2 *g = to_clk_gate2(clk); + struct clk_gate2 *g = to_clk_gate2(hw); u32 val; val = readl(g->reg); - if (g->flags & CLK_GATE_INVERTED) + if (g->flags & CLK_GATE_SET_TO_DISABLE) val |= 3 << g->shift; else val &= ~(3 << g->shift); @@ -56,17 +58,17 @@ static void clk_gate2_disable(struct clk *clk) writel(val, g->reg); } -static int clk_gate2_is_enabled(struct clk *clk) +static int clk_gate2_is_enabled(struct clk_hw *hw) { - struct clk_gate2 *g = to_clk_gate2(clk); + struct clk_gate2 *g = to_clk_gate2(hw); u32 val; val = readl(g->reg); if (val & (1 << g->shift)) - return g->flags & CLK_GATE_INVERTED ? 0 : 1; + return g->flags & CLK_GATE_SET_TO_DISABLE ? 0 : 1; else - return g->flags & CLK_GATE_INVERTED ? 1 : 0; + return g->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; } static struct clk_ops clk_gate2_ops = { @@ -87,13 +89,13 @@ static struct clk *clk_gate2_alloc(const char *name, const char *parent, g->reg = reg; g->cgr_val = cgr_val; g->shift = shift; - g->clk.ops = &clk_gate2_ops; - g->clk.name = name; - g->clk.parent_names = &g->parent; - g->clk.num_parents = 1; - g->clk.flags = CLK_SET_RATE_PARENT | flags; + g->hw.clk.ops = &clk_gate2_ops; + g->hw.clk.name = name; + g->hw.clk.parent_names = &g->parent; + g->hw.clk.num_parents = 1; + g->hw.clk.flags = CLK_SET_RATE_PARENT | flags; - return &g->clk; + return &g->hw.clk; } struct clk *clk_gate2(const char *name, const char *parent, void __iomem *reg, @@ -104,9 +106,10 @@ struct clk *clk_gate2(const char *name, const char *parent, void __iomem *reg, g = clk_gate2_alloc(name , parent, reg, shift, cgr_val, flags); - ret = clk_register(g); + ret = bclk_register(g); if (ret) { - free(to_clk_gate2(g)); + struct clk_hw *hw = clk_to_clk_hw(g); + free(to_clk_gate2(hw)); return ERR_PTR(ret); } diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index 6668146860..af5d582ffc 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -98,6 +98,7 @@ static int imx6_ccm_probe(struct device_d *dev) void __iomem *base, *anatop_base, *ccm_base; int i; struct device_node *ccm_node = dev->device_node; + struct clk_hw *hw; anatop_base = IOMEM(MX6_ANATOP_BASE_ADDR); iores = dev_request_mem_resource(dev, 0); @@ -445,7 +446,8 @@ static int imx6_ccm_probe(struct device_d *dev) clks[IMX6UL_CLK_PLL3_PFD2]); /* Disable GPMI_IO clk before reparenting to avoid glitches */ - clks[IMX6UL_CLK_GPMI_IO]->ops->disable(clks[IMX6UL_CLK_GPMI_IO]); + hw = clk_to_clk_hw(clks[IMX6UL_CLK_GPMI_IO]); + clks[IMX6UL_CLK_GPMI_IO]->ops->disable(hw); clk_set_parent(clks[IMX6UL_CLK_ENFC_SEL], clks[IMX6UL_CLK_PLL2_PFD2]); diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c index a7ca664524..d16e39f85c 100644 --- a/drivers/clk/imx/clk-pfd.c +++ b/drivers/clk/imx/clk-pfd.c @@ -27,37 +27,37 @@ * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc. */ struct clk_pfd { - struct clk clk; + struct clk_hw hw; void __iomem *reg; u8 idx; const char *parent; }; -#define to_clk_pfd(_clk) container_of(_clk, struct clk_pfd, clk) +#define to_clk_pfd(_hw) container_of(_hw, struct clk_pfd, hw) #define SET 0x4 #define CLR 0x8 #define OTG 0xc -static int clk_pfd_enable(struct clk *clk) +static int clk_pfd_enable(struct clk_hw *hw) { - struct clk_pfd *pfd = to_clk_pfd(clk); + struct clk_pfd *pfd = to_clk_pfd(hw); writel(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); return 0; } -static void clk_pfd_disable(struct clk *clk) +static void clk_pfd_disable(struct clk_hw *hw) { - struct clk_pfd *pfd = to_clk_pfd(clk); + struct clk_pfd *pfd = to_clk_pfd(hw); writel(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); } -static unsigned long clk_pfd_recalc_rate(struct clk *clk, +static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_pfd *pfd = to_clk_pfd(clk); + struct clk_pfd *pfd = to_clk_pfd(hw); u64 tmp = parent_rate; u8 frac = (readl(pfd->reg) >> (pfd->idx * 8)) & 0x3f; @@ -67,7 +67,7 @@ static unsigned long clk_pfd_recalc_rate(struct clk *clk, return tmp; } -static long clk_pfd_round_rate(struct clk *clk, unsigned long rate, +static long clk_pfd_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { u64 tmp = *prate; @@ -87,10 +87,10 @@ static long clk_pfd_round_rate(struct clk *clk, unsigned long rate, return tmp; } -static int clk_pfd_set_rate(struct clk *clk, unsigned long rate, +static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_pfd *pfd = to_clk_pfd(clk); + struct clk_pfd *pfd = to_clk_pfd(hw); u64 tmp = parent_rate; u8 frac; @@ -127,16 +127,16 @@ struct clk *imx_clk_pfd(const char *name, const char *parent, pfd->reg = reg; pfd->idx = idx; pfd->parent = parent; - pfd->clk.name = name; - pfd->clk.ops = &clk_pfd_ops; - pfd->clk.parent_names = &pfd->parent; - pfd->clk.num_parents = 1; + pfd->hw.clk.name = name; + pfd->hw.clk.ops = &clk_pfd_ops; + pfd->hw.clk.parent_names = &pfd->parent; + pfd->hw.clk.num_parents = 1; - ret = clk_register(&pfd->clk); + ret = bclk_register(&pfd->hw.clk); if (ret) { free(pfd); return ERR_PTR(ret); } - return &pfd->clk; + return &pfd->hw.clk; } diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 3fd5a49ee7..bc837bd838 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -37,7 +37,7 @@ #define LOCK_TIMEOUT_US 10000 struct clk_pll14xx { - struct clk clk; + struct clk_hw hw; void __iomem *base; enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; @@ -45,7 +45,7 @@ struct clk_pll14xx { const char *parent; }; -#define to_clk_pll14xx(clk) container_of(clk, struct clk_pll14xx, clk) +#define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { PLL_1416X_RATE(1800000000U, 225, 3, 0), @@ -92,10 +92,10 @@ static const struct imx_pll14xx_rate_table *imx_get_pll_settings( return NULL; } -static long clk_pll14xx_round_rate(struct clk *clk, unsigned long rate, +static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { - struct clk_pll14xx *pll = to_clk_pll14xx(clk); + struct clk_pll14xx *pll = to_clk_pll14xx(hw); const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; int i; @@ -108,10 +108,10 @@ static long clk_pll14xx_round_rate(struct clk *clk, unsigned long rate, return rate_table[i - 1].rate; } -static unsigned long clk_pll1416x_recalc_rate(struct clk *clk, +static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_pll14xx *pll = to_clk_pll14xx(clk); + struct clk_pll14xx *pll = to_clk_pll14xx(hw); u32 mdiv, pdiv, sdiv, pll_div; u64 fvco = parent_rate; @@ -126,10 +126,10 @@ static unsigned long clk_pll1416x_recalc_rate(struct clk *clk, return fvco; } -static unsigned long clk_pll1443x_recalc_rate(struct clk *clk, +static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_pll14xx *pll = to_clk_pll14xx(clk); + struct clk_pll14xx *pll = to_clk_pll14xx(hw); u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1; short int kdiv; u64 fvco = parent_rate; @@ -169,10 +169,10 @@ static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll) LOCK_TIMEOUT_US); } -static int clk_pll1416x_set_rate(struct clk *clk, unsigned long drate, +static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { - struct clk_pll14xx *pll = to_clk_pll14xx(clk); + struct clk_pll14xx *pll = to_clk_pll14xx(hw); const struct imx_pll14xx_rate_table *rate; u32 tmp, div_val; int ret; @@ -180,7 +180,7 @@ static int clk_pll1416x_set_rate(struct clk *clk, unsigned long drate, rate = imx_get_pll_settings(pll, drate); if (!rate) { pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, clk->name); + drate, hw->clk.name); return -EINVAL; } @@ -239,7 +239,7 @@ int clk_pll1416x_early_set_rate(void __iomem *base, unsigned long drate, unsigned long prate) { struct clk_pll14xx pll = { - .clk = { + .hw.clk = { .name = "pll1416x", }, .base = base, @@ -247,13 +247,14 @@ int clk_pll1416x_early_set_rate(void __iomem *base, unsigned long drate, .rate_count = ARRAY_SIZE(imx_pll1416x_tbl), }; - return clk_pll1416x_set_rate(&pll.clk, drate, prate); + return clk_pll1416x_set_rate(&pll.hw, drate, prate); } -static int clk_pll1443x_set_rate(struct clk *clk, unsigned long drate, +static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { - struct clk_pll14xx *pll = to_clk_pll14xx(clk); + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + struct clk *clk = clk_hw_to_clk(hw); const struct imx_pll14xx_rate_table *rate; u32 tmp, div_val; int ret; @@ -316,9 +317,9 @@ static int clk_pll1443x_set_rate(struct clk *clk, unsigned long drate, return 0; } -static int clk_pll14xx_prepare(struct clk *clk) +static int clk_pll14xx_prepare(struct clk_hw *hw) { - struct clk_pll14xx *pll = to_clk_pll14xx(clk); + struct clk_pll14xx *pll = to_clk_pll14xx(hw); u32 val; int ret; @@ -344,9 +345,9 @@ static int clk_pll14xx_prepare(struct clk *clk) return 0; } -static int clk_pll14xx_is_prepared(struct clk *clk) +static int clk_pll14xx_is_prepared(struct clk_hw *hw) { - struct clk_pll14xx *pll = to_clk_pll14xx(clk); + struct clk_pll14xx *pll = to_clk_pll14xx(hw); u32 val; val = readl(pll->base + GNRL_CTL); @@ -354,9 +355,9 @@ static int clk_pll14xx_is_prepared(struct clk *clk) return (val & RST_MASK) ? 1 : 0; } -static void clk_pll14xx_unprepare(struct clk *clk) +static void clk_pll14xx_unprepare(struct clk_hw *hw) { - struct clk_pll14xx *pll = to_clk_pll14xx(clk); + struct clk_pll14xx *pll = to_clk_pll14xx(hw); u32 val; /* @@ -403,7 +404,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, if (!pll) return ERR_PTR(-ENOMEM); - clk = &pll->clk; + clk = &pll->hw.clk; pll->parent = parent_name; clk->name = name; @@ -435,7 +436,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, val &= ~BYPASS_MASK; writel(val, pll->base + GNRL_CTL); - ret = clk_register(clk); + ret = bclk_register(clk); if (ret) { free(pll); return ERR_PTR(ret); diff --git a/drivers/clk/imx/clk-pllv1.c b/drivers/clk/imx/clk-pllv1.c index 36192bb211..62afa2b6b2 100644 --- a/drivers/clk/imx/clk-pllv1.c +++ b/drivers/clk/imx/clk-pllv1.c @@ -17,7 +17,7 @@ #define MFN_MASK (MFN_SIGN - 1) struct clk_pllv1 { - struct clk clk; + struct clk_hw hw; void __iomem *reg; const char *parent; }; @@ -27,10 +27,10 @@ static inline bool mfn_is_negative(unsigned int mfn) return mfn & MFN_SIGN; } -static unsigned long clk_pllv1_recalc_rate(struct clk *clk, +static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_pllv1 *pll = container_of(clk, struct clk_pllv1, clk); + struct clk_pllv1 *pll = container_of(hw, struct clk_pllv1, hw); unsigned long long ll; int mfn_abs; unsigned int mfi, mfn, mfd, pd; @@ -79,16 +79,16 @@ struct clk *imx_clk_pllv1(const char *name, const char *parent, pll->parent = parent; pll->reg = base; - pll->clk.ops = &clk_pllv1_ops; - pll->clk.name = name; - pll->clk.parent_names = &pll->parent; - pll->clk.num_parents = 1; + pll->hw.clk.ops = &clk_pllv1_ops; + pll->hw.clk.name = name; + pll->hw.clk.parent_names = &pll->parent; + pll->hw.clk.num_parents = 1; - ret = clk_register(&pll->clk); + ret = bclk_register(&pll->hw.clk); if (ret) { free(pll); return ERR_PTR(ret); } - return &pll->clk; + return &pll->hw.clk; } diff --git a/drivers/clk/imx/clk-pllv2.c b/drivers/clk/imx/clk-pllv2.c index 6af2d71352..d997e465d5 100644 --- a/drivers/clk/imx/clk-pllv2.c +++ b/drivers/clk/imx/clk-pllv2.c @@ -70,7 +70,7 @@ #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ struct clk_pllv2 { - struct clk clk; + struct clk_hw hw; void __iomem *reg; const char *parent; }; @@ -110,12 +110,12 @@ static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate, return temp; } -static unsigned long clk_pllv2_recalc_rate(struct clk *clk, +static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { u32 dp_op, dp_mfd, dp_mfn, dp_ctl; void __iomem *pllbase; - struct clk_pllv2 *pll = container_of(clk, struct clk_pllv2, clk); + struct clk_pllv2 *pll = container_of(hw, struct clk_pllv2, hw); pllbase = pll->reg; @@ -156,10 +156,10 @@ static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate, return 0; } -static int clk_pllv2_set_rate(struct clk *clk, unsigned long rate, +static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_pllv2 *pll = container_of(clk, struct clk_pllv2, clk); + struct clk_pllv2 *pll = container_of(hw, struct clk_pllv2, hw); void __iomem *pllbase; u32 dp_ctl, dp_op, dp_mfd, dp_mfn; int ret; @@ -181,7 +181,7 @@ static int clk_pllv2_set_rate(struct clk *clk, unsigned long rate, return 0; } -static long clk_pllv2_round_rate(struct clk *clk, unsigned long rate, +static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { u32 dp_op, dp_mfd, dp_mfn; @@ -205,16 +205,16 @@ struct clk *imx_clk_pllv2(const char *name, const char *parent, pll->parent = parent; pll->reg = base; - pll->clk.ops = &clk_pllv2_ops; - pll->clk.name = name; - pll->clk.parent_names = &pll->parent; - pll->clk.num_parents = 1; + pll->hw.clk.ops = &clk_pllv2_ops; + pll->hw.clk.name = name; + pll->hw.clk.parent_names = &pll->parent; + pll->hw.clk.num_parents = 1; - ret = clk_register(&pll->clk); + ret = bclk_register(&pll->hw.clk); if (ret) { free(pll); return ERR_PTR(ret); } - return &pll->clk; + return &pll->hw.clk; } diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 51e620a040..cb1d65058f 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -25,7 +25,7 @@ #define IMX7_ENET_PLL_POWER (0x1 << 5) struct clk_pllv3 { - struct clk clk; + struct clk_hw hw; void __iomem *base; bool powerup_set; u32 div_mask; @@ -35,11 +35,11 @@ struct clk_pllv3 { u32 power_bit; }; -#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk) +#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) -static int clk_pllv3_enable(struct clk *clk) +static int clk_pllv3_enable(struct clk_hw *hw) { - struct clk_pllv3 *pll = to_clk_pllv3(clk); + struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val; int timeout = 10000; @@ -66,9 +66,9 @@ static int clk_pllv3_enable(struct clk *clk) return 0; } -static void clk_pllv3_disable(struct clk *clk) +static void clk_pllv3_disable(struct clk_hw *hw) { - struct clk_pllv3 *pll = to_clk_pllv3(clk); + struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val; val = readl(pll->base); @@ -82,16 +82,16 @@ static void clk_pllv3_disable(struct clk *clk) writel(val, pll->base); } -static unsigned long clk_pllv3_recalc_rate(struct clk *clk, +static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_pllv3 *pll = to_clk_pllv3(clk); + struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; return (div == 1) ? parent_rate * 22 : parent_rate * 20; } -static long clk_pllv3_round_rate(struct clk *clk, unsigned long rate, +static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { unsigned long parent_rate = *prate; @@ -100,10 +100,10 @@ static long clk_pllv3_round_rate(struct clk *clk, unsigned long rate, parent_rate * 20; } -static int clk_pllv3_set_rate(struct clk *clk, unsigned long rate, +static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_pllv3 *pll = to_clk_pllv3(clk); + struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val, div; if (rate == parent_rate * 22) @@ -129,16 +129,16 @@ static const struct clk_ops clk_pllv3_ops = { .set_rate = clk_pllv3_set_rate, }; -static unsigned long clk_pllv3_sys_recalc_rate(struct clk *clk, +static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_pllv3 *pll = to_clk_pllv3(clk); + struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 div = readl(pll->base) & pll->div_mask; return parent_rate * div / 2; } -static long clk_pllv3_sys_round_rate(struct clk *clk, unsigned long rate, +static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { unsigned long parent_rate = *prate; @@ -155,10 +155,10 @@ static long clk_pllv3_sys_round_rate(struct clk *clk, unsigned long rate, return parent_rate * div / 2; } -static int clk_pllv3_sys_set_rate(struct clk *clk, unsigned long rate, +static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_pllv3 *pll = to_clk_pllv3(clk); + struct clk_pllv3 *pll = to_clk_pllv3(hw); unsigned long min_rate = parent_rate * 54 / 2; unsigned long max_rate = parent_rate * 108 / 2; u32 val, div; @@ -183,10 +183,11 @@ static const struct clk_ops clk_pllv3_sys_ops = { .set_rate = clk_pllv3_sys_set_rate, }; -static unsigned long clk_pllv3_av_recalc_rate(struct clk *clk, +static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_pllv3 *pll = to_clk_pllv3(clk); + struct clk_pllv3 *pll = to_clk_pllv3(hw); + u32 mfn = readl(pll->base + PLL_NUM_OFFSET); u32 mfd = readl(pll->base + PLL_DENOM_OFFSET); u32 div = readl(pll->base) & pll->div_mask; @@ -194,7 +195,7 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk *clk, return (parent_rate * div) + ((parent_rate / mfd) * mfn); } -static long clk_pllv3_av_round_rate(struct clk *clk, unsigned long rate, +static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { unsigned long parent_rate = *prate; @@ -218,10 +219,11 @@ static long clk_pllv3_av_round_rate(struct clk *clk, unsigned long rate, return parent_rate * div + parent_rate / mfd * mfn; } -static int clk_pllv3_av_set_rate(struct clk *clk, unsigned long rate, +static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_pllv3 *pll = to_clk_pllv3(clk); + struct clk_pllv3 *pll = to_clk_pllv3(hw); + unsigned long min_rate = parent_rate * 27; unsigned long max_rate = parent_rate * 54; u32 val, div; @@ -255,10 +257,10 @@ static const struct clk_ops clk_pllv3_av_ops = { .set_rate = clk_pllv3_av_set_rate, }; -static unsigned long clk_pllv3_enet_recalc_rate(struct clk *clk, +static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_pllv3 *pll = to_clk_pllv3(clk); + struct clk_pllv3 *pll = to_clk_pllv3(hw); return pll->ref_clock; } @@ -274,10 +276,10 @@ static const struct clk_ops clk_pllv3_mlb_ops = { .disable = clk_pllv3_disable, }; -static unsigned long clk_pllv3_sys_vf610_recalc_rate(struct clk *clk, +static unsigned long clk_pllv3_sys_vf610_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_pllv3 *pll = to_clk_pllv3(clk); + struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 mfn = readl(pll->base + SYS_VF610_PLL_OFFSET + PLL_NUM_OFFSET); u32 mfd = readl(pll->base + SYS_VF610_PLL_OFFSET + PLL_DENOM_OFFSET); @@ -286,7 +288,7 @@ static unsigned long clk_pllv3_sys_vf610_recalc_rate(struct clk *clk, return (parent_rate * div) + ((parent_rate / mfd) * mfn); } -static long clk_pllv3_sys_vf610_round_rate(struct clk *clk, unsigned long rate, +static long clk_pllv3_sys_vf610_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { unsigned long parent_rate = *prate; @@ -308,10 +310,10 @@ static long clk_pllv3_sys_vf610_round_rate(struct clk *clk, unsigned long rate, return parent_rate * 20 + parent_rate / mfd * mfn; } -static int clk_pllv3_sys_vf610_set_rate(struct clk *clk, unsigned long rate, +static int clk_pllv3_sys_vf610_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_pllv3 *pll = to_clk_pllv3(clk); + struct clk_pllv3 *pll = to_clk_pllv3(hw); unsigned long min_rate = parent_rate * 20; unsigned long max_rate = 528000000; u32 val; @@ -400,20 +402,20 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, pll->base = base; pll->div_mask = div_mask; pll->parent = parent; - pll->clk.ops = ops; - pll->clk.name = name; - pll->clk.parent_names = &pll->parent; - pll->clk.num_parents = 1; + pll->hw.clk.ops = ops; + pll->hw.clk.name = name; + pll->hw.clk.parent_names = &pll->parent; + pll->hw.clk.num_parents = 1; val = readl(pll->base); val &= ~BM_PLL_BYPASS; writel(val, pll->base); - ret = clk_register(&pll->clk); + ret = bclk_register(&pll->hw.clk); if (ret) { free(pll); return ERR_PTR(ret); } - return &pll->clk; + return &pll->hw.clk; } diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c index 755ece0e12..f911bf4aa1 100644 --- a/drivers/clk/imx/clk-sccg-pll.c +++ b/drivers/clk/imx/clk-sccg-pll.c @@ -39,26 +39,26 @@ #define OSC_27M 27000000 struct clk_sccg_pll { - struct clk clk; + struct clk_hw hw; void __iomem *base; const char *parent; }; -#define to_clk_sccg_pll(_clk) container_of(_clk, struct clk_sccg_pll, clk) +#define to_clk_sccg_pll(_hw) container_of(_hw, struct clk_sccg_pll, hw) -static int clk_pll1_is_prepared(struct clk *clk) +static int clk_pll1_is_prepared(struct clk_hw *hw) { - struct clk_sccg_pll *pll = to_clk_sccg_pll(clk); + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); u32 val; val = readl(pll->base + PLL_CFG0); return (val & (1 << PLL_PD)) ? 0 : 1; } -static unsigned long clk_pll1_recalc_rate(struct clk *clk, +static unsigned long clk_pll1_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_sccg_pll *pll = to_clk_sccg_pll(clk); + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); u32 val, divf; val = readl(pll->base + PLL_CFG2); @@ -67,7 +67,7 @@ static unsigned long clk_pll1_recalc_rate(struct clk *clk, return parent_rate * 2 * (divf + 1); } -static long clk_pll1_round_rate(struct clk *clk, unsigned long rate, +static long clk_pll1_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { unsigned long parent_rate = *prate; @@ -78,10 +78,10 @@ static long clk_pll1_round_rate(struct clk *clk, unsigned long rate, return parent_rate * div * 2; } -static int clk_pll1_set_rate(struct clk *clk, unsigned long rate, +static int clk_pll1_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_sccg_pll *pll = to_clk_sccg_pll(clk); + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); u32 val; u32 divf; @@ -97,9 +97,9 @@ static int clk_pll1_set_rate(struct clk *clk, unsigned long rate, return 0; } -static int clk_pll1_prepare(struct clk *clk) +static int clk_pll1_prepare(struct clk_hw *hw) { - struct clk_sccg_pll *pll = to_clk_sccg_pll(clk); + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); u32 val; val = readl(pll->base); @@ -111,19 +111,20 @@ static int clk_pll1_prepare(struct clk *clk) return 0; } -static void clk_pll1_unprepare(struct clk *clk) +static void clk_pll1_unprepare(struct clk_hw *hw) { - struct clk_sccg_pll *pll = to_clk_sccg_pll(clk); + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); u32 val; + val = readl(pll->base); val |= (1 << PLL_PD); writel(val, pll->base); } -static unsigned long clk_pll2_recalc_rate(struct clk *clk, +static unsigned long clk_pll2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_sccg_pll *pll = to_clk_sccg_pll(clk); + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); u32 val, ref, divr1, divf1, divr2, divf2; u64 temp64; @@ -154,7 +155,7 @@ static unsigned long clk_pll2_recalc_rate(struct clk *clk, return (unsigned long)temp64; } -static long clk_pll2_round_rate(struct clk *clk, unsigned long rate, +static long clk_pll2_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { u32 div; @@ -165,12 +166,12 @@ static long clk_pll2_round_rate(struct clk *clk, unsigned long rate, return parent_rate * div; } -static int clk_pll2_set_rate(struct clk *clk, unsigned long rate, +static int clk_pll2_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); u32 val; u32 divf; - struct clk_sccg_pll *pll = to_clk_sccg_pll(clk); divf = rate / (parent_rate); @@ -210,25 +211,25 @@ struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name, return ERR_PTR(-ENOMEM); pll->base = base; - pll->clk.name = name; + pll->hw.clk.name = name; switch (pll_type) { case SCCG_PLL1: - pll->clk.ops = &clk_sccg_pll1_ops; + pll->hw.clk.ops = &clk_sccg_pll1_ops; break; case SCCG_PLL2: - pll->clk.ops = &clk_sccg_pll2_ops; + pll->hw.clk.ops = &clk_sccg_pll2_ops; break; } pll->parent = parent_name; - pll->clk.parent_names = &pll->parent; - pll->clk.num_parents = 1; + pll->hw.clk.parent_names = &pll->parent; + pll->hw.clk.num_parents = 1; - ret = clk_register(&pll->clk); + ret = bclk_register(&pll->hw.clk); if (ret) { free(pll); return ERR_PTR(ret); } - return &pll->clk; + return &pll->hw.clk; } diff --git a/drivers/clk/loongson/clk-ls1b200.c b/drivers/clk/loongson/clk-ls1b200.c index 66f8e261ac..6ac545224f 100644 --- a/drivers/clk/loongson/clk-ls1b200.c +++ b/drivers/clk/loongson/clk-ls1b200.c @@ -35,21 +35,21 @@ static struct clk *clks[LS1B_CLK_END]; static struct clk_onecell_data clk_data; struct clk_ls1b200 { - struct clk clk; + struct clk_hw hw; void __iomem *base; int div_shift; int div_mask; const char *parent; }; -static unsigned long clk_ls1b200_recalc_rate(struct clk *clk, unsigned long parent_rate) +static unsigned long clk_ls1b200_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { int n; unsigned long rate; int pll_freq; struct clk_ls1b200 *ls1bclk; - ls1bclk = container_of(clk, struct clk_ls1b200, clk); + ls1bclk = container_of(hw, struct clk_ls1b200, hw); pll_freq = __raw_readl(ls1bclk->base); n = 12 * 1024; @@ -77,14 +77,14 @@ static struct clk *clk_ls1b200(const char *name, const char *parent, f->div_shift = div_shift; f->div_mask = div_mask; - f->clk.ops = &clk_ls1b200_ops; - f->clk.name = name; - f->clk.parent_names = &f->parent; - f->clk.num_parents = 1; + f->hw.clk.ops = &clk_ls1b200_ops; + f->hw.clk.name = name; + f->hw.clk.parent_names = &f->parent; + f->hw.clk.num_parents = 1; - clk_register(&f->clk); + bclk_register(&f->hw.clk); - return &f->clk; + return &f->hw.clk; } static const char * const cpu_mux[] = {"cpu_div", "oscillator", }; diff --git a/drivers/clk/mvebu/corediv.c b/drivers/clk/mvebu/corediv.c index 1577a2149c..1b7fa12701 100644 --- a/drivers/clk/mvebu/corediv.c +++ b/drivers/clk/mvebu/corediv.c @@ -51,7 +51,7 @@ struct clk_corediv_soc_desc { * existing in the current SoC. */ struct clk_corediv { - struct clk clk; + struct clk_hw hw; void __iomem *reg; const struct clk_corediv_desc *desc; const struct clk_corediv_soc_desc *soc_desc; @@ -70,11 +70,11 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = { #define CORE_CLK_DIV_RATIO_MASK 0xff -#define to_corediv_clk(p) container_of(p, struct clk_corediv, clk) +#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw) -static int clk_corediv_is_enabled(struct clk *clk) +static int clk_corediv_is_enabled(struct clk_hw *hw) { - struct clk_corediv *corediv = to_corediv_clk(clk); + struct clk_corediv *corediv = to_corediv_clk(hw); const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc; const struct clk_corediv_desc *desc = corediv->desc; u32 enable_mask = BIT(desc->fieldbit) << soc_desc->enable_bit_offset; @@ -82,9 +82,9 @@ static int clk_corediv_is_enabled(struct clk *clk) return !!(readl(corediv->reg) & enable_mask); } -static int clk_corediv_enable(struct clk *clk) +static int clk_corediv_enable(struct clk_hw *hw) { - struct clk_corediv *corediv = to_corediv_clk(clk); + struct clk_corediv *corediv = to_corediv_clk(hw); const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc; const struct clk_corediv_desc *desc = corediv->desc; u32 reg; @@ -96,9 +96,9 @@ static int clk_corediv_enable(struct clk *clk) return 0; } -static void clk_corediv_disable(struct clk *clk) +static void clk_corediv_disable(struct clk_hw *hw) { - struct clk_corediv *corediv = to_corediv_clk(clk); + struct clk_corediv *corediv = to_corediv_clk(hw); const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc; const struct clk_corediv_desc *desc = corediv->desc; u32 reg; @@ -108,10 +108,10 @@ static void clk_corediv_disable(struct clk *clk) writel(reg, corediv->reg); } -static unsigned long clk_corediv_recalc_rate(struct clk *clk, +static unsigned long clk_corediv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_corediv *corediv = to_corediv_clk(clk); + struct clk_corediv *corediv = to_corediv_clk(hw); const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc; const struct clk_corediv_desc *desc = corediv->desc; u32 reg, div; @@ -121,7 +121,7 @@ static unsigned long clk_corediv_recalc_rate(struct clk *clk, return parent_rate / div; } -static long clk_corediv_round_rate(struct clk *clk, unsigned long rate, +static long clk_corediv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { /* Valid ratio are 1:4, 1:5, 1:6 and 1:8 */ @@ -136,10 +136,10 @@ static long clk_corediv_round_rate(struct clk *clk, unsigned long rate, return *parent_rate / div; } -static int clk_corediv_set_rate(struct clk *clk, unsigned long rate, +static int clk_corediv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_corediv *corediv = to_corediv_clk(clk); + struct clk_corediv *corediv = to_corediv_clk(hw); const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc; const struct clk_corediv_desc *desc = corediv->desc; u32 reg, div; @@ -225,7 +225,7 @@ static int mvebu_corediv_clk_probe(struct device_d *dev) for (n = 0; n < clk_data.clk_num; n++) { const char *clk_name; - struct clk *clk = &corediv->clk; + struct clk *clk = &corediv->hw.clk; if (of_property_read_string_index(np, "clock-output-names", n, &clk_name)) { @@ -242,7 +242,7 @@ static int mvebu_corediv_clk_probe(struct device_d *dev) corediv->desc = &soc_desc->descs[n]; corediv->reg = base; clk_data.clks[n] = clk; - WARN_ON(IS_ERR_VALUE(clk_register(clk))); + WARN_ON(IS_ERR_VALUE(bclk_register(clk))); } return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); diff --git a/drivers/clk/mxs/clk-div.c b/drivers/clk/mxs/clk-div.c index 104587a8dc..17083a051a 100644 --- a/drivers/clk/mxs/clk-div.c +++ b/drivers/clk/mxs/clk-div.c @@ -28,40 +28,40 @@ struct clk_div { u8 busy; }; -static inline struct clk_div *to_clk_div(struct clk *clk) +static inline struct clk_div *to_clk_div(struct clk_hw *hw) { - struct clk_divider *divider = container_of(clk, struct clk_divider, clk); + struct clk_divider *divider = to_clk_divider(hw); return container_of(divider, struct clk_div, divider); } -static unsigned long clk_div_recalc_rate(struct clk *clk, +static unsigned long clk_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_div *div = to_clk_div(clk); + struct clk_div *div = to_clk_div(hw); - return div->ops->recalc_rate(&div->divider.clk, parent_rate); + return div->ops->recalc_rate(&div->divider.hw, parent_rate); } -static long clk_div_round_rate(struct clk *clk, unsigned long rate, +static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { - struct clk_div *div = to_clk_div(clk); + struct clk_div *div = to_clk_div(hw); - return div->ops->round_rate(&div->divider.clk, rate, prate); + return div->ops->round_rate(&div->divider.hw, rate, prate); } -static int clk_div_set_rate(struct clk *clk, unsigned long rate, +static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_div *div = to_clk_div(clk); + struct clk_div *div = to_clk_div(hw); int ret; - ret = div->ops->set_rate(&div->divider.clk, rate, parent_rate); + ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); if (ret) return ret; - if (clk_is_enabled(clk)) + if (clk_hw_is_enabled(hw)) while (readl(div->reg) & 1 << div->busy); return 0; @@ -82,10 +82,10 @@ struct clk *mxs_clk_div(const char *name, const char *parent_name, div = xzalloc(sizeof(*div)); div->parent = parent_name; - div->divider.clk.name = name; - div->divider.clk.ops = &clk_div_ops; - div->divider.clk.parent_names = &div->parent; - div->divider.clk.num_parents = 1; + div->divider.hw.clk.name = name; + div->divider.hw.clk.ops = &clk_div_ops; + div->divider.hw.clk.parent_names = &div->parent; + div->divider.hw.clk.num_parents = 1; div->reg = reg; div->busy = busy; @@ -96,9 +96,9 @@ struct clk *mxs_clk_div(const char *name, const char *parent_name, div->divider.flags = CLK_DIVIDER_ONE_BASED; div->ops = &clk_divider_ops; - ret = clk_register(&div->divider.clk); + ret = bclk_register(&div->divider.hw.clk); if (ret) return ERR_PTR(ret); - return &div->divider.clk; + return &div->divider.hw.clk; } diff --git a/drivers/clk/mxs/clk-frac.c b/drivers/clk/mxs/clk-frac.c index a9d390121e..6fb479dfad 100644 --- a/drivers/clk/mxs/clk-frac.c +++ b/drivers/clk/mxs/clk-frac.c @@ -23,7 +23,7 @@ * when the divider is adjusted. */ struct clk_frac { - struct clk clk; + struct clk_hw hw; const char *parent; void __iomem *reg; u8 shift; @@ -31,12 +31,12 @@ struct clk_frac { u8 busy; }; -#define to_clk_frac(_hw) container_of(_hw, struct clk_frac, clk) +#define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw) -static unsigned long clk_frac_recalc_rate(struct clk *clk, +static unsigned long clk_frac_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_frac *frac = to_clk_frac(clk); + struct clk_frac *frac = to_clk_frac(hw); u32 div; div = readl(frac->reg) >> frac->shift; @@ -45,10 +45,10 @@ static unsigned long clk_frac_recalc_rate(struct clk *clk, return (parent_rate >> frac->width) * div; } -static long clk_frac_round_rate(struct clk *clk, unsigned long rate, +static long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { - struct clk_frac *frac = to_clk_frac(clk); + struct clk_frac *frac = to_clk_frac(hw); unsigned long parent_rate = *prate; u32 div; u64 tmp; @@ -67,10 +67,10 @@ static long clk_frac_round_rate(struct clk *clk, unsigned long rate, return (parent_rate >> frac->width) * div; } -static int clk_frac_set_rate(struct clk *clk, unsigned long rate, +static int clk_frac_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_frac *frac = to_clk_frac(clk); + struct clk_frac *frac = to_clk_frac(hw); u32 div, val; u64 tmp; @@ -90,7 +90,7 @@ static int clk_frac_set_rate(struct clk *clk, unsigned long rate, val |= div << frac->shift; writel(val, frac->reg); - if (clk_is_enabled(clk)) + if (clk_hw_is_enabled(hw)) while (readl(frac->reg) & 1 << frac->busy); return 0; @@ -113,18 +113,18 @@ struct clk *mxs_clk_frac(const char *name, const char *parent_name, return ERR_PTR(-ENOMEM); frac->parent = parent_name; - frac->clk.name = name; - frac->clk.ops = &clk_frac_ops; - frac->clk.parent_names = &frac->parent; - frac->clk.num_parents = 1; + frac->hw.clk.name = name; + frac->hw.clk.ops = &clk_frac_ops; + frac->hw.clk.parent_names = &frac->parent; + frac->hw.clk.num_parents = 1; frac->reg = reg; frac->shift = shift; frac->width = width; - ret = clk_register(&frac->clk); + ret = bclk_register(&frac->hw.clk); if (ret) return ERR_PTR(ret); - return &frac->clk; + return &frac->hw.clk; } diff --git a/drivers/clk/mxs/clk-lcdif.c b/drivers/clk/mxs/clk-lcdif.c index 246e68068d..a395701262 100644 --- a/drivers/clk/mxs/clk-lcdif.c +++ b/drivers/clk/mxs/clk-lcdif.c @@ -7,18 +7,18 @@ #include "clk.h" struct clk_lcdif { - struct clk clk; + struct clk_hw hw; struct clk *frac, *div, *gate; const char *parent; }; -#define to_clk_lcdif(_hw) container_of(_hw, struct clk_lcdif, clk) +#define to_clk_lcdif(_hw) container_of(_hw, struct clk_lcdif, hw) -static int clk_lcdif_set_rate(struct clk *clk, unsigned long rate, +static int clk_lcdif_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long unused) { - struct clk_lcdif *lcdif = to_clk_lcdif(clk); + struct clk_lcdif *lcdif = to_clk_lcdif(hw); unsigned long frac, div, best_div = 1; int delta, best_delta = 0x7fffffff; unsigned long frate, rrate, best_frate; @@ -63,14 +63,14 @@ struct clk *mxs_clk_lcdif(const char *name, struct clk *frac, struct clk *div, lcdif->frac = frac; lcdif->div = div; lcdif->gate = gate; - lcdif->clk.name = name; - lcdif->clk.ops = &clk_lcdif_ops; - lcdif->clk.parent_names = &lcdif->parent; - lcdif->clk.num_parents = 1; + lcdif->hw.clk.name = name; + lcdif->hw.clk.ops = &clk_lcdif_ops; + lcdif->hw.clk.parent_names = &lcdif->parent; + lcdif->hw.clk.num_parents = 1; - ret = clk_register(&lcdif->clk); + ret = bclk_register(&lcdif->hw.clk); if (ret) return ERR_PTR(ret); - return &lcdif->clk; + return &lcdif->hw.clk; } diff --git a/drivers/clk/mxs/clk-pll.c b/drivers/clk/mxs/clk-pll.c index 7527a77731..2c55ab7d8b 100644 --- a/drivers/clk/mxs/clk-pll.c +++ b/drivers/clk/mxs/clk-pll.c @@ -24,18 +24,18 @@ * and the shift of gate bit is always 31. */ struct clk_pll { - struct clk clk; + struct clk_hw hw; const char *parent; void __iomem *base; u8 power; unsigned long rate; }; -#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, clk) +#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) -static int clk_pll_enable(struct clk *clk) +static int clk_pll_enable(struct clk_hw *hw) { - struct clk_pll *pll = to_clk_pll(clk); + struct clk_pll *pll = to_clk_pll(hw); writel(1 << pll->power, pll->base + SET); @@ -46,18 +46,18 @@ static int clk_pll_enable(struct clk *clk) return 0; } -static void clk_pll_disable(struct clk *clk) +static void clk_pll_disable(struct clk_hw *hw) { - struct clk_pll *pll = to_clk_pll(clk); + struct clk_pll *pll = to_clk_pll(hw); writel(1 << 31, pll->base + SET); writel(1 << pll->power, pll->base + CLR); } -static int clk_pll_is_enabled(struct clk *clk) +static int clk_pll_is_enabled(struct clk_hw *hw) { - struct clk_pll *pll = to_clk_pll(clk); + struct clk_pll *pll = to_clk_pll(hw); u32 val; val = readl(pll->base); @@ -68,10 +68,10 @@ static int clk_pll_is_enabled(struct clk *clk) return 1; } -static unsigned long clk_pll_recalc_rate(struct clk *clk, +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_pll *pll = to_clk_pll(clk); + struct clk_pll *pll = to_clk_pll(hw); return pll->rate; } @@ -92,18 +92,18 @@ struct clk *mxs_clk_pll(const char *name, const char *parent_name, pll = xzalloc(sizeof(*pll)); pll->parent = parent_name; - pll->clk.name = name; - pll->clk.ops = &clk_pll_ops; - pll->clk.parent_names = &pll->parent; - pll->clk.num_parents = 1; + pll->hw.clk.name = name; + pll->hw.clk.ops = &clk_pll_ops; + pll->hw.clk.parent_names = &pll->parent; + pll->hw.clk.num_parents = 1; pll->base = base; pll->rate = rate; pll->power = power; - ret = clk_register(&pll->clk); + ret = bclk_register(&pll->hw.clk); if (ret) ERR_PTR(ret); - return &pll->clk; + return &pll->hw.clk; } diff --git a/drivers/clk/mxs/clk-ref.c b/drivers/clk/mxs/clk-ref.c index 69361f9ac3..d483c9c6b2 100644 --- a/drivers/clk/mxs/clk-ref.c +++ b/drivers/clk/mxs/clk-ref.c @@ -23,20 +23,20 @@ * as pll rate * (18 / FRAC), where FRAC = 18 ~ 35. */ struct clk_ref { - struct clk clk; + struct clk_hw hw; const char *parent; void __iomem *reg; u8 idx; }; -#define to_clk_ref(_hw) container_of(_hw, struct clk_ref, clk) +#define to_clk_ref(_hw) container_of(_hw, struct clk_ref, hw) #define SET 0x4 #define CLR 0x8 -static int clk_ref_is_enabled(struct clk *clk) +static int clk_ref_is_enabled(struct clk_hw *hw) { - struct clk_ref *ref = to_clk_ref(clk); + struct clk_ref *ref = to_clk_ref(hw); u32 reg = readl(ref->reg); if (reg & 1 << ((ref->idx + 1) * 8 - 1)) @@ -45,26 +45,26 @@ static int clk_ref_is_enabled(struct clk *clk) return 1; } -static int clk_ref_enable(struct clk *clk) +static int clk_ref_enable(struct clk_hw *hw) { - struct clk_ref *ref = to_clk_ref(clk); + struct clk_ref *ref = to_clk_ref(hw); writel(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR); return 0; } -static void clk_ref_disable(struct clk *clk) +static void clk_ref_disable(struct clk_hw *hw) { - struct clk_ref *ref = to_clk_ref(clk); + struct clk_ref *ref = to_clk_ref(hw); writel(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET); } -static unsigned long clk_ref_recalc_rate(struct clk *clk, +static unsigned long clk_ref_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_ref *ref = to_clk_ref(clk); + struct clk_ref *ref = to_clk_ref(hw); u64 tmp = parent_rate; u8 frac = (readl(ref->reg) >> (ref->idx * 8)) & 0x3f; @@ -74,7 +74,7 @@ static unsigned long clk_ref_recalc_rate(struct clk *clk, return tmp; } -static long clk_ref_round_rate(struct clk *clk, unsigned long rate, +static long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { unsigned long parent_rate = *prate; @@ -97,10 +97,10 @@ static long clk_ref_round_rate(struct clk *clk, unsigned long rate, return tmp; } -static int clk_ref_set_rate(struct clk *clk, unsigned long rate, +static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct clk_ref *ref = to_clk_ref(clk); + struct clk_ref *ref = to_clk_ref(hw); u64 tmp = parent_rate; u32 val; u32 frac, shift = ref->idx * 8; @@ -140,17 +140,17 @@ struct clk *mxs_clk_ref(const char *name, const char *parent_name, ref = xzalloc(sizeof(*ref)); ref->parent = parent_name; - ref->clk.name = name; - ref->clk.ops = &clk_ref_ops; - ref->clk.parent_names = &ref->parent; - ref->clk.num_parents = 1; + ref->hw.clk.name = name; + ref->hw.clk.ops = &clk_ref_ops; + ref->hw.clk.parent_names = &ref->parent; + ref->hw.clk.num_parents = 1; ref->reg = reg; ref->idx = idx; - ret = clk_register(&ref->clk); + ret = bclk_register(&ref->hw.clk); if (ret) return ERR_PTR(ret); - return &ref->clk; + return &ref->hw.clk; } diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 5fcf0c2515..a2461d16c1 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y += clk-cpu.o clk-pll.o clk.o +obj-y += clk-cpu.o clk-pll.o clk.o clk-muxgrf.o clk-mmc-phase.o clk-inverter.o +obj-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-$(CONFIG_ARCH_RK3188) += clk-rk3188.o obj-$(CONFIG_ARCH_RK3288) += clk-rk3288.o +obj-$(CONFIG_ARCH_RK3568) += clk-rk3568.o diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 71a64f71f6..8b5d4a0330 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -34,8 +34,10 @@ #include <malloc.h> #include <io.h> #include <xfuncs.h> -#include "clk.h" #include <linux/barebox-wrapper.h> +#include <linux/clk.h> +#include <linux/spinlock.h> +#include "clk.h" /** * struct rockchip_cpuclk: information about clock supplied to a CPU core. @@ -43,31 +45,34 @@ * @alt_parent: alternate parent clock to use when switching the speed * of the primary parent clock. * @reg_base: base register for cpu-clock values. + * @clk_nb: clock notifier registered for changes in clock speed of the + * primary parent clock. * @rate_count: number of rates in the rate_table * @rate_table: pll-rates and their associated dividers * @reg_data: cpu-specific register settings + * @lock: clock lock */ struct rockchip_cpuclk { - struct clk hw; - + struct clk_hw hw; struct clk *alt_parent; void __iomem *reg_base; unsigned int rate_count; struct rockchip_cpuclk_rate_table *rate_table; const struct rockchip_cpuclk_reg_data *reg_data; + spinlock_t *lock; }; #define to_rockchip_cpuclk_hw(hw) container_of(hw, struct rockchip_cpuclk, hw) -static unsigned long rockchip_cpuclk_recalc_rate(struct clk *hw, +static unsigned long rockchip_cpuclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw); const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; - u32 clksel0 = readl(cpuclk->reg_base + reg_data->core_reg); + u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]); - clksel0 >>= reg_data->div_core_shift; - clksel0 &= reg_data->div_core_mask; + clksel0 >>= reg_data->div_core_shift[0]; + clksel0 &= reg_data->div_core_mask[0]; return parent_rate / (clksel0 + 1); } @@ -76,17 +81,18 @@ static const struct clk_ops rockchip_cpuclk_ops = { }; struct clk *rockchip_clk_register_cpuclk(const char *name, - const char **parent_names, u8 num_parents, + const char *const *parent_names, u8 num_parents, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, - int nrates, void __iomem *reg_base) + int nrates, void __iomem *reg_base, spinlock_t *lock) { struct rockchip_cpuclk *cpuclk; - struct clk *clk; + struct clk_init_data init; + struct clk *clk, *cclk; int ret; - if (num_parents != 2) { - pr_err("%s: needs two parent clocks\n", __func__); + if (num_parents < 2) { + pr_err("%s: needs at least two parent clocks\n", __func__); return ERR_PTR(-EINVAL); } @@ -94,21 +100,28 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, if (!cpuclk) return ERR_PTR(-ENOMEM); - cpuclk->hw.name = name; - cpuclk->hw.parent_names = &parent_names[0]; - cpuclk->hw.num_parents = 1; - cpuclk->hw.ops = &rockchip_cpuclk_ops; + init.name = name; + init.parent_names = &parent_names[reg_data->mux_core_main]; + init.num_parents = 1; + init.ops = &rockchip_cpuclk_ops; /* only allow rate changes when we have a rate table */ - cpuclk->hw.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0; + init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0; + + /* disallow automatic parent changes by ccf */ + init.flags |= CLK_SET_RATE_NO_REPARENT; + + init.flags |= CLK_GET_RATE_NOCACHE; cpuclk->reg_base = reg_base; + cpuclk->lock = lock; cpuclk->reg_data = reg_data; + cpuclk->hw.init = &init; - cpuclk->alt_parent = __clk_lookup(parent_names[1]); + cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]); if (!cpuclk->alt_parent) { - pr_err("%s: could not lookup alternate parent\n", - __func__); + pr_err("%s: could not lookup alternate parent: (%d)\n", + __func__, reg_data->mux_core_alt); ret = -EINVAL; goto free_cpuclk; } @@ -120,37 +133,40 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, goto free_cpuclk; } - clk = __clk_lookup(parent_names[0]); + clk = __clk_lookup(parent_names[reg_data->mux_core_main]); if (!clk) { - pr_err("%s: could not lookup parent clock %s\n", - __func__, parent_names[0]); + pr_err("%s: could not lookup parent clock: (%d) %s\n", + __func__, reg_data->mux_core_main, + parent_names[reg_data->mux_core_main]); ret = -EINVAL; - goto free_cpuclk; + goto free_alt_parent; } if (nrates > 0) { cpuclk->rate_count = nrates; - cpuclk->rate_table = xmemdup(rates, - sizeof(*rates) * nrates - ); + cpuclk->rate_table = kmemdup(rates, + sizeof(*rates) * nrates, + GFP_KERNEL); if (!cpuclk->rate_table) { - pr_err("%s: could not allocate memory for cpuclk rates\n", - __func__); ret = -ENOMEM; - goto free_cpuclk; + goto unregister_notifier; } } - ret = clk_register(&cpuclk->hw); - if (ret) { + cclk = clk_register(NULL, &cpuclk->hw); + if (IS_ERR(cclk)) { pr_err("%s: could not register cpuclk %s\n", __func__, name); + ret = PTR_ERR(cclk); goto free_rate_table; } - return &cpuclk->hw; + return cclk; free_rate_table: kfree(cpuclk->rate_table); +unregister_notifier: +free_alt_parent: + clk_disable(cpuclk->alt_parent); free_cpuclk: kfree(cpuclk); return ERR_PTR(ret); diff --git a/drivers/clk/rockchip/clk-inverter.c b/drivers/clk/rockchip/clk-inverter.c new file mode 100644 index 0000000000..7cdcf15fd8 --- /dev/null +++ b/drivers/clk/rockchip/clk-inverter.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015 Heiko Stuebner <heiko@sntech.de> + */ + +#include <common.h> +#include <of.h> +#include <malloc.h> +#include <io.h> +#include <xfuncs.h> +#include <linux/barebox-wrapper.h> +#include <linux/clk.h> +#include <regmap.h> +#include <linux/spinlock.h> +#include "clk.h" + +struct rockchip_inv_clock { + struct clk_hw hw; + void __iomem *reg; + int shift; + int flags; + spinlock_t *lock; +}; + +#define to_inv_clock(_hw) container_of(_hw, struct rockchip_inv_clock, hw) + +#define INVERTER_MASK 0x1 + +static int rockchip_inv_get_phase(struct clk_hw *hw) +{ + struct rockchip_inv_clock *inv_clock = to_inv_clock(hw); + u32 val; + + val = readl(inv_clock->reg) >> inv_clock->shift; + val &= INVERTER_MASK; + return val ? 180 : 0; +} + +static int rockchip_inv_set_phase(struct clk_hw *hw, int degrees) +{ + struct rockchip_inv_clock *inv_clock = to_inv_clock(hw); + u32 val; + + if (degrees % 180 == 0) { + val = !!degrees; + } else { + pr_err("%s: unsupported phase %d for %s\n", + __func__, degrees, clk_hw_get_name(hw)); + return -EINVAL; + } + + if (inv_clock->flags & ROCKCHIP_INVERTER_HIWORD_MASK) { + writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), + inv_clock->reg); + } else { + unsigned long flags; + u32 reg; + + spin_lock_irqsave(inv_clock->lock, flags); + + reg = readl(inv_clock->reg); + reg &= ~BIT(inv_clock->shift); + reg |= val; + writel(reg, inv_clock->reg); + + spin_unlock_irqrestore(inv_clock->lock, flags); + } + + return 0; +} + +static const struct clk_ops rockchip_inv_clk_ops = { + .get_phase = rockchip_inv_get_phase, + .set_phase = rockchip_inv_set_phase, +}; + +struct clk *rockchip_clk_register_inverter(const char *name, + const char *const *parent_names, u8 num_parents, + void __iomem *reg, int shift, int flags, + spinlock_t *lock) +{ + struct clk_init_data init; + struct rockchip_inv_clock *inv_clock; + struct clk *clk; + + inv_clock = kzalloc(sizeof(*inv_clock), GFP_KERNEL); + if (!inv_clock) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.num_parents = num_parents; + init.flags = CLK_SET_RATE_PARENT; + init.parent_names = parent_names; + init.ops = &rockchip_inv_clk_ops; + + inv_clock->hw.init = &init; + inv_clock->reg = reg; + inv_clock->shift = shift; + inv_clock->flags = flags; + inv_clock->lock = lock; + + clk = clk_register(NULL, &inv_clock->hw); + if (IS_ERR(clk)) + kfree(inv_clock); + + return clk; +} diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c new file mode 100644 index 0000000000..822189a2fd --- /dev/null +++ b/drivers/clk/rockchip/clk-mmc-phase.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2014 Google, Inc + * Author: Alexandru M Stan <amstan@chromium.org> + */ + +#include <common.h> +#include <of.h> +#include <malloc.h> +#include <io.h> +#include <xfuncs.h> +#include <linux/barebox-wrapper.h> +#include <linux/clk.h> +#include <linux/spinlock.h> +#include "clk.h" + +struct rockchip_mmc_clock { + struct clk_hw hw; + void __iomem *reg; + int id; + int shift; + int cached_phase; +}; + +#define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw) + +#define RK3288_MMC_CLKGEN_DIV 2 + +static unsigned long rockchip_mmc_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate / RK3288_MMC_CLKGEN_DIV; +} + +#define ROCKCHIP_MMC_DELAY_SEL BIT(10) +#define ROCKCHIP_MMC_DEGREE_MASK 0x3 +#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 +#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) + +#define PSECS_PER_SEC 1000000000000LL + +/* + * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to + * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. + */ +#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 + +static int rockchip_mmc_get_phase(struct clk_hw *hw) +{ + struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw); + unsigned long rate = clk_hw_get_rate(hw); + u32 raw_value; + u16 degrees; + u32 delay_num = 0; + + /* Constant signal, no measurable phase shift */ + if (!rate) + return 0; + + raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); + + degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; + + if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { + /* degrees/delaynum * 1000000 */ + unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * + 36 * (rate / 10000); + + delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); + delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; + degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000); + } + + return degrees % 360; +} + +static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees) +{ + struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw); + unsigned long rate = clk_hw_get_rate(hw); + u8 nineties, remainder; + u8 delay_num; + u32 raw_value; + u32 delay; + + /* + * The below calculation is based on the output clock from + * MMC host to the card, which expects the phase clock inherits + * the clock rate from its parent, namely the output clock + * provider of MMC host. However, things may go wrong if + * (1) It is orphan. + * (2) It is assigned to the wrong parent. + * + * This check help debug the case (1), which seems to be the + * most likely problem we often face and which makes it difficult + * for people to debug unstable mmc tuning results. + */ + if (!rate) { + pr_err("%s: invalid clk rate\n", __func__); + return -EINVAL; + } + + nineties = degrees / 90; + remainder = (degrees % 90); + + /* + * Due to the inexact nature of the "fine" delay, we might + * actually go non-monotonic. We don't go _too_ monotonic + * though, so we should be OK. Here are options of how we may + * work: + * + * Ideally we end up with: + * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0 + * + * On one extreme (if delay is actually 44ps): + * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0 + * The other (if delay is actually 77ps): + * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90 + * + * It's possible we might make a delay that is up to 25 + * degrees off from what we think we're making. That's OK + * though because we should be REALLY far from any bad range. + */ + + /* + * Convert to delay; do a little extra work to make sure we + * don't overflow 32-bit / 64-bit numbers. + */ + delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ + delay *= remainder; + delay = DIV_ROUND_CLOSEST(delay, + (rate / 1000) * 36 * + (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); + + delay_num = (u8) min_t(u32, delay, 255); + + raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; + raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; + raw_value |= nineties; + writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), + mmc_clock->reg); + + pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n", + clk_hw_get_name(hw), degrees, delay_num, + mmc_clock->reg, raw_value>>(mmc_clock->shift), + rockchip_mmc_get_phase(hw) + ); + + return 0; +} + +static const struct clk_ops rockchip_mmc_clk_ops = { + .recalc_rate = rockchip_mmc_recalc, + .get_phase = rockchip_mmc_get_phase, + .set_phase = rockchip_mmc_set_phase, +}; + +struct clk *rockchip_clk_register_mmc(const char *name, + const char *const *parent_names, u8 num_parents, + void __iomem *reg, int shift) +{ + struct clk_init_data init; + struct rockchip_mmc_clock *mmc_clock; + struct clk *clk; + int ret; + + mmc_clock = kzalloc(sizeof(*mmc_clock), GFP_KERNEL); + if (!mmc_clock) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = 0; + init.num_parents = num_parents; + init.parent_names = parent_names; + init.ops = &rockchip_mmc_clk_ops; + + mmc_clock->hw.init = &init; + mmc_clock->reg = reg; + mmc_clock->shift = shift; + + clk = clk_register(NULL, &mmc_clock->hw); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto err_register; + } + + return clk; + +err_register: + kfree(mmc_clock); + return ERR_PTR(ret); +} diff --git a/drivers/clk/rockchip/clk-muxgrf.c b/drivers/clk/rockchip/clk-muxgrf.c new file mode 100644 index 0000000000..f06fa69514 --- /dev/null +++ b/drivers/clk/rockchip/clk-muxgrf.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <of.h> +#include <malloc.h> +#include <io.h> +#include <xfuncs.h> +#include <linux/barebox-wrapper.h> +#include <linux/clk.h> +#include <regmap.h> +#include <linux/spinlock.h> +#include "clk.h" + +struct rockchip_muxgrf_clock { + struct clk_hw hw; + struct regmap *regmap; + u32 reg; + u32 shift; + u32 width; + int flags; +}; + +#define to_muxgrf_clock(_hw) container_of(_hw, struct rockchip_muxgrf_clock, hw) + +static int rockchip_muxgrf_get_parent(struct clk_hw *hw) +{ + struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw); + unsigned int mask = GENMASK(mux->width - 1, 0); + unsigned int val; + + regmap_read(mux->regmap, mux->reg, &val); + + val >>= mux->shift; + val &= mask; + + return val; +} + +static int rockchip_muxgrf_set_parent(struct clk_hw *hw, u8 index) +{ + struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw); + unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); + unsigned int val; + + val = index; + val <<= mux->shift; + + if (mux->flags & CLK_MUX_HIWORD_MASK) + return regmap_write(mux->regmap, mux->reg, val | (mask << 16)); + else + return regmap_update_bits(mux->regmap, mux->reg, mask, val); +} + +static const struct clk_ops rockchip_muxgrf_clk_ops = { + .get_parent = rockchip_muxgrf_get_parent, + .set_parent = rockchip_muxgrf_set_parent, +}; + +struct clk *rockchip_clk_register_muxgrf(const char *name, + const char *const *parent_names, u8 num_parents, + int flags, struct regmap *regmap, int reg, + int shift, int width, int mux_flags) +{ + struct rockchip_muxgrf_clock *muxgrf_clock; + struct clk_init_data init; + struct clk *clk; + + if (IS_ERR(regmap)) { + pr_err("%s: regmap not available\n", __func__); + return ERR_PTR(-ENOTSUPP); + } + + muxgrf_clock = kzalloc(sizeof(*muxgrf_clock), GFP_KERNEL); + if (!muxgrf_clock) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.num_parents = num_parents; + init.parent_names = parent_names; + init.ops = &rockchip_muxgrf_clk_ops; + + muxgrf_clock->hw.init = &init; + muxgrf_clock->regmap = regmap; + muxgrf_clock->reg = reg; + muxgrf_clock->shift = shift; + muxgrf_clock->width = width; + muxgrf_clock->flags = mux_flags; + + clk = clk_register(NULL, &muxgrf_clock->hw); + if (IS_ERR(clk)) + kfree(muxgrf_clock); + + return clk; +} diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 6bb8156f8c..fdbb016e7f 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -2,6 +2,9 @@ /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> + * + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> */ #include <linux/math64.h> @@ -14,16 +17,19 @@ #include <linux/barebox-wrapper.h> #include "clk.h" #include <xfuncs.h> +#include <regmap.h> +#include <linux/iopoll.h> -#define PLL_MODE_MASK 0x3 +#define PLL_MODE_WIDTH 2 #define PLL_MODE_SLOW 0x0 #define PLL_MODE_NORM 0x1 #define PLL_MODE_DEEP 0x2 +#define PLL_RK3328_MODE_WIDTH 1 struct rockchip_clk_pll { - struct clk hw; + struct clk_hw hw; - struct clk pll_mux; + struct clk_mux pll_mux; const struct clk_ops *pll_mux_ops; void __iomem *reg_base; @@ -33,7 +39,9 @@ struct rockchip_clk_pll { u8 flags; const struct rockchip_pll_rate_table *rate_table; unsigned int rate_count; - char pll_name[20]; + spinlock_t *lock; + + struct rockchip_clk_provider *ctx; }; #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw) @@ -52,7 +60,7 @@ static const struct rockchip_pll_rate_table *rockchip_get_pll_settings( return NULL; } -static long rockchip_pll_round_rate(struct clk *hw, +static long rockchip_pll_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); @@ -74,26 +82,282 @@ static long rockchip_pll_round_rate(struct clk *hw, * The calling set_rate function is responsible for making sure the * grf regmap is available. */ -#define RK3188_PLL_LOCK_REG 0x200080ac - static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) { - int delay = 24000000; - int val; + struct regmap *grf = pll->ctx->grf; + unsigned int val; + int ret; + + ret = regmap_read_poll_timeout(grf, pll->lock_offset, val, + val & BIT(pll->lock_shift), 1000); + if (ret) + pr_err("%s: timeout waiting for pll to lock\n", __func__); + + return ret; +} + +/* + * PLL used in RK3036 + */ + +#define RK3036_PLLCON(i) (i * 0x4) +#define RK3036_PLLCON0_FBDIV_MASK 0xfff +#define RK3036_PLLCON0_FBDIV_SHIFT 0 +#define RK3036_PLLCON0_POSTDIV1_MASK 0x7 +#define RK3036_PLLCON0_POSTDIV1_SHIFT 12 +#define RK3036_PLLCON1_REFDIV_MASK 0x3f +#define RK3036_PLLCON1_REFDIV_SHIFT 0 +#define RK3036_PLLCON1_POSTDIV2_MASK 0x7 +#define RK3036_PLLCON1_POSTDIV2_SHIFT 6 +#define RK3036_PLLCON1_LOCK_STATUS BIT(10) +#define RK3036_PLLCON1_DSMPD_MASK 0x1 +#define RK3036_PLLCON1_DSMPD_SHIFT 12 +#define RK3036_PLLCON1_PWRDOWN BIT(13) +#define RK3036_PLLCON2_FRAC_MASK 0xffffff +#define RK3036_PLLCON2_FRAC_SHIFT 0 + +static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll) +{ + u32 pllcon; + int ret; + + /* + * Lock time typical 250, max 500 input clock cycles @24MHz + * So define a very safe maximum of 1000us, meaning 24000 cycles. + */ + ret = readl_poll_timeout(pll->reg_base + RK3036_PLLCON(1), + pllcon, + pllcon & RK3036_PLLCON1_LOCK_STATUS, + 1000); + if (ret) + pr_err("%s: timeout waiting for pll to lock\n", __func__); + + return ret; +} + +static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll, + struct rockchip_pll_rate_table *rate) +{ + u32 pllcon; + + pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); + rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) + & RK3036_PLLCON0_FBDIV_MASK); + rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) + & RK3036_PLLCON0_POSTDIV1_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); + rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) + & RK3036_PLLCON1_REFDIV_MASK); + rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) + & RK3036_PLLCON1_POSTDIV2_MASK); + rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT) + & RK3036_PLLCON1_DSMPD_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); + rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) + & RK3036_PLLCON2_FRAC_MASK); +} + +static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + struct rockchip_pll_rate_table cur; + u64 rate64 = prate; + + rockchip_rk3036_pll_get_params(pll, &cur); + + rate64 *= cur.fbdiv; + do_div(rate64, cur.refdiv); + + if (cur.dsmpd == 0) { + /* fractional mode */ + u64 frac_rate64 = prate * cur.frac; + + do_div(frac_rate64, cur.refdiv); + rate64 += frac_rate64 >> 24; + } + + do_div(rate64, cur.postdiv1); + do_div(rate64, cur.postdiv2); + + return (unsigned long)rate64; +} + +static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, + const struct rockchip_pll_rate_table *rate) +{ + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; + struct clk_mux *pll_mux = &pll->pll_mux; + struct rockchip_pll_rate_table cur; + u32 pllcon; + int rate_change_remuxed = 0; + int cur_parent; + int ret; + + pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", + __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, + rate->postdiv2, rate->dsmpd, rate->frac); + + rockchip_rk3036_pll_get_params(pll, &cur); + cur.rate = 0; + + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); + if (cur_parent == PLL_MODE_NORM) { + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); + rate_change_remuxed = 1; + } + + /* update pll values */ + writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, + RK3036_PLLCON0_FBDIV_SHIFT) | + HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, + RK3036_PLLCON0_POSTDIV1_SHIFT), + pll->reg_base + RK3036_PLLCON(0)); + + writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, + RK3036_PLLCON1_REFDIV_SHIFT) | + HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, + RK3036_PLLCON1_POSTDIV2_SHIFT) | + HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, + RK3036_PLLCON1_DSMPD_SHIFT), + pll->reg_base + RK3036_PLLCON(1)); + + /* GPLL CON2 is not HIWORD_MASK */ + pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); + pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT); + pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; + writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); /* wait for the pll to lock */ - while (delay > 0) { - val = readl(RK3188_PLL_LOCK_REG); - if (val & BIT(pll->lock_shift)) + ret = rockchip_rk3036_pll_wait_lock(pll); + if (ret) { + pr_warn("%s: pll update unsuccessful, trying to restore old params\n", + __func__); + rockchip_rk3036_pll_set_params(pll, &cur); + } + + if (rate_change_remuxed) + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); + + return ret; +} + +static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + + pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", + __func__, clk_hw_get_name(hw), drate, prate); + + /* Get required rate settings from table */ + rate = rockchip_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, clk_hw_get_name(hw)); + return -EINVAL; + } + + return rockchip_rk3036_pll_set_params(pll, rate); +} + +static int rockchip_rk3036_pll_enable(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3036_PLLCON(1)); + rockchip_rk3036_pll_wait_lock(pll); + + return 0; +} + +static void rockchip_rk3036_pll_disable(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, + RK3036_PLLCON1_PWRDOWN, 0), + pll->reg_base + RK3036_PLLCON(1)); +} + +static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1)); + + return !(pllcon & RK3036_PLLCON1_PWRDOWN); +} + +static int rockchip_rk3036_pll_init(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + struct rockchip_pll_rate_table cur; + unsigned long drate; + + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) + return 0; + + drate = clk_hw_get_rate(hw); + rate = rockchip_get_pll_settings(pll, drate); + + /* when no rate setting for the current rate, rely on clk_set_rate */ + if (!rate) + return 0; + + rockchip_rk3036_pll_get_params(pll, &cur); + + pr_debug("%s: pll %s@%lu: Hz\n", __func__, clk_hw_get_name(hw), + drate); + pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", + cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, + cur.dsmpd, cur.frac); + pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", + rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, + rate->dsmpd, rate->frac); + + if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || + rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || + rate->dsmpd != cur.dsmpd || + (!cur.dsmpd && (rate->frac != cur.frac))) { + struct clk *parent = clk_get_parent(clk_hw_to_clk(hw)); + + if (!parent) { + pr_warn("%s: parent of %s not available\n", + __func__, clk_hw_get_name(hw)); return 0; - delay--; + } + + pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", + __func__, clk_hw_get_name(hw)); + rockchip_rk3036_pll_set_params(pll, rate); } - pr_err("%s: timeout waiting for pll to lock\n", __func__); - return -ETIMEDOUT; + return 0; } -/** +static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = { + .recalc_rate = rockchip_rk3036_pll_recalc_rate, + .enable = rockchip_rk3036_pll_enable, + .disable = rockchip_rk3036_pll_disable, + .is_enabled = rockchip_rk3036_pll_is_enabled, +}; + +static const struct clk_ops rockchip_rk3036_pll_clk_ops = { + .recalc_rate = rockchip_rk3036_pll_recalc_rate, + .round_rate = rockchip_pll_round_rate, + .set_rate = rockchip_rk3036_pll_set_rate, + .enable = rockchip_rk3036_pll_enable, + .disable = rockchip_rk3036_pll_disable, + .is_enabled = rockchip_rk3036_pll_is_enabled, + .init = rockchip_rk3036_pll_init, +}; + +/* * PLL used in RK3066, RK3188 and RK3288 */ @@ -106,75 +370,75 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) #define RK3066_PLLCON0_NR_SHIFT 8 #define RK3066_PLLCON1_NF_MASK 0x1fff #define RK3066_PLLCON1_NF_SHIFT 0 -#define RK3066_PLLCON2_BWADJ_MASK 0xfff -#define RK3066_PLLCON2_BWADJ_SHIFT 0 +#define RK3066_PLLCON2_NB_MASK 0xfff +#define RK3066_PLLCON2_NB_SHIFT 0 #define RK3066_PLLCON3_RESET (1 << 5) #define RK3066_PLLCON3_PWRDOWN (1 << 1) #define RK3066_PLLCON3_BYPASS (1 << 0) -static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk *hw, +static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, + struct rockchip_pll_rate_table *rate) +{ + u32 pllcon; + + pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); + rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) + & RK3066_PLLCON0_NR_MASK) + 1; + rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) + & RK3066_PLLCON0_OD_MASK) + 1; + + pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); + rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) + & RK3066_PLLCON1_NF_MASK) + 1; + + pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); + rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) + & RK3066_PLLCON2_NB_MASK) + 1; +} + +static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); - u64 nf, nr, no, rate64 = prate; + struct rockchip_pll_rate_table cur; + u64 rate64 = prate; u32 pllcon; - pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); + pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); if (pllcon & RK3066_PLLCON3_BYPASS) { pr_debug("%s: pll %s is bypassed\n", __func__, - __clk_get_name(hw)); + clk_hw_get_name(hw)); return prate; } - pllcon = readl(pll->reg_base + RK3066_PLLCON(1)); - nf = (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK; - - pllcon = readl(pll->reg_base + RK3066_PLLCON(0)); - nr = (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK; - no = (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK; + rockchip_rk3066_pll_get_params(pll, &cur); - rate64 *= (nf + 1); - do_div(rate64, nr + 1); - do_div(rate64, no + 1); - - pr_debug("%s: %s rate=%lu\n", - __func__, hw->name, (unsigned long)rate64); + rate64 *= cur.nf; + do_div(rate64, cur.nr); + do_div(rate64, cur.no); return (unsigned long)rate64; } -static int rockchip_rk3066_pll_set_rate(struct clk *hw, unsigned long drate, - unsigned long prate) +static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, + const struct rockchip_pll_rate_table *rate) { - struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); - const struct rockchip_pll_rate_table *rate; - unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate); - struct clk *pll_mux = &pll->pll_mux; const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; + struct clk_mux *pll_mux = &pll->pll_mux; + struct rockchip_pll_rate_table cur; int rate_change_remuxed = 0; int cur_parent; int ret; - if (old_rate == drate) - return 0; - - pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", - __func__, __clk_get_name(hw), old_rate, drate, prate); - - /* Get required rate settings from table */ - rate = rockchip_get_pll_settings(pll, drate); - if (!rate) { - pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, __clk_get_name(hw)); - return -EINVAL; - } - pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n", __func__, rate->rate, rate->nr, rate->no, rate->nf); - cur_parent = pll_mux_ops->get_parent(pll_mux); + rockchip_rk3066_pll_get_params(pll, &cur); + cur.rate = 0; + + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); if (cur_parent == PLL_MODE_NORM) { - pll_mux_ops->set_parent(pll_mux, PLL_MODE_SLOW); + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); rate_change_remuxed = 1; } @@ -189,11 +453,11 @@ static int rockchip_rk3066_pll_set_rate(struct clk *hw, unsigned long drate, RK3066_PLLCON0_OD_SHIFT), pll->reg_base + RK3066_PLLCON(0)); - writel(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, + writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, RK3066_PLLCON1_NF_SHIFT), pll->reg_base + RK3066_PLLCON(1)); - writel(HIWORD_UPDATE(rate->bwadj, RK3066_PLLCON2_BWADJ_MASK, - RK3066_PLLCON2_BWADJ_SHIFT), + writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK, + RK3066_PLLCON2_NB_SHIFT), pll->reg_base + RK3066_PLLCON(2)); /* leave reset and wait the reset_delay */ @@ -204,28 +468,49 @@ static int rockchip_rk3066_pll_set_rate(struct clk *hw, unsigned long drate, /* wait for the pll to lock */ ret = rockchip_pll_wait_lock(pll); if (ret) { - pr_warn("%s: pll did not lock, trying to restore old rate %lu\n", - __func__, old_rate); - rockchip_rk3066_pll_set_rate(hw, old_rate, prate); + pr_warn("%s: pll update unsuccessful, trying to restore old params\n", + __func__); + rockchip_rk3066_pll_set_params(pll, &cur); } if (rate_change_remuxed) - pll_mux_ops->set_parent(pll_mux, PLL_MODE_NORM); + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); return ret; } -static int rockchip_rk3066_pll_enable(struct clk *hw) +static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + + pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", + __func__, clk_hw_get_name(hw), drate, prate); + + /* Get required rate settings from table */ + rate = rockchip_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, clk_hw_get_name(hw)); + return -EINVAL; + } + + return rockchip_rk3066_pll_set_params(pll, rate); +} + +static int rockchip_rk3066_pll_enable(struct clk_hw *hw) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), pll->reg_base + RK3066_PLLCON(3)); + rockchip_pll_wait_lock(pll); return 0; } -static void rockchip_rk3066_pll_disable(struct clk *hw) +static void rockchip_rk3066_pll_disable(struct clk_hw *hw) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); @@ -234,7 +519,7 @@ static void rockchip_rk3066_pll_disable(struct clk *hw) pll->reg_base + RK3066_PLLCON(3)); } -static int rockchip_rk3066_pll_is_enabled(struct clk *hw) +static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); @@ -242,6 +527,38 @@ static int rockchip_rk3066_pll_is_enabled(struct clk *hw) return !(pllcon & RK3066_PLLCON3_PWRDOWN); } +static int rockchip_rk3066_pll_init(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + struct rockchip_pll_rate_table cur; + unsigned long drate; + + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) + return 0; + + drate = clk_hw_get_rate(hw); + rate = rockchip_get_pll_settings(pll, drate); + + /* when no rate setting for the current rate, rely on clk_set_rate */ + if (!rate) + return 0; + + rockchip_rk3066_pll_get_params(pll, &cur); + + pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n", + __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, + rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); + if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf + || rate->nb != cur.nb) { + pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", + __func__, clk_hw_get_name(hw)); + rockchip_rk3066_pll_set_params(pll, rate); + } + + return 0; +} + static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = { .recalc_rate = rockchip_rk3066_pll_recalc_rate, .enable = rockchip_rk3066_pll_enable, @@ -256,44 +573,351 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = { .enable = rockchip_rk3066_pll_enable, .disable = rockchip_rk3066_pll_disable, .is_enabled = rockchip_rk3066_pll_is_enabled, + .init = rockchip_rk3066_pll_init, +}; + +/* + * PLL used in RK3399 + */ + +#define RK3399_PLLCON(i) (i * 0x4) +#define RK3399_PLLCON0_FBDIV_MASK 0xfff +#define RK3399_PLLCON0_FBDIV_SHIFT 0 +#define RK3399_PLLCON1_REFDIV_MASK 0x3f +#define RK3399_PLLCON1_REFDIV_SHIFT 0 +#define RK3399_PLLCON1_POSTDIV1_MASK 0x7 +#define RK3399_PLLCON1_POSTDIV1_SHIFT 8 +#define RK3399_PLLCON1_POSTDIV2_MASK 0x7 +#define RK3399_PLLCON1_POSTDIV2_SHIFT 12 +#define RK3399_PLLCON2_FRAC_MASK 0xffffff +#define RK3399_PLLCON2_FRAC_SHIFT 0 +#define RK3399_PLLCON2_LOCK_STATUS BIT(31) +#define RK3399_PLLCON3_PWRDOWN BIT(0) +#define RK3399_PLLCON3_DSMPD_MASK 0x1 +#define RK3399_PLLCON3_DSMPD_SHIFT 3 + +static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll) +{ + u32 pllcon; + int ret; + + /* + * Lock time typical 250, max 500 input clock cycles @24MHz + * So define a very safe maximum of 1000us, meaning 24000 cycles. + */ + ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2), + pllcon, + pllcon & RK3399_PLLCON2_LOCK_STATUS, + 1000); + if (ret) + pr_err("%s: timeout waiting for pll to lock\n", __func__); + + return ret; +} + +static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll, + struct rockchip_pll_rate_table *rate) +{ + u32 pllcon; + + pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0)); + rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT) + & RK3399_PLLCON0_FBDIV_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1)); + rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT) + & RK3399_PLLCON1_REFDIV_MASK); + rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT) + & RK3399_PLLCON1_POSTDIV1_MASK); + rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT) + & RK3399_PLLCON1_POSTDIV2_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); + rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT) + & RK3399_PLLCON2_FRAC_MASK); + + pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3)); + rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT) + & RK3399_PLLCON3_DSMPD_MASK); +} + +static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + struct rockchip_pll_rate_table cur; + u64 rate64 = prate; + + rockchip_rk3399_pll_get_params(pll, &cur); + + rate64 *= cur.fbdiv; + do_div(rate64, cur.refdiv); + + if (cur.dsmpd == 0) { + /* fractional mode */ + u64 frac_rate64 = prate * cur.frac; + + do_div(frac_rate64, cur.refdiv); + rate64 += frac_rate64 >> 24; + } + + do_div(rate64, cur.postdiv1); + do_div(rate64, cur.postdiv2); + + return (unsigned long)rate64; +} + +static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, + const struct rockchip_pll_rate_table *rate) +{ + const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; + struct clk_mux *pll_mux = &pll->pll_mux; + struct rockchip_pll_rate_table cur; + u32 pllcon; + int rate_change_remuxed = 0; + int cur_parent; + int ret; + + pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", + __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, + rate->postdiv2, rate->dsmpd, rate->frac); + + rockchip_rk3399_pll_get_params(pll, &cur); + cur.rate = 0; + + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); + if (cur_parent == PLL_MODE_NORM) { + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); + rate_change_remuxed = 1; + } + + /* update pll values */ + writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, + RK3399_PLLCON0_FBDIV_SHIFT), + pll->reg_base + RK3399_PLLCON(0)); + + writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK, + RK3399_PLLCON1_REFDIV_SHIFT) | + HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK, + RK3399_PLLCON1_POSTDIV1_SHIFT) | + HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK, + RK3399_PLLCON1_POSTDIV2_SHIFT), + pll->reg_base + RK3399_PLLCON(1)); + + /* xPLL CON2 is not HIWORD_MASK */ + pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); + pllcon &= ~(RK3399_PLLCON2_FRAC_MASK << RK3399_PLLCON2_FRAC_SHIFT); + pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT; + writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2)); + + writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK, + RK3399_PLLCON3_DSMPD_SHIFT), + pll->reg_base + RK3399_PLLCON(3)); + + /* wait for the pll to lock */ + ret = rockchip_rk3399_pll_wait_lock(pll); + if (ret) { + pr_warn("%s: pll update unsuccessful, trying to restore old params\n", + __func__); + rockchip_rk3399_pll_set_params(pll, &cur); + } + + if (rate_change_remuxed) + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); + + return ret; +} + +static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + + pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", + __func__, clk_hw_get_name(hw), drate, prate); + + /* Get required rate settings from table */ + rate = rockchip_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, clk_hw_get_name(hw)); + return -EINVAL; + } + + return rockchip_rk3399_pll_set_params(pll, rate); +} + +static int rockchip_rk3399_pll_enable(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0), + pll->reg_base + RK3399_PLLCON(3)); + rockchip_rk3399_pll_wait_lock(pll); + + return 0; +} + +static void rockchip_rk3399_pll_disable(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + + writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN, + RK3399_PLLCON3_PWRDOWN, 0), + pll->reg_base + RK3399_PLLCON(3)); +} + +static int rockchip_rk3399_pll_is_enabled(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3)); + + return !(pllcon & RK3399_PLLCON3_PWRDOWN); +} + +static int rockchip_rk3399_pll_init(struct clk_hw *hw) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + struct rockchip_pll_rate_table cur; + unsigned long drate; + + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) + return 0; + + drate = clk_hw_get_rate(hw); + rate = rockchip_get_pll_settings(pll, drate); + + /* when no rate setting for the current rate, rely on clk_set_rate */ + if (!rate) + return 0; + + rockchip_rk3399_pll_get_params(pll, &cur); + + pr_debug("%s: pll %s@%lu: Hz\n", __func__, clk_hw_get_name(hw), + drate); + pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", + cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, + cur.dsmpd, cur.frac); + pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", + rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, + rate->dsmpd, rate->frac); + + if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || + rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || + rate->dsmpd != cur.dsmpd || + (!cur.dsmpd && (rate->frac != cur.frac))) { + struct clk *parent = clk_get_parent(clk_hw_to_clk(hw)); + + if (!parent) { + pr_warn("%s: parent of %s not available\n", + __func__, clk_hw_get_name(hw)); + return 0; + } + + pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", + __func__, clk_hw_get_name(hw)); + rockchip_rk3399_pll_set_params(pll, rate); + } + + return 0; +} + +static const struct clk_ops rockchip_rk3399_pll_clk_norate_ops = { + .recalc_rate = rockchip_rk3399_pll_recalc_rate, + .enable = rockchip_rk3399_pll_enable, + .disable = rockchip_rk3399_pll_disable, + .is_enabled = rockchip_rk3399_pll_is_enabled, +}; + +static const struct clk_ops rockchip_rk3399_pll_clk_ops = { + .recalc_rate = rockchip_rk3399_pll_recalc_rate, + .round_rate = rockchip_pll_round_rate, + .set_rate = rockchip_rk3399_pll_set_rate, + .enable = rockchip_rk3399_pll_enable, + .disable = rockchip_rk3399_pll_disable, + .is_enabled = rockchip_rk3399_pll_is_enabled, + .init = rockchip_rk3399_pll_init, }; /* * Common registering of pll clocks */ -struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, - const char *name, const char **parent_names, u8 num_parents, - void __iomem *base, int con_offset, int grf_lock_offset, +struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, + enum rockchip_pll_type pll_type, + const char *name, const char *const *parent_names, + u8 num_parents, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, - u8 clk_pll_flags) + unsigned long flags, u8 clk_pll_flags) { - const char **pll_parents; + const char *pll_parents[3]; + struct clk_init_data init; struct rockchip_clk_pll *pll; - struct clk *pll_mux; - struct clk *mux_clk; - int ret; + struct clk_mux *pll_mux; + struct clk *pll_clk, *mux_clk; + char pll_name[20]; - if (num_parents != 2) { + if ((pll_type != pll_rk3328 && num_parents != 2) || + (pll_type == pll_rk3328 && num_parents != 1)) { pr_err("%s: needs two parent clocks\n", __func__); return ERR_PTR(-EINVAL); } + /* name the actual pll */ + snprintf(pll_name, sizeof(pll_name), "pll_%s", name); + pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) return ERR_PTR(-ENOMEM); - pll_parents = kzalloc(sizeof(char *)*3, GFP_KERNEL); - if (!pll_parents) - return ERR_PTR(-ENOMEM); + /* create the mux on top of the real pll */ + pll->pll_mux_ops = &clk_mux_ops; + pll_mux = &pll->pll_mux; + pll_mux->reg = ctx->reg_base + mode_offset; + pll_mux->shift = mode_shift; + if (pll_type == pll_rk3328) + pll_mux->width = PLL_RK3328_MODE_WIDTH; + else + pll_mux->width = PLL_MODE_WIDTH; + pll_mux->flags = 0; + pll_mux->lock = &ctx->lock; + pll_mux->hw.init = &init; + + if (pll_type == pll_rk3036 || + pll_type == pll_rk3066 || + pll_type == pll_rk3328 || + pll_type == pll_rk3399) + pll_mux->flags |= CLK_MUX_HIWORD_MASK; - /* name the actual pll */ - snprintf(pll->pll_name, sizeof(pll->pll_name), "pll_%s", name); - pll->hw.name = pll->pll_name; + /* the actual muxing is xin24m, pll-output, xin32k */ + pll_parents[0] = parent_names[0]; + pll_parents[1] = pll_name; + pll_parents[2] = parent_names[1]; + + init.name = name; + init.flags = CLK_SET_RATE_PARENT; + init.ops = pll->pll_mux_ops; + init.parent_names = pll_parents; + if (pll_type == pll_rk3328) + init.num_parents = 2; + else + init.num_parents = ARRAY_SIZE(pll_parents); - pll->hw.parent_names = &parent_names[0]; - pll->hw.num_parents = 1; + mux_clk = clk_register(NULL, &pll_mux->hw); + if (IS_ERR(mux_clk)) + goto err_mux; + + /* now create the actual pll */ + init.name = pll_name; + + /* keep all plls untouched for now */ + init.flags = flags | CLK_IGNORE_UNUSED; + + init.parent_names = &parent_names[0]; + init.num_parents = 1; if (rate_table) { int len; @@ -303,61 +927,62 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, len++; pll->rate_count = len; - pll->rate_table = xmemdup(rate_table, + pll->rate_table = kmemdup(rate_table, pll->rate_count * - sizeof(struct rockchip_pll_rate_table) - ); + sizeof(struct rockchip_pll_rate_table), + GFP_KERNEL); WARN(!pll->rate_table, "%s: could not allocate rate table for %s\n", __func__, name); } switch (pll_type) { + case pll_rk3036: + case pll_rk3328: + if (!pll->rate_table || IS_ERR(ctx->grf)) + init.ops = &rockchip_rk3036_pll_clk_norate_ops; + else + init.ops = &rockchip_rk3036_pll_clk_ops; + break; case pll_rk3066: + if (!pll->rate_table || IS_ERR(ctx->grf)) + init.ops = &rockchip_rk3066_pll_clk_norate_ops; + else + init.ops = &rockchip_rk3066_pll_clk_ops; + break; + case pll_rk3399: if (!pll->rate_table) - pll->hw.ops = &rockchip_rk3066_pll_clk_norate_ops; + init.ops = &rockchip_rk3399_pll_clk_norate_ops; else - pll->hw.ops = &rockchip_rk3066_pll_clk_ops; + init.ops = &rockchip_rk3399_pll_clk_ops; break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, name); } + pll->hw.init = &init; pll->type = pll_type; - pll->reg_base = base + con_offset; + pll->reg_base = ctx->reg_base + con_offset; pll->lock_offset = grf_lock_offset; pll->lock_shift = lock_shift; pll->flags = clk_pll_flags; - - ret = clk_register(&pll->hw); - if (ret) { - pr_err("%s: failed to register pll clock %s : %d\n", - __func__, name, ret); - mux_clk = &pll->hw; - goto err_exit; + pll->lock = &ctx->lock; + pll->ctx = ctx; + + pll_clk = clk_register(NULL, &pll->hw); + if (IS_ERR(pll_clk)) { + pr_err("%s: failed to register pll clock %s : %ld\n", + __func__, name, PTR_ERR(pll_clk)); + goto err_pll; } - /* the actual muxing is xin24m, pll-output, xin32k */ - pll_parents[0] = parent_names[0]; - pll_parents[1] = pll->pll_name; - pll_parents[2] = parent_names[1]; - - pll_mux = clk_mux_alloc(name, CLK_SET_RATE_PARENT, base + mode_offset, mode_shift, - PLL_MODE_MASK, pll_parents, 3, 0); - pll->pll_mux_ops = pll_mux->ops; - mux_clk = pll_mux; - - if (pll_type == pll_rk3066) - pll_mux->flags |= CLK_MUX_HIWORD_MASK; - - ret = clk_register(pll_mux); - if (ret) - goto err_exit; - return mux_clk; -err_exit: +err_pll: + clk_unregister(mux_clk); + mux_clk = pll_clk; +err_mux: kfree(pll); return mux_clk; } diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index 61dfb27ef4..8597a9d229 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -20,7 +20,7 @@ enum rk3188_plls { apll, cpll, dpll, gpll, }; -struct rockchip_pll_rate_table rk3188_pll_rates[] = { +static struct rockchip_pll_rate_table rk3188_pll_rates[] = { RK3066_PLL_RATE(2208000000, 1, 92, 1), RK3066_PLL_RATE(2184000000, 1, 91, 1), RK3066_PLL_RATE(2160000000, 1, 90, 1), @@ -82,6 +82,7 @@ struct rockchip_pll_rate_table rk3188_pll_rates[] = { RK3066_PLL_RATE( 504000000, 1, 84, 4), RK3066_PLL_RATE( 456000000, 1, 76, 4), RK3066_PLL_RATE( 408000000, 1, 68, 4), + RK3066_PLL_RATE( 400000000, 3, 100, 2), RK3066_PLL_RATE( 384000000, 2, 128, 4), RK3066_PLL_RATE( 360000000, 1, 60, 4), RK3066_PLL_RATE( 312000000, 1, 52, 4), @@ -145,10 +146,14 @@ static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = { }; static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = { - .core_reg = RK2928_CLKSEL_CON(0), - .div_core_shift = 0, - .div_core_mask = 0x1f, + .core_reg[0] = RK2928_CLKSEL_CON(0), + .div_core_shift[0] = 0, + .div_core_mask[0] = 0x1f, + .num_cores = 1, + .mux_core_alt = 1, + .mux_core_main = 0, .mux_core_shift = 8, + .mux_core_mask = 0x1, }; #define RK3188_DIV_ACLK_CORE_MASK 0x7 @@ -181,10 +186,14 @@ static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = { }; static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = { - .core_reg = RK2928_CLKSEL_CON(0), - .div_core_shift = 9, - .div_core_mask = 0x1f, + .core_reg[0] = RK2928_CLKSEL_CON(0), + .div_core_shift[0] = 9, + .div_core_mask[0] = 0x1f, + .num_cores = 1, + .mux_core_alt = 1, + .mux_core_main = 0, .mux_core_shift = 8, + .mux_core_mask = 0x1, }; PNAME(mux_pll_p) = { "xin24m", "xin32k" }; @@ -195,7 +204,7 @@ PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; PNAME(mux_aclk_cpu_p) = { "apll", "gpll" }; PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" }; PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" }; -PNAME(mux_sclk_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" }; +PNAME(mux_sclk_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" }; PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" }; PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" }; PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" }; @@ -229,6 +238,7 @@ static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = { #define MFLAGS CLK_MUX_HIWORD_MASK #define DFLAGS CLK_DIVIDER_HIWORD_MASK #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) +#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK /* 2 ^ (val + 1) */ static struct clk_div_table div_core_peri_t[] = { @@ -239,6 +249,30 @@ static struct clk_div_table div_core_peri_t[] = { { /* sentinel */ }, }; +static struct rockchip_clk_branch common_hsadc_out_fracmux __initdata = + MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0, + RK2928_CLKSEL_CON(22), 4, 2, MFLAGS); + +static struct rockchip_clk_branch common_spdif_fracmux __initdata = + MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(5), 8, 2, MFLAGS); + +static struct rockchip_clk_branch common_uart0_fracmux __initdata = + MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(13), 8, 2, MFLAGS); + +static struct rockchip_clk_branch common_uart1_fracmux __initdata = + MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(14), 8, 2, MFLAGS); + +static struct rockchip_clk_branch common_uart2_fracmux __initdata = + MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); + +static struct rockchip_clk_branch common_uart3_fracmux __initdata = + MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(16), 8, 2, MFLAGS); + static struct rockchip_clk_branch common_clk_branches[] __initdata = { /* * Clock-Architecture Diagram 2 @@ -251,15 +285,15 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY, div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS), - COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0, + COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 9, GFLAGS), - GATE(0, "hclk_vepu", "aclk_vepu", 0, + GATE(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0, RK2928_CLKGATE_CON(3), 10, GFLAGS), - COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0, + COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(3), 11, GFLAGS), - GATE(0, "hclk_vdpu", "aclk_vdpu", 0, + GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0, RK2928_CLKGATE_CON(3), 12, GFLAGS), GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, @@ -268,14 +302,14 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(0), 2, GFLAGS), - GATE(0, "aclk_cpu", "aclk_cpu_pre", 0, + GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, RK2928_CLKGATE_CON(0), 3, GFLAGS), GATE(0, "atclk_cpu", "pclk_cpu_pre", 0, RK2928_CLKGATE_CON(0), 6, GFLAGS), - GATE(0, "pclk_cpu", "pclk_cpu_pre", 0, + GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", 0, RK2928_CLKGATE_CON(0), 5, GFLAGS), - GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED, + GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 4, GFLAGS), COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, @@ -285,12 +319,12 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 4, GFLAGS), - GATE(0, "aclk_peri", "aclk_peri_pre", 0, + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0, RK2928_CLKGATE_CON(2), 1, GFLAGS), - COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_pre", 0, + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", 0, RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(2), 2, GFLAGS), - COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_pre", 0, + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", 0, RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(2), 3, GFLAGS), @@ -304,14 +338,18 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { GATE(0, "pclkin_cif0", "ext_cif0", 0, RK2928_CLKGATE_CON(3), 3, GFLAGS), + INVERTER(0, "pclk_cif0", "pclkin_cif0", + RK2928_CLKSEL_CON(30), 8, IFLAGS), + + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), /* * the 480m are generated inside the usb block from these clocks, * but they are also a source for the hsicphy clock. */ - GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED, + GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(1), 5, GFLAGS), - GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED, + GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(1), 6, GFLAGS), COMPOSITE(0, "mac_src", mux_mac_p, 0, @@ -319,17 +357,18 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKGATE_CON(2), 5, GFLAGS), MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(21), 4, 1, MFLAGS), - GATE(0, "sclk_mac_lbtest", "sclk_macref", - RK2928_CLKGATE_CON(2), 12, 0, GFLAGS), + GATE(0, "sclk_mac_lbtest", "sclk_macref", 0, + RK2928_CLKGATE_CON(2), 12, GFLAGS), COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0, RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS, RK2928_CLKGATE_CON(2), 6, GFLAGS), - COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", 0, + COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0, RK2928_CLKSEL_CON(23), 0, - RK2928_CLKGATE_CON(2), 7, GFLAGS), - MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0, - RK2928_CLKSEL_CON(22), 4, 2, MFLAGS), + RK2928_CLKGATE_CON(2), 7, GFLAGS, + &common_hsadc_out_fracmux), + INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out", + RK2928_CLKSEL_CON(22), 7, IFLAGS), COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, RK2928_CLKSEL_CON(24), 8, 8, DFLAGS, @@ -338,18 +377,17 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0, RK2928_CLKSEL_CON(5), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 13, GFLAGS), - COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0, + COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(9), 0, - RK2928_CLKGATE_CON(0), 14, GFLAGS), - MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, - RK2928_CLKSEL_CON(5), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(0), 14, GFLAGS, + &common_spdif_fracmux), /* * Clock-Architecture Diagram 4 */ - GATE(SCLK_SMC, "sclk_smc", "hclk_peri", - RK2928_CLKGATE_CON(2), 4, 0, GFLAGS), + GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0, + RK2928_CLKGATE_CON(2), 4, GFLAGS), COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0, RK2928_CLKSEL_CON(25), 0, 7, DFLAGS, @@ -373,35 +411,31 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0, RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 8, GFLAGS), - COMPOSITE_FRAC(0, "uart0_frac", "uart0_pre", 0, + COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(17), 0, - RK2928_CLKGATE_CON(1), 9, GFLAGS), - MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0, - RK2928_CLKSEL_CON(13), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(1), 9, GFLAGS, + &common_uart0_fracmux), COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0, RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 10, GFLAGS), - COMPOSITE_FRAC(0, "uart1_frac", "uart1_pre", 0, + COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(18), 0, - RK2928_CLKGATE_CON(1), 11, GFLAGS), - MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0, - RK2928_CLKSEL_CON(14), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(1), 11, GFLAGS, + &common_uart1_fracmux), COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0, RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), - COMPOSITE_FRAC(0, "uart2_frac", "uart2_pre", 0, + COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(19), 0, - RK2928_CLKGATE_CON(1), 13, GFLAGS), - MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0, - RK2928_CLKSEL_CON(15), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(1), 13, GFLAGS, + &common_uart2_fracmux), COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0, RK2928_CLKSEL_CON(16), 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 14, GFLAGS), - COMPOSITE_FRAC(0, "uart3_frac", "uart3_pre", 0, + COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(20), 0, - RK2928_CLKGATE_CON(1), 15, GFLAGS), - MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0, - RK2928_CLKSEL_CON(16), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(1), 15, GFLAGS, + &common_uart3_fracmux), GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS), @@ -418,7 +452,6 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { /* hclk_cpu gates */ GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS), - GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS), GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS), /* hclk_ahb2apb is part of a clk branch */ @@ -468,8 +501,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS), GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS), - GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS), - GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), + GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS), + GATE(PCLK_PUBL, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS), GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS), @@ -511,6 +544,18 @@ static struct clk_div_table div_aclk_cpu_t[] = { { /* sentinel */ }, }; +static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata = + MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(2), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata = + MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata = + MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(4), 8, 2, MFLAGS); + static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { DIVTBL(0, "aclk_cpu_pre", "armclk", 0, RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t), @@ -535,12 +580,12 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS, RK2928_CLKGATE_CON(3), 1, GFLAGS), - MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0, + MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(27), 4, 1, MFLAGS), COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS, RK2928_CLKGATE_CON(3), 2, GFLAGS), - MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0, + MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(28), 4, 1, MFLAGS), COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0, @@ -551,6 +596,8 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { GATE(0, "pclkin_cif1", "ext_cif1", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS), + INVERTER(0, "pclk_cif1", "pclkin_cif1", + RK2928_CLKSEL_CON(30), 12, IFLAGS), COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS, @@ -561,7 +608,7 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 2, GFLAGS), - COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0, + COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0, RK2928_CLKSEL_CON(34), 0, 16, DFLAGS, RK2928_CLKGATE_CON(2), 15, GFLAGS), @@ -570,37 +617,35 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, RK2928_CLKSEL_CON(2), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 7, GFLAGS), - COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0, + COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(6), 0, - RK2928_CLKGATE_CON(0), 8, GFLAGS), - MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0, - RK2928_CLKSEL_CON(2), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(0), 8, GFLAGS, + &rk3066a_i2s0_fracmux), COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0, RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 9, GFLAGS), - COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_pre", 0, + COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(7), 0, - RK2928_CLKGATE_CON(0), 10, GFLAGS), - MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0, - RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(0), 10, GFLAGS, + &rk3066a_i2s1_fracmux), COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0, RK2928_CLKSEL_CON(4), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 11, GFLAGS), - COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_pre", 0, + COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(8), 0, - RK2928_CLKGATE_CON(0), 12, GFLAGS), - MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0, - RK2928_CLKSEL_CON(4), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(0), 12, GFLAGS, + &rk3066a_i2s2_fracmux), - GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), - GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), - GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS), - GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), + GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), + GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), + GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), + GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS), + GATE(HCLK_HDMI, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 14, GFLAGS), - GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS), + GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS), GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS), GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), @@ -621,9 +666,13 @@ static struct clk_div_table div_rk3188_aclk_core_t[] = { { /* sentinel */ }, }; -PNAME(mux_hsicphy_p) = { "sclk_otgphy0", "sclk_otgphy1", +PNAME(mux_hsicphy_p) = { "sclk_otgphy0_480m", "sclk_otgphy1_480m", "gpll", "cpll" }; +static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata = + MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT, + RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); + static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, @@ -677,12 +726,12 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 9, GFLAGS), - COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0, + COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(7), 0, - RK2928_CLKGATE_CON(0), 10, GFLAGS), - MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0, - RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), + RK2928_CLKGATE_CON(0), 10, GFLAGS, + &rk3188_i2s0_fracmux), + GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS), @@ -698,142 +747,104 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), }; -static const char *rk3188_critical_clocks[] __initconst = { +static const char *const rk3188_critical_clocks[] __initconst = { "aclk_cpu", "aclk_peri", "hclk_peri", + "pclk_cpu", + "pclk_peri", + "hclk_cpubus", + "hclk_vio_bus", + "sclk_mac_lbtest", }; - -static void __init rockchip_reparent_clk(char *clock, char *new_parent) -{ - struct clk *clk1, *clk2; - unsigned long rate; - int ret; - - clk1 = __clk_lookup(clock); - clk2 = __clk_lookup(new_parent); - if (!IS_ERR(clk1) && !IS_ERR(clk2)) { - rate = clk_get_rate(clk1); - - ret = clk_set_parent(clk1, clk2); - if (ret < 0) - pr_err("%s: could not reparent %s to %s, ret=%d\n", - __func__, clock, new_parent, ret); - - clk_set_rate(clk1, rate); - } else { - pr_err("%s: missing clocks to reparent %s to %s\n", - __func__, clock, new_parent); - } -} - -static void __init rockchip_clk_set_rate(char *clock, unsigned long rate) -{ - struct clk *clk; - - clk = __clk_lookup(clock); - if(clk && !IS_ERR(clk)) { - clk_set_rate(clk, rate); - return; - } - pr_err("%s: missing clock %s when setting initial rate to %lu\n", - __func__, clock, rate); -} - -static void __init rockchip_clk_set_defaults(void) -{ - struct rockchip_initial_rate { - char *name; - unsigned long rate; - }; - int i; - - struct rockchip_initial_rate rates[] = { - {"gpll", 891000000}, - {"cpll", 600000000}, - {"aclk_cpu", 300000000}, - {"hclk_cpu", 150000000}, - {"pclk_cpu", 75000000}, - {"hclk_ahb2apb", 75000000}, - {"aclk_peri_pre", 150000000}, - {"hclk_peri", 150000000}, - {"pclk_peri", 75000000}, - }; - - rockchip_reparent_clk("aclk_cpu_pre", "gpll"); - rockchip_reparent_clk("mac_src", "dpll"); - rockchip_reparent_clk("aclk_peri_pre", "cpll"); - - for(i = 0; i < ARRAY_SIZE(rates); i++) - rockchip_clk_set_rate(rates[i].name, rates[i].rate); -} - -static void __init rk3188_common_clk_init(struct device_node *np) +static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np) { + struct rockchip_clk_provider *ctx; void __iomem *reg_base; - struct clk *clk; reg_base = of_iomap(np, 0); if (!reg_base) { pr_err("%s: could not map cru region\n", __func__); - return; + return ERR_PTR(-ENOMEM); } - rockchip_clk_init(np, reg_base, CLK_NR_CLKS); - - /* Fixed-clock should be registered before all others */ - clk=clk_fixed("xin24m",24000000); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock xin24m: %ld\n", - __func__, PTR_ERR(clk)); - - /* xin12m is created by an cru-internal divider */ - clk = clk_fixed_factor("xin12m", "xin24m", 1, 2, 0); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock xin12m: %ld\n", - __func__, PTR_ERR(clk)); - - clk = clk_fixed_factor("usb480m", "xin24m", 20, 1, 0); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock usb480m: %ld\n", - __func__, PTR_ERR(clk)); + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + return ERR_PTR(-ENOMEM); + } - rockchip_clk_register_branches(common_clk_branches, + rockchip_clk_register_branches(ctx, common_clk_branches, ARRAY_SIZE(common_clk_branches)); - rockchip_clk_protect_critical(rk3188_critical_clocks, - ARRAY_SIZE(rk3188_critical_clocks)); + + return ctx; } static void __init rk3066a_clk_init(struct device_node *np) { - rk3188_common_clk_init(np); - rockchip_clk_register_plls(rk3066_pll_clks, + struct rockchip_clk_provider *ctx; + + ctx = rk3188_common_clk_init(np); + if (IS_ERR(ctx)) + return; + + rockchip_clk_register_plls(ctx, rk3066_pll_clks, ARRAY_SIZE(rk3066_pll_clks), RK3066_GRF_SOC_STATUS); - rockchip_clk_register_branches(rk3066a_clk_branches, + rockchip_clk_register_branches(ctx, rk3066a_clk_branches, ARRAY_SIZE(rk3066a_clk_branches)); - rockchip_clk_register_armclk(ARMCLK, "armclk", + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", mux_armclk_p, ARRAY_SIZE(mux_armclk_p), &rk3066_cpuclk_data, rk3066_cpuclk_rates, ARRAY_SIZE(rk3066_cpuclk_rates)); + rockchip_clk_protect_critical(rk3188_critical_clocks, + ARRAY_SIZE(rk3188_critical_clocks)); + rockchip_clk_of_add_provider(np, ctx); } CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init); static void __init rk3188a_clk_init(struct device_node *np) { - rk3188_common_clk_init(np); - rockchip_clk_register_plls(rk3188_pll_clks, + struct rockchip_clk_provider *ctx; + struct clk *clk1, *clk2; + unsigned long rate; + int ret; + + ctx = rk3188_common_clk_init(np); + if (IS_ERR(ctx)) + return; + + rockchip_clk_register_plls(ctx, rk3188_pll_clks, ARRAY_SIZE(rk3188_pll_clks), RK3188_GRF_SOC_STATUS); - rockchip_clk_register_branches(rk3188_clk_branches, + rockchip_clk_register_branches(ctx, rk3188_clk_branches, ARRAY_SIZE(rk3188_clk_branches)); - rockchip_clk_register_armclk(ARMCLK, "armclk", + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", mux_armclk_p, ARRAY_SIZE(mux_armclk_p), &rk3188_cpuclk_data, rk3188_cpuclk_rates, ARRAY_SIZE(rk3188_cpuclk_rates)); - rockchip_clk_set_defaults(); + /* reparent aclk_cpu_pre from apll */ + clk1 = __clk_lookup("aclk_cpu_pre"); + clk2 = __clk_lookup("gpll"); + if (clk1 && clk2) { + rate = clk_get_rate(clk1); + + ret = clk_set_parent(clk1, clk2); + if (ret < 0) + pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n", + __func__); + + clk_set_rate(clk1, rate); + } else { + pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n", + __func__); + } + + rockchip_clk_protect_critical(rk3188_critical_clocks, + ARRAY_SIZE(rk3188_critical_clocks)); + rockchip_clk_of_add_provider(np, ctx); } CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init); @@ -850,7 +861,7 @@ static void __init rk3188_clk_init(struct device_node *np) rate = pll->rate_table; while (rate->rate > 0) { - rate->bwadj = 0; + rate->nb = 1; rate++; } } diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index b6c122d393..fc9554e0f3 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -16,6 +16,11 @@ #define RK3288_GRF_SOC_CON(x) (0x244 + x * 4) #define RK3288_GRF_SOC_STATUS1 0x284 +enum rk3288_variant { + RK3288_CRU, + RK3288W_CRU, +}; + enum rk3288_plls { apll, dpll, cpll, gpll, npll, }; @@ -76,24 +81,44 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { RK3066_PLL_RATE( 768000000, 1, 64, 2), RK3066_PLL_RATE( 742500000, 8, 495, 2), RK3066_PLL_RATE( 696000000, 1, 58, 2), + RK3066_PLL_RATE_NB(621000000, 1, 207, 8, 1), RK3066_PLL_RATE( 600000000, 1, 50, 2), - RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1), + RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1), RK3066_PLL_RATE( 552000000, 1, 46, 2), RK3066_PLL_RATE( 504000000, 1, 84, 4), RK3066_PLL_RATE( 500000000, 3, 125, 2), RK3066_PLL_RATE( 456000000, 1, 76, 4), + RK3066_PLL_RATE( 428000000, 1, 107, 6), RK3066_PLL_RATE( 408000000, 1, 68, 4), RK3066_PLL_RATE( 400000000, 3, 100, 2), + RK3066_PLL_RATE_NB( 394000000, 1, 197, 12, 1), RK3066_PLL_RATE( 384000000, 2, 128, 4), RK3066_PLL_RATE( 360000000, 1, 60, 4), + RK3066_PLL_RATE_NB( 356000000, 1, 178, 12, 1), + RK3066_PLL_RATE_NB( 324000000, 1, 189, 14, 1), RK3066_PLL_RATE( 312000000, 1, 52, 4), - RK3066_PLL_RATE( 300000000, 1, 50, 4), - RK3066_PLL_RATE( 297000000, 2, 198, 8), + RK3066_PLL_RATE_NB( 308000000, 1, 154, 12, 1), + RK3066_PLL_RATE_NB( 303000000, 1, 202, 16, 1), + RK3066_PLL_RATE( 300000000, 1, 75, 6), + RK3066_PLL_RATE_NB( 297750000, 2, 397, 16, 1), + RK3066_PLL_RATE_NB( 293250000, 2, 391, 16, 1), + RK3066_PLL_RATE_NB( 292500000, 1, 195, 16, 1), + RK3066_PLL_RATE( 273600000, 1, 114, 10), + RK3066_PLL_RATE_NB( 273000000, 1, 182, 16, 1), + RK3066_PLL_RATE_NB( 270000000, 1, 180, 16, 1), + RK3066_PLL_RATE_NB( 266250000, 2, 355, 16, 1), + RK3066_PLL_RATE_NB( 256500000, 1, 171, 16, 1), RK3066_PLL_RATE( 252000000, 1, 84, 8), - RK3066_PLL_RATE( 216000000, 1, 72, 8), - RK3066_PLL_RATE( 148500000, 2, 99, 8), + RK3066_PLL_RATE_NB( 250500000, 1, 167, 16, 1), + RK3066_PLL_RATE_NB( 243428571, 1, 142, 14, 1), + RK3066_PLL_RATE( 238000000, 1, 119, 12), + RK3066_PLL_RATE_NB( 219750000, 2, 293, 16, 1), + RK3066_PLL_RATE_NB( 216000000, 1, 144, 16, 1), + RK3066_PLL_RATE_NB( 213000000, 1, 142, 16, 1), + RK3066_PLL_RATE( 195428571, 1, 114, 14), + RK3066_PLL_RATE( 160000000, 1, 80, 12), + RK3066_PLL_RATE( 157500000, 1, 105, 16), RK3066_PLL_RATE( 126000000, 1, 84, 16), - RK3066_PLL_RATE( 48000000, 1, 64, 32), { /* sentinel */ }, }; @@ -155,10 +180,14 @@ static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = { }; static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = { - .core_reg = RK3288_CLKSEL_CON(0), - .div_core_shift = 8, - .div_core_mask = 0x1f, + .core_reg[0] = RK3288_CLKSEL_CON(0), + .div_core_shift[0] = 8, + .div_core_mask[0] = 0x1f, + .num_cores = 1, + .mux_core_alt = 1, + .mux_core_main = 0, .mux_core_shift = 15, + .mux_core_mask = 0x1, }; PNAME(mux_pll_p) = { "xin24m", "xin32k" }; @@ -169,8 +198,8 @@ PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" }; PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; -PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usbphy480m_src" }; -PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "usbphy480m_src", "npll" }; +PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" }; +PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" }; PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" }; PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" }; @@ -188,8 +217,9 @@ PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" }; PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" }; PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" }; -PNAME(mux_usbphy480m_p) = { "sclk_otgphy1", "sclk_otgphy2", - "sclk_otgphy0" }; +PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vdpu", "aclk_vepu" }; +PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m", + "sclk_otgphy0_480m" }; PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" }; PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" }; @@ -216,6 +246,39 @@ static struct clk_div_table div_hclk_cpu_t[] = { #define MFLAGS CLK_MUX_HIWORD_MASK #define DFLAGS CLK_DIVIDER_HIWORD_MASK #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) +#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK + +static struct rockchip_clk_branch rk3288_i2s_fracmux __initdata = + MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(4), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3288_spdif_fracmux __initdata = + MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(5), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3288_spdif_8ch_fracmux __initdata = + MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(40), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3288_uart0_fracmux __initdata = + MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(13), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3288_uart1_fracmux __initdata = + MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(14), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3288_uart2_fracmux __initdata = + MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(15), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3288_uart3_fracmux __initdata = + MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(16), 8, 2, MFLAGS); + +static struct rockchip_clk_branch rk3288_uart4_fracmux __initdata = + MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT, + RK3288_CLKSEL_CON(3), 8, 2, MFLAGS); static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { /* @@ -287,20 +350,21 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKGATE_CON(0), 4, GFLAGS), GATE(0, "c2c_host", "aclk_cpu_src", 0, RK3288_CLKGATE_CON(13), 8, GFLAGS), - COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0, + COMPOSITE_NOMUX(SCLK_CRYPTO, "crypto", "aclk_cpu_pre", 0, RK3288_CLKSEL_CON(26), 6, 2, DFLAGS, RK3288_CLKGATE_CON(5), 4, GFLAGS), GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(0), 7, GFLAGS), + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), + COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS, RK3288_CLKGATE_CON(4), 1, GFLAGS), - COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(8), 0, - RK3288_CLKGATE_CON(4), 2, GFLAGS), - MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(4), 8, 2, MFLAGS), + RK3288_CLKGATE_CON(4), 2, GFLAGS, + &rk3288_i2s_fracmux), COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0, RK3288_CLKSEL_CON(4), 12, 1, MFLAGS, RK3288_CLKGATE_CON(4), 0, GFLAGS), @@ -309,27 +373,28 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(5), 15, 1, MFLAGS), - COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", 0, + COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(5), 0, 7, DFLAGS, RK3288_CLKGATE_CON(4), 4, GFLAGS), - COMPOSITE_FRAC(0, "spdif_frac", "spdif_src", 0, + COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(9), 0, - RK3288_CLKGATE_CON(4), 5, GFLAGS), - COMPOSITE_NODIV(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0, - RK3288_CLKSEL_CON(5), 8, 2, MFLAGS, + RK3288_CLKGATE_CON(4), 5, GFLAGS, + &rk3288_spdif_fracmux), + GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT, RK3288_CLKGATE_CON(4), 6, GFLAGS), - COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0, + COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(40), 0, 7, DFLAGS, RK3288_CLKGATE_CON(4), 7, GFLAGS), - COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_pre", 0, + COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(41), 0, - RK3288_CLKGATE_CON(4), 8, GFLAGS), - COMPOSITE_NODIV(SCLK_SPDIF8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0, - RK3288_CLKSEL_CON(40), 8, 2, MFLAGS, + RK3288_CLKGATE_CON(4), 8, GFLAGS, + &rk3288_spdif_8ch_fracmux), + GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT, RK3288_CLKGATE_CON(4), 9, GFLAGS), GATE(0, "sclk_acc_efuse", "xin24m", 0, RK3288_CLKGATE_CON(0), 12, GFLAGS), + GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, RK3288_CLKGATE_CON(1), 0, GFLAGS), GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, @@ -342,6 +407,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKGATE_CON(1), 4, GFLAGS), GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, RK3288_CLKGATE_CON(1), 5, GFLAGS), + /* * Clock-Architecture Diagram 2 */ @@ -352,26 +418,20 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 11, GFLAGS), - /* - * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system, - * so we ignore the mux and make clocks nodes as following, - */ - GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0, + MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT, + RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS), + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0, RK3288_CLKGATE_CON(9), 0, GFLAGS), - /* - * We introduce a virtul node of hclk_vodec_pre_v to split one clock - * struct with a gate and a fix divider into two node in software. - */ - GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0, + + FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, 1, 4, RK3288_CLKGATE_CON(3), 10, GFLAGS), + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, RK3288_CLKGATE_CON(9), 1, GFLAGS), COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3288_CLKGATE_CON(3), 0, GFLAGS), - DIV(0, "hclk_vio", "aclk_vio0", 0, - RK3288_CLKSEL_CON(28), 8, 5, DFLAGS), COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 2, GFLAGS), @@ -425,7 +485,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(26), 8, 1, MFLAGS, RK3288_CLKGATE_CON(3), 7, GFLAGS), - COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0, + COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0, RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS), DIV(0, "pclk_pd_alive", "gpll", 0, @@ -496,11 +556,11 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3288_CLKGATE_CON(4), 10, GFLAGS), - GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED, + GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(13), 4, GFLAGS), - GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED, + GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(13), 5, GFLAGS), - GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", CLK_IGNORE_UNUSED, + GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(13), 6, GFLAGS), GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(13), 7, GFLAGS), @@ -526,45 +586,40 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0, RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS, RK3288_CLKGATE_CON(1), 8, GFLAGS), - COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(17), 0, - RK3288_CLKGATE_CON(1), 9, GFLAGS), - MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(13), 8, 2, MFLAGS), + RK3288_CLKGATE_CON(1), 9, GFLAGS, + &rk3288_uart0_fracmux), MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(13), 15, 1, MFLAGS), COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0, RK3288_CLKSEL_CON(14), 0, 7, DFLAGS, RK3288_CLKGATE_CON(1), 10, GFLAGS), - COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(18), 0, - RK3288_CLKGATE_CON(1), 11, GFLAGS), - MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(14), 8, 2, MFLAGS), + RK3288_CLKGATE_CON(1), 11, GFLAGS, + &rk3288_uart1_fracmux), COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0, RK3288_CLKSEL_CON(15), 0, 7, DFLAGS, RK3288_CLKGATE_CON(1), 12, GFLAGS), - COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(19), 0, - RK3288_CLKGATE_CON(1), 13, GFLAGS), - MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(15), 8, 2, MFLAGS), + RK3288_CLKGATE_CON(1), 13, GFLAGS, + &rk3288_uart2_fracmux), COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0, RK3288_CLKSEL_CON(16), 0, 7, DFLAGS, RK3288_CLKGATE_CON(1), 14, GFLAGS), - COMPOSITE_FRAC(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(20), 0, - RK3288_CLKGATE_CON(1), 15, GFLAGS), - MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(16), 8, 2, MFLAGS), + RK3288_CLKGATE_CON(1), 15, GFLAGS, + &rk3288_uart3_fracmux), COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0, RK3288_CLKSEL_CON(3), 0, 7, DFLAGS, RK3288_CLKGATE_CON(2), 12, GFLAGS), - COMPOSITE_FRAC(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(7), 0, - RK3288_CLKGATE_CON(2), 13, GFLAGS), - MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(3), 8, 2, MFLAGS), + RK3288_CLKGATE_CON(2), 13, GFLAGS, + &rk3288_uart4_fracmux), COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0, RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS, @@ -585,6 +640,8 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKGATE_CON(2), 6, GFLAGS), MUX(0, "sclk_hsadc_out", mux_hsadcout_p, 0, RK3288_CLKSEL_CON(22), 4, 1, MFLAGS), + INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out", + RK3288_CLKSEL_CON(22), 7, IFLAGS), GATE(0, "jtag", "ext_jtag", 0, RK3288_CLKGATE_CON(4), 14, GFLAGS), @@ -632,11 +689,11 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS), GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS), GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS), - GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS), + GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS), GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), - GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS), - GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS), + GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS), + GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS), /* ddrctrl [DDR Controller PHY clock] gates */ GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS), @@ -649,7 +706,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { /* aclk_peri gates */ GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS), GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS), - GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 11, GFLAGS), + GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS), GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS), GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS), GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS), @@ -697,7 +754,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS), GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS), GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS), - GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS), + GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS), /* sclk_gpu gates */ GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS), @@ -712,12 +769,15 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS), GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS), GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS), - GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 12, GFLAGS), + GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS), + + /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */ + SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"), /* pclk_pd_pmu gates */ GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS), GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS), - GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 2, GFLAGS), + GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS), GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS), GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS), @@ -726,7 +786,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS), GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS), GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS), - GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 10, GFLAGS), + GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS), GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS), GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS), GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS), @@ -742,83 +802,106 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { /* aclk_vio0 gates */ GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS), GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS), - GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 11, GFLAGS), + GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS), GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS), /* aclk_vio1 gates */ GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS), GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS), - GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 12, GFLAGS), + GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS), /* aclk_rga_pre gates */ GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS), - GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 13, GFLAGS), + GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS), /* * Other ungrouped clocks. */ GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS), - GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS), + INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS), + GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS), + INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS), +}; + +static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = { + DIV(0, "hclk_vio", "aclk_vio1", 0, + RK3288_CLKSEL_CON(28), 8, 5, DFLAGS), }; -static const char *rk3288_critical_clocks[] __initconst = { +static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = { + DIV(0, "hclk_vio", "aclk_vio0", 0, + RK3288_CLKSEL_CON(28), 8, 5, DFLAGS), +}; + +static const char *const rk3288_critical_clocks[] __initconst = { "aclk_cpu", "aclk_peri", + "aclk_peri_niu", + "aclk_vio0_niu", + "aclk_vio1_niu", + "aclk_rga_niu", "hclk_peri", + "hclk_vio_niu", + "pclk_alive_niu", "pclk_pd_pmu", + "pclk_pmu_niu", + "pmu_hclk_otg0", + /* pwm-regulators on some boards, so handoff-critical later */ + "pclk_rkpwm", }; -static int __init rk3288_clk_init(struct device_node *np) +static void __iomem *rk3288_cru_base; + +static void __init rk3288_common_init(struct device_node *np, + enum rk3288_variant soc) { - void __iomem *reg_base; - struct clk *clk; + struct rockchip_clk_provider *ctx; - reg_base = of_iomap(np, 0); - if (!reg_base) { + rk3288_cru_base = of_iomap(np, 0); + if (!rk3288_cru_base) { pr_err("%s: could not map cru region\n", __func__); - return -ENOMEM; + return; } - rockchip_clk_init(np, reg_base, CLK_NR_CLKS); - - /* xin12m is created by an cru-internal divider */ - clk = clk_fixed_factor("xin12m", "xin24m", 1, 2, 0); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock xin12m: %ld\n", - __func__, PTR_ERR(clk)); - - clk = clk_fixed_factor("usb480m", "xin24m", 20, 1, 0); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock usb480m: %ld\n", - __func__, PTR_ERR(clk)); - - clk = clk_fixed_factor("hclk_vcodec_pre", - "hclk_vcodec_pre_v", 1, 4, 0); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", - __func__, PTR_ERR(clk)); - - /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */ - clk = clk_fixed_factor("pclk_wdt", "pclk_pd_alive", 1, 1, 0); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock pclk_wdt: %ld\n", - __func__, PTR_ERR(clk)); - else - rockchip_clk_add_lookup(clk, PCLK_WDT); + ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + return; + } - rockchip_clk_register_plls(rk3288_pll_clks, + rockchip_clk_register_plls(ctx, rk3288_pll_clks, ARRAY_SIZE(rk3288_pll_clks), RK3288_GRF_SOC_STATUS1); - rockchip_clk_register_branches(rk3288_clk_branches, + rockchip_clk_register_branches(ctx, rk3288_clk_branches, ARRAY_SIZE(rk3288_clk_branches)); + + if (soc == RK3288W_CRU) + rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch, + ARRAY_SIZE(rk3288w_hclkvio_branch)); + else + rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch, + ARRAY_SIZE(rk3288_hclkvio_branch)); + rockchip_clk_protect_critical(rk3288_critical_clocks, ARRAY_SIZE(rk3288_critical_clocks)); - rockchip_clk_register_armclk(ARMCLK, "armclk", + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", mux_armclk_p, ARRAY_SIZE(mux_armclk_p), &rk3288_cpuclk_data, rk3288_cpuclk_rates, ARRAY_SIZE(rk3288_cpuclk_rates)); - return 0; + + rockchip_clk_of_add_provider(np, ctx); +} + +static void __init rk3288_clk_init(struct device_node *np) +{ + rk3288_common_init(np, RK3288_CRU); } CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init); + +static void __init rk3288w_clk_init(struct device_node *np) +{ + rk3288_common_init(np, RK3288W_CRU); +} +CLK_OF_DECLARE(rk3288w_cru, "rockchip,rk3288w-cru", rk3288w_clk_init); diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c new file mode 100644 index 0000000000..4605158500 --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -0,0 +1,1706 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#include <common.h> +#include <linux/clk.h> +#include <of.h> +#include <of_address.h> +#include <linux/barebox-wrapper.h> +#include <init.h> +#include <linux/spinlock.h> +#include <of_device.h> +#include <dt-bindings/clock/rk3568-cru.h> +#include "clk.h" + +#define RK3568_GRF_SOC_STATUS0 0x580 + +enum rk3568_pmu_plls { + ppll, hpll, +}; + +enum rk3568_plls { + apll, dpll, gpll, cpll, npll, vpll, +}; + +static struct rockchip_pll_rate_table rk3568_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), + RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), + RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), + RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), + RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), + RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), + RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), + RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), + RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), + RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), + RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), + RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), + RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0), + RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0), + RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0), + RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0), + RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0), + RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0), + RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0), + RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0), + RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0), + RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0), + RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0), + RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0), + RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0), + RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), + RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), + RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0), + RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), + RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), + RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), + RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), + RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), + RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), + RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), + RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), + { /* sentinel */ }, +}; + +#define RK3568_DIV_ATCLK_CORE_MASK 0x1f +#define RK3568_DIV_ATCLK_CORE_SHIFT 0 +#define RK3568_DIV_GICCLK_CORE_MASK 0x1f +#define RK3568_DIV_GICCLK_CORE_SHIFT 8 +#define RK3568_DIV_PCLK_CORE_MASK 0x1f +#define RK3568_DIV_PCLK_CORE_SHIFT 0 +#define RK3568_DIV_PERIPHCLK_CORE_MASK 0x1f +#define RK3568_DIV_PERIPHCLK_CORE_SHIFT 8 +#define RK3568_DIV_ACLK_CORE_MASK 0x1f +#define RK3568_DIV_ACLK_CORE_SHIFT 8 + +#define RK3568_DIV_SCLK_CORE_MASK 0xf +#define RK3568_DIV_SCLK_CORE_SHIFT 0 +#define RK3568_MUX_SCLK_CORE_MASK 0x3 +#define RK3568_MUX_SCLK_CORE_SHIFT 8 +#define RK3568_MUX_SCLK_CORE_NPLL_MASK 0x1 +#define RK3568_MUX_SCLK_CORE_NPLL_SHIFT 15 +#define RK3568_MUX_CLK_CORE_APLL_MASK 0x1 +#define RK3568_MUX_CLK_CORE_APLL_SHIFT 7 +#define RK3568_MUX_CLK_PVTPLL_MASK 0x1 +#define RK3568_MUX_CLK_PVTPLL_SHIFT 15 + +#define RK3568_CLKSEL1(_sclk_core) \ +{ \ + .reg = RK3568_CLKSEL_CON(2), \ + .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \ + RK3568_MUX_SCLK_CORE_NPLL_SHIFT) | \ + HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \ + RK3568_MUX_SCLK_CORE_SHIFT) | \ + HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \ + RK3568_DIV_SCLK_CORE_SHIFT), \ +} + +#define RK3568_CLKSEL2(_aclk_core) \ +{ \ + .reg = RK3568_CLKSEL_CON(5), \ + .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \ + RK3568_DIV_ACLK_CORE_SHIFT), \ +} + +#define RK3568_CLKSEL3(_atclk_core, _gic_core) \ +{ \ + .reg = RK3568_CLKSEL_CON(3), \ + .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \ + RK3568_DIV_ATCLK_CORE_SHIFT) | \ + HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \ + RK3568_DIV_GICCLK_CORE_SHIFT), \ +} + +#define RK3568_CLKSEL4(_pclk_core, _periph_core) \ +{ \ + .reg = RK3568_CLKSEL_CON(4), \ + .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \ + RK3568_DIV_PCLK_CORE_SHIFT) | \ + HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \ + RK3568_DIV_PERIPHCLK_CORE_SHIFT), \ +} + +#define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \ +{ \ + .prate = _prate##U, \ + .divs = { \ + RK3568_CLKSEL1(_sclk), \ + RK3568_CLKSEL2(_acore), \ + RK3568_CLKSEL3(_atcore, _gicclk), \ + RK3568_CLKSEL4(_pclk, _periph), \ + }, \ +} + +static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = { + RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7), + RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7), + RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3), + RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3), +}; + +static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = { + .core_reg[0] = RK3568_CLKSEL_CON(0), + .div_core_shift[0] = 0, + .div_core_mask[0] = 0x1f, + .core_reg[1] = RK3568_CLKSEL_CON(0), + .div_core_shift[1] = 8, + .div_core_mask[1] = 0x1f, + .core_reg[2] = RK3568_CLKSEL_CON(1), + .div_core_shift[2] = 0, + .div_core_mask[2] = 0x1f, + .core_reg[3] = RK3568_CLKSEL_CON(1), + .div_core_shift[3] = 8, + .div_core_mask[3] = 0x1f, + .num_cores = 4, + .mux_core_alt = 1, + .mux_core_main = 0, + .mux_core_shift = 6, + .mux_core_mask = 0x1, +}; + +PNAME(mux_pll_p) = { "xin24m" }; +PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" }; +PNAME(mux_armclk_p) = { "apll", "gpll" }; +PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half "}; +PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half" }; +PNAME(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" }; +PNAME(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" }; +PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; +PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; +PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; +PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; +PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; +PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; +PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; +PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; +PNAME(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; +PNAME(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" }; +PNAME(clk_rtc32k_pmu_p) = { "clk_32k_pvtm", "xin32k", "clk_rtc32k_frac" }; +PNAME(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" }; +PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" }; +PNAME(npll_gpll_p) = { "npll", "gpll" }; +PNAME(cpll_gpll_p) = { "cpll", "gpll" }; +PNAME(gpll_cpll_p) = { "gpll", "cpll" }; +PNAME(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" }; +PNAME(apll_gpll_npll_p) = { "apll", "gpll", "npll" }; +PNAME(sclk_core_pre_p) = { "sclk_core_src", "npll" }; +PNAME(gpll150_gpll100_gpll75_xin24m_p) = { "gpll_150m", "gpll_100m", "gpll_75m", "xin24m" }; +PNAME(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" }; +PNAME(clk_npu_pre_ndft_p) = { "clk_npu_src", "dummy"}; +PNAME(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" }; +PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" }; +PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" }; +PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" }; +PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" }; +PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" }; +PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" }; +PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" }; +PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" }; +PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" }; +PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" }; +PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" }; +PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" }; +PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" }; +PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" }; +PNAME(gpll300_gpll200_gpll100_p) = { "gpll_300m", "gpll_200m", "gpll_100m" }; +PNAME(clk_nandc_p) = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" }; +PNAME(sclk_sfc_p) = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", "gpll_150m" }; +PNAME(gpll200_gpll150_cpll125_p) = { "gpll_200m", "gpll_150m", "cpll_125m" }; +PNAME(cclk_emmc_p) = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", "cpll_50m", "clk_osc0_div_375k" }; +PNAME(aclk_pipe_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; +PNAME(gpll200_cpll125_p) = { "gpll_200m", "cpll_125m" }; +PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", "gpll_100m", "xin24m" }; +PNAME(clk_sdmmc_p) = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", "cpll_50m", "clk_osc0_div_750k" }; +PNAME(cpll125_cpll50_cpll25_xin24m_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "xin24m" }; +PNAME(clk_gmac_ptp_p) = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" }; +PNAME(cpll333_gpll300_gpll200_p) = { "cpll_333m", "gpll_300m", "gpll_200m" }; +PNAME(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" }; +PNAME(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" }; +PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", "gpll_100m", "xin24m" }; +PNAME(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" }; +PNAME(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" }; +PNAME(gpll400_cpll333_gpll200_p) = { "gpll_400m", "cpll_333m", "gpll_200m" }; +PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", "xin24m" }; +PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" }; +PNAME(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" }; +PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" }; +PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" }; +PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; +PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", "gpll_300m", "xin24m" }; +PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; +PNAME(xin24m_cpll100_p) = { "xin24m", "cpll_100m" }; +PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"}; +PNAME(clk_usbphy0_ref_p) = { "clk_ref24m", "xin_osc0_usbphy0_g" }; +PNAME(clk_usbphy1_ref_p) = { "clk_ref24m", "xin_osc0_usbphy1_g" }; +PNAME(clk_mipidsiphy0_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" }; +PNAME(clk_mipidsiphy1_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" }; +PNAME(clk_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" }; +PNAME(clk_pciephy0_ref_p) = { "clk_pciephy0_osc0", "clk_pciephy0_div" }; +PNAME(clk_pciephy1_ref_p) = { "clk_pciephy1_osc0", "clk_pciephy1_div" }; +PNAME(clk_pciephy2_ref_p) = { "clk_pciephy2_osc0", "clk_pciephy2_div" }; +PNAME(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" }; +PNAME(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" }; +PNAME(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" }; +PNAME(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", "clk_gmac0_xpcs_mii" }; +PNAME(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" }; +PNAME(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" }; +PNAME(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" }; +PNAME(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii" }; +PNAME(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" }; +PNAME(clk_pdpmu_p) = { "ppll", "gpll" }; +PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" }; +PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" }; +PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" }; +PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "dummy_npll", "dummy_vpll" }; + +static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = { + [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p, + 0, RK3568_PMU_PLL_CON(0), + RK3568_PMU_MODE_CON0, 0, 4, 0, rk3568_pll_rates), + [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p, + 0, RK3568_PMU_PLL_CON(16), + RK3568_PMU_MODE_CON0, 2, 7, 0, rk3568_pll_rates), +}; + +static struct rockchip_pll_clock rk3568_pll_clks[] __initdata = { + [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, + 0, RK3568_PLL_CON(0), + RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates), + [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, + 0, RK3568_PLL_CON(8), + RK3568_MODE_CON0, 2, 1, 0, NULL), + [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, + 0, RK3568_PLL_CON(24), + RK3568_MODE_CON0, 4, 2, 0, rk3568_pll_rates), + [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, + 0, RK3568_PLL_CON(16), + RK3568_MODE_CON0, 6, 3, 0, rk3568_pll_rates), + [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, + 0, RK3568_PLL_CON(32), + RK3568_MODE_CON0, 10, 5, 0, rk3568_pll_rates), + [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p, + 0, RK3568_PLL_CON(40), + RK3568_MODE_CON0, 12, 6, 0, rk3568_pll_rates), +}; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata = + MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(11), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata = + MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(13), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata = + MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(15), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata = + MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(17), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_i2s2_2ch_fracmux __initdata = + MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(19), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata = + MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(21), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata = + MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(83), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_spdif_8ch_fracmux __initdata = + MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(23), 15, 1, MFLAGS); + +static struct rockchip_clk_branch rk3568_audpwm_fracmux __initdata = + MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(25), 15, 1, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart1_fracmux __initdata = + MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(52), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart2_fracmux __initdata = + MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(54), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart3_fracmux __initdata = + MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(56), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart4_fracmux __initdata = + MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(58), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart5_fracmux __initdata = + MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(60), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart6_fracmux __initdata = + MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(62), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart7_fracmux __initdata = + MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(64), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart8_fracmux __initdata = + MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(66), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart9_fracmux __initdata = + MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(68), 12, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_uart0_fracmux __initdata = + MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT, + RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_rtc32k_pmu_fracmux __initdata = + MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { + /* + * Clock-Architecture Diagram 1 + */ + /* SRC_CLK */ + COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(75), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 0, GFLAGS), + COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(75), 8, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 1, GFLAGS), + COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(76), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 2, GFLAGS), + COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(76), 8, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 3, GFLAGS), + COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(77), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 4, GFLAGS), + COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(77), 8, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 5, GFLAGS), + COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(78), 0, 6, DFLAGS, + RK3568_CLKGATE_CON(35), 6, GFLAGS), + COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(78), 8, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 7, GFLAGS), + COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(79), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 8, GFLAGS), + COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(79), 8, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 9, GFLAGS), + COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(80), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 10, GFLAGS), + COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 11, GFLAGS), + COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(80), 8, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 12, GFLAGS), + COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(81), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 13, GFLAGS), + COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(81), 8, 6, DFLAGS, + RK3568_CLKGATE_CON(35), 14, GFLAGS), + COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(82), 8, 6, DFLAGS, + RK3568_CLKGATE_CON(35), 15, GFLAGS), + FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 0, 1, 2), + FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2), + MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, + RK3568_MODE_CON0, 14, 2, MFLAGS), + + /* PD_CORE */ + COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(2), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(0), 7, GFLAGS), + + COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(0), 9, GFLAGS), + COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(4), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(0), 10, GFLAGS), + COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(4), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(0), 11, GFLAGS), + COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(5), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(0), 14, GFLAGS), + COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(5), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(5), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(1), 0, GFLAGS), + + COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(5), 14, 2, MFLAGS, + RK3568_CLKGATE_CON(1), 2, GFLAGS), + + GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0, + RK3568_CLKGATE_CON(1), 10, GFLAGS), + GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0, + RK3568_CLKGATE_CON(1), 11, GFLAGS), + GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(1), 12, GFLAGS), + GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0, + RK3568_CLKGATE_CON(1), 9, GFLAGS), + + /* PD_GPU */ + COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3568_CLKGATE_CON(2), 0, GFLAGS), + MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY), + DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0, + RK3568_CLKSEL_CON(6), 8, 2, DFLAGS), + DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0, + RK3568_CLKSEL_CON(6), 12, 4, DFLAGS), + GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0, + RK3568_CLKGATE_CON(2), 3, GFLAGS), + + GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0, + RK3568_CLKGATE_CON(2), 6, GFLAGS), + GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, + RK3568_CLKGATE_CON(2), 7, GFLAGS), + GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0, + RK3568_CLKGATE_CON(2), 8, GFLAGS), + GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(2), 9, GFLAGS), + + /* PD_NPU */ + COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0, + RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS, + RK3568_CLKGATE_CON(3), 0, GFLAGS), + MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + RK3568_CLKSEL_CON(7), 8, 1, MFLAGS), + MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(7), 15, 1, MFLAGS), + COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 0, + RK3568_CLKSEL_CON(8), 0, 4, DFLAGS, + RK3568_CLKGATE_CON(3), 2, GFLAGS), + COMPOSITE_NOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 0, + RK3568_CLKSEL_CON(8), 4, 4, DFLAGS, + RK3568_CLKGATE_CON(3), 3, GFLAGS), + GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0, + RK3568_CLKGATE_CON(3), 4, GFLAGS), + GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0, + RK3568_CLKGATE_CON(3), 7, GFLAGS), + GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0, + RK3568_CLKGATE_CON(3), 8, GFLAGS), + + GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0, + RK3568_CLKGATE_CON(3), 9, GFLAGS), + GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, + RK3568_CLKGATE_CON(3), 10, GFLAGS), + GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0, + RK3568_CLKGATE_CON(3), 11, GFLAGS), + GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(3), 12, GFLAGS), + + /* PD_DDR */ + COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(4), 0, GFLAGS), + MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(9), 15, 1, MFLAGS), + + COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(10), 0, 2, DFLAGS, + RK3568_CLKGATE_CON(4), 2, GFLAGS), + GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(4), 15, GFLAGS), + + /* PD_GIC_AUDIO */ + COMPOSITE_NODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", gpll200_gpll150_gpll100_xin24m_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(10), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(5), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(10), 10, 2, MFLAGS, + RK3568_CLKGATE_CON(5), 1, GFLAGS), + GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(5), 8, GFLAGS), + COMPOSITE_NODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", gpll100_gpll75_gpll50_p, 0, + RK3568_CLKSEL_CON(10), 12, 2, MFLAGS, + RK3568_CLKGATE_CON(5), 9, GFLAGS), + GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(5), 4, GFLAGS), + GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(5), 7, GFLAGS), + GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(5), 10, GFLAGS), + GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(5), 11, GFLAGS), + GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(5), 12, GFLAGS), + GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(5), 13, GFLAGS), + + COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(6), 0, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(12), 0, + RK3568_CLKGATE_CON(6), 1, GFLAGS, + &rk3568_i2s0_8ch_tx_fracmux), + GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, + RK3568_CLKGATE_CON(6), 2, GFLAGS), + COMPOSITE_NODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(11), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(6), 3, GFLAGS), + + COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(13), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(6), 4, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(14), 0, + RK3568_CLKGATE_CON(6), 5, GFLAGS, + &rk3568_i2s0_8ch_rx_fracmux), + GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, + RK3568_CLKGATE_CON(6), 6, GFLAGS), + COMPOSITE_NODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(13), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(6), 7, GFLAGS), + + COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(15), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(6), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(16), 0, + RK3568_CLKGATE_CON(6), 9, GFLAGS, + &rk3568_i2s1_8ch_tx_fracmux), + GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, + RK3568_CLKGATE_CON(6), 10, GFLAGS), + COMPOSITE_NODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(15), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(6), 11, GFLAGS), + + COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(6), 12, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(18), 0, + RK3568_CLKGATE_CON(6), 13, GFLAGS, + &rk3568_i2s1_8ch_rx_fracmux), + GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, + RK3568_CLKGATE_CON(6), 14, GFLAGS), + COMPOSITE_NODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(17), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(6), 15, GFLAGS), + + COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(7), 0, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(20), 0, + RK3568_CLKGATE_CON(7), 1, GFLAGS, + &rk3568_i2s2_2ch_fracmux), + GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, + RK3568_CLKGATE_CON(7), 2, GFLAGS), + COMPOSITE_NODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(19), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(7), 3, GFLAGS), + + COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(7), 4, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(22), 0, + RK3568_CLKGATE_CON(7), 5, GFLAGS, + &rk3568_i2s3_2ch_tx_fracmux), + GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0, + RK3568_CLKGATE_CON(7), 6, GFLAGS), + COMPOSITE_NODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(21), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(7), 7, GFLAGS), + + COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(83), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(7), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(84), 0, + RK3568_CLKGATE_CON(7), 9, GFLAGS, + &rk3568_i2s3_2ch_rx_fracmux), + GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0, + RK3568_CLKGATE_CON(7), 10, GFLAGS), + COMPOSITE_NODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(83), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(7), 11, GFLAGS), + + GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(5), 14, GFLAGS), + COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0, + RK3568_CLKSEL_CON(23), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(5), 15, GFLAGS), + GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(7), 12, GFLAGS), + GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(7), 13, GFLAGS), + + COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 0, + RK3568_CLKSEL_CON(23), 14, 1, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(7), 14, GFLAGS), + COMPOSITE_FRACMUX(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(24), 0, + RK3568_CLKGATE_CON(7), 15, GFLAGS, + &rk3568_spdif_8ch_fracmux), + + GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(8), 0, GFLAGS), + COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0, + RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS, + RK3568_CLKGATE_CON(8), 1, GFLAGS), + COMPOSITE_FRACMUX(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(26), 0, + RK3568_CLKGATE_CON(8), 2, GFLAGS, + &rk3568_audpwm_fracmux), + + GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0, + RK3568_CLKGATE_CON(8), 3, GFLAGS), + COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0, + RK3568_CLKSEL_CON(23), 10, 2, MFLAGS, + RK3568_CLKGATE_CON(8), 4, GFLAGS), + GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0, + RK3568_CLKGATE_CON(8), 5, GFLAGS), + GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0, + RK3568_CLKGATE_CON(8), 6, GFLAGS), + + /* PD_SECURE_FLASH */ + COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, 0, + RK3568_CLKSEL_CON(27), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(8), 7, GFLAGS), + COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, 0, + RK3568_CLKSEL_CON(27), 2, 2, MFLAGS, + RK3568_CLKGATE_CON(8), 8, GFLAGS), + GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0, + RK3568_CLKGATE_CON(8), 11, GFLAGS), + GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0, + RK3568_CLKGATE_CON(8), 12, GFLAGS), + COMPOSITE_NODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", gpll200_gpll150_gpll100_p, 0, + RK3568_CLKSEL_CON(27), 4, 2, MFLAGS, + RK3568_CLKGATE_CON(8), 13, GFLAGS), + COMPOSITE_NODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", gpll300_gpll200_gpll100_p, 0, + RK3568_CLKSEL_CON(27), 6, 2, MFLAGS, + RK3568_CLKGATE_CON(8), 14, GFLAGS), + GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0, + RK3568_CLKGATE_CON(8), 15, GFLAGS), + GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(9), 10, GFLAGS), + GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(9), 11, GFLAGS), + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0, + RK3568_CLKGATE_CON(26), 9, GFLAGS), + GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0, + RK3568_CLKGATE_CON(26), 10, GFLAGS), + GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0, + RK3568_CLKGATE_CON(26), 11, GFLAGS), + GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0, + RK3568_CLKGATE_CON(9), 0, GFLAGS), + COMPOSITE_NODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 0, + RK3568_CLKSEL_CON(28), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(9), 1, GFLAGS), + GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0, + RK3568_CLKGATE_CON(9), 2, GFLAGS), + GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0, + RK3568_CLKGATE_CON(9), 3, GFLAGS), + COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0, + RK3568_CLKSEL_CON(28), 4, 3, MFLAGS, + RK3568_CLKGATE_CON(9), 4, GFLAGS), + GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0, + RK3568_CLKGATE_CON(9), 5, GFLAGS), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0, + RK3568_CLKGATE_CON(9), 6, GFLAGS), + COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 0, + RK3568_CLKSEL_CON(28), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(9), 7, GFLAGS), + COMPOSITE_NODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 0, + RK3568_CLKSEL_CON(28), 12, 3, MFLAGS, + RK3568_CLKGATE_CON(9), 8, GFLAGS), + GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, + RK3568_CLKGATE_CON(9), 9, GFLAGS), + MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_emmc", RK3568_EMMC_CON0, 1), + MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_emmc", RK3568_EMMC_CON1, 1), + + /* PD_PIPE */ + COMPOSITE_NODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 0, + RK3568_CLKSEL_CON(29), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(10), 0, GFLAGS), + COMPOSITE_NOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 0, + RK3568_CLKSEL_CON(29), 4, 4, DFLAGS, + RK3568_CLKGATE_CON(10), 1, GFLAGS), + GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0, + RK3568_CLKGATE_CON(12), 0, GFLAGS), + GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0, + RK3568_CLKGATE_CON(12), 1, GFLAGS), + GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0, + RK3568_CLKGATE_CON(12), 2, GFLAGS), + GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0, + RK3568_CLKGATE_CON(12), 3, GFLAGS), + GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0, + RK3568_CLKGATE_CON(12), 4, GFLAGS), + GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0, + RK3568_CLKGATE_CON(12), 8, GFLAGS), + GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0, + RK3568_CLKGATE_CON(12), 9, GFLAGS), + GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0, + RK3568_CLKGATE_CON(12), 10, GFLAGS), + GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0, + RK3568_CLKGATE_CON(12), 11, GFLAGS), + GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0, + RK3568_CLKGATE_CON(12), 12, GFLAGS), + GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0, + RK3568_CLKGATE_CON(13), 0, GFLAGS), + GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0, + RK3568_CLKGATE_CON(13), 1, GFLAGS), + GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0, + RK3568_CLKGATE_CON(13), 2, GFLAGS), + GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0, + RK3568_CLKGATE_CON(13), 3, GFLAGS), + GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0, + RK3568_CLKGATE_CON(13), 4, GFLAGS), + GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0, + RK3568_CLKGATE_CON(11), 0, GFLAGS), + GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0, + RK3568_CLKGATE_CON(11), 1, GFLAGS), + GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0, + RK3568_CLKGATE_CON(11), 2, GFLAGS), + GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0, + RK3568_CLKGATE_CON(11), 4, GFLAGS), + GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0, + RK3568_CLKGATE_CON(11), 5, GFLAGS), + GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0, + RK3568_CLKGATE_CON(11), 6, GFLAGS), + GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0, + RK3568_CLKGATE_CON(11), 8, GFLAGS), + GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0, + RK3568_CLKGATE_CON(11), 9, GFLAGS), + GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0, + RK3568_CLKGATE_CON(11), 10, GFLAGS), + GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0, + RK3568_CLKGATE_CON(10), 8, GFLAGS), + GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0, + RK3568_CLKGATE_CON(10), 9, GFLAGS), + COMPOSITE_NODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 0, + RK3568_CLKSEL_CON(29), 8, 1, MFLAGS, + RK3568_CLKGATE_CON(10), 10, GFLAGS), + GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0, + RK3568_CLKGATE_CON(10), 12, GFLAGS), + GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0, + RK3568_CLKGATE_CON(10), 13, GFLAGS), + COMPOSITE_NODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 0, + RK3568_CLKSEL_CON(29), 9, 1, MFLAGS, + RK3568_CLKGATE_CON(10), 14, GFLAGS), + COMPOSITE_NODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 0, + RK3568_CLKSEL_CON(29), 13, 1, MFLAGS, + RK3568_CLKGATE_CON(10), 4, GFLAGS), + GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0, + RK3568_CLKGATE_CON(13), 6, GFLAGS), + + /* PD_PHP */ + COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0, + RK3568_CLKSEL_CON(30), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(14), 8, GFLAGS), + COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 0, + RK3568_CLKSEL_CON(30), 2, 2, MFLAGS, + RK3568_CLKGATE_CON(14), 9, GFLAGS), + COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0, + RK3568_CLKSEL_CON(30), 4, 4, DFLAGS, + RK3568_CLKGATE_CON(14), 10, GFLAGS), + GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0, + RK3568_CLKGATE_CON(15), 0, GFLAGS), + COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0, + RK3568_CLKSEL_CON(30), 8, 3, MFLAGS, + RK3568_CLKGATE_CON(15), 1, GFLAGS), + MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "clk_sdmmc0", RK3568_SDMMC0_CON0, 1), + MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "clk_sdmmc0", RK3568_SDMMC0_CON1, 1), + + GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0, + RK3568_CLKGATE_CON(15), 2, GFLAGS), + COMPOSITE_NODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 0, + RK3568_CLKSEL_CON(30), 12, 3, MFLAGS, + RK3568_CLKGATE_CON(15), 3, GFLAGS), + MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "clk_sdmmc1", RK3568_SDMMC1_CON0, 1), + MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "clk_sdmmc1", RK3568_SDMMC1_CON1, 1), + + GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 0, + RK3568_CLKGATE_CON(15), 5, GFLAGS), + GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 0, + RK3568_CLKGATE_CON(15), 6, GFLAGS), + COMPOSITE_NODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 0, + RK3568_CLKSEL_CON(31), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(15), 7, GFLAGS), + COMPOSITE_NODIV(CLK_MAC0_OUT, "clk_mac0_out", cpll125_cpll50_cpll25_xin24m_p, 0, + RK3568_CLKSEL_CON(31), 14, 2, MFLAGS, + RK3568_CLKGATE_CON(15), 8, GFLAGS), + GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0, + RK3568_CLKGATE_CON(15), 12, GFLAGS), + COMPOSITE_NODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 0, + RK3568_CLKSEL_CON(31), 12, 2, MFLAGS, + RK3568_CLKGATE_CON(15), 4, GFLAGS), + MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3568_CLKSEL_CON(31), 2, 1, MFLAGS), + FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 0, 1, 5), + FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 0, 1, 50), + FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 0, 1, 2), + FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 0, 1, 20), + MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", mux_gmac0_rgmii_speed_p, 0, + RK3568_CLKSEL_CON(31), 4, 2, MFLAGS), + MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", mux_gmac0_rmii_speed_p, 0, + RK3568_CLKSEL_CON(31), 3, 1, MFLAGS), + MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(31), 0, 2, MFLAGS), + + /* PD_USB */ + COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0, + RK3568_CLKSEL_CON(32), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(16), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 0, + RK3568_CLKSEL_CON(32), 2, 2, MFLAGS, + RK3568_CLKGATE_CON(16), 1, GFLAGS), + COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 0, + RK3568_CLKSEL_CON(32), 4, 4, DFLAGS, + RK3568_CLKGATE_CON(16), 2, GFLAGS), + GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0, + RK3568_CLKGATE_CON(16), 12, GFLAGS), + GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0, + RK3568_CLKGATE_CON(16), 13, GFLAGS), + GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0, + RK3568_CLKGATE_CON(16), 14, GFLAGS), + GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0, + RK3568_CLKGATE_CON(16), 15, GFLAGS), + GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0, + RK3568_CLKGATE_CON(17), 0, GFLAGS), + COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0, + RK3568_CLKSEL_CON(32), 8, 3, MFLAGS, + RK3568_CLKGATE_CON(17), 1, GFLAGS), + MMC(SCLK_SDMMC2_DRV, "sdmmc2_drv", "clk_sdmmc2", RK3568_SDMMC2_CON0, 1), + MMC(SCLK_SDMMC2_SAMPLE, "sdmmc2_sample", "clk_sdmmc2", RK3568_SDMMC2_CON1, 1), + + GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0, + RK3568_CLKGATE_CON(17), 3, GFLAGS), + GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0, + RK3568_CLKGATE_CON(17), 4, GFLAGS), + COMPOSITE_NODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 0, + RK3568_CLKSEL_CON(33), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(17), 5, GFLAGS), + COMPOSITE_NODIV(CLK_MAC1_OUT, "clk_mac1_out", cpll125_cpll50_cpll25_xin24m_p, 0, + RK3568_CLKSEL_CON(33), 14, 2, MFLAGS, + RK3568_CLKGATE_CON(17), 6, GFLAGS), + GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0, + RK3568_CLKGATE_CON(17), 10, GFLAGS), + COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 0, + RK3568_CLKSEL_CON(33), 12, 2, MFLAGS, + RK3568_CLKGATE_CON(17), 2, GFLAGS), + MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3568_CLKSEL_CON(33), 2, 1, MFLAGS), + FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 0, 1, 5), + FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 0, 1, 50), + FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 0, 1, 2), + FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 0, 1, 20), + MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", mux_gmac1_rgmii_speed_p, 0, + RK3568_CLKSEL_CON(33), 4, 2, MFLAGS), + MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0, + RK3568_CLKSEL_CON(33), 3, 1, MFLAGS), + MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(33), 0, 2, MFLAGS), + + /* PD_PERI */ + COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(10), 4, 2, MFLAGS, + RK3568_CLKGATE_CON(14), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(10), 6, 2, MFLAGS, + RK3568_CLKGATE_CON(14), 1, GFLAGS), + + /* PD_VI */ + COMPOSITE_NODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 0, + RK3568_CLKSEL_CON(34), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(18), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 0, + RK3568_CLKSEL_CON(34), 4, 4, DFLAGS, + RK3568_CLKGATE_CON(18), 1, GFLAGS), + COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 0, + RK3568_CLKSEL_CON(34), 8, 4, DFLAGS, + RK3568_CLKGATE_CON(18), 2, GFLAGS), + GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0, + RK3568_CLKGATE_CON(18), 9, GFLAGS), + GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0, + RK3568_CLKGATE_CON(18), 10, GFLAGS), + COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 0, + RK3568_CLKSEL_CON(34), 14, 2, MFLAGS, + RK3568_CLKGATE_CON(18), 11, GFLAGS), + GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0, + RK3568_CLKGATE_CON(18), 13, GFLAGS), + GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0, + RK3568_CLKGATE_CON(19), 0, GFLAGS), + GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0, + RK3568_CLKGATE_CON(19), 1, GFLAGS), + COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0, + RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(19), 2, GFLAGS), + GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0, + RK3568_CLKGATE_CON(19), 4, GFLAGS), + COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0, + RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3568_CLKGATE_CON(19), 8, GFLAGS), + COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0, + RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3568_CLKGATE_CON(19), 9, GFLAGS), + COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 0, + RK3568_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3568_CLKGATE_CON(19), 10, GFLAGS), + + /* PD_VO */ + COMPOSITE_NODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 0, + RK3568_CLKSEL_CON(37), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(20), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 0, + RK3568_CLKSEL_CON(37), 8, 4, DFLAGS, + RK3568_CLKGATE_CON(20), 1, GFLAGS), + COMPOSITE_NOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 0, + RK3568_CLKSEL_CON(37), 12, 4, DFLAGS, + RK3568_CLKGATE_CON(20), 2, GFLAGS), + COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0, + RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(20), 6, GFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, + RK3568_CLKGATE_CON(20), 8, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0, + RK3568_CLKGATE_CON(20), 9, GFLAGS), + COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, + RK3568_CLKGATE_CON(20), 10, GFLAGS), + COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, + RK3568_CLKGATE_CON(20), 11, GFLAGS), + COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0, + RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS, + RK3568_CLKGATE_CON(20), 12, GFLAGS), + GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0, + RK3568_CLKGATE_CON(20), 13, GFLAGS), + GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0, + RK3568_CLKGATE_CON(21), 0, GFLAGS), + GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0, + RK3568_CLKGATE_CON(21), 1, GFLAGS), + GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0, + RK3568_CLKGATE_CON(21), 2, GFLAGS), + GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0, + RK3568_CLKGATE_CON(21), 3, GFLAGS), + GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0, + RK3568_CLKGATE_CON(21), 4, GFLAGS), + GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0, + RK3568_CLKGATE_CON(21), 5, GFLAGS), + GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0, + RK3568_CLKGATE_CON(21), 6, GFLAGS), + GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0, + RK3568_CLKGATE_CON(21), 7, GFLAGS), + GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0, + RK3568_CLKGATE_CON(21), 8, GFLAGS), + COMPOSITE_NODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 0, + RK3568_CLKSEL_CON(38), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(21), 9, GFLAGS), + + /* PD_VPU */ + COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0, + RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(22), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, + RK3568_CLKSEL_CON(42), 8, 4, DFLAGS, + RK3568_CLKGATE_CON(22), 1, GFLAGS), + GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, + RK3568_CLKGATE_CON(22), 4, GFLAGS), + GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, + RK3568_CLKGATE_CON(22), 5, GFLAGS), + + /* PD_RGA */ + COMPOSITE_NODIV(ACLK_RGA_PRE, "aclk_rga_pre", gpll300_cpll250_gpll100_xin24m_p, 0, + RK3568_CLKSEL_CON(43), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(23), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 0, + RK3568_CLKSEL_CON(43), 8, 4, DFLAGS, + RK3568_CLKGATE_CON(23), 1, GFLAGS), + COMPOSITE_NOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 0, + RK3568_CLKSEL_CON(43), 12, 4, DFLAGS, + RK3568_CLKGATE_CON(22), 12, GFLAGS), + GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 4, GFLAGS), + GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 5, GFLAGS), + COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0, + RK3568_CLKSEL_CON(43), 2, 2, MFLAGS, + RK3568_CLKGATE_CON(23), 6, GFLAGS), + GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 7, GFLAGS), + GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 8, GFLAGS), + COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0, + RK3568_CLKSEL_CON(43), 4, 2, MFLAGS, + RK3568_CLKGATE_CON(23), 9, GFLAGS), + GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS), + COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0, + RK3568_CLKSEL_CON(43), 6, 2, MFLAGS, + RK3568_CLKGATE_CON(23), 11, GFLAGS), + GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 12, GFLAGS), + GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 13, GFLAGS), + GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 14, GFLAGS), + GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0, + RK3568_CLKGATE_CON(23), 15, GFLAGS), + GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0, + RK3568_CLKGATE_CON(22), 14, GFLAGS), + GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0, + RK3568_CLKGATE_CON(22), 15, GFLAGS), + + /* PD_RKVENC */ + COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0, + RK3568_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(24), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, + RK3568_CLKSEL_CON(44), 8, 4, DFLAGS, + RK3568_CLKGATE_CON(24), 1, GFLAGS), + GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0, + RK3568_CLKGATE_CON(24), 6, GFLAGS), + GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0, + RK3568_CLKGATE_CON(24), 7, GFLAGS), + COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0, + RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(24), 8, GFLAGS), + COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT, + RK3568_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(25), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, + RK3568_CLKSEL_CON(47), 8, 4, DFLAGS, + RK3568_CLKGATE_CON(25), 1, GFLAGS), + GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, + RK3568_CLKGATE_CON(25), 4, GFLAGS), + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, + RK3568_CLKGATE_CON(25), 5, GFLAGS), + COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0, + RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(25), 6, GFLAGS), + COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT, + RK3568_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3568_CLKGATE_CON(25), 7, GFLAGS), + COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0, + RK3568_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(25), 8, GFLAGS), + + /* PD_BUS */ + COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 0, + RK3568_CLKSEL_CON(50), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(26), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 0, + RK3568_CLKSEL_CON(50), 4, 2, MFLAGS, + RK3568_CLKGATE_CON(26), 1, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, + RK3568_CLKGATE_CON(26), 4, GFLAGS), + COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 0, + RK3568_CLKSEL_CON(51), 4, 2, MFLAGS, 0, 3, DFLAGS, + RK3568_CLKGATE_CON(26), 5, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0, + RK3568_CLKSEL_CON(51), 8, 7, DFLAGS, + RK3568_CLKGATE_CON(26), 6, GFLAGS), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, + RK3568_CLKGATE_CON(26), 7, GFLAGS), + GATE(CLK_SARADC, "clk_saradc", "xin24m", 0, + RK3568_CLKGATE_CON(26), 8, GFLAGS), + GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(26), 12, GFLAGS), + GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0, + RK3568_CLKGATE_CON(26), 13, GFLAGS), + GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0, + RK3568_CLKGATE_CON(26), 14, GFLAGS), + GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(32), 13, GFLAGS), + GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED, + RK3568_CLKGATE_CON(32), 14, GFLAGS), + GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, + RK3568_CLKGATE_CON(32), 15, GFLAGS), + + GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, + RK3568_CLKGATE_CON(27), 12, GFLAGS), + COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(27), 13, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(53), 0, + RK3568_CLKGATE_CON(27), 14, GFLAGS, + &rk3568_uart1_fracmux), + GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0, + RK3568_CLKGATE_CON(27), 15, GFLAGS), + + GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, + RK3568_CLKGATE_CON(28), 0, GFLAGS), + COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(28), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(55), 0, + RK3568_CLKGATE_CON(28), 2, GFLAGS, + &rk3568_uart2_fracmux), + GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0, + RK3568_CLKGATE_CON(28), 3, GFLAGS), + + GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, + RK3568_CLKGATE_CON(28), 4, GFLAGS), + COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(28), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(57), 0, + RK3568_CLKGATE_CON(28), 6, GFLAGS, + &rk3568_uart3_fracmux), + GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0, + RK3568_CLKGATE_CON(28), 7, GFLAGS), + + GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0, + RK3568_CLKGATE_CON(28), 8, GFLAGS), + COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(28), 9, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(59), 0, + RK3568_CLKGATE_CON(28), 10, GFLAGS, + &rk3568_uart4_fracmux), + GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0, + RK3568_CLKGATE_CON(28), 11, GFLAGS), + + GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0, + RK3568_CLKGATE_CON(28), 12, GFLAGS), + COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(28), 13, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(61), 0, + RK3568_CLKGATE_CON(28), 14, GFLAGS, + &rk3568_uart5_fracmux), + GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0, + RK3568_CLKGATE_CON(28), 15, GFLAGS), + + GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0, + RK3568_CLKGATE_CON(29), 0, GFLAGS), + COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(29), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(63), 0, + RK3568_CLKGATE_CON(29), 2, GFLAGS, + &rk3568_uart6_fracmux), + GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0, + RK3568_CLKGATE_CON(29), 3, GFLAGS), + + GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0, + RK3568_CLKGATE_CON(29), 4, GFLAGS), + COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(29), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(65), 0, + RK3568_CLKGATE_CON(29), 6, GFLAGS, + &rk3568_uart7_fracmux), + GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0, + RK3568_CLKGATE_CON(29), 7, GFLAGS), + + GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0, + RK3568_CLKGATE_CON(29), 8, GFLAGS), + COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(29), 9, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(67), 0, + RK3568_CLKGATE_CON(29), 10, GFLAGS, + &rk3568_uart8_fracmux), + GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0, + RK3568_CLKGATE_CON(29), 11, GFLAGS), + + GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0, + RK3568_CLKGATE_CON(29), 12, GFLAGS), + COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0, + RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_CLKGATE_CON(29), 13, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, + RK3568_CLKSEL_CON(69), 0, + RK3568_CLKGATE_CON(29), 14, GFLAGS, + &rk3568_uart9_fracmux), + GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0, + RK3568_CLKGATE_CON(29), 15, GFLAGS), + + GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0, + RK3568_CLKGATE_CON(27), 5, GFLAGS), + COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, + RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(27), 6, GFLAGS), + GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0, + RK3568_CLKGATE_CON(27), 7, GFLAGS), + COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, + RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS, + RK3568_CLKGATE_CON(27), 8, GFLAGS), + GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0, + RK3568_CLKGATE_CON(27), 9, GFLAGS), + COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, + RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3568_CLKGATE_CON(27), 10, GFLAGS), + COMPOSITE_NODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 0, + RK3568_CLKSEL_CON(71), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(32), 10, GFLAGS), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 0, GFLAGS), + GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0, + RK3568_CLKGATE_CON(30), 1, GFLAGS), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 2, GFLAGS), + GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0, + RK3568_CLKGATE_CON(30), 3, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 4, GFLAGS), + GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0, + RK3568_CLKGATE_CON(30), 5, GFLAGS), + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 6, GFLAGS), + GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0, + RK3568_CLKGATE_CON(30), 7, GFLAGS), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 8, GFLAGS), + GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0, + RK3568_CLKGATE_CON(30), 9, GFLAGS), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 10, GFLAGS), + COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(72), 0, 1, MFLAGS, + RK3568_CLKGATE_CON(30), 11, GFLAGS), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 12, GFLAGS), + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(72), 2, 1, MFLAGS, + RK3568_CLKGATE_CON(30), 13, GFLAGS), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, + RK3568_CLKGATE_CON(30), 14, GFLAGS), + COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(72), 4, 1, MFLAGS, + RK3568_CLKGATE_CON(30), 15, GFLAGS), + GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0, + RK3568_CLKGATE_CON(31), 0, GFLAGS), + COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS), + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS), + COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(72), 8, 1, MFLAGS, + RK3568_CLKGATE_CON(31), 11, GFLAGS), + GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, + RK3568_CLKGATE_CON(31), 12, GFLAGS), + GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0, + RK3568_CLKGATE_CON(31), 13, GFLAGS), + COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(72), 10, 1, MFLAGS, + RK3568_CLKGATE_CON(31), 14, GFLAGS), + GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, + RK3568_CLKGATE_CON(31), 15, GFLAGS), + GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0, + RK3568_CLKGATE_CON(32), 0, GFLAGS), + COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(72), 12, 1, MFLAGS, + RK3568_CLKGATE_CON(32), 1, GFLAGS), + GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, + RK3568_CLKGATE_CON(32), 2, GFLAGS), + COMPOSITE_NODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 0, + RK3568_CLKSEL_CON(72), 14, 1, MFLAGS, + RK3568_CLKGATE_CON(32), 11, GFLAGS), + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, + RK3568_CLKGATE_CON(31), 2, GFLAGS), + GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0, + RK3568_CLKGATE_CON(31), 3, GFLAGS), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, + RK3568_CLKGATE_CON(31), 4, GFLAGS), + GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0, + RK3568_CLKGATE_CON(31), 5, GFLAGS), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, + RK3568_CLKGATE_CON(31), 6, GFLAGS), + GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0, + RK3568_CLKGATE_CON(31), 7, GFLAGS), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0, + RK3568_CLKGATE_CON(31), 8, GFLAGS), + GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0, + RK3568_CLKGATE_CON(31), 9, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, + RK3568_CLKGATE_CON(32), 3, GFLAGS), + GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0, + RK3568_CLKGATE_CON(32), 4, GFLAGS), + GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0, + RK3568_CLKGATE_CON(32), 5, GFLAGS), + GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0, + RK3568_CLKGATE_CON(32), 6, GFLAGS), + GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0, + RK3568_CLKGATE_CON(32), 7, GFLAGS), + GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0, + RK3568_CLKGATE_CON(32), 8, GFLAGS), + GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0, + RK3568_CLKGATE_CON(32), 9, GFLAGS), + + /* PD_TOP */ + COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, 0, + RK3568_CLKSEL_CON(73), 0, 2, MFLAGS, + RK3568_CLKGATE_CON(33), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, 0, + RK3568_CLKSEL_CON(73), 4, 2, MFLAGS, + RK3568_CLKGATE_CON(33), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 0, + RK3568_CLKSEL_CON(73), 8, 2, MFLAGS, + RK3568_CLKGATE_CON(33), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 0, + RK3568_CLKSEL_CON(73), 12, 2, MFLAGS, + RK3568_CLKGATE_CON(33), 3, GFLAGS), + GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0, + RK3568_CLKGATE_CON(33), 8, GFLAGS), + COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 0, + RK3568_CLKSEL_CON(73), 15, 1, MFLAGS, + RK3568_CLKGATE_CON(33), 9, GFLAGS), + GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0, + RK3568_CLKGATE_CON(33), 13, GFLAGS), + GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0, + RK3568_CLKGATE_CON(33), 14, GFLAGS), + GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0, + RK3568_CLKGATE_CON(33), 15, GFLAGS), + GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0, + RK3568_CLKGATE_CON(34), 4, GFLAGS), + GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0, + RK3568_CLKGATE_CON(34), 5, GFLAGS), + GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0, + RK3568_CLKGATE_CON(34), 6, GFLAGS), + GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0, + RK3568_CLKGATE_CON(34), 11, GFLAGS), + GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0, + RK3568_CLKGATE_CON(34), 12, GFLAGS), + GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0, + RK3568_CLKGATE_CON(34), 13, GFLAGS), + GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0, + RK3568_CLKGATE_CON(34), 14, GFLAGS), +}; + +static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = { + /* PD_PMU */ + FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2), + FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2), + FACTOR(0, "hpll_ph0", "hpll", 0, 1, 2), + + MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0, + RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS), + COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", 0, + RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS, + RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS), + GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0, + RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS), + GATE(CLK_PMU, "clk_pmu", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0, + RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0, + RK3568_PMU_CLKSEL_CON(3), 0, 7, DFLAGS, + RK3568_PMU_CLKGATE_CON(1), 1, GFLAGS), + GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0, + RK3568_PMU_CLKGATE_CON(1), 2, GFLAGS), + + COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED, + RK3568_PMU_CLKSEL_CON(1), 0, + RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS, + &rk3568_rtc32k_pmu_fracmux), + + COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED, + RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS, + RK3568_PMU_CLKGATE_CON(0), 0, GFLAGS), + + COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0, + RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS, + RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT, + RK3568_PMU_CLKSEL_CON(5), 0, + RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS, + &rk3568_uart0_fracmux), + GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0, + RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS), + + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0, + RK3568_PMU_CLKGATE_CON(1), 9, GFLAGS), + COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", xin24m_32k_p, 0, + RK3568_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, + RK3568_PMU_CLKGATE_CON(1), 10, GFLAGS), + GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0, + RK3568_PMU_CLKGATE_CON(1), 6, GFLAGS), + COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0, + RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3568_PMU_CLKGATE_CON(1), 7, GFLAGS), + GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(1), 8, GFLAGS), + GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0, + RK3568_PMU_CLKGATE_CON(1), 11, GFLAGS), + GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(1), 12, GFLAGS), + GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(1), 13, GFLAGS), + COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 0, + RK3568_PMU_CLKSEL_CON(7), 0, 6, DFLAGS, + RK3568_PMU_CLKGATE_CON(2), 0, GFLAGS), + GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 1, GFLAGS), + MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0, + RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS), + GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 2, GFLAGS), + MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0, + RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS), + GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 3, GFLAGS), + MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0, + RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS), + GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 4, GFLAGS), + MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0, + RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS), + COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "clk_pdpmu", 0, + RK3568_PMU_CLKSEL_CON(8), 8, 6, DFLAGS, + RK3568_PMU_CLKGATE_CON(2), 5, GFLAGS), + GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS), + MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT, + RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS), + COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0, + RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS, + RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS), + GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS), + MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT, + RK3568_PMU_CLKSEL_CON(9), 3, 1, MFLAGS), + COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0, + RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS, + RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS), + GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS), + MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT, + RK3568_PMU_CLKSEL_CON(9), 7, 1, MFLAGS), + COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0, + RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS, + RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS), + GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS), + MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT, + RK3568_PMU_CLKSEL_CON(9), 11, 1, MFLAGS), + GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0, + RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS), + GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0, + RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS), + GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS), + MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, + RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS), +}; + +static const char *const rk3568_cru_critical_clocks[] __initconst = { + "armclk", + "pclk_core_pre", + "aclk_bus", + "pclk_bus", + "aclk_top_high", + "aclk_top_low", + "hclk_top", + "pclk_top", + "aclk_perimid", + "hclk_perimid", + "aclk_secure_flash", + "hclk_secure_flash", + "aclk_core_niu2bus", + "npll", + "clk_optc_arb", + "hclk_php", + "pclk_php", + "hclk_usb", +}; + +static const char *const rk3568_pmucru_critical_clocks[] __initconst = { + "pclk_pdpmu", + "pclk_pmu", + "clk_pmu", +}; + +static void __init rk3568_pmu_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + void __iomem *reg_base; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru pmu region\n", __func__); + return; + } + + ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip pmu clk init failed\n", __func__); + return; + } + + rockchip_clk_register_plls(ctx, rk3568_pmu_pll_clks, + ARRAY_SIZE(rk3568_pmu_pll_clks), + RK3568_GRF_SOC_STATUS0); + + rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches, + ARRAY_SIZE(rk3568_clk_pmu_branches)); + + rockchip_clk_protect_critical(rk3568_pmucru_critical_clocks, + ARRAY_SIZE(rk3568_pmucru_critical_clocks)); + + rockchip_clk_of_add_provider(np, ctx); +} + +static void __init rk3568_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + void __iomem *reg_base; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + return; + } + + rockchip_clk_register_plls(ctx, rk3568_pll_clks, + ARRAY_SIZE(rk3568_pll_clks), + RK3568_GRF_SOC_STATUS0); + + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", + mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + &rk3568_cpuclk_data, rk3568_cpuclk_rates, + ARRAY_SIZE(rk3568_cpuclk_rates)); + + rockchip_clk_register_branches(ctx, rk3568_clk_branches, + ARRAY_SIZE(rk3568_clk_branches)); + + rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST); + + rockchip_clk_protect_critical(rk3568_cru_critical_clocks, + ARRAY_SIZE(rk3568_cru_critical_clocks)); + + rockchip_clk_of_add_provider(np, ctx); +} + +struct clk_rk3568_inits { + void (*inits)(struct device_node *np); +}; + +static const struct clk_rk3568_inits clk_rk3568_pmucru_init = { + .inits = rk3568_pmu_clk_init, +}; + +static const struct clk_rk3568_inits clk_3568_cru_init = { + .inits = rk3568_clk_init, +}; + +static const struct of_device_id clk_rk3568_match_table[] = { + { + .compatible = "rockchip,rk3568-cru", + .data = &clk_3568_cru_init, + }, { + .compatible = "rockchip,rk3568-pmucru", + .data = &clk_rk3568_pmucru_init, + }, + { } +}; + +static int __init clk_rk3568_probe(struct device_d *dev) +{ + struct device_node *np = dev->device_node; + const struct clk_rk3568_inits *init_data; + + init_data = of_device_get_match_data(dev); + if (init_data->inits) + init_data->inits(np); + + return 0; +} + +static struct driver_d clk_rk3568_driver = { + .probe = clk_rk3568_probe, + .name = "clk-rk3568", + .of_compatible = DRV_OF_COMPAT(clk_rk3568_match_table), +}; + +core_platform_driver(clk_rk3568_driver); diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 833e9bed0e..6e7bba414f 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -3,6 +3,9 @@ * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> * + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> + * * based on * * samsung/clk.c @@ -14,10 +17,14 @@ #include <common.h> #include <malloc.h> #include <linux/clk.h> +#include <regmap.h> +#include <mfd/syscon.h> +#include <linux/spinlock.h> +#include <linux/rational.h> +#include <restart.h> #include "clk.h" -#include <init.h> -/** +/* * Register a clock branch. * Most clock branches have a form like * @@ -28,134 +35,366 @@ * sometimes without one of those components. */ static struct clk *rockchip_clk_register_branch(const char *name, - const char **parent_names, u8 num_parents, void __iomem *base, + const char *const *parent_names, u8 num_parents, + void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, - u8 div_shift, u8 div_width, u8 div_flags, + int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, - u8 gate_shift, u8 gate_flags, unsigned long flags - ) + u8 gate_shift, u8 gate_flags, unsigned long flags, + spinlock_t *lock) { struct clk *clk; - struct clk *mux = NULL; - struct clk *gate = NULL; - struct clk *div = NULL; + struct clk_mux *mux = NULL; + struct clk_gate *gate = NULL; + struct clk_divider *div = NULL; + int ret; if (num_parents > 1) { - mux = clk_mux_alloc(name, 0, base + muxdiv_offset, mux_shift, - mux_width, parent_names, num_parents, mux_flags); + mux = kzalloc(sizeof(*mux), GFP_KERNEL); if (!mux) return ERR_PTR(-ENOMEM); + + mux->reg = base + muxdiv_offset; + mux->shift = mux_shift; + mux->width = mux_width; + mux->flags = mux_flags; + mux->lock = lock; + mux->hw.clk.ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops + : &clk_mux_ops; } if (gate_offset >= 0) { - gate = clk_gate_alloc(name, *parent_names, base + gate_offset, - gate_shift, flags, gate_flags); - if (!gate) - return ERR_PTR(-ENOMEM); + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) { + ret = -ENOMEM; + goto err_gate; + } + + gate->flags = gate_flags; + gate->reg = base + gate_offset; + gate->shift = gate_shift; + gate->lock = lock; + gate->hw.clk.ops = &clk_gate_ops; } if (div_width > 0) { - div = clk_divider_alloc(name, *parent_names, 0, - base + muxdiv_offset, div_shift, div_width, div_flags); - if (!div) - return ERR_PTR(-ENOMEM); + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) { + ret = -ENOMEM; + goto err_div; + } + + div->flags = div_flags; + if (div_offset) + div->reg = base + div_offset; + else + div->reg = base + muxdiv_offset; + div->shift = div_shift; + div->width = div_width; + div->lock = lock; + div->table = div_table; + div->hw.clk.ops = (div_flags & CLK_DIVIDER_READ_ONLY) + ? &clk_divider_ro_ops + : &clk_divider_ops; } clk = clk_register_composite(name, parent_names, num_parents, - mux, - div, - gate, - flags); + mux ? &mux->hw.clk : NULL, + div ? &div->hw.clk : NULL, + gate ? &gate->hw.clk : NULL, + flags); + if (IS_ERR(clk)) { + kfree(div); + kfree(gate); + return ERR_CAST(clk); + } return clk; +err_div: + kfree(gate); +err_gate: + kfree(mux); + return ERR_PTR(ret); } -static struct clk *rockchip_clk_register_frac_branch(const char *name, - const char **parent_names, u8 num_parents, void __iomem *base, - int muxdiv_offset, u8 div_flags, +struct rockchip_clk_frac { + struct clk_fractional_divider div; + struct clk_gate gate; + + struct clk_mux mux; + const struct clk_ops *mux_ops; + int mux_frac_idx; + + bool rate_change_remuxed; + int rate_change_idx; +}; + +/* + * fractional divider must set that denominator is 20 times larger than + * numerator to generate precise clock frequency. + */ +static void rockchip_fractional_approximation(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate, + unsigned long *m, unsigned long *n) +{ + struct clk_fractional_divider *fd = to_clk_fd(hw); + unsigned long p_rate, p_parent_rate; + struct clk_hw *p_parent; + unsigned long scale; + + p_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); + if ((rate * 20 > p_rate) && (p_rate % rate != 0)) { + p_parent = clk_hw_get_parent(clk_hw_get_parent(hw)); + p_parent_rate = clk_hw_get_rate(p_parent); + *parent_rate = p_parent_rate; + } + + /* + * Get rate closer to *parent_rate to guarantee there is no overflow + * for m and n. In the result it will be the nearest rate left shifted + * by (scale - fd->nwidth) bits. + */ + scale = fls_long(*parent_rate / rate - 1); + if (scale > fd->nwidth) + rate <<= scale - fd->nwidth; + + rational_best_approximation(rate, *parent_rate, + GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), + m, n); +} + +static struct clk *rockchip_clk_register_frac_branch( + struct rockchip_clk_provider *ctx, const char *name, + const char *const *parent_names, u8 num_parents, + void __iomem *base, int muxdiv_offset, u8 div_flags, int gate_offset, u8 gate_shift, u8 gate_flags, - unsigned long flags) + unsigned long flags, struct rockchip_clk_branch *child, + spinlock_t *lock) { struct clk *clk; - struct clk *gate = NULL; - struct clk *div = NULL; - - if (gate_offset >= 0) { - gate = clk_gate_alloc(name, *parent_names, base + gate_offset, - gate_shift, flags, gate_flags); - if (!gate) - return ERR_PTR(-ENOMEM); - } + struct rockchip_clk_frac *frac; + struct clk_gate *gate = NULL; + struct clk_fractional_divider *div = NULL; if (muxdiv_offset < 0) return ERR_PTR(-EINVAL); - div = clk_fractional_divider_alloc(name, *parent_names, flags, - base + muxdiv_offset, 16, 16, 0, 16, div_flags); - if (!div) + if (child && child->branch_type != branch_mux) { + pr_err("%s: fractional child clock for %s can only be a mux\n", + __func__, name); + return ERR_PTR(-EINVAL); + } + + frac = kzalloc(sizeof(*frac), GFP_KERNEL); + if (!frac) return ERR_PTR(-ENOMEM); + if (gate_offset >= 0) { + gate = &frac->gate; + gate->flags = gate_flags; + gate->reg = base + gate_offset; + gate->shift = gate_shift; + gate->lock = lock; + gate->hw.clk.ops = &clk_gate_ops; + } + + div = &frac->div; + div->flags = div_flags; + div->reg = base + muxdiv_offset; + div->mshift = 16; + div->mwidth = 16; + div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift; + div->nshift = 0; + div->nwidth = 16; + div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift; + div->lock = lock; + div->approximation = rockchip_fractional_approximation; + div->hw.clk.ops = &clk_fractional_divider_ops; + clk = clk_register_composite(name, parent_names, num_parents, - NULL, - div, - gate, - flags); + NULL, + &div->hw.clk, + gate ? &gate->hw.clk : NULL, + flags | CLK_SET_RATE_UNGATE); + if (IS_ERR(clk)) { + kfree(frac); + return ERR_CAST(clk); + } + + if (child) { + struct clk_mux *frac_mux = &frac->mux; + struct clk_init_data init; + struct clk *mux_clk; + + frac->mux_frac_idx = match_string(child->parent_names, + child->num_parents, name); + frac->mux_ops = &clk_mux_ops; + + frac_mux->reg = base + child->muxdiv_offset; + frac_mux->shift = child->mux_shift; + frac_mux->width = child->mux_width; + frac_mux->flags = child->mux_flags; + frac_mux->lock = lock; + frac_mux->hw.init = &init; + + init.name = child->name; + init.flags = child->flags | CLK_SET_RATE_PARENT; + init.ops = frac->mux_ops; + init.parent_names = child->parent_names; + init.num_parents = child->num_parents; + + mux_clk = clk_register(NULL, &frac_mux->hw); + if (IS_ERR(mux_clk)) { + kfree(frac); + return mux_clk; + } + + rockchip_clk_add_lookup(ctx, mux_clk, child->id); + + /* notifier on the fraction divider to catch rate changes */ + if (frac->mux_frac_idx >= 0) { + pr_debug("%s: found fractional parent in mux at pos %d\n", + __func__, frac->mux_frac_idx); + } else { + pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n", + __func__, name, child->name); + } + } return clk; } -static struct clk **clk_table; -static void __iomem *reg_base; -static struct clk_onecell_data clk_data; -static struct device_node *cru_node; +static struct clk *rockchip_clk_register_factor_branch(const char *name, + const char *const *parent_names, u8 num_parents, + void __iomem *base, unsigned int mult, unsigned int div, + int gate_offset, u8 gate_shift, u8 gate_flags, + unsigned long flags, spinlock_t *lock) +{ + struct clk *clk; + struct clk_gate *gate = NULL; + struct clk_fixed_factor *fix = NULL; + + /* without gate, register a simple factor clock */ + if (gate_offset == 0) { + return clk_register_fixed_factor(NULL, name, + parent_names[0], flags, mult, + div); + } + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + gate->flags = gate_flags; + gate->reg = base + gate_offset; + gate->shift = gate_shift; + gate->lock = lock; + gate->hw.clk.ops = &clk_gate_ops; + + fix = kzalloc(sizeof(*fix), GFP_KERNEL); + if (!fix) { + kfree(gate); + return ERR_PTR(-ENOMEM); + } + + fix->mult = mult; + fix->div = div; + fix->hw.clk.ops = &clk_fixed_factor_ops; -void __init rockchip_clk_init(struct device_node *np, void __iomem *base, - unsigned long nr_clks) + clk = clk_register_composite(name, parent_names, num_parents, + NULL, + &fix->hw.clk, + &gate->hw.clk, flags); + if (IS_ERR(clk)) { + kfree(fix); + kfree(gate); + return ERR_CAST(clk); + } + + return clk; +} + +struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, + void __iomem *base, + unsigned long nr_clks) { - reg_base = base; - cru_node = np; + struct rockchip_clk_provider *ctx; + struct clk **clk_table; + int i; + + ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); - clk_table = calloc(nr_clks, sizeof(struct clk *)); + clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); if (!clk_table) - pr_err("%s: could not allocate clock lookup table\n", __func__); + goto err_free; + + for (i = 0; i < nr_clks; ++i) + clk_table[i] = ERR_PTR(-ENOENT); + + ctx->reg_base = base; + ctx->clk_data.clks = clk_table; + ctx->clk_data.clk_num = nr_clks; + ctx->cru_node = np; + spin_lock_init(&ctx->lock); - clk_data.clks = clk_table; - clk_data.clk_num = nr_clks; - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node, + "rockchip,grf"); + + return ctx; + +err_free: + kfree(ctx); + return ERR_PTR(-ENOMEM); +} +EXPORT_SYMBOL_GPL(rockchip_clk_init); + +void rockchip_clk_of_add_provider(struct device_node *np, + struct rockchip_clk_provider *ctx) +{ + if (of_clk_add_provider(np, of_clk_src_onecell_get, + &ctx->clk_data)) + pr_err("%s: could not register clk provider\n", __func__); } +EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider); -void rockchip_clk_add_lookup(struct clk *clk, unsigned int id) +void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, + struct clk *clk, unsigned int id) { - if (clk_table && id) - clk_table[id] = clk; + if (ctx->clk_data.clks && id) + ctx->clk_data.clks[id] = clk; } +EXPORT_SYMBOL_GPL(rockchip_clk_add_lookup); -void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list, +void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, + struct rockchip_pll_clock *list, unsigned int nr_pll, int grf_lock_offset) { struct clk *clk; int idx; for (idx = 0; idx < nr_pll; idx++, list++) { - clk = rockchip_clk_register_pll(list->type, list->name, + clk = rockchip_clk_register_pll(ctx, list->type, list->name, list->parent_names, list->num_parents, - reg_base, list->con_offset, grf_lock_offset, + list->con_offset, grf_lock_offset, list->lock_shift, list->mode_offset, list->mode_shift, list->rate_table, - list->pll_flags); + list->flags, list->pll_flags); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, list->name); continue; } - rockchip_clk_add_lookup(clk, list->id); + rockchip_clk_add_lookup(ctx, clk, list->id); } } +EXPORT_SYMBOL_GPL(rockchip_clk_register_plls); -void __init rockchip_clk_register_branches( - struct rockchip_clk_branch *list, - unsigned int nr_clk) +void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *list, + unsigned int nr_clk) { struct clk *clk = NULL; unsigned int idx; @@ -167,50 +406,89 @@ void __init rockchip_clk_register_branches( /* catch simple muxes */ switch (list->branch_type) { case branch_mux: - clk = clk_mux(list->name, flags, - reg_base + list->muxdiv_offset, list->mux_shift, - list->mux_width, list->parent_names, - list->num_parents, list->mux_flags); + clk = clk_register_mux(NULL, list->name, + list->parent_names, list->num_parents, + flags, ctx->reg_base + list->muxdiv_offset, + list->mux_shift, list->mux_width, + list->mux_flags, &ctx->lock); + break; + case branch_muxgrf: + clk = rockchip_clk_register_muxgrf(list->name, + list->parent_names, list->num_parents, + flags, ctx->grf, list->muxdiv_offset, + list->mux_shift, list->mux_width, + list->mux_flags); break; case branch_divider: if (list->div_table) - clk = clk_divider_table(list->name, - list->parent_names[0], flags, - reg_base + list->muxdiv_offset, - list->div_shift, list->div_width, - list->div_table, list->div_flags); + clk = clk_register_divider_table(NULL, + list->name, list->parent_names[0], + flags, + ctx->reg_base + list->muxdiv_offset, + list->div_shift, list->div_width, + list->div_flags, list->div_table, + &ctx->lock); else - clk = clk_divider(list->name, - list->parent_names[0], flags, - reg_base + list->muxdiv_offset, - list->div_shift, list->div_width, - list->div_flags); + clk = clk_register_divider(NULL, list->name, + list->parent_names[0], flags, + ctx->reg_base + list->muxdiv_offset, + list->div_shift, list->div_width, + list->div_flags, &ctx->lock); break; case branch_fraction_divider: - clk = rockchip_clk_register_frac_branch(list->name, + clk = rockchip_clk_register_frac_branch(ctx, list->name, list->parent_names, list->num_parents, - reg_base, list->muxdiv_offset, list->div_flags, + ctx->reg_base, list->muxdiv_offset, + list->div_flags, list->gate_offset, list->gate_shift, - list->gate_flags, flags); + list->gate_flags, flags, list->child, + &ctx->lock); + break; + case branch_half_divider: break; case branch_gate: flags |= CLK_SET_RATE_PARENT; - clk = clk_gate(list->name, list->parent_names[0], - reg_base + list->gate_offset, list->gate_shift, - flags, list->gate_flags); + clk = clk_register_gate(NULL, list->name, + list->parent_names[0], flags, + ctx->reg_base + list->gate_offset, + list->gate_shift, list->gate_flags, &ctx->lock); break; case branch_composite: clk = rockchip_clk_register_branch(list->name, list->parent_names, list->num_parents, - reg_base, list->muxdiv_offset, list->mux_shift, + ctx->reg_base, list->muxdiv_offset, + list->mux_shift, list->mux_width, list->mux_flags, - list->div_shift, list->div_width, + list->div_offset, list->div_shift, list->div_width, list->div_flags, list->div_table, list->gate_offset, list->gate_shift, - list->gate_flags, flags); + list->gate_flags, flags, &ctx->lock); break; case branch_mmc: + clk = rockchip_clk_register_mmc( + list->name, + list->parent_names, list->num_parents, + ctx->reg_base + list->muxdiv_offset, + list->div_shift + ); + break; + case branch_inverter: + clk = rockchip_clk_register_inverter( + list->name, list->parent_names, + list->num_parents, + ctx->reg_base + list->muxdiv_offset, + list->div_shift, list->div_flags, &ctx->lock); + break; + case branch_factor: + clk = rockchip_clk_register_factor_branch( + list->name, list->parent_names, + list->num_parents, ctx->reg_base, + list->div_shift, list->div_width, + list->gate_offset, list->gate_shift, + list->gate_flags, flags, &ctx->lock); + break; + case branch_ddrclk: break; } @@ -227,32 +505,36 @@ void __init rockchip_clk_register_branches( continue; } - rockchip_clk_add_lookup(clk, list->id); + rockchip_clk_add_lookup(ctx, clk, list->id); } } - -void __init rockchip_clk_register_armclk(unsigned int lookup_id, - const char *name, const char **parent_names, - u8 num_parents, - const struct rockchip_cpuclk_reg_data *reg_data, - const struct rockchip_cpuclk_rate_table *rates, - int nrates) +EXPORT_SYMBOL_GPL(rockchip_clk_register_branches); + +void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, + unsigned int lookup_id, + const char *name, const char *const *parent_names, + u8 num_parents, + const struct rockchip_cpuclk_reg_data *reg_data, + const struct rockchip_cpuclk_rate_table *rates, + int nrates) { struct clk *clk; clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents, - reg_data, rates, nrates, reg_base - ); + reg_data, rates, nrates, + ctx->reg_base, &ctx->lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s: %ld\n", __func__, name, PTR_ERR(clk)); return; } - rockchip_clk_add_lookup(clk, lookup_id); + rockchip_clk_add_lookup(ctx, clk, lookup_id); } +EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk); -void __init rockchip_clk_protect_critical(const char *clocks[], int nclocks) +void rockchip_clk_protect_critical(const char *const clocks[], + int nclocks) { int i; @@ -260,7 +542,34 @@ void __init rockchip_clk_protect_critical(const char *clocks[], int nclocks) for (i = 0; i < nclocks; i++) { struct clk *clk = __clk_lookup(clocks[i]); - if (clk) - clk_enable(clk); + clk_enable(clk); } } +EXPORT_SYMBOL_GPL(rockchip_clk_protect_critical); + +static void rockchip_restart(struct restart_handler *this) +{ + struct rockchip_clk_provider *ctx = + container_of(this, struct rockchip_clk_provider, restart_handler); + + writel(0xfdb9, ctx->reg_base + ctx->reg_restart); + mdelay(1000); +} + +void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, + unsigned int reg) +{ + int ret; + + ctx->restart_handler.name = "rockchip-pmu", + ctx->restart_handler.restart = rockchip_restart, + ctx->restart_handler.priority = RESTART_DEFAULT_PRIORITY, + + ctx->reg_restart = reg; + + ret = restart_handler_register(&ctx->restart_handler); + if (ret) + pr_err("%s: cannot register restart handler, %d\n", + __func__, ret); +} +EXPORT_SYMBOL_GPL(rockchip_register_restart_notifier); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 006225b7e8..a3db88dfc8 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -3,6 +3,9 @@ * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> * + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> + * * based on * * samsung/clk.h @@ -16,31 +19,97 @@ #include <io.h> #include <linux/clk.h> - -/* To keep changes from kernel smaller */ -#define CLK_GATE_SET_TO_DISABLE CLK_GATE_INVERTED -#define CLK_GET_RATE_NOCACHE 0 +#include <restart.h> #define HIWORD_UPDATE(val, mask, shift) \ ((val) << (shift) | (mask) << ((shift) + 16)) -/* register positions shared by RK2928, RK3066 and RK3188 */ -#define RK2928_PLL_CON(x) (x * 0x4) +/* register positions shared by PX30, RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */ +#define BOOST_PLL_H_CON(x) ((x) * 0x4) +#define BOOST_CLK_CON 0x0008 +#define BOOST_BOOST_CON 0x000c +#define BOOST_SWITCH_CNT 0x0010 +#define BOOST_HIGH_PERF_CNT0 0x0014 +#define BOOST_HIGH_PERF_CNT1 0x0018 +#define BOOST_STATIS_THRESHOLD 0x001c +#define BOOST_SHORT_SWITCH_CNT 0x0020 +#define BOOST_SWITCH_THRESHOLD 0x0024 +#define BOOST_FSM_STATUS 0x0028 +#define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c) +#define BOOST_RECOVERY_MASK 0x1 +#define BOOST_RECOVERY_SHIFT 1 +#define BOOST_SW_CTRL_MASK 0x1 +#define BOOST_SW_CTRL_SHIFT 2 +#define BOOST_LOW_FREQ_EN_MASK 0x1 +#define BOOST_LOW_FREQ_EN_SHIFT 3 +#define BOOST_BUSY_STATE BIT(8) + +#define PX30_PLL_CON(x) ((x) * 0x4) +#define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200) +#define PX30_GLB_SRST_FST 0xb8 +#define PX30_GLB_SRST_SND 0xbc +#define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300) +#define PX30_MODE_CON 0xa0 +#define PX30_MISC_CON 0xa4 +#define PX30_SDMMC_CON0 0x380 +#define PX30_SDMMC_CON1 0x384 +#define PX30_SDIO_CON0 0x388 +#define PX30_SDIO_CON1 0x38c +#define PX30_EMMC_CON0 0x390 +#define PX30_EMMC_CON1 0x394 + +#define PX30_PMU_PLL_CON(x) ((x) * 0x4) +#define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40) +#define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80) +#define PX30_PMU_MODE 0x0020 + +#define RV1108_PLL_CON(x) ((x) * 0x4) +#define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60) +#define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120) +#define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180) +#define RV1108_GLB_SRST_FST 0x1c0 +#define RV1108_GLB_SRST_SND 0x1c4 +#define RV1108_MISC_CON 0x1cc +#define RV1108_SDMMC_CON0 0x1d8 +#define RV1108_SDMMC_CON1 0x1dc +#define RV1108_SDIO_CON0 0x1e0 +#define RV1108_SDIO_CON1 0x1e4 +#define RV1108_EMMC_CON0 0x1e8 +#define RV1108_EMMC_CON1 0x1ec + +#define RK2928_PLL_CON(x) ((x) * 0x4) #define RK2928_MODE_CON 0x40 -#define RK2928_CLKSEL_CON(x) (x * 0x4 + 0x44) -#define RK2928_CLKGATE_CON(x) (x * 0x4 + 0xd0) +#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) +#define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0) #define RK2928_GLB_SRST_FST 0x100 #define RK2928_GLB_SRST_SND 0x104 -#define RK2928_SOFTRST_CON(x) (x * 0x4 + 0x110) +#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110) #define RK2928_MISC_CON 0x134 +#define RK3036_SDMMC_CON0 0x144 +#define RK3036_SDMMC_CON1 0x148 +#define RK3036_SDIO_CON0 0x14c +#define RK3036_SDIO_CON1 0x150 +#define RK3036_EMMC_CON0 0x154 +#define RK3036_EMMC_CON1 0x158 + +#define RK3228_GLB_SRST_FST 0x1f0 +#define RK3228_GLB_SRST_SND 0x1f4 +#define RK3228_SDMMC_CON0 0x1c0 +#define RK3228_SDMMC_CON1 0x1c4 +#define RK3228_SDIO_CON0 0x1c8 +#define RK3228_SDIO_CON1 0x1cc +#define RK3228_EMMC_CON0 0x1d8 +#define RK3228_EMMC_CON1 0x1dc + #define RK3288_PLL_CON(x) RK2928_PLL_CON(x) #define RK3288_MODE_CON 0x50 -#define RK3288_CLKSEL_CON(x) (x * 0x4 + 0x60) -#define RK3288_CLKGATE_CON(x) (x * 0x4 + 0x160) +#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60) +#define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160) #define RK3288_GLB_SRST_FST 0x1b0 #define RK3288_GLB_SRST_SND 0x1b4 -#define RK3288_SOFTRST_CON(x) (x * 0x4 + 0x1b8) +#define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8) #define RK3288_MISC_CON 0x1e8 #define RK3288_SDMMC_CON0 0x200 #define RK3288_SDMMC_CON1 0x204 @@ -51,41 +120,177 @@ #define RK3288_EMMC_CON0 0x218 #define RK3288_EMMC_CON1 0x21c +#define RK3308_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300) +#define RK3308_GLB_SRST_FST 0xb8 +#define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400) +#define RK3308_MODE_CON 0xa0 +#define RK3308_SDMMC_CON0 0x480 +#define RK3308_SDMMC_CON1 0x484 +#define RK3308_SDIO_CON0 0x488 +#define RK3308_SDIO_CON1 0x48c +#define RK3308_EMMC_CON0 0x490 +#define RK3308_EMMC_CON1 0x494 + +#define RK3328_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200) +#define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3328_GLB_SRST_FST 0x9c +#define RK3328_GLB_SRST_SND 0x98 +#define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300) +#define RK3328_MODE_CON 0x80 +#define RK3328_MISC_CON 0x84 +#define RK3328_SDMMC_CON0 0x380 +#define RK3328_SDMMC_CON1 0x384 +#define RK3328_SDIO_CON0 0x388 +#define RK3328_SDIO_CON1 0x38c +#define RK3328_EMMC_CON0 0x390 +#define RK3328_EMMC_CON1 0x394 +#define RK3328_SDMMC_EXT_CON0 0x398 +#define RK3328_SDMMC_EXT_CON1 0x39C + +#define RK3368_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200) +#define RK3368_GLB_SRST_FST 0x280 +#define RK3368_GLB_SRST_SND 0x284 +#define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300) +#define RK3368_MISC_CON 0x380 +#define RK3368_SDMMC_CON0 0x400 +#define RK3368_SDMMC_CON1 0x404 +#define RK3368_SDIO0_CON0 0x408 +#define RK3368_SDIO0_CON1 0x40c +#define RK3368_SDIO1_CON0 0x410 +#define RK3368_SDIO1_CON1 0x414 +#define RK3368_EMMC_CON0 0x418 +#define RK3368_EMMC_CON1 0x41c + +#define RK3399_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300) +#define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400) +#define RK3399_GLB_SRST_FST 0x500 +#define RK3399_GLB_SRST_SND 0x504 +#define RK3399_GLB_CNT_TH 0x508 +#define RK3399_MISC_CON 0x50c +#define RK3399_RST_CON 0x510 +#define RK3399_RST_ST 0x514 +#define RK3399_SDMMC_CON0 0x580 +#define RK3399_SDMMC_CON1 0x584 +#define RK3399_SDIO_CON0 0x588 +#define RK3399_SDIO_CON1 0x58c + +#define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80) +#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) +#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) + +#define RK3568_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3568_MODE_CON0 0xc0 +#define RK3568_MISC_CON0 0xc4 +#define RK3568_MISC_CON1 0xc8 +#define RK3568_MISC_CON2 0xcc +#define RK3568_GLB_CNT_TH 0xd0 +#define RK3568_GLB_SRST_FST 0xd4 +#define RK3568_GLB_SRST_SND 0xd8 +#define RK3568_GLB_RST_CON 0xdc +#define RK3568_GLB_RST_ST 0xe0 +#define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300) +#define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400) +#define RK3568_SDMMC0_CON0 0x580 +#define RK3568_SDMMC0_CON1 0x584 +#define RK3568_SDMMC1_CON0 0x588 +#define RK3568_SDMMC1_CON1 0x58c +#define RK3568_SDMMC2_CON0 0x590 +#define RK3568_SDMMC2_CON1 0x594 +#define RK3568_EMMC_CON0 0x598 +#define RK3568_EMMC_CON1 0x59c + +#define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3568_PMU_MODE_CON0 0x80 +#define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) +#define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) + enum rockchip_pll_type { + pll_rk3036, pll_rk3066, + pll_rk3328, + pll_rk3399, }; +#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ + _postdiv2, _dsmpd, _frac) \ +{ \ + .rate = _rate##U, \ + .fbdiv = _fbdiv, \ + .postdiv1 = _postdiv1, \ + .refdiv = _refdiv, \ + .postdiv2 = _postdiv2, \ + .dsmpd = _dsmpd, \ + .frac = _frac, \ +} + #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \ { \ .rate = _rate##U, \ .nr = _nr, \ .nf = _nf, \ .no = _no, \ - .bwadj = (_nf >> 1), \ + .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \ } -#define RK3066_PLL_RATE_BWADJ(_rate, _nr, _nf, _no, _bw) \ +#define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \ { \ .rate = _rate##U, \ .nr = _nr, \ .nf = _nf, \ .no = _no, \ - .bwadj = _bw, \ + .nb = _nb, \ } +/** + * struct rockchip_clk_provider - information about clock provider + * @reg_base: virtual address for the register base. + * @clk_data: holds clock related data like clk* and number of clocks. + * @cru_node: device-node of the clock-provider + * @grf: regmap of the general-register-files syscon + * @lock: maintains exclusion between callbacks for a given clock-provider. + */ +struct rockchip_clk_provider { + void __iomem *reg_base; + struct clk_onecell_data clk_data; + struct device_node *cru_node; + struct regmap *grf; + struct restart_handler restart_handler; + unsigned int reg_restart; + spinlock_t lock; +}; + struct rockchip_pll_rate_table { unsigned long rate; unsigned int nr; unsigned int nf; unsigned int no; - unsigned int bwadj; + unsigned int nb; + /* for RK3036/RK3399 */ + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; }; /** - * struct rockchip_pll_clock: information about pll clock + * struct rockchip_pll_clock - information about pll clock * @id: platform specific id of the clock. * @name: name of this pll clock. - * @parent_name: name of the parent clock. + * @parent_names: name of the parent clock. + * @num_parents: number of parents * @flags: optional flags for basic clock. * @con_offset: offset of the register for configuring the PLL. * @mode_offset: offset of the register for configuring the PLL-mode. @@ -102,7 +307,7 @@ struct rockchip_pll_rate_table { struct rockchip_pll_clock { unsigned int id; const char *name; - const char **parent_names; + const char *const *parent_names; u8 num_parents; unsigned long flags; int con_offset; @@ -133,71 +338,111 @@ struct rockchip_pll_clock { .rate_table = _rtable, \ } -struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, - const char *name, const char **parent_names, u8 num_parents, - void __iomem *base, int con_offset, int grf_lock_offset, - int lock_shift, int reg_mode, int mode_shift, +struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, + enum rockchip_pll_type pll_type, + const char *name, const char *const *parent_names, + u8 num_parents, int con_offset, int grf_lock_offset, + int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, - u8 clk_pll_flags); + unsigned long flags, u8 clk_pll_flags); struct rockchip_cpuclk_clksel { int reg; u32 val; }; -#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2 +#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 5 +#define ROCKCHIP_CPUCLK_MAX_CORES 4 struct rockchip_cpuclk_rate_table { unsigned long prate; struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; }; /** - * struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock - * @core_reg: register offset of the core settings register - * @div_core_shift: core divider offset used to divide the pll value - * @div_core_mask: core divider mask + * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock + * @core_reg[]: register offset of the cores setting register + * @div_core_shift[]: cores divider offset used to divide the pll value + * @div_core_mask[]: cores divider mask + * @num_cores: number of cpu cores + * @mux_core_main: mux value to select main parent of core * @mux_core_shift: offset of the core multiplexer + * @mux_core_mask: core multiplexer mask */ struct rockchip_cpuclk_reg_data { - int core_reg; - u8 div_core_shift; - u32 div_core_mask; - int mux_core_reg; - u8 mux_core_shift; + int core_reg[ROCKCHIP_CPUCLK_MAX_CORES]; + u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES]; + u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES]; + int num_cores; + u8 mux_core_alt; + u8 mux_core_main; + u8 mux_core_shift; + u32 mux_core_mask; }; struct clk *rockchip_clk_register_cpuclk(const char *name, - const char **parent_names, u8 num_parents, + const char *const *parent_names, u8 num_parents, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, - int nrates, void __iomem *reg_base); + int nrates, void __iomem *reg_base, spinlock_t *lock); struct clk *rockchip_clk_register_mmc(const char *name, - const char **parent_names, u8 num_parents, + const char *const *parent_names, u8 num_parents, void __iomem *reg, int shift); -#define PNAME(x) static const char *x[] __initconst +/* + * DDRCLK flags, including method of setting the rate + * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate. + */ +#define ROCKCHIP_DDRCLK_SIP BIT(0) + +struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, + const char *const *parent_names, + u8 num_parents, int mux_offset, + int mux_shift, int mux_width, + int div_shift, int div_width, + int ddr_flags, void __iomem *reg_base, + spinlock_t *lock); + +#define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0) + +struct clk *rockchip_clk_register_inverter(const char *name, + const char *const *parent_names, u8 num_parents, + void __iomem *reg, int shift, int flags, + spinlock_t *lock); + +struct clk *rockchip_clk_register_muxgrf(const char *name, + const char *const *parent_names, u8 num_parents, + int flags, struct regmap *grf, int reg, + int shift, int width, int mux_flags); + +#define PNAME(x) static const char *const x[] __initconst enum rockchip_clk_branch_type { branch_composite, branch_mux, + branch_muxgrf, branch_divider, branch_fraction_divider, branch_gate, branch_mmc, + branch_inverter, + branch_factor, + branch_ddrclk, + branch_half_divider, }; struct rockchip_clk_branch { unsigned int id; enum rockchip_clk_branch_type branch_type; const char *name; - const char **parent_names; + const char *const *parent_names; u8 num_parents; unsigned long flags; int muxdiv_offset; u8 mux_shift; u8 mux_width; u8 mux_flags; + int div_offset; u8 div_shift; u8 div_width; u8 div_flags; @@ -205,6 +450,7 @@ struct rockchip_clk_branch { int gate_offset; u8 gate_shift; u8 gate_flags; + struct rockchip_clk_branch *child; }; #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ @@ -228,6 +474,28 @@ struct rockchip_clk_branch { .gate_flags = gf, \ } +#define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \ + mf, do, ds, dw, df, go, gs, gf) \ + { \ + .id = _id, \ + .branch_type = branch_composite, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = mo, \ + .mux_shift = ms, \ + .mux_width = mw, \ + .mux_flags = mf, \ + .div_offset = do, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .gate_offset = go, \ + .gate_shift = gs, \ + .gate_flags = gf, \ + } + #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \ go, gs, gf) \ { \ @@ -302,6 +570,26 @@ struct rockchip_clk_branch { .gate_offset = -1, \ } +#define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \ + mw, mf, ds, dw, df, dt) \ + { \ + .id = _id, \ + .branch_type = branch_composite, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = mo, \ + .mux_shift = ms, \ + .mux_width = mw, \ + .mux_flags = mf, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .div_table = dt, \ + .gate_offset = -1, \ + } + #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\ { \ .id = _id, \ @@ -319,6 +607,58 @@ struct rockchip_clk_branch { .gate_flags = gf, \ } +#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \ + { \ + .id = _id, \ + .branch_type = branch_fraction_divider, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .flags = f, \ + .muxdiv_offset = mo, \ + .div_shift = 16, \ + .div_width = 16, \ + .div_flags = df, \ + .gate_offset = go, \ + .gate_shift = gs, \ + .gate_flags = gf, \ + .child = ch, \ + } + +#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \ + { \ + .id = _id, \ + .branch_type = branch_fraction_divider, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .flags = f, \ + .muxdiv_offset = mo, \ + .div_shift = 16, \ + .div_width = 16, \ + .div_flags = df, \ + .gate_offset = -1, \ + .child = ch, \ + } + +#define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \ + ds, dw, df) \ + { \ + .id = _id, \ + .branch_type = branch_ddrclk, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = mo, \ + .mux_shift = ms, \ + .mux_width = mw, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .gate_offset = -1, \ + } + #define MUX(_id, cname, pnames, f, o, s, w, mf) \ { \ .id = _id, \ @@ -334,6 +674,21 @@ struct rockchip_clk_branch { .gate_offset = -1, \ } +#define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \ + { \ + .id = _id, \ + .branch_type = branch_muxgrf, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = o, \ + .mux_shift = s, \ + .mux_width = w, \ + .mux_flags = mf, \ + .gate_offset = -1, \ + } + #define DIV(_id, cname, pname, f, o, s, w, df) \ { \ .id = _id, \ @@ -388,19 +743,83 @@ struct rockchip_clk_branch { .div_shift = shift, \ } -void rockchip_clk_init(struct device_node *np, void __iomem *base, - unsigned long nr_clks); -struct regmap *rockchip_clk_get_grf(void); -void rockchip_clk_add_lookup(struct clk *clk, unsigned int id); -void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list, +#define INVERTER(_id, cname, pname, io, is, if) \ + { \ + .id = _id, \ + .branch_type = branch_inverter, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .muxdiv_offset = io, \ + .div_shift = is, \ + .div_flags = if, \ + } + +#define FACTOR(_id, cname, pname, f, fm, fd) \ + { \ + .id = _id, \ + .branch_type = branch_factor, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .flags = f, \ + .div_shift = fm, \ + .div_width = fd, \ + } + +#define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \ + { \ + .id = _id, \ + .branch_type = branch_factor, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .flags = f, \ + .div_shift = fm, \ + .div_width = fd, \ + .gate_offset = go, \ + .gate_shift = gb, \ + .gate_flags = gf, \ + } + +/* SGRF clocks are only accessible from secure mode, so not controllable */ +#define SGRF_GATE(_id, cname, pname) \ + FACTOR(_id, cname, pname, 0, 1, 1) + +struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, + void __iomem *base, unsigned long nr_clks); +void rockchip_clk_of_add_provider(struct device_node *np, + struct rockchip_clk_provider *ctx); +void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, + struct clk *clk, unsigned int id); +void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *list, unsigned int nr_clk); -void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list, +void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, + struct rockchip_pll_clock *pll_list, unsigned int nr_pll, int grf_lock_offset); -void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name, - const char **parent_names, u8 num_parents, +void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, + unsigned int lookup_id, const char *name, + const char *const *parent_names, u8 num_parents, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, int nrates); -void rockchip_clk_protect_critical(const char *clocks[], int nclocks); +void rockchip_clk_protect_critical(const char *const clocks[], int nclocks); +void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, + unsigned int reg); + +#ifdef CONFIG_RESET_CONTROLLER +void rockchip_register_softrst(struct device_node *np, + unsigned int num_regs, + void __iomem *base, u8 flags); +#else +static inline void rockchip_register_softrst(struct device_node *np, + unsigned int num_regs, + void __iomem *base, u8 flags) +{ +} +#endif + +#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0) #endif diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c new file mode 100644 index 0000000000..e3f3937ca0 --- /dev/null +++ b/drivers/clk/rockchip/softrst.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + */ + +#include <common.h> +#include <io.h> +#include <linux/bitops.h> +#include <linux/reset-controller.h> +#include <linux/spinlock.h> +#include "clk.h" + +struct rockchip_softrst { + struct reset_controller_dev rcdev; + void __iomem *reg_base; + int num_regs; + int num_per_reg; + u8 flags; + spinlock_t lock; +}; + +static int rockchip_softrst_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rockchip_softrst *softrst = container_of(rcdev, + struct rockchip_softrst, + rcdev); + int bank = id / softrst->num_per_reg; + int offset = id % softrst->num_per_reg; + + if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) { + writel(BIT(offset) | (BIT(offset) << 16), + softrst->reg_base + (bank * 4)); + } else { + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&softrst->lock, flags); + + reg = readl(softrst->reg_base + (bank * 4)); + writel(reg | BIT(offset), softrst->reg_base + (bank * 4)); + + spin_unlock_irqrestore(&softrst->lock, flags); + } + + return 0; +} + +static int rockchip_softrst_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rockchip_softrst *softrst = container_of(rcdev, + struct rockchip_softrst, + rcdev); + int bank = id / softrst->num_per_reg; + int offset = id % softrst->num_per_reg; + + if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) { + writel((BIT(offset) << 16), softrst->reg_base + (bank * 4)); + } else { + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&softrst->lock, flags); + + reg = readl(softrst->reg_base + (bank * 4)); + writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4)); + + spin_unlock_irqrestore(&softrst->lock, flags); + } + + return 0; +} + +static const struct reset_control_ops rockchip_softrst_ops = { + .assert = rockchip_softrst_assert, + .deassert = rockchip_softrst_deassert, +}; + +void rockchip_register_softrst(struct device_node *np, + unsigned int num_regs, + void __iomem *base, u8 flags) +{ + struct rockchip_softrst *softrst; + int ret; + + softrst = kzalloc(sizeof(*softrst), GFP_KERNEL); + if (!softrst) + return; + + spin_lock_init(&softrst->lock); + + softrst->reg_base = base; + softrst->flags = flags; + softrst->num_regs = num_regs; + softrst->num_per_reg = (flags & ROCKCHIP_SOFTRST_HIWORD_MASK) ? 16 + : 32; + + softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg; + softrst->rcdev.ops = &rockchip_softrst_ops; + softrst->rcdev.of_node = np; + ret = reset_controller_register(&softrst->rcdev); + if (ret) { + pr_err("%s: could not register reset controller, %d\n", + __func__, ret); + kfree(softrst); + } +}; +EXPORT_SYMBOL_GPL(rockchip_register_softrst); diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index b452bbf8cc..1701a2c5a0 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -185,7 +185,7 @@ static void __prci_wrpll_write_cfg1(struct __prci_data *pd, * these functions. */ -unsigned long sifive_prci_wrpll_recalc_rate(struct clk *hw, +unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct __prci_clock *pc = clk_hw_to_prci_clock(hw); @@ -194,7 +194,7 @@ unsigned long sifive_prci_wrpll_recalc_rate(struct clk *hw, return wrpll_calc_output_rate(&pwd->c, parent_rate); } -long sifive_prci_wrpll_round_rate(struct clk *hw, +long sifive_prci_wrpll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { @@ -209,7 +209,7 @@ long sifive_prci_wrpll_round_rate(struct clk *hw, return wrpll_calc_output_rate(&c, *parent_rate); } -int sifive_prci_wrpll_set_rate(struct clk *hw, +int sifive_prci_wrpll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct __prci_clock *pc = clk_hw_to_prci_clock(hw); @@ -231,7 +231,7 @@ int sifive_prci_wrpll_set_rate(struct clk *hw, return 0; } -int sifive_clk_is_enabled(struct clk *hw) +int sifive_clk_is_enabled(struct clk_hw *hw) { struct __prci_clock *pc = clk_hw_to_prci_clock(hw); struct __prci_wrpll_data *pwd = pc->pwd; @@ -246,7 +246,7 @@ int sifive_clk_is_enabled(struct clk *hw) return 0; } -int sifive_prci_clock_enable(struct clk *hw) +int sifive_prci_clock_enable(struct clk_hw *hw) { struct __prci_clock *pc = clk_hw_to_prci_clock(hw); struct __prci_wrpll_data *pwd = pc->pwd; @@ -263,7 +263,7 @@ int sifive_prci_clock_enable(struct clk *hw) return 0; } -void sifive_prci_clock_disable(struct clk *hw) +void sifive_prci_clock_disable(struct clk_hw *hw) { struct __prci_clock *pc = clk_hw_to_prci_clock(hw); struct __prci_wrpll_data *pwd = pc->pwd; @@ -281,7 +281,7 @@ void sifive_prci_clock_disable(struct clk *hw) /* TLCLKSEL clock integration */ -unsigned long sifive_prci_tlclksel_recalc_rate(struct clk *hw, +unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct __prci_clock *pc = clk_hw_to_prci_clock(hw); @@ -298,7 +298,7 @@ unsigned long sifive_prci_tlclksel_recalc_rate(struct clk *hw, /* HFPCLK clock integration */ -unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk *hw, +unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct __prci_clock *pc = clk_hw_to_prci_clock(hw); @@ -473,6 +473,7 @@ void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd) static int __prci_register_clocks(struct device_d *dev, struct __prci_data *pd, const struct prci_clk_desc *desc) { + struct clk_init_data init = { }; struct __prci_clock *pic; int parent_count, i, r; @@ -485,33 +486,36 @@ static int __prci_register_clocks(struct device_d *dev, struct __prci_data *pd, /* Register PLLs */ for (i = 0; i < desc->num_clks; ++i) { + struct clk *clk; + pic = &(desc->clks[i]); - pic->hw.name = pic->name; - pic->hw.parent_names = &pic->parent_name; - pic->hw.num_parents = 1; - pic->hw.ops = pic->ops; + init.name = pic->name; + init.parent_names = &pic->parent_name; + init.num_parents = 1; + init.ops = pic->ops; + pic->hw.init = &init; pic->pd = pd; if (pic->pwd) __prci_wrpll_read_cfg0(pd, pic->pwd); - r = clk_register(&pic->hw); - if (r) { + clk = clk_register(dev, &pic->hw); + if (IS_ERR(clk)) { dev_warn(dev, "Failed to register clock %s: %d\n", - pic->hw.name, r); - return r; + clk_hw_get_name(&pic->hw), r); + return PTR_ERR(clk); } - r = clk_register_clkdev(&pic->hw, pic->name, dev_name(dev)); + r = clk_register_clkdev(clk, pic->name, dev_name(dev)); if (r) { dev_warn(dev, "Failed to register clkdev for %s: %d\n", - pic->hw.name, r); + clk_hw_get_name(&pic->hw), r); return r; } - pd->hw_clks.clks[i] = &pic->hw; + pd->hw_clks.clks[i] = clk; } pd->hw_clks.clk_num = i; diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index d851553818..e7a04ae790 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -254,7 +254,7 @@ struct __prci_clock { const char *name; const char *parent_name; const struct clk_ops *ops; - struct clk hw; + struct clk_hw hw; struct __prci_wrpll_data *pwd; struct __prci_data *pd; }; @@ -281,18 +281,18 @@ void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd); void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd); /* Linux clock framework integration */ -long sifive_prci_wrpll_round_rate(struct clk *hw, unsigned long rate, +long sifive_prci_wrpll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate); -int sifive_prci_wrpll_set_rate(struct clk *hw, unsigned long rate, +int sifive_prci_wrpll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); -int sifive_clk_is_enabled(struct clk *hw); -int sifive_prci_clock_enable(struct clk *hw); -void sifive_prci_clock_disable(struct clk *hw); -unsigned long sifive_prci_wrpll_recalc_rate(struct clk *hw, +int sifive_clk_is_enabled(struct clk_hw *hw); +int sifive_prci_clock_enable(struct clk_hw *hw); +void sifive_prci_clock_disable(struct clk_hw *hw); +unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate); -unsigned long sifive_prci_tlclksel_recalc_rate(struct clk *hw, +unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw, unsigned long parent_rate); -unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk *hw, +unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate); #endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index 401eb20d24..cbdec98fc6 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -14,15 +14,15 @@ #include "clk.h" -#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, clk) +#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw) /* SDMMC Group for System Manager defines */ #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x28 -static unsigned long socfpga_gate_clk_recalc_rate(struct clk *clk, +static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(clk); + struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hw); u32 div = 1, val; if (socfpgaclk->fixed_div) @@ -36,9 +36,9 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk *clk, return parent_rate / div; } -static int socfpga_clk_prepare(struct clk *clk) +static int socfpga_clk_prepare(struct clk_hw *hw) { - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(clk); + struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hw); int i; u32 hs_timing; u32 clk_phase[2]; @@ -82,12 +82,12 @@ static int socfpga_clk_prepare(struct clk *clk) return 0; } -static int clk_socfpga_enable(struct clk *clk) +static int clk_socfpga_enable(struct clk_hw *hw) { - struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(clk); + struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(hw); u32 val; - socfpga_clk_prepare(clk); + socfpga_clk_prepare(hw); val = readl(socfpga_clk->reg); val |= 1 << socfpga_clk->bit_idx; @@ -96,9 +96,9 @@ static int clk_socfpga_enable(struct clk *clk) return 0; } -static void clk_socfpga_disable(struct clk *clk) +static void clk_socfpga_disable(struct clk_hw *hw) { - struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(clk); + struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(hw); u32 val; val = readl(socfpga_clk->reg); @@ -159,8 +159,8 @@ static struct clk *__socfpga_gate_init(struct device_node *node, of_property_read_string(node, "clock-output-names", &clk_name); - socfpga_clk->clk.name = xstrdup(clk_name); - socfpga_clk->clk.ops = ops; + socfpga_clk->hw.clk.name = xstrdup(clk_name); + socfpga_clk->hw.clk.ops = ops; for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) { socfpga_clk->parent_names[i] = of_clk_get_parent_name(node, i); @@ -168,16 +168,16 @@ static struct clk *__socfpga_gate_init(struct device_node *node, break; } - socfpga_clk->clk.num_parents = i; - socfpga_clk->clk.parent_names = socfpga_clk->parent_names; + socfpga_clk->hw.clk.num_parents = i; + socfpga_clk->hw.clk.parent_names = socfpga_clk->parent_names; - rc = clk_register(&socfpga_clk->clk); + rc = bclk_register(&socfpga_clk->hw.clk); if (rc) { free(socfpga_clk); return ERR_PTR(rc); } - return &socfpga_clk->clk; + return &socfpga_clk->hw.clk; } struct clk *socfpga_a10_gate_init(struct device_node *node) diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c index 4ef00052e4..f9cf40b0aa 100644 --- a/drivers/clk/socfpga/clk-periph-a10.c +++ b/drivers/clk/socfpga/clk-periph-a10.c @@ -17,12 +17,12 @@ #define SOCFPGA_MPU_FREE_CLK "mpu_free_clk" #define SOCFPGA_NOC_FREE_CLK "noc_free_clk" #define SOCFPGA_SDMMC_FREE_CLK "sdmmc_free_clk" -#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, clk) +#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw) -static unsigned long clk_periclk_recalc_rate(struct clk *clk, +static unsigned long clk_periclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(clk); + struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hw); u32 div; if (socfpgaclk->fixed_div) { @@ -38,15 +38,15 @@ static unsigned long clk_periclk_recalc_rate(struct clk *clk, return parent_rate / div; } -static int clk_periclk_get_parent(struct clk *clk) +static int clk_periclk_get_parent(struct clk_hw *hw) { - struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(clk); + struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hw); u32 clk_src; clk_src = readl(socfpgaclk->reg); - if (streq(clk->name, SOCFPGA_MPU_FREE_CLK) || - streq(clk->name, SOCFPGA_NOC_FREE_CLK) || - streq(clk->name, SOCFPGA_SDMMC_FREE_CLK)) + if (streq(clk_hw_get_name(hw), SOCFPGA_MPU_FREE_CLK) || + streq(clk_hw_get_name(hw), SOCFPGA_NOC_FREE_CLK) || + streq(clk_hw_get_name(hw), SOCFPGA_SDMMC_FREE_CLK)) return (clk_src >> CLK_MGR_FREE_SHIFT) & CLK_MGR_FREE_MASK; else @@ -98,19 +98,19 @@ static struct clk *__socfpga_periph_init(struct device_node *node, break; } - periph_clk->clk.num_parents = i; - periph_clk->clk.parent_names = periph_clk->parent_names; + periph_clk->hw.clk.num_parents = i; + periph_clk->hw.clk.parent_names = periph_clk->parent_names; - periph_clk->clk.name = xstrdup(clk_name); - periph_clk->clk.ops = ops; + periph_clk->hw.clk.name = xstrdup(clk_name); + periph_clk->hw.clk.ops = ops; - rc = clk_register(&periph_clk->clk); + rc = bclk_register(&periph_clk->hw.clk); if (rc) { free(periph_clk); return ERR_PTR(rc); } - return &periph_clk->clk; + return &periph_clk->hw.clk; } struct clk *socfpga_a10_periph_init(struct device_node *node) diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index fcf31e9ea1..2e58a2eb5d 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -28,12 +28,12 @@ #define SOCFPGA_MAIN_PLL_CLK "main_pll" #define SOCFPGA_PERIP_PLL_CLK "periph_pll" -#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, clk) +#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw) -static unsigned long clk_pll_recalc_rate(struct clk *clk, +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct socfpga_pll *socfpgaclk = to_socfpga_clk(clk); + struct socfpga_pll *socfpgaclk = to_socfpga_clk(hw); unsigned long divf, divq, reg; unsigned long long vco_freq; @@ -46,9 +46,9 @@ static unsigned long clk_pll_recalc_rate(struct clk *clk, return (unsigned long)vco_freq; } -static int clk_pll_get_parent(struct clk *clk) +static int clk_pll_get_parent(struct clk_hw *hw) { - struct socfpga_pll *socfpgaclk = to_socfpga_clk(clk); + struct socfpga_pll *socfpgaclk = to_socfpga_clk(hw); u32 pll_src; pll_src = readl(socfpgaclk->reg); @@ -57,9 +57,9 @@ static int clk_pll_get_parent(struct clk *clk) CLK_MGR_PLL_CLK_SRC_MASK; } -static int clk_socfpga_enable(struct clk *clk) +static int clk_socfpga_enable(struct clk_hw *hw) { - struct socfpga_pll *socfpga_clk = to_socfpga_clk(clk); + struct socfpga_pll *socfpga_clk = to_socfpga_clk(hw); u32 val; val = readl(socfpga_clk->reg); @@ -69,9 +69,9 @@ static int clk_socfpga_enable(struct clk *clk) return 0; } -static void clk_socfpga_disable(struct clk *clk) +static void clk_socfpga_disable(struct clk_hw *hw) { - struct socfpga_pll *socfpga_clk = to_socfpga_clk(clk); + struct socfpga_pll *socfpga_clk = to_socfpga_clk(hw); u32 val; val = readl(socfpga_clk->reg); @@ -101,8 +101,8 @@ static struct clk *__socfpga_pll_init(struct device_node *node, of_property_read_string(node, "clock-output-names", &clk_name); - pll_clk->clk.name = xstrdup(clk_name); - pll_clk->clk.ops = ops; + pll_clk->hw.clk.name = xstrdup(clk_name); + pll_clk->hw.clk.ops = ops; for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) { pll_clk->parent_names[i] = of_clk_get_parent_name(node, i); @@ -111,19 +111,19 @@ static struct clk *__socfpga_pll_init(struct device_node *node, } pll_clk->bit_idx = SOCFPGA_PLL_EXT_ENA; - pll_clk->clk.num_parents = i; - pll_clk->clk.parent_names = pll_clk->parent_names; + pll_clk->hw.clk.num_parents = i; + pll_clk->hw.clk.parent_names = pll_clk->parent_names; clk_pll_ops.enable = clk_socfpga_enable; clk_pll_ops.disable = clk_socfpga_disable; - rc = clk_register(&pll_clk->clk); + rc = bclk_register(&pll_clk->hw.clk); if (rc) { free(pll_clk); return NULL; } - return &pll_clk->clk; + return &pll_clk->hw.clk; } struct clk *socfpga_a10_pll_init(struct device_node *node) diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c index 09e2039bd5..8ee405c6c6 100644 --- a/drivers/clk/socfpga/clk.c +++ b/drivers/clk/socfpga/clk.c @@ -50,15 +50,15 @@ void __iomem *clk_mgr_base_addr; struct clk_pll { - struct clk clk; + struct clk_hw hw; const char *parent; unsigned regofs; }; -static unsigned long clk_pll_recalc_rate(struct clk *clk, +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_pll *pll = container_of(clk, struct clk_pll, clk); + struct clk_pll *pll = container_of(hw, struct clk_pll, hw); unsigned long divf, divq, vco_freq, reg; unsigned long bypass; @@ -90,24 +90,24 @@ static struct clk *socfpga_pll_clk(struct device_node *node) if (!pll->parent) return ERR_PTR(-EINVAL); - pll->clk.parent_names = &pll->parent; - pll->clk.num_parents = 1; - pll->clk.name = xstrdup(node->name); - pll->clk.ops = &clk_pll_ops; + pll->hw.clk.parent_names = &pll->parent; + pll->hw.clk.num_parents = 1; + pll->hw.clk.name = xstrdup(node->name); + pll->hw.clk.ops = &clk_pll_ops; of_property_read_u32(node, "reg", &pll->regofs); - ret = clk_register(&pll->clk); + ret = bclk_register(&pll->hw.clk); if (ret) { free(pll); return ERR_PTR(ret); } - return &pll->clk; + return &pll->hw.clk; } struct clk_periph { - struct clk clk; + struct clk_hw hw; const char *parent; unsigned regofs; unsigned int fixed_div; @@ -116,10 +116,10 @@ struct clk_periph { unsigned int shift; }; -static unsigned long clk_periph_recalc_rate(struct clk *clk, +static unsigned long clk_periph_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_periph *periph = container_of(clk, struct clk_periph, clk); + struct clk_periph *periph = container_of(hw, struct clk_periph, hw); u32 div, val; if (periph->fixed_div) { @@ -152,10 +152,10 @@ static struct clk *socfpga_periph_clk(struct device_node *node) if (!periph->parent) return ERR_PTR(-EINVAL); - periph->clk.parent_names = &periph->parent; - periph->clk.num_parents = 1; - periph->clk.name = xstrdup(node->name); - periph->clk.ops = &clk_periph_ops; + periph->hw.clk.parent_names = &periph->parent; + periph->hw.clk.num_parents = 1; + periph->hw.clk.name = xstrdup(node->name); + periph->hw.clk.ops = &clk_periph_ops; ret = of_property_read_u32_array(node, "div-reg", div_reg, 3); if (!ret) { @@ -169,17 +169,17 @@ static struct clk *socfpga_periph_clk(struct device_node *node) of_property_read_u32(node, "reg", &periph->regofs); of_property_read_u32(node, "fixed-divider", &periph->fixed_div); - ret = clk_register(&periph->clk); + ret = bclk_register(&periph->hw.clk); if (ret) { free(periph); return ERR_PTR(ret); } - return &periph->clk; + return &periph->hw.clk; } struct clk_socfpga { - struct clk clk; + struct clk_hw hw; const char *parent; void __iomem *reg; void __iomem *div_reg; @@ -190,9 +190,9 @@ struct clk_socfpga { const char *parent_names[SOCFGPA_MAX_PARENTS]; }; -static int clk_socfpga_enable(struct clk *clk) +static int clk_socfpga_enable(struct clk_hw *hw) { - struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk); + struct clk_socfpga *cs = container_of(hw, struct clk_socfpga, hw); u32 val; val = readl(cs->reg); @@ -202,9 +202,9 @@ static int clk_socfpga_enable(struct clk *clk) return 0; } -static void clk_socfpga_disable(struct clk *clk) +static void clk_socfpga_disable(struct clk_hw *hw) { - struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk); + struct clk_socfpga *cs = container_of(hw, struct clk_socfpga, hw); u32 val; val = readl(cs->reg); @@ -212,9 +212,9 @@ static void clk_socfpga_disable(struct clk *clk) writel(val, cs->reg); } -static int clk_socfpga_is_enabled(struct clk *clk) +static int clk_socfpga_is_enabled(struct clk_hw *hw) { - struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk); + struct clk_socfpga *cs = container_of(hw, struct clk_socfpga, hw); u32 val; val = readl(cs->reg); @@ -225,10 +225,10 @@ static int clk_socfpga_is_enabled(struct clk *clk) return 0; } -static unsigned long clk_socfpga_recalc_rate(struct clk *clk, +static unsigned long clk_socfpga_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk); + struct clk_socfpga *cs = container_of(hw, struct clk_socfpga, hw); u32 div = 1, val; if (cs->fixed_div) { @@ -236,7 +236,7 @@ static unsigned long clk_socfpga_recalc_rate(struct clk *clk, } else if (cs->div_reg) { val = readl(cs->div_reg) >> cs->shift; val &= div_mask(cs->width); - if (streq(clk->name, SOCFPGA_DB_CLK)) + if (streq(clk_hw_get_name(hw), SOCFPGA_DB_CLK)) div = val + 1; else div = (1 << val); @@ -245,8 +245,9 @@ static unsigned long clk_socfpga_recalc_rate(struct clk *clk, return parent_rate / div; } -static int clk_socfpga_get_parent(struct clk *clk) +static int clk_socfpga_get_parent(struct clk_hw *hw) { + struct clk *clk = clk_hw_to_clk(hw); u32 perpll_src; u32 l4_src; @@ -270,8 +271,9 @@ static int clk_socfpga_get_parent(struct clk *clk) return (perpll_src >> 4) & 3; } -static int clk_socfpga_set_parent(struct clk *clk, u8 parent) +static int clk_socfpga_set_parent(struct clk_hw *hw, u8 parent) { + struct clk *clk = clk_hw_to_clk(hw); u32 src_reg; if (streq(clk->name, SOCFPGA_L4_MP_CLK)) { @@ -351,18 +353,18 @@ static struct clk *socfpga_gate_clk(struct device_node *node) break; } - cs->clk.parent_names = cs->parent_names; - cs->clk.num_parents = i; - cs->clk.name = xstrdup(node->name); - cs->clk.ops = &clk_socfpga_ops; + cs->hw.clk.parent_names = cs->parent_names; + cs->hw.clk.num_parents = i; + cs->hw.clk.name = xstrdup(node->name); + cs->hw.clk.ops = &clk_socfpga_ops; - ret = clk_register(&cs->clk); + ret = bclk_register(&cs->hw.clk); if (ret) { free(cs); return ERR_PTR(ret); } - return &cs->clk; + return &cs->hw.clk; } static void socfpga_register_clocks(struct device_d *dev, struct device_node *node) diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h index 9d291f7243..402f714436 100644 --- a/drivers/clk/socfpga/clk.h +++ b/drivers/clk/socfpga/clk.h @@ -47,14 +47,14 @@ static inline struct clk *socfpga_a10_gate_init(struct device_node *node) #endif struct socfpga_pll { - struct clk clk; + struct clk_hw hw; void __iomem *reg; u32 bit_idx; const char *parent_names[SOCFPGA_MAX_PARENTS]; }; struct socfpga_gate_clk { - struct clk clk; + struct clk_hw hw; char *parent_name; u32 fixed_div; void __iomem *div_reg; @@ -68,7 +68,7 @@ struct socfpga_gate_clk { }; struct socfpga_periph_clk { - struct clk clk; + struct clk_hw hw; void __iomem *reg; char *parent_name; u32 fixed_div; diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index cc8b85520c..f1a913d983 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -46,21 +46,22 @@ static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, if (flags & TEGRA_DIVIDER_INT) divider_ux1 *= mul; - divider_ux1 -= mul; - - if (divider_ux1 < 0) + if (divider_ux1 < mul) return 0; + divider_ux1 -= mul; + if (divider_ux1 > get_max_div(divider)) return -EINVAL; return divider_ux1; } -static unsigned long clk_frac_div_recalc_rate(struct clk *hw, +static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); + struct clk *clk = clk_hw_to_clk(hw); + struct tegra_clk_frac_div *divider = to_clk_frac_div(clk); u32 reg; int div, mul; u64 rate = parent_rate; @@ -78,10 +79,11 @@ static unsigned long clk_frac_div_recalc_rate(struct clk *hw, return rate; } -static long clk_frac_div_round_rate(struct clk *hw, unsigned long rate, +static long clk_frac_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { - struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); + struct clk *clk = clk_hw_to_clk(hw); + struct tegra_clk_frac_div *divider = to_clk_frac_div(clk); int div, mul; unsigned long output_rate = *prate; @@ -97,10 +99,11 @@ static long clk_frac_div_round_rate(struct clk *hw, unsigned long rate, return DIV_ROUND_UP(output_rate * mul, div + mul); } -static int clk_frac_div_set_rate(struct clk *hw, unsigned long rate, +static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); + struct clk *clk = clk_hw_to_clk(hw); + struct tegra_clk_frac_div *divider = to_clk_frac_div(clk); int div; u32 val; @@ -180,7 +183,7 @@ struct clk *tegra_clk_register_divider(const char *name, reg, flags, clk_divider_flags, shift, width, frac_width)); - ret = clk_register(÷r->hw); + ret = bclk_register(÷r->hw); if (ret) { kfree(divider); return ERR_PTR(ret); diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index 0cd5200e84..7bfb14875d 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c @@ -16,65 +16,65 @@ #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) -static int clk_periph_get_parent(struct clk *hw) +static int clk_periph_get_parent(struct clk_hw *hw) { struct tegra_clk_periph *periph = to_clk_periph(hw); - return periph->mux->ops->get_parent(periph->mux); + return periph->mux->ops->get_parent(clk_to_clk_hw(periph->mux)); } -static int clk_periph_set_parent(struct clk *hw, u8 index) +static int clk_periph_set_parent(struct clk_hw *hw, u8 index) { struct tegra_clk_periph *periph = to_clk_periph(hw); - return periph->mux->ops->set_parent(periph->mux, index); + return periph->mux->ops->set_parent(clk_to_clk_hw(periph->mux), index); } -static unsigned long clk_periph_recalc_rate(struct clk *hw, +static unsigned long clk_periph_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct tegra_clk_periph *periph = to_clk_periph(hw); - return periph->div->ops->recalc_rate(periph->div, parent_rate); + return periph->div->ops->recalc_rate(clk_to_clk_hw(periph->div), parent_rate); } -static long clk_periph_round_rate(struct clk *hw, unsigned long rate, +static long clk_periph_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct tegra_clk_periph *periph = to_clk_periph(hw); - return periph->div->ops->round_rate(periph->div, rate, prate); + return periph->div->ops->round_rate(clk_to_clk_hw(periph->div), rate, prate); } -static int clk_periph_set_rate(struct clk *hw, unsigned long rate, +static int clk_periph_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct tegra_clk_periph *periph = to_clk_periph(hw); - return periph->div->ops->set_rate(periph->div, rate, parent_rate); + return periph->div->ops->set_rate(clk_to_clk_hw(periph->div), rate, parent_rate); } -static int clk_periph_is_enabled(struct clk *hw) +static int clk_periph_is_enabled(struct clk_hw *hw) { struct tegra_clk_periph *periph = to_clk_periph(hw); - return periph->gate->ops->is_enabled(periph->gate); + return periph->gate->ops->is_enabled(clk_to_clk_hw(periph->gate)); } -static int clk_periph_enable(struct clk *hw) +static int clk_periph_enable(struct clk_hw *hw) { struct tegra_clk_periph *periph = to_clk_periph(hw); - periph->gate->ops->enable(periph->gate); + periph->gate->ops->enable(clk_to_clk_hw(periph->gate)); return 0; } -static void clk_periph_disable(struct clk *hw) +static void clk_periph_disable(struct clk_hw *hw) { struct tegra_clk_periph *periph = to_clk_periph(hw); - periph->gate->ops->disable(periph->gate); + periph->gate->ops->disable(clk_to_clk_hw(periph->gate)); } const struct clk_ops tegra_clk_periph_ops = { @@ -139,11 +139,11 @@ static struct clk *_tegra_clk_register_periph(const char *name, goto out_div; } - periph->hw.name = name; - periph->hw.ops = div ? &tegra_clk_periph_ops : + periph->hw.clk.name = name; + periph->hw.clk.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops; - periph->hw.parent_names = parent_names; - periph->hw.num_parents = num_parents; + periph->hw.clk.parent_names = parent_names; + periph->hw.clk.num_parents = num_parents; periph->flags = flags; if (id >= 96) @@ -153,11 +153,11 @@ static struct clk *_tegra_clk_register_periph(const char *name, periph->rst_reg = clk_base + rst_offs; periph->rst_shift = id & 0x1f; - ret = clk_register(&periph->hw); + ret = bclk_register(&periph->hw.clk); if (ret) goto out_register; - return &periph->hw; + return &periph->hw.clk; out_register: tegra_clk_divider_free(periph->div); diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c index e186275563..f14b41c04a 100644 --- a/drivers/clk/tegra/clk-pll-out.c +++ b/drivers/clk/tegra/clk-pll-out.c @@ -18,7 +18,7 @@ #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) -static int clk_pll_out_is_enabled(struct clk *hw) +static int clk_pll_out_is_enabled(struct clk_hw *hw) { struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); u32 val = readl(pll_out->reg); @@ -30,7 +30,7 @@ static int clk_pll_out_is_enabled(struct clk *hw) return state; } -static int clk_pll_out_enable(struct clk *hw) +static int clk_pll_out_enable(struct clk_hw *hw) { struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); u32 val; @@ -45,7 +45,7 @@ static int clk_pll_out_enable(struct clk *hw) return 0; } -static void clk_pll_out_disable(struct clk *hw) +static void clk_pll_out_disable(struct clk_hw *hw) { struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); u32 val; @@ -58,28 +58,28 @@ static void clk_pll_out_disable(struct clk *hw) udelay(2); } -static unsigned long clk_pll_out_recalc_rate(struct clk *hw, +static unsigned long clk_pll_out_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); - return pll_out->div->ops->recalc_rate(pll_out->div, parent_rate); + return pll_out->div->ops->recalc_rate(clk_to_clk_hw(pll_out->div), parent_rate); } -static long clk_pll_out_round_rate(struct clk *hw, unsigned long rate, +static long clk_pll_out_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); - return pll_out->div->ops->round_rate(pll_out->div, rate, prate); + return pll_out->div->ops->round_rate(clk_to_clk_hw(pll_out->div), rate, prate); } -static int clk_pll_out_set_rate(struct clk *hw, unsigned long rate, +static int clk_pll_out_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); - return pll_out->div->ops->set_rate(pll_out->div, rate, parent_rate); + return pll_out->div->ops->set_rate(clk_to_clk_hw(pll_out->div), rate, parent_rate); } const struct clk_ops tegra_clk_pll_out_ops = { @@ -108,21 +108,21 @@ struct clk *tegra_clk_register_pll_out(const char *name, } pll_out->parent = parent_name; - pll_out->hw.name = name; - pll_out->hw.ops = &tegra_clk_pll_out_ops; - pll_out->hw.parent_names = (pll_out->parent ? &pll_out->parent : NULL); - pll_out->hw.num_parents = (pll_out->parent ? 1 : 0); + pll_out->hw.clk.name = name; + pll_out->hw.clk.ops = &tegra_clk_pll_out_ops; + pll_out->hw.clk.parent_names = (pll_out->parent ? &pll_out->parent : NULL); + pll_out->hw.clk.num_parents = (pll_out->parent ? 1 : 0); pll_out->reg = reg; pll_out->enb_bit_idx = shift + 1; pll_out->rst_bit_idx = shift; - ret = clk_register(&pll_out->hw); + ret = bclk_register(&pll_out->hw.clk); if (ret) { tegra_clk_divider_free(pll_out->div); kfree(pll_out); return ERR_PTR(ret); } - return &pll_out->hw; + return &pll_out->hw.clk; } diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 832b3c5ea1..0d364f318d 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -144,7 +144,7 @@ #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) -static int clk_pll_is_enabled(struct clk *hw) +static int clk_pll_is_enabled(struct clk_hw *hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); u32 val; @@ -187,12 +187,12 @@ static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll, } pr_err("%s: Timed out waiting for pll %s lock\n", __func__, - pll->hw.name); + clk_hw_get_name(&pll->hw)); return -1; } -static int clk_pll_enable(struct clk *hw) +static int clk_pll_enable(struct clk_hw *hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); u32 val; @@ -210,7 +210,7 @@ static int clk_pll_enable(struct clk *hw) return 0; } -static void clk_pll_disable(struct clk *hw) +static void clk_pll_disable(struct clk_hw *hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); u32 val; @@ -220,7 +220,7 @@ static void clk_pll_disable(struct clk *hw) pll_writel_base(val, pll); } -static int _get_table_rate(struct clk *hw, +static int _get_table_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) { @@ -245,7 +245,7 @@ static int _get_table_rate(struct clk *hw, return 0; } -static unsigned long clk_pll_recalc_rate(struct clk *hw, +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct tegra_clk_pll *pll = to_clk_pll(hw); @@ -260,7 +260,7 @@ static unsigned long clk_pll_recalc_rate(struct clk *hw, struct tegra_clk_pll_freq_table sel; if (_get_table_rate(hw, &sel, pll->fixed_rate, parent_rate)) { pr_err("Clock %s has unknown fixed frequency\n", - hw->name); + clk_hw_get_name(hw)); BUG(); } return pll->fixed_rate; @@ -280,7 +280,7 @@ static unsigned long clk_pll_recalc_rate(struct clk *hw, return rate; } -static int _calc_rate(struct clk *hw, struct tegra_clk_pll_freq_table *cfg, +static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) { struct tegra_clk_pll *pll = to_clk_pll(hw); @@ -325,14 +325,14 @@ static int _calc_rate(struct clk *hw, struct tegra_clk_pll_freq_table *cfg, if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || cfg->p > divp_max(pll) || cfg->output_rate > pll->params->vco_max) { pr_err("%s: Failed to set %s rate %lu\n", - __func__, hw->name, rate); + __func__, clk_hw_get_name(hw), rate); return -EINVAL; } return 0; } -static long clk_pll_round_rate(struct clk *hw, unsigned long rate, +static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct tegra_clk_pll *pll = to_clk_pll(hw); @@ -344,7 +344,7 @@ static long clk_pll_round_rate(struct clk *hw, unsigned long rate, /* PLLM is used for memory; we do not change rate */ if (pll->flags & TEGRA_PLLM) - return clk_get_rate(hw); + return clk_get_rate(clk_hw_to_clk(hw)); if (_get_table_rate(hw, &cfg, rate, *prate) && _calc_rate(hw, &cfg, rate, *prate)) @@ -356,7 +356,7 @@ static long clk_pll_round_rate(struct clk *hw, unsigned long rate, return output_rate; } -static int _program_pll(struct clk *hw, struct tegra_clk_pll_freq_table *cfg, +static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate) { struct tegra_clk_pll *pll = to_clk_pll(hw); @@ -411,7 +411,7 @@ static int _program_pll(struct clk *hw, struct tegra_clk_pll_freq_table *cfg, return 0; } -static int clk_pll_set_rate(struct clk *hw, unsigned long rate, +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct tegra_clk_pll_freq_table cfg; @@ -432,7 +432,7 @@ const struct clk_ops tegra_clk_pll_ops = { .set_rate = clk_pll_set_rate, }; -static unsigned long clk_plle_recalc_rate(struct clk *hw, +static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct tegra_clk_pll *pll = to_clk_pll(hw); @@ -474,10 +474,10 @@ static int clk_plle_training(struct tegra_clk_pll *pll) (pll_readl_misc(pll) & PLLE_MISC_READY)); } -static int clk_plle_enable(struct clk *hw) +static int clk_plle_enable(struct clk_hw *hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); - unsigned long input_rate = clk_get_rate(clk_get_parent(hw)); + unsigned long input_rate = clk_get_rate(clk_get_parent(clk_hw_to_clk(hw))); struct tegra_clk_pll_freq_table sel; u32 val; int err; @@ -534,10 +534,10 @@ const struct clk_ops tegra_clk_plle_ops = { .enable = clk_plle_enable, }; -static int clk_plle_tegra114_enable(struct clk *hw) +static int clk_plle_tegra114_enable(struct clk_hw *hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); - unsigned long input_rate = clk_get_rate(clk_get_parent(hw)); + unsigned long input_rate = clk_get_rate(clk_get_parent(clk_hw_to_clk(hw))); struct tegra_clk_pll_freq_table sel; u32 val; int ret; @@ -623,7 +623,7 @@ static int clk_plle_tegra114_enable(struct clk *hw) return ret; } -static void clk_plle_tegra114_disable(struct clk *hw) +static void clk_plle_tegra114_disable(struct clk_hw *hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); u32 val; @@ -658,11 +658,11 @@ static struct clk *_tegra_clk_register_pll(const char *name, return NULL; pll->parent = parent_name; - pll->hw.name = name; - pll->hw.ops = ops; - pll->hw.flags = flags; - pll->hw.parent_names = (pll->parent ? &pll->parent : NULL); - pll->hw.num_parents = (pll->parent ? 1 : 0); + pll->hw.clk.name = name; + pll->hw.clk.ops = ops; + pll->hw.clk.flags = flags; + pll->hw.clk.parent_names = (pll->parent ? &pll->parent : NULL); + pll->hw.clk.num_parents = (pll->parent ? 1 : 0); pll->clk_base = clk_base; @@ -678,13 +678,13 @@ static struct clk *_tegra_clk_register_pll(const char *name, pll->divm_shift = PLL_BASE_DIVM_SHIFT; pll->divm_width = PLL_BASE_DIVM_WIDTH; - ret = clk_register(&pll->hw); + ret = bclk_register(&pll->hw.clk); if (ret) { kfree(pll); return ERR_PTR(ret); } - return &pll->hw; + return &pll->hw.clk; } struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 5195e6dba4..80a83c7865 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -61,7 +61,7 @@ struct tegra_clk_pll_params { /* struct tegra_clk_pll - Tegra PLL clock */ struct tegra_clk_pll { - struct clk hw; + struct clk_hw hw; void __iomem *clk_base; u8 flags; unsigned long fixed_rate; @@ -105,7 +105,7 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name, /* struct tegra_clk_pll_out - PLL output divider */ struct tegra_clk_pll_out { - struct clk hw; + struct clk_hw hw; struct clk *div; void __iomem *reg; u8 enb_bit_idx; @@ -119,7 +119,7 @@ struct clk *tegra_clk_register_pll_out(const char *name, /* struct clk-periph - peripheral clock */ struct tegra_clk_periph { - struct clk hw; + struct clk_hw hw; struct clk *gate; struct clk *mux; struct clk *div; diff --git a/drivers/clk/vexpress/clk-sp810.c b/drivers/clk/vexpress/clk-sp810.c index 968921203b..6eba0a2285 100644 --- a/drivers/clk/vexpress/clk-sp810.c +++ b/drivers/clk/vexpress/clk-sp810.c @@ -15,15 +15,15 @@ struct clk_sp810; struct clk_sp810_timerclken { - struct clk hw; + struct clk_hw hw; struct clk_sp810 *sp810; int channel; }; static inline struct clk_sp810_timerclken * -to_clk_sp810_timerclken(struct clk *clk) +to_clk_sp810_timerclken(struct clk_hw *hw) { - return container_of(clk, struct clk_sp810_timerclken, hw); + return container_of(hw, struct clk_sp810_timerclken, hw); } struct clk_sp810 { @@ -32,12 +32,12 @@ struct clk_sp810 { struct clk_sp810_timerclken timerclken[4]; }; -static int clk_sp810_timerclken_get_parent(struct clk *hw) +static int clk_sp810_timerclken_get_parent(struct clk_hw *hw) { return 1; } -static int clk_sp810_timerclken_set_parent(struct clk *hw, u8 index) +static int clk_sp810_timerclken_set_parent(struct clk_hw *hw, u8 index) { struct clk_sp810_timerclken *timerclken = to_clk_sp810_timerclken(hw); struct clk_sp810 *sp810 = timerclken->sp810; @@ -71,7 +71,7 @@ static struct clk *clk_sp810_timerclken_of_get(struct of_phandle_args *clkspec, clkspec->args[0] >= ARRAY_SIZE(sp810->timerclken))) return NULL; - return &sp810->timerclken[clkspec->args[0]].hw; + return &sp810->timerclken[clkspec->args[0]].hw.clk; } static void clk_sp810_of_setup(struct device_node *node) @@ -100,18 +100,18 @@ static void clk_sp810_of_setup(struct device_node *node) sp810->timerclken[i].sp810 = sp810; sp810->timerclken[i].channel = i; - sp810->timerclken[i].hw.name = strdup(name); - sp810->timerclken[i].hw.parent_names = parent_names; - sp810->timerclken[i].hw.num_parents = num; - sp810->timerclken[i].hw.ops = &clk_sp810_timerclken_ops; + sp810->timerclken[i].hw.clk.name = strdup(name); + sp810->timerclken[i].hw.clk.parent_names = parent_names; + sp810->timerclken[i].hw.clk.num_parents = num; + sp810->timerclken[i].hw.clk.ops = &clk_sp810_timerclken_ops; + + bclk_register(&sp810->timerclken[i].hw.clk); /* * Always set parent to 1MHz clock to match QEMU emulation * and satisfy requirements on real HW. */ clk_sp810_timerclken_set_parent(&sp810->timerclken[i].hw, 1); - - clk_register(&sp810->timerclken[i].hw); } of_clk_add_provider(node, clk_sp810_timerclken_of_get, sp810); diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 23259a5324..e4ce102d6e 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -50,25 +50,25 @@ static struct clk *clks[clk_max]; static struct clk_onecell_data clk_data; struct zynq_pll_clk { - struct clk clk; + struct clk_hw hw; u32 pll_lock; void __iomem *pll_ctrl; }; -#define to_zynq_pll_clk(c) container_of(c, struct zynq_pll_clk, clk) +#define to_zynq_pll_clk(c) container_of(c, struct zynq_pll_clk, hw) #define PLL_CTRL_FDIV(x) (((x) >> 12) & 0x7F) -static unsigned long zynq_pll_recalc_rate(struct clk *clk, +static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct zynq_pll_clk *pll = to_zynq_pll_clk(clk); + struct zynq_pll_clk *pll = to_zynq_pll_clk(hw); return parent_rate * PLL_CTRL_FDIV(readl(pll->pll_ctrl)); } -static int zynq_pll_enable(struct clk *clk) +static int zynq_pll_enable(struct clk_hw *hw) { - struct zynq_pll_clk *pll = to_zynq_pll_clk(clk); + struct zynq_pll_clk *pll = to_zynq_pll_clk(hw); u32 val; int timeout = 10000; @@ -87,9 +87,9 @@ static int zynq_pll_enable(struct clk *clk) return 0; } -static int zynq_pll_is_enabled(struct clk *clk) +static int zynq_pll_is_enabled(struct clk_hw *hw) { - struct zynq_pll_clk *pll = to_zynq_pll_clk(clk); + struct zynq_pll_clk *pll = to_zynq_pll_clk(hw); u32 val = readl(pll->pll_ctrl); return !(val & (PLL_CTRL_PWRDOWN | PLL_CTRL_RESET)); @@ -111,10 +111,10 @@ static inline struct clk *zynq_pll_clk(enum zynq_pll_type type, pll = xzalloc(sizeof(*pll)); pll->pll_ctrl = pll_ctrl; - pll->clk.ops = &zynq_pll_clk_ops; - pll->clk.name = name; - pll->clk.parent_names = &pll_parent; - pll->clk.num_parents = 1; + pll->hw.clk.ops = &zynq_pll_clk_ops; + pll->hw.clk.name = name; + pll->hw.clk.parent_names = &pll_parent; + pll->hw.clk.num_parents = 1; switch(type) { case ZYNQ_PLL_ARM: @@ -128,17 +128,17 @@ static inline struct clk *zynq_pll_clk(enum zynq_pll_type type, break; } - ret = clk_register(&pll->clk); + ret = bclk_register(&pll->hw.clk); if (ret) { free(pll); return ERR_PTR(ret); } - return &pll->clk; + return &pll->hw.clk; } struct zynq_periph_clk { - struct clk clk; + struct clk_hw hw; void __iomem *clk_ctrl; }; @@ -150,16 +150,16 @@ static const u8 periph_clk_parent_map[] = { #define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >> 4]) #define PERIPH_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8) -static unsigned long zynq_periph_recalc_rate(struct clk *clk, +static unsigned long zynq_periph_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct zynq_periph_clk *periph = to_zynq_periph_clk(clk); + struct zynq_periph_clk *periph = to_zynq_periph_clk(hw); return parent_rate / PERIPH_CLK_CTRL_DIV(readl(periph->clk_ctrl)); } -static int zynq_periph_get_parent(struct clk *clk) +static int zynq_periph_get_parent(struct clk_hw *hw) { - struct zynq_periph_clk *periph = to_zynq_periph_clk(clk); + struct zynq_periph_clk *periph = to_zynq_periph_clk(hw); return PERIPH_CLK_CTRL_SRC(readl(periph->clk_ctrl)); } @@ -181,18 +181,18 @@ static struct clk *zynq_periph_clk(const char *name, void __iomem *clk_ctrl) periph = xzalloc(sizeof(*periph)); periph->clk_ctrl = clk_ctrl; - periph->clk.name = name; - periph->clk.ops = &zynq_periph_clk_ops; - periph->clk.parent_names = peripheral_parents; - periph->clk.num_parents = ARRAY_SIZE(peripheral_parents); + periph->hw.clk.name = name; + periph->hw.clk.ops = &zynq_periph_clk_ops; + periph->hw.clk.parent_names = peripheral_parents; + periph->hw.clk.num_parents = ARRAY_SIZE(peripheral_parents); - ret = clk_register(&periph->clk); + ret = bclk_register(&periph->hw.clk); if (ret) { free(periph); return ERR_PTR(ret); } - return &periph->clk; + return &periph->hw.clk; } /* CPU Clock domain is modelled as a mux with 4 children subclks, whose @@ -200,7 +200,7 @@ static struct clk *zynq_periph_clk(const char *name, void __iomem *clk_ctrl) */ struct zynq_cpu_clk { - struct clk clk; + struct clk_hw hw; void __iomem *clk_ctrl; }; @@ -212,16 +212,16 @@ static const u8 zynq_cpu_clk_parent_map[] = { #define CPU_CLK_SRCSEL(x) (zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)]) #define CPU_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8) -static unsigned long zynq_cpu_clk_recalc_rate(struct clk *clk, +static unsigned long zynq_cpu_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(clk); + struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw); return parent_rate / CPU_CLK_CTRL_DIV(readl(cpuclk->clk_ctrl)); } -static int zynq_cpu_clk_get_parent(struct clk *clk) +static int zynq_cpu_clk_get_parent(struct clk_hw *hw) { - struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(clk); + struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw); return CPU_CLK_SRCSEL(readl(cpuclk->clk_ctrl)); } @@ -243,18 +243,18 @@ static struct clk *zynq_cpu_clk(const char *name, void __iomem *clk_ctrl) cpu = xzalloc(sizeof(*cpu)); cpu->clk_ctrl = clk_ctrl; - cpu->clk.ops = &zynq_cpu_clk_ops; - cpu->clk.name = name; - cpu->clk.parent_names = cpu_parents; - cpu->clk.num_parents = ARRAY_SIZE(cpu_parents); + cpu->hw.clk.ops = &zynq_cpu_clk_ops; + cpu->hw.clk.name = name; + cpu->hw.clk.parent_names = cpu_parents; + cpu->hw.clk.num_parents = ARRAY_SIZE(cpu_parents); - ret = clk_register(&cpu->clk); + ret = bclk_register(&cpu->hw.clk); if (ret) { free(cpu); return ERR_PTR(ret); } - return &cpu->clk; + return &cpu->hw.clk; } enum zynq_cpu_subclk_which { @@ -265,7 +265,7 @@ enum zynq_cpu_subclk_which { }; struct zynq_cpu_subclk { - struct clk clk; + struct clk_hw hw; void __iomem *clk_ctrl; void __iomem *clk_621; enum zynq_cpu_subclk_which which; @@ -273,16 +273,16 @@ struct zynq_cpu_subclk { #define CLK_621_TRUE(x) ((x) & 1) -#define to_zynq_cpu_subclk(c) container_of(c, struct zynq_cpu_subclk, c); +#define to_zynq_cpu_subclk(c) container_of(c, struct zynq_cpu_subclk, hw); -static unsigned long zynq_cpu_subclk_recalc_rate(struct clk *clk, +static unsigned long zynq_cpu_subclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { unsigned long uninitialized_var(rate); struct zynq_cpu_subclk *subclk; bool is_621; - subclk = to_zynq_cpu_subclk(clk); + subclk = to_zynq_cpu_subclk(hw); is_621 = CLK_621_TRUE(readl(subclk->clk_621)); switch (subclk->which) { @@ -303,12 +303,12 @@ static unsigned long zynq_cpu_subclk_recalc_rate(struct clk *clk, return rate; } -static int zynq_cpu_subclk_enable(struct clk *clk) +static int zynq_cpu_subclk_enable(struct clk_hw *hw) { struct zynq_cpu_subclk *subclk; u32 tmp; - subclk = to_zynq_cpu_subclk(clk); + subclk = to_zynq_cpu_subclk(hw); tmp = readl(subclk->clk_ctrl); tmp |= 1 << (24 + subclk->which); @@ -317,12 +317,12 @@ static int zynq_cpu_subclk_enable(struct clk *clk) return 0; } -static void zynq_cpu_subclk_disable(struct clk *clk) +static void zynq_cpu_subclk_disable(struct clk_hw *hw) { struct zynq_cpu_subclk *subclk; u32 tmp; - subclk = to_zynq_cpu_subclk(clk); + subclk = to_zynq_cpu_subclk(hw); tmp = readl(subclk->clk_ctrl); tmp &= ~(1 << (24 + subclk->which)); @@ -349,19 +349,19 @@ static struct clk *zynq_cpu_subclk(const char *name, subclk->clk_ctrl = clk_ctrl; subclk->clk_621 = clk_621; subclk->which = which; - subclk->clk.name = name; - subclk->clk.ops = &zynq_cpu_subclk_ops; + subclk->hw.clk.name = name; + subclk->hw.clk.ops = &zynq_cpu_subclk_ops; - subclk->clk.parent_names = &subclk_parent; - subclk->clk.num_parents = 1; + subclk->hw.clk.parent_names = &subclk_parent; + subclk->hw.clk.num_parents = 1; - ret = clk_register(&subclk->clk); + ret = bclk_register(&subclk->hw.clk); if (ret) { free(subclk); return ERR_PTR(ret); } - return &subclk->clk; + return &subclk->hw.clk; } static int zynq_clock_probe(struct device_d *dev) diff --git a/drivers/clk/zynqmp/clk-divider-zynqmp.c b/drivers/clk/zynqmp/clk-divider-zynqmp.c index 2fe65b566a..b96cab615b 100644 --- a/drivers/clk/zynqmp/clk-divider-zynqmp.c +++ b/drivers/clk/zynqmp/clk-divider-zynqmp.c @@ -16,14 +16,14 @@ #include "clk-zynqmp.h" struct zynqmp_clk_divider { - struct clk clk; + struct clk_hw hw; unsigned int clk_id; enum topology_type type; const char *parent; const struct zynqmp_eemi_ops *ops; }; -#define to_zynqmp_clk_divider(clk) \ - container_of(clk, struct zynqmp_clk_divider, clk) +#define to_zynqmp_clk_divider(_hw) \ + container_of(_hw, struct zynqmp_clk_divider, hw) static int zynqmp_clk_divider_bestdiv(unsigned long rate, unsigned long *best_parent_rate) @@ -31,10 +31,10 @@ static int zynqmp_clk_divider_bestdiv(unsigned long rate, return DIV_ROUND_CLOSEST(*best_parent_rate, rate); } -static unsigned long zynqmp_clk_divider_recalc_rate(struct clk *clk, +static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct zynqmp_clk_divider *div = to_zynqmp_clk_divider(clk); + struct zynqmp_clk_divider *div = to_zynqmp_clk_divider(hw); u32 value; div->ops->clock_getdivider(div->clk_id, &value); @@ -46,7 +46,7 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk *clk, return DIV_ROUND_UP(parent_rate, value); } -static long zynqmp_clk_divider_round_rate(struct clk *clk, unsigned long rate, +static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { int bestdiv; @@ -56,10 +56,10 @@ static long zynqmp_clk_divider_round_rate(struct clk *clk, unsigned long rate, return *parent_rate / bestdiv; } -static int zynqmp_clk_divider_set_rate(struct clk *clk, unsigned long rate, +static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct zynqmp_clk_divider *div = to_zynqmp_clk_divider(clk); + struct zynqmp_clk_divider *div = to_zynqmp_clk_divider(hw); u32 bestdiv; bestdiv = zynqmp_clk_divider_bestdiv(rate, &parent_rate); @@ -95,17 +95,17 @@ struct clk *zynqmp_clk_register_divider(const char *name, div->ops = zynqmp_pm_get_eemi_ops(); div->parent = strdup(parents[0]); - div->clk.name = strdup(name); - div->clk.ops = &zynqmp_clk_divider_ops; - div->clk.flags = nodes->flag; - div->clk.parent_names = &div->parent; - div->clk.num_parents = 1; + div->hw.clk.name = strdup(name); + div->hw.clk.ops = &zynqmp_clk_divider_ops; + div->hw.clk.flags = nodes->flag; + div->hw.clk.parent_names = &div->parent; + div->hw.clk.num_parents = 1; - ret = clk_register(&div->clk); + ret = bclk_register(&div->hw.clk); if (ret) { kfree(div); return ERR_PTR(ret); } - return &div->clk; + return &div->hw.clk; } diff --git a/drivers/clk/zynqmp/clk-gate-zynqmp.c b/drivers/clk/zynqmp/clk-gate-zynqmp.c index 6f03357768..a3b9ee21e5 100644 --- a/drivers/clk/zynqmp/clk-gate-zynqmp.c +++ b/drivers/clk/zynqmp/clk-gate-zynqmp.c @@ -16,31 +16,31 @@ #include "clk-zynqmp.h" struct zynqmp_clk_gate { - struct clk clk; + struct clk_hw hw; unsigned int clk_id; const char *parent; const struct zynqmp_eemi_ops *ops; }; -#define to_zynqmp_clk_gate(_hw) container_of(_hw, struct zynqmp_clk_gate, clk) +#define to_zynqmp_clk_gate(_hw) container_of(_hw, struct zynqmp_clk_gate, hw) -static int zynqmp_clk_gate_enable(struct clk *clk) +static int zynqmp_clk_gate_enable(struct clk_hw *hw) { - struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(clk); + struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); return gate->ops->clock_enable(gate->clk_id); } -static void zynqmp_clk_gate_disable(struct clk *clk) +static void zynqmp_clk_gate_disable(struct clk_hw *hw) { - struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(clk); + struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); gate->ops->clock_disable(gate->clk_id); } -static int zynqmp_clk_gate_is_enabled(struct clk *clk) +static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw) { - struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(clk); + struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); u32 state; int ret; const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); @@ -77,17 +77,17 @@ struct clk *zynqmp_clk_register_gate(const char *name, gate->ops = zynqmp_pm_get_eemi_ops(); gate->parent = strdup(parents[0]); - gate->clk.name = strdup(name); - gate->clk.ops = &zynqmp_clk_gate_ops; - gate->clk.flags = nodes->flag | CLK_SET_RATE_PARENT; - gate->clk.parent_names = &gate->parent; - gate->clk.num_parents = 1; + gate->hw.clk.name = strdup(name); + gate->hw.clk.ops = &zynqmp_clk_gate_ops; + gate->hw.clk.flags = nodes->flag | CLK_SET_RATE_PARENT; + gate->hw.clk.parent_names = &gate->parent; + gate->hw.clk.num_parents = 1; - ret = clk_register(&gate->clk); + ret = bclk_register(&gate->hw.clk); if (ret) { kfree(gate); return ERR_PTR(ret); } - return &gate->clk; + return &gate->hw.clk; } diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c index 4c15223980..e7264375f5 100644 --- a/drivers/clk/zynqmp/clk-mux-zynqmp.c +++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c @@ -18,17 +18,17 @@ #define ZYNQMP_CLK_MUX_READ_ONLY BIT(3) struct zynqmp_clk_mux { - struct clk clk; + struct clk_hw hw; u32 clk_id; const struct zynqmp_eemi_ops *ops; }; -#define to_zynqmp_clk_mux(clk) \ - container_of(clk, struct zynqmp_clk_mux, clk) +#define to_zynqmp_clk_mux(_hw) \ + container_of(_hw, struct zynqmp_clk_mux, hw) -static int zynqmp_clk_mux_get_parent(struct clk *clk) +static int zynqmp_clk_mux_get_parent(struct clk_hw *hw) { - struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(clk); + struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw); u32 value; mux->ops->clock_getparent(mux->clk_id, &value); @@ -36,9 +36,9 @@ static int zynqmp_clk_mux_get_parent(struct clk *clk) return value; } -static int zynqmp_clk_mux_set_parent(struct clk *clk, u8 index) +static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index) { - struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(clk); + struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw); return mux->ops->clock_setparent(mux->clk_id, index); } @@ -82,21 +82,21 @@ struct clk *zynqmp_clk_register_mux(const char *name, mux->clk_id = clk_id; mux->ops = zynqmp_pm_get_eemi_ops(); - mux->clk.name = strdup(name); + mux->hw.clk.name = strdup(name); if (nodes->type_flag & ZYNQMP_CLK_MUX_READ_ONLY) - mux->clk.ops = &zynqmp_clk_mux_ro_ops; + mux->hw.clk.ops = &zynqmp_clk_mux_ro_ops; else - mux->clk.ops = &zynqmp_clk_mux_ops; - mux->clk.flags = nodes->flag | CLK_SET_RATE_PARENT; - mux->clk.parent_names = parent_names; - mux->clk.num_parents = num_parents; + mux->hw.clk.ops = &zynqmp_clk_mux_ops; + mux->hw.clk.flags = nodes->flag | CLK_SET_RATE_PARENT; + mux->hw.clk.parent_names = parent_names; + mux->hw.clk.num_parents = num_parents; - ret = clk_register(&mux->clk); + ret = bclk_register(&mux->hw.clk); if (ret) { kfree(parent_names); kfree(mux); return ERR_PTR(ret); } - return &mux->clk; + return &mux->hw.clk; } diff --git a/drivers/clk/zynqmp/clk-pll-zynqmp.c b/drivers/clk/zynqmp/clk-pll-zynqmp.c index e4b759b73c..2e24d9d01c 100644 --- a/drivers/clk/zynqmp/clk-pll-zynqmp.c +++ b/drivers/clk/zynqmp/clk-pll-zynqmp.c @@ -16,14 +16,14 @@ #include "clk-zynqmp.h" struct zynqmp_pll { - struct clk clk; + struct clk_hw hw; unsigned int clk_id; const char *parent; const struct zynqmp_eemi_ops *ops; }; -#define to_zynqmp_pll(clk) \ - container_of(clk, struct zynqmp_pll, clk) +#define to_zynqmp_pll(_hw) \ + container_of(_hw, struct zynqmp_pll, hw) #define PLL_FBDIV_MIN 25 #define PLL_FBDIV_MAX 125 @@ -53,10 +53,10 @@ static inline void zynqmp_pll_set_mode(struct zynqmp_pll *pll, enum pll_mode mod pll->ops->ioctl(0, IOCTL_SET_PLL_FRAC_MODE, pll->clk_id, mode, NULL); } -static long zynqmp_pll_round_rate(struct clk *clk, unsigned long rate, +static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { - struct zynqmp_pll *pll = to_zynqmp_pll(clk); + struct zynqmp_pll *pll = to_zynqmp_pll(hw); u32 fbdiv; long rate_div; @@ -84,10 +84,10 @@ static long zynqmp_pll_round_rate(struct clk *clk, unsigned long rate, return rate; } -static unsigned long zynqmp_pll_recalc_rate(struct clk *clk, +static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct zynqmp_pll *pll = to_zynqmp_pll(clk); + struct zynqmp_pll *pll = to_zynqmp_pll(hw); u32 clk_id = pll->clk_id; u32 fbdiv, data; unsigned long rate, frac; @@ -109,10 +109,10 @@ static unsigned long zynqmp_pll_recalc_rate(struct clk *clk, return rate; } -static int zynqmp_pll_set_rate(struct clk *clk, unsigned long rate, +static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct zynqmp_pll *pll = to_zynqmp_pll(clk); + struct zynqmp_pll *pll = to_zynqmp_pll(hw); u32 clk_id = pll->clk_id; u32 fbdiv; long rate_div, frac, m, f; @@ -138,9 +138,9 @@ static int zynqmp_pll_set_rate(struct clk *clk, unsigned long rate, } } -static int zynqmp_pll_is_enabled(struct clk *clk) +static int zynqmp_pll_is_enabled(struct clk_hw *hw) { - struct zynqmp_pll *pll = to_zynqmp_pll(clk); + struct zynqmp_pll *pll = to_zynqmp_pll(hw); u32 is_enabled; int ret; @@ -151,21 +151,21 @@ static int zynqmp_pll_is_enabled(struct clk *clk) return !!(is_enabled); } -static int zynqmp_pll_enable(struct clk *clk) +static int zynqmp_pll_enable(struct clk_hw *hw) { - struct zynqmp_pll *pll = to_zynqmp_pll(clk); + struct zynqmp_pll *pll = to_zynqmp_pll(hw); - if (zynqmp_pll_is_enabled(clk)) + if (zynqmp_pll_is_enabled(hw)) return 0; return pll->ops->clock_enable(pll->clk_id); } -static void zynqmp_pll_disable(struct clk *clk) +static void zynqmp_pll_disable(struct clk_hw *hw) { - struct zynqmp_pll *pll = to_zynqmp_pll(clk); + struct zynqmp_pll *pll = to_zynqmp_pll(hw); - if (!zynqmp_pll_is_enabled(clk)) + if (!zynqmp_pll_is_enabled(hw)) return; pll->ops->clock_disable(pll->clk_id); @@ -197,17 +197,17 @@ struct clk *zynqmp_clk_register_pll(const char *name, pll->ops = zynqmp_pm_get_eemi_ops(); pll->parent = strdup(parents[0]); - pll->clk.name = strdup(name); - pll->clk.ops = &zynqmp_pll_ops; - pll->clk.flags = nodes->flag | CLK_SET_RATE_PARENT; - pll->clk.parent_names = &pll->parent; - pll->clk.num_parents = 1; + pll->hw.clk.name = strdup(name); + pll->hw.clk.ops = &zynqmp_pll_ops; + pll->hw.clk.flags = nodes->flag | CLK_SET_RATE_PARENT; + pll->hw.clk.parent_names = &pll->parent; + pll->hw.clk.num_parents = 1; - ret = clk_register(&pll->clk); + ret = bclk_register(&pll->hw.clk); if (ret) { kfree(pll); return ERR_PTR(ret); } - return &pll->clk; + return &pll->hw.clk; } diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c index 366a12e70a..86d85b6daa 100644 --- a/drivers/clk/zynqmp/clkc.c +++ b/drivers/clk/zynqmp/clkc.c @@ -453,7 +453,7 @@ static int zynqmp_register_clocks(struct device_d *dev, const char *parent_names[MAX_PARENT]; char *name; struct device_node *node = dev->device_node; - unsigned int num_parents; + int num_parents; for (i = 0; i < num_clocks; i++) { if (zynqmp_get_clock_type(i) != CLK_TYPE_OUTPUT) diff --git a/drivers/eeprom/at24.c b/drivers/eeprom/at24.c index 8c04c5684b..1d35088c6b 100644 --- a/drivers/eeprom/at24.c +++ b/drivers/eeprom/at24.c @@ -245,12 +245,9 @@ static ssize_t at24_read(struct at24_data *at24, return retval; } -static int at24_nvmem_read(struct device_d *dev, int off, - void *buf, int count) +static int at24_nvmem_read(void *ctx, unsigned off, void *buf, size_t count) { - struct at24_data *at24 = dev->parent->priv; - - return at24_read(at24, buf, off, count); + return at24_read(ctx, buf, off, count); } /* @@ -363,12 +360,9 @@ static ssize_t at24_write(struct at24_data *at24, const char *buf, loff_t off, return retval; } -static int at24_nvmem_write(struct device_d *dev, const int off, - const void *buf, int count) +static int at24_nvmem_write(void *ctx, unsigned off, const void *buf, size_t count) { - struct at24_data *at24 = dev->parent->priv; - - return at24_write(at24, buf, off, count); + return at24_write(ctx, buf, off, count); } static const struct nvmem_bus at24_nvmem_bus = { @@ -495,14 +489,13 @@ static int at24_probe(struct device_d *dev) at24->nvmem_config.name = devname; at24->nvmem_config.dev = dev; + at24->nvmem_config.priv = at24; at24->nvmem_config.read_only = !writable; at24->nvmem_config.bus = &at24_nvmem_bus; at24->nvmem_config.stride = 1; at24->nvmem_config.word_size = 1; at24->nvmem_config.size = chip.byte_len; - dev->priv = at24; - at24->nvmem = nvmem_register(&at24->nvmem_config); err = PTR_ERR_OR_ZERO(at24->nvmem); if (err) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index 20311d968b..b4f2176606 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -13,9 +13,6 @@ #include <io.h> #include <linux/err.h> -#define readl_relaxed readl -#define writel_relaxed writel - struct davinci_gpio_regs { u32 dir; u32 out_data; diff --git a/drivers/gpio/gpio-generic.c b/drivers/gpio/gpio-generic.c index 713085267a..3066b3f7a1 100644 --- a/drivers/gpio/gpio-generic.c +++ b/drivers/gpio/gpio-generic.c @@ -537,7 +537,7 @@ static int bgpio_dev_probe(struct device_d *dev) if (IS_ERR(pdata)) return PTR_ERR(pdata); - r = dev_request_mem_resource_by_name(dev, "dat"); + r = dev_get_resource_by_name(dev, IORESOURCE_MEM, "dat"); if (!r) return -EINVAL; diff --git a/drivers/mci/imx-esdhc-common.c b/drivers/mci/imx-esdhc-common.c index c9d589468f..7ee0674b99 100644 --- a/drivers/mci/imx-esdhc-common.c +++ b/drivers/mci/imx-esdhc-common.c @@ -156,7 +156,9 @@ static void __udelay(int us) #define udelay(n) __udelay(n) #undef dev_err +#undef dev_dbg #define dev_err(d, ...) pr_err(__VA_ARGS__) +#define dev_dbg(d, ...) pr_debug(__VA_ARGS__) #endif diff --git a/drivers/mfd/stpmic1.c b/drivers/mfd/stpmic1.c index d22758bd61..11154e742e 100644 --- a/drivers/mfd/stpmic1.c +++ b/drivers/mfd/stpmic1.c @@ -8,47 +8,10 @@ #include <errno.h> #include <i2c/i2c.h> #include <init.h> -#include <malloc.h> #include <of.h> #include <regmap.h> -#include <xfuncs.h> #include <linux/mfd/stpmic1.h> -struct stpmic1 { - struct device_d *dev; - struct i2c_client *client; -}; - -static int stpmic1_i2c_reg_read(void *ctx, unsigned int reg, unsigned int *val) -{ - struct stpmic1 *stpmic1 = ctx; - u8 buf[1]; - int ret; - - ret = i2c_read_reg(stpmic1->client, reg, buf, 1); - *val = buf[0]; - - return ret == 1 ? 0 : ret; -} - -static int stpmic1_i2c_reg_write(void *ctx, unsigned int reg, unsigned int val) -{ - struct stpmic1 *stpmic1 = ctx; - u8 buf[] = { - val & 0xff, - }; - int ret; - - ret = i2c_write_reg(stpmic1->client, reg, buf, 1); - - return ret == 1 ? 0 : ret; -} - -static struct regmap_bus regmap_stpmic1_i2c_bus = { - .reg_write = stpmic1_i2c_reg_write, - .reg_read = stpmic1_i2c_reg_read, -}; - static const struct regmap_config stpmic1_regmap_i2c_config = { .reg_bits = 8, .val_bits = 8, @@ -57,17 +20,13 @@ static const struct regmap_config stpmic1_regmap_i2c_config = { static int __init stpmic1_probe(struct device_d *dev) { - struct stpmic1 *stpmic1; struct regmap *regmap; u32 reg; int ret; - stpmic1 = xzalloc(sizeof(*stpmic1)); - stpmic1->dev = dev; - - stpmic1->client = to_i2c_client(dev); - regmap = regmap_init(dev, ®map_stpmic1_i2c_bus, - stpmic1, &stpmic1_regmap_i2c_config); + regmap = regmap_init_i2c(to_i2c_client(dev), &stpmic1_regmap_i2c_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); ret = regmap_register_cdev(regmap, NULL); if (ret) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 7c93260892..c69e5ce4e1 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -32,14 +32,27 @@ config NAND_ALLOW_ERASE_BAD config NAND_IMX bool - prompt "i.MX NAND driver" + prompt "i.MX21 to 53 NAND driver aka 'mxc', for NFC" depends on ARCH_IMX + help + Support for NAND flash on Freescale/NXP i.MX devices. This is for the + "MXC" series: i.MX21/25/27/31/35/51/53. + + This is not for the "MXS" series i.MX processors (23 & 28), or i.MX6 + and later, which use the GPMI NAND controller from the MXS series. + See the i.MX 'mxs' driver for those chips. config NAND_MXS bool select STMP_DEVICE - prompt "i.MX23/28/6 NAND driver" + prompt "i.MX23/28 & 6+ NAND driver aka 'mxs', for GPMI" depends on MXS_APBH_DMA + help + Support for NAND flash on Freescale/NXP i.MX devices. This is for the + "MXS" series: i.MX23/28 and all i.MX6 and later SoCs. + + This is not for the "MXC" series of i.MX processors in the i.MX21 to + i.MX53 range. See the i.MX "mxc" driver for those chips. config NAND_OMAP_GPMC tristate "NAND Flash Support for GPMC based OMAP platforms" diff --git a/drivers/mtd/nor/cfi_flash.c b/drivers/mtd/nor/cfi_flash.c index ba0bd1b4eb..ffd29d80a7 100644 --- a/drivers/mtd/nor/cfi_flash.c +++ b/drivers/mtd/nor/cfi_flash.c @@ -466,9 +466,16 @@ flash_sect_t find_sector(struct flash_info *info, unsigned long addr) { flash_sect_t sector; - for (sector = info->sector_count - 1; sector >= 0; sector--) { + sector = info->sector_count - 1; + + while (1) { if (addr >= info->start[sector]) break; + + if (sector == 0) + BUG(); + + sector--; } return sector; diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 14a0b45322..511846122a 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -52,6 +52,10 @@ #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE) #define GEM_Q1_DESC_BYTES (sizeof(struct macb_dma_desc) * GEM_Q1_DESCS) +struct macb_config { + int (*txclk_init)(struct device_d *dev, struct clk **tx_clk); +}; + struct macb_device { void __iomem *regs; @@ -666,12 +670,115 @@ static void macb_init_rx_buffer_size(struct macb_device *bp, size_t size) size, bp->rx_buffer_size); } +#ifdef CONFIG_COMMON_CLK +/* This structure is only used for MACB on SiFive FU540 devices */ +struct sifive_fu540_macb_mgmt { + void __iomem *reg; + unsigned long rate; + struct clk clk; +}; + +static struct sifive_fu540_macb_mgmt *mgmt; + +static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return mgmt->rate; +} + +static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + if (WARN_ON(rate < 2500000)) + return 2500000; + else if (rate == 2500000) + return 2500000; + else if (WARN_ON(rate < 13750000)) + return 2500000; + else if (WARN_ON(rate < 25000000)) + return 25000000; + else if (rate == 25000000) + return 25000000; + else if (WARN_ON(rate < 75000000)) + return 25000000; + else if (WARN_ON(rate < 125000000)) + return 125000000; + else if (rate == 125000000) + return 125000000; + + WARN_ON(rate > 125000000); + + return 125000000; +} + +static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate); + if (rate != 125000000) + iowrite32(1, mgmt->reg); + else + iowrite32(0, mgmt->reg); + mgmt->rate = rate; + + return 0; +} + +static const struct clk_ops fu540_c000_ops = { + .recalc_rate = fu540_macb_tx_recalc_rate, + .round_rate = fu540_macb_tx_round_rate, + .set_rate = fu540_macb_tx_set_rate, +}; + +static int fu540_c000_txclk_init(struct device_d *dev, struct clk **tx_clk) +{ + struct clk *clk; + struct resource *res; + int err = 0; + + mgmt = xzalloc(sizeof(*mgmt)); + + res = dev_request_mem_resource(dev, 1); + if (IS_ERR(res)) + return PTR_ERR(res); + + mgmt->reg = IOMEM(res->start); + + clk = &mgmt->clk; + + clk->name = "sifive-gemgxl-mgmt"; + clk->ops = &fu540_c000_ops; + + err = bclk_register(&mgmt->clk); + if (err) + return err; + + *tx_clk = &mgmt->clk; + + err = clk_enable(*tx_clk); + if (err) { + dev_err(dev, "failed to enable tx_clk (%u)\n", err); + *tx_clk = NULL; + return err; + } + + dev_info(dev, "Registered clk switch '%s'\n", clk->name); + return 0; +} +#else +static int fu540_c000_txclk_init(struct device_d *dev, struct clk **tx_clk) +{ + return -ENOSYS; +} +#endif + static int macb_probe(struct device_d *dev) { struct resource *iores; struct eth_device *edev; struct macb_device *macb; const char *pclk_name, *hclk_name; + const struct macb_config *config = NULL; u32 ncfgr; macb = xzalloc(sizeof(*macb)); @@ -725,6 +832,8 @@ static int macb_probe(struct device_d *dev) macb->phy_addr = -1; pclk_name = "pclk"; hclk_name = "hclk"; + + config = device_get_match_data(dev); } else { dev_err(dev, "macb: no platform_data\n"); return -ENODEV; @@ -767,6 +876,12 @@ static int macb_probe(struct device_d *dev) if (!IS_ERR(macb->rxclk)) clk_enable(macb->rxclk); + if (config) { + int ret = config->txclk_init(dev, &macb->txclk); + if (ret) + return ret; + } + macb->is_gem = read_is_gem(macb); if (macb_is_gem(macb)) @@ -808,12 +923,17 @@ static void macb_remove(struct device_d *dev) macb_halt(&macb->netdev); } +static const struct macb_config fu540_c000_config = { + .txclk_init = fu540_c000_txclk_init, +}; + static const struct of_device_id macb_dt_ids[] = { { .compatible = "cdns,at91sam9260-macb",}, { .compatible = "atmel,sama5d2-gem",}, { .compatible = "atmel,sama5d3-gem",}, { .compatible = "cdns,zynq-gem",}, { .compatible = "cdns,zynqmp-gem",}, + { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, { /* sentinel */ } }; diff --git a/drivers/net/phy/mv88e6xxx/chip.c b/drivers/net/phy/mv88e6xxx/chip.c index b1bffe5cbc..873c6f8463 100644 --- a/drivers/net/phy/mv88e6xxx/chip.c +++ b/drivers/net/phy/mv88e6xxx/chip.c @@ -779,10 +779,9 @@ static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) return 0; } -static int mv88e6xxx_eeprom_read(struct device_d *dev, const int offset, - void *val, int bytes) +static int mv88e6xxx_eeprom_read(void *ctx, unsigned offset, void *val, size_t bytes) { - struct mv88e6xxx_chip *chip = dev->parent->priv; + struct mv88e6xxx_chip *chip = ctx; struct ethtool_eeprom eeprom = { .offset = offset, .len = bytes, @@ -794,10 +793,9 @@ static int mv88e6xxx_eeprom_read(struct device_d *dev, const int offset, return chip->info->ops->get_eeprom(chip, &eeprom, val); } -static int mv88e6xxx_eeprom_write(struct device_d *dev, const int offset, - const void *val, int bytes) +static int mv88e6xxx_eeprom_write(void *ctx, unsigned offset, const void *val, size_t bytes) { - struct mv88e6xxx_chip *chip = dev->parent->priv; + struct mv88e6xxx_chip *chip = ctx; struct ethtool_eeprom eeprom = { .offset = offset, .len = bytes, @@ -883,6 +881,7 @@ static int mv88e6xxx_probe(struct device_d *dev) struct nvmem_config config = { .name = basprintf("%s-eeprom", dev_name(dev)), .dev = dev, + .priv = chip, .word_size = 1, .stride = 1, .size = eeprom_len, diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 7101c5aca4..617e3725a7 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -3,7 +3,7 @@ # obj-$(CONFIG_NVMEM) += nvmem_core.o -nvmem_core-y := core.o +nvmem_core-y := core.o regmap.o # Devices obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o diff --git a/drivers/nvmem/bsec.c b/drivers/nvmem/bsec.c index 836e62ecbc..509a5fa872 100644 --- a/drivers/nvmem/bsec.c +++ b/drivers/nvmem/bsec.c @@ -21,9 +21,7 @@ #define BSEC_OTP_SERIAL 13 struct bsec_priv { - struct regmap *map; u32 svc_id; - struct device_d dev; struct regmap_config map_config; struct nvmem_config config; }; @@ -72,61 +70,6 @@ static struct regmap_bus stm32_bsec_regmap_bus = { .reg_read = stm32_bsec_read_shadow, }; -static int stm32_bsec_write(struct device_d *dev, int offset, - const void *val, int bytes) -{ - struct bsec_priv *priv = dev->parent->priv; - - /* Allow only writing complete 32-bits aligned words */ - if ((bytes % 4) || (offset % 4)) - return -EINVAL; - - return regmap_bulk_write(priv->map, offset, val, bytes); -} - -static int stm32_bsec_read(struct device_d *dev, int offset, - void *buf, int bytes) -{ - struct bsec_priv *priv = dev->parent->priv; - u32 roffset, rbytes, val; - u8 *buf8 = buf, *val8 = (u8 *)&val; - int i, j = 0, ret, skip_bytes, size; - - /* Round unaligned access to 32-bits */ - roffset = rounddown(offset, 4); - skip_bytes = offset & 0x3; - rbytes = roundup(bytes + skip_bytes, 4); - - if (roffset + rbytes > priv->config.size) - return -EINVAL; - - for (i = roffset; i < roffset + rbytes; i += 4) { - ret = regmap_bulk_read(priv->map, i, &val, 4); - if (ret) { - dev_err(dev, "Can't read data%d (%d)\n", i, ret); - return ret; - } - - /* skip first bytes in case of unaligned read */ - if (skip_bytes) - size = min(bytes, 4 - skip_bytes); - else - size = min(bytes, 4); - - memcpy(&buf8[j], &val8[skip_bytes], size); - bytes -= size; - j += size; - skip_bytes = 0; - } - - return 0; -} - -static const struct nvmem_bus stm32_bsec_nvmem_bus = { - .write = stm32_bsec_write, - .read = stm32_bsec_read, -}; - static void stm32_bsec_set_unique_machine_id(struct regmap *map) { u32 unique_id[3]; @@ -153,9 +96,9 @@ static int stm32_bsec_read_mac(struct regmap *map, int offset, u8 *mac) return 0; } -static void stm32_bsec_init_dt(struct bsec_priv *priv) +static void stm32_bsec_init_dt(struct device_d *dev, struct regmap *map) { - struct device_node *node = priv->dev.parent->device_node; + struct device_node *node = dev->device_node; struct device_node *rnode; u32 phandle, offset; char mac[ETH_ALEN]; @@ -164,9 +107,6 @@ static void stm32_bsec_init_dt(struct bsec_priv *priv) int len; int ret; - if (!node) - return; - prop = of_get_property(node, "barebox,provide-mac-address", &len); if (!prop) return; @@ -179,10 +119,9 @@ static void stm32_bsec_init_dt(struct bsec_priv *priv) rnode = of_find_node_by_phandle(phandle); offset = be32_to_cpup(prop++); - ret = stm32_bsec_read_mac(priv->map, offset, mac); + ret = stm32_bsec_read_mac(map, offset, mac); if (ret) { - dev_warn(&priv->dev, "error setting MAC address: %s\n", - strerror(-ret)); + dev_warn(dev, "error setting MAC address: %s\n", strerror(-ret)); return; } @@ -191,6 +130,7 @@ static void stm32_bsec_init_dt(struct bsec_priv *priv) static int stm32_bsec_probe(struct device_d *dev) { + struct regmap *map; struct bsec_priv *priv; int ret = 0; const struct stm32_bsec_data *data; @@ -204,35 +144,23 @@ static int stm32_bsec_probe(struct device_d *dev) priv->svc_id = data->svc_id; - dev_set_name(&priv->dev, "bsec"); - priv->dev.parent = dev; - register_device(&priv->dev); - priv->map_config.reg_bits = 32; priv->map_config.val_bits = 32; priv->map_config.reg_stride = 4; priv->map_config.max_register = data->num_regs; - priv->map = regmap_init(dev, &stm32_bsec_regmap_bus, priv, &priv->map_config); - if (IS_ERR(priv->map)) - return PTR_ERR(priv->map); - - priv->config.name = "stm32-bsec"; - priv->config.dev = dev; - priv->config.stride = 1; - priv->config.word_size = 1; - priv->config.size = data->num_regs; - priv->config.bus = &stm32_bsec_nvmem_bus; - dev->priv = priv; + map = regmap_init(dev, &stm32_bsec_regmap_bus, priv, &priv->map_config); + if (IS_ERR(map)) + return PTR_ERR(map); - nvmem = nvmem_register(&priv->config); + nvmem = nvmem_regmap_register(map, "stm32-bsec"); if (IS_ERR(nvmem)) return PTR_ERR(nvmem); if (IS_ENABLED(CONFIG_MACHINE_ID)) - stm32_bsec_set_unique_machine_id(priv->map); + stm32_bsec_set_unique_machine_id(map); - stm32_bsec_init_dt(priv); + stm32_bsec_init_dt(dev, map); return 0; } diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index 2a1c4b6941..cfeecf70cd 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -33,6 +33,7 @@ struct nvmem_device { size_t size; bool read_only; struct cdev cdev; + void *priv; }; struct nvmem_cell { @@ -206,6 +207,7 @@ struct nvmem_device *nvmem_register(const struct nvmem_config *config) nvmem->bus = config->bus; np = config->dev->device_node; nvmem->dev.device_node = np; + nvmem->priv = config->priv; nvmem->read_only = of_property_read_bool(np, "read-only") | config->read_only; @@ -507,7 +509,7 @@ static int __nvmem_cell_read(struct nvmem_device *nvmem, { int rc; - rc = nvmem->bus->read(&nvmem->dev, cell->offset, buf, cell->bytes); + rc = nvmem->bus->read(nvmem->priv, cell->offset, buf, cell->bytes); if (IS_ERR_VALUE(rc)) return rc; @@ -572,7 +574,7 @@ static inline void *nvmem_cell_prepare_write_buffer(struct nvmem_cell *cell, *b <<= bit_offset; /* setup the first byte with lsb bits from nvmem */ - rc = nvmem->bus->read(&nvmem->dev, cell->offset, &v, 1); + rc = nvmem->bus->read(nvmem->priv, cell->offset, &v, 1); *b++ |= GENMASK(bit_offset - 1, 0) & v; /* setup rest of the byte if any */ @@ -589,7 +591,7 @@ static inline void *nvmem_cell_prepare_write_buffer(struct nvmem_cell *cell, /* if it's not end on byte boundary */ if ((nbits + bit_offset) % BITS_PER_BYTE) { /* setup the last byte with msb bits from nvmem */ - rc = nvmem->bus->read(&nvmem->dev, cell->offset + cell->bytes - 1, + rc = nvmem->bus->read(nvmem->priv, cell->offset + cell->bytes - 1, &v, 1); *p |= GENMASK(7, (nbits + bit_offset) % BITS_PER_BYTE) & v; @@ -622,7 +624,7 @@ int nvmem_cell_write(struct nvmem_cell *cell, void *buf, size_t len) return PTR_ERR(buf); } - rc = nvmem->bus->write(&nvmem->dev, cell->offset, buf, cell->bytes); + rc = nvmem->bus->write(nvmem->priv, cell->offset, buf, cell->bytes); /* free the tmp buffer */ if (cell->bit_offset || cell->nbits) @@ -719,7 +721,7 @@ int nvmem_device_read(struct nvmem_device *nvmem, if (!bytes) return 0; - rc = nvmem->bus->read(&nvmem->dev, offset, buf, bytes); + rc = nvmem->bus->read(nvmem->priv, offset, buf, bytes); if (IS_ERR_VALUE(rc)) return rc; @@ -753,7 +755,7 @@ int nvmem_device_write(struct nvmem_device *nvmem, if (!bytes) return 0; - rc = nvmem->bus->write(&nvmem->dev, offset, buf, bytes); + rc = nvmem->bus->write(nvmem->priv, offset, buf, bytes); if (IS_ERR_VALUE(rc)) return rc; diff --git a/drivers/nvmem/eeprom_93xx46.c b/drivers/nvmem/eeprom_93xx46.c index 49ed396dc2..5833cb0d86 100644 --- a/drivers/nvmem/eeprom_93xx46.c +++ b/drivers/nvmem/eeprom_93xx46.c @@ -79,10 +79,9 @@ static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev) return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH; } -static int eeprom_93xx46_read(struct device_d *dev, int off, - void *val, int count) +static int eeprom_93xx46_read(void *ctx, unsigned off, void *val, size_t count) { - struct eeprom_93xx46_dev *edev = dev->parent->priv; + struct eeprom_93xx46_dev *edev = ctx; char *buf = val; int err = 0; @@ -241,10 +240,9 @@ eeprom_93xx46_write_word(struct eeprom_93xx46_dev *edev, return ret; } -static int eeprom_93xx46_write(struct device_d *dev, const int off, - const void *val, int count) +static int eeprom_93xx46_write(void *ctx, unsigned off, const void *val, size_t count) { - struct eeprom_93xx46_dev *edev = dev->parent->priv; + struct eeprom_93xx46_dev *edev = ctx; const char *buf = val; int i, ret, step = 1; @@ -411,14 +409,13 @@ static int eeprom_93xx46_probe(struct device_d *dev) edev->size = 128; edev->nvmem_config.name = dev_name(&spi->dev); edev->nvmem_config.dev = &spi->dev; + edev->nvmem_config.priv = edev; edev->nvmem_config.read_only = pd->flags & EE_READONLY; edev->nvmem_config.bus = &eeprom_93xx46_nvmem_bus; edev->nvmem_config.stride = 4; edev->nvmem_config.word_size = 1; edev->nvmem_config.size = edev->size; - dev->priv = edev; - edev->nvmem = nvmem_register(&edev->nvmem_config); if (IS_ERR(edev->nvmem)) { err = PTR_ERR(edev->nvmem); diff --git a/drivers/nvmem/ocotp.c b/drivers/nvmem/ocotp.c index cee50955e9..b2fad3c687 100644 --- a/drivers/nvmem/ocotp.c +++ b/drivers/nvmem/ocotp.c @@ -673,18 +673,16 @@ static void imx_ocotp_init_dt(struct ocotp_priv *priv) } } -static int imx_ocotp_write(struct device_d *dev, const int offset, - const void *val, int bytes) +static int imx_ocotp_write(void *ctx, unsigned offset, const void *val, size_t bytes) { - struct ocotp_priv *priv = dev->parent->priv; + struct ocotp_priv *priv = ctx; return regmap_bulk_write(priv->map, offset, val, bytes); } -static int imx_ocotp_read(struct device_d *dev, const int offset, void *val, - int bytes) +static int imx_ocotp_read(void *ctx, unsigned offset, void *val, size_t bytes) { - struct ocotp_priv *priv = dev->parent->priv; + struct ocotp_priv *priv = ctx; return regmap_bulk_read(priv->map, offset, val, bytes); } @@ -746,11 +744,11 @@ static int imx_ocotp_probe(struct device_d *dev) priv->config.name = "imx-ocotp"; priv->config.dev = dev; + priv->config.priv = priv; priv->config.stride = 4; priv->config.word_size = 4; priv->config.size = data->num_regs; priv->config.bus = &imx_ocotp_nvmem_bus; - dev->priv = priv; nvmem = nvmem_register(&priv->config); if (IS_ERR(nvmem)) diff --git a/drivers/nvmem/rave-sp-eeprom.c b/drivers/nvmem/rave-sp-eeprom.c index 6c6ed17f18..f27491e547 100644 --- a/drivers/nvmem/rave-sp-eeprom.c +++ b/drivers/nvmem/rave-sp-eeprom.c @@ -280,19 +280,15 @@ static int rave_sp_eeprom_access(struct rave_sp_eeprom *eeprom, return 0; } -static int rave_sp_eeprom_read(struct device_d *dev, const int offset, - void *val, int bytes) +static int rave_sp_eeprom_read(void *ctx, unsigned offset, void *val, size_t bytes) { - return rave_sp_eeprom_access(dev->parent->priv, - RAVE_SP_EEPROM_READ, + return rave_sp_eeprom_access(ctx, RAVE_SP_EEPROM_READ, offset, val, bytes); } -static int rave_sp_eeprom_write(struct device_d *dev, const int offset, - const void *val, int bytes) +static int rave_sp_eeprom_write(void *ctx, unsigned offset, const void *val, size_t bytes) { - return rave_sp_eeprom_access(dev->parent->priv, - RAVE_SP_EEPROM_WRITE, + return rave_sp_eeprom_access(ctx, RAVE_SP_EEPROM_WRITE, offset, (void *)val, bytes); } @@ -329,8 +325,6 @@ static int rave_sp_eeprom_probe(struct device_d *dev) eeprom->address = reg[0]; eeprom->sp = sp; - dev->priv = eeprom; - if (size > SZ_8K) eeprom->header_size = RAVE_SP_EEPROM_HEADER_BIG; else @@ -343,6 +337,7 @@ static int rave_sp_eeprom_probe(struct device_d *dev) of_property_read_string(dev->device_node, "zii,eeprom-name", &config.name); config.dev = dev; + config.priv = eeprom; config.word_size = 1; config.stride = 1; config.size = reg[1]; diff --git a/drivers/nvmem/regmap.c b/drivers/nvmem/regmap.c new file mode 100644 index 0000000000..346d2516f3 --- /dev/null +++ b/drivers/nvmem/regmap.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <common.h> +#include <driver.h> +#include <malloc.h> +#include <xfuncs.h> +#include <errno.h> +#include <init.h> +#include <io.h> +#include <regmap.h> +#include <linux/nvmem-provider.h> + +static int nvmem_regmap_write(void *ctx, unsigned offset, const void *val, size_t bytes) +{ + return regmap_bulk_write(ctx, offset, val, bytes); +} + +static int nvmem_regmap_read(void *ctx, unsigned offset, void *buf, size_t bytes) +{ + struct regmap *map = ctx; + size_t rbytes, stride, skip_bytes; + u32 roffset, val; + u8 *buf8 = buf, *val8 = (u8 *)&val; + int i, j = 0, ret, size; + + stride = regmap_get_reg_stride(map); + + roffset = rounddown(offset, stride); + skip_bytes = offset & (stride - 1); + rbytes = roundup(bytes + skip_bytes, stride); + + if (roffset + rbytes > stride * regmap_get_max_register(map)) + return -EINVAL; + + for (i = roffset; i < roffset + rbytes; i += stride) { + ret = regmap_bulk_read(map, i, &val, stride); + if (ret) { + dev_err(regmap_get_device(map), "Can't read data%d (%d)\n", i, ret); + return ret; + } + + /* skip first bytes in case of unaligned read */ + if (skip_bytes) + size = min(bytes, stride - skip_bytes); + else + size = min(bytes, stride); + + memcpy(&buf8[j], &val8[skip_bytes], size); + bytes -= size; + j += size; + skip_bytes = 0; + } + + return 0; +} + +static struct nvmem_bus nvmem_regmap_bus = { + .read = nvmem_regmap_read, + .write = nvmem_regmap_write, +}; + +struct nvmem_device *nvmem_regmap_register(struct regmap *map, const char *name) +{ + struct nvmem_config config; + + /* Can be retrofitted if needed */ + if (regmap_get_reg_stride(map) != regmap_get_val_bytes(map)) + return ERR_PTR(-EINVAL); + + config.name = name; + config.dev = regmap_get_device(map); + config.priv = map; + config.stride = 1; + config.word_size = 1; + config.size = regmap_get_max_register(map) * regmap_get_reg_stride(map); + config.bus = &nvmem_regmap_bus; + + return nvmem_register(&config); +} diff --git a/drivers/nvmem/snvs_lpgpr.c b/drivers/nvmem/snvs_lpgpr.c index fe7fe599f6..1890af135d 100644 --- a/drivers/nvmem/snvs_lpgpr.c +++ b/drivers/nvmem/snvs_lpgpr.c @@ -42,10 +42,9 @@ static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx6q = { .offset_lplr = IMX6Q_SNVS_LPLR, }; -static int snvs_lpgpr_write(struct device_d *dev, const int offset, - const void *val, int bytes) +static int snvs_lpgpr_write(void *ctx, unsigned offset, const void *val, size_t bytes) { - struct snvs_lpgpr_priv *priv = dev->parent->priv; + struct snvs_lpgpr_priv *priv = ctx; const struct snvs_lpgpr_cfg *dcfg = priv->dcfg; unsigned int lock_reg; int ret; @@ -68,10 +67,9 @@ static int snvs_lpgpr_write(struct device_d *dev, const int offset, bytes); } -static int snvs_lpgpr_read(struct device_d *dev, const int offset, void *val, - int bytes) +static int snvs_lpgpr_read(void *ctx, unsigned offset, void *val, size_t bytes) { - struct snvs_lpgpr_priv *priv = dev->parent->priv; + struct snvs_lpgpr_priv *priv = ctx; const struct snvs_lpgpr_cfg *dcfg = priv->dcfg; return regmap_bulk_read(priv->regmap, dcfg->offset + offset, @@ -113,6 +111,7 @@ static int snvs_lpgpr_probe(struct device_d *dev) cfg = &priv->cfg; cfg->name = dev_name(dev); cfg->dev = dev; + cfg->priv = priv; cfg->stride = 4; cfg->word_size = 4; cfg->size = 4; @@ -124,8 +123,6 @@ static int snvs_lpgpr_probe(struct device_d *dev) return PTR_ERR(nvmem); } - dev->priv = priv; - return 0; } diff --git a/drivers/pci/pci-mvebu.c b/drivers/pci/pci-mvebu.c index ae2e83dacd..0c5e34116c 100644 --- a/drivers/pci/pci-mvebu.c +++ b/drivers/pci/pci-mvebu.c @@ -270,8 +270,8 @@ static struct mvebu_pcie *mvebu_pcie_port_probe(struct device_d *dev, enum of_gpio_flags flags; struct property *prop; const __be32 *p; - int reset_gpio; - u32 u, port, lane, lane_mask, devfn; + int reset_gpio, devfn; + u32 u, port, lane, lane_mask; int mem_target, mem_attr; int io_target, io_attr; int ret; diff --git a/drivers/regulator/stm32-vrefbuf.c b/drivers/regulator/stm32-vrefbuf.c index 3956b1f64f..77287c2b0e 100644 --- a/drivers/regulator/stm32-vrefbuf.c +++ b/drivers/regulator/stm32-vrefbuf.c @@ -10,6 +10,7 @@ #include <linux/clk.h> #include <linux/iopoll.h> #include <of.h> +#include <io.h> #include <regulator.h> /* STM32 VREFBUF registers */ @@ -23,9 +24,6 @@ #define STM32_VREFBUF_AUTO_SUSPEND_DELAY_MS 10 -#define readl_relaxed readl -#define writel_relaxed writel - struct stm32_vrefbuf { void __iomem *base; struct clk *clk; diff --git a/drivers/rtc/rtc-imxdi.c b/drivers/rtc/rtc-imxdi.c index 8fcaf631ff..82ed6d5007 100644 --- a/drivers/rtc/rtc-imxdi.c +++ b/drivers/rtc/rtc-imxdi.c @@ -511,10 +511,9 @@ static const struct rtc_class_ops dryice_rtc_ops = { .set_time = dryice_rtc_set_time, }; -static int nvstore_write(struct device_d *dev, const int reg, const void *val, - int bytes) +static int nvstore_write(void *ctx, unsigned reg, const void *val, size_t bytes) { - struct imxdi_dev *imxdi = dev->parent->priv; + struct imxdi_dev *imxdi = ctx; const u32 *val32 = val; if (bytes != 4) @@ -525,10 +524,9 @@ static int nvstore_write(struct device_d *dev, const int reg, const void *val, return 0; } -static int nvstore_read(struct device_d *dev, const int reg, void *val, - int bytes) +static int nvstore_read(void *ctx, unsigned reg, void *val, size_t bytes) { - struct imxdi_dev *imxdi = dev->parent->priv; + struct imxdi_dev *imxdi = ctx; u32 *val32 = val; if (bytes != 4) @@ -588,9 +586,8 @@ static int __init dryice_rtc_probe(struct device_d *dev) if (ret) goto err; - dev->priv = imxdi; - nvstore_nvmem_config.dev = dev; + nvstore_nvmem_config.priv = imxdi; imxdi->nvmem = nvmem_register(&nvstore_nvmem_config); if (IS_ENABLED(CONFIG_NVMEM) && IS_ERR(imxdi->nvmem)) { diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 6799f95ea3..af2191726f 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -34,9 +34,6 @@ #include <of_device.h> #include <linux/iopoll.h> -#define writel_relaxed writel -#define readl_relaxed readl - /* QSPI register offsets */ #define QSPI_CR 0x0000 /* Control Register */ #define QSPI_MR 0x0004 /* Mode Register */ diff --git a/drivers/video/imx-ipu-v3/ipu-di.c b/drivers/video/imx-ipu-v3/ipu-di.c index 97613207c9..85dde1882e 100644 --- a/drivers/video/imx-ipu-v3/ipu-di.c +++ b/drivers/video/imx-ipu-v3/ipu-di.c @@ -167,9 +167,10 @@ static int ipu_di_clk_calc_div(unsigned long inrate, unsigned long outrate) return div; } -static unsigned long clk_di_recalc_rate(struct clk *clk, +static unsigned long clk_di_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { + struct clk *clk = clk_hw_to_clk(hw); struct ipu_di *di = container_of(clk, struct ipu_di, clk_di_pixel); unsigned long outrate; u32 div = ipu_di_read(di, DI_BS_CLKGEN0); @@ -182,9 +183,10 @@ static unsigned long clk_di_recalc_rate(struct clk *clk, return outrate; } -static long clk_di_round_rate(struct clk *clk, unsigned long rate, +static long clk_di_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { + struct clk *clk = clk_hw_to_clk(hw); struct ipu_di *di = container_of(clk, struct ipu_di, clk_di_pixel); unsigned long outrate; int div; @@ -206,9 +208,10 @@ static long clk_di_round_rate(struct clk *clk, unsigned long rate, return outrate; } -static int clk_di_set_rate(struct clk *clk, unsigned long rate, +static int clk_di_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { + struct clk *clk = clk_hw_to_clk(hw); struct ipu_di *di = container_of(clk, struct ipu_di, clk_di_pixel); int div; u32 clkgen0; @@ -224,8 +227,9 @@ static int clk_di_set_rate(struct clk *clk, unsigned long rate, return 0; } -static int clk_di_get_parent(struct clk *clk) +static int clk_di_get_parent(struct clk_hw *hw) { + struct clk *clk = clk_hw_to_clk(hw); struct ipu_di *di = container_of(clk, struct ipu_di, clk_di_pixel); u32 val; @@ -234,8 +238,9 @@ static int clk_di_get_parent(struct clk *clk) return val & DI_GEN_DI_CLK_EXT ? 1 : 0; } -static int clk_di_set_parent(struct clk *clk, u8 index) +static int clk_di_set_parent(struct clk_hw *hw, u8 index) { + struct clk *clk = clk_hw_to_clk(hw); struct ipu_di *di = container_of(clk, struct ipu_di, clk_di_pixel); u32 val; @@ -740,7 +745,7 @@ int ipu_di_init(struct ipu_soc *ipu, struct device_d *dev, int id, di->clk_di_pixel.ops = &clk_di_ops; di->clk_di_pixel.num_parents = 2; di->clk_di_pixel.name = di->clk_name; - ret = clk_register(&di->clk_di_pixel); + ret = bclk_register(&di->clk_di_pixel); if (ret) goto failed_clk_register; diff --git a/dts/Bindings/clock/idt,versaclock5.yaml b/dts/Bindings/clock/idt,versaclock5.yaml index c268debe5b..28675b0b80 100644 --- a/dts/Bindings/clock/idt,versaclock5.yaml +++ b/dts/Bindings/clock/idt,versaclock5.yaml @@ -60,7 +60,6 @@ properties: maxItems: 2 idt,xtal-load-femtofarads: - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 9000 maximum: 22760 description: Optional load capacitor for XTAL1 and XTAL2 @@ -84,7 +83,6 @@ patternProperties: enum: [ 1800000, 2500000, 3300000 ] idt,slew-percent: description: The Slew rate control for CMOS single-ended. - $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 80, 85, 90, 100 ] required: diff --git a/dts/Bindings/i2c/i2c-mpc.yaml b/dts/Bindings/i2c/i2c-mpc.yaml index 7b553d559c..98c6fcf7bf 100644 --- a/dts/Bindings/i2c/i2c-mpc.yaml +++ b/dts/Bindings/i2c/i2c-mpc.yaml @@ -46,6 +46,13 @@ properties: description: | I2C bus timeout in microseconds + fsl,i2c-erratum-a004447: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Indicates the presence of QorIQ erratum A-004447, which + says that the standard i2c recovery scheme mechanism does + not work and an alternate implementation is needed. + required: - compatible - reg diff --git a/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml index 6f2398cdc8..1e7894e524 100644 --- a/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml +++ b/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -102,7 +102,6 @@ patternProperties: st,adc-channel-names: description: List of single-ended channel names. - $ref: /schemas/types.yaml#/definitions/string-array st,filter-order: description: | diff --git a/dts/Bindings/input/input.yaml b/dts/Bindings/input/input.yaml index 74244d21d2..d41d8743aa 100644 --- a/dts/Bindings/input/input.yaml +++ b/dts/Bindings/input/input.yaml @@ -38,6 +38,5 @@ properties: Duration in seconds which the key should be kept pressed for device to reset automatically. Device with key pressed reset feature can specify this property. - $ref: /schemas/types.yaml#/definitions/uint32 additionalProperties: true diff --git a/dts/Bindings/interconnect/qcom,rpmh.yaml b/dts/Bindings/interconnect/qcom,rpmh.yaml index cb6498108b..36c955965d 100644 --- a/dts/Bindings/interconnect/qcom,rpmh.yaml +++ b/dts/Bindings/interconnect/qcom,rpmh.yaml @@ -92,7 +92,6 @@ properties: this interconnect to send RPMh commands. qcom,bcm-voter-names: - $ref: /schemas/types.yaml#/definitions/string-array description: | Names for each of the qcom,bcm-voters specified. diff --git a/dts/Bindings/leds/leds-bcm6328.txt b/dts/Bindings/leds/leds-bcm6328.txt index ccebce597f..a555d94084 100644 --- a/dts/Bindings/leds/leds-bcm6328.txt +++ b/dts/Bindings/leds/leds-bcm6328.txt @@ -4,8 +4,8 @@ This controller is present on BCM6318, BCM6328, BCM6362 and BCM63268. In these SoCs it's possible to control LEDs both as GPIOs or by hardware. However, on some devices there are Serial LEDs (LEDs connected to a 74x164 controller), which can either be controlled by software (exporting the 74x164 -as spi-gpio. See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or -by hardware using this driver. +as spi-gpio. See Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml), +or by hardware using this driver. Some of these Serial LEDs are hardware controlled (e.g. ethernet LEDs) and exporting the 74x164 as spi-gpio prevents those LEDs to be hardware controlled, so the only chance to keep them working is by using this driver. diff --git a/dts/Bindings/leds/leds-bcm6358.txt b/dts/Bindings/leds/leds-bcm6358.txt index da5708e7b4..6e51c6b91e 100644 --- a/dts/Bindings/leds/leds-bcm6358.txt +++ b/dts/Bindings/leds/leds-bcm6358.txt @@ -3,7 +3,7 @@ LEDs connected to Broadcom BCM6358 controller This controller is present on BCM6358 and BCM6368. In these SoCs there are Serial LEDs (LEDs connected to a 74x164 controller), which can either be controlled by software (exporting the 74x164 as spi-gpio. -See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or +See Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml), or by hardware using this driver. Required properties: diff --git a/dts/Bindings/media/renesas,drif.yaml b/dts/Bindings/media/renesas,drif.yaml index f1bdaeab40..ce505a7c00 100644 --- a/dts/Bindings/media/renesas,drif.yaml +++ b/dts/Bindings/media/renesas,drif.yaml @@ -99,32 +99,26 @@ properties: Indicates that the channel acts as primary among the bonded channels. port: - type: object + $ref: /schemas/graph.yaml#/properties/port + unevaluatedProperties: false description: - Child port node corresponding to the data input, in accordance with the - video interface bindings defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - The port node must contain at least one endpoint. + Child port node corresponding to the data input. The port node must + contain at least one endpoint. properties: endpoint: - type: object + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false properties: - remote-endpoint: - description: - A phandle to the remote tuner endpoint subnode in remote node - port. - sync-active: + $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] description: Indicates sync signal polarity, 0/1 for low/high respectively. This property maps to SYNCAC bit in the hardware manual. The default is 1 (active high). - additionalProperties: false - required: - compatible - reg diff --git a/dts/Bindings/net/qcom,ipa.yaml b/dts/Bindings/net/qcom,ipa.yaml index 7443490d4c..5fe6d3dceb 100644 --- a/dts/Bindings/net/qcom,ipa.yaml +++ b/dts/Bindings/net/qcom,ipa.yaml @@ -105,7 +105,6 @@ properties: - description: Whether the IPA clock is enabled (if valid) qcom,smem-state-names: - $ref: /schemas/types.yaml#/definitions/string-array description: The names of the state bits used for SMP2P output items: - const: ipa-clock-enabled-valid diff --git a/dts/Bindings/net/renesas,ether.yaml b/dts/Bindings/net/renesas,ether.yaml index 8ce5ed8a58..c101a1ec84 100644 --- a/dts/Bindings/net/renesas,ether.yaml +++ b/dts/Bindings/net/renesas,ether.yaml @@ -10,7 +10,7 @@ allOf: - $ref: ethernet-controller.yaml# maintainers: - - Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> + - Sergei Shtylyov <sergei.shtylyov@gmail.com> properties: compatible: diff --git a/dts/Bindings/nvmem/mtk-efuse.txt b/dts/Bindings/nvmem/mtk-efuse.txt index d479ad977e..b6791702bc 100644 --- a/dts/Bindings/nvmem/mtk-efuse.txt +++ b/dts/Bindings/nvmem/mtk-efuse.txt @@ -9,7 +9,6 @@ Required properties: "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173 "mediatek,mt8192-efuse", "mediatek,efuse": for MT8192 "mediatek,mt8516-efuse", "mediatek,efuse": for MT8516 - "mediatek,mt8192-efuse", "mediatek,efuse": for MT8192 - reg: Should contain registers location and length = Data cells = diff --git a/dts/Bindings/phy/phy-cadence-torrent.yaml b/dts/Bindings/phy/phy-cadence-torrent.yaml index 01dcd14e7b..320a232c72 100644 --- a/dts/Bindings/phy/phy-cadence-torrent.yaml +++ b/dts/Bindings/phy/phy-cadence-torrent.yaml @@ -118,7 +118,7 @@ patternProperties: description: Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC, EXTERNAL_SSC or INTERNAL_SSC. - Refer include/dt-bindings/phy/phy-cadence-torrent.h for the constants to be used. + Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used. $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2] default: 0 diff --git a/dts/Bindings/power/supply/sc2731-charger.yaml b/dts/Bindings/power/supply/sc2731-charger.yaml index db1aa238cd..b62c2431f9 100644 --- a/dts/Bindings/power/supply/sc2731-charger.yaml +++ b/dts/Bindings/power/supply/sc2731-charger.yaml @@ -20,7 +20,7 @@ properties: maxItems: 1 phys: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 description: phandle to the USB phy monitored-battery: diff --git a/dts/Bindings/sound/fsl,rpmsg.yaml b/dts/Bindings/sound/fsl,rpmsg.yaml index b4c190bddd..61802a11ba 100644 --- a/dts/Bindings/sound/fsl,rpmsg.yaml +++ b/dts/Bindings/sound/fsl,rpmsg.yaml @@ -49,7 +49,7 @@ properties: maxItems: 1 memory-region: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 description: phandle to a node describing reserved memory (System RAM memory) The M core can't access all the DDR memory space on some platform, diff --git a/dts/Bindings/spi/spi-mux.yaml b/dts/Bindings/spi/spi-mux.yaml index d09c6355e2..51c7622dc2 100644 --- a/dts/Bindings/spi/spi-mux.yaml +++ b/dts/Bindings/spi/spi-mux.yaml @@ -72,7 +72,7 @@ examples: mux-controls = <&mux>; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; diff --git a/dts/include/dt-bindings/input/linux-event-codes.h b/dts/include/dt-bindings/input/linux-event-codes.h index ee93428ced..225ec87d4f 100644 --- a/dts/include/dt-bindings/input/linux-event-codes.h +++ b/dts/include/dt-bindings/input/linux-event-codes.h @@ -611,6 +611,7 @@ #define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ #define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */ #define KEY_KBD_LAYOUT_NEXT 0x248 /* AC Next Keyboard Layout Select */ +#define KEY_EMOJI_PICKER 0x249 /* Show/hide emoji picker (HUTRR101) */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ diff --git a/dts/src/arm/imx6dl-yapp4-common.dtsi b/dts/src/arm/imx6dl-yapp4-common.dtsi index 7d2c72562c..9148a01ed6 100644 --- a/dts/src/arm/imx6dl-yapp4-common.dtsi +++ b/dts/src/arm/imx6dl-yapp4-common.dtsi @@ -105,9 +105,13 @@ phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; phy-reset-duration = <20>; phy-supply = <&sw2_reg>; - phy-handle = <ðphy0>; status = "okay"; + fixed-link { + speed = <1000>; + full-duplex; + }; + mdio { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm/imx6q-dhcom-som.dtsi b/dts/src/arm/imx6q-dhcom-som.dtsi index 236fc205c3..d0768ae429 100644 --- a/dts/src/arm/imx6q-dhcom-som.dtsi +++ b/dts/src/arm/imx6q-dhcom-som.dtsi @@ -406,6 +406,18 @@ vin-supply = <&sw1_reg>; }; +®_pu { + vin-supply = <&sw1_reg>; +}; + +®_vdd1p1 { + vin-supply = <&sw2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&sw2_reg>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/dts/src/arm/imx6qdl-emcon-avari.dtsi b/dts/src/arm/imx6qdl-emcon-avari.dtsi index 828cf3e397..c4e146f334 100644 --- a/dts/src/arm/imx6qdl-emcon-avari.dtsi +++ b/dts/src/arm/imx6qdl-emcon-avari.dtsi @@ -126,7 +126,7 @@ compatible = "nxp,pca8574"; reg = <0x3a>; gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; }; }; diff --git a/dts/src/arm/imx7d-meerkat96.dts b/dts/src/arm/imx7d-meerkat96.dts index 5339210b63..dd8003bd1f 100644 --- a/dts/src/arm/imx7d-meerkat96.dts +++ b/dts/src/arm/imx7d-meerkat96.dts @@ -193,7 +193,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; keep-power-in-suspend; - tuning-step = <2>; + fsl,tuning-step = <2>; vmmc-supply = <®_3p3v>; no-1-8-v; broken-cd; diff --git a/dts/src/arm/imx7d-pico.dtsi b/dts/src/arm/imx7d-pico.dtsi index e57da0d32b..e519897fae 100644 --- a/dts/src/arm/imx7d-pico.dtsi +++ b/dts/src/arm/imx7d-pico.dtsi @@ -351,7 +351,7 @@ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; bus-width = <4>; - tuning-step = <2>; + fsl,tuning-step = <2>; vmmc-supply = <®_3p3v>; wakeup-source; no-1-8-v; diff --git a/dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var1.dts b/dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var1.dts index 6c309b9758..e8d31279b7 100644 --- a/dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var1.dts +++ b/dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var1.dts @@ -46,7 +46,8 @@ eee-broken-100tx; qca,clk-out-frequency = <125000000>; qca,clk-out-strength = <AR803X_STRENGTH_FULL>; - vddio-supply = <&vddh>; + qca,keep-pll-enabled; + vddio-supply = <&vddio>; vddio: vddio-regulator { regulator-name = "VDDIO"; diff --git a/dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var4.dts b/dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var4.dts index df212ed5bb..e65d1c477e 100644 --- a/dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var4.dts +++ b/dts/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var4.dts @@ -31,11 +31,10 @@ reg = <0x4>; eee-broken-1000t; eee-broken-100tx; - qca,clk-out-frequency = <125000000>; qca,clk-out-strength = <AR803X_STRENGTH_FULL>; - - vddio-supply = <&vddh>; + qca,keep-pll-enabled; + vddio-supply = <&vddio>; vddio: vddio-regulator { regulator-name = "VDDIO"; diff --git a/dts/src/arm64/freescale/fsl-ls1028a.dtsi b/dts/src/arm64/freescale/fsl-ls1028a.dtsi index eca06a0c3c..a30249ebff 100644 --- a/dts/src/arm64/freescale/fsl-ls1028a.dtsi +++ b/dts/src/arm64/freescale/fsl-ls1028a.dtsi @@ -197,8 +197,8 @@ ddr: memory-controller@1080000 { compatible = "fsl,qoriq-memory-controller"; reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - big-endian; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + little-endian; }; dcfg: syscon@1e00000 { diff --git a/dts/src/arm64/freescale/imx8mq-zii-ultra-rmb3.dts b/dts/src/arm64/freescale/imx8mq-zii-ultra-rmb3.dts index 631e01c1b9..be1e7d6f0e 100644 --- a/dts/src/arm64/freescale/imx8mq-zii-ultra-rmb3.dts +++ b/dts/src/arm64/freescale/imx8mq-zii-ultra-rmb3.dts @@ -88,11 +88,11 @@ pinctrl-0 = <&pinctrl_codec2>; reg = <0x18>; #sound-dai-cells = <0>; - HPVDD-supply = <®_3p3v>; - SPRVDD-supply = <®_3p3v>; - SPLVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; + HPVDD-supply = <®_gen_3p3>; + SPRVDD-supply = <®_gen_3p3>; + SPLVDD-supply = <®_gen_3p3>; + AVDD-supply = <®_gen_3p3>; + IOVDD-supply = <®_gen_3p3>; DVDD-supply = <&vgen4_reg>; reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; }; diff --git a/dts/src/arm64/freescale/imx8mq-zii-ultra.dtsi b/dts/src/arm64/freescale/imx8mq-zii-ultra.dtsi index 4dc8383478..a08a568c31 100644 --- a/dts/src/arm64/freescale/imx8mq-zii-ultra.dtsi +++ b/dts/src/arm64/freescale/imx8mq-zii-ultra.dtsi @@ -45,8 +45,8 @@ reg_12p0_main: regulator-12p0-main { compatible = "regulator-fixed"; regulator-name = "12V_MAIN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; regulator-always-on; }; @@ -77,15 +77,6 @@ regulator-always-on; }; - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - vin-supply = <®_3p3_main>; - regulator-name = "GEN_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - reg_usdhc2_vmmc: regulator-vsd-3v3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usdhc2>; @@ -415,11 +406,11 @@ pinctrl-0 = <&pinctrl_codec1>; reg = <0x18>; #sound-dai-cells = <0>; - HPVDD-supply = <®_3p3v>; - SPRVDD-supply = <®_3p3v>; - SPLVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - IOVDD-supply = <®_3p3v>; + HPVDD-supply = <®_gen_3p3>; + SPRVDD-supply = <®_gen_3p3>; + SPLVDD-supply = <®_gen_3p3>; + AVDD-supply = <®_gen_3p3>; + IOVDD-supply = <®_gen_3p3>; DVDD-supply = <&vgen4_reg>; reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; }; diff --git a/dts/src/arm64/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi b/dts/src/arm64/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi index c62ddb9b2b..3771144a2c 100644 --- a/dts/src/arm64/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi +++ b/dts/src/arm64/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi @@ -14,7 +14,6 @@ ports { port@0 { - reg = <0>; csi20_in: endpoint { clock-lanes = <0>; data-lanes = <1 2>; @@ -29,7 +28,6 @@ ports { port@0 { - reg = <0>; csi40_in: endpoint { clock-lanes = <0>; data-lanes = <1 2>; diff --git a/dts/src/arm64/renesas/r8a774a1.dtsi b/dts/src/arm64/renesas/r8a774a1.dtsi index d64fb8b1b8..46f8dbf689 100644 --- a/dts/src/arm64/renesas/r8a774a1.dtsi +++ b/dts/src/arm64/renesas/r8a774a1.dtsi @@ -2573,6 +2573,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; @@ -2628,6 +2632,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/renesas/r8a774b1.dtsi b/dts/src/arm64/renesas/r8a774b1.dtsi index 5b05474dc2..d16a4be5ef 100644 --- a/dts/src/arm64/renesas/r8a774b1.dtsi +++ b/dts/src/arm64/renesas/r8a774b1.dtsi @@ -2419,6 +2419,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; @@ -2474,6 +2478,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/renesas/r8a774c0-ek874-mipi-2.1.dts b/dts/src/arm64/renesas/r8a774c0-ek874-mipi-2.1.dts index e7b4a929bb..2e3d1981ca 100644 --- a/dts/src/arm64/renesas/r8a774c0-ek874-mipi-2.1.dts +++ b/dts/src/arm64/renesas/r8a774c0-ek874-mipi-2.1.dts @@ -33,7 +33,7 @@ status = "okay"; ports { - port { + port@0 { csi40_in: endpoint { clock-lanes = <0>; data-lanes = <1 2>; diff --git a/dts/src/arm64/renesas/r8a774c0.dtsi b/dts/src/arm64/renesas/r8a774c0.dtsi index 20fa3caa05..1aef34447a 100644 --- a/dts/src/arm64/renesas/r8a774c0.dtsi +++ b/dts/src/arm64/renesas/r8a774c0.dtsi @@ -1823,6 +1823,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/renesas/r8a774e1.dtsi b/dts/src/arm64/renesas/r8a774e1.dtsi index 8eb006cbd9..1f51237ab0 100644 --- a/dts/src/arm64/renesas/r8a774e1.dtsi +++ b/dts/src/arm64/renesas/r8a774e1.dtsi @@ -2709,6 +2709,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; @@ -2764,6 +2768,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/renesas/r8a77950.dtsi b/dts/src/arm64/renesas/r8a77950.dtsi index 25b87da32e..b643d3079d 100644 --- a/dts/src/arm64/renesas/r8a77950.dtsi +++ b/dts/src/arm64/renesas/r8a77950.dtsi @@ -192,6 +192,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/renesas/r8a77951.dtsi b/dts/src/arm64/renesas/r8a77951.dtsi index 5c39152e45..85d66d1546 100644 --- a/dts/src/arm64/renesas/r8a77951.dtsi +++ b/dts/src/arm64/renesas/r8a77951.dtsi @@ -3097,6 +3097,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; @@ -3152,6 +3156,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; @@ -3191,6 +3199,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/renesas/r8a77960.dtsi b/dts/src/arm64/renesas/r8a77960.dtsi index 25d947a81b..12476e354d 100644 --- a/dts/src/arm64/renesas/r8a77960.dtsi +++ b/dts/src/arm64/renesas/r8a77960.dtsi @@ -2761,6 +2761,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; @@ -2816,6 +2820,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/renesas/r8a77961.dtsi b/dts/src/arm64/renesas/r8a77961.dtsi index ab081f14af..d980476842 100644 --- a/dts/src/arm64/renesas/r8a77961.dtsi +++ b/dts/src/arm64/renesas/r8a77961.dtsi @@ -2499,6 +2499,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; @@ -2554,6 +2558,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/renesas/r8a77965.dtsi b/dts/src/arm64/renesas/r8a77965.dtsi index 657b20d353..dcb9df861d 100644 --- a/dts/src/arm64/renesas/r8a77965.dtsi +++ b/dts/src/arm64/renesas/r8a77965.dtsi @@ -2575,6 +2575,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; @@ -2630,6 +2634,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/renesas/r8a77970.dtsi b/dts/src/arm64/renesas/r8a77970.dtsi index 5a5d564933..e8f6352c36 100644 --- a/dts/src/arm64/renesas/r8a77970.dtsi +++ b/dts/src/arm64/renesas/r8a77970.dtsi @@ -1106,6 +1106,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/renesas/r8a77980.dtsi b/dts/src/arm64/renesas/r8a77980.dtsi index 1ffa4a995a..7b51d464de 100644 --- a/dts/src/arm64/renesas/r8a77980.dtsi +++ b/dts/src/arm64/renesas/r8a77980.dtsi @@ -1439,6 +1439,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; @@ -1478,6 +1482,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/renesas/r8a77990-ebisu.dts b/dts/src/arm64/renesas/r8a77990-ebisu.dts index 295d34f1d2..4715e4a4ab 100644 --- a/dts/src/arm64/renesas/r8a77990-ebisu.dts +++ b/dts/src/arm64/renesas/r8a77990-ebisu.dts @@ -298,8 +298,6 @@ ports { port@0 { - reg = <0>; - csi40_in: endpoint { clock-lanes = <0>; data-lanes = <1 2>; diff --git a/dts/src/arm64/renesas/r8a77990.dtsi b/dts/src/arm64/renesas/r8a77990.dtsi index 5010f23faf..0eaea58f42 100644 --- a/dts/src/arm64/renesas/r8a77990.dtsi +++ b/dts/src/arm64/renesas/r8a77990.dtsi @@ -1970,6 +1970,10 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/renesas/salvator-common.dtsi b/dts/src/arm64/renesas/salvator-common.dtsi index e18747df21..453ffcef24 100644 --- a/dts/src/arm64/renesas/salvator-common.dtsi +++ b/dts/src/arm64/renesas/salvator-common.dtsi @@ -349,7 +349,6 @@ ports { port@0 { - reg = <0>; csi20_in: endpoint { clock-lanes = <0>; data-lanes = <1>; @@ -364,8 +363,6 @@ ports { port@0 { - reg = <0>; - csi40_in: endpoint { clock-lanes = <0>; data-lanes = <1 2 3 4>; diff --git a/dts/src/arm64/ti/k3-am64-main.dtsi b/dts/src/arm64/ti/k3-am64-main.dtsi index b2bcbf23ee..ca59d1f711 100644 --- a/dts/src/arm64/ti/k3-am64-main.dtsi +++ b/dts/src/arm64/ti/k3-am64-main.dtsi @@ -42,12 +42,12 @@ }; }; - dmss: dmss { + dmss: bus@48000000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; dma-ranges; - ranges; + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; ti,sci-dev-id = <25>; @@ -134,7 +134,7 @@ }; }; - dmsc: dmsc@44043000 { + dmsc: system-controller@44043000 { compatible = "ti,k2g-sci"; ti,host-id = <12>; mbox-names = "rx", "tx"; @@ -148,7 +148,7 @@ #power-domain-cells = <2>; }; - k3_clks: clocks { + k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; @@ -373,8 +373,9 @@ clocks = <&k3_clks 145 0>; }; - main_gpio_intr: interrupt-controller0 { + main_gpio_intr: interrupt-controller@a00000 { compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; diff --git a/dts/src/arm64/ti/k3-am64-mcu.dtsi b/dts/src/arm64/ti/k3-am64-mcu.dtsi index 99e94dee1b..deb19ae5e1 100644 --- a/dts/src/arm64/ti/k3-am64-mcu.dtsi +++ b/dts/src/arm64/ti/k3-am64-mcu.dtsi @@ -74,8 +74,9 @@ clocks = <&k3_clks 148 0>; }; - mcu_gpio_intr: interrupt-controller1 { + mcu_gpio_intr: interrupt-controller@4210000 { compatible = "ti,sci-intr"; + reg = <0x00 0x04210000 0x00 0x200>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; diff --git a/dts/src/arm64/ti/k3-am65-main.dtsi b/dts/src/arm64/ti/k3-am65-main.dtsi index cb340d1b40..6cd3131eb9 100644 --- a/dts/src/arm64/ti/k3-am65-main.dtsi +++ b/dts/src/arm64/ti/k3-am65-main.dtsi @@ -433,8 +433,9 @@ #phy-cells = <0>; }; - intr_main_gpio: interrupt-controller0 { + intr_main_gpio: interrupt-controller@a00000 { compatible = "ti,sci-intr"; + reg = <0x0 0x00a00000 0x0 0x400>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; @@ -444,18 +445,19 @@ ti,interrupt-ranges = <0 392 32>; }; - main-navss { + main_navss: bus@30800000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>; dma-coherent; dma-ranges; ti,sci-dev-id = <118>; - intr_main_navss: interrupt-controller1 { + intr_main_navss: interrupt-controller@310e0000 { compatible = "ti,sci-intr"; + reg = <0x0 0x310e0000 0x0 0x2000>; ti,intr-trigger-type = <4>; interrupt-controller; interrupt-parent = <&gic500>; diff --git a/dts/src/arm64/ti/k3-am65-mcu.dtsi b/dts/src/arm64/ti/k3-am65-mcu.dtsi index 0388c02c22..f5b8ef2f5f 100644 --- a/dts/src/arm64/ti/k3-am65-mcu.dtsi +++ b/dts/src/arm64/ti/k3-am65-mcu.dtsi @@ -116,11 +116,11 @@ }; }; - mcu-navss { + mcu_navss: bus@28380000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; dma-coherent; dma-ranges; diff --git a/dts/src/arm64/ti/k3-am65-wakeup.dtsi b/dts/src/arm64/ti/k3-am65-wakeup.dtsi index ed42f13e76..7cb864b4d7 100644 --- a/dts/src/arm64/ti/k3-am65-wakeup.dtsi +++ b/dts/src/arm64/ti/k3-am65-wakeup.dtsi @@ -6,24 +6,24 @@ */ &cbass_wakeup { - dmsc: dmsc { + dmsc: system-controller@44083000 { compatible = "ti,am654-sci"; ti,host-id = <12>; - #address-cells = <1>; - #size-cells = <1>; - ranges; mbox-names = "rx", "tx"; mboxes= <&secure_proxy_main 11>, <&secure_proxy_main 13>; + reg-names = "debug_messages"; + reg = <0x44083000 0x1000>; + k3_pds: power-controller { compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; }; - k3_clks: clocks { + k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; @@ -69,8 +69,9 @@ power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; }; - intr_wkup_gpio: interrupt-controller2 { + intr_wkup_gpio: interrupt-controller@42200000 { compatible = "ti,sci-intr"; + reg = <0x42200000 0x200>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; diff --git a/dts/src/arm64/ti/k3-am654-base-board.dts b/dts/src/arm64/ti/k3-am654-base-board.dts index 9e87fb313a..eddb2ffb93 100644 --- a/dts/src/arm64/ti/k3-am654-base-board.dts +++ b/dts/src/arm64/ti/k3-am654-base-board.dts @@ -85,12 +85,6 @@ gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>; }; }; - - clk_ov5640_fixed: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; }; &wkup_pmx0 { @@ -287,23 +281,6 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - - clocks = <&clk_ov5640_fixed>; - clock-names = "xclk"; - - port { - csi2_cam0: endpoint { - remote-endpoint = <&csi2_phy0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - }; &main_i2c2 { @@ -496,14 +473,6 @@ }; }; -&csi2_0 { - csi2_phy0: endpoint { - remote-endpoint = <&csi2_cam0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; -}; - &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; diff --git a/dts/src/arm64/ti/k3-j7200-main.dtsi b/dts/src/arm64/ti/k3-j7200-main.dtsi index f86c493a44..19fea8adbc 100644 --- a/dts/src/arm64/ti/k3-j7200-main.dtsi +++ b/dts/src/arm64/ti/k3-j7200-main.dtsi @@ -68,8 +68,9 @@ }; }; - main_gpio_intr: interrupt-controller0 { + main_gpio_intr: interrupt-controller@a00000 { compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; @@ -85,9 +86,12 @@ #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; ti,sci-dev-id = <199>; + dma-coherent; + dma-ranges; - main_navss_intr: interrupt-controller1 { + main_navss_intr: interrupt-controller@310e0000 { compatible = "ti,sci-intr"; + reg = <0x00 0x310e0000 0x00 0x4000>; ti,intr-trigger-type = <4>; interrupt-controller; interrupt-parent = <&gic500>; diff --git a/dts/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi b/dts/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi index 5e74e43822..5663fe3ea4 100644 --- a/dts/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi +++ b/dts/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi @@ -6,7 +6,7 @@ */ &cbass_mcu_wakeup { - dmsc: dmsc@44083000 { + dmsc: system-controller@44083000 { compatible = "ti,k2g-sci"; ti,host-id = <12>; @@ -23,7 +23,7 @@ #power-domain-cells = <2>; }; - k3_clks: clocks { + k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; @@ -96,8 +96,9 @@ clock-names = "fclk"; }; - wkup_gpio_intr: interrupt-controller2 { + wkup_gpio_intr: interrupt-controller@42200000 { compatible = "ti,sci-intr"; + reg = <0x00 0x42200000 0x00 0x400>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; diff --git a/dts/src/arm64/ti/k3-j721e-main.dtsi b/dts/src/arm64/ti/k3-j721e-main.dtsi index c2aa45a3ac..3bcafe4c17 100644 --- a/dts/src/arm64/ti/k3-j721e-main.dtsi +++ b/dts/src/arm64/ti/k3-j721e-main.dtsi @@ -76,8 +76,9 @@ }; }; - main_gpio_intr: interrupt-controller0 { + main_gpio_intr: interrupt-controller@a00000 { compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; @@ -87,18 +88,19 @@ ti,interrupt-ranges = <8 392 56>; }; - main-navss { + main_navss: bus@30000000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; dma-coherent; dma-ranges; ti,sci-dev-id = <199>; - main_navss_intr: interrupt-controller1 { + main_navss_intr: interrupt-controller@310e0000 { compatible = "ti,sci-intr"; + reg = <0x0 0x310e0000 0x0 0x4000>; ti,intr-trigger-type = <4>; interrupt-controller; interrupt-parent = <&gic500>; diff --git a/dts/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi b/dts/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi index d56e3475ae..5e825e4d03 100644 --- a/dts/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi +++ b/dts/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi @@ -6,7 +6,7 @@ */ &cbass_mcu_wakeup { - dmsc: dmsc@44083000 { + dmsc: system-controller@44083000 { compatible = "ti,k2g-sci"; ti,host-id = <12>; @@ -23,7 +23,7 @@ #power-domain-cells = <2>; }; - k3_clks: clocks { + k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; @@ -96,8 +96,9 @@ clock-names = "fclk"; }; - wkup_gpio_intr: interrupt-controller2 { + wkup_gpio_intr: interrupt-controller@42200000 { compatible = "ti,sci-intr"; + reg = <0x00 0x42200000 0x00 0x400>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; @@ -249,11 +250,11 @@ }; }; - mcu-navss { + mcu_navss: bus@28380000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; dma-coherent; dma-ranges; diff --git a/dts/src/powerpc/fsl/p1010si-post.dtsi b/dts/src/powerpc/fsl/p1010si-post.dtsi index c2717f3192..ccda0a91ab 100644 --- a/dts/src/powerpc/fsl/p1010si-post.dtsi +++ b/dts/src/powerpc/fsl/p1010si-post.dtsi @@ -122,7 +122,15 @@ }; /include/ "pq3-i2c-0.dtsi" + i2c@3000 { + fsl,i2c-erratum-a004447; + }; + /include/ "pq3-i2c-1.dtsi" + i2c@3100 { + fsl,i2c-erratum-a004447; + }; + /include/ "pq3-duart-0.dtsi" /include/ "pq3-espi-0.dtsi" spi0: spi@7000 { diff --git a/dts/src/powerpc/fsl/p2041si-post.dtsi b/dts/src/powerpc/fsl/p2041si-post.dtsi index 872e4485dc..ddc018d422 100644 --- a/dts/src/powerpc/fsl/p2041si-post.dtsi +++ b/dts/src/powerpc/fsl/p2041si-post.dtsi @@ -371,7 +371,23 @@ }; /include/ "qoriq-i2c-0.dtsi" + i2c@118000 { + fsl,i2c-erratum-a004447; + }; + + i2c@118100 { + fsl,i2c-erratum-a004447; + }; + /include/ "qoriq-i2c-1.dtsi" + i2c@119000 { + fsl,i2c-erratum-a004447; + }; + + i2c@119100 { + fsl,i2c-erratum-a004447; + }; + /include/ "qoriq-duart-0.dtsi" /include/ "qoriq-duart-1.dtsi" /include/ "qoriq-gpio-0.dtsi" diff --git a/firmware/Makefile b/firmware/Makefile index cc28c0fc39..3a38c40079 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -1,7 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -# -# kbuild file for firmware/ -# firmware-$(CONFIG_FIRMWARE_IMX_LPDDR4_PMU_TRAIN) += \ lpddr4_pmu_train_1d_dmem.bin \ @@ -19,52 +16,39 @@ firmware-$(CONFIG_ARCH_LAYERSCAPE_PPA) += ppa-ls1046a.bin firmware-$(CONFIG_FIRMWARE_CCBV2_OPTEE) += ccbv2_optee.bin -# Create $(fwabs) from $(CONFIG_EXTRA_FIRMWARE_DIR) -- if it doesn't have a +# Create $(fwdir) from $(CONFIG_EXTRA_FIRMWARE_DIR) -- if it doesn't have a # leading /, it's relative to $(srctree). fwdir := $(subst $(quote),,$(CONFIG_EXTRA_FIRMWARE_DIR)) -fwabs := $(addprefix $(srctree)/,$(filter-out /%,$(fwdir)))$(filter /%,$(fwdir)) +fwdir := $(addprefix $(srctree)/,$(filter-out /%,$(fwdir)))$(filter /%,$(fwdir)) -fw-external-y := $(firmware-y) +obj-pbl-y := $(addsuffix .gen.o, $(firmware-y)) -quiet_cmd_fwbin = MK_FW $@ - cmd_fwbin = FWNAME="$(patsubst firmware/%.gen.S,%,$@)"; \ - FWSTR="$(subst /,_,$(subst .,_,$(subst -,_,$(patsubst \ - firmware/%.gen.S,%,$@))))"; \ - ASM_WORD=$(if $(CONFIG_64BIT),.quad,.long); \ - ASM_ALIGN=$(if $(CONFIG_64BIT),3,2); \ - PROGBITS=$(if $(CONFIG_ARM),%,@)progbits; \ - echo "/* Generated by firmware/Makefile */" > $@;\ - echo " .section .rodata.$${FWSTR}" >>$@;\ - echo " .p2align $${ASM_ALIGN}" >>$@;\ - echo ".global _fw_$${FWSTR}_start" >>$@;\ - echo "_fw_$${FWSTR}_start:" >>$@;\ - echo " .incbin \"$(2)\"" >>$@;\ - echo ".global _fw_$${FWSTR}_end" >>$@;\ - echo "_fw_$${FWSTR}_end:" >>$@; +FWNAME = $(patsubst $(obj)/%.gen.S,%,$@) +FWSTR = $(subst /,_,$(subst .,_,$(subst -,_,$(FWNAME)))) +ASM_ALIGN = $(if $(CONFIG_64BIT),3,2) -# One of these files will change, or come into existence, whenever -# the configuration changes between 32-bit and 64-bit. The .S files -# need to change when that happens. -wordsize_deps := $(wildcard include/config/64bit.h include/config/32bit.h) +filechk_fwbin = { \ + echo "/* Generated by $(src)/Makefile */" ;\ + echo " .section .rodata.$(FWSTR)" ;\ + echo " .p2align $(ASM_ALIGN)" ;\ + echo ".global _fw_$(FWSTR)_start" ;\ + echo "_fw_$(FWSTR)_start:" ;\ + echo " .incbin \"$(fwdir)/$(FWNAME)\"" ;\ + echo ".global _fw_$(FWSTR)_end" ;\ + echo "_fw_$(FWSTR)_end:" ;\ +} -$(patsubst %,$(obj)/%.gen.S, $(fw-external-y)): %: $(wordsize_deps) \ - include/config/extra/firmware/dir.h - $(call cmd,fwbin,$(fwabs)/$(patsubst $(obj)/%.gen.S,%,$@)) +$(obj)/%.gen.S: FORCE + $(call filechk,fwbin) # The .o files depend on the binaries directly; the .S files don't. -$(patsubst %,$(obj)/%.gen.o, $(fw-external-y)): $(obj)/%.gen.o: $(fwdir)/% +$(patsubst %,$(obj)/%.gen.o, $(obj-pbl-y)): $(obj)/%.gen.o: $(fwdir)/% # The same for pbl: -$(patsubst %,$(obj)/%.gen.pbl.o, $(fw-external-y)): $(obj)/%.gen.pbl.o: $(fwdir)/% +$(patsubst %,$(obj)/%.gen.pbl.o, $(obj-pbl-y)): $(obj)/%.gen.pbl.o: $(fwdir)/% obj-pbl-y += $(patsubst %,%.gen.o, $(fw-external-y)) -ifndef building_out_of_srctree -# Makefile.build only creates subdirectories for O= builds, but external -# firmware might live outside the kernel source tree -_dummy := $(foreach d,$(addprefix $(obj)/,$(dir $(fw-external-y))), $(shell [ -d $(d) ] || mkdir -p $(d))) -endif - targets := $(patsubst $(obj)/%,%, \ $(shell find $(obj) -name \*.gen.S 2>/dev/null)) diff --git a/images/Makefile.imx b/images/Makefile.imx index 382493488b..dd927aba55 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -215,7 +215,9 @@ $(call build_imx_habv4img, CONFIG_MACH_SABRELITE, start_imx6q_sabrelite, freesca $(call build_imx_habv4img, CONFIG_MACH_SABRELITE, start_imx6dl_sabrelite, freescale-mx6-sabrelite/flash-header-mx6-sabrelite, freescale-imx6dl-sabrelite) -$(call build_imx_habv4img, CONFIG_MACH_SABRESD, start_imx6q_sabresd, freescale-mx6-sabresd/flash-header-mx6-sabresd, freescale-imx6q-sabresd) +$(call build_imx_habv4img, CONFIG_MACH_SABRESD, start_imx6q_sabresd, freescale-mx6-sabresd/flash-header-mx6q-sabresd, freescale-imx6q-sabresd) + +$(call build_imx_habv4img, CONFIG_MACH_SABRESD, start_imx6qp_sabresd, freescale-mx6-sabresd/flash-header-mx6qp-sabresd, freescale-imx6qp-sabresd) $(call build_imx_habv4img, CONFIG_MACH_UDOO_NEO, start_imx6sx_udoo_neo, udoo-neo/flash-header-mx6sx-udoo-neo_full, udoo-neo) @@ -366,7 +368,9 @@ $(call build_imx_habv4img, CONFIG_MACH_TECHNEXION_PICO_HOBBIT, start_imx6ul_pico $(call build_imx_habv4img, CONFIG_MACH_DIGI_CCIMX6ULSBCPRO, start_imx6ul_ccimx6ulsbcpro, digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro, imx6ul-ccimx6ulsbcpro) -$(call build_imx_habv4img, CONFIG_MACH_WEBASTO_CCBV2, start_imx6ul_ccbv2, webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2, imx6ul-webasto-ccbv2) +$(call build_imx_habv4img, CONFIG_MACH_WEBASTO_CCBV2, start_imx6ul_ccbv2_256m, webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-256, imx6ul-webasto-ccbv2-256m) + +$(call build_imx_habv4img, CONFIG_MACH_WEBASTO_CCBV2, start_imx6ul_ccbv2_512m, webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-512, imx6ul-webasto-ccbv2-512m) # ----------------------- vf6xx based boards --------------------------- pblb-$(CONFIG_MACH_VF610_TWR) += start_vf610_twr @@ -416,6 +420,11 @@ CFG_start_nxp_imx8mm_evk.pblb.imximg = $(board)/nxp-imx8mm-evk/flash-header-imx8 FILE_barebox-nxp-imx8mm-evk.img = start_nxp_imx8mm_evk.pblb.pimximg image-$(CONFIG_MACH_NXP_IMX8MM_EVK) += barebox-nxp-imx8mm-evk.img +pblb-$(CONFIG_MACH_PROTONIC_IMX8M) += start_prt_prt8mm +CFG_start_prt_prt8mm.pblb.imximg = $(board)/protonic-imx8m/flash-header-prt8mm.imxcfg +FILE_barebox-prt-prt8mm.img = start_prt_prt8mm.pblb.pimximg +image-$(CONFIG_MACH_PROTONIC_IMX8M) += barebox-prt-prt8mm.img + # ----------------------- i.MX8mp based boards -------------------------- pblb-$(CONFIG_MACH_NXP_IMX8MP_EVK) += start_nxp_imx8mp_evk CFG_start_nxp_imx8mp_evk.pblb.imximg = $(board)/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga index b36e2a5033..26220178af 100644 --- a/images/Makefile.socfpga +++ b/images/Makefile.socfpga @@ -30,6 +30,14 @@ pblb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += start_socfpga_de0_nano_soc FILE_barebox-socfpga-de0_nano_soc.img = start_socfpga_de0_nano_soc.pblb socfpga-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += barebox-socfpga-de0_nano_soc.img +pblb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += start_socfpga_de10_nano_xload +FILE_barebox-socfpga-de10_nano-xload.img = start_socfpga_de10_nano_xload.pblb.socfpgaimg +socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += barebox-socfpga-de10_nano-xload.img + +pblb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += start_socfpga_de10_nano +FILE_barebox-socfpga-de10_nano.img = start_socfpga_de10_nano.pblb +socfpga-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += barebox-socfpga-de10_nano.img + pblb-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += start_socfpga_achilles_xload FILE_barebox-socfpga-achilles-xload.img = start_socfpga_achilles_xload.pblb.socfpgaimg socfpga-barebox-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += barebox-socfpga-achilles-xload.img diff --git a/include/io.h b/include/io.h index 79d8b56c4e..6a74246ea7 100644 --- a/include/io.h +++ b/include/io.h @@ -6,4 +6,36 @@ #define IOMEM_ERR_PTR(err) (__force void __iomem *)ERR_PTR(err) +#ifndef readq_relaxed +#define readq_relaxed(addr) readq(addr) +#endif + +#ifndef readl_relaxed +#define readl_relaxed(addr) readl(addr) +#endif + +#ifndef readw_relaxed +#define readw_relaxed(addr) readw(addr) +#endif + +#ifndef readb_relaxed +#define readb_relaxed(addr) readb(addr) +#endif + +#ifndef writeq_relaxed +#define writeq_relaxed(val, addr) writeq((val), (addr)) +#endif + +#ifndef writel_relaxed +#define writel_relaxed(val, addr) writel((val), (addr)) +#endif + +#ifndef writew_relaxed +#define writew_relaxed(val, addr) writew((val), (addr)) +#endif + +#ifndef writeb_relaxed +#define writeb_relaxed(val, addr) writeb((val), (addr)) +#endif + #endif /* __IO_H */ diff --git a/include/linux/clk.h b/include/linux/clk.h index c49fe9a54c..e54acdd918 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -11,6 +11,7 @@ #define __LINUX_CLK_H #include <linux/err.h> +#include <linux/spinlock.h> #include <linux/stringify.h> struct device_d; @@ -23,6 +24,7 @@ struct device_d; * struct clk - an machine class defined object / cookie. */ struct clk; +struct clk_hw; /** * struct clk_bulk_data - Data used for bulk clk operations. @@ -83,6 +85,19 @@ int __must_check clk_bulk_get(struct device_d *dev, int num_clks, struct clk_bulk_data *clks); /** + * clk_bulk_get_optional - lookup and obtain a number of references to clock producer + * @dev: device for clock "consumer" + * @num_clks: the number of clk_bulk_data + * @clks: the clk_bulk_data table of consumer + * + * Behaves the same as clk_bulk_get() except where there is no clock producer. + * In this case, instead of returning -ENOENT, the function returns 0 and + * NULL for a clk for which a clock producer could not be determined. + */ +int __must_check clk_bulk_get_optional(struct device_d *dev, int num_clks, + struct clk_bulk_data *clks); + +/** * clk_bulk_get_all - lookup and obtain all available references to clock * producer. * @dev: device for clock "consumer" @@ -163,6 +178,7 @@ void clk_bulk_disable(int num_clks, const struct clk_bulk_data *clks); * @clk: clock source */ unsigned long clk_get_rate(struct clk *clk); +unsigned long clk_hw_get_rate(struct clk_hw *hw); /** * clk_bulk_put - "free" the clock source @@ -203,7 +219,7 @@ void clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks); * Returns rounded clock rate in Hz, or negative errno. */ long clk_round_rate(struct clk *clk, unsigned long rate); - +long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); /** * clk_set_rate - set the clock rate for a clock source * @clk: clock source @@ -212,6 +228,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate); * Returns success (0) or negative errno. */ int clk_set_rate(struct clk *clk, unsigned long rate); +int clk_hw_set_rate(struct clk_hw *hw, unsigned long rate); /** * clk_set_parent - set the parent clock source for this clock @@ -221,6 +238,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate); * Returns success (0) or negative errno. */ int clk_set_parent(struct clk *clk, struct clk *parent); +int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *hwp); /** * clk_get_parent - get the parent clock source for this clock @@ -230,6 +248,10 @@ int clk_set_parent(struct clk *clk, struct clk *parent); * valid IS_ERR() condition containing errno. */ struct clk *clk_get_parent(struct clk *clk); +struct clk_hw *clk_hw_get_parent(struct clk_hw *hw); + +int clk_set_phase(struct clk *clk, int degrees); +int clk_get_phase(struct clk *clk); /** * clk_get_sys - get a clock based upon the device name @@ -274,6 +296,13 @@ static inline int __must_check clk_bulk_get(struct device_d *dev, int num_clks, return 0; } +static inline int __must_check clk_bulk_get_optional(struct device_d *dev, + int num_clks, + struct clk_bulk_data *clks) +{ + return 0; +} + static inline int __must_check clk_bulk_get_all(struct device_d *dev, struct clk_bulk_data **clks) { @@ -327,26 +356,49 @@ static inline void clk_put(struct clk *clk) #define CLK_SET_RATE_PARENT (1 << 0) /* propagate rate change up one level */ #define CLK_IGNORE_UNUSED (1 << 3) /* do not gate even if unused */ +#define CLK_GET_RATE_NOCACHE (1 << 6) /* do not use the cached clk rate */ #define CLK_SET_RATE_NO_REPARENT (1 << 7) /* don't re-parent on rate change */ +#define CLK_SET_RATE_UNGATE (1 << 10) /* clock needs to run to set rate */ #define CLK_IS_CRITICAL (1 << 11) /* do not gate, ever */ /* parents need enable during gate/ungate, set rate and re-parent */ #define CLK_OPS_PARENT_ENABLE (1 << 12) -#define CLK_GATE_INVERTED (1 << 0) +#define CLK_GATE_SET_TO_DISABLE (1 << 0) #define CLK_GATE_HIWORD_MASK (1 << 1) struct clk_ops { - int (*enable)(struct clk *clk); - void (*disable)(struct clk *clk); - int (*is_enabled)(struct clk *clk); - unsigned long (*recalc_rate)(struct clk *clk, + int (*init)(struct clk_hw *hw); + int (*enable)(struct clk_hw *hw); + void (*disable)(struct clk_hw *hw); + int (*is_enabled)(struct clk_hw *hw); + unsigned long (*recalc_rate)(struct clk_hw *hw, unsigned long parent_rate); - long (*round_rate)(struct clk *clk, unsigned long, + long (*round_rate)(struct clk_hw *hw, unsigned long, unsigned long *); - int (*set_parent)(struct clk *clk, u8 index); - int (*get_parent)(struct clk *clk); - int (*set_rate)(struct clk *clk, unsigned long, + int (*set_parent)(struct clk_hw *hw, u8 index); + int (*get_parent)(struct clk_hw *hw); + int (*set_rate)(struct clk_hw *hw, unsigned long, unsigned long); + int (*set_phase)(struct clk_hw *hw, int degrees); + int (*get_phase)(struct clk_hw *hw); +}; + +/** + * struct clk_init_data - holds init data that's common to all clocks and is + * shared between the clock provider and the common clock framework. + * + * @name: clock name + * @ops: operations this clock supports + * @parent_names: array of string names for all possible parents + * @num_parents: number of possible parents + * @flags: framework-level hints and quirks + */ +struct clk_init_data { + const char *name; + const struct clk_ops *ops; + const char * const *parent_names; + unsigned int num_parents; + unsigned long flags; }; struct clk { @@ -361,6 +413,33 @@ struct clk { unsigned long flags; }; +/** + * struct clk_hw - handle for traversing from a struct clk to its corresponding + * hardware-specific structure. struct clk_hw should be declared within struct + * clk_foo and then referenced by the struct clk instance that uses struct + * clk_foo's clk_ops + * + * @clk: pointer to the per-user struct clk instance that can be used to call + * into the clk API + * + * @init: pointer to struct clk_init_data that contains the init data shared + * with the common clock framework. + */ +struct clk_hw { + struct clk clk; + const struct clk_init_data *init; +}; + +static inline struct clk *clk_hw_to_clk(struct clk_hw *hw) +{ + return &hw->clk; +} + +static inline struct clk_hw *clk_to_clk_hw(struct clk *clk) +{ + return container_of(clk, struct clk_hw, clk); +} + struct clk_div_table { unsigned int val; unsigned int div; @@ -376,7 +455,7 @@ static inline struct clk *clk_fixed(const char *name, int rate) } struct clk_divider { - struct clk clk; + struct clk_hw hw; u8 shift; u8 width; void __iomem *reg; @@ -386,8 +465,11 @@ struct clk_divider { const struct clk_div_table *table; int max_div_index; int table_size; + spinlock_t *lock; }; +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) + #define clk_div_mask(width) ((1 << (width)) - 1) #define CLK_DIVIDER_POWER_OF_TWO (1 << 1) @@ -397,7 +479,8 @@ struct clk_divider { #define CLK_MUX_HIWORD_MASK (1 << 2) #define CLK_MUX_READ_ONLY (1 << 3) /* mux can't be changed */ -extern struct clk_ops clk_divider_ops; +extern const struct clk_ops clk_divider_ops; +extern const struct clk_ops clk_divider_ro_ops; unsigned long divider_recalc_rate(struct clk *clk, unsigned long parent_rate, unsigned int val, @@ -419,6 +502,10 @@ void clk_divider_free(struct clk *clk_divider); struct clk *clk_divider(const char *name, const char *parent, unsigned clk_flags, void __iomem *reg, u8 shift, u8 width, unsigned div_flags); +struct clk *clk_register_divider(struct device_d *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, spinlock_t *lock); struct clk *clk_divider_one_based(const char *name, const char *parent, unsigned clk_flags, void __iomem *reg, u8 shift, u8 width, unsigned div_flags); @@ -426,9 +513,73 @@ struct clk *clk_divider_table(const char *name, const char *parent, unsigned clk_flags, void __iomem *reg, u8 shift, u8 width, const struct clk_div_table *table, unsigned div_flags); +struct clk *clk_register_divider_table(struct device_d *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock); + +struct clk_fixed_factor { + struct clk_hw hw; + int mult; + int div; + const char *parent; +}; + +static inline struct clk_fixed_factor *to_clk_fixed_factor(struct clk_hw *hw) +{ + return container_of(hw, struct clk_fixed_factor, hw); +} + +extern struct clk_ops clk_fixed_factor_ops; + struct clk *clk_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div, unsigned flags); +struct clk *clk_register_fixed_factor(struct device_d *dev, const char *name, + const char *parent_name, unsigned long flags, + unsigned int mult, unsigned int div); + +/** + * struct clk_fractional_divider - adjustable fractional divider clock + * + * @hw: handle between common and hardware-specific interfaces + * @reg: register containing the divider + * @mshift: shift to the numerator bit field + * @mwidth: width of the numerator bit field + * @nshift: shift to the denominator bit field + * @nwidth: width of the denominator bit field + * + * Clock with adjustable fractional divider affecting its output frequency. + * + * Flags: + * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator + * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED + * is set then the numerator and denominator are both the value read + * plus one. + * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are + * used for the divider register. Setting this flag makes the register + * accesses big endian. + */ +struct clk_fractional_divider { + struct clk_hw hw; + void __iomem *reg; + u8 mshift; + u8 mwidth; + u32 mmask; + u8 nshift; + u8 nwidth; + u32 nmask; + u8 flags; + void (*approximation)(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate, + unsigned long *m, unsigned long *n); + spinlock_t *lock; +}; + +#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) +#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) + struct clk *clk_fractional_divider_alloc( const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, @@ -439,17 +590,23 @@ struct clk *clk_fractional_divider( u8 clk_divider_flags); void clk_fractional_divider_free(struct clk *clk_fd); +#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) + +extern const struct clk_ops clk_fractional_divider_ops; + struct clk_mux { - struct clk clk; + struct clk_hw hw; void __iomem *reg; int shift; int width; unsigned flags; + spinlock_t *lock; }; -#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk) +#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) -extern struct clk_ops clk_mux_ops; +extern const struct clk_ops clk_mux_ops; +extern const struct clk_ops clk_mux_ro_ops; struct clk *clk_mux_alloc(const char *name, unsigned clk_flags, void __iomem *reg, u8 shift, u8 width, @@ -459,18 +616,24 @@ void clk_mux_free(struct clk *clk_mux); struct clk *clk_mux(const char *name, unsigned clk_flags, void __iomem *reg, u8 shift, u8 width, const char * const *parents, u8 num_parents, unsigned mux_flags); +struct clk *clk_register_mux(struct device_d *dev, const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_mux_flags, spinlock_t *lock); struct clk_gate { - struct clk clk; + struct clk_hw hw; void __iomem *reg; int shift; const char *parent; unsigned flags; + spinlock_t *lock; }; -int clk_gate_is_enabled(struct clk *clk); +int clk_gate_is_enabled(struct clk_hw *hw); -#define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk) +#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) extern struct clk_ops clk_gate_ops; @@ -484,16 +647,22 @@ struct clk *clk_gate_inverted(const char *name, const char *parent, void __iomem u8 shift, unsigned flags); struct clk *clk_gate_shared(const char *name, const char *parent, const char *shared, unsigned flags); +struct clk *clk_register_gate(struct device_d *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); int clk_is_enabled(struct clk *clk); +int clk_hw_is_enabled(struct clk_hw *hw); -int clk_is_enabled_always(struct clk *clk); -long clk_parent_round_rate(struct clk *clk, unsigned long rate, +int clk_is_enabled_always(struct clk_hw *hw); +long clk_parent_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate); -int clk_parent_set_rate(struct clk *clk, unsigned long rate, +int clk_parent_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); -int clk_register(struct clk *clk); +int bclk_register(struct clk *clk); +struct clk *clk_register(struct device_d *dev, struct clk_hw *hw); struct clk *clk_lookup(const char *name); @@ -506,6 +675,12 @@ struct clk *clk_register_composite(const char *name, struct clk *rate_clk, struct clk *gate_clk, unsigned long flags); + +static inline const char *clk_hw_get_name(struct clk_hw *hw) +{ + return hw->clk.name; +} + #endif struct device_node; diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h index 6ef5ea6854..2d73898373 100644 --- a/include/linux/nvmem-provider.h +++ b/include/linux/nvmem-provider.h @@ -18,10 +18,8 @@ struct nvmem_device; struct nvmem_bus { - int (*write)(struct device_d *dev, const int reg, const void *val, - int val_size); - int (*read)(struct device_d *dev, const int reg, void *val, - int val_size); + int (*write)(void *ctx, unsigned int reg, const void *val, size_t val_size); + int (*read)(void *ctx, unsigned int reg, void *val, size_t val_size); }; struct nvmem_config { @@ -32,11 +30,15 @@ struct nvmem_config { int word_size; int size; const struct nvmem_bus *bus; + void *priv; }; +struct regmap; + #if IS_ENABLED(CONFIG_NVMEM) struct nvmem_device *nvmem_register(const struct nvmem_config *cfg); +struct nvmem_device *nvmem_regmap_register(struct regmap *regmap, const char *name); #else @@ -45,5 +47,10 @@ static inline struct nvmem_device *nvmem_register(const struct nvmem_config *c) return ERR_PTR(-ENOSYS); } +static inline struct nvmem_device *nvmem_regmap_register(struct regmap *regmap, const char *name) +{ + return ERR_PTR(-ENOSYS); +} + #endif /* CONFIG_NVMEM */ #endif /* ifndef _LINUX_NVMEM_PROVIDER_H */ diff --git a/include/linux/rational.h b/include/linux/rational.h new file mode 100644 index 0000000000..33f5f5fc3e --- /dev/null +++ b/include/linux/rational.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * rational fractions + * + * Copyright (C) 2009 emlix GmbH, Oskar Schirmer <oskar@scara.com> + * + * helper functions when coping with rational numbers, + * e.g. when calculating optimum numerator/denominator pairs for + * pll configuration taking into account restricted register size + */ + +#ifndef _LINUX_RATIONAL_H +#define _LINUX_RATIONAL_H + +void rational_best_approximation( + unsigned long given_numerator, unsigned long given_denominator, + unsigned long max_numerator, unsigned long max_denominator, + unsigned long *best_numerator, unsigned long *best_denominator); + +#endif /* _LINUX_RATIONAL_H */ diff --git a/include/regmap.h b/include/regmap.h index b43cd936fa..db84c7a534 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -77,6 +77,19 @@ struct regmap *regmap_init_mmio_clk(struct device_d *dev, const char *clk_id, const struct regmap_config *config); /** + * regmap_init_i2c() - Initialise i2c register map + * + * @i2c: Device that will be interacted with + * @config: Configuration for register map + * + * The return value will be an ERR_PTR() on error or a valid pointer + * to a struct regmap. + */ +struct i2c_client; +struct regmap *regmap_init_i2c(struct i2c_client *i2c, + const struct regmap_config *config); + +/** * regmap_init_mmio() - Initialise register map * * @dev: Device that will be interacted with @@ -96,6 +109,7 @@ void regmap_mmio_detach_clk(struct regmap *map); void regmap_exit(struct regmap *map); struct regmap *dev_get_regmap(struct device_d *dev, const char *name); +struct device_d *regmap_get_device(struct regmap *map); int regmap_register_cdev(struct regmap *map, const char *name); @@ -116,4 +130,28 @@ int regmap_write_bits(struct regmap *map, unsigned int reg, int regmap_update_bits(struct regmap *map, unsigned int reg, unsigned int mask, unsigned int val); +/** + * regmap_read_poll_timeout - Poll until a condition is met or a timeout occurs + * + * @map: Regmap to read from + * @addr: Address to poll + * @val: Unsigned integer variable to read the value into + * @cond: Break condition (usually involving @val) + * @timeout_us: Timeout in us, 0 means never timeout + * + * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_read + * error return value in case of a error read. In the two former cases, + * the last read value at @addr is stored in @val. Must not be called + * from atomic context if sleep_us or timeout_us are used. + * + * This is modelled after the readx_poll_timeout macros in linux/iopoll.h. + */ +#define regmap_read_poll_timeout(map, addr, val, cond, timeout_us) \ +({ \ + int __ret, __tmp; \ + __tmp = read_poll_timeout(regmap_read, __ret, __ret || (cond), \ + timeout_us, (map), (addr), &(val)); \ + __ret ?: __tmp; \ +}) + #endif /* __REGMAP_H */ diff --git a/lib/math/Makefile b/lib/math/Makefile index c2c892dd55..756d7dd90d 100644 --- a/lib/math/Makefile +++ b/lib/math/Makefile @@ -1,2 +1,3 @@ obj-y += div64.o pbl-y += div64.o +obj-y += rational.o diff --git a/lib/math/rational.c b/lib/math/rational.c new file mode 100644 index 0000000000..8411e912fb --- /dev/null +++ b/lib/math/rational.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * rational fractions + * + * Copyright (C) 2009 emlix GmbH, Oskar Schirmer <oskar@scara.com> + * Copyright (C) 2019 Trent Piepho <tpiepho@gmail.com> + * + * helper functions when coping with rational numbers + */ + +#include <linux/rational.h> +#include <linux/compiler.h> +#include <linux/export.h> +#include <linux/kernel.h> + +/* + * calculate best rational approximation for a given fraction + * taking into account restricted register size, e.g. to find + * appropriate values for a pll with 5 bit denominator and + * 8 bit numerator register fields, trying to set up with a + * frequency ratio of 3.1415, one would say: + * + * rational_best_approximation(31415, 10000, + * (1 << 8) - 1, (1 << 5) - 1, &n, &d); + * + * you may look at given_numerator as a fixed point number, + * with the fractional part size described in given_denominator. + * + * for theoretical background, see: + * https://en.wikipedia.org/wiki/Continued_fraction + */ + +void rational_best_approximation( + unsigned long given_numerator, unsigned long given_denominator, + unsigned long max_numerator, unsigned long max_denominator, + unsigned long *best_numerator, unsigned long *best_denominator) +{ + /* n/d is the starting rational, which is continually + * decreased each iteration using the Euclidean algorithm. + * + * dp is the value of d from the prior iteration. + * + * n2/d2, n1/d1, and n0/d0 are our successively more accurate + * approximations of the rational. They are, respectively, + * the current, previous, and two prior iterations of it. + * + * a is current term of the continued fraction. + */ + unsigned long n, d, n0, d0, n1, d1, n2, d2; + n = given_numerator; + d = given_denominator; + n0 = d1 = 0; + n1 = d0 = 1; + + for (;;) { + unsigned long dp, a; + + if (d == 0) + break; + /* Find next term in continued fraction, 'a', via + * Euclidean algorithm. + */ + dp = d; + a = n / d; + d = n % d; + n = dp; + + /* Calculate the current rational approximation (aka + * convergent), n2/d2, using the term just found and + * the two prior approximations. + */ + n2 = n0 + a * n1; + d2 = d0 + a * d1; + + /* If the current convergent exceeds the maxes, then + * return either the previous convergent or the + * largest semi-convergent, the final term of which is + * found below as 't'. + */ + if ((n2 > max_numerator) || (d2 > max_denominator)) { + unsigned long t = ULONG_MAX; + + if (d1) + t = (max_denominator - d0) / d1; + if (n1) + t = min(t, (max_numerator - n0) / n1); + + /* This tests if the semi-convergent is closer than the previous + * convergent. If d1 is zero there is no previous convergent as this + * is the 1st iteration, so always choose the semi-convergent. + */ + if (!d1 || 2u * t > a || (2u * t == a && d0 * dp > d1 * d)) { + n1 = n0 + t * n1; + d1 = d0 + t * d1; + } + break; + } + n0 = n1; + n1 = n2; + d0 = d1; + d1 = d2; + } + *best_numerator = n1; + *best_denominator = d1; +} @@ -215,7 +215,7 @@ int resolv(const char *host, IPaddr_t *ip) nameserver = net_get_nameserver(); if (!nameserver) { - pr_err("no nameserver specified in $net.nameserver\n"); + pr_err("no nameserver specified in $global.net.nameserver\n"); return 0; } diff --git a/scripts/basic/.gitignore b/scripts/basic/.gitignore index 98ae1f5095..961c91c8a8 100644 --- a/scripts/basic/.gitignore +++ b/scripts/basic/.gitignore @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -fixdep +/fixdep diff --git a/scripts/basic/fixdep.c b/scripts/basic/fixdep.c index 877ca2c882..44e887cff4 100644 --- a/scripts/basic/fixdep.c +++ b/scripts/basic/fixdep.c @@ -34,7 +34,7 @@ * the config symbols are rebuilt. * * So if the user changes his CONFIG_HIS_DRIVER option, only the objects - * which depend on "include/config/his/driver.h" will be rebuilt, + * which depend on "include/config/HIS_DRIVER" will be rebuilt, * so most likely only his driver ;-) * * The idea above dates, by the way, back to Michael E Chastain, AFAIK. @@ -74,7 +74,7 @@ * * and then basically copies the .<target>.d file to stdout, in the * process filtering out the dependency on autoconf.h and adding - * dependencies on include/config/my/option.h for every + * dependencies on include/config/MY_OPTION for every * CONFIG_MY_OPTION encountered in any of the prerequisites. * * We don't even try to really parse the header files, but @@ -107,8 +107,8 @@ static void usage(void) /* * In the intended usage of this program, the stdout is redirected to .*.cmd - * files. The return value of printf() and putchar() must be checked to catch - * any error, e.g. "No space left on device". + * files. The return value of printf() must be checked to catch any error, + * e.g. "No space left on device". */ static void xprintf(const char *format, ...) { @@ -124,43 +124,11 @@ static void xprintf(const char *format, ...) va_end(ap); } -static void xputchar(int c) -{ - int ret; - - ret = putchar(c); - if (ret == EOF) { - perror("fixdep"); - exit(1); - } -} - -/* - * Print out a dependency path from a symbol name - */ -static void print_dep(const char *m, int slen, const char *dir) -{ - int c, prev_c = '/', i; - - xprintf(" $(wildcard %s/", dir); - for (i = 0; i < slen; i++) { - c = m[i]; - if (c == '_') - c = '/'; - else - c = tolower(c); - if (c != '/' || prev_c != '/') - xputchar(c); - prev_c = c; - } - xprintf(".h) \\\n"); -} - struct item { struct item *next; unsigned int len; unsigned int hash; - char name[0]; + char name[]; }; #define HASHSZ 256 @@ -220,7 +188,8 @@ static void use_config(const char *m, int slen) return; define_config(m, slen, hash); - print_dep(m, slen, "include/config"); + /* Print out a dependency path from a symbol name. */ + xprintf(" $(wildcard include/config/%.*s) \\\n", slen, m); } /* test if s ends in sub */ diff --git a/scripts/imx/imx-image.c b/scripts/imx/imx-image.c index 3e277e82fa..b97f561897 100644 --- a/scripts/imx/imx-image.c +++ b/scripts/imx/imx-image.c @@ -770,7 +770,7 @@ int main(int argc, char *argv[]) int outfd; int dcd_only = 0; int now = 0; - int add_barebox_header; + int add_barebox_header = 0; uint32_t barebox_image_size = 0; struct config_data data = { .image_ivt_offset = 0xffffffff, diff --git a/scripts/kconfig/.gitignore b/scripts/kconfig/.gitignore index c3d537cd02..500e7424b3 100644 --- a/scripts/kconfig/.gitignore +++ b/scripts/kconfig/.gitignore @@ -1,12 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only +/conf +/[gmnq]conf +/[gmnq]conf-cfg /qconf-moc.cc -*conf-cfg - -# -# configuration programs -# -conf -mconf -nconf -qconf -gconf diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile index 52b59bf9ef..5a215880b2 100644 --- a/scripts/kconfig/Makefile +++ b/scripts/kconfig/Makefile @@ -3,45 +3,51 @@ # Kernel configuration targets # These targets are used from top-level makefile -PHONY += xconfig gconfig menuconfig config localmodconfig localyesconfig \ - build_menuconfig build_nconfig build_gconfig build_xconfig - ifdef KBUILD_KCONFIG Kconfig := $(KBUILD_KCONFIG) else Kconfig := Kconfig endif +ifndef KBUILD_DEFCONFIG +KBUILD_DEFCONFIG := defconfig +endif + ifeq ($(quiet),silent_) silent := -s endif +export KCONFIG_DEFCONFIG_LIST := +ifndef cross_compiling +kernel-release := $(shell uname -r) +KCONFIG_DEFCONFIG_LIST += \ + /lib/modules/$(kernel-release)/.config \ + /etc/kernel-config \ + /boot/config-$(kernel-release) +endif +KCONFIG_DEFCONFIG_LIST += arch/$(SRCARCH)/configs/$(KBUILD_DEFCONFIG) + # We need this, in case the user has it in its environment unexport CONFIG_ -xconfig: $(obj)/qconf - $< $(silent) $(Kconfig) - -gconfig: $(obj)/gconf - $< $(silent) $(Kconfig) +config-prog := conf +menuconfig-prog := mconf +nconfig-prog := nconf +gconfig-prog := gconf +xconfig-prog := qconf -menuconfig: $(obj)/mconf - $< $(silent) $(Kconfig) +define config_rule +PHONY += $(1) +$(1): $(obj)/$($(1)-prog) + $(Q)$$< $(silent) $(Kconfig) -config: $(obj)/conf - $< $(silent) --oldaskconfig $(Kconfig) +PHONY += build_$(1) +build_$(1): $(obj)/$($(1)-prog) +endef -nconfig: $(obj)/nconf - $< $(silent) $(Kconfig) - -build_menuconfig: $(obj)/mconf - -build_nconfig: $(obj)/nconf - -build_gconfig: $(obj)/gconf - -build_xconfig: $(obj)/qconf +$(foreach c, config menuconfig nconfig gconfig xconfig, $(eval $(call config_rule,$(c)))) +PHONY += localmodconfig localyesconfig localyesconfig localmodconfig: $(obj)/conf $(Q)$(PERL) $(srctree)/$(src)/streamline_config.pl --$@ $(srctree) $(Kconfig) > .tmp.config $(Q)if [ -f .config ]; then \ @@ -68,12 +74,12 @@ simple-targets := oldconfig allnoconfig allyesconfig allmodconfig \ PHONY += $(simple-targets) $(simple-targets): $(obj)/conf - $< $(silent) --$@ $(Kconfig) + $(Q)$< $(silent) --$@ $(Kconfig) PHONY += savedefconfig defconfig savedefconfig: $(obj)/conf - $< $(silent) --$@=defconfig $(Kconfig) + $(Q)$< $(silent) --$@=defconfig $(Kconfig) defconfig: $(obj)/conf ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/configs/$(KBUILD_DEFCONFIG)),) @@ -94,24 +100,15 @@ configfiles=$(wildcard $(srctree)/kernel/configs/$@ $(srctree)/arch/$(SRCARCH)/c $(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh -m .config $(configfiles) $(Q)$(MAKE) -f $(srctree)/Makefile olddefconfig -PHONY += kvmconfig -kvmconfig: kvm_guest.config - @echo >&2 "WARNING: 'make $@' will be removed after Linux 5.10" - @echo >&2 " Please use 'make $<' instead." - -PHONY += xenconfig -xenconfig: xen.config - @echo >&2 "WARNING: 'make $@' will be removed after Linux 5.10" - @echo >&2 " Please use 'make $<' instead." - PHONY += tinyconfig tinyconfig: - $(Q)$(MAKE) -f $(srctree)/Makefile allnoconfig tiny.config + $(Q)KCONFIG_ALLCONFIG=kernel/configs/tiny-base.config $(MAKE) -f $(srctree)/Makefile allnoconfig + $(Q)$(MAKE) -f $(srctree)/Makefile tiny.config # CHECK: -o cache_dir=<path> working? PHONY += testconfig testconfig: $(obj)/conf - $(PYTHON3) -B -m pytest $(srctree)/$(src)/tests \ + $(Q)$(PYTHON3) -B -m pytest $(srctree)/$(src)/tests \ -o cache_dir=$(abspath $(obj)/tests/.cache) \ $(if $(findstring 1,$(KBUILD_VERBOSE)),--capture=no) clean-files += tests/.cache @@ -146,8 +143,8 @@ help: # =========================================================================== # object files used by all kconfig flavours -common-objs := confdata.o expr.o lexer.lex.o parser.tab.o preprocess.o \ - symbol.o util.o +common-objs := confdata.o expr.o lexer.lex.o menu.o parser.tab.o \ + preprocess.o symbol.o util.o $(obj)/lexer.lex.o: $(obj)/parser.tab.h HOSTCFLAGS_lexer.lex.o := -I $(srctree)/$(src) diff --git a/scripts/kconfig/conf.c b/scripts/kconfig/conf.c index f6e548b8f7..bfa1ea8f5f 100644 --- a/scripts/kconfig/conf.c +++ b/scripts/kconfig/conf.c @@ -11,7 +11,6 @@ #include <time.h> #include <unistd.h> #include <getopt.h> -#include <sys/stat.h> #include <sys/time.h> #include <errno.h> @@ -38,7 +37,7 @@ enum input_mode { mod2yesconfig, }; static enum input_mode input_mode = oldaskconfig; - +static int input_mode_opt; static int indent = 1; static int tty_stdio; static int sync_kconfig; @@ -83,10 +82,243 @@ static void xfgets(char *str, int size, FILE *in) printf("%s", str); } -static int conf_askvalue(struct symbol *sym, const char *def) +static void set_randconfig_seed(void) +{ + unsigned int seed; + char *env; + bool seed_set = false; + + env = getenv("KCONFIG_SEED"); + if (env && *env) { + char *endp; + + seed = strtol(env, &endp, 0); + if (*endp == '\0') + seed_set = true; + } + + if (!seed_set) { + struct timeval now; + + /* + * Use microseconds derived seed, compensate for systems where it may + * be zero. + */ + gettimeofday(&now, NULL); + seed = (now.tv_sec + 1) * (now.tv_usec + 1); + } + + printf("KCONFIG_SEED=0x%X\n", seed); + srand(seed); +} + +static bool randomize_choice_values(struct symbol *csym) { - enum symbol_type type = sym_get_type(sym); + struct property *prop; + struct symbol *sym; + struct expr *e; + int cnt, def; + + /* + * If choice is mod then we may have more items selected + * and if no then no-one. + * In both cases stop. + */ + if (csym->curr.tri != yes) + return false; + + prop = sym_get_choice_prop(csym); + + /* count entries in choice block */ + cnt = 0; + expr_list_for_each_sym(prop->expr, e, sym) + cnt++; + + /* + * find a random value and set it to yes, + * set the rest to no so we have only one set + */ + def = rand() % cnt; + + cnt = 0; + expr_list_for_each_sym(prop->expr, e, sym) { + if (def == cnt++) { + sym->def[S_DEF_USER].tri = yes; + csym->def[S_DEF_USER].val = sym; + } else { + sym->def[S_DEF_USER].tri = no; + } + sym->flags |= SYMBOL_DEF_USER; + /* clear VALID to get value calculated */ + sym->flags &= ~SYMBOL_VALID; + } + csym->flags |= SYMBOL_DEF_USER; + /* clear VALID to get value calculated */ + csym->flags &= ~SYMBOL_VALID; + + return true; +} + +enum conf_def_mode { + def_default, + def_yes, + def_mod, + def_y2m, + def_m2y, + def_no, + def_random +}; + +static bool conf_set_all_new_symbols(enum conf_def_mode mode) +{ + struct symbol *sym, *csym; + int i, cnt; + /* + * can't go as the default in switch-case below, otherwise gcc whines + * about -Wmaybe-uninitialized + */ + int pby = 50; /* probability of bool = y */ + int pty = 33; /* probability of tristate = y */ + int ptm = 33; /* probability of tristate = m */ + bool has_changed = false; + + if (mode == def_random) { + int n, p[3]; + char *env = getenv("KCONFIG_PROBABILITY"); + + n = 0; + while (env && *env) { + char *endp; + int tmp = strtol(env, &endp, 10); + + if (tmp >= 0 && tmp <= 100) { + p[n++] = tmp; + } else { + errno = ERANGE; + perror("KCONFIG_PROBABILITY"); + exit(1); + } + env = (*endp == ':') ? endp + 1 : endp; + if (n >= 3) + break; + } + switch (n) { + case 1: + pby = p[0]; + ptm = pby / 2; + pty = pby - ptm; + break; + case 2: + pty = p[0]; + ptm = p[1]; + pby = pty + ptm; + break; + case 3: + pby = p[0]; + pty = p[1]; + ptm = p[2]; + break; + } + + if (pty + ptm > 100) { + errno = ERANGE; + perror("KCONFIG_PROBABILITY"); + exit(1); + } + } + + for_all_symbols(i, sym) { + if (sym_has_value(sym) || sym->flags & SYMBOL_VALID) + continue; + switch (sym_get_type(sym)) { + case S_BOOLEAN: + case S_TRISTATE: + has_changed = true; + switch (mode) { + case def_yes: + sym->def[S_DEF_USER].tri = yes; + break; + case def_mod: + sym->def[S_DEF_USER].tri = mod; + break; + case def_no: + sym->def[S_DEF_USER].tri = no; + break; + case def_random: + sym->def[S_DEF_USER].tri = no; + cnt = rand() % 100; + if (sym->type == S_TRISTATE) { + if (cnt < pty) + sym->def[S_DEF_USER].tri = yes; + else if (cnt < pty + ptm) + sym->def[S_DEF_USER].tri = mod; + } else if (cnt < pby) + sym->def[S_DEF_USER].tri = yes; + break; + default: + continue; + } + if (!(sym_is_choice(sym) && mode == def_random)) + sym->flags |= SYMBOL_DEF_USER; + break; + default: + break; + } + + } + + sym_clear_all_valid(); + + /* + * We have different type of choice blocks. + * If curr.tri equals to mod then we can select several + * choice symbols in one block. + * In this case we do nothing. + * If curr.tri equals yes then only one symbol can be + * selected in a choice block and we set it to yes, + * and the rest to no. + */ + if (mode != def_random) { + for_all_symbols(i, csym) { + if ((sym_is_choice(csym) && !sym_has_value(csym)) || + sym_is_choice_value(csym)) + csym->flags |= SYMBOL_NEED_SET_CHOICE_VALUES; + } + } + + for_all_symbols(i, csym) { + if (sym_has_value(csym) || !sym_is_choice(csym)) + continue; + + sym_calc_value(csym); + if (mode == def_random) + has_changed |= randomize_choice_values(csym); + else { + set_all_choice_values(csym); + has_changed = true; + } + } + + return has_changed; +} +static void conf_rewrite_mod_or_yes(enum conf_def_mode mode) +{ + struct symbol *sym; + int i; + tristate old_val = (mode == def_y2m) ? yes : mod; + tristate new_val = (mode == def_y2m) ? mod : yes; + + for_all_symbols(i, sym) { + if (sym_get_type(sym) == S_TRISTATE && + sym->def[S_DEF_USER].tri == old_val) + sym->def[S_DEF_USER].tri = new_val; + } + sym_clear_all_valid(); +} + +static int conf_askvalue(struct symbol *sym, const char *def) +{ if (!sym_has_value(sym)) printf("(NEW) "); @@ -108,24 +340,12 @@ static int conf_askvalue(struct symbol *sym, const char *def) return 0; } /* fall through */ - case oldaskconfig: + default: fflush(stdout); xfgets(line, sizeof(line), stdin); - return 1; - default: break; } - switch (type) { - case S_INT: - case S_HEX: - case S_STRING: - printf("%s\n", def); - return 1; - default: - ; - } - printf("%s", line); return 1; } @@ -138,7 +358,7 @@ static int conf_string(struct menu *menu) printf("%*s%s ", indent - 1, "", menu->prompt->text); printf("(%s) ", sym->name); def = sym_get_string_value(sym); - if (sym_get_string_value(sym)) + if (def) printf("[%s] ", def); if (!conf_askvalue(sym, def)) return 0; @@ -420,34 +640,37 @@ static void check_conf(struct menu *menu) return; sym = menu->sym; - if (sym && !sym_has_value(sym)) { - if (sym_is_changeable(sym) || - (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes)) { - if (input_mode == listnewconfig) { - if (sym->name) { - const char *str; - - if (sym->type == S_STRING) { - str = sym_get_string_value(sym); - str = sym_escape_string_value(str); - printf("%s%s=%s\n", CONFIG_, sym->name, str); - free((void *)str); - } else { - str = sym_get_string_value(sym); - printf("%s%s=%s\n", CONFIG_, sym->name, str); - } - } - } else if (input_mode == helpnewconfig) { - printf("-----\n"); - print_help(menu); - printf("-----\n"); + if (sym && !sym_has_value(sym) && + (sym_is_changeable(sym) || + (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes))) { - } else { - if (!conf_cnt++) - printf("*\n* Restart config...\n*\n"); - rootEntry = menu_get_parent_menu(menu); - conf(rootEntry); + switch (input_mode) { + case listnewconfig: + if (sym->name) { + const char *str; + + if (sym->type == S_STRING) { + str = sym_get_string_value(sym); + str = sym_escape_string_value(str); + printf("%s%s=%s\n", CONFIG_, sym->name, str); + free((void *)str); + } else { + str = sym_get_string_value(sym); + printf("%s%s=%s\n", CONFIG_, sym->name, str); + } } + break; + case helpnewconfig: + printf("-----\n"); + print_help(menu); + printf("-----\n"); + break; + default: + if (!conf_cnt++) + printf("*\n* Restart config...\n*\n"); + rootEntry = menu_get_parent_menu(menu); + conf(rootEntry); + break; } } @@ -456,29 +679,35 @@ static void check_conf(struct menu *menu) } static struct option long_opts[] = { - {"oldaskconfig", no_argument, NULL, oldaskconfig}, - {"oldconfig", no_argument, NULL, oldconfig}, - {"syncconfig", no_argument, NULL, syncconfig}, - {"defconfig", required_argument, NULL, defconfig}, - {"savedefconfig", required_argument, NULL, savedefconfig}, - {"allnoconfig", no_argument, NULL, allnoconfig}, - {"allyesconfig", no_argument, NULL, allyesconfig}, - {"allmodconfig", no_argument, NULL, allmodconfig}, - {"alldefconfig", no_argument, NULL, alldefconfig}, - {"randconfig", no_argument, NULL, randconfig}, - {"listnewconfig", no_argument, NULL, listnewconfig}, - {"helpnewconfig", no_argument, NULL, helpnewconfig}, - {"olddefconfig", no_argument, NULL, olddefconfig}, - {"yes2modconfig", no_argument, NULL, yes2modconfig}, - {"mod2yesconfig", no_argument, NULL, mod2yesconfig}, + {"help", no_argument, NULL, 'h'}, + {"silent", no_argument, NULL, 's'}, + {"oldaskconfig", no_argument, &input_mode_opt, oldaskconfig}, + {"oldconfig", no_argument, &input_mode_opt, oldconfig}, + {"syncconfig", no_argument, &input_mode_opt, syncconfig}, + {"defconfig", required_argument, &input_mode_opt, defconfig}, + {"savedefconfig", required_argument, &input_mode_opt, savedefconfig}, + {"allnoconfig", no_argument, &input_mode_opt, allnoconfig}, + {"allyesconfig", no_argument, &input_mode_opt, allyesconfig}, + {"allmodconfig", no_argument, &input_mode_opt, allmodconfig}, + {"alldefconfig", no_argument, &input_mode_opt, alldefconfig}, + {"randconfig", no_argument, &input_mode_opt, randconfig}, + {"listnewconfig", no_argument, &input_mode_opt, listnewconfig}, + {"helpnewconfig", no_argument, &input_mode_opt, helpnewconfig}, + {"olddefconfig", no_argument, &input_mode_opt, olddefconfig}, + {"yes2modconfig", no_argument, &input_mode_opt, yes2modconfig}, + {"mod2yesconfig", no_argument, &input_mode_opt, mod2yesconfig}, {NULL, 0, NULL, 0} }; static void conf_usage(const char *progname) { - - printf("Usage: %s [-s] [option] <kconfig-file>\n", progname); - printf("[option] is _one_ of the following:\n"); + printf("Usage: %s [options] <kconfig-file>\n", progname); + printf("\n"); + printf("Generic options:\n"); + printf(" -h, --help Print this message and exit.\n"); + printf(" -s, --silent Do not print log.\n"); + printf("\n"); + printf("Mode options:\n"); printf(" --listnewconfig List new options\n"); printf(" --helpnewconfig List new options and help text\n"); printf(" --oldaskconfig Start a new configuration using a line-oriented program\n"); @@ -495,6 +724,7 @@ static void conf_usage(const char *progname) printf(" --randconfig New config with random answer to all options\n"); printf(" --yes2modconfig Change answers from yes to mod if possible\n"); printf(" --mod2yesconfig Change answers from mod to yes if possible\n"); + printf(" (If none of the above is given, --oldaskconfig is the default)\n"); } int main(int ac, char **av) @@ -506,65 +736,38 @@ int main(int ac, char **av) tty_stdio = isatty(0) && isatty(1); - while ((opt = getopt_long(ac, av, "s", long_opts, NULL)) != -1) { - if (opt == 's') { - conf_set_message_callback(NULL); - continue; - } - input_mode = (enum input_mode)opt; + while ((opt = getopt_long(ac, av, "hs", long_opts, NULL)) != -1) { switch (opt) { - case syncconfig: - /* - * syncconfig is invoked during the build stage. - * Suppress distracting "configuration written to ..." - */ - conf_set_message_callback(NULL); - sync_kconfig = 1; + case 'h': + conf_usage(progname); + exit(1); break; - case defconfig: - case savedefconfig: - defconfig_file = optarg; + case 's': + conf_set_message_callback(NULL); break; - case randconfig: - { - struct timeval now; - unsigned int seed; - char *seed_env; - - /* - * Use microseconds derived seed, - * compensate for systems where it may be zero - */ - gettimeofday(&now, NULL); - seed = (unsigned int)((now.tv_sec + 1) * (now.tv_usec + 1)); - - seed_env = getenv("KCONFIG_SEED"); - if( seed_env && *seed_env ) { - char *endp; - int tmp = (int)strtol(seed_env, &endp, 0); - if (*endp == '\0') { - seed = tmp; - } + case 0: + input_mode = input_mode_opt; + switch (input_mode) { + case syncconfig: + /* + * syncconfig is invoked during the build stage. + * Suppress distracting + * "configuration written to ..." + */ + conf_set_message_callback(NULL); + sync_kconfig = 1; + break; + case defconfig: + case savedefconfig: + defconfig_file = optarg; + break; + case randconfig: + set_randconfig_seed(); + break; + default: + break; } - fprintf( stderr, "KCONFIG_SEED=0x%X\n", seed ); - srand(seed); - break; - } - case oldaskconfig: - case oldconfig: - case allnoconfig: - case allyesconfig: - case allmodconfig: - case alldefconfig: - case listnewconfig: - case helpnewconfig: - case olddefconfig: - case yes2modconfig: - case mod2yesconfig: - break; - case '?': - conf_usage(progname); - exit(1); + default: break; } } @@ -573,8 +776,7 @@ int main(int ac, char **av) conf_usage(progname); exit(1); } - name = av[optind]; - conf_parse(name); + conf_parse(av[optind]); //zconfdump(stdout); switch (input_mode) { diff --git a/scripts/kconfig/confdata.c b/scripts/kconfig/confdata.c index a39d93e3c6..cf72680cd7 100644 --- a/scripts/kconfig/confdata.c +++ b/scripts/kconfig/confdata.c @@ -5,6 +5,7 @@ #include <sys/mman.h> #include <sys/stat.h> +#include <sys/types.h> #include <ctype.h> #include <errno.h> #include <fcntl.h> @@ -32,7 +33,7 @@ static bool is_dir(const char *path) struct stat st; if (stat(path, &st)) - return 0; + return false; return S_ISDIR(st.st_mode); } @@ -129,19 +130,14 @@ static size_t depfile_prefix_len; static int conf_touch_dep(const char *name) { int fd, ret; - const char *s; - char *d, c; + char *d; - /* check overflow: prefix + name + ".h" + '\0' must fit in buffer. */ - if (depfile_prefix_len + strlen(name) + 3 > sizeof(depfile_path)) + /* check overflow: prefix + name + '\0' must fit in buffer. */ + if (depfile_prefix_len + strlen(name) + 1 > sizeof(depfile_path)) return -1; d = depfile_path + depfile_prefix_len; - s = name; - - while ((c = *s++)) - *d++ = (c == '_') ? '/' : tolower(c); - strcpy(d, ".h"); + strcpy(d, name); /* Assume directory path already exists. */ fd = open(depfile_path, O_WRONLY | O_CREAT | O_TRUNC, 0644); @@ -359,28 +355,46 @@ int conf_read_simple(const char *name, int def) if (name) { in = zconf_fopen(name); } else { - struct property *prop; + char *env; name = conf_get_configname(); in = zconf_fopen(name); if (in) goto load; - sym_add_change_count(1); - if (!sym_defconfig_list) + conf_set_changed(true); + + env = getenv("KCONFIG_DEFCONFIG_LIST"); + if (!env) return 1; - for_all_defaults(sym_defconfig_list, prop) { - if (expr_calc_value(prop->visible.expr) == no || - prop->expr->type != E_SYMBOL) - continue; - sym_calc_value(prop->expr->left.sym); - name = sym_get_string_value(prop->expr->left.sym); - in = zconf_fopen(name); + while (1) { + bool is_last; + + while (isspace(*env)) + env++; + + if (!*env) + break; + + p = env; + while (*p && !isspace(*p)) + p++; + + is_last = (*p == '\0'); + + *p = '\0'; + + in = zconf_fopen(env); if (in) { conf_message("using defaults found in %s", - name); + env); goto load; } + + if (is_last) + break; + + env = p + 1; } } if (!in) @@ -425,7 +439,7 @@ load: if (def == S_DEF_USER) { sym = sym_find(line + 2 + strlen(CONFIG_)); if (!sym) { - sym_add_change_count(1); + conf_set_changed(true); continue; } } else { @@ -464,11 +478,11 @@ load: * Reading from include/config/auto.conf * If CONFIG_FOO previously existed in * auto.conf but it is missing now, - * include/config/foo.h must be touched. + * include/config/FOO must be touched. */ conf_touch_dep(line + strlen(CONFIG_)); else - sym_add_change_count(1); + conf_set_changed(true); continue; } @@ -516,7 +530,7 @@ int conf_read(const char *name) int conf_unsaved = 0; int i; - sym_set_change_count(0); + conf_set_changed(false); if (conf_read_simple(name, S_DEF_USER)) { sym_calc_value(modules_sym); @@ -574,7 +588,8 @@ int conf_read(const char *name) } } - sym_add_change_count(conf_warnings || conf_unsaved); + if (conf_warnings || conf_unsaved) + conf_set_changed(true); return 0; } @@ -919,7 +934,7 @@ next: if (is_same(name, tmpname)) { conf_message("No change to %s", name); unlink(tmpname); - sym_set_change_count(0); + conf_set_changed(false); return 0; } @@ -931,7 +946,7 @@ next: conf_message("configuration written to %s", name); - sym_set_change_count(0); + conf_set_changed(false); return 0; } @@ -1099,26 +1114,20 @@ int conf_write_autoconf(int overwrite) return 0; } -static int sym_change_count; +static bool conf_changed; static void (*conf_changed_callback)(void); -void sym_set_change_count(int count) +void conf_set_changed(bool val) { - int _sym_change_count = sym_change_count; - sym_change_count = count; - if (conf_changed_callback && - (bool)_sym_change_count != (bool)count) + if (conf_changed_callback && conf_changed != val) conf_changed_callback(); -} -void sym_add_change_count(int count) -{ - sym_set_change_count(count + sym_change_count); + conf_changed = val; } bool conf_get_changed(void) { - return sym_change_count; + return conf_changed; } void conf_set_changed_callback(void (*fn)(void)) @@ -1126,54 +1135,6 @@ void conf_set_changed_callback(void (*fn)(void)) conf_changed_callback = fn; } -static bool randomize_choice_values(struct symbol *csym) -{ - struct property *prop; - struct symbol *sym; - struct expr *e; - int cnt, def; - - /* - * If choice is mod then we may have more items selected - * and if no then no-one. - * In both cases stop. - */ - if (csym->curr.tri != yes) - return false; - - prop = sym_get_choice_prop(csym); - - /* count entries in choice block */ - cnt = 0; - expr_list_for_each_sym(prop->expr, e, sym) - cnt++; - - /* - * find a random value and set it to yes, - * set the rest to no so we have only one set - */ - def = (rand() % cnt); - - cnt = 0; - expr_list_for_each_sym(prop->expr, e, sym) { - if (def == cnt++) { - sym->def[S_DEF_USER].tri = yes; - csym->def[S_DEF_USER].val = sym; - } - else { - sym->def[S_DEF_USER].tri = no; - } - sym->flags |= SYMBOL_DEF_USER; - /* clear VALID to get value calculated */ - sym->flags &= ~SYMBOL_VALID; - } - csym->flags |= SYMBOL_DEF_USER; - /* clear VALID to get value calculated */ - csym->flags &= ~(SYMBOL_VALID); - - return true; -} - void set_all_choice_values(struct symbol *csym) { struct property *prop; @@ -1193,146 +1154,3 @@ void set_all_choice_values(struct symbol *csym) /* clear VALID to get value calculated */ csym->flags &= ~(SYMBOL_VALID | SYMBOL_NEED_SET_CHOICE_VALUES); } - -bool conf_set_all_new_symbols(enum conf_def_mode mode) -{ - struct symbol *sym, *csym; - int i, cnt, pby, pty, ptm; /* pby: probability of bool = y - * pty: probability of tristate = y - * ptm: probability of tristate = m - */ - - pby = 50; pty = ptm = 33; /* can't go as the default in switch-case - * below, otherwise gcc whines about - * -Wmaybe-uninitialized */ - if (mode == def_random) { - int n, p[3]; - char *env = getenv("KCONFIG_PROBABILITY"); - n = 0; - while( env && *env ) { - char *endp; - int tmp = strtol( env, &endp, 10 ); - if( tmp >= 0 && tmp <= 100 ) { - p[n++] = tmp; - } else { - errno = ERANGE; - perror( "KCONFIG_PROBABILITY" ); - exit( 1 ); - } - env = (*endp == ':') ? endp+1 : endp; - if( n >=3 ) { - break; - } - } - switch( n ) { - case 1: - pby = p[0]; ptm = pby/2; pty = pby-ptm; - break; - case 2: - pty = p[0]; ptm = p[1]; pby = pty + ptm; - break; - case 3: - pby = p[0]; pty = p[1]; ptm = p[2]; - break; - } - - if( pty+ptm > 100 ) { - errno = ERANGE; - perror( "KCONFIG_PROBABILITY" ); - exit( 1 ); - } - } - bool has_changed = false; - - for_all_symbols(i, sym) { - if (sym_has_value(sym) || (sym->flags & SYMBOL_VALID)) - continue; - switch (sym_get_type(sym)) { - case S_BOOLEAN: - case S_TRISTATE: - has_changed = true; - switch (mode) { - case def_yes: - sym->def[S_DEF_USER].tri = yes; - break; - case def_mod: - sym->def[S_DEF_USER].tri = mod; - break; - case def_no: - if (sym->flags & SYMBOL_ALLNOCONFIG_Y) - sym->def[S_DEF_USER].tri = yes; - else - sym->def[S_DEF_USER].tri = no; - break; - case def_random: - sym->def[S_DEF_USER].tri = no; - cnt = rand() % 100; - if (sym->type == S_TRISTATE) { - if (cnt < pty) - sym->def[S_DEF_USER].tri = yes; - else if (cnt < (pty+ptm)) - sym->def[S_DEF_USER].tri = mod; - } else if (cnt < pby) - sym->def[S_DEF_USER].tri = yes; - break; - default: - continue; - } - if (!(sym_is_choice(sym) && mode == def_random)) - sym->flags |= SYMBOL_DEF_USER; - break; - default: - break; - } - - } - - sym_clear_all_valid(); - - /* - * We have different type of choice blocks. - * If curr.tri equals to mod then we can select several - * choice symbols in one block. - * In this case we do nothing. - * If curr.tri equals yes then only one symbol can be - * selected in a choice block and we set it to yes, - * and the rest to no. - */ - if (mode != def_random) { - for_all_symbols(i, csym) { - if ((sym_is_choice(csym) && !sym_has_value(csym)) || - sym_is_choice_value(csym)) - csym->flags |= SYMBOL_NEED_SET_CHOICE_VALUES; - } - } - - for_all_symbols(i, csym) { - if (sym_has_value(csym) || !sym_is_choice(csym)) - continue; - - sym_calc_value(csym); - if (mode == def_random) - has_changed |= randomize_choice_values(csym); - else { - set_all_choice_values(csym); - has_changed = true; - } - } - - return has_changed; -} - -void conf_rewrite_mod_or_yes(enum conf_def_mode mode) -{ - struct symbol *sym; - int i; - tristate old_val = (mode == def_y2m) ? yes : mod; - tristate new_val = (mode == def_y2m) ? mod : yes; - - for_all_symbols(i, sym) { - if (sym_get_type(sym) == S_TRISTATE && - sym->def[S_DEF_USER].tri == old_val) - sym->def[S_DEF_USER].tri = new_val; - } - sym_clear_all_valid(); -} diff --git a/scripts/kconfig/expr.h b/scripts/kconfig/expr.h index 5c3443692f..9c9caca5bd 100644 --- a/scripts/kconfig/expr.h +++ b/scripts/kconfig/expr.h @@ -156,9 +156,6 @@ struct symbol { /* choice values need to be set before calculating this symbol value */ #define SYMBOL_NEED_SET_CHOICE_VALUES 0x100000 -/* Set symbol to y if allnoconfig; used for symbols that hide others */ -#define SYMBOL_ALLNOCONFIG_Y 0x200000 - #define SYMBOL_MAXLENGTH 256 #define SYMBOL_HASHSIZE 9973 @@ -281,15 +278,12 @@ struct jump_key { int index; }; -#define JUMP_NB 9 - extern struct file *file_list; extern struct file *current_file; struct file *lookup_file(const char *name); extern struct symbol symbol_yes, symbol_no, symbol_mod; extern struct symbol *modules_sym; -extern struct symbol *sym_defconfig_list; extern int cdebug; struct expr *expr_alloc_symbol(struct symbol *sym); struct expr *expr_alloc_one(enum expr_type type, struct expr *ce); diff --git a/scripts/kconfig/gconf.c b/scripts/kconfig/gconf.c index 5527482c30..17adabfd6e 100644 --- a/scripts/kconfig/gconf.c +++ b/scripts/kconfig/gconf.c @@ -3,10 +3,6 @@ * Copyright (C) 2002-2003 Romain Lievin <roms@tilp.info> */ -#ifdef HAVE_CONFIG_H -# include <config.h> -#endif - #include <stdlib.h> #include "lkc.h" #include "images.h" @@ -1048,8 +1044,13 @@ static gchar **fill_row(struct menu *menu) g_free(row[i]); bzero(row, sizeof(row)); + ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN; + row[COL_OPTION] = - g_strdup_printf("%s %s", menu_get_prompt(menu), + g_strdup_printf("%s %s %s %s", + ptype == P_COMMENT ? "***" : "", + menu_get_prompt(menu), + ptype == P_COMMENT ? "***" : "", sym && !sym_has_value(sym) ? "(NEW)" : ""); if (opt_mode == OPT_ALL && !menu_is_visible(menu)) @@ -1060,7 +1061,6 @@ static gchar **fill_row(struct menu *menu) else row[COL_COLOR] = g_strdup("Black"); - ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN; switch (ptype) { case P_MENU: row[COL_PIXBUF] = (gchar *) xpm_menu; @@ -1452,9 +1452,6 @@ int main(int ac, char *av[]) gtk_init(&ac, &av); glade_init(); - //add_pixmap_directory (PACKAGE_DATA_DIR "/" PACKAGE "/pixmaps"); - //add_pixmap_directory (PACKAGE_SOURCE_DIR "/pixmaps"); - /* Determine GUI path */ env = getenv(SRCTREE); if (env) diff --git a/scripts/kconfig/internal.h b/scripts/kconfig/internal.h new file mode 100644 index 0000000000..2f7298c21b --- /dev/null +++ b/scripts/kconfig/internal.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef INTERNAL_H +#define INTERNAL_H + +struct menu; + +extern struct menu *current_menu, *current_entry; + +#endif /* INTERNAL_H */ diff --git a/scripts/kconfig/lexer.l b/scripts/kconfig/lexer.l index 240109f965..312cbad2d3 100644 --- a/scripts/kconfig/lexer.l +++ b/scripts/kconfig/lexer.l @@ -12,7 +12,6 @@ #include <stdio.h> #include <stdlib.h> #include <string.h> -#include <unistd.h> #include "lkc.h" #include "parser.tab.h" @@ -92,7 +91,6 @@ n [A-Za-z0-9_-] [ \t]* /* whitespaces */ \\\n /* escaped new line */ \n return T_EOL; -"allnoconfig_y" return T_ALLNOCONFIG_Y; "bool" return T_BOOL; "choice" return T_CHOICE; "comment" return T_COMMENT; @@ -100,7 +98,6 @@ n [A-Za-z0-9_-] "def_bool" return T_DEF_BOOL; "def_tristate" return T_DEF_TRISTATE; "default" return T_DEFAULT; -"defconfig_list" return T_DEFCONFIG_LIST; "depends" return T_DEPENDS; "endchoice" return T_ENDCHOICE; "endif" return T_ENDIF; @@ -115,7 +112,6 @@ n [A-Za-z0-9_-] "menuconfig" return T_MENUCONFIG; "modules" return T_MODULES; "on" return T_ON; -"option" return T_OPTION; "optional" return T_OPTIONAL; "prompt" return T_PROMPT; "range" return T_RANGE; diff --git a/scripts/kconfig/lkc.h b/scripts/kconfig/lkc.h index d4ca829736..fa8c010aa6 100644 --- a/scripts/kconfig/lkc.h +++ b/scripts/kconfig/lkc.h @@ -6,6 +6,10 @@ #ifndef LKC_H #define LKC_H +#include <assert.h> +#include <stdio.h> +#include <stdlib.h> + #include "expr.h" #ifdef __cplusplus @@ -16,10 +20,6 @@ extern "C" { #define SRCTREE "srctree" -#ifndef PACKAGE -#define PACKAGE "linux" -#endif - #ifndef CONFIG_ #define CONFIG_ "CONFIG_" #endif @@ -30,16 +30,6 @@ static inline const char *CONFIG_prefix(void) #undef CONFIG_ #define CONFIG_ CONFIG_prefix() -enum conf_def_mode { - def_default, - def_yes, - def_mod, - def_y2m, - def_m2y, - def_no, - def_random -}; - extern int yylineno; void zconfdump(FILE *out); void zconf_starthelp(void); @@ -51,10 +41,6 @@ const char *zconf_curname(void); /* confdata.c */ const char *conf_get_configname(void); -void sym_set_change_count(int count); -void sym_add_change_count(int count); -bool conf_set_all_new_symbols(enum conf_def_mode mode); -void conf_rewrite_mod_or_yes(enum conf_def_mode mode); void set_all_choice_values(struct symbol *csym); /* confdata.c and expr.c */ @@ -66,23 +52,6 @@ static inline void xfwrite(const void *str, size_t len, size_t count, FILE *out) fprintf(stderr, "Error in writing or end of file.\n"); } -/* menu.c */ -void _menu_init(void); -void menu_warn(struct menu *menu, const char *fmt, ...); -struct menu *menu_add_menu(void); -void menu_end_menu(void); -void menu_add_entry(struct symbol *sym); -void menu_add_dep(struct expr *dep); -void menu_add_visibility(struct expr *dep); -struct property *menu_add_prompt(enum prop_type type, char *prompt, struct expr *dep); -void menu_add_expr(enum prop_type type, struct expr *expr, struct expr *dep); -void menu_add_symbol(enum prop_type type, struct symbol *sym, struct expr *dep); -void menu_add_option_modules(void); -void menu_add_option_defconfig_list(void); -void menu_add_option_allnoconfig_y(void); -void menu_finalize(struct menu *parent); -void menu_set_type(int type); - /* util.c */ struct file *file_lookup(const char *name); void *xmalloc(size_t size); @@ -109,6 +78,33 @@ void str_append(struct gstr *gs, const char *s); void str_printf(struct gstr *gs, const char *fmt, ...); const char *str_get(struct gstr *gs); +/* menu.c */ +void _menu_init(void); +void menu_warn(struct menu *menu, const char *fmt, ...); +struct menu *menu_add_menu(void); +void menu_end_menu(void); +void menu_add_entry(struct symbol *sym); +void menu_add_dep(struct expr *dep); +void menu_add_visibility(struct expr *dep); +struct property *menu_add_prompt(enum prop_type type, char *prompt, struct expr *dep); +void menu_add_expr(enum prop_type type, struct expr *expr, struct expr *dep); +void menu_add_symbol(enum prop_type type, struct symbol *sym, struct expr *dep); +void menu_finalize(struct menu *parent); +void menu_set_type(int type); + +extern struct menu rootmenu; + +bool menu_is_empty(struct menu *menu); +bool menu_is_visible(struct menu *menu); +bool menu_has_prompt(struct menu *menu); +const char *menu_get_prompt(struct menu *menu); +struct menu *menu_get_root_menu(struct menu *menu); +struct menu *menu_get_parent_menu(struct menu *menu); +bool menu_has_help(struct menu *menu); +const char *menu_get_help(struct menu *menu); +struct gstr get_relations_str(struct symbol **sym_arr, struct list_head *head); +void menu_get_ext_help(struct menu *menu, struct gstr *help); + /* symbol.c */ void sym_clear_all_valid(void); struct symbol *sym_choice_default(struct symbol *sym); diff --git a/scripts/kconfig/lkc_proto.h b/scripts/kconfig/lkc_proto.h index f9ab98238a..a11626bdc4 100644 --- a/scripts/kconfig/lkc_proto.h +++ b/scripts/kconfig/lkc_proto.h @@ -8,24 +8,11 @@ int conf_read_simple(const char *name, int); int conf_write_defconfig(const char *name); int conf_write(const char *name); int conf_write_autoconf(int overwrite); +void conf_set_changed(bool val); bool conf_get_changed(void); void conf_set_changed_callback(void (*fn)(void)); void conf_set_message_callback(void (*fn)(const char *s)); -/* menu.c */ -extern struct menu rootmenu; - -bool menu_is_empty(struct menu *menu); -bool menu_is_visible(struct menu *menu); -bool menu_has_prompt(struct menu *menu); -const char * menu_get_prompt(struct menu *menu); -struct menu * menu_get_root_menu(struct menu *menu); -struct menu * menu_get_parent_menu(struct menu *menu); -bool menu_has_help(struct menu *menu); -const char * menu_get_help(struct menu *menu); -struct gstr get_relations_str(struct symbol **sym_arr, struct list_head *head); -void menu_get_ext_help(struct menu *menu, struct gstr *help); - /* symbol.c */ extern struct symbol * symbol_hash[SYMBOL_HASHSIZE]; diff --git a/scripts/kconfig/lxdialog/util.c b/scripts/kconfig/lxdialog/util.c index 1b490d4af0..3f78fb2651 100644 --- a/scripts/kconfig/lxdialog/util.c +++ b/scripts/kconfig/lxdialog/util.c @@ -363,7 +363,7 @@ void print_title(WINDOW *dialog, const char *title, int width) /* * Print a string of text in a window, automatically wrap around to the * next line if the string is too long to fit on one line. Newline - * characters '\n' are propperly processed. We start on a new line + * characters '\n' are properly processed. We start on a new line * if there is no room for at least 4 nonblanks following a double-space. */ void print_autowrap(WINDOW * win, const char *prompt, int width, int y, int x) @@ -541,7 +541,7 @@ int first_alpha(const char *string, const char *exempt) * lxdialog suggest <ESC> <ESC> which is correctly translated to two * times esc. But then we need to ignore the second esc to avoid stepping * out one menu too much. Filter away all escaped key sequences since - * keypad(FALSE) turn off ncurses support for escape sequences - and thats + * keypad(FALSE) turn off ncurses support for escape sequences - and that's * needed to make notimeout() do as expected. */ int on_key_esc(WINDOW *win) diff --git a/scripts/kconfig/mconf-cfg.sh b/scripts/kconfig/mconf-cfg.sh index aa68ec9562..b520e407a8 100755 --- a/scripts/kconfig/mconf-cfg.sh +++ b/scripts/kconfig/mconf-cfg.sh @@ -33,7 +33,9 @@ if [ -f /usr/include/ncurses/ncurses.h ]; then exit 0 fi -if [ -f /usr/include/ncurses.h ]; then +# As a final fallback before giving up, check if $HOSTCC knows of a default +# ncurses installation (e.g. from a vendor-specific sysroot). +if echo '#include <ncurses.h>' | ${HOSTCC} -E - >/dev/null 2>&1; then echo cflags=\"-D_GNU_SOURCE\" echo libs=\"-lncurses\" exit 0 diff --git a/scripts/kconfig/mconf.c b/scripts/kconfig/mconf.c index 4063dbc1b9..9d3cf51056 100644 --- a/scripts/kconfig/mconf.c +++ b/scripts/kconfig/mconf.c @@ -22,6 +22,8 @@ #include "lkc.h" #include "lxdialog/dialog.h" +#define JUMP_NB 9 + static const char mconf_readme[] = "Overview\n" "--------\n" @@ -297,17 +299,12 @@ static char filename[PATH_MAX+1]; static void set_config_filename(const char *config_filename) { static char menu_backtitle[PATH_MAX+128]; - int size; - size = snprintf(menu_backtitle, sizeof(menu_backtitle), - "%s - %s", config_filename, rootmenu.prompt->text); - if (size >= sizeof(menu_backtitle)) - menu_backtitle[sizeof(menu_backtitle)-1] = '\0'; + snprintf(menu_backtitle, sizeof(menu_backtitle), "%s - %s", + config_filename, rootmenu.prompt->text); set_dialog_backtitle(menu_backtitle); - size = snprintf(filename, sizeof(filename), "%s", config_filename); - if (size >= sizeof(filename)) - filename[sizeof(filename)-1] = '\0'; + snprintf(filename, sizeof(filename), "%s", config_filename); } struct subtitle_part { @@ -908,7 +905,7 @@ static void conf_load(void) return; if (!conf_read(dialog_input_result)) { set_config_filename(dialog_input_result); - sym_set_change_count(1); + conf_set_changed(true); return; } show_textbox(NULL, "File does not exist!", 5, 38); diff --git a/scripts/kconfig/menu.c b/scripts/kconfig/menu.c index a5fbd6ccc0..606ba8a63c 100644 --- a/scripts/kconfig/menu.c +++ b/scripts/kconfig/menu.c @@ -9,6 +9,7 @@ #include <string.h> #include "lkc.h" +#include "internal.h" static const char nohelp_text[] = "There is no help available for this option."; @@ -211,28 +212,6 @@ void menu_add_symbol(enum prop_type type, struct symbol *sym, struct expr *dep) menu_add_prop(type, expr_alloc_symbol(sym), dep); } -void menu_add_option_modules(void) -{ - if (modules_sym) - zconf_error("symbol '%s' redefines option 'modules' already defined by symbol '%s'", - current_entry->sym->name, modules_sym->name); - modules_sym = current_entry->sym; -} - -void menu_add_option_defconfig_list(void) -{ - if (!sym_defconfig_list) - sym_defconfig_list = current_entry->sym; - else if (sym_defconfig_list != current_entry->sym) - zconf_error("trying to redefine defconfig symbol"); - sym_defconfig_list->flags |= SYMBOL_NO_WRITE; -} - -void menu_add_option_allnoconfig_y(void) -{ - current_entry->sym->flags |= SYMBOL_ALLNOCONFIG_Y; -} - static int menu_validate_number(struct symbol *sym, struct symbol *sym2) { return sym2->type == S_INT || sym2->type == S_HEX || diff --git a/scripts/kconfig/nconf.c b/scripts/kconfig/nconf.c index daf1c1506e..7b371bd7fb 100644 --- a/scripts/kconfig/nconf.c +++ b/scripts/kconfig/nconf.c @@ -268,7 +268,7 @@ static int mwin_max_cols; static MENU *curses_menu; static ITEM *curses_menu_items[MAX_MENU_ITEMS]; static struct mitem k_menu_items[MAX_MENU_ITEMS]; -static int items_num; +static unsigned int items_num; static int global_exit; /* the currently selected button */ static const char *current_instructions = menu_instructions; @@ -370,18 +370,18 @@ static void print_function_line(void) int lines = getmaxy(stdscr); for (i = 0; i < function_keys_num; i++) { - (void) wattrset(main_window, attributes[FUNCTION_HIGHLIGHT]); + wattrset(main_window, attr_function_highlight); mvwprintw(main_window, lines-3, offset, "%s", function_keys[i].key_str); - (void) wattrset(main_window, attributes[FUNCTION_TEXT]); + wattrset(main_window, attr_function_text); offset += strlen(function_keys[i].key_str); mvwprintw(main_window, lines-3, offset, "%s", function_keys[i].func); offset += strlen(function_keys[i].func) + skip; } - (void) wattrset(main_window, attributes[NORMAL]); + wattrset(main_window, attr_normal); } /* help */ @@ -496,16 +496,20 @@ typedef enum {MATCH_TINKER_PATTERN_UP, MATCH_TINKER_PATTERN_DOWN, /* return the index of the matched item, or -1 if no such item exists */ static int get_mext_match(const char *match_str, match_f flag) { - int match_start = item_index(current_item(curses_menu)); - int index; + int match_start, index; + + /* Do not search if the menu is empty (i.e. items_num == 0) */ + match_start = item_index(current_item(curses_menu)); + if (match_start == ERR) + return -1; if (flag == FIND_NEXT_MATCH_DOWN) ++match_start; else if (flag == FIND_NEXT_MATCH_UP) --match_start; + match_start = (match_start + items_num) % items_num; index = match_start; - index = (index + items_num) % items_num; while (true) { char *str = k_menu_items[index].str; if (strcasestr(str, match_str) != NULL) @@ -627,19 +631,12 @@ static int item_is_tag(char tag) static char filename[PATH_MAX+1]; static char menu_backtitle[PATH_MAX+128]; -static const char *set_config_filename(const char *config_filename) +static void set_config_filename(const char *config_filename) { - int size; + snprintf(menu_backtitle, sizeof(menu_backtitle), "%s - %s", + config_filename, rootmenu.prompt->text); - size = snprintf(menu_backtitle, sizeof(menu_backtitle), - "%s - %s", config_filename, rootmenu.prompt->text); - if (size >= sizeof(menu_backtitle)) - menu_backtitle[sizeof(menu_backtitle)-1] = '\0'; - - size = snprintf(filename, sizeof(filename), "%s", config_filename); - if (size >= sizeof(filename)) - filename[sizeof(filename)-1] = '\0'; - return menu_backtitle; + snprintf(filename, sizeof(filename), "%s", config_filename); } /* return = 0 means we are successful. @@ -755,7 +752,6 @@ static void build_conf(struct menu *menu) switch (ptype) { case P_MENU: child_count++; - prompt = prompt; if (single_menu_mode) { item_make(menu, 'm', "%s%*c%s", @@ -957,16 +953,15 @@ static void show_menu(const char *prompt, const char *instructions, current_instructions = instructions; clear(); - (void) wattrset(main_window, attributes[NORMAL]); - print_in_middle(stdscr, 1, 0, getmaxx(stdscr), + print_in_middle(stdscr, 1, getmaxx(stdscr), menu_backtitle, - attributes[MAIN_HEADING]); + attr_main_heading); - (void) wattrset(main_window, attributes[MAIN_MENU_BOX]); + wattrset(main_window, attr_main_menu_box); box(main_window, 0, 0); - (void) wattrset(main_window, attributes[MAIN_MENU_HEADING]); + wattrset(main_window, attr_main_menu_heading); mvwprintw(main_window, 0, 3, " %s ", prompt); - (void) wattrset(main_window, attributes[NORMAL]); + wattrset(main_window, attr_normal); set_menu_items(curses_menu, curses_menu_items); @@ -1069,7 +1064,6 @@ static int do_match(int key, struct match_state *state, int *ans) static void conf(struct menu *menu) { struct menu *submenu = NULL; - const char *prompt = menu_get_prompt(menu); struct symbol *sym; int res; int current_index = 0; @@ -1087,9 +1081,8 @@ static void conf(struct menu *menu) if (!child_count) break; - show_menu(prompt ? prompt : "Main Menu", - menu_instructions, - current_index, &last_top_row); + show_menu(menu_get_prompt(menu), menu_instructions, + current_index, &last_top_row); keypad((menu_win(curses_menu)), TRUE); while (!global_exit) { if (match_state.in_search) { @@ -1405,7 +1398,7 @@ static void conf_load(void) return; if (!conf_read(dialog_input_result)) { set_config_filename(dialog_input_result); - sym_set_change_count(1); + conf_set_changed(true); return; } btn_dialog(main_window, "File does not exist!", 0); @@ -1524,9 +1517,9 @@ int main(int ac, char **av) menu_opts_on(curses_menu, O_NONCYCLIC); menu_opts_on(curses_menu, O_IGNORECASE); set_menu_mark(curses_menu, " "); - set_menu_fore(curses_menu, attributes[MAIN_MENU_FORE]); - set_menu_back(curses_menu, attributes[MAIN_MENU_BACK]); - set_menu_grey(curses_menu, attributes[MAIN_MENU_GREY]); + set_menu_fore(curses_menu, attr_main_menu_fore); + set_menu_back(curses_menu, attr_main_menu_back); + set_menu_grey(curses_menu, attr_main_menu_grey); set_config_filename(conf_get_configname()); setup_windows(); diff --git a/scripts/kconfig/nconf.gui.c b/scripts/kconfig/nconf.gui.c index 77f525a861..9aedf40f1d 100644 --- a/scripts/kconfig/nconf.gui.c +++ b/scripts/kconfig/nconf.gui.c @@ -7,169 +7,120 @@ #include "nconf.h" #include "lkc.h" -/* a list of all the different widgets we use */ -attributes_t attributes[ATTR_MAX+1] = {0}; - -/* available colors: - COLOR_BLACK 0 - COLOR_RED 1 - COLOR_GREEN 2 - COLOR_YELLOW 3 - COLOR_BLUE 4 - COLOR_MAGENTA 5 - COLOR_CYAN 6 - COLOR_WHITE 7 - */ -static void set_normal_colors(void) -{ - init_pair(NORMAL, -1, -1); - init_pair(MAIN_HEADING, COLOR_MAGENTA, -1); - - /* FORE is for the selected item */ - init_pair(MAIN_MENU_FORE, -1, -1); - /* BACK for all the rest */ - init_pair(MAIN_MENU_BACK, -1, -1); - init_pair(MAIN_MENU_GREY, -1, -1); - init_pair(MAIN_MENU_HEADING, COLOR_GREEN, -1); - init_pair(MAIN_MENU_BOX, COLOR_YELLOW, -1); - - init_pair(SCROLLWIN_TEXT, -1, -1); - init_pair(SCROLLWIN_HEADING, COLOR_GREEN, -1); - init_pair(SCROLLWIN_BOX, COLOR_YELLOW, -1); - - init_pair(DIALOG_TEXT, -1, -1); - init_pair(DIALOG_BOX, COLOR_YELLOW, -1); - init_pair(DIALOG_MENU_BACK, COLOR_YELLOW, -1); - init_pair(DIALOG_MENU_FORE, COLOR_RED, -1); - - init_pair(INPUT_BOX, COLOR_YELLOW, -1); - init_pair(INPUT_HEADING, COLOR_GREEN, -1); - init_pair(INPUT_TEXT, -1, -1); - init_pair(INPUT_FIELD, -1, -1); - - init_pair(FUNCTION_HIGHLIGHT, -1, -1); - init_pair(FUNCTION_TEXT, COLOR_YELLOW, -1); -} - -/* available attributes: - A_NORMAL Normal display (no highlight) - A_STANDOUT Best highlighting mode of the terminal. - A_UNDERLINE Underlining - A_REVERSE Reverse video - A_BLINK Blinking - A_DIM Half bright - A_BOLD Extra bright or bold - A_PROTECT Protected mode - A_INVIS Invisible or blank mode - A_ALTCHARSET Alternate character set - A_CHARTEXT Bit-mask to extract a character - COLOR_PAIR(n) Color-pair number n - */ -static void normal_color_theme(void) -{ - /* automatically add color... */ -#define mkattr(name, attr) do { \ -attributes[name] = attr | COLOR_PAIR(name); } while (0) - mkattr(NORMAL, NORMAL); - mkattr(MAIN_HEADING, A_BOLD | A_UNDERLINE); - - mkattr(MAIN_MENU_FORE, A_REVERSE); - mkattr(MAIN_MENU_BACK, A_NORMAL); - mkattr(MAIN_MENU_GREY, A_NORMAL); - mkattr(MAIN_MENU_HEADING, A_BOLD); - mkattr(MAIN_MENU_BOX, A_NORMAL); - - mkattr(SCROLLWIN_TEXT, A_NORMAL); - mkattr(SCROLLWIN_HEADING, A_BOLD); - mkattr(SCROLLWIN_BOX, A_BOLD); - - mkattr(DIALOG_TEXT, A_BOLD); - mkattr(DIALOG_BOX, A_BOLD); - mkattr(DIALOG_MENU_FORE, A_STANDOUT); - mkattr(DIALOG_MENU_BACK, A_NORMAL); - - mkattr(INPUT_BOX, A_NORMAL); - mkattr(INPUT_HEADING, A_BOLD); - mkattr(INPUT_TEXT, A_NORMAL); - mkattr(INPUT_FIELD, A_UNDERLINE); - - mkattr(FUNCTION_HIGHLIGHT, A_BOLD); - mkattr(FUNCTION_TEXT, A_REVERSE); -} - -static void no_colors_theme(void) -{ - /* automatically add highlight, no color */ -#define mkattrn(name, attr) { attributes[name] = attr; } - - mkattrn(NORMAL, NORMAL); - mkattrn(MAIN_HEADING, A_BOLD | A_UNDERLINE); - - mkattrn(MAIN_MENU_FORE, A_STANDOUT); - mkattrn(MAIN_MENU_BACK, A_NORMAL); - mkattrn(MAIN_MENU_GREY, A_NORMAL); - mkattrn(MAIN_MENU_HEADING, A_BOLD); - mkattrn(MAIN_MENU_BOX, A_NORMAL); - - mkattrn(SCROLLWIN_TEXT, A_NORMAL); - mkattrn(SCROLLWIN_HEADING, A_BOLD); - mkattrn(SCROLLWIN_BOX, A_BOLD); - - mkattrn(DIALOG_TEXT, A_NORMAL); - mkattrn(DIALOG_BOX, A_BOLD); - mkattrn(DIALOG_MENU_FORE, A_STANDOUT); - mkattrn(DIALOG_MENU_BACK, A_NORMAL); - - mkattrn(INPUT_BOX, A_BOLD); - mkattrn(INPUT_HEADING, A_BOLD); - mkattrn(INPUT_TEXT, A_NORMAL); - mkattrn(INPUT_FIELD, A_UNDERLINE); - - mkattrn(FUNCTION_HIGHLIGHT, A_BOLD); - mkattrn(FUNCTION_TEXT, A_REVERSE); -} +int attr_normal; +int attr_main_heading; +int attr_main_menu_box; +int attr_main_menu_fore; +int attr_main_menu_back; +int attr_main_menu_grey; +int attr_main_menu_heading; +int attr_scrollwin_text; +int attr_scrollwin_heading; +int attr_scrollwin_box; +int attr_dialog_text; +int attr_dialog_menu_fore; +int attr_dialog_menu_back; +int attr_dialog_box; +int attr_input_box; +int attr_input_heading; +int attr_input_text; +int attr_input_field; +int attr_function_text; +int attr_function_highlight; + +#define COLOR_ATTR(_at, _fg, _bg, _hl) \ + { .attr = &(_at), .has_color = true, .color_fg = _fg, .color_bg = _bg, .highlight = _hl } +#define NO_COLOR_ATTR(_at, _hl) \ + { .attr = &(_at), .has_color = false, .highlight = _hl } +#define COLOR_DEFAULT -1 + +struct nconf_attr_param { + int *attr; + bool has_color; + int color_fg; + int color_bg; + int highlight; +}; + +static const struct nconf_attr_param color_theme_params[] = { + COLOR_ATTR(attr_normal, COLOR_DEFAULT, COLOR_DEFAULT, A_NORMAL), + COLOR_ATTR(attr_main_heading, COLOR_MAGENTA, COLOR_DEFAULT, A_BOLD | A_UNDERLINE), + COLOR_ATTR(attr_main_menu_box, COLOR_YELLOW, COLOR_DEFAULT, A_NORMAL), + COLOR_ATTR(attr_main_menu_fore, COLOR_DEFAULT, COLOR_DEFAULT, A_REVERSE), + COLOR_ATTR(attr_main_menu_back, COLOR_DEFAULT, COLOR_DEFAULT, A_NORMAL), + COLOR_ATTR(attr_main_menu_grey, COLOR_DEFAULT, COLOR_DEFAULT, A_NORMAL), + COLOR_ATTR(attr_main_menu_heading, COLOR_GREEN, COLOR_DEFAULT, A_BOLD), + COLOR_ATTR(attr_scrollwin_text, COLOR_DEFAULT, COLOR_DEFAULT, A_NORMAL), + COLOR_ATTR(attr_scrollwin_heading, COLOR_GREEN, COLOR_DEFAULT, A_BOLD), + COLOR_ATTR(attr_scrollwin_box, COLOR_YELLOW, COLOR_DEFAULT, A_BOLD), + COLOR_ATTR(attr_dialog_text, COLOR_DEFAULT, COLOR_DEFAULT, A_BOLD), + COLOR_ATTR(attr_dialog_menu_fore, COLOR_RED, COLOR_DEFAULT, A_STANDOUT), + COLOR_ATTR(attr_dialog_menu_back, COLOR_YELLOW, COLOR_DEFAULT, A_NORMAL), + COLOR_ATTR(attr_dialog_box, COLOR_YELLOW, COLOR_DEFAULT, A_BOLD), + COLOR_ATTR(attr_input_box, COLOR_YELLOW, COLOR_DEFAULT, A_NORMAL), + COLOR_ATTR(attr_input_heading, COLOR_GREEN, COLOR_DEFAULT, A_BOLD), + COLOR_ATTR(attr_input_text, COLOR_DEFAULT, COLOR_DEFAULT, A_NORMAL), + COLOR_ATTR(attr_input_field, COLOR_DEFAULT, COLOR_DEFAULT, A_UNDERLINE), + COLOR_ATTR(attr_function_text, COLOR_YELLOW, COLOR_DEFAULT, A_REVERSE), + COLOR_ATTR(attr_function_highlight, COLOR_DEFAULT, COLOR_DEFAULT, A_BOLD), + { /* sentinel */ } +}; + +static const struct nconf_attr_param no_color_theme_params[] = { + NO_COLOR_ATTR(attr_normal, A_NORMAL), + NO_COLOR_ATTR(attr_main_heading, A_BOLD | A_UNDERLINE), + NO_COLOR_ATTR(attr_main_menu_box, A_NORMAL), + NO_COLOR_ATTR(attr_main_menu_fore, A_STANDOUT), + NO_COLOR_ATTR(attr_main_menu_back, A_NORMAL), + NO_COLOR_ATTR(attr_main_menu_grey, A_NORMAL), + NO_COLOR_ATTR(attr_main_menu_heading, A_BOLD), + NO_COLOR_ATTR(attr_scrollwin_text, A_NORMAL), + NO_COLOR_ATTR(attr_scrollwin_heading, A_BOLD), + NO_COLOR_ATTR(attr_scrollwin_box, A_BOLD), + NO_COLOR_ATTR(attr_dialog_text, A_NORMAL), + NO_COLOR_ATTR(attr_dialog_menu_fore, A_STANDOUT), + NO_COLOR_ATTR(attr_dialog_menu_back, A_NORMAL), + NO_COLOR_ATTR(attr_dialog_box, A_BOLD), + NO_COLOR_ATTR(attr_input_box, A_BOLD), + NO_COLOR_ATTR(attr_input_heading, A_BOLD), + NO_COLOR_ATTR(attr_input_text, A_NORMAL), + NO_COLOR_ATTR(attr_input_field, A_UNDERLINE), + NO_COLOR_ATTR(attr_function_text, A_REVERSE), + NO_COLOR_ATTR(attr_function_highlight, A_BOLD), + { /* sentinel */ } +}; void set_colors(void) { - start_color(); - use_default_colors(); - set_normal_colors(); + const struct nconf_attr_param *p; + int pair = 0; + if (has_colors()) { - normal_color_theme(); + start_color(); + use_default_colors(); + p = color_theme_params; } else { - /* give defaults */ - no_colors_theme(); + p = no_color_theme_params; } -} + for (; p->attr; p++) { + int attr = p->highlight; + + if (p->has_color) { + pair++; + init_pair(pair, p->color_fg, p->color_bg); + attr |= COLOR_PAIR(pair); + } + + *p->attr = attr; + } +} /* this changes the windows attributes !!! */ -void print_in_middle(WINDOW *win, - int starty, - int startx, - int width, - const char *string, - chtype color) -{ int length, x, y; - float temp; - - - if (win == NULL) - win = stdscr; - getyx(win, y, x); - if (startx != 0) - x = startx; - if (starty != 0) - y = starty; - if (width == 0) - width = 80; - - length = strlen(string); - temp = (width - length) / 2; - x = startx + (int)temp; - (void) wattrset(win, color); - mvwprintw(win, y, x, "%s", string); - refresh(); +void print_in_middle(WINDOW *win, int y, int width, const char *str, int attrs) +{ + wattrset(win, attrs); + mvwprintw(win, y, (width - strlen(str)) / 2, "%s", str); } int get_line_no(const char *text) @@ -294,14 +245,14 @@ int btn_dialog(WINDOW *main_window, const char *msg, int btn_num, ...) msg_win = derwin(win, win_rows-2, msg_width, 1, 1+(total_width+2-msg_width)/2); - set_menu_fore(menu, attributes[DIALOG_MENU_FORE]); - set_menu_back(menu, attributes[DIALOG_MENU_BACK]); + set_menu_fore(menu, attr_dialog_menu_fore); + set_menu_back(menu, attr_dialog_menu_back); - (void) wattrset(win, attributes[DIALOG_BOX]); + wattrset(win, attr_dialog_box); box(win, 0, 0); /* print message */ - (void) wattrset(msg_win, attributes[DIALOG_TEXT]); + wattrset(msg_win, attr_dialog_text); fill_window(msg_win, msg); set_menu_win(menu, win); @@ -405,16 +356,16 @@ int dialog_inputbox(WINDOW *main_window, form_win = derwin(win, 1, prompt_width, prompt_lines+3, 2); keypad(form_win, TRUE); - (void) wattrset(form_win, attributes[INPUT_FIELD]); + wattrset(form_win, attr_input_field); - (void) wattrset(win, attributes[INPUT_BOX]); + wattrset(win, attr_input_box); box(win, 0, 0); - (void) wattrset(win, attributes[INPUT_HEADING]); + wattrset(win, attr_input_heading); if (title) mvwprintw(win, 0, 3, "%s", title); /* print message */ - (void) wattrset(prompt_win, attributes[INPUT_TEXT]); + wattrset(prompt_win, attr_input_text); fill_window(prompt_win, prompt); mvwprintw(form_win, 0, 0, "%*s", prompt_width, " "); @@ -576,7 +527,7 @@ void show_scroll_win(WINDOW *main_window, /* create the pad */ pad = newpad(total_lines+10, total_cols+10); - (void) wattrset(pad, attributes[SCROLLWIN_TEXT]); + wattrset(pad, attr_scrollwin_text); fill_window(pad, text); win_lines = min(total_lines+4, lines-2); @@ -591,9 +542,9 @@ void show_scroll_win(WINDOW *main_window, win = newwin(win_lines, win_cols, y, x); keypad(win, TRUE); /* show the help in the help window, and show the help panel */ - (void) wattrset(win, attributes[SCROLLWIN_BOX]); + wattrset(win, attr_scrollwin_box); box(win, 0, 0); - (void) wattrset(win, attributes[SCROLLWIN_HEADING]); + wattrset(win, attr_scrollwin_heading); mvwprintw(win, 0, 3, " %s ", title); panel = new_panel(win); @@ -604,10 +555,9 @@ void show_scroll_win(WINDOW *main_window, text_cols, 0); print_in_middle(win, text_lines+2, - 0, text_cols, "<OK>", - attributes[DIALOG_MENU_FORE]); + attr_dialog_menu_fore); wrefresh(win); res = wgetch(win); diff --git a/scripts/kconfig/nconf.h b/scripts/kconfig/nconf.h index fa5245eb93..6f925bc74e 100644 --- a/scripts/kconfig/nconf.h +++ b/scripts/kconfig/nconf.h @@ -32,30 +32,26 @@ typeof(b) _b = b;\ _a < _b ? _a : _b; }) -typedef enum { - NORMAL = 1, - MAIN_HEADING, - MAIN_MENU_BOX, - MAIN_MENU_FORE, - MAIN_MENU_BACK, - MAIN_MENU_GREY, - MAIN_MENU_HEADING, - SCROLLWIN_TEXT, - SCROLLWIN_HEADING, - SCROLLWIN_BOX, - DIALOG_TEXT, - DIALOG_MENU_FORE, - DIALOG_MENU_BACK, - DIALOG_BOX, - INPUT_BOX, - INPUT_HEADING, - INPUT_TEXT, - INPUT_FIELD, - FUNCTION_TEXT, - FUNCTION_HIGHLIGHT, - ATTR_MAX -} attributes_t; -extern attributes_t attributes[]; +extern int attr_normal; +extern int attr_main_heading; +extern int attr_main_menu_box; +extern int attr_main_menu_fore; +extern int attr_main_menu_back; +extern int attr_main_menu_grey; +extern int attr_main_menu_heading; +extern int attr_scrollwin_text; +extern int attr_scrollwin_heading; +extern int attr_scrollwin_box; +extern int attr_dialog_text; +extern int attr_dialog_menu_fore; +extern int attr_dialog_menu_back; +extern int attr_dialog_box; +extern int attr_input_box; +extern int attr_input_heading; +extern int attr_input_text; +extern int attr_input_field; +extern int attr_function_text; +extern int attr_function_highlight; typedef enum { F_HELP = 1, @@ -72,12 +68,7 @@ typedef enum { void set_colors(void); /* this changes the windows attributes !!! */ -void print_in_middle(WINDOW *win, - int starty, - int startx, - int width, - const char *string, - chtype color); +void print_in_middle(WINDOW *win, int y, int width, const char *str, int attrs); int get_line_length(const char *line); int get_line_no(const char *text); const char *get_line(const char *text, int line_no); diff --git a/scripts/kconfig/parser.y b/scripts/kconfig/parser.y index 190f1117f3..2af7ce4e15 100644 --- a/scripts/kconfig/parser.y +++ b/scripts/kconfig/parser.y @@ -12,6 +12,7 @@ #include <stdbool.h> #include "lkc.h" +#include "internal.h" #define printd(mask, fmt...) if (cdebug & (mask)) printf(fmt) @@ -28,7 +29,7 @@ static bool zconf_endtoken(const char *tokenname, struct symbol *symbol_hash[SYMBOL_HASHSIZE]; -static struct menu *current_menu, *current_entry; +struct menu *current_menu, *current_entry; %} @@ -45,7 +46,6 @@ static struct menu *current_menu, *current_entry; %token <string> T_HELPTEXT %token <string> T_WORD %token <string> T_WORD_QUOTE -%token T_ALLNOCONFIG_Y %token T_BOOL %token T_CHOICE %token T_CLOSE_PAREN @@ -53,7 +53,6 @@ static struct menu *current_menu, *current_entry; %token T_COMMENT %token T_CONFIG %token T_DEFAULT -%token T_DEFCONFIG_LIST %token T_DEF_BOOL %token T_DEF_TRISTATE %token T_DEPENDS @@ -71,7 +70,6 @@ static struct menu *current_menu, *current_entry; %token T_MODULES %token T_ON %token T_OPEN_PAREN -%token T_OPTION %token T_OPTIONAL %token T_PLUS_EQUAL %token T_PROMPT @@ -218,19 +216,12 @@ config_option: T_RANGE symbol symbol if_expr T_EOL printd(DEBUG_PARSE, "%s:%d:range\n", zconf_curname(), zconf_lineno()); }; -config_option: T_OPTION T_MODULES T_EOL +config_option: T_MODULES T_EOL { - menu_add_option_modules(); -}; - -config_option: T_OPTION T_DEFCONFIG_LIST T_EOL -{ - menu_add_option_defconfig_list(); -}; - -config_option: T_OPTION T_ALLNOCONFIG_Y T_EOL -{ - menu_add_option_allnoconfig_y(); + if (modules_sym) + zconf_error("symbol '%s' redefines option 'modules' already defined by symbol '%s'", + current_entry->sym->name, modules_sym->name); + modules_sym = current_entry->sym; }; /* choice entry */ @@ -517,7 +508,7 @@ void conf_parse(const char *name) } if (yynerrs) exit(1); - sym_set_change_count(1); + conf_set_changed(true); } static bool zconf_endtoken(const char *tokenname, @@ -723,5 +714,3 @@ void zconfdump(FILE *out) } } } - -#include "menu.c" diff --git a/scripts/kconfig/preprocess.c b/scripts/kconfig/preprocess.c index 0243086fb1..0590f86df6 100644 --- a/scripts/kconfig/preprocess.c +++ b/scripts/kconfig/preprocess.c @@ -114,7 +114,7 @@ static char *do_error_if(int argc, char *argv[]) if (!strcmp(argv[0], "y")) pperror("%s", argv[1]); - return NULL; + return xstrdup(""); } static char *do_filename(int argc, char *argv[]) diff --git a/scripts/kconfig/qconf-cfg.sh b/scripts/kconfig/qconf-cfg.sh index 02ccc0ae10..fa564cd795 100755 --- a/scripts/kconfig/qconf-cfg.sh +++ b/scripts/kconfig/qconf-cfg.sh @@ -2,7 +2,6 @@ # SPDX-License-Identifier: GPL-2.0 PKG="Qt5Core Qt5Gui Qt5Widgets" -PKG2="QtCore QtGui" if [ -z "$(command -v pkg-config)" ]; then echo >&2 "*" @@ -12,21 +11,14 @@ if [ -z "$(command -v pkg-config)" ]; then fi if pkg-config --exists $PKG; then - echo cflags=\"-std=c++11 -fPIC $(pkg-config --cflags Qt5Core Qt5Gui Qt5Widgets)\" + echo cflags=\"-std=c++11 -fPIC $(pkg-config --cflags $PKG)\" echo libs=\"$(pkg-config --libs $PKG)\" echo moc=\"$(pkg-config --variable=host_bins Qt5Core)/moc\" exit 0 fi -if pkg-config --exists $PKG2; then - echo cflags=\"$(pkg-config --cflags $PKG2)\" - echo libs=\"$(pkg-config --libs $PKG2)\" - echo moc=\"$(pkg-config --variable=moc_location QtCore)\" - exit 0 -fi - echo >&2 "*" -echo >&2 "* Could not find Qt via pkg-config." -echo >&2 "* Please install either Qt 4.8 or 5.x. and make sure it's in PKG_CONFIG_PATH" +echo >&2 "* Could not find Qt5 via pkg-config." +echo >&2 "* Please install Qt5 and make sure it's in PKG_CONFIG_PATH" echo >&2 "*" exit 1 diff --git a/scripts/kconfig/qconf.cc b/scripts/kconfig/qconf.cc index 8638785328..78087b2d9a 100644 --- a/scripts/kconfig/qconf.cc +++ b/scripts/kconfig/qconf.cc @@ -83,14 +83,6 @@ QIcon ConfigItem::menuIcon; QIcon ConfigItem::menubackIcon; /* - * set the new data - * TODO check the value - */ -void ConfigItem::okRename(int col) -{ -} - -/* * update the displayed of a menu entry */ void ConfigItem::updateMenu(void) @@ -130,6 +122,7 @@ void ConfigItem::updateMenu(void) goto set_prompt; case P_COMMENT: setIcon(promptColIdx, QIcon()); + prompt = "*** " + prompt + " ***"; goto set_prompt; default: ; @@ -147,9 +140,6 @@ void ConfigItem::updateMenu(void) if (!sym_is_changeable(sym) && list->optMode == normalOpt) { setIcon(promptColIdx, QIcon()); - setText(noColIdx, QString()); - setText(modColIdx, QString()); - setText(yesColIdx, QString()); break; } expr = sym_get_tristate_value(sym); @@ -159,12 +149,10 @@ void ConfigItem::updateMenu(void) setIcon(promptColIdx, choiceYesIcon); else setIcon(promptColIdx, symbolYesIcon); - setText(yesColIdx, "Y"); ch = 'Y'; break; case mod: setIcon(promptColIdx, symbolModIcon); - setText(modColIdx, "M"); ch = 'M'; break; default: @@ -172,31 +160,16 @@ void ConfigItem::updateMenu(void) setIcon(promptColIdx, choiceNoIcon); else setIcon(promptColIdx, symbolNoIcon); - setText(noColIdx, "N"); ch = 'N'; break; } - if (expr != no) - setText(noColIdx, sym_tristate_within_range(sym, no) ? "_" : 0); - if (expr != mod) - setText(modColIdx, sym_tristate_within_range(sym, mod) ? "_" : 0); - if (expr != yes) - setText(yesColIdx, sym_tristate_within_range(sym, yes) ? "_" : 0); setText(dataColIdx, QChar(ch)); break; case S_INT: case S_HEX: case S_STRING: - const char* data; - - data = sym_get_string_value(sym); - - setText(dataColIdx, data); - if (type == S_STRING) - prompt = QString("%1: %2").arg(prompt).arg(data); - else - prompt = QString("(%2) %1").arg(prompt).arg(data); + setText(dataColIdx, sym_get_string_value(sym)); break; } if (!sym_has_value(sym) && visible) @@ -237,6 +210,17 @@ void ConfigItem::init(void) if (list->mode != fullMode) setExpanded(true); sym_calc_value(menu->sym); + + if (menu->sym) { + enum symbol_type type = menu->sym->type; + + // Allow to edit "int", "hex", and "string" in-place in + // the data column. Unfortunately, you cannot specify + // the flags per column. Set ItemIsEditable for all + // columns here, and check the column in createEditor(). + if (type == S_INT || type == S_HEX || type == S_STRING) + setFlags(flags() | Qt::ItemIsEditable); + } } updateMenu(); } @@ -257,46 +241,65 @@ ConfigItem::~ConfigItem(void) } } -ConfigLineEdit::ConfigLineEdit(ConfigView* parent) - : Parent(parent) +QWidget *ConfigItemDelegate::createEditor(QWidget *parent, + const QStyleOptionViewItem &option, + const QModelIndex &index) const { - connect(this, SIGNAL(editingFinished()), SLOT(hide())); -} + ConfigItem *item; -void ConfigLineEdit::show(ConfigItem* i) -{ - item = i; - if (sym_get_string_value(item->menu->sym)) - setText(sym_get_string_value(item->menu->sym)); - else - setText(QString()); - Parent::show(); - setFocus(); + // Only the data column is editable + if (index.column() != dataColIdx) + return nullptr; + + // You cannot edit invisible menus + item = static_cast<ConfigItem *>(index.internalPointer()); + if (!item || !item->menu || !menu_is_visible(item->menu)) + return nullptr; + + return QStyledItemDelegate::createEditor(parent, option, index); } -void ConfigLineEdit::keyPressEvent(QKeyEvent* e) +void ConfigItemDelegate::setModelData(QWidget *editor, + QAbstractItemModel *model, + const QModelIndex &index) const { - switch (e->key()) { - case Qt::Key_Escape: - break; - case Qt::Key_Return: - case Qt::Key_Enter: - sym_set_string_value(item->menu->sym, text().toLatin1()); - parent()->updateList(); - break; - default: - Parent::keyPressEvent(e); - return; + QLineEdit *lineEdit; + ConfigItem *item; + struct symbol *sym; + bool success; + + lineEdit = qobject_cast<QLineEdit *>(editor); + // If this is not a QLineEdit, use the parent's default. + // (does this happen?) + if (!lineEdit) + goto parent; + + item = static_cast<ConfigItem *>(index.internalPointer()); + if (!item || !item->menu) + goto parent; + + sym = item->menu->sym; + if (!sym) + goto parent; + + success = sym_set_string_value(sym, lineEdit->text().toUtf8().data()); + if (success) { + ConfigList::updateListForAll(); + } else { + QMessageBox::information(editor, "qconf", + "Cannot set the data (maybe due to out of range).\n" + "Setting the old value."); + lineEdit->setText(sym_get_string_value(sym)); } - e->accept(); - parent()->list->setFocus(); - hide(); + +parent: + QStyledItemDelegate::setModelData(editor, model, index); } -ConfigList::ConfigList(ConfigView* p, const char *name) - : Parent(p), +ConfigList::ConfigList(QWidget *parent, const char *name) + : QTreeWidget(parent), updateAll(false), - showName(false), showRange(false), showData(false), mode(singleMode), optMode(normalOpt), + showName(false), mode(singleMode), optMode(normalOpt), rootEntry(0), headerPopup(0) { setObjectName(name); @@ -306,26 +309,34 @@ ConfigList::ConfigList(ConfigView* p, const char *name) setVerticalScrollMode(ScrollPerPixel); setHorizontalScrollMode(ScrollPerPixel); - setHeaderLabels(QStringList() << "Option" << "Name" << "N" << "M" << "Y" << "Value"); + setHeaderLabels(QStringList() << "Option" << "Name" << "Value"); - connect(this, SIGNAL(itemSelectionChanged(void)), - SLOT(updateSelection(void))); + connect(this, &ConfigList::itemSelectionChanged, + this, &ConfigList::updateSelection); if (name) { configSettings->beginGroup(name); showName = configSettings->value("/showName", false).toBool(); - showRange = configSettings->value("/showRange", false).toBool(); - showData = configSettings->value("/showData", false).toBool(); optMode = (enum optionMode)configSettings->value("/optionMode", 0).toInt(); configSettings->endGroup(); - connect(configApp, SIGNAL(aboutToQuit()), SLOT(saveSettings())); + connect(configApp, &QApplication::aboutToQuit, + this, &ConfigList::saveSettings); } showColumn(promptColIdx); + setItemDelegate(new ConfigItemDelegate(this)); + + allLists.append(this); + reinit(); } +ConfigList::~ConfigList() +{ + allLists.removeOne(this); +} + bool ConfigList::menuSkip(struct menu *menu) { if (optMode == normalOpt && menu_is_visible(menu)) @@ -339,21 +350,10 @@ bool ConfigList::menuSkip(struct menu *menu) void ConfigList::reinit(void) { - hideColumn(dataColIdx); - hideColumn(yesColIdx); - hideColumn(modColIdx); - hideColumn(noColIdx); hideColumn(nameColIdx); if (showName) showColumn(nameColIdx); - if (showRange) { - showColumn(noColIdx); - showColumn(modColIdx); - showColumn(yesColIdx); - } - if (showData) - showColumn(dataColIdx); updateListAll(); } @@ -375,8 +375,6 @@ void ConfigList::saveSettings(void) if (!objectName().isEmpty()) { configSettings->beginGroup(objectName()); configSettings->setValue("/showName", showName); - configSettings->setValue("/showRange", showRange); - configSettings->setValue("/showData", showData); configSettings->setValue("/optionMode", (int)optMode); configSettings->endGroup(); } @@ -462,6 +460,28 @@ update: resizeColumnToContents(0); } +void ConfigList::updateListForAll() +{ + QListIterator<ConfigList *> it(allLists); + + while (it.hasNext()) { + ConfigList *list = it.next(); + + list->updateList(); + } +} + +void ConfigList::updateListAllForAll() +{ + QListIterator<ConfigList *> it(allLists); + + while (it.hasNext()) { + ConfigList *list = it.next(); + + list->updateList(); + } +} + void ConfigList::setValue(ConfigItem* item, tristate val) { struct symbol* sym; @@ -482,7 +502,7 @@ void ConfigList::setValue(ConfigItem* item, tristate val) return; if (oldval == no && item->menu->list) item->setExpanded(true); - parent()->updateList(); + ConfigList::updateListForAll(); break; } } @@ -516,12 +536,9 @@ void ConfigList::changeValue(ConfigItem* item) item->setExpanded(true); } if (oldexpr != newexpr) - parent()->updateList(); + ConfigList::updateListForAll(); break; - case S_INT: - case S_HEX: - case S_STRING: - parent()->lineEdit->show(item); + default: break; } } @@ -804,15 +821,6 @@ void ConfigList::mouseReleaseEvent(QMouseEvent* e) } } break; - case noColIdx: - setValue(item, no); - break; - case modColIdx: - setValue(item, mod); - break; - case yesColIdx: - setValue(item, yes); - break; case dataColIdx: changeValue(item); break; @@ -882,96 +890,32 @@ void ConfigList::contextMenuEvent(QContextMenuEvent *e) headerPopup = new QMenu(this); action = new QAction("Show Name", this); action->setCheckable(true); - connect(action, SIGNAL(toggled(bool)), - parent(), SLOT(setShowName(bool))); - connect(parent(), SIGNAL(showNameChanged(bool)), - action, SLOT(setChecked(bool))); + connect(action, &QAction::toggled, + this, &ConfigList::setShowName); + connect(this, &ConfigList::showNameChanged, + action, &QAction::setChecked); action->setChecked(showName); headerPopup->addAction(action); - - action = new QAction("Show Range", this); - action->setCheckable(true); - connect(action, SIGNAL(toggled(bool)), - parent(), SLOT(setShowRange(bool))); - connect(parent(), SIGNAL(showRangeChanged(bool)), - action, SLOT(setChecked(bool))); - action->setChecked(showRange); - headerPopup->addAction(action); - - action = new QAction("Show Data", this); - action->setCheckable(true); - connect(action, SIGNAL(toggled(bool)), - parent(), SLOT(setShowData(bool))); - connect(parent(), SIGNAL(showDataChanged(bool)), - action, SLOT(setChecked(bool))); - action->setChecked(showData); - headerPopup->addAction(action); } headerPopup->exec(e->globalPos()); e->accept(); } -ConfigView*ConfigView::viewList; -QAction *ConfigList::showNormalAction; -QAction *ConfigList::showAllAction; -QAction *ConfigList::showPromptAction; - -ConfigView::ConfigView(QWidget* parent, const char *name) - : Parent(parent) -{ - setObjectName(name); - QVBoxLayout *verticalLayout = new QVBoxLayout(this); - verticalLayout->setContentsMargins(0, 0, 0, 0); - - list = new ConfigList(this); - verticalLayout->addWidget(list); - lineEdit = new ConfigLineEdit(this); - lineEdit->hide(); - verticalLayout->addWidget(lineEdit); - - this->nextView = viewList; - viewList = this; -} - -ConfigView::~ConfigView(void) -{ - ConfigView** vp; - - for (vp = &viewList; *vp; vp = &(*vp)->nextView) { - if (*vp == this) { - *vp = nextView; - break; - } - } -} - -void ConfigView::setShowName(bool b) +void ConfigList::setShowName(bool on) { - if (list->showName != b) { - list->showName = b; - list->reinit(); - emit showNameChanged(b); - } -} + if (showName == on) + return; -void ConfigView::setShowRange(bool b) -{ - if (list->showRange != b) { - list->showRange = b; - list->reinit(); - emit showRangeChanged(b); - } + showName = on; + reinit(); + emit showNameChanged(on); } -void ConfigView::setShowData(bool b) -{ - if (list->showData != b) { - list->showData = b; - list->reinit(); - emit showDataChanged(b); - } -} +QList<ConfigList *> ConfigList::allLists; +QAction *ConfigList::showNormalAction; +QAction *ConfigList::showAllAction; +QAction *ConfigList::showPromptAction; void ConfigList::setAllOpen(bool open) { @@ -984,22 +928,6 @@ void ConfigList::setAllOpen(bool open) } } -void ConfigView::updateList() -{ - ConfigView* v; - - for (v = viewList; v; v = v->nextView) - v->list->updateList(); -} - -void ConfigView::updateListAll(void) -{ - ConfigView* v; - - for (v = viewList; v; v = v->nextView) - v->list->updateListAll(); -} - ConfigInfoView::ConfigInfoView(QWidget* parent, const char *name) : Parent(parent), sym(0), _menu(0) { @@ -1010,15 +938,18 @@ ConfigInfoView::ConfigInfoView(QWidget* parent, const char *name) configSettings->beginGroup(objectName()); setShowDebug(configSettings->value("/showDebug", false).toBool()); configSettings->endGroup(); - connect(configApp, SIGNAL(aboutToQuit()), SLOT(saveSettings())); + connect(configApp, &QApplication::aboutToQuit, + this, &ConfigInfoView::saveSettings); } contextMenu = createStandardContextMenu(); QAction *action = new QAction("Show Debug Info", contextMenu); action->setCheckable(true); - connect(action, SIGNAL(toggled(bool)), SLOT(setShowDebug(bool))); - connect(this, SIGNAL(showDebugChanged(bool)), action, SLOT(setChecked(bool))); + connect(action, &QAction::toggled, + this, &ConfigInfoView::setShowDebug); + connect(this, &ConfigInfoView::showDebugChanged, + action, &QAction::setChecked); action->setChecked(showDebug()); contextMenu->addSeparator(); contextMenu->addAction(action); @@ -1108,6 +1039,11 @@ void ConfigInfoView::menuInfo(void) if (showDebug()) stream << debug_info(sym); + struct gstr help_gstr = str_new(); + + menu_get_ext_help(_menu, &help_gstr); + stream << print_filter(str_get(&help_gstr)); + str_free(&help_gstr); } else if (_menu->prompt) { stream << "<big><b>"; stream << print_filter(_menu->prompt->text); @@ -1119,11 +1055,11 @@ void ConfigInfoView::menuInfo(void) expr_print_help, &stream, E_NONE); stream << "<br><br>"; } + + stream << "defined at " << _menu->file->name << ":" + << _menu->lineno << "<br><br>"; } } - if (showDebug()) - stream << "defined at " << _menu->file->name << ":" - << _menu->lineno << "<br><br>"; setText(info); } @@ -1276,7 +1212,7 @@ void ConfigInfoView::clicked(const QUrl &url) } free(result); - delete data; + delete[] data; } void ConfigInfoView::contextMenuEvent(QContextMenuEvent *event) @@ -1300,23 +1236,25 @@ ConfigSearchWindow::ConfigSearchWindow(ConfigMainWindow *parent) layout2->setSpacing(6); layout2->addWidget(new QLabel("Find:", this)); editField = new QLineEdit(this); - connect(editField, SIGNAL(returnPressed()), SLOT(search())); + connect(editField, &QLineEdit::returnPressed, + this, &ConfigSearchWindow::search); layout2->addWidget(editField); searchButton = new QPushButton("Search", this); searchButton->setAutoDefault(false); - connect(searchButton, SIGNAL(clicked()), SLOT(search())); + connect(searchButton, &QPushButton::clicked, + this, &ConfigSearchWindow::search); layout2->addWidget(searchButton); layout1->addLayout(layout2); split = new QSplitter(this); split->setOrientation(Qt::Vertical); - list = new ConfigView(split, "search"); - list->list->mode = listMode; + list = new ConfigList(split, "search"); + list->mode = listMode; info = new ConfigInfoView(split, "search"); - connect(list->list, SIGNAL(menuChanged(struct menu *)), - info, SLOT(setInfo(struct menu *))); - connect(list->list, SIGNAL(menuChanged(struct menu *)), - parent, SLOT(setMenuLink(struct menu *))); + connect(list, &ConfigList::menuChanged, + info, &ConfigInfoView::setInfo); + connect(list, &ConfigList::menuChanged, + parent, &ConfigMainWindow::setMenuLink); layout1->addWidget(split); @@ -1336,7 +1274,8 @@ ConfigSearchWindow::ConfigSearchWindow(ConfigMainWindow *parent) if (ok) split->setSizes(sizes); configSettings->endGroup(); - connect(configApp, SIGNAL(aboutToQuit()), SLOT(saveSettings())); + connect(configApp, &QApplication::aboutToQuit, + this, &ConfigSearchWindow::saveSettings); } void ConfigSearchWindow::saveSettings(void) @@ -1359,7 +1298,7 @@ void ConfigSearchWindow::search(void) ConfigItem *lastItem = NULL; free(result); - list->list->clear(); + list->clear(); info->clear(); result = sym_re_search(editField->text().toLatin1()); @@ -1367,7 +1306,7 @@ void ConfigSearchWindow::search(void) return; for (p = result; *p; p++) { for_all_prompts((*p), prop) - lastItem = new ConfigItem(list->list, lastItem, prop->menu, + lastItem = new ConfigItem(list, lastItem, prop->menu, menu_is_visible(prop->menu)); } } @@ -1415,42 +1354,44 @@ ConfigMainWindow::ConfigMainWindow(void) split1->setOrientation(Qt::Horizontal); split1->setChildrenCollapsible(false); - menuView = new ConfigView(widget, "menu"); - menuList = menuView->list; + menuList = new ConfigList(widget, "menu"); split2 = new QSplitter(widget); split2->setChildrenCollapsible(false); split2->setOrientation(Qt::Vertical); // create config tree - configView = new ConfigView(widget, "config"); - configList = configView->list; + configList = new ConfigList(widget, "config"); helpText = new ConfigInfoView(widget, "help"); layout->addWidget(split2); split2->addWidget(split1); - split1->addWidget(configView); - split1->addWidget(menuView); + split1->addWidget(configList); + split1->addWidget(menuList); split2->addWidget(helpText); setTabOrder(configList, helpText); configList->setFocus(); backAction = new QAction(QPixmap(xpm_back), "Back", this); - connect(backAction, SIGNAL(triggered(bool)), SLOT(goBack())); + connect(backAction, &QAction::triggered, + this, &ConfigMainWindow::goBack); QAction *quitAction = new QAction("&Quit", this); quitAction->setShortcut(Qt::CTRL + Qt::Key_Q); - connect(quitAction, SIGNAL(triggered(bool)), SLOT(close())); + connect(quitAction, &QAction::triggered, + this, &ConfigMainWindow::close); QAction *loadAction = new QAction(QPixmap(xpm_load), "&Load", this); loadAction->setShortcut(Qt::CTRL + Qt::Key_L); - connect(loadAction, SIGNAL(triggered(bool)), SLOT(loadConfig())); + connect(loadAction, &QAction::triggered, + this, &ConfigMainWindow::loadConfig); saveAction = new QAction(QPixmap(xpm_save), "&Save", this); saveAction->setShortcut(Qt::CTRL + Qt::Key_S); - connect(saveAction, SIGNAL(triggered(bool)), SLOT(saveConfig())); + connect(saveAction, &QAction::triggered, + this, &ConfigMainWindow::saveConfig); conf_set_changed_callback(conf_changed); @@ -1459,37 +1400,37 @@ ConfigMainWindow::ConfigMainWindow(void) configname = xstrdup(conf_get_configname()); QAction *saveAsAction = new QAction("Save &As...", this); - connect(saveAsAction, SIGNAL(triggered(bool)), SLOT(saveConfigAs())); + connect(saveAsAction, &QAction::triggered, + this, &ConfigMainWindow::saveConfigAs); QAction *searchAction = new QAction("&Find", this); searchAction->setShortcut(Qt::CTRL + Qt::Key_F); - connect(searchAction, SIGNAL(triggered(bool)), SLOT(searchConfig())); + connect(searchAction, &QAction::triggered, + this, &ConfigMainWindow::searchConfig); singleViewAction = new QAction(QPixmap(xpm_single_view), "Single View", this); singleViewAction->setCheckable(true); - connect(singleViewAction, SIGNAL(triggered(bool)), SLOT(showSingleView())); + connect(singleViewAction, &QAction::triggered, + this, &ConfigMainWindow::showSingleView); splitViewAction = new QAction(QPixmap(xpm_split_view), "Split View", this); splitViewAction->setCheckable(true); - connect(splitViewAction, SIGNAL(triggered(bool)), SLOT(showSplitView())); + connect(splitViewAction, &QAction::triggered, + this, &ConfigMainWindow::showSplitView); fullViewAction = new QAction(QPixmap(xpm_tree_view), "Full View", this); fullViewAction->setCheckable(true); - connect(fullViewAction, SIGNAL(triggered(bool)), SLOT(showFullView())); + connect(fullViewAction, &QAction::triggered, + this, &ConfigMainWindow::showFullView); QAction *showNameAction = new QAction("Show Name", this); showNameAction->setCheckable(true); - connect(showNameAction, SIGNAL(toggled(bool)), configView, SLOT(setShowName(bool))); - showNameAction->setChecked(configView->showName()); - QAction *showRangeAction = new QAction("Show Range", this); - showRangeAction->setCheckable(true); - connect(showRangeAction, SIGNAL(toggled(bool)), configView, SLOT(setShowRange(bool))); - QAction *showDataAction = new QAction("Show Data", this); - showDataAction->setCheckable(true); - connect(showDataAction, SIGNAL(toggled(bool)), configView, SLOT(setShowData(bool))); + connect(showNameAction, &QAction::toggled, + configList, &ConfigList::setShowName); + showNameAction->setChecked(configList->showName); QActionGroup *optGroup = new QActionGroup(this); optGroup->setExclusive(true); - connect(optGroup, SIGNAL(triggered(QAction*)), configList, - SLOT(setOptionMode(QAction *))); - connect(optGroup, SIGNAL(triggered(QAction *)), menuList, - SLOT(setOptionMode(QAction *))); + connect(optGroup, &QActionGroup::triggered, + configList, &ConfigList::setOptionMode); + connect(optGroup, &QActionGroup::triggered, + menuList, &ConfigList::setOptionMode); ConfigList::showNormalAction = new QAction("Show Normal Options", optGroup); ConfigList::showNormalAction->setCheckable(true); @@ -1500,13 +1441,16 @@ ConfigMainWindow::ConfigMainWindow(void) QAction *showDebugAction = new QAction("Show Debug Info", this); showDebugAction->setCheckable(true); - connect(showDebugAction, SIGNAL(toggled(bool)), helpText, SLOT(setShowDebug(bool))); + connect(showDebugAction, &QAction::toggled, + helpText, &ConfigInfoView::setShowDebug); showDebugAction->setChecked(helpText->showDebug()); QAction *showIntroAction = new QAction("Introduction", this); - connect(showIntroAction, SIGNAL(triggered(bool)), SLOT(showIntro())); + connect(showIntroAction, &QAction::triggered, + this, &ConfigMainWindow::showIntro); QAction *showAboutAction = new QAction("About", this); - connect(showAboutAction, SIGNAL(triggered(bool)), SLOT(showAbout())); + connect(showAboutAction, &QAction::triggered, + this, &ConfigMainWindow::showAbout); // init tool bar QToolBar *toolBar = addToolBar("Tools"); @@ -1534,8 +1478,6 @@ ConfigMainWindow::ConfigMainWindow(void) // create options menu menu = menuBar()->addMenu("&Option"); menu->addAction(showNameAction); - menu->addAction(showRangeAction); - menu->addAction(showDataAction); menu->addSeparator(); menu->addActions(optGroup->actions()); menu->addSeparator(); @@ -1546,30 +1488,30 @@ ConfigMainWindow::ConfigMainWindow(void) menu->addAction(showIntroAction); menu->addAction(showAboutAction); - connect (helpText, SIGNAL (anchorClicked (const QUrl &)), - helpText, SLOT (clicked (const QUrl &)) ); - - connect(configList, SIGNAL(menuChanged(struct menu *)), - helpText, SLOT(setInfo(struct menu *))); - connect(configList, SIGNAL(menuSelected(struct menu *)), - SLOT(changeMenu(struct menu *))); - connect(configList, SIGNAL(itemSelected(struct menu *)), - SLOT(changeItens(struct menu *))); - connect(configList, SIGNAL(parentSelected()), - SLOT(goBack())); - connect(menuList, SIGNAL(menuChanged(struct menu *)), - helpText, SLOT(setInfo(struct menu *))); - connect(menuList, SIGNAL(menuSelected(struct menu *)), - SLOT(changeMenu(struct menu *))); - - connect(configList, SIGNAL(gotFocus(struct menu *)), - helpText, SLOT(setInfo(struct menu *))); - connect(menuList, SIGNAL(gotFocus(struct menu *)), - helpText, SLOT(setInfo(struct menu *))); - connect(menuList, SIGNAL(gotFocus(struct menu *)), - SLOT(listFocusChanged(void))); - connect(helpText, SIGNAL(menuSelected(struct menu *)), - SLOT(setMenuLink(struct menu *))); + connect(helpText, &ConfigInfoView::anchorClicked, + helpText, &ConfigInfoView::clicked); + + connect(configList, &ConfigList::menuChanged, + helpText, &ConfigInfoView::setInfo); + connect(configList, &ConfigList::menuSelected, + this, &ConfigMainWindow::changeMenu); + connect(configList, &ConfigList::itemSelected, + this, &ConfigMainWindow::changeItens); + connect(configList, &ConfigList::parentSelected, + this, &ConfigMainWindow::goBack); + connect(menuList, &ConfigList::menuChanged, + helpText, &ConfigInfoView::setInfo); + connect(menuList, &ConfigList::menuSelected, + this, &ConfigMainWindow::changeMenu); + + connect(configList, &ConfigList::gotFocus, + helpText, &ConfigInfoView::setInfo); + connect(menuList, &ConfigList::gotFocus, + helpText, &ConfigInfoView::setInfo); + connect(menuList, &ConfigList::gotFocus, + this, &ConfigMainWindow::listFocusChanged); + connect(helpText, &ConfigInfoView::menuSelected, + this, &ConfigMainWindow::setMenuLink); QString listMode = configSettings->value("/listMode", "symbol").toString(); if (listMode == "single") @@ -1608,7 +1550,7 @@ void ConfigMainWindow::loadConfig(void) free(configname); configname = xstrdup(name); - ConfigView::updateListAll(); + ConfigList::updateListAllForAll(); } bool ConfigMainWindow::saveConfig(void) @@ -1743,7 +1685,7 @@ void ConfigMainWindow::showSingleView(void) backAction->setEnabled(true); - menuView->hide(); + menuList->hide(); menuList->setRootMenu(0); configList->mode = singleMode; if (configList->rootEntry == &rootmenu) @@ -1774,7 +1716,7 @@ void ConfigMainWindow::showSplitView(void) menuList->mode = symbolMode; menuList->setRootMenu(&rootmenu); menuList->setAllOpen(true); - menuView->show(); + menuList->show(); menuList->setFocus(); } @@ -1789,7 +1731,7 @@ void ConfigMainWindow::showFullView(void) backAction->setEnabled(false); - menuView->hide(); + menuList->hide(); menuList->setRootMenu(0); configList->mode = fullMode; if (configList->rootEntry == &rootmenu) @@ -1831,17 +1773,26 @@ void ConfigMainWindow::closeEvent(QCloseEvent* e) void ConfigMainWindow::showIntro(void) { - static const QString str = "Welcome to the qconf graphical configuration tool.\n\n" - "For each option, a blank box indicates the feature is disabled, a check\n" - "indicates it is enabled, and a dot indicates that it is to be compiled\n" - "as a module. Clicking on the box will cycle through the three states.\n\n" - "If you do not see an option (e.g., a device driver) that you believe\n" - "should be present, try turning on Show All Options under the Options menu.\n" - "Although there is no cross reference yet to help you figure out what other\n" - "options must be enabled to support the option you are interested in, you can\n" - "still view the help of a grayed-out option.\n\n" - "Toggling Show Debug Info under the Options menu will show the dependencies,\n" - "which you can then match by examining other options.\n\n"; + static const QString str = + "Welcome to the qconf graphical configuration tool.\n" + "\n" + "For bool and tristate options, a blank box indicates the " + "feature is disabled, a check indicates it is enabled, and a " + "dot indicates that it is to be compiled as a module. Clicking " + "on the box will cycle through the three states. For int, hex, " + "and string options, double-clicking or pressing F2 on the " + "Value cell will allow you to edit the value.\n" + "\n" + "If you do not see an option (e.g., a device driver) that you " + "believe should be present, try turning on Show All Options " + "under the Options menu. Enabling Show Debug Info will help you" + "figure out what other options must be enabled to support the " + "option you are interested in, and hyperlinks will navigate to " + "them.\n" + "\n" + "Toggling Show Debug Info under the Options menu will show the " + "dependencies, which you can then match by examining other " + "options.\n"; QMessageBox::information(this, "qconf", str); } @@ -1849,10 +1800,13 @@ void ConfigMainWindow::showIntro(void) void ConfigMainWindow::showAbout(void) { static const QString str = "qconf is Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>.\n" - "Copyright (C) 2015 Boris Barbulovski <bbarbulovski@gmail.com>.\n\n" - "Bug reports and feature request can also be entered at http://bugzilla.kernel.org/\n"; + "Copyright (C) 2015 Boris Barbulovski <bbarbulovski@gmail.com>.\n" + "\n" + "Bug reports and feature request can also be entered at http://bugzilla.kernel.org/\n" + "\n" + "Qt Version: "; - QMessageBox::information(this, "qconf", str); + QMessageBox::information(this, "qconf", str + qVersion()); } void ConfigMainWindow::saveSettings(void) @@ -1921,7 +1875,6 @@ int main(int ac, char** av) const char *name; progname = av[0]; - configApp = new QApplication(ac, av); if (ac > 1 && av[1][0] == '-') { switch (av[1][1]) { case 's': @@ -1942,6 +1895,8 @@ int main(int ac, char** av) conf_read(NULL); //zconfdump(stdout); + configApp = new QApplication(ac, av); + configSettings = new ConfigSettings(); configSettings->beginGroup("/kconfig/qconf"); v = new ConfigMainWindow(); diff --git a/scripts/kconfig/qconf.h b/scripts/kconfig/qconf.h index f97376a812..78b0a1dfcd 100644 --- a/scripts/kconfig/qconf.h +++ b/scripts/kconfig/qconf.h @@ -11,15 +11,14 @@ #include <QPushButton> #include <QSettings> #include <QSplitter> +#include <QStyledItemDelegate> #include <QTextBrowser> #include <QTreeWidget> #include "expr.h" -class ConfigView; class ConfigList; class ConfigItem; -class ConfigLineEdit; class ConfigMainWindow; class ConfigSettings : public QSettings { @@ -30,7 +29,7 @@ public: }; enum colIdx { - promptColIdx, nameColIdx, noColIdx, modColIdx, yesColIdx, dataColIdx + promptColIdx, nameColIdx, dataColIdx }; enum listMode { singleMode, menuMode, symbolMode, fullMode, listMode @@ -43,13 +42,10 @@ class ConfigList : public QTreeWidget { Q_OBJECT typedef class QTreeWidget Parent; public: - ConfigList(ConfigView* p, const char *name = 0); + ConfigList(QWidget *parent, const char *name = 0); + ~ConfigList(); void reinit(void); ConfigItem* findConfigItem(struct menu *); - ConfigView* parent(void) const - { - return (ConfigView*)Parent::parent(); - } void setSelected(QTreeWidgetItem *item, bool enable) { for (int i = 0; i < selectedItems().size(); i++) selectedItems().at(i)->setSelected(false); @@ -75,6 +71,7 @@ public slots: void updateSelection(void); void saveSettings(void); void setOptionMode(QAction *action); + void setShowName(bool on); signals: void menuChanged(struct menu *menu); @@ -82,6 +79,7 @@ signals: void itemSelected(struct menu *menu); void parentSelected(void); void gotFocus(struct menu *); + void showNameChanged(bool on); public: void updateListAll(void) @@ -100,7 +98,7 @@ public: bool updateAll; - bool showName, showRange, showData; + bool showName; enum listMode mode; enum optionMode optMode; struct menu *rootEntry; @@ -108,6 +106,10 @@ public: QPalette inactivedColorGroup; QMenu* headerPopup; + static QList<ConfigList *> allLists; + static void updateListForAll(); + static void updateListAllForAll(); + static QAction *showNormalAction, *showAllAction, *showPromptAction; }; @@ -131,7 +133,6 @@ public: } ~ConfigItem(void); void init(void); - void okRename(int col); void updateMenu(void); void testUpdateMenu(bool v); ConfigList* listView() const @@ -168,48 +169,18 @@ public: static QIcon menuIcon, menubackIcon; }; -class ConfigLineEdit : public QLineEdit { - Q_OBJECT - typedef class QLineEdit Parent; -public: - ConfigLineEdit(ConfigView* parent); - ConfigView* parent(void) const - { - return (ConfigView*)Parent::parent(); - } - void show(ConfigItem *i); - void keyPressEvent(QKeyEvent *e); - -public: - ConfigItem *item; -}; - -class ConfigView : public QWidget { - Q_OBJECT - typedef class QWidget Parent; -public: - ConfigView(QWidget* parent, const char *name = 0); - ~ConfigView(void); - static void updateList(); - static void updateListAll(void); - - bool showName(void) const { return list->showName; } - bool showRange(void) const { return list->showRange; } - bool showData(void) const { return list->showData; } -public slots: - void setShowName(bool); - void setShowRange(bool); - void setShowData(bool); -signals: - void showNameChanged(bool); - void showRangeChanged(bool); - void showDataChanged(bool); +class ConfigItemDelegate : public QStyledItemDelegate +{ +private: + struct menu *menu; public: - ConfigList* list; - ConfigLineEdit* lineEdit; - - static ConfigView* viewList; - ConfigView* nextView; + ConfigItemDelegate(QObject *parent = nullptr) + : QStyledItemDelegate(parent) {} + QWidget *createEditor(QWidget *parent, + const QStyleOptionViewItem &option, + const QModelIndex &index) const override; + void setModelData(QWidget *editor, QAbstractItemModel *model, + const QModelIndex &index) const override; }; class ConfigInfoView : public QTextBrowser { @@ -257,7 +228,7 @@ protected: QLineEdit* editField; QPushButton* searchButton; QSplitter* split; - ConfigView* list; + ConfigList *list; ConfigInfoView* info; struct symbol **result; @@ -292,9 +263,7 @@ protected: void closeEvent(QCloseEvent *e); ConfigSearchWindow *searchWindow; - ConfigView *menuView; ConfigList *menuList; - ConfigView *configView; ConfigList *configList; ConfigInfoView *helpText; QAction *backAction; diff --git a/scripts/kconfig/streamline_config.pl b/scripts/kconfig/streamline_config.pl index 19857d18d8..911c72a2db 100755 --- a/scripts/kconfig/streamline_config.pl +++ b/scripts/kconfig/streamline_config.pl @@ -21,7 +21,7 @@ # 1. Boot up the kernel that you want to stream line the config on. # 2. Change directory to the directory holding the source of the # kernel that you just booted. -# 3. Copy the configuraton file to this directory as .config +# 3. Copy the configuration file to this directory as .config # 4. Have all your devices that you need modules for connected and # operational (make sure that their corresponding modules are loaded) # 5. Run this script redirecting the output to some other file @@ -481,7 +481,7 @@ sub parse_config_depends # The idea is we look at all the configs that select it. If one # is already in our list of configs to enable, then there's nothing # else to do. If there isn't, we pick the first config that was -# enabled in the orignal config and use that. +# enabled in the original config and use that. sub parse_config_selects { my ($config, $p) = @_; @@ -593,7 +593,10 @@ while ($repeat) { } my %setconfigs; -my @preserved_kconfigs = split(/:/,$ENV{LMC_KEEP}); +my @preserved_kconfigs; +if (defined($ENV{'LMC_KEEP'})) { + @preserved_kconfigs = split(/:/,$ENV{LMC_KEEP}); +} sub in_preserved_kconfigs { my $kconfig = $config2kfile{$_[0]}; diff --git a/scripts/kconfig/symbol.c b/scripts/kconfig/symbol.c index ffa3ec65cc..5844d636d3 100644 --- a/scripts/kconfig/symbol.c +++ b/scripts/kconfig/symbol.c @@ -3,11 +3,11 @@ * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org> */ +#include <sys/types.h> #include <ctype.h> #include <stdlib.h> #include <string.h> #include <regex.h> -#include <sys/utsname.h> #include "lkc.h" @@ -35,7 +35,6 @@ static struct symbol symbol_empty = { .flags = SYMBOL_VALID, }; -struct symbol *sym_defconfig_list; struct symbol *modules_sym; static tristate modules_val; @@ -473,7 +472,7 @@ void sym_clear_all_valid(void) for_all_symbols(i, sym) sym->flags &= ~SYMBOL_VALID; - sym_add_change_count(1); + conf_set_changed(true); sym_calc_value(modules_sym); } diff --git a/scripts/kconfig/tests/choice/Kconfig b/scripts/kconfig/tests/choice/Kconfig index a412205b1b..0930eb65e9 100644 --- a/scripts/kconfig/tests/choice/Kconfig +++ b/scripts/kconfig/tests/choice/Kconfig @@ -2,7 +2,7 @@ config MODULES bool "Enable loadable module support" - option modules + modules default y choice diff --git a/scripts/kconfig/tests/choice_value_with_m_dep/Kconfig b/scripts/kconfig/tests/choice_value_with_m_dep/Kconfig index 7106c26bb3..bd970cec07 100644 --- a/scripts/kconfig/tests/choice_value_with_m_dep/Kconfig +++ b/scripts/kconfig/tests/choice_value_with_m_dep/Kconfig @@ -2,7 +2,7 @@ config MODULES def_bool y - option modules + modules config DEP tristate diff --git a/scripts/kconfig/tests/conftest.py b/scripts/kconfig/tests/conftest.py index 0345ef6e32..af8774a569 100644 --- a/scripts/kconfig/tests/conftest.py +++ b/scripts/kconfig/tests/conftest.py @@ -53,6 +53,10 @@ class Conf: # Override 'srctree' environment to make the test as the top directory extra_env['srctree'] = self._test_dir + # Clear KCONFIG_DEFCONFIG_LIST to keep unit tests from being affected + # by the user's environment. + extra_env['KCONFIG_DEFCONFIG_LIST'] = '' + # Run Kconfig in a temporary directory. # This directory is automatically removed when done. with tempfile.TemporaryDirectory() as temp_dir: diff --git a/scripts/kconfig/tests/inter_choice/Kconfig b/scripts/kconfig/tests/inter_choice/Kconfig index 5698a4018d..26c25f6869 100644 --- a/scripts/kconfig/tests/inter_choice/Kconfig +++ b/scripts/kconfig/tests/inter_choice/Kconfig @@ -2,7 +2,7 @@ config MODULES def_bool y - option modules + modules choice prompt "Choice" diff --git a/scripts/zynq_mkimage.c b/scripts/zynq_mkimage.c index 8b95b41960..b611d5c69b 100644 --- a/scripts/zynq_mkimage.c +++ b/scripts/zynq_mkimage.c @@ -142,7 +142,7 @@ static char *readcmd(FILE *f) } } -int parse_config(char *buf, const char *filename) +static int parse_config(char *buf, const char *filename) { FILE *f; int lineno = 0; |