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-rw-r--r--Makefile2
-rw-r--r--arch/arm/boards/Makefile1
-rw-r--r--arch/arm/boards/advantech-mx6/Makefile2
-rw-r--r--arch/arm/boards/advantech-mx6/board.c101
-rw-r--r--arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg66
-rw-r--r--arch/arm/boards/advantech-mx6/lowlevel.c56
-rw-r--r--arch/arm/boards/datamodul-edm-qmx6/board.c2
-rw-r--r--arch/arm/boards/dfi-fs700-m60/board.c2
-rw-r--r--arch/arm/boards/freescale-vf610-twr/lowlevel.c15
-rw-r--r--arch/arm/boards/phytec-som-imx6/board.c59
-rw-r--r--arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/boot/emmc5
-rw-r--r--arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/emmc10
-rw-r--r--arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc7
-rw-r--r--arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand11
-rw-r--r--arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount5
-rw-r--r--arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg8
-rw-r--r--arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg8
-rw-r--r--arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h112
-rw-r--r--arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg2
-rw-r--r--arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg2
-rw-r--r--arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h2
-rw-r--r--arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg2
-rw-r--r--arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg2
-rw-r--r--arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg2
-rw-r--r--arch/arm/boards/phytec-som-imx6/lowlevel.c2
-rw-r--r--arch/arm/boards/zii-imx6q-rdu2/lowlevel.c8
-rw-r--r--arch/arm/boards/zii-vf610-dev/lowlevel.c3
-rw-r--r--arch/arm/configs/imx_v7_defconfig10
-rw-r--r--arch/arm/configs/omap3530_beagle_defconfig2
-rw-r--r--arch/arm/configs/omap3530_beagle_xload_defconfig3
-rw-r--r--arch/arm/cpu/common.c1
-rw-r--r--arch/arm/cpu/start.c13
-rw-r--r--arch/arm/dts/Makefile2
-rwxr-xr-xarch/arm/dts/imx6dl-advantech-rom-7421.dts225
-rw-r--r--arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts8
-rw-r--r--arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts8
-rw-r--r--arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi12
-rw-r--r--arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts8
-rw-r--r--arch/arm/dts/imx6q-phytec-phycore-som-nand.dts8
-rw-r--r--arch/arm/dts/imx6qdl-phytec-pfla02.dtsi12
-rw-r--r--arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi252
-rw-r--r--arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts69
-rw-r--r--arch/arm/dts/vf610-ddrmc.dtsi15
-rw-r--r--arch/arm/dts/vf610-twr.dts1
-rw-r--r--arch/arm/dts/vf610-zii-dev.dtsi4
-rw-r--r--arch/arm/include/asm/barebox-arm.h9
-rw-r--r--arch/arm/mach-imx/Kconfig5
-rw-r--r--arch/arm/mach-imx/Makefile1
-rw-r--r--arch/arm/mach-imx/boot.c435
-rw-r--r--arch/arm/mach-imx/esdctl.c144
-rw-r--r--arch/arm/mach-imx/imx.c52
-rw-r--r--arch/arm/mach-imx/imx51.c20
-rw-r--r--arch/arm/mach-imx/imx53.c4
-rw-r--r--arch/arm/mach-imx/imx6.c104
-rw-r--r--arch/arm/mach-imx/imx7.c19
-rw-r--r--arch/arm/mach-imx/include/mach/esdctl.h2
-rw-r--r--arch/arm/mach-imx/include/mach/generic.h3
-rw-r--r--arch/arm/mach-imx/include/mach/imx6-regs.h4
-rw-r--r--arch/arm/mach-imx/include/mach/imx6.h88
-rw-r--r--arch/arm/mach-imx/include/mach/reset-reason.h37
-rw-r--r--arch/arm/mach-imx/include/mach/vf610-ddrmc.h18
-rw-r--r--arch/arm/mach-imx/include/mach/vf610-regs.h5
-rw-r--r--arch/arm/mach-imx/include/mach/vf610.h51
-rw-r--r--arch/arm/mach-imx/vf610.c59
-rw-r--r--arch/arm/mach-imx/xload.c2
-rw-r--r--commands/i2c.c2
-rw-r--r--common/bootsource.c1
-rw-r--r--common/reset_source.c23
-rw-r--r--drivers/aiodev/Kconfig6
-rw-r--r--drivers/aiodev/Makefile1
-rw-r--r--drivers/aiodev/mc13xxx_adc.c234
-rw-r--r--drivers/clk/imx/clk-imx6.c26
-rw-r--r--drivers/mfd/mc13xxx.c15
-rw-r--r--drivers/serial/serial_lpuart.c4
-rw-r--r--drivers/video/fb.c3
-rw-r--r--drivers/video/imx-ipu-v3/imx-ldb.c2
-rw-r--r--drivers/watchdog/omap_wdt.c1
-rw-r--r--drivers/watchdog/wd_core.c6
-rw-r--r--dts/Bindings/arm/arm,scmi.txt179
-rw-r--r--dts/Bindings/arm/cpu-enable-method/nuvoton,npcm750-smp42
-rw-r--r--dts/Bindings/arm/cpus.txt2
-rw-r--r--dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt33
-rw-r--r--dts/Bindings/arm/hisilicon/hisilicon.txt23
-rw-r--r--dts/Bindings/arm/mediatek.txt9
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,audsys.txt20
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,ethsys.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,pciesys.txt2
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,ssusbsys.txt2
-rw-r--r--dts/Bindings/arm/npcm/npcm.txt6
-rw-r--r--dts/Bindings/arm/omap/ctrl.txt1
-rw-r--r--dts/Bindings/arm/omap/mpu.txt16
-rw-r--r--dts/Bindings/arm/qcom.txt1
-rw-r--r--dts/Bindings/arm/rockchip.txt12
-rw-r--r--dts/Bindings/arm/samsung/pmu.txt6
-rw-r--r--dts/Bindings/arm/samsung/samsung-boards.txt4
-rw-r--r--dts/Bindings/arm/shmobile.txt18
-rw-r--r--dts/Bindings/arm/stm32.txt1
-rw-r--r--dts/Bindings/arm/sunxi/smp-sram.txt44
-rw-r--r--dts/Bindings/arm/tegra.txt16
-rw-r--r--dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt2
-rw-r--r--dts/Bindings/arm/xilinx.txt56
-rw-r--r--dts/Bindings/ata/ahci-platform.txt1
-rw-r--r--dts/Bindings/ata/imx-sata.txt1
-rw-r--r--dts/Bindings/ata/nvidia,tegra124-ahci.txt36
-rw-r--r--dts/Bindings/bus/nvidia,tegra20-gmi.txt6
-rw-r--r--dts/Bindings/clock/imx6sll-clock.txt36
-rw-r--r--dts/Bindings/clock/intc_stratix10.txt20
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.txt6
-rw-r--r--dts/Bindings/clock/rockchip,rk3328-cru.txt1
-rw-r--r--dts/Bindings/clock/silabs,si544.txt25
-rw-r--r--dts/Bindings/clock/st,stm32mp1-rcc.txt60
-rw-r--r--dts/Bindings/clock/sunxi-ccu.txt4
-rw-r--r--dts/Bindings/clock/ti/davinci/da8xx-cfgchip.txt93
-rw-r--r--dts/Bindings/clock/ti/davinci/pll.txt96
-rw-r--r--dts/Bindings/clock/ti/davinci/psc.txt71
-rw-r--r--dts/Bindings/clock/ti/divider.txt3
-rw-r--r--dts/Bindings/clock/ti/mux.txt3
-rw-r--r--dts/Bindings/connector/samsung,usb-connector-11pin.txt49
-rw-r--r--dts/Bindings/connector/usb-connector.txt75
-rw-r--r--dts/Bindings/cpufreq/cpufreq-dt.txt4
-rw-r--r--dts/Bindings/cpufreq/cpufreq-mediatek.txt4
-rw-r--r--dts/Bindings/cris/axis.txt9
-rw-r--r--dts/Bindings/cris/boards.txt8
-rw-r--r--dts/Bindings/crypto/arm-cryptocell.txt3
-rw-r--r--dts/Bindings/crypto/fsl-sec4.txt17
-rw-r--r--dts/Bindings/crypto/inside-secure-safexcel.txt6
-rw-r--r--dts/Bindings/display/bridge/renesas,lvds.txt58
-rw-r--r--dts/Bindings/display/bridge/ti,ths813x.txt (renamed from dts/Bindings/display/bridge/ti,ths8135.txt)13
-rw-r--r--dts/Bindings/display/connector/dvi-connector.txt1
-rw-r--r--dts/Bindings/display/etnaviv/etnaviv-drm.txt24
-rw-r--r--dts/Bindings/display/msm/dsi.txt26
-rw-r--r--dts/Bindings/display/panel/arm,versatile-tft-panel.txt31
-rw-r--r--dts/Bindings/display/panel/auo,g104sn02.txt12
-rw-r--r--dts/Bindings/display/panel/display-timing.txt5
-rw-r--r--dts/Bindings/display/panel/koe,tx31d200vm0baa.txt25
-rw-r--r--dts/Bindings/display/panel/orisetech,otm8009a.txt2
-rw-r--r--dts/Bindings/display/panel/raydium,rm68200.txt25
-rw-r--r--dts/Bindings/display/panel/simple-panel.txt4
-rw-r--r--dts/Bindings/display/renesas,du.txt35
-rw-r--r--dts/Bindings/display/rockchip/cdn-dp-rockchip.txt74
-rw-r--r--dts/Bindings/display/st,stm32-ltdc.txt2
-rw-r--r--dts/Bindings/display/sunxi/sun4i-drm.txt104
-rw-r--r--dts/Bindings/dma/brcm,bcm2835-dma.txt4
-rw-r--r--dts/Bindings/dma/mtk-hsdma.txt33
-rw-r--r--dts/Bindings/dma/qcom_bam_dma.txt4
-rw-r--r--dts/Bindings/dma/renesas,rcar-dmac.txt2
-rw-r--r--dts/Bindings/dma/renesas,usb-dmac.txt1
-rw-r--r--dts/Bindings/dma/snps,dw-axi-dmac.txt41
-rw-r--r--dts/Bindings/dma/stm32-dma.txt6
-rw-r--r--dts/Bindings/eeprom/at24.txt4
-rw-r--r--dts/Bindings/fsi/fsi.txt151
-rw-r--r--dts/Bindings/gpio/gpio-eic-sprd.txt97
-rw-r--r--dts/Bindings/gpio/gpio-etraxfs.txt22
-rw-r--r--dts/Bindings/gpio/gpio-pca953x.txt2
-rw-r--r--dts/Bindings/gpio/gpio-sprd.txt28
-rw-r--r--dts/Bindings/gpio/gpio-tz1090-pdc.txt45
-rw-r--r--dts/Bindings/gpio/gpio-tz1090.txt88
-rw-r--r--dts/Bindings/gpio/gpio.txt7
-rw-r--r--dts/Bindings/gpio/nintendo,hollywood-gpio.txt27
-rw-r--r--dts/Bindings/gpio/raspberrypi,firmware-gpio.txt30
-rw-r--r--dts/Bindings/gpu/arm,mali-utgard.txt1
-rw-r--r--dts/Bindings/i2c/i2c-rcar.txt2
-rw-r--r--dts/Bindings/i2c/i2c-sh_mobile.txt1
-rw-r--r--dts/Bindings/i2c/i2c-synquacer.txt29
-rw-r--r--dts/Bindings/iio/adc/axp20x_adc.txt48
-rw-r--r--dts/Bindings/iio/adc/st,stm32-dfsdm-adc.txt8
-rw-r--r--dts/Bindings/iio/potentiometer/ad5272.txt27
-rw-r--r--dts/Bindings/iio/temperature/mlx90632.txt28
-rw-r--r--dts/Bindings/input/gpio-keys.txt8
-rw-r--r--dts/Bindings/input/zii,rave-sp-pwrbutton.txt22
-rw-r--r--dts/Bindings/interrupt-controller/andestech,ativic32.txt19
-rw-r--r--dts/Bindings/interrupt-controller/axis,crisv32-intc.txt23
-rw-r--r--dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt22
-rw-r--r--dts/Bindings/interrupt-controller/qcom,pdc.txt78
-rw-r--r--dts/Bindings/iommu/renesas,ipmmu-vmsa.txt5
-rw-r--r--dts/Bindings/iommu/rockchip,iommu.txt7
-rw-r--r--dts/Bindings/ipmi/aspeed-kcs-bmc.txt25
-rw-r--r--dts/Bindings/jailhouse.txt8
-rw-r--r--dts/Bindings/mailbox/hisilicon,hi3660-mailbox.txt51
-rw-r--r--dts/Bindings/mailbox/mailbox.txt28
-rw-r--r--dts/Bindings/media/coda.txt5
-rw-r--r--dts/Bindings/media/i2c/adv7604.txt18
-rw-r--r--dts/Bindings/media/i2c/ov2685.txt41
-rw-r--r--dts/Bindings/media/i2c/ov5695.txt41
-rw-r--r--dts/Bindings/media/i2c/ov7670.txt16
-rw-r--r--dts/Bindings/media/i2c/ov9650.txt36
-rw-r--r--dts/Bindings/media/i2c/tda1997x.txt178
-rw-r--r--dts/Bindings/media/rcar_vin.txt4
-rw-r--r--dts/Bindings/media/renesas,ceu.txt81
-rw-r--r--dts/Bindings/media/s5p-mfc.txt1
-rw-r--r--dts/Bindings/media/spi/sony-cxd2880.txt14
-rw-r--r--dts/Bindings/media/sunxi-ir.txt3
-rw-r--r--dts/Bindings/memory-controllers/ti/emif.txt13
-rw-r--r--dts/Bindings/metag/meta.txt30
-rw-r--r--dts/Bindings/mfd/aspeed-lpc.txt62
-rw-r--r--dts/Bindings/mips/mscc.txt43
-rw-r--r--dts/Bindings/mmc/hi3798cv200-dw-mshc.txt40
-rw-r--r--dts/Bindings/mmc/mtk-sd.txt1
-rw-r--r--dts/Bindings/mmc/rockchip-dw-mshc.txt4
-rw-r--r--dts/Bindings/mmc/synopsys-dw-mshc.txt9
-rw-r--r--dts/Bindings/mmc/tmio_mmc.txt1
-rw-r--r--dts/Bindings/mtd/fsl-quadspi.txt24
-rw-r--r--dts/Bindings/mtd/marvell-nand.txt5
-rw-r--r--dts/Bindings/mtd/mtd-physmap.txt7
-rw-r--r--dts/Bindings/mtd/pxa3xx-nand.txt50
-rw-r--r--dts/Bindings/mtd/sunxi-nand.txt4
-rw-r--r--dts/Bindings/nds32/andestech-boards40
-rw-r--r--dts/Bindings/nds32/atl2c.txt28
-rw-r--r--dts/Bindings/nds32/cpus.txt38
-rw-r--r--dts/Bindings/net/dsa/marvell.txt11
-rw-r--r--dts/Bindings/net/ethernet.txt2
-rw-r--r--dts/Bindings/net/fsl-tsec-phy.txt6
-rw-r--r--dts/Bindings/net/ieee802154/mcr20a.txt23
-rw-r--r--dts/Bindings/net/macb.txt1
-rw-r--r--dts/Bindings/net/meson-dwmac.txt5
-rw-r--r--dts/Bindings/net/nixge.txt32
-rw-r--r--dts/Bindings/net/renesas,ravb.txt1
-rw-r--r--dts/Bindings/net/sff,sfp.txt5
-rw-r--r--dts/Bindings/net/socionext,uniphier-ave4.txt1
-rw-r--r--dts/Bindings/net/ti,dp83867.txt2
-rw-r--r--dts/Bindings/nvmem/imx-ocotp.txt23
-rw-r--r--dts/Bindings/nvmem/snvs-lpgpr.txt3
-rw-r--r--dts/Bindings/pci/hisilicon-histb-pcie.txt1
-rw-r--r--dts/Bindings/pci/mediatek-pcie.txt11
-rw-r--r--dts/Bindings/pci/qcom,pcie.txt4
-rw-r--r--dts/Bindings/pci/rcar-pci.txt6
-rw-r--r--dts/Bindings/perf/arm-ccn.txt (renamed from dts/Bindings/arm/ccn.txt)0
-rw-r--r--dts/Bindings/phy/meson-gxl-usb2-phy.txt4
-rw-r--r--dts/Bindings/phy/meson-gxl-usb3-phy.txt31
-rw-r--r--dts/Bindings/phy/nvidia,tegra20-usb-phy.txt4
-rw-r--r--dts/Bindings/phy/phy-hi3798cv200-combphy.txt59
-rw-r--r--dts/Bindings/phy/phy-hisi-inno-usb2.txt71
-rw-r--r--dts/Bindings/phy/phy-mapphone-mdm6600.txt29
-rw-r--r--dts/Bindings/phy/phy-mtk-tphy.txt4
-rw-r--r--dts/Bindings/phy/phy-rockchip-typec.txt35
-rw-r--r--dts/Bindings/phy/phy-stm32-usbphyc.txt73
-rw-r--r--dts/Bindings/phy/qcom-qmp-phy.txt6
-rw-r--r--dts/Bindings/phy/qcom-qusb2-phy.txt5
-rw-r--r--dts/Bindings/phy/rcar-gen3-phy-usb2.txt2
-rw-r--r--dts/Bindings/phy/rcar-gen3-phy-usb3.txt2
-rw-r--r--dts/Bindings/phy/sun4i-usb-phy.txt1
-rw-r--r--dts/Bindings/pinctrl/actions,s900-pinctrl.txt178
-rw-r--r--dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt1
-rw-r--r--dts/Bindings/pinctrl/axis,artpec6-pinctrl.txt16
-rw-r--r--dts/Bindings/pinctrl/fsl,imx6sll-pinctrl.txt40
-rw-r--r--dts/Bindings/pinctrl/img,tz1090-pdc-pinctrl.txt127
-rw-r--r--dts/Bindings/pinctrl/img,tz1090-pinctrl.txt227
-rw-r--r--dts/Bindings/pinctrl/pinctrl-mcp23s08.txt2
-rw-r--r--dts/Bindings/pinctrl/pinctrl-mt65xx.txt4
-rw-r--r--dts/Bindings/pinctrl/qcom,sdm845-pinctrl.txt176
-rw-r--r--dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt4
-rw-r--r--dts/Bindings/pinctrl/st,stm32-pinctrl.txt1
-rw-r--r--dts/Bindings/pmem/pmem-region.txt65
-rw-r--r--dts/Bindings/power/renesas,rcar-sysc.txt2
-rw-r--r--dts/Bindings/power/reset/gpio-poweroff.txt3
-rw-r--r--dts/Bindings/power/reset/ocelot-reset.txt14
-rw-r--r--dts/Bindings/power/supply/axp20x_battery.txt8
-rw-r--r--dts/Bindings/powerpc/nintendo/wii.txt9
-rw-r--r--dts/Bindings/pwm/ingenic,jz47xx-pwm.txt25
-rw-r--r--dts/Bindings/pwm/pwm-stm32-lp.txt3
-rw-r--r--dts/Bindings/pwm/pwm-sun4i.txt2
-rw-r--r--dts/Bindings/pwm/renesas,pwm-rcar.txt11
-rw-r--r--dts/Bindings/pwm/renesas,tpu-pwm.txt10
-rw-r--r--dts/Bindings/regulator/88pg86x.txt22
-rw-r--r--dts/Bindings/regulator/fixed-regulator.txt1
-rw-r--r--dts/Bindings/regulator/gpio-regulator.txt2
-rw-r--r--dts/Bindings/regulator/qcom,smd-rpm-regulator.txt48
-rw-r--r--dts/Bindings/reset/renesas,rst.txt2
-rw-r--r--dts/Bindings/reset/st,stm32mp1-rcc.txt6
-rw-r--r--dts/Bindings/rng/imx-rng.txt (renamed from dts/Bindings/rng/imx-rngc.txt)11
-rw-r--r--dts/Bindings/rng/ks-sa-rng.txt21
-rw-r--r--dts/Bindings/rng/omap_rng.txt7
-rw-r--r--dts/Bindings/rng/st,stm32-rng.txt4
-rw-r--r--dts/Bindings/rtc/isil,isl12026.txt28
-rw-r--r--dts/Bindings/scsi/hisilicon-sas.txt7
-rw-r--r--dts/Bindings/serial/8250.txt1
-rw-r--r--dts/Bindings/serial/amlogic,meson-uart.txt2
-rw-r--r--dts/Bindings/serial/axis,etraxfs-uart.txt22
-rw-r--r--dts/Bindings/serial/mvebu-uart.txt2
-rw-r--r--dts/Bindings/serial/renesas,sci-serial.txt4
-rw-r--r--dts/Bindings/serial/st,stm32-usart.txt2
-rw-r--r--dts/Bindings/soc/bcm/brcm,bcm2835-vchiq.txt16
-rw-r--r--dts/Bindings/soc/mediatek/scpsys.txt5
-rw-r--r--dts/Bindings/sound/ak4458.txt23
-rw-r--r--dts/Bindings/sound/ak5558.txt22
-rw-r--r--dts/Bindings/sound/brcm,bcm2835-i2s.txt9
-rw-r--r--dts/Bindings/sound/da7219.txt6
-rw-r--r--dts/Bindings/sound/dmic.txt2
-rw-r--r--dts/Bindings/sound/fsl-asoc-card.txt1
-rw-r--r--dts/Bindings/sound/imx-audio-wm8962.txt53
-rw-r--r--dts/Bindings/sound/max98090.txt2
-rw-r--r--dts/Bindings/sound/maxim,max9759.txt18
-rw-r--r--dts/Bindings/sound/mt2701-afe-pcm.txt2
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-rw-r--r--dts/src/arm64/hisilicon/hi3660.dtsi34
-rw-r--r--dts/src/arm64/hisilicon/hi6220-hikey.dts2
-rw-r--r--dts/src/arm64/hisilicon/hi6220.dtsi10
-rw-r--r--dts/src/arm64/hisilicon/hip06.dtsi56
-rw-r--r--dts/src/arm64/hisilicon/hip07.dtsi33
-rw-r--r--dts/src/arm64/marvell/armada-371x.dtsi38
-rw-r--r--dts/src/arm64/marvell/armada-3720-db.dts39
-rw-r--r--dts/src/arm64/marvell/armada-3720-espressobin.dts41
-rw-r--r--dts/src/arm64/marvell/armada-372x.dtsi38
-rw-r--r--dts/src/arm64/marvell/armada-37xx.dtsi38
-rw-r--r--dts/src/arm64/marvell/armada-7020.dtsi41
-rw-r--r--dts/src/arm64/marvell/armada-7040-db.dts93
-rw-r--r--dts/src/arm64/marvell/armada-7040.dtsi41
-rw-r--r--dts/src/arm64/marvell/armada-70x0.dtsi41
-rw-r--r--dts/src/arm64/marvell/armada-8020.dtsi41
-rw-r--r--dts/src/arm64/marvell/armada-8040-db.dts87
-rw-r--r--dts/src/arm64/marvell/armada-8040-mcbin.dts65
-rw-r--r--dts/src/arm64/marvell/armada-8040.dtsi41
-rw-r--r--dts/src/arm64/marvell/armada-8080-db.dts41
-rw-r--r--dts/src/arm64/marvell/armada-8080.dtsi41
-rw-r--r--dts/src/arm64/marvell/armada-80x0.dtsi41
-rw-r--r--dts/src/arm64/marvell/armada-ap806-dual.dtsi41
-rw-r--r--dts/src/arm64/marvell/armada-ap806-quad.dtsi41
-rw-r--r--dts/src/arm64/marvell/armada-ap806.dtsi41
-rw-r--r--dts/src/arm64/marvell/armada-ap810-ap0-octa-core.dtsi41
-rw-r--r--dts/src/arm64/marvell/armada-ap810-ap0.dtsi41
-rw-r--r--dts/src/arm64/marvell/armada-common.dtsi2
-rw-r--r--dts/src/arm64/marvell/armada-cp110.dtsi118
-rw-r--r--dts/src/arm64/mediatek/mt2712-evb.dts4
-rw-r--r--dts/src/arm64/mediatek/mt2712e.dtsi9
-rw-r--r--dts/src/arm64/mediatek/mt6380.dtsi86
-rw-r--r--dts/src/arm64/mediatek/mt7622-rfb1.dts469
-rw-r--r--dts/src/arm64/mediatek/mt7622.dtsi675
-rw-r--r--dts/src/arm64/nvidia/tegra194-p2888.dtsi248
-rw-r--r--dts/src/arm64/nvidia/tegra194-p2972-0000.dts16
-rw-r--r--dts/src/arm64/nvidia/tegra194.dtsi344
-rw-r--r--dts/src/arm64/nvidia/tegra210-p2597.dtsi5
-rw-r--r--dts/src/arm64/nvidia/tegra210.dtsi16
-rw-r--r--dts/src/arm64/qcom/msm8916.dtsi60
-rw-r--r--dts/src/arm64/qcom/msm8996.dtsi23
-rw-r--r--dts/src/arm64/renesas/r8a7795-es1.dtsi3
-rw-r--r--dts/src/arm64/renesas/r8a7795.dtsi194
-rw-r--r--dts/src/arm64/renesas/r8a7796.dtsi130
-rw-r--r--dts/src/arm64/renesas/r8a77965-salvator-x.dts21
-rw-r--r--dts/src/arm64/renesas/r8a77965-salvator-xs.dts21
-rw-r--r--dts/src/arm64/renesas/r8a77965.dtsi878
-rw-r--r--dts/src/arm64/renesas/r8a77970-eagle.dts33
-rw-r--r--dts/src/arm64/renesas/r8a77970-v3msk.dts11
-rw-r--r--dts/src/arm64/renesas/r8a77970.dtsi218
-rw-r--r--dts/src/arm64/renesas/r8a77980-condor.dts58
-rw-r--r--dts/src/arm64/renesas/r8a77980.dtsi385
-rw-r--r--dts/src/arm64/renesas/r8a77995-draak.dts124
-rw-r--r--dts/src/arm64/renesas/r8a77995.dtsi193
-rw-r--r--dts/src/arm64/renesas/salvator-common.dtsi8
-rw-r--r--dts/src/arm64/renesas/ulcb.dtsi1
-rw-r--r--dts/src/arm64/rockchip/rk3328-roc-cc.dts267
-rw-r--r--dts/src/arm64/rockchip/rk3328.dtsi6
-rw-r--r--dts/src/arm64/rockchip/rk3368-lion-haikou.dts146
-rw-r--r--dts/src/arm64/rockchip/rk3368-lion.dtsi317
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru.dtsi13
-rw-r--r--dts/src/arm64/rockchip/rk3399-puma-haikou.dts71
-rw-r--r--dts/src/arm64/rockchip/rk3399-puma.dtsi28
-rw-r--r--dts/src/arm64/rockchip/rk3399-sapphire-excavator.dts44
-rw-r--r--dts/src/arm64/rockchip/rk3399-sapphire.dts12
-rw-r--r--dts/src/arm64/rockchip/rk3399-sapphire.dtsi67
-rw-r--r--dts/src/arm64/rockchip/rk3399.dtsi79
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11-global.dts109
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11-ref.dts25
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11.dtsi127
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-global.dts111
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-ref.dts25
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20.dtsi138
-rw-r--r--dts/src/arm64/socionext/uniphier-pxs3-ref.dts36
-rw-r--r--dts/src/arm64/socionext/uniphier-pxs3.dtsi50
-rw-r--r--dts/src/arm64/sprd/sc2731.dtsi169
-rw-r--r--dts/src/arm64/sprd/sp9860g-1h10.dts2
-rw-r--r--dts/src/arm64/sprd/whale2.dtsi81
-rw-r--r--dts/src/arm64/xilinx/zynqmp-clk.dtsi213
-rw-r--r--dts/src/arm64/xilinx/zynqmp-ep108-clk.dtsi1
-rw-r--r--dts/src/arm64/xilinx/zynqmp-ep108.dts13
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1232-revA.dts54
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1254-revA.dts42
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1275-revA.dts42
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts131
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts168
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts150
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts178
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts125
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu100-revC.dts289
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu102-rev1.0.dts36
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu102-revA.dts548
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu102-revB.dts40
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu104-revA.dts195
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu106-revA.dts522
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu111-revA.dts444
-rw-r--r--dts/src/arm64/xilinx/zynqmp.dtsi17
-rw-r--r--dts/src/cris/artpec3.dtsi47
-rw-r--r--dts/src/cris/dev88.dts68
-rw-r--r--dts/src/cris/etraxfs.dtsi47
-rw-r--r--dts/src/cris/p1343.dts77
-rw-r--r--dts/src/metag/skeleton.dts10
-rw-r--r--dts/src/metag/skeleton.dtsi15
-rw-r--r--dts/src/metag/tz1090.dtsi108
-rw-r--r--dts/src/metag/tz1090_generic.dts10
-rw-r--r--dts/src/mips/brcm/bcm7125.dtsi7
-rw-r--r--dts/src/mips/brcm/bcm7346.dtsi62
-rw-r--r--dts/src/mips/brcm/bcm7358.dtsi17
-rw-r--r--dts/src/mips/brcm/bcm7360.dtsi62
-rw-r--r--dts/src/mips/brcm/bcm7362.dtsi62
-rw-r--r--dts/src/mips/brcm/bcm7420.dtsi7
-rw-r--r--dts/src/mips/brcm/bcm7425.dtsi89
-rw-r--r--dts/src/mips/brcm/bcm7435.dtsi89
-rw-r--r--dts/src/mips/brcm/bcm97125cbmb.dts4
-rw-r--r--dts/src/mips/brcm/bcm97346dbsmb.dts8
-rw-r--r--dts/src/mips/brcm/bcm97358svmb.dts8
-rw-r--r--dts/src/mips/brcm/bcm97360svmb.dts8
-rw-r--r--dts/src/mips/brcm/bcm97362svmb.dts8
-rw-r--r--dts/src/mips/brcm/bcm97420c.dts4
-rw-r--r--dts/src/mips/brcm/bcm97425svmb.dts8
-rw-r--r--dts/src/mips/brcm/bcm97435svmb.dts8
-rw-r--r--dts/src/mips/img/boston.dts8
-rw-r--r--dts/src/mips/ingenic/ci20.dts8
-rw-r--r--dts/src/mips/mscc/ocelot.dtsi117
-rw-r--r--dts/src/mips/mscc/ocelot_pcb123.dts27
-rw-r--r--dts/src/nds32/ae3xx.dts85
-rw-r--r--dts/src/powerpc/acadia.dts2
-rw-r--r--dts/src/powerpc/adder875-redboot.dts2
-rw-r--r--dts/src/powerpc/adder875-uboot.dts2
-rw-r--r--dts/src/powerpc/akebono.dts2
-rw-r--r--dts/src/powerpc/amigaone.dts2
-rw-r--r--dts/src/powerpc/asp834x-redboot.dts2
-rw-r--r--dts/src/powerpc/bamboo.dts2
-rw-r--r--dts/src/powerpc/c2k.dts2
-rw-r--r--dts/src/powerpc/currituck.dts2
-rw-r--r--dts/src/powerpc/digsy_mtc.dts2
-rw-r--r--dts/src/powerpc/ebony.dts2
-rw-r--r--dts/src/powerpc/eiger.dts2
-rw-r--r--dts/src/powerpc/ep405.dts2
-rw-r--r--dts/src/powerpc/fsl/mvme7100.dts2
-rw-r--r--dts/src/powerpc/fsp2.dts2
-rw-r--r--dts/src/powerpc/holly.dts2
-rw-r--r--dts/src/powerpc/hotfoot.dts2
-rw-r--r--dts/src/powerpc/icon.dts2
-rw-r--r--dts/src/powerpc/iss4xx-mpic.dts2
-rw-r--r--dts/src/powerpc/iss4xx.dts2
-rw-r--r--dts/src/powerpc/katmai.dts2
-rw-r--r--dts/src/powerpc/klondike.dts2
-rw-r--r--dts/src/powerpc/ksi8560.dts2
-rw-r--r--dts/src/powerpc/media5200.dts2
-rw-r--r--dts/src/powerpc/mpc8272ads.dts2
-rw-r--r--dts/src/powerpc/mpc866ads.dts2
-rw-r--r--dts/src/powerpc/mpc885ads.dts2
-rw-r--r--dts/src/powerpc/mvme5100.dts2
-rw-r--r--dts/src/powerpc/obs600.dts2
-rw-r--r--dts/src/powerpc/pq2fads.dts2
-rw-r--r--dts/src/powerpc/rainier.dts2
-rw-r--r--dts/src/powerpc/redwood.dts2
-rw-r--r--dts/src/powerpc/sam440ep.dts2
-rw-r--r--dts/src/powerpc/sequoia.dts2
-rw-r--r--dts/src/powerpc/storcenter.dts2
-rw-r--r--dts/src/powerpc/taishan.dts2
-rw-r--r--dts/src/powerpc/virtex440-ml507.dts2
-rw-r--r--dts/src/powerpc/virtex440-ml510.dts2
-rw-r--r--dts/src/powerpc/walnut.dts2
-rw-r--r--dts/src/powerpc/warp.dts2
-rw-r--r--dts/src/powerpc/wii.dts21
-rw-r--r--dts/src/powerpc/xpedite5200_xmon.dts2
-rw-r--r--dts/src/powerpc/yosemite.dts2
-rw-r--r--images/.gitignore1
-rw-r--r--images/Makefile.imx15
-rw-r--r--include/bootsource.h1
-rw-r--r--include/linux/bitfield.h152
-rw-r--r--include/linux/bug.h25
-rw-r--r--include/linux/build_bug.h83
-rw-r--r--include/memory.h8
-rw-r--r--include/mfd/mc13xxx.h19
-rw-r--r--include/reset_source.h17
-rw-r--r--include/serial/lpuart.h21
1298 files changed, 48548 insertions, 22476 deletions
diff --git a/Makefile b/Makefile
index e298c7d53..88c199173 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
VERSION = 2018
-PATCHLEVEL = 04
+PATCHLEVEL = 05
SUBLEVEL = 0
EXTRAVERSION =
NAME = None
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 30f4c299f..b2fea4a40 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -1,4 +1,5 @@
# keep sorted by CONFIG_* macro name.
+obj-$(CONFIG_MACH_ADVANTECH_ROM_742X) += advantech-mx6/
obj-$(CONFIG_MACH_AFI_GF) += afi-gf/
obj-$(CONFIG_MACH_ANIMEO_IP) += animeo_ip/
obj-$(CONFIG_MACH_ARCHOSG9) += archosg9/
diff --git a/arch/arm/boards/advantech-mx6/Makefile b/arch/arm/boards/advantech-mx6/Makefile
new file mode 100644
index 000000000..01c7a259e
--- /dev/null
+++ b/arch/arm/boards/advantech-mx6/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/advantech-mx6/board.c b/arch/arm/boards/advantech-mx6/board.c
new file mode 100644
index 000000000..4a30a845f
--- /dev/null
+++ b/arch/arm/boards/advantech-mx6/board.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2018 Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <platform_data/eth-fec.h>
+#include <bootsource.h>
+#include <mach/bbu.h>
+
+static int ar8035_phy_fixup(struct phy_device *dev)
+{
+ u16 val;
+
+ /* Ar803x phy SmartEEE feature cause link status generates glitch,
+ * which cause ethernet link down/up issue, so disable SmartEEE
+ */
+ phy_write(dev, 0xd, 0x3);
+ phy_write(dev, 0xe, 0x805d);
+ phy_write(dev, 0xd, 0x4003);
+
+ val = phy_read(dev, 0xe);
+ phy_write(dev, 0xe, val & ~BIT(8));
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(dev, 0xd, 0x7);
+ phy_write(dev, 0xe, 0x8016);
+ phy_write(dev, 0xd, 0x4007);
+
+ val = phy_read(dev, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(dev, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(dev, 0x1d, 0x5);
+ val = phy_read(dev, 0x1e);
+ val |= 0x0100;
+ phy_write(dev, 0x1e, val);
+
+ return 0;
+}
+
+static int advantech_mx6_devices_init(void)
+{
+ int ret;
+ char *environment_path, *envdev;
+
+ if (!of_machine_is_compatible("advantech,imx6dl-rom-7421"))
+ return 0;
+
+ phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup);
+
+ switch (bootsource_get()) {
+ case BOOTSOURCE_MMC:
+ environment_path = basprintf("/chosen/environment-sd%d",
+ bootsource_get_instance() + 1);
+ if (bootsource_get_instance() + 1 == 4)
+ envdev = "eMMC";
+ else if (bootsource_get_instance() + 1 == 2)
+ envdev = "microSD";
+ else
+ envdev = "MMC";
+ break;
+ case BOOTSOURCE_SPI:
+ envdev = "SPI";
+ environment_path = basprintf("/chosen/environment-spi");
+ break;
+ default:
+ environment_path = basprintf("/chosen/environment-sd4");
+ envdev = "MMC";
+ break;
+ }
+
+ if (environment_path) {
+ ret = of_device_enable_path(environment_path);
+ if (ret < 0)
+ pr_warn("Failed to enable env partition '%s' (%d)\n",
+ environment_path, ret);
+ free(environment_path);
+ }
+
+ pr_notice("Using environment in %s\n", envdev);
+
+ imx6_bbu_internal_mmc_register_handler("mmc3", "/dev/mmc3",
+ BBU_HANDLER_FLAG_DEFAULT);
+
+ return 0;
+}
+device_initcall(advantech_mx6_devices_init);
diff --git a/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg
new file mode 100644
index 000000000..996ecc708
--- /dev/null
+++ b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg
@@ -0,0 +1,66 @@
+soc imx6
+loadaddr 0x10000000
+dcdofs 0x400
+
+wm 32 0x020e0774 0x000C0000
+wm 32 0x020e0754 0x00000000
+wm 32 0x020e04ac 0x00000030
+wm 32 0x020e04b0 0x00000030
+wm 32 0x020e0464 0x00000030
+wm 32 0x020e0490 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e0494 0x00000030
+wm 32 0x020e04a0 0x00000000
+wm 32 0x020e04b4 0x00000030
+wm 32 0x020e04b8 0x00000030
+wm 32 0x020e076c 0x00000030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e04bc 0x00000030
+wm 32 0x020e04c0 0x00000030
+wm 32 0x020e04c4 0x00000030
+wm 32 0x020e04c8 0x00000030
+wm 32 0x020e0760 0x00020000
+wm 32 0x020e0764 0x00000030
+wm 32 0x020e0770 0x00000030
+wm 32 0x020e0778 0x00000030
+wm 32 0x020e077c 0x00000030
+wm 32 0x020e0470 0x00000030
+wm 32 0x020e0474 0x00000030
+wm 32 0x020e0478 0x00000030
+wm 32 0x020e047c 0x00000030
+wm 32 0x021b0800 0xa1390003
+wm 32 0x021b080c 0x001F001F
+wm 32 0x021b0810 0x001F001F
+wm 32 0x021b083c 0x42480248
+wm 32 0x021b0840 0x022C0234
+wm 32 0x021b0848 0x3E404244
+wm 32 0x021b0850 0x30302C30
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b0004 0x0002002D
+wm 32 0x021b0008 0x00333030
+wm 32 0x021b000c 0x3F435333
+wm 32 0x021b0010 0xB68E8B63
+wm 32 0x021b0014 0x01FF00DB
+wm 32 0x021b0018 0x00001740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x00431023
+wm 32 0x021b0040 0x00000017
+wm 32 0x021b0000 0x83190000
+wm 32 0x021b001c 0x04008032
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x00048031
+wm 32 0x021b001c 0x05208030
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b0020 0x00005800
+wm 32 0x021b0818 0x00011117
+wm 32 0x021b0004 0x0002556D
+wm 32 0x021b0404 0x00011006
+wm 32 0x021b001c 0x00000000
+wm 32 0x020e0010 0xF00000CF
+wm 32 0x020e0018 0x007F007F
+wm 32 0x020e001c 0x007F007F
diff --git a/arch/arm/boards/advantech-mx6/lowlevel.c b/arch/arm/boards/advantech-mx6/lowlevel.c
new file mode 100644
index 000000000..8921cd4dd
--- /dev/null
+++ b/arch/arm/boards/advantech-mx6/lowlevel.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2018 Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <debug_ll.h>
+#include <common.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <image-metadata.h>
+#include <mach/generic.h>
+#include <mach/esdctl.h>
+#include <mach/iomux-mx6.h>
+#include <linux/sizes.h>
+
+#include <linux/sizes.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+static inline void setup_uart(void)
+{
+ void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;
+
+ imx6_ungate_all_peripherals();
+
+ imx_setup_pad(iomuxbase, MX6Q_PAD_CSI0_DAT10__UART1_TXD);
+
+ imx6_uart_setup_ll();
+
+ putc_ll('>');
+}
+
+extern char __dtb_imx6dl_advantech_rom_7421_start[];
+
+ENTRY_FUNCTION(start_advantech_imx6dl_rom_7421, r0, r1, r2)
+{
+ imx6_cpu_lowlevel_init();
+
+ relocate_to_current_adr();
+ setup_c();
+ barrier();
+
+ if (IS_ENABLED(CONFIG_DEBUG_LL))
+ setup_uart();
+
+ imx6q_barebox_entry(__dtb_imx6dl_advantech_rom_7421_start);
+}
diff --git a/arch/arm/boards/datamodul-edm-qmx6/board.c b/arch/arm/boards/datamodul-edm-qmx6/board.c
index 043a93461..d93c940e3 100644
--- a/arch/arm/boards/datamodul-edm-qmx6/board.c
+++ b/arch/arm/boards/datamodul-edm-qmx6/board.c
@@ -132,7 +132,7 @@ static int realq7_device_init(void)
}
break;
default:
- case BOOTSOURCE_SPI:
+ case BOOTSOURCE_SPI_NOR:
of_device_enable_path("/chosen/environment-spi");
break;
}
diff --git a/arch/arm/boards/dfi-fs700-m60/board.c b/arch/arm/boards/dfi-fs700-m60/board.c
index bef4612d9..2cb8e3106 100644
--- a/arch/arm/boards/dfi-fs700-m60/board.c
+++ b/arch/arm/boards/dfi-fs700-m60/board.c
@@ -105,7 +105,7 @@ static int dfi_fs700_m60_init(void)
phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, ar8031_phy_fixup);
- if (bootsource_get() == BOOTSOURCE_SPI)
+ if (bootsource_get() == BOOTSOURCE_SPI_NOR)
flag_spi |= BBU_HANDLER_FLAG_DEFAULT;
else
flag_mmc |= BBU_HANDLER_FLAG_DEFAULT;
diff --git a/arch/arm/boards/freescale-vf610-twr/lowlevel.c b/arch/arm/boards/freescale-vf610-twr/lowlevel.c
index deabe4e37..8fec9f4b9 100644
--- a/arch/arm/boards/freescale-vf610-twr/lowlevel.c
+++ b/arch/arm/boards/freescale-vf610-twr/lowlevel.c
@@ -3,6 +3,7 @@
#include <mach/generic.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
+#include <mach/esdctl.h>
#include <mach/vf610-regs.h>
#include <mach/clock-vf610.h>
#include <mach/iomux-vf610.h>
@@ -13,27 +14,21 @@ static inline void setup_uart(void)
void __iomem *iomuxbase = IOMEM(VF610_IOMUXC_BASE_ADDR);
vf610_ungate_all_peripherals();
-
- /*
- * VF610_PAD_PTB4__UART1_TX
- */
- writel(VF610_UART_PAD_CTRL | (2 << 20), iomuxbase + 0x0068);
- writel(0, iomuxbase + 0x0380);
-
+ vf610_setup_pad(iomuxbase, VF610_PAD_PTB4__UART1_TX);
vf610_uart_setup_ll();
+
+ putc_ll('>');
}
extern char __dtb_vf610_twr_start[];
ENTRY_FUNCTION(start_vf610_twr, r0, r1, r2)
{
- void *fdt;
vf610_cpu_lowlevel_init();
if (IS_ENABLED(CONFIG_DEBUG_LL))
setup_uart();
- fdt = __dtb_vf610_twr_start + get_runtime_offset();
- barebox_arm_entry(0x80000000, SZ_128M, fdt);
+ vf610_barebox_entry(__dtb_vf610_twr_start + get_runtime_offset());
}
diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c
index 717a22963..34a0fe418 100644
--- a/arch/arm/boards/phytec-som-imx6/board.c
+++ b/arch/arm/boards/phytec-som-imx6/board.c
@@ -28,6 +28,7 @@
#include <gpio.h>
#include <init.h>
#include <of.h>
+#include <i2c/i2c.h>
#include <mach/bbu.h>
#include <platform_data/eth-fec.h>
#include <mfd/imx6q-iomuxc-gpr.h>
@@ -51,6 +52,14 @@
#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
+#define DA9062_I2C_ADDRESS 0x58
+
+#define DA9062_BUCK1_CFG 0x9e
+#define DA9062_BUCK2_CFG 0x9d
+#define DA9062_BUCK3_CFG 0xa0
+#define DA9062_BUCK4_CFG 0x9f
+#define DA9062_BUCKx_MODE_SYNCHRONOUS (2 << 6)
+
static void phyflex_err006282_workaround(void)
{
/*
@@ -66,7 +75,7 @@ static void phyflex_err006282_workaround(void)
mdelay(2);
gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
- if (cpu_is_mx6q() || cpu_is_mx6d())
+ if (cpu_is_mx6q() || cpu_is_mx6d() || cpu_is_mx6qp() || cpu_is_mx6dp())
mxc_iomux_v3_setup_pad(MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD);
else if (cpu_is_mx6dl() || cpu_is_mx6s())
mxc_iomux_v3_setup_pad(MX6DL_PAD_SD4_DAT3__GPIO_2_11);
@@ -96,6 +105,45 @@ int ksz8081_phy_fixup(struct phy_device *phydev)
return 0;
}
+static int phycore_da9062_setup_buck_mode(void)
+{
+ struct i2c_adapter *adapter = NULL;
+ struct i2c_client client;
+ unsigned char value;
+ int bus = 0;
+ int ret;
+
+ adapter = i2c_get_adapter(bus);
+ if (!adapter)
+ return -ENODEV;
+
+ client.adapter = adapter;
+ client.addr = DA9062_I2C_ADDRESS;
+
+ value = DA9062_BUCKx_MODE_SYNCHRONOUS;
+
+ ret = i2c_write_reg(&client, DA9062_BUCK1_CFG, &value, 1);
+ if (ret != 1)
+ goto err_out;
+
+ ret = i2c_write_reg(&client, DA9062_BUCK2_CFG, &value, 1);
+ if (ret != 1)
+ goto err_out;
+
+ ret = i2c_write_reg(&client, DA9062_BUCK3_CFG, &value, 1);
+ if (ret != 1)
+ goto err_out;
+
+ ret = i2c_write_reg(&client, DA9062_BUCK4_CFG, &value, 1);
+ if (ret != 1)
+ goto err_out;
+
+ return 0;
+
+err_out:
+ return ret;
+}
+
static int physom_imx6_devices_init(void)
{
int ret;
@@ -125,8 +173,12 @@ static int physom_imx6_devices_init(void)
} else if (of_machine_is_compatible("phytec,imx6q-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
+ || of_machine_is_compatible("phytec,imx6qp-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
+ if (phycore_da9062_setup_buck_mode())
+ pr_err("Setting PMIC BUCK mode failed\n");
+
barebox_set_hostname("phyCORE-i.MX6");
default_environment_path = "/chosen/environment-spinor";
default_envdev = "SPI NOR flash";
@@ -152,7 +204,7 @@ static int physom_imx6_devices_init(void)
environment_path = basprintf("/chosen/environment-nand");
envdev = "NAND flash";
break;
- case BOOTSOURCE_SPI:
+ case BOOTSOURCE_SPI_NOR:
environment_path = basprintf("/chosen/environment-spinor");
envdev = "SPI NOR flash";
break;
@@ -184,7 +236,8 @@ static int physom_imx6_devices_init(void)
defaultenv_append_directory(defaultenv_physom_imx6);
/* Overwrite file /env/init/automount */
- if (of_machine_is_compatible("phytec,imx6q-pcm058-nand")
+ if (of_machine_is_compatible("phytec,imx6qp-pcm058-nand")
+ || of_machine_is_compatible("phytec,imx6q-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/boot/emmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/boot/emmc
new file mode 100644
index 000000000..7ba1d0d0c
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/boot/emmc
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+global.bootm.image="/mnt/emmc/zImage"
+global.bootm.oftree="/mnt/emmc/oftree"
+global.linux.bootargs.dyn.root="root=/dev/mmcblk1p2 rootwait rw"
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/emmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/emmc
new file mode 100644
index 000000000..f0d019c3e
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/emmc
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+if [ -f /mnt/mmc3/android ]; then
+ # configure here the android specific stuff
+ global linux.bootargs.sec="selinux=0 enforcing=0"
+fi
+
+global.bootm.image="/mnt/mmc3/zImage"
+global.bootm.oftree="/mnt/mmc3/oftree"
+global.linux.bootargs.dyn.root="root=/dev/mmcblk3p2 rootwait rw"
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc
index 332fc26ad..3e175122d 100644
--- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc
@@ -1,5 +1,10 @@
#!/bin/sh
-global.bootm.image="/mnt/mmc/linuximage"
+if [ -f /mnt/mmc/android ]; then
+ # configure here the android specific stuff
+ global linux.bootargs.sec="selinux=0 enforcing=0"
+fi
+
+global.bootm.image="/mnt/mmc/zImage"
global.bootm.oftree="/mnt/mmc/oftree"
global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootwait rw"
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand
index a23aa21cc..0c2b1cbe4 100644
--- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand
@@ -1,5 +1,12 @@
#!/bin/sh
-global.bootm.image="/dev/nand0.kernel.bb"
-global.bootm.oftree="/dev/nand0.oftree.bb"
+[ ! -e /dev/nand0.root.ubi ] && ubiattach /dev/nand0.root
+
+if [ -e /dev/nand0.root.ubi.system ]; then
+ # configure here the android specific stuff
+ global linux.bootargs.sec="selinux=0 enforcing=0"
+fi
+
+global.bootm.image="/dev/nand0.root.ubi.kernel"
+global.bootm.oftree="/dev/nand0.root.ubi.oftree"
global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw"
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount
index 4b223d803..fea64d627 100644
--- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount
@@ -7,3 +7,8 @@ automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp'
mkdir -p /mnt/mmc
automount -d /mnt/mmc 'mmc2.probe=1 && [ -e /dev/mmc2.0 ] && mount /dev/mmc2.0 /mnt/mmc'
+
+if [ -e /dev/mmc3 ]; then
+ mkdir -p /mnt/mmc3
+ automount -d /mnt/mmc3 'mmc3.probe=1 && [ -e /dev/mmc3.0 ] && mount /dev/mmc3.0 /mnt/mmc3'
+fi
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg
new file mode 100644
index 000000000..bf95d0f6a
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg
@@ -0,0 +1,8 @@
+#define SETUP_MDCFG0 \
+ wm 32 0x021b000c 0x8c929b85
+
+#define SETUP_MDASP_MDCTL \
+ wm 32 0x021b0040 0x00000027; \
+ wm 32 0x021b0000 0x84190000
+
+#include "flash-header-phytec-pcm058dl.h"
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg
new file mode 100644
index 000000000..bf85f0a19
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg
@@ -0,0 +1,8 @@
+#define SETUP_MDCFG0 \
+ wm 32 0x021b000c 0x555A7955
+
+#define SETUP_MDASP_MDCTL \
+ wm 32 0x021b0040 0x00000027; \
+ wm 32 0x021b0000 0x831A0000
+
+#include "flash-header-phytec-pcm058qp.h"
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h
new file mode 100644
index 000000000..6e7b740a6
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h
@@ -0,0 +1,112 @@
+soc imx6
+loadaddr 0x10000000
+dcdofs 0x400
+
+/* NOC setup */
+wm 32 0x00bb0008 0x00000000
+wm 32 0x00bb000c 0x2891E41A
+wm 32 0x00bb0038 0x00000564
+wm 32 0x00bb0014 0x00000040
+wm 32 0x00bb0028 0x00000020
+wm 32 0x00bb002c 0x00000020
+
+wm 32 0x020e0798 0x000C0000
+wm 32 0x020e0758 0x00000000
+wm 32 0x020e0588 0x00000030
+wm 32 0x020e0594 0x00000030
+wm 32 0x020e056c 0x00000030
+wm 32 0x020e0578 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e057c 0x00000030
+wm 32 0x020e058c 0x00000000
+wm 32 0x020e059c 0x00000030
+wm 32 0x020e05a0 0x00000030
+wm 32 0x020e0590 0x00003000
+wm 32 0x020e0598 0x00003000
+wm 32 0x020e078c 0x00000030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e05a8 0x00000028
+wm 32 0x020e05b0 0x00000028
+wm 32 0x020e0524 0x00000028
+wm 32 0x020e051c 0x00000028
+wm 32 0x020e0518 0x00000028
+wm 32 0x020e050c 0x00000028
+wm 32 0x020e05b8 0x00000028
+wm 32 0x020e05c0 0x00000028
+wm 32 0x020e0774 0x00020000
+wm 32 0x020e0784 0x00000028
+wm 32 0x020e0788 0x00000028
+wm 32 0x020e0794 0x00000028
+wm 32 0x020e079c 0x00000028
+wm 32 0x020e07a0 0x00000028
+wm 32 0x020e07a4 0x00000028
+wm 32 0x020e07a8 0x00000028
+wm 32 0x020e0748 0x00000028
+wm 32 0x020e05ac 0x00000028
+wm 32 0x020e05b4 0x00000028
+wm 32 0x020e0528 0x00000028
+wm 32 0x020e0520 0x00000028
+wm 32 0x020e0514 0x00000028
+wm 32 0x020e0510 0x00000028
+wm 32 0x020e05bc 0x00000028
+wm 32 0x020e05c4 0x00000028
+wm 32 0x021b0800 0xa1390003
+wm 32 0x021b4800 0xa1380003
+wm 32 0x021b080c 0x00140014
+wm 32 0x021b0810 0x00230018
+wm 32 0x021b480c 0x000A001E
+wm 32 0x021b4810 0x000A0015
+wm 32 0x021b083c 0x43080314
+wm 32 0x021b0840 0x02680300
+wm 32 0x021b483c 0x430C0318
+wm 32 0x021b4840 0x03000254
+wm 32 0x021b0848 0x3A323234
+wm 32 0x021b4848 0x3E3C3242
+wm 32 0x021b0850 0x2A2E3632
+wm 32 0x021b4850 0x3C323E34
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b0004 0x00020036
+wm 32 0x021b0008 0x09444040
+
+SETUP_MDCFG0
+
+wm 32 0x021b0010 0xFF328F64
+wm 32 0x021b0014 0x01FF00DB
+wm 32 0x021b0018 0x00011740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x003F1023
+
+SETUP_MDASP_MDCTL
+
+wm 32 0x021b001c 0x04088032
+wm 32 0x021b001c 0x0408803a
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x0000803b
+wm 32 0x021b001c 0x00048031
+wm 32 0x021b001c 0x00048039
+wm 32 0x021b001c 0x09408030
+wm 32 0x021b001c 0x09408038
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b001c 0x04008048
+wm 32 0x021b0020 0x00007800
+wm 32 0x021b0818 0x00011117
+wm 32 0x021b4818 0x00011117
+wm 32 0x021b0890 0x00400c58
+wm 32 0x021b0400 0x14420000
+wm 32 0x021b0004 0x00025576
+wm 32 0x021b0404 0x00011006
+wm 32 0x021b001c 0x00000000
+wm 32 0x020e0010 0xf00000ff
+wm 32 0x020e0018 0x007F007F
+wm 32 0x020e001c 0x007F007F
+wm 32 0x020c8000 0x80002021
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg
index 156eea971..7b64e5d2f 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg
@@ -1,5 +1,5 @@
#define SETUP_MDCFG0 \
- wm 32 0x021b000c 0x565c9b85
+ wm 32 0x021b000c 0x41447525
#define SETUP_MDASP_MDCTL \
wm 32 0x021b0040 0x00000027; \
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
index e76867004..04c489d7e 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
@@ -1,5 +1,5 @@
#define SETUP_MDCFG0 \
- wm 32 0x021b000c 0x8c929b85
+ wm 32 0x021b000c 0x2d307525
#define SETUP_MDASP_MDCTL \
wm 32 0x021b0040 0x00000017; \
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h
index 405529ddf..b0f3faa0b 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h
@@ -74,7 +74,7 @@ wm 32 MX6_MMDC_P0_MDOTC 0x09444040
SETUP_MDCFG0
-wm 32 MX6_MMDC_P0_MDCFG1 0xff538f64
+wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8b64
wm 32 MX6_MMDC_P0_MDCFG2 0x01ff0124
wm 32 MX6_MMDC_P0_MDMISC 0x00091740
wm 32 MX6_MMDC_P0_MDSCR 0x00008000
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg
index 26fe2b2f7..ebe5a968b 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg
@@ -1,5 +1,5 @@
#define SETUP_MDCFG0 \
- wm 32 0x021b000c 0x3c409b85
+ wm 32 0x021b000c 0x2D307525
#define SETUP_MDASP_MDCTL \
wm 32 0x021b0040 0x0000000B; \
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg
index babb0dfe2..5f1585a40 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg
@@ -1,5 +1,5 @@
#define SETUP_MDCFG0 \
- wm 32 0x021b000c 0x3c409b85
+ wm 32 0x021b000c 0x2D307525
#define SETUP_MDASP_MDCTL \
wm 32 0x021b0040 0x0000000F; \
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg
index 6a46cd958..5ff3ec69d 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg
@@ -1,5 +1,5 @@
#define SETUP_MDCFG0 \
- wm 32 0x021b000c 0x565c9b85
+ wm 32 0x021b000c 0x41447525
#define SETUP_MDASP_MDCTL \
wm 32 0x021b0040 0x00000017; \
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 12c3cfa64..f9d70c745 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -107,8 +107,10 @@ PHYTEC_ENTRY(start_phytec_phyboard_subra_512mb_1bank, imx6dl_phytec_phyboard_sub
PHYTEC_ENTRY(start_phytec_phyboard_subra_1gib_1bank, imx6q_phytec_phyboard_subra, SZ_1G, false);
PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_256mb, imx6dl_phytec_phycore_som_nand, SZ_256M, true);
+PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_1gib, imx6dl_phytec_phycore_som_nand, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_1gib, imx6dl_phytec_phycore_som_emmc, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib, imx6q_phytec_phycore_som_nand, SZ_1G, true);
+PHYTEC_ENTRY(start_phytec_phycore_imx6qp_som_nand_1gib, imx6qp_phytec_phycore_som_nand, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true);
diff --git a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
index 22ffdf85e..6b9c719c6 100644
--- a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
+++ b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
@@ -284,13 +284,13 @@ static noinline void rdu2_sram_setup(void)
relocate_to_current_adr();
setup_c();
- if (__imx6_cpu_revision() == IMX_CHIP_REV_2_0)
+ if (__imx6_cpu_type() == IMX6_CPUTYPE_IMX6QP)
write_regs(imx6qp_dcd, ARRAY_SIZE(imx6qp_dcd));
else
write_regs(imx6q_dcd, ARRAY_SIZE(imx6q_dcd));
imx6_get_boot_source(&bootsrc, &instance);
- if (bootsrc == BOOTSOURCE_SPI)
+ if (bootsrc == BOOTSOURCE_SPI_NOR)
imx6_spi_start_image(0);
else
imx6_esdhc_start_image(instance);
@@ -304,10 +304,10 @@ ENTRY_FUNCTION(start_imx6_zii_rdu2, r0, r1, r2)
* When still running in SRAM, we need to setup the DRAM now and load
* the remaining image.
*/
- if (get_pc() < MX6_MMDC_PORT0_BASE_ADDR)
+ if (get_pc() < MX6_MMDC_PORT01_BASE_ADDR)
rdu2_sram_setup();
- if (__imx6_cpu_revision() == IMX_CHIP_REV_2_0)
+ if (__imx6_cpu_type() == IMX6_CPUTYPE_IMX6QP)
imx6q_barebox_entry(__dtb_imx6qp_zii_rdu2_start +
get_runtime_offset());
else
diff --git a/arch/arm/boards/zii-vf610-dev/lowlevel.c b/arch/arm/boards/zii-vf610-dev/lowlevel.c
index c6663c141..f3d67501a 100644
--- a/arch/arm/boards/zii-vf610-dev/lowlevel.c
+++ b/arch/arm/boards/zii-vf610-dev/lowlevel.c
@@ -18,6 +18,7 @@
#include <mach/generic.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
+#include <mach/esdctl.h>
#include <mach/vf610-regs.h>
#include <mach/clock-vf610.h>
#include <mach/iomux-vf610.h>
@@ -133,5 +134,5 @@ ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2)
break;
}
- barebox_arm_entry(0x80000000, SZ_512M, fdt + get_runtime_offset());
+ vf610_barebox_entry(fdt + get_runtime_offset());
}
diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
index 426bc0465..8aef9d6ef 100644
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@@ -32,16 +32,21 @@ CONFIG_MACH_UDOO=y
CONFIG_MACH_VARISCITE_MX6=y
CONFIG_MACH_GW_VENTANA=y
CONFIG_MACH_CM_FX6=y
+CONFIG_MACH_ADVANTECH_ROM_742X=y
+CONFIG_MACH_WARP7=y
+CONFIG_MACH_VF610_TWR=y
+CONFIG_MACH_ZII_RDU2=y
+CONFIG_MACH_ZII_VF610_DEV=y
CONFIG_MACH_PHYTEC_PHYCORE_IMX7=y
+CONFIG_MACH_FREESCALE_MX7_SABRESD=y
+CONFIG_MACH_NXP_IMX6ULL_EVK=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
-CONFIG_IMX_OCOTP=y
CONFIG_THUMB2_BAREBOX=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_PSCI=y
CONFIG_MMU=y
-CONFIG_TEXT_BASE=0x0
CONFIG_MALLOC_SIZE=0x0
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
@@ -164,6 +169,7 @@ CONFIG_DRIVER_VIDEO_EDID=y
CONFIG_MCI=y
CONFIG_MCI_MMC_BOOT_PARTITIONS=y
CONFIG_MCI_IMX_ESDHC=y
+CONFIG_MFD_DA9063=y
CONFIG_MFD_MC34704=y
CONFIG_MFD_MC9SDZ60=y
CONFIG_MFD_STMPE=y
diff --git a/arch/arm/configs/omap3530_beagle_defconfig b/arch/arm/configs/omap3530_beagle_defconfig
index b454cf2b4..cf7914855 100644
--- a/arch/arm/configs/omap3530_beagle_defconfig
+++ b/arch/arm/configs/omap3530_beagle_defconfig
@@ -5,7 +5,6 @@ CONFIG_THUMB2_BAREBOX=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
-CONFIG_TEXT_BASE=0x0
CONFIG_MALLOC_SIZE=0x0
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
@@ -26,7 +25,6 @@ CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_RESET_SOURCE=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_OMAP_UART_PORT=3
-CONFIG_DEBUG_INITCALLS=y
CONFIG_CMD_DMESG=y
CONFIG_LONGHELP=y
CONFIG_CMD_IOMEM=y
diff --git a/arch/arm/configs/omap3530_beagle_xload_defconfig b/arch/arm/configs/omap3530_beagle_xload_defconfig
index d36aaf319..2105c0b9d 100644
--- a/arch/arm/configs/omap3530_beagle_xload_defconfig
+++ b/arch/arm/configs/omap3530_beagle_xload_defconfig
@@ -8,7 +8,6 @@ CONFIG_THUMB2_BAREBOX=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
-CONFIG_TEXT_BASE=0x0
CONFIG_STACK_SIZE=0xc00
CONFIG_MALLOC_SIZE=0x0
CONFIG_MALLOC_DUMMY=y
@@ -18,7 +17,6 @@ CONFIG_SHELL_NONE=y
# CONFIG_ERRNO_MESSAGES is not set
# CONFIG_TIMESTAMP is not set
CONFIG_CONSOLE_SIMPLE=y
-CONFIG_OFDEVICE=y
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
# CONFIG_SPI is not set
@@ -36,7 +34,6 @@ CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
# CONFIG_MCI_WRITE is not set
CONFIG_MCI_OMAP_HSMMC=y
-# CONFIG_PINCTRL is not set
# CONFIG_FS_RAMFS is not set
# CONFIG_FS_DEVFS is not set
CONFIG_FS_FAT=y
diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
index 00ce3efb2..51fe7ed98 100644
--- a/arch/arm/cpu/common.c
+++ b/arch/arm/cpu/common.c
@@ -85,6 +85,7 @@ void relocate_to_current_adr(void)
unsigned long *fixup = (unsigned long *)(rel->r_offset + offset);
*fixup = *fixup + r + offset;
+ rel->r_offset += offset;
} else {
putc_ll('>');
puthex_ll(rel->r_info);
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index 68fff892e..64bd942ad 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -144,13 +144,11 @@ __noreturn void barebox_non_pbl_start(unsigned long membase,
unsigned long endmem = membase + memsize;
unsigned long malloc_start, malloc_end;
unsigned long barebox_size = barebox_image_size + MAX_BSS_SIZE;
-
- if (IS_ENABLED(CONFIG_RELOCATABLE)) {
- unsigned long barebox_base = arm_mem_barebox_image(membase,
- endmem,
- barebox_size);
+ unsigned long barebox_base = arm_mem_barebox_image(membase,
+ endmem,
+ barebox_size);
+ if (IS_ENABLED(CONFIG_RELOCATABLE))
relocate_to_adr(barebox_base);
- }
setup_c();
@@ -160,8 +158,7 @@ __noreturn void barebox_non_pbl_start(unsigned long membase,
arm_stack_top = arm_mem_stack_top(membase, endmem);
arm_barebox_size = barebox_size;
- malloc_end = arm_mem_barebox_image(membase, endmem,
- arm_barebox_size);
+ malloc_end = barebox_base;
if (IS_ENABLED(CONFIG_MMU_EARLY)) {
unsigned long ttb = arm_mem_ttb(membase, endmem);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e60e0ea0c..b69592e64 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -7,6 +7,7 @@ endif
# created.
obj- += dummy.o
+pbl-dtb-$(CONFIG_MACH_ADVANTECH_ROM_742X) += imx6dl-advantech-rom-7421.dtb.o
pbl-dtb-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o
pbl-dtb-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o
pbl-dtb-$(CONFIG_MACH_CM_FX6) += imx6dl-cm-fx6.dtb.o imx6q-cm-fx6.dtb.o imx6q-utilite.dtb.o
@@ -57,6 +58,7 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
imx6dl-phytec-phyboard-subra.dtb.o \
imx6q-phytec-phycore-som-nand.dtb.o \
imx6q-phytec-phycore-som-emmc.dtb.o \
+ imx6qp-phytec-phycore-som-nand.dtb.o \
imx6dl-phytec-phycore-som-nand.dtb.o \
imx6dl-phytec-phycore-som-emmc.dtb.o \
imx6ul-phytec-phycore-som.dtb.o \
diff --git a/arch/arm/dts/imx6dl-advantech-rom-7421.dts b/arch/arm/dts/imx6dl-advantech-rom-7421.dts
new file mode 100755
index 000000000..1d5fd8926
--- /dev/null
+++ b/arch/arm/dts/imx6dl-advantech-rom-7421.dts
@@ -0,0 +1,225 @@
+/*
+ * Copyright(c) 2018 Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <arm/imx6dl.dtsi>
+#include "imx6dl.dtsi"
+
+/ {
+ model = "Advantech i.MX6 ROM-7421";
+ compatible = "advantech,imx6dl-rom-7421", "fsl,imx6dl";
+
+ chosen {
+ stdout-path = &uart1;
+
+ environment-sd2 { /* Micro SD */
+ compatible = "barebox,environment";
+ device-path = &usdhc2, "partname:barebox-environment";
+ status = "disabled";
+ };
+
+ environment-sd4 { /* eMMC */
+ compatible = "barebox,environment";
+ device-path = &usdhc4, "partname:barebox-environment";
+ status = "disabled";
+ };
+
+ environment-spi { /* spi nor */
+ compatible = "barebox,environment";
+ device-path = &ecspi1, "partname:barebox-environment";
+ status = "disabled";
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio3 19 0>;
+ status = "okay";
+
+ flash: m25p80@0 {
+ compatible = "m25p80";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe0000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ fsl,magic-packet;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usdhc2 { /* Micro SD */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <8>;
+ cd-gpios = <&gpio2 0 0>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe0000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+};
+
+&usdhc3 { /* SD Card */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <4>;
+ cd-gpios = <&gpio2 1 0>;
+ en-gpios = <&gpio2 2 0>;
+ wp-gpios = <&gpio2 3 0>;
+ status = "okay";
+};
+
+&usdhc4 { /* eMMC */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ non-removable;
+ no-1-8-v;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe0000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0A0B1
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
index bffee5f15..7e4a5aba2 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
@@ -41,6 +41,14 @@
status = "okay";
};
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
&usdhc1 {
status = "okay";
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
index 1b66fdabc..ffcbdc213 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
@@ -36,6 +36,14 @@
status = "okay";
};
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
&usdhc1 {
status = "okay";
diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
index a6ea7b5cc..63dd966b8 100644
--- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
+++ b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
@@ -145,18 +145,8 @@
};
partition@420000 {
- label = "oftree";
- reg = <0x420000 0x20000>;
- };
-
- partition@440000 {
- label = "kernel";
- reg = <0x440000 0x800000>;
- };
-
- partition@C40000 {
label = "root";
- reg = <0xC40000 0x0>;
+ reg = <0x420000 0x0>;
};
};
diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
index ecc5aa38e..6e12b26d3 100644
--- a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
@@ -40,6 +40,14 @@
status = "okay";
};
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
&usdhc1 {
status = "okay";
diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
index 9ad7eda74..d9e37b7fc 100644
--- a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
@@ -45,6 +45,14 @@
status = "okay";
};
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
&usdhc1 {
status = "okay";
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
index 7cc8be195..8bb9ec8db 100644
--- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
@@ -115,18 +115,8 @@
};
partition@500000 {
- label = "oftree";
- reg = <0x500000 0x100000>;
- };
-
- partition@600000 {
- label = "kernel";
- reg = <0x600000 0x800000>;
- };
-
- partition@e00000 {
label = "root";
- reg = <0xe00000 0x0>;
+ reg = <0x500000 0x0>;
};
};
diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
index c492b2ea4..ec1441539 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -32,6 +32,34 @@
device-path = &gpmi, "partname:barebox-environment";
status = "disabled";
};
+
+ environment-spinor {
+ compatible = "barebox,environment";
+ device-path = &flash, "partname:barebox-environment";
+ status = "disabled";
+ };
+ };
+
+ reg_usbh1_vbus: regulator-usbh1 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1_vbus>;
+ regulator-name = "usbh1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usbotg_vbus: regulator-usbotg {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg_vbus>;
+ regulator-name = "usbotg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
};
@@ -42,8 +70,8 @@
cs-gpios = <&gpio3 19 0>;
status = "disabled";
- flash: m25p80@0 {
- compatible = "m25p80";
+ flash: flash@0 {
+ compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
status = "disabled";
@@ -112,18 +140,8 @@
};
partition@500000 {
- label = "oftree";
- reg = <0x500000 0x100000>;
- };
-
- partition@600000 {
- label = "kernel";
- reg = <0x600000 0x800000>;
- };
-
- partition@e00000 {
label = "root";
- reg = <0xe00000 0x0>;
+ reg = <0x500000 0x0>;
};
};
@@ -151,104 +169,118 @@
};
&iomuxc {
- pinctrl-names = "default";
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
+ >;
+ };
- imx6qdl-phytec-phycore-som {
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
- >;
- };
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x80000000
+ >;
+ };
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x80000000
- >;
- };
+ pinctrl_gpmi_nand: gpmigrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+ >;
+ };
- pinctrl_gpmi_nand: gpmigrp {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
- MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
- MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
- >;
- };
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ >;
+ };
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
- >;
- };
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ >;
+ };
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
- >;
- };
+ pinctrl_usbh1_vbus: usbh1vbusgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0xb0b1
+ >;
+ };
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000 /* CD */
- >;
- };
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
+ };
- pinctrl_usdhc4: usdhc4grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ pinctrl_usbotg_vbus: usbotgvbusgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0xb0b1
>;
- };
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
+ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000 /* CD */
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
};
};
@@ -262,6 +294,20 @@
status = "okay";
};
+&usbh1 {
+ vbus-supply = <&reg_usbh1_vbus>;
+ disable-over-current;
+ status = "disabled";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ vbus-supply = <&reg_usbotg_vbus>;
+ disable-over-current;
+ status = "disabled";
+};
+
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
diff --git a/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts
new file mode 100644
index 000000000..c2756142b
--- /dev/null
+++ b/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2016 Phytec Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include <arm/imx6qp.dtsi>
+#include "imx6qdl-phytec-phycore-som.dtsi"
+
+/ {
+ model = "Phytec phyCORE-i.MX6 Quad with NAND";
+ compatible = "phytec,imx6qp-pcm058-nand", "fsl,imx6qp";
+};
+
+&ecspi1 {
+ status = "okay";
+};
+
+&eeprom {
+ status = "okay";
+};
+
+&ethphy {
+ max-speed = <1000>;
+};
+
+&fec {
+ status = "okay";
+};
+
+&flash {
+ status = "okay";
+};
+
+&gpmi {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe0000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+};
diff --git a/arch/arm/dts/vf610-ddrmc.dtsi b/arch/arm/dts/vf610-ddrmc.dtsi
new file mode 100644
index 000000000..772131ec2
--- /dev/null
+++ b/arch/arm/dts/vf610-ddrmc.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Include file to switch board DTS form using hardcoded memory node
+ * to dynamic memory size detection based on DDR controller settings
+ */
+
+/ {
+ /delete-node/ memory;
+};
+
+&aips1 {
+ ddrmc@400ae000 {
+ compatible = "fsl,vf610-ddrmc";
+ reg = <0x400ae000 0x1000>;
+ };
+};
diff --git a/arch/arm/dts/vf610-twr.dts b/arch/arm/dts/vf610-twr.dts
index 5947fdbda..2456ade5f 100644
--- a/arch/arm/dts/vf610-twr.dts
+++ b/arch/arm/dts/vf610-twr.dts
@@ -8,6 +8,7 @@
*/
#include <arm/vf610-twr.dts>
+#include "vf610-ddrmc.dtsi"
&usbdev0 {
status = "disabled";
diff --git a/arch/arm/dts/vf610-zii-dev.dtsi b/arch/arm/dts/vf610-zii-dev.dtsi
index 4bf81451a..dc16280bc 100644
--- a/arch/arm/dts/vf610-zii-dev.dtsi
+++ b/arch/arm/dts/vf610-zii-dev.dtsi
@@ -40,7 +40,9 @@ n * copy, modify, merge, publish, distribute, sublicense, and/or
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
- */
+*/
+
+#include "vf610-ddrmc.dtsi"
/ {
audio_ext: mclk_osc {
diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index fa673a63a..480323711 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -114,8 +114,7 @@ static inline unsigned long arm_mem_ttb(unsigned long membase,
unsigned long endmem)
{
endmem = arm_mem_stack(membase, endmem);
- endmem &= ~(SZ_16K - 1);
- endmem -= SZ_16K;
+ endmem = ALIGN_DOWN(endmem, SZ_16K) - SZ_16K;
return endmem;
}
@@ -138,7 +137,7 @@ static inline unsigned long arm_mem_ramoops(unsigned long membase,
endmem = arm_mem_ttb(membase, endmem);
#ifdef CONFIG_FS_PSTORE_RAMOOPS
endmem -= CONFIG_FS_PSTORE_RAMOOPS_SIZE;
- endmem &= ~(SZ_4K - 1); /* Align to 4K */
+ endmem = ALIGN_DOWN(endmem, SZ_4K);
#endif
return endmem;
@@ -151,9 +150,7 @@ static inline unsigned long arm_mem_barebox_image(unsigned long membase,
endmem = arm_mem_ramoops(membase, endmem);
if (IS_ENABLED(CONFIG_RELOCATABLE)) {
- endmem -= size;
- endmem &= ~(SZ_1M - 1);
- return endmem;
+ return ALIGN_DOWN(endmem - size, SZ_1M);
} else {
if (TEXT_BASE >= membase && TEXT_BASE < endmem)
return TEXT_BASE;
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 9052a94ea..e6956acbd 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -393,6 +393,11 @@ config MACH_CM_FX6
bool "CM FX6"
select ARCH_IMX6
+config MACH_ADVANTECH_ROM_742X
+ bool "Advantech ROM 742X"
+ select ARCH_IMX6
+ select ARM_USE_COMPRESSED_DTB
+
config MACH_WARP7
bool "NXP i.MX7: element 14 WaRP7 Board"
select ARCH_IMX7
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 8ec846cce..160ed4b08 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_IMX6) += imx6.o usb-imx6.o
CFLAGS_imx6.o := -march=armv7-a
lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o
obj-$(CONFIG_ARCH_IMX7) += imx7.o
+obj-$(CONFIG_ARCH_VF610) += vf610.o
obj-$(CONFIG_ARCH_IMX_XLOAD) += xload.o
obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_IMX_OCOTP) += ocotp.o
diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index 72597f5e2..22cf08e6a 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -15,6 +15,7 @@
#include <bootsource.h>
#include <environment.h>
#include <init.h>
+#include <linux/bitfield.h>
#include <magicvar.h>
#include <io.h>
@@ -26,6 +27,21 @@
#include <mach/imx53-regs.h>
#include <mach/imx6-regs.h>
#include <mach/imx7-regs.h>
+#include <mach/vf610-regs.h>
+
+
+static void
+imx_boot_save_loc(void (*get_boot_source)(enum bootsource *, int *))
+{
+ enum bootsource src = BOOTSOURCE_UNKNOWN;
+ int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
+
+ get_boot_source(&src, &instance);
+
+ bootsource_set(src);
+ bootsource_set_instance(instance);
+}
+
/* [CTRL][TYPE] */
static const enum bootsource locations[4][4] = {
@@ -91,13 +107,7 @@ void imx25_get_boot_source(enum bootsource *src, int *instance)
void imx25_boot_save_loc(void)
{
- enum bootsource src = BOOTSOURCE_UNKNOWN;
- int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
-
- imx25_get_boot_source(&src, &instance);
-
- bootsource_set(src);
- bootsource_set_instance(instance);
+ imx_boot_save_loc(imx25_get_boot_source);
}
void imx35_get_boot_source(enum bootsource *src, int *instance)
@@ -112,13 +122,7 @@ void imx35_get_boot_source(enum bootsource *src, int *instance)
void imx35_boot_save_loc(void)
{
- enum bootsource src = BOOTSOURCE_UNKNOWN;
- int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
-
- imx35_get_boot_source(&src, &instance);
-
- bootsource_set(src);
- bootsource_set_instance(instance);
+ imx_boot_save_loc(imx35_get_boot_source);
}
#define IMX27_SYSCTRL_GPCR 0x18
@@ -159,13 +163,7 @@ void imx27_get_boot_source(enum bootsource *src, int *instance)
void imx27_boot_save_loc(void)
{
- enum bootsource src = BOOTSOURCE_UNKNOWN;
- int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
-
- imx27_get_boot_source(&src, &instance);
-
- bootsource_set(src);
- bootsource_set_instance(instance);
+ imx_boot_save_loc(imx27_get_boot_source);
}
#define IMX51_SRC_SBMR 0x4
@@ -203,36 +201,82 @@ void imx51_get_boot_source(enum bootsource *src, int *instance)
void imx51_boot_save_loc(void)
{
- enum bootsource src = BOOTSOURCE_UNKNOWN;
- int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
+ imx_boot_save_loc(imx51_get_boot_source);
+}
- imx51_get_boot_source(&src, &instance);
+#define IMX53_SRC_SBMR 0x4
+#define SRC_SBMR_BMOD GENMASK(25, 24)
+#define IMX53_BMOD_SERIAL 0b11
+
+#define __BOOT_CFG(n, m, l) GENMASK((m) + ((n) - 1) * 8, \
+ (l) + ((n) - 1) * 8)
+#define BOOT_CFG1(m, l) __BOOT_CFG(1, m, l)
+#define BOOT_CFG2(m, l) __BOOT_CFG(2, m, l)
+#define BOOT_CFG3(m, l) __BOOT_CFG(3, m, l)
+#define BOOT_CFG4(m, l) __BOOT_CFG(4, m, l)
+
+#define ___BOOT_CFG(n, i) __BOOT_CFG(n, i, i)
+#define __MAKE_BOOT_CFG_BITS(idx) \
+ enum { \
+ BOOT_CFG##idx##_0 = ___BOOT_CFG(idx, 0), \
+ BOOT_CFG##idx##_1 = ___BOOT_CFG(idx, 1), \
+ BOOT_CFG##idx##_2 = ___BOOT_CFG(idx, 2), \
+ BOOT_CFG##idx##_3 = ___BOOT_CFG(idx, 3), \
+ BOOT_CFG##idx##_4 = ___BOOT_CFG(idx, 4), \
+ BOOT_CFG##idx##_5 = ___BOOT_CFG(idx, 5), \
+ BOOT_CFG##idx##_6 = ___BOOT_CFG(idx, 6), \
+ BOOT_CFG##idx##_7 = ___BOOT_CFG(idx, 7), \
+ };
- bootsource_set(src);
- bootsource_set_instance(instance);
+__MAKE_BOOT_CFG_BITS(1)
+__MAKE_BOOT_CFG_BITS(2)
+__MAKE_BOOT_CFG_BITS(4)
+#undef __MAKE_BOOT_CFG
+#undef ___BOOT_CFG
+
+
+static unsigned int imx53_get_bmod(uint32_t r)
+{
+ return FIELD_GET(SRC_SBMR_BMOD, r);
+}
+
+static int imx53_bootsource_internal(uint32_t r)
+{
+ return FIELD_GET(BOOT_CFG1(7, 4), r);
+}
+
+static int imx53_port_select(uint32_t r)
+{
+ return FIELD_GET(BOOT_CFG3(5, 4), r);
+}
+
+static bool imx53_bootsource_nand(uint32_t r)
+{
+ return FIELD_GET(BOOT_CFG1_7, r);
+}
+
+static enum bootsource imx53_bootsource_serial_rom(uint32_t r)
+{
+ return BOOT_CFG1(r, 3) ? BOOTSOURCE_SPI : BOOTSOURCE_I2C;
}
-#define IMX53_SRC_SBMR 0x4
void imx53_get_boot_source(enum bootsource *src, int *instance)
{
void __iomem *src_base = IOMEM(MX53_SRC_BASE_ADDR);
uint32_t cfg1 = readl(src_base + IMX53_SRC_SBMR);
- if (((cfg1 >> 24) & 0x3) == 0x3) {
+ if (imx53_get_bmod(cfg1) == IMX53_BMOD_SERIAL) {
*src = BOOTSOURCE_USB;
*instance = 0;
return;
}
- switch ((cfg1 & 0xff) >> 4) {
+ switch (imx53_bootsource_internal(cfg1)) {
case 2:
*src = BOOTSOURCE_HD;
break;
case 3:
- if (cfg1 & (1 << 3))
- *src = BOOTSOURCE_SPI;
- else
- *src = BOOTSOURCE_I2C;
+ *src = imx53_bootsource_serial_rom(cfg1);
break;
case 4:
case 5:
@@ -241,18 +285,16 @@ void imx53_get_boot_source(enum bootsource *src, int *instance)
*src = BOOTSOURCE_MMC;
break;
default:
+ if (imx53_bootsource_nand(cfg1))
+ *src = BOOTSOURCE_NAND;
break;
}
- if (cfg1 & (1 << 7))
- *src = BOOTSOURCE_NAND;
-
-
switch (*src) {
case BOOTSOURCE_MMC:
case BOOTSOURCE_SPI:
case BOOTSOURCE_I2C:
- *instance = (cfg1 >> 20) & 0x3;
+ *instance = imx53_port_select(cfg1);
break;
default:
*instance = 0;
@@ -273,123 +315,206 @@ void imx53_boot_save_loc(void)
#define IMX6_SRC_SBMR1 0x04
#define IMX6_SRC_SBMR2 0x1c
+#define IMX6_BMOD_SERIAL 0b01
+#define IMX6_BMOD_RESERVED 0b11
+#define IMX6_BMOD_FUSES 0b00
+#define BT_FUSE_SEL BIT(4)
+
+static bool imx6_bootsource_reserved(uint32_t sbmr2)
+{
+ return imx53_get_bmod(sbmr2) == IMX6_BMOD_RESERVED;
+}
+
+static bool imx6_bootsource_serial(uint32_t sbmr2)
+{
+ return imx53_get_bmod(sbmr2) == IMX6_BMOD_SERIAL ||
+ /*
+ * If boot from fuses is selected and fuses are not
+ * programmed by setting BT_FUSE_SEL, ROM code will
+ * fallback to serial mode
+ */
+ (imx53_get_bmod(sbmr2) == IMX6_BMOD_FUSES &&
+ !(sbmr2 & BT_FUSE_SEL));
+}
+
+static int __imx6_bootsource_serial_rom(uint32_t r)
+{
+ return FIELD_GET(BOOT_CFG4(2, 0), r);
+}
+
+/*
+ * Serial ROM bootsource on i.MX6 are as follows:
+ *
+ * 000 - ECSPI-1
+ * 001 - ECSPI-2
+ * 010 - ECSPI-3
+ * 011 - ECSPI-4
+ * 100 - ECSPI-5
+ * 101 - I2C1
+ * 110 - I2C2
+ * 111 - I2C3
+ *
+ * There's no single bit that would tell us we are booting from I2C or
+ * SPI, so we just have to compare the "source" agains the value for
+ * I2C1 for both: calculating bootsource and boot instance.
+ */
+#define IMX6_BOOTSOURCE_SERIAL_ROM_I2C1 0b101
+
+static enum bootsource imx6_bootsource_serial_rom(uint32_t sbmr)
+{
+ const int source = __imx6_bootsource_serial_rom(sbmr);
+
+ return source < IMX6_BOOTSOURCE_SERIAL_ROM_I2C1 ?
+ BOOTSOURCE_SPI_NOR : BOOTSOURCE_I2C;
+}
+
+static int imx6_boot_instance_serial_rom(uint32_t sbmr)
+{
+ const int source = __imx6_bootsource_serial_rom(sbmr);
+
+ if (source < IMX6_BOOTSOURCE_SERIAL_ROM_I2C1)
+ return source;
+
+ return source - IMX6_BOOTSOURCE_SERIAL_ROM_I2C1;
+}
+
+static int imx6_boot_instance_mmc(uint32_t r)
+{
+ return FIELD_GET(BOOT_CFG2(4, 3), r);
+}
void imx6_get_boot_source(enum bootsource *src, int *instance)
{
void __iomem *src_base = IOMEM(MX6_SRC_BASE_ADDR);
uint32_t sbmr1 = readl(src_base + IMX6_SRC_SBMR1);
uint32_t sbmr2 = readl(src_base + IMX6_SRC_SBMR2);
- uint32_t boot_cfg_4_2_0;
- int boot_mode;
- /* BMOD[1:0] */
- boot_mode = (sbmr2 >> 24) & 0x3;
+ if (imx6_bootsource_reserved(sbmr2))
+ return;
- switch (boot_mode) {
- case 0: /* Fuses, fall through */
- case 2: /* internal boot */
- goto internal_boot;
- case 1: /* Serial Downloader */
+ if (imx6_bootsource_serial(sbmr2)) {
*src = BOOTSOURCE_SERIAL;
- break;
- case 3: /* reserved */
- break;
- };
-
- return;
-
-internal_boot:
+ return;
+ }
- /* BOOT_CFG1[7:4] */
- switch ((sbmr1 >> 4) & 0xf) {
+ switch (imx53_bootsource_internal(sbmr1)) {
case 2:
*src = BOOTSOURCE_HD;
break;
case 3:
- /* BOOT_CFG4[2:0] */
- boot_cfg_4_2_0 = (sbmr1 >> 24) & 0x7;
-
- if (boot_cfg_4_2_0 > 4) {
- *src = BOOTSOURCE_I2C;
- *instance = boot_cfg_4_2_0 - 5;
- } else {
- *src = BOOTSOURCE_SPI;
- *instance = boot_cfg_4_2_0;
- }
+ *src = imx6_bootsource_serial_rom(sbmr1);
+ *instance = imx6_boot_instance_serial_rom(sbmr1);
break;
case 4:
case 5:
case 6:
case 7:
*src = BOOTSOURCE_MMC;
-
- /* BOOT_CFG2[4:3] */
- *instance = (sbmr1 >> 11) & 0x3;
+ *instance = imx6_boot_instance_mmc(sbmr1);
break;
default:
+ if (imx53_bootsource_nand(sbmr1))
+ *src = BOOTSOURCE_NAND;
break;
}
-
- /* BOOT_CFG1[7:0] */
- if (sbmr1 & (1 << 7))
- *src = BOOTSOURCE_NAND;
-
- return;
}
void imx6_boot_save_loc(void)
{
- enum bootsource src = BOOTSOURCE_UNKNOWN;
- int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
-
- imx6_get_boot_source(&src, &instance);
-
- bootsource_set(src);
- bootsource_set_instance(instance);
+ imx_boot_save_loc(imx6_get_boot_source);
}
#define IMX7_SRC_SBMR1 0x58
#define IMX7_SRC_SBMR2 0x70
+/*
+ * Re-defined to match the naming in reference manual
+ */
+#define BOOT_CFG(m, l) BOOT_CFG1(m, l)
+
+#define IMX_BOOT_SW_INFO_POINTER_ADDR 0x000001E8
+#define IMX_BOOT_SW_INFO_BDT_SD 0x1
+
+static unsigned int imx7_bootsource_internal(uint32_t r)
+{
+ return FIELD_GET(BOOT_CFG(15, 12), r);
+}
+
+static int imx7_boot_instance_spi_nor(uint32_t r)
+{
+ return FIELD_GET(BOOT_CFG(11, 9), r);
+}
+
+static int imx7_boot_instance_mmc(uint32_t r)
+{
+ return FIELD_GET(BOOT_CFG(11, 10), r);
+}
+
+struct imx_boot_sw_info {
+ uint8_t reserved_1;
+ uint8_t boot_device_instance;
+ uint8_t boot_device_type;
+ uint8_t reserved_2;
+ uint32_t frequency_hz[4]; /* Various frequencies (ARM, AXI,
+ * DDR, etc.). Not used */
+ uint32_t reserved_3[3];
+} __packed;
+
void imx7_get_boot_source(enum bootsource *src, int *instance)
{
void __iomem *src_base = IOMEM(MX7_SRC_BASE_ADDR);
uint32_t sbmr1 = readl(src_base + IMX7_SRC_SBMR1);
uint32_t sbmr2 = readl(src_base + IMX7_SRC_SBMR2);
- int boot_mode;
- /* BMOD[1:0] */
- boot_mode = (sbmr2 >> 24) & 0x3;
-
- switch (boot_mode) {
- case 0: /* Fuses, fall through */
- case 2: /* internal boot */
- goto internal_boot;
- case 1: /* Serial Downloader */
- *src = BOOTSOURCE_SERIAL;
- break;
- case 3: /* reserved */
- break;
- };
+ if (imx6_bootsource_reserved(sbmr2))
+ return;
- return;
+ if (imx6_bootsource_serial(sbmr2)) {
+ /*
+ * On i.MX7 ROM code will try to bood from uSDHC1
+ * before entering serial mode. It doesn't seem to be
+ * reflected in the contents of SBMR1 in any way when
+ * that happens, so we check "Boot_SW_Info" structure
+ * (per 6.6.14 Boot information for software) to see
+ * if that really happened.
+ *
+ * FIXME: This behaviour can be inhibited by
+ * DISABLE_SDMMC_MFG, but location of that fuse
+ * doesn't seem to be documented anywhere. Once that
+ * is known it should be taken into account here.
+ */
+ const struct imx_boot_sw_info *info;
+
+ info = (const void *)readl(IMX_BOOT_SW_INFO_POINTER_ADDR);
+
+ if (info->boot_device_type == IMX_BOOT_SW_INFO_BDT_SD) {
+ *src = BOOTSOURCE_MMC;
+ /*
+ * We are expecting to only ever boot from
+ * uSDHC1 here
+ */
+ WARN_ON(*instance = info->boot_device_instance);
+ return;
+ }
-internal_boot:
+ *src = BOOTSOURCE_SERIAL;
+ return;
+ }
- switch ((sbmr1 >> 12) & 0xf) {
+ switch (imx7_bootsource_internal(sbmr1)) {
case 1:
case 2:
*src = BOOTSOURCE_MMC;
- *instance = (sbmr1 >> 10 & 0x3);
+ *instance = imx7_boot_instance_mmc(sbmr1);
break;
case 3:
*src = BOOTSOURCE_NAND;
break;
- case 4:
+ case 6:
*src = BOOTSOURCE_SPI_NOR,
- *instance = (sbmr1 >> 9 & 0x7);
+ *instance = imx7_boot_instance_spi_nor(sbmr1);
break;
- case 6:
+ case 4:
*src = BOOTSOURCE_SPI; /* Really: qspi */
break;
case 5:
@@ -398,21 +523,103 @@ internal_boot:
default:
break;
}
+}
- /* BOOT_CFG1[7:0] */
- if (sbmr1 & (1 << 7))
- *src = BOOTSOURCE_NAND;
+void imx7_boot_save_loc(void)
+{
+ imx_boot_save_loc(imx7_get_boot_source);
+}
- return;
+static int vf610_boot_instance_spi(uint32_t r)
+{
+ return FIELD_GET(BOOT_CFG1_1, r);
}
-void imx7_boot_save_loc(void)
+static int vf610_boot_instance_nor(uint32_t r)
{
- enum bootsource src = BOOTSOURCE_UNKNOWN;
- int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
+ return FIELD_GET(BOOT_CFG1_3, r);
+}
+
+/*
+ * Vybrid's Serial ROM boot sources (BOOT_CFG4[2:0]) are as follows:
+ *
+ * 000 - SPI0
+ * 001 - SPI1
+ * 010 - SPI2
+ * 011 - SPI3
+ * 100 - I2C0
+ * 101 - I2C1
+ * 110 - I2C2
+ * 111 - I2C3
+ *
+ * Which we can neatly divide in two halves and use MSb to detect if
+ * bootsource is I2C or SPI EEPROM and 2 LSbs directly as boot
+ * insance.
+ */
+static enum bootsource vf610_bootsource_serial_rom(uint32_t r)
+{
+ return FIELD_GET(BOOT_CFG4_2, r) ? BOOTSOURCE_I2C : BOOTSOURCE_SPI_NOR;
+}
- imx7_get_boot_source(&src, &instance);
+static int vf610_boot_instance_serial_rom(uint32_t r)
+{
+ return __imx6_bootsource_serial_rom(r) & 0b11;
+}
- bootsource_set(src);
- bootsource_set_instance(instance);
+static int vf610_boot_instance_can(uint32_t r)
+{
+ return FIELD_GET(BOOT_CFG1_0, r);
+}
+
+static int vf610_boot_instance_mmc(uint32_t r)
+{
+ return FIELD_GET(BOOT_CFG2_3, r);
+}
+
+void vf610_get_boot_source(enum bootsource *src, int *instance)
+{
+ void __iomem *src_base = IOMEM(VF610_SRC_BASE_ADDR);
+ uint32_t sbmr1 = readl(src_base + IMX6_SRC_SBMR1);
+ uint32_t sbmr2 = readl(src_base + IMX6_SRC_SBMR2);
+
+ if (imx6_bootsource_reserved(sbmr2))
+ return;
+
+ if (imx6_bootsource_serial(sbmr2)) {
+ *src = BOOTSOURCE_SERIAL;
+ return;
+ }
+
+ switch (imx53_bootsource_internal(sbmr1)) {
+ case 0:
+ *src = BOOTSOURCE_SPI; /* Really: qspi */
+ *instance = vf610_boot_instance_spi(sbmr1);
+ break;
+ case 1:
+ *src = BOOTSOURCE_NOR;
+ *instance = vf610_boot_instance_nor(sbmr1);
+ break;
+ case 2:
+ *src = vf610_bootsource_serial_rom(sbmr1);
+ *instance = vf610_boot_instance_serial_rom(sbmr1);
+ break;
+ case 3:
+ *src = BOOTSOURCE_CAN;
+ *instance = vf610_boot_instance_can(sbmr1);
+ break;
+ case 6:
+ case 7:
+ *src = BOOTSOURCE_MMC;
+ *instance = vf610_boot_instance_mmc(sbmr1);
+ break;
+ default:
+ if (imx53_bootsource_nand(sbmr1))
+ *src = BOOTSOURCE_NAND;
+ break;
+ }
+}
+
+void vf610_boot_save_loc(void)
+{
+ imx_boot_save_loc(vf610_get_boot_source);
}
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 1eebc77b6..c1680d5ff 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -37,6 +37,7 @@
#include <mach/imx51-regs.h>
#include <mach/imx53-regs.h>
#include <mach/imx6-regs.h>
+#include <mach/vf610-ddrmc.h>
struct imx_esdctl_data {
unsigned long base0;
@@ -75,12 +76,9 @@ static inline unsigned long imx_v1_sdram_size(void __iomem *esdctlbase, int num)
if (ctlval & (1 << 17))
width = 4;
- size = (1 << cols) * (1 << rows) * banks * width;
+ size = memory_sdram_size(cols, rows, banks, width);
- if (size > SZ_64M)
- size = SZ_64M;
-
- return size;
+ return min_t(unsigned long, size, SZ_64M);
}
/*
@@ -103,12 +101,9 @@ static inline unsigned long imx_v2_sdram_size(void __iomem *esdctlbase, int num)
if ((ctlval & ESDCTL0_DSIZ_MASK) == ESDCTL0_DSIZ_31_0)
width = 4;
- size = (1 << cols) * (1 << rows) * banks * width;
-
- if (size > SZ_256M)
- size = SZ_256M;
+ size = memory_sdram_size(cols, rows, banks, width);
- return size;
+ return min_t(unsigned long, size, SZ_256M);
}
/*
@@ -120,13 +115,10 @@ static inline unsigned long imx_v3_sdram_size(void __iomem *esdctlbase, int num)
size = imx_v2_sdram_size(esdctlbase, num);
- if (readl(esdctlbase + IMX_ESDMISC) & (1 << 6))
+ if (readl(esdctlbase + IMX_ESDMISC) & ESDMISC_DDR2_8_BANK)
size *= 2;
- if (size > SZ_256M)
- size = SZ_256M;
-
- return size;
+ return min_t(unsigned long, size, SZ_256M);
}
/*
@@ -136,7 +128,6 @@ static inline unsigned long imx_v4_sdram_size(void __iomem *esdctlbase, int cs)
{
u32 ctlval = readl(esdctlbase + ESDCTL_V4_ESDCTL0);
u32 esdmisc = readl(esdctlbase + ESDCTL_V4_ESDMISC);
- unsigned long size;
int rows, cols, width = 2, banks = 8;
if (cs == 0 && !(ctlval & ESDCTL_V4_ESDCTLx_SDE0))
@@ -162,20 +153,17 @@ static inline unsigned long imx_v4_sdram_size(void __iomem *esdctlbase, int cs)
if (esdmisc & ESDCTL_V4_ESDMISC_BANKS_4)
banks = 4;
- size = (1 << cols) * (1 << rows) * banks * width;
-
- return size;
+ return memory_sdram_size(cols, rows, banks, width);
}
/*
* MMDC - found on i.MX6
*/
-static inline u64 imx6_mmdc_sdram_size(void __iomem *mmdcbase, int cs)
+static inline u64 __imx6_mmdc_sdram_size(void __iomem *mmdcbase, int cs)
{
u32 ctlval = readl(mmdcbase + MDCTL);
u32 mdmisc = readl(mmdcbase + MDMISC);
- u64 size;
int rows, cols, width = 2, banks = 8;
if (cs == 0 && !(ctlval & MMDCx_MDCTL_SDE0))
@@ -201,9 +189,7 @@ static inline u64 imx6_mmdc_sdram_size(void __iomem *mmdcbase, int cs)
if (mdmisc & MMDCx_MDMISC_DDR_4_BANKS)
banks = 4;
- size = (u64)(1 << cols) * (1 << rows) * banks * width;
-
- return size;
+ return memory_sdram_size(cols, rows, banks, width);
}
static void add_mem(unsigned long base0, unsigned long size0,
@@ -286,7 +272,7 @@ static void imx_esdctl_v4_add_mem(void *esdctlbase, struct imx_esdctl_data *data
*/
#define IMX6_MAX_SDRAM_SIZE 0xF0000000
-static void imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+static inline resource_size_t imx6_mmdc_sdram_size(void __iomem *mmdcbase)
{
/*
* It is possible to have a configuration in which both chip
@@ -296,14 +282,41 @@ static void imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
* IMX6_MAX_SDRAM_SIZE bytes of memory available.
*/
- u64 size_cs0 = imx6_mmdc_sdram_size(mmdcbase, 0);
- u64 size_cs1 = imx6_mmdc_sdram_size(mmdcbase, 1);
+ u64 size_cs0 = __imx6_mmdc_sdram_size(mmdcbase, 0);
+ u64 size_cs1 = __imx6_mmdc_sdram_size(mmdcbase, 1);
u64 total = size_cs0 + size_cs1;
resource_size_t size = min(total, (u64)IMX6_MAX_SDRAM_SIZE);
+ return size;
+}
+
+static void imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+{
+ arm_add_mem_device("ram0", data->base0,
+ imx6_mmdc_sdram_size(mmdcbase));
+}
+
+static inline resource_size_t vf610_ddrmc_sdram_size(void __iomem *ddrmc)
+{
+ const u32 cr01 = readl(ddrmc + DDRMC_CR(1));
+ const u32 cr73 = readl(ddrmc + DDRMC_CR(73));
+ const u32 cr78 = readl(ddrmc + DDRMC_CR(78));
+
+ unsigned int rows, cols, width, banks;
+
+ rows = DDRMC_CR01_MAX_ROW_REG(cr01) - DDRMC_CR73_ROW_DIFF(cr73);
+ cols = DDRMC_CR01_MAX_COL_REG(cr01) - DDRMC_CR73_COL_DIFF(cr73);
+ banks = 1 << (3 - DDRMC_CR73_BANK_DIFF(cr73));
+ width = (cr78 & DDRMC_CR78_REDUC) ? sizeof(u8) : sizeof(u16);
+
+ return memory_sdram_size(cols, rows, banks, width);
+}
+
+static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+{
arm_add_mem_device("ram0", data->base0,
- size);
+ vf610_ddrmc_sdram_size(mmdcbase));
}
static int imx_esdctl_probe(struct device_d *dev)
@@ -373,15 +386,20 @@ static __maybe_unused struct imx_esdctl_data imx53_data = {
};
static __maybe_unused struct imx_esdctl_data imx6q_data = {
- .base0 = MX6_MMDC_PORT0_BASE_ADDR,
+ .base0 = MX6_MMDC_PORT01_BASE_ADDR,
.add_mem = imx6_mmdc_add_mem,
};
static __maybe_unused struct imx_esdctl_data imx6ul_data = {
- .base0 = 0x80000000,
+ .base0 = MX6_MMDC_PORT0_BASE_ADDR,
.add_mem = imx6_mmdc_add_mem,
};
+static __maybe_unused struct imx_esdctl_data vf610_data = {
+ .base0 = VF610_RAM_BASE_ADDR,
+ .add_mem = vf610_ddrmc_add_mem,
+};
+
static struct platform_device_id imx_esdctl_ids[] = {
#ifdef CONFIG_ARCH_IMX1
{
@@ -441,6 +459,9 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
.compatible = "fsl,imx6q-mmdc",
.data = &imx6q_data
}, {
+ .compatible = "fsl,vf610-ddrmc",
+ .data = &vf610_data
+ }, {
/* sentinel */
}
};
@@ -498,9 +519,9 @@ void __noreturn imx1_barebox_entry(void *boarddata)
unsigned long base, size;
upper_or_coalesced_range(MX1_CSD0_BASE_ADDR,
- imx_v1_sdram_size((void *)MX1_SDRAMC_BASE_ADDR, 0),
+ imx_v1_sdram_size(IOMEM(MX1_SDRAMC_BASE_ADDR), 0),
MX1_CSD1_BASE_ADDR,
- imx_v1_sdram_size((void *)MX1_SDRAMC_BASE_ADDR, 1),
+ imx_v1_sdram_size(IOMEM(MX1_SDRAMC_BASE_ADDR), 1),
&base, &size);
barebox_arm_entry(base, size, boarddata);
@@ -511,9 +532,9 @@ void __noreturn imx25_barebox_entry(void *boarddata)
unsigned long base, size;
upper_or_coalesced_range(MX25_CSD0_BASE_ADDR,
- imx_v2_sdram_size((void *)MX25_ESDCTL_BASE_ADDR, 0),
+ imx_v2_sdram_size(IOMEM(MX25_ESDCTL_BASE_ADDR), 0),
MX25_CSD1_BASE_ADDR,
- imx_v2_sdram_size((void *)MX25_ESDCTL_BASE_ADDR, 1),
+ imx_v2_sdram_size(IOMEM(MX25_ESDCTL_BASE_ADDR), 1),
&base, &size);
barebox_arm_entry(base, size, boarddata);
@@ -523,12 +544,12 @@ void __noreturn imx27_barebox_entry(void *boarddata)
{
unsigned long base, size;
- imx_esdctl_v2_disable_default((void *)MX27_ESDCTL_BASE_ADDR);
+ imx_esdctl_v2_disable_default(IOMEM(MX27_ESDCTL_BASE_ADDR));
upper_or_coalesced_range(MX27_CSD0_BASE_ADDR,
- imx_v2_sdram_size((void *)MX27_ESDCTL_BASE_ADDR, 0),
+ imx_v2_sdram_size(IOMEM(MX27_ESDCTL_BASE_ADDR), 0),
MX27_CSD1_BASE_ADDR,
- imx_v2_sdram_size((void *)MX27_ESDCTL_BASE_ADDR, 1),
+ imx_v2_sdram_size(IOMEM(MX27_ESDCTL_BASE_ADDR), 1),
&base, &size);
barebox_arm_entry(base, size, boarddata);
@@ -538,12 +559,12 @@ void __noreturn imx31_barebox_entry(void *boarddata)
{
unsigned long base, size;
- imx_esdctl_v2_disable_default((void *)MX31_ESDCTL_BASE_ADDR);
+ imx_esdctl_v2_disable_default(IOMEM(MX31_ESDCTL_BASE_ADDR));
upper_or_coalesced_range(MX31_CSD0_BASE_ADDR,
- imx_v2_sdram_size((void *)MX31_ESDCTL_BASE_ADDR, 0),
+ imx_v2_sdram_size(IOMEM(MX31_ESDCTL_BASE_ADDR), 0),
MX31_CSD1_BASE_ADDR,
- imx_v2_sdram_size((void *)MX31_ESDCTL_BASE_ADDR, 1),
+ imx_v2_sdram_size(IOMEM(MX31_ESDCTL_BASE_ADDR), 1),
&base, &size);
barebox_arm_entry(base, size, boarddata);
@@ -553,12 +574,12 @@ void __noreturn imx35_barebox_entry(void *boarddata)
{
unsigned long base, size;
- imx_esdctl_v2_disable_default((void *)MX35_ESDCTL_BASE_ADDR);
+ imx_esdctl_v2_disable_default(IOMEM(MX35_ESDCTL_BASE_ADDR));
upper_or_coalesced_range(MX35_CSD0_BASE_ADDR,
- imx_v2_sdram_size((void *)MX35_ESDCTL_BASE_ADDR, 0),
+ imx_v2_sdram_size(IOMEM(MX35_ESDCTL_BASE_ADDR), 0),
MX35_CSD1_BASE_ADDR,
- imx_v2_sdram_size((void *)MX35_ESDCTL_BASE_ADDR, 1),
+ imx_v2_sdram_size(IOMEM(MX35_ESDCTL_BASE_ADDR), 1),
&base, &size);
barebox_arm_entry(base, size, boarddata);
@@ -569,9 +590,9 @@ void __noreturn imx51_barebox_entry(void *boarddata)
unsigned long base, size;
upper_or_coalesced_range(MX51_CSD0_BASE_ADDR,
- imx_v3_sdram_size((void *)MX51_ESDCTL_BASE_ADDR, 0),
+ imx_v3_sdram_size(IOMEM(MX51_ESDCTL_BASE_ADDR), 0),
MX51_CSD1_BASE_ADDR,
- imx_v3_sdram_size((void *)MX51_ESDCTL_BASE_ADDR, 1),
+ imx_v3_sdram_size(IOMEM(MX51_ESDCTL_BASE_ADDR), 1),
&base, &size);
barebox_arm_entry(base, size, boarddata);
@@ -582,32 +603,35 @@ void __noreturn imx53_barebox_entry(void *boarddata)
unsigned long base, size;
upper_or_coalesced_range(MX53_CSD0_BASE_ADDR,
- imx_v4_sdram_size((void *)MX53_ESDCTL_BASE_ADDR, 0),
+ imx_v4_sdram_size(IOMEM(MX53_ESDCTL_BASE_ADDR), 0),
MX53_CSD1_BASE_ADDR,
- imx_v4_sdram_size((void *)MX53_ESDCTL_BASE_ADDR, 1),
+ imx_v4_sdram_size(IOMEM(MX53_ESDCTL_BASE_ADDR), 1),
&base, &size);
barebox_arm_entry(base, size, boarddata);
}
-void __noreturn imx6q_barebox_entry(void *boarddata)
+static void __noreturn
+imx6_barebox_entry(unsigned long membase, void *boarddata)
{
- u64 size_cs0 = imx6_mmdc_sdram_size((void *)MX6_MMDC_P0_BASE_ADDR, 0);
- u64 size_cs1 = imx6_mmdc_sdram_size((void *)MX6_MMDC_P0_BASE_ADDR, 1);
- u64 total = size_cs0 + size_cs1;
-
- resource_size_t size = min(total, (u64)IMX6_MAX_SDRAM_SIZE);
+ barebox_arm_entry(membase,
+ imx6_mmdc_sdram_size(IOMEM(MX6_MMDC_P0_BASE_ADDR)),
+ boarddata);
+}
- barebox_arm_entry(0x10000000, size, boarddata);
+void __noreturn imx6q_barebox_entry(void *boarddata)
+{
+ imx6_barebox_entry(MX6_MMDC_PORT01_BASE_ADDR, boarddata);
}
void __noreturn imx6ul_barebox_entry(void *boarddata)
{
- u64 size_cs0 = imx6_mmdc_sdram_size((void *)MX6_MMDC_P0_BASE_ADDR, 0);
- u64 size_cs1 = imx6_mmdc_sdram_size((void *)MX6_MMDC_P0_BASE_ADDR, 1);
- u64 total = size_cs0 + size_cs1;
-
- resource_size_t size = min(total, (u64)IMX6_MAX_SDRAM_SIZE);
+ imx6_barebox_entry(MX6_MMDC_PORT0_BASE_ADDR, boarddata);
+}
- barebox_arm_entry(0x80000000, size, boarddata);
+void __noreturn vf610_barebox_entry(void *boarddata)
+{
+ barebox_arm_entry(VF610_RAM_BASE_ADDR,
+ vf610_ddrmc_sdram_size(IOMEM(VF610_DDR_BASE_ADDR)),
+ boarddata);
}
diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
index 9400105c6..1b4c1b3df 100644
--- a/arch/arm/mach-imx/imx.c
+++ b/arch/arm/mach-imx/imx.c
@@ -14,8 +14,10 @@
#include <common.h>
#include <of.h>
#include <init.h>
+#include <io.h>
#include <mach/revision.h>
#include <mach/generic.h>
+#include <mach/reset-reason.h>
static int __imx_silicon_revision = IMX_CHIP_REV_UNKNOWN;
@@ -28,7 +30,10 @@ void imx_set_silicon_revision(const char *soc, int revision)
{
__imx_silicon_revision = revision;
- pr_info("detected %s revision %d.%d\n", soc,
+ if (revision == IMX_CHIP_REV_UNKNOWN)
+ pr_info("detected %s revision unknown\n", soc);
+ else
+ pr_info("detected %s revision %d.%d\n", soc,
(revision >> 4) & 0xf,
revision & 0xf);
}
@@ -114,7 +119,7 @@ static int imx_init(void)
else if (cpu_is_mx7())
ret = imx7_init();
else if (cpu_is_vf610())
- ret = 0;
+ ret = vf610_init();
else
return -EINVAL;
@@ -147,3 +152,46 @@ static int imx_init(void)
return ret;
}
postcore_initcall(imx_init);
+
+const struct imx_reset_reason imx_reset_reasons[] = {
+ { IMX_SRC_SRSR_IPP_RESET, RESET_POR, 0 },
+ { IMX_SRC_SRSR_WDOG1_RESET, RESET_WDG, 0 },
+ { IMX_SRC_SRSR_JTAG_RESET, RESET_JTAG, 0 },
+ { IMX_SRC_SRSR_JTAG_SW_RESET, RESET_JTAG, 0 },
+ { IMX_SRC_SRSR_WARM_BOOT, RESET_RST, 0 },
+ { /* sentinel */ }
+};
+
+void imx_set_reset_reason(void __iomem *srsr,
+ const struct imx_reset_reason *reasons)
+{
+ enum reset_src_type type = RESET_UKWN;
+ const u32 reg = readl(srsr);
+ int i, instance = 0;
+
+ /*
+ * SRSR register captures ALL reset event that occured since
+ * POR, so we need to clear it to make sure we only caputre
+ * the latest one.
+ */
+ writel(reg, srsr);
+
+ for (i = 0; reasons[i].mask; i++) {
+ if (reg & reasons[i].mask) {
+ type = reasons[i].type;
+ instance = reasons[i].instance;
+ break;
+ }
+ }
+
+ /*
+ * Report this with above default priority in order to make
+ * sure we'll always override info from watchdog driver.
+ */
+ reset_source_set_priority(type,
+ RESET_SOURCE_DEFAULT_PRIORITY + 1);
+ reset_source_set_instance(type, instance);
+
+ pr_info("i.MX reset reason %s (SRSR: 0x%08x)\n",
+ reset_source_name(), reg);
+}
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index ffe6a7c65..ec8cdd868 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -21,6 +21,7 @@
#include <mach/revision.h>
#include <mach/clock-imx51_53.h>
#include <mach/generic.h>
+#include <mach/reset-reason.h>
#define IIM_SREV 0x24
@@ -43,7 +44,7 @@ static int imx51_silicon_revision(void)
static void imx51_ipu_mipi_setup(void)
{
- void __iomem *hsc_addr = (void __iomem *)MX51_MIPI_HSC_BASE_ADDR;
+ void __iomem *hsc_addr = IOMEM(MX51_MIPI_HSC_BASE_ADDR);
u32 val;
/* setup MIPI module to legacy mode */
@@ -57,7 +58,10 @@ static void imx51_ipu_mipi_setup(void)
int imx51_init(void)
{
+ void __iomem *src = IOMEM(MX51_SRC_BASE_ADDR);
+
imx_set_silicon_revision("i.MX51", imx51_silicon_revision());
+ imx_set_reset_reason(src + IMX_SRC_SRSR, imx_reset_reasons);
imx51_boot_save_loc();
add_generic_device("imx51-esdctl", 0, NULL, MX51_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
imx51_ipu_mipi_setup();
@@ -97,7 +101,7 @@ int imx51_devices_init(void)
*/
static void imx51_setup_pll800_bug(void)
{
- void __iomem *base = (void *)MX51_PLL1_BASE_ADDR;
+ void __iomem *base = IOMEM(MX51_PLL1_BASE_ADDR);
u32 dp_config;
volatile int i;
@@ -132,7 +136,7 @@ static void imx51_setup_pll800_bug(void)
void imx51_init_lowlevel(unsigned int cpufreq_mhz)
{
- void __iomem *ccm = (void __iomem *)MX51_CCM_BASE_ADDR;
+ void __iomem *ccm = IOMEM(MX51_CCM_BASE_ADDR);
u32 r;
int rev = imx51_silicon_revision();
@@ -167,30 +171,30 @@ void imx51_init_lowlevel(unsigned int cpufreq_mhz)
switch (cpufreq_mhz) {
case 600:
- imx5_setup_pll_600((void __iomem *)MX51_PLL1_BASE_ADDR);
+ imx5_setup_pll_600(IOMEM(MX51_PLL1_BASE_ADDR));
break;
default:
/* Default maximum 800MHz */
if (rev <= IMX_CHIP_REV_3_0)
imx51_setup_pll800_bug();
else
- imx5_setup_pll_800((void __iomem *)MX51_PLL1_BASE_ADDR);
+ imx5_setup_pll_800(IOMEM(MX51_PLL1_BASE_ADDR));
break;
}
- imx5_setup_pll_665((void __iomem *)MX51_PLL3_BASE_ADDR);
+ imx5_setup_pll_665(IOMEM(MX51_PLL3_BASE_ADDR));
/* Switch peripheral to PLL 3 */
writel(0x000010C0, ccm + MX5_CCM_CBCMR);
writel(0x13239145, ccm + MX5_CCM_CBCDR);
- imx5_setup_pll_665((void __iomem *)MX51_PLL2_BASE_ADDR);
+ imx5_setup_pll_665(IOMEM(MX51_PLL2_BASE_ADDR));
/* Switch peripheral to PLL2 */
writel(0x19239145, ccm + MX5_CCM_CBCDR);
writel(0x000020C0, ccm + MX5_CCM_CBCMR);
- imx5_setup_pll_216((void __iomem *)MX51_PLL3_BASE_ADDR);
+ imx5_setup_pll_216(IOMEM(MX51_PLL3_BASE_ADDR));
/* Set the platform clock dividers */
writel(0x00000125, MX51_ARM_BASE_ADDR + 0x14);
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index 2758f1bbc..56f1bda75 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -21,6 +21,7 @@
#include <mach/revision.h>
#include <mach/clock-imx51_53.h>
#include <mach/generic.h>
+#include <mach/reset-reason.h>
#define SI_REV 0x48
@@ -52,7 +53,10 @@ static int imx53_silicon_revision(void)
int imx53_init(void)
{
+ void __iomem *src = IOMEM(MX53_SRC_BASE_ADDR);
+
imx53_silicon_revision();
+ imx_set_reset_reason(src + IMX_SRC_SRSR, imx_reset_reasons);
imx53_boot_save_loc();
add_generic_device("imx53-esdctl", 0, NULL, MX53_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 14a1cba5a..eaf9f2e41 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -16,9 +16,11 @@
#include <io.h>
#include <linux/sizes.h>
#include <mfd/imx6q-iomuxc-gpr.h>
+#include <mach/clock-imx6.h>
#include <mach/imx6.h>
#include <mach/generic.h>
#include <mach/revision.h>
+#include <mach/reset-reason.h>
#include <mach/imx6-anadig.h>
#include <mach/imx6-regs.h>
#include <mach/generic.h>
@@ -44,6 +46,11 @@ static void imx6_init_lowlevel(void)
void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D;
+ uint32_t val_480;
+ uint32_t val_528;
+ uint32_t periph_sel_1;
+ uint32_t periph_sel_2;
+ uint32_t reg;
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -68,32 +75,38 @@ static void imx6_init_lowlevel(void)
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
* to make sure PFD is working right, otherwise, PFDs may
* not output clock after reset, MX6DL and MX6SL have added 396M pfd
- * workaround in ROM code, as bus clock need it
+ * workaround in ROM code, as bus clock need it.
+ * Don't reset PLL2 PFD0 / PLL2 PFD2 if is's used by periph_clk.
*/
if (is_imx6q || is_imx6d) {
- writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
- BM_ANADIG_PFD_480_PFD2_CLKGATE |
- BM_ANADIG_PFD_480_PFD1_CLKGATE |
- BM_ANADIG_PFD_480_PFD0_CLKGATE,
- MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
- writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
- BM_ANADIG_PFD_528_PFD2_CLKGATE |
- BM_ANADIG_PFD_528_PFD1_CLKGATE |
- BM_ANADIG_PFD_528_PFD0_CLKGATE,
- MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
-
- writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
- BM_ANADIG_PFD_480_PFD2_CLKGATE |
- BM_ANADIG_PFD_480_PFD1_CLKGATE |
- BM_ANADIG_PFD_480_PFD0_CLKGATE,
- MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
- writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
- BM_ANADIG_PFD_528_PFD2_CLKGATE |
- BM_ANADIG_PFD_528_PFD1_CLKGATE |
- BM_ANADIG_PFD_528_PFD0_CLKGATE,
- MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
- }
+ val_480 = BM_ANADIG_PFD_480_PFD3_CLKGATE |
+ BM_ANADIG_PFD_480_PFD2_CLKGATE |
+ BM_ANADIG_PFD_480_PFD1_CLKGATE |
+ BM_ANADIG_PFD_480_PFD0_CLKGATE;
+
+ val_528 = BM_ANADIG_PFD_528_PFD3_CLKGATE |
+ BM_ANADIG_PFD_528_PFD1_CLKGATE;
+
+ reg = readl(MXC_CCM_CBCMR);
+ periph_sel_1 = (reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
+ >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
+
+ periph_sel_2 = (reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
+ >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET;
+
+ if ((periph_sel_1 != 0x2) && (periph_sel_2 != 0x2))
+ val_528 |= BM_ANADIG_PFD_528_PFD0_CLKGATE;
+
+ if ((periph_sel_1 != 0x1) && (periph_sel_2 != 0x1)
+ && (periph_sel_1 != 0x3) && (periph_sel_2 != 0x3))
+ val_528 |= BM_ANADIG_PFD_528_PFD2_CLKGATE;
+
+ writel(val_480, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
+ writel(val_528, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
+ writel(val_480, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
+ writel(val_528, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
+ }
}
static void imx6_setup_ipu_qos(void)
@@ -147,10 +160,37 @@ static void imx6ul_enet_clk_init(void)
writel(val, gprbase + IOMUXC_GPR1);
}
+int imx6_cpu_type(void)
+{
+ static int cpu_type = -1;
+
+ if (!cpu_is_mx6())
+ return 0;
+
+ if (cpu_type < 0)
+ cpu_type = __imx6_cpu_type();
+
+ return cpu_type;
+}
+
+int imx6_cpu_revision(void)
+{
+ static int soc_revision = -1;
+
+ if (!cpu_is_mx6())
+ return 0;
+
+ if (soc_revision < 0)
+ soc_revision = __imx6_cpu_revision();
+
+ return soc_revision;
+}
+
int imx6_init(void)
{
const char *cputypestr;
u32 mx6_silicon_revision;
+ void __iomem *src = IOMEM(MX6_SRC_BASE_ADDR);
imx6_init_lowlevel();
@@ -160,16 +200,16 @@ int imx6_init(void)
switch (imx6_cpu_type()) {
case IMX6_CPUTYPE_IMX6Q:
- if (mx6_silicon_revision >= IMX_CHIP_REV_2_0)
- cputypestr = "i.MX6 Quad Plus";
- else
- cputypestr = "i.MX6 Quad";
+ cputypestr = "i.MX6 Quad";
+ break;
+ case IMX6_CPUTYPE_IMX6QP:
+ cputypestr = "i.MX6 Quad Plus";
break;
case IMX6_CPUTYPE_IMX6D:
- if (mx6_silicon_revision >= IMX_CHIP_REV_2_0)
- cputypestr = "i.MX6 Dual Plus";
- else
- cputypestr = "i.MX6 Dual";
+ cputypestr = "i.MX6 Dual";
+ break;
+ case IMX6_CPUTYPE_IMX6DP:
+ cputypestr = "i.MX6 Dual Plus";
break;
case IMX6_CPUTYPE_IMX6DL:
cputypestr = "i.MX6 DualLite";
@@ -195,7 +235,7 @@ int imx6_init(void)
}
imx_set_silicon_revision(cputypestr, mx6_silicon_revision);
-
+ imx_set_reset_reason(src + IMX_SRC_SRSR, imx_reset_reasons);
imx6_setup_ipu_qos();
imx6ul_enet_clk_init();
diff --git a/arch/arm/mach-imx/imx7.c b/arch/arm/mach-imx/imx7.c
index 4eef99c87..e49baf6f7 100644
--- a/arch/arm/mach-imx/imx7.c
+++ b/arch/arm/mach-imx/imx7.c
@@ -19,6 +19,7 @@
#include <mach/imx7.h>
#include <mach/generic.h>
#include <mach/revision.h>
+#include <mach/reset-reason.h>
#include <mach/imx7-regs.h>
void imx7_init_lowlevel(void)
@@ -167,10 +168,21 @@ static struct psci_ops imx7_psci_ops = {
.cpu_off = imx7_cpu_off,
};
+static const struct imx_reset_reason imx7_reset_reasons[] = {
+ { IMX_SRC_SRSR_IPP_RESET, RESET_POR, 0 },
+ { IMX_SRC_SRSR_WDOG1_RESET, RESET_WDG, 0 },
+ { IMX_SRC_SRSR_JTAG_RESET, RESET_JTAG, 0 },
+ { IMX_SRC_SRSR_JTAG_SW_RESET, RESET_JTAG, 0 },
+ { IMX_SRC_SRSR_WDOG3_RESET, RESET_WDG, 1 },
+ { IMX_SRC_SRSR_WDOG4_RESET, RESET_WDG, 2 },
+ { IMX_SRC_SRSR_TEMPSENSE_RESET, RESET_THERM, 0 },
+ { /* sentinel */ }
+};
+
int imx7_init(void)
{
const char *cputypestr;
- u32 imx7_silicon_revision;
+ void __iomem *src = IOMEM(MX7_SRC_BASE_ADDR);
imx7_init_lowlevel();
@@ -180,8 +192,6 @@ int imx7_init(void)
imx7_boot_save_loc();
- imx7_silicon_revision = imx7_cpu_revision();
-
psci_set_ops(&imx7_psci_ops);
switch (imx7_cpu_type()) {
@@ -196,7 +206,8 @@ int imx7_init(void)
break;
}
- imx_set_silicon_revision(cputypestr, imx7_silicon_revision);
+ imx_set_silicon_revision(cputypestr, imx7_cpu_revision());
+ imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons);
return 0;
}
diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h
index 66dcc8974..117e2bbad 100644
--- a/arch/arm/mach-imx/include/mach/esdctl.h
+++ b/arch/arm/mach-imx/include/mach/esdctl.h
@@ -48,6 +48,7 @@
#define ESDMISC_MDDR_MDIS 0x00000010
#define ESDMISC_LHD 0x00000020
#define ESDMISC_SDRAMRDY 0x80000000
+#define ESDMISC_DDR2_8_BANK BIT(6)
#define ESDCFGx_tXP_MASK 0x00600000
#define ESDCFGx_tXP_1 0x00000000
@@ -137,6 +138,7 @@ void __noreturn imx51_barebox_entry(void *boarddata);
void __noreturn imx53_barebox_entry(void *boarddata);
void __noreturn imx6q_barebox_entry(void *boarddata);
void __noreturn imx6ul_barebox_entry(void *boarddata);
+void __noreturn vf610_barebox_entry(void *boarddata);
void imx_esdctl_disable(void);
#endif
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index f68dc875b..ad9d9cb02 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -15,6 +15,7 @@ void imx51_boot_save_loc(void);
void imx53_boot_save_loc(void);
void imx6_boot_save_loc(void);
void imx7_boot_save_loc(void);
+void vf610_boot_save_loc(void);
void imx25_get_boot_source(enum bootsource *src, int *instance);
void imx35_get_boot_source(enum bootsource *src, int *instance);
@@ -22,6 +23,7 @@ void imx51_get_boot_source(enum bootsource *src, int *instance);
void imx53_get_boot_source(enum bootsource *src, int *instance);
void imx6_get_boot_source(enum bootsource *src, int *instance);
void imx7_get_boot_source(enum bootsource *src, int *instance);
+void vf610_get_boot_source(enum bootsource *src, int *instance);
int imx1_init(void);
int imx21_init(void);
@@ -34,6 +36,7 @@ int imx51_init(void);
int imx53_init(void);
int imx6_init(void);
int imx7_init(void);
+int vf610_init(void);
int imx1_devices_init(void);
int imx21_devices_init(void);
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
index ac2aa2109..1ba22b5bc 100644
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -117,6 +117,8 @@
#define MX6_SATA_BASE_ADDR 0x02200000
-#define MX6_MMDC_PORT0_BASE_ADDR 0x10000000
+#define MX6_MMDC_PORT01_BASE_ADDR 0x10000000
+#define MX6_MMDC_PORT0_BASE_ADDR 0x80000000
+
#endif /* __MACH_IMX6_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h
index 6b08e6a52..5701bd480 100644
--- a/arch/arm/mach-imx/include/mach/imx6.h
+++ b/arch/arm/mach-imx/include/mach/imx6.h
@@ -16,7 +16,9 @@ void __noreturn imx6_pm_stby_poweroff(void);
#define IMX6_CPUTYPE_IMX6DL 0x261
#define IMX6_CPUTYPE_IMX6SX 0x462
#define IMX6_CPUTYPE_IMX6D 0x263
+#define IMX6_CPUTYPE_IMX6DP 0x1263
#define IMX6_CPUTYPE_IMX6Q 0x463
+#define IMX6_CPUTYPE_IMX6QP 0x1463
#define IMX6_CPUTYPE_IMX6UL 0x164
#define IMX6_CPUTYPE_IMX6ULL 0x165
@@ -33,36 +35,51 @@ static inline int scu_get_core_count(void)
return (ncores & 0x03) + 1;
}
-static inline int __imx6_cpu_type(void)
+#define SI_REV_CPUTYPE(s) (((s) >> 16) & 0xff)
+#define SI_REV_MAJOR(s) (((s) >> 8) & 0xf)
+#define SI_REV_MINOR(s) ((s) & 0xf)
+
+static inline uint32_t __imx6_read_si_rev(void)
{
- uint32_t val;
-
- val = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV);
- val = (val >> 16) & 0xff;
- /* non-MX6-standard SI_REV reg offset for MX6SL */
- if (IS_ENABLED(CONFIG_ARCH_IMX6SL) &&
- val < (IMX6_CPUTYPE_IMX6S & 0xff)) {
- uint32_t tmp;
- tmp = readl(MX6_ANATOP_BASE_ADDR + IMX6SL_ANATOP_SI_REV);
- tmp = (tmp >> 16) & 0xff;
- if ((IMX6_CPUTYPE_IMX6SL & 0xff) == tmp)
- /* intentionally skip scu_get_core_count() for MX6SL */
- return IMX6_CPUTYPE_IMX6SL;
- }
+ uint32_t si_rev;
+ uint32_t cpu_type;
+
+ si_rev = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV);
+ cpu_type = SI_REV_CPUTYPE(si_rev);
- val |= scu_get_core_count() << 8;
+ if (cpu_type >= 0x61 && cpu_type <= 0x65)
+ return si_rev;
- return val;
+ /* try non-MX6-standard SI_REV reg offset for MX6SL */
+ si_rev = readl(MX6_ANATOP_BASE_ADDR + IMX6SL_ANATOP_SI_REV);
+ cpu_type = SI_REV_CPUTYPE(si_rev);
+
+ if (si_rev == 0x60)
+ return si_rev;
+
+ return 0;
}
-static inline int imx6_cpu_type(void)
+static inline int __imx6_cpu_type(void)
{
- if (!cpu_is_mx6())
- return 0;
+ uint32_t si_rev = __imx6_read_si_rev();
+ uint32_t cpu_type = SI_REV_CPUTYPE(si_rev);
+
+ /* intentionally skip scu_get_core_count() for MX6SL */
+ if (cpu_type == IMX6_CPUTYPE_IMX6SL)
+ return IMX6_CPUTYPE_IMX6SL;
- return __imx6_cpu_type();
+ cpu_type |= scu_get_core_count() << 8;
+
+ if ((cpu_type == IMX6_CPUTYPE_IMX6D || cpu_type == IMX6_CPUTYPE_IMX6Q) &&
+ SI_REV_MAJOR(si_rev) >= 1)
+ cpu_type |= 0x1000;
+
+ return cpu_type;
}
+int imx6_cpu_type(void);
+
#define DEFINE_MX6_CPU_TYPE(str, type) \
static inline int cpu_mx6_is_##str(void) \
{ \
@@ -76,10 +93,19 @@ static inline int imx6_cpu_type(void)
return cpu_mx6_is_##str(); \
}
+/*
+ * Below are defined:
+ *
+ * cpu_is_mx6s(), cpu_is_mx6dl(), cpu_is_mx6q(), cpu_is_mx6qp(), cpu_is_mx6d(),
+ * cpu_is_mx6dp(), cpu_is_mx6sx(), cpu_is_mx6sl(), cpu_is_mx6ul(),
+ * cpu_is_mx6ull()
+ */
DEFINE_MX6_CPU_TYPE(mx6s, IMX6_CPUTYPE_IMX6S);
DEFINE_MX6_CPU_TYPE(mx6dl, IMX6_CPUTYPE_IMX6DL);
DEFINE_MX6_CPU_TYPE(mx6q, IMX6_CPUTYPE_IMX6Q);
+DEFINE_MX6_CPU_TYPE(mx6qp, IMX6_CPUTYPE_IMX6QP);
DEFINE_MX6_CPU_TYPE(mx6d, IMX6_CPUTYPE_IMX6D);
+DEFINE_MX6_CPU_TYPE(mx6dp, IMX6_CPUTYPE_IMX6DP);
DEFINE_MX6_CPU_TYPE(mx6sx, IMX6_CPUTYPE_IMX6SX);
DEFINE_MX6_CPU_TYPE(mx6sl, IMX6_CPUTYPE_IMX6SL);
DEFINE_MX6_CPU_TYPE(mx6ul, IMX6_CPUTYPE_IMX6UL);
@@ -87,27 +113,15 @@ DEFINE_MX6_CPU_TYPE(mx6ull, IMX6_CPUTYPE_IMX6ULL);
static inline int __imx6_cpu_revision(void)
{
- uint32_t rev;
- uint32_t si_rev_offset = IMX6_ANATOP_SI_REV;
+ uint32_t si_rev = __imx6_read_si_rev();
u8 major_part, minor_part;
- if (IS_ENABLED(CONFIG_ARCH_IMX6SL) && cpu_mx6_is_mx6sl())
- si_rev_offset = IMX6SL_ANATOP_SI_REV;
-
- rev = readl(MX6_ANATOP_BASE_ADDR + si_rev_offset);
-
- major_part = (rev >> 8) & 0xf;
- minor_part = rev & 0xf;
+ major_part = (si_rev >> 8) & 0xf;
+ minor_part = si_rev & 0xf;
return ((major_part + 1) << 4) | minor_part;
}
-static inline int imx6_cpu_revision(void)
-{
- if (!cpu_is_mx6())
- return 0;
-
- return __imx6_cpu_revision();
-}
+int imx6_cpu_revision(void);
#endif /* __MACH_IMX6_H */
diff --git a/arch/arm/mach-imx/include/mach/reset-reason.h b/arch/arm/mach-imx/include/mach/reset-reason.h
new file mode 100644
index 000000000..0f644a8c1
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/reset-reason.h
@@ -0,0 +1,37 @@
+#ifndef __MACH_RESET_REASON_H__
+#define __MACH_RESET_REASON_H__
+
+#include <reset_source.h>
+
+#define IMX_SRC_SRSR_IPP_RESET BIT(0)
+#define IMX_SRC_SRSR_CSU_RESET BIT(2)
+#define IMX_SRC_SRSR_IPP_USER_RESET BIT(3)
+#define IMX_SRC_SRSR_WDOG1_RESET BIT(4)
+#define IMX_SRC_SRSR_JTAG_RESET BIT(5)
+#define IMX_SRC_SRSR_JTAG_SW_RESET BIT(6)
+#define IMX_SRC_SRSR_WDOG3_RESET BIT(7)
+#define IMX_SRC_SRSR_WDOG4_RESET BIT(8)
+#define IMX_SRC_SRSR_TEMPSENSE_RESET BIT(9)
+#define IMX_SRC_SRSR_WARM_BOOT BIT(16)
+
+#define IMX_SRC_SRSR 0x008
+#define IMX7_SRC_SRSR 0x05c
+
+#define VF610_SRC_SRSR_SW_RST BIT(18)
+#define VF610_SRC_SRSR_RESETB BIT(7)
+#define VF610_SRC_SRSR_JTAG_RST BIT(5)
+#define VF610_SRC_SRSR_WDOG_M4 BIT(4)
+#define VF610_SRC_SRSR_WDOG_A5 BIT(3)
+#define VF610_SRC_SRSR_POR_RST BIT(0)
+
+struct imx_reset_reason {
+ uint32_t mask;
+ enum reset_src_type type;
+ int instance;
+};
+
+void imx_set_reset_reason(void __iomem *, const struct imx_reset_reason *);
+
+extern const struct imx_reset_reason imx_reset_reasons[];
+
+#endif /* __MACH_RESET_REASON_H__ */
diff --git a/arch/arm/mach-imx/include/mach/vf610-ddrmc.h b/arch/arm/mach-imx/include/mach/vf610-ddrmc.h
new file mode 100644
index 000000000..07feb036e
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/vf610-ddrmc.h
@@ -0,0 +1,18 @@
+#ifndef __MACH_DDRMC_H
+#define __MACH_DDRMC_H
+
+#include <mach/vf610-regs.h>
+
+
+#define DDRMC_CR(x) ((x) * 4)
+
+#define DDRMC_CR01_MAX_COL_REG(reg) (((reg) >> 8) & 0b01111)
+#define DDRMC_CR01_MAX_ROW_REG(reg) (((reg) >> 0) & 0b11111)
+#define DDRMC_CR73_COL_DIFF(reg) (((reg) >> 16) & 0b00111)
+#define DDRMC_CR73_ROW_DIFF(reg) (((reg) >> 8) & 0b00011)
+#define DDRMC_CR73_BANK_DIFF(reg) (((reg) >> 0) & 0b00011)
+
+#define DDRMC_CR78_REDUC BIT(8)
+
+
+#endif /* __MACH_MMDC_H */
diff --git a/arch/arm/mach-imx/include/mach/vf610-regs.h b/arch/arm/mach-imx/include/mach/vf610-regs.h
index 8be220b68..416b457af 100644
--- a/arch/arm/mach-imx/include/mach/vf610-regs.h
+++ b/arch/arm/mach-imx/include/mach/vf610-regs.h
@@ -13,6 +13,8 @@
#define VF610_AIPS0_BASE_ADDR 0x40000000
#define VF610_AIPS1_BASE_ADDR 0x40080000
+#define VF610_RAM_BASE_ADDR 0x80000000
+
/* AIPS 0 */
#define VF610_MSCM_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00001000)
#define VF610_MSCM_IR_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00001800)
@@ -107,4 +109,7 @@
#define VF610_MSCM_IRSPRC_CP0_EN 1
#define VF610_MSCM_IRSPRC_NUM 112
+#define VF610_MSCM_CPxCOUNT 0x00c
+#define VF610_MSCM_CPxCFG1 0x014
+
#endif
diff --git a/arch/arm/mach-imx/include/mach/vf610.h b/arch/arm/mach-imx/include/mach/vf610.h
new file mode 100644
index 000000000..6d00d2e45
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/vf610.h
@@ -0,0 +1,51 @@
+#ifndef __MACH_VF610_H
+#define __MACH_VF610_H
+
+#include <io.h>
+#include <mach/generic.h>
+#include <mach/vf610-regs.h>
+#include <mach/revision.h>
+
+#define VF610_CPUTYPE_VFx10 0x010
+
+#define VF610_CPUTYPE_VF610 0x610
+#define VF610_CPUTYPE_VF600 0x600
+#define VF610_CPUTYPE_VF510 0x510
+#define VF610_CPUTYPE_VF500 0x500
+
+#define VF610_ROM_VERSION_OFFSET 0x80
+
+static inline int __vf610_cpu_type(void)
+{
+ void __iomem *mscm = IOMEM(VF610_MSCM_BASE_ADDR);
+ const u32 cpxcount = readl(mscm + VF610_MSCM_CPxCOUNT);
+ const u32 cpxcfg1 = readl(mscm + VF610_MSCM_CPxCFG1);
+ int cpu_type;
+
+ cpu_type = cpxcount ? VF610_CPUTYPE_VF600 : VF610_CPUTYPE_VF500;
+
+ return cpxcfg1 ? cpu_type | VF610_CPUTYPE_VFx10 : cpu_type;
+}
+
+static inline int vf610_cpu_type(void)
+{
+ if (!cpu_is_vf610())
+ return 0;
+
+ return __vf610_cpu_type();
+}
+
+static inline int vf610_cpu_revision(void)
+{
+ if (!cpu_is_vf610())
+ return IMX_CHIP_REV_UNKNOWN;
+
+ /*
+ * There doesn't seem to be a documented way of retreiving
+ * silicon revision on VFxxx cpus, so we just report Mask ROM
+ * version instead
+ */
+ return readl(VF610_ROM_VERSION_OFFSET) & 0xff;
+}
+
+#endif
diff --git a/arch/arm/mach-imx/vf610.c b/arch/arm/mach-imx/vf610.c
new file mode 100644
index 000000000..c535716c1
--- /dev/null
+++ b/arch/arm/mach-imx/vf610.c
@@ -0,0 +1,59 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <init.h>
+#include <common.h>
+#include <io.h>
+#include <linux/sizes.h>
+#include <mach/generic.h>
+#include <mach/revision.h>
+#include <mach/vf610.h>
+#include <mach/reset-reason.h>
+
+static const struct imx_reset_reason vf610_reset_reasons[] = {
+ { VF610_SRC_SRSR_POR_RST, RESET_POR, 0 },
+ { VF610_SRC_SRSR_WDOG_A5, RESET_WDG, 0 },
+ { VF610_SRC_SRSR_WDOG_M4, RESET_WDG, 1 },
+ { VF610_SRC_SRSR_JTAG_RST, RESET_JTAG, 0 },
+ { VF610_SRC_SRSR_RESETB, RESET_EXT, 0 },
+ { VF610_SRC_SRSR_SW_RST, RESET_RST, 0 },
+ { /* sentinel */ }
+};
+
+int vf610_init(void)
+{
+ const char *cputypestr;
+ void __iomem *src = IOMEM(VF610_SRC_BASE_ADDR);
+
+ switch (vf610_cpu_type()) {
+ case VF610_CPUTYPE_VF610:
+ cputypestr = "VF610";
+ break;
+ case VF610_CPUTYPE_VF600:
+ cputypestr = "VF600";
+ break;
+ case VF610_CPUTYPE_VF510:
+ cputypestr = "VF510";
+ break;
+ case VF610_CPUTYPE_VF500:
+ cputypestr = "VF500";
+ break;
+ default:
+ cputypestr = "unknown VFxxx";
+ break;
+ }
+
+ imx_set_silicon_revision(cputypestr, vf610_cpu_revision());
+ imx_set_reset_reason(src + IMX_SRC_SRSR, vf610_reset_reasons);
+ return 0;
+}
diff --git a/arch/arm/mach-imx/xload.c b/arch/arm/mach-imx/xload.c
index 16d56ab28..921e9ade2 100644
--- a/arch/arm/mach-imx/xload.c
+++ b/arch/arm/mach-imx/xload.c
@@ -24,7 +24,7 @@ static __noreturn int imx_xload(void)
pr_info("booting from MMC\n");
buf = bootstrap_read_disk("disk0.0", "fat");
break;
- case BOOTSOURCE_SPI:
+ case BOOTSOURCE_SPI_NOR:
pr_info("booting from SPI\n");
buf = bootstrap_read_devfs("dataflash0", false,
SZ_256K, SZ_1M, SZ_1M);
diff --git a/commands/i2c.c b/commands/i2c.c
index 21c39fe5a..f0d16af0c 100644
--- a/commands/i2c.c
+++ b/commands/i2c.c
@@ -131,7 +131,7 @@ static int do_i2c_write(int argc, char *argv[])
for (i = 0; i < count; i++)
*(buf + i) = (char) simple_strtol(argv[optind+i], NULL, 0);
- if (reg > 0) {
+ if (reg >= 0) {
ret = i2c_write_reg(&client, reg | wide, buf, count);
} else {
ret = i2c_master_send(&client, buf, count);
diff --git a/common/bootsource.c b/common/bootsource.c
index 707b07924..78ecd8267 100644
--- a/common/bootsource.c
+++ b/common/bootsource.c
@@ -36,6 +36,7 @@ static const char *bootsource_str[] = {
[BOOTSOURCE_HD] = "harddisk",
[BOOTSOURCE_USB] = "usb",
[BOOTSOURCE_NET] = "net",
+ [BOOTSOURCE_CAN] = "can",
};
static enum bootsource bootsource = BOOTSOURCE_UNKNOWN;
diff --git a/common/reset_source.c b/common/reset_source.c
index 06e2ca85f..338d7b9ac 100644
--- a/common/reset_source.c
+++ b/common/reset_source.c
@@ -32,6 +32,7 @@ static const char * const reset_src_names[] = {
static enum reset_src_type reset_source;
static unsigned int reset_source_priority;
+static int reset_source_instance;
enum reset_src_type reset_source_get(void)
{
@@ -39,6 +40,12 @@ enum reset_src_type reset_source_get(void)
}
EXPORT_SYMBOL(reset_source_get);
+int reset_source_get_instance(void)
+{
+ return reset_source_instance;
+}
+EXPORT_SYMBOL(reset_source_get_instance);
+
void reset_source_set_priority(enum reset_src_type st, unsigned int priority)
{
if (priority <= reset_source_priority)
@@ -46,17 +53,33 @@ void reset_source_set_priority(enum reset_src_type st, unsigned int priority)
reset_source = st;
reset_source_priority = priority;
+ reset_source_instance = 0;
pr_debug("Setting reset source to %s with priority %d\n",
reset_src_names[reset_source], priority);
}
EXPORT_SYMBOL(reset_source_set_priority);
+const char *reset_source_name(void)
+{
+ return reset_src_names[reset_source];
+}
+EXPORT_SYMBOL(reset_source_name);
+
+void reset_source_set_instance(enum reset_src_type type, int instance)
+{
+ if (reset_source == type)
+ reset_source_instance = instance;
+}
+EXPORT_SYMBOL(reset_source_set_instance);
+
static int reset_source_init(void)
{
globalvar_add_simple_enum("system.reset", (unsigned int *)&reset_source,
reset_src_names, ARRAY_SIZE(reset_src_names));
+ globalvar_add_simple_int("system.reset_instance", &reset_source_instance,
+ "%d");
return 0;
}
diff --git a/drivers/aiodev/Kconfig b/drivers/aiodev/Kconfig
index 1c5fabe01..8bad94692 100644
--- a/drivers/aiodev/Kconfig
+++ b/drivers/aiodev/Kconfig
@@ -20,4 +20,10 @@ config LM75
help
Support for LM75 and similar devices
+config MC13XXX_ADC
+ tristate "MC13XXX ADC driver"
+ depends on MFD_MC13XXX
+ help
+ Support for MC13783, MC13892, MC34708 ADC
+
endif
diff --git a/drivers/aiodev/Makefile b/drivers/aiodev/Makefile
index c3d2b081a..1dcf6cdc4 100644
--- a/drivers/aiodev/Makefile
+++ b/drivers/aiodev/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_AIODEV) += core.o
obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
obj-$(CONFIG_LM75) += lm75.o
+obj-$(CONFIG_MC13XXX_ADC) += mc13xxx_adc.o
diff --git a/drivers/aiodev/mc13xxx_adc.c b/drivers/aiodev/mc13xxx_adc.c
new file mode 100644
index 000000000..4e7204816
--- /dev/null
+++ b/drivers/aiodev/mc13xxx_adc.c
@@ -0,0 +1,234 @@
+/*
+ * mc13xxx_adc
+ *
+ * Copyright (c) 2018 Zodiac Inflight Innovation
+ * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
+ * Based on the code of analogous driver from Linux:
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009 Sascha Hauer, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <malloc.h>
+#include <driver.h>
+#include <xfuncs.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <io.h>
+#include <aiodev.h>
+#include <mfd/mc13xxx.h>
+#include <linux/err.h>
+
+#define MC13XXX_ADC0_LICELLCON (1 << 0)
+#define MC13XXX_ADC0_CHRGICON (1 << 1)
+#define MC13XXX_ADC0_BATICON (1 << 2)
+#define MC13XXX_ADC0_BUFEN (1 << 3)
+#define MC13XXX_ADC0_ADIN7SEL_DIE (1 << 4)
+#define MC13XXX_ADC0_ADIN7SEL_UID (2 << 4)
+#define MC13XXX_ADC0_ADREFEN (1 << 10)
+#define MC13XXX_ADC0_TSMOD0 (1 << 12)
+#define MC13XXX_ADC0_TSMOD1 (1 << 13)
+#define MC13XXX_ADC0_TSMOD2 (1 << 14)
+#define MC13XXX_ADC0_ADINC1 (1 << 16)
+#define MC13XXX_ADC0_ADINC2 (1 << 17)
+
+#define MC13XXX_ADC0_TSMOD_MASK (MC13XXX_ADC0_TSMOD0 | \
+ MC13XXX_ADC0_TSMOD1 | \
+ MC13XXX_ADC0_TSMOD2)
+
+#define MC13XXX_ADC0_CONFIG_MASK (MC13XXX_ADC0_TSMOD_MASK | \
+ MC13XXX_ADC0_LICELLCON | \
+ MC13XXX_ADC0_CHRGICON | \
+ MC13XXX_ADC0_BATICON)
+
+#define MC13XXX_ADC1_ADEN (1 << 0)
+#define MC13XXX_ADC1_RAND (1 << 1)
+#define MC13XXX_ADC1_ADSEL (1 << 3)
+#define MC13XXX_ADC1_CHAN0_SHIFT 5
+#define MC13XXX_ADC1_CHAN1_SHIFT 8
+#define MC13XXX_ADC1_ASC (1 << 20)
+#define MC13XXX_ADC1_ADTRIGIGN (1 << 21)
+
+struct mc13xx_adc_data {
+ struct mc13xxx *mc_dev;
+
+ struct aiodevice aiodev;
+ struct aiochannel *aiochan;
+};
+
+static inline struct mc13xx_adc_data *
+to_mc13xx_adc_data(struct aiochannel *chan)
+{
+ return container_of(chan->aiodev, struct mc13xx_adc_data, aiodev);
+}
+
+int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx,
+ unsigned int channel, unsigned int *sample)
+{
+ int i;
+ int timeout = 100;
+ u32 adc0, adc1, old_adc0;
+
+ mc13xxx_reg_read(mc13xxx, MC13783_REG_ADC(0), &old_adc0);
+
+ adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2 | MC13XXX_ADC0_BUFEN;
+ adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
+
+ /* Channels mapped through ADIN7:
+ * 7 - General purpose ADIN7
+ * 16 - UID
+ * 17 - Die temperature */
+ if (channel > 7 && channel < 16) {
+ adc1 |= MC13XXX_ADC1_ADSEL;
+ } else if (channel == 16) {
+ adc0 |= MC13XXX_ADC0_ADIN7SEL_UID;
+ channel = 7;
+ } else if (channel == 17) {
+ adc0 |= MC13XXX_ADC0_ADIN7SEL_DIE;
+ channel = 7;
+ }
+
+ adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
+ adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
+ adc1 |= MC13XXX_ADC1_RAND;
+
+ mc13xxx_reg_write(mc13xxx, MC13783_REG_ADC(0), adc0);
+ mc13xxx_reg_write(mc13xxx, MC13783_REG_ADC(1), adc1);
+
+ /* wait for completion. ASC will set to zero */
+ do {
+ mc13xxx_reg_read(mc13xxx, MC13783_REG_ADC(1), &adc1);
+ } while ((adc1 & MC13XXX_ADC1_ASC) && (--timeout > 0));
+
+ if (timeout == 0)
+ return -ETIMEDOUT;
+
+ for (i = 0; i < 4; ++i) {
+ mc13xxx_reg_read(mc13xxx,
+ MC13783_REG_ADC(2), &sample[i]);
+ }
+
+ return 0;
+}
+
+static int mc13xx_adc_read(struct aiochannel *chan, int *val)
+{
+ int i;
+ int ret;
+ int mc_type;
+ unsigned int sample[4];
+ struct mc13xx_adc_data *mc13xxx_adc;
+ int acc = 0;
+ int index = chan->index;
+
+ mc13xxx_adc = to_mc13xx_adc_data(chan);
+ mc_type = mc13xxx_type(mc13xxx_adc->mc_dev);
+
+ /* add offset for all 8 channel devices becouse t and UID
+ * inputs are mapped to channels 16 and 17 */
+ if ((mc_type != MC13783_TYPE) && (chan->index > 7))
+ index += 8;
+
+ ret = mc13xxx_adc_do_conversion(mc13xxx_adc->mc_dev, index, sample);
+ if (ret < 0)
+ goto err;
+
+ for (i = 0; i < 4; i++) {
+ acc += (sample[i] >> 2 & 0x3ff);
+ acc += (sample[i] >> 14 & 0x3ff);
+ }
+ /* div 8 */
+ acc = acc >> 3;
+
+ if (index == 16) {
+ /* UID */
+ if (mc_type == MC13892_TYPE) {
+ /* MC13892 have 1/2 divider
+ * input range is [0, 4.800V] */
+ acc = DIV_ROUND_CLOSEST(acc * 4800, 1024);
+ } else {
+ /* MC13783 have 0.9 divider
+ *input range is [0, 2.555V] */
+ acc = DIV_ROUND_CLOSEST(acc * 2555, 1024);
+ }
+ } else if (index == 17) {
+ /* Die temperature */
+ if (mc_type == MC13892_TYPE) {
+ /* MC13892:
+ * Die Temperature Read Out Code at 25C 680
+ * Temperature change per LSB +0.4244C */
+ acc = DIV_ROUND_CLOSEST(-2635920 + acc * 4244, 10);
+ } else {
+ /* MC13783:
+ * Die Temperature Read Out Code at 25C 282
+ * Temperature change per LSB -1.14C */
+ acc = 346480 - 1140 * acc;
+ }
+ } else {
+ /* GP input
+ * input range is [0, 2.3V], value has 10 bits */
+ acc = DIV_ROUND_CLOSEST(acc * 2300, 1024);
+ }
+
+ *val = acc;
+err:
+ return ret;
+}
+
+int mc13xxx_adc_probe(struct device_d *dev, struct mc13xxx *mc_dev)
+{
+ int i;
+ int ret;
+ int chans;
+ struct mc13xx_adc_data *mc13xxx_adc;
+
+ mc13xxx_adc = xzalloc(sizeof(*mc13xxx_adc));
+
+ if (mc13xxx_type(mc_dev) == MC13783_TYPE) {
+ /* mc13783 has 16 channels */
+ chans = 16 + 2;
+ } else {
+ chans = 8 + 2;
+ }
+
+ mc13xxx_adc->mc_dev = mc_dev;
+ mc13xxx_adc->aiodev.num_channels = chans;
+ mc13xxx_adc->aiochan = xmalloc(mc13xxx_adc->aiodev.num_channels *
+ sizeof(*mc13xxx_adc->aiochan));
+ mc13xxx_adc->aiodev.hwdev = dev;
+ mc13xxx_adc->aiodev.channels =
+ xmalloc(mc13xxx_adc->aiodev.num_channels *
+ sizeof(mc13xxx_adc->aiodev.channels[0]));
+ /* all channels are voltage inputs, expect last one */
+ for (i = 0; i < chans - 1; i++) {
+ mc13xxx_adc->aiodev.channels[i] = &mc13xxx_adc->aiochan[i];
+ mc13xxx_adc->aiochan[i].unit = "mV";
+ }
+ /* temperature input */
+ mc13xxx_adc->aiodev.channels[i] = &mc13xxx_adc->aiochan[i];
+ mc13xxx_adc->aiochan[i].unit = "mC";
+
+ mc13xxx_adc->aiodev.read = mc13xx_adc_read;
+
+ ret = aiodevice_register(&mc13xxx_adc->aiodev);
+ if (!ret)
+ goto done;
+
+ dev_err(dev, "Failed to register AIODEV: %d\n", ret);
+ kfree(mc13xxx_adc);
+done:
+ return ret;
+}
diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index d0571bce5..8c3bb46a4 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -59,6 +59,11 @@
static struct clk *clks[IMX6QDL_CLK_END];
static struct clk_onecell_data clk_data;
+static inline int cpu_is_plus(void)
+{
+ return cpu_is_mx6qp() || cpu_is_mx6dp();
+}
+
static const char *step_sels[] = {
"osc",
"pll2_pfd2_396m",
@@ -109,6 +114,15 @@ static const char *enfc_sels[] = {
"pll2_pfd2_396m",
};
+static const char *enfc_sels_plus[] = {
+ "pll2_pfd0_352m",
+ "pll2_bus",
+ "pll3_usb_otg",
+ "pll2_pfd2_396m",
+ "pll3_pfd3_454m",
+ "dummy",
+};
+
static const char *eim_sels[] = {
"axi",
"pll3_usb_otg",
@@ -404,7 +418,10 @@ static int imx6_ccm_probe(struct device_d *dev)
clks[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
clks[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
clks[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
- clks[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
+ if (cpu_is_plus())
+ clks[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels_plus, ARRAY_SIZE(enfc_sels_plus));
+ else
+ clks[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
clks[IMX6QDL_CLK_EIM_SEL] = imx_clk_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels));
clks[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_sels, ARRAY_SIZE(eim_sels));
clks[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
@@ -514,6 +531,13 @@ static int imx6_ccm_probe(struct device_d *dev)
clk_set_parent(clks[IMX6QDL_CLK_LVDS1_SEL], clks[IMX6QDL_CLK_SATA_REF_100M]);
+ /*
+ * The gpmi needs 100MHz frequency in the EDO/Sync mode,
+ * We can not get the 100MHz from the pll2_pfd0_352m.
+ * So choose pll2_pfd2_396m as enfc_sel's parent.
+ */
+ clk_set_parent(clks[IMX6QDL_CLK_ENFC_SEL], clks[IMX6QDL_CLK_PLL2_PFD2_396M]);
+
return 0;
}
diff --git a/drivers/mfd/mc13xxx.c b/drivers/mfd/mc13xxx.c
index f6aa92242..a5877dbda 100644
--- a/drivers/mfd/mc13xxx.c
+++ b/drivers/mfd/mc13xxx.c
@@ -40,10 +40,12 @@ struct mc13xxx {
struct spi_device *spi;
};
int revision;
+ int type;
};
struct mc13xxx_devtype {
int (*revision)(struct mc13xxx*);
+ int type;
};
#define to_mc13xxx(a) container_of(a, struct mc13xxx, cdev)
@@ -56,6 +58,12 @@ struct mc13xxx *mc13xxx_get(void)
}
EXPORT_SYMBOL(mc13xxx_get);
+int mc13xxx_type(struct mc13xxx *mc13xxx)
+{
+ return mc13xxx->type;
+}
+EXPORT_SYMBOL(mc13xxx_type);
+
int mc13xxx_revision(struct mc13xxx *mc13xxx)
{
return mc13xxx->revision;
@@ -347,6 +355,7 @@ static int __init mc13xxx_probe(struct device_d *dev)
}
mc_dev->revision = rev;
+ mc_dev->type = devtype->type;
ret = regmap_register_cdev(mc_dev->map, NULL);
if (ret)
@@ -355,19 +364,25 @@ static int __init mc13xxx_probe(struct device_d *dev)
if (mc13xxx_init_callback)
mc13xxx_init_callback(mc_dev);
+ if (of_property_read_bool(dev->device_node, "fsl,mc13xxx-uses-adc"))
+ mc13xxx_adc_probe(dev, mc_dev);
+
return 0;
}
static struct mc13xxx_devtype mc13783_devtype = {
.revision = mc13783_revision,
+ .type = MC13783_TYPE,
};
static struct mc13xxx_devtype mc13892_devtype = {
.revision = mc13892_revision,
+ .type = MC13892_TYPE,
};
static struct mc13xxx_devtype mc34708_devtype = {
.revision = mc34708_revision,
+ .type = MC34708_TYPE,
};
static struct platform_device_id mc13xxx_ids[] = {
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 52fb6d39c..8f87f7b9c 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -170,9 +170,7 @@ static int lpuart_serial_probe(struct device_d *dev)
cdev->linux_console_name = "ttyLP";
- lpuart_setup_with_fifo(lpuart->base,
- clk_get_rate(lpuart->clk),
- 15);
+ lpuart_setup(lpuart->base, clk_get_rate(lpuart->clk));
ret = console_register(cdev);
if (!ret) {
diff --git a/drivers/video/fb.c b/drivers/video/fb.c
index 5e829e832..c9d184d50 100644
--- a/drivers/video/fb.c
+++ b/drivers/video/fb.c
@@ -124,6 +124,9 @@ static int fb_enable_set(struct param_d *param, void *priv)
struct fb_info *info = priv;
int enable;
+ if (!info->mode)
+ return -EINVAL;
+
enable = info->p_enable;
if (enable)
diff --git a/drivers/video/imx-ipu-v3/imx-ldb.c b/drivers/video/imx-ipu-v3/imx-ldb.c
index 33dbade87..9b4524274 100644
--- a/drivers/video/imx-ipu-v3/imx-ldb.c
+++ b/drivers/video/imx-ipu-v3/imx-ldb.c
@@ -347,7 +347,7 @@ static int imx_ldb_probe(struct device_d *dev)
return -EINVAL;
if (dual && i > 0) {
- dev_warn(dev, "dual-channel mode, ignoring second output\n");
+ dev_info(dev, "dual-channel mode, ignoring second output\n");
continue;
}
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index 27fdfd13a..c8a7ccf60 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -160,6 +160,7 @@ static int omap_wdt_probe(struct device_d *dev)
wdev = xzalloc(sizeof(*wdev));
wdev->wdog.set_timeout = omap_wdt_set_timeout;
+ wdev->wdog.hwdev = dev;
wdev->wdt_trgr_pattern = 0x1234;
/* reserve static register mappings */
diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index d3305443d..56e8626cb 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -112,10 +112,12 @@ static int watchdog_register_dev(struct watchdog *wd, const char *name, int id)
int watchdog_register(struct watchdog *wd)
{
struct param_d *p;
- const char *alias;
+ const char *alias = NULL;
int ret = 0;
- alias = of_alias_get(wd->hwdev->device_node);
+ if (wd->hwdev)
+ alias = of_alias_get(wd->hwdev->device_node);
+
if (alias)
ret = watchdog_register_dev(wd, alias, DEVICE_ID_SINGLE);
diff --git a/dts/Bindings/arm/arm,scmi.txt b/dts/Bindings/arm/arm,scmi.txt
new file mode 100644
index 000000000..5f3719ab7
--- /dev/null
+++ b/dts/Bindings/arm/arm,scmi.txt
@@ -0,0 +1,179 @@
+System Control and Management Interface (SCMI) Message Protocol
+----------------------------------------------------------
+
+The SCMI is intended to allow agents such as OSPM to manage various functions
+that are provided by the hardware platform it is running on, including power
+and performance functions.
+
+This binding is intended to define the interface the firmware implementing
+the SCMI as described in ARM document number ARM DUI 0922B ("ARM System Control
+and Management Interface Platform Design Document")[0] provide for OSPM in
+the device tree.
+
+Required properties:
+
+The scmi node with the following properties shall be under the /firmware/ node.
+
+- compatible : shall be "arm,scmi"
+- mboxes: List of phandle and mailbox channel specifiers. It should contain
+ exactly one or two mailboxes, one for transmitting messages("tx")
+ and another optional for receiving the notifications("rx") if
+ supported.
+- shmem : List of phandle pointing to the shared memory(SHM) area as per
+ generic mailbox client binding.
+- #address-cells : should be '1' if the device has sub-nodes, maps to
+ protocol identifier for a given sub-node.
+- #size-cells : should be '0' as 'reg' property doesn't have any size
+ associated with it.
+
+Optional properties:
+
+- mbox-names: shall be "tx" or "rx" depending on mboxes entries.
+
+See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
+about the generic mailbox controller and client driver bindings.
+
+The mailbox is the only permitted method of calling the SCMI firmware.
+Mailbox doorbell is used as a mechanism to alert the presence of a
+messages and/or notification.
+
+Each protocol supported shall have a sub-node with corresponding compatible
+as described in the following sections. If the platform supports dedicated
+communication channel for a particular protocol, the 3 properties namely:
+mboxes, mbox-names and shmem shall be present in the sub-node corresponding
+to that protocol.
+
+Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol
+------------------------------------------------------------
+
+This binding uses the common clock binding[1].
+
+Required properties:
+- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands.
+
+Power domain bindings for the power domains based on SCMI Message Protocol
+------------------------------------------------------------
+
+This binding for the SCMI power domain providers uses the generic power
+domain binding[2].
+
+Required properties:
+ - #power-domain-cells : Should be 1. Contains the device or the power
+ domain ID value used by SCMI commands.
+
+Sensor bindings for the sensors based on SCMI Message Protocol
+--------------------------------------------------------------
+SCMI provides an API to access the various sensors on the SoC.
+
+Required properties:
+- #thermal-sensor-cells: should be set to 1. This property follows the
+ thermal device tree bindings[3].
+
+ Valid cell values are raw identifiers (Sensor ID)
+ as used by the firmware. Refer to platform details
+ for your implementation for the IDs to use.
+
+SRAM and Shared Memory for SCMI
+-------------------------------
+
+A small area of SRAM is reserved for SCMI communication between application
+processors and SCP.
+
+The properties should follow the generic mmio-sram description found in [4]
+
+Each sub-node represents the reserved area for SCMI.
+
+Required sub-node properties:
+- reg : The base offset and size of the reserved area with the SRAM
+- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
+ shared memory
+
+[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/power/power_domain.txt
+[3] Documentation/devicetree/bindings/thermal/thermal.txt
+[4] Documentation/devicetree/bindings/sram/sram.txt
+
+Example:
+
+sram@50000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x50000000 0x0 0x10000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x50000000 0x10000>;
+
+ cpu_scp_lpri: scp-shmem@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x200>;
+ };
+
+ cpu_scp_hpri: scp-shmem@200 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x200 0x200>;
+ };
+};
+
+mailbox@40000000 {
+ ....
+ #mbox-cells = <1>;
+ reg = <0x0 0x40000000 0x0 0x10000>;
+};
+
+firmware {
+
+ ...
+
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&mailbox 0 &mailbox 1>;
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_devpd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi_dvfs: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+ };
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_sensors0: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+};
+
+cpu@0 {
+ ...
+ reg = <0 0>;
+ clocks = <&scmi_dvfs 0>;
+};
+
+hdlcd@7ff60000 {
+ ...
+ reg = <0 0x7ff60000 0 0x1000>;
+ clocks = <&scmi_clk 4>;
+ power-domains = <&scmi_devpd 1>;
+};
+
+thermal-zones {
+ soc_thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <1000>;
+ /* sensor ID */
+ thermal-sensors = <&scmi_sensors0 3>;
+ ...
+ };
+};
diff --git a/dts/Bindings/arm/cpu-enable-method/nuvoton,npcm750-smp b/dts/Bindings/arm/cpu-enable-method/nuvoton,npcm750-smp
new file mode 100644
index 000000000..8e043301e
--- /dev/null
+++ b/dts/Bindings/arm/cpu-enable-method/nuvoton,npcm750-smp
@@ -0,0 +1,42 @@
+=========================================================
+Secondary CPU enable-method "nuvoton,npcm750-smp" binding
+=========================================================
+
+To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
+defined in the "cpus" node.
+
+Enable method name: "nuvoton,npcm750-smp"
+Compatible machines: "nuvoton,npcm750"
+Compatible CPUs: "arm,cortex-a9"
+Related properties: (none)
+
+Note:
+This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
+"nuvoton,npcm750-gcr".
+
+Example:
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "nuvoton,npcm750-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt
index f4a777039..29e1dc5d5 100644
--- a/dts/Bindings/arm/cpus.txt
+++ b/dts/Bindings/arm/cpus.txt
@@ -185,6 +185,7 @@ described below.
"nvidia,tegra186-denver"
"qcom,krait"
"qcom,kryo"
+ "qcom,kryo385"
"qcom,scorpion"
- enable-method
Value type: <stringlist>
@@ -198,6 +199,7 @@ described below.
"actions,s500-smp"
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
+ "allwinner,sun9i-a80-smp"
"amlogic,meson8-smp"
"amlogic,meson8b-smp"
"arm,realview-smp"
diff --git a/dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt
new file mode 100644
index 000000000..10bd35f92
--- /dev/null
+++ b/dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt
@@ -0,0 +1,33 @@
+Hisilicon Hip06 Low Pin Count device
+ Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
+ provides I/O access to some legacy ISA devices.
+ Hip06 is based on arm64 architecture where there is no I/O space. So, the
+ I/O ports here are not CPU addresses, and there is no 'ranges' property in
+ LPC device node.
+
+Required properties:
+- compatible: value should be as follows:
+ (a) "hisilicon,hip06-lpc"
+ (b) "hisilicon,hip07-lpc"
+- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
+- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
+- reg: base memory range where the LPC register set is mapped.
+
+Note:
+ The node name before '@' must be "isa" to represent the binding stick to the
+ ISA/EISA binding specification.
+
+Example:
+
+isa@a01b0000 {
+ compatible = "hisilicon,hip06-lpc";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0x0 0xa01b0000 0x0 0x1000>;
+
+ ipmi0: bt@e4 {
+ compatible = "ipmi-bt";
+ device_type = "ipmi";
+ reg = <0x01 0xe4 0x04>;
+ };
+};
diff --git a/dts/Bindings/arm/hisilicon/hisilicon.txt b/dts/Bindings/arm/hisilicon/hisilicon.txt
index 7111fbc82..199cd36fe 100644
--- a/dts/Bindings/arm/hisilicon/hisilicon.txt
+++ b/dts/Bindings/arm/hisilicon/hisilicon.txt
@@ -75,6 +75,29 @@ Example:
};
-----------------------------------------------------------------------
+Hisilicon Hi3798CV200 Peripheral Controller
+
+The Hi3798CV200 Peripheral Controller controls peripherals, queries
+their status, and configures some functions of peripherals.
+
+Required properties:
+- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
+ and "simple-mfd".
+- reg: Register address and size of Peripheral Controller.
+- #address-cells: Should be 1.
+- #size-cells: Should be 1.
+
+Examples:
+
+ perictrl: peripheral-controller@8a20000 {
+ compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
+ "simple-mfd";
+ reg = <0x8a20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+-----------------------------------------------------------------------
Hisilicon Hi6220 system controller
Required properties:
diff --git a/dts/Bindings/arm/mediatek.txt b/dts/Bindings/arm/mediatek.txt
index 91d517849..7d21ab37c 100644
--- a/dts/Bindings/arm/mediatek.txt
+++ b/dts/Bindings/arm/mediatek.txt
@@ -50,6 +50,15 @@ Supported boards:
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+- Reference board for MT7623a with eMMC:
+ Required root node properties:
+ - compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
+- Reference board for MT7623a with NAND:
+ Required root node properties:
+ - compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623";
+- Reference board for MT7623n with eMMC:
+ Required root node properties:
+ - compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
- Reference board for MT7623n with NAND:
Required root node properties:
- compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
diff --git a/dts/Bindings/arm/mediatek/mediatek,audsys.txt b/dts/Bindings/arm/mediatek/mediatek,audsys.txt
index 9b8f578d5..34a69ba67 100644
--- a/dts/Bindings/arm/mediatek/mediatek,audsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,audsys.txt
@@ -6,6 +6,7 @@ The MediaTek AUDSYS controller provides various clocks to the system.
Required Properties:
- compatible: Should be one of:
+ - "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt7622-audsys", "syscon"
- #clock-cells: Must be 1
@@ -13,10 +14,19 @@ The AUDSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+Required sub-nodes:
+-------
+For common binding part and usage, refer to
+../sonud/mt2701-afe-pcm.txt.
+
Example:
-audsys: audsys@11220000 {
- compatible = "mediatek,mt7622-audsys", "syscon";
- reg = <0 0x11220000 0 0x1000>;
- #clock-cells = <1>;
-};
+ audsys: clock-controller@11220000 {
+ compatible = "mediatek,mt7622-audsys", "syscon";
+ reg = <0 0x11220000 0 0x2000>;
+ #clock-cells = <1>;
+
+ afe: audio-controller {
+ ...
+ };
+ };
diff --git a/dts/Bindings/arm/mediatek/mediatek,ethsys.txt b/dts/Bindings/arm/mediatek/mediatek,ethsys.txt
index 6cc7840ff..8f5335b48 100644
--- a/dts/Bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,ethsys.txt
@@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7622-ethsys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The ethsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
diff --git a/dts/Bindings/arm/mediatek/mediatek,pciesys.txt b/dts/Bindings/arm/mediatek/mediatek,pciesys.txt
index d5d5f1227..7fe5dc609 100644
--- a/dts/Bindings/arm/mediatek/mediatek,pciesys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,pciesys.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-pciesys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The PCIESYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0 0x1a100800 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
diff --git a/dts/Bindings/arm/mediatek/mediatek,ssusbsys.txt b/dts/Bindings/arm/mediatek/mediatek,ssusbsys.txt
index 00760019d..b8184da25 100644
--- a/dts/Bindings/arm/mediatek/mediatek,ssusbsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,ssusbsys.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-ssusbsys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The SSUSBSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
diff --git a/dts/Bindings/arm/npcm/npcm.txt b/dts/Bindings/arm/npcm/npcm.txt
new file mode 100644
index 000000000..2d87d9ece
--- /dev/null
+++ b/dts/Bindings/arm/npcm/npcm.txt
@@ -0,0 +1,6 @@
+NPCM Platforms Device Tree Bindings
+-----------------------------------
+NPCM750 SoC
+Required root node properties:
+ - compatible = "nuvoton,npcm750";
+
diff --git a/dts/Bindings/arm/omap/ctrl.txt b/dts/Bindings/arm/omap/ctrl.txt
index ce8dabf8c..f35b77920 100644
--- a/dts/Bindings/arm/omap/ctrl.txt
+++ b/dts/Bindings/arm/omap/ctrl.txt
@@ -25,6 +25,7 @@ Required properties:
"ti,omap4-scm-padconf-wkup"
"ti,omap5-scm-core"
"ti,omap5-scm-padconf-core"
+ "ti,omap5-scm-wkup-pad-conf"
"ti,dra7-scm-core"
- reg: Contains Control Module register address range
(base address and length)
diff --git a/dts/Bindings/arm/omap/mpu.txt b/dts/Bindings/arm/omap/mpu.txt
index 763695db2..f301e636f 100644
--- a/dts/Bindings/arm/omap/mpu.txt
+++ b/dts/Bindings/arm/omap/mpu.txt
@@ -13,6 +13,13 @@ Required properties:
Optional properties:
- sram: Phandle to the ocmcram node
+am335x and am437x only:
+- pm-sram: Phandles to ocmcram nodes to be used for power management.
+ First should be type 'protect-exec' for the driver to use to copy
+ and run PM functions, second should be regular pool to be used for
+ data region for code. See Documentation/devicetree/bindings/sram/sram.txt
+ for more details.
+
Examples:
- For an OMAP5 SMP system:
@@ -36,3 +43,12 @@ mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
};
+
+- For an AM335x system:
+
+mpu {
+ compatible = "ti,omap3-mpu";
+ ti,hwmods = "mpu";
+ pm-sram = <&pm_sram_code
+ &pm_sram_data>;
+};
diff --git a/dts/Bindings/arm/qcom.txt b/dts/Bindings/arm/qcom.txt
index 0ed4d39d7..ee532e705 100644
--- a/dts/Bindings/arm/qcom.txt
+++ b/dts/Bindings/arm/qcom.txt
@@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings:
msm8996
mdm9615
ipq8074
+ sdm845
The 'board' element must be one of the following strings:
diff --git a/dts/Bindings/arm/rockchip.txt b/dts/Bindings/arm/rockchip.txt
index 326d24bca..1c1d62d03 100644
--- a/dts/Bindings/arm/rockchip.txt
+++ b/dts/Bindings/arm/rockchip.txt
@@ -50,6 +50,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
+- Firefly roc-rk3328-cc board:
+ Required root node properties:
+ - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
@@ -181,10 +185,18 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
+- Rockchip RK3399 Sapphire board standalone:
+ Required root node properties:
+ - compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
+
- Rockchip RK3399 Sapphire Excavator board:
Required root node properties:
- compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
+- Theobroma Systems RK3368-uQ7 Haikou Baseboard:
+ Required root node properties:
+ - compatible = "tsd,rk3368-uq7-haikou", "rockchip,rk3368";
+
- Theobroma Systems RK3399-Q7 Haikou Baseboard:
Required root node properties:
- compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399";
diff --git a/dts/Bindings/arm/samsung/pmu.txt b/dts/Bindings/arm/samsung/pmu.txt
index 779f5614b..16685787d 100644
--- a/dts/Bindings/arm/samsung/pmu.txt
+++ b/dts/Bindings/arm/samsung/pmu.txt
@@ -43,6 +43,12 @@ following properties:
- interrupt-parent: a phandle indicating which interrupt controller
this PMU signals interrupts to.
+
+Optional nodes:
+
+- nodes defining the restart and poweroff syscon children
+
+
Example :
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5250-pmu", "syscon";
diff --git a/dts/Bindings/arm/samsung/samsung-boards.txt b/dts/Bindings/arm/samsung/samsung-boards.txt
index 469ac98ec..14510b215 100644
--- a/dts/Bindings/arm/samsung/samsung-boards.txt
+++ b/dts/Bindings/arm/samsung/samsung-boards.txt
@@ -9,7 +9,11 @@ Required root node properties:
- "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
- "samsung,trats" - for Exynos4210-based Tizen Reference board.
- "samsung,universal_c210" - for Exynos4210-based Samsung board.
+ - "samsung,i9300" - for Exynos4412-based Samsung GT-I9300 board.
+ - "samsung,i9305" - for Exynos4412-based Samsung GT-I9305 board.
+ - "samsung,midas" - for Exynos4412-based Samsung Midas board.
- "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board.
+ - "samsung,n710x" - for Exynos4412-based Samsung GT-N7100/GT-N7105 board.
- "samsung,trats2" - for Exynos4412-based Tizen Reference board.
- "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board.
- "samsung,xyref5260" - for Exynos5260-based Samsung board.
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
index 5c3af7ef0..d3d1df978 100644
--- a/dts/Bindings/arm/shmobile.txt
+++ b/dts/Bindings/arm/shmobile.txt
@@ -39,8 +39,12 @@ SoCs:
compatible = "renesas,r8a7795"
- R-Car M3-W (R8A77960)
compatible = "renesas,r8a7796"
+ - R-Car M3-N (R8A77965)
+ compatible = "renesas,r8a77965"
- R-Car V3M (R8A77970)
compatible = "renesas,r8a77970"
+ - R-Car V3H (R8A77980)
+ compatible = "renesas,r8a77980"
- R-Car D3 (R8A77995)
compatible = "renesas,r8a77995"
@@ -52,11 +56,13 @@ Boards:
- APE6-EVM
compatible = "renesas,ape6evm", "renesas,r8a73a4"
- Atmark Techno Armadillo-800 EVA
- compatible = "renesas,armadillo800eva"
+ compatible = "renesas,armadillo800eva", "renesas,r8a7740"
- Blanche (RTP0RC7792SEB00010S)
compatible = "renesas,blanche", "renesas,r8a7792"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
+ - Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01)
+ compatible = "renesas,condor", "renesas,r8a77980"
- Draak (RTP0RC77995SEB0010S)
compatible = "renesas,draak", "renesas,r8a77995"
- Eagle (RTP0RC77970SEB0010S)
@@ -102,19 +108,25 @@ Boards:
compatible = "renesas,salvator-x", "renesas,r8a7795"
- Salvator-X (RTP0RC7796SIPB0011S)
compatible = "renesas,salvator-x", "renesas,r8a7796"
+ - Salvator-X (RTP0RC7796SIPB0011S (M3N))
+ compatible = "renesas,salvator-x", "renesas,r8a77965"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
compatible = "renesas,salvator-xs", "renesas,r8a7795"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
compatible = "renesas,salvator-xs", "renesas,r8a7796"
+ - Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S)
+ compatible = "renesas,salvator-xs", "renesas,r8a77965"
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
- SK-RZG1E (YR8A77450S000BE)
compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
- SK-RZG1M (YR8A77430S000BE)
compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
- - V3MSK
+ - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
+ compatible = "renesas,stout", "renesas,r8a7790"
+ - V3MSK (Y-ASK-RCAR-V3M-WS10)
compatible = "renesas,v3msk", "renesas,r8a77970"
- - Wheat
+ - Wheat (RTP0RC7792ASKB0000JE)
compatible = "renesas,wheat", "renesas,r8a7792"
diff --git a/dts/Bindings/arm/stm32.txt b/dts/Bindings/arm/stm32.txt
index 05762b08a..6808ed9dd 100644
--- a/dts/Bindings/arm/stm32.txt
+++ b/dts/Bindings/arm/stm32.txt
@@ -7,3 +7,4 @@ using one of the following compatible strings:
st,stm32f469
st,stm32f746
st,stm32h743
+ st,stm32mp157
diff --git a/dts/Bindings/arm/sunxi/smp-sram.txt b/dts/Bindings/arm/sunxi/smp-sram.txt
new file mode 100644
index 000000000..082e6a938
--- /dev/null
+++ b/dts/Bindings/arm/sunxi/smp-sram.txt
@@ -0,0 +1,44 @@
+Allwinner SRAM for smp bringup:
+------------------------------------------------
+
+Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
+primary core (cpu0). Once the core gets powered up it checks if a magic
+value is set at a specific location. If it is then the BROM will jump
+to the software entry address, instead of executing a standard boot.
+
+Therefore a reserved section sub-node has to be added to the mmio-sram
+declaration.
+
+Note that this is separate from the Allwinner SRAM controller found in
+../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to
+any device.
+
+Also there are no "secure-only" properties. The implementation should
+check if this SRAM is usable first.
+
+Required sub-node properties:
+- compatible : depending on the SoC this should be one of:
+ "allwinner,sun9i-a80-smp-sram"
+
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sram.txt
+
+Example:
+
+ sram_b: sram@20000 {
+ /* 256 KiB secure SRAM at 0x20000 */
+ compatible = "mmio-sram";
+ reg = <0x00020000 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00020000 0x40000>;
+
+ smp-sram@1000 {
+ /*
+ * This is checked by BROM to determine if
+ * cpu0 should jump to SMP entry vector
+ */
+ compatible = "allwinner,sun9i-a80-smp-sram";
+ reg = <0x1000 0x8>;
+ };
+ };
diff --git a/dts/Bindings/arm/tegra.txt b/dts/Bindings/arm/tegra.txt
index 7f1411bba..32f62bb70 100644
--- a/dts/Bindings/arm/tegra.txt
+++ b/dts/Bindings/arm/tegra.txt
@@ -9,6 +9,12 @@ following compatible values:
nvidia,tegra20
nvidia,tegra30
+ nvidia,tegra114
+ nvidia,tegra124
+ nvidia,tegra132
+ nvidia,tegra210
+ nvidia,tegra186
+ nvidia,tegra194
Boards
-------------------------------------------
@@ -26,8 +32,18 @@ board-specific compatible values:
nvidia,cardhu
nvidia,cardhu-a02
nvidia,cardhu-a04
+ nvidia,dalmore
nvidia,harmony
+ nvidia,jetson-tk1
+ nvidia,norrin
+ nvidia,p2371-0000
+ nvidia,p2371-2180
+ nvidia,p2571
+ nvidia,p2771-0000
+ nvidia,p2972-0000
+ nvidia,roth
nvidia,seaboard
+ nvidia,tn7
nvidia,ventana
toradex,apalis_t30
toradex,apalis_t30-eval
diff --git a/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt
index 078a58b03..5a3bf7c5a 100644
--- a/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt
+++ b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt
@@ -3,6 +3,7 @@ NVIDIA Tegra Power Management Controller (PMC)
Required properties:
- compatible: Should contain one of the following:
- "nvidia,tegra186-pmc": for Tegra186
+ - "nvidia,tegra194-pmc": for Tegra194
- reg: Must contain an (offset, length) pair of the register set for each
entry in reg-names.
- reg-names: Must include the following entries:
@@ -10,6 +11,7 @@ Required properties:
- "wake"
- "aotag"
- "scratch"
+ - "misc" (Only for Tegra194)
Optional properties:
- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
diff --git a/dts/Bindings/arm/xilinx.txt b/dts/Bindings/arm/xilinx.txt
index 1f7995357..b9043bc35 100644
--- a/dts/Bindings/arm/xilinx.txt
+++ b/dts/Bindings/arm/xilinx.txt
@@ -5,3 +5,59 @@ shall have the following properties.
Required root node properties:
- compatible = "xlnx,zynq-7000";
+
+Additional compatible strings:
+
+- Xilinx internal board cc108
+ "xlnx,zynq-cc108"
+
+- Xilinx internal board zc770 with different FMC cards
+ "xlnx,zynq-zc770-xm010"
+ "xlnx,zynq-zc770-xm011"
+ "xlnx,zynq-zc770-xm012"
+ "xlnx,zynq-zc770-xm013"
+
+- Digilent Zybo Z7 board
+ "digilent,zynq-zybo-z7"
+
+---------------------------------------------------------------
+
+Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings
+
+Boards with ZynqMP SOC based on an ARM Cortex A53 processor
+shall have the following properties.
+
+Required root node properties:
+ - compatible = "xlnx,zynqmp";
+
+
+Additional compatible strings:
+
+- Xilinx internal board zc1232
+ "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232"
+
+- Xilinx internal board zc1254
+ "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254"
+
+- Xilinx internal board zc1275
+ "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275"
+
+- Xilinx internal board zc1751
+ "xlnx,zynqmp-zc1751"
+
+- Xilinx 96boards compatible board zcu100
+ "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100"
+
+- Xilinx evaluation board zcu102
+ "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102"
+ "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102"
+ "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102"
+
+- Xilinx evaluation board zcu104
+ "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104"
+
+- Xilinx evaluation board zcu106
+ "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106"
+
+- Xilinx evaluation board zcu111
+ "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111"
diff --git a/dts/Bindings/ata/ahci-platform.txt b/dts/Bindings/ata/ahci-platform.txt
index c760ecb81..f4006d3c9 100644
--- a/dts/Bindings/ata/ahci-platform.txt
+++ b/dts/Bindings/ata/ahci-platform.txt
@@ -30,6 +30,7 @@ compatible:
Optional properties:
- dma-coherent : Present if dma operations are coherent
- clocks : a list of phandle + clock specifier pairs
+- resets : a list of phandle + reset specifier pairs
- target-supply : regulator for SATA target power
- phys : reference to the SATA PHY node
- phy-names : must be "sata-phy"
diff --git a/dts/Bindings/ata/imx-sata.txt b/dts/Bindings/ata/imx-sata.txt
index a3d14719e..781f88751 100644
--- a/dts/Bindings/ata/imx-sata.txt
+++ b/dts/Bindings/ata/imx-sata.txt
@@ -7,6 +7,7 @@ Required properties:
- compatible : should be one of the following:
- "fsl,imx53-ahci" for i.MX53 SATA controller
- "fsl,imx6q-ahci" for i.MX6Q SATA controller
+ - "fsl,imx6qp-ahci" for i.MX6QP SATA controller
- interrupts : interrupt mapping for SATA IRQ
- reg : registers mapping
- clocks : list of clock specifiers, must contain an entry for each
diff --git a/dts/Bindings/ata/nvidia,tegra124-ahci.txt b/dts/Bindings/ata/nvidia,tegra124-ahci.txt
index 66c83c3e8..12ab2f723 100644
--- a/dts/Bindings/ata/nvidia,tegra124-ahci.txt
+++ b/dts/Bindings/ata/nvidia,tegra124-ahci.txt
@@ -1,9 +1,10 @@
-Tegra124 SoC SATA AHCI controller
+Tegra SoC SATA AHCI controller
Required properties :
-- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise,
- must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
- is tegra132.
+- compatible : Must be one of:
+ - Tegra124 : "nvidia,tegra124-ahci"
+ - Tegra132 : "nvidia,tegra132-ahci", "nvidia,tegra124-ahci"
+ - Tegra210 : "nvidia,tegra210-ahci"
- reg : Should contain 2 entries:
- AHCI register set (SATA BAR5)
- SATA register set
@@ -13,8 +14,6 @@ Required properties :
- clock-names : Must include the following entries:
- sata
- sata-oob
- - cml1
- - pll_e
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
@@ -24,9 +23,22 @@ Required properties :
- phys : Must contain an entry for each entry in phy-names.
See ../phy/phy-bindings.txt for details.
- phy-names : Must include the following entries:
- - sata-phy : XUSB PADCTL SATA PHY
-- hvdd-supply : Defines the SATA HVDD regulator
-- vddio-supply : Defines the SATA VDDIO regulator
-- avdd-supply : Defines the SATA AVDD regulator
-- target-5v-supply : Defines the SATA 5V power regulator
-- target-12v-supply : Defines the SATA 12V power regulator
+ - For Tegra124 and Tegra132:
+ - sata-phy : XUSB PADCTL SATA PHY
+- For Tegra124 and Tegra132:
+ - hvdd-supply : Defines the SATA HVDD regulator
+ - vddio-supply : Defines the SATA VDDIO regulator
+ - avdd-supply : Defines the SATA AVDD regulator
+ - target-5v-supply : Defines the SATA 5V power regulator
+ - target-12v-supply : Defines the SATA 12V power regulator
+
+Optional properties:
+- reg :
+ - AUX register set
+- clock-names :
+ - cml1 :
+ cml1 clock should be defined here if the PHY driver
+ doesn't manage them. If it does, they should not be.
+- phy-names :
+ - For T210:
+ - sata-phy
diff --git a/dts/Bindings/bus/nvidia,tegra20-gmi.txt b/dts/Bindings/bus/nvidia,tegra20-gmi.txt
index 3e21eb822..c1e706217 100644
--- a/dts/Bindings/bus/nvidia,tegra20-gmi.txt
+++ b/dts/Bindings/bus/nvidia,tegra20-gmi.txt
@@ -73,7 +73,7 @@ Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the
controllers with a simple-bus node since they are all connected to the same
chip-select (CS4), in this example external address decoding is provided:
-gmi@70090000 {
+gmi@70009000 {
compatible = "nvidia,tegra20-gmi";
reg = <0x70009000 0x1000>;
#address-cells = <2>;
@@ -84,7 +84,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
-
bus@4,0 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -109,7 +108,7 @@ gmi@70090000 {
Example with one SJA1000 CAN controller connected to the GMI bus
on CS4:
-gmi@70090000 {
+gmi@70009000 {
compatible = "nvidia,tegra20-gmi";
reg = <0x70009000 0x1000>;
#address-cells = <2>;
@@ -120,7 +119,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
-
can@4,0 {
reg = <4 0 0x100>;
nvidia,snor-mux-mode;
diff --git a/dts/Bindings/clock/imx6sll-clock.txt b/dts/Bindings/clock/imx6sll-clock.txt
new file mode 100644
index 000000000..fee849d5f
--- /dev/null
+++ b/dts/Bindings/clock/imx6sll-clock.txt
@@ -0,0 +1,36 @@
+* Clock bindings for Freescale i.MX6 SLL
+
+Required properties:
+- compatible: Should be "fsl,imx6sll-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+- clocks: list of clock specifiers, must contain an entry for each required
+ entry in clock-names
+- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sll-clock.h
+for the full list of i.MX6 SLL clock IDs.
+
+Examples:
+
+#include <dt-bindings/clock/imx6sll-clock.h>
+
+clks: clock-controller@20c4000 {
+ compatible = "fsl,imx6sll-ccm";
+ reg = <0x020c4000 0x4000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
+ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
+};
+
+uart1: serial@2020000 {
+ compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02020000 0x4000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
+ <&clks IMX6SLL_CLK_UART1_SERIAL>;
+ clock-names = "ipg", "per";
+};
diff --git a/dts/Bindings/clock/intc_stratix10.txt b/dts/Bindings/clock/intc_stratix10.txt
new file mode 100644
index 000000000..9f4ec5cb5
--- /dev/null
+++ b/dts/Bindings/clock/intc_stratix10.txt
@@ -0,0 +1,20 @@
+Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be
+ "intel,stratix10-clkmgr"
+
+- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
+
+- #clock-cells : from common clock binding, shall be set to 1.
+
+Example:
+ clkmgr: clock-controller@ffd10000 {
+ compatible = "intel,stratix10-clkmgr";
+ reg = <0xffd10000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.txt b/dts/Bindings/clock/renesas,cpg-mssr.txt
index f1890d077..773a52263 100644
--- a/dts/Bindings/clock/renesas,cpg-mssr.txt
+++ b/dts/Bindings/clock/renesas,cpg-mssr.txt
@@ -22,7 +22,9 @@ Required Properties:
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
+ - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
+ - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -32,8 +34,8 @@ Required Properties:
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
- r8a7795, r8a7796, r8a77970, r8a77995)
- - "extalr" (r8a7795, r8a7796, r8a77970)
+ r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)
+ - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
- #clock-cells: Must be 2
diff --git a/dts/Bindings/clock/rockchip,rk3328-cru.txt b/dts/Bindings/clock/rockchip,rk3328-cru.txt
index e71c675ba..904ae682e 100644
--- a/dts/Bindings/clock/rockchip,rk3328-cru.txt
+++ b/dts/Bindings/clock/rockchip,rk3328-cru.txt
@@ -32,6 +32,7 @@ clock-output-names:
- "clkin_i2s" - external I2S clock - optional,
- "gmac_clkin" - external GMAC clock - optional
- "phy_50m_out" - output clock of the pll in the mac phy
+ - "hdmi_phy" - output clock of the hdmi phy pll - optional
Example: Clock controller node:
diff --git a/dts/Bindings/clock/silabs,si544.txt b/dts/Bindings/clock/silabs,si544.txt
new file mode 100644
index 000000000..b86535b80
--- /dev/null
+++ b/dts/Bindings/clock/silabs,si544.txt
@@ -0,0 +1,25 @@
+Binding for Silicon Labs 544 programmable I2C clock generator.
+
+Reference
+This binding uses the common clock binding[1]. Details about the device can be
+found in the datasheet[2].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Si544 datasheet
+ https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
+
+Required properties:
+ - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according
+ to the speed grade of the chip.
+ - reg: I2C device address.
+ - #clock-cells: From common clock bindings: Shall be 0.
+
+Optional properties:
+ - clock-output-names: From common clock bindings. Recommended to be "si544".
+
+Example:
+ si544: clock-controller@55 {
+ reg = <0x55>;
+ #clock-cells = <0>;
+ compatible = "silabs,si544b";
+ };
diff --git a/dts/Bindings/clock/st,stm32mp1-rcc.txt b/dts/Bindings/clock/st,stm32mp1-rcc.txt
new file mode 100644
index 000000000..fb9495ea5
--- /dev/null
+++ b/dts/Bindings/clock/st,stm32mp1-rcc.txt
@@ -0,0 +1,60 @@
+STMicroelectronics STM32 Peripheral Reset Clock Controller
+==========================================================
+
+The RCC IP is both a reset and a clock controller.
+
+RCC makes also power management (resume/supend and wakeup interrupt).
+
+Please also refer to reset.txt for common reset controller binding usage.
+
+Please also refer to clock-bindings.txt for common clock controller
+binding usage.
+
+
+Required properties:
+- compatible: "st,stm32mp1-rcc", "syscon"
+- reg: should be register base and length as documented in the datasheet
+- #clock-cells: 1, device nodes should specify the clock in their
+ "clocks" property, containing a phandle to the clock device node,
+ an index specifying the clock to use.
+- #reset-cells: Shall be 1
+- interrupts: Should contain a general interrupt line and a interrupt line
+ to the wake-up of processor (CSTOP).
+
+Example:
+ rcc: rcc@50000000 {
+ compatible = "st,stm32mp1-rcc", "syscon";
+ reg = <0x50000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>,
+ <GIC_SPI 145 IRQ_TYPE_NONE>;
+ };
+
+Specifying clocks
+=================
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/stm32mp1-clks.h header and can be used in device
+tree sources.
+
+Specifying softreset control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the reset device node and an index specifying
+which channel to use.
+The index is the bit number within the RCC registers bank, starting from RCC
+base address.
+It is calculated as: index = register_offset / 4 * 32 + bit_offset.
+Where bit_offset is the bit offset within the register.
+
+For example on STM32MP1, for LTDC reset:
+ ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
+ = 0x180 / 4 * 32 + 0 = 3072
+
+The list of valid indices for STM32MP1 is available in:
+include/dt-bindings/reset-controller/stm32mp1-resets.h
+
+This file implements defines like:
+#define LTDC_R 3072
diff --git a/dts/Bindings/clock/sunxi-ccu.txt b/dts/Bindings/clock/sunxi-ccu.txt
index 4ca21c3a6..460ef27b1 100644
--- a/dts/Bindings/clock/sunxi-ccu.txt
+++ b/dts/Bindings/clock/sunxi-ccu.txt
@@ -20,6 +20,7 @@ Required properties :
- "allwinner,sun50i-a64-ccu"
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
+ - "allwinner,sun50i-h6-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
@@ -31,6 +32,9 @@ Required properties :
- #clock-cells : must contain 1
- #reset-cells : must contain 1
+For the main CCU on H6, one more clock is needed:
+- "iosc": the SoC's internal frequency oscillator
+
For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
- "pll-periph": the SoC's peripheral PLL from the main CCU
- "iosc": the SoC's internal frequency oscillator
diff --git a/dts/Bindings/clock/ti/davinci/da8xx-cfgchip.txt b/dts/Bindings/clock/ti/davinci/da8xx-cfgchip.txt
new file mode 100644
index 000000000..1e03dce99
--- /dev/null
+++ b/dts/Bindings/clock/ti/davinci/da8xx-cfgchip.txt
@@ -0,0 +1,93 @@
+Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
+
+TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of
+registers call CFGCHIPn. Some of these registers function as clock
+gates. This document describes the bindings for those clocks.
+
+All of the clock nodes described below must be child nodes of a CFGCHIP node
+(compatible = "ti,da830-cfgchip").
+
+USB PHY clocks
+--------------
+Required properties:
+- compatible: shall be "ti,da830-usb-phy-clocks".
+- #clock-cells: from common clock binding; shall be set to 1.
+- clocks: phandles to the parent clocks corresponding to clock-names
+- clock-names: shall be "fck", "usb_refclkin", "auxclk"
+
+This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
+clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.
+
+eHRPWM Time Base Clock (TBCLK)
+------------------------------
+Required properties:
+- compatible: shall be "ti,da830-tbclksync".
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: phandle to the parent clock
+- clock-names: shall be "fck"
+
+PLL DIV4.5 divider
+------------------
+Required properties:
+- compatible: shall be "ti,da830-div4p5ena".
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: phandle to the parent clock
+- clock-names: shall be "pll0_pllout"
+
+EMIFA clock source (ASYNC1)
+---------------------------
+Required properties:
+- compatible: shall be "ti,da850-async1-clksrc".
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: phandles to the parent clocks corresponding to clock-names
+- clock-names: shall be "pll0_sysclk3", "div4.5"
+
+ASYNC3 clock source
+-------------------
+Required properties:
+- compatible: shall be "ti,da850-async3-clksrc".
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: phandles to the parent clocks corresponding to clock-names
+- clock-names: shall be "pll0_sysclk2", "pll1_sysclk2"
+
+Examples:
+
+ cfgchip: syscon@1417c {
+ compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
+ reg = <0x1417c 0x14>;
+
+ usb_phy_clk: usb-phy-clocks {
+ compatible = "ti,da830-usb-phy-clocks";
+ #clock-cells = <1>;
+ clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;
+ clock-names = "fck", "usb_refclkin", "auxclk";
+ };
+ ehrpwm_tbclk: ehrpwm_tbclk {
+ compatible = "ti,da830-tbclksync";
+ #clock-cells = <0>;
+ clocks = <&psc1 17>;
+ clock-names = "fck";
+ };
+ div4p5_clk: div4.5 {
+ compatible = "ti,da830-div4p5ena";
+ #clock-cells = <0>;
+ clocks = <&pll0_pllout>;
+ clock-names = "pll0_pllout";
+ };
+ async1_clk: async1 {
+ compatible = "ti,da850-async1-clksrc";
+ #clock-cells = <0>;
+ clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
+ clock-names = "pll0_sysclk3", "div4.5";
+ };
+ async3_clk: async3 {
+ compatible = "ti,da850-async3-clksrc";
+ #clock-cells = <0>;
+ clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
+ clock-names = "pll0_sysclk2", "pll1_sysclk2";
+ };
+ };
+
+Also see:
+- Documentation/devicetree/bindings/clock/clock-bindings.txt
+
diff --git a/dts/Bindings/clock/ti/davinci/pll.txt b/dts/Bindings/clock/ti/davinci/pll.txt
new file mode 100644
index 000000000..36998e184
--- /dev/null
+++ b/dts/Bindings/clock/ti/davinci/pll.txt
@@ -0,0 +1,96 @@
+Binding for TI DaVinci PLL Controllers
+
+The PLL provides clocks to most of the components on the SoC. In addition
+to the PLL itself, this controller also contains bypasses, gates, dividers,
+an multiplexers for various clock signals.
+
+Required properties:
+- compatible: shall be one of:
+ - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
+ - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
+- reg: physical base address and size of the controller's register area.
+- clocks: phandles corresponding to the clock names
+- clock-names: names of the clock sources - depends on compatible string
+ - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
+ - for "ti,da850-pll1", shall be "clksrc"
+
+Optional properties:
+- ti,clkmode-square-wave: Indicates that the the board is supplying a square
+ wave input on the OSCIN pin instead of using a crystal oscillator.
+ This property is only valid when compatible = "ti,da850-pll0".
+
+
+Optional child nodes:
+
+pllout
+ Describes the main PLL clock output (before POSTDIV). The node name must
+ be "pllout".
+
+ Required properties:
+ - #clock-cells: shall be 0
+
+sysclk
+ Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
+ domains. The node name must be "sysclk". Consumers of this node should
+ use "n" in "SYSCLKn" as the index parameter for the clock cell.
+
+ Required properties:
+ - #clock-cells: shall be 1
+
+auxclk
+ Describes the AUXCLK output of the PLL. The node name must be "auxclk".
+ This child node is only valid when compatible = "ti,da850-pll0".
+
+ Required properties:
+ - #clock-cells: shall be 0
+
+obsclk
+ Describes the OBSCLK output of the PLL. The node name must be "obsclk".
+
+ Required properties:
+ - #clock-cells: shall be 0
+
+
+Examples:
+
+ pll0: clock-controller@11000 {
+ compatible = "ti,da850-pll0";
+ reg = <0x11000 0x1000>;
+ clocks = <&ref_clk>, <&pll1_sysclk 3>;
+ clock-names = "clksrc", "extclksrc";
+ ti,clkmode-square-wave;
+
+ pll0_pllout: pllout {
+ #clock-cells = <0>;
+ };
+
+ pll0_sysclk: sysclk {
+ #clock-cells = <1>;
+ };
+
+ pll0_auxclk: auxclk {
+ #clock-cells = <0>;
+ };
+
+ pll0_obsclk: obsclk {
+ #clock-cells = <0>;
+ };
+ };
+
+ pll1: clock-controller@21a000 {
+ compatible = "ti,da850-pll1";
+ reg = <0x21a000 0x1000>;
+ clocks = <&ref_clk>;
+ clock-names = "clksrc";
+
+ pll0_sysclk: sysclk {
+ #clock-cells = <1>;
+ };
+
+ pll0_obsclk: obsclk {
+ #clock-cells = <0>;
+ };
+ };
+
+Also see:
+- Documentation/devicetree/bindings/clock/clock-bindings.txt
diff --git a/dts/Bindings/clock/ti/davinci/psc.txt b/dts/Bindings/clock/ti/davinci/psc.txt
new file mode 100644
index 000000000..dae4ad8e1
--- /dev/null
+++ b/dts/Bindings/clock/ti/davinci/psc.txt
@@ -0,0 +1,71 @@
+Binding for TI DaVinci Power Sleep Controller (PSC)
+
+The PSC provides power management, clock gating and reset functionality. It is
+primarily used for clocking.
+
+Required properties:
+- compatible: shall be one of:
+ - "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
+ - "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
+- reg: physical base address and size of the controller's register area
+- #clock-cells: from common clock binding; shall be set to 1
+- #power-domain-cells: from generic power domain binding; shall be set to 1.
+- clocks: phandles to clocks corresponding to the clock-names property
+- clock-names: list of parent clock names - depends on compatible value
+ - for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
+ "pll0_sysclk4", "pll0_sysclk6", "async1"
+ - for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
+
+Optional properties:
+- #reset-cells: from reset binding; shall be set to 1 - only applicable when
+ at least one local domain provides a local reset.
+
+Consumers:
+
+ Clock, power domain and reset consumers shall use the local power domain
+ module ID (LPSC) as the index corresponding to the clock cell. Refer to
+ the device-specific datasheet to find these numbers. NB: Most local
+ domains only provide a clock/power domain and not a reset.
+
+Examples:
+
+ psc0: clock-controller@10000 {
+ compatible = "ti,da850-psc0";
+ reg = <0x10000 0x1000>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
+ <&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>;
+ clock_names = "pll0_sysclk1", "pll0_sysclk2",
+ "pll0_sysclk4", "pll0_sysclk6", "async1";
+ };
+ psc1: clock-controller@227000 {
+ compatible = "ti,da850-psc1";
+ reg = <0x227000 0x1000>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>;
+ clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3";
+ };
+
+ /* consumer */
+ dsp: dsp@11800000 {
+ compatible = "ti,da850-dsp";
+ reg = <0x11800000 0x40000>,
+ <0x11e00000 0x8000>,
+ <0x11f00000 0x8000>,
+ <0x01c14044 0x4>,
+ <0x01c14174 0x8>;
+ reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
+ interrupt-parent = <&intc>;
+ interrupts = <28>;
+ clocks = <&psc0 15>;
+ power-domains = <&psc0 15>;
+ resets = <&psc0 15>;
+ };
+
+Also see:
+- Documentation/devicetree/bindings/clock/clock-bindings.txt
+- Documentation/devicetree/bindings/power/power_domain.txt
+- Documentation/devicetree/bindings/reset/reset.txt
diff --git a/dts/Bindings/clock/ti/divider.txt b/dts/Bindings/clock/ti/divider.txt
index 35a6f5c7e..9b13b3297 100644
--- a/dts/Bindings/clock/ti/divider.txt
+++ b/dts/Bindings/clock/ti/divider.txt
@@ -75,6 +75,9 @@ Optional properties:
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
see [2]
- ti,set-rate-parent : clk_set_rate is propagated to parent
+- ti,latch-bit : latch the divider value to HW, only needed if the register
+ access requires this. As an example dra76x DPLL_GMAC H14 divider implements
+ such behavior.
Examples:
dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
diff --git a/dts/Bindings/clock/ti/mux.txt b/dts/Bindings/clock/ti/mux.txt
index 2d0d170f8..eec8994b9 100644
--- a/dts/Bindings/clock/ti/mux.txt
+++ b/dts/Bindings/clock/ti/mux.txt
@@ -48,6 +48,9 @@ Optional properties:
zero
- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
not supported by the composite-mux-clock subtype
+- ti,latch-bit : latch the mux value to HW, only needed if the register
+ access requires this. As an example, dra7x DPLL_GMAC H14 muxing
+ implements such behavior.
Examples:
diff --git a/dts/Bindings/connector/samsung,usb-connector-11pin.txt b/dts/Bindings/connector/samsung,usb-connector-11pin.txt
new file mode 100644
index 000000000..22256e295
--- /dev/null
+++ b/dts/Bindings/connector/samsung,usb-connector-11pin.txt
@@ -0,0 +1,49 @@
+Samsung micro-USB 11-pin connector
+==================================
+
+Samsung micro-USB 11-pin connector is an extension of micro-USB connector.
+It is present in multiple Samsung mobile devices.
+It has additional pins to route MHL traffic simultanously with USB.
+
+The bindings are superset of usb-connector bindings for micro-USB connector[1].
+
+Required properties:
+- compatible: must be: "samsung,usb-connector-11pin", "usb-b-connector",
+- type: must be "micro".
+
+Required nodes:
+- any data bus to the connector should be modeled using the OF graph bindings
+ specified in bindings/graph.txt, unless the bus is between parent node and
+ the connector. Since single connector can have multpile data buses every bus
+ has assigned OF graph port number as follows:
+ 0: High Speed (HS),
+ 3: Mobile High-Definition Link (MHL), specific to 11-pin Samsung micro-USB.
+
+[1]: bindings/connector/usb-connector.txt
+
+Example
+-------
+
+Micro-USB connector with HS lines routed via controller (MUIC) and MHL lines
+connected to HDMI-MHL bridge (sii8620):
+
+muic-max77843@66 {
+ ...
+ usb_con: connector {
+ compatible = "samsung,usb-connector-11pin", "usb-b-connector";
+ label = "micro-USB";
+ type = "micro";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@3 {
+ reg = <3>;
+ usb_con_mhl: endpoint {
+ remote-endpoint = <&sii8620_mhl>;
+ };
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/connector/usb-connector.txt b/dts/Bindings/connector/usb-connector.txt
new file mode 100644
index 000000000..e1463f14a
--- /dev/null
+++ b/dts/Bindings/connector/usb-connector.txt
@@ -0,0 +1,75 @@
+USB Connector
+=============
+
+USB connector node represents physical USB connector. It should be
+a child of USB interface controller.
+
+Required properties:
+- compatible: describes type of the connector, must be one of:
+ "usb-a-connector",
+ "usb-b-connector",
+ "usb-c-connector".
+
+Optional properties:
+- label: symbolic name for the connector,
+- type: size of the connector, should be specified in case of USB-A, USB-B
+ non-fullsize connectors: "mini", "micro".
+
+Required nodes:
+- any data bus to the connector should be modeled using the OF graph bindings
+ specified in bindings/graph.txt, unless the bus is between parent node and
+ the connector. Since single connector can have multpile data buses every bus
+ has assigned OF graph port number as follows:
+ 0: High Speed (HS), present in all connectors,
+ 1: Super Speed (SS), present in SS capable connectors,
+ 2: Sideband use (SBU), present in USB-C.
+
+Examples
+--------
+
+1. Micro-USB connector with HS lines routed via controller (MUIC):
+
+muic-max77843@66 {
+ ...
+ usb_con: connector {
+ compatible = "usb-b-connector";
+ label = "micro-USB";
+ type = "micro";
+ };
+};
+
+2. USB-C connector attached to CC controller (s2mm005), HS lines routed
+to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort.
+DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
+
+ccic: s2mm005@33 {
+ ...
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usb_con_hs: endpoint {
+ remote-endpoint = <&max77865_usbc_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ usb_con_ss: endpoint {
+ remote-endpoint = <&usbdrd_phy_ss>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ usb_con_sbu: endpoint {
+ remote-endpoint = <&dp_aux>;
+ };
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/cpufreq/cpufreq-dt.txt b/dts/Bindings/cpufreq/cpufreq-dt.txt
index dd3929e85..332aed8f4 100644
--- a/dts/Bindings/cpufreq/cpufreq-dt.txt
+++ b/dts/Bindings/cpufreq/cpufreq-dt.txt
@@ -18,8 +18,6 @@ Optional properties:
in unit of nanoseconds.
- voltage-tolerance: Specify the CPU voltage tolerance in percentage.
- #cooling-cells:
-- cooling-min-level:
-- cooling-max-level:
Please refer to Documentation/devicetree/bindings/thermal/thermal.txt.
Examples:
@@ -40,8 +38,6 @@ cpus {
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <2>;
};
cpu@1 {
diff --git a/dts/Bindings/cpufreq/cpufreq-mediatek.txt b/dts/Bindings/cpufreq/cpufreq-mediatek.txt
index f6403089e..d36f07e0a 100644
--- a/dts/Bindings/cpufreq/cpufreq-mediatek.txt
+++ b/dts/Bindings/cpufreq/cpufreq-mediatek.txt
@@ -21,8 +21,6 @@ Optional properties:
flow is handled by hardware, hence no software "voltage tracking" is
needed.
- #cooling-cells:
-- cooling-min-level:
-- cooling-max-level:
Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
for detail.
@@ -67,8 +65,6 @@ Example 1 (MT7623 SoC):
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <7>;
};
cpu@1 {
device_type = "cpu";
diff --git a/dts/Bindings/cris/axis.txt b/dts/Bindings/cris/axis.txt
deleted file mode 100644
index d209ca2a4..000000000
--- a/dts/Bindings/cris/axis.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-Axis Communications AB
-ARTPEC series SoC Device Tree Bindings
-
-
-CRISv32 based SoCs are ETRAX FS and ARTPEC-3:
-
- - compatible = "axis,crisv32";
-
-
diff --git a/dts/Bindings/cris/boards.txt b/dts/Bindings/cris/boards.txt
deleted file mode 100644
index 533dd273c..000000000
--- a/dts/Bindings/cris/boards.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-Boards based on the CRIS SoCs:
-
-Required root node properties:
- - compatible = should be one or more of the following:
- - "axis,dev88" - for Axis devboard 88 with ETRAX FS
-
-Optional:
-
diff --git a/dts/Bindings/crypto/arm-cryptocell.txt b/dts/Bindings/crypto/arm-cryptocell.txt
index cec8d5d74..c2598ab27 100644
--- a/dts/Bindings/crypto/arm-cryptocell.txt
+++ b/dts/Bindings/crypto/arm-cryptocell.txt
@@ -1,7 +1,8 @@
Arm TrustZone CryptoCell cryptographic engine
Required properties:
-- compatible: Should be "arm,cryptocell-712-ree".
+- compatible: Should be one of: "arm,cryptocell-712-ree",
+ "arm,cryptocell-710-ree" or "arm,cryptocell-630p-ree".
- reg: Base physical address of the engine and length of memory mapped region.
- interrupts: Interrupt number for the device.
diff --git a/dts/Bindings/crypto/fsl-sec4.txt b/dts/Bindings/crypto/fsl-sec4.txt
index 76aec8a37..3c1f3a229 100644
--- a/dts/Bindings/crypto/fsl-sec4.txt
+++ b/dts/Bindings/crypto/fsl-sec4.txt
@@ -415,12 +415,27 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
value type: <u32>
Definition: LP register offset. default it is 0x34.
+ - clocks
+ Usage: optional, required if SNVS LP RTC requires explicit
+ enablement of clocks
+ Value type: <prop_encoded-array>
+ Definition: a clock specifier describing the clock required for
+ enabling and disabling SNVS LP RTC.
+
+ - clock-names
+ Usage: optional, required if SNVS LP RTC requires explicit
+ enablement of clocks
+ Value type: <string>
+ Definition: clock name string should be "snvs-rtc".
+
EXAMPLE
sec_mon_rtc_lp@1 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
interrupts = <93 2>;
regmap = <&snvs>;
offset = <0x34>;
+ clocks = <&clks IMX7D_SNVS_CLK>;
+ clock-names = "snvs-rtc";
};
=====================================================================
@@ -543,6 +558,8 @@ FULL EXAMPLE
regmap = <&sec_mon>;
offset = <0x34>;
interrupts = <93 2>;
+ clocks = <&clks IMX7D_SNVS_CLK>;
+ clock-names = "snvs-rtc";
};
snvs-pwrkey@020cc000 {
diff --git a/dts/Bindings/crypto/inside-secure-safexcel.txt b/dts/Bindings/crypto/inside-secure-safexcel.txt
index 30c3ce6b5..5dba55cdf 100644
--- a/dts/Bindings/crypto/inside-secure-safexcel.txt
+++ b/dts/Bindings/crypto/inside-secure-safexcel.txt
@@ -8,7 +8,11 @@ Required properties:
- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
Optional properties:
-- clocks: Reference to the crypto engine clock.
+- clocks: Reference to the crypto engine clocks, the second clock is
+ needed for the Armada 7K/8K SoCs.
+- clock-names: mandatory if there is a second clock, in this case the
+ name must be "core" for the first clock and "reg" for
+ the second one.
Example:
diff --git a/dts/Bindings/display/bridge/renesas,lvds.txt b/dts/Bindings/display/bridge/renesas,lvds.txt
new file mode 100644
index 000000000..4f0ab3ed3
--- /dev/null
+++ b/dts/Bindings/display/bridge/renesas,lvds.txt
@@ -0,0 +1,58 @@
+Renesas R-Car LVDS Encoder
+==========================
+
+These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
+Gen2, R-Car Gen3 and RZ/G SoCs.
+
+Required properties:
+
+- compatible : Shall contain one of
+ - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
+ - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
+ - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
+ - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
+ - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders
+ - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders
+ - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders
+ - "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders
+
+- reg: Base address and length for the memory-mapped registers
+- clocks: A phandle + clock-specifier pair for the functional clock
+- resets: A phandle + reset specifier for the module reset
+
+Required nodes:
+
+The LVDS encoder has two video ports. Their connections are modelled using the
+OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+
+- Video port 0 corresponds to the parallel RGB input
+- Video port 1 corresponds to the LVDS output
+
+Each port shall have a single endpoint.
+
+
+Example:
+
+ lvds0: lvds@feb90000 {
+ compatible = "renesas,r8a7790-lvds";
+ reg = <0 0xfeb90000 0 0x1c>;
+ clocks = <&cpg CPG_MOD 726>;
+ resets = <&cpg 726>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds0_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/bridge/ti,ths8135.txt b/dts/Bindings/display/bridge/ti,ths813x.txt
index 6ec1a880a..df3d7c1ac 100644
--- a/dts/Bindings/display/bridge/ti,ths8135.txt
+++ b/dts/Bindings/display/bridge/ti,ths813x.txt
@@ -1,11 +1,16 @@
-THS8135 Video DAC
------------------
+THS8134 and THS8135 Video DAC
+-----------------------------
-This is the binding for Texas Instruments THS8135 Video DAC bridge.
+This is the binding for Texas Instruments THS8134, THS8134A, THS8134B and
+THS8135 Video DAC bridges.
Required properties:
-- compatible: Must be "ti,ths8135"
+- compatible: Must be one of
+ "ti,ths8134"
+ "ti,ths8134a," "ti,ths8134"
+ "ti,ths8134b", "ti,ths8134"
+ "ti,ths8135"
Required nodes:
diff --git a/dts/Bindings/display/connector/dvi-connector.txt b/dts/Bindings/display/connector/dvi-connector.txt
index fc53f7c60..207e42e9e 100644
--- a/dts/Bindings/display/connector/dvi-connector.txt
+++ b/dts/Bindings/display/connector/dvi-connector.txt
@@ -10,6 +10,7 @@ Optional properties:
- analog: the connector has DVI analog pins
- digital: the connector has DVI digital pins
- dual-link: the connector has pins for DVI dual-link
+- hpd-gpios: HPD GPIO number
Required nodes:
- Video port for DVI input
diff --git a/dts/Bindings/display/etnaviv/etnaviv-drm.txt b/dts/Bindings/display/etnaviv/etnaviv-drm.txt
index 05176f1ae..8def11b16 100644
--- a/dts/Bindings/display/etnaviv/etnaviv-drm.txt
+++ b/dts/Bindings/display/etnaviv/etnaviv-drm.txt
@@ -1,23 +1,3 @@
-Etnaviv DRM master device
-=========================
-
-The Etnaviv DRM master device is a virtual device needed to list all
-Vivante GPU cores that comprise the GPU subsystem.
-
-Required properties:
-- compatible: Should be one of
- "fsl,imx-gpu-subsystem"
- "marvell,dove-gpu-subsystem"
-- cores: Should contain a list of phandles pointing to Vivante GPU devices
-
-example:
-
-gpu-subsystem {
- compatible = "fsl,imx-gpu-subsystem";
- cores = <&gpu_2d>, <&gpu_3d>;
-};
-
-
Vivante GPU core devices
========================
@@ -32,7 +12,9 @@ Required properties:
- clocks: should contain one clock for entry in clock-names
see Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names:
- - "bus": AXI/register clock
+ - "bus": AXI/master interface clock
+ - "reg": AHB/slave interface clock
+ (only required if GPU can gate slave interface independently)
- "core": GPU core clock
- "shader": Shader clock (only required if GPU has feature PIPE_3D)
diff --git a/dts/Bindings/display/msm/dsi.txt b/dts/Bindings/display/msm/dsi.txt
index a6671bd2c..518e9cdf0 100644
--- a/dts/Bindings/display/msm/dsi.txt
+++ b/dts/Bindings/display/msm/dsi.txt
@@ -7,8 +7,6 @@ Required properties:
- reg: Physical base address and length of the registers of controller
- reg-names: The names of register regions. The following regions are required:
* "dsi_ctrl"
-- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
- be 0 or 1, since we have 2 DSI controllers at most for now.
- interrupts: The interrupt signal from the DSI block.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: Phandles to device clocks.
@@ -22,6 +20,8 @@ Required properties:
* "core"
For DSIv2, we need an additional clock:
* "src"
+ For DSI6G v2.0 onwards, we need also need the clock:
+ * "byte_intf"
- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
by a DSI PHY block. See [1] for details on clock bindings.
@@ -88,21 +88,35 @@ Required properties:
* "qcom,dsi-phy-28nm-lp"
* "qcom,dsi-phy-20nm"
* "qcom,dsi-phy-28nm-8960"
-- reg: Physical base address and length of the registers of PLL, PHY and PHY
- regulator
+ * "qcom,dsi-phy-14nm"
+ * "qcom,dsi-phy-10nm"
+- reg: Physical base address and length of the registers of PLL, PHY. Some
+ revisions require the PHY regulator base address, whereas others require the
+ PHY lane base address. See below for each PHY revision.
- reg-names: The names of register regions. The following regions are required:
+ For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
* "dsi_pll"
* "dsi_phy"
* "dsi_phy_regulator"
+ For DSI 14nm and 10nm PHYs:
+ * "dsi_pll"
+ * "dsi_phy"
+ * "dsi_phy_lane"
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
-- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
- be 0 or 1, since we have 2 DSI PHYs at most for now.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
- clock-names: the following clocks are required:
* "iface"
+ For 28nm HPM/LP, 28nm 8960 PHYs:
+- vddio-supply: phandle to vdd-io regulator device node
+ For 20nm PHY:
- vddio-supply: phandle to vdd-io regulator device node
+- vcca-supply: phandle to vcca regulator device node
+ For 14nm PHY:
+- vcca-supply: phandle to vcca regulator device node
+ For 10nm PHY:
+- vdds-supply: phandle to vdds regulator device node
Optional properties:
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
diff --git a/dts/Bindings/display/panel/arm,versatile-tft-panel.txt b/dts/Bindings/display/panel/arm,versatile-tft-panel.txt
new file mode 100644
index 000000000..248141c3c
--- /dev/null
+++ b/dts/Bindings/display/panel/arm,versatile-tft-panel.txt
@@ -0,0 +1,31 @@
+ARM Versatile TFT Panels
+
+These panels are connected to the daughterboards found on the
+ARM Versatile reference designs.
+
+This device node must appear as a child to a "syscon"-compatible
+node.
+
+Required properties:
+- compatible: should be "arm,versatile-tft-panel"
+
+Required subnodes:
+- port: see display/panel/panel-common.txt, graph.txt
+
+
+Example:
+
+sysreg@0 {
+ compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
+ reg = <0x00000 0x1000>;
+
+ panel: display@0 {
+ compatible = "arm,versatile-tft-panel";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&foo>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/display/panel/auo,g104sn02.txt b/dts/Bindings/display/panel/auo,g104sn02.txt
new file mode 100644
index 000000000..85626edf6
--- /dev/null
+++ b/dts/Bindings/display/panel/auo,g104sn02.txt
@@ -0,0 +1,12 @@
+AU Optronics Corporation 10.4" (800x600) color TFT LCD panel
+
+Required properties:
+- compatible: should be "auo,g104sn02"
+- power-supply: as specified in the base binding
+
+Optional properties:
+- backlight: as specified in the base binding
+- enable-gpios: as specified in the base binding
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/display/panel/display-timing.txt b/dts/Bindings/display/panel/display-timing.txt
index 58fa3e484..78222ced1 100644
--- a/dts/Bindings/display/panel/display-timing.txt
+++ b/dts/Bindings/display/panel/display-timing.txt
@@ -80,6 +80,11 @@ The parameters are defined as:
| | v | | |
+----------+-------------------------------------+----------+-------+
+Note: In addition to being used as subnode(s) of display-timings, the timing
+ subnode may also be used on its own. This is appropriate if only one mode
+ need be conveyed. In this case, the node should be named 'panel-timing'.
+
+
Example:
display-timings {
diff --git a/dts/Bindings/display/panel/koe,tx31d200vm0baa.txt b/dts/Bindings/display/panel/koe,tx31d200vm0baa.txt
new file mode 100644
index 000000000..6a036ede3
--- /dev/null
+++ b/dts/Bindings/display/panel/koe,tx31d200vm0baa.txt
@@ -0,0 +1,25 @@
+Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
+
+Required properties:
+- compatible: should be "koe,tx31d200vm0baa"
+
+Optional properties:
+- backlight: phandle of the backlight device attached to the panel
+
+Optional nodes:
+- Video port for LVDS panel input.
+
+Example:
+ panel {
+ compatible = "koe,tx31d200vm0baa";
+ backlight = <&backlight_lvds>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
diff --git a/dts/Bindings/display/panel/orisetech,otm8009a.txt b/dts/Bindings/display/panel/orisetech,otm8009a.txt
index 6862028e7..203b03eef 100644
--- a/dts/Bindings/display/panel/orisetech,otm8009a.txt
+++ b/dts/Bindings/display/panel/orisetech,otm8009a.txt
@@ -9,6 +9,7 @@ Required properties:
Optional properties:
- reset-gpios: a GPIO spec for the reset pin (active low).
+ - power-supply: phandle of the regulator that provides the supply voltage.
Example:
&dsi {
@@ -17,5 +18,6 @@ Example:
compatible = "orisetech,otm8009a";
reg = <0>;
reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
+ power-supply = <&v1v8>;
};
};
diff --git a/dts/Bindings/display/panel/raydium,rm68200.txt b/dts/Bindings/display/panel/raydium,rm68200.txt
new file mode 100644
index 000000000..cbb79ef3b
--- /dev/null
+++ b/dts/Bindings/display/panel/raydium,rm68200.txt
@@ -0,0 +1,25 @@
+Raydium Semiconductor Corporation RM68200 5.5" 720p MIPI-DSI TFT LCD panel
+
+The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD
+panel connected using a MIPI-DSI video interface.
+
+Required properties:
+ - compatible: "raydium,rm68200"
+ - reg: the virtual channel number of a DSI peripheral
+
+Optional properties:
+ - reset-gpios: a GPIO spec for the reset pin (active low).
+ - power-supply: phandle of the regulator that provides the supply voltage.
+ - backlight: phandle of the backlight device attached to the panel.
+
+Example:
+&dsi {
+ ...
+ panel@0 {
+ compatible = "raydium,rm68200";
+ reg = <0>;
+ reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
+ power-supply = <&v1v8>;
+ backlight = <&pwm_backlight>;
+ };
+};
diff --git a/dts/Bindings/display/panel/simple-panel.txt b/dts/Bindings/display/panel/simple-panel.txt
index 16d8ff088..45a457ad3 100644
--- a/dts/Bindings/display/panel/simple-panel.txt
+++ b/dts/Bindings/display/panel/simple-panel.txt
@@ -1,4 +1,8 @@
Simple display panel
+====================
+
+panel node
+----------
Required properties:
- power-supply: See panel-common.txt
diff --git a/dts/Bindings/display/renesas,du.txt b/dts/Bindings/display/renesas,du.txt
index cd48aba3b..c9cd17f99 100644
--- a/dts/Bindings/display/renesas,du.txt
+++ b/dts/Bindings/display/renesas,du.txt
@@ -13,13 +13,10 @@ Required Properties:
- "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
- "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
- "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
+ - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
+ - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU
- - reg: A list of base address and length of each memory resource, one for
- each entry in the reg-names property.
- - reg-names: Name of the memory resources. The DU requires one memory
- resource for the DU core (named "du") and one memory resource for each
- LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical
- index).
+ - reg: the memory-mapped I/O registers base address and length
- interrupt-parent: phandle of the parent interrupt controller.
- interrupts: Interrupt specifiers for the DU interrupts.
@@ -29,14 +26,13 @@ Required Properties:
- clock-names: Name of the clocks. This property is model-dependent.
- R8A7779 uses a single functional clock. The clock doesn't need to be
named.
- - All other DU instances use one functional clock per channel and one
- clock per LVDS encoder (if available). The functional clocks must be
- named "du.x" with "x" being the channel numerical index. The LVDS clocks
- must be named "lvds.x" with "x" being the LVDS encoder numerical index.
- - In addition to the functional and encoder clocks, all DU versions also
- support externally supplied pixel clocks. Those clocks are optional.
- When supplied they must be named "dclkin.x" with "x" being the input
- clock numerical index.
+ - All other DU instances use one functional clock per channel The
+ functional clocks must be named "du.x" with "x" being the channel
+ numerical index.
+ - In addition to the functional clocks, all DU versions also support
+ externally supplied pixel clocks. Those clocks are optional. When
+ supplied they must be named "dclkin.x" with "x" being the input clock
+ numerical index.
- vsps: A list of phandle and channel index tuples to the VSPs that handle
the memory interfaces for the DU channels. The phandle identifies the VSP
@@ -63,15 +59,15 @@ corresponding to each DU output.
R8A7794 (R-Car E2) DPAD 0 DPAD 1 - -
R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0
R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
+ R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - -
+ R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 -
Example: R8A7795 (R-Car H3) ES2.0 DU
du: display@feb00000 {
compatible = "renesas,du-r8a7795";
- reg = <0 0xfeb00000 0 0x80000>,
- <0 0xfeb90000 0 0x14>;
- reg-names = "du", "lvds.0";
+ reg = <0 0xfeb00000 0 0x80000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
@@ -79,9 +75,8 @@ Example: R8A7795 (R-Car H3) ES2.0 DU
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
- <&cpg CPG_MOD 721>,
- <&cpg CPG_MOD 727>;
- clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
+ <&cpg CPG_MOD 721>;
+ clock-names = "du.0", "du.1", "du.2", "du.3";
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
ports {
diff --git a/dts/Bindings/display/rockchip/cdn-dp-rockchip.txt b/dts/Bindings/display/rockchip/cdn-dp-rockchip.txt
new file mode 100644
index 000000000..8df7d2e39
--- /dev/null
+++ b/dts/Bindings/display/rockchip/cdn-dp-rockchip.txt
@@ -0,0 +1,74 @@
+Rockchip RK3399 specific extensions to the cdn Display Port
+================================
+
+Required properties:
+- compatible: must be "rockchip,rk3399-cdn-dp"
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+
+- clock-names: from common clock binding:
+ Required elements: "core-clk" "pclk" "spdif" "grf"
+
+- resets : a list of phandle + reset specifier pairs
+- reset-names : string of reset names
+ Required elements: "apb", "core", "dptx", "spdif"
+- power-domains : power-domain property defined with a phandle
+ to respective power domain.
+- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
+- assigned-clock-rates : the DP core clk frequency, shall be: 100000000
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port nodes with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+ contained 2 endpoints, connecting to the output of vop.
+
+- phys: from general PHY binding: the phandle for the PHY device.
+
+- extcon: extcon specifier for the Power Delivery
+
+- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF
+
+-------------------------------------------------------------------------------
+
+Example:
+ cdn_dp: dp@fec00000 {
+ compatible = "rockchip,rk3399-cdn-dp";
+ reg = <0x0 0xfec00000 0x0 0x100000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
+ <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
+ clock-names = "core-clk", "pclk", "spdif", "grf";
+ assigned-clocks = <&cru SCLK_DP_CORE>;
+ assigned-clock-rates = <100000000>;
+ power-domains = <&power RK3399_PD_HDCP>;
+ phys = <&tcphy0_dp>, <&tcphy1_dp>;
+ resets = <&cru SRST_DPTX_SPDIF_REC>;
+ reset-names = "spdif";
+ extcon = <&fusb0>, <&fusb1>;
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dp_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_dp>;
+ };
+
+ dp_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_dp>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/st,stm32-ltdc.txt b/dts/Bindings/display/st,stm32-ltdc.txt
index 029252253..3eb1b48b4 100644
--- a/dts/Bindings/display/st,stm32-ltdc.txt
+++ b/dts/Bindings/display/st,stm32-ltdc.txt
@@ -98,7 +98,7 @@ Example 2: DSI panel
compatible = "st,stm32-dsi";
reg = <0x40016c00 0x800>;
clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
- clock-names = "ref", "pclk";
+ clock-names = "pclk", "ref";
resets = <&rcc STM32F4_APB2_RESET(DSI)>;
reset-names = "apb";
diff --git a/dts/Bindings/display/sunxi/sun4i-drm.txt b/dts/Bindings/display/sunxi/sun4i-drm.txt
index cd626ee11..3346c1e2a 100644
--- a/dts/Bindings/display/sunxi/sun4i-drm.txt
+++ b/dts/Bindings/display/sunxi/sun4i-drm.txt
@@ -64,6 +64,56 @@ Required properties:
first port should be the input endpoint. The second should be the
output, usually to an HDMI connector.
+DWC HDMI TX Encoder
+-------------------
+
+The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+with Allwinner's own PHY IP. It supports audio and video outputs and CEC.
+
+These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
+Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
+following device-specific properties.
+
+Required properties:
+
+ - compatible: value must be one of:
+ * "allwinner,sun8i-a83t-dw-hdmi"
+ - reg: base address and size of memory-mapped region
+ - reg-io-width: See dw_hdmi.txt. Shall be 1.
+ - interrupts: HDMI interrupt number
+ - clocks: phandles to the clocks feeding the HDMI encoder
+ * iahb: the HDMI bus clock
+ * isfr: the HDMI register clock
+ * tmds: TMDS clock
+ - clock-names: the clock names mentioned above
+ - resets: phandle to the reset controller
+ - reset-names: must be "ctrl"
+ - phys: phandle to the DWC HDMI PHY
+ - phy-names: must be "phy"
+
+ - ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoint. The second should be the
+ output, usually to an HDMI connector.
+
+DWC HDMI PHY
+------------
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun8i-a83t-hdmi-phy
+ * allwinner,sun8i-h3-hdmi-phy
+ - reg: base address and size of memory-mapped region
+ - clocks: phandles to the clocks feeding the HDMI PHY
+ * bus: the HDMI PHY interface clock
+ * mod: the HDMI PHY module clock
+ - clock-names: the clock names mentioned above
+ - resets: phandle to the reset controller driving the PHY
+ - reset-names: must be "phy"
+
+H3 HDMI PHY requires additional clock:
+ - pll-0: parent of phy clock
+
TV Encoder
----------
@@ -94,24 +144,29 @@ Required properties:
* allwinner,sun7i-a20-tcon
* allwinner,sun8i-a33-tcon
* allwinner,sun8i-a83t-tcon-lcd
+ * allwinner,sun8i-a83t-tcon-tv
* allwinner,sun8i-v3s-tcon
+ * allwinner,sun9i-a80-tcon-lcd
+ * allwinner,sun9i-a80-tcon-tv
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- - clocks: phandles to the clocks feeding the TCON. Three are needed:
+ - clocks: phandles to the clocks feeding the TCON.
- 'ahb': the interface clocks
- - 'tcon-ch0': The clock driving the TCON channel 0
+ - 'tcon-ch0': The clock driving the TCON channel 0, if supported
- resets: phandles to the reset controllers driving the encoder
- - "lcd": the reset line for the TCON channel 0
+ - "lcd": the reset line for the TCON
+ - "edp": the reset line for the eDP block (A80 only)
- clock-names: the clock names mentioned above
- reset-names: the reset names mentioned above
- - clock-output-names: Name of the pixel clock created
+ - clock-output-names: Name of the pixel clock created, if TCON supports
+ channel 0.
- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoint, the second one the output
- The output may have multiple endpoints. The TCON has two channels,
+ The output may have multiple endpoints. TCON can have 1 or 2 channels,
usually with the first channel being used for the panels interfaces
(RGB, LVDS, etc.), and the second being used for the outputs that
require another controller (TV Encoder, HDMI, etc.). The endpoints
@@ -119,11 +174,13 @@ Required properties:
channel the endpoint is associated to. If that property is not
present, the endpoint number will be used as the channel number.
-On SoCs other than the A33 and V3s, there is one more clock required:
+For TCONs with channel 0, there is one more clock required:
+ - 'tcon-ch0': The clock driving the TCON channel 0
+For TCONs with channel 1, there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
-On SoCs that support LVDS (all SoCs but the A13, H3, H5 and V3s), you
-need one more reset line:
+When TCON support LVDS (all TCONs except TV TCON on A83T and those found
+in A13, H3, H5 and V3s SoCs), you need one more reset line:
- 'lvds': The reset line driving the LVDS logic
And on the A23, A31, A31s and A33, you need one more clock line:
@@ -134,7 +191,7 @@ DRC
---
The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
-(A31, A23, A33), allows to dynamically adjust pixel
+(A31, A23, A33, A80), allows to dynamically adjust pixel
brightness/contrast based on histogram measurements for LCD content
adaptive backlight control.
@@ -144,6 +201,7 @@ Required properties:
* allwinner,sun6i-a31-drc
* allwinner,sun6i-a31s-drc
* allwinner,sun8i-a33-drc
+ * allwinner,sun9i-a80-drc
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the DRC
@@ -170,6 +228,7 @@ Required properties:
* allwinner,sun6i-a31-display-backend
* allwinner,sun7i-a20-display-backend
* allwinner,sun8i-a33-display-backend
+ * allwinner,sun9i-a80-display-backend
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the frontend and backend
@@ -191,6 +250,28 @@ On the A33, some additional properties are required:
- resets and reset-names need to have a phandle to the SAT bus
resets, whose name will be "sat"
+DEU
+---
+
+The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC,
+can sharpen the display content in both luma and chroma channels.
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun9i-a80-deu
+ - reg: base address and size of the memory-mapped region.
+ - interrupts: interrupt associated to this IP
+ - clocks: phandles to the clocks feeding the DEU
+ * ahb: the DEU interface clock
+ * mod: the DEU module clock
+ * ram: the DEU DRAM clock
+ - clock-names: the clock names mentioned above
+ - resets: phandles to the reset line driving the DEU
+
+- ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoints, the second one the outputs
+
Display Engine Frontend
-----------------------
@@ -204,6 +285,7 @@ Required properties:
* allwinner,sun6i-a31-display-frontend
* allwinner,sun7i-a20-display-frontend
* allwinner,sun8i-a33-display-frontend
+ * allwinner,sun9i-a80-display-frontend
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the frontend and backend
@@ -226,6 +308,8 @@ supported.
Required properties:
- compatible: value must be one of:
* allwinner,sun8i-a83t-de2-mixer-0
+ * allwinner,sun8i-a83t-de2-mixer-1
+ * allwinner,sun8i-h3-de2-mixer-0
* allwinner,sun8i-v3s-de2-mixer
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
@@ -256,7 +340,9 @@ Required properties:
* allwinner,sun7i-a20-display-engine
* allwinner,sun8i-a33-display-engine
* allwinner,sun8i-a83t-display-engine
+ * allwinner,sun8i-h3-display-engine
* allwinner,sun8i-v3s-display-engine
+ * allwinner,sun9i-a80-display-engine
- allwinner,pipelines: list of phandle to the display engine
frontends (DE 1.0) or mixers (DE 2.0) available.
diff --git a/dts/Bindings/dma/brcm,bcm2835-dma.txt b/dts/Bindings/dma/brcm,bcm2835-dma.txt
index baf9b34d2..b6a8cc097 100644
--- a/dts/Bindings/dma/brcm,bcm2835-dma.txt
+++ b/dts/Bindings/dma/brcm,bcm2835-dma.txt
@@ -74,8 +74,8 @@ Example:
bcm2835_i2s: i2s@7e203000 {
compatible = "brcm,bcm2835-i2s";
- reg = < 0x7e203000 0x20>,
- < 0x7e101098 0x02>;
+ reg = < 0x7e203000 0x24>;
+ clocks = <&clocks BCM2835_CLOCK_PCM>;
dmas = <&dma 2>,
<&dma 3>;
diff --git a/dts/Bindings/dma/mtk-hsdma.txt b/dts/Bindings/dma/mtk-hsdma.txt
new file mode 100644
index 000000000..4bb317359
--- /dev/null
+++ b/dts/Bindings/dma/mtk-hsdma.txt
@@ -0,0 +1,33 @@
+MediaTek High-Speed DMA Controller
+==================================
+
+This device follows the generic DMA bindings defined in dma/dma.txt.
+
+Required properties:
+
+- compatible: Must be one of
+ "mediatek,mt7622-hsdma": for MT7622 SoC
+ "mediatek,mt7623-hsdma": for MT7623 SoC
+- reg: Should contain the register's base address and length.
+- interrupts: Should contain a reference to the interrupt used by this
+ device.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "hsdma" entries.
+- power-domains: Phandle to the power domain that the device is part of
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+ hsdma: dma-controller@1b007000 {
+ compatible = "mediatek,mt7623-hsdma";
+ reg = <0 0x1b007000 0 0x1000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&ethsys CLK_ETHSYS_HSDMA>;
+ clock-names = "hsdma";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
diff --git a/dts/Bindings/dma/qcom_bam_dma.txt b/dts/Bindings/dma/qcom_bam_dma.txt
index 9cbf5d9df..cf5b9e444 100644
--- a/dts/Bindings/dma/qcom_bam_dma.txt
+++ b/dts/Bindings/dma/qcom_bam_dma.txt
@@ -15,6 +15,10 @@ Required properties:
the secure world.
- qcom,controlled-remotely : optional, indicates that the bam is controlled by
remote proccessor i.e. execution environment.
+- num-channels : optional, indicates supported number of DMA channels in a
+ remotely controlled bam.
+- qcom,num-ees : optional, indicates supported number of Execution Environments
+ in a remotely controlled bam.
Example:
diff --git a/dts/Bindings/dma/renesas,rcar-dmac.txt b/dts/Bindings/dma/renesas,rcar-dmac.txt
index 891db41e9..aadfb236d 100644
--- a/dts/Bindings/dma/renesas,rcar-dmac.txt
+++ b/dts/Bindings/dma/renesas,rcar-dmac.txt
@@ -18,6 +18,7 @@ Required Properties:
Examples with soctypes are:
- "renesas,dmac-r8a7743" (RZ/G1M)
- "renesas,dmac-r8a7745" (RZ/G1E)
+ - "renesas,dmac-r8a77470" (RZ/G1C)
- "renesas,dmac-r8a7790" (R-Car H2)
- "renesas,dmac-r8a7791" (R-Car M2-W)
- "renesas,dmac-r8a7792" (R-Car V2H)
@@ -26,6 +27,7 @@ Required Properties:
- "renesas,dmac-r8a7795" (R-Car H3)
- "renesas,dmac-r8a7796" (R-Car M3-W)
- "renesas,dmac-r8a77970" (R-Car V3M)
+ - "renesas,dmac-r8a77980" (R-Car V3H)
- reg: base address and length of the registers block for the DMAC
diff --git a/dts/Bindings/dma/renesas,usb-dmac.txt b/dts/Bindings/dma/renesas,usb-dmac.txt
index f3d1f151b..9dc935e24 100644
--- a/dts/Bindings/dma/renesas,usb-dmac.txt
+++ b/dts/Bindings/dma/renesas,usb-dmac.txt
@@ -11,6 +11,7 @@ Required Properties:
- "renesas,r8a7794-usb-dmac" (R-Car E2)
- "renesas,r8a7795-usb-dmac" (R-Car H3)
- "renesas,r8a7796-usb-dmac" (R-Car M3-W)
+ - "renesas,r8a77965-usb-dmac" (R-Car M3-N)
- reg: base address and length of the registers block for the DMAC
- interrupts: interrupt specifiers for the DMAC, one for each entry in
interrupt-names.
diff --git a/dts/Bindings/dma/snps,dw-axi-dmac.txt b/dts/Bindings/dma/snps,dw-axi-dmac.txt
new file mode 100644
index 000000000..f237b7928
--- /dev/null
+++ b/dts/Bindings/dma/snps,dw-axi-dmac.txt
@@ -0,0 +1,41 @@
+Synopsys DesignWare AXI DMA Controller
+
+Required properties:
+- compatible: "snps,axi-dma-1.01a"
+- reg: Address range of the DMAC registers. This should include
+ all of the per-channel registers.
+- interrupt: Should contain the DMAC interrupt number.
+- interrupt-parent: Should be the phandle for the interrupt controller
+ that services interrupts for this device.
+- dma-channels: Number of channels supported by hardware.
+- snps,dma-masters: Number of AXI masters supported by the hardware.
+- snps,data-width: Maximum AXI data width supported by hardware.
+ (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
+- snps,priority: Priority of channel. Array size is equal to the number of
+ dma-channels. Priority value must be programmed within [0:dma-channels-1]
+ range. (0 - minimum priority)
+- snps,block-size: Maximum block size supported by the controller channel.
+ Array size is equal to the number of dma-channels.
+
+Optional properties:
+- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
+ in this property. If this property is missing the maximum AXI burst length
+ supported by DMAC is used. [1:256]
+
+Example:
+
+dmac: dma-controller@80000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x80000 0x400>;
+ clocks = <&core_clk>, <&cfgr_clk>;
+ clock-names = "core-clk", "cfgr-clk";
+ interrupt-parent = <&intc>;
+ interrupts = <27>;
+
+ dma-channels = <4>;
+ snps,dma-masters = <2>;
+ snps,data-width = <3>;
+ snps,block-size = <4096 4096 4096 4096>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <16>;
+};
diff --git a/dts/Bindings/dma/stm32-dma.txt b/dts/Bindings/dma/stm32-dma.txt
index 0b55718bf..c5f519097 100644
--- a/dts/Bindings/dma/stm32-dma.txt
+++ b/dts/Bindings/dma/stm32-dma.txt
@@ -62,14 +62,14 @@ channel: a phandle to the DMA controller plus the following four integer cells:
0x1: medium
0x2: high
0x3: very high
-4. A 32bit mask specifying the DMA FIFO threshold configuration which are device
- dependent:
- -bit 0-1: Fifo threshold
+4. A 32bit bitfield value specifying DMA features which are device dependent:
+ -bit 0-1: DMA FIFO threshold selection
0x0: 1/4 full FIFO
0x1: 1/2 full FIFO
0x2: 3/4 full FIFO
0x3: full FIFO
+
Example:
usart1: serial@40011000 {
diff --git a/dts/Bindings/eeprom/at24.txt b/dts/Bindings/eeprom/at24.txt
index abfae1bec..61d833aba 100644
--- a/dts/Bindings/eeprom/at24.txt
+++ b/dts/Bindings/eeprom/at24.txt
@@ -41,12 +41,16 @@ Required properties:
"nxp",
"ramtron",
"renesas",
+ "rohm",
"st",
Some vendors use different model names for chips which are just
variants of the above. Known such exceptions are listed below:
+ "nxp,se97b" - the fallback is "atmel,24c02",
"renesas,r1ex24002" - the fallback is "atmel,24c02"
+ "renesas,r1ex24128" - the fallback is "atmel,24c128"
+ "rohm,br24t01" - the fallback is "atmel,24c01"
- reg: The I2C address of the EEPROM.
diff --git a/dts/Bindings/fsi/fsi.txt b/dts/Bindings/fsi/fsi.txt
new file mode 100644
index 000000000..ab516c673
--- /dev/null
+++ b/dts/Bindings/fsi/fsi.txt
@@ -0,0 +1,151 @@
+FSI bus & engine generic device tree bindings
+=============================================
+
+The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
+engines within those slaves. However, we have a facility to match devicetree
+nodes to probed engines. This allows for fsi engines to expose non-probeable
+busses, which are then exposed by the device tree. For example, an FSI engine
+that is an I2C master - the I2C bus can be described by the device tree under
+the engine's device tree node.
+
+FSI masters may require their own DT nodes (to describe the master HW itself);
+that requirement is defined by the master's implementation, and is described by
+the fsi-master-* binding specifications.
+
+Under the masters' nodes, we can describe the bus topology using nodes to
+represent the FSI slaves and their slave engines. As a basic outline:
+
+ fsi-master {
+ /* top-level of FSI bus topology, bound to an FSI master driver and
+ * exposes an FSI bus */
+
+ fsi-slave@<link,id> {
+ /* this node defines the FSI slave device, and is handled
+ * entirely with FSI core code */
+
+ fsi-slave-engine@<addr> {
+ /* this node defines the engine endpoint & address range, which
+ * is bound to the relevant fsi device driver */
+ ...
+ };
+
+ fsi-slave-engine@<addr> {
+ ...
+ };
+
+ };
+ };
+
+Note that since the bus is probe-able, some (or all) of the topology may
+not be described; this binding only provides an optional facility for
+adding subordinate device tree nodes as children of FSI engines.
+
+FSI masters
+-----------
+
+FSI master nodes declare themselves as such with the "fsi-master" compatible
+value. It's likely that an implementation-specific compatible value will
+be needed as well, for example:
+
+ compatible = "fsi-master-gpio", "fsi-master";
+
+Since the master nodes describe the top-level of the FSI topology, they also
+need to declare the FSI-standard addressing scheme. This requires two cells for
+addresses (link index and slave ID), and no size:
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+An optional boolean property can be added to indicate that a particular master
+should not scan for connected devices at initialization time. This is
+necessary in cases where a scan could cause arbitration issues with other
+masters that may be present on the bus.
+
+ no-scan-on-init;
+
+FSI slaves
+----------
+
+Slaves are identified by a (link-index, slave-id) pair, so require two cells
+for an address identifier. Since these are not a range, no size cells are
+required. For an example, a slave on link 1, with ID 2, could be represented
+as:
+
+ cfam@1,2 {
+ reg = <1 2>;
+ [...];
+ }
+
+Each slave provides an address-space, under which the engines are accessible.
+That address space has a maximum of 23 bits, so we use one cell to represent
+addresses and sizes in the slave address space:
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+
+FSI engines (devices)
+---------------------
+
+Engines are identified by their address under the slaves' address spaces. We
+use a single cell for address and size. Engine nodes represent the endpoint
+FSI device, and are passed to those FSI device drivers' ->probe() functions.
+
+For example, for a slave using a single 0x400-byte page starting at address
+0xc00:
+
+ engine@c00 {
+ reg = <0xc00 0x400>;
+ };
+
+
+Full example
+------------
+
+Here's an example that illustrates:
+ - an FSI master
+ - connected to an FSI slave
+ - that contains an engine that is an I2C master
+ - connected to an I2C EEPROM
+
+The FSI master may be connected to additional slaves, and slaves may have
+additional engines, but they don't necessarily need to be describe in the
+device tree if no extra platform information is required.
+
+ /* The GPIO-based FSI master node, describing the top level of the
+ * FSI bus
+ */
+ gpio-fsi {
+ compatible = "fsi-master-gpio", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ /* A FSI slave (aka. CFAM) at link 0, ID 0. */
+ cfam@0,0 {
+ reg = <0 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* FSI engine at 0xc00, using a single page. In this example,
+ * it's an I2C master controller, so subnodes describe the
+ * I2C bus.
+ */
+ i2c-controller@c00 {
+ reg = <0xc00 0x400>;
+
+ /* Engine-specific data. In this case, we're describing an
+ * I2C bus, so we're conforming to the generic I2C binding
+ */
+ compatible = "some-vendor,fsi-i2c-controller";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* I2C endpoint device: an Atmel EEPROM */
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ pagesize = <64>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/gpio/gpio-eic-sprd.txt b/dts/Bindings/gpio/gpio-eic-sprd.txt
new file mode 100644
index 000000000..93d98d09d
--- /dev/null
+++ b/dts/Bindings/gpio/gpio-eic-sprd.txt
@@ -0,0 +1,97 @@
+Spreadtrum EIC controller bindings
+
+The EIC is the abbreviation of external interrupt controller, which can
+be used only in input mode. The Spreadtrum platform has 2 EIC controllers,
+one is in digital chip, and another one is in PMIC. The digital chip EIC
+controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and
+EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
+module.
+
+The EIC-debounce sub-module provides up to 8 source input signal
+connections. A debounce mechanism is used to capture the input signals'
+stable status (millisecond resolution) and a single-trigger mechanism
+is introduced into this sub-module to enhance the input event detection
+reliability. In addition, this sub-module's clock can be shut off
+automatically to reduce power dissipation. Moreover the debounce range
+is from 1ms to 4s with a step size of 1ms. The input signal will be
+ignored if it is asserted for less than 1 ms.
+
+The EIC-latch sub-module is used to latch some special power down signals
+and generate interrupts, since the EIC-latch does not depend on the APB
+clock to capture signals.
+
+The EIC-async sub-module uses a 32kHz clock to capture the short signals
+(microsecond resolution) to generate interrupts by level or edge trigger.
+
+The EIC-sync is similar with GPIO's input function, which is a synchronized
+signal input register. It can generate interrupts by level or edge trigger
+when detecting input signals.
+
+Required properties:
+- compatible: Should be one of the following:
+ "sprd,sc9860-eic-debounce",
+ "sprd,sc9860-eic-latch",
+ "sprd,sc9860-eic-async",
+ "sprd,sc9860-eic-sync",
+ "sprd,sc27xx-eic".
+- reg: Define the base and range of the I/O address space containing
+ the GPIO controller registers.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be <2>. The first cell is the gpio number and
+ the second cell is used to specify optional parameters.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be <2>. Specifies the number of cells needed
+ to encode interrupt source.
+- interrupts: Should be the port interrupt shared by all the gpios.
+
+Example:
+ eic_debounce: gpio@40210000 {
+ compatible = "sprd,sc9860-eic-debounce";
+ reg = <0 0x40210000 0 0x80>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ eic_latch: gpio@40210080 {
+ compatible = "sprd,sc9860-eic-latch";
+ reg = <0 0x40210080 0 0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ eic_async: gpio@402100a0 {
+ compatible = "sprd,sc9860-eic-async";
+ reg = <0 0x402100a0 0 0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ eic_sync: gpio@402100c0 {
+ compatible = "sprd,sc9860-eic-sync";
+ reg = <0 0x402100c0 0 0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmic_eic: gpio@300 {
+ compatible = "sprd,sc27xx-eic";
+ reg = <0x300>;
+ interrupt-parent = <&sc2731_pmic>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/dts/Bindings/gpio/gpio-etraxfs.txt b/dts/Bindings/gpio/gpio-etraxfs.txt
deleted file mode 100644
index 170194af3..000000000
--- a/dts/Bindings/gpio/gpio-etraxfs.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-Axis ETRAX FS General I/O controller bindings
-
-Required properties:
-
-- compatible: one of:
- - "axis,etraxfs-gio"
- - "axis,artpec3-gio"
-- reg: Physical base address and length of the controller's registers.
-- #gpio-cells: Should be 3
- - The first cell is the gpio offset number.
- - The second cell is reserved and is currently unused.
- - The third cell is the port number (hex).
-- gpio-controller: Marks the device node as a GPIO controller.
-
-Example:
-
- gio: gpio@b001a000 {
- compatible = "axis,etraxfs-gio";
- reg = <0xb001a000 0x1000>;
- gpio-controller;
- #gpio-cells = <3>;
- };
diff --git a/dts/Bindings/gpio/gpio-pca953x.txt b/dts/Bindings/gpio/gpio-pca953x.txt
index 0d0158728..d2a937682 100644
--- a/dts/Bindings/gpio/gpio-pca953x.txt
+++ b/dts/Bindings/gpio/gpio-pca953x.txt
@@ -16,6 +16,8 @@ Required properties:
nxp,pca9574
nxp,pca9575
nxp,pca9698
+ nxp,pcal6524
+ nxp,pcal9555a
maxim,max7310
maxim,max7312
maxim,max7313
diff --git a/dts/Bindings/gpio/gpio-sprd.txt b/dts/Bindings/gpio/gpio-sprd.txt
new file mode 100644
index 000000000..eca97d453
--- /dev/null
+++ b/dts/Bindings/gpio/gpio-sprd.txt
@@ -0,0 +1,28 @@
+Spreadtrum GPIO controller bindings
+
+The controller's registers are organized as sets of sixteen 16-bit
+registers with each set controlling a bank of up to 16 pins. A single
+interrupt is shared for all of the banks handled by the controller.
+
+Required properties:
+- compatible: Should be "sprd,sc9860-gpio".
+- reg: Define the base and range of the I/O address space containing
+the GPIO controller registers.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be <2>. The first cell is the gpio number and
+the second cell is used to specify optional parameters.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be <2>. Specifies the number of cells needed
+to encode interrupt source.
+- interrupts: Should be the port interrupt shared by all the gpios.
+
+Example:
+ ap_gpio: gpio@40280000 {
+ compatible = "sprd,sc9860-gpio";
+ reg = <0 0x40280000 0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/dts/Bindings/gpio/gpio-tz1090-pdc.txt b/dts/Bindings/gpio/gpio-tz1090-pdc.txt
deleted file mode 100644
index 528f5ef5a..000000000
--- a/dts/Bindings/gpio/gpio-tz1090-pdc.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-ImgTec TZ1090 PDC GPIO Controller
-
-Required properties:
-- compatible: Compatible property value should be "img,tz1090-pdc-gpio".
-
-- reg: Physical base address of the controller and length of memory mapped
- region. This starts at and cover the SOC_GPIO_CONTROL registers.
-
-- gpio-controller: Specifies that the node is a gpio controller.
-
-- #gpio-cells: Should be 2. The syntax of the gpio specifier used by client
- nodes should have the following values.
- <[phandle of the gpio controller node]
- [PDC gpio number]
- [gpio flags]>
-
- Values for gpio specifier:
- - GPIO number: a value in the range 0 to 6.
- - GPIO flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
- Only the following flags are supported:
- GPIO_ACTIVE_HIGH
- GPIO_ACTIVE_LOW
-
-Optional properties:
-- gpio-ranges: Mapping to pin controller pins (as described in
- Documentation/devicetree/bindings/gpio/gpio.txt)
-
-- interrupts: Individual syswake interrupts (other GPIOs cannot interrupt)
-
-
-Example:
-
- pdc_gpios: gpio-controller@2006500 {
- gpio-controller;
- #gpio-cells = <2>;
-
- compatible = "img,tz1090-pdc-gpio";
- reg = <0x02006500 0x100>;
-
- interrupt-parent = <&pdc>;
- interrupts = <8 IRQ_TYPE_NONE>, /* Syswake 0 */
- <9 IRQ_TYPE_NONE>, /* Syswake 1 */
- <10 IRQ_TYPE_NONE>; /* Syswake 2 */
- gpio-ranges = <&pdc_pinctrl 0 0 7>;
- };
diff --git a/dts/Bindings/gpio/gpio-tz1090.txt b/dts/Bindings/gpio/gpio-tz1090.txt
deleted file mode 100644
index b05a90e0a..000000000
--- a/dts/Bindings/gpio/gpio-tz1090.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-ImgTec TZ1090 GPIO Controller
-
-Required properties:
-- compatible: Compatible property value should be "img,tz1090-gpio".
-
-- reg: Physical base address of the controller and length of memory mapped
- region.
-
-- #address-cells: Should be 1 (for bank subnodes)
-
-- #size-cells: Should be 0 (for bank subnodes)
-
-- Each bank of GPIOs should have a subnode to represent it.
-
- Bank subnode required properties:
- - reg: Index of bank in the range 0 to 2.
-
- - gpio-controller: Specifies that the node is a gpio controller.
-
- - #gpio-cells: Should be 2. The syntax of the gpio specifier used by client
- nodes should have the following values.
- <[phandle of the gpio controller node]
- [gpio number within the gpio bank]
- [gpio flags]>
-
- Values for gpio specifier:
- - GPIO number: a value in the range 0 to 29.
- - GPIO flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
- Only the following flags are supported:
- GPIO_ACTIVE_HIGH
- GPIO_ACTIVE_LOW
-
- Bank subnode optional properties:
- - gpio-ranges: Mapping to pin controller pins (as described in
- Documentation/devicetree/bindings/gpio/gpio.txt)
-
- - interrupts: Interrupt for the entire bank
-
- - interrupt-controller: Specifies that the node is an interrupt controller
-
- - #interrupt-cells: Should be 2. The syntax of the interrupt specifier used by
- client nodes should have the following values.
- <[phandle of the interurupt controller]
- [gpio number within the gpio bank]
- [irq flags]>
-
- Values for irq specifier:
- - GPIO number: a value in the range 0 to 29
- - IRQ flags: value to describe edge and level triggering, as defined in
- <dt-bindings/interrupt-controller/irq.h>. Only the following flags are
- supported:
- IRQ_TYPE_EDGE_RISING
- IRQ_TYPE_EDGE_FALLING
- IRQ_TYPE_EDGE_BOTH
- IRQ_TYPE_LEVEL_HIGH
- IRQ_TYPE_LEVEL_LOW
-
-
-
-Example:
-
- gpios: gpio-controller@2005800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "img,tz1090-gpio";
- reg = <0x02005800 0x90>;
-
- /* bank 0 with an interrupt */
- gpios0: bank@0 {
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- reg = <0>;
- interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 0 30>;
- interrupt-controller;
- };
-
- /* bank 2 without interrupt */
- gpios2: bank@2 {
- #gpio-cells = <2>;
- reg = <2>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 60 30>;
- };
- };
-
-
diff --git a/dts/Bindings/gpio/gpio.txt b/dts/Bindings/gpio/gpio.txt
index b5de08e3b..a7c31de29 100644
--- a/dts/Bindings/gpio/gpio.txt
+++ b/dts/Bindings/gpio/gpio.txt
@@ -151,9 +151,9 @@ in a lot of designs, some using all 32 bits, some using 18 and some using
first 18 GPIOs, at local offset 0 .. 17, are in use.
If these GPIOs do not happen to be the first N GP