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-rw-r--r--Makefile2
-rw-r--r--arch/arm/boards/zii-common/board.c3
-rw-r--r--arch/arm/configs/socfpga-arria10_defconfig1
-rw-r--r--arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h1
-rw-r--r--arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h4
-rw-r--r--arch/arm/mach-socfpga/include/mach/arria10-xload.h1
-rw-r--r--arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h11
-rw-r--r--arch/mips/boot/main_entry.c6
-rw-r--r--arch/mips/include/asm/cache.h1
-rw-r--r--arch/mips/lib/cpu-probe.c5
-rw-r--r--arch/mips/lib/reloc.c8
-rw-r--r--arch/mips/mach-loongson/include/mach/loongson1.h50
-rw-r--r--arch/mips/mach-loongson/include/mach/regs-clk.h81
-rw-r--r--arch/mips/mach-loongson/include/mach/regs-mux.h124
-rw-r--r--arch/mips/mach-loongson/include/mach/regs-pwm.h25
-rw-r--r--arch/mips/mach-loongson/include/mach/regs-rtc.h19
-rw-r--r--arch/mips/mach-loongson/include/mach/regs-wdt.h15
-rw-r--r--arch/mips/mach-loongson/loongson1_reset.c6
-rw-r--r--arch/sandbox/board/dev-random.c7
-rw-r--r--arch/sandbox/mach-sandbox/include/mach/linux.h1
-rw-r--r--arch/sandbox/os/common.c10
-rw-r--r--arch/x86/include/asm/linkage.h6
-rw-r--r--arch/x86/mach-efi/reloc_x86_64.c3
-rw-r--r--commands/Kconfig6
-rw-r--r--commands/cp.c3
-rw-r--r--commands/edit.c166
-rw-r--r--common/Kconfig6
-rw-r--r--common/efi-devicepath.c2
-rw-r--r--common/efi-guid.c2
-rw-r--r--common/efi/efi.c3
-rw-r--r--common/partitions.c4
-rw-r--r--drivers/block/efi-block-io.c17
-rw-r--r--drivers/efi/efi-device.c10
-rw-r--r--drivers/hw_random/Kconfig6
-rw-r--r--drivers/mfd/superio.c2
-rw-r--r--drivers/net/designware.h1
-rw-r--r--drivers/net/designware_socfpga.c133
-rw-r--r--drivers/of/of_gpio.c6
-rw-r--r--drivers/of/of_path.c2
-rw-r--r--drivers/serial/efi-stdio.c78
-rw-r--r--drivers/serial/efi-stdio.h58
-rw-r--r--drivers/usb/storage/usb.c7
-rw-r--r--dts/Bindings/arm/rockchip.yaml4
-rw-r--r--dts/Bindings/interrupt-controller/atmel,aic.txt7
-rw-r--r--dts/Bindings/media/allwinner,sun4i-a10-csi.yaml9
-rw-r--r--dts/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml86
-rw-r--r--dts/Bindings/regulator/fixed-regulator.yaml4
-rw-r--r--dts/Bindings/riscv/cpus.yaml29
-rw-r--r--dts/src/arc/hsdk.dts23
-rw-r--r--dts/src/arm/am3874-iceboard.dts9
-rw-r--r--dts/src/arm/bcm2835-rpi-zero-w.dts1
-rw-r--r--dts/src/arm/bcm2837-rpi-cm3.dtsi8
-rw-r--r--dts/src/arm/imx6-logicpd-som.dtsi4
-rw-r--r--dts/src/arm/imx7s.dtsi8
-rw-r--r--dts/src/arm/logicpd-torpedo-som.dtsi4
-rw-r--r--dts/src/arm/mt7629-rfb.dts13
-rw-r--r--dts/src/arm/mt7629.dtsi2
-rw-r--r--dts/src/arm/omap4-droid4-xt894.dts2
-rw-r--r--dts/src/arm/omap4-panda-common.dtsi2
-rw-r--r--dts/src/arm/omap4-sdp.dts2
-rw-r--r--dts/src/arm/omap4-var-som-om44-wlan.dtsi2
-rw-r--r--dts/src/arm/omap5-board-common.dtsi2
-rw-r--r--dts/src/arm/omap54xx-clocks.dtsi2
-rw-r--r--dts/src/arm/stm32mp157-pinctrl.dtsi8
-rw-r--r--dts/src/arm/sun7i-a20.dtsi5
-rw-r--r--dts/src/arm/vf610-zii-scu4-aib.dts2
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-pine64-plus.dts9
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts6
-rw-r--r--dts/src/arm64/allwinner/sun50i-a64.dtsi9
-rw-r--r--dts/src/arm64/broadcom/stingray/stingray-pinctrl.dtsi5
-rw-r--r--dts/src/arm64/broadcom/stingray/stingray.dtsi3
-rw-r--r--dts/src/arm64/freescale/fsl-lx2160a.dtsi36
-rw-r--r--dts/src/arm64/freescale/imx8mm.dtsi6
-rw-r--r--dts/src/arm64/freescale/imx8mn.dtsi6
-rw-r--r--dts/src/arm64/freescale/imx8mq-zii-ultra.dtsi4
-rw-r--r--dts/src/arm64/freescale/imx8mq.dtsi4
-rw-r--r--dts/src/arm64/marvell/armada-3720-turris-mox.dts13
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-kevin.dts2
-rw-r--r--dts/src/arm64/rockchip/rk3399-hugsun-x99.dts4
-rw-r--r--dts/src/arm64/rockchip/rk3399-rockpro64.dts12
-rw-r--r--dts/src/riscv/sifive/hifive-unleashed-a00.dts1
-rw-r--r--dts/src/xtensa/virt.dts2
-rw-r--r--fs/devfs-core.c2
-rw-r--r--fs/efivarfs.c2
-rw-r--r--fs/ext4/ext4_common.c32
-rw-r--r--fs/ext4/ext4fs.c61
-rw-r--r--fs/ubootvarfs.c2
-rw-r--r--include/efi.h5
-rw-r--r--include/efi/efi-device.h1
-rw-r--r--include/param.h6
-rw-r--r--lib/libfile.c17
-rw-r--r--lib/parameter.c5
-rw-r--r--lib/readline.c8
-rw-r--r--scripts/Kbuild.include5
94 files changed, 1041 insertions, 367 deletions
diff --git a/Makefile b/Makefile
index a780bed..b21ad5f 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
VERSION = 2019
-PATCHLEVEL = 10
+PATCHLEVEL = 11
SUBLEVEL = 0
EXTRAVERSION =
NAME = None
diff --git a/arch/arm/boards/zii-common/board.c b/arch/arm/boards/zii-common/board.c
index 9a9564e..eafb5a3 100644
--- a/arch/arm/boards/zii-common/board.c
+++ b/arch/arm/boards/zii-common/board.c
@@ -80,7 +80,8 @@ static int rdu_networkconfig(void)
static char *rdu_netconfig;
struct device_d *sp_dev;
- if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") &&
+ if (!of_machine_is_compatible("zii,imx8mq-ultra") &&
+ !of_machine_is_compatible("zii,imx6q-zii-rdu2") &&
!of_machine_is_compatible("zii,imx6qp-zii-rdu2") &&
!of_machine_is_compatible("zii,imx51-rdu1"))
return 0;
diff --git a/arch/arm/configs/socfpga-arria10_defconfig b/arch/arm/configs/socfpga-arria10_defconfig
index ae420c1..e47a0ab 100644
--- a/arch/arm/configs/socfpga-arria10_defconfig
+++ b/arch/arm/configs/socfpga-arria10_defconfig
@@ -74,6 +74,7 @@ CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_MMC_BOOT_PARTITIONS=y
CONFIG_MCI_DW=y
+CONFIG_STATE_DRV=y
# CONFIG_PINCTRL is not set
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h
index ee2b9b3..c0a5743 100644
--- a/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h
+++ b/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h
@@ -128,6 +128,7 @@ struct arria10_perpll_cfg {
extern int arria10_cm_basic_init(struct arria10_mainpll_cfg *mainpll_cfg,
struct arria10_perpll_cfg *perpll_cfg);
+unsigned int arria10_cm_get_mmc_controller_clk_hz(void);
extern unsigned int cm_get_mmc_controller_clk_hz(void);
extern void arria10_cm_use_intosc(void);
extern uint32_t cm_l4_main_clk_hz;
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
index ebd2043..2033de7 100644
--- a/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
+++ b/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
@@ -108,6 +108,10 @@
void arria10_reset_peripherals(void);
void arria10_reset_deassert_dedicated_peripherals(void);
void arria10_reset_deassert_shared_peripherals(void);
+void arria10_reset_deassert_shared_peripherals_q1(uint32_t *mask0, uint32_t *mask1);
+void arria10_reset_deassert_shared_peripherals_q2(uint32_t *mask0, uint32_t *mask1);
+void arria10_reset_deassert_shared_peripherals_q3(uint32_t *mask0, uint32_t *mask1);
+void arria10_reset_deassert_shared_peripherals_q4(uint32_t *mask0, uint32_t *mask1);
void arria10_reset_deassert_fpga_peripherals(void);
#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-xload.h b/arch/arm/mach-socfpga/include/mach/arria10-xload.h
index 71f8397..7575231 100644
--- a/arch/arm/mach-socfpga/include/mach/arria10-xload.h
+++ b/arch/arm/mach-socfpga/include/mach/arria10-xload.h
@@ -4,6 +4,7 @@
void arria10_init_mmc(void);
int arria10_prepare_mmc(int barebox_part, int rbf_part);
int arria10_read_blocks(void *dst, int blocknum, size_t len);
+int a10_update_bits(unsigned int reg, unsigned int mask, unsigned int val);
struct partition {
uint64_t first_sec;
diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h
index 24f52ef..7cec609 100644
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h
@@ -57,15 +57,4 @@ void socfpga_sysmgr_pinmux_init(unsigned long *sys_mgr_init_table, int num);
#define SYSMGR_FPGAINTF_NAND (1<<4)
#define SYSMGR_FPGAINTF_SDMMC (1<<5)
-/* Enumeration: sysmgr::emacgrp::ctrl::physel::enum */
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
-#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
-#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
-
-#define SYSMGR_FPGAGRP_MODULE 0x00000028
-#define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004
-
#endif /* _SYSTEM_MANAGER_H_ */
diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c
index 4ae4457..2c18bc8 100644
--- a/arch/mips/boot/main_entry.c
+++ b/arch/mips/boot/main_entry.c
@@ -77,12 +77,6 @@ void __bare_init main_entry(void *fdt, u32 fdt_size)
cpu_probe();
- if (cpu_has_4k_cache) {
- extern void r4k_cache_init(void);
-
- r4k_cache_init();
- }
-
trap_init();
malloc_end = (unsigned long)_stext;
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index cceba0a..4bb39b1 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -2,5 +2,6 @@
#define _ASM_MIPS_CACHE_H
void flush_cache_all(void);
+void r4k_cache_init(void);
#endif /* _ASM_MIPS_CACHE_H */
diff --git a/arch/mips/lib/cpu-probe.c b/arch/mips/lib/cpu-probe.c
index 2556a8b..ddabddd 100644
--- a/arch/mips/lib/cpu-probe.c
+++ b/arch/mips/lib/cpu-probe.c
@@ -9,6 +9,8 @@
*/
#include <common.h>
#include <asm/mipsregs.h>
+#include <asm/cache.h>
+#include <asm/cpu-features.h>
#include <asm/cpu-info.h>
#include <asm/cpu.h>
#include <memory.h>
@@ -163,6 +165,9 @@ void cpu_probe(void)
cpu_probe_ingenic(c);
break;
}
+
+ if (cpu_has_4k_cache)
+ r4k_cache_init();
}
unsigned long mips_stack_top;
diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c
index 9a9e404..df9760e 100644
--- a/arch/mips/lib/reloc.c
+++ b/arch/mips/lib/reloc.c
@@ -110,11 +110,13 @@ void relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
{
unsigned long addr, length, bss_len;
u32 relocaddr, new_stack;
- uint8_t *buf, *bss_start;
+ uint8_t *buf;
unsigned int type;
long off;
bss_len = (unsigned long)&__bss_stop - (unsigned long)__bss_start;
+ memset(__bss_start, 0, bss_len);
+ cpu_probe();
length = barebox_image_size + bss_len;
relocaddr = ALIGN_DOWN(ram_size - length, SZ_64K);
@@ -149,10 +151,6 @@ void relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
/* Ensure the icache is coherent */
flush_cache_all();
- /* Clear the .bss section */
- bss_start = (uint8_t *)((unsigned long)__bss_start + off);
- memset(bss_start, 0, bss_len);
-
__asm__ __volatile__ (
"move $a0, %0\n"
" move $a1, %1\n"
diff --git a/arch/mips/mach-loongson/include/mach/loongson1.h b/arch/mips/mach-loongson/include/mach/loongson1.h
index 75e1a55..8b53f47 100644
--- a/arch/mips/mach-loongson/include/mach/loongson1.h
+++ b/arch/mips/mach-loongson/include/mach/loongson1.h
@@ -1,28 +1,54 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * Copyright (c) 2011 Zhang, Keguang <keguang.zhang at gmail.com>
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Register mappings for Loongson 1
*/
-#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H
-#define __ASM_MACH_LOONGSON1_LOONGSON1_H
+#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H
+#define __ASM_MACH_LOONGSON32_LOONGSON1_H
-#include <asm/addrspace.h>
+#if defined(CONFIG_LOONGSON1_LS1B)
+#define DEFAULT_MEMSIZE 64 /* If no memsize provided */
+#elif defined(CONFIG_LOONGSON1_LS1C)
+#define DEFAULT_MEMSIZE 32
+#endif
/* Loongson 1 Register Bases */
+#define LS1X_MUX_BASE 0x1fd00420
+#define LS1X_INTC_BASE 0x1fd01040
+#define LS1X_GPIO0_BASE 0x1fd010c0
+#define LS1X_GPIO1_BASE 0x1fd010c4
+#define LS1X_DMAC_BASE 0x1fd01160
+#define LS1X_CBUS_BASE 0x1fd011c0
+#define LS1X_EHCI_BASE 0x1fe00000
+#define LS1X_OHCI_BASE 0x1fe08000
+#define LS1X_GMAC0_BASE 0x1fe10000
+#define LS1X_GMAC1_BASE 0x1fe20000
+
#define LS1X_UART0_BASE 0x1fe40000
#define LS1X_UART1_BASE 0x1fe44000
#define LS1X_UART2_BASE 0x1fe48000
#define LS1X_UART3_BASE 0x1fe4c000
+#define LS1X_CAN0_BASE 0x1fe50000
+#define LS1X_CAN1_BASE 0x1fe54000
+#define LS1X_I2C0_BASE 0x1fe58000
+#define LS1X_I2C1_BASE 0x1fe68000
+#define LS1X_I2C2_BASE 0x1fe70000
+#define LS1X_PWM0_BASE 0x1fe5c000
+#define LS1X_PWM1_BASE 0x1fe5c010
+#define LS1X_PWM2_BASE 0x1fe5c020
+#define LS1X_PWM3_BASE 0x1fe5c030
#define LS1X_WDT_BASE 0x1fe5c060
+#define LS1X_RTC_BASE 0x1fe64000
+#define LS1X_AC97_BASE 0x1fe74000
+#define LS1X_NAND_BASE 0x1fe78000
+#define LS1X_CLK_BASE 0x1fe78030
-/* Loongson 1 watchdog register definitions */
-#define LS1X_WDT_REG(x) \
- ((void __iomem *)KSEG1ADDR(LS1X_WDT_BASE + (x)))
-
-#define LS1X_WDT_EN LS1X_WDT_REG(0x0)
-#define LS1X_WDT_SET LS1X_WDT_REG(0x4)
-#define LS1X_WDT_TIMER LS1X_WDT_REG(0x8)
+#include <mach/regs-clk.h>
+#include <mach/regs-mux.h>
+#include <mach/regs-pwm.h>
+#include <mach/regs-rtc.h>
+#include <mach/regs-wdt.h>
-#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */
+#endif /* __ASM_MACH_LOONGSON32_LOONGSON1_H */
diff --git a/arch/mips/mach-loongson/include/mach/regs-clk.h b/arch/mips/mach-loongson/include/mach/regs-clk.h
new file mode 100644
index 0000000..98136fa
--- /dev/null
+++ b/arch/mips/mach-loongson/include/mach/regs-clk.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 Clock Register Definitions.
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_REGS_CLK_H
+#define __ASM_MACH_LOONGSON32_REGS_CLK_H
+
+#define LS1X_CLK_REG(x) \
+ ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
+
+#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0)
+#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)
+
+#if defined(CONFIG_LOONGSON1_LS1B)
+/* Clock PLL Divisor Register Bits */
+#define DIV_DC_EN BIT(31)
+#define DIV_DC_RST BIT(30)
+#define DIV_CPU_EN BIT(25)
+#define DIV_CPU_RST BIT(24)
+#define DIV_DDR_EN BIT(19)
+#define DIV_DDR_RST BIT(18)
+#define RST_DC_EN BIT(5)
+#define RST_DC BIT(4)
+#define RST_DDR_EN BIT(3)
+#define RST_DDR BIT(2)
+#define RST_CPU_EN BIT(1)
+#define RST_CPU BIT(0)
+
+#define DIV_DC_SHIFT 26
+#define DIV_CPU_SHIFT 20
+#define DIV_DDR_SHIFT 14
+
+#define DIV_DC_WIDTH 4
+#define DIV_CPU_WIDTH 4
+#define DIV_DDR_WIDTH 4
+
+#define BYPASS_DC_SHIFT 12
+#define BYPASS_DDR_SHIFT 10
+#define BYPASS_CPU_SHIFT 8
+
+#define BYPASS_DC_WIDTH 1
+#define BYPASS_DDR_WIDTH 1
+#define BYPASS_CPU_WIDTH 1
+
+#elif defined(CONFIG_LOONGSON1_LS1C)
+/* PLL/SDRAM Frequency configuration register Bits */
+#define PLL_VALID BIT(31)
+#define FRAC_N GENMASK(23, 16)
+#define RST_TIME GENMASK(3, 2)
+#define SDRAM_DIV GENMASK(1, 0)
+
+/* CPU/CAMERA/DC Frequency configuration register Bits */
+#define DIV_DC_EN BIT(31)
+#define DIV_DC GENMASK(30, 24)
+#define DIV_CAM_EN BIT(23)
+#define DIV_CAM GENMASK(22, 16)
+#define DIV_CPU_EN BIT(15)
+#define DIV_CPU GENMASK(14, 8)
+#define DIV_DC_SEL_EN BIT(5)
+#define DIV_DC_SEL BIT(4)
+#define DIV_CAM_SEL_EN BIT(3)
+#define DIV_CAM_SEL BIT(2)
+#define DIV_CPU_SEL_EN BIT(1)
+#define DIV_CPU_SEL BIT(0)
+
+#define DIV_DC_SHIFT 24
+#define DIV_CAM_SHIFT 16
+#define DIV_CPU_SHIFT 8
+#define DIV_DDR_SHIFT 0
+
+#define DIV_DC_WIDTH 7
+#define DIV_CAM_WIDTH 7
+#define DIV_CPU_WIDTH 7
+#define DIV_DDR_WIDTH 2
+
+#endif
+
+#endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */
diff --git a/arch/mips/mach-loongson/include/mach/regs-mux.h b/arch/mips/mach-loongson/include/mach/regs-mux.h
new file mode 100644
index 0000000..95788a4
--- /dev/null
+++ b/arch/mips/mach-loongson/include/mach/regs-mux.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 MUX Register Definitions.
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_REGS_MUX_H
+#define __ASM_MACH_LOONGSON32_REGS_MUX_H
+
+#define LS1X_MUX_REG(x) \
+ ((void __iomem *)KSEG1ADDR(LS1X_MUX_BASE + (x)))
+
+#define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0)
+#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4)
+
+#if defined(CONFIG_LOONGSON1_LS1B)
+/* MUX CTRL0 Register Bits */
+#define UART0_USE_PWM23 BIT(28)
+#define UART0_USE_PWM01 BIT(27)
+#define UART1_USE_LCD0_5_6_11 BIT(26)
+#define I2C2_USE_CAN1 BIT(25)
+#define I2C1_USE_CAN0 BIT(24)
+#define NAND3_USE_UART5 BIT(23)
+#define NAND3_USE_UART4 BIT(22)
+#define NAND3_USE_UART1_DAT BIT(21)
+#define NAND3_USE_UART1_CTS BIT(20)
+#define NAND3_USE_PWM23 BIT(19)
+#define NAND3_USE_PWM01 BIT(18)
+#define NAND2_USE_UART5 BIT(17)
+#define NAND2_USE_UART4 BIT(16)
+#define NAND2_USE_UART1_DAT BIT(15)
+#define NAND2_USE_UART1_CTS BIT(14)
+#define NAND2_USE_PWM23 BIT(13)
+#define NAND2_USE_PWM01 BIT(12)
+#define NAND1_USE_UART5 BIT(11)
+#define NAND1_USE_UART4 BIT(10)
+#define NAND1_USE_UART1_DAT BIT(9)
+#define NAND1_USE_UART1_CTS BIT(8)
+#define NAND1_USE_PWM23 BIT(7)
+#define NAND1_USE_PWM01 BIT(6)
+#define GMAC1_USE_UART1 BIT(4)
+#define GMAC1_USE_UART0 BIT(3)
+#define LCD_USE_UART0_DAT BIT(2)
+#define LCD_USE_UART15 BIT(1)
+#define LCD_USE_UART0 BIT(0)
+
+/* MUX CTRL1 Register Bits */
+#define USB_RESET BIT(31)
+#define SPI1_CS_USE_PWM01 BIT(24)
+#define SPI1_USE_CAN BIT(23)
+#define DISABLE_DDR_CONFSPACE BIT(20)
+#define DDR32TO16EN BIT(16)
+#define GMAC1_SHUT BIT(13)
+#define GMAC0_SHUT BIT(12)
+#define USB_SHUT BIT(11)
+#define UART1_3_USE_CAN1 BIT(5)
+#define UART1_2_USE_CAN0 BIT(4)
+#define GMAC1_USE_TXCLK BIT(3)
+#define GMAC0_USE_TXCLK BIT(2)
+#define GMAC1_USE_PWM23 BIT(1)
+#define GMAC0_USE_PWM01 BIT(0)
+
+#elif defined(CONFIG_LOONGSON1_LS1C)
+
+/* SHUT_CTRL Register Bits */
+#define UART_SPLIT GENMASK(31, 30)
+#define OUTPUT_CLK GENMASK(29, 26)
+#define ADC_SHUT BIT(25)
+#define SDIO_SHUT BIT(24)
+#define DMA2_SHUT BIT(23)
+#define DMA1_SHUT BIT(22)
+#define DMA0_SHUT BIT(21)
+#define SPI1_SHUT BIT(20)
+#define SPI0_SHUT BIT(19)
+#define I2C2_SHUT BIT(18)
+#define I2C1_SHUT BIT(17)
+#define I2C0_SHUT BIT(16)
+#define AC97_SHUT BIT(15)
+#define I2S_SHUT BIT(14)
+#define UART3_SHUT BIT(13)
+#define UART2_SHUT BIT(12)
+#define UART1_SHUT BIT(11)
+#define UART0_SHUT BIT(10)
+#define CAN1_SHUT BIT(9)
+#define CAN0_SHUT BIT(8)
+#define ECC_SHUT BIT(7)
+#define GMAC_SHUT BIT(6)
+#define USBHOST_SHUT BIT(5)
+#define USBOTG_SHUT BIT(4)
+#define SDRAM_SHUT BIT(3)
+#define SRAM_SHUT BIT(2)
+#define CAM_SHUT BIT(1)
+#define LCD_SHUT BIT(0)
+
+#define UART_SPLIT_SHIFT 30
+#define OUTPUT_CLK_SHIFT 26
+
+/* MISC_CTRL Register Bits */
+#define USBHOST_RSTN BIT(31)
+#define PHY_INTF_SELI GENMASK(30, 28)
+#define AC97_EN BIT(25)
+#define SDIO_DMA_EN GENMASK(24, 23)
+#define ADC_DMA_EN BIT(22)
+#define SDIO_USE_SPI1 BIT(17)
+#define SDIO_USE_SPI0 BIT(16)
+#define SRAM_CTRL GENMASK(15, 0)
+
+#define PHY_INTF_SELI_SHIFT 28
+#define SDIO_DMA_EN_SHIFT 23
+#define SRAM_CTRL_SHIFT 0
+
+#define LS1X_CBUS_REG(n, x) \
+ ((void __iomem *)KSEG1ADDR(LS1X_CBUS_BASE + (n * 0x04) + (x)))
+
+#define LS1X_CBUS_FIRST(n) LS1X_CBUS_REG(n, 0x00)
+#define LS1X_CBUS_SECOND(n) LS1X_CBUS_REG(n, 0x10)
+#define LS1X_CBUS_THIRD(n) LS1X_CBUS_REG(n, 0x20)
+#define LS1X_CBUS_FOURTHT(n) LS1X_CBUS_REG(n, 0x30)
+#define LS1X_CBUS_FIFTHT(n) LS1X_CBUS_REG(n, 0x40)
+
+#endif
+
+#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */
diff --git a/arch/mips/mach-loongson/include/mach/regs-pwm.h b/arch/mips/mach-loongson/include/mach/regs-pwm.h
new file mode 100644
index 0000000..ec870c8
--- /dev/null
+++ b/arch/mips/mach-loongson/include/mach/regs-pwm.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 PWM Register Definitions.
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_REGS_PWM_H
+#define __ASM_MACH_LOONGSON32_REGS_PWM_H
+
+/* Loongson 1 PWM Timer Register Definitions */
+#define PWM_CNT 0x0
+#define PWM_HRC 0x4
+#define PWM_LRC 0x8
+#define PWM_CTRL 0xc
+
+/* PWM Control Register Bits */
+#define CNT_RST BIT(7)
+#define INT_SR BIT(6)
+#define INT_EN BIT(5)
+#define PWM_SINGLE BIT(4)
+#define PWM_OE BIT(3)
+#define CNT_EN BIT(0)
+
+#endif /* __ASM_MACH_LOONGSON32_REGS_PWM_H */
diff --git a/arch/mips/mach-loongson/include/mach/regs-rtc.h b/arch/mips/mach-loongson/include/mach/regs-rtc.h
new file mode 100644
index 0000000..a3d096b
--- /dev/null
+++ b/arch/mips/mach-loongson/include/mach/regs-rtc.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com>
+ *
+ * Loongson 1 RTC timer Register Definitions.
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_REGS_RTC_H
+#define __ASM_MACH_LOONGSON32_REGS_RTC_H
+
+#define LS1X_RTC_REG(x) \
+ ((void __iomem *)KSEG1ADDR(LS1X_RTC_BASE + (x)))
+
+#define LS1X_RTC_CTRL LS1X_RTC_REG(0x40)
+
+#define RTC_EXTCLK_OK (BIT(5) | BIT(8))
+#define RTC_EXTCLK_EN BIT(8)
+
+#endif /* __ASM_MACH_LOONGSON32_REGS_RTC_H */
diff --git a/arch/mips/mach-loongson/include/mach/regs-wdt.h b/arch/mips/mach-loongson/include/mach/regs-wdt.h
new file mode 100644
index 0000000..c6d345f
--- /dev/null
+++ b/arch/mips/mach-loongson/include/mach/regs-wdt.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 Watchdog Register Definitions.
+ */
+
+#ifndef __ASM_MACH_LOONGSON32_REGS_WDT_H
+#define __ASM_MACH_LOONGSON32_REGS_WDT_H
+
+#define WDT_EN 0x0
+#define WDT_TIMER 0x4
+#define WDT_SET 0x8
+
+#endif /* __ASM_MACH_LOONGSON32_REGS_WDT_H */
diff --git a/arch/mips/mach-loongson/loongson1_reset.c b/arch/mips/mach-loongson/loongson1_reset.c
index 3763a10..a6c0590 100644
--- a/arch/mips/mach-loongson/loongson1_reset.c
+++ b/arch/mips/mach-loongson/loongson1_reset.c
@@ -11,9 +11,9 @@
static void __noreturn longhorn_restart_soc(struct restart_handler *rst)
{
- __raw_writel(0x1, LS1X_WDT_EN);
- __raw_writel(0x1, LS1X_WDT_SET);
- __raw_writel(0x1, LS1X_WDT_TIMER);
+ __raw_writel(0x1, WDT_EN);
+ __raw_writel(0x1, WDT_SET);
+ __raw_writel(0x1, WDT_TIMER);
hang();
}
diff --git a/arch/sandbox/board/dev-random.c b/arch/sandbox/board/dev-random.c
index f65e5ef..60295e9 100644
--- a/arch/sandbox/board/dev-random.c
+++ b/arch/sandbox/board/dev-random.c
@@ -4,10 +4,6 @@
devrandom_t *devrandom_init(void) {
devrandom_t *fds = xzalloc(sizeof(*fds));
- fds->randomfd = linux_open("/dev/random", false);
- if (fds->randomfd < 0)
- return ERR_PTR(-EPERM);
-
fds->urandomfd = linux_open("/dev/urandom", false);
if (fds->urandomfd < 0)
return ERR_PTR(-EPERM);
@@ -17,8 +13,7 @@ devrandom_t *devrandom_init(void) {
int devrandom_read(devrandom_t *devrandom, void *buf, size_t len, int wait)
{
- if (wait)
- return linux_read(devrandom->randomfd, buf, len);
+ (void)wait; /* /dev/urandom won't block */
return linux_read(devrandom->urandomfd, buf, len);
}
diff --git a/arch/sandbox/mach-sandbox/include/mach/linux.h b/arch/sandbox/mach-sandbox/include/mach/linux.h
index 1e64d41..9759a37 100644
--- a/arch/sandbox/mach-sandbox/include/mach/linux.h
+++ b/arch/sandbox/mach-sandbox/include/mach/linux.h
@@ -52,7 +52,6 @@ int barebox_libftdi1_update(struct ft2232_bitbang *ftbb);
void barebox_libftdi1_close(void);
typedef struct {
- int randomfd;
int urandomfd;
} devrandom_t;
devrandom_t *devrandom_init(void);
diff --git a/arch/sandbox/os/common.c b/arch/sandbox/os/common.c
index 8611882..3ad12b4 100644
--- a/arch/sandbox/os/common.c
+++ b/arch/sandbox/os/common.c
@@ -39,6 +39,8 @@
#include <signal.h>
#include <sys/select.h>
#include <sys/wait.h>
+#include <sys/ioctl.h>
+#include <linux/fs.h>
/*
* ...except the ones needed to connect with barebox
*/
@@ -260,11 +262,17 @@ static int add_image(char *str, char *devname_template, int *devname_number)
hf->size = s.st_size;
hf->devname = strdup(devname);
+ if (S_ISBLK(s.st_mode)) {
+ if (ioctl(fd, BLKGETSIZE64, &hf->size) == -1) {
+ perror("ioctl");
+ goto err_out;
+ }
+ }
hf->base = (unsigned long)mmap(NULL, hf->size,
PROT_READ | (readonly ? 0 : PROT_WRITE),
MAP_SHARED, fd, 0);
if ((void *)hf->base == MAP_FAILED)
- printf("warning: mmapping %s failed\n", filename);
+ printf("warning: mmapping %s failed: %s\n", filename, strerror(errno));
ret = barebox_register_filedev(hf);
if (ret)
diff --git a/arch/x86/include/asm/linkage.h b/arch/x86/include/asm/linkage.h
new file mode 100644
index 0000000..a8d1bdb
--- /dev/null
+++ b/arch/x86/include/asm/linkage.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+/* referenced by <linux/linkage.h> */
+
+#endif
diff --git a/arch/x86/mach-efi/reloc_x86_64.c b/arch/x86/mach-efi/reloc_x86_64.c
index 1db72f5..e83bacb 100644
--- a/arch/x86/mach-efi/reloc_x86_64.c
+++ b/arch/x86/mach-efi/reloc_x86_64.c
@@ -35,11 +35,14 @@
SUCH DAMAGE.
*/
+#include <linux/linkage.h>
#include <common.h>
#include <efi.h>
#include <elf.h>
+asmlinkage efi_status_t _relocate (long, Elf64_Dyn *, efi_handle_t, efi_system_table_t *);
+
efi_status_t _relocate (long ldbase, Elf64_Dyn *dyn, efi_handle_t image, efi_system_table_t *systab)
{
long relsz = 0, relent = 0;
diff --git a/commands/Kconfig b/commands/Kconfig
index 0189b47..a6db52a 100644
--- a/commands/Kconfig
+++ b/commands/Kconfig
@@ -1389,8 +1389,10 @@ config CMD_PASSWD
help
Set password
- 'Interactively asks for a password. The digest of this password will be
- stored in /env/etc//passwd. This is then used by the 'login' command.
+ Interactively asks for a password. The digest of this password will be
+ stored in /env/etc/passwd. This is then used by the 'login' command.
+
+ Passwords can be generated on the host machine using barebox sandbox.
Entering an empty string will disable the password function.
diff --git a/commands/cp.c b/commands/cp.c
index 54934dd..845dae6 100644
--- a/commands/cp.c
+++ b/commands/cp.c
@@ -100,13 +100,14 @@ BAREBOX_CMD_HELP_START(cp)
BAREBOX_CMD_HELP_TEXT("Copy file from SRC to DEST.")
BAREBOX_CMD_HELP_TEXT("")
BAREBOX_CMD_HELP_TEXT("Options:")
+BAREBOX_CMD_HELP_OPT ("-r", "recursive")
BAREBOX_CMD_HELP_OPT ("-v", "verbose")
BAREBOX_CMD_HELP_END
BAREBOX_CMD_START(cp)
.cmd = do_cp,
BAREBOX_CMD_DESC("copy files")
- BAREBOX_CMD_OPTS("[-v] SRC DEST")
+ BAREBOX_CMD_OPTS("[-rv] SRC DEST")
BAREBOX_CMD_GROUP(CMD_GRP_FILE)
BAREBOX_CMD_HELP(cmd_cp_help)
BAREBOX_CMD_END
diff --git a/commands/edit.c b/commands/edit.c
index ba6a8c7..4e661df 100644
--- a/commands/edit.c
+++ b/commands/edit.c
@@ -55,7 +55,7 @@ static int scrcol = 0; /* the first column on screen */
static void pos(int x, int y)
{
- printf("%c[%d;%dH", 27, y + 2, x + 1);
+ printf("\x1b[%d;%dH", y + 2, x + 1);
}
static char *screenline(char *line, int *pos)
@@ -110,7 +110,7 @@ static void refresh_line(struct line *line, int ypos)
char *str = screenline(line->data, NULL) + scrcol;
pos(0, ypos);
str[screenwidth] = 0;
- printf("%s%c[K", str, 27);
+ printf("%s\x1b[K", str);
pos(cursx, cursy);
}
@@ -130,7 +130,7 @@ static void refresh(int full)
if (!full) {
if (smartscroll) {
if (scrline->next == lastscrline) {
- printf("%c[1T", 27);
+ printf("\x1b[1T");
refresh_line(scrline, 0);
pos(0, screenheight);
printf("%*s", screenwidth, "");
@@ -138,7 +138,7 @@ static void refresh(int full)
}
if (scrline->prev == lastscrline) {
- printf("%c[1S", 27);
+ printf("\x1b[1S");
for (i = 0; i < screenheight - 1; i++) {
l = l->next;
if (!l)
@@ -378,8 +378,128 @@ static void getwinsize(void)
pos(0, 0);
}
+static void statusbar(const char *str)
+{
+ pos(0, screenheight+1);
+ printf("%*c\r%s", screenwidth, ' ', str);
+ pos(cursx, cursy);
+}
+
+static int read_modal_key(bool is_modal)
+{
+ static enum { MODE_INSERT, MODE_NORMAL } mode = MODE_NORMAL;
+ static int backlog[2] = { -1, -1 };
+ int c;
+
+ if (backlog[0] >= 0) {
+ /* pop a character */
+ c = backlog[0];
+ backlog[0] = backlog[1];
+ backlog[1] = -1;
+ } else {
+ c = read_key();
+ }
+
+ if (is_modal && mode == MODE_INSERT && (c == -1 || c == CTL_CH('c'))) {
+ mode = MODE_NORMAL;
+ statusbar("");
+ return -EAGAIN;
+ }
+
+ if (!is_modal || mode == MODE_INSERT)
+ return c;
+
+ switch (c) {
+ case -1: /* invalid escape, e.g. two escapes in a row */
+ break;
+ case 'i':
+ statusbar("-- INSERT --");
+ mode = MODE_INSERT;
+ break;
+ case 'h':
+ return BB_KEY_LEFT;
+ case 'j':
+ return BB_KEY_DOWN;
+ case 'k':
+ return BB_KEY_UP;
+ case 'a':
+ statusbar("-- INSERT --");
+ mode = MODE_INSERT;
+ /* fall through */
+ case 'l':
+ return BB_KEY_RIGHT;
+ case 'O':
+ backlog[0] = '\n';
+ backlog[1] = BB_KEY_UP;
+ /* fall through */
+ case 'I':
+ statusbar("-- INSERT --");
+ mode = MODE_INSERT;
+ /* fall through */
+ case '^':
+ case '0':
+ return BB_KEY_HOME;
+ case 'g':
+ c = read_key();
+ if (c != 'g')
+ break;
+ backlog[0] = CTL_CH('u');
+ backlog[1] = CTL_CH('u');
+ /* fall through */
+ case CTL_CH('u'):
+ return BB_KEY_PAGEUP;
+ case 'G':
+ backlog[0] = CTL_CH('d');
+ backlog[1] = CTL_CH('d');
+ /* fall through */
+ case CTL_CH('d'):
+ return BB_KEY_PAGEDOWN;
+ case 'o':
+ backlog[0] = '\n';
+ /* fall through */
+ case 'A':
+ statusbar("-- INSERT --");
+ mode = MODE_INSERT;
+ /* fall through */
+ case '$':
+ return BB_KEY_END;
+ case CTL_CH('c'):
+ statusbar("Type ZQ to abandon all changes and exit vi."
+ "Type ZZ to exit while saving them.");
+ break;
+ case 'x':
+ return BB_KEY_DEL;
+ case 'X':
+ return '\b';
+ case BB_KEY_PAGEUP:
+ case BB_KEY_PAGEDOWN:
+ case BB_KEY_HOME:
+ case BB_KEY_END:
+ case BB_KEY_UP:
+ case BB_KEY_DOWN:
+ case BB_KEY_RIGHT:
+ case BB_KEY_LEFT:
+ return c;
+ case ':':
+ statusbar("ERROR: command mode not supported");
+ break;
+ case 'Z':
+ c = read_key();
+ if (c == 'Z')
+ return CTL_CH('d');
+ if (c == 'Q')
+ return CTL_CH('c');
+ default:
+ statusbar("ERROR: not implemented");
+ break;
+ }
+
+ return -EAGAIN;
+}
+
static int do_edit(int argc, char *argv[])
{
+ bool is_vi = false;
int lastscrcol;
int i;
int linepos;
@@ -401,10 +521,14 @@ static int do_edit(int argc, char *argv[])
else
screenheight = 25;
- /* check if we are called as "sedit" instead of "edit" */
- if (*argv[0] == 's') {
+ /* check if we are not called as "edit" */
+ if (*argv[0] != 'e') {
smartscroll = 1;
getwinsize();
+
+ /* check if we are called as "vi" */
+ if (*argv[0] == 'v')
+ is_vi = true;
}
buffer = NULL;
@@ -420,18 +544,26 @@ static int do_edit(int argc, char *argv[])
lastscrline = scrline;
lastscrcol = 0;
- printf("%c[2J", 27);
+ printf("\x1b[2J");
pos(0, -1);
- printf("%c[7m %-25s <ctrl-d>: Save and quit <ctrl-c>: quit %c[0m",
- 27, argv[1], 27);
- printf("%c[2;%dr", 27, screenheight);
-
- screenheight--; /* status line */
+ if (is_vi) {
+ screenheight -= 2;
+ printf("\x1b[7m%*c\x1b[0m", screenwidth , ' ');
+ pos(0, screenheight-1);
+ printf("\x1b[7m%*c\x1b[0m", screenwidth , ' ');
+ printf("\r\x1b[7m%-25s\x1b[0m", argv[1]);
+ } else {
+ printf("\x1b[7m %-25s <ctrl-d>: Save and quit <ctrl-c>: quit \x1b[0m",
+ argv[1]);
+ }
+ printf("\x1b[2;%dr", screenheight);
pos(0, 0);
+ screenheight--; /* status line */
+
refresh(1);
while (1) {
@@ -469,7 +601,11 @@ static int do_edit(int argc, char *argv[])
lastscrline = scrline;
pos(cursx, cursy);
- c = read_key();
+again:
+ c = read_modal_key(is_vi);
+ if (c == -EAGAIN)
+ goto again;
+
switch (c) {
case BB_KEY_UP:
if (!curline->prev)
@@ -554,12 +690,12 @@ static int do_edit(int argc, char *argv[])
}
out:
free_buffer();
- printf("%c[2J%c[r", 27, 27);
+ printf("\x1b[2J\x1b[r");
printf("\n");
return ret;
}
-static const char * const edit_aliases[] = { "sedit", NULL};
+static const char * const edit_aliases[] = { "sedit", "vi", NULL};
BAREBOX_CMD_HELP_START(edit)
BAREBOX_CMD_HELP_TEXT("Use cursor keys, Ctrl-C to exit and Ctrl-D to exit-with-save.")
diff --git a/common/Kconfig b/common/Kconfig
index b840242..d397d8b 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -959,11 +959,11 @@ config STATE_CRYPTO
for more information.
config STATE_BACKWARD_COMPATIBLE
- bool "backward compatible 'direct storage backend'"
+ bool "backward compatible 'direct' storage backend"
depends on STATE
help
- With this option enabled the 'direct' storage backend keeps backward
- compatibility with older revisions of the state framework. Newer
+ With this option enabled, the 'direct' storage backend keeps backward
+ compatibility with the state framework of barebox <= v2016.08.0. Newer
revisions expect an additional 'meta header' and fail otherwise.
config BOOTCHOOSER
diff --git a/common/efi-devicepath.c b/common/efi-devicepath.c
index 2472228..3db2cea 100644
--- a/common/efi-devicepath.c
+++ b/common/efi-devicepath.c
@@ -572,7 +572,7 @@ dev_path_vendor(struct string *str, void *dev_path)
}
cprintf(str, "Ven%s(%pU", type, &Vendor->Guid);
- if (efi_compare_guid(&Vendor->Guid, &efi_unknown_device_guid) == 0) {
+ if (efi_guidcmp(Vendor->Guid, efi_unknown_device_guid) == 0) {
/* GUID used by EFI to enumerate an EDD 1.1 device */
unknown_dev_path =
(struct unknown_device_vendor_device_path *) Vendor;
diff --git a/common/efi-guid.c b/common/efi-guid.c
index 1e45ccf..2bf2395 100644
--- a/common/efi-guid.c
+++ b/common/efi-guid.c
@@ -52,7 +52,7 @@ const char *efi_guid_string(efi_guid_t *g)
EFI_GUID_STRING(EFI_ISA_IO_PROTOCOL_GUID, "ISA IO Protocol", "ISA IO Protocol");
EFI_GUID_STRING(EFI_STANDARD_ERROR_DEVICE_GUID, "Standard Error Device Guid", "EFI Standard Error Device Guid");
EFI_GUID_STRING(EFI_CONSOLE_OUT_DEVICE_GUID, "Console Out Device Guid", "EFI Console Out Device Guid");
- EFI_GUID_STRING(EFI_CONSOLE_IN_DEVICE_GUID, "Console In Device Guid", "EFI Conosle In Device Guid");
+ EFI_GUID_STRING(EFI_CONSOLE_IN_DEVICE_GUID, "Console In Device Guid", "EFI Console In Device Guid");
EFI_GUID_STRING(EFI_SIMPLE_TEXT_OUT_PROTOCOL_GUID, "Simple Text Out Protocol", "EFI 1.0 Simple Text Out Protocol");
EFI_GUID_STRING(EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL_GUID, "Simple Text Input Ex Protocol", "UEFI 2.1 Simple Text Input Ex Protocol");
EFI_GUID_STRING(EFI_SIMPLE_TEXT_IN_PROTOCOL_GUID, "Simple Text In Protocol", "EFI 1.0 Simple Text In Protocol");
diff --git a/common/efi/efi.c b/common/efi/efi.c
index a7b25cb..73cea37 100644
--- a/common/efi/efi.c
+++ b/common/efi/efi.c
@@ -17,6 +17,7 @@
*
*/
+#include <linux/linkage.h>
#include <common.h>
#include <linux/sizes.h>
#include <memory.h>
@@ -318,6 +319,8 @@ static int efi_init(void)
}
device_initcall(efi_init);
+asmlinkage efi_status_t efi_main(efi_handle_t, efi_system_table_t *);
+
/**
* efi-main - Entry point for EFI images
*/
diff --git a/common/partitions.c b/common/partitions.c
index 574b31f..4162e86 100644
--- a/common/partitions.c
+++ b/common/partitions.c
@@ -54,8 +54,8 @@ static int register_one_partition(struct block_device *blk,
partition_name = basprintf("%s.%d", blk->cdev.name, no);
if (!partition_name)
return -ENOMEM;
- dev_dbg(blk->dev, "Registering partition %s on drive %s\n",
- partition_name, blk->cdev.name);
+ dev_dbg(blk->dev, "Registering partition %s on drive %s (partuuid=%s)\n",
+ partition_name, blk->cdev.name, part->partuuid);
cdev = devfs_add_partition(blk->cdev.name,
start, size, 0, partition_name);
if (IS_ERR(cdev)) {
diff --git a/drivers/block/efi-block-io.c b/drivers/block/efi-block-io.c
index d167d81..39dbfb0 100644
--- a/drivers/block/efi-block-io.c
+++ b/drivers/block/efi-block-io.c
@@ -14,6 +14,7 @@
#include <disks.h>
#include <efi/efi.h>
#include <efi/efi-device.h>
+#include <bootsource.h>
#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001
#define EFI_BLOCK_IO_PROTOCOL_REVISION3 ((2<<16) | (31))
@@ -145,6 +146,7 @@ static int is_bio_usbdev(struct efi_device *efidev)
static int efi_bio_probe(struct efi_device *efidev)
{
int ret;
+ int instance;
struct efi_bio_priv *priv;
struct efi_block_io_media *media;
@@ -159,10 +161,14 @@ static int efi_bio_probe(struct efi_device *efidev)
efi_bio_print_info(priv);
priv->dev = &efidev->dev;
- if (is_bio_usbdev(efidev))
- priv->blk.cdev.name = xasprintf("usbdisk%d", cdev_find_free_index("usbdisk"));
- else
- priv->blk.cdev.name = xasprintf("disk%d", cdev_find_free_index("disk"));
+ if (is_bio_usbdev(efidev)) {
+ instance = cdev_find_free_index("usbdisk");
+ priv->blk.cdev.name = xasprintf("usbdisk%d", instance);
+ } else {
+ instance = cdev_find_free_index("disk");
+ priv->blk.cdev.name = xasprintf("disk%d", instance);
+ }
+
priv->blk.blockbits = ffs(media->block_size) - 1;
priv->blk.num_blocks = media->last_block + 1;
priv->blk.ops = &efi_bio_ops;
@@ -174,6 +180,9 @@ static int efi_bio_probe(struct efi_device *efidev)
if (ret)
return ret;
+ if (efi_get_bootsource() == efidev)
+ bootsource_set_instance(instance);
+
parse_partition_table(&priv->blk);
return 0;
diff --git a/drivers/efi/efi-device.c b/drivers/efi/efi-device.c
index 305d337..a1aac2d 100644
--- a/drivers/efi/efi-device.c
+++ b/drivers/efi/efi-device.c
@@ -311,7 +311,7 @@ static int efi_bus_match(struct device_d *dev, struct driver_d *drv)
int i;
for (i = 0; i < efidev->num_guids; i++) {
- if (!memcmp(&efidrv->guid, &efidev->guids[i], sizeof(efi_guid_t))) {
+ if (!efi_guidcmp(efidrv->guid, efidev->guids[i])) {
BS->handle_protocol(efidev->handle, &efidev->guids[i],
&efidev->protocol);
return 0;
@@ -398,13 +398,19 @@ static int is_bio_usbdev(struct efi_device *efidev)
return 0;
}
+static struct efi_device *bootdev;
+
+struct efi_device *efi_get_bootsource(void)
+{
+ return bootdev;
+}
+
static void efi_set_bootsource(void)
{
enum bootsource src = BOOTSOURCE_UNKNOWN;
int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
efi_handle_t *efi_parent;
- struct efi_device *bootdev;
if (!efi_loaded_image->parent_handle)
goto out;
diff --git a/drivers/hw_random/Kconfig b/drivers/hw_random/Kconfig
index c579282..242a7ef 100644
--- a/drivers/hw_random/Kconfig
+++ b/drivers/hw_random/Kconfig
@@ -15,11 +15,11 @@ config HWRNG_MXC_RNGC
Generator hardware found on some Freescale i.MX processors.
config HWRNG_DEV_RANDOM
- tristate "Linux /dev/random and /dev/urandom RNG"
+ tristate "Linux /dev/urandom RNG"
depends on SANDBOX
default y
help
- This driver allows use of the host provided /dev/random
- and /dev/urandom as barebox HWRNGs.
+ This driver allows use of the host provided /dev/urandom
+ as barebox HWRNGs.
endif
diff --git a/drivers/mfd/superio.c b/drivers/mfd/superio.c
index 0f08d56..12d74b4 100644
--- a/drivers/mfd/superio.c
+++ b/drivers/mfd/superio.c
@@ -88,7 +88,7 @@ void superio_chip_add(struct superio_chip *siochip)
&superio_regmap_config);
if (IS_ERR(regmap))
pr_warn("creating %s regmap failed: %s\n",
- chipname, strerror(-PTR_ERR(regmap)));
+ chipname, strerrorp(regmap));
ret = regmap_register_cdev(regmap, chipname);
if (ret)
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index 305f674..0a6a6bf 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -35,6 +35,7 @@ struct dw_eth_dev {
struct dw_eth_drvdata {
bool enh_desc;
+ void *priv;
};
struct dw_eth_dev *dwc_drv_probe(struct device_d *dev);
diff --git a/drivers/net/designware_socfpga.c b/drivers/net/designware_socfpga.c
index 77157c2..ce3ac38 100644
--- a/drivers/net/designware_socfpga.c
+++ b/drivers/net/designware_socfpga.c
@@ -14,11 +14,27 @@
#include <net.h>
#include <of_net.h>
#include <linux/reset.h>
-#include <mach/cyclone5-system-manager.h>
#include <mfd/syscon.h>
#include "designware.h"
-#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
+#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010
+#define SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000100
+
+#define SYSMGR_FPGAGRP_MODULE 0x00000028
+#define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004
+#define SYSMGR_FPGAINTF_EMAC_REG 0x00000070
+#define SYSMGR_FPGAINTF_EMAC_BIT 0x1
+
+struct socfpga_dwc_dev;
+struct socfpga_dwmac_ops {
+ int (*set_phy_mode)(struct socfpga_dwc_dev *dwmac_priv);
+};
struct socfpga_dwc_dev {
struct dw_eth_dev *priv;
@@ -26,27 +42,36 @@ struct socfpga_dwc_dev {
u32 reg_shift;
void __iomem *sys_mgr_base;
bool f2h_ptp_ref_clk;
+ const struct socfpga_dwmac_ops *ops;
};
-static int socfpga_dwc_set_phy_mode(struct socfpga_dwc_dev *dwc_dev)
+static int socfpga_set_phy_mode_common(int phymode, u32 *val)
{
- struct dw_eth_dev *eth_dev = dwc_dev->priv;
- int phymode = eth_dev->interface;
- u32 reg_offset = dwc_dev->reg_offset;
- u32 reg_shift = dwc_dev->reg_shift;
- u32 ctrl, val;
-
switch (phymode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
- val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+ *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
break;
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
case PHY_INTERFACE_MODE_SGMII:
- val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+ *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
break;
default:
+ return -EINVAL;
+ }
+ return 0;
+};
+
+static int socfpga_gen5_set_phy_mode(struct socfpga_dwc_dev *dwc_dev)
+{
+ struct dw_eth_dev *eth_dev = dwc_dev->priv;
+ int phymode = eth_dev->interface;
+ u32 reg_offset = dwc_dev->reg_offset;
+ u32 reg_shift = dwc_dev->reg_shift;
+ u32 ctrl, val;
+
+ if (socfpga_set_phy_mode_common(phymode, &val)) {
dev_err(&eth_dev->netdev.dev, "bad phy mode %d\n", phymode);
return -EINVAL;
}
@@ -85,6 +110,54 @@ static int socfpga_dwc_set_phy_mode(struct socfpga_dwc_dev *dwc_dev)
return 0;
}
+static int socfpga_gen10_set_phy_mode(struct socfpga_dwc_dev *dwc_dev)
+{
+ struct dw_eth_dev *eth_dev = dwc_dev->priv;
+ int phymode = eth_dev->interface;
+ u32 reg_offset = dwc_dev->reg_offset;
+ u32 reg_shift = dwc_dev->reg_shift;
+ u32 ctrl, val;
+
+ if (socfpga_set_phy_mode_common(phymode, &val)) {
+ dev_err(&eth_dev->netdev.dev, "bad phy mode %d\n", phymode);
+ return -EINVAL;
+ }
+
+ /* Assert reset to the enet controller before changing the phy mode */
+ if (eth_dev->rst)
+ reset_control_assert(eth_dev->rst);
+
+ ctrl = readl(dwc_dev->sys_mgr_base + reg_offset);
+ ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
+ ctrl |= val << reg_shift;
+
+ if (dwc_dev->f2h_ptp_ref_clk ||
+ phymode == PHY_INTERFACE_MODE_MII ||
+ phymode == PHY_INTERFACE_MODE_GMII ||
+ phymode == PHY_INTERFACE_MODE_SGMII) {
+ u32 module;
+
+ ctrl |= SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK;
+ module = readl(dwc_dev->sys_mgr_base + SYSMGR_FPGAINTF_EMAC_REG);
+ module |= (SYSMGR_FPGAINTF_EMAC_BIT << reg_shift);
+
+ writel(module, dwc_dev->sys_mgr_base + SYSMGR_FPGAINTF_EMAC_REG);
+ } else {
+ ctrl &= ~SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK;
+ }
+
+ writel(ctrl, dwc_dev->sys_mgr_base + reg_offset);
+
+ /* Deassert reset for the phy configuration to be sampled by
+ * the enet controller, and operation to start in requested mode
+ */
+ if (eth_dev->rst)
+ reset_control_deassert(eth_dev->rst);
+
+ return 0;
+}
+
+
static int socfpga_dwc_probe_dt(struct device_d *dev, struct socfpga_dwc_dev *priv)
{
u32 reg_offset, reg_shift;
@@ -120,11 +193,21 @@ static int socfpga_dwc_ether_probe(struct device_d *dev)
{
struct socfpga_dwc_dev *dwc_dev;
struct dw_eth_dev *priv;
+ struct dw_eth_drvdata *drvdata;
int ret;
dwc_dev = xzalloc(sizeof(*dwc_dev));
- priv = dwc_drv_probe(dev);
+ ret = dev_get_drvdata(dev, (const void **)&drvdata);
+ if (ret)
+ return ret;
+
+ if (drvdata && drvdata->priv)
+ dwc_dev->ops = (struct socfpga_dwmac_ops *)drvdata->priv;
+ else
+ return -EINVAL;
+
+ priv = dwc_drv_probe(dev);
if (IS_ERR(priv))
return PTR_ERR(priv);
@@ -145,18 +228,36 @@ static int socfpga_dwc_ether_probe(struct device_d *dev)
if (ret)
return ret;
- return socfpga_dwc_set_phy_mode(dwc_dev);
+ return dwc_dev->ops->set_phy_mode(dwc_dev);
}
-static struct dw_eth_drvdata socfpga_stmmac_drvdata = {
+static struct socfpga_dwmac_ops socfpga_gen5_ops = {
+ .set_phy_mode = socfpga_gen5_set_phy_mode,
+};
+
+static const struct dw_eth_drvdata socfpga_gen5_drvdata = {
.enh_desc = 1,
+ .priv = &socfpga_gen5_ops,
+};
+
+static struct socfpga_dwmac_ops socfpga_gen10_ops = {
+ .set_phy_mode = socfpga_gen10_set_phy_mode,
+};
+static const struct dw_eth_drvdata socfpga_gen10_drvdata = {
+ .enh_desc = 1,
+ .priv = &socfpga_gen10_ops,
};
static __maybe_unused struct of_device_id socfpga_dwc_ether_compatible[] = {
{
.compatible = "altr,socfpga-stmmac",
- .data = &socfpga_stmmac_drvdata,
- }, {
+ .data = &socfpga_gen5_drvdata,
+ },
+ {
+ .compatible = "altr,socfpga-stmmac-a10-s10",
+ .data = &socfpga_gen10_drvdata,
+ },
+ {
/* sentinel */
}
};
diff --git a/drivers/of/of_gpio.c b/drivers/of/of_gpio.c
index 9a8331e..7cbeeaf 100644
--- a/drivers/of/of_gpio.c
+++ b/drivers/of/of_gpio.c
@@ -19,18 +19,20 @@ static void of_gpio_flags_quirks(struct device_node *np,
(!(strcmp(propname, "enable-gpio") &&
strcmp(propname, "enable-gpios")) &&
of_device_is_compatible(np, "regulator-gpio")))) {
+ bool active_low = !of_property_read_bool(np,
+ "enable-active-high");
/*
* The regulator GPIO handles are specified such that the
* presence or absence of "enable-active-high" solely controls
* the polarity of the GPIO line. Any phandle flags must
* be actively ignored.
*/
- if (*flags & OF_GPIO_ACTIVE_LOW) {
+ if ((*flags & OF_GPIO_ACTIVE_LOW) && !active_low) {
pr_warn("%s GPIO handle specifies active low - ignored\n",
np->full_name);
*flags &= ~OF_GPIO_ACTIVE_LOW;
}
- if (!of_property_read_bool(np, "enable-active-high"))
+ if (active_low)
*flags |= OF_GPIO_ACTIVE_LOW;
}
}
diff --git a/drivers/of/of_path.c b/drivers/of/of_path.c
index f8bbf2c..5c3a020 100644
--- a/drivers/of/of_path.c
+++ b/drivers/of/of_path.c
@@ -83,7 +83,7 @@ static int __of_find_path(struct device_node *node, const char *part, char **out
}
if (dev->bus && !dev->driver)
- return -ENODEV;
+ return -EPROBE_DEFER;
device_detect(dev);
diff --git a/drivers/serial/efi-stdio.c b/drivers/serial/efi-stdio.c
index 2ca89fa..9e82518 100644
--- a/drivers/serial/efi-stdio.c
+++ b/drivers/serial/efi-stdio.c
@@ -26,6 +26,8 @@
#include <readkey.h>
#include <linux/ctype.h>
#include <efi/efi.h>
+#include <efi/efi-device.h>
+#include "efi-stdio.h"
#define EFI_SHIFT_STATE_VALID 0x80000000
#define EFI_RIGHT_CONTROL_PRESSED 0x00000004
@@ -71,6 +73,7 @@
struct efi_console_priv {
struct efi_simple_text_output_protocol *out;
struct efi_simple_input_interface *in;
+ struct efi_simple_text_input_ex_protocol *inex;
struct console_device cdev;
int lastkey;
u16 efi_console_buffer[CONFIG_CBSIZE];
@@ -105,35 +108,72 @@ static struct efi_ctrlkey ctrlkeys[] = {
{ 0x17, 27 /* escape key */ },
};
+static int xlate_keypress(struct efi_input_key *k)
+{
+ int i;
+
+ /* 32 bit modifier keys + 16 bit scan code + 16 bit unicode */
+ for (i = 0; i < ARRAY_SIZE(ctrlkeys); i++) {
+ if (ctrlkeys[i].scan_code == k->scan_code)
+ return ctrlkeys[i].bb_key;
+
+ }
+
+ return k->unicode_char & 0xff;
+}
+
static int efi_read_key(struct efi_console_priv *priv, bool wait)
{
unsigned long index;
efi_status_t efiret;
- struct efi_input_key k;
- int i;
+ struct efi_key_data kd;
/* wait until key is pressed */
if (wait)
BS->wait_for_event(1, priv->in->wait_for_key, &index);
- efiret = priv->in->read_key_stroke(efi_sys_table->con_in, &k);
- if (EFI_ERROR(efiret))
- return -efi_errno(efiret);
+ if (priv->inex) {
+ efiret = priv->inex->read_key_stroke_ex(priv->inex, &kd);
- /* 32 bit modifier keys + 16 bit scan code + 16 bit unicode */
- for (i = 0; i < ARRAY_SIZE(ctrlkeys); i++) {
- if (ctrlkeys[i].scan_code == k.scan_code)
- return ctrlkeys[i].bb_key;
+ if (efiret == EFI_NOT_READY)
+ return -EAGAIN;
+
+ if (!EFI_ERROR(efiret)) {
+ if ((kd.state.shift_state & EFI_SHIFT_STATE_VALID) &&
+ (kd.state.shift_state & EFI_CONTROL_PRESSED)) {
+ int ch = tolower(kd.key.unicode_char & 0xff);
+
+ if (isalpha(ch))
+ return CHAR_CTRL(ch);
+ if (ch == '\0') /* ctrl is pressed on its own */
+ return -EAGAIN;
+ }
+
+ if (kd.key.unicode_char || kd.key.scan_code)
+ return xlate_keypress(&kd.key);
+ /* Some broken firmwares offer simple_text_input_ex_protocol,
+ * but never handle any key. Treat those as if
+ * read_key_stroke_ex failed and fall through
+ * to the basic simple_text_input_protocol.
+ */
+ dev_dbg(priv->cdev.dev, "Falling back to simple_text_input_protocol\n");
+ }
}
- return k.unicode_char & 0xff;
+ efiret = priv->in->read_key_stroke(priv->in, &kd.key);
+
+ if (EFI_ERROR(efiret))
+ return -efi_errno(efiret);
+
+ return xlate_keypress(&kd.key);
}
static void efi_console_putc(struct console_device *cdev, char c)
{
uint16_t str[2] = {};
- struct efi_simple_text_output_protocol *con_out = efi_sys_table->con_out;
+ struct efi_console_priv *priv = to_efi(cdev);
+ struct efi_simple_text_output_protocol *con_out = priv->out;
str[0] = c;
@@ -331,8 +371,12 @@ static void efi_set_mode(struct efi_console_priv *priv)
static int efi_console_probe(struct device_d *dev)
{
+ efi_guid_t inex_guid = EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL_GUID;
+ struct efi_simple_text_input_ex_protocol *inex;
struct console_device *cdev;
struct efi_console_priv *priv;
+ efi_status_t efiret;
+
int i;
priv = xzalloc(sizeof(*priv));
@@ -340,6 +384,18 @@ static int efi_console_probe(struct device_d *dev)
priv->out = efi_sys_table->con_out;
priv->in = efi_sys_table->con_in;
+ efiret = BS->open_protocol((void *)efi_sys_table->con_in_handle,
+ &inex_guid,
+ (void **)&inex,
+ efi_parent_image,
+ 0,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+
+ if (!EFI_ERROR(efiret)) {
+ priv->inex = inex;
+ dev_dbg(dev, "Using simple_text_input_ex_protocol\n");
+ }
+
priv->current_color = EFI_WHITE;
efi_set_mode(priv);
diff --git a/drivers/serial/efi-stdio.h b/drivers/serial/efi-stdio.h
new file mode 100644
index 0000000..1fa417c
--- /dev/null
+++ b/drivers/serial/efi-stdio.h
@@ -0,0 +1,58 @@
+#ifndef EFI_STDIO_H_
+#define EFI_STDIO_H_
+
+#include <efi.h>
+
+struct efi_simple_text_input_ex_protocol;
+
+typedef efi_status_t (EFIAPI *efi_input_reset_ex)(
+ struct efi_simple_text_input_ex_protocol *this,
+ efi_bool_t extended_verification
+);
+
+struct efi_key_state {
+ u32 shift_state;
+ u8 toggle_state;
+};
+
+struct efi_key_data {
+ struct efi_input_key key;
+ struct efi_key_state state;
+};
+
+typedef efi_status_t (EFIAPI *efi_input_read_key_ex)(
+ struct efi_simple_text_input_ex_protocol *this,
+ struct efi_key_data *keydata
+);
+
+typedef efi_status_t (EFIAPI *efi_set_state)(
+ struct efi_simple_text_input_ex_protocol *this,
+ u8 *key_toggle_state
+);
+
+typedef efi_status_t (EFIAPI *efi_key_notify_function)(
+ struct efi_key_data *keydata
+);
+
+typedef efi_status_t (EFIAPI *efi_register_keystroke_notify)(
+ struct efi_simple_text_input_ex_protocol *this,
+ struct efi_key_data keydata,
+ efi_key_notify_function key_notification_function,
+ void **notify_handle
+);
+
+typedef efi_status_t (EFIAPI *efi_unregister_keystroke_notify)(
+ struct efi_simple_text_input_ex_protocol *this,
+ void *notification_handle
+);
+
+struct efi_simple_text_input_ex_protocol {
+ efi_input_reset_ex reset;
+ efi_input_read_key_ex read_key_stroke_ex;
+ void *wait_for_key_ex;
+ efi_set_state set_state;
+ efi_register_keystroke_notify register_key_notify;
+ efi_unregister_keystroke_notify unregister_key_notify;
+};
+
+#endif
diff --git a/drivers/usb/storage/usb.c b/drivers/usb/storage/usb.c
index 63d624e..e0ef4f5 100644
--- a/drivers/usb/storage/usb.c
+++ b/drivers/usb/storage/usb.c
@@ -87,8 +87,7 @@ static int usb_stor_transport(struct us_blk_dev *usb_blkdev,
struct device_d *dev = &us->pusb_dev->dev;
int i, ret;
-
- for (i = 0; i < retries; i++) {
+ for (i = 0; i <= retries; i++) {
dev_dbg(dev, "%s\n", usb_stor_opcode_name(cmd[0]));
ret = us->transport(usb_blkdev, cmd, cmdlen, data, datalen);
dev_dbg(dev, "%s returns %d\n", usb_stor_opcode_name(cmd[0]),
@@ -105,6 +104,8 @@ static int usb_stor_transport(struct us_blk_dev *usb_blkdev,
mdelay(request_sense_delay_ms);
}
+ dev_dbg(dev, "Retried %s %d times, and failed.\n", usb_stor_opcode_name(cmd[0]), retries);
+
return -EIO;
}
@@ -194,7 +195,7 @@ static int usb_stor_io_10(struct us_blk_dev *usb_blkdev, u8 opcode,
put_unaligned_be16(blocks, &cmd[7]);
return usb_stor_transport(usb_blkdev, cmd, sizeof(cmd), data,
- blocks * SECTOR_SIZE, 2, 0);
+ blocks * SECTOR_SIZE, 10, 0);
}
/***********************************************************************
diff --git a/dts/Bindings/arm/rockchip.yaml b/dts/Bindings/arm/rockchip.yaml
index c82c5e5..9c7e703 100644
--- a/dts/Bindings/arm/rockchip.yaml
+++ b/dts/Bindings/arm/rockchip.yaml
@@ -496,12 +496,12 @@ properties:
- description: Theobroma Systems RK3368-uQ7 with Haikou baseboard
items:
- - const: tsd,rk3368-uq7-haikou
+ - const: tsd,rk3368-lion-haikou
- const: rockchip,rk3368
- description: Theobroma Systems RK3399-Q7 with Haikou baseboard
items:
- - const: tsd,rk3399-q7-haikou
+ - const: tsd,rk3399-puma-haikou
- const: rockchip,rk3399
- description: Tronsmart Orion R68 Meta
diff --git a/dts/Bindings/interrupt-controller/atmel,aic.txt b/dts/Bindings/interrupt-controller/atmel,aic.txt
index f4c5d34..7079d44 100644
--- a/dts/Bindings/interrupt-controller/atmel,aic.txt
+++ b/dts/Bindings/interrupt-controller/atmel,aic.txt
@@ -1,8 +1,11 @@
* Advanced Interrupt Controller (AIC)
Required properties:
-- compatible: Should be "atmel,<chip>-aic"
- <chip> can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4"
+- compatible: Should be:
+ - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
+ "sama5d3" or "sama5d4"
+ - "microchip,<chip>-aic" where <chip> can be "sam9x60"
+
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
diff --git a/dts/Bindings/media/allwinner,sun4i-a10-csi.yaml b/dts/Bindings/media/allwinner,sun4i-a10-csi.yaml
index 27f38ee..d3e423f 100644
--- a/dts/Bindings/media/allwinner,sun4i-a10-csi.yaml
+++ b/dts/Bindings/media/allwinner,sun4i-a10-csi.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/allwinner,sun4i-a10-csi.yaml#
+$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 CMOS Sensor Interface (CSI) Device Tree Bindings
@@ -27,14 +27,12 @@ properties:
clocks:
items:
- description: The CSI interface clock
- - description: The CSI module clock
- description: The CSI ISP clock
- description: The CSI DRAM clock
clock-names:
items:
- const: bus
- - const: mod
- const: isp
- const: ram
@@ -89,9 +87,8 @@ examples:
compatible = "allwinner,sun7i-a20-csi0";
reg = <0x01c09000 0x1000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
- <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
- clock-names = "bus", "mod", "isp", "ram";
+ clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
+ clock-names = "bus", "isp", "ram";
resets = <&ccu RST_CSI0>;
port {
diff --git a/dts/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/dts/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
index f83d888..064b7df 100644
--- a/dts/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
+++ b/dts/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
@@ -33,13 +33,13 @@ patternProperties:
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
- ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI,
- ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1,
- GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2,
- GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12,
- I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7,
- I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC,
- LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2,
+ ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC,
+ ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0,
+ GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
+ GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11,
+ I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6,
+ I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
+ LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2,
MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2,
NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3,
NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1,
@@ -48,47 +48,45 @@ patternProperties:
PWM8, PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3,
RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12,
SALT13, SALT14, SALT15, SALT16, SALT2, SALT3, SALT4, SALT5,
- SALT6, SALT7, SALT8, SALT9, SD1, SD2, SD3, SD3DAT4, SD3DAT5,
- SD3DAT6, SD3DAT7, SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO,
- SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1,
- SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
- TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5,
- TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1,
- TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13, UART6, UART7,
- UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
- WDTRST4, ]
+ SALT6, SALT7, SALT8, SALT9, SD1, SD2, SGPM1, SGPS1, SIOONCTRL,
+ SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
+ SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1,
+ TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
+ TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
+ THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13,
+ UART6, UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
+ WDTRST3, WDTRST4, ]
groups:
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
- ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI,
- ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWQSPID, FWSPIWP, GPIT0,
- GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
- GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1,
- I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3,
- I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6,
- JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
- MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3,
- MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
- NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1,
- NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE,
- PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0, PWM12G1,
- PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2, PWM3,
- PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
- QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3,
- RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1,
- SALT11G0, SALT11G1, SALT12G0, SALT12G1, SALT13G0, SALT13G1,
- SALT14G0, SALT14G1, SALT15G0, SALT15G1, SALT16G0, SALT16G1,
- SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9G0,
- SALT9G1, SD1, SD2, SD3, SD3DAT4, SD3DAT5, SD3DAT6, SD3DAT7,
- SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD,
- SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
- SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13,
- TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8,
- TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4,
- UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
- UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
- WDTRST4, ]
+ ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1,
+ EMMCG4, EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID,
+ FWQSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5,
+ GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5, GPIU6,
+ GPIU7, HVI3C3, HVI3C4, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14,
+ I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9,
+ I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD,
+ LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3, MACLINK4,
+ MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1,
+ NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
+ NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
+ OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1,
+ PWM12G0, PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0,
+ PWM15G1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1,
+ PWM9G0, PWM9G1, QSPI1, QSPI2, RGMII1, RGMII2, RGMII3, RGMII4,
+ RMII1, RMII2, RMII3, RMII4, RXD1, RXD2, RXD3, RXD4, SALT1,
+ SALT10G0, SALT10G1, SALT11G0, SALT11G1, SALT12G0, SALT12G1,
+ SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0, SALT15G1,
+ SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7,
+ SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPS1, SIOONCTRL,
+ SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
+ SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1,
+ TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
+ TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
+ THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0,
+ UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, VB,
+ VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ]
required:
- compatible
diff --git a/dts/Bindings/regulator/fixed-regulator.yaml b/dts/Bindings/regulator/fixed-regulator.yaml
index a78150c..f324169 100644
--- a/dts/Bindings/regulator/fixed-regulator.yaml
+++ b/dts/Bindings/regulator/fixed-regulator.yaml
@@ -30,8 +30,8 @@ if:
properties:
compatible:
enum:
- - const: regulator-fixed
- - const: regulator-fixed-clock
+ - regulator-fixed
+ - regulator-fixed-clock
regulator-name: true
diff --git a/dts/Bindings/riscv/cpus.yaml b/dts/Bindings/riscv/cpus.yaml
index b261a30..04819ad 100644
--- a/dts/Bindings/riscv/cpus.yaml
+++ b/dts/Bindings/riscv/cpus.yaml
@@ -24,15 +24,17 @@ description: |
properties:
compatible:
- items:
- - enum:
- - sifive,rocket0
- - sifive,e5
- - sifive,e51
- - sifive,u54-mc
- - sifive,u54
- - sifive,u5
- - const: riscv
+ oneOf:
+ - items:
+ - enum:
+ - sifive,rocket0
+ - sifive,e5
+ - sifive,e51
+ - sifive,u54-mc
+ - sifive,u54
+ - sifive,u5
+ - const: riscv
+ - const: riscv # Simulator only
description:
Identifies that the hart uses the RISC-V instruction set
and identifies the type of the hart.
@@ -66,12 +68,8 @@ properties:
insensitive, letters in the riscv,isa string must be all
lowercase to simplify parsing.
- timebase-frequency:
- type: integer
- minimum: 1
- description:
- Specifies the clock frequency of the system timer in Hz.
- This value is common to all harts on a single system image.
+ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
+ timebase-frequency: false
interrupt-controller:
type: object
@@ -93,7 +91,6 @@ properties:
required:
- riscv,isa
- - timebase-frequency
- interrupt-controller
examples:
diff --git a/dts/src/arc/hsdk.dts b/dts/src/arc/hsdk.dts
index bfc7f5f..9acbeba 100644
--- a/dts/src/arc/hsdk.dts
+++ b/dts/src/arc/hsdk.dts
@@ -65,6 +65,14 @@
clock-frequency = <33333333>;
};
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "5v0-supply";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
cpu_intc: cpu-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
@@ -264,6 +272,21 @@
clocks = <&input_clk>;
cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
<&creg_gpio 1 GPIO_ACTIVE_LOW>;
+
+ spi-flash@0 {
+ compatible = "sst26wf016b", "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <4000000>;
+ };
+
+ adc@1 {
+ compatible = "ti,adc108s102";
+ reg = <1>;
+ vref-supply = <&reg_5v0>;
+ spi-max-frequency = <1000000>;
+ };
};
creg_gpio: gpio@14b0 {
diff --git a/dts/src/arm/am3874-iceboard.dts b/dts/src/arm/am3874-iceboard.dts
index 883fb85..1b4b2b0 100644
--- a/dts/src/arm/am3874-iceboard.dts
+++ b/dts/src/arm/am3874-iceboard.dts
@@ -111,13 +111,13 @@
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-mux-idle-disconnect;
i2c@0 {
/* FMC A */
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
- i2c-mux-idle-disconnect;
};
i2c@1 {
@@ -125,7 +125,6 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
- i2c-mux-idle-disconnect;
};
i2c@2 {
@@ -133,7 +132,6 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
- i2c-mux-idle-disconnect;
};
i2c@3 {
@@ -141,7 +139,6 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
- i2c-mux-idle-disconnect;
};
i2c@4 {
@@ -149,14 +146,12 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
- i2c-mux-idle-disconnect;
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
- i2c-mux-idle-disconnect;
ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; };
ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; };
@@ -182,14 +177,12 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
- i2c-mux-idle-disconnect;
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
- i2c-mux-idle-disconnect;
u41: pca9575@20 {
compatible = "nxp,pca9575";
diff --git a/dts/src/arm/bcm2835-rpi-zero-w.dts b/dts/src/arm/bcm2835-rpi-zero-w.dts
index 09a088f..b75af21 100644
--- a/dts/src/arm/bcm2835-rpi-zero-w.dts
+++ b/dts/src/arm/bcm2835-rpi-zero-w.dts
@@ -113,6 +113,7 @@
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
+ bus-width = <4>;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
status = "okay";
diff --git a/dts/src/arm/bcm2837-rpi-cm3.dtsi b/dts/src/arm/bcm2837-rpi-cm3.dtsi
index 7c3cb7e..925cb37 100644
--- a/dts/src/arm/bcm2837-rpi-cm3.dtsi
+++ b/dts/src/arm/bcm2837-rpi-cm3.dtsi
@@ -9,6 +9,14 @@
reg = <0 0x40000000>;
};
+ leds {
+ /*
+ * Since there is no upstream GPIO driver yet,
+ * remove the incomplete node.
+ */
+ /delete-node/ act;
+ };
+
reg_3v3: fixed-regulator {
compatible = "regulator-fixed";
regulator-name = "3V3";
diff --git a/dts/src/arm/imx6-logicpd-som.dtsi b/dts/src/arm/imx6-logicpd-som.dtsi
index 7ceae35..547fb14 100644
--- a/dts/src/arm/imx6-logicpd-som.dtsi
+++ b/dts/src/arm/imx6-logicpd-som.dtsi
@@ -207,6 +207,10 @@
vin-supply = <&sw1c_reg>;
};
+&snvs_poweroff {
+ status = "okay";
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
diff --git a/dts/src/arm/imx7s.dtsi b/dts/src/arm/imx7s.dtsi
index 710f850..e2e604d 100644
--- a/dts/src/arm/imx7s.dtsi
+++ b/dts/src/arm/imx7s.dtsi
@@ -448,7 +448,7 @@
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302d0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_CLK_DUMMY>,
+ clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
<&clks IMX7D_GPT1_ROOT_CLK>;
clock-names = "ipg", "per";
};
@@ -457,7 +457,7 @@
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302e0000 0x10000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_CLK_DUMMY>,
+ clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
<&clks IMX7D_GPT2_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
@@ -467,7 +467,7 @@
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302f0000 0x10000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_CLK_DUMMY>,
+ clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
<&clks IMX7D_GPT3_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
@@ -477,7 +477,7 @@
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x30300000 0x10000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_CLK_DUMMY>,
+ clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
<&clks IMX7D_GPT4_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
diff --git a/dts/src/arm/logicpd-torpedo-som.dtsi b/dts/src/arm/logicpd-torpedo-som.dtsi
index 3fdd0a7..506b118 100644
--- a/dts/src/arm/logicpd-torpedo-som.dtsi
+++ b/dts/src/arm/logicpd-torpedo-som.dtsi
@@ -192,3 +192,7 @@
&twl_gpio {
ti,use-leds;
};
+
+&twl_keypad {
+ status = "disabled";
+};
diff --git a/dts/src/arm/mt7629-rfb.dts b/dts/src/arm/mt7629-rfb.dts
index 3621b7d..9980c10 100644
--- a/dts/src/arm/mt7629-rfb.dts
+++ b/dts/src/arm/mt7629-rfb.dts
@@ -66,9 +66,21 @@
pinctrl-1 = <&ephy_leds_pins>;
status = "okay";
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
+ phy-mode = "gmii";
phy-handle = <&phy0>;
};
@@ -78,7 +90,6 @@
phy0: ethernet-phy@0 {
reg = <0>;
- phy-mode = "gmii";
};
};
};
diff --git a/dts/src/arm/mt7629.dtsi b/dts/src/arm/mt7629.dtsi
index 9608bc2..867b881 100644
--- a/dts/src/arm/mt7629.dtsi
+++ b/dts/src/arm/mt7629.dtsi
@@ -468,14 +468,12 @@
compatible = "mediatek,mt7629-sgmiisys", "syscon";
reg = <0x1b128000 0x3000>;
#clock-cells = <1>;
- mediatek,physpeed = "2500";
};
sgmiisys1: syscon@1b130000 {
compatible = "mediatek,mt7629-sgmiisys", "syscon";
reg = <0x1b130000 0x3000>;
#clock-cells = <1>;
- mediatek,physpeed = "2500";
};
};
};
diff --git a/dts/src/arm/omap4-droid4-xt894.dts b/dts/src/arm/omap4-droid4-xt894.dts
index 4454449..a40fe8d 100644
--- a/dts/src/arm/omap4-droid4-xt894.dts
+++ b/dts/src/arm/omap4-droid4-xt894.dts
@@ -369,7 +369,7 @@
compatible = "ti,wl1285", "ti,wl1283";
reg = <2>;
/* gpio_100 with gpmc_wait2 pad as wakeirq */
- interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>,
+ interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>,
<&omap4_pmx_core 0x4e>;
interrupt-names = "irq", "wakeup";
ref-clock-frequency = <26000000>;
diff --git a/dts/src/arm/omap4-panda-common.dtsi b/dts/src/arm/omap4-panda-common.dtsi
index 14be2ec..55ea8b6 100644
--- a/dts/src/arm/omap4-panda-common.dtsi
+++ b/dts/src/arm/omap4-panda-common.dtsi
@@ -474,7 +474,7 @@
compatible = "ti,wl1271";
reg = <2>;
/* gpio_53 with gpmc_ncs3 pad as wakeup */
- interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_RISING>,
+ interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_HIGH>,
<&omap4_pmx_core 0x3a>;
interrupt-names = "irq", "wakeup";
ref-clock-frequency = <38400000>;
diff --git a/dts/src/arm/omap4-sdp.dts b/dts/src/arm/omap4-sdp.dts
index 3c27496..91480ac 100644
--- a/dts/src/arm/omap4-sdp.dts
+++ b/dts/src/arm/omap4-sdp.dts
@@ -512,7 +512,7 @@
compatible = "ti,wl1281";
reg = <2>;
interrupt-parent = <&gpio1>;
- interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
ref-clock-frequency = <26000000>;
tcxo-clock-frequency = <26000000>;
};
diff --git a/dts/src/arm/omap4-var-som-om44-wlan.dtsi b/dts/src/arm/omap4-var-som-om44-wlan.dtsi
index 6dbbc9b..d003221 100644
--- a/dts/src/arm/omap4-var-som-om44-wlan.dtsi
+++ b/dts/src/arm/omap4-var-som-om44-wlan.dtsi
@@ -69,7 +69,7 @@
compatible = "ti,wl1271";
reg = <2>;
interrupt-parent = <&gpio2>;
- interrupts = <9 IRQ_TYPE_EDGE_RISING>; /* gpio 41 */
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */
ref-clock-frequency = <38400000>;
};
};
diff --git a/dts/src/arm/omap5-board-common.dtsi b/dts/src/arm/omap5-board-common.dtsi
index 7fff555..68ac046 100644
--- a/dts/src/arm/omap5-board-common.dtsi
+++ b/dts/src/arm/omap5-board-common.dtsi
@@ -362,7 +362,7 @@
pinctrl-names = "default";
pinctrl-0 = <&wlcore_irq_pin>;
interrupt-parent = <&gpio1>;
- interrupts = <14 IRQ_TYPE_EDGE_RISING>; /* gpio 14 */
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */
ref-clock-frequency = <26000000>;
};
};
diff --git a/dts/src/arm/omap54xx-clocks.dtsi b/dts/src/arm/omap54xx-clocks.dtsi
index fac2e57..4791834 100644
--- a/dts/src/arm/omap54xx-clocks.dtsi
+++ b/dts/src/arm/omap54xx-clocks.dtsi
@@ -1146,7 +1146,7 @@
};
};
- gpu_cm: clock-controller@1500 {
+ gpu_cm: gpu_cm@1500 {
compatible = "ti,omap4-cm";
reg = <0x1500 0x100>;
#address-cells = <1>;
diff --git a/dts/src/arm/stm32mp157-pinctrl.dtsi b/dts/src/arm/stm32mp157-pinctrl.dtsi
index e4a0d51..0a3a7d6 100644
--- a/dts/src/arm/stm32mp157-pinctrl.dtsi
+++ b/dts/src/arm/stm32mp157-pinctrl.dtsi
@@ -609,13 +609,13 @@
<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
bias-pull-up;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <1>;
};
};
@@ -637,13 +637,13 @@
<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
bias-pull-up;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <1>;
};
};
diff --git a/dts/src/arm/sun7i-a20.dtsi b/dts/src/arm/sun7i-a20.dtsi
index 874231b..8aebefd 100644
--- a/dts/src/arm/sun7i-a20.dtsi
+++ b/dts/src/arm/sun7i-a20.dtsi
@@ -380,9 +380,8 @@
compatible = "allwinner,sun7i-a20-csi0";
reg = <0x01c09000 0x1000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
- <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
- clock-names = "bus", "mod", "isp", "ram";
+ clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
+ clock-names = "bus", "isp", "ram";
resets = <&ccu RST_CSI0>;
status = "disabled";
};
diff --git a/dts/src/arm/vf610-zii-scu4-aib.dts b/dts/src/arm/vf610-zii-scu4-aib.dts
index dc8a5f3..c8ebb23 100644
--- a/dts/src/arm/vf610-zii-scu4-aib.dts
+++ b/dts/src/arm/vf610-zii-scu4-aib.dts
@@ -602,6 +602,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
+ i2c-mux-idle-disconnect;
sff0_i2c: i2c@1 {
#address-cells = <1>;
@@ -640,6 +641,7 @@
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
+ i2c-mux-idle-disconnect;
sff5_i2c: i2c@1 {
#address-cells = <1>;
diff --git a/dts/src/arm64/allwinner/sun50i-a64-pine64-plus.dts b/dts/src/arm64/allwinner/sun50i-a64-pine64-plus.dts
index 24f1aac..d5b6e81 100644
--- a/dts/src/arm64/allwinner/sun50i-a64-pine64-plus.dts
+++ b/dts/src/arm64/allwinner/sun50i-a64-pine64-plus.dts
@@ -63,3 +63,12 @@
reg = <1>;
};
};
+
+&reg_dc1sw {
+ /*
+ * Ethernet PHY needs 30ms to properly power up and some more
+ * to initialize. 100ms should be plenty of time to finish
+ * whole process.
+ */
+ regulator-enable-ramp-delay = <100000>;
+};
diff --git a/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts b/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
index e6fb968..2509920 100644
--- a/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -159,6 +159,12 @@
};
&reg_dc1sw {
+ /*
+ * Ethernet PHY needs 30ms to properly power up and some more
+ * to initialize. 100ms should be plenty of time to finish
+ * whole process.
+ */
+ regulator-enable-ramp-delay = <100000>;
regulator-name = "vcc-phy";
};
diff --git a/dts/src/arm64/allwinner/sun50i-a64.dtsi b/dts/src/arm64/allwinner/sun50i-a64.dtsi
index 3eccbdb..70f4cce 100644
--- a/dts/src/arm64/allwinner/sun50i-a64.dtsi
+++ b/dts/src/arm64/allwinner/sun50i-a64.dtsi
@@ -142,15 +142,6 @@
clock-output-names = "ext-osc32k";
};
- pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
psci {
compatible = "arm,psci-0.2";
method = "smc";
diff --git a/dts/src/arm64/broadcom/stingray/stingray-pinctrl.dtsi b/dts/src/arm64/broadcom/stingray/stingray-pinctrl.dtsi
index 8a3a770..56789cc 100644
--- a/dts/src/arm64/broadcom/stingray/stingray-pinctrl.dtsi
+++ b/dts/src/arm64/broadcom/stingray/stingray-pinctrl.dtsi
@@ -42,13 +42,14 @@
pinmux: pinmux@14029c {
compatible = "pinctrl-single";
- reg = <0x0014029c 0x250>;
+ reg = <0x0014029c 0x26c>;
#address-cells = <1>;
#size-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xf>;
pinctrl-single,gpio-range = <
- &range 0 154 MODE_GPIO
+ &range 0 91 MODE_GPIO
+ &range 95 60 MODE_GPIO
>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
diff --git a/dts/src/arm64/broadcom/stingray/stingray.dtsi b/dts/src/arm64/broadcom/stingray/stingray.dtsi
index 71e2e34..0098dfd 100644
--- a/dts/src/arm64/broadcom/stingray/stingray.dtsi
+++ b/dts/src/arm64/broadcom/stingray/stingray.dtsi
@@ -464,8 +464,7 @@
<&pinmux 108 16 27>,
<&pinmux 135 77 6>,
<&pinmux 141 67 4>,
- <&pinmux 145 149 6>,
- <&pinmux 151 91 4>;
+ <&pinmux 145 149 6>;
};
i2c1: i2c@e0000 {
diff --git a/dts/src/arm64/freescale/fsl-lx2160a.dtsi b/dts/src/arm64/freescale/fsl-lx2160a.dtsi
index 408e0ec..b032f38 100644
--- a/dts/src/arm64/freescale/fsl-lx2160a.dtsi
+++ b/dts/src/arm64/freescale/fsl-lx2160a.dtsi
@@ -33,7 +33,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@1 {
@@ -49,7 +49,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@100 {
@@ -65,7 +65,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@101 {
@@ -81,7 +81,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@200 {
@@ -97,7 +97,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@201 {
@@ -113,7 +113,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@300 {
@@ -129,7 +129,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@301 {
@@ -145,7 +145,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@400 {
@@ -161,7 +161,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@401 {
@@ -177,7 +177,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@500 {
@@ -193,7 +193,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@501 {
@@ -209,7 +209,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@600 {
@@ -225,7 +225,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@601 {
@@ -241,7 +241,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@700 {
@@ -257,7 +257,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@701 {
@@ -273,7 +273,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cluster0_l2: l2-cache0 {
@@ -340,9 +340,9 @@
cache-level = <2>;
};
- cpu_pw20: cpu-pw20 {
+ cpu_pw15: cpu-pw15 {
compatible = "arm,idle-state";
- idle-state-name = "PW20";
+ idle-state-name = "PW15";
arm,psci-suspend-param = <0x0>;
entry-latency-us = <2000>;
exit-latency-us = <2000>;
diff --git a/dts/src/arm64/freescale/imx8mm.dtsi b/dts/src/arm64/freescale/imx8mm.dtsi
index 5f9d0da..58b8cd0 100644
--- a/dts/src/arm64/freescale/imx8mm.dtsi
+++ b/dts/src/arm64/freescale/imx8mm.dtsi
@@ -694,7 +694,7 @@
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_DUMMY>,
+ clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
@@ -710,7 +710,7 @@
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_DUMMY>,
+ clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
@@ -724,7 +724,7 @@
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_DUMMY>,
+ clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
diff --git a/dts/src/arm64/freescale/imx8mn.dtsi b/dts/src/arm64/freescale/imx8mn.dtsi
index 785f4c4..98496f5 100644
--- a/dts/src/arm64/freescale/imx8mn.dtsi
+++ b/dts/src/arm64/freescale/imx8mn.dtsi
@@ -569,7 +569,7 @@
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_DUMMY>,
+ clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
@@ -585,7 +585,7 @@
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_DUMMY>,
+ clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
@@ -599,7 +599,7 @@
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_DUMMY>,
+ clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
diff --git a/dts/src/arm64/freescale/imx8mq-zii-ultra.dtsi b/dts/src/arm64/freescale/imx8mq-zii-ultra.dtsi
index af99473..087b5b6 100644
--- a/dts/src/arm64/freescale/imx8mq-zii-ultra.dtsi
+++ b/dts/src/arm64/freescale/imx8mq-zii-ultra.dtsi
@@ -89,8 +89,8 @@
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
- states = <1000000 0x0
- 900000 0x1>;
+ states = <1000000 0x1
+ 900000 0x0>;
regulator-always-on;
};
};
diff --git a/dts/src/arm64/freescale/imx8mq.dtsi b/dts/src/arm64/freescale/imx8mq.dtsi
index 04115ca..55a3d1c 100644
--- a/dts/src/arm64/freescale/imx8mq.dtsi
+++ b/dts/src/arm64/freescale/imx8mq.dtsi
@@ -850,7 +850,7 @@
"fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_DUMMY>,
+ clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
@@ -867,7 +867,7 @@
"fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_DUMMY>,
+ clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
<&clk IMX8MQ_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
diff --git a/dts/src/arm64/marvell/armada-3720-turris-mox.dts b/dts/src/arm64/marvell/armada-3720-turris-mox.dts
index d105986..5f350cc 100644
--- a/dts/src/arm64/marvell/armada-3720-turris-mox.dts
+++ b/dts/src/arm64/marvell/armada-3720-turris-mox.dts
@@ -60,11 +60,6 @@
gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
};
- usb3_phy: usb3-phy {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&exp_usb3_vbus>;
- };
-
vsdc_reg: vsdc-reg {
compatible = "regulator-gpio";
regulator-name = "vsdc";
@@ -255,10 +250,16 @@
status = "okay";
};
+&comphy2 {
+ connector {
+ compatible = "usb-a-connector";
+ phy-supply = <&exp_usb3_vbus>;
+ };
+};
+
&usb3 {
status = "okay";
phys = <&comphy2 0>;
- usb-phy = <&usb3_phy>;
};
&mdio {
diff --git a/dts/src/arm64/rockchip/rk3399-gru-kevin.dts b/dts/src/arm64/rockchip/rk3399-gru-kevin.dts
index e152b0c..b806686 100644
--- a/dts/src/arm64/rockchip/rk3399-gru-kevin.dts
+++ b/dts/src/arm64/rockchip/rk3399-gru-kevin.dts
@@ -44,7 +44,7 @@
power-supply = <&pp3300_disp>;
panel-timing {
- clock-frequency = <266604720>;
+ clock-frequency = <266666667>;
hactive = <2400>;
hfront-porch = <48>;
hback-porch = <84>;
diff --git a/dts/src/arm64/rockchip/rk3399-hugsun-x99.dts b/dts/src/arm64/rockchip/rk3399-hugsun-x99.dts
index 0d1f5f9..c133e8d 100644
--- a/dts/src/arm64/rockchip/rk3399-hugsun-x99.dts
+++ b/dts/src/arm64/rockchip/rk3399-hugsun-x99.dts
@@ -644,7 +644,7 @@
status = "okay";
u2phy0_host: host-port {
- phy-supply = <&vcc5v0_host>;
+ phy-supply = <&vcc5v0_typec>;
status = "okay";
};
@@ -712,7 +712,7 @@
&usbdrd_dwc3_0 {
status = "okay";
- dr_mode = "otg";
+ dr_mode = "host";
};
&usbdrd3_1 {
diff --git a/dts/src/arm64/rockchip/rk3399-rockpro64.dts b/dts/src/arm64/rockchip/rk3399-rockpro64.dts
index 0401d4e..e544deb 100644
--- a/dts/src/arm64/rockchip/rk3399-rockpro64.dts
+++ b/dts/src/arm64/rockchip/rk3399-rockpro64.dts
@@ -173,7 +173,7 @@
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
+ regulator-max-microvolt = <1700000>;
vin-supply = <&vcc5v0_sys>;
};
};
@@ -247,8 +247,8 @@
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
- interrupt-parent = <&gpio1>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
@@ -574,7 +574,7 @@
pmic {
pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_gpio: vsel1-gpio {
@@ -624,7 +624,6 @@
&sdmmc {
bus-width = <4>;
- cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
disable-wp;
@@ -636,8 +635,7 @@
&sdhci {
bus-width = <8>;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
+ mmc-hs200-1_8v;
non-removable;
status = "okay";
};
diff --git a/dts/src/riscv/sifive/hifive-unleashed-a00.dts b/dts/src/riscv/sifive/hifive-unleashed-a00.dts
index 104d334..88cfcb9 100644
--- a/dts/src/riscv/sifive/hifive-unleashed-a00.dts
+++ b/dts/src/riscv/sifive/hifive-unleashed-a00.dts
@@ -13,6 +13,7 @@
compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
chosen {
+ stdout-path = "serial0";
};
cpus {
diff --git a/dts/src/xtensa/virt.dts b/dts/src/xtensa/virt.dts
index a9dcd87..611b98a 100644
--- a/dts/src/xtensa/virt.dts
+++ b/dts/src/xtensa/virt.dts
@@ -56,7 +56,7 @@
reg = <0xf0100000 0x03f00000>;
// BUS_ADDRESS(3) CPU_PHYSICAL(1) SIZE(2)
- ranges = <0x01000000 0x0 0xf0000000 0xf0000000 0x0 0x00010000>,
+ ranges = <0x01000000 0x0 0x00000000 0xf0000000 0x0 0x00010000>,
<0x02000000 0x0 0xf4000000 0xf4000000 0x0 0x08000000>;
// PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(2)
diff --git a/fs/devfs-core.c b/fs/devfs-core.c
index 258bb2d..5341e39 100644
--- a/fs/devfs-core.c
+++ b/fs/devfs-core.c
@@ -104,7 +104,7 @@ struct cdev *cdev_by_partuuid(const char *partuuid)
return NULL;
list_for_each_entry(cdev, &cdev_list, list) {
- if (!strcmp(cdev->partuuid, partuuid))
+ if (!strcasecmp(cdev->partuuid, partuuid))
return cdev;
}
return NULL;
diff --git a/fs/efivarfs.c b/fs/efivarfs.c
index 1e80493..9eadda4 100644
--- a/fs/efivarfs.c
+++ b/fs/efivarfs.c
@@ -145,7 +145,7 @@ static int efivars_create(struct device_d *dev, const char *pathname, mode_t mod
if (ret)
return -ENOENT;
- if (memcmp(&vendor, &EFI_BAREBOX_VENDOR_GUID, sizeof(efi_guid_t)))
+ if (efi_guidcmp(vendor, EFI_BAREBOX_VENDOR_GUID))
return -EPERM;
inode = xzalloc(sizeof(*inode));
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 55e837b..c9f27f1 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -52,7 +52,7 @@ static struct ext4_extent_header *ext4fs_get_extent_block(struct ext2_data *data
index = (struct ext4_extent_idx *)(ext_block + 1);
if (le16_to_cpu(ext_block->eh_magic) != EXT4_EXT_MAGIC)
- return 0;
+ return NULL;
if (ext_block->eh_depth == 0)
return ext_block;
@@ -64,7 +64,7 @@ static struct ext4_extent_header *ext4fs_get_extent_block(struct ext2_data *data
} while (fileblock >= le32_to_cpu(index[i].ei_block));
if (--i < 0)
- return 0;
+ return NULL;
block = le16_to_cpu(index[i].ei_leaf_hi);
block = (block << 32) + le32_to_cpu(index[i].ei_leaf_lo);
@@ -167,10 +167,11 @@ long int read_allocated_block(struct ext2fs_node *node, int fileblock)
log2_blksz = LOG2_EXT2_BLOCK_SIZE(node->data);
if (le32_to_cpu(inode->flags) & EXT4_EXTENTS_FL) {
+ long int startblock, endblock;
char *buf = zalloc(blksz);
struct ext4_extent_header *ext_block;
struct ext4_extent *extent;
- int i = -1;
+ int i;
if (!buf)
return -ENOMEM;
@@ -186,28 +187,27 @@ long int read_allocated_block(struct ext2fs_node *node, int fileblock)
extent = (struct ext4_extent *)(ext_block + 1);
- do {
- i++;
- if (i >= le16_to_cpu(ext_block->eh_entries))
- break;
- } while (fileblock >= le32_to_cpu(extent[i].ee_block));
+ for (i = 0; i < le16_to_cpu(ext_block->eh_entries); i++) {
+ startblock = le32_to_cpu(extent[i].ee_block);
+ endblock = startblock + le16_to_cpu(extent[i].ee_len);
- if (--i >= 0) {
- fileblock -= le32_to_cpu(extent[i].ee_block);
- if (fileblock >= le16_to_cpu(extent[i].ee_len)) {
+ if (startblock > fileblock) {
+ /* Sparse file */
free(buf);
return 0;
}
- start = le16_to_cpu(extent[i].ee_start_hi);
- start = (start << 32) +
+ if (fileblock < endblock) {
+ start = le16_to_cpu(extent[i].ee_start_hi);
+ start = (start << 32) +
le32_to_cpu(extent[i].ee_start_lo);
- free(buf);
- return fileblock + start;
+ free(buf);
+ return (fileblock - startblock) + start;
+ }
}
free(buf);
- return -EIO;
+ return 0;
}
if (fileblock < INDIRECT_BLOCKS) {
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index bfc5f27..2d231d2 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -55,12 +55,6 @@ int ext4fs_read_file(struct ext2fs_node *node, int pos,
int log2blocksize = LOG2_EXT2_BLOCK_SIZE(node->data);
int blocksize = 1 << (log2blocksize + DISK_SECTOR_BITS);
unsigned int filesize = le32_to_cpu(node->inode.size);
- int previous_block_number = -1;
- int delayed_start = 0;
- int delayed_extent = 0;
- int delayed_skipfirst = 0;
- int delayed_next = 0;
- char *delayed_buf = NULL;
short ret;
struct ext_filesystem *fs = node->data->fs;
@@ -75,6 +69,7 @@ int ext4fs_read_file(struct ext2fs_node *node, int pos,
int blockoff = pos % blocksize;
int blockend = blocksize;
int skipfirst = 0;
+
blknr = read_allocated_block(node, i);
if (blknr < 0)
return blknr;
@@ -95,59 +90,17 @@ int ext4fs_read_file(struct ext2fs_node *node, int pos,
skipfirst = blockoff;
blockend -= skipfirst;
}
+
if (blknr) {
- if (previous_block_number != -1) {
- if (delayed_next == blknr) {
- delayed_extent += blockend;
- delayed_next += blockend >> SECTOR_BITS;
- } else { /* spill */
- ret = ext4fs_devread(fs, delayed_start,
- delayed_skipfirst,
- delayed_extent,
- delayed_buf);
- if (ret)
- return ret;
- previous_block_number = blknr;
- delayed_start = blknr;
- delayed_extent = blockend;
- delayed_skipfirst = skipfirst;
- delayed_buf = buf;
- delayed_next = blknr +
- (blockend >> SECTOR_BITS);
- }
- } else {
- previous_block_number = blknr;
- delayed_start = blknr;
- delayed_extent = blockend;
- delayed_skipfirst = skipfirst;
- delayed_buf = buf;
- delayed_next = blknr +
- (blockend >> SECTOR_BITS);
- }
+ ret = ext4fs_devread(fs, blknr, skipfirst, blockend, buf);
+ if (ret)
+ return ret;
} else {
- if (previous_block_number != -1) {
- /* spill */
- ret = ext4fs_devread(fs, delayed_start,
- delayed_skipfirst,
- delayed_extent,
- delayed_buf);
- if (ret)
- return ret;
- previous_block_number = -1;
- }
- memset(buf, 0, blocksize - skipfirst);
+ memset(buf, 0, blockend);
}
+
buf += blocksize - skipfirst;
}
- if (previous_block_number != -1) {
- /* spill */
- ret = ext4fs_devread(fs, delayed_start,
- delayed_skipfirst, delayed_extent,
- delayed_buf);
- if (ret)
- return ret;
- previous_block_number = -1;
- }
return len;
}
diff --git a/fs/ubootvarfs.c b/fs/ubootvarfs.c
index 81ec05d..475e4b7 100644
--- a/fs/ubootvarfs.c
+++ b/fs/ubootvarfs.c
@@ -409,7 +409,7 @@ static void ubootvarfs_parse(struct ubootvarfs_data *data, char *blob,
list_add_tail(&var->list, &data->var_list);
} else {
- pr_err("No separator in data @ 0x%08x. Skipped.",
+ pr_err("No separator in data @ 0x%08tx. Skipped.",
blob - start);
free(var);
}
diff --git a/include/efi.h b/include/efi.h
index 218333f..166803a 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -664,11 +664,6 @@ typedef union {
efi_ipv6_address v6;
} efi_ip_address;
-static inline int efi_compare_guid(efi_guid_t *a, efi_guid_t *b)
-{
- return memcmp(a, b, sizeof(efi_guid_t));
-}
-
struct efi_device_path *device_path_from_handle(efi_handle_t Handle);
char *device_path_to_str(struct efi_device_path *dev_path);
u8 device_path_to_type(struct efi_device_path *dev_path);
diff --git a/include/efi/efi-device.h b/include/efi/efi-device.h
index 15c293b..5eaf1f2 100644
--- a/include/efi/efi-device.h
+++ b/include/efi/efi-device.h
@@ -43,5 +43,6 @@ static inline int efi_driver_register(struct efi_driver *efidrv)
int efi_connect_all(void);
void efi_register_devices(void);
+struct efi_device *efi_get_bootsource(void);
#endif /* __EFI_EFI_DEVICE_H */
diff --git a/include/param.h b/include/param.h
index dea6990..4ac502e 100644
--- a/include/param.h
+++ b/include/param.h
@@ -264,8 +264,6 @@ static inline struct param_d *dev_add_param_bool_ro(struct device_d *dev, const
}
static inline struct param_d *dev_add_param_string_ro(struct device_d *dev, const char *name,
- int (*set)(struct param_d *p, void *priv),
- int (*get)(struct param_d *p, void *priv),
char **value, void *priv)
{
return dev_add_param_string(dev, name, param_set_readonly, NULL, value, NULL);
@@ -285,9 +283,7 @@ static inline struct param_d *dev_add_param_enum_ro(struct device_d *dev, const
}
static inline struct param_d *dev_add_param_bitmask_ro(struct device_d *dev, const char *name,
- int (*set)(struct param_d *p, void *priv),
- int (*get)(struct param_d *p, void *priv),
- unsigned long *value, const char * const *names, int max, void *priv)
+ unsigned long *value, const char * const *names, int max)
{
return dev_add_param_bitmask(dev, name, param_set_readonly, NULL,
value, names, max, NULL);
diff --git a/lib/libfile.c b/lib/libfile.c
index 02078dd..5a1817e 100644
--- a/lib/libfile.c
+++ b/lib/libfile.c
@@ -332,7 +332,7 @@ int copy_file(const char *src, const char *dst, int verbose)
{
char *rw_buf = NULL;
int srcfd = 0, dstfd = 0;
- int r;
+ int r, s;
int ret = 1, err1 = 0;
int mode;
int total = 0;
@@ -343,22 +343,27 @@ int copy_file(const char *src, const char *dst, int verbose)
srcfd = open(src, O_RDONLY);
if (srcfd < 0) {
printf("could not open %s: %s\n", src, errno_str());
+ ret = srcfd;
goto out;
}
mode = O_WRONLY | O_CREAT;
- ret = stat(dst, &dststat);
- if (ret && ret != -ENOENT)
+ s = stat(dst, &dststat);
+ if (s && s != -ENOENT) {
+ printf("could not stat %s: %s\n", dst, errno_str());
+ ret = s;
goto out;
+ }
/* Set O_TRUNC only if file exist and is a regular file */
- if (!ret && S_ISREG(dststat.st_mode))
+ if (!s && S_ISREG(dststat.st_mode))
mode |= O_TRUNC;
dstfd = open(dst, mode);
if (dstfd < 0) {
printf("could not open %s: %s\n", dst, errno_str());
+ ret = dstfd;
goto out;
}
@@ -373,12 +378,14 @@ int copy_file(const char *src, const char *dst, int verbose)
r = read(srcfd, rw_buf, RW_BUF_SIZE);
if (r < 0) {
perror("read");
+ ret = r;
goto out;
}
if (!r)
break;
- if (write_full(dstfd, rw_buf, r) < 0) {
+ ret = write_full(dstfd, rw_buf, r);
+ if (ret < 0) {
perror("write");
goto out;
}
diff --git a/lib/parameter.c b/lib/parameter.c
index 00e9a9f..fdbb2e7 100644
--- a/lib/parameter.c
+++ b/lib/parameter.c
@@ -253,11 +253,14 @@ static int param_string_set(struct device_d *dev, struct param_d *p, const char
struct param_string *ps = to_param_string(p);
int ret;
char *value_save = *ps->value;
+ char *value_new;
if (!val)
val = "";
- *ps->value = xstrdup(val);
+ value_new = xstrdup(val);
+ value_new = strim(value_new);
+ *ps->value = value_new;
if (!ps->set)
return 0;
diff --git a/lib/readline.c b/lib/readline.c
index d026af1..3d16c18 100644
--- a/lib/readline.c
+++ b/lib/readline.c
@@ -290,9 +290,17 @@ int readline(const char *prompt, char *buf, int len)
insert = !insert;
break;
case BB_KEY_ERASE_LINE:
+ BEGINNING_OF_LINE();
+ ERASE_TO_EOL();
+ break;
case CTL_CH('u'):
+ wlen = eol_num - num;
+ memmove(buf, buf+num, wlen);
BEGINNING_OF_LINE();
ERASE_TO_EOL();
+ eol_num = wlen;
+ REFRESH_TO_EOL();
+ BEGINNING_OF_LINE();
break;
case DEL:
case BB_KEY_DEL7:
diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index fe0de87..919f286 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -134,11 +134,6 @@ cc-ifversion = $(shell [ $(call cc-version, $(CC)) $(1) $(2) ] && echo $(3))
ld-option = $(call try-run,\
$(CC) -x c /dev/null -c -o "$$TMPO" ; $(LD) $(1) "$$TMPO" -o "$$TMP",$(1),$(2))
-# ar-option
-# Usage: KBUILD_ARFLAGS := $(call ar-option,D)
-# Important: no spaces around options
-ar-option = $(call try-run, $(AR) rc$(1) "$$TMP",$(1),$(2))
-
######
###