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-rw-r--r--arch/arm/mach-imx/imx8m.c24
-rw-r--r--arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h4
2 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
index 031b25bfc1..596c4140b3 100644
--- a/arch/arm/mach-imx/imx8m.c
+++ b/arch/arm/mach-imx/imx8m.c
@@ -19,6 +19,7 @@
#include <mach/generic.h>
#include <mach/revision.h>
#include <mach/imx8mq.h>
+#include <mach/imx8m-ccm-regs.h>
#include <mach/reset-reason.h>
#include <mach/ocotp.h>
@@ -28,6 +29,29 @@
#define FSL_SIP_BUILDINFO 0xC2000003
#define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00
+void imx8m_clock_set_target_val(int clock_id, u32 val)
+{
+ void *ccm = IOMEM(MX8M_CCM_BASE_ADDR);
+
+ writel(val, ccm + IMX8M_CCM_TARGET_ROOTn(clock_id));
+}
+
+void imx8m_ccgr_clock_enable(int index)
+{
+ void *ccm = IOMEM(MX8M_CCM_BASE_ADDR);
+
+ writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0),
+ ccm + IMX8M_CCM_CCGRn_SET(index));
+}
+
+void imx8m_ccgr_clock_disable(int index)
+{
+ void *ccm = IOMEM(MX8M_CCM_BASE_ADDR);
+
+ writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0),
+ ccm + IMX8M_CCM_CCGRn_CLR(index));
+}
+
u64 imx8mq_uid(void)
{
return imx_ocotp_read_uid(IOMEM(MX8MQ_OCOTP_BASE_ADDR));
diff --git a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h
index 66ace0f1c4..ff207b80f9 100644
--- a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h
@@ -48,4 +48,8 @@
#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b10)
#define IMX8M_CCM_CCGR_SETTINGn_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b11)
+void imx8m_clock_set_target_val(int clock_id, u32 val);
+void imx8m_ccgr_clock_enable(int index);
+void imx8m_ccgr_clock_disable(int index);
+
#endif