diff options
89 files changed, 2180 insertions, 431 deletions
diff --git a/Documentation/boards/aarch64-qemu-virt.rst b/Documentation/boards/aarch64-qemu-virt.rst index b6b446e4c7..e21791af16 100644 --- a/Documentation/boards/aarch64-qemu-virt.rst +++ b/Documentation/boards/aarch64-qemu-virt.rst @@ -1,10 +1,11 @@ -=========== +Aarch64 +======= Aarch64 Qemu virt ------------------------- +----------------- Running barebox on QEMU aarch64 virt machine -^^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Usage:: $ qemu-system-aarch64 -m 2048M \ diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst index 6912ed9a54..60cdcf072e 100644 --- a/Documentation/boards/imx.rst +++ b/Documentation/boards/imx.rst @@ -16,6 +16,7 @@ The Internal Boot Mode is supported on: * i.MX25 * i.MX35 +* i.MX50 * i.MX51 * i.MX53 * i.MX6 diff --git a/Documentation/user/usb.rst b/Documentation/user/usb.rst index 8602a8f7fe..bbcb045cee 100644 --- a/Documentation/user/usb.rst +++ b/Documentation/user/usb.rst @@ -56,7 +56,9 @@ shall be provided to the host. For the possible ``flags`` see On the host side, the tool `dfu-util <http://dfu-util.gnumonks.org/>`_ can be used to update the partitions. It is available for most distributions and typically -supports the following options:: +supports the following options: + +.. code-block:: none dfu-util -h Usage: dfu-util [options] ... @@ -1,5 +1,5 @@ VERSION = 2016 -PATCHLEVEL = 08 +PATCHLEVEL = 09 SUBLEVEL = 0 EXTRAVERSION = NAME = None diff --git a/arch/arm/boards/afi-gf/defaultenv-gf/boot/sd b/arch/arm/boards/afi-gf/defaultenv-gf/boot/sd index dce060542a..aa94b2fa2e 100644 --- a/arch/arm/boards/afi-gf/defaultenv-gf/boot/sd +++ b/arch/arm/boards/afi-gf/defaultenv-gf/boot/sd @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - boot-menu-add-entry "$0" "kernel & rootfs on SD card" - exit -fi - global.bootm.image=/boot/uImage global.bootm.oftree=/boot/oftree #global.bootm.initrd=<path to initrd> diff --git a/arch/arm/boards/afi-gf/defaultenv-gf/init/automount b/arch/arm/boards/afi-gf/defaultenv-gf/init/automount index c67bd1ba50..560bdb7975 100644 --- a/arch/arm/boards/afi-gf/defaultenv-gf/init/automount +++ b/arch/arm/boards/afi-gf/defaultenv-gf/init/automount @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "Automountpoints" - exit -fi - # automount tftp server based on $eth1.serverip mkdir -p /mnt/tftp diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/automount b/arch/arm/boards/at91sam9m10ihd/env/init/automount index 5bb63ccb9e..96ffa7059a 100644 --- a/arch/arm/boards/at91sam9m10ihd/env/init/automount +++ b/arch/arm/boards/at91sam9m10ihd/env/init/automount @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "Automountpoints" - exit -fi - # automount tftp server based on $eth0.serverip mkdir -p /mnt/tftp diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand index ac516d82d7..433bc888da 100644 --- a/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand +++ b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NAND partitions" - exit -fi - mtdparts="128k(nand0.at91bootstrap),256k(nand0.barebox)ro,128k(nand0.bareboxenv),128k(nand0.bareboxenv2),128k(nand0.oftree),1280k(nand0.free),3M(nand0.kernel),195M(nand0.rootfs),300M(nand0.userdata),-(nand0.cache)" kernelname="atmel_nand" diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80 b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80 index 44198c820e..5457e4e0d4 100644 --- a/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80 +++ b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80 @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "SPI NOR partitions" - exit -fi - mtdparts="32k(m25p0.at91bootstrap)ro,256k(m25p0.barebox),128k(m25p0.bareboxenv),128k(m25p0.bareboxenv2),128k(m25p0.oftree),-(m25p0.kernel)" kernelname="m25p0" diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/ps1 b/arch/arm/boards/at91sam9m10ihd/env/init/ps1 deleted file mode 100644 index a94acc14f8..0000000000 --- a/arch/arm/boards/at91sam9m10ihd/env/init/ps1 +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/sh - -/env/config - -if [ ${global.allow_color} = "true" ]; then - export PS1="\e[1;32mbarebox@\e[1;36m\h:\w\e[0m\n# " -else - export PS1="barebox@\h:\w\n# " -fi diff --git a/arch/arm/boards/beagle/defaultenv-beagle/init/mtdparts-nand b/arch/arm/boards/beagle/defaultenv-beagle/init/mtdparts-nand index 9335bb17a3..48c1c5d9ee 100644 --- a/arch/arm/boards/beagle/defaultenv-beagle/init/mtdparts-nand +++ b/arch/arm/boards/beagle/defaultenv-beagle/init/mtdparts-nand @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NAND partitions" - exit -fi - mtdparts="128k(nand0.xload),256k(nand0.barebox)ro,128k(nand0.bareboxenv),128k(nand0.oftree),4M(nand0.kernel),120M(nand0.rootfs),-(nand0.data)" kernelname="omap2-nand" diff --git a/arch/arm/boards/ccxmx51/env/init/mtdparts-nand b/arch/arm/boards/ccxmx51/env/init/mtdparts-nand index 5ea35d2ef7..27ed38a888 100644 --- a/arch/arm/boards/ccxmx51/env/init/mtdparts-nand +++ b/arch/arm/boards/ccxmx51/env/init/mtdparts-nand @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NAND partitions" - exit -fi - mtdparts="512k(barebox)ro,256k(bareboxenv),3328k(kernel),-(root)" kernelname="mxc_nand" diff --git a/arch/arm/boards/clep7212/defaultenv-clep7212/init/mtdparts-nor b/arch/arm/boards/clep7212/defaultenv-clep7212/init/mtdparts-nor index 8702b4059c..39777f95f2 100644 --- a/arch/arm/boards/clep7212/defaultenv-clep7212/init/mtdparts-nor +++ b/arch/arm/boards/clep7212/defaultenv-clep7212/init/mtdparts-nor @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NOR partitions" - exit -fi - mtdparts="256k(boot),256k(env),3584k(kernel),-(root)" kernelname="physmap-flash.0" diff --git a/arch/arm/boards/crystalfontz-cfa10036/env/init/automount b/arch/arm/boards/crystalfontz-cfa10036/env/init/automount index 8fdca7cd47..6f85c27289 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/env/init/automount +++ b/arch/arm/boards/crystalfontz-cfa10036/env/init/automount @@ -1,9 +1,4 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "Automountpoints" - exit -fi - mkdir -p /mnt/disk0.2 automount -d /mnt/disk0.2 '[ -e /dev/disk0.2 ] && mount /dev/disk0.2 /mnt/disk0.2' diff --git a/arch/arm/boards/datamodul-edm-qmx6/env/init/automount b/arch/arm/boards/datamodul-edm-qmx6/env/init/automount index 2ce37c785a..e786b82bdb 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/env/init/automount +++ b/arch/arm/boards/datamodul-edm-qmx6/env/init/automount @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "Automountpoints" - exit -fi - # automount tftp server based on $eth0.serverip mkdir -p /mnt/tftp diff --git a/arch/arm/boards/efika-mx-smartbook/defaultenv-efikasb/init/automount b/arch/arm/boards/efika-mx-smartbook/defaultenv-efikasb/init/automount index 8cb5eaf792..71dfd95f2b 100644 --- a/arch/arm/boards/efika-mx-smartbook/defaultenv-efikasb/init/automount +++ b/arch/arm/boards/efika-mx-smartbook/defaultenv-efikasb/init/automount @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "Automountpoints" - exit -fi - # automount tftp server based on $eth0.serverip mkdir -p /mnt/tftp diff --git a/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand b/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand index 7271341565..b51104ad76 100644 --- a/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand +++ b/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NAND partitions" - exit -fi - mtdparts="256k(nand0.barebox),128k(nand0.bareboxenv),1536k(nand0.kernel),-(nand0.root)" kernelname="nand" diff --git a/arch/arm/boards/guf-santaro/lowlevel.c b/arch/arm/boards/guf-santaro/lowlevel.c index e2b6df5839..1502bb3d38 100644 --- a/arch/arm/boards/guf-santaro/lowlevel.c +++ b/arch/arm/boards/guf-santaro/lowlevel.c @@ -3,36 +3,47 @@ #include <io.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> +#include <asm/cache.h> #include <mach/generic.h> #include <mach/imx6-regs.h> #include <debug_ll.h> +#include <console.h> +#include <mach/esdctl.h> static inline void setup_uart(void) { - void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; + void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR); writel(0x1, iomuxbase + 0x2b0); imx6_ungate_all_peripherals(); - imx6_uart_setup_ll(); - - putc_ll('>'); + imx6_uart_setup(IOMEM(MX6_UART2_BASE_ADDR)); } extern char __dtb_imx6q_guf_santaro_start[]; -ENTRY_FUNCTION(start_imx6q_guf_santaro, r0, r1, r2) +static noinline void santaro_start(void) { - void *fdt; + pbl_set_putc(imx_uart_putc, IOMEM(MX6_UART2_BASE_ADDR)); + + pr_debug("Garz+Fricke Santaro\n"); + + imx6q_barebox_entry(__dtb_imx6q_guf_santaro_start); +} +ENTRY_FUNCTION(start_imx6q_guf_santaro, r0, r1, r2) +{ imx6_cpu_lowlevel_init(); arm_setup_stack(0x00920000 - 8); - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); + arm_early_mmu_cache_invalidate(); + + setup_uart(); - fdt = __dtb_imx6q_guf_santaro_start - get_runtime_offset(); + relocate_to_current_adr(); + setup_c(); + barrier(); - barebox_arm_entry(0x10000000, SZ_1G, fdt); + santaro_start(); } diff --git a/arch/arm/boards/highbank/env/init/automount b/arch/arm/boards/highbank/env/init/automount index 2c283c6eed..eb5c07a739 100644 --- a/arch/arm/boards/highbank/env/init/automount +++ b/arch/arm/boards/highbank/env/init/automount @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "Automountpoints" - exit -fi - # automount tftp server based on $eth0.serverip mkdir -p /mnt/tftp diff --git a/arch/arm/boards/highbank/env/init/ps1 b/arch/arm/boards/highbank/env/init/ps1 deleted file mode 100644 index a94acc14f8..0000000000 --- a/arch/arm/boards/highbank/env/init/ps1 +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/sh - -/env/config - -if [ ${global.allow_color} = "true" ]; then - export PS1="\e[1;32mbarebox@\e[1;36m\h:\w\e[0m\n# " -else - export PS1="barebox@\h:\w\n# " -fi diff --git a/arch/arm/boards/highbank/init.c b/arch/arm/boards/highbank/init.c index 1cb02e6e48..295d4757f2 100644 --- a/arch/arm/boards/highbank/init.c +++ b/arch/arm/boards/highbank/init.c @@ -77,7 +77,7 @@ static int highbank_mem_init(void) fdt = IOMEM(FIRMWARE_DTB_BASE); root = of_unflatten_dtb(fdt); - if (!root) { + if (IS_ERR(root)) { pr_warn("no dtb found at 0x1000 use default configuration\n"); fdt = NULL; goto not_found; diff --git a/arch/arm/boards/karo-tx25/env/init/mtdparts-nand b/arch/arm/boards/karo-tx25/env/init/mtdparts-nand index e2dcfab49a..0288163ad1 100644 --- a/arch/arm/boards/karo-tx25/env/init/mtdparts-nand +++ b/arch/arm/boards/karo-tx25/env/init/mtdparts-nand @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NAND partitions" - exit -fi - mtdparts="512k(nand0.barebox),512k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" kernelname="mxc_nand" diff --git a/arch/arm/boards/lubbock/env/init/mtdparts-nor b/arch/arm/boards/lubbock/env/init/mtdparts-nor index 3307596467..b5c4e32411 100644 --- a/arch/arm/boards/lubbock/env/init/mtdparts-nor +++ b/arch/arm/boards/lubbock/env/init/mtdparts-nor @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NOR partitions" - exit -fi - mtdparts="2048k@0(nor0.barebox)ro,256k(nor0.barebox-env),256k(nor0.barebox-logo),256k(nor0.barebox-logo2),5120k(nor0.kernel),-(nor0.root)" kernelname="application-flash" diff --git a/arch/arm/boards/mainstone/env/init/mtdparts-nor b/arch/arm/boards/mainstone/env/init/mtdparts-nor index 3307596467..b5c4e32411 100644 --- a/arch/arm/boards/mainstone/env/init/mtdparts-nor +++ b/arch/arm/boards/mainstone/env/init/mtdparts-nor @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NOR partitions" - exit -fi - mtdparts="2048k@0(nor0.barebox)ro,256k(nor0.barebox-env),256k(nor0.barebox-logo),256k(nor0.barebox-logo2),5120k(nor0.kernel),-(nor0.root)" kernelname="application-flash" diff --git a/arch/arm/boards/mx31moboard/env/init/mtdparts-nor b/arch/arm/boards/mx31moboard/env/init/mtdparts-nor index f09a9cc381..ab5b175c37 100644 --- a/arch/arm/boards/mx31moboard/env/init/mtdparts-nor +++ b/arch/arm/boards/mx31moboard/env/init/mtdparts-nor @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NOR partitions" - exit -fi - mtdparts="512k(nor0.barebox)ro,256k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" kernelname="physmap-flash.0" diff --git a/arch/arm/boards/phytec-phycore-imx27/defaultenv-pcm038/boot/nor b/arch/arm/boards/phytec-phycore-imx27/defaultenv-pcm038/boot/nor index 0d10584abc..f584307d7a 100644 --- a/arch/arm/boards/phytec-phycore-imx27/defaultenv-pcm038/boot/nor +++ b/arch/arm/boards/phytec-phycore-imx27/defaultenv-pcm038/boot/nor @@ -1,9 +1,4 @@ #!/bin/sh -if [ "$1" = menu ]; then - boot-menu-add-entry "$0" "nor" - exit -fi - global.bootm.image="/dev/nor0.kernel" global.linux.bootargs.dyn.root="root=/dev/mtdblock3 ro" diff --git a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand index 84220b77b3..540277cdeb 100644 --- a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand +++ b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NAND partitions" - exit -fi - mtdparts="512k(nand0.barebox)ro,128k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" kernelname="mxc_nand" diff --git a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor index 2ef6ead71a..940eb86c95 100644 --- a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor +++ b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NOR partitions" - exit -fi - mtdparts="256k(nor0.barebox)ro,128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" kernelname="physmap-flash.0" diff --git a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand index 8a41f62810..c7185db7f7 100644 --- a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand +++ b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NAND partitions" - exit -fi - mtdparts="512k(nand0.barebox),256k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" kernelname="mxc_nand" diff --git a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor index f787f28442..09c3ba9842 100644 --- a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor +++ b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NOR partitions" - exit -fi - mtdparts="512k(nor0.barebox),128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" kernelname="physmap-flash.0" diff --git a/arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor index e617cbaaba..4423943211 100644 --- a/arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor +++ b/arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NOR partitions" - exit -fi - mtdparts="512k(nor0.barebox),256k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" kernelname="physmap-flash.0" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/automount b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/automount index a059e190e2..91ded44119 100644 --- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/automount +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/automount @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "Automountpoints" - exit -fi - # automount tftp server based on $eth0.serverip mkdir -p /mnt/tftp diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount index 49d99bd78d..4b223d8037 100644 --- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "Automountpoints" - exit -fi - # automount tftp server based on $eth0.serverip mkdir -p /mnt/tftp diff --git a/arch/arm/boards/raspberry-pi/env/init/bootargs-base b/arch/arm/boards/raspberry-pi/env/init/bootargs-base index 4dda5501e3..416dc8a6f4 100644 --- a/arch/arm/boards/raspberry-pi/env/init/bootargs-base +++ b/arch/arm/boards/raspberry-pi/env/init/bootargs-base @@ -1,8 +1,3 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "Base bootargs" - exit -fi - global.linux.bootargs.base="console=ttyAMA0,115200" diff --git a/arch/arm/boards/raspberry-pi/env/init/ps1 b/arch/arm/boards/raspberry-pi/env/init/ps1 deleted file mode 100644 index f8948466d3..0000000000 --- a/arch/arm/boards/raspberry-pi/env/init/ps1 +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh - -if [ ${global.allow_color} = "true" ]; then - export PS1="\e[1;32mbarebox@\e[1;36m\h:\w\e[0m\n# " -else - export PS1="barebox@\h:\w\n# " -fi diff --git a/arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand b/arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand index 58e859bb96..42907ae3a7 100644 --- a/arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand +++ b/arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NAND partitions" - exit -fi - mtdparts="0xC0000(nand0.bootstrap),256k(nand0.barebox)ro,128k(nand0.bareboxenv),3M(nand0.kernel),-(nand0.rootfs)" kernelname="atmel_nand" diff --git a/arch/arm/boards/versatile/env/boot/nor b/arch/arm/boards/versatile/env/boot/nor index 3f31605c4f..f90bcc3fca 100644 --- a/arch/arm/boards/versatile/env/boot/nor +++ b/arch/arm/boards/versatile/env/boot/nor @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - boot-menu-add-entry "$0" "nor" - exit -fi - global.bootm.image="/dev/nor0.kernel" global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=5 rootfstype=ubifs" diff --git a/arch/arm/boards/versatile/env/boot/nor-update b/arch/arm/boards/versatile/env/boot/nor-update index 728889d20f..5799ed68d1 100644 --- a/arch/arm/boards/versatile/env/boot/nor-update +++ b/arch/arm/boards/versatile/env/boot/nor-update @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - boot-menu-add-entry "$0" "nor update" - exit -fi - global.bootm.image="/dev/nor0.update" dtb=/dev/nor0.dtb diff --git a/arch/arm/boards/versatile/env/init/automount b/arch/arm/boards/versatile/env/init/automount index 53f9196a15..d08990b53c 100644 --- a/arch/arm/boards/versatile/env/init/automount +++ b/arch/arm/boards/versatile/env/init/automount @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "Automountpoints" - exit -fi - # automount tftp server based on $eth0.serverip mkdir -p /mnt/tftp diff --git a/arch/arm/boards/versatile/env/init/mtdparts-nor b/arch/arm/boards/versatile/env/init/mtdparts-nor index 9079d482da..20c2b994cc 100644 --- a/arch/arm/boards/versatile/env/init/mtdparts-nor +++ b/arch/arm/boards/versatile/env/init/mtdparts-nor @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NOR partitions" - exit -fi - mtdparts="512k(nor0.barebox)ro,512k(nor0.bareboxenv),4864k(nor0.kernel),256k(nor0.dtb),3M(nor0.update),-(nor0.root)" kernelname="physmap-flash.0" diff --git a/arch/arm/boards/versatile/env/init/ps1 b/arch/arm/boards/versatile/env/init/ps1 deleted file mode 100644 index a1d075499f..0000000000 --- a/arch/arm/boards/versatile/env/init/ps1 +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh - -if [ ${global.allow_color} = "true" ]; then - export PS1="\e[1;32mbarebox@\e[1;36m\h:\w\e[0m\n# " -else - export PS1="barebox@\h:\w\n# " -fi diff --git a/arch/arm/boards/zylonite/env/init/mtdparts-nand b/arch/arm/boards/zylonite/env/init/mtdparts-nand index 9db4652c40..749318b59e 100644 --- a/arch/arm/boards/zylonite/env/init/mtdparts-nand +++ b/arch/arm/boards/zylonite/env/init/mtdparts-nand @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NAND partitions" - exit -fi - mtdparts="128k@0(TIMH)ro,128k@128k(OBMI)ro,768k@256k(barebox),256k@1024k(barebox-env),12M@1280k(kernel),38016k@13568k(root)" kernelname="pxa3xx_nand-0" diff --git a/arch/arm/cpu/dtb.c b/arch/arm/cpu/dtb.c index ae4ff2a9ad..b9390b46e6 100644 --- a/arch/arm/cpu/dtb.c +++ b/arch/arm/cpu/dtb.c @@ -48,7 +48,7 @@ static int of_arm_init(void) } root = of_unflatten_dtb(fdt); - if (root) { + if (!IS_ERR(root)) { of_set_root_node(root); of_fix_tree(root); if (IS_ENABLED(CONFIG_OFDEVICE)) diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c index a31bce4c50..459abe56ba 100644 --- a/arch/arm/cpu/mmu.c +++ b/arch/arm/cpu/mmu.c @@ -307,7 +307,7 @@ static void create_vector_table(unsigned long adr) vectors = xmemalign(PAGE_SIZE, PAGE_SIZE); pr_debug("Creating vector table, virt = 0x%p, phys = 0x%08lx\n", vectors, adr); - exc = arm_create_pte(adr); + exc = arm_create_pte(ALIGN_DOWN(adr, SZ_1M)); idx = (adr & (SZ_1M - 1)) >> PAGE_SHIFT; exc[idx] = (u32)vectors | PTE_TYPE_SMALL | pte_flags_cached; } diff --git a/arch/arm/dts/imx6q-guf-santaro.dts b/arch/arm/dts/imx6q-guf-santaro.dts index 2bd1a26317..3217a5bf90 100644 --- a/arch/arm/dts/imx6q-guf-santaro.dts +++ b/arch/arm/dts/imx6q-guf-santaro.dts @@ -63,6 +63,7 @@ compatible = "simple-panel"; backlight = <&backlight>; enable-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + enable-delay = <200>; port { panel_in: endpoint { @@ -576,6 +577,16 @@ status = "okay"; }; +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + &usdhc2 { /* SD card socket */ pinctrl-names = "default"; diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 404a6ae6ad..56663feb89 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -267,7 +267,7 @@ static int do_bootz_linux_fdt(int fd, struct image_data *data) if (IS_BUILTIN(CONFIG_OFTREE)) { data->of_root_node = of_unflatten_dtb(oftree); - if (!data->of_root_node) { + if (IS_ERR(data->of_root_node)) { pr_err("unable to unflatten devicetree\n"); ret = -EINVAL; goto err_free; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 82fc945d5b..a80bc6b986 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -115,6 +115,12 @@ config ARCH_IMX35 select ARCH_HAS_FEC_IMX select PINCTRL_IMX_IOMUX_V3 +config ARCH_IMX50 + bool + select CPU_V7 + select ARCH_HAS_FEC_IMX + select PINCTRL_IMX_IOMUX_V3 + config ARCH_IMX51 bool select CPU_V7 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index db1cf7df08..0763944895 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -5,6 +5,8 @@ obj-$(CONFIG_ARCH_IMX21) += imx21.o clk-imx21.o obj-$(CONFIG_ARCH_IMX27) += imx27.o clk-imx27.o obj-$(CONFIG_ARCH_IMX31) += imx31.o clk-imx31.o obj-$(CONFIG_ARCH_IMX35) += imx35.o clk-imx35.o +obj-$(CONFIG_ARCH_IMX50) += imx50.o imx5.o clk-imx5.o +pbl-$(CONFIG_ARCH_IMX50) += imx50.o imx5.o obj-$(CONFIG_ARCH_IMX51) += imx51.o imx5.o clk-imx5.o pbl-$(CONFIG_ARCH_IMX51) += imx51.o imx5.o obj-$(CONFIG_ARCH_IMX53) += imx53.o imx5.o clk-imx5.o esdctl-v4.o diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index fccea7fafe..864d06e195 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -171,6 +171,7 @@ static int imx25_ccm_probe(struct device_d *dev) clkdev_add_physbase(clks[ipg], MX25_CSPI3_BASE_ADDR, NULL); clkdev_add_physbase(clks[per3], MX25_ESDHC1_BASE_ADDR, NULL); clkdev_add_physbase(clks[per4], MX25_ESDHC2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per8], MX25_NFC_BASE_ADDR, NULL); clkdev_add_physbase(clks[lcdc_ipg_per], MX25_LCDC_BASE_ADDR, "per"); clkdev_add_physbase(clks[lcdc_ipg], MX25_LCDC_BASE_ADDR, "ipg"); clkdev_add_physbase(clks[lcdc_ahb], MX25_LCDC_BASE_ADDR, "ahb"); diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c index 51a6460c9e..d3cde7e42f 100644 --- a/arch/arm/mach-imx/clk-imx5.c +++ b/arch/arm/mach-imx/clk-imx5.c @@ -14,6 +14,7 @@ #include <of.h> #include <linux/clkdev.h> #include <linux/err.h> +#include <mach/imx50-regs.h> #include <mach/imx51-regs.h> #include <mach/imx53-regs.h> #include <dt-bindings/clock/imx5-clock.h> @@ -68,6 +69,17 @@ static const char *standard_pll_sel[] = { "lp_apm", }; +static const char *mx50_3bit_clk_sel[] = { + "pll1_sw", + "pll2_sw", + "pll3_sw", + "lp_apm", + "pfd0", + "pfd1", + "pfd4", + "osc", +}; + static const char *lp_apm_sel[] = { "osc", }; @@ -83,6 +95,13 @@ static const char *main_bus_sel[] = { "periph_apm", }; +static const char *mx50_periph_clk_sel[] = { + "pll1_sw", + "pll2_sw", + "pll3_sw", + "lp_apm", +}; + static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", @@ -194,12 +213,6 @@ static void __init mx5_clocks_common_init(struct device_d *dev, void __iomem *ba clks[IMX5_CLK_OSC] = clk_fixed("osc", 24000000); } - clks[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", base + CCM_CCSR, 9, 1, - lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); - clks[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", base + CCM_CBCMR, 12, 2, - periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); - clks[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", base + CCM_CBCDR, 25, 1, - main_bus_sel, ARRAY_SIZE(main_bus_sel)); clks[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", base + CCM_CBCMR, 1, 1, per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); clks[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", base + CCM_CBCDR, 6, 2); @@ -215,26 +228,42 @@ static void __init mx5_clocks_common_init(struct device_d *dev, void __iomem *ba standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); clks[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", base + CCM_CSCDR1, 3, 3); clks[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", base + CCM_CSCDR1, 0, 3); + clks[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", + "esdhc_a_sel", base + CCM_CSCDR1, 16, 3); + clks[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", + "esdhc_a_pred", base + CCM_CSCDR1, 11, 3); + clks[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", + "esdhc_b_sel", base + CCM_CSCDR1, 22, 3); + clks[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", + "esdhc_b_pred", base + CCM_CSCDR1, 19, 3); + clks[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + CCM_CSCMR1, + 4, 2, standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); + clks[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", + "ecspi_sel", base + CCM_CSCDR2, 25, 3); + clks[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", + "ecspi_pred", base + CCM_CSCDR2, 19, 6); + clks[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", + "pll1_sw", base + CCM_CACRR, 0, 3); +} +static void mx5_clocks_mx51_mx53_init(void __iomem *base) +{ + clks[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", base + CCM_CCSR, 9, 1, + lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); + clks[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", base + CCM_CBCMR, 12, 2, + periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); + clks[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", base + CCM_CBCDR, 25, 1, + main_bus_sel, ARRAY_SIZE(main_bus_sel)); clks[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", base + CCM_CSCMR1, 20, 2, standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); clks[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", base + CCM_CSCMR1, 16, 2, standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); - clks[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", base + CCM_CSCDR1, 16, 3); - clks[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", base + CCM_CSCDR1, 11, 3); - clks[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", base + CCM_CSCDR1, 22, 3); - clks[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", base + CCM_CSCDR1, 19, 3); clks[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", base + CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel)); clks[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", base + CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel)); - clks[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", base + CCM_CBCDR, 26, 1, emi_slow_sel, ARRAY_SIZE(emi_slow_sel)); clks[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", base + CCM_CBCDR, 22, 3); clks[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", base + CCM_CBCDR, 13, 3); - clks[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + CCM_CSCMR1, 4, 2, - standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); - clks[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", base + CCM_CSCDR2, 25, 3); - clks[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", base + CCM_CSCDR2, 19, 6); clks[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", base + CCM_CSCMR1, 22, 2, standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); clks[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", base + CCM_CSCDR1, 8, 3); @@ -243,7 +272,6 @@ static void __init mx5_clocks_common_init(struct device_d *dev, void __iomem *ba clks[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", base + CCM_CDCDR, 0, 3); clks[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", base + CCM_CSCMR1, 26, 1, usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str)); - clks[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", base + CCM_CACRR, 0, 3); } static void mx5_clocks_ipu_init(void __iomem *regs) @@ -251,6 +279,73 @@ static void mx5_clocks_ipu_init(void __iomem *regs) clks[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", regs + CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel)); } +int __init mx50_clocks_init(struct device_d *dev, void __iomem *regs) +{ + clks[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", + (void *)MX50_PLL1_BASE_ADDR); + clks[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", + (void *)MX50_PLL2_BASE_ADDR); + clks[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", + (void *)MX50_PLL3_BASE_ADDR); + + mx5_clocks_common_init(dev, regs); + + clks[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", regs + CCM_CCSR, 10, 1, lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); + clks[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", regs + CCM_CBCDR, 25, 2, mx50_periph_clk_sel, ARRAY_SIZE(mx50_periph_clk_sel)); + clks[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", regs + CCM_CSCMR1, 21, 2, standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); + clks[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", regs + CCM_CSCMR1, 16, 3, mx50_3bit_clk_sel, ARRAY_SIZE(mx50_3bit_clk_sel)); + clks[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", regs + CCM_CSCMR1, 20, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel)); + clks[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", regs + CCM_CSCMR1, 19, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel)); + clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX50_UART1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX50_UART2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX50_UART3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX50_I2C1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX50_I2C2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX50_I2C3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX50_GPT1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_IPG], MX50_CSPI_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_ECSPI_PODF], MX50_ECSPI1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_ECSPI_PODF], MX50_ECSPI2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_IPG], MX50_FEC_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_ESDHC_A_PODF], MX50_ESDHC1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_ESDHC_C_SEL], MX50_ESDHC2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_ESDHC_B_PODF], MX50_ESDHC3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_ESDHC_D_SEL], MX50_ESDHC4_BASE_ADDR, NULL); + clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX50_PWM1_BASE_ADDR, "per"); + clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX50_PWM2_BASE_ADDR, "per"); + + return 0; +} + +static int imx50_ccm_probe(struct device_d *dev) +{ + struct resource *iores; + void __iomem *regs; + + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + regs = IOMEM(iores->start); + + mx50_clocks_init(dev, regs); + + return 0; +} + +static __maybe_unused struct of_device_id imx50_ccm_dt_ids[] = { + { + .compatible = "fsl,imx50-ccm", + }, { + /* sentinel */ + } +}; + +static struct driver_d imx50_ccm_driver = { + .probe = imx50_ccm_probe, + .name = "imx50-ccm", + .of_compatible = DRV_OF_COMPAT(imx50_ccm_dt_ids), +}; + static void mx51_clocks_ipu_init(void __iomem *regs) { clks[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_p("ipu_di0_sel", regs + CCM_CSCMR2, 26, 3, @@ -277,6 +372,7 @@ int __init mx51_clocks_init(struct device_d *dev, void __iomem *regs) clks[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX51_PLL3_BASE_ADDR); mx5_clocks_common_init(dev, regs); + mx5_clocks_mx51_mx53_init(regs); clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART1_BASE_ADDR, NULL); clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART2_BASE_ADDR, NULL); @@ -365,6 +461,7 @@ int __init mx53_clocks_init(struct device_d *dev, void __iomem *regs) clks[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", (void *)MX53_PLL4_BASE_ADDR); mx5_clocks_common_init(dev, regs); + mx5_clocks_mx51_mx53_init(regs); clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART1_BASE_ADDR, NULL); clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART2_BASE_ADDR, NULL); @@ -423,6 +520,8 @@ static struct driver_d imx53_ccm_driver = { static int imx5_ccm_init(void) { + if (IS_ENABLED(CONFIG_ARCH_IMX50)) + platform_driver_register(&imx50_ccm_driver); if (IS_ENABLED(CONFIG_ARCH_IMX51)) platform_driver_register(&imx51_ccm_driver); if (IS_ENABLED(CONFIG_ARCH_IMX53)) diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c index 2e33325c9f..5ab6afc9bf 100644 --- a/arch/arm/mach-imx/imx.c +++ b/arch/arm/mach-imx/imx.c @@ -49,6 +49,8 @@ static int imx_soc_from_dt(void) return IMX_CPU_IMX31; if (of_machine_is_compatible("fsl,imx35")) return IMX_CPU_IMX35; + if (of_machine_is_compatible("fsl,imx50")) + return IMX_CPU_IMX50; if (of_machine_is_compatible("fsl,imx51")) return IMX_CPU_IMX51; if (of_machine_is_compatible("fsl,imx53")) @@ -89,6 +91,8 @@ static int imx_init(void) ret = imx31_init(); else if (cpu_is_mx35()) ret = imx35_init(); + else if (cpu_is_mx50()) + ret = imx50_init(); else if (cpu_is_mx51()) ret = imx51_init(); else if (cpu_is_mx53()) @@ -113,6 +117,8 @@ static int imx_init(void) ret = imx31_devices_init(); else if (cpu_is_mx35()) ret = imx35_devices_init(); + else if (cpu_is_mx50()) + ret = imx50_devices_init(); else if (cpu_is_mx51()) ret = imx51_devices_init(); else if (cpu_is_mx53()) diff --git a/arch/arm/mach-imx/imx50.c b/arch/arm/mach-imx/imx50.c new file mode 100644 index 0000000000..fb278a5105 --- /dev/null +++ b/arch/arm/mach-imx/imx50.c @@ -0,0 +1,187 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <init.h> +#include <common.h> +#include <io.h> +#include <notifier.h> +#include <linux/sizes.h> +#include <mach/imx5.h> +#include <mach/imx50-regs.h> +#include <mach/revision.h> +#include <mach/clock-imx51_53.h> +#include <mach/generic.h> + +#define SI_REV 0x48 + +static int imx50_silicon_revision(void) +{ + void __iomem *rom = MX50_IROM_BASE_ADDR; + u32 rev; + u32 mx50_silicon_revision; + + rev = readl(rom + SI_REV); + switch (rev) { + case 0x10: + mx50_silicon_revision = IMX_CHIP_REV_1_0; + break; + case 0x11: + mx50_silicon_revision = IMX_CHIP_REV_1_1; + break; + default: + mx50_silicon_revision = IMX_CHIP_REV_UNKNOWN; + } + + imx_set_silicon_revision("i.MX50", mx50_silicon_revision); + + return 0; +} + +int imx50_init(void) +{ + imx50_silicon_revision(); + imx53_boot_save_loc((void *)MX50_SRC_BASE_ADDR); + + return 0; +} + +int imx50_devices_init(void) +{ + add_generic_device("imx-iomuxv3", 0, NULL, MX50_IOMUXC_BASE_ADDR, + 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx50-ccm", 0, NULL, MX50_CCM_BASE_ADDR, + 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpt", 0, NULL, MX50_GPT1_BASE_ADDR, + 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpio", 0, NULL, MX50_GPIO1_BASE_ADDR, + 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpio", 1, NULL, MX50_GPIO2_BASE_ADDR, + 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpio", 2, NULL, MX50_GPIO3_BASE_ADDR, + 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpio", 3, NULL, MX50_GPIO4_BASE_ADDR, + 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpio", 4, NULL, MX50_GPIO5_BASE_ADDR, + 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-gpio", 5, NULL, MX50_GPIO6_BASE_ADDR, + 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx21-wdt", 0, NULL, MX50_WDOG1_BASE_ADDR, + 0x1000, IORESOURCE_MEM, NULL); + + return 0; +} + +void imx50_init_lowlevel_early(unsigned int cpufreq_mhz) +{ + void __iomem *ccm = (void __iomem *)MX50_CCM_BASE_ADDR; + u32 r; + + imx5_init_lowlevel(); + + /* + * AIPS setup - Only setup MPROTx registers. + * The PACR default values are good. + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, MX50_AIPS1_BASE_ADDR + 0); + writel(0x77777777, MX50_AIPS1_BASE_ADDR + 4); + writel(0x77777777, MX50_AIPS2_BASE_ADDR + 0); + writel(0x77777777, MX50_AIPS2_BASE_ADDR + 4); + + /* Gate of clocks to the peripherals first */ + writel(0x3fffffff, ccm + MX5_CCM_CCGR0); + writel(0x00000000, ccm + MX5_CCM_CCGR1); + writel(0x00000000, ccm + MX5_CCM_CCGR2); + writel(0x00000000, ccm + MX5_CCM_CCGR3); + writel(0x00030000, ccm + MX5_CCM_CCGR4); + writel(0x00fff030, ccm + MX5_CCM_CCGR5); + writel(0x0f00030f, ccm + MX5_CCM_CCGR6); + writel(0x00000000, ccm + MX50_CCM_CCGR7); + + /* Switch ARM to step clock */ + writel(0x4, ccm + MX5_CCM_CCSR); + + if (cpufreq_mhz == 400) + imx5_setup_pll_400((void __iomem *)MX50_PLL1_BASE_ADDR); + else + imx5_setup_pll_800((void __iomem *)MX50_PLL1_BASE_ADDR); + + imx5_setup_pll_216((void __iomem *)MX50_PLL3_BASE_ADDR); + + /* Switch peripheral to PLL3 */ + writel(0x00015154, ccm + MX5_CCM_CBCMR); + writel(0x04880945 | (1<<16), ccm + MX5_CCM_CBCDR); + + /* make sure change is effective */ + while (readl(ccm + MX5_CCM_CDHIPR)); + + imx5_setup_pll_400((void __iomem *)MX50_PLL2_BASE_ADDR); + + /* Switch peripheral to PLL2 */ + r = 0x02800145 | + (2 << 10) | + (0 << 16) | + (1 << 19); + + writel(r, ccm + MX5_CCM_CBCDR); + + r = readl(ccm + MX5_CCM_CSCMR1); + + /* change uart clk parent to pll2 */ + r &= ~MX5_CCM_CSCMR1_UART_CLK_SEL_MASK; + r |= 1 << MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET; + + writel(r, ccm + MX5_CCM_CSCMR1); + + /* make sure change is effective */ + while (readl(ccm + MX5_CCM_CDHIPR)); + + /* Set the platform clock dividers */ + writel(0x00000124, MX50_ARM_BASE_ADDR + 0x14); + + writel(0, ccm + MX5_CCM_CACRR); + + /* Switch ARM back to PLL 1. */ + writel(0, ccm + MX5_CCM_CCSR); + + /* make uart div = 6*/ + r = readl(ccm + MX5_CCM_CSCDR1); + r &= ~0x3f; + r |= 0x0a; + + r &= ~MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK; + r &= ~MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK; + r |= 1 << MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET; + + writel(r, ccm + MX5_CCM_CSCDR1); + + /* Restore the default values in the Gate registers */ + writel(0xffffffff, ccm + MX5_CCM_CCGR0); + writel(0xffffffff, ccm + MX5_CCM_CCGR1); + writel(0xffffffff, ccm + MX5_CCM_CCGR2); + writel(0xffffffff, ccm + MX5_CCM_CCGR3); + writel(0xffffffff, ccm + MX5_CCM_CCGR4); + writel(0xffffffff, ccm + MX5_CCM_CCGR5); + writel(0xffffffff, ccm + MX5_CCM_CCGR6); + writel(0xffffffff, ccm + MX50_CCM_CCGR7); + + writel(0, ccm + MX5_CCM_CCDR); +} + +void imx50_init_lowlevel(unsigned int cpufreq_mhz) +{ + imx50_init_lowlevel_early(cpufreq_mhz); + + clock_notifier_call_chain(); +} diff --git a/arch/arm/mach-imx/include/mach/clock-imx51_53.h b/arch/arm/mach-imx/include/mach/clock-imx51_53.h index 0f25dfbf2f..06ea2e2a3c 100644 --- a/arch/arm/mach-imx/include/mach/clock-imx51_53.h +++ b/arch/arm/mach-imx/include/mach/clock-imx51_53.h @@ -102,6 +102,7 @@ #define MX5_CCM_CCGR4 0x78 #define MX5_CCM_CCGR5 0x7C #define MX5_CCM_CCGR6 0x80 +#define MX50_CCM_CCGR7 0x84 #define MX53_CCM_CCGR7 0x84 #define MX51_CCM_CMEOR 0x84 diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h index 4f2d923aa0..5c2db6cd51 100644 --- a/arch/arm/mach-imx/include/mach/debug_ll.h +++ b/arch/arm/mach-imx/include/mach/debug_ll.h @@ -10,6 +10,7 @@ #include <mach/imx27-regs.h> #include <mach/imx31-regs.h> #include <mach/imx35-regs.h> +#include <mach/imx50-regs.h> #include <mach/imx51-regs.h> #include <mach/imx53-regs.h> #include <mach/imx6-regs.h> @@ -33,6 +34,8 @@ #define IMX_DEBUG_SOC MX31 #elif defined CONFIG_DEBUG_IMX35_UART #define IMX_DEBUG_SOC MX35 +#elif defined CONFIG_DEBUG_IMX50_UART +#define IMX_DEBUG_SOC MX50 #elif defined CONFIG_DEBUG_IMX51_UART #define IMX_DEBUG_SOC MX51 #elif defined CONFIG_DEBUG_IMX53_UART @@ -43,6 +46,13 @@ #error "unknown i.MX debug uart soc type" #endif +static inline void imx50_uart_setup_ll(void) +{ + void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); + + imx50_uart_setup(base); +} + static inline void imx51_uart_setup_ll(void) { void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT)); @@ -76,6 +86,7 @@ static inline void PUTC_LL(int c) } #else +static inline void imx50_uart_setup_ll(void) {} static inline void imx51_uart_setup_ll(void) {} static inline void imx53_uart_setup_ll(void) {} static inline void imx6_uart_setup_ll(void) {} diff --git a/arch/arm/mach-imx/include/mach/devices-imx50.h b/arch/arm/mach-imx/include/mach/devices-imx50.h new file mode 100644 index 0000000000..9e0eaa8cbb --- /dev/null +++ b/arch/arm/mach-imx/include/mach/devices-imx50.h @@ -0,0 +1,83 @@ + +#include <mach/devices.h> +#include <mach/imx50-regs.h> + +static inline struct device_d *imx50_add_spi0(struct spi_imx_master *pdata) +{ + return imx_add_spi_imx51((void *)MX50_ECSPI1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx50_add_spi1(struct spi_imx_master *pdata) +{ + return imx_add_spi_imx51((void *)MX50_ECSPI2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx50_add_cspi(struct spi_imx_master *pdata) +{ + return imx_add_spi_imx35((void *)MX50_CSPI_BASE_ADDR, 2, pdata); +} + +static inline struct device_d *imx50_add_i2c0(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)MX50_I2C1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx50_add_i2c1(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)MX50_I2C2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx50_add_i2c2(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)MX50_I2C3_BASE_ADDR, 2, pdata); +} + +static inline struct device_d *imx50_add_uart0(void) +{ + return imx_add_uart_imx21((void *)MX50_UART1_BASE_ADDR, 0); +} + +static inline struct device_d *imx50_add_uart1(void) +{ + return imx_add_uart_imx21((void *)MX50_UART2_BASE_ADDR, 1); +} + +static inline struct device_d *imx50_add_uart2(void) +{ + return imx_add_uart_imx21((void *)MX50_UART3_BASE_ADDR, 2); +} + +static inline struct device_d *imx50_add_uart3(void) +{ + return imx_add_uart_imx21((void *)MX50_UART4_BASE_ADDR, 3); +} + +static inline struct device_d *imx50_add_fec(struct fec_platform_data *pdata) +{ + return imx_add_fec_imx27((void *)MX50_FEC_BASE_ADDR, pdata); +} + +static inline struct device_d *imx50_add_mmc0(struct esdhc_platform_data *pdata) +{ + return imx_add_esdhc((void *)MX50_ESDHC1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx50_add_mmc1(struct esdhc_platform_data *pdata) +{ + return imx_add_esdhc((void *)MX50_ESDHC2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx50_add_mmc2(struct esdhc_platform_data *pdata) +{ + return imx_add_esdhc((void *)MX50_ESDHC3_BASE_ADDR, 2, pdata); +} + +static inline struct device_d *imx50_add_mmc3(struct esdhc_platform_data *pdata) +{ + return imx_add_esdhc((void *)MX50_ESDHC4_BASE_ADDR, 3, pdata); +} + +static inline struct device_d *imx50_add_kpp(struct matrix_keymap_data *pdata) +{ + return imx_add_kpp((void *)MX50_KPP_BASE_ADDR, pdata); +} diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index 0a4200b3f4..cadc501040 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -11,6 +11,7 @@ u64 imx_uid(void); void imx25_boot_save_loc(void __iomem *ccm_base); void imx35_boot_save_loc(void __iomem *ccm_base); void imx27_boot_save_loc(void __iomem *sysctrl_base); +void imx50_boot_save_loc(void __iomem *src_base); void imx51_boot_save_loc(void __iomem *src_base); void imx53_boot_save_loc(void __iomem *src_base); void imx6_boot_save_loc(void __iomem *src_base); @@ -22,6 +23,7 @@ int imx25_init(void); int imx27_init(void); int imx31_init(void); int imx35_init(void); +int imx50_init(void); int imx51_init(void); int imx53_init(void); int imx6_init(void); @@ -32,6 +34,7 @@ int imx25_devices_init(void); int imx27_devices_init(void); int imx31_devices_init(void); int imx35_devices_init(void); +int imx50_devices_init(void); int imx51_devices_init(void); int imx53_devices_init(void); int imx6_devices_init(void); @@ -117,6 +120,19 @@ extern unsigned int __imx_cpu_type; # define cpu_is_mx35() (0) #endif +#ifdef CONFIG_ARCH_IMX50 +# ifdef imx_cpu_type +# undef imx_cpu_type +# define imx_cpu_type __imx_cpu_type +# else +# define imx_cpu_type IMX_CPU_IMX50 +# endif +# define cpu_is_mx50() (imx_cpu_type == IMX_CPU_IMX50) +#else +# define cpu_is_mx50() (0) +#endif + + #ifdef CONFIG_ARCH_IMX51 # ifdef imx_cpu_type # undef imx_cpu_type diff --git a/arch/arm/mach-imx/include/mach/imx5.h b/arch/arm/mach-imx/include/mach/imx5.h index 5d1a7d7d40..5957141298 100644 --- a/arch/arm/mach-imx/include/mach/imx5.h +++ b/arch/arm/mach-imx/include/mach/imx5.h @@ -1,6 +1,7 @@ #ifndef __MACH_MX5_H #define __MACH_MX5_H +void imx50_init_lowlevel(unsigned int cpufreq_mhz); void imx51_init_lowlevel(unsigned int cpufreq_mhz); void imx53_init_lowlevel(unsigned int cpufreq_mhz); void imx53_init_lowlevel_early(unsigned int cpufreq_mhz); diff --git a/arch/arm/mach-imx/include/mach/imx50-regs.h b/arch/arm/mach-imx/include/mach/imx50-regs.h new file mode 100644 index 0000000000..97ac8e2dad --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx50-regs.h @@ -0,0 +1,92 @@ +#ifndef __MACH_IMX50_REGS_H +#define __MACH_IMX50_REGS_H + +#include <linux/sizes.h> + +#define MX50_IROM_BASE_ADDR 0x0 + +#define MX50_IRAM_BASE_ADDR 0xF8000000 +#define MX50_IRAM_SIZE SZ_128K + +/* + * SPBA global module enabled #0 + */ +#define MX50_SPBA0_BASE_ADDR 0x50000000 +#define MX50_SPBA0_SIZE SZ_1M + +#define MX50_ESDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000) +#define MX50_ESDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000) +#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000C000) +#define MX50_ECSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000) +#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000) +#define MX50_ESDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000) +#define MX50_ESDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000) +#define MX50_SPBA_CTRL_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0003C000) + +/* + * AIPS 1 + */ +#define MX50_AIPS1_BASE_ADDR 0x53F00000 +#define MX50_AIPS1_SIZE SZ_512K + +#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000) +#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000) +#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000) +#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008C000) +#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000) +#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000) +#define MX50_WDOG1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000) +#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000A0000) +#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000A4000) +#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000A8000) +#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000AC000) +#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000B4000) +#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000B8000) +#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000BC000) +#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000C0000) + +#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000D0000) +#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000D4000) +#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000D8000) +#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000DC000) +#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000E0000) +#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000EC000) +#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000F0000) + +/* + * AIPS 2 + */ +#define MX50_AIPS2_BASE_ADDR 0x63F00000 +#define MX50_AIPS2_SIZE SZ_512K + +#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000) +#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000) +#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000) +#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000) +#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000) +#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000A0000) +#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000A4000) +#define MX50_ECSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000AC000) +#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000B0000) +#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000B8000) +#define MX50_CSPI_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000C0000) +#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000C4000) +#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000C8000) +#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000CC000) +#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000D0000) +#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000DA000) +#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000EC000) + +/* + * Memory regions and CS + */ +#define MX50_CSD0_BASE_ADDR 0x70000000 +#define MX50_CSD1_BASE_ADDR 0xB0000000 +#define MX50_CS0_BASE_ADDR 0xF0000000 +#define MX50_CS1_32MB_BASE_ADDR 0xF2000000 +#define MX50_CS1_64MB_BASE_ADDR 0xF4000000 +#define MX50_CS2_64MB_BASE_ADDR 0xF4000000 +#define MX50_CS2_96MB_BASE_ADDR 0xF6000000 +#define MX50_CS3_BASE_ADDR 0xF6000000 + +#endif /* __MACH_IMX50_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx_cpu_types.h b/arch/arm/mach-imx/include/mach/imx_cpu_types.h index 781ab9fe74..84724883b5 100644 --- a/arch/arm/mach-imx/include/mach/imx_cpu_types.h +++ b/arch/arm/mach-imx/include/mach/imx_cpu_types.h @@ -7,6 +7,7 @@ #define IMX_CPU_IMX27 27 #define IMX_CPU_IMX31 31 #define IMX_CPU_IMX35 35 +#define IMX_CPU_IMX50 50 #define IMX_CPU_IMX51 51 #define IMX_CPU_IMX53 53 #define IMX_CPU_IMX6 6 diff --git a/arch/arm/mach-imx/include/mach/iomux-mx50.h b/arch/arm/mach-imx/include/mach/iomux-mx50.h new file mode 100644 index 0000000000..c21bb3ea9b --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-mx50.h @@ -0,0 +1,943 @@ +/* + * Copyright 2013 Greg Ungerer <gerg@uclinux.org> + * Copyright 2016 Alexander Kurz <akurz@blala.de> + * based on linux imx50-pinfunc.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc.. + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_IOMUX_MX50_H__ +#define __MACH_IOMUX_MX50_H__ + +#include <mach/iomux-v3.h> + +/* These 2 defines are for pins that may not have a mux register, but could + * have a pad setting register, and vice-versa. */ +#define __NA_ 0x00 + +#define MX50_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH) +#define MX50_SDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) +#define MX50_I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_ODE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) +#define MX50_SPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x2CC, 0x020, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL0__GPIO4_0 IOMUX_PAD(0x2CC, 0x020, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL0__EIM_NANDF_CLE IOMUX_PAD(0x2CC, 0x020, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL0__CTI_TRIGIN7 IOMUX_PAD(0x2CC, 0x020, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL0__USBPHY1_TXREADY IOMUX_PAD(0x2CC, 0x020, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x2D0, 0x024, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW0__GPIO4_1 IOMUX_PAD(0x2D0, 0x024, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE IOMUX_PAD(0x2D0, 0x024, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 IOMUX_PAD(0x2D0, 0x024, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID IOMUX_PAD(0x2D0, 0x024, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x2D4, 0x028, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__GPIO4_2 IOMUX_PAD(0x2D4, 0x028, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0 IOMUX_PAD(0x2D4, 0x028, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6 IOMUX_PAD(0x2D4, 0x028, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE IOMUX_PAD(0x2D4, 0x028, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x2D8, 0x02C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW1__GPIO4_3 IOMUX_PAD(0x2D8, 0x02C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 IOMUX_PAD(0x2D8, 0x02C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7 IOMUX_PAD(0x2D8, 0x02C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR IOMUX_PAD(0x2D8, 0x02C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL2__KPP_COL_1 IOMUX_PAD(0x2DC, 0x030, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL2__GPIO4_4 IOMUX_PAD(0x2DC, 0x030, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 IOMUX_PAD(0x2DC, 0x030, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL2__CTI_TRIGOUT6 IOMUX_PAD(0x2DC, 0x030, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK IOMUX_PAD(0x2DC, 0x030, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x2E0, 0x034, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW2__GPIO4_5 IOMUX_PAD(0x2E0, 0x034, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 IOMUX_PAD(0x2E0, 0x034, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7 IOMUX_PAD(0x2E0, 0x034, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0 IOMUX_PAD(0x2E0, 0x034, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__KPP_COL_2 IOMUX_PAD(0x2E4, 0x038, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__GPIO4_6 IOMUX_PAD(0x2E4, 0x038, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 IOMUX_PAD(0x2E4, 0x038, 2, 0x7B4, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0 IOMUX_PAD(0x2E4, 0x038, 6, 0x7B8, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1 IOMUX_PAD(0x2E4, 0x038, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x2E8, 0x03C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW3__GPIO4_7 IOMUX_PAD(0x2E8, 0x03C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS IOMUX_PAD(0x2E8, 0x03C, 2, 0x7B0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1 IOMUX_PAD(0x2E8, 0x03C, 6, 0x7BC, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID IOMUX_PAD(0x2E8, 0x03C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x040, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C1_SCL__GPIO6_18 IOMUX_PAD(0x2EC, 0x040, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SCL__UART2_TXD_MUX IOMUX_PAD(0x2EC, 0x040, 2, 0x7CC, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x044, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__GPIO6_19 IOMUX_PAD(0x2F0, 0x044, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__UART2_RXD_MUX IOMUX_PAD(0x2F0, 0x044, 2, 0x7CC, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x048, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__GPIO6_20 IOMUX_PAD(0x2F4, 0x048, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x048, 2, __NA_, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x04C, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__GPIO6_21 IOMUX_PAD(0x2F8, 0x04C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__UART2_RTS IOMUX_PAD(0x2F8, 0x04C, 2, 0x7C8, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x050, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__GPIO6_22 IOMUX_PAD(0x2FC, 0x050, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__FEC_MDC IOMUX_PAD(0x2FC, 0x050, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY IOMUX_PAD(0x2FC, 0x050, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 IOMUX_PAD(0x2FC, 0x050, 5, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x2FC, 0x050, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC IOMUX_PAD(0x2FC, 0x050, 7, 0x7E8, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x054, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__GPIO6_23 IOMUX_PAD(0x300, 0x054, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__FEC_MDIO IOMUX_PAD(0x300, 0x054, 2, 0x774, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT IOMUX_PAD(0x300, 0x054, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB IOMUX_PAD(0x300, 0x054, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__GPT_CAPIN2 IOMUX_PAD(0x300, 0x054, 5, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x300, 0x054, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR IOMUX_PAD(0x300, 0x054, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__PWM1_PWMO IOMUX_PAD(0x304, 0x058, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__GPIO6_24 IOMUX_PAD(0x304, 0x058, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__USBOH1_USBOTG_OC IOMUX_PAD(0x304, 0x058, 2, 0x7E8, 1, NO_PAD_CTRL) +#define MX50_PAD_PWM1__GPT_CMPOUT1 IOMUX_PAD(0x304, 0x058, 5, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x304, 0x058, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__SJC_FAIL IOMUX_PAD(0x304, 0x058, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__PWM2_PWMO IOMUX_PAD(0x308, 0x05C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__GPIO6_25 IOMUX_PAD(0x308, 0x05C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__USBOH1_USBOTG_PWR IOMUX_PAD(0x308, 0x05C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__GPT_CMPOUT2 IOMUX_PAD(0x308, 0x05C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x308, 0x05C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__SRC_ANY_PU_RST IOMUX_PAD(0x308, 0x05C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__OWIRE_LINE IOMUX_PAD(0x30C, 0x060, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__GPIO6_26 IOMUX_PAD(0x30C, 0x060, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__USBOH1_USBH1_OC IOMUX_PAD(0x30C, 0x060, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK IOMUX_PAD(0x30C, 0x060, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__EPDC_PWRIRQ IOMUX_PAD(0x30C, 0x060, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__GPT_CMPOUT3 IOMUX_PAD(0x30C, 0x060, 5, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x30C, 0x060, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__SJC_JTAG_ACT IOMUX_PAD(0x30C, 0x060, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__EPIT1_EPITO IOMUX_PAD(0x310, 0x064, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__GPIO6_27 IOMUX_PAD(0x310, 0x064, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__USBOH1_USBH1_PWR IOMUX_PAD(0x310, 0x064, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK IOMUX_PAD(0x310, 0x064, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__DPLLIP1_TOG_EN IOMUX_PAD(0x310, 0x064, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__GPT_CLK_IN IOMUX_PAD(0x310, 0x064, 5, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__PMU_IRQ_B IOMUX_PAD(0x310, 0x064, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__SJC_DE_B IOMUX_PAD(0x310, 0x064, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__WDOG1_WDOG_B IOMUX_PAD(0x314, 0x068, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__GPIO6_28 IOMUX_PAD(0x314, 0x068, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x314, 0x068, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__CCM_XTAL32K IOMUX_PAD(0x314, 0x068, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__SJC_DONE IOMUX_PAD(0x314, 0x068, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS IOMUX_PAD(0x318, 0x06C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXFS__GPIO6_0 IOMUX_PAD(0x318, 0x06C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1 IOMUX_PAD(0x318, 0x06C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8 IOMUX_PAD(0x318, 0x06C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC IOMUX_PAD(0x31C, 0x070, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXC__GPIO6_1 IOMUX_PAD(0x31C, 0x070, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0 IOMUX_PAD(0x31C, 0x070, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9 IOMUX_PAD(0x31C, 0x070, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD IOMUX_PAD(0x320, 0x074, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__GPIO6_2 IOMUX_PAD(0x320, 0x074, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__CSPI_RDY IOMUX_PAD(0x320, 0x074, 4, 0x6E8, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10 IOMUX_PAD(0x320, 0x074, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD IOMUX_PAD(0x324, 0x078, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__GPIO6_3 IOMUX_PAD(0x324, 0x078, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__CSPI_SS3 IOMUX_PAD(0x324, 0x078, 4, 0x6F4, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11 IOMUX_PAD(0x324, 0x078, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS IOMUX_PAD(0x328, 0x07C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__GPIO6_4 IOMUX_PAD(0x328, 0x07C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__UART5_TXD_MUX IOMUX_PAD(0x328, 0x07C, 2, 0x7E4, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6 IOMUX_PAD(0x328, 0x07C, 3, 0x804, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x07C, 4, 0x6F0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x07C, 5, 0x770, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x07C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12 IOMUX_PAD(0x328, 0x07C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC IOMUX_PAD(0x32C, 0x080, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__GPIO6_5 IOMUX_PAD(0x32C, 0x080, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__UART5_RXD_MUX IOMUX_PAD(0x32C, 0x080, 2, 0x7E4, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_SSI_RXC__EIM_WEIM_D_7 IOMUX_PAD(0x32C, 0x080, 3, 0x808, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__CSPI_SS1 IOMUX_PAD(0x32C, 0x080, 4, 0x6EC, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x080, 5, 0x780, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x080, 6, 0x774, 1, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13 IOMUX_PAD(0x32C, 0x080, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_TXD__UART1_TXD_MUX IOMUX_PAD(0x330, 0x084, 0, 0x7C4, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_TXD__GPIO6_6 IOMUX_PAD(0x330, 0x084, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14 IOMUX_PAD(0x330, 0x084, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_RXD__UART1_RXD_MUX IOMUX_PAD(0x334, 0x088, 0, 0x7C4, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RXD__GPIO6_7 IOMUX_PAD(0x334, 0x088, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15 IOMUX_PAD(0x334, 0x088, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x08C, 0, __NA_, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_CTS__GPIO6_8 IOMUX_PAD(0x338, 0x08C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_CTS__UART5_TXD_MUX IOMUX_PAD(0x338, 0x08C, 2, 0x7E4, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_CTS__ESDHC4_DAT4 IOMUX_PAD(0x338, 0x08C, 4, 0x760, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART1_CTS__ESDHC4_CMD IOMUX_PAD(0x338, 0x08C, 5, 0x74C, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8 IOMUX_PAD(0x338, 0x08C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x090, 0, 0x7C0, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RTS__GPIO6_9 IOMUX_PAD(0x33C, 0x090, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_RTS__UART5_RXD_MUX IOMUX_PAD(0x33C, 0x090, 2, 0x7E4, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RTS__ESDHC4_DAT5 IOMUX_PAD(0x33C, 0x090, 4, 0x764, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART1_RTS__ESDHC4_CLK IOMUX_PAD(0x33C, 0x090, 5, 0x748, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9 IOMUX_PAD(0x33C, 0x090, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_TXD__UART2_TXD_MUX IOMUX_PAD(0x340, 0x094, 0, 0x7CC, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_TXD__GPIO6_10 IOMUX_PAD(0x340, 0x094, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_TXD__ESDHC4_DAT6 IOMUX_PAD(0x340, 0x094, 4, 0x768, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART2_TXD__ESDHC4_DAT4 IOMUX_PAD(0x340, 0x094, 5, 0x760, 1, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10 IOMUX_PAD(0x340, 0x094, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RXD__UART2_RXD_MUX IOMUX_PAD(0x344, 0x098, 0, 0x7CC, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_RXD__GPIO6_11 IOMUX_PAD(0x344, 0x098, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RXD__ESDHC4_DAT7 IOMUX_PAD(0x344, 0x098, 4, 0x76C, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART2_RXD__ESDHC4_DAT5 IOMUX_PAD(0x344, 0x098, 5, 0x764, 1, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11 IOMUX_PAD(0x344, 0x098, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x09C, 0, __NA_, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_CTS__GPIO6_12 IOMUX_PAD(0x348, 0x09C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_CTS__ESDHC4_CMD IOMUX_PAD(0x348, 0x09C, 4, 0x74C, 1, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART2_CTS__ESDHC4_DAT6 IOMUX_PAD(0x348, 0x09C, 5, 0x768, 1, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12 IOMUX_PAD(0x348, 0x09C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0x0A0, 0, 0x7C8, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_RTS__GPIO6_13 IOMUX_PAD(0x34C, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RTS__ESDHC4_CLK IOMUX_PAD(0x34C, 0x0A0, 4, 0x748, 1, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART2_RTS__ESDHC4_DAT7 IOMUX_PAD(0x34C, 0x0A0, 5, 0x76C, 1, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13 IOMUX_PAD(0x34C, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_TXD__UART3_TXD_MUX IOMUX_PAD(0x350, 0x0A4, 0, 0x7D4, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART3_TXD__GPIO6_14 IOMUX_PAD(0x350, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_TXD__ESDHC1_DAT4 IOMUX_PAD(0x350, 0x0A4, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART3_TXD__ESDHC4_DAT0 IOMUX_PAD(0x350, 0x0A4, 4, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART3_TXD__ESDHC2_WP IOMUX_PAD(0x350, 0x0A4, 5, 0x744, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART3_TXD__EIM_WEIM_D_12 IOMUX_PAD(0x350, 0x0A4, 6, 0x81C, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14 IOMUX_PAD(0x350, 0x0A4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_RXD__UART3_RXD_MUX IOMUX_PAD(0x354, 0x0A8, 0, 0x7D4, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART3_RXD__GPIO6_15 IOMUX_PAD(0x354, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_RXD__ESDHC1_DAT5 IOMUX_PAD(0x354, 0x0A8, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART3_RXD__ESDHC4_DAT1 IOMUX_PAD(0x354, 0x0A8, 4, 0x754, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART3_RXD__ESDHC2_CD IOMUX_PAD(0x354, 0x0A8, 5, 0x740, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART3_RXD__EIM_WEIM_D_13 IOMUX_PAD(0x354, 0x0A8, 6, 0x820, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15 IOMUX_PAD(0x354, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_TXD__UART4_TXD_MUX IOMUX_PAD(0x358, 0x0AC, 0, 0x7DC, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_TXD__GPIO6_16 IOMUX_PAD(0x358, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0x0AC, 2, 0x7D0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_TXD__ESDHC1_DAT6 IOMUX_PAD(0x358, 0x0AC, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART4_TXD__ESDHC4_DAT2 IOMUX_PAD(0x358, 0x0AC, 4, 0x758, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART4_TXD__ESDHC2_LCTL IOMUX_PAD(0x358, 0x0AC, 5, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART4_TXD__EIM_WEIM_D_14 IOMUX_PAD(0x358, 0x0AC, 6, 0x824, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_RXD__UART4_RXD_MUX IOMUX_PAD(0x35C, 0x0B0, 0, 0x7DC, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_RXD__GPIO6_17 IOMUX_PAD(0x35C, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_RXD__UART3_RTS IOMUX_PAD(0x35C, 0x0B0, 2, 0x7D0, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_RXD__ESDHC1_DAT7 IOMUX_PAD(0x35C, 0x0B0, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART4_RXD__ESDHC4_DAT3 IOMUX_PAD(0x35C, 0x0B0, 4, 0x75C, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART4_RXD__ESDHC1_LCTL IOMUX_PAD(0x35C, 0x0B0, 5, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_UART4_RXD__EIM_WEIM_D_15 IOMUX_PAD(0x35C, 0x0B0, 6, 0x828, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_SCLK__CSPI_SCLK IOMUX_PAD(0x360, 0x0B4, 0, __NA_, 0, MX50_SPI_PAD_CTRL) +#define MX50_PAD_CSPI_SCLK__GPIO4_8 IOMUX_PAD(0x360, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0x0B8, 0, __NA_, 0, MX50_SPI_PAD_CTRL) +#define MX50_PAD_CSPI_MOSI__GPIO4_9 IOMUX_PAD(0x364, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0x0BC, 0, __NA_, 0, MX50_SPI_PAD_CTRL) +#define MX50_PAD_CSPI_MISO__GPIO4_10 IOMUX_PAD(0x368, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_SS0__GPIO4_11 IOMUX_PAD(0x36C, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x370, 0x0C4, 0, __NA_, 0, MX50_SPI_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__GPIO4_12 IOMUX_PAD(0x370, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY IOMUX_PAD(0x370, 0x0C4, 2, 0x6E8, 1, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY IOMUX_PAD(0x370, 0x0C4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__UART3_RTS IOMUX_PAD(0x370, 0x0C4, 4, 0x7D0, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6 IOMUX_PAD(0x370, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8 IOMUX_PAD(0x370, 0x0C4, 7, 0x80C, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x374, 0x0C8, 0, __NA_, 0, MX50_SPI_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__GPIO4_13 IOMUX_PAD(0x374, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0x0C8, 2, 0x6EC, 1, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0x0C8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0x0C8, 4, __NA_, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7 IOMUX_PAD(0x374, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9 IOMUX_PAD(0x374, 0x0C8, 7, 0x810, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x378, 0x0CC, 0, __NA_, 0, MX50_SPI_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__GPIO4_14 IOMUX_PAD(0x378, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 IOMUX_PAD(0x378, 0x0CC, 2, 0x6F0, 1, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 IOMUX_PAD(0x378, 0x0CC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__UART4_RTS IOMUX_PAD(0x378, 0x0CC, 4, 0x7D8, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8 IOMUX_PAD(0x378, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10 IOMUX_PAD(0x378, 0x0CC, 7, 0x814, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x37C, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SS0__GPIO4_15 IOMUX_PAD(0x37C, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0x0D0, 2, 0x6F4, 1, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0x0D0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0x0D0, 4, __NA_, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9 IOMUX_PAD(0x37C, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11 IOMUX_PAD(0x37C, 0x0D0, 7, 0x818, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK IOMUX_PAD(0x380, 0x0D4, 0, __NA_, 0, MX50_SPI_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__GPIO4_16 IOMUX_PAD(0x380, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN IOMUX_PAD(0x380, 0x0D4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY IOMUX_PAD(0x380, 0x0D4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__UART5_RTS IOMUX_PAD(0x380, 0x0D4, 4, 0x7E0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK IOMUX_PAD(0x380, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4 IOMUX_PAD(0x380, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8 IOMUX_PAD(0x380, 0x0D4, 7, 0x80C, 1, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI IOMUX_PAD(0x384, 0x0D8, 0, __NA_, 0, MX50_SPI_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__GPIO4_17 IOMUX_PAD(0x384, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E IOMUX_PAD(0x384, 0x0D8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0x0D8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0x0D8, 4, 0x7E0, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE IOMUX_PAD(0x384, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5 IOMUX_PAD(0x384, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9 IOMUX_PAD(0x384, 0x0D8, 7, 0x810, 1, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0x0DC, 0, __NA_, 0, MX50_SPI_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__GPIO4_18 IOMUX_PAD(0x388, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0x0DC, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0x0DC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX IOMUX_PAD(0x388, 0x0DC, 4, 0x7E4, 4, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0x0DC, 5, 0x73C, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6 IOMUX_PAD(0x388, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10 IOMUX_PAD(0x388, 0x0DC, 7, 0x814, 1, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 IOMUX_PAD(0x38C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__GPIO4_19 IOMUX_PAD(0x38C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS IOMUX_PAD(0x38C, 0x0E0, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3 IOMUX_PAD(0x38C, 0x0E0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX IOMUX_PAD(0x38C, 0x0E0, 4, 0x7E4, 5, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC IOMUX_PAD(0x38C, 0x0E0, 5, 0x6F8, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7 IOMUX_PAD(0x38C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11 IOMUX_PAD(0x38C, 0x0E0, 7, 0x818, 1, NO_PAD_CTRL) +#define MX50_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x390, 0x0E4, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD1_CLK__GPIO5_0 IOMUX_PAD(0x390, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_CLK__CCM_CLKO IOMUX_PAD(0x390, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x394, 0x0E8, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD1_CMD__GPIO5_1 IOMUX_PAD(0x394, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_CMD__CCM_CLKO2 IOMUX_PAD(0x394, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D0__ESDHC1_DAT0 IOMUX_PAD(0x398, 0x0EC, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD1_D0__GPIO5_2 IOMUX_PAD(0x398, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D0__CCM_PLL1_BYP IOMUX_PAD(0x398, 0x0EC, 7, 0x6DC, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D1__ESDHC1_DAT1 IOMUX_PAD(0x39C, 0x0F0, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD1_D1__GPIO5_3 IOMUX_PAD(0x39C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D1__CCM_PLL2_BYP IOMUX_PAD(0x39C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D2__ESDHC1_DAT2 IOMUX_PAD(0x3A0, 0x0F4, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD1_D2__GPIO5_4 IOMUX_PAD(0x3A0, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D2__CCM_PLL3_BYP IOMUX_PAD(0x3A0, 0x0F4, 7, 0x6E4, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D3__ESDHC1_DAT3 IOMUX_PAD(0x3A4, 0x0F8, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD1_D3__GPIO5_5 IOMUX_PAD(0x3A4, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x3A8, 0x0FC, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD2_CLK__GPIO5_6 IOMUX_PAD(0x3A8, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CLK__MSHC_SCLK IOMUX_PAD(0x3A8, 0x0FC, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x3AC, 0x100, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD2_CMD__GPIO5_7 IOMUX_PAD(0x3AC, 0x100, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CMD__MSHC_BS IOMUX_PAD(0x3AC, 0x100, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D0__ESDHC2_DAT0 IOMUX_PAD(0x3B0, 0x104, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD2_D0__GPIO5_8 IOMUX_PAD(0x3B0, 0x104, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D0__MSHC_DATA_0 IOMUX_PAD(0x3B0, 0x104, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D0__KPP_COL_4 IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D1__ESDHC2_DAT1 IOMUX_PAD(0x3B4, 0x108, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD2_D1__GPIO5_9 IOMUX_PAD(0x3B4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D1__MSHC_DATA_1 IOMUX_PAD(0x3B4, 0x108, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D1__KPP_ROW_4 IOMUX_PAD(0x3B4, 0x108, 3, 0x7A0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D2__ESDHC2_DAT2 IOMUX_PAD(0x3B8, 0x10C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD2_D2__GPIO5_10 IOMUX_PAD(0x3B8, 0x10C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D2__MSHC_DATA_2 IOMUX_PAD(0x3B8, 0x10C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D2__KPP_COL_5 IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D3__ESDHC2_DAT3 IOMUX_PAD(0x3BC, 0x110, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD2_D3__GPIO5_11 IOMUX_PAD(0x3BC, 0x110, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D3__MSHC_DATA_3 IOMUX_PAD(0x3BC, 0x110, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D3__KPP_ROW_5 IOMUX_PAD(0x3BC, 0x110, 3, 0x7A4, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__ESDHC2_DAT4 IOMUX_PAD(0x3C0, 0x114, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD2_D4__GPIO5_12 IOMUX_PAD(0x3C0, 0x114, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3C0, 0x114, 2, 0x6D0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__KPP_COL_6 IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__EIM_WEIM_D_0 IOMUX_PAD(0x3C0, 0x114, 4, 0x7EC, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__CCM_CCM_OUT_0 IOMUX_PAD(0x3C0, 0x114, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__ESDHC2_DAT5 IOMUX_PAD(0x3C4, 0x118, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD2_D5__GPIO5_13 IOMUX_PAD(0x3C4, 0x118, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC IOMUX_PAD(0x3C4, 0x118, 2, 0x6CC, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__KPP_ROW_6 IOMUX_PAD(0x3C4, 0x118, 3, 0x7A8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__EIM_WEIM_D_1 IOMUX_PAD(0x3C4, 0x118, 4, 0x7F0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__CCM_CCM_OUT_1 IOMUX_PAD(0x3C4, 0x118, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__ESDHC2_DAT6 IOMUX_PAD(0x3C8, 0x11C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD2_D6__GPIO5_14 IOMUX_PAD(0x3C8, 0x11C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD IOMUX_PAD(0x3C8, 0x11C, 2, 0x6C4, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__KPP_COL_7 IOMUX_PAD(0x3C8, 0x11C, 3, 0x79C, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__EIM_WEIM_D_2 IOMUX_PAD(0x3C8, 0x11C, 4, 0x7F4, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__CCM_CCM_OUT_2 IOMUX_PAD(0x3C8, 0x11C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__ESDHC2_DAT7 IOMUX_PAD(0x3CC, 0x120, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD2_D7__GPIO5_15 IOMUX_PAD(0x3CC, 0x120, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3CC, 0x120, 2, 0x6D8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__KPP_ROW_7 IOMUX_PAD(0x3CC, 0x120, 3, 0x7AC, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__EIM_WEIM_D_3 IOMUX_PAD(0x3CC, 0x120, 4, 0x7F8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__CCM_STOP IOMUX_PAD(0x3CC, 0x120, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__ESDHC2_WP IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD2_WP__GPIO5_16 IOMUX_PAD(0x3D0, 0x124, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD IOMUX_PAD(0x3D0, 0x124, 2, 0x6C8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__EIM_WEIM_D_4 IOMUX_PAD(0x3D0, 0x124, 4, 0x7FC, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__CCM_WAIT IOMUX_PAD(0x3D0, 0x124, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CD__ESDHC2_CD IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD2_CD__GPIO5_17 IOMUX_PAD(0x3D4, 0x128, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC IOMUX_PAD(0x3D4, 0x128, 2, 0x6D4, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CD__EIM_WEIM_D_5 IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CD__CCM_REF_EN_B IOMUX_PAD(0x3D4, 0x128, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D0__ELCDIF_DAT_0 IOMUX_PAD(0x40C, 0x12C, 0, 0x6FC, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D0__GPIO2_0 IOMUX_PAD(0x40C, 0x12C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D0__FEC_TX_CLK IOMUX_PAD(0x40C, 0x12C, 2, 0x78C, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D0__EIM_WEIM_A_16 IOMUX_PAD(0x40C, 0x12C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0 IOMUX_PAD(0x40C, 0x12C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0 IOMUX_PAD(0x40C, 0x12C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D1__ELCDIF_DAT_1 IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D1__GPIO2_1 IOMUX_PAD(0x410, 0x130, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D1__FEC_RX_ERR IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D1__EIM_WEIM_A_17 IOMUX_PAD(0x410, 0x130, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1 IOMUX_PAD(0x410, 0x130, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1 IOMUX_PAD(0x410, 0x130, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D2__ELCDIF_DAT_2 IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D2__GPIO2_2 IOMUX_PAD(0x414, 0x134, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D2__EIM_WEIM_A_18 IOMUX_PAD(0x414, 0x134, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2 IOMUX_PAD(0x414, 0x134, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2 IOMUX_PAD(0x414, 0x134, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__ELCDIF_DAT_3 IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__GPIO2_3 IOMUX_PAD(0x418, 0x138, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__FEC_RDATA_1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__EIM_WEIM_A_19 IOMUX_PAD(0x418, 0x138, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__FEC_COL IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3 IOMUX_PAD(0x418, 0x138, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3 IOMUX_PAD(0x418, 0x138, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D4__ELCDIF_DAT_4 IOMUX_PAD(0x41C, 0x13C, 0, 0x70C, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D4__GPIO2_4 IOMUX_PAD(0x41C, 0x13C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D4__FEC_RDATA_0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D4__EIM_WEIM_A_20 IOMUX_PAD(0x41C, 0x13C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4 IOMUX_PAD(0x41C, 0x13C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4 IOMUX_PAD(0x41C, 0x13C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D5__ELCDIF_DAT_5 IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D5__GPIO2_5 IOMUX_PAD(0x420, 0x140, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D5__EIM_WEIM_A_21 IOMUX_PAD(0x420, 0x140, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5 IOMUX_PAD(0x420, 0x140, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5 IOMUX_PAD(0x420, 0x140, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__ELCDIF_DAT_6 IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__GPIO2_6 IOMUX_PAD(0x424, 0x144, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__FEC_TDATA_1 IOMUX_PAD(0x424, 0x144, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__EIM_WEIM_A_22 IOMUX_PAD(0x424, 0x144, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__FEC_RX_CLK IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6 IOMUX_PAD(0x424, 0x144, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6 IOMUX_PAD(0x424, 0x144, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D7__ELCDIF_DAT_7 IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D7__GPIO2_7 IOMUX_PAD(0x428, 0x148, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D7__FEC_TDATA_0 IOMUX_PAD(0x428, 0x148, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D7__EIM_WEIM_A_23 IOMUX_PAD(0x428, 0x148, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7 IOMUX_PAD(0x428, 0x148, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7 IOMUX_PAD(0x428, 0x148, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_WR__ELCDIF_WR_RWN IOMUX_PAD(0x42C, 0x14C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_WR__GPIO2_16 IOMUX_PAD(0x42C, 0x14C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_WR__ELCDIF_DOTCLK IOMUX_PAD(0x42C, 0x14C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_WR__EIM_WEIM_A_24 IOMUX_PAD(0x42C, 0x14C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8 IOMUX_PAD(0x42C, 0x14C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_WR__USBPHY1_AVALID IOMUX_PAD(0x42C, 0x14C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RD__ELCDIF_RD_E IOMUX_PAD(0x430, 0x150, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RD__GPIO2_19 IOMUX_PAD(0x430, 0x150, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RD__ELCDIF_ENABLE IOMUX_PAD(0x430, 0x150, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RD__EIM_WEIM_A_25 IOMUX_PAD(0x430, 0x150, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9 IOMUX_PAD(0x430, 0x150, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RD__USBPHY1_BVALID IOMUX_PAD(0x430, 0x150, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RS__GPIO2_17 IOMUX_PAD(0x434, 0x154, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73C, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_RS__EIM_WEIM_A_26 IOMUX_PAD(0x434, 0x154, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10 IOMUX_PAD(0x434, 0x154, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION IOMUX_PAD(0x434, 0x154, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__ELCDIF_CS IOMUX_PAD(0x438, 0x158, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__GPIO2_21 IOMUX_PAD(0x438, 0x158, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x6F8, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__EIM_WEIM_A_27 IOMUX_PAD(0x438, 0x158, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__EIM_WEIM_CS_3 IOMUX_PAD(0x438, 0x158, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11 IOMUX_PAD(0x438, 0x158, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__USBPHY1_IDDIG IOMUX_PAD(0x438, 0x158, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__ELCDIF_BUSY IOMUX_PAD(0x43C, 0x15C, 0, 0x6F8, 2, NO_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__GPIO2_18 IOMUX_PAD(0x43C, 0x15C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3 IOMUX_PAD(0x43C, 0x15C, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12 IOMUX_PAD(0x43C, 0x15C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x43C, 0x15C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RESET__ELCDIF_RESET IOMUX_PAD(0x440, 0x160, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RESET__GPIO2_20 IOMUX_PAD(0x440, 0x160, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3 IOMUX_PAD(0x440, 0x160, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13 IOMUX_PAD(0x440, 0x160, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RESET__USBPHY2_BISTOK IOMUX_PAD(0x440, 0x160, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_CMD__ESDHC3_CMD IOMUX_PAD(0x444, 0x164, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD3_CMD__GPIO5_18 IOMUX_PAD(0x444, 0x164, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_CMD__EIM_NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_CMD__SSP_CMD IOMUX_PAD(0x444, 0x164, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_CLK__ESDHC3_CLK IOMUX_PAD(0x448, 0x168, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD3_CLK__GPIO5_19 IOMUX_PAD(0x448, 0x168, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_CLK__EIM_NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_CLK__SSP_CLK IOMUX_PAD(0x448, 0x168, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D0__ESDHC3_DAT0 IOMUX_PAD(0x44C, 0x16C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD3_D0__GPIO5_20 IOMUX_PAD(0x44C, 0x16C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D0__EIM_NANDF_D_4 IOMUX_PAD(0x44C, 0x16C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D0__SSP_D0 IOMUX_PAD(0x44C, 0x16C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D0__CCM_PLL1_BYP IOMUX_PAD(0x44C, 0x16C, 7, 0x6DC, 1, NO_PAD_CTRL) +#define MX50_PAD_SD3_D1__ESDHC3_DAT1 IOMUX_PAD(0x450, 0x170, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD3_D1__GPIO5_21 IOMUX_PAD(0x450, 0x170, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D1__EIM_NANDF_D_5 IOMUX_PAD(0x450, 0x170, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D1__SSP_D1 IOMUX_PAD(0x450, 0x170, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D1__CCM_PLL2_BYP IOMUX_PAD(0x450, 0x170, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D2__ESDHC3_DAT2 IOMUX_PAD(0x454, 0x174, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD3_D2__GPIO5_22 IOMUX_PAD(0x454, 0x174, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D2__EIM_NANDF_D_6 IOMUX_PAD(0x454, 0x174, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D2__SSP_D2 IOMUX_PAD(0x454, 0x174, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D2__CCM_PLL3_BYP IOMUX_PAD(0x454, 0x174, 7, 0x6E4, 1, NO_PAD_CTRL) +#define MX50_PAD_SD3_D3__ESDHC3_DAT3 IOMUX_PAD(0x458, 0x178, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD3_D3__GPIO5_23 IOMUX_PAD(0x458, 0x178, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D3__EIM_NANDF_D_7 IOMUX_PAD(0x458, 0x178, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D3__SSP_D3 IOMUX_PAD(0x458, 0x178, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D4__ESDHC3_DAT4 IOMUX_PAD(0x45C, 0x17C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD3_D4__GPIO5_24 IOMUX_PAD(0x45C, 0x17C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D4__EIM_NANDF_D_0 IOMUX_PAD(0x45C, 0x17C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D4__SSP_D4 IOMUX_PAD(0x45C, 0x17C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D5__ESDHC3_DAT5 IOMUX_PAD(0x460, 0x180, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD3_D5__GPIO5_25 IOMUX_PAD(0x460, 0x180, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D5__EIM_NANDF_D_1 IOMUX_PAD(0x460, 0x180, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D5__SSP_D5 IOMUX_PAD(0x460, 0x180, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D6__ESDHC3_DAT6 IOMUX_PAD(0x464, 0x184, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD3_D6__GPIO5_26 IOMUX_PAD(0x464, 0x184, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D6__EIM_NANDF_D_2 IOMUX_PAD(0x464, 0x184, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D6__SSP_D6 IOMUX_PAD(0x464, 0x184, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D7__ESDHC3_DAT7 IOMUX_PAD(0x468, 0x188, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD3_D7__GPIO5_27 IOMUX_PAD(0x468, 0x188, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D7__EIM_NANDF_D_3 IOMUX_PAD(0x468, 0x188, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D7__SSP_D7 IOMUX_PAD(0x468, 0x188, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_WP__ESDHC3_WP IOMUX_PAD(0x46C, 0x18C, 0, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD3_WP__GPIO5_28 IOMUX_PAD(0x46C, 0x18C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_WP__EIM_NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_WP__SSP_CD IOMUX_PAD(0x46C, 0x18C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_WP__ESDHC4_LCTL IOMUX_PAD(0x46C, 0x18C, 4, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_SD3_WP__EIM_WEIM_CS_3 IOMUX_PAD(0x46C, 0x18C, 5, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__ELCDIF_DAT_8 IOMUX_PAD(0x470, 0x190, 0, 0x71C, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__GPIO2_8 IOMUX_PAD(0x470, 0x190, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__EIM_NANDF_CLE IOMUX_PAD(0x470, 0x190, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__ESDHC1_LCTL IOMUX_PAD(0x470, 0x190, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D8__ESDHC4_CMD IOMUX_PAD(0x470, 0x190, 4, 0x74C, 2, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D8__KPP_COL_4 IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__FEC_TX_CLK IOMUX_PAD(0x470, 0x190, 6, 0x78C, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0 IOMUX_PAD(0x470, 0x190, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__ELCDIF_DAT_9 IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__GPIO2_9 IOMUX_PAD(0x474, 0x194, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__EIM_NANDF_ALE IOMUX_PAD(0x474, 0x194, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__ESDHC2_LCTL IOMUX_PAD(0x474, 0x194, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D9__ESDHC4_CLK IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D9__KPP_ROW_4 IOMUX_PAD(0x474, 0x194, 5, 0x7A0, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__FEC_RX_ER IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1 IOMUX_PAD(0x474, 0x194, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__ELCDIF_DAT_10 IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__GPIO2_10 IOMUX_PAD(0x478, 0x198, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0 IOMUX_PAD(0x478, 0x198, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__ESDHC3_LCTL IOMUX_PAD(0x478, 0x198, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D10__ESDHC4_DAT0 IOMUX_PAD(0x478, 0x198, 4, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D10__KPP_COL_5 IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__FEC_RX_DV IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2 IOMUX_PAD(0x478, 0x198, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__ELCDIF_DAT_11 IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__GPIO2_11 IOMUX_PAD(0x47C, 0x19C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1 IOMUX_PAD(0x47C, 0x19C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__ESDHC4_DAT1 IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D11__KPP_ROW_5 IOMUX_PAD(0x47C, 0x19C, 5, 0x7A4, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__FEC_RDATA_1 IOMUX_PAD(0x47C, 0x19C, 6, 0x77C, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3 IOMUX_PAD(0x47C, 0x19C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__ELCDIF_DAT_12 IOMUX_PAD(0x480, 0x1A0, 0, 0x72C, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__GPIO2_12 IOMUX_PAD(0x480, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2 IOMUX_PAD(0x480, 0x1A0, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__ESDHC1_CD IOMUX_PAD(0x480, 0x1A0, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D12__ESDHC4_DAT2 IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D12__KPP_COL_6 IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__FEC_RDATA_0 IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4 IOMUX_PAD(0x480, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__ELCDIF_DAT_13 IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__GPIO2_13 IOMUX_PAD(0x484, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3 IOMUX_PAD(0x484, 0x1A4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__ESDHC3_CD IOMUX_PAD(0x484, 0x1A4, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D13__ESDHC4_DAT3 IOMUX_PAD(0x484, 0x1A4, 4, 0x75C, 1, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D13__KPP_ROW_6 IOMUX_PAD(0x484, 0x1A4, 5, 0x7A8, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__FEC_TX_EN IOMUX_PAD(0x484, 0x1A4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5 IOMUX_PAD(0x484, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__ELCDIF_DAT_14 IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__GPIO2_14 IOMUX_PAD(0x488, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__EIM_NANDF_READY0 IOMUX_PAD(0x488, 0x1A8, 2, 0x7B4, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__ESDHC1_WP IOMUX_PAD(0x488, 0x1A8, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D14__ESDHC4_WP IOMUX_PAD(0x488, 0x1A8, 4, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D14__KPP_COL_7 IOMUX_PAD(0x488, 0x1A8, 5, 0x79C, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__FEC_TDATA_1 IOMUX_PAD(0x488, 0x1A8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6 IOMUX_PAD(0x488, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__ELCDIF_DAT_15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__GPIO2_15 IOMUX_PAD(0x48C, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__EIM_NANDF_DQS IOMUX_PAD(0x48C, 0x1AC, 2, 0x7B0, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__ESDHC3_RST IOMUX_PAD(0x48C, 0x1AC, 3, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D15__ESDHC4_CD IOMUX_PAD(0x48C, 0x1AC, 4, __NA_, 0, MX50_SDHC_PAD_CTRL) +#define MX50_PAD_DISP_D15__KPP_ROW_7 IOMUX_PAD(0x48C, 0x1AC, 5, 0x7AC, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__FEC_TDATA_0 IOMUX_PAD(0x48C, 0x1AC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7 IOMUX_PAD(0x48C, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__EPDC_SDDO_0 IOMUX_PAD(0x54C, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__GPIO3_0 IOMUX_PAD(0x54C, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__EIM_WEIM_D_0 IOMUX_PAD(0x54C, 0x1B0, 2, 0x7EC, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__ELCDIF_RS IOMUX_PAD(0x54C, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK IOMUX_PAD(0x54C, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0 IOMUX_PAD(0x54C, 0x1B0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x54C, 0x1B0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__EPDC_SDDO_1 IOMUX_PAD(0x550, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__GPIO3_1 IOMUX_PAD(0x550, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__EIM_WEIM_D_1 IOMUX_PAD(0x550, 0x1B4, 2, 0x7F0, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__ELCDIF_CS IOMUX_PAD(0x550, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__ELCDIF_ENABLE IOMUX_PAD(0x550, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1 IOMUX_PAD(0x550, 0x1B4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1 IOMUX_PAD(0x550, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__EPDC_SDDO_2 IOMUX_PAD(0x554, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__GPIO3_2 IOMUX_PAD(0x554, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__EIM_WEIM_D_2 IOMUX_PAD(0x554, 0x1B8, 2, 0x7F4, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN IOMUX_PAD(0x554, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC IOMUX_PAD(0x554, 0x1B8, 4, 0x73C, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2 IOMUX_PAD(0x554, 0x1B8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2 IOMUX_PAD(0x554, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__EPDC_SDDO_3 IOMUX_PAD(0x558, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__GPIO3_3 IOMUX_PAD(0x558, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__EIM_WEIM_D_3 IOMUX_PAD(0x558, 0x1BC, 2, 0x7F8, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__ELCDIF_RD_E IOMUX_PAD(0x558, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC IOMUX_PAD(0x558, 0x1BC, 4, 0x6F8, 3, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3 IOMUX_PAD(0x558, 0x1BC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3 IOMUX_PAD(0x558, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__EPDC_SDDO_4 IOMUX_PAD(0x55C, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__GPIO3_4 IOMUX_PAD(0x55C, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__EIM_WEIM_D_4 IOMUX_PAD(0x55C, 0x1C0, 2, 0x7FC, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4 IOMUX_PAD(0x55C, 0x1C0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4 IOMUX_PAD(0x55C, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__EPDC_SDDO_5 IOMUX_PAD(0x560, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__GPIO3_5 IOMUX_PAD(0x560, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__EIM_WEIM_D_5 IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5 IOMUX_PAD(0x560, 0x1C4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5 IOMUX_PAD(0x560, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__EPDC_SDDO_6 IOMUX_PAD(0x564, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__GPIO3_6 IOMUX_PAD(0x564, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__EIM_WEIM_D_6 IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6 IOMUX_PAD(0x564, 0x1C8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6 IOMUX_PAD(0x564, 0x1C8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__EPDC_SDDO_7 IOMUX_PAD(0x568, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__GPIO3_7 IOMUX_PAD(0x568, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__EIM_WEIM_D_7 IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7 IOMUX_PAD(0x568, 0x1CC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7 IOMUX_PAD(0x568, 0x1CC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__EPDC_SDDO_8 IOMUX_PAD(0x56C, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__GPIO3_8 IOMUX_PAD(0x56C, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__EIM_WEIM_D_8 IOMUX_PAD(0x56C, 0x1D0, 2, 0x80C, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__ELCDIF_DAT_24 IOMUX_PAD(0x56C, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x56C, 0x1D0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0 IOMUX_PAD(0x56C, 0x1D0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__EPDC_SDDO_9 IOMUX_PAD(0x570, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__GPIO3_9 IOMUX_PAD(0x570, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__EIM_WEIM_D_9 IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__ELCDIF_DAT_25 IOMUX_PAD(0x570, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x570, 0x1D4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1 IOMUX_PAD(0x570, 0x1D4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__EPDC_SDDO_10 IOMUX_PAD(0x574, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__GPIO3_10 IOMUX_PAD(0x574, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__EIM_WEIM_D_10 IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__ELCDIF_DAT_26 IOMUX_PAD(0x574, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x574, 0x1D8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2 IOMUX_PAD(0x574, 0x1D8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__EPDC_SDDO_11 IOMUX_PAD(0x578, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__GPIO3_11 IOMUX_PAD(0x578, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__EIM_WEIM_D_11 IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__ELCDIF_DAT_27 IOMUX_PAD(0x578, 0x1DC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x578, 0x1DC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3 IOMUX_PAD(0x578, 0x1DC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__EPDC_SDDO_12 IOMUX_PAD(0x57C, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__GPIO3_12 IOMUX_PAD(0x57C, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__EIM_WEIM_D_12 IOMUX_PAD(0x57C, 0x1E0, 2, 0x81C, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__ELCDIF_DAT_28 IOMUX_PAD(0x57C, 0x1E0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x57C, 0x1E0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4 IOMUX_PAD(0x57C, 0x1E0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__EPDC_SDDO_13 IOMUX_PAD(0x580, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__GPIO3_13 IOMUX_PAD(0x580, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__EIM_WEIM_D_13 IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__ELCDIF_DAT_29 IOMUX_PAD(0x580, 0x1E4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x580, 0x1E4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5 IOMUX_PAD(0x580, 0x1E4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__EPDC_SDDO_14 IOMUX_PAD(0x584, 0x1E8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__GPIO3_14 IOMUX_PAD(0x584, 0x1E8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__EIM_WEIM_D_14 IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__ELCDIF_DAT_30 IOMUX_PAD(0x584, 0x1E8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD IOMUX_PAD(0x584, 0x1E8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x584, 0x1E8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6 IOMUX_PAD(0x584, 0x1E8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__EPDC_SDDO_15 IOMUX_PAD(0x588, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__GPIO3_15 IOMUX_PAD(0x588, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__EIM_WEIM_D_15 IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__ELCDIF_DAT_31 IOMUX_PAD(0x588, 0x1EC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC IOMUX_PAD(0x588, 0x1EC, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x588, 0x1EC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7 IOMUX_PAD(0x588, 0x1EC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__GPIO3_16 IOMUX_PAD(0x58C, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16 IOMUX_PAD(0x58C, 0x1F0, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16 IOMUX_PAD(0x58C, 0x1F0, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS IOMUX_PAD(0x58C, 0x1F0, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x58C, 0x1F0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK IOMUX_PAD(0x58C, 0x1F0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__EPCD_GDSP IOMUX_PAD(0x590, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__GPIO3_17 IOMUX_PAD(0x590, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17 IOMUX_PAD(0x590, 0x1F4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17 IOMUX_PAD(0x590, 0x1F4, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD IOMUX_PAD(0x590, 0x1F4, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x590, 0x1F4, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID IOMUX_PAD(0x590, 0x1F4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__EPCD_GDOE IOMUX_PAD(0x594, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__GPIO3_18 IOMUX_PAD(0x594, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18 IOMUX_PAD(0x594, 0x1F8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18 IOMUX_PAD(0x594, 0x1F8, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC IOMUX_PAD(0x594, 0x1F8, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x594, 0x1F8, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION IOMUX_PAD(0x594, 0x1F8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__EPCD_GDRL IOMUX_PAD(0x598, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__GPIO3_19 IOMUX_PAD(0x598, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19 IOMUX_PAD(0x598, 0x1F8, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19 IOMUX_PAD(0x598, 0x1FC, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS IOMUX_PAD(0x598, 0x1FC, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x598, 0x1FC, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG IOMUX_PAD(0x598, 0x1FC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK IOMUX_PAD(0x59C, 0x200, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__GPIO3_20 IOMUX_PAD(0x59C, 0x200, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20 IOMUX_PAD(0x59C, 0x200, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20 IOMUX_PAD(0x59C, 0x200, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD IOMUX_PAD(0x59C, 0x200, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x59C, 0x200, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x59C, 0x200, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__GPIO3_21 IOMUX_PAD(0x5A0, 0x204, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21 IOMUX_PAD(0x5A0, 0x204, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21 IOMUX_PAD(0x5A0, 0x204, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC IOMUX_PAD(0x5A0, 0x204, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x5A0, 0x204, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY IOMUX_PAD(0x5A0, 0x204, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__EPCD_SDOED IOMUX_PAD(0x5A4, 0x208, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__GPIO3_22 IOMUX_PAD(0x5A4, 0x208, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22 IOMUX_PAD(0x5A4, 0x208, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22 IOMUX_PAD(0x5A4, 0x208, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS IOMUX_PAD(0x5A4, 0x208, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x5A4, 0x208, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID IOMUX_PAD(0x5A4, 0x208, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__EPCD_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__GPIO3_23 IOMUX_PAD(0x5A8, 0x20C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23 IOMUX_PAD(0x5A8, 0x20C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23 IOMUX_PAD(0x5A8, 0x20C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD IOMUX_PAD(0x5A8, 0x20C, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5A8, 0x20C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE IOMUX_PAD(0x5A8, 0x20C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__EPCD_SDLE IOMUX_PAD(0x5AC, 0x210, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__GPIO3_24 IOMUX_PAD(0x5AC, 0x210, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24 IOMUX_PAD(0x5AC, 0x210, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8 IOMUX_PAD(0x5AC, 0x210, 3, 0x71C, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC IOMUX_PAD(0x5AC, 0x210, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5AC, 0x210, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR IOMUX_PAD(0x5AC, 0x210, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN IOMUX_PAD(0x5B0, 0x214, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__GPIO3_25 IOMUX_PAD(0x5B0, 0x214, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25 IOMUX_PAD(0x5B0, 0x214, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9 IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS IOMUX_PAD(0x5B0, 0x214, 4, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x5B0, 0x214, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK IOMUX_PAD(0x5B0, 0x214, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__GPIO3_26 IOMUX_PAD(0x5B4, 0x218, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26 IOMUX_PAD(0x5B4, 0x218, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD IOMUX_PAD(0x5B4, 0x218, 4, 0x6C8, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x5B4, 0x218, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0 IOMUX_PAD(0x5B4, 0x218, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM IOMUX_PAD(0x5B8, 0x21C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__GPIO3_27 IOMUX_PAD(0x5B8, 0x21C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27 IOMUX_PAD(0x5B8, 0x21C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11 IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC IOMUX_PAD(0x5B8, 0x21C, 4, 0x6D4, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x5B8, 0x21C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1 IOMUX_PAD(0x5B8, 0x21C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT IOMUX_PAD(0x5BC, 0x220, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__GPIO3_28 IOMUX_PAD(0x5BC, 0x220, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28 IOMUX_PAD(0x5BC, 0x220, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12 IOMUX_PAD(0x5BC, 0x220, 3, 0x72C, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS IOMUX_PAD(0x5BC, 0x220, 4, 0x6D8, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE IOMUX_PAD(0x5BC, 0x220, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID IOMUX_PAD(0x5BC, 0x220, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0 IOMUX_PAD(0x5C0, 0x224, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 IOMUX_PAD(0x5C0, 0x224, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29 IOMUX_PAD(0x5C0, 0x224, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13 IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD IOMUX_PAD(0x5C0, 0x224, 4, 0x6C4, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x5C0, 0x224, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID IOMUX_PAD(0x5C0, 0x224, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1 IOMUX_PAD(0x5C4, 0x228, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30 IOMUX_PAD(0x5C4, 0x228, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30 IOMUX_PAD(0x5C4, 0x228, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14 IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC IOMUX_PAD(0x5C4, 0x228, 4, 0x6CC, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD IOMUX_PAD(0x5C4, 0x228, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST IOMUX_PAD(0x5C4, 0x228, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2 IOMUX_PAD(0x5C8, 0x22C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31 IOMUX_PAD(0x5C8, 0x22C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31 IOMUX_PAD(0x5C8, 0x22C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15 IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS IOMUX_PAD(0x5C8, 0x22C, 4, 0x6D0, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0 IOMUX_PAD(0x5C8, 0x22C, 6, 0x7B8, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST IOMUX_PAD(0x5C8, 0x22C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3 IOMUX_PAD(0x5CC, 0x230, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20 IOMUX_PAD(0x5CC, 0x230, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2 IOMUX_PAD(0x5CC, 0x230, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1 IOMUX_PAD(0x5CC, 0x230, 6, 0x7BC, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK IOMUX_PAD(0x5CC, 0x230, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0 IOMUX_PAD(0x5D0, 0x234, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM0__GPIO4_21 IOMUX_PAD(0x5D0, 0x234, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3 IOMUX_PAD(0x5D0, 0x234, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK IOMUX_PAD(0x5D0, 0x234, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1 IOMUX_PAD(0x5D4, 0x238, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM1__GPIO4_22 IOMUX_PAD(0x5D4, 0x238, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3 IOMUX_PAD(0x5D4, 0x238, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__EPCD_BDR_0 IOMUX_PAD(0x5D8, 0x23C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__GPIO4_23 IOMUX_PAD(0x5D8, 0x23C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7 IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR1__EPCD_BDR_1 IOMUX_PAD(0x5DC, 0x240, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR1__GPIO4_24 IOMUX_PAD(0x5DC, 0x240, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6 IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0 IOMUX_PAD(0x5E0, 0x244, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__GPIO4_25 IOMUX_PAD(0x5E0, 0x244, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5 IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1 IOMUX_PAD(0x5E4, 0x248, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__GPIO4_26 IOMUX_PAD(0x5E4, 0x248, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4 IOMUX_PAD(0x5E4, 0x248, 3, 0x70C, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2 IOMUX_PAD(0x5E8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__GPIO4_27 IOMUX_PAD(0x5E8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3 IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3 IOMUX_PAD(0x5EC, 0x250, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE3__GPIO4_28 IOMUX_PAD(0x5EC, 0x250, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2 IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4 IOMUX_PAD(0x5F0, 0x254, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE4__GPIO4_29 IOMUX_PAD(0x5F0, 0x254, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1 IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5 IOMUX_PAD(0x5F4, 0x258, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE5__GPIO4_30 IOMUX_PAD(0x5F4, 0x258, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0 IOMUX_PAD(0x5F4, 0x258, 3, 0x6FC, 1, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA0__EIM_WEIM_A_0 IOMUX_PAD(0x5F8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA0__GPIO1_0 IOMUX_PAD(0x5F8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA0__KPP_COL_4 IOMUX_PAD(0x5F8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA0__TPIU_TRACE_0 IOMUX_PAD(0x5F8, 0x25C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0 IOMUX_PAD(0x5F8, 0x25C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA1__EIM_WEIM_A_1 IOMUX_PAD(0x5FC, 0x260, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA1__GPIO1_1 IOMUX_PAD(0x5FC, 0x260, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA1__KPP_ROW_4 IOMUX_PAD(0x5FC, 0x260, 3, 0x7A0, 2, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA1__TPIU_TRACE_1 IOMUX_PAD(0x5FC, 0x260, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1 IOMUX_PAD(0x5FC, 0x260, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA2__EIM_WEIM_A_2 IOMUX_PAD(0x600, 0x264, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA2__GPIO1_2 IOMUX_PAD(0x600, 0x264, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA2__KPP_COL_5 IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA2__TPIU_TRACE_2 IOMUX_PAD(0x600, 0x264, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2 IOMUX_PAD(0x600, 0x264, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA3__EIM_WEIM_A_3 IOMUX_PAD(0x604, 0x268, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA3__GPIO1_3 IOMUX_PAD(0x604, 0x268, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA3__KPP_ROW_5 IOMUX_PAD(0x604, 0x268, 3, 0x7A4, 2, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA3__TPIU_TRACE_3 IOMUX_PAD(0x604, 0x268, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3 IOMUX_PAD(0x604, 0x268, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA4__EIM_WEIM_A_4 IOMUX_PAD(0x608, 0x26C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA4__GPIO1_4 IOMUX_PAD(0x608, 0x26C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA4__KPP_COL_6 IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA4__TPIU_TRACE_4 IOMUX_PAD(0x608, 0x26C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4 IOMUX_PAD(0x608, 0x26C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA5__EIM_WEIM_A_5 IOMUX_PAD(0x60C, 0x270, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA5__GPIO1_5 IOMUX_PAD(0x60C, 0x270, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA5__KPP_ROW_6 IOMUX_PAD(0x60C, 0x270, 3, 0x7A8, 2, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA5__TPIU_TRACE_5 IOMUX_PAD(0x60C, 0x270, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5 IOMUX_PAD(0x60C, 0x270, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA6__EIM_WEIM_A_6 IOMUX_PAD(0x610, 0x274, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA6__GPIO1_6 IOMUX_PAD(0x610, 0x274, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA6__KPP_COL_7 IOMUX_PAD(0x610, 0x274, 3, 0x79C, 2, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA6__TPIU_TRACE_6 IOMUX_PAD(0x610, 0x274, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6 IOMUX_PAD(0x610, 0x274, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA7__EIM_WEIM_A_7 IOMUX_PAD(0x614, 0x278, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA7__GPIO1_7 IOMUX_PAD(0x614, 0x278, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA7__KPP_ROW_7 IOMUX_PAD(0x614, 0x278, 3, 0x7AC, 2, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA7__TPIU_TRACE_7 IOMUX_PAD(0x614, 0x278, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7 IOMUX_PAD(0x614, 0x278, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA8__EIM_WEIM_A_8 IOMUX_PAD(0x618, 0x27C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA8__GPIO1_8 IOMUX_PAD(0x618, 0x27C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA8__EIM_NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA8__TPIU_TRACE_8 IOMUX_PAD(0x618, 0x27C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0 IOMUX_PAD(0x618, 0x27C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA9__EIM_WEIM_A_9 IOMUX_PAD(0x61C, 0x280, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA9__GPIO1_9 IOMUX_PAD(0x61C, 0x280, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA9__EIM_NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA9__TPIU_TRACE_9 IOMUX_PAD(0x61C, 0x280, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1 IOMUX_PAD(0x61C, 0x280, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA10__EIM_WEIM_A_10 IOMUX_PAD(0x620, 0x284, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA10__GPIO1_10 IOMUX_PAD(0x620, 0x284, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0 IOMUX_PAD(0x620, 0x284, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA10__TPIU_TRACE_10 IOMUX_PAD(0x620, 0x284, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2 IOMUX_PAD(0x620, 0x284, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA11__EIM_WEIM_A_11 IOMUX_PAD(0x624, 0x288, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA11__GPIO1_11 IOMUX_PAD(0x624, 0x288, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1 IOMUX_PAD(0x624, 0x288, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA11__TPIU_TRACE_11 IOMUX_PAD(0x624, 0x288, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3 IOMUX_PAD(0x624, 0x288, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA12__EIM_WEIM_A_12 IOMUX_PAD(0x628, 0x28C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA12__GPIO1_12 IOMUX_PAD(0x628, 0x28C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2 IOMUX_PAD(0x628, 0x28C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA12__EPDC_SDCE_6 IOMUX_PAD(0x628, 0x28C, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA12__TPIU_TRACE_12 IOMUX_PAD(0x628, 0x28C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4 IOMUX_PAD(0x628, 0x28C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA13__EIM_WEIM_A_13 IOMUX_PAD(0x62C, 0x290, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA13__GPIO1_13 IOMUX_PAD(0x62C, 0x290, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3 IOMUX_PAD(0x62C, 0x290, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA13__EPDC_SDCE_7 IOMUX_PAD(0x62C, 0x290, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA13__TPIU_TRACE_13 IOMUX_PAD(0x62C, 0x290, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5 IOMUX_PAD(0x62C, 0x290, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA14__EIM_WEIM_A_14 IOMUX_PAD(0x630, 0x294, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA14__GPIO1_14 IOMUX_PAD(0x630, 0x294, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA14__EIM_NANDF_READY0 IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA14__EPDC_SDCE_8 IOMUX_PAD(0x630, 0x294, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA14__TPIU_TRACE_14 IOMUX_PAD(0x630, 0x294, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6 IOMUX_PAD(0x630, 0x294, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA15__EIM_WEIM_A_15 IOMUX_PAD(0x634, 0x298, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA15__GPIO1_15 IOMUX_PAD(0x634, 0x298, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA15__EIM_NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA15__EPDC_SDCE_9 IOMUX_PAD(0x634, 0x298, 3, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA15__TPIU_TRACE_15 IOMUX_PAD(0x634, 0x298, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7 IOMUX_PAD(0x634, 0x298, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2 IOMUX_PAD(0x638, 0x29C, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS2__GPIO1_16 IOMUX_PAD(0x638, 0x29C, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS2__EIM_WEIM_A_27 IOMUX_PAD(0x638, 0x29C, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS2__TPIU_TRCLK IOMUX_PAD(0x638, 0x29C, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0 IOMUX_PAD(0x638, 0x29C, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1 IOMUX_PAD(0x63C, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS1__GPIO1_17 IOMUX_PAD(0x63C, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS1__TPIU_TRCTL IOMUX_PAD(0x63C, 0x2A0, 6, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1 IOMUX_PAD(0x63C, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0 IOMUX_PAD(0x640, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS0__GPIO1_18 IOMUX_PAD(0x640, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2 IOMUX_PAD(0x640, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0 IOMUX_PAD(0x644, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_EB0__GPIO1_19 IOMUX_PAD(0x644, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3 IOMUX_PAD(0x644, 0x2A8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1 IOMUX_PAD(0x648, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_EB1__GPIO1_20 IOMUX_PAD(0x648, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4 IOMUX_PAD(0x648, 0x2AC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT IOMUX_PAD(0x64C, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_WAIT__GPIO1_21 IOMUX_PAD(0x64C, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B IOMUX_PAD(0x64C, 0x2B0, 2, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5 IOMUX_PAD(0x64C, 0x2B0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK IOMUX_PAD(0x650, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_BCLK__GPIO1_22 IOMUX_PAD(0x650, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6 IOMUX_PAD(0x650, 0x2B4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_RDY__EIM_WEIM_RDY IOMUX_PAD(0x654, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_RDY__GPIO1_23 IOMUX_PAD(0x654, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7 IOMUX_PAD(0x654, 0x2B8, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_OE__EIM_WEIM_OE IOMUX_PAD(0x658, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_OE__GPIO1_24 IOMUX_PAD(0x658, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_OE__INT_BOOT IOMUX_PAD(0x658, 0x2BC, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_RW__EIM_WEIM_RW IOMUX_PAD(0x65C, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_RW__GPIO1_25 IOMUX_PAD(0x65C, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_RW__SYSTEM_RST IOMUX_PAD(0x65C, 0x2C0, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_LBA__EIM_WEIM_LBA IOMUX_PAD(0x660, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_LBA__GPIO1_26 IOMUX_PAD(0x660, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_LBA__TESTER_ACK IOMUX_PAD(0x660, 0x2C4, 7, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CRE__EIM_WEIM_CRE IOMUX_PAD(0x664, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CRE__GPIO1_27 IOMUX_PAD(0x664, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX50_H__ */ diff --git a/arch/mips/boot/dtb.c b/arch/mips/boot/dtb.c index 977c837887..e7633a5aff 100644 --- a/arch/mips/boot/dtb.c +++ b/arch/mips/boot/dtb.c @@ -51,7 +51,7 @@ static int of_mips_init(void) return 0; root = of_unflatten_dtb(__dtb_start); - if (root) { + if (!IS_ERR(root)) { pr_debug("using internal DTB\n"); of_set_root_node(root); if (IS_ENABLED(CONFIG_OFDEVICE)) diff --git a/arch/mips/dts/tplink-mr3020.dts b/arch/mips/dts/tplink-mr3020.dts index 831fab8108..1e843ee003 100644 --- a/arch/mips/dts/tplink-mr3020.dts +++ b/arch/mips/dts/tplink-mr3020.dts @@ -1,73 +1,7 @@ -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> - -#include <mips/qca/ar9331.dtsi> +#include <mips/qca/ar9331_tl_mr3020.dts> / { - model = "TP-Link TL-MR3020"; - compatible = "tplink,tl-mr3020"; - aliases { spiflash = &spiflash; }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x2000000>; - }; - - leds { - compatible = "gpio-leds"; - - wlan { - label = "tp-link:green:wlan"; - gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - lan { - label = "tp-link:green:lan"; - gpios = <&gpio 17 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - wps { - label = "tp-link:green:wps"; - gpios = <&gpio 26 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3g { - label = "tp-link:green:3g"; - gpios = <&gpio 27 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; -}; - -&ref { - clock-frequency = <25000000>; -}; - -&uart { - status = "okay"; -}; - -&gpio { - status = "okay"; -}; - -&spi { - num-chipselects = <1>; - status = "okay"; - - /* Spansion S25FL032PIF SPI flash */ - spiflash: s25sl032p@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,s25sl032p", "jedec,spi-nor"; - spi-max-frequency = <104000000>; - reg = <0>; - }; }; diff --git a/arch/openrisc/lib/dtb.c b/arch/openrisc/lib/dtb.c index 4f63a7760f..04bb6d25cc 100644 --- a/arch/openrisc/lib/dtb.c +++ b/arch/openrisc/lib/dtb.c @@ -32,7 +32,7 @@ static int of_openrisc_init(void) return 0; root = of_unflatten_dtb(__dtb_start); - if (root) { + if (!IS_ERR(root)) { pr_debug("using internal DTB\n"); of_set_root_node(root); if (IS_ENABLED(CONFIG_OFDEVICE)) diff --git a/arch/ppc/boards/pcm030/env/init/mtdparts-nor b/arch/ppc/boards/pcm030/env/init/mtdparts-nor index e900a3b223..44c07ead21 100644 --- a/arch/ppc/boards/pcm030/env/init/mtdparts-nor +++ b/arch/ppc/boards/pcm030/env/init/mtdparts-nor @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NOR partitions" - exit -fi - mtdparts="512k(nor0.bareboxlow),4M(nor0.kernel),512k(nor0.oftree),26M(nor0.root),512k(nor0.barebox),512k(nor0.bareboxenv)" kernelname="physmap-flash.0" diff --git a/commands/menu.c b/commands/menu.c index e1079fd51e..72db26e5d1 100644 --- a/commands/menu.c +++ b/commands/menu.c @@ -22,6 +22,7 @@ #include <menu.h> #include <getopt.h> #include <errno.h> +#include <libbb.h> #include <linux/err.h> typedef enum { @@ -146,9 +147,7 @@ static int do_menu_add(struct cmd_menu *cm) if (!m->name) goto free; - m->display = strdup(cm->description); - if (!m->display) - goto free; + menu_add_title(m, strdup(cm->description)); ret = menu_add(m); @@ -271,7 +270,23 @@ static int do_menu_list(struct cmd_menu *cm) } list_for_each_entry(m, &menus->list, list) { - printf("%s: %s\n", m->name, m->display? m->display : m->name); + printf("%s: ", m->name); + if (m->display_lines) { + static char outstr[256]; + int i; + + printf("\n"); + for (i = 0; i < m->display_lines; i++) + /* Conform to menu rendering logic */ + if (IS_ENABLED(CONFIG_SHELL_HUSH)) { + process_escape_sequence(m->display[i], outstr, 256); + printf("\t%s\n", outstr); + } else { + printf("\t%s\n", m->display[i]); + } + } else { + printf("%s\n", m->name); + } if (is_entry(cm)) print_entries(m); } diff --git a/commands/ubi.c b/commands/ubi.c index 65d2d256a8..26b521f374 100644 --- a/commands/ubi.c +++ b/commands/ubi.c @@ -14,10 +14,9 @@ static int do_ubiupdatevol(int argc, char *argv[]) { - int fd_img, fd_vol, ret = 0; + int count, fd_img, fd_vol, ret = 0; uint64_t size = 0; struct stat st; - unsigned int count; void *buf; if (argc - optind < 2) @@ -66,9 +65,10 @@ static int do_ubiupdatevol(int argc, char *argv[]) break; } - ret = write(fd_vol, buf, count); - if (ret < 0) { + count = write(fd_vol, buf, count); + if (count < 0) { perror("write"); + ret = 1; break; } diff --git a/commands/usbgadget.c b/commands/usbgadget.c index fc2252ad09..a7e8d6c0c3 100644 --- a/commands/usbgadget.c +++ b/commands/usbgadget.c @@ -96,7 +96,7 @@ BAREBOX_CMD_HELP_OPT ("-a", "Create CDC ACM function") BAREBOX_CMD_HELP_OPT ("-s", "Create Generic Serial function") BAREBOX_CMD_HELP_OPT ("-A <desc>", "Create Android Fastboot function") BAREBOX_CMD_HELP_OPT ("-D <desc>", "Create DFU function") -BAREBOX_CMD_HELP_OPT ("-d", "Disable the serial gadget") +BAREBOX_CMD_HELP_OPT ("-d", "Disable the currently running gadget") BAREBOX_CMD_HELP_END BAREBOX_CMD_START(usbgadget) diff --git a/common/Kconfig b/common/Kconfig index aa721b52d1..5bd50cb66d 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1043,6 +1043,13 @@ config DEBUG_IMX35_UART Say Y here if you want kernel low-level debugging support on i.MX35. +config DEBUG_IMX50_UART + bool "i.MX50 Debug UART" + depends on ARCH_IMX50 + help + Say Y here if you want kernel low-level debugging support + on i.MX50. + config DEBUG_IMX51_UART bool "i.MX51 Debug UART" depends on ARCH_IMX51 diff --git a/common/boot.c b/common/boot.c index e66bacbb0e..a971cb7a30 100644 --- a/common/boot.c +++ b/common/boot.c @@ -43,7 +43,7 @@ struct bootentries *bootentries_alloc(void) if (IS_ENABLED(CONFIG_MENU)) { bootentries->menu = menu_alloc(); - bootentries->menu->display = basprintf("boot"); + menu_add_title(bootentries->menu, basprintf("boot")); } return bootentries; @@ -61,8 +61,12 @@ void bootentries_free(struct bootentries *bootentries) be->release(be); } - if (bootentries->menu) + if (bootentries->menu) { + int i; + for (i = 0; i < bootentries->menu->display_lines; i++) + free(bootentries->menu->display[i]); free(bootentries->menu->display); + } free(bootentries->menu); free(bootentries); } @@ -165,7 +169,6 @@ static void bootscript_entry_release(struct bootentry *entry) struct bootentry_script *bs = container_of(entry, struct bootentry_script, entry); free(bs->scriptpath); - free(bs->entry.me.display); free(bs); } @@ -250,6 +253,7 @@ static int bootscript_scan_path(struct bootentries *bootentries, const char *pat * - a cdev name * - a full path of a directory containing bootloader spec entries * - a full path of a directory containing bootscripts + * - a nfs:// path * * Returns the number of entries found or a negative error code. */ @@ -263,7 +267,7 @@ int bootentry_create_from_name(struct bootentries *bootentries, if (ret > 0) found += ret; - if (*name == '/') { + if (*name == '/' || !strncmp(name, "nfs://", 6)) { ret = blspec_scan_directory(bootentries, name); if (ret > 0) found += ret; @@ -319,6 +323,7 @@ void bootsources_menu(struct bootentries *bootentries, int timeout) menu_show(bootentries->menu); + menu_remove_entry(bootentries->menu, back_entry); free(back_entry); } diff --git a/common/bootm.c b/common/bootm.c index 78d04d5806..59843195cd 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -336,6 +336,9 @@ int bootm_load_devicetree(struct image_data *data, unsigned long load_address) if (data->os_fit && data->os_fit->oftree) { data->of_root_node = of_unflatten_dtb(data->os_fit->oftree); + + if (IS_ERR(data->of_root_node)) + data->of_root_node = NULL; } else if (data->oftree_file) { size_t size; @@ -367,7 +370,8 @@ int bootm_load_devicetree(struct image_data *data, unsigned long load_address) free(oftree); - if (!data->of_root_node) { + if (IS_ERR(data->of_root_node)) { + data->of_root_node = NULL; pr_err("unable to unflatten devicetree\n"); return -EINVAL; } diff --git a/common/menu.c b/common/menu.c index 9819569f6f..64df458e68 100644 --- a/common/menu.c +++ b/common/menu.c @@ -43,10 +43,13 @@ EXPORT_SYMBOL(menu_get_menus); void menu_free(struct menu *m) { struct menu_entry *me, *tmp; + int i; if (!m) return; free(m->name); + for (i = 0; i < m->display_lines; i++) + free(m->display[i]); free(m->display); free(m->auto_display); @@ -164,7 +167,7 @@ static void __print_entry(const char *str) static void print_menu_entry(struct menu *m, struct menu_entry *me, int selected) { - gotoXY(3, me->num + 1); + gotoXY(3, me->num + m->display_lines); if (me->type == MENU_ENTRY_BOX) { if (me->box_state) @@ -232,14 +235,12 @@ EXPORT_SYMBOL(menu_set_auto_select); static void print_menu(struct menu *m) { struct menu_entry *me; + int i; clear(); - gotoXY(2, 1); - if(m->display) { - __print_entry(m->display); - } else { - puts("Menu : "); - puts(m->name); + for (i = 0; i < m->display_lines; i++) { + gotoXY(2, 1 + i); + __print_entry(m->display[i]); } list_for_each_entry(me, &m->entries, list) { @@ -269,7 +270,7 @@ int menu_show(struct menu *m) countdown = m->auto_select; if (m->auto_select >= 0) { - gotoXY(3, m->nb_entries + 2); + gotoXY(3, m->nb_entries + m->display_lines + 1); if (!m->auto_display) { printf("Auto Select in"); } else { @@ -293,10 +294,10 @@ int menu_show(struct menu *m) } } - gotoXY(3, m->nb_entries + 2); + gotoXY(3, m->nb_entries + m->display_lines + 1); printf("%*c", auto_display_len + 4, ' '); - gotoXY(3, m->selected->num + 1); + gotoXY(3, m->selected->num + m->display_lines); do { struct menu_entry *old_selected = m->selected; @@ -517,3 +518,63 @@ err_free: return ERR_PTR(ret); } EXPORT_SYMBOL(menu_add_command_entry); + +/* + * Add title to menu. + * Lines are separated by explicit char '\n' or by string "\n". + * + * @display: NULL or pointer to the string which will be freed in this function. + * If NULL or zero length string is provided, default title will be added. + */ +void menu_add_title(struct menu *m, char *display) +{ + char *tmp, *src, *dst; + int lines = 1; + int i; + + if (!display || !strlen(display)) { + free(display); + display = xasprintf("Menu : %s", m->name ? m->name : ""); + } + + src = dst = tmp = xstrdup(display); + /* Count lines and separate single string into multiple strings */ + while (*src) { + if (*src == '\\') { + if (*(src + 1) == '\\') { + *dst++ = *src++; + *dst++ = *src++; + continue; + } + if (*(src + 1) == 'n') { + *dst = 0; + src += 2; + dst++; + lines++; + continue; + } + } + if (*src == '\n') { + *dst = 0; + src++; + dst++; + lines++; + continue; + } + *dst++ = *src++; + } + *dst = 0; + + m->display = xzalloc(sizeof(*m->display) * lines); + m->display_lines = lines; + + for (src = tmp, i = 0; i < lines; i++) { + m->display[i] = xstrdup(src); + /* Go to the next line */ + src += strlen(src) + 1; + } + + free(tmp); + free(display); +} +EXPORT_SYMBOL(menu_add_title); diff --git a/common/menutree.c b/common/menutree.c index eb14da0d01..400d1a6939 100644 --- a/common/menutree.c +++ b/common/menutree.c @@ -19,6 +19,7 @@ #include <shell.h> #include <libfile.h> +#include <linux/ctype.h> #include <linux/stat.h> struct menutree { @@ -95,6 +96,7 @@ int menutree(const char *path, int toplevel) glob_t g; int i; char *globpath, *display; + size_t size; menu = menu_alloc(); @@ -106,14 +108,17 @@ int menutree(const char *path, int toplevel) goto out; } - display = read_file_line("%s/title", path); + globpath = basprintf("%s/title", path); + display = read_file(globpath, &size); + free(globpath); if (!display) { eprintf("no title found in %s/title\n", path); ret = -EINVAL; goto out; } - menu->display = shell_expand(display); + strim(display); + menu_add_title(menu, shell_expand(display)); free(display); for (i = 0; i < g.gl_pathc; i++) { diff --git a/defaultenv/defaultenv-2-base/init/automount b/defaultenv/defaultenv-2-base/init/automount index fd1f5a6f49..959b2c148e 100644 --- a/defaultenv/defaultenv-2-base/init/automount +++ b/defaultenv/defaultenv-2-base/init/automount @@ -1,10 +1,5 @@ #!/bin/sh -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "Automountpoints" - exit -fi - # automount tftp server based on $eth0.serverip mkdir -p /mnt/tftp diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c index 66786ffec7..262a904ace 100644 --- a/drivers/mci/imx-esdhc.c +++ b/drivers/mci/imx-esdhc.c @@ -85,7 +85,7 @@ static u32 esdhc_xfertyp(struct mci_cmd *cmd, struct mci_data *data) xfertyp |= COMMAND_RSPTYP_48_BUSY; else if (cmd->resp_type & MMC_RSP_PRESENT) xfertyp |= COMMAND_RSPTYP_48; - if ((cpu_is_mx51() || cpu_is_mx53()) && + if ((cpu_is_mx50() || cpu_is_mx51() || cpu_is_mx53()) && cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= SDHCI_CMD_ABORTCMD; @@ -638,6 +638,8 @@ static __maybe_unused struct of_device_id fsl_esdhc_compatible[] = { { .compatible = "fsl,imx25-esdhc", }, { + .compatible = "fsl,imx50-esdhc", + }, { .compatible = "fsl,imx51-esdhc", }, { .compatible = "fsl,imx53-esdhc", diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 8809238e54..6088512745 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -3,7 +3,7 @@ obj-$(CONFIG_NAND) += nand_ecc.o obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o obj-$(CONFIG_MTD_NAND_IDS) += nand_ids.o -obj-$(CONFIG_NAND) += nand_base.o nand-bb.o +obj-$(CONFIG_NAND) += nand_base.o nand-bb.o nand_timings.o obj-$(CONFIG_NAND_BBT) += nand_bbt.o obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o diff --git a/drivers/mtd/nand/nand_imx.c b/drivers/mtd/nand/nand_imx.c index f54fe21f7d..6f31c28ec6 100644 --- a/drivers/mtd/nand/nand_imx.c +++ b/drivers/mtd/nand/nand_imx.c @@ -24,6 +24,7 @@ #include <init.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> +#include <linux/clk.h> #include <mach/generic.h> #include <mach/imx-nand.h> #include <io.h> @@ -784,16 +785,63 @@ static int get_eccsize(struct mtd_info *mtd) return 8; } -static void preset_v1_v2(struct mtd_info *mtd) +static void preset_v1(struct mtd_info *mtd) { struct nand_chip *nand_chip = mtd->priv; struct imx_nand_host *host = nand_chip->priv; uint16_t config1 = 0; - if (nfc_is_v21()) - config1 |= NFC_V2_CONFIG1_FP_INT; + host->eccsize = 1; + + writew(config1, host->regs + NFC_V1_V2_CONFIG1); + /* preset operation */ + + /* Unlock the internal RAM Buffer */ + writew(0x2, host->regs + NFC_V1_V2_CONFIG); + + /* Blocks to be unlocked */ + writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR); + writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR); + + /* Unlock Block Command for given address range */ + writew(0x4, host->regs + NFC_V1_V2_WRPROT); +} - if (nfc_is_v21() && mtd->writesize) { +static void preset_v2(struct mtd_info *mtd) +{ + struct nand_chip *nand_chip = mtd->priv; + struct imx_nand_host *host = nand_chip->priv; + uint16_t config1 = 0; + int mode; + + mode = onfi_get_async_timing_mode(nand_chip); + if (mode != ONFI_TIMING_MODE_UNKNOWN && !IS_ERR(host->clk)) { + const struct nand_sdr_timings *timings; + + mode = fls(mode) - 1; + if (mode < 0) + mode = 0; + + timings = onfi_async_timing_mode_to_sdr_timings(mode); + if (!IS_ERR(timings)) { + unsigned long rate; + int tRC_min_ns = timings->tRC_min / 1000; + + rate = 1000000000 / tRC_min_ns; + if (tRC_min_ns < 30) + /* If tRC is smaller than 30ns we have to use EDO timing */ + config1 |= NFC_V1_V2_CONFIG1_ONE_CYCLE; + else + /* Otherwise we have two clock cycles per access */ + rate *= 2; + + clk_set_rate(host->clk, rate); + } + } + + config1 |= NFC_V2_CONFIG1_FP_INT; + + if (mtd->writesize) { uint16_t pages_per_block = mtd->erasesize / mtd->writesize; host->eccsize = get_eccsize(mtd); @@ -812,14 +860,8 @@ static void preset_v1_v2(struct mtd_info *mtd) writew(0x2, host->regs + NFC_V1_V2_CONFIG); /* Blocks to be unlocked */ - if (nfc_is_v21()) { - writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR); - writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR); - } else if (nfc_is_v1()) { - writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR); - writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR); - } else - BUG(); + writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR); + writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR); /* Unlock Block Command for given address range */ writew(0x4, host->regs + NFC_V1_V2_WRPROT); @@ -1166,8 +1208,10 @@ static int __init imxnd_probe(struct device_d *dev) host->data_buf = (uint8_t *)(host + 1); + /* No error check, not all SoCs provide a clk yet */ + host->clk = clk_get(dev, NULL); + if (nfc_is_v1() || nfc_is_v21()) { - host->preset = preset_v1_v2; host->send_cmd = send_cmd_v1_v2; host->send_addr = send_addr_v1_v2; host->send_page = send_page_v1_v2; @@ -1189,6 +1233,7 @@ static int __init imxnd_probe(struct device_d *dev) oob_smallpage = &nandv2_hw_eccoob_smallpage; oob_largepage = &nandv2_hw_eccoob_largepage; oob_4kpage = &nandv2_hw_eccoob_4k; /* FIXME : to check */ + host->preset = preset_v2; } else if (nfc_is_v1()) { iores = dev_request_mem_resource(dev, 0); if (IS_ERR(iores)) @@ -1201,6 +1246,7 @@ static int __init imxnd_probe(struct device_d *dev) oob_smallpage = &nandv1_hw_eccoob_smallpage; oob_largepage = &nandv1_hw_eccoob_largepage; oob_4kpage = &nandv1_hw_eccoob_smallpage; /* FIXME : to check */ + host->preset = preset_v1; } else if (nfc_is_v3_2()) { iores = dev_request_mem_resource(dev, 0); if (IS_ERR(iores)) diff --git a/drivers/mtd/nand/nand_timings.c b/drivers/mtd/nand/nand_timings.c new file mode 100644 index 0000000000..7a939510b7 --- /dev/null +++ b/drivers/mtd/nand/nand_timings.c @@ -0,0 +1,251 @@ +/* + * Copyright (C) 2014 Free Electrons + * + * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include <linux/kernel.h> +#include <linux/err.h> +#include <linux/mtd/nand.h> + +static const struct nand_sdr_timings onfi_sdr_timings[] = { + /* Mode 0 */ + { + .tADL_min = 200000, + .tALH_min = 20000, + .tALS_min = 50000, + .tAR_min = 25000, + .tCEA_max = 100000, + .tCEH_min = 20000, + .tCH_min = 20000, + .tCHZ_max = 100000, + .tCLH_min = 20000, + .tCLR_min = 20000, + .tCLS_min = 50000, + .tCOH_min = 0, + .tCS_min = 70000, + .tDH_min = 20000, + .tDS_min = 40000, + .tFEAT_max = 1000000, + .tIR_min = 10000, + .tITC_max = 1000000, + .tRC_min = 100000, + .tREA_max = 40000, + .tREH_min = 30000, + .tRHOH_min = 0, + .tRHW_min = 200000, + .tRHZ_max = 200000, + .tRLOH_min = 0, + .tRP_min = 50000, + .tRST_max = 250000000000, + .tWB_max = 200000, + .tRR_min = 40000, + .tWC_min = 100000, + .tWH_min = 30000, + .tWHR_min = 120000, + .tWP_min = 50000, + .tWW_min = 100000, + }, + /* Mode 1 */ + { + .tADL_min = 100000, + .tALH_min = 10000, + .tALS_min = 25000, + .tAR_min = 10000, + .tCEA_max = 45000, + .tCEH_min = 20000, + .tCH_min = 10000, + .tCHZ_max = 50000, + .tCLH_min = 10000, + .tCLR_min = 10000, + .tCLS_min = 25000, + .tCOH_min = 15000, + .tCS_min = 35000, + .tDH_min = 10000, + .tDS_min = 20000, + .tFEAT_max = 1000000, + .tIR_min = 0, + .tITC_max = 1000000, + .tRC_min = 50000, + .tREA_max = 30000, + .tREH_min = 15000, + .tRHOH_min = 15000, + .tRHW_min = 100000, + .tRHZ_max = 100000, + .tRLOH_min = 0, + .tRP_min = 25000, + .tRR_min = 20000, + .tRST_max = 500000000, + .tWB_max = 100000, + .tWC_min = 45000, + .tWH_min = 15000, + .tWHR_min = 80000, + .tWP_min = 25000, + .tWW_min = 100000, + }, + /* Mode 2 */ + { + .tADL_min = 100000, + .tALH_min = 10000, + .tALS_min = 15000, + .tAR_min = 10000, + .tCEA_max = 30000, + .tCEH_min = 20000, + .tCH_min = 10000, + .tCHZ_max = 50000, + .tCLH_min = 10000, + .tCLR_min = 10000, + .tCLS_min = 15000, + .tCOH_min = 15000, + .tCS_min = 25000, + .tDH_min = 5000, + .tDS_min = 15000, + .tFEAT_max = 1000000, + .tIR_min = 0, + .tITC_max = 1000000, + .tRC_min = 35000, + .tREA_max = 25000, + .tREH_min = 15000, + .tRHOH_min = 15000, + .tRHW_min = 100000, + .tRHZ_max = 100000, + .tRLOH_min = 0, + .tRR_min = 20000, + .tRST_max = 500000000, + .tWB_max = 100000, + .tRP_min = 17000, + .tWC_min = 35000, + .tWH_min = 15000, + .tWHR_min = 80000, + .tWP_min = 17000, + .tWW_min = 100000, + }, + /* Mode 3 */ + { + .tADL_min = 100000, + .tALH_min = 5000, + .tALS_min = 10000, + .tAR_min = 10000, + .tCEA_max = 25000, + .tCEH_min = 20000, + .tCH_min = 5000, + .tCHZ_max = 50000, + .tCLH_min = 5000, + .tCLR_min = 10000, + .tCLS_min = 10000, + .tCOH_min = 15000, + .tCS_min = 25000, + .tDH_min = 5000, + .tDS_min = 10000, + .tFEAT_max = 1000000, + .tIR_min = 0, + .tITC_max = 1000000, + .tRC_min = 30000, + .tREA_max = 20000, + .tREH_min = 10000, + .tRHOH_min = 15000, + .tRHW_min = 100000, + .tRHZ_max = 100000, + .tRLOH_min = 0, + .tRP_min = 15000, + .tRR_min = 20000, + .tRST_max = 500000000, + .tWB_max = 100000, + .tWC_min = 30000, + .tWH_min = 10000, + .tWHR_min = 80000, + .tWP_min = 15000, + .tWW_min = 100000, + }, + /* Mode 4 */ + { + .tADL_min = 70000, + .tALH_min = 5000, + .tALS_min = 10000, + .tAR_min = 10000, + .tCEA_max = 25000, + .tCEH_min = 20000, + .tCH_min = 5000, + .tCHZ_max = 30000, + .tCLH_min = 5000, + .tCLR_min = 10000, + .tCLS_min = 10000, + .tCOH_min = 15000, + .tCS_min = 20000, + .tDH_min = 5000, + .tDS_min = 10000, + .tFEAT_max = 1000000, + .tIR_min = 0, + .tITC_max = 1000000, + .tRC_min = 25000, + .tREA_max = 20000, + .tREH_min = 10000, + .tRHOH_min = 15000, + .tRHW_min = 100000, + .tRHZ_max = 100000, + .tRLOH_min = 5000, + .tRP_min = 12000, + .tRR_min = 20000, + .tRST_max = 500000000, + .tWB_max = 100000, + .tWC_min = 25000, + .tWH_min = 10000, + .tWHR_min = 80000, + .tWP_min = 12000, + .tWW_min = 100000, + }, + /* Mode 5 */ + { + .tADL_min = 70000, + .tALH_min = 5000, + .tALS_min = 10000, + .tAR_min = 10000, + .tCEA_max = 25000, + .tCEH_min = 20000, + .tCH_min = 5000, + .tCHZ_max = 30000, + .tCLH_min = 5000, + .tCLR_min = 10000, + .tCLS_min = 10000, + .tCOH_min = 15000, + .tCS_min = 15000, + .tDH_min = 5000, + .tDS_min = 7000, + .tFEAT_max = 1000000, + .tIR_min = 0, + .tITC_max = 1000000, + .tRC_min = 20000, + .tREA_max = 16000, + .tREH_min = 7000, + .tRHOH_min = 15000, + .tRHW_min = 100000, + .tRHZ_max = 100000, + .tRLOH_min = 5000, + .tRP_min = 10000, + .tRR_min = 20000, + .tRST_max = 500000000, + .tWB_max = 100000, + .tWC_min = 20000, + .tWH_min = 7000, + .tWHR_min = 80000, + .tWP_min = 10000, + .tWW_min = 100000, + }, +}; + +/** + * onfi_async_timing_mode_to_sdr_timings - [NAND Interface] Retrieve NAND + * timings according to the given ONFI timing mode + * @mode: ONFI timing mode + */ +const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode) +{ + if (mode < 0 || mode >= ARRAY_SIZE(onfi_sdr_timings)) + return ERR_PTR(-EINVAL); + + return &onfi_sdr_timings[mode]; +} diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 9a71b3bc25..43ba8f49ec 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -33,12 +33,12 @@ config DRIVER_SPI_IMX_0_0 config DRIVER_SPI_IMX_0_7 bool - depends on ARCH_IMX25 || ARCH_IMX31 || ARCH_IMX35 || ARCH_IMX53 + depends on ARCH_IMX25 || ARCH_IMX31 || ARCH_IMX35 || ARCH_IMX50 || ARCH_IMX53 default y config DRIVER_SPI_IMX_2_3 bool - depends on ARCH_IMX51 || ARCH_IMX53 || ARCH_IMX6 + depends on ARCH_IMX50 || ARCH_IMX51 || ARCH_IMX53 || ARCH_IMX6 default y config DRIVER_SPI_MXS diff --git a/drivers/usb/imx/chipidea-imx.c b/drivers/usb/imx/chipidea-imx.c index a799abe4ee..a6f59261c3 100644 --- a/drivers/usb/imx/chipidea-imx.c +++ b/drivers/usb/imx/chipidea-imx.c @@ -150,13 +150,23 @@ static int imx_chipidea_probe_dt(struct imx_chipidea *ci) static int ci_register_role(struct imx_chipidea *ci) { - if (ci->role_registered) + int ret; + + if (ci->role_registered != IMX_USB_MODE_OTG) return -EBUSY; if (ci->mode == IMX_USB_MODE_HOST) { if (IS_ENABLED(CONFIG_USB_EHCI)) { ci->role_registered = 1; - return ehci_register(ci->dev, &ci->data); + ret = regulator_enable(ci->vbus); + if (ret) + return ret; + + ret = ehci_register(ci->dev, &ci->data); + if (!ret) + return 0; + + regulator_disable(ci->vbus); } else { dev_err(ci->dev, "Host support not available\n"); return -ENODEV; @@ -180,8 +190,12 @@ static int ci_set_mode(struct param_d *param, void *priv) { struct imx_chipidea *ci = priv; - if (ci->role_registered) - return -EBUSY; + if (ci->role_registered != IMX_USB_MODE_OTG) { + if (ci->role_registered == ci->mode) + return 0; + else + return -EBUSY; + } return ci_register_role(ci); } @@ -225,6 +239,7 @@ static int imx_chipidea_probe(struct device_d *dev) ci = xzalloc(sizeof(*ci)); ci->dev = dev; + ci->role_registered = IMX_USB_MODE_OTG; if (IS_ENABLED(CONFIG_OFDEVICE) && dev->device_node) { ret = imx_chipidea_probe_dt(ci); @@ -242,9 +257,8 @@ static int imx_chipidea_probe(struct device_d *dev) } ci->vbus = regulator_get(dev, "vbus"); - - if (!IS_ERR(ci->vbus)) - regulator_enable(ci->vbus); + if (IS_ERR(ci->vbus)) + ci->vbus = NULL; iores = dev_request_mem_resource(dev, 0); if (IS_ERR(iores)) diff --git a/drivers/usb/imx/imx-usb-misc.c b/drivers/usb/imx/imx-usb-misc.c index d938a2cd87..7c18ca2a18 100644 --- a/drivers/usb/imx/imx-usb-misc.c +++ b/drivers/usb/imx/imx-usb-misc.c @@ -447,6 +447,12 @@ static struct platform_device_id imx_usbmisc_ids[] = { .driver_data = (unsigned long)&mx35_data, }, #endif +#ifdef CONFIG_ARCH_IMX50 + { + .name = "imx50-usb-misc", + .driver_data = (unsigned long)&mx5_data, + }, +#endif #ifdef CONFIG_ARCH_IMX51 { .name = "imx51-usb-misc", diff --git a/drivers/video/backlight-pwm.c b/drivers/video/backlight-pwm.c index 7f1715ddde..2915dba174 100644 --- a/drivers/video/backlight-pwm.c +++ b/drivers/video/backlight-pwm.c @@ -156,6 +156,8 @@ static int pwm_backlight_parse_dt(struct device_d *dev, if (ret < 0) return ret; + pwm_backlight->backlight.brightness_max = length - 1; + for (i = 0; i < length; i++) if (pwm_backlight->levels[i] > pwm_backlight->scale) pwm_backlight->scale = pwm_backlight->levels[i]; @@ -165,8 +167,8 @@ static int pwm_backlight_parse_dt(struct device_d *dev, } else { /* We implicitly assume here a linear levels array { 0, 1, 2, ... 100 } */ pwm_backlight->scale = 100; + pwm_backlight->backlight.brightness_max = pwm_backlight->scale; } - pwm_backlight->backlight.brightness_max = pwm_backlight->scale; pwm_backlight->enable_gpio = of_get_named_gpio_flags(node, "enable-gpios", 0, &flags); diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 76a6425be8..66c936ee70 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -742,4 +742,56 @@ static inline bool nand_is_slc(struct nand_chip *chip) return chip->bits_per_cell == 1; } +/** + * struct nand_sdr_timings - SDR NAND chip timings + * + * This struct defines the timing requirements of a SDR NAND chip. + * These informations can be found in every NAND datasheets and the timings + * meaning are described in the ONFI specifications: + * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing + * Parameters) + * + * All these timings are expressed in picoseconds. + */ + +struct nand_sdr_timings { + u32 tALH_min; + u32 tADL_min; + u32 tALS_min; + u32 tAR_min; + u32 tCEA_max; + u32 tCEH_min; + u32 tCH_min; + u32 tCHZ_max; + u32 tCLH_min; + u32 tCLR_min; + u32 tCLS_min; + u32 tCOH_min; + u32 tCS_min; + u32 tDH_min; + u32 tDS_min; + u32 tFEAT_max; + u32 tIR_min; + u32 tITC_max; + u32 tRC_min; + u32 tREA_max; + u32 tREH_min; + u32 tRHOH_min; + u32 tRHW_min; + u32 tRHZ_max; + u32 tRLOH_min; + u32 tRP_min; + u32 tRR_min; + u64 tRST_max; + u32 tWB_max; + u32 tWC_min; + u32 tWH_min; + u32 tWHR_min; + u32 tWP_min; + u32 tWW_min; +}; + +/* get timing characteristics from ONFI timing mode. */ +const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); + #endif /* __LINUX_MTD_NAND_H */ diff --git a/include/menu.h b/include/menu.h index 8b0ffb1f83..3e704a8907 100644 --- a/include/menu.h +++ b/include/menu.h @@ -47,7 +47,10 @@ struct menu_entry { struct menu { char *name; - char *display; + /* Multiline title */ + char **display; + /* Number of lines */ + int display_lines; int auto_select; char *auto_display; @@ -88,6 +91,7 @@ int menu_set_selected_entry(struct menu *m, struct menu_entry* me); int menu_set_selected(struct menu *m, int num); int menu_set_auto_select(struct menu *m, int delay); struct menu* menu_get_menus(void); +void menu_add_title(struct menu *m, char *display); /* * menu entry functions diff --git a/include/serial/imx-uart.h b/include/serial/imx-uart.h index 29b117c51f..901b26add6 100644 --- a/include/serial/imx-uart.h +++ b/include/serial/imx-uart.h @@ -146,6 +146,11 @@ static inline void imx_uart_setup(void __iomem *uartbase, writel(UCR1_UARTEN, uartbase + UCR1); } +static inline void imx50_uart_setup(void __iomem *uartbase) +{ + imx_uart_setup(uartbase, 66666666); +} + static inline void imx51_uart_setup(void __iomem *uartbase) { imx_uart_setup(uartbase, 54000000); diff --git a/lib/xfuncs.c b/lib/xfuncs.c index aaf0788544..1dc2ea92d8 100644 --- a/lib/xfuncs.c +++ b/lib/xfuncs.c @@ -56,10 +56,15 @@ EXPORT_SYMBOL(xzalloc); char *xstrdup(const char *s) { - char *p = strdup(s); + char *p; + + if (!s) + return NULL; + p = strdup(s); if (!p) panic("ERROR: out of memory\n"); + return p; } EXPORT_SYMBOL(xstrdup); diff --git a/scripts/imx/imx-image.c b/scripts/imx/imx-image.c index c0bf9c004f..650a67f604 100644 --- a/scripts/imx/imx-image.c +++ b/scripts/imx/imx-image.c @@ -274,7 +274,7 @@ static int write_mem_v1(uint32_t addr, uint32_t val, int width, int set_bits, in /* * ============================================================================ - * i.MX flash header v2 handling. Found on i.MX53 and i.MX6 + * i.MX flash header v2 handling. Found on i.MX50, i.MX53 and i.MX6 * ============================================================================ */ @@ -380,7 +380,7 @@ static int write_mem_v2(uint32_t addr, uint32_t val, int width, int set_bits, in if (set_bits) cmd |= 3 << 3; if (clear_bits) - cmd |= 2 << 3; + cmd |= 1 << 3; if (curdcd > MAX_DCD - 3) { fprintf(stderr, "At maximum %d dcd entried are allowed\n", MAX_DCD); @@ -450,6 +450,11 @@ static int write_dcd(const char *outfile) static int check(const struct config_data *data, uint32_t cmd, uint32_t addr, uint32_t mask) { + if (data->header_version != 2) { + fprintf(stderr, "DCD check command is not available or " + "not yet implemented for this SOC\n"); + return -EINVAL; + } if (curdcd > MAX_DCD - 3) { fprintf(stderr, "At maximum %d dcd entried are allowed\n", MAX_DCD); return -ENOMEM; diff --git a/scripts/imx/imx-usb-loader.c b/scripts/imx/imx-usb-loader.c index 17324972bf..c0aaa7d629 100644 --- a/scripts/imx/imx-usb-loader.c +++ b/scripts/imx/imx-usb-loader.c @@ -32,6 +32,7 @@ #include <stdlib.h> #include <libusb.h> #include <getopt.h> +#include <endian.h> #include <arpa/inet.h> #include <linux/kernel.h> @@ -45,7 +46,6 @@ #define FT_LOAD_ONLY 0x00 int verbose; -static int skip_image_dcd; static struct libusb_device_handle *usb_dev_handle; static struct usb_id *usb_id; @@ -67,7 +67,7 @@ struct mach_id { struct usb_work { char filename[256]; - unsigned char dcd; + unsigned char do_dcd_once; unsigned char plug; }; @@ -90,6 +90,9 @@ struct mach_id imx_ids[] = { .vid = 0x15a2, .pid = 0x0052, .name = "i.MX50", + .header_type = HDR_MX53, + .mode = MODE_HID, + .max_transfer = 1024, }, { .vid = 0x15a2, .pid = 0x0054, @@ -743,7 +746,45 @@ static int sdp_jump_address(unsigned addr) return 0; } -static int write_dcd_table_ivt(const struct imx_flash_header_v2 *hdr, +static int do_dcd_v2_cmd_write(const unsigned char *dcd) +{ + int set_bits = 0, clear_bits = 0; + int idx, bytes; + struct imx_dcd_v2_write *recs = (struct imx_dcd_v2_write *) dcd; + int num_rec = (ntohs(recs->length) - 4) / + sizeof(struct imx_dcd_v2_write_rec); + printf("DCD write: sub dcd length: 0x%04x, flags: 0x%02x\n", + ntohs(recs->length), recs->param); + + if (recs->param & PARAMETER_FLAG_MASK) { + if (recs->param & PARAMETER_FLAG_SET) + set_bits = 1; + else + clear_bits = 1; + } + bytes = recs->param & 7; + switch (bytes) { + case 1: + case 2: + case 4: + break; + default: + fprintf(stderr, "ERROR: bad DCD write width %i\n", bytes); + return -1; + } + + for (idx = 0; idx < num_rec; idx++) { + const struct imx_dcd_v2_write_rec *record = &recs->data[idx]; + int ret = modify_memory(ntohl(record->addr), + ntohl(record->val), bytes, + set_bits, clear_bits); + if (ret < 0) + return ret; + } + return 0; +} + +static int process_dcd_table_ivt(const struct imx_flash_header_v2 *hdr, const unsigned char *file_start, unsigned cnt) { unsigned char *dcd_end; @@ -751,7 +792,7 @@ static int write_dcd_table_ivt(const struct imx_flash_header_v2 *hdr, #define cvt_dest_to_src (((unsigned char *)hdr) - hdr->self) unsigned char* dcd; const unsigned char *file_end = file_start + cnt; - int err = 0; + struct imx_ivt_header *dcd_hdr; if (!hdr->dcd_ptr) { printf("No dcd table in this ivt\n"); @@ -761,65 +802,60 @@ static int write_dcd_table_ivt(const struct imx_flash_header_v2 *hdr, dcd = hdr->dcd_ptr + cvt_dest_to_src; if ((dcd < file_start) || ((dcd + 4) > file_end)) { - printf("bad dcd_ptr %08x\n", hdr->dcd_ptr); + fprintf(stderr, "bad dcd_ptr %08x\n", hdr->dcd_ptr); return -1; } - m_length = (dcd[1] << 8) + dcd[2]; - - printf("main dcd length %x\n", m_length); - - if ((dcd[0] != 0xd2) || (dcd[3] != 0x40)) { - printf("Unknown tag\n"); + dcd_hdr = (struct imx_ivt_header *) dcd; + if ((dcd_hdr->tag != TAG_DCD_HEADER) || + (dcd_hdr->version != DCD_VERSION)) { + fprintf(stderr, "Error: Unknown DCD header tag\n"); return -1; } - + m_length = ntohs(dcd_hdr->length); dcd_end = dcd + m_length; - if (dcd_end > file_end) { - printf("bad dcd length %08x\n", m_length); + fprintf(stderr, "Error: DCD length %08x exceeds EOF\n", + m_length); return -1; } + printf("main dcd length %x\n", m_length); dcd += 4; while (dcd < dcd_end) { - unsigned s_length = (dcd[1] << 8) + dcd[2]; - unsigned char *s_end = dcd + s_length; - int set_bits = 0, clear_bits = 0; - - printf("command: 0x%02x sub dcd length: 0x%04x, flags: 0x%02x\n", dcd[0], s_length, dcd[3]); - - if ((dcd[0] != 0xcc)) { - printf("Skipping unknown sub tag 0x%02x with len %04x\n", dcd[0], s_length); - usleep(50000); - dcd += s_length; - continue; - } - - if (dcd[3] & PARAMETER_FLAG_MASK) { - if (dcd[3] & PARAMETER_FLAG_SET) - set_bits = 1; - else - clear_bits = 1; - } - - dcd += 4; - - if (s_end > dcd_end) { - printf("error s_end(%p) > dcd_end(%p)\n", s_end, dcd_end); + int ret = 0; + struct imx_ivt_header *cmd_hdr = (struct imx_ivt_header *) dcd; + unsigned s_length = ntohs(cmd_hdr->length); + if (dcd + s_length > file_end) { + fprintf(stderr, "Error: DCD length %08x exceeds EOF\n", + s_length); return -1; } - - while (dcd < s_end) { - unsigned addr = (dcd[0] << 24) | (dcd[1] << 16) | (dcd[2] << 8) | dcd[3]; - unsigned val = (dcd[4] << 24) | (dcd[5] << 16) | (dcd[6] << 8) | dcd[7]; - - dcd += 8; - - modify_memory(addr, val, 4, set_bits, clear_bits); + switch (cmd_hdr->tag) { + case TAG_WRITE: + ret = do_dcd_v2_cmd_write(dcd); + break; + case TAG_CHECK: + fprintf(stderr, "DCD check not implemented yet\n"); + usleep(50000); + break; + case TAG_UNLOCK: + fprintf(stderr, "DCD unlock not implemented yet\n"); + usleep(50000); + break; + case TAG_NOP: + break; + default: + fprintf(stderr, "Skipping unknown DCD sub tag 0x%02x " + "with len %04x\n", cmd_hdr->tag, s_length); + usleep(50000); + break; } + dcd += s_length; + if (ret < 0) + return ret; } - return err; + return 0; } static int get_dcd_range_old(const struct imx_flash_header *hdr, @@ -872,7 +908,6 @@ static int get_dcd_range_old(const struct imx_flash_header *hdr, static int write_dcd_table_old(const struct imx_flash_header *hdr, const unsigned char *file_start, unsigned cnt) { - unsigned val; unsigned char *dcd_end; unsigned char* dcd; int err = get_dcd_range_old(hdr, file_start, cnt, &dcd, &dcd_end); @@ -882,28 +917,26 @@ static int write_dcd_table_old(const struct imx_flash_header *hdr, printf("writing DCD table...\n"); while (dcd < dcd_end) { - unsigned type = (dcd[0] << 0) | (dcd[1] << 8) | (dcd[2] << 16) | (dcd[3] << 24); - unsigned addr = (dcd[4] << 0) | (dcd[5] << 8) | (dcd[6] << 16) | (dcd[7] << 24); - val = (dcd[8] << 0) | (dcd[9] << 8) | (dcd[10] << 16) | (dcd[11] << 24); - dcd += 12; + struct imx_dcd_rec_v1 *rec = (struct imx_dcd_rec_v1 *) dcd; + unsigned type = le32toh(rec->type); + dcd += sizeof *rec; switch (type) { case 1: - if (verbose > 1) - printf("type=%08x *0x%08x = 0x%08x\n", type, addr, val); - err = write_memory(addr, val, 1); - if (err < 0) - return err; - break; + case 2: case 4: if (verbose > 1) - printf("type=%08x *0x%08x = 0x%08x\n", type, addr, val); - err = write_memory(addr, val, 4); + printf("type=%08x *0x%08x = 0x%08x\n", type, + le32toh(rec->addr), + le32toh(rec->val)); + err = write_memory(le32toh(rec->addr), + le32toh(rec->val), type); if (err < 0) return err; break; default: - printf("!!!unknown type=%08x *0x%08x = 0x%08x\n", type, addr, val); + printf("WARNING: unknown DCD type=%08x ignored\n", + type); } } @@ -980,9 +1013,6 @@ static int perform_dcd(unsigned char *p, const unsigned char *file_start, struct imx_flash_header_v2 *hdr = (struct imx_flash_header_v2 *)p; int ret = 0; - if (skip_image_dcd) - return 0; - switch (usb_id->mach_id->header_type) { case HDR_MX51: ret = write_dcd_table_old(ohdr, file_start, cnt); @@ -990,7 +1020,7 @@ static int perform_dcd(unsigned char *p, const unsigned char *file_start, break; case HDR_MX53: - ret = write_dcd_table_ivt(hdr, file_start, cnt); + ret = process_dcd_table_ivt(hdr, file_start, cnt); hdr->dcd_ptr = 0; break; @@ -1066,13 +1096,13 @@ static int process_header(struct usb_work *curr, unsigned char *buf, int cnt, return ret; } - if (curr->dcd) { + if (curr->do_dcd_once) { ret = perform_dcd(p, buf, cnt); if (ret < 0) { printf("!!perform_dcd returned %i\n", ret); return ret; } - curr->dcd = 0; + curr->do_dcd_once = 0; } if (*p_plugin && (!curr->plug) && (!header_cnt)) { @@ -1264,6 +1294,8 @@ int main(int argc, char *argv[]) int opt; char *initfile = NULL; + w.do_dcd_once = 1; + while ((opt = getopt(argc, argv, "cvhi:s")) != -1) { switch (opt) { case 'c': @@ -1278,7 +1310,7 @@ int main(int argc, char *argv[]) initfile = optarg; break; case 's': - skip_image_dcd = 1; + w.do_dcd_once = 0; break; default: exit(1); @@ -1292,7 +1324,6 @@ int main(int argc, char *argv[]) } w.plug = 1; - w.dcd = 1; strncpy(w.filename, argv[optind], sizeof(w.filename) - 1); r = libusb_init(NULL); diff --git a/scripts/imx/imx.c b/scripts/imx/imx.c index 4ec8c89541..c8ee3091e0 100644 --- a/scripts/imx/imx.c +++ b/scripts/imx/imx.c @@ -219,6 +219,7 @@ struct soc_type { static struct soc_type socs[] = { { .name = "imx25", .header_version = 1, .cpu_type = IMX_CPU_IMX25 }, { .name = "imx35", .header_version = 1, .cpu_type = IMX_CPU_IMX35 }, + { .name = "imx50", .header_version = 2, .cpu_type = IMX_CPU_IMX50 }, { .name = "imx51", .header_version = 1, .cpu_type = IMX_CPU_IMX51 }, { .name = "imx53", .header_version = 2, .cpu_type = IMX_CPU_IMX53 }, { .name = "imx6", .header_version = 2, .cpu_type = IMX_CPU_IMX6 }, diff --git a/scripts/imx/imx.h b/scripts/imx/imx.h index 8db7e7b46c..ae3702c116 100644 --- a/scripts/imx/imx.h +++ b/scripts/imx/imx.h @@ -26,14 +26,22 @@ struct imx_boot_data { uint32_t plugin; } __attribute__((packed)); +struct imx_dcd_rec_v1 { + uint32_t type; + uint32_t addr; + uint32_t val; +} __attribute__((packed)); + #define TAG_IVT_HEADER 0xd1 #define IVT_VERSION 0x40 #define TAG_DCD_HEADER 0xd2 #define DCD_VERSION 0x40 +#define TAG_UNLOCK 0xb2 +#define TAG_NOP 0xc0 #define TAG_WRITE 0xcc +#define TAG_CHECK 0xcf #define PARAMETER_FLAG_MASK (1 << 3) #define PARAMETER_FLAG_SET (1 << 4) -#define TAG_CHECK 0xcf struct imx_ivt_header { uint8_t tag; @@ -73,4 +81,17 @@ struct config_data { char *csf; }; +#define MAX_RECORDS_DCD_V2 1024 +struct imx_dcd_v2_write_rec { + uint32_t addr; + uint32_t val; +} __attribute__((packed)); + +struct imx_dcd_v2_write { + uint8_t tag; + uint16_t length; + uint8_t param; + struct imx_dcd_v2_write_rec data[MAX_RECORDS_DCD_V2]; +} __attribute__((packed)); + int parse_config(struct config_data *data, const char *filename); |