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-rw-r--r--drivers/clk/imx/clk-imx7.c17
-rw-r--r--dts/Bindings/arm/amlogic.txt6
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm2835.txt4
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,g3dsys.txt30
-rw-r--r--dts/Bindings/arm/samsung/samsung-boards.txt2
-rw-r--r--dts/Bindings/arm/shmobile.txt12
-rw-r--r--dts/Bindings/arm/stm32/stm32-syscon.txt14
-rw-r--r--dts/Bindings/arm/stm32/stm32.txt (renamed from dts/Bindings/arm/stm32.txt)0
-rw-r--r--dts/Bindings/arm/tegra/nvidia,tegra30-mc.txt18
-rw-r--r--dts/Bindings/arm/ux500/boards.txt2
-rw-r--r--dts/Bindings/bus/ti-sysc.txt6
-rw-r--r--dts/Bindings/clock/actions,s900-cmu.txt47
-rw-r--r--dts/Bindings/clock/amlogic,gxbb-aoclkc.txt1
-rw-r--r--dts/Bindings/clock/amlogic,gxbb-clkc.txt16
-rw-r--r--dts/Bindings/clock/brcm,iproc-clocks.txt26
-rw-r--r--dts/Bindings/clock/nuvoton,npcm750-clk.txt100
-rw-r--r--dts/Bindings/clock/qcom,gcc.txt2
-rw-r--r--dts/Bindings/clock/qcom,rpmh-clk.txt22
-rw-r--r--dts/Bindings/clock/qcom,videocc.txt19
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.txt10
-rw-r--r--dts/Bindings/clock/rockchip.txt77
-rw-r--r--dts/Bindings/clock/st/st,clkgen.txt8
-rw-r--r--dts/Bindings/clock/sunxi-ccu.txt3
-rw-r--r--dts/Bindings/clock/ti/gate.txt2
-rw-r--r--dts/Bindings/clock/ti/interface.txt2
-rw-r--r--dts/Bindings/cpufreq/cpufreq-mediatek.txt2
-rw-r--r--dts/Bindings/devfreq/rk3399_dmc.txt2
-rw-r--r--dts/Bindings/display/bridge/adi,adv7511.txt18
-rw-r--r--dts/Bindings/display/bridge/cdns,dsi.txt133
-rw-r--r--dts/Bindings/display/bridge/renesas,dw-hdmi.txt1
-rw-r--r--dts/Bindings/display/bridge/tda998x.txt5
-rw-r--r--dts/Bindings/display/bridge/thine,thc63lvd1024.txt60
-rw-r--r--dts/Bindings/display/exynos/exynos5433-decon.txt9
-rw-r--r--dts/Bindings/display/renesas,du.txt28
-rw-r--r--dts/Bindings/display/sunxi/sun6i-dsi.txt93
-rw-r--r--dts/Bindings/dma/k3dma.txt1
-rw-r--r--dts/Bindings/dma/renesas,rcar-dmac.txt1
-rw-r--r--dts/Bindings/dma/renesas,usb-dmac.txt2
-rw-r--r--dts/Bindings/dma/ti-edma.txt1
-rw-r--r--dts/Bindings/edac/socfpga-eccmgr.txt (renamed from dts/Bindings/arm/altera/socfpga-eccmgr.txt)35
-rw-r--r--dts/Bindings/firmware/qcom,scm.txt3
-rw-r--r--dts/Bindings/fpga/lattice-machxo2-spi.txt29
-rw-r--r--dts/Bindings/fsi/fsi-master-gpio.txt4
-rw-r--r--dts/Bindings/gpio/gpio-pca953x.txt34
-rw-r--r--dts/Bindings/gpio/renesas,gpio-rcar.txt3
-rw-r--r--dts/Bindings/gpio/snps-dwapb-gpio.txt9
-rw-r--r--dts/Bindings/gpu/arm,mali-midgard.txt2
-rw-r--r--dts/Bindings/gpu/arm,mali-utgard.txt2
-rw-r--r--dts/Bindings/gpu/brcm,bcm-v3d.txt28
-rw-r--r--dts/Bindings/gpu/samsung-scaler.txt27
-rw-r--r--dts/Bindings/hwmon/gpio-fan.txt2
-rw-r--r--dts/Bindings/hwmon/ltc2990.txt36
-rw-r--r--dts/Bindings/i2c/i2c-davinci.txt2
-rw-r--r--dts/Bindings/i2c/i2c-rcar.txt1
-rw-r--r--dts/Bindings/i2c/i2c-s3c2410.txt4
-rw-r--r--dts/Bindings/iio/adc/amlogic,meson-saradc.txt1
-rw-r--r--dts/Bindings/iio/adc/mcp320x.txt2
-rw-r--r--dts/Bindings/iio/adc/samsung,exynos-adc.txt (renamed from dts/Bindings/arm/samsung/exynos-adc.txt)0
-rw-r--r--dts/Bindings/iio/adc/st,stm32-adc.txt6
-rw-r--r--dts/Bindings/iio/adc/st,stm32-dfsdm-adc.txt7
-rw-r--r--dts/Bindings/iio/afe/current-sense-amplifier.txt26
-rw-r--r--dts/Bindings/iio/afe/current-sense-shunt.txt41
-rw-r--r--dts/Bindings/iio/afe/voltage-divider.txt53
-rw-r--r--dts/Bindings/iio/dac/ltc2632.txt14
-rw-r--r--dts/Bindings/iio/dac/ti,dac5571.txt24
-rw-r--r--dts/Bindings/iio/imu/inv_mpu6050.txt12
-rw-r--r--dts/Bindings/iio/imu/st_lsm6dsx.txt1
-rw-r--r--dts/Bindings/iio/potentiostat/lmp91000.txt9
-rw-r--r--dts/Bindings/input/elan_i2c.txt1
-rw-r--r--dts/Bindings/input/mtk-pmic-keys.txt43
-rw-r--r--dts/Bindings/input/rmi4/rmi_2d_sensor.txt2
-rw-r--r--dts/Bindings/input/rotary-encoder.txt2
-rw-r--r--dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt11
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic-v3.txt17
-rw-r--r--dts/Bindings/interrupt-controller/st,stm32-exti.txt3
-rw-r--r--dts/Bindings/ipmi/npcm7xx-kcs-bmc.txt39
-rw-r--r--dts/Bindings/leds/backlight/pwm-backlight.txt6
-rw-r--r--dts/Bindings/leds/backlight/zii,rave-sp-backlight.txt23
-rw-r--r--dts/Bindings/leds/leds-cr0014114.txt54
-rw-r--r--dts/Bindings/leds/leds-lm3601x.txt45
-rw-r--r--dts/Bindings/leds/leds-sc27xx-bltc.txt41
-rw-r--r--dts/Bindings/mailbox/qcom,apcs-kpss-global.txt2
-rw-r--r--dts/Bindings/mailbox/stm32-ipcc.txt47
-rw-r--r--dts/Bindings/marvell.txt516
-rw-r--r--dts/Bindings/media/cdns,csi2rx.txt100
-rw-r--r--dts/Bindings/media/cdns,csi2tx.txt98
-rw-r--r--dts/Bindings/media/i2c/ov7251.txt52
-rw-r--r--dts/Bindings/media/i2c/ov772x.txt40
-rw-r--r--dts/Bindings/media/i2c/panasonic,amg88xx.txt19
-rw-r--r--dts/Bindings/media/rcar_vin.txt138
-rw-r--r--dts/Bindings/media/renesas,ceu.txt7
-rw-r--r--dts/Bindings/media/renesas,rcar-csi2.txt101
-rw-r--r--dts/Bindings/media/stih407-c8sectpfe.txt2
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra20-mc.txt (renamed from dts/Bindings/arm/tegra/nvidia,tegra20-mc.txt)12
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra30-mc.txt5
-rw-r--r--dts/Bindings/mfd/arizona.txt6
-rw-r--r--dts/Bindings/mfd/as3722.txt2
-rw-r--r--dts/Bindings/mfd/axp20x.txt3
-rw-r--r--dts/Bindings/mfd/bd9571mwv.txt21
-rw-r--r--dts/Bindings/mfd/da9063.txt32
-rw-r--r--dts/Bindings/mfd/motorola-cpcap.txt42
-rw-r--r--dts/Bindings/mfd/mt6397.txt8
-rw-r--r--dts/Bindings/mfd/qcom,spmi-pmic.txt3
-rw-r--r--dts/Bindings/mfd/stm32-timers.txt20
-rw-r--r--dts/Bindings/mfd/sun6i-prcm.txt4
-rw-r--r--dts/Bindings/mips/lantiq/rcu.txt2
-rw-r--r--dts/Bindings/mmc/amlogic,meson-gx.txt3
-rw-r--r--dts/Bindings/mmc/bluefield-dw-mshc.txt29
-rw-r--r--dts/Bindings/mmc/exynos-dw-mshc.txt2
-rw-r--r--dts/Bindings/mmc/jz4740.txt38
-rw-r--r--dts/Bindings/mmc/microchip,sdhci-pic32.txt2
-rw-r--r--dts/Bindings/mmc/mmc.txt6
-rw-r--r--dts/Bindings/mmc/sdhci-omap.txt7
-rw-r--r--dts/Bindings/mmc/sdhci-st.txt2
-rw-r--r--dts/Bindings/mmc/tmio_mmc.txt6
-rw-r--r--dts/Bindings/mtd/gpmi-nand.txt5
-rw-r--r--dts/Bindings/mtd/ibm,ndfc.txt (renamed from dts/Bindings/powerpc/4xx/ndfc.txt)0
-rw-r--r--dts/Bindings/mtd/mtk-nand.txt28
-rw-r--r--dts/Bindings/mtd/partition.txt2
-rw-r--r--dts/Bindings/mtd/partitions/brcm,bcm947xx-cfe-partitions.txt42
-rw-r--r--dts/Bindings/mtd/sunxi-nand.txt2
-rw-r--r--dts/Bindings/net/dsa/dsa.txt6
-rw-r--r--dts/Bindings/net/dsa/ksz.txt2
-rw-r--r--dts/Bindings/net/dsa/mt7530.txt2
-rw-r--r--dts/Bindings/net/dsa/qca8k.txt23
-rw-r--r--dts/Bindings/net/dwmac-sun8i.txt21
-rw-r--r--dts/Bindings/net/fsl-tsec-phy.txt68
-rw-r--r--dts/Bindings/net/ibm,emac.txt (renamed from dts/Bindings/powerpc/4xx/emac.txt)0
-rw-r--r--dts/Bindings/net/meson-dwmac.txt1
-rw-r--r--dts/Bindings/net/microchip,lan78xx.txt54
-rw-r--r--dts/Bindings/net/mscc-miim.txt26
-rw-r--r--dts/Bindings/net/mscc-ocelot.txt82
-rw-r--r--dts/Bindings/net/qualcomm-bluetooth.txt30
-rw-r--r--dts/Bindings/net/renesas,ravb.txt1
-rw-r--r--dts/Bindings/net/sff,sfp.txt4
-rw-r--r--dts/Bindings/net/sh_eth.txt1
-rw-r--r--dts/Bindings/net/socionext,uniphier-ave4.txt19
-rw-r--r--dts/Bindings/net/stm32-dwmac.txt18
-rw-r--r--dts/Bindings/net/wireless/qcom,ath10k.txt31
-rw-r--r--dts/Bindings/nvmem/allwinner,sunxi-sid.txt1
-rw-r--r--dts/Bindings/nvmem/zii,rave-sp-eeprom.txt40
-rw-r--r--dts/Bindings/opp/kryo-cpufreq.txt680
-rw-r--r--dts/Bindings/opp/opp.txt7
-rw-r--r--dts/Bindings/pci/designware-pcie.txt24
-rw-r--r--dts/Bindings/pci/hisilicon-pcie.txt2
-rw-r--r--dts/Bindings/pci/kirin-pcie.txt2
-rw-r--r--dts/Bindings/pci/mobiveil-pcie.txt73
-rw-r--r--dts/Bindings/pci/pci-armada8k.txt5
-rw-r--r--dts/Bindings/pci/pci-keystone.txt4
-rw-r--r--dts/Bindings/pci/rcar-pci.txt6
-rw-r--r--dts/Bindings/pci/rockchip-pcie-ep.txt62
-rw-r--r--dts/Bindings/pci/rockchip-pcie-host.txt (renamed from dts/Bindings/pci/rockchip-pcie.txt)0
-rw-r--r--dts/Bindings/pci/xgene-pci.txt7
-rw-r--r--dts/Bindings/phy/phy-mtk-xsphy.txt109
-rw-r--r--dts/Bindings/phy/qcom-qmp-phy.txt3
-rw-r--r--dts/Bindings/phy/qcom-qusb2-phy.txt23
-rw-r--r--dts/Bindings/pinctrl/actions,s900-pinctrl.txt16
-rw-r--r--dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt1
-rw-r--r--dts/Bindings/pinctrl/brcm,bcm2835-gpio.txt18
-rw-r--r--dts/Bindings/pinctrl/meson,pinctrl.txt2
-rw-r--r--dts/Bindings/pinctrl/pinctrl-max77620.txt4
-rw-r--r--dts/Bindings/pinctrl/pinctrl-mcp23s08.txt8
-rw-r--r--dts/Bindings/pinctrl/pinctrl-mt7622.txt10
-rw-r--r--dts/Bindings/pinctrl/pinctrl-rk805.txt4
-rw-r--r--dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt2
-rw-r--r--dts/Bindings/pinctrl/rockchip,pinctrl.txt1
-rw-r--r--dts/Bindings/power/fsl,imx-gpc.txt2
-rw-r--r--dts/Bindings/power/pd-samsung.txt20
-rw-r--r--dts/Bindings/power/power_domain.txt25
-rw-r--r--dts/Bindings/power/renesas,rcar-sysc.txt2
-rw-r--r--dts/Bindings/power/rockchip-io-domain.txt15
-rw-r--r--dts/Bindings/power/supply/ab8500/btemp.txt2
-rw-r--r--dts/Bindings/power/supply/ab8500/chargalg.txt2
-rw-r--r--dts/Bindings/power/supply/ab8500/charger.txt2
-rw-r--r--dts/Bindings/power/supply/bq27xxx.txt1
-rw-r--r--dts/Bindings/power/wakeup-source.txt2
-rw-r--r--dts/Bindings/pps/pps-gpio.txt1
-rw-r--r--dts/Bindings/ptp/ptp-qoriq.txt69
-rw-r--r--dts/Bindings/pwm/pwm-omap-dmtimer.txt2
-rw-r--r--dts/Bindings/regulator/pfuze100.txt6
-rw-r--r--dts/Bindings/regulator/qcom,spmi-regulator.txt45
-rw-r--r--dts/Bindings/regulator/regulator.txt10
-rw-r--r--dts/Bindings/regulator/rohm,bd71837-regulator.txt126
-rw-r--r--dts/Bindings/regulator/sy8106a-regulator.txt23
-rw-r--r--dts/Bindings/remoteproc/qcom,q6v5.txt1
-rw-r--r--dts/Bindings/reserved-memory/qcom,cmd-db.txt37
-rw-r--r--dts/Bindings/reset/renesas,rst.txt2
-rw-r--r--dts/Bindings/rng/brcm,bcm2835.txt9
-rw-r--r--dts/Bindings/rng/samsung,exynos4-rng.txt (renamed from dts/Bindings/crypto/samsung,exynos-rng4.txt)0
-rw-r--r--dts/Bindings/rng/sparc_sun_oracle_rng.txt (renamed from dts/Bindings/sparc_sun_oracle_rng.txt)0
-rw-r--r--dts/Bindings/rtc/nxp,rtc-2123.txt2
-rw-r--r--dts/Bindings/rtc/st,stm32-rtc.txt37
-rw-r--r--dts/Bindings/serial/microchip,pic32-uart.txt2
-rw-r--r--dts/Bindings/soc/qcom/qcom,apr.txt84
-rw-r--r--dts/Bindings/soc/qcom/qcom,geni-se.txt119
-rw-r--r--dts/Bindings/soc/qcom/qcom,smd-rpm.txt1
-rw-r--r--dts/Bindings/soc/qcom/qcom,smd.txt8
-rw-r--r--dts/Bindings/soc/rockchip/power_domain.txt12
-rw-r--r--dts/Bindings/soc/ti/keystone-navigator-qmss.txt9
-rw-r--r--dts/Bindings/sound/adi,ssm2305.txt14
-rw-r--r--dts/Bindings/sound/atmel-i2s.txt47
-rw-r--r--dts/Bindings/sound/cs42xx8.txt2
-rw-r--r--dts/Bindings/sound/fsl,asrc.txt10
-rw-r--r--dts/Bindings/sound/fsl,esai.txt2
-rw-r--r--dts/Bindings/sound/fsl,spdif.txt2
-rw-r--r--dts/Bindings/sound/fsl-sai.txt8
-rw-r--r--dts/Bindings/sound/mt2701-afe-pcm.txt4
-rw-r--r--dts/Bindings/sound/mt6351.txt16
-rw-r--r--dts/Bindings/sound/mt6797-afe-pcm.txt42
-rw-r--r--dts/Bindings/sound/mt6797-mt6351.txt14
-rw-r--r--dts/Bindings/sound/qcom,apq8096.txt109
-rw-r--r--dts/Bindings/sound/qcom,q6adm.txt33
-rw-r--r--dts/Bindings/sound/qcom,q6afe.txt172
-rw-r--r--dts/Bindings/sound/qcom,q6asm.txt33
-rw-r--r--dts/Bindings/sound/qcom,q6core.txt21
-rw-r--r--dts/Bindings/sound/rt274.txt2
-rw-r--r--dts/Bindings/sound/rt5514.txt2
-rw-r--r--dts/Bindings/sound/rt5616.txt2
-rw-r--r--dts/Bindings/sound/rt5640.txt35
-rw-r--r--dts/Bindings/sound/rt5645.txt2
-rw-r--r--dts/Bindings/sound/rt5651.txt2
-rw-r--r--dts/Bindings/sound/rt5663.txt2
-rw-r--r--dts/Bindings/sound/rt5668.txt50
-rw-r--r--dts/Bindings/sound/sgtl5000.txt2
-rw-r--r--dts/Bindings/sound/simple-card.txt5
-rw-r--r--dts/Bindings/sound/st,stm32-i2s.txt2
-rw-r--r--dts/Bindings/sound/st,stm32-sai.txt2
-rw-r--r--dts/Bindings/sound/ti,tas6424.txt2
-rw-r--r--dts/Bindings/sound/tscs42xx.txt6
-rw-r--r--dts/Bindings/sound/tscs454.txt23
-rw-r--r--dts/Bindings/sound/wm8510.txt2
-rw-r--r--dts/Bindings/sound/wm8523.txt2
-rw-r--r--dts/Bindings/sound/wm8524.txt2
-rw-r--r--dts/Bindings/sound/wm8580.txt2
-rw-r--r--dts/Bindings/sound/wm8711.txt2
-rw-r--r--dts/Bindings/sound/wm8728.txt2
-rw-r--r--dts/Bindings/sound/wm8731.txt2
-rw-r--r--dts/Bindings/sound/wm8737.txt2
-rw-r--r--dts/Bindings/sound/wm8741.txt2
-rw-r--r--dts/Bindings/sound/wm8750.txt2
-rw-r--r--dts/Bindings/sound/wm8753.txt2
-rw-r--r--dts/Bindings/sound/wm8770.txt2
-rw-r--r--dts/Bindings/sound/wm8776.txt2
-rw-r--r--dts/Bindings/sound/wm8804.txt2
-rw-r--r--dts/Bindings/sound/wm8903.txt2
-rw-r--r--dts/Bindings/sound/wm8960.txt2
-rw-r--r--dts/Bindings/sound/wm8962.txt2
-rw-r--r--dts/Bindings/sound/wm8994.txt2
-rw-r--r--dts/Bindings/spi/spi-st-ssc.txt2
-rw-r--r--dts/Bindings/submitting-patches.txt9
-rw-r--r--dts/Bindings/thermal/exynos-thermal.txt14
-rw-r--r--dts/Bindings/thermal/imx-thermal.txt9
-rw-r--r--dts/Bindings/thermal/mediatek-thermal.txt1
-rw-r--r--dts/Bindings/thermal/qcom-tsens.txt1
-rw-r--r--dts/Bindings/thermal/rcar-gen3-thermal.txt9
-rw-r--r--dts/Bindings/thermal/rcar-thermal.txt7
-rw-r--r--dts/Bindings/thermal/uniphier-thermal.txt1
-rw-r--r--dts/Bindings/timer/altr,timer-1.0.txt (renamed from dts/Bindings/nios2/timer.txt)0
-rw-r--r--dts/Bindings/timer/arm,arch_timer.txt (renamed from dts/Bindings/arm/arch_timer.txt)0
-rw-r--r--dts/Bindings/timer/arm,armv7m-systick.txt (renamed from dts/Bindings/arm/armv7m_systick.txt)0
-rw-r--r--dts/Bindings/timer/arm,global_timer.txt (renamed from dts/Bindings/arm/global_timer.txt)0
-rw-r--r--dts/Bindings/timer/arm,twd.txt (renamed from dts/Bindings/arm/twd.txt)0
-rw-r--r--dts/Bindings/timer/fsl,gtm.txt (renamed from dts/Bindings/powerpc/fsl/gtm.txt)0
-rw-r--r--dts/Bindings/timer/mrvl,mmp-timer.txt (renamed from dts/Bindings/arm/mrvl/timer.txt)0
-rw-r--r--dts/Bindings/timer/qcom,msm-timer.txt (renamed from dts/Bindings/arm/msm/timer.txt)0
-rw-r--r--dts/Bindings/timer/renesas,cmt.txt14
-rw-r--r--dts/Bindings/timer/st,spear-timer.txt (renamed from dts/Bindings/arm/spear-timer.txt)0
-rw-r--r--dts/Bindings/timer/ti,c64x+timer64.txt (renamed from dts/Bindings/c6x/timer64.txt)0
-rw-r--r--dts/Bindings/timer/ti,timer.txt (renamed from dts/Bindings/arm/omap/timer.txt)0
-rw-r--r--dts/Bindings/timer/via,vt8500-timer.txt (renamed from dts/Bindings/arm/vt8500/via,vt8500-timer.txt)0
-rw-r--r--dts/Bindings/usb/ci-hdrc-usb2.txt6
-rw-r--r--dts/Bindings/usb/dwc3.txt21
-rw-r--r--dts/Bindings/usb/fcs,fusb302.txt6
-rw-r--r--dts/Bindings/usb/hisilicon,histb-xhci.txt45
-rw-r--r--dts/Bindings/usb/qcom,dwc3.txt85
-rw-r--r--dts/Bindings/usb/richtek,rt1711h.txt17
-rw-r--r--dts/Bindings/usb/rockchip,dwc3.txt2
-rw-r--r--dts/Bindings/vendor-prefixes.txt10
-rw-r--r--dts/Bindings/watchdog/ingenic,jz4740-wdt.txt7
-rw-r--r--dts/Bindings/watchdog/renesas-wdt.txt23
-rw-r--r--dts/include/dt-bindings/clock/actions,s900-cmu.h129
-rw-r--r--dts/include/dt-bindings/clock/aspeed-clock.h4
-rw-r--r--dts/include/dt-bindings/clock/axg-aoclkc.h26
-rw-r--r--dts/include/dt-bindings/clock/bcm-sr.h24
-rw-r--r--dts/include/dt-bindings/clock/gxbb-clkc.h2
-rw-r--r--dts/include/dt-bindings/clock/histb-clock.h8
-rw-r--r--dts/include/dt-bindings/clock/imx6qdl-clock.h4
-rw-r--r--dts/include/dt-bindings/clock/imx6sx-clock.h6
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-rw-r--r--dts/src/arm64/synaptics/berlin4ct-stb.dts29
-rw-r--r--dts/src/arm64/synaptics/berlin4ct.dtsi (renamed from dts/src/arm64/marvell/berlin4ct.dtsi)39
-rw-r--r--dts/src/mips/ingenic/ci20.dts34
-rw-r--r--dts/src/mips/ingenic/jz4740.dtsi8
-rw-r--r--dts/src/mips/ingenic/jz4780.dtsi57
-rw-r--r--dts/src/mips/mscc/ocelot.dtsi88
-rw-r--r--dts/src/mips/mscc/ocelot_pcb123.dts20
-rw-r--r--dts/src/powerpc/c2k.dts366
-rw-r--r--dts/src/powerpc/fsl/t104xqds.dtsi2
-rw-r--r--dts/src/powerpc/sbc8349.dts331
844 files changed, 31399 insertions, 11575 deletions
diff --git a/drivers/clk/imx/clk-imx7.c b/drivers/clk/imx/clk-imx7.c
index 1025c9d..97fe7ab 100644
--- a/drivers/clk/imx/clk-imx7.c
+++ b/drivers/clk/imx/clk-imx7.c
@@ -739,15 +739,14 @@ static int imx7_ccm_probe(struct device_d *dev)
clks[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_gate4("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0);
clks[IMX7D_LCDIF_PIXEL_ROOT_CLK] = imx_clk_gate4("lcdif_pixel_root_clk", "lcdif_pixel_post_div", base + 0x44b0, 0);
- /*
- * Linux code controls gates at 0x44e0, 0x44f0, 0x4500 and 0x4500. However, these do not seem to
- * exist in hardware. According to the reference manual the ethernet clocks are controlled by
- * gates at 0x4700 and 0x4710
- */
- clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate4("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x4700, 0);
- clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate_shared("enet1_time_root_clk", "enet1_time_post_div", "enet1_ref_root_clk");
- clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate4("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4710, 0);
- clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate_shared("enet2_time_root_clk", "enet2_time_post_div", "enet2_ref_root_clk");
+ clks[IMX7D_ENET1_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet1_ipg_root_clk",
+ "enet_axi_post_div", base + 0x4700, 0);
+ clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet1_time_root_clk",
+ "enet1_time_post_div", base + 0x4700, 0);
+ clks[IMX7D_ENET2_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet2_ipg_root_clk",
+ "enet_axi_post_div", base + 0x4710, 0);
+ clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet2_time_root_clk",
+ "enet2_time_post_div", base + 0x4710, 0);
clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0);
clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0);
diff --git a/dts/Bindings/arm/amlogic.txt b/dts/Bindings/arm/amlogic.txt
index f747f47..6988056 100644
--- a/dts/Bindings/arm/amlogic.txt
+++ b/dts/Bindings/arm/amlogic.txt
@@ -25,6 +25,10 @@ Boards with the Amlogic Meson8b SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson8b";
+Boards with the Amlogic Meson8m2 SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,meson8m2";
+
Boards with the Amlogic Meson GXBaby SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson-gxbb";
@@ -54,6 +58,8 @@ Board compatible values (alphabetically, grouped by SoC):
- "hardkernel,odroid-c1" (Meson8b)
- "tronfy,mxq" (Meson8b)
+ - "tronsmart,mxiii-plus" (Meson8m2)
+
- "amlogic,p200" (Meson gxbb)
- "amlogic,p201" (Meson gxbb)
- "friendlyarm,nanopi-k2" (Meson gxbb)
diff --git a/dts/Bindings/arm/bcm/brcm,bcm2835.txt b/dts/Bindings/arm/bcm/brcm,bcm2835.txt
index 3e3efa0..1e3e29a 100644
--- a/dts/Bindings/arm/bcm/brcm,bcm2835.txt
+++ b/dts/Bindings/arm/bcm/brcm,bcm2835.txt
@@ -34,6 +34,10 @@ Raspberry Pi 3 Model B
Required root node properties:
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
+Raspberry Pi 3 Model B+
+Required root node properties:
+compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837";
+
Raspberry Pi Compute Module
Required root node properties:
compatible = "raspberrypi,compute-module", "brcm,bcm2835";
diff --git a/dts/Bindings/arm/mediatek/mediatek,g3dsys.txt b/dts/Bindings/arm/mediatek/mediatek,g3dsys.txt
new file mode 100644
index 0000000..7de43bf
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,g3dsys.txt
@@ -0,0 +1,30 @@
+MediaTek g3dsys controller
+============================
+
+The MediaTek g3dsys controller provides various clocks and reset controller to
+the GPU.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt2701-g3dsys", "syscon":
+ for MT2701 SoC
+ - "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon":
+ for MT7623 SoC
+- #clock-cells: Must be 1
+- #reset-cells: Must be 1
+
+The g3dsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+g3dsys: clock-controller@13000000 {
+ compatible = "mediatek,mt7623-g3dsys",
+ "mediatek,mt2701-g3dsys",
+ "syscon";
+ reg = <0 0x13000000 0 0x200>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
diff --git a/dts/Bindings/arm/samsung/samsung-boards.txt b/dts/Bindings/arm/samsung/samsung-boards.txt
index 14510b2..bdadc3d 100644
--- a/dts/Bindings/arm/samsung/samsung-boards.txt
+++ b/dts/Bindings/arm/samsung/samsung-boards.txt
@@ -21,8 +21,6 @@ Required root node properties:
- "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
- "samsung,tm2" - for Exynos5433-based Samsung TM2 board.
- "samsung,tm2e" - for Exynos5433-based Samsung TM2E board.
- - "samsung,sd5v1" - for Exynos5440-based Samsung board.
- - "samsung,ssdk5440" - for Exynos5440-based Samsung board.
* Other companies Exynos SoC based
* FriendlyARM
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
index d3d1df9..d8cf740 100644
--- a/dts/Bindings/arm/shmobile.txt
+++ b/dts/Bindings/arm/shmobile.txt
@@ -21,6 +21,8 @@ SoCs:
compatible = "renesas,r8a7744"
- RZ/G1E (R8A77450)
compatible = "renesas,r8a7745"
+ - RZ/G1C (R8A77470)
+ compatible = "renesas,r8a77470"
- R-Car M1A (R8A77781)
compatible = "renesas,r8a7778"
- R-Car H1 (R8A77790)
@@ -45,6 +47,8 @@ SoCs:
compatible = "renesas,r8a77970"
- R-Car V3H (R8A77980)
compatible = "renesas,r8a77980"
+ - R-Car E3 (R8A77990)
+ compatible = "renesas,r8a77990"
- R-Car D3 (R8A77995)
compatible = "renesas,r8a77995"
@@ -67,6 +71,8 @@ Boards:
compatible = "renesas,draak", "renesas,r8a77995"
- Eagle (RTP0RC77970SEB0010S)
compatible = "renesas,eagle", "renesas,r8a77970"
+ - Ebisu (RTP0RC77990SEB0010S)
+ compatible = "renesas,ebisu", "renesas,r8a77990"
- Genmai (RTK772100BC00000BR)
compatible = "renesas,genmai", "renesas,r7s72100"
- GR-Peach (X28A-M01-E/F)
@@ -78,6 +84,8 @@ Boards:
compatible = "renesas,h3ulcb", "renesas,r8a7795"
- Henninger
compatible = "renesas,henninger", "renesas,r8a7791"
+ - iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S)
+ compatible = "iwave,g23s", "renesas,r8a77470"
- iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
- iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
@@ -108,7 +116,7 @@ Boards:
compatible = "renesas,salvator-x", "renesas,r8a7795"
- Salvator-X (RTP0RC7796SIPB0011S)
compatible = "renesas,salvator-x", "renesas,r8a7796"
- - Salvator-X (RTP0RC7796SIPB0011S (M3N))
+ - Salvator-X (RTP0RC7796SIPB0011S (M3-N))
compatible = "renesas,salvator-x", "renesas,r8a77965"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
compatible = "renesas,salvator-xs", "renesas,r8a7795"
@@ -124,6 +132,8 @@ Boards:
compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
- Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
compatible = "renesas,stout", "renesas,r8a7790"
+ - V3HSK (Y-ASK-RCAR-V3H-WS10)
+ compatible = "renesas,v3hsk", "renesas,r8a77980"
- V3MSK (Y-ASK-RCAR-V3M-WS10)
compatible = "renesas,v3msk", "renesas,r8a77970"
- Wheat (RTP0RC7792ASKB0000JE)
diff --git a/dts/Bindings/arm/stm32/stm32-syscon.txt b/dts/Bindings/arm/stm32/stm32-syscon.txt
new file mode 100644
index 0000000..99980ae
--- /dev/null
+++ b/dts/Bindings/arm/stm32/stm32-syscon.txt
@@ -0,0 +1,14 @@
+STMicroelectronics STM32 Platforms System Controller
+
+Properties:
+ - compatible : should contain two values. First value must be :
+ - " st,stm32mp157-syscfg " - for stm32mp157 based SoCs,
+ second value must be always "syscon".
+ - reg : offset and length of the register set.
+
+ Example:
+ syscfg: syscon@50020000 {
+ compatible = "st,stm32mp157-syscfg", "syscon";
+ reg = <0x50020000 0x400>;
+ };
+
diff --git a/dts/Bindings/arm/stm32.txt b/dts/Bindings/arm/stm32/stm32.txt
index 6808ed9..6808ed9 100644
--- a/dts/Bindings/arm/stm32.txt
+++ b/dts/Bindings/arm/stm32/stm32.txt
diff --git a/dts/Bindings/arm/tegra/nvidia,tegra30-mc.txt b/dts/Bindings/arm/tegra/nvidia,tegra30-mc.txt
deleted file mode 100644
index bdf1a61..0000000
--- a/dts/Bindings/arm/tegra/nvidia,tegra30-mc.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-NVIDIA Tegra30 MC(Memory Controller)
-
-Required properties:
-- compatible : "nvidia,tegra30-mc"
-- reg : Should contain 4 register ranges(address and length); see the
- example below. Note that the MC registers are interleaved with the
- SMMU registers, and hence must be represented as multiple ranges.
-- interrupts : Should contain MC General interrupt.
-
-Example:
- memory-controller {
- compatible = "nvidia,tegra30-mc";
- reg = <0x7000f000 0x010
- 0x7000f03c 0x1b4
- 0x7000f200 0x028
- 0x7000f284 0x17c>;
- interrupts = <0 77 0x04>;
- };
diff --git a/dts/Bindings/arm/ux500/boards.txt b/dts/Bindings/arm/ux500/boards.txt
index 7334c24..0fa4295 100644
--- a/dts/Bindings/arm/ux500/boards.txt
+++ b/dts/Bindings/arm/ux500/boards.txt
@@ -26,7 +26,7 @@ interrupt-controller:
see binding for interrupt-controller/arm,gic.txt
timer:
- see binding for arm/twd.txt
+ see binding for timer/arm,twd.txt
clocks:
see binding for clocks/ux500.txt
diff --git a/dts/Bindings/bus/ti-sysc.txt b/dts/Bindings/bus/ti-sysc.txt
index 2957a9a..d8ed5b7 100644
--- a/dts/Bindings/bus/ti-sysc.txt
+++ b/dts/Bindings/bus/ti-sysc.txt
@@ -79,7 +79,11 @@ Optional properties:
mode as for example omap4 L4_CFG_CLKCTRL
- clock-names should contain at least "fck", and optionally also "ick"
- depending on the SoC and the interconnect target module
+ depending on the SoC and the interconnect target module,
+ some interconnect target modules also need additional
+ optional clocks that can be specified as listed in TRM
+ for the related CLKCTRL register bits 8 to 15 such as
+ "dbclk" or "clk32k" depending on their role
- ti,hwmods optional TI interconnect module name to use legacy
hwmod platform data
diff --git a/dts/Bindings/clock/actions,s900-cmu.txt b/dts/Bindings/clock/actions,s900-cmu.txt
new file mode 100644
index 0000000..93e4fb8
--- /dev/null
+++ b/dts/Bindings/clock/actions,s900-cmu.txt
@@ -0,0 +1,47 @@
+* Actions S900 Clock Management Unit (CMU)
+
+The Actions S900 clock management unit generates and supplies clock to various
+controllers within the SoC. The clock binding described here is applicable to
+S900 SoC.
+
+Required Properties:
+
+- compatible: should be "actions,s900-cmu"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- clocks: Reference to the parent clocks ("hosc", "losc")
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier, and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/actions,s900-cmu.h header and can be used in device
+tree sources.
+
+External clocks:
+
+The hosc clock used as input for the plls is generated outside the SoC. It is
+expected that it is defined using standard clock bindings as "hosc".
+
+Actions S900 CMU also requires one more clock:
+ - "losc" - internal low frequency oscillator
+
+Example: Clock Management Unit node:
+
+ cmu: clock-controller@e0160000 {
+ compatible = "actions,s900-cmu";
+ reg = <0x0 0xe0160000 0x0 0x1000>;
+ clocks = <&hosc>, <&losc>;
+ #clock-cells = <1>;
+ };
+
+Example: UART controller node that consumes clock generated by the clock
+management unit:
+
+ uart: serial@e012a000 {
+ compatible = "actions,s900-uart", "actions,owl-uart";
+ reg = <0x0 0xe012a000 0x0 0x2000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART5>;
+ };
diff --git a/dts/Bindings/clock/amlogic,gxbb-aoclkc.txt b/dts/Bindings/clock/amlogic,gxbb-aoclkc.txt
index 786dc39..3a88052 100644
--- a/dts/Bindings/clock/amlogic,gxbb-aoclkc.txt
+++ b/dts/Bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -9,6 +9,7 @@ Required Properties:
- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
- GXM (S912) : "amlogic,meson-gxm-aoclkc"
+ - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
followed by the common "amlogic,meson-gx-aoclkc"
- #clock-cells: should be 1.
diff --git a/dts/Bindings/clock/amlogic,gxbb-clkc.txt b/dts/Bindings/clock/amlogic,gxbb-clkc.txt
index e2b377e..e950599 100644
--- a/dts/Bindings/clock/amlogic,gxbb-clkc.txt
+++ b/dts/Bindings/clock/amlogic,gxbb-clkc.txt
@@ -10,9 +10,6 @@ Required Properties:
"amlogic,gxl-clkc" for GXL and GXM SoC,
"amlogic,axg-clkc" for AXG SoC.
-- reg: physical base address of the clock controller and length of memory
- mapped region.
-
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
@@ -20,13 +17,22 @@ to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
used in device tree sources.
+Parent node should have the following properties :
+- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or
+ "amlogic,meson-axg-hhi-sysctrl"
+- reg: base address and size of the HHI system control register space.
+
Example: Clock controller node:
- clkc: clock-controller@c883c000 {
+sysctrl: system-controller@0 {
+ compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
+ reg = <0 0 0 0x400>;
+
+ clkc: clock-controller {
#clock-cells = <1>;
compatible = "amlogic,gxbb-clkc";
- reg = <0x0 0xc883c000 0x0 0x3db>;
};
+};
Example: UART controller node that consumes the clock generated by the clock
controller:
diff --git a/dts/Bindings/clock/brcm,iproc-clocks.txt b/dts/Bindings/clock/brcm,iproc-clocks.txt
index f8e4a93..ab730ea 100644
--- a/dts/Bindings/clock/brcm,iproc-clocks.txt
+++ b/dts/Bindings/clock/brcm,iproc-clocks.txt
@@ -276,36 +276,38 @@ These clock IDs are defined in:
clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
- clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH
+ clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK
+ clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK
genpll3 crystal 0 BCM_SR_GENPLL3
clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
genpll4 crystal 0 BCM_SR_GENPLL4
- ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
+ clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
- noc_clk genpll4 3 BCM_SR_GENPLL4_NOC_CLK
+ clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK
clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
-
genpll5 crystal 0 BCM_SR_GENPLL5
- fs4_hf_clk genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
- crypto_ae_clk genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
- raid_ae_clk genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
+ clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
+ clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
+ clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
genpll6 crystal 0 BCM_SR_GENPLL6
- 48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
+ clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
lcpll0 crystal 0 BCM_SR_LCPLL0
clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
- clk_usb_ref lcpll0 3 BCM_SR_LCPLL0_USB_REF_CLK
- sata_refpn lcpll0 3 BCM_SR_LCPLL0_SATA_REFPN_CLK
+ clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK
+ clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK
lcpll1 crystal 0 BCM_SR_LCPLL1
- wan lcpll1 1 BCM_SR_LCPLL0_WAN_CLK
+ clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK
+ clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK
+ clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK
lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
- pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
+ clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
diff --git a/dts/Bindings/clock/nuvoton,npcm750-clk.txt b/dts/Bindings/clock/nuvoton,npcm750-clk.txt
new file mode 100644
index 0000000..f820645
--- /dev/null
+++ b/dts/Bindings/clock/nuvoton,npcm750-clk.txt
@@ -0,0 +1,100 @@
+* Nuvoton NPCM7XX Clock Controller
+
+Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
+generates and supplies clocks to all modules within the BMC.
+
+External clocks:
+
+There are six fixed clocks that are generated outside the BMC. All clocks are of
+a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
+clk_sysbypck are inputs to the clock controller.
+clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
+network. They are set on the device tree, but not used by the clock module. The
+network devices use them directly.
+Example can be found below.
+
+All available clocks are defined as preprocessor macros in:
+dt-bindings/clock/nuvoton,npcm7xx-clock.h
+and can be reused as DT sources.
+
+Required Properties of clock controller:
+
+ - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
+ Poleg BMC NPCM750
+
+ - reg: physical base address of the clock controller and length of
+ memory mapped region.
+
+ - #clock-cells: should be 1.
+
+Example: Clock controller node:
+
+ clk: clock-controller@f0801000 {
+ compatible = "nuvoton,npcm750-clk";
+ #clock-cells = <1>;
+ reg = <0xf0801000 0x1000>;
+ clock-names = "refclk", "sysbypck", "mcbypck";
+ clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
+ };
+
+Example: Required external clocks for network:
+
+ /* external reference clock */
+ clk_refclk: clk-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "refclk";
+ };
+
+ /* external reference clock for cpu. float in normal operation */
+ clk_sysbypck: clk-sysbypck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "sysbypck";
+ };
+
+ /* external reference clock for MC. float in normal operation */
+ clk_mcbypck: clk-mcbypck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "mcbypck";
+ };
+
+ /* external clock signal rg1refck, supplied by the phy */
+ clk_rg1refck: clk-rg1refck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "clk_rg1refck";
+ };
+
+ /* external clock signal rg2refck, supplied by the phy */
+ clk_rg2refck: clk-rg2refck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "clk_rg2refck";
+ };
+
+ clk_xin: clk-xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "clk_xin";
+ };
+
+
+Example: GMAC controller node that consumes two clocks: a generated clk by the
+clock controller and a fixed clock from DT (clk_rg1refck).
+
+ ethernet0: ethernet@f0802000 {
+ compatible = "snps,dwmac";
+ reg = <0xf0802000 0x2000>;
+ interrupts = <0 14 4>;
+ interrupt-names = "macirq";
+ clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
+ clock-names = "stmmaceth", "clk_gmac";
+ };
diff --git a/dts/Bindings/clock/qcom,gcc.txt b/dts/Bindings/clock/qcom,gcc.txt
index 551d03b..664ea1f 100644
--- a/dts/Bindings/clock/qcom,gcc.txt
+++ b/dts/Bindings/clock/qcom,gcc.txt
@@ -17,7 +17,9 @@ Required properties :
"qcom,gcc-msm8974pro-ac"
"qcom,gcc-msm8994"
"qcom,gcc-msm8996"
+ "qcom,gcc-msm8998"
"qcom,gcc-mdm9615"
+ "qcom,gcc-sdm845"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1
diff --git a/dts/Bindings/clock/qcom,rpmh-clk.txt b/dts/Bindings/clock/qcom,rpmh-clk.txt
new file mode 100644
index 0000000..3c00765
--- /dev/null
+++ b/dts/Bindings/clock/qcom,rpmh-clk.txt
@@ -0,0 +1,22 @@
+Qualcomm Technologies, Inc. RPMh Clocks
+-------------------------------------------------------
+
+Resource Power Manager Hardened (RPMh) manages shared resources on
+some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
+other hardware subsystems via RSC to control clocks.
+
+Required properties :
+- compatible : shall contain "qcom,sdm845-rpmh-clk"
+
+- #clock-cells : must contain 1
+
+Example :
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+
+ &apps_rsc {
+ rpmhcc: clock-controller {
+ compatible = "qcom,sdm845-rpmh-clk";
+ #clock-cells = <1>;
+ };
+ };
diff --git a/dts/Bindings/clock/qcom,videocc.txt b/dts/Bindings/clock/qcom,videocc.txt
new file mode 100644
index 0000000..e7c035a
--- /dev/null
+++ b/dts/Bindings/clock/qcom,videocc.txt
@@ -0,0 +1,19 @@
+Qualcomm Video Clock & Reset Controller Binding
+-----------------------------------------------
+
+Required properties :
+- compatible : shall contain "qcom,sdm845-videocc"
+- reg : shall contain base register location and length
+- #clock-cells : from common clock binding, shall contain 1.
+- #power-domain-cells : from generic power domain binding, shall contain 1.
+
+Optional properties :
+- #reset-cells : from common reset binding, shall contain 1.
+
+Example:
+ videocc: clock-controller@ab00000 {
+ compatible = "qcom,sdm845-videocc";
+ reg = <0xab00000 0x10000>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.txt b/dts/Bindings/clock/renesas,cpg-mssr.txt
index 773a522..db542ab 100644
--- a/dts/Bindings/clock/renesas,cpg-mssr.txt
+++ b/dts/Bindings/clock/renesas,cpg-mssr.txt
@@ -15,6 +15,7 @@ Required Properties:
- compatible: Must be one of:
- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
+ - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
- "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
- "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
- "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
@@ -25,6 +26,7 @@ Required Properties:
- "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
- "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
+ - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -33,10 +35,12 @@ Required Properties:
- clocks: References to external parent clocks, one entry for each entry in
clock-names
- clock-names: List of external parent clock names. Valid names are:
- - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
- r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)
+ - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,
+ r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,
+ r8a77980, r8a77990, r8a77995)
- "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
- - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
+ - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
+ r8a7794)
- #clock-cells: Must be 2
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
diff --git a/dts/Bindings/clock/rockchip.txt b/dts/Bindings/clock/rockchip.txt
deleted file mode 100644
index 22f6769..0000000
--- a/dts/Bindings/clock/rockchip.txt
+++ /dev/null
@@ -1,77 +0,0 @@
-Device Tree Clock bindings for arch-rockchip
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-== Gate clocks ==
-
-These bindings are deprecated!
-Please use the soc specific CRU bindings instead.
-
-The gate registers form a continuos block which makes the dt node
-structure a matter of taste, as either all gates can be put into
-one gate clock spanning all registers or they can be divided into
-the 10 individual gates containing 16 clocks each.
-The code supports both approaches.
-
-Required properties:
-- compatible : "rockchip,rk2928-gate-clk"
-- reg : shall be the control register address(es) for the clock.
-- #clock-cells : from common clock binding; shall be set to 1
-- clock-output-names : the corresponding gate names that the clock controls
-- clocks : should contain the parent clock for each individual gate,
- therefore the number of clocks elements should match the number of
- clock-output-names
-
-Example using multiple gate clocks:
-
- clk_gates0: gate-clk@200000d0 {
- compatible = "rockchip,rk2928-gate-clk";
- reg = <0x200000d0 0x4>;
- clocks = <&dummy>, <&dummy>,
- <&dummy>, <&dummy>,
- <&dummy>, <&dummy>,
- <&dummy>, <&dummy>,
- <&dummy>, <&dummy>,
- <&dummy>, <&dummy>,
- <&dummy>, <&dummy>,
- <&dummy>, <&dummy>;
-
- clock-output-names =
- "gate_core_periph", "gate_cpu_gpll",
- "gate_ddrphy", "gate_aclk_cpu",
- "gate_hclk_cpu", "gate_pclk_cpu",
- "gate_atclk_cpu", "gate_i2s0",
- "gate_i2s0_frac", "gate_i2s1",
- "gate_i2s1_frac", "gate_i2s2",
- "gate_i2s2_frac", "gate_spdif",
- "gate_spdif_frac", "gate_testclk";
-
- #clock-cells = <1>;
- };
-
- clk_gates1: gate-clk@200000d4 {
- compatible = "rockchip,rk2928-gate-clk";
- reg = <0x200000d4 0x4>;
- clocks = <&xin24m>, <&xin24m>,
- <&xin24m>, <&dummy>,
- <&dummy>, <&xin24m>,
- <&xin24m>, <&dummy>,
- <&xin24m>, <&dummy>,
- <&xin24m>, <&dummy>,
- <&xin24m>, <&dummy>,
- <&xin24m>, <&dummy>;
-
- clock-output-names =
- "gate_timer0", "gate_timer1",
- "gate_timer2", "gate_jtag",
- "gate_aclk_lcdc1_src", "gate_otgphy0",
- "gate_otgphy1", "gate_ddr_gpll",
- "gate_uart0", "gate_frac_uart0",
- "gate_uart1", "gate_frac_uart1",
- "gate_uart2", "gate_frac_uart2",
- "gate_uart3", "gate_frac_uart3";
-
- #clock-cells = <1>;
- };
diff --git a/dts/Bindings/clock/st/st,clkgen.txt b/dts/Bindings/clock/st/st,clkgen.txt
index 7364953..45ac19b 100644
--- a/dts/Bindings/clock/st/st,clkgen.txt
+++ b/dts/Bindings/clock/st/st,clkgen.txt
@@ -31,10 +31,10 @@ This binding uses the common clock binding[1].
Each subnode should use the binding described in [2]..[7]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
-[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
-[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
-[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
+[3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
+[4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+[7] Documentation/devicetree/bindings/clock/st/st,quadfs.txt
+[8] Documentation/devicetree/bindings/clock/st/st,flexgen.txt
Required properties:
diff --git a/dts/Bindings/clock/sunxi-ccu.txt b/dts/Bindings/clock/sunxi-ccu.txt
index 460ef27..47d2e90 100644
--- a/dts/Bindings/clock/sunxi-ccu.txt
+++ b/dts/Bindings/clock/sunxi-ccu.txt
@@ -21,6 +21,7 @@ Required properties :
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
- "allwinner,sun50i-h6-ccu"
+ - "allwinner,sun50i-h6-r-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
@@ -35,7 +36,7 @@ Required properties :
For the main CCU on H6, one more clock is needed:
- "iosc": the SoC's internal frequency oscillator
-For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
+For the PRCM CCUs on A83T/H3/A64/H6, two more clocks are needed:
- "pll-periph": the SoC's peripheral PLL from the main CCU
- "iosc": the SoC's internal frequency oscillator
diff --git a/dts/Bindings/clock/ti/gate.txt b/dts/Bindings/clock/ti/gate.txt
index 03f8fde..56d603c 100644
--- a/dts/Bindings/clock/ti/gate.txt
+++ b/dts/Bindings/clock/ti/gate.txt
@@ -10,7 +10,7 @@ will be controlled instead and the corresponding hw-ops for
that is used.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
Required properties:
diff --git a/dts/Bindings/clock/ti/interface.txt b/dts/Bindings/clock/ti/interface.txt
index 3111a40..3f47040 100644
--- a/dts/Bindings/clock/ti/interface.txt
+++ b/dts/Bindings/clock/ti/interface.txt
@@ -9,7 +9,7 @@ companion clock finding (match corresponding functional gate
clock) and hardware autoidle enable / disable.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
Required properties:
- compatible : shall be one of:
diff --git a/dts/Bindings/cpufreq/cpufreq-mediatek.txt b/dts/Bindings/cpufreq/cpufreq-mediatek.txt
index d36f07e..0551c78 100644
--- a/dts/Bindings/cpufreq/cpufreq-mediatek.txt
+++ b/dts/Bindings/cpufreq/cpufreq-mediatek.txt
@@ -8,7 +8,7 @@ Required properties:
"intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
source (usually MAINPLL) when the original CPU PLL is under
transition and not stable yet.
- Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
+ Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
generic clock consumer properties.
- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
for detail.
diff --git a/dts/Bindings/devfreq/rk3399_dmc.txt b/dts/Bindings/devfreq/rk3399_dmc.txt
index d6d2833..fc2bcbe 100644
--- a/dts/Bindings/devfreq/rk3399_dmc.txt
+++ b/dts/Bindings/devfreq/rk3399_dmc.txt
@@ -12,7 +12,7 @@ Required properties:
- clocks: Phandles for clock specified in "clock-names" property
- clock-names : The name of clock used by the DFI, must be
"pclk_ddr_mon";
-- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt
+- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt
for details.
- center-supply: DMC supply node.
- status: Marks the node enabled/disabled.
diff --git a/dts/Bindings/display/bridge/adi,adv7511.txt b/dts/Bindings/display/bridge/adi,adv7511.txt
index 0047b13..2c88753 100644
--- a/dts/Bindings/display/bridge/adi,adv7511.txt
+++ b/dts/Bindings/display/bridge/adi,adv7511.txt
@@ -14,7 +14,13 @@ Required properties:
"adi,adv7513"
"adi,adv7533"
-- reg: I2C slave address
+- reg: I2C slave addresses
+ The ADV7511 internal registers are split into four pages exposed through
+ different I2C addresses, creating four register maps. Each map has it own
+ I2C address and acts as a standard slave device on the I2C bus. The main
+ address is mandatory, others are optional and revert to defaults if not
+ specified.
+
The ADV7511 supports a large number of input data formats that differ by their
color depth, color format, clock mode, bit justification and random
@@ -70,6 +76,9 @@ Optional properties:
rather than generate its own timings for HDMI output.
- clocks: from common clock binding: reference to the CEC clock.
- clock-names: from common clock binding: must be "cec".
+- reg-names : Names of maps with programmable addresses.
+ It can contain any map needing a non-default address.
+ Possible maps names are : "main", "edid", "cec", "packet"
Required nodes:
@@ -88,7 +97,12 @@ Example
adv7511w: hdmi@39 {
compatible = "adi,adv7511w";
- reg = <39>;
+ /*
+ * The EDID page will be accessible on address 0x66 on the I2C
+ * bus. All other maps continue to use their default addresses.
+ */
+ reg = <0x39>, <0x66>;
+ reg-names = "main", "edid";
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
clocks = <&cec_clock>;
diff --git a/dts/Bindings/display/bridge/cdns,dsi.txt b/dts/Bindings/display/bridge/cdns,dsi.txt
new file mode 100644
index 0000000..f5725bb
--- /dev/null
+++ b/dts/Bindings/display/bridge/cdns,dsi.txt
@@ -0,0 +1,133 @@
+Cadence DSI bridge
+==================
+
+The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
+
+Required properties:
+- compatible: should be set to "cdns,dsi".
+- reg: physical base address and length of the controller's registers.
+- interrupts: interrupt line connected to the DSI bridge.
+- clocks: DSI bridge clocks.
+- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
+- phys: phandle link to the MIPI D-PHY controller.
+- phy-names: must contain "dphy".
+- #address-cells: must be set to 1.
+- #size-cells: must be set to 0.
+
+Optional properties:
+- resets: DSI reset lines.
+- reset-names: can contain "dsi_p_rst".
+
+Required subnodes:
+- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
+ 2 ports are available:
+ * port 0: this port is only needed if some of your DSI devices are
+ controlled through an external bus like I2C or SPI. Can have at
+ most 4 endpoints. The endpoint number is directly encoding the
+ DSI virtual channel used by this device.
+ * port 1: represents the DPI input.
+ Other ports will be added later to support the new kind of inputs.
+
+- one subnode per DSI device connected on the DSI bus. Each DSI device should
+ contain a reg property encoding its virtual channel.
+
+Cadence DPHY
+============
+
+Cadence DPHY block.
+
+Required properties:
+- compatible: should be set to "cdns,dphy".
+- reg: physical base address and length of the DPHY registers.
+- clocks: DPHY reference clocks.
+- clock-names: must contain "psm" and "pll_ref".
+- #phy-cells: must be set to 0.
+
+
+Example:
+ dphy0: dphy@fd0e0000{
+ compatible = "cdns,dphy";
+ reg = <0x0 0xfd0e0000 0x0 0x1000>;
+ clocks = <&psm_clk>, <&pll_ref_clk>;
+ clock-names = "psm", "pll_ref";
+ #phy-cells = <0>;
+ };
+
+ dsi0: dsi@fd0c0000 {
+ compatible = "cdns,dsi";
+ reg = <0x0 0xfd0c0000 0x0 0x1000>;
+ clocks = <&pclk>, <&sysclk>;
+ clock-names = "dsi_p_clk", "dsi_sys_clk";
+ interrupts = <1>;
+ phys = <&dphy0>;
+ phy-names = "dphy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ dsi0_dpi_input: endpoint {
+ remote-endpoint = <&xxx_dpi_output>;
+ };
+ };
+ };
+
+ panel: dsi-dev@0 {
+ compatible = "<vendor,panel>";
+ reg = <0>;
+ };
+ };
+
+or
+
+ dsi0: dsi@fd0c0000 {
+ compatible = "cdns,dsi";
+ reg = <0x0 0xfd0c0000 0x0 0x1000>;
+ clocks = <&pclk>, <&sysclk>;
+ clock-names = "dsi_p_clk", "dsi_sys_clk";
+ interrupts = <1>;
+ phys = <&dphy1>;
+ phy-names = "dphy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi0_output: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_panel_input>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_dpi_input: endpoint {
+ remote-endpoint = <&xxx_dpi_output>;
+ };
+ };
+ };
+ };
+
+ i2c@xxx {
+ panel: panel@59 {
+ compatible = "<vendor,panel>";
+ reg = <0x59>;
+
+ port {
+ dsi_panel_input: endpoint {
+ remote-endpoint = <&dsi0_output>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/bridge/renesas,dw-hdmi.txt b/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
index 3a72a10..a41d280 100644
--- a/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
+++ b/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
@@ -14,6 +14,7 @@ Required properties:
- compatible : Shall contain one or more of
- "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
- "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
+ - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
- "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX
When compatible with generic versions, nodes must list the SoC-specific
diff --git a/dts/Bindings/display/bridge/tda998x.txt b/dts/Bindings/display/bridge/tda998x.txt
index 24cc246..f5a02f6 100644
--- a/dts/Bindings/display/bridge/tda998x.txt
+++ b/dts/Bindings/display/bridge/tda998x.txt
@@ -27,7 +27,10 @@ Optional properties:
in question is used. The implementation allows one or two DAIs. If two
DAIs are defined, they must be of different type.
-[1] Documentation/sound/alsa/soc/DAI.txt
+ - nxp,calib-gpios: calibration GPIO, which must correspond with the
+ gpio used for the TDA998x interrupt pin.
+
+[1] Documentation/sound/soc/dai.rst
[2] include/dt-bindings/display/tda998x.h
Example:
diff --git a/dts/Bindings/display/bridge/thine,thc63lvd1024.txt b/dts/Bindings/display/bridge/thine,thc63lvd1024.txt
new file mode 100644
index 0000000..37f0c04
--- /dev/null
+++ b/dts/Bindings/display/bridge/thine,thc63lvd1024.txt
@@ -0,0 +1,60 @@
+Thine Electronics THC63LVD1024 LVDS decoder
+-------------------------------------------
+
+The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS streams
+to parallel data outputs. The chip supports single/dual input/output modes,
+handling up to two LVDS input streams and up to two digital CMOS/TTL outputs.
+
+Single or dual operation mode, output data mapping and DDR output modes are
+configured through input signals and the chip does not expose any control bus.
+
+Required properties:
+- compatible: Shall be "thine,thc63lvd1024"
+- vcc-supply: Power supply for TTL output, TTL CLOCKOUT signal, LVDS input,
+ PPL and digital circuitry
+
+Optional properties:
+- powerdown-gpios: Power down GPIO signal, pin name "/PDWN". Active low
+- oe-gpios: Output enable GPIO signal, pin name "OE". Active high
+
+The THC63LVD1024 video port connections are modeled according
+to OF graph bindings specified by Documentation/devicetree/bindings/graph.txt
+
+Required video port nodes:
+- port@0: First LVDS input port
+- port@2: First digital CMOS/TTL parallel output
+
+Optional video port nodes:
+- port@1: Second LVDS input port
+- port@3: Second digital CMOS/TTL parallel output
+
+Example:
+--------
+
+ thc63lvd1024: lvds-decoder {
+ compatible = "thine,thc63lvd1024";
+
+ vcc-supply = <&reg_lvds_vcc>;
+ powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lvds_dec_in_0: endpoint {
+ remote-endpoint = <&lvds_out>;
+ };
+ };
+
+ port@2{
+ reg = <2>;
+
+ lvds_dec_out_2: endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/exynos/exynos5433-decon.txt b/dts/Bindings/display/exynos/exynos5433-decon.txt
index fc25882..775193e 100644
--- a/dts/Bindings/display/exynos/exynos5433-decon.txt
+++ b/dts/Bindings/display/exynos/exynos5433-decon.txt
@@ -19,7 +19,8 @@ Required properties:
clock-names property.
- clock-names: list of clock names sorted in the same order as the clocks
property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
- "aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk",
+ "aclk_xiu_decon0x", "pclk_smmu_decon0x", "aclk_smmu_decon1x",
+ "aclk_xiu_decon1x", "pclk_smmu_decon1x", clk_decon_vclk",
"sclk_decon_eclk"
- ports: contains a port which is connected to mic node. address-cells and
size-cells must 1 and 0, respectively.
@@ -34,10 +35,14 @@ decon: decon@13800000 {
clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
<&cmu_disp CLK_ACLK_XIU_DECON0X>,
<&cmu_disp CLK_PCLK_SMMU_DECON0X>,
+ <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
+ <&cmu_disp CLK_ACLK_XIU_DECON1X>,
+ <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
<&cmu_disp CLK_SCLK_DECON_VCLK>,
<&cmu_disp CLK_SCLK_DECON_ECLK>;
clock-names = "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x",
- "pclk_smmu_decon0x", "sclk_decon_vclk", "sclk_decon_eclk";
+ "pclk_smmu_decon0x", "aclk_smmu_decon1x", "aclk_xiu_decon1x",
+ "pclk_smmu_decon1x", "sclk_decon_vclk", "sclk_decon_eclk";
interrupt-names = "vsync", "lcd_sys";
interrupts = <0 202 0>, <0 203 0>;
diff --git a/dts/Bindings/display/renesas,du.txt b/dts/Bindings/display/renesas,du.txt
index c9cd17f..7c6854b 100644
--- a/dts/Bindings/display/renesas,du.txt
+++ b/dts/Bindings/display/renesas,du.txt
@@ -13,6 +13,7 @@ Required Properties:
- "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
- "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
- "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
+ - "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU
- "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
- "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU
@@ -47,20 +48,21 @@ bindings specified in Documentation/devicetree/bindings/graph.txt.
The following table lists for each supported model the port number
corresponding to each DU output.
- Port0 Port1 Port2 Port3
+ Port0 Port1 Port2 Port3
-----------------------------------------------------------------------------
- R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - -
- R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
- R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
- R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
- R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - -
- R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - -
- R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - -
- R8A7794 (R-Car E2) DPAD 0 DPAD 1 - -
- R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0
- R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
- R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - -
- R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 -
+ R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - -
+ R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
+ R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
+ R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
+ R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - -
+ R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - -
+ R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - -
+ R8A7794 (R-Car E2) DPAD 0 DPAD 1 - -
+ R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0
+ R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
+ R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 -
+ R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - -
+ R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 -
Example: R8A7795 (R-Car H3) ES2.0 DU
diff --git a/dts/Bindings/display/sunxi/sun6i-dsi.txt b/dts/Bindings/display/sunxi/sun6i-dsi.txt
new file mode 100644
index 0000000..6a6cf5d
--- /dev/null
+++ b/dts/Bindings/display/sunxi/sun6i-dsi.txt
@@ -0,0 +1,93 @@
+Allwinner A31 DSI Encoder
+=========================
+
+The DSI pipeline consists of two separate blocks: the DSI controller
+itself, and its associated D-PHY.
+
+DSI Encoder
+-----------
+
+The DSI Encoder generates the DSI signal from the TCON's.
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun6i-a31-mipi-dsi
+ - reg: base address and size of memory-mapped region
+ - interrupts: interrupt associated to this IP
+ - clocks: phandles to the clocks feeding the DSI encoder
+ * bus: the DSI interface clock
+ * mod: the DSI module clock
+ - clock-names: the clock names mentioned above
+ - phys: phandle to the D-PHY
+ - phy-names: must be "dphy"
+ - resets: phandle to the reset controller driving the encoder
+
+ - ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoint, usually coming from the
+ associated TCON.
+
+Any MIPI-DSI device attached to this should be described according to
+the bindings defined in ../mipi-dsi-bus.txt
+
+D-PHY
+-----
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun6i-a31-mipi-dphy
+ - reg: base address and size of memory-mapped region
+ - clocks: phandles to the clocks feeding the DSI encoder
+ * bus: the DSI interface clock
+ * mod: the DSI module clock
+ - clock-names: the clock names mentioned above
+ - resets: phandle to the reset controller driving the encoder
+
+Example:
+
+dsi0: dsi@1ca0000 {
+ compatible = "allwinner,sun6i-a31-mipi-dsi";
+ reg = <0x01ca0000 0x1000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MIPI_DSI>,
+ <&ccu CLK_DSI_SCLK>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_MIPI_DSI>;
+ phys = <&dphy0>;
+ phy-names = "dphy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
+ reg = <0>;
+ power-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* PB07 */
+ reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
+ backlight = <&pwm_bl>;
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ dsi0_in_tcon0: endpoint {
+ remote-endpoint = <&tcon0_out_dsi0>;
+ };
+ };
+ };
+};
+
+dphy0: d-phy@1ca1000 {
+ compatible = "allwinner,sun6i-a31-mipi-dphy";
+ reg = <0x01ca1000 0x1000>;
+ clocks = <&ccu CLK_BUS_MIPI_DSI>,
+ <&ccu CLK_DSI_DPHY>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_MIPI_DSI>;
+ #phy-cells = <0>;
+};
diff --git a/dts/Bindings/dma/k3dma.txt b/dts/Bindings/dma/k3dma.txt
index 23f8d71..4945aea 100644
--- a/dts/Bindings/dma/k3dma.txt
+++ b/dts/Bindings/dma/k3dma.txt
@@ -23,7 +23,6 @@ Controller:
dma-requests = <27>;
interrupts = <0 12 4>;
clocks = <&pclk>;
- status = "disable";
};
Client:
diff --git a/dts/Bindings/dma/renesas,rcar-dmac.txt b/dts/Bindings/dma/renesas,rcar-dmac.txt
index 61315ea..b1ba639 100644
--- a/dts/Bindings/dma/renesas,rcar-dmac.txt
+++ b/dts/Bindings/dma/renesas,rcar-dmac.txt
@@ -29,6 +29,7 @@ Required Properties:
- "renesas,dmac-r8a77965" (R-Car M3-N)
- "renesas,dmac-r8a77970" (R-Car V3M)
- "renesas,dmac-r8a77980" (R-Car V3H)
+ - "renesas,dmac-r8a77995" (R-Car D3)
- reg: base address and length of the registers block for the DMAC
diff --git a/dts/Bindings/dma/renesas,usb-dmac.txt b/dts/Bindings/dma/renesas,usb-dmac.txt
index 9dc935e..482e543 100644
--- a/dts/Bindings/dma/renesas,usb-dmac.txt
+++ b/dts/Bindings/dma/renesas,usb-dmac.txt
@@ -12,6 +12,8 @@ Required Properties:
- "renesas,r8a7795-usb-dmac" (R-Car H3)
- "renesas,r8a7796-usb-dmac" (R-Car M3-W)
- "renesas,r8a77965-usb-dmac" (R-Car M3-N)
+ - "renesas,r8a77990-usb-dmac" (R-Car E3)
+ - "renesas,r8a77995-usb-dmac" (R-Car D3)
- reg: base address and length of the registers block for the DMAC
- interrupts: interrupt specifiers for the DMAC, one for each entry in
interrupt-names.
diff --git a/dts/Bindings/dma/ti-edma.txt b/dts/Bindings/dma/ti-edma.txt
index 66026dc..3f15f66 100644
--- a/dts/Bindings/dma/ti-edma.txt
+++ b/dts/Bindings/dma/ti-edma.txt
@@ -190,7 +190,6 @@ mmc0: mmc@23000000 {
power-domains = <&k2g_pds 0xb>;
clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
clock-names = "fck", "mmchsdb_fck";
- status = "disabled";
};
------------------------------------------------------------------------------
diff --git a/dts/Bindings/arm/altera/socfpga-eccmgr.txt b/dts/Bindings/edac/socfpga-eccmgr.txt
index 4a1714f..5626560 100644
--- a/dts/Bindings/arm/altera/socfpga-eccmgr.txt
+++ b/dts/Bindings/edac/socfpga-eccmgr.txt
@@ -231,3 +231,38 @@ Example:
<48 IRQ_TYPE_LEVEL_HIGH>;
};
};
+
+Stratix10 SoCFPGA ECC Manager
+The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
+in a shared register similar to the Arria10. However, ECC requires
+access to registers that can only be read from Secure Monitor with
+SMC calls. Therefore the device tree is slightly different.
+
+Required Properties:
+- compatible : Should be "altr,socfpga-s10-ecc-manager"
+- interrupts : Should be single bit error interrupt, then double bit error
+ interrupt.
+- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
+- #interrupt-cells : must be set to 2.
+
+Subcomponents:
+
+SDRAM ECC
+Required Properties:
+- compatible : Should be "altr,sdram-edac-s10"
+- interrupts : Should be single bit error interrupt, then double bit error
+ interrupt, in this order.
+
+Example:
+
+ eccmgr {
+ compatible = "altr,socfpga-s10-ecc-manager";
+ interrupts = <0 15 4>, <0 95 4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ sdramedac {
+ compatible = "altr,sdram-edac-s10";
+ interrupts = <16 4>, <48 4>;
+ };
+ };
diff --git a/dts/Bindings/firmware/qcom,scm.txt b/dts/Bindings/firmware/qcom,scm.txt
index 7b40054..fcf6979 100644
--- a/dts/Bindings/firmware/qcom,scm.txt
+++ b/dts/Bindings/firmware/qcom,scm.txt
@@ -11,9 +11,10 @@ Required properties:
* "qcom,scm-msm8660" for MSM8660 platforms
* "qcom,scm-msm8690" for MSM8690 platforms
* "qcom,scm-msm8996" for MSM8996 platforms
+ * "qcom,scm-ipq4019" for IPQ4019 platforms
* "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
- clocks: One to three clocks may be required based on compatible.
- * No clock required for "qcom,scm-msm8996"
+ * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019"
* Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"
* Core, iface, and bus clocks required for "qcom,scm"
- clock-names: Must contain "core" for the core clock, "iface" for the interface
diff --git a/dts/Bindings/fpga/lattice-machxo2-spi.txt b/dts/Bindings/fpga/lattice-machxo2-spi.txt
new file mode 100644
index 0000000..a8c362e
--- /dev/null
+++ b/dts/Bindings/fpga/lattice-machxo2-spi.txt
@@ -0,0 +1,29 @@
+Lattice MachXO2 Slave SPI FPGA Manager
+
+Lattice MachXO2 FPGAs support a method of loading the bitstream over
+'slave SPI' interface.
+
+See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com
+
+Required properties:
+- compatible: should contain "lattice,machxo2-slave-spi"
+- reg: spi chip select of the FPGA
+
+Example for full FPGA configuration:
+
+ fpga-region0 {
+ compatible = "fpga-region";
+ fpga-mgr = <&fpga_mgr_spi>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ };
+
+ spi1: spi@2000 {
+ ...
+
+ fpga_mgr_spi: fpga-mgr@0 {
+ compatible = "lattice,machxo2-slave-spi";
+ spi-max-frequency = <8000000>;
+ reg = <0>;
+ };
+ };
diff --git a/dts/Bindings/fsi/fsi-master-gpio.txt b/dts/Bindings/fsi/fsi-master-gpio.txt
index a767259..1e44245 100644
--- a/dts/Bindings/fsi/fsi-master-gpio.txt
+++ b/dts/Bindings/fsi/fsi-master-gpio.txt
@@ -11,6 +11,10 @@ Optional properties:
- trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
- mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
functions (eg, external FSI masters)
+ - no-gpio-delays; : Don't add extra delays between GPIO
+ accesses. This is useful when the HW
+ GPIO block is running at a low enough
+ frequency.
Examples:
diff --git a/dts/Bindings/gpio/gpio-pca953x.txt b/dts/Bindings/gpio/gpio-pca953x.txt
index d2a9376..88f2286 100644
--- a/dts/Bindings/gpio/gpio-pca953x.txt
+++ b/dts/Bindings/gpio/gpio-pca953x.txt
@@ -31,10 +31,15 @@ Required properties:
ti,tca9554
onnn,pca9654
exar,xra1202
+ - gpio-controller: if used as gpio expander.
+ - #gpio-cells: if used as gpio expander.
+ - interrupt-controller: if to be used as interrupt expander.
+ - #interrupt-cells: if to be used as interrupt expander.
Optional properties:
- reset-gpios: GPIO specification for the RESET input. This is an
active low signal to the PCA953x.
+ - vcc-supply: power supply regulator.
Example:
@@ -47,3 +52,32 @@ Example:
interrupt-parent = <&gpio3>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
};
+
+
+Example with Interrupts:
+
+
+ gpio99: gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* gpio6_161 */
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ vcc-supply = <&vdds_1v8_main>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "hdmi-ct-hpd", "hdmi.ls-oe", "p02", "p03", "vibra", "fault2", "p06", "p07",
+ "en-usb", "en-host1", "en-host2", "chg-int", "p14", "p15", "mic-int", "en-modem",
+ "shdn-hs-amp", "chg-status+red", "green", "blue", "en-esata", "fault1", "p26", "p27";
+ };
+
+ ts3a227@3b {
+ compatible = "ti,ts3a227e";
+ reg = <0x3b>;
+ interrupt-parent = <&gpio99>;
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
+ ti,micbias = <0>; /* 2.1V */
+ };
+
diff --git a/dts/Bindings/gpio/renesas,gpio-rcar.txt b/dts/Bindings/gpio/renesas,gpio-rcar.txt
index 9474138..378f132 100644
--- a/dts/Bindings/gpio/renesas,gpio-rcar.txt
+++ b/dts/Bindings/gpio/renesas,gpio-rcar.txt
@@ -5,6 +5,7 @@ Required Properties:
- compatible: should contain one or more of the following:
- "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
- "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.
+ - "renesas,gpio-r8a77470": for R8A77470 (RZ/G1C) compatible GPIO controller.
- "renesas,gpio-r8a7778": for R8A7778 (R-Car M1) compatible GPIO controller.
- "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
- "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
@@ -14,7 +15,9 @@ Required Properties:
- "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
- "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
- "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller.
+ - "renesas,gpio-r8a77965": for R8A77965 (R-Car M3-N) compatible GPIO controller.
- "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO controller.
+ - "renesas,gpio-r8a77990": for R8A77990 (R-Car E3) compatible GPIO controller.
- "renesas,gpio-r8a77995": for R8A77995 (R-Car D3) compatible GPIO controller.
- "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
- "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller.
diff --git a/dts/Bindings/gpio/snps-dwapb-gpio.txt b/dts/Bindings/gpio/snps-dwapb-gpio.txt
index 4a75da7..3c1118b 100644
--- a/dts/Bindings/gpio/snps-dwapb-gpio.txt
+++ b/dts/Bindings/gpio/snps-dwapb-gpio.txt
@@ -26,8 +26,13 @@ controller.
the second encodes the triger flags encoded as described in
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- interrupt-parent : The parent interrupt controller.
-- interrupts : The interrupt to the parent controller raised when GPIOs
- generate the interrupts.
+- interrupts : The interrupts to the parent controller raised when GPIOs
+ generate the interrupts. If the controller provides one combined interrupt
+ for all GPIOs, specify a single interrupt. If the controller provides one
+ interrupt for each GPIO, provide a list of interrupts that correspond to each
+ of the GPIO pins. When specifying multiple interrupts, if any are unconnected,
+ use the interrupts-extended property to specify the interrupts and set the
+ interrupt controller handle for unused interrupts to 0.
- snps,nr-gpios : The number of pins in the port, a single cell.
- resets : Reset line for the controller.
diff --git a/dts/Bindings/gpu/arm,mali-midgard.txt b/dts/Bindings/gpu/arm,mali-midgard.txt
index 039219d..18a2cde 100644
--- a/dts/Bindings/gpu/arm,mali-midgard.txt
+++ b/dts/Bindings/gpu/arm,mali-midgard.txt
@@ -34,7 +34,7 @@ Optional properties:
- mali-supply : Phandle to regulator for the Mali device. Refer to
Documentation/devicetree/bindings/regulator/regulator.txt for details.
-- operating-points-v2 : Refer to Documentation/devicetree/bindings/power/opp.txt
+- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
for details.
diff --git a/dts/Bindings/gpu/arm,mali-utgard.txt b/dts/Bindings/gpu/arm,mali-utgard.txt
index c1f65d1..63cd911 100644
--- a/dts/Bindings/gpu/arm,mali-utgard.txt
+++ b/dts/Bindings/gpu/arm,mali-utgard.txt
@@ -44,7 +44,7 @@ Optional properties:
- memory-region:
Memory region to allocate from, as defined in
- Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt
+ Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
- mali-supply:
Phandle to regulator for the Mali device, as defined in
diff --git a/dts/Bindings/gpu/brcm,bcm-v3d.txt b/dts/Bindings/gpu/brcm,bcm-v3d.txt
new file mode 100644
index 0000000..c907aa8
--- /dev/null
+++ b/dts/Bindings/gpu/brcm,bcm-v3d.txt
@@ -0,0 +1,28 @@
+Broadcom V3D GPU
+
+Only the Broadcom V3D 3.x and newer GPUs are covered by this binding.
+For V3D 2.x, see brcm,bcm-vc4.txt.
+
+Required properties:
+- compatible: Should be "brcm,7268-v3d" or "brcm,7278-v3d"
+- reg: Physical base addresses and lengths of the register areas
+- reg-names: Names for the register areas. The "hub", "bridge", and "core0"
+ register areas are always required. The "gca" register area
+ is required if the GCA cache controller is present.
+- interrupts: The interrupt numbers. The first interrupt is for the hub,
+ while the following interrupts are for the cores.
+ See bindings/interrupt-controller/interrupts.txt
+
+Optional properties:
+- clocks: The core clock the unit runs on
+
+v3d {
+ compatible = "brcm,7268-v3d";
+ reg = <0xf1204000 0x100>,
+ <0xf1200000 0x4000>,
+ <0xf1208000 0x4000>,
+ <0xf1204100 0x100>;
+ reg-names = "bridge", "hub", "core0", "gca";
+ interrupts = <0 78 4>,
+ <0 77 4>;
+};
diff --git a/dts/Bindings/gpu/samsung-scaler.txt b/dts/Bindings/gpu/samsung-scaler.txt
new file mode 100644
index 0000000..9c3d981
--- /dev/null
+++ b/dts/Bindings/gpu/samsung-scaler.txt
@@ -0,0 +1,27 @@
+* Samsung Exynos Image Scaler
+
+Required properties:
+ - compatible : value should be one of the following:
+ (a) "samsung,exynos5420-scaler" for Scaler IP in Exynos5420
+ (b) "samsung,exynos5433-scaler" for Scaler IP in Exynos5433
+
+ - reg : Physical base address of the IP registers and length of memory
+ mapped region.
+
+ - interrupts : Interrupt specifier for scaler interrupt, according to format
+ specific to interrupt parent.
+
+ - clocks : Clock specifier for scaler clock, according to generic clock
+ bindings. (See Documentation/devicetree/bindings/clock/exynos*.txt)
+
+ - clock-names : Names of clocks. For exynos scaler, it should be "mscl"
+ on 5420 and "pclk", "aclk" and "aclk_xiu" on 5433.
+
+Example:
+ scaler@12800000 {
+ compatible = "samsung,exynos5420-scaler";
+ reg = <0x12800000 0x1294>;
+ interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_MSCL0>;
+ clock-names = "mscl";
+ };
diff --git a/dts/Bindings/hwmon/gpio-fan.txt b/dts/Bindings/hwmon/gpio-fan.txt
index 439a743..2becdcf 100644
--- a/dts/Bindings/hwmon/gpio-fan.txt
+++ b/dts/Bindings/hwmon/gpio-fan.txt
@@ -11,7 +11,7 @@ Optional properties:
must have the RPM values in ascending order.
- alarm-gpios: This pin going active indicates something is wrong with
the fan, and a udev event will be fired.
-- cooling-cells: If used as a cooling device, must be <2>
+- #cooling-cells: If used as a cooling device, must be <2>
Also see: Documentation/devicetree/bindings/thermal/thermal.txt
min and max states are derived from the speed-map of the fan.
diff --git a/dts/Bindings/hwmon/ltc2990.txt b/dts/Bindings/hwmon/ltc2990.txt
new file mode 100644
index 0000000..f92f540
--- /dev/null
+++ b/dts/Bindings/hwmon/ltc2990.txt
@@ -0,0 +1,36 @@
+ltc2990: Linear Technology LTC2990 power monitor
+
+Required properties:
+- compatible: Must be "lltc,ltc2990"
+- reg: I2C slave address
+- lltc,meas-mode:
+ An array of two integers for configuring the chip measurement mode.
+
+ The first integer defines the bits 2..0 in the control register. In all
+ cases the internal temperature and supply voltage are measured. In
+ addition the following input measurements are enabled per mode:
+
+ 0: V1, V2, TR2
+ 1: V1-V2, TR2
+ 2: V1-V2, V3, V4
+ 3: TR1, V3, V4
+ 4: TR1, V3-V4
+ 5: TR1, TR2
+ 6: V1-V2, V3-V4
+ 7: V1, V2, V3, V4
+
+ The second integer defines the bits 4..3 in the control register. This
+ allows a subset of the measurements to be enabled:
+
+ 0: Internal temperature and supply voltage only
+ 1: TR1, V1 or V1-V2 only per mode
+ 2: TR2, V3 or V3-V4 only per mode
+ 3: All measurements per mode
+
+Example:
+
+ltc2990@4c {
+ compatible = "lltc,ltc2990";
+ reg = <0x4c>;
+ lltc,meas-mode = <7 3>; /* V1, V2, V3, V4 */
+};
diff --git a/dts/Bindings/i2c/i2c-davinci.txt b/dts/Bindings/i2c/i2c-davinci.txt
index 64e6e65..b745f37 100644
--- a/dts/Bindings/i2c/i2c-davinci.txt
+++ b/dts/Bindings/i2c/i2c-davinci.txt
@@ -24,7 +24,7 @@ Recommended properties :
- clock-frequency : desired I2C bus clock frequency in Hz.
- ti,has-pfunc: boolean; if defined, it indicates that SoC supports PFUNC
registers. PFUNC registers allow to switch I2C pins to function as
- GPIOs, so they can by toggled manually.
+ GPIOs, so they can be toggled manually.
Example (enbw_cmc board):
i2c@1c22000 {
diff --git a/dts/Bindings/i2c/i2c-rcar.txt b/dts/Bindings/i2c/i2c-rcar.txt
index 4a7811e..7ce8fae 100644
--- a/dts/Bindings/i2c/i2c-rcar.txt
+++ b/dts/Bindings/i2c/i2c-rcar.txt
@@ -15,6 +15,7 @@ Required properties:
"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
"renesas,i2c-r8a77965" if the device is a part of a R8A77965 SoC.
"renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC.
+ "renesas,i2c-r8a77980" if the device is a part of a R8A77980 SoC.
"renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC.
"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
"renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
diff --git a/dts/Bindings/i2c/i2c-s3c2410.txt b/dts/Bindings/i2c/i2c-s3c2410.txt
index 89b3250..66ae46d 100644
--- a/dts/Bindings/i2c/i2c-s3c2410.txt
+++ b/dts/Bindings/i2c/i2c-s3c2410.txt
@@ -8,9 +8,7 @@ Required properties:
(b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c.
(c) "samsung, s3c2440-hdmiphy-i2c", for s3c2440-like i2c used
inside HDMIPHY block found on several samsung SoCs
- (d) "samsung, exynos5440-i2c", for s3c2440-like i2c used
- on EXYNOS5440 which does not need GPIO configuration.
- (e) "samsung, exynos5-sata-phy-i2c", for s3c2440-like i2c used as
+ (d) "samsung, exynos5-sata-phy-i2c", for s3c2440-like i2c used as
a host to SATA PHY controller on an internal bus.
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/dts/Bindings/iio/adc/amlogic,meson-saradc.txt b/dts/Bindings/iio/adc/amlogic,meson-saradc.txt
index 1e6ee3d..d1acd5e 100644
--- a/dts/Bindings/iio/adc/amlogic,meson-saradc.txt
+++ b/dts/Bindings/iio/adc/amlogic,meson-saradc.txt
@@ -7,6 +7,7 @@ Required properties:
- "amlogic,meson-gxbb-saradc" for GXBB
- "amlogic,meson-gxl-saradc" for GXL
- "amlogic,meson-gxm-saradc" for GXM
+ - "amlogic,meson-axg-saradc" for AXG
along with the generic "amlogic,meson-saradc"
- reg: the physical base address and length of the registers
- interrupts: the interrupt indicating end of sampling
diff --git a/dts/Bindings/iio/adc/mcp320x.txt b/dts/Bindings/iio/adc/mcp320x.txt
index 7d64753..56373d6 100644
--- a/dts/Bindings/iio/adc/mcp320x.txt
+++ b/dts/Bindings/iio/adc/mcp320x.txt
@@ -49,7 +49,7 @@ Required properties:
Examples:
spi_controller {
mcp3x0x@0 {
- compatible = "mcp3002";
+ compatible = "microchip,mcp3002";
reg = <0>;
spi-max-frequency = <1000000>;
vref-supply = <&vref_reg>;
diff --git a/dts/Bindings/arm/samsung/exynos-adc.txt b/dts/Bindings/iio/adc/samsung,exynos-adc.txt
index 6c49db7..6c49db7 100644
--- a/dts/Bindings/arm/samsung/exynos-adc.txt
+++ b/dts/Bindings/iio/adc/samsung,exynos-adc.txt
diff --git a/dts/Bindings/iio/adc/st,stm32-adc.txt b/dts/Bindings/iio/adc/st,stm32-adc.txt
index e8bb824..f1ead43 100644
--- a/dts/Bindings/iio/adc/st,stm32-adc.txt
+++ b/dts/Bindings/iio/adc/st,stm32-adc.txt
@@ -24,8 +24,11 @@ Required properties:
- compatible: Should be one of:
"st,stm32f4-adc-core"
"st,stm32h7-adc-core"
+ "st,stm32mp1-adc-core"
- reg: Offset and length of the ADC block register set.
-- interrupts: Must contain the interrupt for ADC block.
+- interrupts: One or more interrupts for ADC block. Some parts like stm32f4
+ and stm32h7 share a common ADC interrupt line. stm32mp1 has two separate
+ interrupt lines, one for each ADC within ADC block.
- clocks: Core can use up to two clocks, depending on part used:
- "adc" clock: for the analog circuitry, common to all ADCs.
It's required on stm32f4.
@@ -53,6 +56,7 @@ Required properties:
- compatible: Should be one of:
"st,stm32f4-adc"
"st,stm32h7-adc"
+ "st,stm32mp1-adc"
- reg: Offset of ADC instance in ADC block (e.g. may be 0x0, 0x100, 0x200).
- clocks: Input clock private to this ADC instance. It's required only on
stm32f4, that has per instance clock input for registers access.
diff --git a/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.txt b/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.txt
index ed7520d..75ba25d 100644
--- a/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.txt
+++ b/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.txt
@@ -8,14 +8,16 @@ It is mainly targeted for:
- PDM microphones (audio digital microphone)
It features up to 8 serial digital interfaces (SPI or Manchester) and
-up to 4 filters on stm32h7.
+up to 4 filters on stm32h7 or 6 filters on stm32mp1.
Each child node match with a filter instance.
Contents of a STM32 DFSDM root node:
------------------------------------
Required properties:
-- compatible: Should be "st,stm32h7-dfsdm".
+- compatible: Should be one of:
+ "st,stm32h7-dfsdm"
+ "st,stm32mp1-dfsdm"
- reg: Offset and length of the DFSDM block register set.
- clocks: IP and serial interfaces clocking. Should be set according
to rcc clock ID and "clock-names".
@@ -45,6 +47,7 @@ Required properties:
"st,stm32-dfsdm-adc" for sigma delta ADCs
"st,stm32-dfsdm-dmic" for audio digital microphone.
- reg: Specifies the DFSDM filter instance used.
+ Valid values are from 0 to 3 on stm32h7, 0 to 5 on stm32mp1.
- interrupts: IRQ lines connected to each DFSDM filter instance.
- st,adc-channels: List of single-ended channels muxed for this ADC.
valid values:
diff --git a/dts/Bindings/iio/afe/current-sense-amplifier.txt b/dts/Bindings/iio/afe/current-sense-amplifier.txt
new file mode 100644
index 0000000..821b61b
--- /dev/null
+++ b/dts/Bindings/iio/afe/current-sense-amplifier.txt
@@ -0,0 +1,26 @@
+Current Sense Amplifier
+=======================
+
+When an io-channel measures the output voltage from a current sense
+amplifier, the interesting measurement is almost always the current
+through the sense resistor, not the voltage output. This binding
+describes such a current sense circuit.
+
+Required properties:
+- compatible : "current-sense-amplifier"
+- io-channels : Channel node of a voltage io-channel.
+- sense-resistor-micro-ohms : The sense resistance in microohms.
+
+Optional properties:
+- sense-gain-mult: Amplifier gain multiplier. The default is <1>.
+- sense-gain-div: Amplifier gain divider. The default is <1>.
+
+Example:
+
+sysi {
+ compatible = "current-sense-amplifier";
+ io-channels = <&tiadc 0>;
+
+ sense-resistor-micro-ohms = <20000>;
+ sense-gain-mul = <50>;
+};
diff --git a/dts/Bindings/iio/afe/current-sense-shunt.txt b/dts/Bindings/iio/afe/current-sense-shunt.txt
new file mode 100644
index 0000000..0f67108
--- /dev/null
+++ b/dts/Bindings/iio/afe/current-sense-shunt.txt
@@ -0,0 +1,41 @@
+Current Sense Shunt
+===================
+
+When an io-channel measures the voltage over a current sense shunt,
+the interesting measurement is almost always the current through the
+shunt, not the voltage over it. This binding describes such a current
+sense circuit.
+
+Required properties:
+- compatible : "current-sense-shunt"
+- io-channels : Channel node of a voltage io-channel.
+- shunt-resistor-micro-ohms : The shunt resistance in microohms.
+
+Example:
+The system current is measured by measuring the voltage over a
+3.3 ohms shunt resistor.
+
+sysi {
+ compatible = "current-sense-shunt";
+ io-channels = <&tiadc 0>;
+
+ /* Divide the voltage by 3300000/1000000 (or 3.3) for the current. */
+ shunt-resistor-micro-ohms = <3300000>;
+};
+
+&i2c {
+ tiadc: adc@48 {
+ compatible = "ti,ads1015";
+ reg = <0x48>;
+ #io-channel-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 { /* IN0,IN1 differential */
+ reg = <0>;
+ ti,gain = <1>;
+ ti,datarate = <4>;
+ };
+ };
+};
diff --git a/dts/Bindings/iio/afe/voltage-divider.txt b/dts/Bindings/iio/afe/voltage-divider.txt
new file mode 100644
index 0000000..b452a84
--- /dev/null
+++ b/dts/Bindings/iio/afe/voltage-divider.txt
@@ -0,0 +1,53 @@
+Voltage divider
+===============
+
+When an io-channel measures the midpoint of a voltage divider, the
+interesting voltage is often the voltage over the full resistance
+of the divider. This binding describes the voltage divider in such
+a curcuit.
+
+ Vin ----.
+ |
+ .-----.
+ | R |
+ '-----'
+ |
+ +---- Vout
+ |
+ .-----.
+ | Rout|
+ '-----'
+ |
+ GND
+
+Required properties:
+- compatible : "voltage-divider"
+- io-channels : Channel node of a voltage io-channel measuring Vout.
+- output-ohms : Resistance Rout over which the output voltage is measured.
+ See full-ohms.
+- full-ohms : Resistance R + Rout for the full divider. The io-channel
+ is scaled by the Rout / (R + Rout) quotient.
+
+Example:
+The system voltage is circa 12V, but divided down with a 22/222
+voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC.
+
+sysv {
+ compatible = "voltage-divider";
+ io-channels = <&maxadc 1>;
+
+ /* Scale the system voltage by 22/222 to fit the ADC range. */
+ output-ohms = <22>;
+ full-ohms = <222>; /* 200 + 22 */
+};
+
+&spi {
+ maxadc: adc@0 {
+ compatible = "maxim,max1027";
+ reg = <0>;
+ #io-channel-cells = <1>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <15 IRQ_TYPE_EDGE_RISING>;
+ spi-max-frequency = <1000000>;
+ };
+};
diff --git a/dts/Bindings/iio/dac/ltc2632.txt b/dts/Bindings/iio/dac/ltc2632.txt
index eb911e5..e0d5fea 100644
--- a/dts/Bindings/iio/dac/ltc2632.txt
+++ b/dts/Bindings/iio/dac/ltc2632.txt
@@ -12,12 +12,26 @@ Required properties:
Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt
apply. In particular, "reg" and "spi-max-frequency" properties must be given.
+Optional properties:
+ - vref-supply: Phandle to the external reference voltage supply. This should
+ only be set if there is an external reference voltage connected to the VREF
+ pin. If the property is not set the internal reference is used.
+
Example:
+ vref: regulator-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-ltc2632";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ };
+
spi_master {
dac: ltc2632@0 {
compatible = "lltc,ltc2632-l12";
reg = <0>; /* CS0 */
spi-max-frequency = <1000000>;
+ vref-supply = <&vref>; /* optional */
};
};
diff --git a/dts/Bindings/iio/dac/ti,dac5571.txt b/dts/Bindings/iio/dac/ti,dac5571.txt
new file mode 100644
index 0000000..03af6b9
--- /dev/null
+++ b/dts/Bindings/iio/dac/ti,dac5571.txt
@@ -0,0 +1,24 @@
+* Texas Instruments DAC5571 Family
+
+Required properties:
+ - compatible: Should contain
+ "ti,dac5571"
+ "ti,dac6571"
+ "ti,dac7571"
+ "ti,dac5574"
+ "ti,dac6574"
+ "ti,dac7574"
+ "ti,dac5573"
+ "ti,dac6573"
+ "ti,dac7573"
+ - reg: Should contain the DAC I2C address
+
+Optional properties:
+ - vref-supply: The regulator supply for DAC reference voltage
+
+Example:
+dac@0 {
+ compatible = "ti,dac5571";
+ reg = <0x4C>;
+ vref-supply = <&vdd_supply>;
+};
diff --git a/dts/Bindings/iio/imu/inv_mpu6050.txt b/dts/Bindings/iio/imu/inv_mpu6050.txt
index 2b45145..5f4777e 100644
--- a/dts/Bindings/iio/imu/inv_mpu6050.txt
+++ b/dts/Bindings/iio/imu/inv_mpu6050.txt
@@ -8,10 +8,16 @@ Required properties:
"invensense,mpu6500"
"invensense,mpu9150"
"invensense,mpu9250"
+ "invensense,mpu9255"
"invensense,icm20608"
- reg : the I2C address of the sensor
- interrupt-parent : should be the phandle for the interrupt controller
- - interrupts : interrupt mapping for GPIO IRQ
+ - interrupts: interrupt mapping for IRQ. It should be configured with flags
+ IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
+ IRQ_TYPE_EDGE_FALLING.
+
+ Refer to interrupt-controller/interrupts.txt for generic interrupt client node
+ bindings.
Optional properties:
- mount-matrix: an optional 3x3 mounting rotation matrix
@@ -24,7 +30,7 @@ Example:
compatible = "invensense,mpu6050";
reg = <0x68>;
interrupt-parent = <&gpio1>;
- interrupts = <18 1>;
+ interrupts = <18 IRQ_TYPE_EDGE_RISING>;
mount-matrix = "-0.984807753012208", /* x0 */
"0", /* y0 */
"-0.173648177666930", /* z0 */
@@ -41,7 +47,7 @@ Example:
compatible = "invensense,mpu9250";
reg = <0x68>;
interrupt-parent = <&gpio3>;
- interrupts = <21 1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
i2c-gate {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/Bindings/iio/imu/st_lsm6dsx.txt b/dts/Bindings/iio/imu/st_lsm6dsx.txt
index 1ff1af7..ef8a856 100644
--- a/dts/Bindings/iio/imu/st_lsm6dsx.txt
+++ b/dts/Bindings/iio/imu/st_lsm6dsx.txt
@@ -6,6 +6,7 @@ Required properties:
"st,lsm6ds3h"
"st,lsm6dsl"
"st,lsm6dsm"
+ "st,ism330dlc"
- reg: i2c address of the sensor / spi cs line
Optional properties:
diff --git a/dts/Bindings/iio/potentiostat/lmp91000.txt b/dts/Bindings/iio/potentiostat/lmp91000.txt
index b9b621e..e6d0c2e 100644
--- a/dts/Bindings/iio/potentiostat/lmp91000.txt
+++ b/dts/Bindings/iio/potentiostat/lmp91000.txt
@@ -1,10 +1,13 @@
-* Texas Instruments LMP91000 potentiostat
+* Texas Instruments LMP91000 series of potentiostats
-http://www.ti.com/lit/ds/symlink/lmp91000.pdf
+LMP91000: http://www.ti.com/lit/ds/symlink/lmp91000.pdf
+LMP91002: http://www.ti.com/lit/ds/symlink/lmp91002.pdf
Required properties:
- - compatible: should be "ti,lmp91000"
+ - compatible: should be one of the following:
+ "ti,lmp91000"
+ "ti,lmp91002"
- reg: the I2C address of the device
- io-channels: the phandle of the iio provider
diff --git a/dts/Bindings/input/elan_i2c.txt b/dts/Bindings/input/elan_i2c.txt
index ee3242c..d80a835 100644
--- a/dts/Bindings/input/elan_i2c.txt
+++ b/dts/Bindings/input/elan_i2c.txt
@@ -14,6 +14,7 @@ Optional properties:
- pinctrl-0: a phandle pointing to the pin settings for the device (see
pinctrl binding [1]).
- vcc-supply: a phandle for the regulator supplying 3.3V power.
+- elan,trackpoint: touchpad can support a trackpoint (boolean)
[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
diff --git a/dts/Bindings/input/mtk-pmic-keys.txt b/dts/Bindings/input/mtk-pmic-keys.txt
new file mode 100644
index 0000000..2888d07
--- /dev/null
+++ b/dts/Bindings/input/mtk-pmic-keys.txt
@@ -0,0 +1,43 @@
+MediaTek MT6397/MT6323 PMIC Keys Device Driver
+
+There are two key functions provided by MT6397/MT6323 PMIC, pwrkey
+and homekey. The key functions are defined as the subnode of the function
+node provided by MT6397/MT6323 PMIC that is being defined as one kind
+of Muti-Function Device (MFD)
+
+For MT6397/MT6323 MFD bindings see:
+Documentation/devicetree/bindings/mfd/mt6397.txt
+
+Required properties:
+- compatible: "mediatek,mt6397-keys" or "mediatek,mt6323-keys"
+- linux,keycodes: See Documentation/devicetree/bindings/input/keys.txt
+
+Optional Properties:
+- wakeup-source: See Documentation/devicetree/bindings/power/wakeup-source.txt
+- mediatek,long-press-mode: Long press key shutdown setting, 1 for
+ pwrkey only, 2 for pwrkey/homekey together, others for disabled.
+- power-off-time-sec: See Documentation/devicetree/bindings/input/keys.txt
+
+Example:
+
+ pmic: mt6397 {
+ compatible = "mediatek,mt6397";
+
+ ...
+
+ mt6397keys: mt6397keys {
+ compatible = "mediatek,mt6397-keys";
+ mediatek,long-press-mode = <1>;
+ power-off-time-sec = <0>;
+
+ power {
+ linux,keycodes = <116>;
+ wakeup-source;
+ };
+
+ home {
+ linux,keycodes = <114>;
+ };
+ };
+
+ };
diff --git a/dts/Bindings/input/rmi4/rmi_2d_sensor.txt b/dts/Bindings/input/rmi4/rmi_2d_sensor.txt
index f2c30c8..9afffbd 100644
--- a/dts/Bindings/input/rmi4/rmi_2d_sensor.txt
+++ b/dts/Bindings/input/rmi4/rmi_2d_sensor.txt
@@ -12,7 +12,7 @@ Additional documentation for F11 can be found at:
http://www.synaptics.com/sites/default/files/511-000136-01-Rev-E-RMI4-Interfacing-Guide.pdf
Optional Touch Properties:
-Description in Documentation/devicetree/bindings/input/touch
+Description in Documentation/devicetree/bindings/input/touchscreen
- touchscreen-inverted-x
- touchscreen-inverted-y
- touchscreen-swapped-x-y
diff --git a/dts/Bindings/input/rotary-encoder.txt b/dts/Bindings/input/rotary-encoder.txt
index f99fe5c..a644408 100644
--- a/dts/Bindings/input/rotary-encoder.txt
+++ b/dts/Bindings/input/rotary-encoder.txt
@@ -28,7 +28,7 @@ Deprecated properties:
This property is deprecated. Instead, a 'steps-per-period ' value should
be used, such as "rotary-encoder,steps-per-period = <2>".
-See Documentation/input/rotary-encoder.txt for more information.
+See Documentation/input/devices/rotary-encoder.rst for more information.
Example:
diff --git a/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
index a83f9a5..89674ad 100644
--- a/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
+++ b/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -9,11 +9,12 @@ number of interrupt exposed depends on the SoC.
Required properties:
-- compatible : must have "amlogic,meson8-gpio-intc” and either
- “amlogic,meson8-gpio-intc” for meson8 SoCs (S802) or
- “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or
- “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or
- “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912)
+- compatible : must have "amlogic,meson8-gpio-intc" and either
+ "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or
+ "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or
+ "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
+ "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
+ "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
- interrupt-parent : a phandle to the GIC the interrupts are routed to.
Usually this is provided at the root level of the device tree as it is
common to most of the SoC.
diff --git a/dts/Bindings/interrupt-controller/arm,gic-v3.txt b/dts/Bindings/interrupt-controller/arm,gic-v3.txt
index 0a57f2f..3ea78c4 100644
--- a/dts/Bindings/interrupt-controller/arm,gic-v3.txt
+++ b/dts/Bindings/interrupt-controller/arm,gic-v3.txt
@@ -57,6 +57,20 @@ Optional
occupied by the redistributors. Required if more than one such
region is present.
+- msi-controller: Boolean property. Identifies the node as an MSI
+ controller. Only present if the Message Based Interrupt
+ functionnality is being exposed by the HW, and the mbi-ranges
+ property present.
+
+- mbi-ranges: A list of pairs <intid span>, where "intid" is the first
+ SPI of a range that can be used an MBI, and "span" the size of that
+ range. Multiple ranges can be provided. Requires "msi-controller" to
+ be set.
+
+- mbi-alias: Address property. Base address of an alias of the GICD
+ region containing only the {SET,CLR}SPI registers to be used if
+ isolation is required, and if supported by the HW.
+
Sub-nodes:
PPI affinity can be expressed as a single "ppi-partitions" node,
@@ -99,6 +113,9 @@ Examples:
<0x0 0x2c020000 0 0x2000>; // GICV
interrupts = <1 9 4>;
+ msi-controller;
+ mbi-ranges = <256 128>;
+
gic-its@2c200000 {
compatible = "arm,gic-v3-its";
msi-controller;
diff --git a/dts/Bindings/interrupt-controller/st,stm32-exti.txt b/dts/Bindings/interrupt-controller/st,stm32-exti.txt
index edf03f0..136bd61 100644
--- a/dts/Bindings/interrupt-controller/st,stm32-exti.txt
+++ b/dts/Bindings/interrupt-controller/st,stm32-exti.txt
@@ -5,11 +5,14 @@ Required properties:
- compatible: Should be:
"st,stm32-exti"
"st,stm32h7-exti"
+ "st,stm32mp1-exti"
- reg: Specifies base physical address and size of the registers
- interrupt-controller: Indentifies the node as an interrupt controller
- #interrupt-cells: Specifies the number of cells to encode an interrupt
specifier, shall be 2
- interrupts: interrupts references to primary interrupt controller
+ (only needed for exti controller with multiple exti under
+ same parent interrupt: st,stm32-exti and st,stm32h7-exti")
Example:
diff --git a/dts/Bindings/ipmi/npcm7xx-kcs-bmc.txt b/dts/Bindings/ipmi/npcm7xx-kcs-bmc.txt
new file mode 100644
index 0000000..3538a21
--- /dev/null
+++ b/dts/Bindings/ipmi/npcm7xx-kcs-bmc.txt
@@ -0,0 +1,39 @@
+* Nuvoton NPCM7xx KCS (Keyboard Controller Style) IPMI interface
+
+The Nuvoton SOCs (NPCM7xx) are commonly used as BMCs
+(Baseboard Management Controllers) and the KCS interface can be
+used to perform in-band IPMI communication with their host.
+
+Required properties:
+- compatible : should be one of
+ "nuvoton,npcm750-kcs-bmc"
+- interrupts : interrupt generated by the controller
+- kcs_chan : The KCS channel number in the controller
+
+Example:
+
+ lpc_kcs: lpc_kcs@f0007000 {
+ compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
+ reg = <0xf0007000 0x40>;
+ reg-io-width = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf0007000 0x40>;
+
+ kcs1: kcs1@0 {
+ compatible = "nuvoton,npcm750-kcs-bmc";
+ reg = <0x0 0x40>;
+ interrupts = <0 9 4>;
+ kcs_chan = <1>;
+ status = "disabled";
+ };
+
+ kcs2: kcs2@0 {
+ compatible = "nuvoton,npcm750-kcs-bmc";
+ reg = <0x0 0x40>;
+ interrupts = <0 9 4>;
+ kcs_chan = <2>;
+ status = "disabled";
+ };
+ }; \ No newline at end of file
diff --git a/dts/Bindings/leds/backlight/pwm-backlight.txt b/dts/Bindings/leds/backlight/pwm-backlight.txt
index 764db86..3108109 100644
--- a/dts/Bindings/leds/backlight/pwm-backlight.txt
+++ b/dts/Bindings/leds/backlight/pwm-backlight.txt
@@ -17,6 +17,10 @@ Optional properties:
"pwms" property (see PWM binding[0])
- enable-gpios: contains a single GPIO specifier for the GPIO which enables
and disables the backlight (see GPIO binding[1])
+ - post-pwm-on-delay-ms: Delay in ms between setting an initial (non-zero) PWM
+ and enabling the backlight using GPIO.
+ - pwm-off-delay-ms: Delay in ms between disabling the backlight using GPIO
+ and setting PWM value to 0.
[0]: Documentation/devicetree/bindings/pwm/pwm.txt
[1]: Documentation/devicetree/bindings/gpio/gpio.txt
@@ -32,4 +36,6 @@ Example:
power-supply = <&vdd_bl_reg>;
enable-gpios = <&gpio 58 0>;
+ post-pwm-on-delay-ms = <10>;
+ pwm-off-delay-ms = <10>;
};
diff --git a/dts/Bindings/leds/backlight/zii,rave-sp-backlight.txt b/dts/Bindings/leds/backlight/zii,rave-sp-backlight.txt
new file mode 100644
index 0000000..ff5c921
--- /dev/null
+++ b/dts/Bindings/leds/backlight/zii,rave-sp-backlight.txt
@@ -0,0 +1,23 @@
+Zodiac Inflight Innovations RAVE Supervisory Processor Backlight Bindings
+
+RAVE SP backlight device is a "MFD cell" device corresponding to
+backlight functionality of RAVE Supervisory Processor. It is expected
+that its Device Tree node is specified as a child of the node
+corresponding to the parent RAVE SP device (as documented in
+Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)
+
+Required properties:
+
+- compatible: Should be "zii,rave-sp-backlight"
+
+Example:
+
+ rave-sp {
+ compatible = "zii,rave-sp-rdu1";
+ current-speed = <38400>;
+
+ backlight {
+ compatible = "zii,rave-sp-backlight";
+ };
+ }
+
diff --git a/dts/Bindings/leds/leds-cr0014114.txt b/dts/Bindings/leds/leds-cr0014114.txt
new file mode 100644
index 0000000..4255b19
--- /dev/null
+++ b/dts/Bindings/leds/leds-cr0014114.txt
@@ -0,0 +1,54 @@
+Crane Merchandising System - cr0014114 LED driver
+-------------------------------------------------
+
+This LED Board is widely used in vending machines produced
+by Crane Merchandising Systems.
+
+Required properties:
+- compatible: "crane,cr0014114"
+
+Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt
+apply. In particular, "reg" and "spi-max-frequency" properties must be given.
+
+LED sub-node properties:
+- label :
+ see Documentation/devicetree/bindings/leds/common.txt
+- linux,default-trigger : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
+
+Example
+-------
+
+led-controller@0 {
+ compatible = "crane,cr0014114";
+ reg = <0>;
+ spi-max-frequency = <50000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ label = "red:coin";
+ };
+ led@1 {
+ reg = <1>;
+ label = "green:coin";
+ };
+ led@2 {
+ reg = <2>;
+ label = "blue:coin";
+ };
+ led@3 {
+ reg = <3>;
+ label = "red:bill";
+ };
+ led@4 {
+ reg = <4>;
+ label = "green:bill";
+ };
+ led@5 {
+ reg = <5>;
+ label = "blue:bill";
+ };
+ ...
+};
diff --git a/dts/Bindings/leds/leds-lm3601x.txt b/dts/Bindings/leds/leds-lm3601x.txt
new file mode 100644
index 0000000..a88b2c4
--- /dev/null
+++ b/dts/Bindings/leds/leds-lm3601x.txt
@@ -0,0 +1,45 @@
+* Texas Instruments - lm3601x Single-LED Flash Driver
+
+The LM3601X are ultra-small LED flash drivers that
+provide a high level of adjustability.
+
+Required properties:
+ - compatible : Can be one of the following
+ "ti,lm36010"
+ "ti,lm36011"
+ - reg : I2C slave address
+ - #address-cells : 1
+ - #size-cells : 0
+
+Required child properties:
+ - reg : 0 - Indicates a IR mode
+ 1 - Indicates a Torch (white LED) mode
+
+Required properties for flash LED child nodes:
+ See Documentation/devicetree/bindings/leds/common.txt
+ - flash-max-microamp : Range from 11mA - 1.5A
+ - flash-max-timeout-us : Range from 40ms - 1600ms
+ - led-max-microamp : Range from 2.4mA - 376mA
+
+Optional child properties:
+ - label : see Documentation/devicetree/bindings/leds/common.txt
+
+Example:
+led-controller@64 {
+ compatible = "ti,lm36010";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x64>;
+
+ led@0 {
+ reg = <1>;
+ label = "white:torch";
+ led-max-microamp = <376000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <1600000>;
+ };
+}
+
+For more product information please see the links below:
+http://www.ti.com/product/LM36010
+http://www.ti.com/product/LM36011
diff --git a/dts/Bindings/leds/leds-sc27xx-bltc.txt b/dts/Bindings/leds/leds-sc27xx-bltc.txt
new file mode 100644
index 0000000..dddf84f
--- /dev/null
+++ b/dts/Bindings/leds/leds-sc27xx-bltc.txt
@@ -0,0 +1,41 @@
+LEDs connected to Spreadtrum SC27XX PMIC breathing light controller
+
+The SC27xx breathing light controller supports to 3 outputs:
+red LED, green LED and blue LED. Each LED can work at normal
+PWM mode or breath light mode.
+
+Required properties:
+- compatible: Should be "sprd,sc2731-bltc".
+- #address-cells: Must be 1.
+- #size-cells: Must be 0.
+- reg: Specify the controller address.
+
+Required child properties:
+- reg: Port this LED is connected to.
+
+Optional child properties:
+- label: See Documentation/devicetree/bindings/leds/common.txt.
+
+Examples:
+
+led-controller@200 {
+ compatible = "sprd,sc2731-bltc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x200>;
+
+ led@0 {
+ label = "red";
+ reg = <0x0>;
+ };
+
+ led@1 {
+ label = "green";
+ reg = <0x1>;
+ };
+
+ led@2 {
+ label = "blue";
+ reg = <0x2>;
+ };
+};
diff --git a/dts/Bindings/mailbox/qcom,apcs-kpss-global.txt b/dts/Bindings/mailbox/qcom,apcs-kpss-global.txt
index 16964f0..6e8a9ab 100644
--- a/dts/Bindings/mailbox/qcom,apcs-kpss-global.txt
+++ b/dts/Bindings/mailbox/qcom,apcs-kpss-global.txt
@@ -10,6 +10,8 @@ platforms.
Definition: must be one of:
"qcom,msm8916-apcs-kpss-global",
"qcom,msm8996-apcs-hmss-global"
+ "qcom,msm8998-apcs-hmss-global"
+ "qcom,sdm845-apss-shared"
- reg:
Usage: required
diff --git a/dts/Bindings/mailbox/stm32-ipcc.txt b/dts/Bindings/mailbox/stm32-ipcc.txt
new file mode 100644
index 0000000..1d2b7fe
--- /dev/null
+++ b/dts/Bindings/mailbox/stm32-ipcc.txt
@@ -0,0 +1,47 @@
+* STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller)
+
+The IPCC block provides a non blocking signaling mechanism to post and
+retrieve messages in an atomic way between two processors.
+It provides the signaling for N bidirectionnal channels. The number of channels
+(N) can be read from a dedicated register.
+
+Required properties:
+- compatible: Must be "st,stm32mp1-ipcc"
+- reg: Register address range (base address and length)
+- st,proc-id: Processor id using the mailbox (0 or 1)
+- clocks: Input clock
+- interrupt-names: List of names for the interrupts described by the interrupt
+ property. Must contain the following entries:
+ - "rx"
+ - "tx"
+ - "wakeup"
+- interrupts: Interrupt specifiers for "rx channel occupied", "tx channel
+ free" and "system wakeup".
+- #mbox-cells: Number of cells required for the mailbox specifier. Must be 1.
+ The data contained in the mbox specifier of the "mboxes"
+ property in the client node is the mailbox channel index.
+
+Optional properties:
+- wakeup-source: Flag to indicate whether this device can wake up the system
+
+
+
+Example:
+ ipcc: mailbox@4c001000 {
+ compatible = "st,stm32mp1-ipcc";
+ #mbox-cells = <1>;
+ reg = <0x4c001000 0x400>;
+ st,proc-id = <0>;
+ interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>,
+ <&intc GIC_SPI 101 IRQ_TYPE_NONE>,
+ <&aiec 62 1>;
+ interrupt-names = "rx", "tx", "wakeup";
+ clocks = <&rcc_clk IPCC>;
+ wakeup-source;
+ }
+
+Client:
+ mbox_test {
+ ...
+ mboxes = <&ipcc 0>, <&ipcc 1>;
+ };
diff --git a/dts/Bindings/marvell.txt b/dts/Bindings/marvell.txt
deleted file mode 100644
index 7f72231..0000000
--- a/dts/Bindings/marvell.txt
+++ /dev/null
@@ -1,516 +0,0 @@
-Marvell Discovery mv64[345]6x System Controller chips
-===========================================================
-
-The Marvell mv64[345]60 series of system controller chips contain
-many of the peripherals needed to implement a complete computer
-system. In this section, we define device tree nodes to describe
-the system controller chip itself and each of the peripherals
-which it contains. Compatible string values for each node are
-prefixed with the string "marvell,", for Marvell Technology Group Ltd.
-
-1) The /system-controller node
-
- This node is used to represent the system-controller and must be
- present when the system uses a system controller chip. The top-level
- system-controller node contains information that is global to all
- devices within the system controller chip. The node name begins
- with "system-controller" followed by the unit address, which is
- the base address of the memory-mapped register set for the system
- controller chip.
-
- Required properties:
-
- - ranges : Describes the translation of system controller addresses
- for memory mapped registers.
- - clock-frequency: Contains the main clock frequency for the system
- controller chip.
- - reg : This property defines the address and size of the
- memory-mapped registers contained within the system controller
- chip. The address specified in the "reg" property should match
- the unit address of the system-controller node.
- - #address-cells : Address representation for system controller
- devices. This field represents the number of cells needed to
- represent the address of the memory-mapped registers of devices
- within the system controller chip.
- - #size-cells : Size representation for the memory-mapped
- registers within the system controller chip.
- - #interrupt-cells : Defines the width of cells used to represent
- interrupts.
-
- Optional properties:
-
- - model : The specific model of the system controller chip. Such
- as, "mv64360", "mv64460", or "mv64560".
- - compatible : A string identifying the compatibility identifiers
- of the system controller chip.
-
- The system-controller node contains child nodes for each system
- controller device that the platform uses. Nodes should not be created
- for devices which exist on the system controller chip but are not used
-
- Example Marvell Discovery mv64360 system-controller node:
-
- system-controller@f1000000 { /* Marvell Discovery mv64360 */
- #address-cells = <1>;
- #size-cells = <1>;
- model = "mv64360"; /* Default */
- compatible = "marvell,mv64360";
- clock-frequency = <133333333>;
- reg = <0xf1000000 0x10000>;
- virtual-reg = <0xf1000000>;
- ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
- 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
- 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
- 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
- 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
-
- [ child node definitions... ]
- }
-
-2) Child nodes of /system-controller
-
- a) Marvell Discovery MDIO bus
-
- The MDIO is a bus to which the PHY devices are connected. For each
- device that exists on this bus, a child node should be created. See
- the definition of the PHY node below for an example of how to define
- a PHY.
-
- Required properties:
- - #address-cells : Should be <1>
- - #size-cells : Should be <0>
- - compatible : Should be "marvell,mv64360-mdio"
-
- Example:
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,mv64360-mdio";
-
- ethernet-phy@0 {
- ......
- };
- };
-
-
- b) Marvell Discovery ethernet controller
-
- The Discover ethernet controller is described with two levels
- of nodes. The first level describes an ethernet silicon block
- and the second level describes up to 3 ethernet nodes within
- that block. The reason for the multiple levels is that the
- registers for the node are interleaved within a single set
- of registers. The "ethernet-block" level describes the
- shared register set, and the "ethernet" nodes describe ethernet
- port-specific properties.
-
- Ethernet block node
-
- Required properties:
- - #address-cells : <1>
- - #size-cells : <0>
- - compatible : "marvell,mv64360-eth-block"
- - reg : Offset and length of the register set for this block
-
- Optional properties:
- - clocks : Phandle to the clock control device and gate bit
-
- Example Discovery Ethernet block node:
- ethernet-block@2000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,mv64360-eth-block";
- reg = <0x2000 0x2000>;
- ethernet@0 {
- .......
- };
- };
-
- Ethernet port node
-
- Required properties:
- - compatible : Should be "marvell,mv64360-eth".
- - reg : Should be <0>, <1>, or <2>, according to which registers
- within the silicon block the device uses.
- - interrupts : <a> where a is the interrupt number for the port.
- - interrupt-parent : the phandle for the interrupt controller
- that services interrupts for this device.
- - phy : the phandle for the PHY connected to this ethernet
- controller.
- - local-mac-address : 6 bytes, MAC address
-
- Example Discovery Ethernet port node:
- ethernet@0 {
- compatible = "marvell,mv64360-eth";
- reg = <0>;
- interrupts = <32>;
- interrupt-parent = <&PIC>;
- phy = <&PHY0>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- };
-
-
-
- c) Marvell Discovery PHY nodes
-
- Required properties:
- - interrupts : <a> where a is the interrupt number for this phy.
- - interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
- - reg : The ID number for the phy, usually a small integer
-
- Example Discovery PHY node:
- ethernet-phy@1 {
- compatible = "broadcom,bcm5421";
- interrupts = <76>; /* GPP 12 */
- interrupt-parent = <&PIC>;
- reg = <1>;
- };
-
-
- d) Marvell Discovery SDMA nodes
-
- Represent DMA hardware associated with the MPSC (multiprotocol
- serial controllers).
-
- Required properties:
- - compatible : "marvell,mv64360-sdma"
- - reg : Offset and length of the register set for this device
- - interrupts : <a> where a is the interrupt number for the DMA
- device.
- - interrupt-parent : the phandle for the interrupt controller
- that services interrupts for this device.
-
- Example Discovery SDMA node:
- sdma@4000 {
- compatible = "marvell,mv64360-sdma";
- reg = <0x4000 0xc18>;
- virtual-reg = <0xf1004000>;
- interrupts = <36>;
- interrupt-parent = <&PIC>;
- };
-
-
- e) Marvell Discovery BRG nodes
-
- Represent baud rate generator hardware associated with the MPSC
- (multiprotocol serial controllers).
-
- Required properties:
- - compatible : "marvell,mv64360-brg"
- - reg : Offset and length of the register set for this device
- - clock-src : A value from 0 to 15 which selects the clock
- source for the baud rate generator. This value corresponds
- to the CLKS value in the BRGx configuration register. See
- the mv64x60 User's Manual.
- - clock-frequence : The frequency (in Hz) of the baud rate
- generator's input clock.
- - current-speed : The current speed setting (presumably by
- firmware) of the baud rate generator.
-
- Example Discovery BRG node:
- brg@b200 {
- compatible = "marvell,mv64360-brg";
- reg = <0xb200 0x8>;
- clock-src = <8>;
- clock-frequency = <133333333>;
- current-speed = <9600>;
- };
-
-
- f) Marvell Discovery CUNIT nodes
-
- Represent the Serial Communications Unit device hardware.
-
- Required properties:
- - reg : Offset and length of the register set for this device
-
- Example Discovery CUNIT node:
- cunit@f200 {
- reg = <0xf200 0x200>;
- };
-
-
- g) Marvell Discovery MPSCROUTING nodes
-
- Represent the Discovery's MPSC routing hardware
-
- Required properties:
- - reg : Offset and length of the register set for this device
-
- Example Discovery CUNIT node:
- mpscrouting@b500 {
- reg = <0xb400 0xc>;
- };
-
-
- h) Marvell Discovery MPSCINTR nodes
-
- Represent the Discovery's MPSC DMA interrupt hardware registers
- (SDMA cause and mask registers).
-
- Required properties:
- - reg : Offset and length of the register set for this device
-
- Example Discovery MPSCINTR node:
- mpsintr@b800 {
- reg = <0xb800 0x100>;
- };
-
-
- i) Marvell Discovery MPSC nodes
-
- Represent the Discovery's MPSC (Multiprotocol Serial Controller)
- serial port.
-
- Required properties:
- - compatible : "marvell,mv64360-mpsc"
- - reg : Offset and length of the register set for this device
- - sdma : the phandle for the SDMA node used by this port
- - brg : the phandle for the BRG node used by this port
- - cunit : the phandle for the CUNIT node used by this port
- - mpscrouting : the phandle for the MPSCROUTING node used by this port
- - mpscintr : the phandle for the MPSCINTR node used by this port
- - cell-index : the hardware index of this cell in the MPSC core
- - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
- register
- - interrupts : <a> where a is the interrupt number for the MPSC.
- - interrupt-parent : the phandle for the interrupt controller
- that services interrupts for this device.
-
- Example Discovery MPSCINTR node:
- mpsc@8000 {
- compatible = "marvell,mv64360-mpsc";
- reg = <0x8000 0x38>;
- virtual-reg = <0xf1008000>;
- sdma = <&SDMA0>;
- brg = <&BRG0>;
- cunit = <&CUNIT>;
- mpscrouting = <&MPSCROUTING>;
- mpscintr = <&MPSCINTR>;
- cell-index = <0>;
- max_idle = <40>;
- interrupts = <40>;
- interrupt-parent = <&PIC>;
- };
-
-
- j) Marvell Discovery Watch Dog Timer nodes
-
- Represent the Discovery's watchdog timer hardware
-
- Required properties:
- - compatible : "marvell,mv64360-wdt"
- - reg : Offset and length of the register set for this device
-
- Example Discovery Watch Dog Timer node:
- wdt@b410 {
- compatible = "marvell,mv64360-wdt";
- reg = <0xb410 0x8>;
- };
-
-
- k) Marvell Discovery I2C nodes
-
- Represent the Discovery's I2C hardware
-
- Required properties:
- - device_type : "i2c"
- - compatible : "marvell,mv64360-i2c"
- - reg : Offset and length of the register set for this device
- - interrupts : <a> where a is the interrupt number for the I2C.
- - interrupt-parent : the phandle for the interrupt controller
- that services interrupts for this device.
-
- Example Discovery I2C node:
- compatible = "marvell,mv64360-i2c";
- reg = <0xc000 0x20>;
- virtual-reg = <0xf100c000>;
- interrupts = <37>;
- interrupt-parent = <&PIC>;
- };
-
-
- l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
-
- Represent the Discovery's PIC hardware
-
- Required properties:
- - #interrupt-cells : <1>
- - #address-cells : <0>
- - compatible : "marvell,mv64360-pic"
- - reg : Offset and length of the register set for this device
- - interrupt-controller
-
- Example Discovery PIC node:
- pic {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- compatible = "marvell,mv64360-pic";
- reg = <0x0 0x88>;
- interrupt-controller;
- };
-
-
- m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
-
- Represent the Discovery's MPP hardware
-
- Required properties:
- - compatible : "marvell,mv64360-mpp"
- - reg : Offset and length of the register set for this device
-
- Example Discovery MPP node:
- mpp@f000 {
- compatible = "marvell,mv64360-mpp";
- reg = <0xf000 0x10>;
- };
-
-
- n) Marvell Discovery GPP (General Purpose Pins) nodes
-
- Represent the Discovery's GPP hardware
-
- Required properties:
- - compatible : "marvell,mv64360-gpp"
- - reg : Offset and length of the register set for this device
-
- Example Discovery GPP node:
- gpp@f000 {
- compatible = "marvell,mv64360-gpp";
- reg = <0xf100 0x20>;
- };
-
-
- o) Marvell Discovery PCI host bridge node
-
- Represents the Discovery's PCI host bridge device. The properties
- for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
- 1275-1994. A typical value for the compatible property is
- "marvell,mv64360-pci".
-
- Example Discovery PCI host bridge node
- pci@80000000 {
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- compatible = "marvell,mv64360-pci";
- reg = <0xcf8 0x8>;
- ranges = <0x01000000 0x0 0x0
- 0x88000000 0x0 0x01000000
- 0x02000000 0x0 0x80000000
- 0x80000000 0x0 0x08000000>;
- bus-range = <0 255>;
- clock-frequency = <66000000>;
- interrupt-parent = <&PIC>;
- interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
- interrupt-map = <
- /* IDSEL 0x0a */
- 0x5000 0 0 1 &PIC 80
- 0x5000 0 0 2 &PIC 81
- 0x5000 0 0 3 &PIC 91
- 0x5000 0 0 4 &PIC 93
-
- /* IDSEL 0x0b */
- 0x5800 0 0 1 &PIC 91
- 0x5800 0 0 2 &PIC 93
- 0x5800 0 0 3 &PIC 80
- 0x5800 0 0 4 &PIC 81
-
- /* IDSEL 0x0c */
- 0x6000 0 0 1 &PIC 91
- 0x6000 0 0 2 &PIC 93
- 0x6000 0 0 3 &PIC 80
- 0x6000 0 0 4 &PIC 81
-
- /* IDSEL 0x0d */
- 0x6800 0 0 1 &PIC 93
- 0x6800 0 0 2 &PIC 80
- 0x6800 0 0 3 &PIC 81
- 0x6800 0 0 4 &PIC 91
- >;
- };
-
-
- p) Marvell Discovery CPU Error nodes
-
- Represent the Discovery's CPU error handler device.
-
- Required properties:
- - compatible : "marvell,mv64360-cpu-error"
- - reg : Offset and length of the register set for this device
- - interrupts : the interrupt number for this device
- - interrupt-parent : the phandle for the interrupt controller
- that services interrupts for this device.
-
- Example Discovery CPU Error node:
- cpu-error@70 {
- compatible = "marvell,mv64360-cpu-error";
- reg = <0x70 0x10 0x128 0x28>;
- interrupts = <3>;
- interrupt-parent = <&PIC>;
- };
-
-
- q) Marvell Discovery SRAM Controller nodes
-
- Represent the Discovery's SRAM controller device.
-
- Required properties:
- - compatible : "marvell,mv64360-sram-ctrl"
- - reg : Offset and length of the register set for this device
- - interrupts : the interrupt number for this device
- - interrupt-parent : the phandle for the interrupt controller
- that services interrupts for this device.
-
- Example Discovery SRAM Controller node:
- sram-ctrl@380 {
- compatible = "marvell,mv64360-sram-ctrl";
- reg = <0x380 0x80>;
- interrupts = <13>;
- interrupt-parent = <&PIC>;
- };
-
-
- r) Marvell Discovery PCI Error Handler nodes
-
- Represent the Discovery's PCI error handler device.
-
- Required properties:
- - compatible : "marvell,mv64360-pci-error"
- - reg : Offset and length of the register set for this device
- - interrupts : the interrupt number for this device
- - interrupt-parent : the phandle for the interrupt controller
- that services interrupts for this device.
-
- Example Discovery PCI Error Handler node:
- pci-error@1d40 {
- compatible = "marvell,mv64360-pci-error";
- reg = <0x1d40 0x40 0xc28 0x4>;
- interrupts = <12>;
- interrupt-parent = <&PIC>;
- };
-
-
- s) Marvell Discovery Memory Controller nodes
-
- Represent the Discovery's memory controller device.
-
- Required properties:
- - compatible : "marvell,mv64360-mem-ctrl"
- - reg : Offset and length of the register set for this device
- - interrupts : the interrupt number for this device
- - interrupt-parent : the phandle for the interrupt controller
- that services interrupts for this device.
-
- Example Discovery Memory Controller node:
- mem-ctrl@1400 {
- compatible = "marvell,mv64360-mem-ctrl";
- reg = <0x1400 0x60>;
- interrupts = <17>;
- interrupt-parent = <&PIC>;
- };
-
-
diff --git a/dts/Bindings/media/cdns,csi2rx.txt b/dts/Bindings/media/cdns,csi2rx.txt
new file mode 100644
index 0000000..6b02a06
--- /dev/null
+++ b/dts/Bindings/media/cdns,csi2rx.txt
@@ -0,0 +1,100 @@
+Cadence MIPI-CSI2 RX controller
+===============================
+
+The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
+lanes in input, and 4 different pixel streams in output.
+
+Required properties:
+ - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
+ - reg: base address and size of the memory mapped region
+ - clocks: phandles to the clocks driving the controller
+ - clock-names: must contain:
+ * sys_clk: main clock
+ * p_clk: register bank clock
+ * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
+ implemented in hardware, between 0 and 3
+
+Optional properties:
+ - phys: phandle to the external D-PHY, phy-names must be provided
+ - phy-names: must contain "dphy", if the implementation uses an
+ external D-PHY
+
+Required subnodes:
+ - ports: A ports node with one port child node per device input and output
+ port, in accordance with the video interface bindings defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ port nodes are numbered as follows:
+
+ Port Description
+ -----------------------------
+ 0 CSI-2 input
+ 1 Stream 0 output
+ 2 Stream 1 output
+ 3 Stream 2 output
+ 4 Stream 3 output
+
+ The stream output port nodes are optional if they are not
+ connected to anything at the hardware level or implemented
+ in the design.Since there is only one endpoint per port,
+ the endpoints are not numbered.
+
+
+Example:
+
+csi2rx: csi-bridge@0d060000 {
+ compatible = "cdns,csi2rx";
+ reg = <0x0d060000 0x1000>;
+ clocks = <&byteclock>, <&byteclock>
+ <&coreclock>, <&coreclock>,
+ <&coreclock>, <&coreclock>;
+ clock-names = "sys_clk", "p_clk",
+ "pixel_if0_clk", "pixel_if1_clk",
+ "pixel_if2_clk", "pixel_if3_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csi2rx_in_sensor: endpoint {
+ remote-endpoint = <&sensor_out_csi2rx>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csi2rx_out_grabber0: endpoint {
+ remote-endpoint = <&grabber0_in_csi2rx>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ csi2rx_out_grabber1: endpoint {
+ remote-endpoint = <&grabber1_in_csi2rx>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ csi2rx_out_grabber2: endpoint {
+ remote-endpoint = <&grabber2_in_csi2rx>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ csi2rx_out_grabber3: endpoint {
+ remote-endpoint = <&grabber3_in_csi2rx>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/media/cdns,csi2tx.txt b/dts/Bindings/media/cdns,csi2tx.txt
new file mode 100644
index 0000000..459c6e3
--- /dev/null
+++ b/dts/Bindings/media/cdns,csi2tx.txt
@@ -0,0 +1,98 @@
+Cadence MIPI-CSI2 TX controller
+===============================
+
+The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
+4 CSI lanes in output, and up to 4 different pixel streams in input.
+
+Required properties:
+ - compatible: must be set to "cdns,csi2tx"
+ - reg: base address and size of the memory mapped region
+ - clocks: phandles to the clocks driving the controller
+ - clock-names: must contain:
+ * esc_clk: escape mode clock
+ * p_clk: register bank clock
+ * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
+ implemented in hardware, between 0 and 3
+
+Optional properties
+ - phys: phandle to the D-PHY. If it is set, phy-names need to be set
+ - phy-names: must contain "dphy"
+
+Required subnodes:
+ - ports: A ports node with one port child node per device input and output
+ port, in accordance with the video interface bindings defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ port nodes are numbered as follows.
+
+ Port Description
+ -----------------------------
+ 0 CSI-2 output
+ 1 Stream 0 input
+ 2 Stream 1 input
+ 3 Stream 2 input
+ 4 Stream 3 input
+
+ The stream input port nodes are optional if they are not
+ connected to anything at the hardware level or implemented
+ in the design. Since there is only one endpoint per port,
+ the endpoints are not numbered.
+
+Example:
+
+csi2tx: csi-bridge@0d0e1000 {
+ compatible = "cdns,csi2tx";
+ reg = <0x0d0e1000 0x1000>;
+ clocks = <&byteclock>, <&byteclock>,
+ <&coreclock>, <&coreclock>,
+ <&coreclock>, <&coreclock>;
+ clock-names = "p_clk", "esc_clk",
+ "pixel_if0_clk", "pixel_if1_clk",
+ "pixel_if2_clk", "pixel_if3_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csi2tx_out: endpoint {
+ remote-endpoint = <&remote_in>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csi2tx_in_stream0: endpoint {
+ remote-endpoint = <&stream0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ csi2tx_in_stream1: endpoint {
+ remote-endpoint = <&stream1_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ csi2tx_in_stream2: endpoint {
+ remote-endpoint = <&stream2_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ csi2tx_in_stream3: endpoint {
+ remote-endpoint = <&stream3_out>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/media/i2c/ov7251.txt b/dts/Bindings/media/i2c/ov7251.txt
new file mode 100644
index 0000000..8281151
--- /dev/null
+++ b/dts/Bindings/media/i2c/ov7251.txt
@@ -0,0 +1,52 @@
+* Omnivision 1/7.5-Inch B&W VGA CMOS Digital Image Sensor
+
+The Omnivision OV7251 is a 1/7.5-Inch CMOS active pixel digital image sensor
+with an active array size of 640H x 480V. It is programmable through a serial
+I2C interface.
+
+Required Properties:
+- compatible: Value should be "ovti,ov7251".
+- clocks: Reference to the xclk clock.
+- clock-names: Should be "xclk".
+- clock-frequency: Frequency of the xclk clock.
+- enable-gpios: Chip enable GPIO. Polarity is GPIO_ACTIVE_HIGH. This corresponds
+ to the hardware pin XSHUTDOWN which is physically active low.
+- vdddo-supply: Chip digital IO regulator.
+- vdda-supply: Chip analog regulator.
+- vddd-supply: Chip digital core regulator.
+
+The device node shall contain one 'port' child node with a single 'endpoint'
+subnode for its digital output video port, in accordance with the video
+interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Example:
+
+ &i2c1 {
+ ...
+
+ ov7251: camera-sensor@60 {
+ compatible = "ovti,ov7251";
+ reg = <0x60>;
+
+ enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&camera_bw_default>;
+
+ clocks = <&clks 200>;
+ clock-names = "xclk";
+ clock-frequency = <24000000>;
+
+ vdddo-supply = <&camera_dovdd_1v8>;
+ vdda-supply = <&camera_avdd_2v8>;
+ vddd-supply = <&camera_dvdd_1v2>;
+
+ port {
+ ov7251_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0>;
+ remote-endpoint = <&csi0_ep>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/media/i2c/ov772x.txt b/dts/Bindings/media/i2c/ov772x.txt
new file mode 100644
index 0000000..0b3ede5
--- /dev/null
+++ b/dts/Bindings/media/i2c/ov772x.txt
@@ -0,0 +1,40 @@
+* Omnivision OV7720/OV7725 CMOS sensor
+
+The Omnivision OV7720/OV7725 sensor supports multiple resolutions output,
+such as VGA, QVGA, and any size scaling down from CIF to 40x30. It also can
+support the YUV422, RGB565/555/444, GRB422 or raw RGB output formats.
+
+Required Properties:
+- compatible: shall be one of
+ "ovti,ov7720"
+ "ovti,ov7725"
+- clocks: reference to the xclk input clock.
+
+Optional Properties:
+- reset-gpios: reference to the GPIO connected to the RSTB pin which is
+ active low, if any.
+- powerdown-gpios: reference to the GPIO connected to the PWDN pin which is
+ active high, if any.
+
+The device node shall contain one 'port' child node with one child 'endpoint'
+subnode for its digital output video port, in accordance with the video
+interface bindings defined in Documentation/devicetree/bindings/media/
+video-interfaces.txt.
+
+Example:
+
+&i2c0 {
+ ov772x: camera@21 {
+ compatible = "ovti,ov7725";
+ reg = <0x21>;
+ reset-gpios = <&axi_gpio_0 0 GPIO_ACTIVE_LOW>;
+ powerdown-gpios = <&axi_gpio_0 1 GPIO_ACTIVE_LOW>;
+ clocks = <&xclk>;
+
+ port {
+ ov772x_0: endpoint {
+ remote-endpoint = <&vcap1_in0>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/media/i2c/panasonic,amg88xx.txt b/dts/Bindings/media/i2c/panasonic,amg88xx.txt
new file mode 100644
index 0000000..4a3181a
--- /dev/null
+++ b/dts/Bindings/media/i2c/panasonic,amg88xx.txt
@@ -0,0 +1,19 @@
+* Panasonic AMG88xx
+
+The Panasonic family of AMG88xx Grid-Eye sensors allow recording
+8x8 10Hz video which consists of thermal datapoints
+
+Required Properties:
+ - compatible : Must be "panasonic,amg88xx"
+ - reg : i2c address of the device
+
+Example:
+
+ i2c0@1c22000 {
+ ...
+ amg88xx@69 {
+ compatible = "panasonic,amg88xx";
+ reg = <0x69>;
+ };
+ ...
+ };
diff --git a/dts/Bindings/media/rcar_vin.txt b/dts/Bindings/media/rcar_vin.txt
index 1ce7ff9..a19517e 100644
--- a/dts/Bindings/media/rcar_vin.txt
+++ b/dts/Bindings/media/rcar_vin.txt
@@ -2,20 +2,28 @@ Renesas R-Car Video Input driver (rcar_vin)
-------------------------------------------
The rcar_vin device provides video input capabilities for the Renesas R-Car
-family of devices. The current blocks are always slaves and suppot one input
-channel which can be either RGB, YUYV or BT656.
+family of devices.
+
+Each VIN instance has a single parallel input that supports RGB and YUV video,
+with both external synchronization and BT.656 synchronization for the latter.
+Depending on the instance the VIN input is connected to external SoC pins, or
+on Gen3 platforms to a CSI-2 receiver.
- compatible: Must be one or more of the following
- - "renesas,vin-r8a7795" for the R8A7795 device
- - "renesas,vin-r8a7794" for the R8A7794 device
- - "renesas,vin-r8a7793" for the R8A7793 device
- - "renesas,vin-r8a7792" for the R8A7792 device
- - "renesas,vin-r8a7791" for the R8A7791 device
- - "renesas,vin-r8a7790" for the R8A7790 device
- - "renesas,vin-r8a7779" for the R8A7779 device
+ - "renesas,vin-r8a7743" for the R8A7743 device
+ - "renesas,vin-r8a7745" for the R8A7745 device
- "renesas,vin-r8a7778" for the R8A7778 device
- - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 compatible device.
- - "renesas,rcar-gen3-vin" for a generic R-Car Gen3 compatible device.
+ - "renesas,vin-r8a7779" for the R8A7779 device
+ - "renesas,vin-r8a7790" for the R8A7790 device
+ - "renesas,vin-r8a7791" for the R8A7791 device
+ - "renesas,vin-r8a7792" for the R8A7792 device
+ - "renesas,vin-r8a7793" for the R8A7793 device
+ - "renesas,vin-r8a7794" for the R8A7794 device
+ - "renesas,vin-r8a7795" for the R8A7795 device
+ - "renesas,vin-r8a7796" for the R8A7796 device
+ - "renesas,vin-r8a77970" for the R8A77970 device
+ - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible
+ device.
When compatible with the generic version nodes must list the
SoC-specific version corresponding to the platform first
@@ -28,21 +36,38 @@ channel which can be either RGB, YUYV or BT656.
Additionally, an alias named vinX will need to be created to specify
which video input device this is.
-The per-board settings:
+The per-board settings Gen2 platforms:
- port sub-node describing a single endpoint connected to the vin
as described in video-interfaces.txt[1]. Only the first one will
be considered as each vin interface has one input port.
- These settings are used to work out video input format and widths
- into the system.
+The per-board settings Gen3 platforms:
+Gen3 platforms can support both a single connected parallel input source
+from external SoC pins (port0) and/or multiple parallel input sources
+from local SoC CSI-2 receivers (port1) depending on SoC.
-Device node example
--------------------
+- renesas,id - ID number of the VIN, VINx in the documentation.
+- ports
+ - port 0 - sub-node describing a single endpoint connected to the VIN
+ from external SoC pins described in video-interfaces.txt[1].
+ Describing more then one endpoint in port 0 is invalid. Only VIN
+ instances that are connected to external pins should have port 0.
+ - port 1 - sub-nodes describing one or more endpoints connected to
+ the VIN from local SoC CSI-2 receivers. The endpoint numbers must
+ use the following schema.
- aliases {
- vin0 = &vin0;
- };
+ - Endpoint 0 - sub-node describing the endpoint connected to CSI20
+ - Endpoint 1 - sub-node describing the endpoint connected to CSI21
+ - Endpoint 2 - sub-node describing the endpoint connected to CSI40
+ - Endpoint 3 - sub-node describing the endpoint connected to CSI41
+
+Device node example for Gen2 platforms
+--------------------------------------
+
+ aliases {
+ vin0 = &vin0;
+ };
vin0: vin@e6ef0000 {
compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
@@ -52,8 +77,8 @@ Device node example
status = "disabled";
};
-Board setup example (vin1 composite video input)
-------------------------------------------------
+Board setup example for Gen2 platforms (vin1 composite video input)
+-------------------------------------------------------------------
&i2c2 {
status = "okay";
@@ -92,6 +117,77 @@ Board setup example (vin1 composite video input)
};
};
+Device node example for Gen3 platforms
+--------------------------------------
+
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a7795";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ renesas,id = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi20: endpoint@0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin0>;
+ };
+ vin0csi21: endpoint@1 {
+ reg = <1>;
+ remote-endpoint= <&csi21vin0>;
+ };
+ vin0csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
+ };
+ csi20: csi2@fea80000 {
+ compatible = "renesas,r8a7795-csi2";
+ reg = <0 0xfea80000 0 0x10000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 714>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ csi20_in: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1>;
+ remote-endpoint = <&adv7482_txb>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi20vin0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi20>;
+ };
+ };
+ };
+ };
[1] video-interfaces.txt common video media interface
diff --git a/dts/Bindings/media/renesas,ceu.txt b/dts/Bindings/media/renesas,ceu.txt
index 3fc66df..8a7a616 100644
--- a/dts/Bindings/media/renesas,ceu.txt
+++ b/dts/Bindings/media/renesas,ceu.txt
@@ -2,14 +2,15 @@ Renesas Capture Engine Unit (CEU)
----------------------------------------------
The Capture Engine Unit is the image capture interface found in the Renesas
-SH Mobile and RZ SoCs.
+SH Mobile, R-Mobile and RZ SoCs.
The interface supports a single parallel input with data bus width of 8 or 16
bits.
Required properties:
-- compatible: Shall be "renesas,r7s72100-ceu" for CEU units found in RZ/A1H
- and RZ/A1M SoCs.
+- compatible: Shall be one of the following values:
+ "renesas,r7s72100-ceu" for CEU units found in RZ/A1H and RZ/A1M SoCs
+ "renesas,r8a7740-ceu" for CEU units found in R-Mobile A1 R8A7740 SoCs
- reg: Registers address base and size.
- interrupts: The interrupt specifier.
diff --git a/dts/Bindings/media/renesas,rcar-csi2.txt b/dts/Bindings/media/renesas,rcar-csi2.txt
new file mode 100644
index 0000000..2d385b6
--- /dev/null
+++ b/dts/Bindings/media/renesas,rcar-csi2.txt
@@ -0,0 +1,101 @@
+Renesas R-Car MIPI CSI-2
+------------------------
+
+The R-Car CSI-2 receiver device provides MIPI CSI-2 capabilities for the
+Renesas R-Car family of devices. It is used in conjunction with the
+R-Car VIN module, which provides the video capture capabilities.
+
+Mandatory properties
+--------------------
+ - compatible: Must be one or more of the following
+ - "renesas,r8a7795-csi2" for the R8A7795 device.
+ - "renesas,r8a7796-csi2" for the R8A7796 device.
+ - "renesas,r8a77965-csi2" for the R8A77965 device.
+ - "renesas,r8a77970-csi2" for the R8A77970 device.
+
+ - reg: the register base and size for the device registers
+ - interrupts: the interrupt for the device
+ - clocks: reference to the parent clock
+
+The device node shall contain two 'port' child nodes according to the
+bindings defined in Documentation/devicetree/bindings/media/
+video-interfaces.txt. port@0 shall connect to the CSI-2 source. port@1
+shall connect to all the R-Car VIN modules that have a hardware
+connection to the CSI-2 receiver.
+
+- port@0- Video source (mandatory)
+ - endpoint@0 - sub-node describing the endpoint that is the video source
+
+- port@1 - VIN instances (optional)
+ - One endpoint sub-node for every R-Car VIN instance which is connected
+ to the R-Car CSI-2 receiver.
+
+Example:
+
+ csi20: csi2@fea80000 {
+ compatible = "renesas,r8a7796-csi2";
+ reg = <0 0xfea80000 0 0x10000>;
+ interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 714>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+
+ csi20_in: endpoint@0 {
+ reg = <0>;
+ clock-lanes = <0>;
+ data-lanes = <1>;
+ remote-endpoint = <&adv7482_txb>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi20vin0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi20>;
+ };
+ csi20vin1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi20>;
+ };
+ csi20vin2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi20>;
+ };
+ csi20vin3: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi20>;
+ };
+ csi20vin4: endpoint@4 {
+ reg = <4>;
+ remote-endpoint = <&vin4csi20>;
+ };
+ csi20vin5: endpoint@5 {
+ reg = <5>;
+ remote-endpoint = <&vin5csi20>;
+ };
+ csi20vin6: endpoint@6 {
+ reg = <6>;
+ remote-endpoint = <&vin6csi20>;
+ };
+ csi20vin7: endpoint@7 {
+ reg = <7>;
+ remote-endpoint = <&vin7csi20>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/media/stih407-c8sectpfe.txt b/dts/Bindings/media/stih407-c8sectpfe.txt
index c7888d6..880d4d7 100644
--- a/dts/Bindings/media/stih407-c8sectpfe.txt
+++ b/dts/Bindings/media/stih407-c8sectpfe.txt
@@ -28,7 +28,7 @@ See: Documentation/devicetree/bindings/clock/clock-bindings.txt
- pinctrl-names : a pinctrl state named tsin%d-serial or tsin%d-parallel (where %d is tsin-num)
must be defined for each tsin child node.
- pinctrl-0 : phandle referencing pin configuration for this tsin configuration
-See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
Required properties (tsin (child) node):
diff --git a/dts/Bindings/arm/tegra/nvidia,tegra20-mc.txt b/dts/Bindings/memory-controllers/nvidia,tegra20-mc.txt
index f9632ba..7d60a50 100644
--- a/dts/Bindings/arm/tegra/nvidia,tegra20-mc.txt
+++ b/dts/Bindings/memory-controllers/nvidia,tegra20-mc.txt
@@ -6,11 +6,21 @@ Required properties:
example below. Note that the MC registers are interleaved with the
GART registers, and hence must be represented as multiple ranges.
- interrupts : Should contain MC General interrupt.
+- #reset-cells : Should be 1. This cell represents memory client module ID.
+ The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>
+ or in the TRM documentation.
Example:
- memory-controller@7000f000 {
+ mc: memory-controller@7000f000 {
compatible = "nvidia,tegra20-mc";
reg = <0x7000f000 0x024
0x7000f03c 0x3c4>;
interrupts = <0 77 0x04>;
+ #reset-cells = <1>;
+ };
+
+ video-codec@6001a000 {
+ compatible = "nvidia,tegra20-vde";
+ ...
+ resets = <&mc TEGRA20_MC_RESET_VDE>;
};
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra30-mc.txt b/dts/Bindings/memory-controllers/nvidia,tegra30-mc.txt
index 14968b0..a878b59 100644
--- a/dts/Bindings/memory-controllers/nvidia,tegra30-mc.txt
+++ b/dts/Bindings/memory-controllers/nvidia,tegra30-mc.txt
@@ -12,6 +12,9 @@ Required properties:
- clock-names: Must include the following entries:
- mc: the module's clock input
- interrupts: The interrupt outputs from the controller.
+- #reset-cells : Should be 1. This cell represents memory client module ID.
+ The assignments may be found in header file <dt-bindings/memory/tegra30-mc.h>
+ or in the TRM documentation.
Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210:
- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
@@ -72,12 +75,14 @@ Example SoC include file:
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
+ #reset-cells = <1>;
};
sdhci@700b0000 {
compatible = "nvidia,tegra124-sdhci";
...
iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
+ resets = <&mc TEGRA124_MC_RESET_SDMMC1>;
};
};
diff --git a/dts/Bindings/mfd/arizona.txt b/dts/Bindings/mfd/arizona.txt
index bdd0176..a014afb 100644
--- a/dts/Bindings/mfd/arizona.txt
+++ b/dts/Bindings/mfd/arizona.txt
@@ -50,7 +50,7 @@ Required properties:
Optional properties:
- - wlf,reset : GPIO specifier for the GPIO controlling /RESET
+ - reset-gpios : GPIO specifier for the GPIO controlling /RESET
- clocks: Should reference the clocks supplied on MCLK1 and MCLK2
- clock-names: Should contains two strings:
@@ -70,6 +70,10 @@ Optional properties:
Documentation/devicetree/bindings/regulator/regulator.txt
(wm5102, wm5110, wm8280, wm8997, wm8998, wm1814)
+Deprecated properties:
+
+ - wlf,reset : GPIO specifier for the GPIO controlling /RESET
+
Also see child specific device properties:
Regulator - ../regulator/arizona-regulator.txt
Extcon - ../extcon/extcon-arizona.txt
diff --git a/dts/Bindings/mfd/as3722.txt b/dts/Bindings/mfd/as3722.txt
index 0b2a609..5297b22 100644
--- a/dts/Bindings/mfd/as3722.txt
+++ b/dts/Bindings/mfd/as3722.txt
@@ -46,7 +46,7 @@ is required:
Following properties are require if pin control setting is required
at boot.
- pinctrl-names: A pinctrl state named "default" be defined, using the
- bindings in pinctrl/pinctrl-binding.txt.
+ bindings in pinctrl/pinctrl-bindings.txt.
- pinctrl[0...n]: Properties to contain the phandle that refer to
different nodes of pin control settings. These nodes represents
the pin control setting of state 0 to state n. Each of these
diff --git a/dts/Bindings/mfd/axp20x.txt b/dts/Bindings/mfd/axp20x.txt
index 9455503..d1762f3 100644
--- a/dts/Bindings/mfd/axp20x.txt
+++ b/dts/Bindings/mfd/axp20x.txt
@@ -43,7 +43,7 @@ Optional properties:
regulator to drive the OTG VBus, rather then
as an input pin which signals whether the
board is driving OTG VBus or not.
- (axp221 / axp223 / axp813 only)
+ (axp221 / axp223 / axp803/ axp813 only)
- x-powers,master-mode: Boolean (axp806 only). Set this when the PMIC is
wired for master mode. The default is slave mode.
@@ -132,6 +132,7 @@ FLDO2 : LDO : fldoin-supply : shared supply
LDO_IO0 : LDO : ips-supply : GPIO 0
LDO_IO1 : LDO : ips-supply : GPIO 1
RTC_LDO : LDO : ips-supply : always on
+DRIVEVBUS : Enable output : drivevbus-supply : external regulator
AXP806 regulators, type, and corresponding input supply names:
diff --git a/dts/Bindings/mfd/bd9571mwv.txt b/dts/Bindings/mfd/bd9571mwv.txt
index 9ab216a..25d1f69 100644
--- a/dts/Bindings/mfd/bd9571mwv.txt
+++ b/dts/Bindings/mfd/bd9571mwv.txt
@@ -25,6 +25,25 @@ Required properties:
Each child node is defined using the standard
binding for regulators.
+Optional properties:
+ - rohm,ddr-backup-power : Value to use for DDR-Backup Power (default 0).
+ This is a bitmask that specifies which DDR power
+ rails need to be kept powered when backup mode is
+ entered, for system suspend:
+ - bit 0: DDR0
+ - bit 1: DDR1
+ - bit 2: DDR0C
+ - bit 3: DDR1C
+ These bits match the KEEPON_DDR* bits in the
+ documentation for the "BKUP Mode Cnt" register.
+ - rohm,rstbmode-level: The RSTB signal is configured for level mode, to
+ accommodate a toggle power switch (the RSTBMODE pin is
+ strapped low).
+ - rohm,rstbmode-pulse: The RSTB signal is configured for pulse mode, to
+ accommodate a momentary power switch (the RSTBMODE pin
+ is strapped high).
+ The two properties above are mutually exclusive.
+
Example:
pmic: pmic@30 {
@@ -36,6 +55,8 @@ Example:
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
+ rohm,ddr-backup-power = <0xf>;
+ rohm,rstbmode-pulse;
regulators {
dvfs: dvfs {
diff --git a/dts/Bindings/mfd/da9063.txt b/dts/Bindings/mfd/da9063.txt
index 05b21bc..443e682 100644
--- a/dts/Bindings/mfd/da9063.txt
+++ b/dts/Bindings/mfd/da9063.txt
@@ -1,4 +1,4 @@
-* Dialog DA9063 Power Management Integrated Circuit (PMIC)
+* Dialog DA9063/DA9063L Power Management Integrated Circuit (PMIC)
DA9093 consists of a large and varied group of sub-devices (I2C Only):
@@ -6,14 +6,14 @@ Device Supply Names Description
------ ------------ -----------
da9063-regulator : : LDOs & BUCKs
da9063-onkey : : On Key
-da9063-rtc : : Real-Time Clock
+da9063-rtc : : Real-Time Clock (DA9063 only)
da9063-watchdog : : Watchdog
======
Required properties:
-- compatible : Should be "dlg,da9063"
+- compatible : Should be "dlg,da9063" or "dlg,da9063l"
- reg : Specifies the I2C slave address (this defaults to 0x58 but it can be
modified to match the chip's OTP settings).
- interrupt-parent : Specifies the reference to the interrupt controller for
@@ -23,8 +23,8 @@ Required properties:
Sub-nodes:
-- regulators : This node defines the settings for the LDOs and BUCKs. The
- DA9063 regulators are bound using their names listed below:
+- regulators : This node defines the settings for the LDOs and BUCKs.
+ The DA9063(L) regulators are bound using their names listed below:
bcore1 : BUCK CORE1
bcore2 : BUCK CORE2
@@ -32,16 +32,16 @@ Sub-nodes:
bmem : BUCK MEM
bio : BUCK IO
bperi : BUCK PERI
- ldo1 : LDO_1
- ldo2 : LDO_2
+ ldo1 : LDO_1 (DA9063 only)
+ ldo2 : LDO_2 (DA9063 only)
ldo3 : LDO_3
- ldo4 : LDO_4
- ldo5 : LDO_5
- ldo6 : LDO_6
+ ldo4 : LDO_4 (DA9063 only)
+ ldo5 : LDO_5 (DA9063 only)
+ ldo6 : LDO_6 (DA9063 only)
ldo7 : LDO_7
ldo8 : LDO_8
ldo9 : LDO_9
- ldo10 : LDO_10
+ ldo10 : LDO_10 (DA9063 only)
ldo11 : LDO_11
The component follows the standard regulator framework and the bindings
@@ -49,8 +49,9 @@ Sub-nodes:
Documentation/devicetree/bindings/regulator/regulator.txt
- rtc : This node defines settings for the Real-Time Clock associated with
- the DA9063. There are currently no entries in this binding, however
- compatible = "dlg,da9063-rtc" should be added if a node is created.
+ the DA9063 only. The RTC is not present in DA9063L. There are currently
+ no entries in this binding, however compatible = "dlg,da9063-rtc" should
+ be added if a node is created.
- onkey : This node defines the OnKey settings for controlling the key
functionality of the device. The node should contain the compatible property
@@ -65,8 +66,9 @@ Sub-nodes:
and KEY_SLEEP.
- watchdog : This node defines settings for the Watchdog timer associated
- with the DA9063. There are currently no entries in this binding, however
- compatible = "dlg,da9063-watchdog" should be added if a node is created.
+ with the DA9063 and DA9063L. There are currently no entries in this
+ binding, however compatible = "dlg,da9063-watchdog" should be added
+ if a node is created.
Example:
diff --git a/dts/Bindings/mfd/motorola-cpcap.txt b/dts/Bindings/mfd/motorola-cpcap.txt
index 15bc885..c639705 100644
--- a/dts/Bindings/mfd/motorola-cpcap.txt
+++ b/dts/Bindings/mfd/motorola-cpcap.txt
@@ -12,6 +12,30 @@ Required properties:
- spi-max-frequency : Typically set to 3000000
- spi-cs-high : SPI chip select direction
+Optional subnodes:
+
+The sub-functions of CPCAP get their own node with their own compatible values,
+which are described in the following files:
+
+- ../power/supply/cpcap-battery.txt
+- ../power/supply/cpcap-charger.txt
+- ../regulator/cpcap-regulator.txt
+- ../phy/phy-cpcap-usb.txt
+- ../input/cpcap-pwrbutton.txt
+- ../rtc/cpcap-rtc.txt
+- ../leds/leds-cpcap.txt
+- ../iio/adc/cpcap-adc.txt
+
+The only exception is the audio codec. Instead of a compatible value its
+node must be named "audio-codec".
+
+Required properties for the audio-codec subnode:
+
+- #sound-dai-cells = <1>;
+
+The audio-codec provides two DAIs. The first one is connected to the
+Stereo HiFi DAC and the second one is connected to the Voice DAC.
+
Example:
&mcspi1 {
@@ -26,6 +50,24 @@ Example:
#size-cells = <0>;
spi-max-frequency = <3000000>;
spi-cs-high;
+
+ audio-codec {
+ #sound-dai-cells = <1>;
+
+ /* HiFi */
+ port@0 {
+ endpoint {
+ remote-endpoint = <&cpu_dai1>;
+ };
+ };
+
+ /* Voice */
+ port@1 {
+ endpoint {
+ remote-endpoint = <&cpu_dai2>;
+ };
+ };
+ };
};
};
diff --git a/dts/Bindings/mfd/mt6397.txt b/dts/Bindings/mfd/mt6397.txt
index 522a3bb..0ebd08a 100644
--- a/dts/Bindings/mfd/mt6397.txt
+++ b/dts/Bindings/mfd/mt6397.txt
@@ -7,11 +7,12 @@ MT6397/MT6323 is a multifunction device with the following sub modules:
- GPIO
- Clock
- LED
+- Keys
It is interfaced to host controller using SPI interface by a proprietary hardware
called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap.
See the following for pwarp node definitions:
-Documentation/devicetree/bindings/soc/pwrap.txt
+Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
This document describes the binding for MFD device and its sub module.
@@ -40,6 +41,11 @@ Optional subnodes:
- compatible: "mediatek,mt6323-led"
see Documentation/devicetree/bindings/leds/leds-mt6323.txt
+- keys
+ Required properties:
+ - compatible: "mediatek,mt6397-keys" or "mediatek,mt6323-keys"
+ see Documentation/devicetree/bindings/input/mtk-pmic-keys.txt
+
Example:
pwrap: pwrap@1000f000 {
compatible = "mediatek,mt8135-pwrap";
diff --git a/dts/Bindings/mfd/qcom,spmi-pmic.txt b/dts/Bindings/mfd/qcom,spmi-pmic.txt
index 6ac06c1..1437062 100644
--- a/dts/Bindings/mfd/qcom,spmi-pmic.txt
+++ b/dts/Bindings/mfd/qcom,spmi-pmic.txt
@@ -29,6 +29,9 @@ Required properties:
"qcom,pm8916",
"qcom,pm8004",
"qcom,pm8909",
+ "qcom,pm8998",
+ "qcom,pmi8998",
+ "qcom,pm8005",
or generalized "qcom,spmi-pmic".
- reg: Specifies the SPMI USID slave address for this device.
For more information see:
diff --git a/dts/Bindings/mfd/stm32-timers.txt b/dts/Bindings/mfd/stm32-timers.txt
index 1db6e00..0e900b5 100644
--- a/dts/Bindings/mfd/stm32-timers.txt
+++ b/dts/Bindings/mfd/stm32-timers.txt
@@ -19,6 +19,11 @@ Required parameters:
Optional parameters:
- resets: Phandle to the parent reset controller.
See ../reset/st,stm32-rcc.txt
+- dmas: List of phandle to dma channels that can be used for
+ this timer instance. There may be up to 7 dma channels.
+- dma-names: List of dma names. Must match 'dmas' property. Valid
+ names are: "ch1", "ch2", "ch3", "ch4", "up", "trig",
+ "com".
Optional subnodes:
- pwm: See ../pwm/pwm-stm32.txt
@@ -44,3 +49,18 @@ Example:
reg = <0>;
};
};
+
+Example with all dmas:
+ timer@40010000 {
+ ...
+ dmas = <&dmamux1 11 0x400 0x0>,
+ <&dmamux1 12 0x400 0x0>,
+ <&dmamux1 13 0x400 0x0>,
+ <&dmamux1 14 0x400 0x0>,
+ <&dmamux1 15 0x400 0x0>,
+ <&dmamux1 16 0x400 0x0>,
+ <&dmamux1 17 0x400 0x0>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig", "com";
+ ...
+ child nodes...
+ };
diff --git a/dts/Bindings/mfd/sun6i-prcm.txt b/dts/Bindings/mfd/sun6i-prcm.txt
index dd2c065..daa091c 100644
--- a/dts/Bindings/mfd/sun6i-prcm.txt
+++ b/dts/Bindings/mfd/sun6i-prcm.txt
@@ -8,8 +8,8 @@ Required properties:
- reg: The PRCM registers range
The prcm node may contain several subdevices definitions:
- - see Documentation/devicetree/clk/sunxi.txt for clock devices
- - see Documentation/devicetree/reset/allwinner,sunxi-clock-reset.txt for reset
+ - see Documentation/devicetree/bindings/clock/sunxi.txt for clock devices
+ - see Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt for reset
controller devices
diff --git a/dts/Bindings/mips/lantiq/rcu.txt b/dts/Bindings/mips/lantiq/rcu.txt
index a086f1e..7f0822b 100644
--- a/dts/Bindings/mips/lantiq/rcu.txt
+++ b/dts/Bindings/mips/lantiq/rcu.txt
@@ -61,7 +61,6 @@ Example of the RCU bindings on a xRX200 SoC:
usb_phy0: usb2-phy@18 {
compatible = "lantiq,xrx200-usb2-phy";
reg = <0x18 4>, <0x38 4>;
- status = "disabled";
resets = <&reset1 4 4>, <&reset0 4 4>;
reset-names = "phy", "ctrl";
@@ -71,7 +70,6 @@ Example of the RCU bindings on a xRX200 SoC:
usb_phy1: usb2-phy@34 {
compatible = "lantiq,xrx200-usb2-phy";
reg = <0x34 4>, <0x3C 4>;
- status = "disabled";
resets = <&reset1 5 4>, <&reset0 4 4>;
reset-names = "phy", "ctrl";
diff --git a/dts/Bindings/mmc/amlogic,meson-gx.txt b/dts/Bindings/mmc/amlogic,meson-gx.txt
index 50bf611..13e7040 100644
--- a/dts/Bindings/mmc/amlogic,meson-gx.txt
+++ b/dts/Bindings/mmc/amlogic,meson-gx.txt
@@ -12,6 +12,7 @@ Required properties:
- "amlogic,meson-gxbb-mmc"
- "amlogic,meson-gxl-mmc"
- "amlogic,meson-gxm-mmc"
+ - "amlogic,meson-axg-mmc"
- clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
- clock-names: Should contain the following:
"core" - Main peripheral bus clock
@@ -19,6 +20,7 @@ Required properties:
"clkin1" - Other parent clock of internal mux
The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the
clock rate requested by the MMC core.
+- resets : phandle of the internal reset line
Example:
@@ -29,4 +31,5 @@ Example:
clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
pinctrl-0 = <&emmc_pins>;
+ resets = <&reset RESET_SD_EMMC_A>;
};
diff --git a/dts/Bindings/mmc/bluefield-dw-mshc.txt b/dts/Bindings/mmc/bluefield-dw-mshc.txt
new file mode 100644
index 0000000..b0f0999
--- /dev/null
+++ b/dts/Bindings/mmc/bluefield-dw-mshc.txt
@@ -0,0 +1,29 @@
+* Mellanox Bluefield SoC specific extensions to the Synopsys Designware
+ Mobile Storage Host Controller
+
+Read synopsys-dw-mshc.txt for more details
+
+The Synopsys designware mobile storage host controller is used to interface
+a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
+differences between the core Synopsys dw mshc controller properties described
+by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC
+specific extensions to the Synopsys Designware Mobile Storage Host Controller.
+
+Required Properties:
+
+* compatible: should be one of the following.
+ - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC
+ specific extensions.
+
+Example:
+
+ /* Mellanox Bluefield SoC MMC */
+ mmc@6008000 {
+ compatible = "mellanox,bluefield-dw-mshc";
+ reg = <0x6008000 0x400>;
+ interrupts = <32>;
+ fifo-depth = <0x100>;
+ clock-frequency = <24000000>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ };
diff --git a/dts/Bindings/mmc/exynos-dw-mshc.txt b/dts/Bindings/mmc/exynos-dw-mshc.txt
index a58c173..0419a63 100644
--- a/dts/Bindings/mmc/exynos-dw-mshc.txt
+++ b/dts/Bindings/mmc/exynos-dw-mshc.txt
@@ -62,7 +62,7 @@ Required properties for a slot (Deprecated - Recommend to use one slot per host)
rest of the gpios (depending on the bus-width property) are the data lines in
no particular order. The format of the gpio specifier depends on the gpio
controller.
-(Deprecated - Refer to Documentation/devicetree/binding/pinctrl/samsung-pinctrl.txt)
+(Deprecated - Refer to Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt)
Example:
diff --git a/dts/Bindings/mmc/jz4740.txt b/dts/Bindings/mmc/jz4740.txt
new file mode 100644
index 0000000..7cd8c43
--- /dev/null
+++ b/dts/Bindings/mmc/jz4740.txt
@@ -0,0 +1,38 @@
+* Ingenic JZ47xx MMC controllers
+
+This file documents the device tree properties used for the MMC controller in
+Ingenic JZ4740/JZ4780 SoCs. These are in addition to the core MMC properties
+described in mmc.txt.
+
+Required properties:
+- compatible: Should be one of the following:
+ - "ingenic,jz4740-mmc" for the JZ4740
+ - "ingenic,jz4780-mmc" for the JZ4780
+- reg: Should contain the MMC controller registers location and length.
+- interrupts: Should contain the interrupt specifier of the MMC controller.
+- clocks: Clock for the MMC controller.
+
+Optional properties:
+- dmas: List of DMA specifiers with the controller specific format
+ as described in the generic DMA client binding. A tx and rx
+ specifier is required.
+- dma-names: RX and TX DMA request names.
+ Should be "rx" and "tx", in that order.
+
+For additional details on DMA client bindings see ../dma/dma.txt.
+
+Example:
+
+mmc0: mmc@13450000 {
+ compatible = "ingenic,jz4780-mmc";
+ reg = <0x13450000 0x1000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <37>;
+
+ clocks = <&cgu JZ4780_CLK_MSC0>;
+ clock-names = "mmc";
+
+ dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>, <&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
+ dma-names = "rx", "tx";
+};
diff --git a/dts/Bindings/mmc/microchip,sdhci-pic32.txt b/dts/Bindings/mmc/microchip,sdhci-pic32.txt
index 3149297..f064528 100644
--- a/dts/Bindings/mmc/microchip,sdhci-pic32.txt
+++ b/dts/Bindings/mmc/microchip,sdhci-pic32.txt
@@ -12,7 +12,7 @@ Required properties:
See: Documentation/devicetree/bindings/clock/clock-bindings.txt
- pinctrl-names: A pinctrl state names "default" must be defined.
- pinctrl-0: Phandle referencing pin configuration of the SDHCI controller.
- See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+ See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
Example:
diff --git a/dts/Bindings/mmc/mmc.txt b/dts/Bindings/mmc/mmc.txt
index 467cd7b..f5a0923 100644
--- a/dts/Bindings/mmc/mmc.txt
+++ b/dts/Bindings/mmc/mmc.txt
@@ -19,6 +19,8 @@ Optional properties:
- wp-gpios: Specify GPIOs for write protection, see gpio binding
- cd-inverted: when present, polarity on the CD line is inverted. See the note
below for the case, when a GPIO is used for the CD line
+- cd-debounce-delay-ms: Set delay time before detecting card after card insert interrupt.
+ It's only valid when cd-gpios is present.
- wp-inverted: when present, polarity on the WP line is inverted. See the note
below for the case, when a GPIO is used for the WP line
- disable-wp: When set no physical WP line is present. This property should
@@ -56,6 +58,10 @@ Optional properties:
- fixed-emmc-driver-type: for non-removable eMMC, enforce this driver type.
The value <n> is the driver type as specified in the eMMC specification
(table 206 in spec version 5.1).
+- post-power-on-delay-ms : It was invented for MMC pwrseq-simple which could
+ be referred to mmc-pwrseq-simple.txt. But now it's reused as a tunable delay
+ waiting for I/O signalling and card power supply to be stable, regardless of
+ whether pwrseq-simple is used. Default to 10ms if no available.
*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
polarity properties, we have to fix the meaning of the "normal" and "inverted"
diff --git a/dts/Bindings/mmc/sdhci-omap.txt b/dts/Bindings/mmc/sdhci-omap.txt
index 51775a3..393848c 100644
--- a/dts/Bindings/mmc/sdhci-omap.txt
+++ b/dts/Bindings/mmc/sdhci-omap.txt
@@ -4,7 +4,14 @@ Refer to mmc.txt for standard MMC bindings.
Required properties:
- compatible: Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers
+ Should be "ti,k2g-sdhci" for K2G
- ti,hwmods: Must be "mmc<n>", <n> is controller instance starting 1
+ (Not required for K2G).
+- pinctrl-names: Should be subset of "default", "hs", "sdr12", "sdr25", "sdr50",
+ "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104",
+ "ddr_1_8v-rev11", "ddr_1_8v" or "ddr_3_3v", "hs200_1_8v-rev11",
+ "hs200_1_8v",
+- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
Example:
mmc1: mmc@4809c000 {
diff --git a/dts/Bindings/mmc/sdhci-st.txt b/dts/Bindings/mmc/sdhci-st.txt
index 6b3d40c..ccf82b4 100644
--- a/dts/Bindings/mmc/sdhci-st.txt
+++ b/dts/Bindings/mmc/sdhci-st.txt
@@ -20,7 +20,7 @@ Required properties:
- pinctrl-names: A pinctrl state names "default" must be defined.
- pinctrl-0: Phandle referencing pin configuration of the sd/emmc controller.
- See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+ See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
- reg: This must provide the host controller base address and it can also
contain the FlashSS Top register for TX/RX delay used by the driver
diff --git a/dts/Bindings/mmc/tmio_mmc.txt b/dts/Bindings/mmc/tmio_mmc.txt
index 2d5287e..839f469 100644
--- a/dts/Bindings/mmc/tmio_mmc.txt
+++ b/dts/Bindings/mmc/tmio_mmc.txt
@@ -26,6 +26,8 @@ Required properties:
"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
+ "renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC
+ "renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
"renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
"renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
"renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller
@@ -67,7 +69,6 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
max-frequency = <195000000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 314>;
- status = "disabled";
};
sdhi1: sd@ee120000 {
@@ -81,7 +82,6 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
max-frequency = <195000000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 313>;
- status = "disabled";
};
sdhi2: sd@ee140000 {
@@ -95,7 +95,6 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
max-frequency = <97500000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 312>;
- status = "disabled";
};
sdhi3: sd@ee160000 {
@@ -109,5 +108,4 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
max-frequency = <97500000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 311>;
- status = "disabled";
};
diff --git a/dts/Bindings/mtd/gpmi-nand.txt b/dts/Bindings/mtd/gpmi-nand.txt
index b289ef3..3935883 100644
--- a/dts/Bindings/mtd/gpmi-nand.txt
+++ b/dts/Bindings/mtd/gpmi-nand.txt
@@ -47,6 +47,11 @@ Optional properties:
partitions written from Linux with this feature
turned on may not be accessible by the BootROM
code.
+ - nand-ecc-strength: integer representing the number of bits to correct
+ per ECC step. Needs to be a multiple of 2.
+ - nand-ecc-step-size: integer representing the number of data bytes
+ that are covered by a single ECC step. The driver
+ supports 512 and 1024.
The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
diff --git a/dts/Bindings/powerpc/4xx/ndfc.txt b/dts/Bindings/mtd/ibm,ndfc.txt
index 869f0b5..869f0b5 100644
--- a/dts/Bindings/powerpc/4xx/ndfc.txt
+++ b/dts/Bindings/mtd/ibm,ndfc.txt
diff --git a/dts/Bindings/mtd/mtk-nand.txt b/dts/Bindings/mtd/mtk-nand.txt
index 1c88526..4d3ec5e 100644
--- a/dts/Bindings/mtd/mtk-nand.txt
+++ b/dts/Bindings/mtd/mtk-nand.txt
@@ -20,7 +20,6 @@ Required NFI properties:
- interrupts: Interrupts of NFI.
- clocks: NFI required clocks.
- clock-names: NFI clocks internal name.
-- status: Disabled default. Then set "okay" by platform.
- ecc-engine: Required ECC Engine node.
- #address-cells: NAND chip index, should be 1.
- #size-cells: Should be 0.
@@ -34,7 +33,6 @@ Example:
clocks = <&pericfg CLK_PERI_NFI>,
<&pericfg CLK_PERI_NFI_PAD>;
clock-names = "nfi_clk", "pad_clk";
- status = "disabled";
ecc-engine = <&bch>;
#address-cells = <1>;
#size-cells = <0>;
@@ -50,14 +48,19 @@ Optional:
- nand-on-flash-bbt: Store BBT on NAND Flash.
- nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
- nand-ecc-step-size: Number of data bytes covered by a single ECC step.
- valid values: 512 and 1024.
+ valid values:
+ 512 and 1024 on mt2701 and mt2712.
+ 512 only on mt7622.
1024 is recommended for large page NANDs.
- nand-ecc-strength: Number of bits to correct per ECC step.
- The valid values that the controller supports are: 4, 6,
- 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
- 48, 52, 56, 60.
+ The valid values that each controller supports:
+ mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
+ 32, 36, 40, 44, 48, 52, 56, 60.
+ mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
+ 32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
+ mt7622: 4, 6, 8, 10, 12, 14, 16.
The strength should be calculated as follows:
- E = (S - F) * 8 / 14
+ E = (S - F) * 8 / B
S = O / (P / Q)
E : nand-ecc-strength.
S : spare size per sector.
@@ -66,6 +69,15 @@ Optional:
O : oob size.
P : page size.
Q : nand-ecc-step-size.
+ B : number of parity bits needed to correct
+ 1 bitflip.
+ According to MTK NAND controller design,
+ this number depends on max ecc step size
+ that MTK NAND controller supports.
+ If max ecc step size supported is 1024,
+ then it should be always 14. And if max
+ ecc step size is 512, then it should be
+ always 13.
If the result does not match any one of the listed
choices above, please select the smaller valid value from
the list.
@@ -152,7 +164,6 @@ Required BCH properties:
- interrupts: Interrupts of ECC.
- clocks: ECC required clocks.
- clock-names: ECC clocks internal name.
-- status: Disabled default. Then set "okay" by platform.
Example:
@@ -162,5 +173,4 @@ Example:
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_NFI_ECC>;
clock-names = "nfiecc_clk";
- status = "disabled";
};
diff --git a/dts/Bindings/mtd/partition.txt b/dts/Bindings/mtd/partition.txt
index 36f3b76..a8f3826 100644
--- a/dts/Bindings/mtd/partition.txt
+++ b/dts/Bindings/mtd/partition.txt
@@ -14,7 +14,7 @@ method is used for a given flash device. To describe the method there should be
a subnode of the flash device that is named 'partitions'. It must have a
'compatible' property, which is used to identify the method to use.
-We currently only document a binding for fixed layouts.
+Available bindings are listed in the "partitions" subdirectory.
Fixed Partitions
diff --git a/dts/Bindings/mtd/partitions/brcm,bcm947xx-cfe-partitions.txt b/dts/Bindings/mtd/partitions/brcm,bcm947xx-cfe-partitions.txt
new file mode 100644
index 0000000..1d61a02
--- /dev/null
+++ b/dts/Bindings/mtd/partitions/brcm,bcm947xx-cfe-partitions.txt
@@ -0,0 +1,42 @@
+Broadcom BCM47xx Partitions
+===========================
+
+Broadcom is one of hardware manufacturers providing SoCs (BCM47xx) used in
+home routers. Their BCM947xx boards using CFE bootloader have several partitions
+without any on-flash partition table. On some devices their sizes and/or
+meanings can also vary so fixed partitioning can't be used.
+
+Discovering partitions on these devices is possible thanks to having a special
+header and/or magic signature at the beginning of each of them. They are also
+block aligned which is important for determinig a size.
+
+Most of partitions use ASCII text based magic for determining a type. More
+complex partitions (like TRX with its HDR0 magic) may include extra header
+containing some details, including a length.
+
+A list of supported partitions includes:
+1) Bootloader with Broadcom's CFE (Common Firmware Environment)
+2) NVRAM with configuration/calibration data
+3) Device manufacturer's data with some default values (e.g. SSIDs)
+4) TRX firmware container which can hold up to 4 subpartitions
+5) Backup TRX firmware used after failed upgrade
+
+As mentioned earlier, role of some partitions may depend on extra configuration.
+For example both: main firmware and backup firmware use the same TRX format with
+the same header. To distinguish currently used firmware a CFE's environment
+variable "bootpartition" is used.
+
+
+Devices using Broadcom partitions described above should should have flash node
+with a subnode named "partitions" using following properties:
+
+Required properties:
+- compatible : (required) must be "brcm,bcm947xx-cfe-partitions"
+
+Example:
+
+flash@0 {
+ partitions {
+ compatible = "brcm,bcm947xx-cfe-partitions";
+ };
+};
diff --git a/dts/Bindings/mtd/sunxi-nand.txt b/dts/Bindings/mtd/sunxi-nand.txt
index 0734f03..dcd5a5d 100644
--- a/dts/Bindings/mtd/sunxi-nand.txt
+++ b/dts/Bindings/mtd/sunxi-nand.txt
@@ -22,8 +22,6 @@ Optional properties:
- reset : phandle + reset specifier pair
- reset-names : must contain "ahb"
- allwinner,rb : shall contain the native Ready/Busy ids.
- or
-- rb-gpios : shall contain the gpios used as R/B pins.
- nand-ecc-mode : one of the supported ECC modes ("hw", "soft", "soft_bch" or
"none")
diff --git a/dts/Bindings/net/dsa/dsa.txt b/dts/Bindings/net/dsa/dsa.txt
index cfe8f64..3ceeb8d 100644
--- a/dts/Bindings/net/dsa/dsa.txt
+++ b/dts/Bindings/net/dsa/dsa.txt
@@ -82,8 +82,6 @@ linked into one DSA cluster.
switch0: switch0@0 {
compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
dsa,member = <0 0>;
@@ -135,8 +133,6 @@ linked into one DSA cluster.
switch1: switch1@0 {
compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
dsa,member = <0 1>;
@@ -204,8 +200,6 @@ linked into one DSA cluster.
switch2: switch2@0 {
compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
dsa,member = <0 2>;
diff --git a/dts/Bindings/net/dsa/ksz.txt b/dts/Bindings/net/dsa/ksz.txt
index fd23904..a700943 100644
--- a/dts/Bindings/net/dsa/ksz.txt
+++ b/dts/Bindings/net/dsa/ksz.txt
@@ -6,7 +6,7 @@ Required properties:
- compatible: For external switch chips, compatible string must be exactly one
of: "microchip,ksz9477"
-See Documentation/devicetree/bindings/dsa/dsa.txt for a list of additional
+See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
required and optional properties.
Examples:
diff --git a/dts/Bindings/net/dsa/mt7530.txt b/dts/Bindings/net/dsa/mt7530.txt
index a9bc27b..aa3527f 100644
--- a/dts/Bindings/net/dsa/mt7530.txt
+++ b/dts/Bindings/net/dsa/mt7530.txt
@@ -31,7 +31,7 @@ Required properties for the child nodes within ports container:
- phy-mode: String, must be either "trgmii" or "rgmii" for port labeled
"cpu".
-See Documentation/devicetree/bindings/dsa/dsa.txt for a list of additional
+See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
required, optional properties and how the integrated switch subnodes must
be specified.
diff --git a/dts/Bindings/net/dsa/qca8k.txt b/dts/Bindings/net/dsa/qca8k.txt
index 9c67ee4..bbcb255 100644
--- a/dts/Bindings/net/dsa/qca8k.txt
+++ b/dts/Bindings/net/dsa/qca8k.txt
@@ -2,7 +2,10 @@
Required properties:
-- compatible: should be "qca,qca8337"
+- compatible: should be one of:
+ "qca,qca8334"
+ "qca,qca8337"
+
- #size-cells: must be 0
- #address-cells: must be 1
@@ -14,6 +17,20 @@ port and PHY id, each subnode describing a port needs to have a valid phandle
referencing the internal PHY connected to it. The CPU port of this switch is
always port 0.
+A CPU port node has the following optional node:
+
+- fixed-link : Fixed-link subnode describing a link to a non-MDIO
+ managed entity. See
+ Documentation/devicetree/bindings/net/fixed-link.txt
+ for details.
+
+For QCA8K the 'fixed-link' sub-node supports only the following properties:
+
+- 'speed' (integer, mandatory), to indicate the link speed. Accepted
+ values are 10, 100 and 1000
+- 'full-duplex' (boolean, optional), to indicate that full duplex is
+ used. When absent, half duplex is assumed.
+
Example:
@@ -53,6 +70,10 @@ Example:
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
+ fixed-link {
+ speed = 1000;
+ full-duplex;
+ };
};
port@1 {
diff --git a/dts/Bindings/net/dwmac-sun8i.txt b/dts/Bindings/net/dwmac-sun8i.txt
index 3d6d5fa..cfe7243 100644
--- a/dts/Bindings/net/dwmac-sun8i.txt
+++ b/dts/Bindings/net/dwmac-sun8i.txt
@@ -7,6 +7,7 @@ Required properties:
- compatible: must be one of the following string:
"allwinner,sun8i-a83t-emac"
"allwinner,sun8i-h3-emac"
+ "allwinner,sun8i-r40-gmac"
"allwinner,sun8i-v3s-emac"
"allwinner,sun50i-a64-emac"
- reg: address and length of the register for the device.
@@ -20,18 +21,18 @@ Required properties:
- phy-handle: See ethernet.txt
- #address-cells: shall be 1
- #size-cells: shall be 0
-- syscon: A phandle to the syscon of the SoC with one of the following
- compatible string:
- - allwinner,sun8i-h3-system-controller
- - allwinner,sun8i-v3s-system-controller
- - allwinner,sun50i-a64-system-controller
- - allwinner,sun8i-a83t-system-controller
+- syscon: A phandle to the device containing the EMAC or GMAC clock register
Optional properties:
-- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
-- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
-Both delay properties need to be a multiple of 100. They control the delay for
-external PHY.
+- allwinner,tx-delay-ps: TX clock delay chain value in ps.
+ Range is 0-700. Default is 0.
+ Unavailable for allwinner,sun8i-r40-gmac
+- allwinner,rx-delay-ps: RX clock delay chain value in ps.
+ Range is 0-3100. Default is 0.
+ Range is 0-700 for allwinner,sun8i-r40-gmac
+Both delay properties need to be a multiple of 100. They control the
+clock delay for external RGMII PHY. They do not apply to the internal
+PHY or external non-RGMII PHYs.
Optional properties for the following compatibles:
- "allwinner,sun8i-h3-emac",
diff --git a/dts/Bindings/net/fsl-tsec-phy.txt b/dts/Bindings/net/fsl-tsec-phy.txt
index 79bf352..047bdf7 100644
--- a/dts/Bindings/net/fsl-tsec-phy.txt
+++ b/dts/Bindings/net/fsl-tsec-phy.txt
@@ -86,70 +86,4 @@ Example:
* Gianfar PTP clock nodes
-General Properties:
-
- - compatible Should be "fsl,etsec-ptp"
- - reg Offset and length of the register set for the device
- - interrupts There should be at least two interrupts. Some devices
- have as many as four PTP related interrupts.
-
-Clock Properties:
-
- - fsl,cksel Timer reference clock source.
- - fsl,tclk-period Timer reference clock period in nanoseconds.
- - fsl,tmr-prsc Prescaler, divides the output clock.
- - fsl,tmr-add Frequency compensation value.
- - fsl,tmr-fiper1 Fixed interval period pulse generator.
- - fsl,tmr-fiper2 Fixed interval period pulse generator.
- - fsl,max-adj Maximum frequency adjustment in parts per billion.
-
- These properties set the operational parameters for the PTP
- clock. You must choose these carefully for the clock to work right.
- Here is how to figure good values:
-
- TimerOsc = selected reference clock MHz
- tclk_period = desired clock period nanoseconds
- NominalFreq = 1000 / tclk_period MHz
- FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
- tmr_add = ceil(2^32 / FreqDivRatio)
- OutputClock = NominalFreq / tmr_prsc MHz
- PulseWidth = 1 / OutputClock microseconds
- FiperFreq1 = desired frequency in Hz
- FiperDiv1 = 1000000 * OutputClock / FiperFreq1
- tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
- max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
-
- The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
- driver expects that tmr_fiper1 will be correctly set to produce a 1
- Pulse Per Second (PPS) signal, since this will be offered to the PPS
- subsystem to synchronize the Linux clock.
-
- Reference clock source is determined by the value, which is holded
- in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
- value, which will be directly written in those bits, that is why,
- according to reference manual, the next clock sources can be used:
-
- <0> - external high precision timer reference clock (TSEC_TMR_CLK
- input is used for this purpose);
- <1> - eTSEC system clock;
- <2> - eTSEC1 transmit clock;
- <3> - RTC clock input.
-
- When this attribute is not used, eTSEC system clock will serve as
- IEEE 1588 timer reference clock.
-
-Example:
-
- ptp_clock@24e00 {
- compatible = "fsl,etsec-ptp";
- reg = <0x24E00 0xB0>;
- interrupts = <12 0x8 13 0x8>;
- interrupt-parent = < &ipic >;
- fsl,cksel = <1>;
- fsl,tclk-period = <10>;
- fsl,tmr-prsc = <100>;
- fsl,tmr-add = <0x999999A4>;
- fsl,tmr-fiper1 = <0x3B9AC9F6>;
- fsl,tmr-fiper2 = <0x00018696>;
- fsl,max-adj = <659999998>;
- };
+Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
diff --git a/dts/Bindings/powerpc/4xx/emac.txt b/dts/Bindings/net/ibm,emac.txt
index 44b842b..44b842b 100644
--- a/dts/Bindings/powerpc/4xx/emac.txt
+++ b/dts/Bindings/net/ibm,emac.txt
diff --git a/dts/Bindings/net/meson-dwmac.txt b/dts/Bindings/net/meson-dwmac.txt
index 61cada2..1321bb1 100644
--- a/dts/Bindings/net/meson-dwmac.txt
+++ b/dts/Bindings/net/meson-dwmac.txt
@@ -11,6 +11,7 @@ Required properties on all platforms:
- "amlogic,meson8b-dwmac"
- "amlogic,meson8m2-dwmac"
- "amlogic,meson-gxbb-dwmac"
+ - "amlogic,meson-axg-dwmac"
Additionally "snps,dwmac" and any applicable more
detailed version number described in net/stmmac.txt
should be used.
diff --git a/dts/Bindings/net/microchip,lan78xx.txt b/dts/Bindings/net/microchip,lan78xx.txt
new file mode 100644
index 0000000..76786a0
--- /dev/null
+++ b/dts/Bindings/net/microchip,lan78xx.txt
@@ -0,0 +1,54 @@
+Microchip LAN78xx Gigabit Ethernet controller
+
+The LAN78XX devices are usually configured by programming their OTP or with
+an external EEPROM, but some platforms (e.g. Raspberry Pi 3 B+) have neither.
+The Device Tree properties, if present, override the OTP and EEPROM.
+
+Required properties:
+- compatible: Should be one of "usb424,7800", "usb424,7801" or "usb424,7850".
+
+Optional properties:
+- local-mac-address: see ethernet.txt
+- mac-address: see ethernet.txt
+
+Optional properties of the embedded PHY:
+- microchip,led-modes: a 0..4 element vector, with each element configuring
+ the operating mode of an LED. Omitted LEDs are turned off. Allowed values
+ are defined in "include/dt-bindings/net/microchip-lan78xx.h".
+
+Example:
+
+/* Based on the configuration for a Raspberry Pi 3 B+ */
+&usb {
+ usb-port@1 {
+ compatible = "usb424,2514";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb-port@1 {
+ compatible = "usb424,2514";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet: ethernet@1 {
+ compatible = "usb424,7800";
+ reg = <1>;
+ local-mac-address = [ 00 11 22 33 44 55 ];
+
+ mdio {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ eth_phy: ethernet-phy@1 {
+ reg = <1>;
+ microchip,led-modes = <
+ LAN78XX_LINK_1000_ACTIVITY
+ LAN78XX_LINK_10_100_ACTIVITY
+ >;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/net/mscc-miim.txt b/dts/Bindings/net/mscc-miim.txt
new file mode 100644
index 0000000..7104679
--- /dev/null
+++ b/dts/Bindings/net/mscc-miim.txt
@@ -0,0 +1,26 @@
+Microsemi MII Management Controller (MIIM) / MDIO
+=================================================
+
+Properties:
+- compatible: must be "mscc,ocelot-miim"
+- reg: The base address of the MDIO bus controller register bank. Optionally, a
+ second register bank can be defined if there is an associated reset register
+ for internal PHYs
+- #address-cells: Must be <1>.
+- #size-cells: Must be <0>. MDIO addresses have no size component.
+- interrupts: interrupt specifier (refer to the interrupt binding)
+
+Typically an MDIO bus might have several children.
+
+Example:
+ mdio@107009c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,ocelot-miim";
+ reg = <0x107009c 0x36>, <0x10700f0 0x8>;
+ interrupts = <14>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
diff --git a/dts/Bindings/net/mscc-ocelot.txt b/dts/Bindings/net/mscc-ocelot.txt
new file mode 100644
index 0000000..0a84711
--- /dev/null
+++ b/dts/Bindings/net/mscc-ocelot.txt
@@ -0,0 +1,82 @@
+Microsemi Ocelot network Switch
+===============================
+
+The Microsemi Ocelot network switch can be found on Microsemi SoCs (VSC7513,
+VSC7514)
+
+Required properties:
+- compatible: Should be "mscc,vsc7514-switch"
+- reg: Must contain an (offset, length) pair of the register set for each
+ entry in reg-names.
+- reg-names: Must include the following entries:
+ - "sys"
+ - "rew"
+ - "qs"
+ - "hsio"
+ - "qsys"
+ - "ana"
+ - "portX" with X from 0 to the number of last port index available on that
+ switch
+- interrupts: Should contain the switch interrupts for frame extraction and
+ frame injection
+- interrupt-names: should contain the interrupt names: "xtr", "inj"
+- ethernet-ports: A container for child nodes representing switch ports.
+
+The ethernet-ports container has the following properties
+
+Required properties:
+
+- #address-cells: Must be 1
+- #size-cells: Must be 0
+
+Each port node must have the following mandatory properties:
+- reg: Describes the port address in the switch
+
+Port nodes may also contain the following optional standardised
+properties, described in binding documents:
+
+- phy-handle: Phandle to a PHY on an MDIO bus. See
+ Documentation/devicetree/bindings/net/ethernet.txt for details.
+
+Example:
+
+ switch@1010000 {
+ compatible = "mscc,vsc7514-switch";
+ reg = <0x1010000 0x10000>,
+ <0x1030000 0x10000>,
+ <0x1080000 0x100>,
+ <0x10d0000 0x10000>,
+ <0x11e0000 0x100>,
+ <0x11f0000 0x100>,
+ <0x1200000 0x100>,
+ <0x1210000 0x100>,
+ <0x1220000 0x100>,
+ <0x1230000 0x100>,
+ <0x1240000 0x100>,
+ <0x1250000 0x100>,
+ <0x1260000 0x100>,
+ <0x1270000 0x100>,
+ <0x1280000 0x100>,
+ <0x1800000 0x80000>,
+ <0x1880000 0x10000>;
+ reg-names = "sys", "rew", "qs", "hsio", "port0",
+ "port1", "port2", "port3", "port4", "port5",
+ "port6", "port7", "port8", "port9", "port10",
+ "qsys", "ana";
+ interrupts = <21 22>;
+ interrupt-names = "xtr", "inj";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port@0 {
+ reg = <0>;
+ phy-handle = <&phy0>;
+ };
+ port1: port@1 {
+ reg = <1>;
+ phy-handle = <&phy1>;
+ };
+ };
+ };
diff --git a/dts/Bindings/net/qualcomm-bluetooth.txt b/dts/Bindings/net/qualcomm-bluetooth.txt
new file mode 100644
index 0000000..0ea18a5
--- /dev/null
+++ b/dts/Bindings/net/qualcomm-bluetooth.txt
@@ -0,0 +1,30 @@
+Qualcomm Bluetooth Chips
+---------------------
+
+This documents the binding structure and common properties for serial
+attached Qualcomm devices.
+
+Serial attached Qualcomm devices shall be a child node of the host UART
+device the slave device is attached to.
+
+Required properties:
+ - compatible: should contain one of the following:
+ * "qcom,qca6174-bt"
+
+Optional properties:
+ - enable-gpios: gpio specifier used to enable chip
+ - clocks: clock provided to the controller (SUSCLK_32KHZ)
+
+Example:
+
+serial@7570000 {
+ label = "BT-UART";
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,qca6174-bt";
+
+ enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
+ clocks = <&divclk4>;
+ };
+};
diff --git a/dts/Bindings/net/renesas,ravb.txt b/dts/Bindings/net/renesas,ravb.txt
index 890526d..fac897d 100644
--- a/dts/Bindings/net/renesas,ravb.txt
+++ b/dts/Bindings/net/renesas,ravb.txt
@@ -21,6 +21,7 @@ Required properties:
- "renesas,etheravb-r8a77965" for the R8A77965 SoC.
- "renesas,etheravb-r8a77970" for the R8A77970 SoC.
- "renesas,etheravb-r8a77980" for the R8A77980 SoC.
+ - "renesas,etheravb-r8a77990" for the R8A77990 SoC.
- "renesas,etheravb-r8a77995" for the R8A77995 SoC.
- "renesas,etheravb-rcar-gen3" as a fallback for the above
R-Car Gen3 devices.
diff --git a/dts/Bindings/net/sff,sfp.txt b/dts/Bindings/net/sff,sfp.txt
index 929591d..8321399 100644
--- a/dts/Bindings/net/sff,sfp.txt
+++ b/dts/Bindings/net/sff,sfp.txt
@@ -7,11 +7,11 @@ Required properties:
"sff,sfp" for SFP modules
"sff,sff" for soldered down SFF modules
-Optional Properties:
-
- i2c-bus : phandle of an I2C bus controller for the SFP two wire serial
interface
+Optional Properties:
+
- mod-def0-gpios : GPIO phandle and a specifier of the MOD-DEF0 (AKA Mod_ABS)
module presence input gpio signal, active (module absent) high. Must
not be present for SFF modules
diff --git a/dts/Bindings/net/sh_eth.txt b/dts/Bindings/net/sh_eth.txt
index 5172799..82a4cf2c 100644
--- a/dts/Bindings/net/sh_eth.txt
+++ b/dts/Bindings/net/sh_eth.txt
@@ -14,6 +14,7 @@ Required properties:
"renesas,ether-r8a7791" if the device is a part of R8A7791 SoC.
"renesas,ether-r8a7793" if the device is a part of R8A7793 SoC.
"renesas,ether-r8a7794" if the device is a part of R8A7794 SoC.
+ "renesas,gether-r8a77980" if the device is a part of R8A77980 SoC.
"renesas,ether-r7s72100" if the device is a part of R7S72100 SoC.
"renesas,rcar-gen1-ether" for a generic R-Car Gen1 device.
"renesas,rcar-gen2-ether" for a generic R-Car Gen2 or RZ/G1
diff --git a/dts/Bindings/net/socionext,uniphier-ave4.txt b/dts/Bindings/net/socionext,uniphier-ave4.txt
index 96398cc..fc8f017 100644
--- a/dts/Bindings/net/socionext,uniphier-ave4.txt
+++ b/dts/Bindings/net/socionext,uniphier-ave4.txt
@@ -13,13 +13,25 @@ Required properties:
- reg: Address where registers are mapped and size of region.
- interrupts: Should contain the MAC interrupt.
- phy-mode: See ethernet.txt in the same directory. Allow to choose
- "rgmii", "rmii", or "mii" according to the PHY.
+ "rgmii", "rmii", "mii", or "internal" according to the PHY.
+ The acceptable mode is SoC-dependent.
- phy-handle: Should point to the external phy device.
See ethernet.txt file in the same directory.
- clocks: A phandle to the clock for the MAC.
+ For Pro4 SoC, that is "socionext,uniphier-pro4-ave4",
+ another MAC clock, GIO bus clock and PHY clock are also required.
+ - clock-names: Should contain
+ - "ether", "ether-gb", "gio", "ether-phy" for Pro4 SoC
+ - "ether" for others
+ - resets: A phandle to the reset control for the MAC. For Pro4 SoC,
+ GIO bus reset is also required.
+ - reset-names: Should contain
+ - "ether", "gio" for Pro4 SoC
+ - "ether" for others
+ - socionext,syscon-phy-mode: A phandle to syscon with one argument
+ that configures phy mode. The argument is the ID of MAC instance.
Optional properties:
- - resets: A phandle to the reset control for the MAC.
- local-mac-address: See ethernet.txt in the same directory.
Required subnode:
@@ -34,8 +46,11 @@ Example:
interrupts = <0 66 4>;
phy-mode = "rgmii";
phy-handle = <&ethphy>;
+ clock-names = "ether";
clocks = <&sys_clk 6>;
+ reset-names = "ether";
resets = <&sys_rst 6>;
+ socionext,syscon-phy-mode = <&soc_glue 0>;
local-mac-address = [00 00 00 00 00 00];
mdio {
diff --git a/dts/Bindings/net/stm32-dwmac.txt b/dts/Bindings/net/stm32-dwmac.txt
index 489dbcb..1341012 100644
--- a/dts/Bindings/net/stm32-dwmac.txt
+++ b/dts/Bindings/net/stm32-dwmac.txt
@@ -6,14 +6,28 @@ Please see stmmac.txt for the other unchanged properties.
The device node has following properties.
Required properties:
-- compatible: Should be "st,stm32-dwmac" to select glue, and
+- compatible: For MCU family should be "st,stm32-dwmac" to select glue, and
"snps,dwmac-3.50a" to select IP version.
+ For MPU family should be "st,stm32mp1-dwmac" to select
+ glue, and "snps,dwmac-4.20a" to select IP version.
- clocks: Must contain a phandle for each entry in clock-names.
- clock-names: Should be "stmmaceth" for the host clock.
Should be "mac-clk-tx" for the MAC TX clock.
Should be "mac-clk-rx" for the MAC RX clock.
+ For MPU family need to add also "ethstp" for power mode clock and,
+ "syscfg-clk" for SYSCFG clock.
+- interrupt-names: Should contain a list of interrupt names corresponding to
+ the interrupts in the interrupts property, if available.
+ Should be "macirq" for the main MAC IRQ
+ Should be "eth_wake_irq" for the IT which wake up system
- st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
- encompases the glue register, and the offset of the control register.
+ encompases the glue register, and the offset of the control register.
+
+Optional properties:
+- clock-names: For MPU family "mac-clk-ck" for PHY without quartz
+- st,int-phyclk (boolean) : valid only where PHY do not have quartz and need to be clock
+ by RCC
+
Example:
ethernet@40028000 {
diff --git a/dts/Bindings/net/wireless/qcom,ath10k.txt b/dts/Bindings/net/wireless/qcom,ath10k.txt
index 3d2a031..7fd4e8c 100644
--- a/dts/Bindings/net/wireless/qcom,ath10k.txt
+++ b/dts/Bindings/net/wireless/qcom,ath10k.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: Should be one of the following:
* "qcom,ath10k"
* "qcom,ipq4019-wifi"
+ * "qcom,wcn3990-wifi"
PCI based devices uses compatible string "qcom,ath10k" and takes calibration
data along with board specific data via "qcom,ath10k-calibration-data".
@@ -18,8 +19,12 @@ In general, entry "qcom,ath10k-pre-calibration-data" and
"qcom,ath10k-calibration-data" conflict with each other and only one
can be provided per device.
+SNOC based devices (i.e. wcn3990) uses compatible string "qcom,wcn3990-wifi".
+
Optional properties:
- reg: Address and length of the register set for the device.
+- reg-names: Must include the list of following reg names,
+ "membase"
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reseti.txt for details.
- reset-names: Must include the list of following reset names,
@@ -49,6 +54,8 @@ Optional properties:
hw versions.
- qcom,ath10k-pre-calibration-data : pre calibration data as an array,
the length can vary between hw versions.
+- <supply-name>-supply: handle to the regulator device tree node
+ optional "supply-name" is "vdd-0.8-cx-mx".
Example (to supply the calibration data alone):
@@ -119,3 +126,27 @@ wifi0: wifi@a000000 {
qcom,msi_base = <0x40>;
qcom,ath10k-pre-calibration-data = [ 01 02 03 ... ];
};
+
+Example (to supply wcn3990 SoC wifi block details):
+
+wifi@18000000 {
+ compatible = "qcom,wcn3990-wifi";
+ reg = <0x18800000 0x800000>;
+ reg-names = "membase";
+ clocks = <&clock_gcc clk_aggre2_noc_clk>;
+ clock-names = "smmu_aggre2_noc_clk"
+ interrupts =
+ <0 130 0 /* CE0 */ >,
+ <0 131 0 /* CE1 */ >,
+ <0 132 0 /* CE2 */ >,
+ <0 133 0 /* CE3 */ >,
+ <0 134 0 /* CE4 */ >,
+ <0 135 0 /* CE5 */ >,
+ <0 136 0 /* CE6 */ >,
+ <0 137 0 /* CE7 */ >,
+ <0 138 0 /* CE8 */ >,
+ <0 139 0 /* CE9 */ >,
+ <0 140 0 /* CE10 */ >,
+ <0 141 0 /* CE11 */ >;
+ vdd-0.8-cx-mx-supply = <&pm8998_l5>;
+};
diff --git a/dts/Bindings/nvmem/allwinner,sunxi-sid.txt b/dts/Bindings/nvmem/allwinner,sunxi-sid.txt
index d695437..e319fe5 100644
--- a/dts/Bindings/nvmem/allwinner,sunxi-sid.txt
+++ b/dts/Bindings/nvmem/allwinner,sunxi-sid.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: Should be one of the following:
"allwinner,sun4i-a10-sid"
"allwinner,sun7i-a20-sid"
+ "allwinner,sun8i-a83t-sid"
"allwinner,sun8i-h3-sid"
"allwinner,sun50i-a64-sid"
diff --git a/dts/Bindings/nvmem/zii,rave-sp-eeprom.txt b/dts/Bindings/nvmem/zii,rave-sp-eeprom.txt
new file mode 100644
index 0000000..0df79d9
--- /dev/null
+++ b/dts/Bindings/nvmem/zii,rave-sp-eeprom.txt
@@ -0,0 +1,40 @@
+Zodiac Inflight Innovations RAVE EEPROM Bindings
+
+RAVE SP EEPROM device is a "MFD cell" device exposing physical EEPROM
+attached to RAVE Supervisory Processor. It is expected that its Device
+Tree node is specified as a child of the node corresponding to the
+parent RAVE SP device (as documented in
+Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)
+
+Required properties:
+
+- compatible: Should be "zii,rave-sp-eeprom"
+
+Optional properties:
+
+- zii,eeprom-name: Unique EEPROM identifier describing its function in the
+ system. Will be used as created NVMEM deivce's name.
+
+Data cells:
+
+Data cells are child nodes of eerpom node, bindings for which are
+documented in Documentation/devicetree/bindings/nvmem/nvmem.txt
+
+Example:
+
+ rave-sp {
+ compatible = "zii,rave-sp-rdu1";
+ current-speed = <38400>;
+
+ eeprom@a4 {
+ compatible = "zii,rave-sp-eeprom";
+ reg = <0xa4 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ zii,eeprom-name = "main-eeprom";
+
+ wdt_timeout: wdt-timeout@81 {
+ reg = <0x81 2>;
+ };
+ };
+ }
diff --git a/dts/Bindings/opp/kryo-cpufreq.txt b/dts/Bindings/opp/kryo-cpufreq.txt
new file mode 100644
index 0000000..c2127b9
--- /dev/null
+++ b/dts/Bindings/opp/kryo-cpufreq.txt
@@ -0,0 +1,680 @@
+Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings
+===================================
+
+In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
+that have KRYO processors, the CPU ferequencies subset and voltage value
+of each OPP varies based on the silicon variant in use.
+Qualcomm Technologies, Inc. Process Voltage Scaling Tables
+defines the voltage and frequency value based on the msm-id in SMEM
+and speedbin blown in the efuse combination.
+The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
+to provide the OPP framework with required information (existing HW bitmap).
+This is used to determine the voltage and frequency value for each OPP of
+operating-points-v2 table when it is parsed by the OPP framework.
+
+Required properties:
+--------------------
+In 'cpus' nodes:
+- operating-points-v2: Phandle to the operating-points-v2 table to use.
+
+In 'operating-points-v2' table:
+- compatible: Should be
+ - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
+- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
+ efuse registers that has information about the
+ speedbin that is used to select the right frequency/voltage
+ value pair.
+ Please refer the for nvmem-cells
+ bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
+ and also examples below.
+
+In every OPP node:
+- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
+ Bitmap:
+ 0: MSM8996 V3, speedbin 0
+ 1: MSM8996 V3, speedbin 1
+ 2: MSM8996 V3, speedbin 2
+ 3: unused
+ 4: MSM8996 SG, speedbin 0
+ 5: MSM8996 SG, speedbin 1
+ 6: MSM8996 SG, speedbin 2
+ 7-31: unused
+
+Example 1:
+---------
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ clocks = <&kryocc 0>;
+ cpu-supply = <&pm8994_s11_saw>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ clocks = <&kryocc 0>;
+ cpu-supply = <&pm8994_s11_saw>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU2: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ clocks = <&kryocc 1>;
+ cpu-supply = <&pm8994_s11_saw>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU3: cpu@101 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ clocks = <&kryocc 1>;
+ cpu-supply = <&pm8994_s11_saw>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_1>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU2>;
+ };
+
+ core1 {
+ cpu = <&CPU3>;
+ };
+ };
+ };
+ };
+
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+ opp-shared;
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-422400000 {
+ opp-hz = /bits/ 64 <422400000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-460800000 {
+ opp-hz = /bits/ 64 <460800000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-537600000 {
+ opp-hz = /bits/ 64 <537600000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-556800000 {
+ opp-hz = /bits/ 64 <556800000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-614400000 {
+ opp-hz = /bits/ 64 <614400000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-691200000 {
+ opp-hz = /bits/ 64 <691200000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-768000000 {
+ opp-hz = /bits/ 64 <768000000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-844800000 {
+ opp-hz = /bits/ 64 <844800000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-979200000 {
+ opp-hz = /bits/ 64 <979200000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1132800000 {
+ opp-hz = /bits/ 64 <1132800000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1209600000 {
+ opp-hz = /bits/ 64 <1209600000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1286400000 {
+ opp-hz = /bits/ 64 <1286400000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x5>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x72>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x5>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1440000000 {
+ opp-hz = /bits/ 64 <1440000000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1478400000 {
+ opp-hz = /bits/ 64 <1478400000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x4>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x71>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x20>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2188800000 {
+ opp-hz = /bits/ 64 <2188800000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x10>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+ opp-shared;
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-403200000 {
+ opp-hz = /bits/ 64 <403200000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-460800000 {
+ opp-hz = /bits/ 64 <460800000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-537600000 {
+ opp-hz = /bits/ 64 <537600000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-556800000 {
+ opp-hz = /bits/ 64 <556800000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-614400000 {
+ opp-hz = /bits/ 64 <614400000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-691200000 {
+ opp-hz = /bits/ 64 <691200000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-748800000 {
+ opp-hz = /bits/ 64 <748800000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-806400000 {
+ opp-hz = /bits/ 64 <806400000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-825600000 {
+ opp-hz = /bits/ 64 <825600000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-883200000 {
+ opp-hz = /bits/ 64 <883200000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-940800000 {
+ opp-hz = /bits/ 64 <940800000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-979200000 {
+ opp-hz = /bits/ 64 <979200000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1132800000 {
+ opp-hz = /bits/ 64 <1132800000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1209600000 {
+ opp-hz = /bits/ 64 <1209600000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1286400000 {
+ opp-hz = /bits/ 64 <1286400000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1440000000 {
+ opp-hz = /bits/ 64 <1440000000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1478400000 {
+ opp-hz = /bits/ 64 <1478400000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1555200000 {
+ opp-hz = /bits/ 64 <1555200000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1632000000 {
+ opp-hz = /bits/ 64 <1632000000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1670400000 {
+ opp-hz = /bits/ 64 <1670400000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1747200000 {
+ opp-hz = /bits/ 64 <1747200000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x6>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1824000000 {
+ opp-hz = /bits/ 64 <1824000000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x71>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x74>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1977600000 {
+ opp-hz = /bits/ 64 <1977600000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x30>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2054400000 {
+ opp-hz = /bits/ 64 <2054400000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x30>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2073600000 {
+ opp-hz = /bits/ 64 <2073600000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2150400000 {
+ opp-hz = /bits/ 64 <2150400000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x31>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2246400000 {
+ opp-hz = /bits/ 64 <2246400000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x10>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2342400000 {
+ opp-hz = /bits/ 64 <2342400000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x10>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
+....
+
+reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+....
+ smem_mem: smem-mem@86000000 {
+ reg = <0x0 0x86000000 0x0 0x200000>;
+ no-map;
+ };
+....
+};
+
+smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+};
+
+soc {
+....
+ qfprom: qfprom@74000 {
+ compatible = "qcom,qfprom";
+ reg = <0x00074000 0x8ff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ....
+ speedbin_efuse: speedbin@133 {
+ reg = <0x133 0x1>;
+ bits = <5 3>;
+ };
+ };
+};
diff --git a/dts/Bindings/opp/opp.txt b/dts/Bindings/opp/opp.txt
index 4e4f302..c396c4c 100644
--- a/dts/Bindings/opp/opp.txt
+++ b/dts/Bindings/opp/opp.txt
@@ -82,7 +82,10 @@ This defines voltage-current-frequency combinations along with other related
properties.
Required properties:
-- opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer.
+- opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer. This is a
+ required property for all device nodes but devices like power domains. The
+ power domain nodes must have another (implementation dependent) property which
+ uniquely identifies the OPP nodes.
Optional properties:
- opp-microvolt: voltage in micro Volts.
@@ -159,7 +162,7 @@ Optional properties:
- status: Marks the node enabled/disabled.
-- required-opp: This contains phandle to an OPP node in another device's OPP
+- required-opps: This contains phandle to an OPP node in another device's OPP
table. It may contain an array of phandles, where each phandle points to an
OPP of a different device. It should not contain multiple phandles to the OPP
nodes in the same OPP table. This specifies the minimum required OPP of the
diff --git a/dts/Bindings/pci/designware-pcie.txt b/dts/Bindings/pci/designware-pcie.txt
index 1da7ade..c124f9b 100644
--- a/dts/Bindings/pci/designware-pcie.txt
+++ b/dts/Bindings/pci/designware-pcie.txt
@@ -1,7 +1,9 @@
* Synopsys DesignWare PCIe interface
Required properties:
-- compatible: should contain "snps,dw-pcie" to identify the core.
+- compatible:
+ "snps,dw-pcie" for RC mode;
+ "snps,dw-pcie-ep" for EP mode;
- reg: Should contain the configuration address space.
- reg-names: Must be "config" for the PCIe configuration space.
(The old way of getting the configuration address space from "ranges"
@@ -41,11 +43,11 @@ EP mode:
Example configuration:
- pcie: pcie@dffff000 {
+ pcie: pcie@dfc00000 {
compatible = "snps,dw-pcie";
- reg = <0xdffff000 0x1000>, /* Controller registers */
- <0xd0000000 0x2000>; /* PCI config space */
- reg-names = "ctrlreg", "config";
+ reg = <0xdfc00000 0x0001000>, /* IP registers */
+ <0xd0000000 0x0002000>; /* Configuration space */
+ reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -54,5 +56,15 @@ Example configuration:
interrupts = <25>, <24>;
#interrupt-cells = <1>;
num-lanes = <1>;
- num-viewport = <3>;
+ };
+or
+ pcie: pcie@dfc00000 {
+ compatible = "snps,dw-pcie-ep";
+ reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
+ <0xdfc01000 0x0001000>, /* IP registers 2 */
+ <0xd0000000 0x2000000>; /* Configuration space */
+ reg-names = "dbi", "dbi2", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <2>;
+ num-lanes = <1>;
};
diff --git a/dts/Bindings/pci/hisilicon-pcie.txt b/dts/Bindings/pci/hisilicon-pcie.txt
index 7bf9df0..0dcb87d 100644
--- a/dts/Bindings/pci/hisilicon-pcie.txt
+++ b/dts/Bindings/pci/hisilicon-pcie.txt
@@ -3,7 +3,7 @@ HiSilicon Hip05 and Hip06 PCIe host bridge DT description
HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and inherits
common properties defined in
-Documentation/devicetree/bindings/pci/designware-pci.txt.
+Documentation/devicetree/bindings/pci/designware-pcie.txt.
Additional properties are described here:
diff --git a/dts/Bindings/pci/kirin-pcie.txt b/dts/Bindings/pci/kirin-pcie.txt
index 6e217c6..6bbe438 100644
--- a/dts/Bindings/pci/kirin-pcie.txt
+++ b/dts/Bindings/pci/kirin-pcie.txt
@@ -3,7 +3,7 @@ HiSilicon Kirin SoCs PCIe host DT description
Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and
inherits common properties defined in
-Documentation/devicetree/bindings/pci/designware-pci.txt.
+Documentation/devicetree/bindings/pci/designware-pcie.txt.
Additional properties are described here:
diff --git a/dts/Bindings/pci/mobiveil-pcie.txt b/dts/Bindings/pci/mobiveil-pcie.txt
new file mode 100644
index 0000000..65038aa
--- /dev/null
+++ b/dts/Bindings/pci/mobiveil-pcie.txt
@@ -0,0 +1,73 @@
+* Mobiveil AXI PCIe Root Port Bridge DT description
+
+Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
+has up to 8 outbound and inbound windows for the address translation.
+
+Required properties:
+- #address-cells: Address representation for root ports, set to <3>
+- #size-cells: Size representation for root ports, set to <2>
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- compatible: Should contain "mbvl,gpex40-pcie"
+- reg: Should contain PCIe registers location and length
+ "config_axi_slave": PCIe controller registers
+ "csr_axi_slave" : Bridge config registers
+ "gpio_slave" : GPIO registers to control slot power
+ "apb_csr" : MSI registers
+
+- device_type: must be "pci"
+- apio-wins : number of requested apio outbound windows
+ default 2 outbound windows are configured -
+ 1. Config window
+ 2. Memory window
+- ppio-wins : number of requested ppio inbound windows
+ default 1 inbound memory window is configured.
+- bus-range: PCI bus numbers covered
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- interrupt-parent : phandle to the interrupt controller that
+ it is attached to, it should be set to gic to point to
+ ARM's Generic Interrupt Controller node in system DT.
+- interrupts: The interrupt line of the PCIe controller
+ last cell of this field is set to 4 to
+ denote it as IRQ_TYPE_LEVEL_HIGH type interrupt.
+- interrupt-map-mask,
+ interrupt-map: standard PCI properties to define the mapping of the
+ PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+ supported by hardware)
+ Please refer to the standard PCI bus binding document for a more
+ detailed explanation
+
+
+Example:
+++++++++
+ pcie0: pcie@a0000000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "mbvl,gpex40-pcie";
+ reg = <0xa0000000 0x00001000>,
+ <0xb0000000 0x00010000>,
+ <0xff000000 0x00200000>,
+ <0xb0010000 0x00001000>;
+ reg-names = "config_axi_slave",
+ "csr_axi_slave",
+ "gpio_slave",
+ "apb_csr";
+ device_type = "pci";
+ apio-wins = <2>;
+ ppio-wins = <1>;
+ bus-range = <0x00000000 0x000000ff>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ interrupts = < 0 89 4 >;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 0 &pci_express 0>,
+ <0 0 0 1 &pci_express 1>,
+ <0 0 0 2 &pci_express 2>,
+ <0 0 0 3 &pci_express 3>;
+ ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
+
+ };
diff --git a/dts/Bindings/pci/pci-armada8k.txt b/dts/Bindings/pci/pci-armada8k.txt
index c1e4c3d..9e3fc15 100644
--- a/dts/Bindings/pci/pci-armada8k.txt
+++ b/dts/Bindings/pci/pci-armada8k.txt
@@ -12,7 +12,10 @@ Required properties:
- "ctrl" for the control register region
- "config" for the config space region
- interrupts: Interrupt specifier for the PCIe controler
-- clocks: reference to the PCIe controller clock
+- clocks: reference to the PCIe controller clocks
+- clock-names: mandatory if there is a second clock, in this case the
+ name must be "core" for the first clock and "reg" for the second
+ one
Example:
diff --git a/dts/Bindings/pci/pci-keystone.txt b/dts/Bindings/pci/pci-keystone.txt
index 7e05487..3d4a209 100644
--- a/dts/Bindings/pci/pci-keystone.txt
+++ b/dts/Bindings/pci/pci-keystone.txt
@@ -3,9 +3,9 @@ TI Keystone PCIe interface
Keystone PCI host Controller is based on the Synopsys DesignWare PCI
hardware version 3.65. It shares common functions with the PCIe DesignWare
core driver and inherits common properties defined in
-Documentation/devicetree/bindings/pci/designware-pci.txt
+Documentation/devicetree/bindings/pci/designware-pcie.txt
-Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
+Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
for the details of DesignWare DT bindings. Additional properties are
described here as well as properties that are not applicable.
diff --git a/dts/Bindings/pci/rcar-pci.txt b/dts/Bindings/pci/rcar-pci.txt
index 1fb614e..a5f7fc6 100644
--- a/dts/Bindings/pci/rcar-pci.txt
+++ b/dts/Bindings/pci/rcar-pci.txt
@@ -8,6 +8,7 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
"renesas,pcie-r8a7793" for the R8A7793 SoC;
"renesas,pcie-r8a7795" for the R8A7795 SoC;
"renesas,pcie-r8a7796" for the R8A7796 SoC;
+ "renesas,pcie-r8a77980" for the R8A77980 SoC;
"renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
RZ/G1 compatible device.
"renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device.
@@ -32,6 +33,11 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
and PCIe bus clocks.
- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
+Optional properties:
+- phys: from common PHY binding: PHY phandle and specifier (only make sense
+ for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks).
+- phy-names: from common PHY binding: should be "pcie".
+
Example:
SoC-specific DT Entry:
diff --git a/dts/Bindings/pci/rockchip-pcie-ep.txt b/dts/Bindings/pci/rockchip-pcie-ep.txt
new file mode 100644
index 0000000..7784673
--- /dev/null
+++ b/dts/Bindings/pci/rockchip-pcie-ep.txt
@@ -0,0 +1,62 @@
+* Rockchip AXI PCIe Endpoint Controller DT description
+
+Required properties:
+- compatible: Should contain "rockchip,rk3399-pcie-ep"
+- reg: Two register ranges as listed in the reg-names property
+- reg-names: Must include the following names
+ - "apb-base"
+ - "mem-base"
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - "aclk"
+ - "aclk-perf"
+ - "hclk"
+ - "pm"
+- resets: Must contain seven entries for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must include the following names
+ - "core"
+ - "mgmt"
+ - "mgmt-sticky"
+ - "pipe"
+ - "pm"
+ - "aclk"
+ - "pclk"
+- pinctrl-names : The pin control state names
+- pinctrl-0: The "default" pinctrl state
+- phys: Must contain an phandle to a PHY for each entry in phy-names.
+- phy-names: Must include 4 entries for all 4 lanes even if some of
+ them won't be used for your cases. Entries are of the form "pcie-phy-N":
+ where N ranges from 0 to 3.
+ (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
+ for changing the #phy-cells of phy node to support it)
+- rockchip,max-outbound-regions: Maximum number of outbound regions
+
+Optional Property:
+- num-lanes: number of lanes to use
+- max-functions: Maximum number of functions that can be configured (default 1).
+
+pcie0-ep: pcie@f8000000 {
+ compatible = "rockchip,rk3399-pcie-ep";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ rockchip,max-outbound-regions = <16>;
+ clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
+ <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
+ clock-names = "aclk", "aclk-perf",
+ "hclk", "pm";
+ max-functions = /bits/ 8 <8>;
+ num-lanes = <4>;
+ reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
+ reg-names = "apb-base", "mem-base";
+ resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
+ <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
+ <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
+ reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
+ "pm", "pclk", "aclk";
+ phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
+ phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreq>;
+};
diff --git a/dts/Bindings/pci/rockchip-pcie.txt b/dts/Bindings/pci/rockchip-pcie-host.txt
index af34c65..af34c65 100644
--- a/dts/Bindings/pci/rockchip-pcie.txt
+++ b/dts/Bindings/pci/rockchip-pcie-host.txt
diff --git a/dts/Bindings/pci/xgene-pci.txt b/dts/Bindings/pci/xgene-pci.txt
index 6fd2dec..9249033 100644
--- a/dts/Bindings/pci/xgene-pci.txt
+++ b/dts/Bindings/pci/xgene-pci.txt
@@ -25,8 +25,6 @@ Optional properties:
Example:
-SoC-specific DT Entry:
-
pcie0: pcie@1f2b0000 {
status = "disabled";
device_type = "pci";
@@ -50,8 +48,3 @@ SoC-specific DT Entry:
clocks = <&pcie0clk 0>;
};
-
-Board-specific DT Entry:
- &pcie0 {
- status = "ok";
- };
diff --git a/dts/Bindings/phy/phy-mtk-xsphy.txt b/dts/Bindings/phy/phy-mtk-xsphy.txt
new file mode 100644
index 0000000..e7caefa
--- /dev/null
+++ b/dts/Bindings/phy/phy-mtk-xsphy.txt
@@ -0,0 +1,109 @@
+MediaTek XS-PHY binding
+--------------------------
+
+The XS-PHY controller supports physical layer functionality for USB3.1
+GEN2 controller on MediaTek SoCs.
+
+Required properties (controller (parent) node):
+ - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
+ soc-model is the name of SoC, such as mt3611 etc;
+ when using "mediatek,xsphy" compatible string, you need SoC specific
+ ones in addition, one of:
+ - "mediatek,mt3611-xsphy"
+
+ - #address-cells, #size-cells : should use the same values as the root node
+ - ranges: must be present
+
+Optional properties (controller (parent) node):
+ - reg : offset and length of register shared by multiple U3 ports,
+ exclude port's private register, if only U2 ports provided,
+ shouldn't use the property.
+ - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
+ calibrate
+ - mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on
+ SoC process
+
+Required nodes : a sub-node is required for each port the controller
+ provides. Address range information including the usual
+ 'reg' property is used inside these nodes to describe
+ the controller's topology.
+
+Required properties (port (child) node):
+- reg : address and length of the register set for the port.
+- clocks : a list of phandle + clock-specifier pairs, one for each
+ entry in clock-names
+- clock-names : must contain
+ "ref": 48M reference clock for HighSpeed analog phy; and 26M
+ reference clock for SuperSpeedPlus analog phy, sometimes is
+ 24M, 25M or 27M, depended on platform.
+- #phy-cells : should be 1
+ cell after port phandle is phy type from:
+ - PHY_TYPE_USB2
+ - PHY_TYPE_USB3
+
+The following optional properties are only for debug or HQA test
+Optional properties (PHY_TYPE_USB2 port (child) node):
+- mediatek,eye-src : u32, the value of slew rate calibrate
+- mediatek,eye-vrt : u32, the selection of VRT reference voltage
+- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
+- mediatek,efuse-intr : u32, the selection of Internal Resistor
+
+Optional properties (PHY_TYPE_USB3 port (child) node):
+- mediatek,efuse-intr : u32, the selection of Internal Resistor
+- mediatek,efuse-tx-imp : u32, the selection of TX Impedance
+- mediatek,efuse-rx-imp : u32, the selection of RX Impedance
+
+Banks layout of xsphy
+-------------------------------------------------------------
+port offset bank
+u2 port0 0x0000 MISC
+ 0x0100 FMREG
+ 0x0300 U2PHY_COM
+u2 port1 0x1000 MISC
+ 0x1100 FMREG
+ 0x1300 U2PHY_COM
+u2 port2 0x2000 MISC
+ ...
+u31 common 0x3000 DIG_GLB
+ 0x3100 PHYA_GLB
+u31 port0 0x3400 DIG_LN_TOP
+ 0x3500 DIG_LN_TX0
+ 0x3600 DIG_LN_RX0
+ 0x3700 DIG_LN_DAIF
+ 0x3800 PHYA_LN
+u31 port1 0x3a00 DIG_LN_TOP
+ 0x3b00 DIG_LN_TX0
+ 0x3c00 DIG_LN_RX0
+ 0x3d00 DIG_LN_DAIF
+ 0x3e00 PHYA_LN
+ ...
+
+DIG_GLB & PHYA_GLB are shared by U31 ports.
+
+Example:
+
+u3phy: usb-phy@11c40000 {
+ compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
+ reg = <0 0x11c43000 0 0x0200>;
+ mediatek,src-ref-clk-mhz = <26>;
+ mediatek,src-coef = <17>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ u2port0: usb-phy@11c40000 {
+ reg = <0 0x11c40000 0 0x0400>;
+ clocks = <&clk48m>;
+ clock-names = "ref";
+ mediatek,eye-src = <4>;
+ #phy-cells = <1>;
+ };
+
+ u3port0: usb-phy@11c43000 {
+ reg = <0 0x11c43400 0 0x0500>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ mediatek,efuse-intr = <28>;
+ #phy-cells = <1>;
+ };
+};
diff --git a/dts/Bindings/phy/qcom-qmp-phy.txt b/dts/Bindings/phy/qcom-qmp-phy.txt
index dcf1b8f..266a1bb 100644
--- a/dts/Bindings/phy/qcom-qmp-phy.txt
+++ b/dts/Bindings/phy/qcom-qmp-phy.txt
@@ -9,7 +9,8 @@ Required properties:
"qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
- "qcom,qmp-v3-usb3-phy" for USB3 QMP V3 phy.
+ "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
+ "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845.
- reg: offset and length of register set for PHY's common serdes block.
diff --git a/dts/Bindings/phy/qcom-qusb2-phy.txt b/dts/Bindings/phy/qcom-qusb2-phy.txt
index 42c9742..03025d9 100644
--- a/dts/Bindings/phy/qcom-qusb2-phy.txt
+++ b/dts/Bindings/phy/qcom-qusb2-phy.txt
@@ -6,7 +6,7 @@ QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
Required properties:
- compatible: compatible list, contains
"qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
- "qcom,qusb2-v2-phy" for QUSB2 V2 PHY.
+ "qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
- reg: offset and length of the PHY register set.
- #phy-cells: must be 0.
@@ -27,6 +27,27 @@ Optional properties:
tuning parameter value for qusb2 phy.
- qcom,tcsr-syscon: Phandle to TCSR syscon register region.
+ - qcom,imp-res-offset-value: It is a 6 bit value that specifies offset to be
+ added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
+ tuning parameter that may vary for different boards of same SOC.
+ This property is applicable to only QUSB2 v2 PHY (sdm845).
+ - qcom,hstx-trim-value: It is a 4 bit value that specifies tuning for HSTX
+ output current.
+ Possible range is - 15mA to 24mA (stepsize of 600 uA).
+ See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
+ This property is applicable to only QUSB2 v2 PHY (sdm845).
+ Default value is 22.2mA for sdm845.
+ - qcom,preemphasis-level: It is a 2 bit value that specifies pre-emphasis level.
+ Possible range is 0 to 15% (stepsize of 5%).
+ See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
+ This property is applicable to only QUSB2 v2 PHY (sdm845).
+ Default value is 10% for sdm845.
+- qcom,preemphasis-width: It is a 1 bit value that specifies how long the HSTX
+ pre-emphasis (specified using qcom,preemphasis-level) must be in
+ effect. Duration could be half-bit of full-bit.
+ See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
+ This property is applicable to only QUSB2 v2 PHY (sdm845).
+ Default value is full-bit width for sdm845.
Example:
hsusb_phy: phy@7411000 {
diff --git a/dts/Bindings/pinctrl/actions,s900-pinctrl.txt b/dts/Bindings/pinctrl/actions,s900-pinctrl.txt
index fb87c7d..8fb5a53 100644
--- a/dts/Bindings/pinctrl/actions,s900-pinctrl.txt
+++ b/dts/Bindings/pinctrl/actions,s900-pinctrl.txt
@@ -8,6 +8,17 @@ Required Properties:
- reg: Should contain the register base address and size of
the pin controller.
- clocks: phandle of the clock feeding the pin controller
+- gpio-controller: Marks the device node as a GPIO controller.
+- gpio-ranges: Specifies the mapping between gpio controller and
+ pin-controller pins.
+- #gpio-cells: Should be two. The first cell is the gpio pin number
+ and the second cell is used for optional parameters.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Specifies the number of cells needed to encode an
+ interrupt. Shall be set to 2. The first cell
+ defines the interrupt number, the second encodes
+ the trigger flags described in
+ bindings/interrupt-controller/interrupts.txt
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
@@ -164,6 +175,11 @@ Example:
compatible = "actions,s900-pinctrl";
reg = <0x0 0xe01b0000 0x0 0x1000>;
clocks = <&cmu CLK_GPIO>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 146>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
uart2-default: uart2-default {
pinmux {
diff --git a/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 64bc5c2..258a464 100644
--- a/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -28,6 +28,7 @@ Required properties:
"allwinner,sun50i-a64-r-pinctrl"
"allwinner,sun50i-h5-pinctrl"
"allwinner,sun50i-h6-pinctrl"
+ "allwinner,sun50i-h6-r-pinctrl"
"nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
diff --git a/dts/Bindings/pinctrl/brcm,bcm2835-gpio.txt b/dts/Bindings/pinctrl/brcm,bcm2835-gpio.txt
index 2569866..3fac0a0 100644
--- a/dts/Bindings/pinctrl/brcm,bcm2835-gpio.txt
+++ b/dts/Bindings/pinctrl/brcm,bcm2835-gpio.txt
@@ -36,6 +36,24 @@ listed. In other words, a subnode that lists only a mux function implies no
information about any pull configuration. Similarly, a subnode that lists only
a pul parameter implies no information about the mux function.
+The BCM2835 pin configuration and multiplexing supports the generic bindings.
+For details on each properties, you can refer to ./pinctrl-bindings.txt.
+
+Required sub-node properties:
+ - pins
+ - function
+
+Optional sub-node properties:
+ - bias-disable
+ - bias-pull-up
+ - bias-pull-down
+ - output-high
+ - output-low
+
+Legacy pin configuration and multiplexing binding:
+*** (Its use is deprecated, use generic multiplexing and configuration
+bindings instead)
+
Required subnode-properties:
- brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs
are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53.
diff --git a/dts/Bindings/pinctrl/meson,pinctrl.txt b/dts/Bindings/pinctrl/meson,pinctrl.txt
index 2c12f97..54ecb8a 100644
--- a/dts/Bindings/pinctrl/meson,pinctrl.txt
+++ b/dts/Bindings/pinctrl/meson,pinctrl.txt
@@ -3,8 +3,10 @@
Required properties for the root node:
- compatible: one of "amlogic,meson8-cbus-pinctrl"
"amlogic,meson8b-cbus-pinctrl"
+ "amlogic,meson8m2-cbus-pinctrl"
"amlogic,meson8-aobus-pinctrl"
"amlogic,meson8b-aobus-pinctrl"
+ "amlogic,meson8m2-aobus-pinctrl"
"amlogic,meson-gxbb-periphs-pinctrl"
"amlogic,meson-gxbb-aobus-pinctrl"
"amlogic,meson-gxl-periphs-pinctrl"
diff --git a/dts/Bindings/pinctrl/pinctrl-max77620.txt b/dts/Bindings/pinctrl/pinctrl-max77620.txt
index ad4fce3..511fc23 100644
--- a/dts/Bindings/pinctrl/pinctrl-max77620.txt
+++ b/dts/Bindings/pinctrl/pinctrl-max77620.txt
@@ -11,9 +11,9 @@ Optional Pinmux properties:
--------------------------
Following properties are required if default setting of pins are required
at boot.
-- pinctrl-names: A pinctrl state named per <pinctrl-binding.txt>.
+- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
- <pinctrl-binding.txt>.
+ <pinctrl-bindings.txt>.
The pin configurations are defined as child of the pinctrl states node. Each
sub-node have following properties:
diff --git a/dts/Bindings/pinctrl/pinctrl-mcp23s08.txt b/dts/Bindings/pinctrl/pinctrl-mcp23s08.txt
index a5a8322..625a22e 100644
--- a/dts/Bindings/pinctrl/pinctrl-mcp23s08.txt
+++ b/dts/Bindings/pinctrl/pinctrl-mcp23s08.txt
@@ -18,7 +18,9 @@ Required properties:
removed.
- #gpio-cells : Should be two.
- first cell is the pin number
- - second cell is used to specify flags. Flags are currently unused.
+ - second cell is used to specify flags as described in
+ 'Documentation/devicetree/bindings/gpio/gpio.txt'. Allowed values defined by
+ 'include/dt-bindings/gpio/gpio.h' (e.g. GPIO_ACTIVE_LOW).
- gpio-controller : Marks the device node as a GPIO controller.
- reg : For an address on its bus. I2C uses this a the I2C address of the chip.
SPI uses this to specify the chipselect line which the chip is
@@ -99,9 +101,9 @@ Optional Pinmux properties:
--------------------------
Following properties are required if default setting of pins are required
at boot.
-- pinctrl-names: A pinctrl state named per <pinctrl-binding.txt>.
+- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
- <pinctrl-binding.txt>.
+ <pinctrl-bindings.txt>.
The pin configurations are defined as child of the pinctrl states node. Each
sub-node have following properties:
diff --git a/dts/Bindings/pinctrl/pinctrl-mt7622.txt b/dts/Bindings/pinctrl/pinctrl-mt7622.txt
index f18ed99..def8fca 100644
--- a/dts/Bindings/pinctrl/pinctrl-mt7622.txt
+++ b/dts/Bindings/pinctrl/pinctrl-mt7622.txt
@@ -9,6 +9,16 @@ Required properties for the root node:
- #gpio-cells: Should be two. The first cell is the pin number and the
second is the GPIO flags.
+Optional properties:
+- interrupt-controller : Marks the device node as an interrupt controller
+
+If the property interrupt-controller is defined, following property is required
+- reg-names: A string describing the "reg" entries. Must contain "eint".
+- interrupts : The interrupt output from the controller.
+- #interrupt-cells: Should be two.
+- interrupt-parent: Phandle of the interrupt parent to which the external
+ GPIO interrupts are forwarded to.
+
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
diff --git a/dts/Bindings/pinctrl/pinctrl-rk805.txt b/dts/Bindings/pinctrl/pinctrl-rk805.txt
index eee3dc2..cbcbd31 100644
--- a/dts/Bindings/pinctrl/pinctrl-rk805.txt
+++ b/dts/Bindings/pinctrl/pinctrl-rk805.txt
@@ -10,9 +10,9 @@ Optional Pinmux properties:
--------------------------
Following properties are required if default setting of pins are required
at boot.
-- pinctrl-names: A pinctrl state named per <pinctrl-binding.txt>.
+- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
- <pinctrl-binding.txt>.
+ <pinctrl-bindings.txt>.
The pin configurations are defined as child of the pinctrl states node. Each
sub-node have following properties:
diff --git a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
index 892d8fd..abd8fbc 100644
--- a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -15,6 +15,7 @@ Required Properties:
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
+ - "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
@@ -27,6 +28,7 @@ Required Properties:
- "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
- "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.
+ - "renesas,pfc-r8a77990": for R8A77990 (R-Car E3) compatible pin-controller.
- "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
diff --git a/dts/Bindings/pinctrl/rockchip,pinctrl.txt b/dts/Bindings/pinctrl/rockchip,pinctrl.txt
index a01a3b8..0919db2 100644
--- a/dts/Bindings/pinctrl/rockchip,pinctrl.txt
+++ b/dts/Bindings/pinctrl/rockchip,pinctrl.txt
@@ -20,6 +20,7 @@ defined as gpio sub-nodes of the pinmux controller.
Required properties for iomux controller:
- compatible: should be
+ "rockchip,px30-pinctrl": for Rockchip PX30
"rockchip,rv1108-pinctrl": for Rockchip RV1108
"rockchip,rk2928-pinctrl": for Rockchip RK2928
"rockchip,rk3066a-pinctrl": for Rockchip RK3066a
diff --git a/dts/Bindings/power/fsl,imx-gpc.txt b/dts/Bindings/power/fsl,imx-gpc.txt
index b31d6bb..726ec28 100644
--- a/dts/Bindings/power/fsl,imx-gpc.txt
+++ b/dts/Bindings/power/fsl,imx-gpc.txt
@@ -14,7 +14,7 @@ Required properties:
datasheet
- interrupts: Should contain one interrupt specifier for the GPC interrupt
- clocks: Must contain an entry for each entry in clock-names.
- See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- ipg
diff --git a/dts/Bindings/power/pd-samsung.txt b/dts/Bindings/power/pd-samsung.txt
index 549f7de..92ef355 100644
--- a/dts/Bindings/power/pd-samsung.txt
+++ b/dts/Bindings/power/pd-samsung.txt
@@ -15,23 +15,13 @@ Required Properties:
Optional Properties:
- label: Human readable string with domain name. Will be visible in userspace
to let user to distinguish between multiple domains in SoC.
-- clocks: List of clock handles. The parent clocks of the input clocks to the
- devices in this power domain are set to oscclk before power gating
- and restored back after powering on a domain. This is required for
- all domains which are powered on and off and not required for unused
- domains.
-- clock-names: The following clocks can be specified:
- - oscclk: Oscillator clock.
- - clkN: Input clocks to the devices in this power domain. These clocks
- will be reparented to oscclk before switching power domain off.
- Their original parent will be brought back after turning on
- the domain. Maximum of 4 clocks (N = 0 to 3) are supported.
- - asbN: Clocks required by asynchronous bridges (ASB) present in
- the power domain. These clock should be enabled during power
- domain on/off operations.
- power-domains: phandle pointing to the parent power domain, for more details
see Documentation/devicetree/bindings/power/power_domain.txt
+Deprecated Properties:
+- clocks
+- clock-names
+
Node of a device using power domains must have a power-domains property
defined with a phandle to respective power domain.
@@ -47,8 +37,6 @@ Example:
mfc_pd: power-domain@10044060 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044060 0x20>;
- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
- clock-names = "oscclk", "clk0";
#power-domain-cells = <0>;
label = "MFC";
};
diff --git a/dts/Bindings/power/power_domain.txt b/dts/Bindings/power/power_domain.txt
index f335531..9b387f8 100644
--- a/dts/Bindings/power/power_domain.txt
+++ b/dts/Bindings/power/power_domain.txt
@@ -111,8 +111,8 @@ Example 3:
==PM domain consumers==
Required properties:
- - power-domains : A phandle and PM domain specifier as defined by bindings of
- the power controller specified by phandle.
+ - power-domains : A list of PM domain specifiers, as defined by bindings of
+ the power controller that is the PM domain provider.
Example:
@@ -122,12 +122,21 @@ Example:
power-domains = <&power 0>;
};
-The node above defines a typical PM domain consumer device, which is located
-inside a PM domain with index 0 of a power controller represented by a node
-with the label "power".
+ leaky-device@12351000 {
+ compatible = "foo,i-leak-current";
+ reg = <0x12351000 0x1000>;
+ power-domains = <&power 0>, <&power 1> ;
+ };
+
+The first example above defines a typical PM domain consumer device, which is
+located inside a PM domain with index 0 of a power controller represented by a
+node with the label "power".
+In the second example the consumer device are partitioned across two PM domains,
+the first with index 0 and the second with index 1, of a power controller that
+is represented by a node with the label "power.
Optional properties:
-- required-opp: This contains phandle to an OPP node in another device's OPP
+- required-opps: This contains phandle to an OPP node in another device's OPP
table. It may contain an array of phandles, where each phandle points to an
OPP of a different device. It should not contain multiple phandles to the OPP
nodes in the same OPP table. This specifies the minimum required OPP of the
@@ -175,14 +184,14 @@ Example:
compatible = "foo,i-leak-current";
reg = <0x12350000 0x1000>;
power-domains = <&power 0>;
- required-opp = <&domain0_opp_0>;
+ required-opps = <&domain0_opp_0>;
};
leaky-device1@12350000 {
compatible = "foo,i-leak-current";
reg = <0x12350000 0x1000>;
power-domains = <&power 1>;
- required-opp = <&domain1_opp_1>;
+ required-opps = <&domain1_opp_1>;
};
[1]. Documentation/devicetree/bindings/power/domain-idle-state.txt
diff --git a/dts/Bindings/power/renesas,rcar-sysc.txt b/dts/Bindings/power/renesas,rcar-sysc.txt
index ab399e5..180ae65 100644
--- a/dts/Bindings/power/renesas,rcar-sysc.txt
+++ b/dts/Bindings/power/renesas,rcar-sysc.txt
@@ -9,6 +9,7 @@ Required properties:
- compatible: Must contain exactly one of the following:
- "renesas,r8a7743-sysc" (RZ/G1M)
- "renesas,r8a7745-sysc" (RZ/G1E)
+ - "renesas,r8a77470-sysc" (RZ/G1C)
- "renesas,r8a7779-sysc" (R-Car H1)
- "renesas,r8a7790-sysc" (R-Car H2)
- "renesas,r8a7791-sysc" (R-Car M2-W)
@@ -20,6 +21,7 @@ Required properties:
- "renesas,r8a77965-sysc" (R-Car M3-N)
- "renesas,r8a77970-sysc" (R-Car V3M)
- "renesas,r8a77980-sysc" (R-Car V3H)
+ - "renesas,r8a77990-sysc" (R-Car E3)
- "renesas,r8a77995-sysc" (R-Car D3)
- reg: Address start and address range for the device.
- #power-domain-cells: Must be 1.
diff --git a/dts/Bindings/power/rockchip-io-domain.txt b/dts/Bindings/power/rockchip-io-domain.txt
index 4a4766e..e66fd4e 100644
--- a/dts/Bindings/power/rockchip-io-domain.txt
+++ b/dts/Bindings/power/rockchip-io-domain.txt
@@ -31,6 +31,8 @@ SoC is on the same page.
Required properties:
- compatible: should be one of:
+ - "rockchip,px30-io-voltage-domain" for px30
+ - "rockchip,px30-pmu-io-voltage-domain" for px30 pmu-domains
- "rockchip,rk3188-io-voltage-domain" for rk3188
- "rockchip,rk3228-io-voltage-domain" for rk3228
- "rockchip,rk3288-io-voltage-domain" for rk3288
@@ -51,6 +53,19 @@ a phandle the relevant regulator. All specified supplies must be able
to report their voltage. The IO Voltage Domain for any non-specified
supplies will be not be touched.
+Possible supplies for PX30:
+- vccio6-supply: The supply connected to VCCIO6.
+- vccio1-supply: The supply connected to VCCIO1.
+- vccio2-supply: The supply connected to VCCIO2.
+- vccio3-supply: The supply connected to VCCIO3.
+- vccio4-supply: The supply connected to VCCIO4.
+- vccio5-supply: The supply connected to VCCIO5.
+- vccio-oscgpi-supply: The supply connected to VCCIO_OSCGPI.
+
+Possible supplies for PX30 pmu-domains:
+- pmuio1-supply: The supply connected to PMUIO1.
+- pmuio2-supply: The supply connected to PMUIO2.
+
Possible supplies for rk3188:
- ap0-supply: The supply connected to AP0_VCC.
- ap1-supply: The supply connected to AP1_VCC.
diff --git a/dts/Bindings/power/supply/ab8500/btemp.txt b/dts/Bindings/power/supply/ab8500/btemp.txt
index 0ba1bcc..f181e46 100644
--- a/dts/Bindings/power/supply/ab8500/btemp.txt
+++ b/dts/Bindings/power/supply/ab8500/btemp.txt
@@ -13,4 +13,4 @@ Required Properties:
};
For information on battery specific node, Ref:
-Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
+Documentation/devicetree/bindings/power/supply/ab8500/fg.txt
diff --git a/dts/Bindings/power/supply/ab8500/chargalg.txt b/dts/Bindings/power/supply/ab8500/chargalg.txt
index ef53283..56636f9 100644
--- a/dts/Bindings/power/supply/ab8500/chargalg.txt
+++ b/dts/Bindings/power/supply/ab8500/chargalg.txt
@@ -13,4 +13,4 @@ ab8500_chargalg {
};
For information on battery specific node, Ref:
-Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
+Documentation/devicetree/bindings/power/supply/ab8500/fg.txt
diff --git a/dts/Bindings/power/supply/ab8500/charger.txt b/dts/Bindings/power/supply/ab8500/charger.txt
index 6bdbb08..24ada03 100644
--- a/dts/Bindings/power/supply/ab8500/charger.txt
+++ b/dts/Bindings/power/supply/ab8500/charger.txt
@@ -22,4 +22,4 @@ Required Properties:
};
For information on battery specific node, Ref:
-Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
+Documentation/devicetree/bindings/power/supply/ab8500/fg.txt
diff --git a/dts/Bindings/power/supply/bq27xxx.txt b/dts/Bindings/power/supply/bq27xxx.txt
index 615c1cb..37994fd 100644
--- a/dts/Bindings/power/supply/bq27xxx.txt
+++ b/dts/Bindings/power/supply/bq27xxx.txt
@@ -25,6 +25,7 @@ Required properties:
* "ti,bq27545" - BQ27545
* "ti,bq27421" - BQ27421
* "ti,bq27425" - BQ27425
+ * "ti,bq27426" - BQ27426
* "ti,bq27441" - BQ27441
* "ti,bq27621" - BQ27621
- reg: integer, I2C address of the fuel gauge.
diff --git a/dts/Bindings/power/wakeup-source.txt b/dts/Bindings/power/wakeup-source.txt
index 5d254ab..cfd7465 100644
--- a/dts/Bindings/power/wakeup-source.txt
+++ b/dts/Bindings/power/wakeup-source.txt
@@ -22,7 +22,7 @@ List of legacy properties and respective binding document
3. "has-tpo" Documentation/devicetree/bindings/rtc/rtc-opal.txt
4. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt
Documentation/devicetree/bindings/mfd/tc3589x.txt
- Documentation/devicetree/bindings/input/ads7846.txt
+ Documentation/devicetree/bindings/input/touchscreen/ads7846.txt
5. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt
6. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung-keypad.txt
7. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
diff --git a/dts/Bindings/pps/pps-gpio.txt b/dts/Bindings/pps/pps-gpio.txt
index 0de23b7..3683874 100644
--- a/dts/Bindings/pps/pps-gpio.txt
+++ b/dts/Bindings/pps/pps-gpio.txt
@@ -20,5 +20,4 @@ Example:
assert-falling-edge;
compatible = "pps-gpio";
- status = "okay";
};
diff --git a/dts/Bindings/ptp/ptp-qoriq.txt b/dts/Bindings/ptp/ptp-qoriq.txt
new file mode 100644
index 0000000..0f569d8
--- /dev/null
+++ b/dts/Bindings/ptp/ptp-qoriq.txt
@@ -0,0 +1,69 @@
+* Freescale QorIQ 1588 timer based PTP clock
+
+General Properties:
+
+ - compatible Should be "fsl,etsec-ptp"
+ - reg Offset and length of the register set for the device
+ - interrupts There should be at least two interrupts. Some devices
+ have as many as four PTP related interrupts.
+
+Clock Properties:
+
+ - fsl,cksel Timer reference clock source.
+ - fsl,tclk-period Timer reference clock period in nanoseconds.
+ - fsl,tmr-prsc Prescaler, divides the output clock.
+ - fsl,tmr-add Frequency compensation value.
+ - fsl,tmr-fiper1 Fixed interval period pulse generator.
+ - fsl,tmr-fiper2 Fixed interval period pulse generator.
+ - fsl,max-adj Maximum frequency adjustment in parts per billion.
+
+ These properties set the operational parameters for the PTP
+ clock. You must choose these carefully for the clock to work right.
+ Here is how to figure good values:
+
+ TimerOsc = selected reference clock MHz
+ tclk_period = desired clock period nanoseconds
+ NominalFreq = 1000 / tclk_period MHz
+ FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
+ tmr_add = ceil(2^32 / FreqDivRatio)
+ OutputClock = NominalFreq / tmr_prsc MHz
+ PulseWidth = 1 / OutputClock microseconds
+ FiperFreq1 = desired frequency in Hz
+ FiperDiv1 = 1000000 * OutputClock / FiperFreq1
+ tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
+ max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
+
+ The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
+ driver expects that tmr_fiper1 will be correctly set to produce a 1
+ Pulse Per Second (PPS) signal, since this will be offered to the PPS
+ subsystem to synchronize the Linux clock.
+
+ Reference clock source is determined by the value, which is holded
+ in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
+ value, which will be directly written in those bits, that is why,
+ according to reference manual, the next clock sources can be used:
+
+ <0> - external high precision timer reference clock (TSEC_TMR_CLK
+ input is used for this purpose);
+ <1> - eTSEC system clock;
+ <2> - eTSEC1 transmit clock;
+ <3> - RTC clock input.
+
+ When this attribute is not used, eTSEC system clock will serve as
+ IEEE 1588 timer reference clock.
+
+Example:
+
+ ptp_clock@24e00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,cksel = <1>;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc = <100>;
+ fsl,tmr-add = <0x999999A4>;
+ fsl,tmr-fiper1 = <0x3B9AC9F6>;
+ fsl,tmr-fiper2 = <0x00018696>;
+ fsl,max-adj = <659999998>;
+ };
diff --git a/dts/Bindings/pwm/pwm-omap-dmtimer.txt b/dts/Bindings/pwm/pwm-omap-dmtimer.txt
index 2e53324..5ccfcc8 100644
--- a/dts/Bindings/pwm/pwm-omap-dmtimer.txt
+++ b/dts/Bindings/pwm/pwm-omap-dmtimer.txt
@@ -2,7 +2,7 @@
Required properties:
- compatible: Shall contain "ti,omap-dmtimer-pwm".
-- ti,timers: phandle to PWM capable OMAP timer. See arm/omap/timer.txt for info
+- ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer.txt for info
about these timers.
- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
the cells format.
diff --git a/dts/Bindings/regulator/pfuze100.txt b/dts/Bindings/regulator/pfuze100.txt
index c6dd3f5..f0ada3b 100644
--- a/dts/Bindings/regulator/pfuze100.txt
+++ b/dts/Bindings/regulator/pfuze100.txt
@@ -21,7 +21,7 @@ Each regulator is defined using the standard binding for regulators.
Example 1: PFUZE100
- pmic: pfuze100@8 {
+ pfuze100: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
@@ -122,7 +122,7 @@ Example 1: PFUZE100
Example 2: PFUZE200
- pmic: pfuze200@8 {
+ pfuze200: pmic@8 {
compatible = "fsl,pfuze200";
reg = <0x08>;
@@ -216,7 +216,7 @@ Example 2: PFUZE200
Example 3: PFUZE3000
- pmic: pfuze3000@8 {
+ pfuze3000: pmic@8 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
diff --git a/dts/Bindings/regulator/qcom,spmi-regulator.txt b/dts/Bindings/regulator/qcom,spmi-regulator.txt
index 57d2c65..406f2e5 100644
--- a/dts/Bindings/regulator/qcom,spmi-regulator.txt
+++ b/dts/Bindings/regulator/qcom,spmi-regulator.txt
@@ -110,6 +110,11 @@ Qualcomm SPMI Regulators
Definition: Reference to regulator supplying the input pin, as
described in the data sheet.
+- qcom,saw-reg:
+ Usage: optional
+ Value type: <phandle>
+ Description: Reference to syscon node defining the SAW registers.
+
The regulator node houses sub-nodes for each regulator within the device. Each
sub-node is identified using the node's name, with valid values listed for each
@@ -201,6 +206,17 @@ see regulator.txt - with additional custom properties described below:
2 = 0.55 uA
3 = 0.75 uA
+- qcom,saw-slave:
+ Usage: optional
+ Value type: <boo>
+ Description: SAW controlled gang slave. Will not be configured.
+
+- qcom,saw-leader:
+ Usage: optional
+ Value type: <boo>
+ Description: SAW controlled gang leader. Will be configured as
+ SAW regulator.
+
Example:
regulators {
@@ -221,3 +237,32 @@ Example:
....
};
+
+Example 2:
+
+ saw3: syscon@9A10000 {
+ compatible = "syscon";
+ reg = <0x9A10000 0x1000>;
+ };
+
+ ...
+
+ spm-regulators {
+ compatible = "qcom,pm8994-regulators";
+ qcom,saw-reg = <&saw3>;
+ s8 {
+ qcom,saw-slave;
+ };
+ s9 {
+ qcom,saw-slave;
+ };
+ s10 {
+ qcom,saw-slave;
+ };
+ pm8994_s11_saw: s11 {
+ qcom,saw-leader;
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1140000>;
+ };
+ };
diff --git a/dts/Bindings/regulator/regulator.txt b/dts/Bindings/regulator/regulator.txt
index 2babe15..a7cd368 100644
--- a/dts/Bindings/regulator/regulator.txt
+++ b/dts/Bindings/regulator/regulator.txt
@@ -59,6 +59,11 @@ Optional properties:
- regulator-initial-mode: initial operating mode. The set of possible operating
modes depends on the capabilities of every hardware so each device binding
documentation explains which values the regulator supports.
+- regulator-allowed-modes: list of operating modes that software is allowed to
+ configure for the regulator at run-time. Elements may be specified in any
+ order. The set of possible operating modes depends on the capabilities of
+ every hardware so each device binding document explains which values the
+ regulator supports.
- regulator-system-load: Load in uA present on regulator that is not captured by
any consumer request.
- regulator-pull-down: Enable pull down resistor when the regulator is disabled.
@@ -68,6 +73,11 @@ Optional properties:
0: Disable active discharge.
1: Enable active discharge.
Absence of this property will leave configuration to default.
+- regulator-coupled-with: Regulators with which the regulator
+ is coupled. The linkage is 2-way - all coupled regulators should be linked
+ with each other. A regulator should not be coupled with its supplier.
+- regulator-coupled-max-spread: Max spread between voltages of coupled regulators
+ in microvolts.
Deprecated properties:
- regulator-compatible: If a regulator chip contains multiple
diff --git a/dts/Bindings/regulator/rohm,bd71837-regulator.txt b/dts/Bindings/regulator/rohm,bd71837-regulator.txt
new file mode 100644
index 0000000..4edf313
--- /dev/null
+++ b/dts/Bindings/regulator/rohm,bd71837-regulator.txt
@@ -0,0 +1,126 @@
+ROHM BD71837 Power Management Integrated Circuit (PMIC) regulator bindings
+
+BD71837MWV is a programmable Power Management
+IC (PMIC) for powering single-core, dual-core, and
+quad-core SoC’s such as NXP-i.MX 8M. It is optimized
+for low BOM cost and compact solution footprint. It
+integrates 8 Buck regulators and 7 LDO’s to provide all
+the power rails required by the SoC and the commonly
+used peripherals.
+
+Required properties:
+ - regulator-name: should be "buck1", ..., "buck8" and "ldo1", ..., "ldo7"
+
+List of regulators provided by this controller. BD71837 regulators node
+should be sub node of the BD71837 MFD node. See BD71837 MFD bindings at
+Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.txt
+Regulator nodes should be named to BUCK_<number> and LDO_<number>. The
+definition for each of these nodes is defined using the standard
+binding for regulators at
+Documentation/devicetree/bindings/regulator/regulator.txt.
+Note that if BD71837 starts at RUN state you probably want to use
+regulator-boot-on at least for BUCK6 and BUCK7 so that those are not
+disabled by driver at startup. LDO5 and LDO6 are supplied by those and
+if they are disabled at startup the voltage monitoring for LDO5/LDO6 will
+cause PMIC to reset.
+
+The valid names for regulator nodes are:
+BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6, BUCK7, BUCK8
+LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7
+
+Optional properties:
+- Any optional property defined in bindings/regulator/regulator.txt
+
+Example:
+regulators {
+ buck1: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-ramp-delay = <1250>;
+ };
+ buck2: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+ buck3: BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ };
+ buck4: BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ };
+ buck5: BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ };
+ buck6: BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+ buck7: BUCK7 {
+ regulator-name = "buck7";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ };
+ buck8: BUCK8 {
+ regulator-name = "buck8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+ ldo2: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ };
+ ldo3: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo4: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ ldo5: LDO5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo6: LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ ldo7_reg: LDO7 {
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+
diff --git a/dts/Bindings/regulator/sy8106a-regulator.txt b/dts/Bindings/regulator/sy8106a-regulator.txt
new file mode 100644
index 0000000..39a8ca7
--- /dev/null
+++ b/dts/Bindings/regulator/sy8106a-regulator.txt
@@ -0,0 +1,23 @@
+SY8106A Voltage regulator
+
+Required properties:
+- compatible: Must be "silergy,sy8106a"
+- reg: I2C slave address - must be <0x65>
+- silergy,fixed-microvolt - the voltage when I2C regulating is disabled (set
+ by external resistor like a fixed voltage)
+
+Any property defined as part of the core regulator binding, defined in
+./regulator.txt, can also be used.
+
+Example:
+
+ sy8106a {
+ compatible = "silergy,sy8106a";
+ reg = <0x65>;
+ regulator-name = "sy8106a-vdd";
+ silergy,fixed-microvolt = <1200000>;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
diff --git a/dts/Bindings/remoteproc/qcom,q6v5.txt b/dts/Bindings/remoteproc/qcom,q6v5.txt
index 00d3d58..d901824 100644
--- a/dts/Bindings/remoteproc/qcom,q6v5.txt
+++ b/dts/Bindings/remoteproc/qcom,q6v5.txt
@@ -11,6 +11,7 @@ on the Qualcomm Hexagon core.
"qcom,msm8916-mss-pil",
"qcom,msm8974-mss-pil"
"qcom,msm8996-mss-pil"
+ "qcom,sdm845-mss-pil"
- reg:
Usage: required
diff --git a/dts/Bindings/reserved-memory/qcom,cmd-db.txt b/dts/Bindings/reserved-memory/qcom,cmd-db.txt
new file mode 100644
index 0000000..6839553
--- /dev/null
+++ b/dts/Bindings/reserved-memory/qcom,cmd-db.txt
@@ -0,0 +1,37 @@
+Command DB
+---------
+
+Command DB is a database that provides a mapping between resource key and the
+resource address for a system resource managed by a remote processor. The data
+is stored in a shared memory region and is loaded by the remote processor.
+
+Some of the Qualcomm Technologies Inc SoC's have hardware accelerators for
+controlling shared resources. Depending on the board configuration the shared
+resource properties may change. These properties are dynamically probed by the
+remote processor and made available in the shared memory.
+
+The bindings for Command DB is specified in the reserved-memory section in
+devicetree. The devicetree representation of the command DB driver should be:
+
+Properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: Should be "qcom,cmd-db"
+
+- reg:
+ Usage: required
+ Value type: <prop encoded array>
+ Definition: The register address that points to the actual location of
+ the Command DB in memory.
+
+Example:
+
+ reserved-memory {
+ [...]
+ reserved-memory@85fe0000 {
+ reg = <0x0 0x85fe0000 0x0 0x20000>;
+ compatible = "qcom,cmd-db";
+ no-map;
+ };
+ };
diff --git a/dts/Bindings/reset/renesas,rst.txt b/dts/Bindings/reset/renesas,rst.txt
index 294a0da..67e83b0 100644
--- a/dts/Bindings/reset/renesas,rst.txt
+++ b/dts/Bindings/reset/renesas,rst.txt
@@ -17,6 +17,7 @@ Required properties:
Examples with soctypes are:
- "renesas,r8a7743-rst" (RZ/G1M)
- "renesas,r8a7745-rst" (RZ/G1E)
+ - "renesas,r8a77470-rst" (RZ/G1C)
- "renesas,r8a7778-reset-wdt" (R-Car M1A)
- "renesas,r8a7779-reset-wdt" (R-Car H1)
- "renesas,r8a7790-rst" (R-Car H2)
@@ -29,6 +30,7 @@ Required properties:
- "renesas,r8a77965-rst" (R-Car M3-N)
- "renesas,r8a77970-rst" (R-Car V3M)
- "renesas,r8a77980-rst" (R-Car V3H)
+ - "renesas,r8a77990-rst" (R-Car E3)
- "renesas,r8a77995-rst" (R-Car D3)
- reg: Address start and address range for the device.
diff --git a/dts/Bindings/rng/brcm,bcm2835.txt b/dts/Bindings/rng/brcm,bcm2835.txt
index 627b295..aaac797 100644
--- a/dts/Bindings/rng/brcm,bcm2835.txt
+++ b/dts/Bindings/rng/brcm,bcm2835.txt
@@ -14,11 +14,16 @@ Optional properties:
- clocks : phandle to clock-controller plus clock-specifier pair
- clock-names : "ipsec" as a clock name
+Optional properties:
+
+- interrupts: specify the interrupt for the RNG block
+
Example:
rng {
- compatible = "brcm,bcm2835-rng";
- reg = <0x7e104000 0x10>;
+ compatible = "brcm,bcm2835-rng";
+ reg = <0x7e104000 0x10>;
+ interrupts = <2 29>;
};
rng@18033000 {
diff --git a/dts/Bindings/crypto/samsung,exynos-rng4.txt b/dts/Bindings/rng/samsung,exynos4-rng.txt
index a13fbdb..a13fbdb 100644
--- a/dts/Bindings/crypto/samsung,exynos-rng4.txt
+++ b/dts/Bindings/rng/samsung,exynos4-rng.txt
diff --git a/dts/Bindings/sparc_sun_oracle_rng.txt b/dts/Bindings/rng/sparc_sun_oracle_rng.txt
index b0b2111..b0b2111 100644
--- a/dts/Bindings/sparc_sun_oracle_rng.txt
+++ b/dts/Bindings/rng/sparc_sun_oracle_rng.txt
diff --git a/dts/Bindings/rtc/nxp,rtc-2123.txt b/dts/Bindings/rtc/nxp,rtc-2123.txt
index 5cbc0b1..811124a 100644
--- a/dts/Bindings/rtc/nxp,rtc-2123.txt
+++ b/dts/Bindings/rtc/nxp,rtc-2123.txt
@@ -9,7 +9,7 @@ Optional properties:
Example:
-rtc: nxp,rtc-pcf2123@3 {
+pcf2123: rtc@3 {
compatible = "nxp,rtc-pcf2123"
reg = <3>
spi-cs-high;
diff --git a/dts/Bindings/rtc/st,stm32-rtc.txt b/dts/Bindings/rtc/st,stm32-rtc.txt
index a66692a..c920e27 100644
--- a/dts/Bindings/rtc/st,stm32-rtc.txt
+++ b/dts/Bindings/rtc/st,stm32-rtc.txt
@@ -1,23 +1,29 @@
STM32 Real Time Clock
Required properties:
-- compatible: can be either "st,stm32-rtc" or "st,stm32h7-rtc", depending on
- the device is compatible with stm32(f4/f7) or stm32h7.
+- compatible: can be one of the following:
+ - "st,stm32-rtc" for devices compatible with stm32(f4/f7).
+ - "st,stm32h7-rtc" for devices compatible with stm32h7.
+ - "st,stm32mp1-rtc" for devices compatible with stm32mp1.
- reg: address range of rtc register set.
- clocks: can use up to two clocks, depending on part used:
- "rtc_ck": RTC clock source.
- It is required on stm32(f4/f7) and stm32h7.
- "pclk": RTC APB interface clock.
It is not present on stm32(f4/f7).
- It is required on stm32h7.
+ It is required on stm32(h7/mp1).
- clock-names: must be "rtc_ck" and "pclk".
- It is required only on stm32h7.
+ It is required on stm32(h7/mp1).
- interrupt-parent: phandle for the interrupt controller.
-- interrupts: rtc alarm interrupt.
-- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
- (RTC registers) write protection.
+ It is required on stm32(f4/f7/h7).
+- interrupts: rtc alarm interrupt. On stm32mp1, a second interrupt is required
+ for rtc alarm wakeup interrupt.
+- st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg used to
+ access control register at offset, and change the dbp (Disable Backup
+ Protection) bit represented by the mask, mandatory to disable/enable backup
+ domain (RTC registers) write protection.
+ It is required on stm32(f4/f7/h7).
-Optional properties (to override default rtc_ck parent clock):
+Optional properties (to override default rtc_ck parent clock on stm32(f4/f7/h7):
- assigned-clocks: reference to the rtc_ck clock entry.
- assigned-clock-parents: phandle of the new parent clock of rtc_ck.
@@ -31,7 +37,7 @@ Example:
assigned-clock-parents = <&rcc 1 CLK_LSE>;
interrupt-parent = <&exti>;
interrupts = <17 1>;
- st,syscfg = <&pwrcfg>;
+ st,syscfg = <&pwrcfg 0x00 0x100>;
};
rtc: rtc@58004000 {
@@ -44,5 +50,14 @@ Example:
interrupt-parent = <&exti>;
interrupts = <17 1>;
interrupt-names = "alarm";
- st,syscfg = <&pwrcfg>;
+ st,syscfg = <&pwrcfg 0x00 0x100>;
+ };
+
+ rtc: rtc@5c004000 {
+ compatible = "st,stm32mp1-rtc";
+ reg = <0x5c004000 0x400>;
+ clocks = <&rcc RTCAPB>, <&rcc RTC>;
+ clock-names = "pclk", "rtc_ck";
+ interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_NONE>,
+ <&exti 19 1>;
};
diff --git a/dts/Bindings/serial/microchip,pic32-uart.txt b/dts/Bindings/serial/microchip,pic32-uart.txt
index 7a34345..c8dd440 100644
--- a/dts/Bindings/serial/microchip,pic32-uart.txt
+++ b/dts/Bindings/serial/microchip,pic32-uart.txt
@@ -8,7 +8,7 @@ Required properties:
See: Documentation/devicetree/bindings/clock/clock-bindings.txt
- pinctrl-names: A pinctrl state names "default" must be defined.
- pinctrl-0: Phandle referencing pin configuration of the UART peripheral.
- See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+ See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
Optional properties:
- cts-gpios: CTS pin for UART
diff --git a/dts/Bindings/soc/qcom/qcom,apr.txt b/dts/Bindings/soc/qcom/qcom,apr.txt
new file mode 100644
index 0000000..bcc612c
--- /dev/null
+++ b/dts/Bindings/soc/qcom/qcom,apr.txt
@@ -0,0 +1,84 @@
+Qualcomm APR (Asynchronous Packet Router) binding
+
+This binding describes the Qualcomm APR. APR is a IPC protocol for
+communication between Application processor and QDSP. APR is mainly
+used for audio/voice services on the QDSP.
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "qcom,apr-v<VERSION-NUMBER>", example "qcom,apr-v2"
+
+- reg
+ Usage: required
+ Value type: <u32>
+ Definition: Destination processor ID.
+ Possible values are :
+ 1 - APR simulator
+ 2 - PC
+ 3 - MODEM
+ 4 - ADSP
+ 5 - APPS
+ 6 - MODEM2
+ 7 - APPS2
+
+= APR SERVICES
+Each subnode of the APR node represents service tied to this apr. The name
+of the nodes are not important. The properties of these nodes are defined
+by the individual bindings for the specific service
+- All APR services MUST contain the following property:
+
+- reg
+ Usage: required
+ Value type: <u32>
+ Definition: APR Service ID
+ Possible values are :
+ 3 - DSP Core Service
+ 4 - Audio Front End Service.
+ 5 - Voice Stream Manager Service.
+ 6 - Voice processing manager.
+ 7 - Audio Stream Manager Service.
+ 8 - Audio Device Manager Service.
+ 9 - Multimode voice manager.
+ 10 - Core voice stream.
+ 11 - Core voice processor.
+ 12 - Ultrasound stream manager.
+ 13 - Listen stream manager.
+
+= EXAMPLE
+The following example represents a QDSP based sound card on a MSM8996 device
+which uses apr as communication between Apps and QDSP.
+
+ apr@4 {
+ compatible = "qcom,apr-v2";
+ reg = <APR_DOMAIN_ADSP>;
+
+ q6core@3 {
+ compatible = "qcom,q6core";
+ reg = <APR_SVC_ADSP_CORE>;
+ };
+
+ q6afe@4 {
+ compatible = "qcom,q6afe";
+ reg = <APR_SVC_AFE>;
+
+ dais {
+ #sound-dai-cells = <1>;
+ hdmi@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ q6asm@7 {
+ compatible = "qcom,q6asm";
+ reg = <APR_SVC_ASM>;
+ ...
+ };
+
+ q6adm@8 {
+ compatible = "qcom,q6adm";
+ reg = <APR_SVC_ADM>;
+ ...
+ };
+ };
diff --git a/dts/Bindings/soc/qcom/qcom,geni-se.txt b/dts/Bindings/soc/qcom/qcom,geni-se.txt
new file mode 100644
index 0000000..d330c73
--- /dev/null
+++ b/dts/Bindings/soc/qcom/qcom,geni-se.txt
@@ -0,0 +1,119 @@
+Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller
+
+Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
+is a programmable module for supporting a wide range of serial interfaces
+like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
+Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
+Wrapper controller is modeled as a node with zero or more child nodes each
+representing a serial engine.
+
+Required properties:
+- compatible: Must be "qcom,geni-se-qup".
+- reg: Must contain QUP register address and length.
+- clock-names: Must contain "m-ahb" and "s-ahb".
+- clocks: AHB clocks needed by the device.
+
+Required properties if child node exists:
+- #address-cells: Must be <1> for Serial Engine Address
+- #size-cells: Must be <1> for Serial Engine Address Size
+- ranges: Must be present
+
+Properties for children:
+
+A GENI based QUP wrapper controller node can contain 0 or more child nodes
+representing serial devices. These serial devices can be a QCOM UART, I2C
+controller, SPI controller, or some combination of aforementioned devices.
+Please refer below the child node definitions for the supported serial
+interface protocols.
+
+Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller
+
+Required properties:
+- compatible: Must be "qcom,geni-i2c".
+- reg: Must contain QUP register address and length.
+- interrupts: Must contain I2C interrupt.
+- clock-names: Must contain "se".
+- clocks: Serial engine core clock needed by the device.
+- #address-cells: Must be <1> for I2C device address.
+- #size-cells: Must be <0> as I2C addresses have no size component.
+
+Optional property:
+- clock-frequency: Desired I2C bus clock frequency in Hz.
+ When missing default to 400000Hz.
+
+Child nodes should conform to I2C bus binding as described in i2c.txt.
+
+Qualcomm Technologies Inc. GENI Serial Engine based UART Controller
+
+Required properties:
+- compatible: Must be "qcom,geni-debug-uart".
+- reg: Must contain UART register location and length.
+- interrupts: Must contain UART core interrupts.
+- clock-names: Must contain "se".
+- clocks: Serial engine core clock needed by the device.
+
+Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller
+
+Required properties:
+- compatible: Must contain "qcom,geni-spi".
+- reg: Must contain SPI register location and length.
+- interrupts: Must contain SPI controller interrupts.
+- clock-names: Must contain "se".
+- clocks: Serial engine core clock needed by the device.
+- spi-max-frequency: Specifies maximum SPI clock frequency, units - Hz.
+- #address-cells: Must be <1> to define a chip select address on
+ the SPI bus.
+- #size-cells: Must be <0>.
+
+SPI slave nodes must be children of the SPI master node and conform to SPI bus
+binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
+
+Example:
+ geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x8c0000 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ i2c0: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0xa94000 0x4000>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_i2c_5_active>;
+ pinctrl-1 = <&qup_1_i2c_5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ uart0: serial@a88000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0xa88000 0x7000>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_uart_3_active>;
+ pinctrl-1 = <&qup_1_uart_3_sleep>;
+ };
+
+ spi0: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0xa84000 0x4000>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_spi_2_active>;
+ pinctrl-1 = <&qup_1_spi_2_sleep>;
+ spi-max-frequency = <19200000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ }
diff --git a/dts/Bindings/soc/qcom/qcom,smd-rpm.txt b/dts/Bindings/soc/qcom/qcom,smd-rpm.txt
index a48049c..89e1cb9 100644
--- a/dts/Bindings/soc/qcom/qcom,smd-rpm.txt
+++ b/dts/Bindings/soc/qcom/qcom,smd-rpm.txt
@@ -22,6 +22,7 @@ resources.
"qcom,rpm-apq8084"
"qcom,rpm-msm8916"
"qcom,rpm-msm8974"
+ "qcom,rpm-msm8998"
- qcom,smd-channels:
Usage: required
diff --git a/dts/Bindings/soc/qcom/qcom,smd.txt b/dts/Bindings/soc/qcom/qcom,smd.txt
index ea1dc75..234ae22 100644
--- a/dts/Bindings/soc/qcom/qcom,smd.txt
+++ b/dts/Bindings/soc/qcom/qcom,smd.txt
@@ -22,9 +22,15 @@ The edge is described by the following properties:
Definition: should specify the IRQ used by the remote processor to
signal this processor about communication related updates
-- qcom,ipc:
+- mboxes:
Usage: required
Value type: <prop-encoded-array>
+ Definition: reference to the associated doorbell in APCS, as described
+ in mailbox/mailbox.txt
+
+- qcom,ipc:
+ Usage: required, unless mboxes is specified
+ Value type: <prop-encoded-array>
Definition: three entries specifying the outgoing ipc bit used for
signaling the remote processor:
- phandle to a syscon node representing the apcs registers
diff --git a/dts/Bindings/soc/rockchip/power_domain.txt b/dts/Bindings/soc/rockchip/power_domain.txt
index 301d2a9..5d49d0a 100644
--- a/dts/Bindings/soc/rockchip/power_domain.txt
+++ b/dts/Bindings/soc/rockchip/power_domain.txt
@@ -5,6 +5,10 @@ powered up/down by software based on different application scenes to save power.
Required properties for power domain controller:
- compatible: Should be one of the following.
+ "rockchip,px30-power-controller" - for PX30 SoCs.
+ "rockchip,rk3036-power-controller" - for RK3036 SoCs.
+ "rockchip,rk3128-power-controller" - for RK3128 SoCs.
+ "rockchip,rk3228-power-controller" - for RK3228 SoCs.
"rockchip,rk3288-power-controller" - for RK3288 SoCs.
"rockchip,rk3328-power-controller" - for RK3328 SoCs.
"rockchip,rk3366-power-controller" - for RK3366 SoCs.
@@ -17,6 +21,10 @@ Required properties for power domain controller:
Required properties for power domain sub nodes:
- reg: index of the power domain, should use macros in:
+ "include/dt-bindings/power/px30-power.h" - for PX30 type power domain.
+ "include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain.
+ "include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain.
+ "include/dt-bindings/power/rk3228-power.h" - for RK3228 type power domain.
"include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain.
"include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain.
"include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain.
@@ -93,6 +101,10 @@ Node of a device using power domains must have a power-domains property,
containing a phandle to the power device node and an index specifying which
power domain to use.
The index should use macros in:
+ "include/dt-bindings/power/px30-power.h" - for px30 type power domain.
+ "include/dt-bindings/power/rk3036-power.h" - for rk3036 type power domain.
+ "include/dt-bindings/power/rk3128-power.h" - for rk3128 type power domain.
+ "include/dt-bindings/power/rk3128-power.h" - for rk3228 type power domain.
"include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain.
"include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain.
"include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain.
diff --git a/dts/Bindings/soc/ti/keystone-navigator-qmss.txt b/dts/Bindings/soc/ti/keystone-navigator-qmss.txt
index 77cd42c..b025770 100644
--- a/dts/Bindings/soc/ti/keystone-navigator-qmss.txt
+++ b/dts/Bindings/soc/ti/keystone-navigator-qmss.txt
@@ -17,7 +17,8 @@ pool management.
Required properties:
-- compatible : Must be "ti,keystone-navigator-qmss";
+- compatible : Must be "ti,keystone-navigator-qmss".
+ : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
- clocks : phandle to the reference clock for this device.
- queue-range : <start number> total range of queue numbers for the device.
- linkram0 : <address size> for internal link ram, where size is the total
@@ -39,6 +40,12 @@ Required properties:
- Descriptor memory setup region.
- Queue Management/Queue Proxy region for queue Push.
- Queue Management/Queue Proxy region for queue Pop.
+
+For QMSS on K2G SoC, following QM reg indexes are used in that order
+ - Queue Peek region.
+ - Queue configuration region.
+ - Queue Management/Queue Proxy region for queue Push/Pop.
+
- queue-pools : child node classifying the queue ranges into pools.
Queue ranges are grouped into 3 type of pools:
- qpend : pool of qpend(interruptible) queues
diff --git a/dts/Bindings/sound/adi,ssm2305.txt b/dts/Bindings/sound/adi,ssm2305.txt
new file mode 100644
index 0000000..a9c9d83
--- /dev/null
+++ b/dts/Bindings/sound/adi,ssm2305.txt
@@ -0,0 +1,14 @@
+Analog Devices SSM2305 Speaker Amplifier
+========================================
+
+Required properties:
+ - compatible : "adi,ssm2305"
+ - shutdown-gpios : The gpio connected to the shutdown pin.
+ The gpio signal is ACTIVE_LOW.
+
+Example:
+
+ssm2305: analog-amplifier {
+ compatible = "adi,ssm2305";
+ shutdown-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/Bindings/sound/atmel-i2s.txt b/dts/Bindings/sound/atmel-i2s.txt
new file mode 100644
index 0000000..735368b
--- /dev/null
+++ b/dts/Bindings/sound/atmel-i2s.txt
@@ -0,0 +1,47 @@
+* Atmel I2S controller
+
+Required properties:
+- compatible: Should be "atmel,sama5d2-i2s".
+- reg: Should be the physical base address of the controller and the
+ length of memory mapped region.
+- interrupts: Should contain the interrupt for the controller.
+- dmas: Should be one per channel name listed in the dma-names property,
+ as described in atmel-dma.txt and dma.txt files.
+- dma-names: Two dmas have to be defined, "tx" and "rx".
+ This IP also supports one shared channel for both rx and tx;
+ if this mode is used, one "rx-tx" name must be used.
+- clocks: Must contain an entry for each entry in clock-names.
+ Please refer to clock-bindings.txt.
+- clock-names: Should be one of each entry matching the clocks phandles list:
+ - "pclk" (peripheral clock) Required.
+ - "gclk" (generated clock) Optional (1).
+ - "aclk" (Audio PLL clock) Optional (1).
+ - "muxclk" (I2S mux clock) Optional (1).
+
+Optional properties:
+- pinctrl-0: Should specify pin control groups used for this controller.
+- princtrl-names: Should contain only one value - "default".
+
+
+(1) : Only the peripheral clock is required. The generated clock, the Audio
+ PLL clock adn the I2S mux clock are optional and should only be set
+ together, when Master Mode is required.
+
+Example:
+
+ i2s@f8050000 {
+ compatible = "atmel,sama5d2-i2s";
+ reg = <0xf8050000 0x300>;
+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(31))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(32))>;
+ dma-names = "tx", "rx";
+ clocks = <&i2s0_clk>, <&i2s0_gclk>, <&audio_pll_pmc>, <&i2s0muxck>;
+ clock-names = "pclk", "gclk", "aclk", "muxclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2s0_default>;
+ };
diff --git a/dts/Bindings/sound/cs42xx8.txt b/dts/Bindings/sound/cs42xx8.txt
index f631fbc..8619a15 100644
--- a/dts/Bindings/sound/cs42xx8.txt
+++ b/dts/Bindings/sound/cs42xx8.txt
@@ -16,7 +16,7 @@ Required properties:
Example:
-codec: cs42888@48 {
+cs42888: codec@48 {
compatible = "cirrus,cs42888";
reg = <0x48>;
clocks = <&codec_mclk 0>;
diff --git a/dts/Bindings/sound/fsl,asrc.txt b/dts/Bindings/sound/fsl,asrc.txt
index f5a1411..1d4d9f9 100644
--- a/dts/Bindings/sound/fsl,asrc.txt
+++ b/dts/Bindings/sound/fsl,asrc.txt
@@ -31,14 +31,16 @@ Required properties:
it. This property is optional depending on the SoC
design.
- - big-endian : If this property is absent, the little endian mode
- will be in use as default. Otherwise, the big endian
- mode will be in use for all the device registers.
-
- fsl,asrc-rate : Defines a mutual sample rate used by DPCM Back Ends.
- fsl,asrc-width : Defines a mutual sample width used by DPCM Back Ends.
+Optional properties:
+
+ - big-endian : If this property is absent, the little endian mode
+ will be in use as default. Otherwise, the big endian
+ mode will be in use for all the device registers.
+
Example:
asrc: asrc@2034000 {
diff --git a/dts/Bindings/sound/fsl,esai.txt b/dts/Bindings/sound/fsl,esai.txt
index cacd18b..5b99143 100644
--- a/dts/Bindings/sound/fsl,esai.txt
+++ b/dts/Bindings/sound/fsl,esai.txt
@@ -42,6 +42,8 @@ Required properties:
means all the settings for Receiving would be
duplicated from Transmition related registers.
+Optional properties:
+
- big-endian : If this property is absent, the native endian mode
will be in use as default, or the big endian mode
will be in use for all the device registers.
diff --git a/dts/Bindings/sound/fsl,spdif.txt b/dts/Bindings/sound/fsl,spdif.txt
index 38cfa75..8b324f8 100644
--- a/dts/Bindings/sound/fsl,spdif.txt
+++ b/dts/Bindings/sound/fsl,spdif.txt
@@ -33,6 +33,8 @@ Required properties:
it. This property is optional depending on the SoC
design.
+Optional properties:
+
- big-endian : If this property is absent, the native endian mode
will be in use as default, or the big endian mode
will be in use for all the device registers.
diff --git a/dts/Bindings/sound/fsl-sai.txt b/dts/Bindings/sound/fsl-sai.txt
index 740b467..dd9e597 100644
--- a/dts/Bindings/sound/fsl-sai.txt
+++ b/dts/Bindings/sound/fsl-sai.txt
@@ -28,9 +28,6 @@ Required properties:
pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
for details of the property values.
- - big-endian : Boolean property, required if all the FTM_PWM
- registers are big-endian rather than little-endian.
-
- lsb-first : Configures whether the LSB or the MSB is transmitted
first for the fifo data. If this property is absent,
the MSB is transmitted first as default, or the LSB
@@ -48,6 +45,11 @@ Required properties:
receive data by following their own bit clocks and
frame sync clocks separately.
+Optional properties:
+
+ - big-endian : Boolean property, required if all the SAI
+ registers are big-endian rather than little-endian.
+
Optional properties (for mx6ul):
- fsl,sai-mclk-direction-output: This is a boolean property. If present,
diff --git a/dts/Bindings/sound/mt2701-afe-pcm.txt b/dts/Bindings/sound/mt2701-afe-pcm.txt
index e2f7f49..560762e 100644
--- a/dts/Bindings/sound/mt2701-afe-pcm.txt
+++ b/dts/Bindings/sound/mt2701-afe-pcm.txt
@@ -1,7 +1,9 @@
Mediatek AFE PCM controller for mt2701
Required properties:
-- compatible = "mediatek,mt2701-audio";
+- compatible: should be one of the followings.
+ - "mediatek,mt2701-audio"
+ - "mediatek,mt7622-audio"
- interrupts: should contain AFE and ASYS interrupts
- interrupt-names: should be "afe" and "asys"
- power-domains: should define the power domain
diff --git a/dts/Bindings/sound/mt6351.txt b/dts/Bindings/sound/mt6351.txt
new file mode 100644
index 0000000..7fb2cb9
--- /dev/null
+++ b/dts/Bindings/sound/mt6351.txt
@@ -0,0 +1,16 @@
+Mediatek MT6351 Audio Codec
+
+The communication between MT6351 and SoC is through Mediatek PMIC wrapper.
+For more detail, please visit Mediatek PMIC wrapper documentation.
+
+Must be a child node of PMIC wrapper.
+
+Required properties:
+
+- compatible : "mediatek,mt6351-sound".
+
+Example:
+
+mt6351_snd {
+ compatible = "mediatek,mt6351-sound";
+};
diff --git a/dts/Bindings/sound/mt6797-afe-pcm.txt b/dts/Bindings/sound/mt6797-afe-pcm.txt
new file mode 100644
index 0000000..0ae29de
--- /dev/null
+++ b/dts/Bindings/sound/mt6797-afe-pcm.txt
@@ -0,0 +1,42 @@
+Mediatek AFE PCM controller for mt6797
+
+Required properties:
+- compatible = "mediatek,mt6797-audio";
+- reg: register location and size
+- interrupts: should contain AFE interrupt
+- power-domains: should define the power domain
+- clocks: Must contain an entry for each entry in clock-names
+- clock-names: should have these clock names:
+ "infra_sys_audio_clk",
+ "infra_sys_audio_26m",
+ "mtkaif_26m_clk",
+ "top_mux_audio",
+ "top_mux_aud_intbus",
+ "top_sys_pll3_d4",
+ "top_sys_pll1_d4",
+ "top_clk26m_clk";
+
+Example:
+
+ afe: mt6797-afe-pcm@11220000 {
+ compatible = "mediatek,mt6797-audio";
+ reg = <0 0x11220000 0 0x1000>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT6797_POWER_DOMAIN_AUDIO>;
+ clocks = <&infrasys CLK_INFRA_AUDIO>,
+ <&infrasys CLK_INFRA_AUDIO_26M>,
+ <&infrasys CLK_INFRA_AUDIO_26M_PAD_TOP>,
+ <&topckgen CLK_TOP_MUX_AUDIO>,
+ <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
+ <&topckgen CLK_TOP_SYSPLL3_D4>,
+ <&topckgen CLK_TOP_SYSPLL1_D4>,
+ <&clk26m>;
+ clock-names = "infra_sys_audio_clk",
+ "infra_sys_audio_26m",
+ "mtkaif_26m_clk",
+ "top_mux_audio",
+ "top_mux_aud_intbus",
+ "top_sys_pll3_d4",
+ "top_sys_pll1_d4",
+ "top_clk26m_clk";
+ };
diff --git a/dts/Bindings/sound/mt6797-mt6351.txt b/dts/Bindings/sound/mt6797-mt6351.txt
new file mode 100644
index 0000000..1d95a88
--- /dev/null
+++ b/dts/Bindings/sound/mt6797-mt6351.txt
@@ -0,0 +1,14 @@
+MT6797 with MT6351 CODEC
+
+Required properties:
+- compatible: "mediatek,mt6797-mt6351-sound"
+- mediatek,platform: the phandle of MT6797 ASoC platform
+- mediatek,audio-codec: the phandles of MT6351 codec
+
+Example:
+
+ sound {
+ compatible = "mediatek,mt6797-mt6351-sound";
+ mediatek,audio-codec = <&mt6351_snd>;
+ mediatek,platform = <&afe>;
+ };
diff --git a/dts/Bindings/sound/qcom,apq8096.txt b/dts/Bindings/sound/qcom,apq8096.txt
new file mode 100644
index 0000000..aa54e49
--- /dev/null
+++ b/dts/Bindings/sound/qcom,apq8096.txt
@@ -0,0 +1,109 @@
+* Qualcomm Technologies APQ8096 ASoC sound card driver
+
+This binding describes the APQ8096 sound card, which uses qdsp for audio.
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "qcom,apq8096-sndcard"
+
+- qcom,audio-routing:
+ Usage: Optional
+ Value type: <stringlist>
+ Definition: A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the
+ connection's sink, the second being the connection's
+ source. Valid names could be power supplies, MicBias
+ of codec and the jacks on the board:
+ Valid names include:
+
+ Board Connectors:
+ "Headphone Left"
+ "Headphone Right"
+ "Earphone"
+ "Line Out1"
+ "Line Out2"
+ "Line Out3"
+ "Line Out4"
+ "Analog Mic1"
+ "Analog Mic2"
+ "Analog Mic3"
+ "Analog Mic4"
+ "Analog Mic5"
+ "Analog Mic6"
+ "Digital Mic2"
+ "Digital Mic3"
+
+ Audio pins and MicBias on WCD9335 Codec:
+ "MIC_BIAS1
+ "MIC_BIAS2"
+ "MIC_BIAS3"
+ "MIC_BIAS4"
+ "AMIC1"
+ "AMIC2"
+ "AMIC3"
+ "AMIC4"
+ "AMIC5"
+ "AMIC6"
+ "AMIC6"
+ "DMIC1"
+ "DMIC2"
+ "DMIC3"
+= dailinks
+Each subnode of sndcard represents either a dailink, and subnodes of each
+dailinks would be cpu/codec/platform dais.
+
+- link-name:
+ Usage: required
+ Value type: <string>
+ Definition: User friendly name for dai link
+
+= CPU, PLATFORM, CODEC dais subnodes
+- cpu:
+ Usage: required
+ Value type: <subnode>
+ Definition: cpu dai sub-node
+
+- codec:
+ Usage: Optional
+ Value type: <subnode>
+ Definition: codec dai sub-node
+
+- platform:
+ Usage: Optional
+ Value type: <subnode>
+ Definition: platform dai sub-node
+
+- sound-dai:
+ Usage: required
+ Value type: <phandle with arguments>
+ Definition: dai phandle/s and port of CPU/CODEC/PLATFORM node.
+
+Example:
+
+audio {
+ compatible = "qcom,apq8096-sndcard";
+ qcom,model = "DB820c";
+
+ mm1-dai-link {
+ link-name = "MultiMedia1";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+ };
+ };
+
+ hdmi-dai-link {
+ link-name = "HDMI Playback";
+ cpu {
+ sound-dai = <&q6afe HDMI_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6adm>;
+ };
+
+ codec {
+ sound-dai = <&hdmi 0>;
+ };
+ };
+};
diff --git a/dts/Bindings/sound/qcom,q6adm.txt b/dts/Bindings/sound/qcom,q6adm.txt
new file mode 100644
index 0000000..cb709e5
--- /dev/null
+++ b/dts/Bindings/sound/qcom,q6adm.txt
@@ -0,0 +1,33 @@
+Qualcomm Audio Device Manager (Q6ADM) binding
+
+Q6ADM is one of the APR audio service on Q6DSP.
+Please refer to qcom,apr.txt for details of the coommon apr service bindings
+used by the apr service device.
+
+- but must contain the following property:
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "qcom,q6adm-v<MAJOR-NUMBER>.<MINOR-NUMBER>".
+ Or "qcom,q6adm" where the version number can be queried
+ from DSP.
+ example "qcom,q6adm-v2.0"
+
+
+= ADM routing
+"routing" subnode of the ADM node represents adm routing specific configuration
+
+- #sound-dai-cells
+ Usage: required
+ Value type: <u32>
+ Definition: Must be 0
+
+= EXAMPLE
+q6adm@8 {
+ compatible = "qcom,q6adm";
+ reg = <APR_SVC_ADM>;
+ q6routing: routing {
+ #sound-dai-cells = <0>;
+ };
+};
diff --git a/dts/Bindings/sound/qcom,q6afe.txt b/dts/Bindings/sound/qcom,q6afe.txt
new file mode 100644
index 0000000..bdbf87d
--- /dev/null
+++ b/dts/Bindings/sound/qcom,q6afe.txt
@@ -0,0 +1,172 @@
+Qualcomm Audio Front End (Q6AFE) binding
+
+AFE is one of the APR audio service on Q6DSP
+Please refer to qcom,apr.txt for details of the common apr service bindings
+used by all apr services. Must contain the following properties.
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "qcom,q6afe-v<MAJOR-NUMBER>.<MINOR-NUMBER>"
+ Or "qcom,q6afe" where the version number can be queried
+ from DSP.
+ example "qcom,q6afe"
+
+= AFE DAIs (Digial Audio Interface)
+"dais" subnode of the AFE node. It represents afe dais, each afe dai is a
+subnode of "dais" representing board specific dai setup.
+"dais" node should have following properties followed by dai children.
+
+- #sound-dai-cells
+ Usage: required
+ Value type: <u32>
+ Definition: Must be 1
+
+- #address-cells
+ Usage: required
+ Value type: <u32>
+ Definition: Must be 1
+
+- #size-cells
+ Usage: required
+ Value type: <u32>
+ Definition: Must be 0
+
+== AFE DAI is subnode of "dais" and represent a dai, it includes board specific
+configuration of each dai. Must contain the following properties.
+
+- reg
+ Usage: required
+ Value type: <u32>
+ Definition: Must be dai id
+
+- qcom,sd-lines
+ Usage: required for mi2s interface
+ Value type: <prop-encoded-array>
+ Definition: Must be list of serial data lines used by this dai.
+ should be one or more of the 1-4 sd lines.
+
+ - qcom,tdm-sync-mode:
+ Usage: required for tdm interface
+ Value type: <prop-encoded-array>
+ Definition: Synchronization mode.
+ 0 - Short sync bit mode
+ 1 - Long sync mode
+ 2 - Short sync slot mode
+
+ - qcom,tdm-sync-src:
+ Usage: required for tdm interface
+ Value type: <prop-encoded-array>
+ Definition: Synchronization source.
+ 0 - External source
+ 1 - Internal source
+
+ - qcom,tdm-data-out:
+ Usage: required for tdm interface
+ Value type: <prop-encoded-array>
+ Definition: Data out signal to drive with other masters.
+ 0 - Disable
+ 1 - Enable
+
+ - qcom,tdm-invert-sync:
+ Usage: required for tdm interface
+ Value type: <prop-encoded-array>
+ Definition: Invert the sync.
+ 0 - Normal
+ 1 - Invert
+
+ - qcom,tdm-data-delay:
+ Usage: required for tdm interface
+ Value type: <prop-encoded-array>
+ Definition: Number of bit clock to delay data
+ with respect to sync edge.
+ 0 - 0 bit clock cycle
+ 1 - 1 bit clock cycle
+ 2 - 2 bit clock cycle
+
+ - qcom,tdm-data-align:
+ Usage: required for tdm interface
+ Value type: <prop-encoded-array>
+ Definition: Indicate how data is packed
+ within the slot. For example, 32 slot width in case of
+ sample bit width is 24.
+ 0 - MSB
+ 1 - LSB
+
+= EXAMPLE
+
+q6afe@4 {
+ compatible = "qcom,q6afe";
+ reg = <APR_SVC_AFE>;
+
+ dais {
+ #sound-dai-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi@1 {
+ reg = <1>;
+ };
+
+ tdm@24 {
+ reg = <24>;
+ qcom,tdm-sync-mode = <1>:
+ qcom,tdm-sync-src = <1>;
+ qcom,tdm-data-out = <0>;
+ qcom,tdm-invert-sync = <1>;
+ qcom,tdm-data-delay = <1>;
+ qcom,tdm-data-align = <0>;
+
+ };
+
+ tdm@25 {
+ reg = <25>;
+ qcom,tdm-sync-mode = <1>:
+ qcom,tdm-sync-src = <1>;
+ qcom,tdm-data-out = <0>;
+ qcom,tdm-invert-sync = <1>;
+ qcom,tdm-data-delay <1>:
+ qcom,tdm-data-align = <0>;
+ };
+
+ prim-mi2s-rx@16 {
+ reg = <16>;
+ qcom,sd-lines = <1 3>;
+ };
+
+ prim-mi2s-tx@17 {
+ reg = <17>;
+ qcom,sd-lines = <2>;
+ };
+
+ sec-mi2s-rx@18 {
+ reg = <18>;
+ qcom,sd-lines = <1 4>;
+ };
+
+ sec-mi2s-tx@19 {
+ reg = <19>;
+ qcom,sd-lines = <2>;
+ };
+
+ tert-mi2s-rx@20 {
+ reg = <20>;
+ qcom,sd-lines = <2 4>;
+ };
+
+ tert-mi2s-tx@21 {
+ reg = <21>;
+ qcom,sd-lines = <1>;
+ };
+
+ quat-mi2s-rx@22 {
+ reg = <22>;
+ qcom,sd-lines = <1>;
+ };
+
+ quat-mi2s-tx@23 {
+ reg = <23>;
+ qcom,sd-lines = <2>;
+ };
+ };
+};
diff --git a/dts/Bindings/sound/qcom,q6asm.txt b/dts/Bindings/sound/qcom,q6asm.txt
new file mode 100644
index 0000000..2178eb9
--- /dev/null
+++ b/dts/Bindings/sound/qcom,q6asm.txt
@@ -0,0 +1,33 @@
+Qualcomm Audio Stream Manager (Q6ASM) binding
+
+Q6ASM is one of the APR audio service on Q6DSP.
+Please refer to qcom,apr.txt for details of the common apr service bindings
+used by the apr service device.
+
+- but must contain the following property:
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "qcom,q6asm-v<MAJOR-NUMBER>.<MINOR-NUMBER>".
+ Or "qcom,q6asm" where the version number can be queried
+ from DSP.
+ example "qcom,q6asm-v2.0"
+
+= ASM DAIs (Digial Audio Interface)
+"dais" subnode of the ASM node represents dai specific configuration
+
+- #sound-dai-cells
+ Usage: required
+ Value type: <u32>
+ Definition: Must be 1
+
+= EXAMPLE
+
+q6asm@7 {
+ compatible = "qcom,q6asm";
+ reg = <APR_SVC_ASM>;
+ q6asmdai: dais {
+ #sound-dai-cells = <1>;
+ };
+};
diff --git a/dts/Bindings/sound/qcom,q6core.txt b/dts/Bindings/sound/qcom,q6core.txt
new file mode 100644
index 0000000..7f36ff8
--- /dev/null
+++ b/dts/Bindings/sound/qcom,q6core.txt
@@ -0,0 +1,21 @@
+Qualcomm ADSP Core service binding
+
+Q6CORE is one of the APR audio service on Q6DSP.
+Please refer to qcom,apr.txt for details of the common apr service bindings
+used by the apr service device.
+
+- but must contain the following property:
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "qcom,q6core-v<MAJOR-NUMBER>.<MINOR-NUMBER>".
+ Or "qcom,q6core" where the version number can be queried
+ from DSP.
+ example "qcom,q6core-v2.0"
+
+= EXAMPLE
+q6core@3 {
+ compatible = "qcom,q6core";
+ reg = <APR_SVC_ADSP_CORE>;
+};
diff --git a/dts/Bindings/sound/rt274.txt b/dts/Bindings/sound/rt274.txt
index e9a6178..791a1bd 100644
--- a/dts/Bindings/sound/rt274.txt
+++ b/dts/Bindings/sound/rt274.txt
@@ -26,7 +26,7 @@ Pins on the device (for linking into audio routes) for RT274:
Example:
-codec: rt274@1c {
+rt274: codec@1c {
compatible = "realtek,rt274";
reg = <0x1c>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
diff --git a/dts/Bindings/sound/rt5514.txt b/dts/Bindings/sound/rt5514.txt
index 4f33b0d..b25ed08 100644
--- a/dts/Bindings/sound/rt5514.txt
+++ b/dts/Bindings/sound/rt5514.txt
@@ -32,7 +32,7 @@ Pins on the device (for linking into audio routes) for I2C:
Example:
-codec: rt5514@57 {
+rt5514: codec@57 {
compatible = "realtek,rt5514";
reg = <0x57>;
};
diff --git a/dts/Bindings/sound/rt5616.txt b/dts/Bindings/sound/rt5616.txt
index e410858..540a4bf 100644
--- a/dts/Bindings/sound/rt5616.txt
+++ b/dts/Bindings/sound/rt5616.txt
@@ -26,7 +26,7 @@ Pins on the device (for linking into audio routes) for RT5616:
Example:
-codec: rt5616@1b {
+rt5616: codec@1b {
compatible = "realtek,rt5616";
reg = <0x1b>;
};
diff --git a/dts/Bindings/sound/rt5640.txt b/dts/Bindings/sound/rt5640.txt
index 57fe646..e40e489 100644
--- a/dts/Bindings/sound/rt5640.txt
+++ b/dts/Bindings/sound/rt5640.txt
@@ -22,6 +22,41 @@ Optional properties:
- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
+- realtek,dmic1-data-pin
+ 0: dmic1 is not used
+ 1: using IN1P pin as dmic1 data pin
+ 2: using GPIO3 pin as dmic1 data pin
+
+- realtek,dmic2-data-pin
+ 0: dmic2 is not used
+ 1: using IN1N pin as dmic2 data pin
+ 2: using GPIO4 pin as dmic2 data pin
+
+- realtek,jack-detect-source
+ u32. Valid values:
+ 0: jack-detect is not used
+ 1: Use GPIO1 for jack-detect
+ 2: Use JD1_IN4P for jack-detect
+ 3: Use JD2_IN4N for jack-detect
+ 4: Use GPIO2 for jack-detect
+ 5: Use GPIO3 for jack-detect
+ 6: Use GPIO4 for jack-detect
+
+- realtek,jack-detect-not-inverted
+ bool. Normal jack-detect switches give an inverted signal, set this bool
+ in the rare case you've a jack-detect switch which is not inverted.
+
+- realtek,over-current-threshold-microamp
+ u32, micbias over-current detection threshold in µA, valid values are
+ 600, 1500 and 2000µA.
+
+- realtek,over-current-scale-factor
+ u32, micbias over-current detection scale-factor, valid values are:
+ 0: Scale current by 0.5
+ 1: Scale current by 0.75
+ 2: Scale current by 1.0
+ 3: Scale current by 1.5
+
Pins on the device (for linking into audio routes) for RT5639/RT5640:
* DMIC1
diff --git a/dts/Bindings/sound/rt5645.txt b/dts/Bindings/sound/rt5645.txt
index 7cee1f5..a03f9a8 100644
--- a/dts/Bindings/sound/rt5645.txt
+++ b/dts/Bindings/sound/rt5645.txt
@@ -69,4 +69,4 @@ codec: rt5650@1a {
realtek,dmic-en = "true";
realtek,en-jd-func = "true";
realtek,jd-mode = <3>;
-}; \ No newline at end of file
+};
diff --git a/dts/Bindings/sound/rt5651.txt b/dts/Bindings/sound/rt5651.txt
index b852218..a41199a 100644
--- a/dts/Bindings/sound/rt5651.txt
+++ b/dts/Bindings/sound/rt5651.txt
@@ -50,7 +50,7 @@ Pins on the device (for linking into audio routes) for RT5651:
Example:
-codec: rt5651@1a {
+rt5651: codec@1a {
compatible = "realtek,rt5651";
reg = <0x1a>;
realtek,dmic-en = "true";
diff --git a/dts/Bindings/sound/rt5663.txt b/dts/Bindings/sound/rt5663.txt
index 497bcfc..2338644 100644
--- a/dts/Bindings/sound/rt5663.txt
+++ b/dts/Bindings/sound/rt5663.txt
@@ -47,7 +47,7 @@ Pins on the device (for linking into audio routes) for RT5663:
Example:
-codec: rt5663@12 {
+rt5663: codec@12 {
compatible = "realtek,rt5663";
reg = <0x12>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
diff --git a/dts/Bindings/sound/rt5668.txt b/dts/Bindings/sound/rt5668.txt
new file mode 100644
index 0000000..c88b96e
--- /dev/null
+++ b/dts/Bindings/sound/rt5668.txt
@@ -0,0 +1,50 @@
+RT5668B audio CODEC
+
+This device supports I2C only.
+
+Required properties:
+
+- compatible : "realtek,rt5668b"
+
+- reg : The I2C address of the device.
+
+Optional properties:
+
+- interrupts : The CODEC's interrupt output.
+
+- realtek,dmic1-data-pin
+ 0: dmic1 is not used
+ 1: using GPIO2 pin as dmic1 data pin
+ 2: using GPIO5 pin as dmic1 data pin
+
+- realtek,dmic1-clk-pin
+ 0: using GPIO1 pin as dmic1 clock pin
+ 1: using GPIO3 pin as dmic1 clock pin
+
+- realtek,jd-src
+ 0: No JD is used
+ 1: using JD1 as JD source
+
+- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
+
+Pins on the device (for linking into audio routes) for RT5668B:
+
+ * DMIC L1
+ * DMIC R1
+ * IN1P
+ * HPOL
+ * HPOR
+
+Example:
+
+rt5668 {
+ compatible = "realtek,rt5668b";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
+ realtek,ldo1-en-gpios =
+ <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ realtek,dmic1-data-pin = <1>;
+ realtek,dmic1-clk-pin = <1>;
+ realtek,jd-src = <1>;
+};
diff --git a/dts/Bindings/sound/sgtl5000.txt b/dts/Bindings/sound/sgtl5000.txt
index 9a36c7e..0f21445 100644
--- a/dts/Bindings/sound/sgtl5000.txt
+++ b/dts/Bindings/sound/sgtl5000.txt
@@ -39,7 +39,7 @@ VDDIO 1.8V 2.5V 3.3V
Example:
-codec: sgtl5000@a {
+sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
diff --git a/dts/Bindings/sound/simple-card.txt b/dts/Bindings/sound/simple-card.txt
index 17c13e7..a4c72d0 100644
--- a/dts/Bindings/sound/simple-card.txt
+++ b/dts/Bindings/sound/simple-card.txt
@@ -86,6 +86,11 @@ Optional CPU/CODEC subnodes properties:
in dai startup() and disabled with
clk_disable_unprepare() in dai
shutdown().
+ If a clock is specified and a
+ multiplication factor is given with
+ mclk-fs, the clock will be set to the
+ calculated mclk frequency when the
+ stream starts.
- system-clock-direction-out : specifies clock direction as 'out' on
initialization. It is useful for some aCPUs with
fixed clocks.
diff --git a/dts/Bindings/sound/st,stm32-i2s.txt b/dts/Bindings/sound/st,stm32-i2s.txt
index 4bda520..58c3413 100644
--- a/dts/Bindings/sound/st,stm32-i2s.txt
+++ b/dts/Bindings/sound/st,stm32-i2s.txt
@@ -18,7 +18,7 @@ Required properties:
See Documentation/devicetree/bindings/dma/stm32-dma.txt.
- dma-names: Identifier for each DMA request line. Must be "tx" and "rx".
- pinctrl-names: should contain only value "default"
- - pinctrl-0: see Documentation/devicetree/bindings/pinctrl/pinctrl-stm32.txt
+ - pinctrl-0: see Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
Optional properties:
- resets: Reference to a reset controller asserting the reset controller
diff --git a/dts/Bindings/sound/st,stm32-sai.txt b/dts/Bindings/sound/st,stm32-sai.txt
index f301cdf..3a3fc50 100644
--- a/dts/Bindings/sound/st,stm32-sai.txt
+++ b/dts/Bindings/sound/st,stm32-sai.txt
@@ -37,7 +37,7 @@ SAI subnodes required properties:
"tx": if sai sub-block is configured as playback DAI
"rx": if sai sub-block is configured as capture DAI
- pinctrl-names: should contain only value "default"
- - pinctrl-0: see Documentation/devicetree/bindings/pinctrl/pinctrl-stm32.txt
+ - pinctrl-0: see Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
SAI subnodes Optional properties:
- st,sync: specify synchronization mode.
diff --git a/dts/Bindings/sound/ti,tas6424.txt b/dts/Bindings/sound/ti,tas6424.txt
index 1c4ada0..eacb54f 100644
--- a/dts/Bindings/sound/ti,tas6424.txt
+++ b/dts/Bindings/sound/ti,tas6424.txt
@@ -6,6 +6,8 @@ Required properties:
- compatible: "ti,tas6424" - TAS6424
- reg: I2C slave address
- sound-dai-cells: must be equal to 0
+ - standby-gpios: GPIO used to shut the TAS6424 down.
+ - mute-gpios: GPIO used to mute all the outputs
Example:
diff --git a/dts/Bindings/sound/tscs42xx.txt b/dts/Bindings/sound/tscs42xx.txt
index 2ac2f09..7eea32e 100644
--- a/dts/Bindings/sound/tscs42xx.txt
+++ b/dts/Bindings/sound/tscs42xx.txt
@@ -8,9 +8,15 @@ Required Properties:
- reg : <0x71> for analog mic
<0x69> for digital mic
+ - clock-names: Must one of the following "mclk1", "xtal", "mclk2"
+
+ - clocks: phandle of the clock that provides the codec sysclk
+
Example:
wookie: codec@69 {
compatible = "tempo,tscs42A2";
reg = <0x69>;
+ clock-names = "xtal";
+ clocks = <&audio_xtal>;
};
diff --git a/dts/Bindings/sound/tscs454.txt b/dts/Bindings/sound/tscs454.txt
new file mode 100644
index 0000000..3ba3e2d
--- /dev/null
+++ b/dts/Bindings/sound/tscs454.txt
@@ -0,0 +1,23 @@
+TSCS454 Audio CODEC
+
+Required Properties:
+
+ - compatible : "tempo,tscs454"
+
+ - reg : <0x69>
+
+ - clock-names: Must one of the following "xtal", "mclk1", "mclk2"
+
+ - clocks: phandle of the clock that provides the codec sysclk
+
+ Note: If clock is not provided then bit clock is assumed
+
+Example:
+
+redwood: codec@69 {
+ #sound-dai-cells = <1>;
+ compatible = "tempo,tscs454";
+ reg = <0x69>;
+ clock-names = "mclk1";
+ clocks = <&audio_mclk>;
+};
diff --git a/dts/Bindings/sound/wm8510.txt b/dts/Bindings/sound/wm8510.txt
index fa1a32b..e6b6cc0 100644
--- a/dts/Bindings/sound/wm8510.txt
+++ b/dts/Bindings/sound/wm8510.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-codec: wm8510@1a {
+wm8510: codec@1a {
compatible = "wlf,wm8510";
reg = <0x1a>;
};
diff --git a/dts/Bindings/sound/wm8523.txt b/dts/Bindings/sound/wm8523.txt
index 0474618..f3a6485 100644
--- a/dts/Bindings/sound/wm8523.txt
+++ b/dts/Bindings/sound/wm8523.txt
@@ -10,7 +10,7 @@ Required properties:
Example:
-codec: wm8523@1a {
+wm8523: codec@1a {
compatible = "wlf,wm8523";
reg = <0x1a>;
};
diff --git a/dts/Bindings/sound/wm8524.txt b/dts/Bindings/sound/wm8524.txt
index 0f05535..f6c0c26 100644
--- a/dts/Bindings/sound/wm8524.txt
+++ b/dts/Bindings/sound/wm8524.txt
@@ -10,7 +10,7 @@ Required properties:
Example:
-codec: wm8524 {
+wm8524: codec {
compatible = "wlf,wm8524";
wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/Bindings/sound/wm8580.txt b/dts/Bindings/sound/wm8580.txt
index 78fce9b..ff3f9f5 100644
--- a/dts/Bindings/sound/wm8580.txt
+++ b/dts/Bindings/sound/wm8580.txt
@@ -10,7 +10,7 @@ Required properties:
Example:
-codec: wm8580@1a {
+wm8580: codec@1a {
compatible = "wlf,wm8580";
reg = <0x1a>;
};
diff --git a/dts/Bindings/sound/wm8711.txt b/dts/Bindings/sound/wm8711.txt
index 8ed9998..c30a138 100644
--- a/dts/Bindings/sound/wm8711.txt
+++ b/dts/Bindings/sound/wm8711.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-codec: wm8711@1a {
+wm8711: codec@1a {
compatible = "wlf,wm8711";
reg = <0x1a>;
};
diff --git a/dts/Bindings/sound/wm8728.txt b/dts/Bindings/sound/wm8728.txt
index a8b5c36..a3608b4 100644
--- a/dts/Bindings/sound/wm8728.txt
+++ b/dts/Bindings/sound/wm8728.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-codec: wm8728@1a {
+wm8728: codec@1a {
compatible = "wlf,wm8728";
reg = <0x1a>;
};
diff --git a/dts/Bindings/sound/wm8731.txt b/dts/Bindings/sound/wm8731.txt
index 236690e..f660d9b 100644
--- a/dts/Bindings/sound/wm8731.txt
+++ b/dts/Bindings/sound/wm8731.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-codec: wm8731@1a {
+wm8731: codec@1a {
compatible = "wlf,wm8731";
reg = <0x1a>;
};
diff --git a/dts/Bindings/sound/wm8737.txt b/dts/Bindings/sound/wm8737.txt
index 4bc2cea..eda1ec6 100644
--- a/dts/Bindings/sound/wm8737.txt
+++ b/dts/Bindings/sound/wm8737.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-codec: wm8737@1a {
+wm8737: codec@1a {
compatible = "wlf,wm8737";
reg = <0x1a>;
};
diff --git a/dts/Bindings/sound/wm8741.txt b/dts/Bindings/sound/wm8741.txt
index a133154..b69e196 100644
--- a/dts/Bindings/sound/wm8741.txt
+++ b/dts/Bindings/sound/wm8741.txt
@@ -21,7 +21,7 @@ Optional properties:
Example:
-codec: wm8741@1a {
+wm8741: codec@1a {
compatible = "wlf,wm8741";
reg = <0x1a>;
diff --git a/dts/Bindings/sound/wm8750.txt b/dts/Bindings/sound/wm8750.txt
index 8db239f..682f221 100644
--- a/dts/Bindings/sound/wm8750.txt
+++ b/dts/Bindings/sound/wm8750.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-codec: wm8750@1a {
+wm8750: codec@1a {
compatible = "wlf,wm8750";
reg = <0x1a>;
};
diff --git a/dts/Bindings/sound/wm8753.txt b/dts/Bindings/sound/wm8753.txt
index 8eee612..eca9e5a 100644
--- a/dts/Bindings/sound/wm8753.txt
+++ b/dts/Bindings/sound/wm8753.txt
@@ -34,7 +34,7 @@ Pins on the device (for linking into audio routes):
Example:
-codec: wm8753@1a {
+wm8753: codec@1a {
compatible = "wlf,wm8753";
reg = <0x1a>;
};
diff --git a/dts/Bindings/sound/wm8770.txt b/dts/Bindings/sound/wm8770.txt
index 866e00c..cac762a 100644
--- a/dts/Bindings/sound/wm8770.txt
+++ b/dts/Bindings/sound/wm8770.txt
@@ -10,7 +10,7 @@ Required properties:
Example:
-codec: wm8770@1 {
+wm8770: codec@1 {
compatible = "wlf,wm8770";
reg = <1>;
};
diff --git a/dts/Bindings/sound/wm8776.txt b/dts/Bindings/sound/wm8776.txt
index 3b9ca49..0117336 100644
--- a/dts/Bindings/sound/wm8776.txt
+++ b/dts/Bindings/sound/wm8776.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-codec: wm8776@1a {
+wm8776: codec@1a {
compatible = "wlf,wm8776";
reg = <0x1a>;
};
diff --git a/dts/Bindings/sound/wm8804.txt b/dts/Bindings/sound/wm8804.txt
index 6fd124b..2c1641c 100644
--- a/dts/Bindings/sound/wm8804.txt
+++ b/dts/Bindings/sound/wm8804.txt
@@ -19,7 +19,7 @@ Optional properties:
Example:
-codec: wm8804@1a {
+wm8804: codec@1a {
compatible = "wlf,wm8804";
reg = <0x1a>;
};
diff --git a/dts/Bindings/sound/wm8903.txt b/dts/Bindings/sound/wm8903.txt
index afc51ca..6371c24 100644
--- a/dts/Bindings/sound/wm8903.txt
+++ b/dts/Bindings/sound/wm8903.txt
@@ -57,7 +57,7 @@ Pins on the device (for linking into audio routes):
Example:
-codec: wm8903@1a {
+wm8903: codec@1a {
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupts = < 347 >;
diff --git a/dts/Bindings/sound/wm8960.txt b/dts/Bindings/sound/wm8960.txt
index 2deb8a3..6d29ac3 100644
--- a/dts/Bindings/sound/wm8960.txt
+++ b/dts/Bindings/sound/wm8960.txt
@@ -23,7 +23,7 @@ Optional properties:
Example:
-codec: wm8960@1a {
+wm8960: codec@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
diff --git a/dts/Bindings/sound/wm8962.txt b/dts/Bindings/sound/wm8962.txt
index 7f82b59..dcfa9a3 100644
--- a/dts/Bindings/sound/wm8962.txt
+++ b/dts/Bindings/sound/wm8962.txt
@@ -24,7 +24,7 @@ Optional properties:
Example:
-codec: wm8962@1a {
+wm8962: codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
diff --git a/dts/Bindings/sound/wm8994.txt b/dts/Bindings/sound/wm8994.txt
index 68c4e8d..4a9dead 100644
--- a/dts/Bindings/sound/wm8994.txt
+++ b/dts/Bindings/sound/wm8994.txt
@@ -59,7 +59,7 @@ Optional properties:
Example:
-codec: wm8994@1a {
+wm8994: codec@1a {
compatible = "wlf,wm8994";
reg = <0x1a>;
diff --git a/dts/Bindings/spi/spi-st-ssc.txt b/dts/Bindings/spi/spi-st-ssc.txt
index fe54959..1bdc470 100644
--- a/dts/Bindings/spi/spi-st-ssc.txt
+++ b/dts/Bindings/spi/spi-st-ssc.txt
@@ -9,7 +9,7 @@ Required properties:
- clocks : Must contain an entry for each name in clock-names
See ../clk/*
- pinctrl-names : Uses "default", can use "sleep" if provided
- See ../pinctrl/pinctrl-binding.txt
+ See ../pinctrl/pinctrl-bindings.txt
Optional properties:
- cs-gpios : List of GPIO chip selects
diff --git a/dts/Bindings/submitting-patches.txt b/dts/Bindings/submitting-patches.txt
index 274058c..de0d609 100644
--- a/dts/Bindings/submitting-patches.txt
+++ b/dts/Bindings/submitting-patches.txt
@@ -6,7 +6,14 @@ I. For patch submitters
0) Normal patch submission rules from Documentation/process/submitting-patches.rst
applies.
- 1) The Documentation/ portion of the patch should be a separate patch.
+ 1) The Documentation/ and include/dt-bindings/ portion of the patch should
+ be a separate patch. The preferred subject prefix for binding patches is:
+
+ "dt-bindings: <binding dir>: ..."
+
+ The 80 characters of the subject are precious. It is recommended to not
+ use "Documentation" or "doc" because that is implied. All bindings are
+ docs. Repeating "binding" again should also be avoided.
2) Submit the entire series to the devicetree mailinglist at
diff --git a/dts/Bindings/thermal/exynos-thermal.txt b/dts/Bindings/thermal/exynos-thermal.txt
index b957acf..ad648d9 100644
--- a/dts/Bindings/thermal/exynos-thermal.txt
+++ b/dts/Bindings/thermal/exynos-thermal.txt
@@ -12,7 +12,6 @@
"samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
Exynos5420 (Must pass triminfo base and triminfo clock)
"samsung,exynos5433-tmu"
- "samsung,exynos5440-tmu"
"samsung,exynos7-tmu"
- interrupt-parent : The phandle for the interrupt controller
- reg : Address range of the thermal registers. For soc's which has multiple
@@ -68,18 +67,7 @@ Example 1):
#thermal-sensor-cells = <0>;
};
-Example 2):
-
- tmuctrl_0: tmuctrl@160118 {
- compatible = "samsung,exynos5440-tmu";
- reg = <0x160118 0x230>, <0x160368 0x10>;
- interrupts = <0 58 0>;
- clocks = <&clock 21>;
- clock-names = "tmu_apbif";
- #thermal-sensor-cells = <0>;
- };
-
-Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
+Example 2): (In case of Exynos5420 "with misplaced TRIMINFO register")
tmu_cpu2: tmu@10068000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
diff --git a/dts/Bindings/thermal/imx-thermal.txt b/dts/Bindings/thermal/imx-thermal.txt
index 379eb76..823e417 100644
--- a/dts/Bindings/thermal/imx-thermal.txt
+++ b/dts/Bindings/thermal/imx-thermal.txt
@@ -1,8 +1,13 @@
* Temperature Monitor (TEMPMON) on Freescale i.MX SoCs
Required properties:
-- compatible : "fsl,imx6q-tempmon" for i.MX6Q, "fsl,imx6sx-tempmon" for i.MX6SX.
- i.MX6SX has two more IRQs than i.MX6Q, one is IRQ_LOW and the other is IRQ_PANIC,
+- compatible : must be one of following:
+ - "fsl,imx6q-tempmon" for i.MX6Q,
+ - "fsl,imx6sx-tempmon" for i.MX6SX,
+ - "fsl,imx7d-tempmon" for i.MX7S/D.
+- interrupts : the interrupt output of the controller:
+ i.MX6Q has one IRQ which will be triggered when temperature is higher than high threshold,
+ i.MX6SX and i.MX7S/D have two more IRQs than i.MX6Q, one is IRQ_LOW and the other is IRQ_PANIC,
when temperature is below than low threshold, IRQ_LOW will be triggered, when temperature
is higher than panic threshold, system will auto reboot by SRC module.
- fsl,tempmon : phandle pointer to system controller that contains TEMPMON
diff --git a/dts/Bindings/thermal/mediatek-thermal.txt b/dts/Bindings/thermal/mediatek-thermal.txt
index 0d73ea5..41d6a44 100644
--- a/dts/Bindings/thermal/mediatek-thermal.txt
+++ b/dts/Bindings/thermal/mediatek-thermal.txt
@@ -12,6 +12,7 @@ Required properties:
- "mediatek,mt8173-thermal" : For MT8173 family of SoCs
- "mediatek,mt2701-thermal" : For MT2701 family of SoCs
- "mediatek,mt2712-thermal" : For MT2712 family of SoCs
+ - "mediatek,mt7622-thermal" : For MT7622 SoC
- reg: Address range of the thermal controller
- interrupts: IRQ for the thermal controller
- clocks, clock-names: Clocks needed for the thermal controller. required
diff --git a/dts/Bindings/thermal/qcom-tsens.txt b/dts/Bindings/thermal/qcom-tsens.txt
index 292ed89..06195e8 100644
--- a/dts/Bindings/thermal/qcom-tsens.txt
+++ b/dts/Bindings/thermal/qcom-tsens.txt
@@ -8,6 +8,7 @@ Required properties:
- reg: Address range of the thermal registers
- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.
+- #qcom,sensors: Number of sensors in tsens block
- Refer to Documentation/devicetree/bindings/nvmem/nvmem.txt to know how to specify
nvmem cells
diff --git a/dts/Bindings/thermal/rcar-gen3-thermal.txt b/dts/Bindings/thermal/rcar-gen3-thermal.txt
index fdf5caa..cfa154b 100644
--- a/dts/Bindings/thermal/rcar-gen3-thermal.txt
+++ b/dts/Bindings/thermal/rcar-gen3-thermal.txt
@@ -9,6 +9,7 @@ Required properties:
Examples with soctypes are:
- "renesas,r8a7795-thermal" (R-Car H3)
- "renesas,r8a7796-thermal" (R-Car M3-W)
+ - "renesas,r8a77965-thermal" (R-Car M3-N)
- reg : Address ranges of the thermal registers. Each sensor
needs one address range. Sorting must be done in
increasing order according to datasheet, i.e.
@@ -18,7 +19,7 @@ Required properties:
Optional properties:
-- interrupts : interrupts routed to the TSC (3 for H3 and M3-W)
+- interrupts : interrupts routed to the TSC (3 for H3, M3-W and M3-N)
- power-domain : Must contain a reference to the power domain. This
property is mandatory if the thermal sensor instance
is part of a controllable power domain.
@@ -27,9 +28,9 @@ Example:
tsc: thermal@e6198000 {
compatible = "renesas,r8a7795-thermal";
- reg = <0 0xe6198000 0 0x68>,
- <0 0xe61a0000 0 0x5c>,
- <0 0xe61a8000 0 0x5c>;
+ reg = <0 0xe6198000 0 0x100>,
+ <0 0xe61a0000 0 0x100>,
+ <0 0xe61a8000 0 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/Bindings/thermal/rcar-thermal.txt b/dts/Bindings/thermal/rcar-thermal.txt
index 349e635..67c563f 100644
--- a/dts/Bindings/thermal/rcar-thermal.txt
+++ b/dts/Bindings/thermal/rcar-thermal.txt
@@ -3,7 +3,8 @@
Required properties:
- compatible : "renesas,thermal-<soctype>",
"renesas,rcar-gen2-thermal" (with thermal-zone) or
- "renesas,rcar-thermal" (without thermal-zone) as fallback.
+ "renesas,rcar-thermal" (without thermal-zone) as
+ fallback except R-Car D3.
Examples with soctypes are:
- "renesas,thermal-r8a73a4" (R-Mobile APE6)
- "renesas,thermal-r8a7743" (RZ/G1M)
@@ -12,13 +13,15 @@ Required properties:
- "renesas,thermal-r8a7791" (R-Car M2-W)
- "renesas,thermal-r8a7792" (R-Car V2H)
- "renesas,thermal-r8a7793" (R-Car M2-N)
+ - "renesas,thermal-r8a77995" (R-Car D3)
- reg : Address range of the thermal registers.
The 1st reg will be recognized as common register
if it has "interrupts".
Option properties:
-- interrupts : use interrupt
+- interrupts : If present should contain 3 interrupts for
+ R-Car D3 or 1 interrupt otherwise.
Example (non interrupt support):
diff --git a/dts/Bindings/thermal/uniphier-thermal.txt b/dts/Bindings/thermal/uniphier-thermal.txt
index 686c0b4..ceb92a9 100644
--- a/dts/Bindings/thermal/uniphier-thermal.txt
+++ b/dts/Bindings/thermal/uniphier-thermal.txt
@@ -8,6 +8,7 @@ Required properties:
- compatible :
- "socionext,uniphier-pxs2-thermal" : For UniPhier PXs2 SoC
- "socionext,uniphier-ld20-thermal" : For UniPhier LD20 SoC
+ - "socionext,uniphier-pxs3-thermal" : For UniPhier PXs3 SoC
- interrupts : IRQ for the temperature alarm
- #thermal-sensor-cells : Should be 0. See ./thermal.txt for details.
diff --git a/dts/Bindings/nios2/timer.txt b/dts/Bindings/timer/altr,timer-1.0.txt
index 904a584..904a584 100644
--- a/dts/Bindings/nios2/timer.txt
+++ b/dts/Bindings/timer/altr,timer-1.0.txt
diff --git a/dts/Bindings/arm/arch_timer.txt b/dts/Bindings/timer/arm,arch_timer.txt
index 68301b7..68301b7 100644
--- a/dts/Bindings/arm/arch_timer.txt
+++ b/dts/Bindings/timer/arm,arch_timer.txt
diff --git a/dts/Bindings/arm/armv7m_systick.txt b/dts/Bindings/timer/arm,armv7m-systick.txt
index 7cf4a24..7cf4a24 100644
--- a/dts/Bindings/arm/armv7m_systick.txt
+++ b/dts/Bindings/timer/arm,armv7m-systick.txt
diff --git a/dts/Bindings/arm/global_timer.txt b/dts/Bindings/timer/arm,global_timer.txt
index bdae3a8..bdae3a8 100644
--- a/dts/Bindings/arm/global_timer.txt
+++ b/dts/Bindings/timer/arm,global_timer.txt
diff --git a/dts/Bindings/arm/twd.txt b/dts/Bindings/timer/arm,twd.txt
index 383ea19..383ea19 100644
--- a/dts/Bindings/arm/twd.txt
+++ b/dts/Bindings/timer/arm,twd.txt
diff --git a/dts/Bindings/powerpc/fsl/gtm.txt b/dts/Bindings/timer/fsl,gtm.txt
index 9a33efd..9a33efd 100644
--- a/dts/Bindings/powerpc/fsl/gtm.txt
+++ b/dts/Bindings/timer/fsl,gtm.txt
diff --git a/dts/Bindings/arm/mrvl/timer.txt b/dts/Bindings/timer/mrvl,mmp-timer.txt
index 9a6e251..9a6e251 100644
--- a/dts/Bindings/arm/mrvl/timer.txt
+++ b/dts/Bindings/timer/mrvl,mmp-timer.txt
diff --git a/dts/Bindings/arm/msm/timer.txt b/dts/Bindings/timer/qcom,msm-timer.txt
index 5e10c34..5e10c34 100644
--- a/dts/Bindings/arm/msm/timer.txt
+++ b/dts/Bindings/timer/qcom,msm-timer.txt
diff --git a/dts/Bindings/timer/renesas,cmt.txt b/dts/Bindings/timer/renesas,cmt.txt
index d740989..b40add2 100644
--- a/dts/Bindings/timer/renesas,cmt.txt
+++ b/dts/Bindings/timer/renesas,cmt.txt
@@ -22,6 +22,10 @@ Required Properties:
- "renesas,r8a73a4-cmt0" for the 32-bit CMT0 device included in r8a73a4.
- "renesas,r8a73a4-cmt1" for the 48-bit CMT1 device included in r8a73a4.
+ - "renesas,r8a7743-cmt0" for the 32-bit CMT0 device included in r8a7743.
+ - "renesas,r8a7743-cmt1" for the 48-bit CMT1 device included in r8a7743.
+ - "renesas,r8a7745-cmt0" for the 32-bit CMT0 device included in r8a7745.
+ - "renesas,r8a7745-cmt1" for the 48-bit CMT1 device included in r8a7745.
- "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790.
- "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790.
- "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791.
@@ -31,10 +35,12 @@ Required Properties:
- "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794.
- "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794.
- - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2.
- - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2.
- These are fallbacks for r8a73a4 and all the R-Car Gen2
- entries listed above.
+ - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2
+ and RZ/G1.
+ - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2
+ and RZ/G1.
+ These are fallbacks for r8a73a4, R-Car Gen2 and RZ/G1 entries
+ listed above.
- reg: base address and length of the registers block for the timer module.
- interrupts: interrupt-specifier for the timer, one per channel.
diff --git a/dts/Bindings/arm/spear-timer.txt b/dts/Bindings/timer/st,spear-timer.txt
index c001722..c001722 100644
--- a/dts/Bindings/arm/spear-timer.txt
+++ b/dts/Bindings/timer/st,spear-timer.txt
diff --git a/dts/Bindings/c6x/timer64.txt b/dts/Bindings/timer/ti,c64x+timer64.txt
index 95911fe..95911fe 100644
--- a/dts/Bindings/c6x/timer64.txt
+++ b/dts/Bindings/timer/ti,c64x+timer64.txt
diff --git a/dts/Bindings/arm/omap/timer.txt b/dts/Bindings/timer/ti,timer.txt
index d02e27c..d02e27c 100644
--- a/dts/Bindings/arm/omap/timer.txt
+++ b/dts/Bindings/timer/ti,timer.txt
diff --git a/dts/Bindings/arm/vt8500/via,vt8500-timer.txt b/dts/Bindings/timer/via,vt8500-timer.txt
index 901c73f..901c73f 100644
--- a/dts/Bindings/arm/vt8500/via,vt8500-timer.txt
+++ b/dts/Bindings/timer/via,vt8500-timer.txt
diff --git a/dts/Bindings/usb/ci-hdrc-usb2.txt b/dts/Bindings/usb/ci-hdrc-usb2.txt
index 0e03344..2e93181 100644
--- a/dts/Bindings/usb/ci-hdrc-usb2.txt
+++ b/dts/Bindings/usb/ci-hdrc-usb2.txt
@@ -76,6 +76,10 @@ Optional properties:
needs to make sure it does not send more than 90%
maximum_periodic_data_per_frame. The use case is multiple transactions, but
less frame rate.
+- mux-controls: The mux control for toggling host/device output of this
+ controller. It's expected that a mux state of 0 indicates device mode and a
+ mux state of 1 indicates host mode.
+- mux-control-names: Shall be "usb_switch" if mux-controls is specified.
i.mx specific properties
- fsl,usbmisc: phandler of non-core register device, with one
@@ -102,4 +106,6 @@ Example:
rx-burst-size-dword = <0x10>;
extcon = <0>, <&usb_id>;
phy-clkgate-delay-us = <400>;
+ mux-controls = <&usb_switch>;
+ mux-control-names = "usb_switch";
};
diff --git a/dts/Bindings/usb/dwc3.txt b/dts/Bindings/usb/dwc3.txt
index 0dbd308..7f13ebe 100644
--- a/dts/Bindings/usb/dwc3.txt
+++ b/dts/Bindings/usb/dwc3.txt
@@ -7,6 +7,26 @@ Required properties:
- compatible: must be "snps,dwc3"
- reg : Address and length of the register set for the device
- interrupts: Interrupts used by the dwc3 controller.
+ - clock-names: should contain "ref", "bus_early", "suspend"
+ - clocks: list of phandle and clock specifier pairs corresponding to
+ entries in the clock-names property.
+
+Exception for clocks:
+ clocks are optional if the parent node (i.e. glue-layer) is compatible to
+ one of the following:
+ "amlogic,meson-axg-dwc3"
+ "amlogic,meson-gxl-dwc3"
+ "cavium,octeon-7130-usb-uctl"
+ "qcom,dwc3"
+ "samsung,exynos5250-dwusb3"
+ "samsung,exynos7-dwusb3"
+ "sprd,sc9860-dwc3"
+ "st,stih407-dwc3"
+ "ti,am437x-dwc3"
+ "ti,dwc3"
+ "ti,keystone-dwc3"
+ "rockchip,rk3399-dwc3"
+ "xlnx,zynqmp-dwc3"
Optional properties:
- usb-phy : array of phandle for the PHY device. The first element
@@ -15,6 +35,7 @@ Optional properties:
- phys: from the *Generic PHY* bindings
- phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy"
or "usb3-phy".
+ - resets: a single pair of phandle and reset specifier
- snps,usb3_lpm_capable: determines if platform is USB3 LPM capable
- snps,disable_scramble_quirk: true when SW should disable data scrambling.
Only really useful for FPGA builds.
diff --git a/dts/Bindings/usb/fcs,fusb302.txt b/dts/Bindings/usb/fcs,fusb302.txt
index 472facf..6087dc7 100644
--- a/dts/Bindings/usb/fcs,fusb302.txt
+++ b/dts/Bindings/usb/fcs,fusb302.txt
@@ -6,12 +6,6 @@ Required properties :
- interrupts : Interrupt specifier
Optional properties :
-- fcs,max-sink-microvolt : Maximum voltage to negotiate when configured as sink
-- fcs,max-sink-microamp : Maximum current to negotiate when configured as sink
-- fcs,max-sink-microwatt : Maximum power to negotiate when configured as sink
- If this is less then max-sink-microvolt *
- max-sink-microamp then the configured current will
- be clamped.
- fcs,operating-sink-microwatt :
Minimum amount of power accepted from a sink
when negotiating
diff --git a/dts/Bindings/usb/hisilicon,histb-xhci.txt b/dts/Bindings/usb/hisilicon,histb-xhci.txt
new file mode 100644
index 0000000..f463349
--- /dev/null
+++ b/dts/Bindings/usb/hisilicon,histb-xhci.txt
@@ -0,0 +1,45 @@
+HiSilicon STB xHCI
+
+The device node for HiSilicon STB xHCI host controller
+
+Required properties:
+ - compatible: should be "hisilicon,hi3798cv200-xhci"
+ - reg: specifies physical base address and size of the registers
+ - interrupts : interrupt used by the controller
+ - clocks: a list of phandle + clock-specifier pairs, one for each
+ entry in clock-names
+ - clock-names: must contain
+ "bus": for bus clock
+ "utmi": for utmi clock
+ "pipe": for pipe clock
+ "suspend": for suspend clock
+ - resets: a list of phandle and reset specifier pairs as listed in
+ reset-names property.
+ - reset-names: must contain
+ "soft": for soft reset
+ - phys: a list of phandle + phy specifier pairs
+ - phy-names: must contain at least one of following:
+ "inno": for inno phy
+ "combo": for combo phy
+
+Optional properties:
+ - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM
+ - usb3-lpm-capable: determines if platform is USB3 LPM capable
+ - imod-interval-ns: default interrupt moderation interval is 40000ns
+
+Example:
+
+xhci0: xchi@f98a0000 {
+ compatible = "hisilicon,hi3798cv200-xhci";
+ reg = <0xf98a0000 0x10000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_USB3_BUS_CLK>,
+ <&crg HISTB_USB3_UTMI_CLK>,
+ <&crg HISTB_USB3_PIPE_CLK>,
+ <&crg HISTB_USB3_SUSPEND_CLK>;
+ clock-names = "bus", "utmi", "pipe", "suspend";
+ resets = <&crg 0xb0 12>;
+ reset-names = "soft";
+ phys = <&usb2_phy1_port1 0>, <&combphy0 PHY_TYPE_USB3>;
+ phy-names = "inno", "combo";
+};
diff --git a/dts/Bindings/usb/qcom,dwc3.txt b/dts/Bindings/usb/qcom,dwc3.txt
index bc8a2fa..95afdcf 100644
--- a/dts/Bindings/usb/qcom,dwc3.txt
+++ b/dts/Bindings/usb/qcom,dwc3.txt
@@ -1,54 +1,95 @@
Qualcomm SuperSpeed DWC3 USB SoC controller
Required properties:
-- compatible: should contain "qcom,dwc3"
+- compatible: Compatible list, contains
+ "qcom,dwc3"
+ "qcom,msm8996-dwc3" for msm8996 SOC.
+ "qcom,sdm845-dwc3" for sdm845 SOC.
+- reg: Offset and length of register set for QSCRATCH wrapper
+- power-domains: specifies a phandle to PM domain provider node
- clocks: A list of phandle + clock-specifier pairs for the
clocks listed in clock-names
-- clock-names: Should contain the following:
+- clock-names: Should contain the following:
"core" Master/Core clock, have to be >= 125 MHz for SS
operation and >= 60MHz for HS operation
+ "mock_utmi" Mock utmi clock needed for ITP/SOF generation in
+ host mode. Its frequency should be 19.2MHz.
+ "sleep" Sleep clock, used for wakeup when USB3 core goes
+ into low power mode (U3).
Optional clocks:
- "iface" System bus AXI clock. Not present on all platforms
- "sleep" Sleep clock, used when USB3 core goes into low
- power mode (U3).
+ "iface" System bus AXI clock.
+ Not present on "qcom,msm8996-dwc3" compatible.
+ "cfg_noc" System Config NOC clock.
+ Not present on "qcom,msm8996-dwc3" compatible.
+- assigned-clocks: Should be:
+ MOCK_UTMI_CLK
+ MASTER_CLK
+- assigned-clock-rates: Should be:
+ 19.2Mhz (192000000) for MOCK_UTMI_CLK
+ >=125Mhz (125000000) for MASTER_CLK in SS mode
+ >=60Mhz (60000000) for MASTER_CLK in HS mode
+
+Optional properties:
+- resets: Phandle to reset control that resets core and wrapper.
+- interrupts: specifies interrupts from controller wrapper used
+ to wakeup from low power/susepnd state. Must contain
+ one or more entry for interrupt-names property
+- interrupt-names: Must include the following entries:
+ - "hs_phy_irq": The interrupt that is asserted when a
+ wakeup event is received on USB2 bus
+ - "ss_phy_irq": The interrupt that is asserted when a
+ wakeup event is received on USB3 bus
+ - "dm_hs_phy_irq" and "dp_hs_phy_irq": Separate
+ interrupts for any wakeup event on DM and DP lines
+- qcom,select-utmi-as-pipe-clk: if present, disable USB3 pipe_clk requirement.
+ Used when dwc3 operates without SSPHY and only
+ HS/FS/LS modes are supported.
Required child node:
A child node must exist to represent the core DWC3 IP block. The name of
the node is not important. The content of the node is defined in dwc3.txt.
Phy documentation is provided in the following places:
-Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
+Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - USB3 QMP PHY
+Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt - USB2 QUSB2 PHY
Example device nodes:
hs_phy: phy@100f8800 {
- compatible = "qcom,dwc3-hs-usb-phy";
- reg = <0x100f8800 0x30>;
- clocks = <&gcc USB30_0_UTMI_CLK>;
- clock-names = "ref";
- #phy-cells = <0>;
-
+ compatible = "qcom,qusb2-v2-phy";
+ ...
};
ss_phy: phy@100f8830 {
- compatible = "qcom,dwc3-ss-usb-phy";
- reg = <0x100f8830 0x30>;
- clocks = <&gcc USB30_0_MASTER_CLK>;
- clock-names = "ref";
- #phy-cells = <0>;
-
+ compatible = "qcom,qmp-v3-usb3-phy";
+ ...
};
- usb3_0: usb30@0 {
+ usb3_0: usb30@a6f8800 {
compatible = "qcom,dwc3";
+ reg = <0xa6f8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
- clocks = <&gcc USB30_0_MASTER_CLK>;
- clock-names = "core";
-
ranges;
+ interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>;
+ interrupt-names = "hs_phy_irq", "ss_phy_irq",
+ "dm_hs_phy_irq", "dp_hs_phy_irq";
+
+ clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
+ clock-names = "core", "mock_utmi", "sleep";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <133000000>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+ reset-names = "core_reset";
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+ qcom,select-utmi-as-pipe-clk;
dwc3@10000000 {
compatible = "snps,dwc3";
diff --git a/dts/Bindings/usb/richtek,rt1711h.txt b/dts/Bindings/usb/richtek,rt1711h.txt
new file mode 100644
index 0000000..09e847e
--- /dev/null
+++ b/dts/Bindings/usb/richtek,rt1711h.txt
@@ -0,0 +1,17 @@
+Richtek RT1711H TypeC PD Controller.
+
+Required properties:
+ - compatible : Must be "richtek,rt1711h".
+ - reg : Must be 0x4e, it's slave address of RT1711H.
+ - interrupt-parent : the phandle for the interrupt controller that
+ provides interrupts for this device.
+ - interrupts : <a b> where a is the interrupt number and b represents an
+ encoding of the sense and level information for the interrupt.
+
+Example :
+rt1711h@4e {
+ compatible = "richtek,rt1711h";
+ reg = <0x4e>;
+ interrupt-parent = <&gpio26>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+};
diff --git a/dts/Bindings/usb/rockchip,dwc3.txt b/dts/Bindings/usb/rockchip,dwc3.txt
index 50a3153..252a05c 100644
--- a/dts/Bindings/usb/rockchip,dwc3.txt
+++ b/dts/Bindings/usb/rockchip,dwc3.txt
@@ -16,7 +16,7 @@ A child node must exist to represent the core DWC3 IP block. The name of
the node is not important. The content of the node is defined in dwc3.txt.
Phy documentation is provided in the following places:
-Documentation/devicetree/bindings/phy/rockchip,dwc3-usb-phy.txt
+Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
Example device nodes:
diff --git a/dts/Bindings/vendor-prefixes.txt b/dts/Bindings/vendor-prefixes.txt
index a38d8bf..7cad066 100644
--- a/dts/Bindings/vendor-prefixes.txt
+++ b/dts/Bindings/vendor-prefixes.txt
@@ -32,6 +32,7 @@ andestech Andes Technology Corporation
apm Applied Micro Circuits Corporation (APM)
aptina Aptina Imaging
arasan Arasan Chip Systems
+archermind ArcherMind Technology (Nanjing) Co., Ltd.
arctic Arctic Sand
aries Aries Embedded GmbH
arm ARM Ltd.
@@ -47,6 +48,7 @@ auvidea Auvidea GmbH
avago Avago Technologies
avia avia semiconductor
avic Shanghai AVIC Optoelectronics Co., Ltd.
+avnet Avnet, Inc.
axentia Axentia Technologies AB
axis Axis Communications AB
bananapi BIPAI KEJI LIMITED
@@ -56,6 +58,7 @@ bosch Bosch Sensortec GmbH
boundary Boundary Devices Inc.
brcm Broadcom Corporation
buffalo Buffalo, Inc.
+bticino Bticino International
calxeda Calxeda
capella Capella Microsystems, Inc
cascoda Cascoda, Ltd.
@@ -75,6 +78,7 @@ cnxt Conexant Systems, Inc.
compulab CompuLab Ltd.
cortina Cortina Systems, Inc.
cosmic Cosmic Circuits
+crane Crane Connectivity Solutions
creative Creative Technology Ltd
crystalfontz Crystalfontz America, Inc.
cubietech Cubietech, Ltd.
@@ -185,6 +189,7 @@ khadas Khadas
kiebackpeter Kieback & Peter GmbH
kinetic Kinetic Technologies
kingnovel Kingnovel Technology Co., Ltd.
+koe Kaohsiung Opto-Electronics Inc.
kosagi Sutajio Ko-Usagi PTE Ltd.
kyo Kyocera Corporation
lacie LaCie
@@ -199,11 +204,13 @@ linaro Linaro Limited
linksys Belkin International, Inc. (Linksys)
linux Linux-specific binding
lltc Linear Technology Corporation
+logicpd Logic PD, Inc.
lsi LSI Corp. (LSI Logic)
lwn Liebherr-Werk Nenzing GmbH
macnica Macnica Americas
marvell Marvell Technology Group Ltd.
maxim Maxim Integrated Products
+mbvl Mobiveil Inc.
mcube mCube
meas Measurement Specialties
mediatek MediaTek Inc.
@@ -279,6 +286,7 @@ pine64 Pine64
pixcir PIXCIR MICROELECTRONICS Co., Ltd
plathome Plat'Home Co., Ltd.
plda PLDA
+portwell Portwell Inc.
poslab Poslab Technology Co., Ltd.
powervr PowerVR (deprecated, use img)
probox2 PROBOX2 (by W2COMP Co., Ltd.)
@@ -318,6 +326,7 @@ sgx SGX Sensortech
sharp Sharp Corporation
shimafuji Shimafuji Electric, Inc.
si-en Si-En Technology Ltd.
+sifive SiFive, Inc.
sigma Sigma Designs, Inc.
sii Seiko Instruments, Inc.
sil Silicon Image
@@ -393,6 +402,7 @@ vot Vision Optical Technology Co., Ltd.
wd Western Digital Corp.
wetek WeTek Electronics, limited.
wexler Wexler
+wi2wi Wi2Wi, Inc.
winbond Winbond Electronics corp.
winstar Winstar Display Corp.
wlf Wolfson Microelectronics
diff --git a/dts/Bindings/watchdog/ingenic,jz4740-wdt.txt b/dts/Bindings/watchdog/ingenic,jz4740-wdt.txt
index cb44918..ce1cb72 100644
--- a/dts/Bindings/watchdog/ingenic,jz4740-wdt.txt
+++ b/dts/Bindings/watchdog/ingenic,jz4740-wdt.txt
@@ -3,10 +3,15 @@ Ingenic Watchdog Timer (WDT) Controller for JZ4740 & JZ4780
Required properties:
compatible: "ingenic,jz4740-watchdog" or "ingenic,jz4780-watchdog"
reg: Register address and length for watchdog registers
+clocks: phandle to the RTC clock
+clock-names: should be "rtc"
Example:
watchdog: jz4740-watchdog@10002000 {
compatible = "ingenic,jz4740-watchdog";
- reg = <0x10002000 0x100>;
+ reg = <0x10002000 0x10>;
+
+ clocks = <&cgu JZ4740_CLK_RTC>;
+ clock-names = "rtc";
};
diff --git a/dts/Bindings/watchdog/renesas-wdt.txt b/dts/Bindings/watchdog/renesas-wdt.txt
index 74b2f03..f24d802 100644
--- a/dts/Bindings/watchdog/renesas-wdt.txt
+++ b/dts/Bindings/watchdog/renesas-wdt.txt
@@ -1,18 +1,27 @@
Renesas Watchdog Timer (WDT) Controller
Required properties:
-- compatible : Should be "renesas,<soctype>-wdt", and
- "renesas,rcar-gen3-wdt" or "renesas,rza-wdt" as fallback.
+ - compatible : Must be "renesas,<soctype>-wdt", followed by a generic
+ fallback compatible string when compatible with the generic
+ version.
Examples with soctypes are:
- - "renesas,r7s72100-wdt" (RZ/A1)
+ - "renesas,r8a7743-wdt" (RZ/G1M)
+ - "renesas,r8a7745-wdt" (RZ/G1E)
+ - "renesas,r8a7790-wdt" (R-Car H2)
+ - "renesas,r8a7791-wdt" (R-Car M2-W)
+ - "renesas,r8a7792-wdt" (R-Car V2H)
+ - "renesas,r8a7793-wdt" (R-Car M2-N)
+ - "renesas,r8a7794-wdt" (R-Car E2)
- "renesas,r8a7795-wdt" (R-Car H3)
- "renesas,r8a7796-wdt" (R-Car M3-W)
+ - "renesas,r8a77965-wdt" (R-Car M3-N)
- "renesas,r8a77970-wdt" (R-Car V3M)
- "renesas,r8a77995-wdt" (R-Car D3)
-
- When compatible with the generic version, nodes must list the SoC-specific
- version corresponding to the platform first, followed by the generic
- version.
+ - "renesas,r7s72100-wdt" (RZ/A1)
+ The generic compatible string must be:
+ - "renesas,rza-wdt" for RZ/A
+ - "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G
+ - "renesas,rcar-gen3-wdt" for R-Car Gen3
- reg : Should contain WDT registers location and length
- clocks : the clock feeding the watchdog timer.
diff --git a/dts/include/dt-bindings/clock/actions,s900-cmu.h b/dts/include/dt-bindings/clock/actions,s900-cmu.h
new file mode 100644
index 0000000..7c12515
--- /dev/null
+++ b/dts/include/dt-bindings/clock/actions,s900-cmu.h
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Device Tree binding constants for Actions Semi S900 Clock Management Unit
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
+#define __DT_BINDINGS_CLOCK_S900_CMU_H
+
+#define CLK_NONE 0
+
+/* fixed rate clocks */
+#define CLK_LOSC 1
+#define CLK_HOSC 2
+
+/* pll clocks */
+#define CLK_CORE_PLL 3
+#define CLK_DEV_PLL 4
+#define CLK_DDR_PLL 5
+#define CLK_NAND_PLL 6
+#define CLK_DISPLAY_PLL 7
+#define CLK_DSI_PLL 8
+#define CLK_ASSIST_PLL 9
+#define CLK_AUDIO_PLL 10
+
+/* system clock */
+#define CLK_CPU 15
+#define CLK_DEV 16
+#define CLK_NOC 17
+#define CLK_NOC_MUX 18
+#define CLK_NOC_DIV 19
+#define CLK_AHB 20
+#define CLK_APB 21
+#define CLK_DMAC 22
+
+/* peripheral device clock */
+#define CLK_GPIO 23
+
+#define CLK_BISP 24
+#define CLK_CSI0 25
+#define CLK_CSI1 26
+
+#define CLK_DE0 27
+#define CLK_DE1 28
+#define CLK_DE2 29
+#define CLK_DE3 30
+#define CLK_DSI 32
+
+#define CLK_GPU 33
+#define CLK_GPU_CORE 34
+#define CLK_GPU_MEM 35
+#define CLK_GPU_SYS 36
+
+#define CLK_HDE 37
+#define CLK_I2C0 38
+#define CLK_I2C1 39
+#define CLK_I2C2 40
+#define CLK_I2C3 41
+#define CLK_I2C4 42
+#define CLK_I2C5 43
+#define CLK_I2SRX 44
+#define CLK_I2STX 45
+#define CLK_IMX 46
+#define CLK_LCD 47
+#define CLK_NAND0 48
+#define CLK_NAND1 49
+#define CLK_PWM0 50
+#define CLK_PWM1 51
+#define CLK_PWM2 52
+#define CLK_PWM3 53
+#define CLK_PWM4 54
+#define CLK_PWM5 55
+#define CLK_SD0 56
+#define CLK_SD1 57
+#define CLK_SD2 58
+#define CLK_SD3 59
+#define CLK_SENSOR 60
+#define CLK_SPEED_SENSOR 61
+#define CLK_SPI0 62
+#define CLK_SPI1 63
+#define CLK_SPI2 64
+#define CLK_SPI3 65
+#define CLK_THERMAL_SENSOR 66
+#define CLK_UART0 67
+#define CLK_UART1 68
+#define CLK_UART2 69
+#define CLK_UART3 70
+#define CLK_UART4 71
+#define CLK_UART5 72
+#define CLK_UART6 73
+#define CLK_VCE 74
+#define CLK_VDE 75
+
+#define CLK_USB3_480MPLL0 76
+#define CLK_USB3_480MPHY0 77
+#define CLK_USB3_5GPHY 78
+#define CLK_USB3_CCE 79
+#define CLK_USB3_MAC 80
+
+#define CLK_TIMER 83
+
+#define CLK_HDMI_AUDIO 84
+
+#define CLK_24M 85
+
+#define CLK_EDP 86
+
+#define CLK_24M_EDP 87
+#define CLK_EDP_PLL 88
+#define CLK_EDP_LINK 89
+
+#define CLK_USB2H0_PLLEN 90
+#define CLK_USB2H0_PHY 91
+#define CLK_USB2H0_CCE 92
+#define CLK_USB2H1_PLLEN 93
+#define CLK_USB2H1_PHY 94
+#define CLK_USB2H1_CCE 95
+
+#define CLK_DDR0 96
+#define CLK_DDR1 97
+#define CLK_DMM 98
+
+#define CLK_ETH_MAC 99
+#define CLK_RMII_REF 100
+
+#define CLK_NR_CLKS (CLK_RMII_REF + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */
diff --git a/dts/include/dt-bindings/clock/aspeed-clock.h b/dts/include/dt-bindings/clock/aspeed-clock.h
index d3558d8..4476184 100644
--- a/dts/include/dt-bindings/clock/aspeed-clock.h
+++ b/dts/include/dt-bindings/clock/aspeed-clock.h
@@ -38,6 +38,7 @@
#define ASPEED_CLK_MAC 32
#define ASPEED_CLK_BCLK 33
#define ASPEED_CLK_MPLL 34
+#define ASPEED_CLK_24M 35
#define ASPEED_RESET_XDMA 0
#define ASPEED_RESET_MCTP 1
@@ -45,8 +46,9 @@
#define ASPEED_RESET_JTAG_MASTER 3
#define ASPEED_RESET_MIC 4
#define ASPEED_RESET_PWM 5
-#define ASPEED_RESET_PCIVGA 6
+#define ASPEED_RESET_PECI 6
#define ASPEED_RESET_I2C 7
#define ASPEED_RESET_AHB 8
+#define ASPEED_RESET_CRT1 9
#endif
diff --git a/dts/include/dt-bindings/clock/axg-aoclkc.h b/dts/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 0000000..6195501
--- /dev/null
+++ b/dts/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE 0
+#define CLKID_AO_I2C_MASTER 1
+#define CLKID_AO_I2C_SLAVE 2
+#define CLKID_AO_UART1 3
+#define CLKID_AO_UART2 4
+#define CLKID_AO_IR_BLASTER 5
+#define CLKID_AO_SAR_ADC 6
+#define CLKID_AO_CLK81 7
+#define CLKID_AO_SAR_ADC_SEL 8
+#define CLKID_AO_SAR_ADC_DIV 9
+#define CLKID_AO_SAR_ADC_CLK 10
+#define CLKID_AO_ALT_XTAL 11
+
+#endif
diff --git a/dts/include/dt-bindings/clock/bcm-sr.h b/dts/include/dt-bindings/clock/bcm-sr.h
index cff6c6f..419011b 100644
--- a/dts/include/dt-bindings/clock/bcm-sr.h
+++ b/dts/include/dt-bindings/clock/bcm-sr.h
@@ -35,7 +35,7 @@
/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
#define BCM_SR_GENPLL0 0
-#define BCM_SR_GENPLL0_SATA_CLK 1
+#define BCM_SR_GENPLL0_125M_CLK 1
#define BCM_SR_GENPLL0_SCR_CLK 2
#define BCM_SR_GENPLL0_250M_CLK 3
#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
@@ -50,9 +50,11 @@
/* GENPLL 2 clock channel ID NITRO MHB*/
#define BCM_SR_GENPLL2 0
#define BCM_SR_GENPLL2_NIC_CLK 1
-#define BCM_SR_GENPLL2_250_NITRO_CLK 2
+#define BCM_SR_GENPLL2_TS_500_CLK 2
#define BCM_SR_GENPLL2_125_NITRO_CLK 3
#define BCM_SR_GENPLL2_CHIMP_CLK 4
+#define BCM_SR_GENPLL2_NIC_FLASH_CLK 5
+#define BCM_SR_GENPLL2_FS4_CLK 6
/* GENPLL 3 HSLS clock channel ID */
#define BCM_SR_GENPLL3 0
@@ -62,11 +64,16 @@
/* GENPLL 4 SCR clock channel ID */
#define BCM_SR_GENPLL4 0
#define BCM_SR_GENPLL4_CCN_CLK 1
+#define BCM_SR_GENPLL4_TPIU_PLL_CLK 2
+#define BCM_SR_GENPLL4_NOC_CLK 3
+#define BCM_SR_GENPLL4_CHCLK_FS4_CLK 4
+#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5
/* GENPLL 5 FS4 clock channel ID */
#define BCM_SR_GENPLL5 0
-#define BCM_SR_GENPLL5_FS_CLK 1
-#define BCM_SR_GENPLL5_SPU_CLK 2
+#define BCM_SR_GENPLL5_FS4_HF_CLK 1
+#define BCM_SR_GENPLL5_CRYPTO_AE_CLK 2
+#define BCM_SR_GENPLL5_RAID_AE_CLK 3
/* GENPLL 6 NITRO clock channel ID */
#define BCM_SR_GENPLL6 0
@@ -74,13 +81,16 @@
/* LCPLL0 clock channel ID */
#define BCM_SR_LCPLL0 0
-#define BCM_SR_LCPLL0_SATA_REF_CLK 1
-#define BCM_SR_LCPLL0_USB_REF_CLK 2
-#define BCM_SR_LCPLL0_SATA_REFPN_CLK 3
+#define BCM_SR_LCPLL0_SATA_REFP_CLK 1
+#define BCM_SR_LCPLL0_SATA_REFN_CLK 2
+#define BCM_SR_LCPLL0_SATA_350_CLK 3
+#define BCM_SR_LCPLL0_SATA_500_CLK 4
/* LCPLL1 clock channel ID */
#define BCM_SR_LCPLL1 0
#define BCM_SR_LCPLL1_WAN_CLK 1
+#define BCM_SR_LCPLL1_USB_REF_CLK 2
+#define BCM_SR_LCPLL1_CRMU_TS_CLK 3
/* LCPLL PCIE clock channel ID */
#define BCM_SR_LCPLL_PCIE 0
diff --git a/dts/include/dt-bindings/clock/gxbb-clkc.h b/dts/include/dt-bindings/clock/gxbb-clkc.h
index 8ba99a5..7a892be 100644
--- a/dts/include/dt-bindings/clock/gxbb-clkc.h
+++ b/dts/include/dt-bindings/clock/gxbb-clkc.h
@@ -125,5 +125,7 @@
#define CLKID_VAPB_1 138
#define CLKID_VAPB_SEL 139
#define CLKID_VAPB 140
+#define CLKID_VDEC_1 153
+#define CLKID_VDEC_HEVC 156
#endif /* __GXBB_CLKC_H */
diff --git a/dts/include/dt-bindings/clock/histb-clock.h b/dts/include/dt-bindings/clock/histb-clock.h
index fab30b3..136de24 100644
--- a/dts/include/dt-bindings/clock/histb-clock.h
+++ b/dts/include/dt-bindings/clock/histb-clock.h
@@ -62,6 +62,14 @@
#define HISTB_USB2_PHY1_REF_CLK 40
#define HISTB_USB2_PHY2_REF_CLK 41
#define HISTB_COMBPHY0_CLK 42
+#define HISTB_USB3_BUS_CLK 43
+#define HISTB_USB3_UTMI_CLK 44
+#define HISTB_USB3_PIPE_CLK 45
+#define HISTB_USB3_SUSPEND_CLK 46
+#define HISTB_USB3_BUS_CLK1 47
+#define HISTB_USB3_UTMI_CLK1 48
+#define HISTB_USB3_PIPE_CLK1 49
+#define HISTB_USB3_SUSPEND_CLK1 50
/* clocks provided by mcu CRG */
#define HISTB_MCE_CLK 1
diff --git a/dts/include/dt-bindings/clock/imx6qdl-clock.h b/dts/include/dt-bindings/clock/imx6qdl-clock.h
index da59fd9..7ad171b 100644
--- a/dts/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/dts/include/dt-bindings/clock/imx6qdl-clock.h
@@ -271,6 +271,8 @@
#define IMX6QDL_CLK_PRE_AXI 258
#define IMX6QDL_CLK_MLB_SEL 259
#define IMX6QDL_CLK_MLB_PODF 260
-#define IMX6QDL_CLK_END 261
+#define IMX6QDL_CLK_EPIT1 261
+#define IMX6QDL_CLK_EPIT2 262
+#define IMX6QDL_CLK_END 263
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/dts/include/dt-bindings/clock/imx6sx-clock.h b/dts/include/dt-bindings/clock/imx6sx-clock.h
index 36f0324..cd2d6c5 100644
--- a/dts/include/dt-bindings/clock/imx6sx-clock.h
+++ b/dts/include/dt-bindings/clock/imx6sx-clock.h
@@ -275,6 +275,10 @@
#define IMX6SX_PLL6_BYPASS 262
#define IMX6SX_PLL7_BYPASS 263
#define IMX6SX_CLK_SPDIF_GCLK 264
-#define IMX6SX_CLK_CLK_END 265
+#define IMX6SX_CLK_LVDS2_SEL 265
+#define IMX6SX_CLK_LVDS2_OUT 266
+#define IMX6SX_CLK_LVDS2_IN 267
+#define IMX6SX_CLK_ANACLK2 268
+#define IMX6SX_CLK_CLK_END 269
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
diff --git a/dts/include/dt-bindings/clock/imx6ul-clock.h b/dts/include/dt-bindings/clock/imx6ul-clock.h
index ee9f1a5..9564597 100644
--- a/dts/include/dt-bindings/clock/imx6ul-clock.h
+++ b/dts/include/dt-bindings/clock/imx6ul-clock.h
@@ -235,20 +235,27 @@
#define IMX6UL_CLK_CSI_PODF 222
#define IMX6UL_CLK_PLL3_120M 223
#define IMX6UL_CLK_KPP 224
+#define IMX6UL_CLK_CKO1_SEL 225
+#define IMX6UL_CLK_CKO1_PODF 226
+#define IMX6UL_CLK_CKO1 227
+#define IMX6UL_CLK_CKO2_SEL 228
+#define IMX6UL_CLK_CKO2_PODF 229
+#define IMX6UL_CLK_CKO2 230
+#define IMX6UL_CLK_CKO 231
/* For i.MX6ULL */
-#define IMX6ULL_CLK_ESAI_PRED 225
-#define IMX6ULL_CLK_ESAI_PODF 226
-#define IMX6ULL_CLK_ESAI_EXTAL 227
-#define IMX6ULL_CLK_ESAI_MEM 228
-#define IMX6ULL_CLK_ESAI_IPG 229
-#define IMX6ULL_CLK_DCP_CLK 230
-#define IMX6ULL_CLK_EPDC_PRE_SEL 231
-#define IMX6ULL_CLK_EPDC_SEL 232
-#define IMX6ULL_CLK_EPDC_PODF 233
-#define IMX6ULL_CLK_EPDC_ACLK 234
-#define IMX6ULL_CLK_EPDC_PIX 235
-#define IMX6ULL_CLK_ESAI_SEL 236
-#define IMX6UL_CLK_END 237
+#define IMX6ULL_CLK_ESAI_PRED 232
+#define IMX6ULL_CLK_ESAI_PODF 233
+#define IMX6ULL_CLK_ESAI_EXTAL 234
+#define IMX6ULL_CLK_ESAI_MEM 235
+#define IMX6ULL_CLK_ESAI_IPG 236
+#define IMX6ULL_CLK_DCP_CLK 237
+#define IMX6ULL_CLK_EPDC_PRE_SEL 238
+#define IMX6ULL_CLK_EPDC_SEL 239
+#define IMX6ULL_CLK_EPDC_PODF 240
+#define IMX6ULL_CLK_EPDC_ACLK 241
+#define IMX6ULL_CLK_EPDC_PIX 242
+#define IMX6ULL_CLK_ESAI_SEL 243
+#define IMX6UL_CLK_END 244
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/dts/include/dt-bindings/clock/imx7d-clock.h b/dts/include/dt-bindings/clock/imx7d-clock.h
index b2325d3..0d67f53 100644
--- a/dts/include/dt-bindings/clock/imx7d-clock.h
+++ b/dts/include/dt-bindings/clock/imx7d-clock.h
@@ -168,7 +168,7 @@
#define IMX7D_SPDIF_ROOT_SRC 155
#define IMX7D_SPDIF_ROOT_CG 156
#define IMX7D_SPDIF_ROOT_DIV 157
-#define IMX7D_ENET1_REF_ROOT_CLK 158
+#define IMX7D_ENET1_IPG_ROOT_CLK 158
#define IMX7D_ENET1_REF_ROOT_SRC 159
#define IMX7D_ENET1_REF_ROOT_CG 160
#define IMX7D_ENET1_REF_ROOT_DIV 161
@@ -176,7 +176,7 @@
#define IMX7D_ENET1_TIME_ROOT_SRC 163
#define IMX7D_ENET1_TIME_ROOT_CG 164
#define IMX7D_ENET1_TIME_ROOT_DIV 165
-#define IMX7D_ENET2_REF_ROOT_CLK 166
+#define IMX7D_ENET2_IPG_ROOT_CLK 166
#define IMX7D_ENET2_REF_ROOT_SRC 167
#define IMX7D_ENET2_REF_ROOT_CG 168
#define IMX7D_ENET2_REF_ROOT_DIV 169
diff --git a/dts/include/dt-bindings/clock/meson8b-clkc.h b/dts/include/dt-bindings/clock/meson8b-clkc.h
index dea9d46..a60f47b 100644
--- a/dts/include/dt-bindings/clock/meson8b-clkc.h
+++ b/dts/include/dt-bindings/clock/meson8b-clkc.h
@@ -102,5 +102,6 @@
#define CLKID_MPLL0 93
#define CLKID_MPLL1 94
#define CLKID_MPLL2 95
+#define CLKID_NAND_CLK 112
#endif /* __MESON8B_CLKC_H */
diff --git a/dts/include/dt-bindings/clock/mt2701-clk.h b/dts/include/dt-bindings/clock/mt2701-clk.h
index 24e93df..9ac2f2b 100644
--- a/dts/include/dt-bindings/clock/mt2701-clk.h
+++ b/dts/include/dt-bindings/clock/mt2701-clk.h
@@ -171,13 +171,12 @@
#define CLK_TOP_8BDAC 151
#define CLK_TOP_WBG_DIG_416M 152
#define CLK_TOP_DPI 153
-#define CLK_TOP_HDMITX_CLKDIG_CTS 154
-#define CLK_TOP_DSI0_LNTC_DSI 155
-#define CLK_TOP_AUD_EXT1 156
-#define CLK_TOP_AUD_EXT2 157
-#define CLK_TOP_NFI1X_PAD 158
-#define CLK_TOP_AXISEL_D4 159
-#define CLK_TOP_NR 160
+#define CLK_TOP_DSI0_LNTC_DSI 154
+#define CLK_TOP_AUD_EXT1 155
+#define CLK_TOP_AUD_EXT2 156
+#define CLK_TOP_NFI1X_PAD 157
+#define CLK_TOP_AXISEL_D4 158
+#define CLK_TOP_NR 159
/* APMIXEDSYS */
@@ -194,7 +193,8 @@
#define CLK_APMIXED_HADDS2PLL 11
#define CLK_APMIXED_AUD2PLL 12
#define CLK_APMIXED_TVD2PLL 13
-#define CLK_APMIXED_NR 14
+#define CLK_APMIXED_HDMI_REF 14
+#define CLK_APMIXED_NR 15
/* DDRPHY */
@@ -431,6 +431,10 @@
#define CLK_ETHSYS_CRYPTO 8
#define CLK_ETHSYS_NR 9
+/* G3DSYS */
+#define CLK_G3DSYS_CORE 1
+#define CLK_G3DSYS_NR 2
+
/* BDP */
#define CLK_BDP_BRG_BA 1
diff --git a/dts/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/dts/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
new file mode 100644
index 0000000..f215226
--- /dev/null
+++ b/dts/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Nuvoton NPCM7xx Clock Generator binding
+ * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk
+ *
+ * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H
+#define __DT_BINDINGS_CLOCK_NPCM7XX_H
+
+
+#define NPCM7XX_CLK_CPU 0
+#define NPCM7XX_CLK_GFX_PIXEL 1
+#define NPCM7XX_CLK_MC 2
+#define NPCM7XX_CLK_ADC 3
+#define NPCM7XX_CLK_AHB 4
+#define NPCM7XX_CLK_TIMER 5
+#define NPCM7XX_CLK_UART 6
+#define NPCM7XX_CLK_MMC 7
+#define NPCM7XX_CLK_SPI3 8
+#define NPCM7XX_CLK_PCI 9
+#define NPCM7XX_CLK_AXI 10
+#define NPCM7XX_CLK_APB4 11
+#define NPCM7XX_CLK_APB3 12
+#define NPCM7XX_CLK_APB2 13
+#define NPCM7XX_CLK_APB1 14
+#define NPCM7XX_CLK_APB5 15
+#define NPCM7XX_CLK_CLKOUT 16
+#define NPCM7XX_CLK_GFX 17
+#define NPCM7XX_CLK_SU 18
+#define NPCM7XX_CLK_SU48 19
+#define NPCM7XX_CLK_SDHC 20
+#define NPCM7XX_CLK_SPI0 21
+#define NPCM7XX_CLK_SPIX 22
+
+#define NPCM7XX_CLK_REFCLK 23
+#define NPCM7XX_CLK_SYSBYPCK 24
+#define NPCM7XX_CLK_MCBYPCK 25
+
+#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_MCBYPCK+1)
+
+#endif
diff --git a/dts/include/dt-bindings/clock/qcom,gcc-msm8998.h b/dts/include/dt-bindings/clock/qcom,gcc-msm8998.h
new file mode 100644
index 0000000..58a242e
--- /dev/null
+++ b/dts/include/dt-bindings/clock/qcom,gcc-msm8998.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
+#define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
+
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC 8
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC 9
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC 10
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC 11
+#define BLSP1_UART1_APPS_CLK_SRC 12
+#define BLSP1_UART2_APPS_CLK_SRC 13
+#define BLSP1_UART3_APPS_CLK_SRC 14
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 15
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 16
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 17
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 18
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 19
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 20
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 21
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 22
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC 23
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC 24
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC 25
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC 26
+#define BLSP2_UART1_APPS_CLK_SRC 27
+#define BLSP2_UART2_APPS_CLK_SRC 28
+#define BLSP2_UART3_APPS_CLK_SRC 29
+#define GCC_AGGRE1_NOC_XO_CLK 30
+#define GCC_AGGRE1_UFS_AXI_CLK 31
+#define GCC_AGGRE1_USB3_AXI_CLK 32
+#define GCC_APSS_QDSS_TSCTR_DIV2_CLK 33
+#define GCC_APSS_QDSS_TSCTR_DIV8_CLK 34
+#define GCC_BIMC_HMSS_AXI_CLK 35
+#define GCC_BIMC_MSS_Q6_AXI_CLK 36
+#define GCC_BLSP1_AHB_CLK 37
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 38
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 39
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 40
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 41
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 42
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 43
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 44
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 45
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK 46
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK 47
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK 48
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK 49
+#define GCC_BLSP1_SLEEP_CLK 50
+#define GCC_BLSP1_UART1_APPS_CLK 51
+#define GCC_BLSP1_UART2_APPS_CLK 52
+#define GCC_BLSP1_UART3_APPS_CLK 53
+#define GCC_BLSP2_AHB_CLK 54
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 55
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 56
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 57
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 58
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 59
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 60
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 61
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 62
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK 63
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK 64
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK 65
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK 66
+#define GCC_BLSP2_SLEEP_CLK 67
+#define GCC_BLSP2_UART1_APPS_CLK 68
+#define GCC_BLSP2_UART2_APPS_CLK 69
+#define GCC_BLSP2_UART3_APPS_CLK 70
+#define GCC_CFG_NOC_USB3_AXI_CLK 71
+#define GCC_GP1_CLK 72
+#define GCC_GP2_CLK 73
+#define GCC_GP3_CLK 74
+#define GCC_GPU_BIMC_GFX_CLK 75
+#define GCC_GPU_BIMC_GFX_SRC_CLK 76
+#define GCC_GPU_CFG_AHB_CLK 77
+#define GCC_GPU_SNOC_DVM_GFX_CLK 78
+#define GCC_HMSS_AHB_CLK 79
+#define GCC_HMSS_AT_CLK 80
+#define GCC_HMSS_DVM_BUS_CLK 81
+#define GCC_HMSS_RBCPR_CLK 82
+#define GCC_HMSS_TRIG_CLK 83
+#define GCC_LPASS_AT_CLK 84
+#define GCC_LPASS_TRIG_CLK 85
+#define GCC_MMSS_NOC_CFG_AHB_CLK 86
+#define GCC_MMSS_QM_AHB_CLK 87
+#define GCC_MMSS_QM_CORE_CLK 88
+#define GCC_MMSS_SYS_NOC_AXI_CLK 89
+#define GCC_MSS_AT_CLK 90
+#define GCC_PCIE_0_AUX_CLK 91
+#define GCC_PCIE_0_CFG_AHB_CLK 92
+#define GCC_PCIE_0_MSTR_AXI_CLK 93
+#define GCC_PCIE_0_PIPE_CLK 94
+#define GCC_PCIE_0_SLV_AXI_CLK 95
+#define GCC_PCIE_PHY_AUX_CLK 96
+#define GCC_PDM2_CLK 97
+#define GCC_PDM_AHB_CLK 98
+#define GCC_PDM_XO4_CLK 99
+#define GCC_PRNG_AHB_CLK 100
+#define GCC_SDCC2_AHB_CLK 101
+#define GCC_SDCC2_APPS_CLK 102
+#define GCC_SDCC4_AHB_CLK 103
+#define GCC_SDCC4_APPS_CLK 104
+#define GCC_TSIF_AHB_CLK 105
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK 106
+#define GCC_TSIF_REF_CLK 107
+#define GCC_UFS_AHB_CLK 108
+#define GCC_UFS_AXI_CLK 109
+#define GCC_UFS_ICE_CORE_CLK 110
+#define GCC_UFS_PHY_AUX_CLK 111
+#define GCC_UFS_RX_SYMBOL_0_CLK 112
+#define GCC_UFS_RX_SYMBOL_1_CLK 113
+#define GCC_UFS_TX_SYMBOL_0_CLK 114
+#define GCC_UFS_UNIPRO_CORE_CLK 115
+#define GCC_USB30_MASTER_CLK 116
+#define GCC_USB30_MOCK_UTMI_CLK 117
+#define GCC_USB30_SLEEP_CLK 118
+#define GCC_USB3_PHY_AUX_CLK 119
+#define GCC_USB3_PHY_PIPE_CLK 120
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 121
+#define GP1_CLK_SRC 122
+#define GP2_CLK_SRC 123
+#define GP3_CLK_SRC 124
+#define GPLL0 125
+#define GPLL0_OUT_EVEN 126
+#define GPLL0_OUT_MAIN 127
+#define GPLL0_OUT_ODD 128
+#define GPLL0_OUT_TEST 129
+#define GPLL1 130
+#define GPLL1_OUT_EVEN 131
+#define GPLL1_OUT_MAIN 132
+#define GPLL1_OUT_ODD 133
+#define GPLL1_OUT_TEST 134
+#define GPLL2 135
+#define GPLL2_OUT_EVEN 136
+#define GPLL2_OUT_MAIN 137
+#define GPLL2_OUT_ODD 138
+#define GPLL2_OUT_TEST 139
+#define GPLL3 140
+#define GPLL3_OUT_EVEN 141
+#define GPLL3_OUT_MAIN 142
+#define GPLL3_OUT_ODD 143
+#define GPLL3_OUT_TEST 144
+#define GPLL4 145
+#define GPLL4_OUT_EVEN 146
+#define GPLL4_OUT_MAIN 147
+#define GPLL4_OUT_ODD 148
+#define GPLL4_OUT_TEST 149
+#define GPLL6 150
+#define GPLL6_OUT_EVEN 151
+#define GPLL6_OUT_MAIN 152
+#define GPLL6_OUT_ODD 153
+#define GPLL6_OUT_TEST 154
+#define HMSS_AHB_CLK_SRC 155
+#define HMSS_RBCPR_CLK_SRC 156
+#define PCIE_AUX_CLK_SRC 157
+#define PDM2_CLK_SRC 158
+#define SDCC2_APPS_CLK_SRC 159
+#define SDCC4_APPS_CLK_SRC 160
+#define TSIF_REF_CLK_SRC 161
+#define UFS_AXI_CLK_SRC 162
+#define USB30_MASTER_CLK_SRC 163
+#define USB30_MOCK_UTMI_CLK_SRC 164
+#define USB3_PHY_AUX_CLK_SRC 165
+
+#define PCIE_0_GDSC 0
+#define UFS_GDSC 1
+#define USB_30_GDSC 2
+
+#define GCC_BLSP1_QUP1_BCR 0
+#define GCC_BLSP1_QUP2_BCR 1
+#define GCC_BLSP1_QUP3_BCR 2
+#define GCC_BLSP1_QUP4_BCR 3
+#define GCC_BLSP1_QUP5_BCR 4
+#define GCC_BLSP1_QUP6_BCR 5
+#define GCC_BLSP2_QUP1_BCR 6
+#define GCC_BLSP2_QUP2_BCR 7
+#define GCC_BLSP2_QUP3_BCR 8
+#define GCC_BLSP2_QUP4_BCR 9
+#define GCC_BLSP2_QUP5_BCR 10
+#define GCC_BLSP2_QUP6_BCR 11
+#define GCC_PCIE_0_BCR 12
+#define GCC_PDM_BCR 13
+#define GCC_SDCC2_BCR 14
+#define GCC_SDCC4_BCR 15
+#define GCC_TSIF_BCR 16
+#define GCC_UFS_BCR 17
+#define GCC_USB_30_BCR 18
+
+#endif
diff --git a/dts/include/dt-bindings/clock/qcom,gcc-sdm845.h b/dts/include/dt-bindings/clock/qcom,gcc-sdm845.h
new file mode 100644
index 0000000..aca6126
--- /dev/null
+++ b/dts/include/dt-bindings/clock/qcom,gcc-sdm845.h
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
+
+/* GCC clock registers */
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
+#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
+#define GCC_AGGRE_USB3_SEC_AXI_CLK 4
+#define GCC_BOOT_ROM_AHB_CLK 5
+#define GCC_CAMERA_AHB_CLK 6
+#define GCC_CAMERA_AXI_CLK 7
+#define GCC_CAMERA_XO_CLK 8
+#define GCC_CE1_AHB_CLK 9
+#define GCC_CE1_AXI_CLK 10
+#define GCC_CE1_CLK 11
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
+#define GCC_CPUSS_AHB_CLK 14
+#define GCC_CPUSS_AHB_CLK_SRC 15
+#define GCC_CPUSS_RBCPR_CLK 16
+#define GCC_CPUSS_RBCPR_CLK_SRC 17
+#define GCC_DDRSS_GPU_AXI_CLK 18
+#define GCC_DISP_AHB_CLK 19
+#define GCC_DISP_AXI_CLK 20
+#define GCC_DISP_GPLL0_CLK_SRC 21
+#define GCC_DISP_GPLL0_DIV_CLK_SRC 22
+#define GCC_DISP_XO_CLK 23
+#define GCC_GP1_CLK 24
+#define GCC_GP1_CLK_SRC 25
+#define GCC_GP2_CLK 26
+#define GCC_GP2_CLK_SRC 27
+#define GCC_GP3_CLK 28
+#define GCC_GP3_CLK_SRC 29
+#define GCC_GPU_CFG_AHB_CLK 30
+#define GCC_GPU_GPLL0_CLK_SRC 31
+#define GCC_GPU_GPLL0_DIV_CLK_SRC 32
+#define GCC_GPU_MEMNOC_GFX_CLK 33
+#define GCC_GPU_SNOC_DVM_GFX_CLK 34
+#define GCC_MSS_AXIS2_CLK 35
+#define GCC_MSS_CFG_AHB_CLK 36
+#define GCC_MSS_GPLL0_DIV_CLK_SRC 37
+#define GCC_MSS_MFAB_AXIS_CLK 38
+#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39
+#define GCC_MSS_SNOC_AXI_CLK 40
+#define GCC_PCIE_0_AUX_CLK 41
+#define GCC_PCIE_0_AUX_CLK_SRC 42
+#define GCC_PCIE_0_CFG_AHB_CLK 43
+#define GCC_PCIE_0_CLKREF_CLK 44
+#define GCC_PCIE_0_MSTR_AXI_CLK 45
+#define GCC_PCIE_0_PIPE_CLK 46
+#define GCC_PCIE_0_SLV_AXI_CLK 47
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48
+#define GCC_PCIE_1_AUX_CLK 49
+#define GCC_PCIE_1_AUX_CLK_SRC 50
+#define GCC_PCIE_1_CFG_AHB_CLK 51
+#define GCC_PCIE_1_CLKREF_CLK 52
+#define GCC_PCIE_1_MSTR_AXI_CLK 53
+#define GCC_PCIE_1_PIPE_CLK 54
+#define GCC_PCIE_1_SLV_AXI_CLK 55
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56
+#define GCC_PCIE_PHY_AUX_CLK 57
+#define GCC_PCIE_PHY_REFGEN_CLK 58
+#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59
+#define GCC_PDM2_CLK 60
+#define GCC_PDM2_CLK_SRC 61
+#define GCC_PDM_AHB_CLK 62
+#define GCC_PDM_XO4_CLK 63
+#define GCC_PRNG_AHB_CLK 64
+#define GCC_QMIP_CAMERA_AHB_CLK 65
+#define GCC_QMIP_DISP_AHB_CLK 66
+#define GCC_QMIP_VIDEO_AHB_CLK 67
+#define GCC_QUPV3_WRAP0_S0_CLK 68
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69
+#define GCC_QUPV3_WRAP0_S1_CLK 70
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71
+#define GCC_QUPV3_WRAP0_S2_CLK 72
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73
+#define GCC_QUPV3_WRAP0_S3_CLK 74
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75
+#define GCC_QUPV3_WRAP0_S4_CLK 76
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77
+#define GCC_QUPV3_WRAP0_S5_CLK 78
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79
+#define GCC_QUPV3_WRAP0_S6_CLK 80
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81
+#define GCC_QUPV3_WRAP0_S7_CLK 82
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83
+#define GCC_QUPV3_WRAP1_S0_CLK 84
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85
+#define GCC_QUPV3_WRAP1_S1_CLK 86
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87
+#define GCC_QUPV3_WRAP1_S2_CLK 88
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89
+#define GCC_QUPV3_WRAP1_S3_CLK 90
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91
+#define GCC_QUPV3_WRAP1_S4_CLK 92
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93
+#define GCC_QUPV3_WRAP1_S5_CLK 94
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95
+#define GCC_QUPV3_WRAP1_S6_CLK 96
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97
+#define GCC_QUPV3_WRAP1_S7_CLK 98
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103
+#define GCC_SDCC2_AHB_CLK 104
+#define GCC_SDCC2_APPS_CLK 105
+#define GCC_SDCC2_APPS_CLK_SRC 106
+#define GCC_SDCC4_AHB_CLK 107
+#define GCC_SDCC4_APPS_CLK 108
+#define GCC_SDCC4_APPS_CLK_SRC 109
+#define GCC_SYS_NOC_CPUSS_AHB_CLK 110
+#define GCC_TSIF_AHB_CLK 111
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112
+#define GCC_TSIF_REF_CLK 113
+#define GCC_TSIF_REF_CLK_SRC 114
+#define GCC_UFS_CARD_AHB_CLK 115
+#define GCC_UFS_CARD_AXI_CLK 116
+#define GCC_UFS_CARD_AXI_CLK_SRC 117
+#define GCC_UFS_CARD_CLKREF_CLK 118
+#define GCC_UFS_CARD_ICE_CORE_CLK 119
+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120
+#define GCC_UFS_CARD_PHY_AUX_CLK 121
+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127
+#define GCC_UFS_MEM_CLKREF_CLK 128
+#define GCC_UFS_PHY_AHB_CLK 129
+#define GCC_UFS_PHY_AXI_CLK 130
+#define GCC_UFS_PHY_AXI_CLK_SRC 131
+#define GCC_UFS_PHY_ICE_CORE_CLK 132
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133
+#define GCC_UFS_PHY_PHY_AUX_CLK 134
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140
+#define GCC_USB30_PRIM_MASTER_CLK 141
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 142
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144
+#define GCC_USB30_PRIM_SLEEP_CLK 145
+#define GCC_USB30_SEC_MASTER_CLK 146
+#define GCC_USB30_SEC_MASTER_CLK_SRC 147
+#define GCC_USB30_SEC_MOCK_UTMI_CLK 148
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149
+#define GCC_USB30_SEC_SLEEP_CLK 150
+#define GCC_USB3_PRIM_CLKREF_CLK 151
+#define GCC_USB3_PRIM_PHY_AUX_CLK 152
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 155
+#define GCC_USB3_SEC_CLKREF_CLK 156
+#define GCC_USB3_SEC_PHY_AUX_CLK 157
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158
+#define GCC_USB3_SEC_PHY_PIPE_CLK 159
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161
+#define GCC_VIDEO_AHB_CLK 162
+#define GCC_VIDEO_AXI_CLK 163
+#define GCC_VIDEO_XO_CLK 164
+#define GPLL0 165
+#define GPLL0_OUT_EVEN 166
+#define GPLL0_OUT_MAIN 167
+#define GCC_GPU_IREF_CLK 168
+#define GCC_SDCC1_AHB_CLK 169
+#define GCC_SDCC1_APPS_CLK 170
+#define GCC_SDCC1_ICE_CORE_CLK 171
+#define GCC_SDCC1_APPS_CLK_SRC 172
+#define GCC_SDCC1_ICE_CORE_CLK_SRC 173
+#define GCC_APC_VS_CLK 174
+#define GCC_GPU_VS_CLK 175
+#define GCC_MSS_VS_CLK 176
+#define GCC_VDDA_VS_CLK 177
+#define GCC_VDDCX_VS_CLK 178
+#define GCC_VDDMX_VS_CLK 179
+#define GCC_VS_CTRL_AHB_CLK 180
+#define GCC_VS_CTRL_CLK 181
+#define GCC_VS_CTRL_CLK_SRC 182
+#define GCC_VSENSOR_CLK_SRC 183
+#define GPLL4 184
+
+/* GCC Resets */
+#define GCC_MMSS_BCR 0
+#define GCC_PCIE_0_BCR 1
+#define GCC_PCIE_1_BCR 2
+#define GCC_PCIE_PHY_BCR 3
+#define GCC_PDM_BCR 4
+#define GCC_PRNG_BCR 5
+#define GCC_QUPV3_WRAPPER_0_BCR 6
+#define GCC_QUPV3_WRAPPER_1_BCR 7
+#define GCC_QUSB2PHY_PRIM_BCR 8
+#define GCC_QUSB2PHY_SEC_BCR 9
+#define GCC_SDCC2_BCR 10
+#define GCC_SDCC4_BCR 11
+#define GCC_TSIF_BCR 12
+#define GCC_UFS_CARD_BCR 13
+#define GCC_UFS_PHY_BCR 14
+#define GCC_USB30_PRIM_BCR 15
+#define GCC_USB30_SEC_BCR 16
+#define GCC_USB3_PHY_PRIM_BCR 17
+#define GCC_USB3PHY_PHY_PRIM_BCR 18
+#define GCC_USB3_DP_PHY_PRIM_BCR 19
+#define GCC_USB3_PHY_SEC_BCR 20
+#define GCC_USB3PHY_PHY_SEC_BCR 21
+#define GCC_USB3_DP_PHY_SEC_BCR 22
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
+#define GCC_PCIE_0_PHY_BCR 24
+#define GCC_PCIE_1_PHY_BCR 25
+
+/* GCC GDSCRs */
+#define PCIE_0_GDSC 0
+#define PCIE_1_GDSC 1
+#define UFS_CARD_GDSC 2
+#define UFS_PHY_GDSC 3
+#define USB30_PRIM_GDSC 4
+#define USB30_SEC_GDSC 5
+#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6
+#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12
+
+#endif
diff --git a/dts/include/dt-bindings/clock/qcom,rpmh.h b/dts/include/dt-bindings/clock/qcom,rpmh.h
new file mode 100644
index 0000000..f48fbd6
--- /dev/null
+++ b/dts/include/dt-bindings/clock/qcom,rpmh.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
+
+
+#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
+#define _DT_BINDINGS_CLK_MSM_RPMH_H
+
+/* RPMh controlled clocks */
+#define RPMH_CXO_CLK 0
+#define RPMH_CXO_CLK_A 1
+#define RPMH_LN_BB_CLK2 2
+#define RPMH_LN_BB_CLK2_A 3
+#define RPMH_LN_BB_CLK3 4
+#define RPMH_LN_BB_CLK3_A 5
+#define RPMH_RF_CLK1 6
+#define RPMH_RF_CLK1_A 7
+#define RPMH_RF_CLK2 8
+#define RPMH_RF_CLK2_A 9
+#define RPMH_RF_CLK3 10
+#define RPMH_RF_CLK3_A 11
+
+#endif
diff --git a/dts/include/dt-bindings/clock/qcom,videocc-sdm845.h b/dts/include/dt-bindings/clock/qcom,videocc-sdm845.h
new file mode 100644
index 0000000..1b86816
--- /dev/null
+++ b/dts/include/dt-bindings/clock/qcom,videocc-sdm845.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
+
+/* VIDEO_CC clock registers */
+#define VIDEO_CC_APB_CLK 0
+#define VIDEO_CC_AT_CLK 1
+#define VIDEO_CC_QDSS_TRIG_CLK 2
+#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3
+#define VIDEO_CC_VCODEC0_AXI_CLK 4
+#define VIDEO_CC_VCODEC0_CORE_CLK 5
+#define VIDEO_CC_VCODEC1_AXI_CLK 6
+#define VIDEO_CC_VCODEC1_CORE_CLK 7
+#define VIDEO_CC_VENUS_AHB_CLK 8
+#define VIDEO_CC_VENUS_CLK_SRC 9
+#define VIDEO_CC_VENUS_CTL_AXI_CLK 10
+#define VIDEO_CC_VENUS_CTL_CORE_CLK 11
+#define VIDEO_PLL0 12
+
+/* VIDEO_CC Resets */
+#define VIDEO_CC_VENUS_BCR 0
+#define VIDEO_CC_VCODEC0_BCR 1
+#define VIDEO_CC_VCODEC1_BCR 2
+#define VIDEO_CC_INTERFACE_BCR 3
+
+/* VIDEO_CC GDSCRs */
+#define VENUS_GDSC 0
+#define VCODEC0_GDSC 1
+#define VCODEC1_GDSC 2
+
+#endif
diff --git a/dts/include/dt-bindings/clock/r8a77470-cpg-mssr.h b/dts/include/dt-bindings/clock/r8a77470-cpg-mssr.h
new file mode 100644
index 0000000..34cba49
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a77470-cpg-mssr.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77470 CPG Core Clocks */
+#define R8A77470_CLK_Z2 0
+#define R8A77470_CLK_ZTR 1
+#define R8A77470_CLK_ZTRD2 2
+#define R8A77470_CLK_ZT 3
+#define R8A77470_CLK_ZX 4
+#define R8A77470_CLK_ZS 5
+#define R8A77470_CLK_HP 6
+#define R8A77470_CLK_B 7
+#define R8A77470_CLK_LB 8
+#define R8A77470_CLK_P 9
+#define R8A77470_CLK_CL 10
+#define R8A77470_CLK_CP 11
+#define R8A77470_CLK_M2 12
+#define R8A77470_CLK_ZB3 13
+#define R8A77470_CLK_SDH 14
+#define R8A77470_CLK_SD0 15
+#define R8A77470_CLK_SD1 16
+#define R8A77470_CLK_SD2 17
+#define R8A77470_CLK_MP 18
+#define R8A77470_CLK_QSPI 19
+#define R8A77470_CLK_CPEX 20
+#define R8A77470_CLK_RCAN 21
+#define R8A77470_CLK_R 22
+#define R8A77470_CLK_OSC 23
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */
diff --git a/dts/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/dts/include/dt-bindings/clock/r8a77990-cpg-mssr.h
new file mode 100644
index 0000000..a596a48
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a77990-cpg-mssr.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77990 CPG Core Clocks */
+#define R8A77990_CLK_Z2 0
+#define R8A77990_CLK_ZR 1
+#define R8A77990_CLK_ZG 2
+#define R8A77990_CLK_ZTR 3
+#define R8A77990_CLK_ZT 4
+#define R8A77990_CLK_ZX 5
+#define R8A77990_CLK_S0D1 6
+#define R8A77990_CLK_S0D3 7
+#define R8A77990_CLK_S0D6 8
+#define R8A77990_CLK_S0D12 9
+#define R8A77990_CLK_S0D24 10
+#define R8A77990_CLK_S1D1 11
+#define R8A77990_CLK_S1D2 12
+#define R8A77990_CLK_S1D4 13
+#define R8A77990_CLK_S2D1 14
+#define R8A77990_CLK_S2D2 15
+#define R8A77990_CLK_S2D4 16
+#define R8A77990_CLK_S3D1 17
+#define R8A77990_CLK_S3D2 18
+#define R8A77990_CLK_S3D4 19
+#define R8A77990_CLK_S0D6C 20
+#define R8A77990_CLK_S3D1C 21
+#define R8A77990_CLK_S3D2C 22
+#define R8A77990_CLK_S3D4C 23
+#define R8A77990_CLK_LB 24
+#define R8A77990_CLK_CL 25
+#define R8A77990_CLK_ZB3 26
+#define R8A77990_CLK_ZB3D2 27
+#define R8A77990_CLK_CR 28
+#define R8A77990_CLK_CRD2 29
+#define R8A77990_CLK_SD0H 30
+#define R8A77990_CLK_SD0 31
+#define R8A77990_CLK_SD1H 32
+#define R8A77990_CLK_SD1 33
+#define R8A77990_CLK_SD3H 34
+#define R8A77990_CLK_SD3 35
+#define R8A77990_CLK_RPC 36
+#define R8A77990_CLK_RPCD2 37
+#define R8A77990_CLK_ZA2 38
+#define R8A77990_CLK_ZA8 39
+#define R8A77990_CLK_Z2D 40
+#define R8A77990_CLK_CANFD 41
+#define R8A77990_CLK_MSO 42
+#define R8A77990_CLK_R 43
+#define R8A77990_CLK_OSC 44
+#define R8A77990_CLK_LV0 45
+#define R8A77990_CLK_LV1 46
+#define R8A77990_CLK_CSI0 47
+#define R8A77990_CLK_CP 48
+#define R8A77990_CLK_CPEX 49
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */
diff --git a/dts/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/dts/include/dt-bindings/clock/sun50i-h6-r-ccu.h
new file mode 100644
index 0000000..7613613
--- /dev/null
+++ b/dts/include/dt-bindings/clock/sun50i-h6-r-ccu.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+
+#define CLK_AR100 0
+
+#define CLK_R_APB1 2
+
+#define CLK_R_APB1_TIMER 4
+#define CLK_R_APB1_TWD 5
+#define CLK_R_APB1_PWM 6
+#define CLK_R_APB2_UART 7
+#define CLK_R_APB2_I2C 8
+#define CLK_R_APB1_IR 9
+#define CLK_R_APB1_W1 10
+
+#define CLK_IR 11
+#define CLK_W1 12
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */
diff --git a/dts/include/dt-bindings/dma/jz4780-dma.h b/dts/include/dt-bindings/dma/jz4780-dma.h
new file mode 100644
index 0000000..df017fd
--- /dev/null
+++ b/dts/include/dt-bindings/dma/jz4780-dma.h
@@ -0,0 +1,49 @@
+#ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__
+#define __DT_BINDINGS_DMA_JZ4780_DMA_H__
+
+/*
+ * Request type numbers for the JZ4780 DMA controller (written to the DRTn
+ * register for the channel).
+ */
+#define JZ4780_DMA_I2S1_TX 0x4
+#define JZ4780_DMA_I2S1_RX 0x5
+#define JZ4780_DMA_I2S0_TX 0x6
+#define JZ4780_DMA_I2S0_RX 0x7
+#define JZ4780_DMA_AUTO 0x8
+#define JZ4780_DMA_SADC_RX 0x9
+#define JZ4780_DMA_UART4_TX 0xc
+#define JZ4780_DMA_UART4_RX 0xd
+#define JZ4780_DMA_UART3_TX 0xe
+#define JZ4780_DMA_UART3_RX 0xf
+#define JZ4780_DMA_UART2_TX 0x10
+#define JZ4780_DMA_UART2_RX 0x11
+#define JZ4780_DMA_UART1_TX 0x12
+#define JZ4780_DMA_UART1_RX 0x13
+#define JZ4780_DMA_UART0_TX 0x14
+#define JZ4780_DMA_UART0_RX 0x15
+#define JZ4780_DMA_SSI0_TX 0x16
+#define JZ4780_DMA_SSI0_RX 0x17
+#define JZ4780_DMA_SSI1_TX 0x18
+#define JZ4780_DMA_SSI1_RX 0x19
+#define JZ4780_DMA_MSC0_TX 0x1a
+#define JZ4780_DMA_MSC0_RX 0x1b
+#define JZ4780_DMA_MSC1_TX 0x1c
+#define JZ4780_DMA_MSC1_RX 0x1d
+#define JZ4780_DMA_MSC2_TX 0x1e
+#define JZ4780_DMA_MSC2_RX 0x1f
+#define JZ4780_DMA_PCM0_TX 0x20
+#define JZ4780_DMA_PCM0_RX 0x21
+#define JZ4780_DMA_SMB0_TX 0x24
+#define JZ4780_DMA_SMB0_RX 0x25
+#define JZ4780_DMA_SMB1_TX 0x26
+#define JZ4780_DMA_SMB1_RX 0x27
+#define JZ4780_DMA_SMB2_TX 0x28
+#define JZ4780_DMA_SMB2_RX 0x29
+#define JZ4780_DMA_SMB3_TX 0x2a
+#define JZ4780_DMA_SMB3_RX 0x2b
+#define JZ4780_DMA_SMB4_TX 0x2c
+#define JZ4780_DMA_SMB4_RX 0x2d
+#define JZ4780_DMA_DES_TX 0x2e
+#define JZ4780_DMA_DES_RX 0x2f
+
+#endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */
diff --git a/dts/include/dt-bindings/memory/tegra114-mc.h b/dts/include/dt-bindings/memory/tegra114-mc.h
index 27c8386..dfe99c8 100644
--- a/dts/include/dt-bindings/memory/tegra114-mc.h
+++ b/dts/include/dt-bindings/memory/tegra114-mc.h
@@ -23,4 +23,21 @@
#define TEGRA_SWGROUP_EMUCIF 18
#define TEGRA_SWGROUP_TSEC 19
+#define TEGRA114_MC_RESET_AVPC 0
+#define TEGRA114_MC_RESET_DC 1
+#define TEGRA114_MC_RESET_DCB 2
+#define TEGRA114_MC_RESET_EPP 3
+#define TEGRA114_MC_RESET_2D 4
+#define TEGRA114_MC_RESET_HC 5
+#define TEGRA114_MC_RESET_HDA 6
+#define TEGRA114_MC_RESET_ISP 7
+#define TEGRA114_MC_RESET_MPCORE 8
+#define TEGRA114_MC_RESET_MPCORELP 9
+#define TEGRA114_MC_RESET_MPE 10
+#define TEGRA114_MC_RESET_3D 11
+#define TEGRA114_MC_RESET_3D2 12
+#define TEGRA114_MC_RESET_PPCS 13
+#define TEGRA114_MC_RESET_VDE 14
+#define TEGRA114_MC_RESET_VI 15
+
#endif
diff --git a/dts/include/dt-bindings/memory/tegra124-mc.h b/dts/include/dt-bindings/memory/tegra124-mc.h
index f534d7c..186e6b7 100644
--- a/dts/include/dt-bindings/memory/tegra124-mc.h
+++ b/dts/include/dt-bindings/memory/tegra124-mc.h
@@ -29,4 +29,29 @@
#define TEGRA_SWGROUP_VIC 24
#define TEGRA_SWGROUP_VI 25
+#define TEGRA124_MC_RESET_AFI 0
+#define TEGRA124_MC_RESET_AVPC 1
+#define TEGRA124_MC_RESET_DC 2
+#define TEGRA124_MC_RESET_DCB 3
+#define TEGRA124_MC_RESET_HC 4
+#define TEGRA124_MC_RESET_HDA 5
+#define TEGRA124_MC_RESET_ISP2 6
+#define TEGRA124_MC_RESET_MPCORE 7
+#define TEGRA124_MC_RESET_MPCORELP 8
+#define TEGRA124_MC_RESET_MSENC 9
+#define TEGRA124_MC_RESET_PPCS 10
+#define TEGRA124_MC_RESET_SATA 11
+#define TEGRA124_MC_RESET_VDE 12
+#define TEGRA124_MC_RESET_VI 13
+#define TEGRA124_MC_RESET_VIC 14
+#define TEGRA124_MC_RESET_XUSB_HOST 15
+#define TEGRA124_MC_RESET_XUSB_DEV 16
+#define TEGRA124_MC_RESET_TSEC 17
+#define TEGRA124_MC_RESET_SDMMC1 18
+#define TEGRA124_MC_RESET_SDMMC2 19
+#define TEGRA124_MC_RESET_SDMMC3 20
+#define TEGRA124_MC_RESET_SDMMC4 21
+#define TEGRA124_MC_RESET_ISP2B 22
+#define TEGRA124_MC_RESET_GPU 23
+
#endif
diff --git a/dts/include/dt-bindings/memory/tegra20-mc.h b/dts/include/dt-bindings/memory/tegra20-mc.h
new file mode 100644
index 0000000..35e131e
--- /dev/null
+++ b/dts/include/dt-bindings/memory/tegra20-mc.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA20_MC_H
+
+#define TEGRA20_MC_RESET_AVPC 0
+#define TEGRA20_MC_RESET_DC 1
+#define TEGRA20_MC_RESET_DCB 2
+#define TEGRA20_MC_RESET_EPP 3
+#define TEGRA20_MC_RESET_2D 4
+#define TEGRA20_MC_RESET_HC 5
+#define TEGRA20_MC_RESET_ISP 6
+#define TEGRA20_MC_RESET_MPCORE 7
+#define TEGRA20_MC_RESET_MPEA 8
+#define TEGRA20_MC_RESET_MPEB 9
+#define TEGRA20_MC_RESET_MPEC 10
+#define TEGRA20_MC_RESET_3D 11
+#define TEGRA20_MC_RESET_PPCS 12
+#define TEGRA20_MC_RESET_VDE 13
+#define TEGRA20_MC_RESET_VI 14
+
+#endif
diff --git a/dts/include/dt-bindings/memory/tegra210-mc.h b/dts/include/dt-bindings/memory/tegra210-mc.h
index 4490f7c..cacf056 100644
--- a/dts/include/dt-bindings/memory/tegra210-mc.h
+++ b/dts/include/dt-bindings/memory/tegra210-mc.h
@@ -34,4 +34,35 @@
#define TEGRA_SWGROUP_ETR 29
#define TEGRA_SWGROUP_TSECB 30
+#define TEGRA210_MC_RESET_AFI 0
+#define TEGRA210_MC_RESET_AVPC 1
+#define TEGRA210_MC_RESET_DC 2
+#define TEGRA210_MC_RESET_DCB 3
+#define TEGRA210_MC_RESET_HC 4
+#define TEGRA210_MC_RESET_HDA 5
+#define TEGRA210_MC_RESET_ISP2 6
+#define TEGRA210_MC_RESET_MPCORE 7
+#define TEGRA210_MC_RESET_NVENC 8
+#define TEGRA210_MC_RESET_PPCS 9
+#define TEGRA210_MC_RESET_SATA 10
+#define TEGRA210_MC_RESET_VI 11
+#define TEGRA210_MC_RESET_VIC 12
+#define TEGRA210_MC_RESET_XUSB_HOST 13
+#define TEGRA210_MC_RESET_XUSB_DEV 14
+#define TEGRA210_MC_RESET_A9AVP 15
+#define TEGRA210_MC_RESET_TSEC 16
+#define TEGRA210_MC_RESET_SDMMC1 17
+#define TEGRA210_MC_RESET_SDMMC2 18
+#define TEGRA210_MC_RESET_SDMMC3 19
+#define TEGRA210_MC_RESET_SDMMC4 20