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-rw-r--r--Documentation/boards/imx.rst27
-rw-r--r--Documentation/boards/imx/amazon-kindle-4-5.rst81
-rw-r--r--Makefile2
-rw-r--r--arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg1
-rw-r--r--arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg1
-rw-r--r--arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg1
-rw-r--r--arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg1
-rw-r--r--arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg1
-rw-r--r--arch/arm/boards/freescale-mx51-babbage/board.c83
-rw-r--r--arch/arm/boards/freescale-mx51-babbage/flash-header-common.imxcfg58
-rw-r--r--arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg3
-rw-r--r--arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg60
-rw-r--r--arch/arm/boards/freescale-mx51-babbage/lowlevel.c25
-rw-r--r--arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg1
-rw-r--r--arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg1
-rw-r--r--arch/arm/boards/nxp-imx8mq-evk/board.c3
-rw-r--r--arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/emmc2
-rw-r--r--arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/mmc2
-rw-r--r--arch/arm/boards/zii-vf610-dev/board.c19
-rw-r--r--arch/arm/configs/imx_v7-xload_defconfig31
-rw-r--r--arch/arm/configs/kindle-mx50_defconfig70
-rw-r--r--arch/arm/cpu/cache-l2x0.c12
-rw-r--r--arch/arm/cpu/mmu.c2
-rw-r--r--arch/arm/cpu/mmu_64.c3
-rw-r--r--arch/arm/dts/am335x-bone-common-strip.dtsi297
-rw-r--r--arch/arm/dts/am335x-bone-common.dts2
-rw-r--r--arch/arm/dts/am335x-bone-common.dtsi290
-rw-r--r--arch/arm/dts/am33xx-strip.dtsi4
-rw-r--r--arch/arm/dts/imx51-babbage.dts20
-rw-r--r--arch/arm/dts/imx51-zii-rdu1.dts42
-rw-r--r--arch/arm/dts/tegra20-colibri.dtsi2
-rw-r--r--arch/arm/dts/vf610-zii-dev-rev-b.dts11
-rw-r--r--arch/arm/mach-imx/Kconfig46
-rw-r--r--arch/arm/mach-imx/Makefile1
-rw-r--r--arch/arm/mach-imx/imx-bbu-external-nand.c2
-rw-r--r--arch/arm/mach-imx/imx-bbu-internal.c344
-rw-r--r--arch/arm/mach-imx/imx50.c4
-rw-r--r--arch/arm/mach-imx/imx51.c4
-rw-r--r--arch/arm/mach-imx/imx53.c4
-rw-r--r--arch/arm/mach-imx/imx6.c5
-rw-r--r--arch/arm/mach-imx/include/mach/bbu.h60
-rw-r--r--arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h13
-rw-r--r--arch/arm/mach-imx/include/mach/imx-header.h19
-rw-r--r--arch/arm/mach-imx/include/mach/imx6-ccm-regs.h24
-rw-r--r--arch/arm/mach-imx/include/mach/ocotp-fusemap.h6
-rw-r--r--arch/arm/mach-imx/include/mach/usb.h23
-rw-r--r--arch/arm/mach-imx/xload-esdhc.c43
-rw-r--r--arch/arm/mach-imx/xload.c52
-rw-r--r--arch/arm/mach-omap/am33xx_bbu_emmc.c2
-rw-r--r--commands/Kconfig5
-rw-r--r--commands/dhcp.c10
-rw-r--r--commands/i2c.c31
-rw-r--r--commands/nand.c11
-rw-r--r--commands/of_property.c3
-rw-r--r--common/Makefile1
-rw-r--r--common/bbu.c14
-rw-r--r--common/block.c17
-rw-r--r--common/bootsource.c1
-rw-r--r--common/filetype.c11
-rw-r--r--drivers/clk/imx/clk-sccg-pll.c2
-rw-r--r--drivers/crypto/caam/caamrng.c9
-rw-r--r--drivers/crypto/caam/ctrl.c240
-rw-r--r--drivers/crypto/caam/ctrl.h1
-rw-r--r--drivers/crypto/caam/desc.h35
-rw-r--r--drivers/crypto/caam/desc_constr.h118
-rw-r--r--drivers/crypto/caam/error.c5
-rw-r--r--drivers/crypto/caam/jr.c64
-rw-r--r--drivers/crypto/caam/regs.h123
-rw-r--r--drivers/gpio/gpio-pca953x.c35
-rw-r--r--drivers/hab/hab.c6
-rw-r--r--drivers/hab/habv4.c247
-rw-r--r--drivers/led/Kconfig9
-rw-r--r--drivers/led/Makefile1
-rw-r--r--drivers/led/core.c4
-rw-r--r--drivers/led/led-pca955x.c421
-rw-r--r--drivers/mci/imx-esdhc.c4
-rw-r--r--drivers/mfd/rave-sp.c116
-rw-r--r--drivers/net/Kconfig1
-rw-r--r--drivers/net/fec_imx.c4
-rw-r--r--drivers/pinctrl/imx-iomux-v3.c2
-rw-r--r--dts/Bindings/arm/adapteva.txt7
-rw-r--r--dts/Bindings/arm/amlogic.txt13
-rw-r--r--dts/Bindings/arm/atmel-pmc.txt14
-rw-r--r--dts/Bindings/arm/bcm/brcm,brcmstb.txt4
-rw-r--r--dts/Bindings/arm/coresight.txt58
-rw-r--r--dts/Bindings/arm/cpu-capacity.txt2
-rw-r--r--dts/Bindings/arm/cpus.txt2
-rw-r--r--dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt3
-rw-r--r--dts/Bindings/arm/freescale/m4if.txt12
-rw-r--r--dts/Bindings/arm/freescale/tigerp.txt12
-rw-r--r--dts/Bindings/arm/fsl.txt4
-rw-r--r--dts/Bindings/arm/idle-states.txt4
-rw-r--r--dts/Bindings/arm/insignal-boards.txt8
-rw-r--r--dts/Bindings/arm/marvell/ap806-system-controller.txt48
-rw-r--r--dts/Bindings/arm/marvell/armada-37xx.txt15
-rw-r--r--dts/Bindings/arm/marvell/cp110-system-controller.txt (renamed from dts/Bindings/arm/marvell/cp110-system-controller0.txt)61
-rw-r--r--dts/Bindings/arm/mediatek.txt10
-rw-r--r--dts/Bindings/arm/msm/qcom,llcc.txt26
-rw-r--r--dts/Bindings/arm/omap/crossbar.txt1
-rw-r--r--dts/Bindings/arm/omap/l4.txt15
-rw-r--r--dts/Bindings/arm/rockchip.txt14
-rw-r--r--dts/Bindings/arm/samsung/pmu.txt3
-rw-r--r--dts/Bindings/arm/samsung/samsung-boards.txt5
-rw-r--r--dts/Bindings/arm/shmobile.txt5
-rw-r--r--dts/Bindings/arm/ti/k3.txt23
-rw-r--r--dts/Bindings/arm/xilinx.txt30
-rw-r--r--dts/Bindings/ata/ahci-platform.txt2
-rw-r--r--dts/Bindings/ata/fsl-sata.txt1
-rw-r--r--dts/Bindings/ata/pata-arasan.txt2
-rw-r--r--dts/Bindings/ata/sata_rcar.txt1
-rw-r--r--dts/Bindings/board/fsl-board.txt1
-rw-r--r--dts/Bindings/bus/brcm,gisb-arb.txt2
-rw-r--r--dts/Bindings/bus/sun50i-de2-bus.txt37
-rw-r--r--dts/Bindings/bus/ti-sysc.txt1
-rw-r--r--dts/Bindings/clock/actions,owl-cmu.txt (renamed from dts/Bindings/clock/actions,s900-cmu.txt)20
-rw-r--r--dts/Bindings/clock/amlogic,axg-audio-clkc.txt56
-rw-r--r--dts/Bindings/clock/at91-clock.txt51
-rw-r--r--dts/Bindings/clock/exynos5440-clock.txt28
-rw-r--r--dts/Bindings/clock/maxim,max9485.txt59
-rw-r--r--dts/Bindings/clock/qcom,dispcc.txt19
-rw-r--r--dts/Bindings/clock/renesas,r9a06g032-sysctrl.txt43
-rw-r--r--dts/Bindings/clock/rockchip,px30-cru.txt65
-rw-r--r--dts/Bindings/clock/sun8i-de2.txt1
-rw-r--r--dts/Bindings/connector/usb-connector.txt44
-rw-r--r--dts/Bindings/cpufreq/brcm,stb-avs-cpu-freq.txt2
-rw-r--r--dts/Bindings/cpufreq/cpufreq-exynos5440.txt28
-rw-r--r--dts/Bindings/crypto/amd-ccp.txt2
-rw-r--r--dts/Bindings/crypto/arm-cryptocell.txt2
-rw-r--r--dts/Bindings/crypto/fsl-sec2.txt5
-rw-r--r--dts/Bindings/crypto/fsl-sec4.txt21
-rw-r--r--dts/Bindings/crypto/hisilicon,hip07-sec.txt67
-rw-r--r--dts/Bindings/crypto/inside-secure-safexcel.txt15
-rw-r--r--dts/Bindings/crypto/picochip-spacc.txt2
-rw-r--r--dts/Bindings/crypto/qcom,prng.txt (renamed from dts/Bindings/rng/qcom,prng.txt)4
-rw-r--r--dts/Bindings/devfreq/rk3399_dmc.txt211
-rw-r--r--dts/Bindings/display/brcm,bcm-vc4.txt6
-rw-r--r--dts/Bindings/display/bridge/analogix_dp.txt2
-rw-r--r--dts/Bindings/display/bridge/anx7814.txt2
-rw-r--r--dts/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt2
-rw-r--r--dts/Bindings/display/bridge/sii902x.txt4
-rw-r--r--dts/Bindings/display/bridge/sii9234.txt2
-rw-r--r--dts/Bindings/display/bridge/sil-sii8620.txt2
-rw-r--r--dts/Bindings/display/exynos/exynos7-decon.txt3
-rw-r--r--dts/Bindings/display/exynos/exynos_dp.txt2
-rw-r--r--dts/Bindings/display/exynos/samsung-fimd.txt3
-rw-r--r--dts/Bindings/display/ht16k33.txt2
-rw-r--r--dts/Bindings/display/ilitek,ili9341.txt27
-rw-r--r--dts/Bindings/display/marvell,pxa2xx-lcdc.txt3
-rw-r--r--dts/Bindings/display/marvell,pxa300-gcu.txt17
-rw-r--r--dts/Bindings/display/mediatek/mediatek,disp.txt2
-rw-r--r--dts/Bindings/display/msm/dpu.txt131
-rw-r--r--dts/Bindings/display/msm/dsi.txt18
-rw-r--r--dts/Bindings/display/msm/edp.txt4
-rw-r--r--dts/Bindings/display/msm/mdp5.txt2
-rw-r--r--dts/Bindings/display/panel/auo,g070vvn01.txt29
-rw-r--r--dts/Bindings/display/panel/boe,hv070wsa-100.txt28
-rw-r--r--dts/Bindings/display/panel/dataimage,scf0700c48ggu18.txt8
-rw-r--r--dts/Bindings/display/panel/dlc,dlc0700yzg-1.txt13
-rw-r--r--dts/Bindings/display/panel/edt,et-series.txt39
-rw-r--r--dts/Bindings/display/panel/edt,et070080dh6.txt10
-rw-r--r--dts/Bindings/display/panel/edt,etm0700g0dh6.txt10
-rw-r--r--dts/Bindings/display/panel/ilitek,ili9881c.txt20
-rw-r--r--dts/Bindings/display/panel/innolux,g070y2-l01.txt12
-rw-r--r--dts/Bindings/display/panel/innolux,p097pfg.txt24
-rw-r--r--dts/Bindings/display/panel/innolux,tv123wam.txt20
-rw-r--r--dts/Bindings/display/panel/kingdisplay,kd097d04.txt22
-rw-r--r--dts/Bindings/display/panel/newhaven,nhd-4.3-480272ef-atxl.txt (renamed from dts/Bindings/display/panel/edt,et057090dhu.txt)4
-rw-r--r--dts/Bindings/display/panel/rocktech,rk070er9427.txt25
-rw-r--r--dts/Bindings/display/panel/sharp,lq035q7db03.txt12
-rw-r--r--dts/Bindings/display/renesas,du.txt1
-rw-r--r--dts/Bindings/display/sm501fb.txt2
-rw-r--r--dts/Bindings/display/sunxi/sun4i-drm.txt64
-rw-r--r--dts/Bindings/display/tilcdc/tilcdc.txt2
-rw-r--r--dts/Bindings/dma/jz4780-dma.txt1
-rw-r--r--dts/Bindings/dma/nvidia,tegra210-adma.txt1
-rw-r--r--dts/Bindings/dma/owl-dma.txt47
-rw-r--r--dts/Bindings/dma/renesas,rcar-dmac.txt1
-rw-r--r--dts/Bindings/dma/snps,dw-axi-dmac.txt2
-rw-r--r--dts/Bindings/dma/snps-dma.txt2
-rw-r--r--dts/Bindings/dma/ti-edma.txt1
-rw-r--r--dts/Bindings/dma/xilinx/xilinx_dma.txt2
-rw-r--r--dts/Bindings/dma/xilinx/zynqmp_dma.txt1
-rw-r--r--dts/Bindings/eeprom/at24.txt2
-rw-r--r--dts/Bindings/extcon/extcon-rt8973a.txt2
-rw-r--r--dts/Bindings/extcon/extcon-sm5502.txt2
-rw-r--r--dts/Bindings/fsi/fsi-master-ast-cf.txt36
-rw-r--r--dts/Bindings/fsi/fsi.txt5
-rw-r--r--dts/Bindings/gnss/gnss.txt36
-rw-r--r--dts/Bindings/gnss/sirfstar.txt45
-rw-r--r--dts/Bindings/gnss/u-blox.txt44
-rw-r--r--dts/Bindings/gpio/8xxx_gpio.txt2
-rw-r--r--dts/Bindings/gpio/abilis,tb10x-gpio.txt1
-rw-r--r--dts/Bindings/gpio/brcm,brcmstb-gpio.txt3
-rw-r--r--dts/Bindings/gpio/fsl-imx-gpio.txt3
-rw-r--r--dts/Bindings/gpio/gpio-adnp.txt1
-rw-r--r--dts/Bindings/gpio/gpio-aspeed.txt1
-rw-r--r--dts/Bindings/gpio/gpio-ath79.txt1
-rw-r--r--dts/Bindings/gpio/gpio-davinci.txt2
-rw-r--r--dts/Bindings/gpio/gpio-max732x.txt1
-rw-r--r--dts/Bindings/gpio/gpio-pca953x.txt3
-rw-r--r--dts/Bindings/gpio/gpio-pcf857x.txt1
-rw-r--r--dts/Bindings/gpio/gpio-uniphier.txt1
-rw-r--r--dts/Bindings/gpio/gpio-xgene-sb.txt1
-rw-r--r--dts/Bindings/gpio/gpio-xilinx.txt2
-rw-r--r--dts/Bindings/gpio/gpio-xlp.txt1
-rw-r--r--dts/Bindings/gpio/gpio-zynq.txt1
-rw-r--r--dts/Bindings/gpio/mediatek,mt7621-gpio.txt35
-rw-r--r--dts/Bindings/gpio/nintendo,hollywood-gpio.txt1
-rw-r--r--dts/Bindings/gpio/nvidia,tegra186-gpio.txt4
-rw-r--r--dts/Bindings/gpio/renesas,gpio-rcar.txt2
-rw-r--r--dts/Bindings/gpio/rockchip,rk3328-grf-gpio.txt32
-rw-r--r--dts/Bindings/gpio/snps-dwapb-gpio.txt1
-rw-r--r--dts/Bindings/hsi/omap-ssi.txt1
-rw-r--r--dts/Bindings/hwmon/npcm750-pwm-fan.txt84
-rw-r--r--dts/Bindings/i2c/i2c-aspeed.txt3
-rw-r--r--dts/Bindings/i2c/i2c-brcmstb.txt2
-rw-r--r--dts/Bindings/i2c/i2c-fsi.txt40
-rw-r--r--dts/Bindings/i2c/i2c-imx-lpi2c.txt1
-rw-r--r--dts/Bindings/i2c/i2c-jz4780.txt4
-rw-r--r--dts/Bindings/i2c/i2c-mpc.txt2
-rw-r--r--dts/Bindings/i2c/i2c-mux-pca954x.txt2
-rw-r--r--dts/Bindings/i2c/i2c-owl.txt27
-rw-r--r--dts/Bindings/i2c/i2c-pca-platform.txt2
-rw-r--r--dts/Bindings/i2c/i2c-pnx.txt2
-rw-r--r--dts/Bindings/i2c/i2c-pxa.txt3
-rw-r--r--dts/Bindings/i2c/i2c-rcar.txt5
-rw-r--r--dts/Bindings/i2c/i2c-sh_mobile.txt4
-rw-r--r--dts/Bindings/iio/accel/adxl345.txt9
-rw-r--r--dts/Bindings/iio/accel/bma180.txt2
-rw-r--r--dts/Bindings/iio/accel/mma8452.txt2
-rw-r--r--dts/Bindings/iio/adc/amlogic,meson-saradc.txt1
-rw-r--r--dts/Bindings/iio/adc/at91-sama5d2_adc.txt9
-rw-r--r--dts/Bindings/iio/adc/avia-hx711.txt8
-rw-r--r--dts/Bindings/iio/adc/cpcap-adc.txt1
-rw-r--r--dts/Bindings/iio/adc/fsl,imx25-gcq.txt1
-rw-r--r--dts/Bindings/iio/adc/max1027-adc.txt2
-rw-r--r--dts/Bindings/iio/adc/sigma-delta-modulator.txt2
-rw-r--r--dts/Bindings/iio/adc/sprd,sc27xx-adc.txt36
-rw-r--r--dts/Bindings/iio/adc/st,stm32-adc.txt1
-rw-r--r--dts/Bindings/iio/adc/xilinx-xadc.txt1
-rw-r--r--dts/Bindings/iio/chemical/atlas,ec-sm.txt1
-rw-r--r--dts/Bindings/iio/chemical/atlas,orp-sm.txt1
-rw-r--r--dts/Bindings/iio/chemical/atlas,ph-sm.txt1
-rw-r--r--dts/Bindings/iio/dac/ad5758.txt78
-rw-r--r--dts/Bindings/iio/gyroscope/invensense,mpu3050.txt1
-rw-r--r--dts/Bindings/iio/health/afe4403.txt1
-rw-r--r--dts/Bindings/iio/health/afe4404.txt1
-rw-r--r--dts/Bindings/iio/health/max30100.txt1
-rw-r--r--dts/Bindings/iio/health/max30102.txt1
-rw-r--r--dts/Bindings/iio/humidity/hts221.txt1
-rw-r--r--dts/Bindings/iio/imu/bmi160.txt1
-rw-r--r--dts/Bindings/iio/imu/inv_mpu6050.txt2
-rw-r--r--dts/Bindings/iio/imu/st_lsm6dsx.txt1
-rw-r--r--dts/Bindings/iio/light/apds9300.txt1
-rw-r--r--dts/Bindings/iio/light/apds9960.txt1
-rw-r--r--dts/Bindings/iio/light/isl29018.txt1
-rw-r--r--dts/Bindings/iio/light/isl29501.txt13
-rw-r--r--dts/Bindings/iio/light/opt3001.txt1
-rw-r--r--dts/Bindings/iio/light/tsl2583.txt1
-rw-r--r--dts/Bindings/iio/light/uvis25.txt1
-rw-r--r--dts/Bindings/iio/magnetometer/bmc150_magn.txt1
-rw-r--r--dts/Bindings/iio/pressure/bmp085.txt8
-rw-r--r--dts/Bindings/iio/pressure/zpa2326.txt2
-rw-r--r--dts/Bindings/iio/proximity/as3935.txt1
-rw-r--r--dts/Bindings/iio/proximity/sx9500.txt1
-rw-r--r--dts/Bindings/iio/sensorhub.txt1
-rw-r--r--dts/Bindings/iio/temperature/tmp007.txt2
-rw-r--r--dts/Bindings/infiniband/hisilicon-hns-roce.txt1
-rw-r--r--dts/Bindings/input/cypress,cyapa.txt2
-rw-r--r--dts/Bindings/input/cypress,tm2-touchkey.txt2
-rw-r--r--dts/Bindings/input/e3x0-button.txt2
-rw-r--r--dts/Bindings/input/elan_i2c.txt2
-rw-r--r--dts/Bindings/input/elants_i2c.txt2
-rw-r--r--dts/Bindings/input/hid-over-i2c.txt4
-rw-r--r--dts/Bindings/input/keys.txt8
-rw-r--r--dts/Bindings/input/qcom,pm8941-pwrkey.txt10
-rw-r--r--dts/Bindings/input/raydium_i2c_ts.txt1
-rw-r--r--dts/Bindings/input/rmi4/rmi_i2c.txt1
-rw-r--r--dts/Bindings/input/rmi4/rmi_spi.txt1
-rw-r--r--dts/Bindings/input/ti,palmas-pwrbutton.txt1
-rw-r--r--dts/Bindings/input/touchscreen/ad7879.txt1
-rw-r--r--dts/Bindings/input/touchscreen/ads7846.txt1
-rw-r--r--dts/Bindings/input/touchscreen/ar1021.txt1
-rw-r--r--dts/Bindings/input/touchscreen/bu21029.txt35
-rw-r--r--dts/Bindings/input/touchscreen/chipone_icn8318.txt2
-rw-r--r--dts/Bindings/input/touchscreen/colibri-vf50-ts.txt1
-rw-r--r--dts/Bindings/input/touchscreen/cyttsp.txt2
-rw-r--r--dts/Bindings/input/touchscreen/edt-ft5x06.txt2
-rw-r--r--dts/Bindings/input/touchscreen/eeti.txt30
-rw-r--r--dts/Bindings/input/touchscreen/egalax-ts.txt1
-rw-r--r--dts/Bindings/input/touchscreen/ektf2127.txt2
-rw-r--r--dts/Bindings/input/touchscreen/exc3000.txt1
-rw-r--r--dts/Bindings/input/touchscreen/fsl-mx25-tcq.txt1
-rw-r--r--dts/Bindings/input/touchscreen/goodix.txt1
-rw-r--r--dts/Bindings/input/touchscreen/hideep.txt1
-rw-r--r--dts/Bindings/input/touchscreen/max11801-ts.txt1
-rw-r--r--dts/Bindings/input/touchscreen/melfas_mip4.txt1
-rw-r--r--dts/Bindings/input/touchscreen/resistive-adc-touch.txt30
-rw-r--r--dts/Bindings/input/touchscreen/samsung,s6sy761.txt2
-rw-r--r--dts/Bindings/input/touchscreen/silead_gsl1680.txt2
-rw-r--r--dts/Bindings/input/touchscreen/sis_i2c.txt2
-rw-r--r--dts/Bindings/input/touchscreen/st,stmfts.txt2
-rw-r--r--dts/Bindings/input/touchscreen/sx8654.txt1
-rw-r--r--dts/Bindings/input/touchscreen/touchscreen.txt3
-rw-r--r--dts/Bindings/input/touchscreen/tsc2007.txt2
-rw-r--r--dts/Bindings/input/touchscreen/zet6223.txt2
-rw-r--r--dts/Bindings/interrupt-controller/abilis,tb10x-ictl.txt1
-rw-r--r--dts/Bindings/interrupt-controller/al,alpine-msix.txt1
-rw-r--r--dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt1
-rw-r--r--dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt3
-rw-r--r--dts/Bindings/interrupt-controller/atmel,aic.txt2
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt2
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt2
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt2
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt2
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt2
-rw-r--r--dts/Bindings/interrupt-controller/brcm,l2-intc.txt2
-rw-r--r--dts/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt3
-rw-r--r--dts/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt2
-rw-r--r--dts/Bindings/interrupt-controller/ingenic,intc.txt2
-rw-r--r--dts/Bindings/interrupt-controller/marvell,odmi-controller.txt2
-rw-r--r--dts/Bindings/interrupt-controller/mediatek,cirq.txt2
-rw-r--r--dts/Bindings/interrupt-controller/mediatek,sysirq.txt3
-rw-r--r--dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt1
-rw-r--r--dts/Bindings/interrupt-controller/nvidia,tegra20-ictlr.txt2
-rw-r--r--dts/Bindings/interrupt-controller/nxp,lpc3220-mic.txt2
-rw-r--r--dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt1
-rw-r--r--dts/Bindings/interrupt-controller/qcom,pdc.txt6
-rw-r--r--dts/Bindings/interrupt-controller/renesas,irqc.txt3
-rw-r--r--dts/Bindings/interrupt-controller/riscv,cpu-intc.txt52
-rw-r--r--dts/Bindings/interrupt-controller/samsung,exynos4210-combiner.txt2
-rw-r--r--dts/Bindings/interrupt-controller/sifive,plic-1.0.0.txt58
-rw-r--r--dts/Bindings/interrupt-controller/sigma,smp8642-intc.txt1
-rw-r--r--dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt1
-rw-r--r--dts/Bindings/interrupt-controller/snps,dw-apb-ictl.txt1
-rw-r--r--dts/Bindings/interrupt-controller/socionext,synquacer-exiu.txt1
-rw-r--r--dts/Bindings/interrupt-controller/st,spear3xx-shirq.txt4
-rw-r--r--dts/Bindings/interrupt-controller/technologic,ts4800.txt2
-rw-r--r--dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt1
-rw-r--r--dts/Bindings/interrupt-controller/ti,omap4-wugen-mpu2
-rw-r--r--dts/Bindings/iommu/mediatek,iommu.txt6
-rw-r--r--dts/Bindings/iommu/renesas,ipmmu-vmsa.txt3
-rw-r--r--dts/Bindings/iommu/samsung,sysmmu.txt1
-rw-r--r--dts/Bindings/leds/backlight/pwm-backlight.txt34
-rw-r--r--dts/Bindings/leds/common.txt2
-rw-r--r--dts/Bindings/leds/leds-lm3692x.txt5
-rw-r--r--dts/Bindings/leds/leds-lt3593.txt32
-rw-r--r--dts/Bindings/mailbox/altera-mailbox.txt1
-rw-r--r--dts/Bindings/mailbox/fsl,mu.txt54
-rw-r--r--dts/Bindings/mailbox/mtk-gce.txt57
-rw-r--r--dts/Bindings/mailbox/ti,secure-proxy.txt50
-rw-r--r--dts/Bindings/media/cec-gpio.txt22
-rw-r--r--dts/Bindings/media/i2c/ak7375.txt8
-rw-r--r--dts/Bindings/media/i2c/aptina,mt9v111.txt46
-rw-r--r--dts/Bindings/media/i2c/dongwoon,dw9807.txt9
-rw-r--r--dts/Bindings/media/i2c/nokia,smia.txt3
-rw-r--r--dts/Bindings/media/i2c/ov2680.txt46
-rw-r--r--dts/Bindings/media/i2c/ov5640.txt5
-rw-r--r--dts/Bindings/media/i2c/tc358743.txt2
-rw-r--r--dts/Bindings/media/nvidia,tegra-vde.txt11
-rw-r--r--dts/Bindings/media/qcom,camss.txt128
-rw-r--r--dts/Bindings/media/qcom,venus.txt1
-rw-r--r--dts/Bindings/media/rcar_vin.txt54
-rw-r--r--dts/Bindings/media/sh_mobile_ceu.txt1
-rw-r--r--dts/Bindings/media/video-interfaces.txt6
-rw-r--r--dts/Bindings/memory-controllers/mediatek,smi-common.txt6
-rw-r--r--dts/Bindings/memory-controllers/mediatek,smi-larb.txt5
-rw-r--r--dts/Bindings/mfd/ac100.txt4
-rw-r--r--dts/Bindings/mfd/altera-a10sr.txt1
-rw-r--r--dts/Bindings/mfd/arizona.txt1
-rw-r--r--dts/Bindings/mfd/as3722.txt2
-rw-r--r--dts/Bindings/mfd/axp20x.txt8
-rw-r--r--dts/Bindings/mfd/bd9571mwv.txt1
-rw-r--r--dts/Bindings/mfd/bfticu.txt1
-rw-r--r--dts/Bindings/mfd/da9055.txt2
-rw-r--r--dts/Bindings/mfd/da9062.txt2
-rw-r--r--dts/Bindings/mfd/da9063.txt2
-rw-r--r--dts/Bindings/mfd/da9150.txt2
-rw-r--r--dts/Bindings/mfd/madera.txt102
-rw-r--r--dts/Bindings/mfd/max14577.txt1
-rw-r--r--dts/Bindings/mfd/max77686.txt1
-rw-r--r--dts/Bindings/mfd/max77693.txt1
-rw-r--r--dts/Bindings/mfd/max77802.txt1
-rw-r--r--dts/Bindings/mfd/max8998.txt2
-rw-r--r--dts/Bindings/mfd/motorola-cpcap.txt1
-rw-r--r--dts/Bindings/mfd/palmas.txt1
-rw-r--r--dts/Bindings/mfd/retu.txt1
-rw-r--r--dts/Bindings/mfd/rk808.txt1
-rw-r--r--dts/Bindings/mfd/rohm,bd71837-pmic.txt62
-rw-r--r--dts/Bindings/mfd/samsung,sec-core.txt2
-rw-r--r--dts/Bindings/mfd/stmpe.txt1
-rw-r--r--dts/Bindings/mfd/tc3589x.txt1
-rw-r--r--dts/Bindings/mfd/tps65086.txt1
-rw-r--r--dts/Bindings/mfd/tps65910.txt2
-rw-r--r--dts/Bindings/mfd/tps65912.txt1
-rw-r--r--dts/Bindings/mfd/twl-familly.txt1
-rw-r--r--dts/Bindings/mfd/twl6040.txt1
-rw-r--r--dts/Bindings/mfd/wm831x.txt1
-rw-r--r--dts/Bindings/mips/cavium/cib.txt2
-rw-r--r--dts/Bindings/misc/aspeed,cvic.txt35
-rw-r--r--dts/Bindings/mmc/arasan,sdhci.txt4
-rw-r--r--dts/Bindings/mmc/fsl-esdhc.txt1
-rw-r--r--dts/Bindings/mmc/mmc-spi-slot.txt2
-rw-r--r--dts/Bindings/mmc/pxa-mmc.txt6
-rw-r--r--dts/Bindings/mmc/rockchip-dw-mshc.txt1
-rw-r--r--dts/Bindings/mmc/sdhci-msm.txt7
-rw-r--r--dts/Bindings/mmc/sdhci-of-dwcmshc.txt20
-rw-r--r--dts/Bindings/mmc/sunxi-mmc.txt2
-rw-r--r--dts/Bindings/mmc/tmio_mmc.txt1
-rw-r--r--dts/Bindings/mtd/brcm,brcmnand.txt1
-rw-r--r--dts/Bindings/mtd/denali-nand.txt5
-rw-r--r--dts/Bindings/mtd/gpmc-nand.txt1
-rw-r--r--dts/Bindings/mtd/jedec,spi-nor.txt9
-rw-r--r--dts/Bindings/mtd/nand.txt6
-rw-r--r--dts/Bindings/mtd/nvidia-tegra20-nand.txt64
-rw-r--r--dts/Bindings/mtd/partition.txt46
-rw-r--r--dts/Bindings/mtd/partitions/brcm,trx.txt37
-rw-r--r--dts/Bindings/mtd/qcom_nandc.txt7
-rw-r--r--dts/Bindings/mtd/spear_smi.txt2
-rw-r--r--dts/Bindings/mtd/spi-nand.txt5
-rw-r--r--dts/Bindings/mux/adi,adgs1408.txt48
-rw-r--r--dts/Bindings/net/amd-xgbe.txt2
-rw-r--r--dts/Bindings/net/brcm,mdio-mux-iproc.txt7
-rw-r--r--dts/Bindings/net/btusb.txt1
-rw-r--r--dts/Bindings/net/can/holt_hi311x.txt1
-rw-r--r--dts/Bindings/net/can/microchip,mcp251x.txt1
-rw-r--r--dts/Bindings/net/can/xilinx_can.txt36
-rw-r--r--dts/Bindings/net/cpsw.txt1
-rw-r--r--dts/Bindings/net/davicom-dm9000.txt1
-rw-r--r--dts/Bindings/net/dsa/b53.txt8
-rw-r--r--dts/Bindings/net/dsa/ksz.txt4
-rw-r--r--dts/Bindings/net/dsa/marvell.txt1
-rw-r--r--dts/Bindings/net/dsa/realtek-smi.txt153
-rw-r--r--dts/Bindings/net/dsa/vitesse,vsc73xx.txt81
-rw-r--r--dts/Bindings/net/dwmac-sun8i.txt8
-rw-r--r--dts/Bindings/net/fsl-fman.txt25
-rw-r--r--dts/Bindings/net/hisilicon-hns-dsaf.txt1
-rw-r--r--dts/Bindings/net/ibm,emac.txt1
-rw-r--r--dts/Bindings/net/marvell-bt-8xxx.txt1
-rw-r--r--dts/Bindings/net/mediatek,mt7620-gsw.txt2
-rw-r--r--dts/Bindings/net/mediatek-bluetooth.txt35
-rw-r--r--dts/Bindings/net/mediatek-net.txt3
-rw-r--r--dts/Bindings/net/microchip,enc28j60.txt3
-rw-r--r--dts/Bindings/net/nfc/nxp-nci.txt1
-rw-r--r--dts/Bindings/net/nfc/pn533-i2c.txt1
-rw-r--r--dts/Bindings/net/nfc/pn544.txt3
-rw-r--r--dts/Bindings/net/nfc/s3fwrn5.txt1
-rw-r--r--dts/Bindings/net/nfc/st-nci-i2c.txt1
-rw-r--r--dts/Bindings/net/nfc/st-nci-spi.txt1
-rw-r--r--dts/Bindings/net/nfc/st21nfca.txt2
-rw-r--r--dts/Bindings/net/nfc/st95hf.txt3
-rw-r--r--dts/Bindings/net/nfc/trf7970a.txt1
-rw-r--r--dts/Bindings/net/phy.txt2
-rw-r--r--dts/Bindings/net/qca,qca7000.txt1
-rw-r--r--dts/Bindings/net/qualcomm-bluetooth.txt29
-rw-r--r--dts/Bindings/net/ralink,rt2880-net.txt2
-rw-r--r--dts/Bindings/net/ralink,rt3050-esw.txt2
-rw-r--r--dts/Bindings/net/renesas,ravb.txt5
-rw-r--r--dts/Bindings/net/rockchip-dwmac.txt1
-rw-r--r--dts/Bindings/net/samsung-sxgbe.txt2
-rw-r--r--dts/Bindings/net/sh_eth.txt2
-rw-r--r--dts/Bindings/net/snps,dwc-qos-ethernet.txt2
-rw-r--r--dts/Bindings/net/stmmac.txt7
-rw-r--r--dts/Bindings/net/wireless/brcm,bcm43xx-fmac.txt2
-rw-r--r--dts/Bindings/net/wireless/marvell-8xxx.txt1
-rw-r--r--dts/Bindings/net/wireless/ti,wl1251.txt2
-rw-r--r--dts/Bindings/net/wireless/ti,wlcore,spi.txt4
-rw-r--r--dts/Bindings/net/wireless/ti,wlcore.txt2
-rw-r--r--dts/Bindings/nvmem/imx-ocotp.txt3
-rw-r--r--dts/Bindings/nvmem/sc27xx-efuse.txt52
-rw-r--r--dts/Bindings/pci/altera-pcie-msi.txt1
-rw-r--r--dts/Bindings/pci/altera-pcie.txt1
-rw-r--r--dts/Bindings/pci/brcm,iproc-pcie.txt1
-rw-r--r--dts/Bindings/pci/cdns,cdns-pcie-ep.txt5
-rw-r--r--dts/Bindings/pci/cdns,cdns-pcie-host.txt6
-rw-r--r--dts/Bindings/pci/faraday,ftpci100.txt1
-rw-r--r--dts/Bindings/pci/mobiveil-pcie.txt3
-rw-r--r--dts/Bindings/pci/pci-keystone.txt3
-rw-r--r--dts/Bindings/pci/ralink,rt3883-pci.txt3
-rw-r--r--dts/Bindings/phy/brcm,sr-pcie-phy.txt41
-rw-r--r--dts/Bindings/phy/phy-ath79-usb.txt4
-rw-r--r--dts/Bindings/phy/phy-mtk-tphy.txt6
-rw-r--r--dts/Bindings/phy/qcom-qmp-phy.txt14
-rw-r--r--dts/Bindings/phy/rcar-gen3-phy-pcie.txt24
-rw-r--r--dts/Bindings/phy/rcar-gen3-phy-usb2.txt2
-rw-r--r--dts/Bindings/pinctrl/actions,s900-pinctrl.txt10
-rw-r--r--dts/Bindings/pinctrl/atmel,at91-pio4-pinctrl.txt3
-rw-r--r--dts/Bindings/pinctrl/berlin,pinctrl.txt3
-rw-r--r--dts/Bindings/pinctrl/cirrus,madera-pinctrl.txt99
-rw-r--r--dts/Bindings/pinctrl/fsl,imx8mq-pinctrl.txt36
-rw-r--r--dts/Bindings/pinctrl/nvidia,tegra124-pinmux.txt2
-rw-r--r--dts/Bindings/pinctrl/nvidia,tegra210-pinmux.txt2
-rw-r--r--dts/Bindings/pinctrl/pinctrl-bindings.txt6
-rw-r--r--dts/Bindings/pinctrl/pinctrl-mt7622.txt2
-rw-r--r--dts/Bindings/pinctrl/pinctrl-sx150x.txt2
-rw-r--r--dts/Bindings/pinctrl/qcom,apq8064-pinctrl.txt6
-rw-r--r--dts/Bindings/pinctrl/qcom,apq8084-pinctrl.txt9
-rw-r--r--dts/Bindings/pinctrl/qcom,ipq4019-pinctrl.txt6
-rw-r--r--dts/Bindings/pinctrl/qcom,ipq8064-pinctrl.txt6
-rw-r--r--dts/Bindings/pinctrl/qcom,ipq8074-pinctrl.txt9
-rw-r--r--dts/Bindings/pinctrl/qcom,mdm9615-pinctrl.txt9
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8660-pinctrl.txt6
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8916-pinctrl.txt9
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8960-pinctrl.txt9
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8974-pinctrl.txt6
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8994-pinctrl.txt9
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8996-pinctrl.txt9
-rw-r--r--dts/Bindings/pinctrl/qcom,pmic-gpio.txt6
-rw-r--r--dts/Bindings/pinctrl/samsung-pinctrl.txt17
-rw-r--r--dts/Bindings/pinctrl/st,stm32-pinctrl.txt11
-rw-r--r--dts/Bindings/power/power_domain.txt8
-rw-r--r--dts/Bindings/power/reset/qcom,pon.txt45
-rw-r--r--dts/Bindings/power/supply/act8945a-charger.txt2
-rw-r--r--dts/Bindings/power/supply/bq24257.txt2
-rw-r--r--dts/Bindings/power/supply/lp8727_charger.txt1
-rw-r--r--dts/Bindings/power/supply/maxim,ds2760.txt26
-rw-r--r--dts/Bindings/power/supply/maxim,max14656.txt1
-rw-r--r--dts/Bindings/power/supply/rt9455_charger.txt2
-rw-r--r--dts/Bindings/power/supply/sbs_sbs-battery.txt12
-rw-r--r--dts/Bindings/power/supply/sbs_sbs-charger.txt2
-rw-r--r--dts/Bindings/powerpc/4xx/akebono.txt2
-rw-r--r--dts/Bindings/powerpc/4xx/hsta.txt1
-rw-r--r--dts/Bindings/powerpc/4xx/ppc440spe-adma.txt2
-rw-r--r--dts/Bindings/powerpc/fsl/dcsr.txt7
-rw-r--r--dts/Bindings/powerpc/fsl/diu.txt2
-rw-r--r--dts/Bindings/powerpc/fsl/dma.txt4
-rw-r--r--dts/Bindings/powerpc/fsl/ecm.txt4
-rw-r--r--dts/Bindings/powerpc/fsl/mcm.txt4
-rw-r--r--dts/Bindings/powerpc/fsl/mpc5121-psc.txt4
-rw-r--r--dts/Bindings/powerpc/fsl/msi-pic.txt5
-rw-r--r--dts/Bindings/powerpc/fsl/pamu.txt2
-rw-r--r--dts/Bindings/powerpc/nintendo/wii.txt1
-rw-r--r--dts/Bindings/ptp/ptp-qoriq.txt15
-rw-r--r--dts/Bindings/pwm/pwm-fsl-ftm.txt5
-rw-r--r--dts/Bindings/pwm/pwm-mediatek.txt4
-rw-r--r--dts/Bindings/pwm/renesas,pwm-rcar.txt1
-rw-r--r--dts/Bindings/regulator/cpcap-regulator.txt1
-rw-r--r--dts/Bindings/regulator/max8997-regulator.txt2
-rw-r--r--dts/Bindings/regulator/palmas-pmic.txt1
-rw-r--r--dts/Bindings/regulator/pfuze100.txt86
-rw-r--r--dts/Bindings/regulator/qcom,rpmh-regulator.txt160
-rw-r--r--dts/Bindings/regulator/rohm,bd71837-regulator.txt8
-rw-r--r--dts/Bindings/regulator/uniphier-regulator.txt57
-rw-r--r--dts/Bindings/remoteproc/qcom,q6v5.txt7
-rw-r--r--dts/Bindings/remoteproc/ti,davinci-rproc.txt6
-rw-r--r--dts/Bindings/remoteproc/ti,keystone-rproc.txt6
-rw-r--r--dts/Bindings/reserved-memory/reserved-memory.txt2
-rw-r--r--dts/Bindings/reset/amlogic,meson-axg-audio-arb.txt21
-rw-r--r--dts/Bindings/reset/qcom,aoss-reset.txt52
-rw-r--r--dts/Bindings/reset/uniphier-reset.txt56
-rw-r--r--dts/Bindings/rtc/brcm,brcmstb-waketimer.txt2
-rw-r--r--dts/Bindings/rtc/isil,isl12057.txt3
-rw-r--r--dts/Bindings/rtc/isil,isl1219.txt29
-rw-r--r--dts/Bindings/rtc/rtc-cmos.txt1
-rw-r--r--dts/Bindings/rtc/rtc-ds1307.txt2
-rw-r--r--dts/Bindings/rtc/rtc-m41t80.txt1
-rw-r--r--dts/Bindings/rtc/rtc-omap.txt1
-rw-r--r--dts/Bindings/rtc/rtc-palmas.txt1
-rw-r--r--dts/Bindings/rtc/spear-rtc.txt2
-rw-r--r--dts/Bindings/rtc/sprd,sc27xx-rtc.txt1
-rw-r--r--dts/Bindings/rtc/st,stm32-rtc.txt2
-rw-r--r--dts/Bindings/rtc/stericsson,coh901331.txt1
-rw-r--r--dts/Bindings/security/tpm/st33zp24-i2c.txt1
-rw-r--r--dts/Bindings/security/tpm/st33zp24-spi.txt1
-rw-r--r--dts/Bindings/security/tpm/tpm_tis_mmio.txt2
-rw-r--r--dts/Bindings/serial/fsl-imx-uart.txt6
-rw-r--r--dts/Bindings/serial/maxim,max310x.txt2
-rw-r--r--dts/Bindings/serial/mtk-uart.txt1
-rw-r--r--dts/Bindings/serial/nxp,sc16is7xx.txt4
-rw-r--r--dts/Bindings/serial/omap_serial.txt1
-rw-r--r--dts/Bindings/serial/qca,ar9330-uart.txt3
-rw-r--r--dts/Bindings/serial/renesas,rzn1-uart.txt10
-rw-r--r--dts/Bindings/serial/renesas,sci-serial.txt19
-rw-r--r--dts/Bindings/serial/xlnx,opb-uartlite.txt23
-rw-r--r--dts/Bindings/slimbus/slim-ngd-qcom-ctrl.txt84
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/gpio.txt1
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/qe/ucc.txt2
-rw-r--r--dts/Bindings/soc/fsl/cpm_qe/qe/usb.txt1
-rw-r--r--dts/Bindings/soc/mediatek/pwrap.txt1
-rw-r--r--dts/Bindings/soc/qcom/qcom,geni-se.txt2
-rw-r--r--dts/Bindings/soc/qcom/qcom,glink.txt5
-rw-r--r--dts/Bindings/soc/qcom/rpmh-rsc.txt137
-rw-r--r--dts/Bindings/sound/ac97-bus.txt32
-rw-r--r--dts/Bindings/sound/amlogic,axg-fifo.txt23
-rw-r--r--dts/Bindings/sound/amlogic,axg-sound-card.txt124
-rw-r--r--dts/Bindings/sound/amlogic,axg-spdifout.txt20
-rw-r--r--dts/Bindings/sound/amlogic,axg-tdm-formatters.txt28
-rw-r--r--dts/Bindings/sound/amlogic,axg-tdm-iface.txt22
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-rw-r--r--dts/src/arm64/freescale/fsl-ls2088a-rdb.dts38
-rw-r--r--dts/src/arm64/freescale/fsl-ls2088a.dtsi42
-rw-r--r--dts/src/arm64/freescale/fsl-ls208xa-qds.dtsi38
-rw-r--r--dts/src/arm64/freescale/fsl-ls208xa-rdb.dtsi38
-rw-r--r--dts/src/arm64/freescale/fsl-ls208xa.dtsi38
-rw-r--r--dts/src/arm64/freescale/qoriq-bman-portals.dtsi2
-rw-r--r--dts/src/arm64/freescale/qoriq-fman3-0-10g-0.dtsi2
-rw-r--r--dts/src/arm64/freescale/qoriq-fman3-0-10g-1.dtsi2
-rw-r--r--dts/src/arm64/freescale/qoriq-fman3-0-1g-0.dtsi2
-rw-r--r--dts/src/arm64/freescale/qoriq-fman3-0-1g-1.dtsi2
-rw-r--r--dts/src/arm64/freescale/qoriq-fman3-0-1g-2.dtsi2
-rw-r--r--dts/src/arm64/freescale/qoriq-fman3-0-1g-3.dtsi2
-rw-r--r--dts/src/arm64/freescale/qoriq-fman3-0-1g-4.dtsi2
-rw-r--r--dts/src/arm64/freescale/qoriq-fman3-0-1g-5.dtsi2
-rw-r--r--dts/src/arm64/freescale/qoriq-fman3-0.dtsi17
-rw-r--r--dts/src/arm64/freescale/qoriq-qman-portals.dtsi2
-rw-r--r--dts/src/arm64/hisilicon/hi3660-hikey960.dts26
-rw-r--r--dts/src/arm64/hisilicon/hi3660.dtsi97
-rw-r--r--dts/src/arm64/hisilicon/hi6220-hikey.dts1
-rw-r--r--dts/src/arm64/hisilicon/hi6220.dtsi16
-rw-r--r--dts/src/arm64/hisilicon/hip07.dtsi284
-rw-r--r--dts/src/arm64/marvell/armada-37xx.dtsi23
-rw-r--r--dts/src/arm64/marvell/armada-8040-mcbin.dts2
-rw-r--r--dts/src/arm64/marvell/armada-cp110.dtsi2
-rw-r--r--dts/src/arm64/mediatek/mt2712e.dtsi2
-rw-r--r--dts/src/arm64/mediatek/mt6797-x20-dev.dts33
-rw-r--r--dts/src/arm64/mediatek/mt7622-rfb1.dts4
-rw-r--r--dts/src/arm64/mediatek/mt7622.dtsi12
-rw-r--r--dts/src/arm64/mediatek/mt8173.dtsi2
-rw-r--r--dts/src/arm64/nvidia/tegra194-p2888.dtsi22
-rw-r--r--dts/src/arm64/nvidia/tegra194.dtsi106
-rw-r--r--dts/src/arm64/qcom/apq8016-sbc.dtsi2
-rw-r--r--dts/src/arm64/qcom/apq8096-db820c.dtsi239
-rw-r--r--dts/src/arm64/qcom/msm8916.dtsi28
-rw-r--r--dts/src/arm64/qcom/msm8996.dtsi22
-rw-r--r--dts/src/arm64/qcom/pm8005.dtsi33
-rw-r--r--dts/src/arm64/qcom/pm8998.dtsi55
-rw-r--r--dts/src/arm64/qcom/sdm845-mtp.dts45
-rw-r--r--dts/src/arm64/qcom/sdm845.dtsi780
-rw-r--r--dts/src/arm64/renesas/r8a7795-es1-h3ulcb-kf.dts5
-rw-r--r--dts/src/arm64/renesas/r8a7795-es1-h3ulcb.dts5
-rw-r--r--dts/src/arm64/renesas/r8a7795-es1-salvator-x.dts5
-rw-r--r--dts/src/arm64/renesas/r8a7795-es1.dtsi7
-rw-r--r--dts/src/arm64/renesas/r8a7795-h3ulcb-kf.dts5
-rw-r--r--dts/src/arm64/renesas/r8a7795-h3ulcb.dts5
-rw-r--r--dts/src/arm64/renesas/r8a7795-salvator-x.dts5
-rw-r--r--dts/src/arm64/renesas/r8a7795-salvator-xs.dts5
-rw-r--r--dts/src/arm64/renesas/r8a7795.dtsi22
-rw-r--r--dts/src/arm64/renesas/r8a7796-m3ulcb-kf.dts5
-rw-r--r--dts/src/arm64/renesas/r8a7796-m3ulcb.dts5
-rw-r--r--dts/src/arm64/renesas/r8a7796-salvator-x.dts5
-rw-r--r--dts/src/arm64/renesas/r8a7796-salvator-xs.dts5
-rw-r--r--dts/src/arm64/renesas/r8a7796.dtsi63
-rw-r--r--dts/src/arm64/renesas/r8a77965.dtsi253
-rw-r--r--dts/src/arm64/renesas/r8a77970-eagle.dts5
-rw-r--r--dts/src/arm64/renesas/r8a77970-v3msk.dts5
-rw-r--r--dts/src/arm64/renesas/r8a77970.dtsi7
-rw-r--r--dts/src/arm64/renesas/r8a77980-condor.dts29
-rw-r--r--dts/src/arm64/renesas/r8a77980-v3hsk.dts23
-rw-r--r--dts/src/arm64/renesas/r8a77980.dtsi403
-rw-r--r--dts/src/arm64/renesas/r8a77990-ebisu.dts37
-rw-r--r--dts/src/arm64/renesas/r8a77990.dtsi169
-rw-r--r--dts/src/arm64/renesas/r8a77995-draak.dts133
-rw-r--r--dts/src/arm64/renesas/r8a77995.dtsi251
-rw-r--r--dts/src/arm64/renesas/salvator-common.dtsi34
-rw-r--r--dts/src/arm64/renesas/salvator-x.dtsi7
-rw-r--r--dts/src/arm64/renesas/salvator-xs.dtsi7
-rw-r--r--dts/src/arm64/renesas/ulcb-kf.dtsi5
-rw-r--r--dts/src/arm64/renesas/ulcb.dtsi11
-rw-r--r--dts/src/arm64/rockchip/rk3328-evb.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3328-rock64.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3328.dtsi44
-rw-r--r--dts/src/arm64/rockchip/rk3368-evb-act8846.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3368-evb.dtsi39
-rw-r--r--dts/src/arm64/rockchip/rk3368-geekbox.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3368-px5-evb.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3368-r88.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3368.dtsi47
-rw-r--r--dts/src/arm64/rockchip/rk3399-evb.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3399-ficus.dts599
-rw-r--r--dts/src/arm64/rockchip/rk3399-firefly.dts86
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-bob.dts79
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-chromebook.dtsi397
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru-kevin.dts86
-rw-r--r--dts/src/arm64/rockchip/rk3399-gru.dtsi367
-rw-r--r--dts/src/arm64/rockchip/rk3399-op1-opp.dtsi39
-rw-r--r--dts/src/arm64/rockchip/rk3399-opp.dtsi39
-rw-r--r--dts/src/arm64/rockchip/rk3399-puma-haikou.dts39
-rw-r--r--dts/src/arm64/rockchip/rk3399-puma.dtsi40
-rw-r--r--dts/src/arm64/rockchip/rk3399-sapphire-excavator.dts41
-rw-r--r--dts/src/arm64/rockchip/rk3399-sapphire.dtsi44
-rw-r--r--dts/src/arm64/rockchip/rk3399.dtsi161
-rw-r--r--dts/src/arm64/socionext/uniphier-ld11-global.dts1
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20-global.dts1
-rw-r--r--dts/src/arm64/socionext/uniphier-ld20.dtsi2
-rw-r--r--dts/src/arm64/sprd/sc2731.dtsi44
-rw-r--r--dts/src/arm64/sprd/sc9860.dtsi2
-rw-r--r--dts/src/arm64/sprd/whale2.dtsi6
-rw-r--r--dts/src/arm64/ti/k3-am65-main.dtsi31
-rw-r--r--dts/src/arm64/ti/k3-am65.dtsi87
-rw-r--r--dts/src/arm64/ti/k3-am654-base-board.dts36
-rw-r--r--dts/src/arm64/ti/k3-am654.dtsi115
-rw-r--r--dts/src/arm64/xilinx/avnet-ultra96-rev1.dts19
-rw-r--r--dts/src/arm64/xilinx/zynqmp-ep108-clk.dtsi137
-rw-r--r--dts/src/arm64/xilinx/zynqmp-ep108.dts154
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu100-revC.dts12
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu102-revA.dts2
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu106-revA.dts2
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zcu111-revA.dts2
-rw-r--r--dts/src/arm64/xilinx/zynqmp.dtsi2
-rw-r--r--dts/src/h8300/h8300h_sim.dts2
-rw-r--r--dts/src/mips/ingenic/jz4780.dtsi19
-rw-r--r--dts/src/mips/mscc/ocelot.dtsi32
-rw-r--r--dts/src/mips/mscc/ocelot_pcb123.dts10
-rw-r--r--dts/src/mips/qca/ar9132.dtsi2
-rw-r--r--dts/src/mips/qca/ar9132_tl_wr1043nd_v1.dts3
-rw-r--r--dts/src/mips/qca/ar9331.dtsi2
-rw-r--r--dts/src/mips/qca/ar9331_dpt_module.dts5
-rw-r--r--dts/src/mips/qca/ar9331_dragino_ms14.dts5
-rw-r--r--dts/src/mips/qca/ar9331_omega.dts5
-rw-r--r--dts/src/mips/qca/ar9331_tl_mr3020.dts5
-rw-r--r--dts/src/powerpc/ac14xx.dts20
-rw-r--r--dts/src/powerpc/fsl/kmcent2.dts2
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman-0.dtsi15
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman-1.dtsi15
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-0.dtsi15
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-1.dtsi15
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3l-0.dtsi15
-rw-r--r--dts/src/powerpc/fsl/t2080rdb.dts4
-rw-r--r--dts/src/powerpc/fsl/t4240rdb.dts8
-rw-r--r--dts/src/powerpc/pdm360ng.dts2
-rw-r--r--fs/tftp.c97
-rw-r--r--images/Makefile.imx35
-rw-r--r--include/common.h4
-rw-r--r--include/dhcp.h1
-rw-r--r--include/dma.h12
-rw-r--r--include/driver.h2
-rw-r--r--include/filetype.h2
-rw-r--r--include/libfile.h1
-rw-r--r--include/linux/log2.h89
-rw-r--r--include/linux/mfd/rave-sp.h1
-rw-r--r--include/ratp.h2
-rw-r--r--lib/libfile.c24
-rw-r--r--lib/ratp.c6
-rw-r--r--net/dhcp.c11
-rw-r--r--net/net.c2
-rw-r--r--scripts/Makefile.lib17
-rw-r--r--scripts/dtc/.gitignore1
-rw-r--r--scripts/imx/imx-image.c86
-rw-r--r--scripts/imx/imx-usb-loader.c76
-rw-r--r--scripts/imx/imx.c221
-rw-r--r--scripts/remote/controller.py3
1304 files changed, 32652 insertions, 9788 deletions
diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst
index 56fd3ab..99ca10b 100644
--- a/Documentation/boards/imx.rst
+++ b/Documentation/boards/imx.rst
@@ -118,33 +118,6 @@ Some notes about the mentioned *conditions*.
- ``until_any_bit_clear`` waits until ``(*addr & mask) != mask`` is true
- ``until_any_bit_set`` waits until ``(*addr & mask) != 0`` is true.
-Internal Boot Mode Through Internal RAM(IRAM)
----------------------------------------------
-
-The Internal Boot Mode Through Internal RAM is supported on:
-
-* i.MX51
-
-As can be easily deduced from its name, the Internal Boot Mode Through
-Internal RAM is just a variant of Internal Boot Mode so all of the
-stated above still applies in this case. What it differs in is the following:
-
-* Boot process is done in two stages(First stage binary can be
- produced with ``imx_v7-xload_defconfig``)
-* DCD of the first stage image is set such that the image is fetched
- into an unoccupied area or IRAM
-* First stage image once uncompressed and set up will look for a
- second stage bootloader on the same media it booted from and start
- it(see mach-imx/xload.c for more details)
-* Second stage images are just regular i.MX boot images
-
-Since on a typical i.MX SoC unused IRAM area is not enough to run
-anything but a PBL this mode, due to its very limited usability,
-serves only one purpose -- allow for a portion of a bootloader to be
-executed without depending on DRAM to be functional. This peculiarity
-of the mode can be used to implement various memory testing
-scenarious.
-
USB Boot
^^^^^^^^
diff --git a/Documentation/boards/imx/amazon-kindle-4-5.rst b/Documentation/boards/imx/amazon-kindle-4-5.rst
index bc6bf26..58f38a0 100644
--- a/Documentation/boards/imx/amazon-kindle-4-5.rst
+++ b/Documentation/boards/imx/amazon-kindle-4-5.rst
@@ -1,7 +1,8 @@
-Amazon Kindle 4/5 Model No. D01100, D01200 and EY21
-===================================================
+Amazon Kindle 4/5 (Wi-Fi/No-Touch, Touch and Paperwhite)
+========================================================
-The Kindle Model No. D01100 (Kindle Wi-Fi), D01200 (Kindle Touch)
+The Kindle Models No. D01100 (Kindle Wi-Fi, also known as No-Touch or K4NT),
+D01200 (Kindle Touch)
and EY21 (Paperwhite) are refered as the Kindle 4th and 5th generation.
Those e-book readers share a common set of hardware:
@@ -15,55 +16,55 @@ while the newer EY21 uses 256MiB of LPDDR2.
The devices boot up in internal boot mode from an eMMC boot partition and
are shipped with a vendor modified u-boot imximage based on u-boot v2009.08.
-To upload and run a new bootloader the older devices can be put into
-USB-downloader mode by the SOC microcode when a specific key is pressed during
-startup:
+This device is battery-powered and there is no way to switch the device off.
+When the device is inactive, the Kindle software will first reduce the
+power consumption to a few milliamps of battery power, after some minutes
+the power consumption is further reduced to about 550 microamps. Switching
+on iomux pullups may significantly reduce your standby-time.
-* the fiveway down button on the model D01100
-* the home button on model D01200
+Building barebox
+----------------
-A new USB device "NS Blank CODEX" should appear, barebox may be uploaded using
+``make kindle-mx50_defconfig`` should get you a working config.
-::
+Uploading barebox
+-----------------
- $ scripts/imx/imx-usb-loader barebox-kindle-d01100.img
- $ scripts/imx/imx-usb-loader barebox-kindle-d01200.img
+To upload and run a new bootloader, the older devices can be put into
+USB bootloader mode by the SoC microcode:
-Hint: keep the select button pressed down to get the barebox USB console.
+1. Connect the Kindle to your host computer with a USB cable.
+2. Power down the device by holding the power button until the power LED goes
+ dark (about 10 seconds).
+4. Hold the power button, and hold down a device-specific special key:
+ * the fiveway down button on the model D01100
+ * the home button on model D01200
+4. Then release the power button, but still hold the special key.
+5. A new USB device named ``NS Blank CODEX`` should appear on your host computer.
+ You can now release the special button.
+7. Finally, upload barebox to the Kindle by using:
-Barebox may be used as drop-in replacement for the shipped bootloader, when
-the imximg fits into 258048 bytes. When installing the barebox imximg on
-the eMMC, take care not to overwrite the vendor supplied serial numbers stored
-on the eMMC,
-e.g. for the D01100 just write the imx-header and the application section::
+ .. code-block:: console
- loady -t usbserial
- memcpy -b -s barebox-kindle-d01100.img -d /dev/disk0.boot0.imx_header 1024 0 2048
- memcpy -b -s barebox-kindle-d01100.img -d /dev/disk0.boot0.self 4096 0 253952
+ $ scripts/imx/imx-usb-loader barebox-kindle-d01100.img
+ $ scripts/imx/imx-usb-loader barebox-kindle-d01200.img
-Note: a USB serial ACM console will be launched by a barebox init script
-when
+Additionally, a USB serial ACM console will be launched by a barebox init script
+when:
* the cursor select key is pressed during startup of model D01100
* the home button is pressed within a second after startup of model D01200.
- If you press the home button during startup, you will enter USB boot mode.
+ (If you press the home button during startup, you will enter USB boot mode.)
* the EY21 has no keys to press, a USB console will be launched for 10s.
-This device is battery-powered and there is no way to switch the device off.
-When the device is inactive, the kindle software will first reduce the
-power consumption to a few milliamps of battery power, after some minutes
-the power consumption is further reduced to about 550 microamps. Switching
-on iomux pullups may significantly reduce your standby-time.
-
-Hints to reduce the build image size
-------------------------------------
+Barebox may be used as drop-in replacement for the shipped bootloader, when
+the imximg fits into 258048 bytes. When installing the barebox imximg on
+the eMMC, take care not to overwrite the vendor supplied serial numbers stored
+on the eMMC,
+e.g. for the D01100 just write the imx-header and the application section:
-Note that a drop-in replacement barebox imximage must not exceed 258048 bytes
-since the space behind it is in use. Hence, don't build in drivers and FS
-that are not required, e.g.
-``NET, DISK_AHCI, DISK_INTF_PLATFORM_IDE, DISK_ATA, VIDEO, PWM, LED,
-USB_STORAGE, USB_ULPI, NAND, MTD_UBI, FS_UBIFS, MFD_MC34704, MFD_MC9SDZ60,
-MFD_STMPE, EEPROM_AT25, EEPROM_AT24, KEYBOARD_GPIO, PARTITION_DISK_EFI``
+.. code-block:: console
-Also unselect support for other boards to get rid of their dependencies.
-Further select ``IMAGE_COMPRESSION_XZKERN``.
+ $ loady -t usbserial
+ $ memcpy -b -s barebox-kindle-d01100.img -d /dev/disk0.boot0.imx_header 1024 0 2048
+ $ memcpy -b -s barebox-kindle-d01100.img -d /dev/disk0.boot0.self 4096 0 253952
diff --git a/Makefile b/Makefile
index 973a8d1..518e683 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
VERSION = 2018
-PATCHLEVEL = 08
+PATCHLEVEL = 09
SUBLEVEL = 0
EXTRAVERSION =
NAME = None
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg
index 0773f4d..47b572d 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg
@@ -4,7 +4,6 @@ dcdofs 0x400
#include <mach/imx6-ddr-regs.h>
#include <mach/imx6dl-ddr-regs.h>
-#include <mach/imx6-ccm-regs.h>
#include "ram-base.imxcfg"
#include "800mhz_4x128mx16.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg
index 6622c51..cf3716d 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg
@@ -4,7 +4,6 @@ dcdofs 0x400
#include <mach/imx6-ddr-regs.h>
#include <mach/imx6dl-ddr-regs.h>
-#include <mach/imx6-ccm-regs.h>
#include "ram-base.imxcfg"
#include "800mhz_4x256mx16.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg
index bd4134f..8ed987d 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg
@@ -4,7 +4,6 @@ dcdofs 0x400
#include <mach/imx6-ddr-regs.h>
#include <mach/imx6q-ddr-regs.h>
-#include <mach/imx6-ccm-regs.h>
#include "ram-base.imxcfg"
#include "1066mhz_4x128mx16.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg
index 89aa21c..e6d97d1 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg
@@ -4,7 +4,6 @@ dcdofs 0x400
#include <mach/imx6-ddr-regs.h>
#include <mach/imx6q-ddr-regs.h>
-#include <mach/imx6-ccm-regs.h>
#include "ram-base.imxcfg"
#include "1066mhz_4x256mx16.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg
index 66f0e1a..50bbfc5 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg
@@ -4,7 +4,6 @@ dcdofs 0x400
#include <mach/imx6-ddr-regs.h>
#include <mach/imx6q-ddr-regs.h>
-#include <mach/imx6-ccm-regs.h>
#include "ram-base.imxcfg"
#include "1066mhz_4x512mx16-qp.imxcfg"
diff --git a/arch/arm/boards/freescale-mx51-babbage/board.c b/arch/arm/boards/freescale-mx51-babbage/board.c
index 74ad7fa..4839aa5 100644
--- a/arch/arm/boards/freescale-mx51-babbage/board.c
+++ b/arch/arm/boards/freescale-mx51-babbage/board.c
@@ -43,80 +43,55 @@
#define MX51_CCM_CACRR 0x10
-static int imx51_babbage_init(void)
+#define USBH1_STP IMX_GPIO_NR(1, 27)
+#define USBH1_PHY_RESET IMX_GPIO_NR(2, 5)
+#define USBH1_HUB_RESET IMX_GPIO_NR(1, 7)
+
+static int imx51_babbage_reset_usbh1(void)
{
+ void __iomem *iomuxbase = IOMEM(MX51_IOMUXC_BASE_ADDR);
+
if (!of_machine_is_compatible("fsl,imx51-babbage"))
return 0;
- imx51_babbage_power_init();
+ imx_setup_pad(iomuxbase, MX51_PAD_EIM_D21__GPIO2_5);
+ imx_setup_pad(iomuxbase, MX51_PAD_GPIO1_7__GPIO1_7);
- barebox_set_hostname("babbage");
+ gpio_direction_output(USBH1_PHY_RESET, 0);
+ gpio_direction_output(USBH1_HUB_RESET, 0);
- armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
+ mdelay(10);
- imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0",
- BBU_HANDLER_FLAG_DEFAULT);
-
- return 0;
-}
-coredevice_initcall(imx51_babbage_init);
+ gpio_set_value(USBH1_PHY_RESET, 1);
+ gpio_set_value(USBH1_HUB_RESET, 1);
-#ifdef CONFIG_ARCH_IMX_XLOAD
+ imx_setup_pad(iomuxbase, MX51_PAD_USBH1_STP__GPIO1_27);
+ gpio_direction_output(USBH1_STP, 1);
-static int imx51_babbage_xload_init_pinmux(void)
-{
- static const iomux_v3_cfg_t pinmux[] = {
- /* (e)CSPI */
- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
- MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+ mdelay(1);
- /* (e)CSPI chip select lines */
- MX51_PAD_CSPI1_SS1__GPIO4_25,
+ imx_setup_pad(iomuxbase, MX51_PAD_USBH1_STP__USBH1_STP);
-
- /* eSDHC 1 */
- MX51_PAD_SD1_CMD__SD1_CMD,
- MX51_PAD_SD1_CLK__SD1_CLK,
- MX51_PAD_SD1_DATA0__SD1_DATA0,
- MX51_PAD_SD1_DATA1__SD1_DATA1,
- MX51_PAD_SD1_DATA2__SD1_DATA2,
- MX51_PAD_SD1_DATA3__SD1_DATA3,
- };
-
- mxc_iomux_v3_setup_multiple_pads(ARRAY_AND_SIZE(pinmux));
+ gpio_free(USBH1_PHY_RESET);
return 0;
}
-coredevice_initcall(imx51_babbage_xload_init_pinmux);
+console_initcall(imx51_babbage_reset_usbh1);
-static int imx51_babbage_xload_init_devices(void)
+static int imx51_babbage_init(void)
{
- static int spi0_chipselects[] = {
- IMX_GPIO_NR(4, 25),
- };
+ if (!of_machine_is_compatible("fsl,imx51-babbage"))
+ return 0;
- static struct spi_imx_master spi0_pdata = {
- .chipselect = spi0_chipselects,
- .num_chipselect = ARRAY_SIZE(spi0_chipselects),
- };
+ imx51_babbage_power_init();
- static const struct spi_board_info spi0_devices[] = {
- {
- .name = "mtd_dataflash",
- .chip_select = 0,
- .max_speed_hz = 25 * 1000 * 1000,
- .bus_num = 0,
- },
- };
+ barebox_set_hostname("babbage");
- imx51_add_mmc0(NULL);
+ armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
- spi_register_board_info(ARRAY_AND_SIZE(spi0_devices));
- imx51_add_spi0(&spi0_pdata);
+ imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0",
+ BBU_HANDLER_FLAG_DEFAULT);
return 0;
}
-device_initcall(imx51_babbage_xload_init_devices);
-
-#endif
+coredevice_initcall(imx51_babbage_init);
diff --git a/arch/arm/boards/freescale-mx51-babbage/flash-header-common.imxcfg b/arch/arm/boards/freescale-mx51-babbage/flash-header-common.imxcfg
deleted file mode 100644
index 1332b74..0000000
--- a/arch/arm/boards/freescale-mx51-babbage/flash-header-common.imxcfg
+++ /dev/null
@@ -1,58 +0,0 @@
-soc imx51
-dcdofs 0x400
-wm 32 0x73fa88a0 0x00000200
-wm 32 0x73fa850c 0x000020c5
-wm 32 0x73fa8510 0x000020c5
-wm 32 0x73fa883c 0x00000002
-wm 32 0x73fa8848 0x00000002
-wm 32 0x73fa84b8 0x000000e7
-wm 32 0x73fa84bc 0x00000045
-wm 32 0x73fa84c0 0x00000045
-wm 32 0x73fa84c4 0x00000045
-wm 32 0x73fa84c8 0x00000045
-wm 32 0x73fa8820 0x00000000
-wm 32 0x73fa84a4 0x00000003
-wm 32 0x73fa84a8 0x00000003
-wm 32 0x73fa84ac 0x000000e3
-wm 32 0x73fa84b0 0x000000e3
-wm 32 0x73fa84b4 0x000000e3
-wm 32 0x73fa84cc 0x000000e3
-wm 32 0x73fa84d0 0x000000e2
-wm 32 0x73fa882c 0x00000004
-wm 32 0x73fa88a4 0x00000004
-wm 32 0x73fa88ac 0x00000004
-wm 32 0x73fa88b8 0x00000004
-wm 32 0x83fd9000 0x82a20000
-wm 32 0x83fd9008 0x82a20000
-wm 32 0x83fd9010 0x000ad0d0
-wm 32 0x83fd9004 0x3f3584ab
-wm 32 0x83fd900c 0x3f3584ab
-wm 32 0x83fd9014 0x04008008
-wm 32 0x83fd9014 0x0000801a
-wm 32 0x83fd9014 0x0000801b
-wm 32 0x83fd9014 0x00448019
-wm 32 0x83fd9014 0x07328018
-wm 32 0x83fd9014 0x04008008
-wm 32 0x83fd9014 0x00008010
-wm 32 0x83fd9014 0x00008010
-wm 32 0x83fd9014 0x06328018
-wm 32 0x83fd9014 0x03808019
-wm 32 0x83fd9014 0x00408019
-wm 32 0x83fd9014 0x00008000
-wm 32 0x83fd9014 0x0400800c
-wm 32 0x83fd9014 0x0000801e
-wm 32 0x83fd9014 0x0000801f
-wm 32 0x83fd9014 0x0000801d
-wm 32 0x83fd9014 0x0732801c
-wm 32 0x83fd9014 0x0400800c
-wm 32 0x83fd9014 0x00008014
-wm 32 0x83fd9014 0x00008014
-wm 32 0x83fd9014 0x0632801c
-wm 32 0x83fd9014 0x0380801d
-wm 32 0x83fd9014 0x0040801d
-wm 32 0x83fd9014 0x00008004
-wm 32 0x83fd9000 0xb2a20000
-wm 32 0x83fd9008 0xb2a20000
-wm 32 0x83fd9010 0x000ad6d0
-wm 32 0x83fd9034 0x90000000
-wm 32 0x83fd9014 0x00000000
diff --git a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg
deleted file mode 100644
index b249a7d..0000000
--- a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage-xload.imxcfg
+++ /dev/null
@@ -1,3 +0,0 @@
-loadaddr CONFIG_ARCH_IMX_UNUSED_IRAM_BASE
-
-#include "flash-header-common.imxcfg" \ No newline at end of file
diff --git a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg
index cb60e47..bac6816 100644
--- a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg
+++ b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg
@@ -1,3 +1,59 @@
loadaddr 0x90000000
-
-#include "flash-header-common.imxcfg" \ No newline at end of file
+soc imx51
+dcdofs 0x400
+wm 32 0x73fa88a0 0x00000200
+wm 32 0x73fa850c 0x000020c5
+wm 32 0x73fa8510 0x000020c5
+wm 32 0x73fa883c 0x00000002
+wm 32 0x73fa8848 0x00000002
+wm 32 0x73fa84b8 0x000000e7
+wm 32 0x73fa84bc 0x00000045
+wm 32 0x73fa84c0 0x00000045
+wm 32 0x73fa84c4 0x00000045
+wm 32 0x73fa84c8 0x00000045
+wm 32 0x73fa8820 0x00000000
+wm 32 0x73fa84a4 0x00000003
+wm 32 0x73fa84a8 0x00000003
+wm 32 0x73fa84ac 0x000000e3
+wm 32 0x73fa84b0 0x000000e3
+wm 32 0x73fa84b4 0x000000e3
+wm 32 0x73fa84cc 0x000000e3
+wm 32 0x73fa84d0 0x000000e2
+wm 32 0x73fa882c 0x00000004
+wm 32 0x73fa88a4 0x00000004
+wm 32 0x73fa88ac 0x00000004
+wm 32 0x73fa88b8 0x00000004
+wm 32 0x83fd9000 0x82a20000
+wm 32 0x83fd9008 0x82a20000
+wm 32 0x83fd9010 0x000ad0d0
+wm 32 0x83fd9004 0x3f3584ab
+wm 32 0x83fd900c 0x3f3584ab
+wm 32 0x83fd9014 0x04008008
+wm 32 0x83fd9014 0x0000801a
+wm 32 0x83fd9014 0x0000801b
+wm 32 0x83fd9014 0x00448019
+wm 32 0x83fd9014 0x07328018
+wm 32 0x83fd9014 0x04008008
+wm 32 0x83fd9014 0x00008010
+wm 32 0x83fd9014 0x00008010
+wm 32 0x83fd9014 0x06328018
+wm 32 0x83fd9014 0x03808019
+wm 32 0x83fd9014 0x00408019
+wm 32 0x83fd9014 0x00008000
+wm 32 0x83fd9014 0x0400800c
+wm 32 0x83fd9014 0x0000801e
+wm 32 0x83fd9014 0x0000801f
+wm 32 0x83fd9014 0x0000801d
+wm 32 0x83fd9014 0x0732801c
+wm 32 0x83fd9014 0x0400800c
+wm 32 0x83fd9014 0x00008014
+wm 32 0x83fd9014 0x00008014
+wm 32 0x83fd9014 0x0632801c
+wm 32 0x83fd9014 0x0380801d
+wm 32 0x83fd9014 0x0040801d
+wm 32 0x83fd9014 0x00008004
+wm 32 0x83fd9000 0xb2a20000
+wm 32 0x83fd9008 0xb2a20000
+wm 32 0x83fd9010 0x000ad6d0
+wm 32 0x83fd9034 0x90000000
+wm 32 0x83fd9014 0x00000000
diff --git a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
index 216576c..f254db7 100644
--- a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
+++ b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
@@ -4,7 +4,6 @@
#include <common.h>
#include <mach/esdctl.h>
#include <mach/generic.h>
-#include <asm/cache.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
@@ -47,27 +46,3 @@ ENTRY_FUNCTION(start_imx51_babbage, r0, r1, r2)
imx51_barebox_entry(fdt);
}
-
-static noinline void babbage_entry(void)
-{
- arm_early_mmu_cache_invalidate();
-
- relocate_to_current_adr();
- setup_c();
-
- puts_ll("lowlevel init done\n");
-
- imx51_barebox_entry(NULL);
-}
-
-ENTRY_FUNCTION(start_imx51_babbage_xload, r0, r1, r2)
-{
- imx5_cpu_lowlevel_init();
-
- if (IS_ENABLED(CONFIG_DEBUG_LL))
- setup_uart();
-
- arm_setup_stack(0x20000000 - 16);
-
- babbage_entry();
-}
diff --git a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg
index f4506f1..b9a6fc1 100644
--- a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg
+++ b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg
@@ -4,7 +4,6 @@ dcdofs 0x400
#include <mach/imx6-ddr-regs.h>
#include <mach/imx6q-ddr-regs.h>
-#include <mach/imx6-ccm-regs.h>
#include "ram-base.imxcfg"
#include "quad_128x64.imxcfg"
diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg
index 2a1c42a..b7a914f 100644
--- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg
+++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg
@@ -4,7 +4,6 @@ dcdofs 0x400
#include <mach/imx6-ddr-regs.h>
#include <mach/imx6dl-ddr-regs.h>
-#include <mach/imx6-ccm-regs.h>
#include "ram-base.imxcfg"
#include "1600mhz_4x128mx16.imxcfg"
diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c
index d93e21d..868c25e 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/board.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/board.c
@@ -21,6 +21,7 @@
#include <init.h>
#include <asm/memory.h>
#include <linux/sizes.h>
+#include <mach/bbu.h>
static int imx8mq_evk_mem_init(void)
{
@@ -39,6 +40,8 @@ static int nxp_imx8mq_evk_init(void)
barebox_set_hostname("imx8mq-evk");
+ imx8mq_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc0", 0);
+
return 0;
}
device_initcall(nxp_imx8mq_evk_init);
diff --git a/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/emmc b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/emmc
index b1792a6..47dc951 100644
--- a/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/emmc
+++ b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/emmc
@@ -1,5 +1,5 @@
#!/bin/sh
-global.bootm.image=/mnt/mmc1.0/linuximage
+global.bootm.image=/mnt/mmc1.0/zImage
global.bootm.oftree=/mnt/mmc1.0/oftree
global.linux.bootargs.dyn.root="root=/dev/mmcblk1p2 rootflags='data=journal'"
diff --git a/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/mmc b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/mmc
index 77a076d..b025a57 100644
--- a/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/mmc
+++ b/arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/mmc
@@ -1,5 +1,5 @@
#!/bin/sh
-global.bootm.image=/mnt/mmc0.0/linuximage
+global.bootm.image=/mnt/mmc0.0/zImage
global.bootm.oftree=/mnt/mmc0.0/oftree
global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootflags='data=journal'"
diff --git a/arch/arm/boards/zii-vf610-dev/board.c b/arch/arm/boards/zii-vf610-dev/board.c
index c90644b..91c6538 100644
--- a/arch/arm/boards/zii-vf610-dev/board.c
+++ b/arch/arm/boards/zii-vf610-dev/board.c
@@ -149,6 +149,25 @@ static int zii_vf610_dev_set_hostname(void)
}
late_initcall(zii_vf610_dev_set_hostname);
+static int zii_vf610_dev_register_bbu(void)
+{
+ int ret;
+ if (!of_machine_is_compatible("zii,vf610dev-c") &&
+ !of_machine_is_compatible("zii,vf610dev-b"))
+ return 0;
+
+ ret = vf610_bbu_internal_spi_i2c_register_handler("SPI",
+ "/dev/m25p0.bootloader",
+ 0);
+ if (ret) {
+ pr_err("Failed to register SPI BBU handler");
+ return ret;
+ }
+
+ return 0;
+}
+late_initcall(zii_vf610_dev_register_bbu);
+
static int zii_vf610_spu3_register_bbu(void)
{
int ret;
diff --git a/arch/arm/configs/imx_v7-xload_defconfig b/arch/arm/configs/imx_v7-xload_defconfig
deleted file mode 100644
index dcf100d..0000000
--- a/arch/arm/configs/imx_v7-xload_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_ARCH_IMX=y
-CONFIG_ARCH_IMX_XLOAD=y
-CONFIG_IMX_MULTI_BOARDS=y
-CONFIG_MACH_FREESCALE_MX51_PDK=y
-CONFIG_THUMB2_BAREBOX=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_MMU=y
-CONFIG_TEXT_BASE=0x0
-CONFIG_MALLOC_SIZE=0x0
-CONFIG_MALLOC_DUMMY=y
-CONFIG_RELOCATABLE=y
-CONFIG_SHELL_NONE=y
-# CONFIG_ERRNO_MESSAGES is not set
-# CONFIG_TIMESTAMP is not set
-CONFIG_DEBUG_LL=y
-CONFIG_MTD=y
-# CONFIG_MTD_WRITE is not set
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MCI=y
-CONFIG_MCI_STARTUP=y
-# CONFIG_MCI_WRITE is not set
-CONFIG_MCI_IMX_ESDHC=y
-CONFIG_EEPROM_AT25=y
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_IMX=y
-# CONFIG_FS_RAMFS is not set
-# CONFIG_FS_DEVFS is not set
-CONFIG_FS_FAT=y
-CONFIG_BOOTSTRAP=y
-CONFIG_BOOTSTRAP_DEVFS=y
-CONFIG_BOOTSTRAP_DISK=y
diff --git a/arch/arm/configs/kindle-mx50_defconfig b/arch/arm/configs/kindle-mx50_defconfig
new file mode 100644
index 0000000..31bfc9c
--- /dev/null
+++ b/arch/arm/configs/kindle-mx50_defconfig
@@ -0,0 +1,70 @@
+CONFIG_ARCH_IMX=y
+CONFIG_IMX_MULTI_BOARDS=y
+CONFIG_MACH_KINDLE_MX50=y
+CONFIG_THUMB2_BAREBOX=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_MMU_EARLY=y
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_RELOCATABLE=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_FLEXIBLE_BOOTARGS=y
+CONFIG_BOOTM_SHOW_TYPE=y
+CONFIG_BOOTM_VERBOSE=y
+CONFIG_BOOTM_INITRD=y
+CONFIG_BOOTM_OFTREE=y
+CONFIG_CONSOLE_ACTIVATE_ALL=y
+CONFIG_CONSOLE_ALLOW_COLOR=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_CMD_DMESG=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_BOOT=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_AUTOMOUNT=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_GLOBAL=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USBGADGET=y
+CONFIG_CMD_OF_DUMP=y
+CONFIG_CMD_OFTREE=y
+CONFIG_OFDEVICE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_MTD=y
+CONFIG_MTD_WRITE=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_USB=y
+CONFIG_USB_HOST=y
+CONFIG_USB_IMX_CHIPIDEA=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DRIVER_ARC=y
+CONFIG_USB_GADGET_SERIAL=y
+CONFIG_USB_GADGET_FASTBOOT=y
+CONFIG_MCI=y
+CONFIG_MCI_INFO=y
+CONFIG_MCI_WRITE=y
+CONFIG_MCI_MMC_BOOT_PARTITIONS=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_PINCTRL=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED=y
+CONFIG_GENERIC_PHY=y
+CONFIG_USB_NOP_XCEIV=y
+CONFIG_FS_AUTOMOUNT=y
+CONFIG_IMAGE_COMPRESSION_XZKERN=y
diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c
index 8e0fff6..e975ecf 100644
--- a/arch/arm/cpu/cache-l2x0.c
+++ b/arch/arm/cpu/cache-l2x0.c
@@ -60,14 +60,14 @@ static inline void l2x0_inv_all(void)
static void l2x0_inv_range(unsigned long start, unsigned long end)
{
- if (start & (CACHE_LINE_SIZE - 1)) {
- start &= ~(CACHE_LINE_SIZE - 1);
+ if (!IS_ALIGNED(start, CACHE_LINE_SIZE)) {
+ start = ALIGN_DOWN(start, CACHE_LINE_SIZE);
l2x0_flush_line(start);
start += CACHE_LINE_SIZE;
}
- if (end & (CACHE_LINE_SIZE - 1)) {
- end &= ~(CACHE_LINE_SIZE - 1);
+ if (!IS_ALIGNED(end, CACHE_LINE_SIZE)) {
+ end = ALIGN_DOWN(end, CACHE_LINE_SIZE);
l2x0_flush_line(end);
}
@@ -87,7 +87,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
{
void __iomem *base = l2x0_base;
- start &= ~(CACHE_LINE_SIZE - 1);
+ start = ALIGN_DOWN(start, CACHE_LINE_SIZE);
while (start < end) {
unsigned long blk_end = start + min(end - start, 4096UL);
@@ -102,7 +102,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
static void l2x0_flush_range(unsigned long start, unsigned long end)
{
- start &= ~(CACHE_LINE_SIZE - 1);
+ start = ALIGN_DOWN(start, CACHE_LINE_SIZE);
while (start < end) {
unsigned long blk_end = start + min(end - start, 4096UL);
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 88ee11c..f6c44e3 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -151,7 +151,7 @@ static u32 *arm_create_pte(unsigned long virt, uint32_t flags)
dma_flush_range(table, PTRS_PER_PTE * sizeof(u32));
ttb[ttb_idx] = (unsigned long)table | PMD_TYPE_TABLE;
- dma_flush_range(ttb, sizeof(u32));
+ dma_flush_range(&ttb[ttb_idx], sizeof(u32));
return table;
}
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index b6287ae..69d1b20 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -297,7 +297,8 @@ void dma_sync_single_for_device(dma_addr_t address, size_t size,
{
if (dir == DMA_FROM_DEVICE)
v8_inv_dcache_range(address, address + size - 1);
- v8_flush_dcache_range(address, address + size - 1);
+ else
+ v8_flush_dcache_range(address, address + size - 1);
}
dma_addr_t dma_map_single(struct device_d *dev, void *ptr, size_t size,
diff --git a/arch/arm/dts/am335x-bone-common-strip.dtsi b/arch/arm/dts/am335x-bone-common-strip.dtsi
new file mode 100644
index 0000000..e03ae2a
--- /dev/null
+++ b/arch/arm/dts/am335x-bone-common-strip.dtsi
@@ -0,0 +1,297 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&dcdc2_reg>;
+ };
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds_s0>;
+
+ compatible = "gpio-leds";
+
+ led@2 {
+ label = "beaglebone:green:heartbeat";
+ gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led@3 {
+ label = "beaglebone:green:mmc0";
+ gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led@4 {
+ label = "beaglebone:green:usr2";
+ gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "cpu0";
+ default-state = "off";
+ };
+
+ led@5 {
+ label = "beaglebone:green:usr3";
+ gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+ };
+
+ vmmcsd_fixed: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&am33xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clkout2_pin>;
+
+ user_leds_s0: user_leds_s0 {
+ pinctrl-single,pins = <
+ 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
+ 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
+ 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
+ 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
+ >;
+ };
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
+
+ clkout2_pin: pinmux_clkout2_pin {
+ pinctrl-single,pins = <
+ 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
+ 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
+ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
+ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
+ 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
+ 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
+ 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
+ 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
+ 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
+ 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
+ >;
+ };
+
+ emmc_pins: pinmux_emmc_pins {
+ pinctrl-single,pins = <
+ 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+ 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+ 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+ 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+ 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+ 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+ 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
+ 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
+ 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
+ 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
+ >;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "peripheral";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&cppi41dma {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@24 {
+ reg = <0x24>;
+ };
+
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+ regulators {
+ dcdc1_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ dcdc2_reg: regulator@1 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1325000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc3_reg: regulator@2 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: regulator@3 {
+ regulator-always-on;
+ };
+
+ ldo2_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ ldo3_reg: regulator@5 {
+ regulator-always-on;
+ };
+
+ ldo4_reg: regulator@6 {
+ regulator-always-on;
+ };
+ };
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "mii";
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "mii";
+};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+ status = "okay";
+};
+
+&mmc1 {
+ status = "okay";
+ bus-width = <0x4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+};
diff --git a/arch/arm/dts/am335x-bone-common.dts b/arch/arm/dts/am335x-bone-common.dts
index 0488cbe..26896b4 100644
--- a/arch/arm/dts/am335x-bone-common.dts
+++ b/arch/arm/dts/am335x-bone-common.dts
@@ -10,7 +10,7 @@
#include "am33xx.dtsi"
#include "am33xx-strip.dtsi"
#include "am33xx-clocks-strip.dtsi"
-#include "am335x-bone-common.dtsi"
+#include "am335x-bone-common-strip.dtsi"
/ {
model = "TI AM335x BeagleBone";
diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
index e03ae2a..8711802 100644
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -6,292 +6,4 @@
* published by the Free Software Foundation.
*/
-/ {
- chosen {
- stdout-path = &uart0;
- };
-
- cpus {
- cpu@0 {
- cpu0-supply = <&dcdc2_reg>;
- };
- };
-
- leds {
- pinctrl-names = "default";
- pinctrl-0 = <&user_leds_s0>;
-
- compatible = "gpio-leds";
-
- led@2 {
- label = "beaglebone:green:heartbeat";
- gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- led@3 {
- label = "beaglebone:green:mmc0";
- gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
- default-state = "off";
- };
-
- led@4 {
- label = "beaglebone:green:usr2";
- gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "cpu0";
- default-state = "off";
- };
-
- led@5 {
- label = "beaglebone:green:usr3";
- gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc1";
- default-state = "off";
- };
- };
-
- vmmcsd_fixed: fixedregulator@0 {
- compatible = "regulator-fixed";
- regulator-name = "vmmcsd_fixed";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&am33xx_pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&clkout2_pin>;
-
- user_leds_s0: user_leds_s0 {
- pinctrl-single,pins = <
- 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
- 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
- 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
- 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
- >;
- };
-
- i2c0_pins: pinmux_i2c0_pins {
- pinctrl-single,pins = <
- 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
- 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
- >;
- };
-
- uart0_pins: pinmux_uart0_pins {
- pinctrl-single,pins = <
- 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
- 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
- >;
- };
-
- clkout2_pin: pinmux_clkout2_pin {
- pinctrl-single,pins = <
- 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
- >;
- };
-
- cpsw_default: cpsw_default {
- pinctrl-single,pins = <
- /* Slave 1 */
- 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
- 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
- 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
- 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
- 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
- 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
- 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
- 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
- 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
- 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
- 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
- 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
- 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
- >;
- };
-
- cpsw_sleep: cpsw_sleep {
- pinctrl-single,pins = <
- /* Slave 1 reset value */
- 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- >;
- };
-
- davinci_mdio_default: davinci_mdio_default {
- pinctrl-single,pins = <
- /* MDIO */
- 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
- 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
- >;
- };
-
- davinci_mdio_sleep: davinci_mdio_sleep {
- pinctrl-single,pins = <
- /* MDIO reset value */
- 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
- 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
- >;
- };
-
- mmc1_pins: pinmux_mmc1_pins {
- pinctrl-single,pins = <
- 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
- >;
- };
-
- emmc_pins: pinmux_emmc_pins {
- pinctrl-single,pins = <
- 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
- 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
- 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
- 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
- 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
- 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
- 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
- 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
- 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
- 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
- >;
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
-
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
- dr_mode = "peripheral";
-};
-
-&usb1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&cppi41dma {
- status = "okay";
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
-
- status = "okay";
- clock-frequency = <400000>;
-
- tps: tps@24 {
- reg = <0x24>;
- };
-
-};
-
-/include/ "tps65217.dtsi"
-
-&tps {
- regulators {
- dcdc1_reg: regulator@0 {
- regulator-always-on;
- };
-
- dcdc2_reg: regulator@1 {
- /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
- regulator-name = "vdd_mpu";
- regulator-min-microvolt = <925000>;
- regulator-max-microvolt = <1325000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- dcdc3_reg: regulator@2 {
- /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
- regulator-name = "vdd_core";
- regulator-min-microvolt = <925000>;
- regulator-max-microvolt = <1150000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: regulator@3 {
- regulator-always-on;
- };
-
- ldo2_reg: regulator@4 {
- regulator-always-on;
- };
-
- ldo3_reg: regulator@5 {
- regulator-always-on;
- };
-
- ldo4_reg: regulator@6 {
- regulator-always-on;
- };
- };
-};
-
-&cpsw_emac0 {
- phy_id = <&davinci_mdio>, <0>;
- phy-mode = "mii";
-};
-
-&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <1>;
- phy-mode = "mii";
-};
-
-&mac {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&cpsw_default>;
- pinctrl-1 = <&cpsw_sleep>;
- status = "okay";
-};
-
-&davinci_mdio {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&davinci_mdio_default>;
- pinctrl-1 = <&davinci_mdio_sleep>;
- status = "okay";
-};
-
-&mmc1 {
- status = "okay";
- bus-width = <0x4>;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins>;
- cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
-};
+#include <arm/am335x-bone-common.dtsi>
diff --git a/arch/arm/dts/am33xx-strip.dtsi b/arch/arm/dts/am33xx-strip.dtsi
index 83d23a8..0c9d852 100644
--- a/arch/arm/dts/am33xx-strip.dtsi
+++ b/arch/arm/dts/am33xx-strip.dtsi
@@ -12,8 +12,8 @@
/delete-property/ i2c1;
/delete-property/ i2c2;
/delete-property/ mmc2;
- /delete-property/ d_can0;
- /delete-property/ d_can1;
+ /delete-property/ d-can0;
+ /delete-property/ d-can1;
/delete-property/ spi1;
};
};
diff --git a/arch/arm/dts/imx51-babbage.dts b/arch/arm/dts/imx51-babbage.dts
index 5147195..f85415f 100644
--- a/arch/arm/dts/imx51-babbage.dts
+++ b/arch/arm/dts/imx51-babbage.dts
@@ -67,5 +67,25 @@
MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
>;
};
+
+ pinctrl_usbh1: usbh1grp {
+ /*
+ * Ditto for USBH1 iomux settings.
+ */
+ fsl,pins = <
+ MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
+ MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
+ MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
+ MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
+ MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
+ MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
+ MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
+ MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
+ MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
+ MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
+ MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
+ MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
+ >;
+ };
};
};
diff --git a/arch/arm/dts/imx51-zii-rdu1.dts b/arch/arm/dts/imx51-zii-rdu1.dts
index 979c4c9..bde565f 100644
--- a/arch/arm/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/dts/imx51-zii-rdu1.dts
@@ -86,3 +86,45 @@
};
};
};
+
+&iomuxc {
+ pinctrl_usbh1: usbh1grp {
+
+ /*
+ * Overwrite upstream USBH1,2 iomux settings to match
+ * the setting U-Boot would set these to. Remove this
+ * once this is fixed upstream.
+ */
+ fsl,pins = <
+ MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
+ MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
+ MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
+ MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
+ MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
+ MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
+ MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
+ MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
+ MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
+ MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
+ MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
+ MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
+ >;
+ };
+
+ pinctrl_usbh2: usbh2grp {
+ fsl,pins = <
+ MX51_PAD_EIM_A26__USBH2_STP 0x1e5
+ MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
+ MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
+ MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
+ MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
+ MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
+ MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
+ MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
+ MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
+ MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
+ MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
+ MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
+ >;
+ };
+};
diff --git a/arch/arm/dts/tegra20-colibri.dtsi b/arch/arm/dts/tegra20-colibri.dtsi
index e931c07..4f6dc9d 100644
--- a/arch/arm/dts/tegra20-colibri.dtsi
+++ b/arch/arm/dts/tegra20-colibri.dtsi
@@ -1,2 +1,2 @@
-#include <arm/tegra20-colibri-512.dtsi>
+#include <arm/tegra20-colibri.dtsi>
#include "tegra20.dtsi"
diff --git a/arch/arm/dts/vf610-zii-dev-rev-b.dts b/arch/arm/dts/vf610-zii-dev-rev-b.dts
index 1eb01f4..ac0807c 100644
--- a/arch/arm/dts/vf610-zii-dev-rev-b.dts
+++ b/arch/arm/dts/vf610-zii-dev-rev-b.dts
@@ -45,3 +45,14 @@
#include <arm/vf610-zii-dev-rev-b.dts>
#include "vf610-zii-dev.dtsi"
+
+/ {
+ spi0 {
+ m25p128@0 {
+ partition@0 {
+ label = "bootloader";
+ reg = <0x0 0x100000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 7cb9138..1d6b4e1 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -53,21 +53,6 @@ config ARCH_IMX_IMXIMAGE_SSL_SUPPORT
This enables SSL support for the imx-image tool. This is required
for created images for HABv3. This adds openssl to the build dependencies
-config ARCH_IMX_XLOAD
- bool
- depends on ARCH_IMX51
- prompt "Build preloader image"
-
-config ARCH_IMX_UNUSED_IRAM_BASE
- hex
- depends on ARCH_IMX_XLOAD
- default 0x1ffe2000 if ARCH_IMX51
-
-config ARCH_IMX_UNUSED_IRAM_SIZE
- hex
- depends on ARCH_IMX_XLOAD
- default 0x16000 if ARCH_IMX51
-
config ARCH_IMX_EXTERNAL_BOOT_NAND
bool
depends on ARCH_IMX25 || ARCH_IMX27 || ARCH_IMX31 || ARCH_IMX35
@@ -242,6 +227,7 @@ config MACH_KINDLE_MX50
select MFD_MC13XXX
select ARM_BOARD_APPEND_ATAG
select ARM_LINUX
+ select OFTREE
help
Say Y here if you are using the fourth or fifth generation Amazon
Kindle Model No. D01100 (Kindle Wi-Fi), D01200 (Kindle Touch) or
@@ -433,7 +419,7 @@ config MACH_ZII_RDU2
select ARCH_IMX6
config MACH_ZII_VF610_DEV
- bool "Zodiac VF610 Dev Family"
+ bool "ZII VF610 Dev Family"
select ARCH_VF610
select CLKDEV_LOOKUP
@@ -767,7 +753,29 @@ config HABV4
help
High Assurance Boot, as found on i.MX28/i.MX6.
-if HABV4
+config HAB_CERTS_ENV
+ depends on HAB
+ bool "Specify certificates in environment"
+ help
+ If this option is enabled the pathes to the HAB certificates are
+ taken from environment variables which allows for better integration
+ with build systems. With this option disabled the pathes can be
+ specified below.
+
+ The environment variables have the same name as the corresponding
+ Kconfig variables. For HABv3 these are:
+
+ CONFIG_HABV3_SRK_PEM
+ CONFIG_HABV3_CSF_CRT_DER
+ CONFIG_HABV3_IMG_CRT_DER
+
+ For HABv4:
+
+ CONFIG_HABV4_TABLE_BIN
+ CONFIG_HABV4_CSF_CRT_PEM
+ CONFIG_HABV4_IMG_CRT_PEM
+
+if HABV4 && !HAB_CERTS_ENV
config HABV4_TABLE_BIN
string "Path to SRK table"
@@ -791,7 +799,7 @@ config HABV4_CSF_CRT_PEM
config HABV4_IMG_CRT_PEM
string "Path to IMG certificate"
- default "../crts/IMG_1_sha256_4096_65537_v3_usr_crt.pem"
+ default "../crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem"
help
Path to the Image certificate, produced by the Freescale
Public Key Infrastructure (PKI) script.
@@ -810,7 +818,7 @@ config HABV3
help
High Assurance Boot, as found on i.MX25.
-if HABV3
+if HABV3 && !HAB_CERTS_ENV
config HABV3_SRK_PEM
string "Path to SRK Certificate (PEM)"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 595a751..5a01dd5 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -18,7 +18,6 @@ obj-$(CONFIG_ARCH_IMX7) += imx7.o
obj-$(CONFIG_ARCH_VF610) += vf610.o
obj-$(CONFIG_ARCH_IMX8MQ) += imx8mq.o
lwl-$(CONFIG_ARCH_IMX8MQ) += imx8-ddrc.o atf.o
-obj-$(CONFIG_ARCH_IMX_XLOAD) += xload.o
obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_NAND_IMX) += nand.o
lwl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
diff --git a/arch/arm/mach-imx/imx-bbu-external-nand.c b/arch/arm/mach-imx/imx-bbu-external-nand.c
index 0f1a028..52622ac 100644
--- a/arch/arm/mach-imx/imx-bbu-external-nand.c
+++ b/arch/arm/mach-imx/imx-bbu-external-nand.c
@@ -190,7 +190,7 @@ out:
* each bit represents a single block. With 2k NAND flashes this is enough for
* 4MiB size including bad blocks.
*/
-int imx_bbu_external_nand_register_handler(const char *name, char *devicefile,
+int imx_bbu_external_nand_register_handler(const char *name, const char *devicefile,
unsigned long flags)
{
struct bbu_handler *handler;
diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c
index 55e344c..504e359 100644
--- a/arch/arm/mach-imx/imx-bbu-internal.c
+++ b/arch/arm/mach-imx/imx-bbu-internal.c
@@ -16,8 +16,6 @@
* GNU General Public License for more details.
*/
-#define IMX_INTERNAL_NAND_BBU
-
#include <common.h>
#include <malloc.h>
#include <bbu.h>
@@ -31,18 +29,55 @@
#include <ioctl.h>
#include <environment.h>
#include <mach/bbu.h>
+#include <mach/generic.h>
+#include <libfile.h>
-#define FLASH_HEADER_OFFSET_MMC 0x400
-
-#define IMX_INTERNAL_FLAG_NAND BIT(31)
#define IMX_INTERNAL_FLAG_ERASE BIT(30)
struct imx_internal_bbu_handler {
struct bbu_handler handler;
+ int (*write_device)(struct imx_internal_bbu_handler *,
+ struct bbu_data *);
unsigned long flash_header_offset;
size_t device_size;
+ enum filetype expected_type;
};
+static bool
+imx_bbu_erase_required(struct imx_internal_bbu_handler *imx_handler)
+{
+ return imx_handler->handler.flags & IMX_INTERNAL_FLAG_ERASE;
+}
+
+static int imx_bbu_protect(int fd, struct imx_internal_bbu_handler *imx_handler,
+ const char *devicefile, int offset, int image_len,
+ int prot)
+{
+ const char *prefix = prot ? "" : "un";
+ int ret;
+
+ if (!imx_bbu_erase_required(imx_handler))
+ return 0;
+
+ pr_debug("%s: %sprotecting %s from 0x%08x to 0x%08x\n", __func__,
+ prefix, devicefile, offset, image_len);
+
+ ret = protect(fd, image_len, offset, prot);
+ if (ret) {
+ /*
+ * If protect() is not implemented for this device,
+ * just report success
+ */
+ if (ret == -ENOSYS)
+ return 0;
+
+ pr_err("%sprotecting %s failed with %s\n", prefix, devicefile,
+ strerror(-ret));
+ }
+
+ return ret;
+}
+
/*
* Actually write an image to the target device, eventually keeping a
* DOS partition table on the device
@@ -66,16 +101,12 @@ static int imx_bbu_write_device(struct imx_internal_bbu_handler *imx_handler,
if (imx_handler->handler.flags & IMX_BBU_FLAG_KEEP_HEAD)
offset += imx_handler->flash_header_offset;
- if (imx_handler->handler.flags & IMX_INTERNAL_FLAG_ERASE) {
- pr_debug("%s: unprotecting %s from 0x%08x to 0x%08x\n", __func__,
- devicefile, offset, image_len);
- ret = protect(fd, image_len, offset, 0);
- if (ret && ret != -ENOSYS) {
- pr_err("unprotecting %s failed with %s\n", devicefile,
- strerror(-ret));
- goto err_close;
- }
+ ret = imx_bbu_protect(fd, imx_handler, devicefile, offset,
+ image_len, 0);
+ if (ret)
+ goto err_close;
+ if (imx_bbu_erase_required(imx_handler)) {
pr_debug("%s: erasing %s from 0x%08x to 0x%08x\n", __func__,
devicefile, offset, image_len);
ret = erase(fd, image_len, offset);
@@ -86,33 +117,66 @@ static int imx_bbu_write_device(struct imx_internal_bbu_handler *imx_handler,
}
}
- ret = pwrite(fd, buf, image_len, offset);
- if (ret < 0)
+ ret = pwrite_full(fd, buf, image_len, offset);
+ if (ret < 0) {
+ pr_err("writing to %s failed with %s\n", devicefile,
+ strerror(-ret));
goto err_close;
-
- if (imx_handler->handler.flags & IMX_INTERNAL_FLAG_ERASE) {
- pr_debug("%s: protecting %s from 0x%08x to 0x%08x\n", __func__,
- devicefile, offset, image_len);
- ret = protect(fd, image_len, offset, 1);
- if (ret && ret != -ENOSYS) {
- pr_err("protecting %s failed with %s\n", devicefile,
- strerror(-ret));
- }
}
- ret = 0;
+ imx_bbu_protect(fd, imx_handler, devicefile, offset,
+ image_len, 1);
err_close:
close(fd);
- return ret;
+ return ret < 0 ? ret : 0;
}
-static int imx_bbu_check_prereq(const char *devicefile, struct bbu_data *data)
+static int __imx_bbu_write_device(struct imx_internal_bbu_handler *imx_handler,
+ struct bbu_data *data)
{
- int ret;
+ return imx_bbu_write_device(imx_handler, data->devicefile, data,
+ data->image, data->len);
+}
- if (file_detect_type(data->image, data->len) != filetype_arm_barebox) {
+static int imx_bbu_check_prereq(struct imx_internal_bbu_handler *imx_handler,
+ const char *devicefile, struct bbu_data *data,
+ enum filetype expected_type)
+{
+ int ret;
+ const void *blob;
+ size_t len;
+ enum filetype type;
+
+ type = file_detect_type(data->image, data->len);
+
+ switch (type) {
+ case filetype_arm_barebox:
+ /*
+ * Specifying expected_type as unknown will disable the
+ * inner image type check.
+ *
+ * The only user of this code is
+ * imx_bbu_external_nor_register_handler() used by
+ * i.MX27.
+ */
+ if (expected_type == filetype_unknown)
+ break;
+
+ blob = data->image + imx_handler->flash_header_offset;
+ len = data->len - imx_handler->flash_header_offset;
+ type = file_detect_type(blob, len);
+
+ if (type != expected_type) {
+ pr_err("Expected image type: %s, "
+ "detected image type: %s\n",
+ file_type_to_string(expected_type),
+ file_type_to_string(type));
+ return -EINVAL;
+ }
+ break;
+ default:
if (!bbu_force(data, "Not an ARM barebox image"))
return -EINVAL;
}
@@ -126,30 +190,6 @@ static int imx_bbu_check_prereq(const char *devicefile, struct bbu_data *data)
return 0;
}
-/*
- * Update barebox on a v1 type internal boot (i.MX25, i.MX35, i.MX51)
- *
- * This constructs a DCD header, adds the specific DCD data and writes
- * the resulting image to the device. Currently this handles MMC/SD
- * devices.
- */
-static int imx_bbu_internal_v1_update(struct bbu_handler *handler, struct bbu_data *data)
-{
- struct imx_internal_bbu_handler *imx_handler =
- container_of(handler, struct imx_internal_bbu_handler, handler);
- int ret;
-
- ret = imx_bbu_check_prereq(data->devicefile, data);
- if (ret)
- return ret;
-
- pr_info("updating to %s\n", data->devicefile);
-
- ret = imx_bbu_write_device(imx_handler, data->devicefile, data, data->image, data->len);
-
- return ret;
-}
-
#define DBBT_MAGIC 0x44424254
#define FCB_MAGIC 0x20424346
@@ -321,40 +361,44 @@ out:
return ret;
}
-#define IVT_BARKER 0x402000d1
+static enum filetype imx_bbu_expected_filetype(void)
+{
+ if (cpu_is_mx8mq() ||
+ cpu_is_mx7() ||
+ cpu_is_mx6() ||
+ cpu_is_vf610() ||
+ cpu_is_mx53())
+ return filetype_imx_image_v2;
+
+ return filetype_imx_image_v1;
+}
-/*
- * Update barebox on a v2 type internal boot (i.MX53)
- *
- * This constructs a DCD header, adds the specific DCD data and writes
- * the resulting image to the device. Currently this handles MMC/SD
- * and NAND devices.
- */
-static int imx_bbu_internal_v2_update(struct bbu_handler *handler, struct bbu_data *data)
+static unsigned long imx_bbu_flash_header_offset_mmc(void)
+{
+ unsigned long offset = SZ_1K;
+
+ /*
+ * i.MX8MQ moved the header by 32K to accomodate for GPT
+ * partition tables
+ */
+ if (cpu_is_mx8mq())
+ offset += SZ_32K;
+
+ return offset;
+}
+
+static int imx_bbu_update(struct bbu_handler *handler, struct bbu_data *data)
{
struct imx_internal_bbu_handler *imx_handler =
container_of(handler, struct imx_internal_bbu_handler, handler);
int ret;
- const uint32_t *barker;
- ret = imx_bbu_check_prereq(data->devicefile, data);
+ ret = imx_bbu_check_prereq(imx_handler, data->devicefile, data,
+ imx_handler->expected_type);
if (ret)
return ret;
- barker = data->image + imx_handler->flash_header_offset;
-
- if (*barker != IVT_BARKER) {
- pr_err("Board does not provide DCD data and this image is no imximage\n");
- return -EINVAL;
- }
-
- if (imx_handler->handler.flags & IMX_INTERNAL_FLAG_NAND)
- ret = imx_bbu_internal_v2_write_nand_dbbt(imx_handler, data);
- else
- ret = imx_bbu_write_device(imx_handler, data->devicefile, data,
- data->image, data->len);
-
- return ret;
+ return imx_handler->write_device(imx_handler, data);
}
static int imx_bbu_internal_v2_mmcboot_update(struct bbu_handler *handler,
@@ -363,18 +407,10 @@ static int imx_bbu_internal_v2_mmcboot_update(struct bbu_handler *handler,
struct imx_internal_bbu_handler *imx_handler =
container_of(handler, struct imx_internal_bbu_handler, handler);
int ret;
- const uint32_t *barker;
char *bootpartvar;
const char *bootpart;
char *devicefile;
- barker = data->image + imx_handler->flash_header_offset;
-
- if (*barker != IVT_BARKER) {
- pr_err("Board does not provide DCD data and this image is no imximage\n");
- return -EINVAL;
- }
-
ret = asprintf(&bootpartvar, "%s.boot", data->devicefile);
if (ret < 0)
return ret;
@@ -391,7 +427,8 @@ static int imx_bbu_internal_v2_mmcboot_update(struct bbu_handler *handler,
if (ret < 0)
goto free_bootpartvar;
- ret = imx_bbu_check_prereq(devicefile, data);
+ ret = imx_bbu_check_prereq(imx_handler, devicefile, data,
+ filetype_imx_image_v2);
if (ret)
goto free_devicefile;
@@ -410,22 +447,9 @@ free_bootpartvar:
return ret;
}
-static int imx_bbu_external_update(struct bbu_handler *handler, struct bbu_data *data)
-{
- struct imx_internal_bbu_handler *imx_handler =
- container_of(handler, struct imx_internal_bbu_handler, handler);
- int ret;
-
- ret = imx_bbu_check_prereq(data->devicefile, data);
- if (ret)
- return ret;
-
- return imx_bbu_write_device(imx_handler, data->devicefile, data,
- data->image, data->len);
-}
-
-static struct imx_internal_bbu_handler *__init_handler(const char *name, char *devicefile,
- unsigned long flags)
+static struct imx_internal_bbu_handler *__init_handler(const char *name,
+ const char *devicefile,
+ unsigned long flags)
{
struct imx_internal_bbu_handler *imx_handler;
struct bbu_handler *handler;
@@ -435,6 +459,10 @@ static struct imx_internal_bbu_handler *__init_handler(const char *name, char *d
handler->devicefile = devicefile;
handler->name = name;
handler->flags = flags;
+ handler->handler = imx_bbu_update;
+
+ imx_handler->expected_type = imx_bbu_expected_filetype();
+ imx_handler->write_device = __imx_bbu_write_device;
return imx_handler;
}
@@ -451,73 +479,62 @@ static int __register_handler(struct imx_internal_bbu_handler *imx_handler)
}
static int
-imx_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
- unsigned long flags, void *handler)
+imx_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
+ unsigned long flags)
{
struct imx_internal_bbu_handler *imx_handler;
imx_handler = __init_handler(name, devicefile, flags |
IMX_BBU_FLAG_KEEP_HEAD);
- imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
-
- imx_handler->handler.handler = handler;
+ imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc();
return __register_handler(imx_handler);
}
-int imx51_bbu_internal_spi_i2c_register_handler(const char *name,
- char *devicefile, unsigned long flags)
+static int
+imx_bbu_internal_spi_i2c_register_handler(const char *name,
+ const char *devicefile,
+ unsigned long flags)
{
struct imx_internal_bbu_handler *imx_handler;
imx_handler = __init_handler(name, devicefile, flags |
IMX_INTERNAL_FLAG_ERASE);
- imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
-
- imx_handler->handler.handler = imx_bbu_internal_v1_update;
+ imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc();
return __register_handler(imx_handler);
}
+int imx51_bbu_internal_spi_i2c_register_handler(const char *name,
+ const char *devicefile,
+ unsigned long flags)
+ __alias(imx_bbu_internal_spi_i2c_register_handler);
+
/*
* Register an i.MX51 internal boot update handler for MMC/SD
*/
-int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
- unsigned long flags)
-{
-
- return imx_bbu_internal_mmc_register_handler(name, devicefile, flags,
- imx_bbu_internal_v1_update);
-}
+int imx51_bbu_internal_mmc_register_handler(const char *name,
+ const char *devicefile,
+ unsigned long flags)
+ __alias(imx_bbu_internal_mmc_register_handler);
/*
* Register an i.MX53 internal boot update handler for MMC/SD
*/
-int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
- unsigned long flags)
-{
- return imx_bbu_internal_mmc_register_handler(name, devicefile, flags,
- imx_bbu_internal_v2_update);
-}
+int imx53_bbu_internal_mmc_register_handler(const char *name,
+ const char *devicefile,
+ unsigned long flags)
+ __alias(imx_bbu_internal_mmc_register_handler);
/*
* Register an i.MX6 internal boot update handler for i2c/spi
* EEPROMs / flashes. Nearly the same as MMC/SD, but we do not need to
* keep a partition table. We have to erase the device beforehand though.
*/
-int imx53_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
- unsigned long flags)
-{
- struct imx_internal_bbu_handler *imx_handler;
-
- imx_handler = __init_handler(name, devicefile, flags |
- IMX_INTERNAL_FLAG_ERASE);
- imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
-
- imx_handler->handler.handler = imx_bbu_internal_v2_update;
-
- return __register_handler(imx_handler);
-}
+int imx53_bbu_internal_spi_i2c_register_handler(const char *name,
+ const char *devicefile,
+ unsigned long flags)
+ __alias(imx_bbu_internal_spi_i2c_register_handler);
/*
* Register an i.MX53 internal boot update handler for NAND
@@ -527,13 +544,11 @@ int imx53_bbu_internal_nand_register_handler(const char *name,
{
struct imx_internal_bbu_handler *imx_handler;
- imx_handler = __init_handler(name, NULL, flags |
- IMX_INTERNAL_FLAG_NAND);
- imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
+ imx_handler = __init_handler(name, "/dev/nand0", flags);
+ imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc();
- imx_handler->handler.handler = imx_bbu_internal_v2_update;
- imx_handler->handler.devicefile = "/dev/nand0";
imx_handler->device_size = partition_size;
+ imx_handler->write_device = imx_bbu_internal_v2_write_nand_dbbt;
return __register_handler(imx_handler);
}
@@ -541,18 +556,28 @@ int imx53_bbu_internal_nand_register_handler(const char *name,
/*
* Register an i.MX6 internal boot update handler for MMC/SD
*/
-int imx6_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+int imx6_bbu_internal_mmc_register_handler(const char *name,
+ const char *devicefile,
unsigned long flags)
__alias(imx53_bbu_internal_mmc_register_handler);
/*
* Register an VF610 internal boot update handler for MMC/SD
*/
-int vf610_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+int vf610_bbu_internal_mmc_register_handler(const char *name,
+ const char *devicefile,
unsigned long flags)
__alias(imx6_bbu_internal_mmc_register_handler);
/*
+ * Register an i.MX8MQ internal boot update handler for MMC/SD
+ */
+int imx8mq_bbu_internal_mmc_register_handler(const char *name,
+ const char *devicefile,
+ unsigned long flags)
+ __alias(imx6_bbu_internal_mmc_register_handler);
+
+/*
* Register a handler that writes to the non-active boot partition of an mmc
* medium and on success activates the written-to partition. So the machine can
* still boot even after a failed try to write a boot image.
@@ -561,13 +586,14 @@ int vf610_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
* Note that no further partitioning of the boot partition is supported up to
* now.
*/
-int imx6_bbu_internal_mmcboot_register_handler(const char *name, char *devicefile,
+int imx6_bbu_internal_mmcboot_register_handler(const char *name,
+ const char *devicefile,
unsigned long flags)
{
struct imx_internal_bbu_handler *imx_handler;
imx_handler = __init_handler(name, devicefile, flags);
- imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
+ imx_handler->flash_header_offset = imx_bbu_flash_header_offset_mmc();
imx_handler->handler.handler = imx_bbu_internal_v2_mmcboot_update;
@@ -580,18 +606,30 @@ int imx6_bbu_internal_mmcboot_register_handler(const char *name, char *devicefil
* keep a partition table. We have to erase the device beforehand though.
*/
int imx6_bbu_internal_spi_i2c_register_handler(const char *name,
- char *devicefile,
+ const char *devicefile,
unsigned long flags)
__alias(imx53_bbu_internal_spi_i2c_register_handler);
-int imx_bbu_external_nor_register_handler(const char *name, char *devicefile,
- unsigned long flags)
+/*
+ * Register an VFxxx internal boot update handler for i2c/spi
+ * EEPROMs / flashes. Nearly the same as MMC/SD, but we do not need to
+ * keep a partition table. We have to erase the device beforehand though.
+ */
+int vf610_bbu_internal_spi_i2c_register_handler(const char *name,
+ const char *devicefile,
+ unsigned long flags)
+ __alias(imx6_bbu_internal_spi_i2c_register_handler);
+
+int imx_bbu_external_nor_register_handler(const char *name,
+ const char *devicefile,
+ unsigned long flags)
{
struct imx_internal_bbu_handler *imx_handler;
imx_handler = __init_handler(name, devicefile, flags |
IMX_INTERNAL_FLAG_ERASE);
- imx_handler->handler.handler = imx_bbu_external_update;
+
+ imx_handler->expected_type = filetype_unknown;
return __register_handler(imx_handler);
}
diff --git a/arch/arm/mach-imx/imx50.c b/arch/arm/mach-imx/imx50.c
index f7cbc9d..4fd5481 100644
--- a/arch/arm/mach-imx/imx50.c
+++ b/arch/arm/mach-imx/imx50.c
@@ -22,6 +22,7 @@
#include <mach/clock-imx51_53.h>
#include <mach/generic.h>
#include <mach/reset-reason.h>
+#include <mach/usb.h>
#define SI_REV 0x48
@@ -90,6 +91,9 @@ void imx50_init_lowlevel_early(unsigned int cpufreq_mhz)
void __iomem *ccm = IOMEM(MX50_CCM_BASE_ADDR);
u32 r;
+ if ((readl(ccm + MX5_CCM_CCGR2) & MX5_CCM_CCGRx_CG13_MASK))
+ imx_reset_otg_controller(IOMEM(MX50_OTG_BASE_ADDR));
+
imx5_init_lowlevel();
/*
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index ec8cdd8..7404254 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -22,6 +22,7 @@
#include <mach/clock-imx51_53.h>
#include <mach/generic.h>
#include <mach/reset-reason.h>
+#include <mach/usb.h>
#define IIM_SREV 0x24
@@ -140,6 +141,9 @@ void imx51_init_lowlevel(unsigned int cpufreq_mhz)
u32 r;
int rev = imx51_silicon_revision();
+ if ((readl(ccm + MX5_CCM_CCGR2) & MX5_CCM_CCGRx_CG13_MASK))
+ imx_reset_otg_controller(IOMEM(MX51_OTG_BASE_ADDR));
+
imx5_init_lowlevel();
/* disable write combine for TO 2 and lower revs */
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index b22929f..f8e34a3 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -22,6 +22,7 @@
#include <mach/clock-imx51_53.h>
#include <mach/generic.h>
#include <mach/reset-reason.h>
+#include <mach/usb.h>
#define SI_REV 0x48
@@ -88,6 +89,9 @@ void imx53_init_lowlevel_early(unsigned int cpufreq_mhz)
void __iomem *ccm = (void __iomem *)MX53_CCM_BASE_ADDR;
u32 r, cbcdr, cbcmr;
+ if ((readl(ccm + MX5_CCM_CCGR2) & MX5_CCM_CCGRx_CG13_MASK))
+ imx_reset_otg_controller(IOMEM(MX53_OTG_BASE_ADDR));
+
imx5_init_lowlevel();
/*
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 3d95c9e..cc368c5 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -24,11 +24,13 @@
#include <mach/imx6-anadig.h>
#include <mach/imx6-regs.h>
#include <mach/generic.h>
+#include <mach/usb.h>
#include <asm/mmu.h>
#include <asm/cache-l2x0.h>
#include <poweroff.h>
#include <mach/imx6-regs.h>
+#include <mach/clock-imx6.h>
#include <io.h>
#define CLPCR 0x54
@@ -52,6 +54,9 @@ static void imx6_init_lowlevel(void)
uint32_t periph_sel_2;
uint32_t reg;
+ if ((readl(MXC_CCM_CCGR6) & 0x3))
+ imx_reset_otg_controller(IOMEM(MX6_OTG_BASE_ADDR));
+
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h
index b9b2c5b..b64c8d1 100644
--- a/arch/arm/mach-imx/include/mach/bbu.h
+++ b/arch/arm/mach-imx/include/mach/bbu.h
@@ -32,57 +32,63 @@ struct imx_dcd_v2_entry;
#ifdef CONFIG_BAREBOX_UPDATE
-int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+int imx51_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
unsigned long flags);
int imx51_bbu_internal_spi_i2c_register_handler(const char *name,
- char *devicefile, unsigned long flags);
+ const char *devicefile, unsigned long flags);
-int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+int imx53_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
unsigned long flags);
-int imx53_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
+int imx53_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
unsigned long flags);
int imx53_bbu_internal_nand_register_handler(const char *name,
unsigned long flags, int partition_size);
-int imx6_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+int imx6_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
unsigned long flags);
-int imx6_bbu_internal_mmcboot_register_handler(const char *name, char *devicefile,
+int imx6_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile,
unsigned long flags);
-int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
+int imx6_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
unsigned long flags);
-int vf610_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+int vf610_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
unsigned long flags);
-int imx_bbu_external_nor_register_handler(const char *name, char *devicefile,
+int vf610_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
+ unsigned long flags);
+
+int imx8mq_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
+ unsigned long flags);
+
+int imx_bbu_external_nor_register_handler(const char *name, const char *devicefile,
unsigned long flags);
#else
-static inline int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+static inline int imx51_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
unsigned long flags)
{
return -ENOSYS;
}
static inline int imx51_bbu_internal_spi_i2c_register_handler(const char *name,
- char *devicefile, unsigned long flags)
+ const char *devicefile, unsigned long flags)
{
return -ENOSYS;
}
-static inline int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+static inline int imx53_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
unsigned long flags)
{
return -ENOSYS;
}
-static inline int imx53_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
+static inline int imx53_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
unsigned long flags)
{
return -ENOSYS;
@@ -94,43 +100,57 @@ static inline int imx53_bbu_internal_nand_register_handler(const char *name,
return -ENOSYS;
}
-static inline int imx6_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+static inline int imx6_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
unsigned long flags)
{
return -ENOSYS;
}
static inline int imx6_bbu_internal_mmcboot_register_handler(const char *name,
- char *devicefile,
+ const char *devicefile,
unsigned long flags)
{
return -ENOSYS;
}
-static inline int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
+static inline int imx6_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
unsigned long flags)
{
return -ENOSYS;
}
-static inline int vf610_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
+static inline int vf610_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
unsigned long flags)
{
return -ENOSYS;
}
-static inline int imx_bbu_external_nor_register_handler(const char *name, char *devicefile,
+static inline int imx8mq_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
+ unsigned long flags)
+{
+ return -ENOSYS;
+}
+
+static inline int imx_bbu_external_nor_register_handler(const char *name, const char *devicefile,
unsigned long flags)
{
return -ENOSYS;
}
+
+static inline int
+vf610_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
+ unsigned long flags)
+{
+ return -ENOSYS;
+}
+
#endif
#if defined(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND)
-int imx_bbu_external_nand_register_handler(const char *name, char *devicefile,
+int imx_bbu_external_nand_register_handler(const char *name, const char *devicefile,
unsigned long flags);
#else
-static inline int imx_bbu_external_nand_register_handler(const char *name, char *devicefile,
+static inline int imx_bbu_external_nand_register_handler(const char *name, const char *devicefile,
unsigned long flags)
{
return -ENOSYS;
diff --git a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h
index 0649caa..5818879 100644
--- a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h
+++ b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h
@@ -43,3 +43,16 @@ hab [Authenticate Data]
hab Verification index = 2
hab_blocks
+
+hab_encrypt [Install Secret Key]
+hab_encrypt Verification index = 0
+hab_encrypt Target index = 0
+hab_encrypt_key
+hab_encrypt_key_length 256
+hab_encrypt_blob_address
+
+hab_encrypt [Decrypt Data]
+hab_encrypt Verification index = 0
+hab_encrypt Mac Bytes = 16
+
+hab_encrypt_blocks
diff --git a/arch/arm/mach-imx/include/mach/imx-header.h b/arch/arm/mach-imx/include/mach/imx-header.h
index c9b2a58..05f1669 100644
--- a/arch/arm/mach-imx/include/mach/imx-header.h
+++ b/arch/arm/mach-imx/include/mach/imx-header.h
@@ -4,6 +4,14 @@
#include <linux/types.h>
#define HEADER_LEN 0x1000 /* length of the blank area + IVT + DCD */
+#define CSF_LEN 0x2000 /* length of the CSF (needed for HAB) */
+
+#define DEK_BLOB_HEADER 8 /* length of DEK blob header */
+#define DEK_BLOB_KEY 32 /* length of DEK blob AES-256 key */
+#define DEK_BLOB_MAC 16 /* length of DEK blob MAC */
+
+/* DEK blob length excluding DEK itself */
+#define DEK_BLOB_OVERHEAD (DEK_BLOB_HEADER + DEK_BLOB_KEY + DEK_BLOB_MAC)
/*
* ============================================================================
@@ -47,6 +55,14 @@ struct imx_dcd_rec_v1 {
#define PARAMETER_FLAG_MASK (1 << 3)
#define PARAMETER_FLAG_SET (1 << 4)
+#define PLUGIN_HDMI_IMAGE 0x0002
+
+/*
+ * As per Table 6-22 "eMMC/SD BOOT layout", in Normal Boot layout HDMI
+ * firmware image starts at LBA# 64 and ends at LBA# 271
+ */
+#define PLUGIN_HDMI_SIZE ((271 - 64 + 1) * 512)
+
struct imx_ivt_header {
uint8_t tag;
uint16_t length;
@@ -94,6 +110,9 @@ struct config_data {
int (*nop)(const struct config_data *data);
int csf_space;
char *csf;
+ char *signed_hdmi_firmware_file;
+ int encrypt_image;
+ size_t dek_size;
};
#define MAX_RECORDS_DCD_V2 1024
diff --git a/arch/arm/mach-imx/include/mach/imx6-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx6-ccm-regs.h
deleted file mode 100644
index 099d562..0000000
--- a/arch/arm/mach-imx/include/mach/imx6-ccm-regs.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define MX6_CCM_CCOSR 0x020c4060
-#define MX6_CCM_CCGR0 0x020C4068
-#define MX6_CCM_CCGR1 0x020C406c
-#define MX6_CCM_CCGR2 0x020C4070
-#define MX6_CCM_CCGR3 0x020C4074
-#define MX6_CCM_CCGR4 0x020C4078
-#define MX6_CCM_CCGR5 0x020C407c
-#define MX6_CCM_CCGR6 0x020C4080
-
-#define MX6_PMU_MISC2 0x020C8170
diff --git a/arch/arm/mach-imx/include/mach/ocotp-fusemap.h b/arch/arm/mach-imx/include/mach/ocotp-fusemap.h
index 44b58ca..aec50db 100644
--- a/arch/arm/mach-imx/include/mach/ocotp-fusemap.h
+++ b/arch/arm/mach-imx/include/mach/ocotp-fusemap.h
@@ -23,7 +23,11 @@
#define OCOTP_BOOT_CFG2 (OCOTP_WORD(0x450) | OCOTP_BIT(8) | OCOTP_WIDTH(8))
#define OCOTP_BOOT_CFG3 (OCOTP_WORD(0x450) | OCOTP_BIT(16) | OCOTP_WIDTH(8))
#define OCOTP_BOOT_CFG4 (OCOTP_WORD(0x450) | OCOTP_BIT(24) | OCOTP_WIDTH(8))
+/* available on i.MX6SDL silicon revision >=1.4, "reserved" elsewhere */
+#define OCOTP_SDP_DISABLE (OCOTP_WORD(0x460) | OCOTP_BIT(0) | OCOTP_WIDTH(1))
#define OCOTP_SEC_CONFIG_1 (OCOTP_WORD(0x460) | OCOTP_BIT(1) | OCOTP_WIDTH(1))
+/* available on i.MX6SDL silicon revision >=1.4, "reserved" elsewhere */
+#define OCOTP_SDP_READ_DISABLE (OCOTP_WORD(0x460) | OCOTP_BIT(2) | OCOTP_WIDTH(1))
#define OCOTP_DIR_BT_DIS (OCOTP_WORD(0x460) | OCOTP_BIT(3) | OCOTP_WIDTH(1))
#define OCOTP_BT_FUSE_SEL (OCOTP_WORD(0x460) | OCOTP_BIT(4) | OCOTP_WIDTH(1))
#define OCOTP_SJC_DISABLE (OCOTP_WORD(0x460) | OCOTP_BIT(20) | OCOTP_WIDTH(1))
@@ -31,6 +35,8 @@
#define OCOTP_JTAG_SMODE (OCOTP_WORD(0x460) | OCOTP_BIT(22) | OCOTP_WIDTH(2))
#define OCOTP_KTE (OCOTP_WORD(0x460) | OCOTP_BIT(26) | OCOTP_WIDTH(1))
#define OCOTP_JTAG_HEO (OCOTP_WORD(0x460) | OCOTP_BIT(27) | OCOTP_WIDTH(1))
+/* available on i.MX6SDL silicon revision >=1.4, "reserved" elsewhere */
+#define OCOTP_FORCE_INTERNAL_BOOT (OCOTP_WORD(0x460) | OCOTP_BIT(31) | OCOTP_WIDTH(1))
#define OCOTP_NAND_READ_CMD_CODE1 (OCOTP_WORD(0x470) | OCOTP_BIT(0) | OCOTP_WIDTH(8))
#define OCOTP_NAND_READ_CMD_CODE2 (OCOTP_WORD(0x470) | OCOTP_BIT(8) | OCOTP_WIDTH(8))
#define OCOTP_TEMP_SENSE (OCOTP_WORD(0x4e0) | OCOTP_BIT(0) | OCOTP_WIDTH(32))
diff --git a/arch/arm/mach-imx/include/mach/usb.h b/arch/arm/mach-imx/include/mach/usb.h
index 85528d7..3b5e24d 100644
--- a/arch/arm/mach-imx/include/mach/usb.h
+++ b/arch/arm/mach-imx/include/mach/usb.h
@@ -14,4 +14,27 @@
int imx6_usb_phy2_disable_oc(void);
int imx6_usb_phy2_enable(void);
+#define USBCMD 0x140
+#define USB_CMD_RESET 0x00000002
+
+/*
+ * imx_reset_otg_controller - reset the USB OTG controller
+ * @base: The base address of the controller
+ *
+ * When booting from USB the ROM just leaves the controller enabled. This can
+ * have bad side effects when for example we change PLL frequencies. In this
+ * case it is seen that the hub the board is connected to gets confused and USB
+ * is no longer working properly on the remote host. This function resets the
+ * OTG controller. It should be called before the clocks the controller hangs on
+ * is fiddled with.
+ */
+static inline void imx_reset_otg_controller(void __iomem *base)
+{
+ u32 r;
+
+ r = readl(base + USBCMD);
+ r |= USB_CMD_RESET;
+ writel(r, base + USBCMD);
+}
+
#endif /* __MACH_USB_H_*/
diff --git a/arch/arm/mach-imx/xload-esdhc.c b/arch/arm/mach-imx/xload-esdhc.c
index 55d6c69..6455cab 100644
--- a/arch/arm/mach-imx/xload-esdhc.c
+++ b/arch/arm/mach-imx/xload-esdhc.c
@@ -224,24 +224,47 @@ esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, ptrdiff_t entry, u32 o
{
void *buf = (void *)address;
- struct imx_flash_header_v2 *hdr = buf + offset + SZ_1K;
+ struct imx_flash_header_v2 *hdr;
int ret, len;
void __noreturn (*bb)(void);
unsigned int ofs;
+ int i, header_count = 1;
len = imx_image_size();
len = ALIGN(len, SECTOR_SIZE);
- ret = esdhc_read_blocks(esdhc, buf, offset + SZ_1K + SECTOR_SIZE);
- if (ret)
- return ret;
+ for (i = 0; i < header_count; i++) {
+ ret = esdhc_read_blocks(esdhc, buf,
+ offset + SZ_1K + SECTOR_SIZE);
+ if (ret)
+ return ret;
- if (!is_imx_flash_header_v2(hdr)) {
- pr_debug("IVT header not found on SD card. "
- "Found tag: 0x%02x length: 0x%04x version: %02x\n",
- hdr->header.tag, hdr->header.length,
- hdr->header.version);
- return -EINVAL;
+ hdr = buf + offset + SZ_1K;
+
+ if (!is_imx_flash_header_v2(hdr)) {
+ pr_debug("IVT header not found on SD card. "
+ "Found tag: 0x%02x length: 0x%04x "
+ "version: %02x\n",
+ hdr->header.tag, hdr->header.length,
+ hdr->header.version);
+ return -EINVAL;
+ }
+
+ if (IS_ENABLED(CONFIG_ARCH_IMX8MQ) &&
+ hdr->boot_data.plugin & PLUGIN_HDMI_IMAGE) {
+ /*
+ * In images that include signed HDMI
+ * firmware, first v2 header would be
+ * dedicated to that and would not contain any
+ * useful for us information. In order for us
+ * to pull the rest of the bootloader image
+ * in, we need to re-read header from SD/MMC,
+ * this time skipping anything HDMI firmware
+ * related.
+ */
+ offset += hdr->boot_data.size + hdr->header.length;
+ header_count++;
+ }
}
pr_debug("Check ok, loading image\n");
diff --git a/arch/arm/mach-imx/xload.c b/arch/arm/mach-imx/xload.c
deleted file mode 100644
index 921e9ad..0000000
--- a/arch/arm/mach-imx/xload.c
+++ /dev/null
@@ -1,52 +0,0 @@
-#include <bootsource.h>
-#include <bootstrap.h>
-#include <common.h>
-#include <malloc.h>
-#include <init.h>
-#include <envfs.h>
-#include <linux/sizes.h>
-#include <fs.h>
-#include <io.h>
-
-#include <linux/clkdev.h>
-#include <linux/stat.h>
-#include <linux/clk.h>
-
-#include <mach/devices-imx51.h>
-
-static __noreturn int imx_xload(void)
-{
- enum bootsource bootsource = bootsource_get();
- void *buf;
-
- switch (bootsource) {
- case BOOTSOURCE_MMC:
- pr_info("booting from MMC\n");
- buf = bootstrap_read_disk("disk0.0", "fat");
- break;
- case BOOTSOURCE_SPI_NOR:
- pr_info("booting from SPI\n");
- buf = bootstrap_read_devfs("dataflash0", false,
- SZ_256K, SZ_1M, SZ_1M);
- break;
- default:
- pr_err("unknown bootsource %d\n", bootsource);
- hang();
- }
-
- if (!buf) {
- pr_err("failed to load barebox.bin\n");
- hang();
- }
-
- bootstrap_boot(buf, 0);
-
- hang();
-}
-
-static int imx_devices_init(void)
-{
- barebox_main = imx_xload;
- return 0;
-}
-coredevice_initcall(imx_devices_init);
diff --git a/arch/arm/mach-omap/am33xx_bbu_emmc.c b/arch/arm/mach-omap/am33xx_bbu_emmc.c
index d3adb37..1fd7222 100644
--- a/arch/arm/mach-omap/am33xx_bbu_emmc.c
+++ b/arch/arm/mach-omap/am33xx_bbu_emmc.c
@@ -73,7 +73,7 @@ error_save_part_table:
error:
close(fd);
- return ret;
+ return (ret > 0) ? 0 : ret;
}
int am33xx_bbu_emmc_mlo_register_handler(const char *name, char *devicefile)
diff --git a/commands/Kconfig b/commands/Kconfig
index 951a869..675bd1c 100644
--- a/commands/Kconfig
+++ b/commands/Kconfig
@@ -1127,7 +1127,7 @@ config CMD_DHCP
help
DHCP client to obtain IP or boot params
- Usage: dhcp [-HvcuUr]
+ Usage: dhcp [-HvcuUro]
Options:
-H HOSTNAME hostname to send to the DHCP server
@@ -1135,7 +1135,8 @@ config CMD_DHCP
-c ID DHCP Client ID (code 61) submitted in DHCP requests
-u UUID DHCP Client UUID (code 97) submitted in DHCP requests
-U CLASS DHCP User class (code 77) submitted in DHCP requests
- -r RETRY retry limit (default 20)#
+ -r RETRY retry limit (default 20)
+ -o PRIVATE DATA private data (code 224) submitted in DHCP requests
config CMD_HOST
tristate
diff --git a/commands/dhcp.c b/commands/dhcp.c
index 1f07b2f..d9e844b 100644
--- a/commands/dhcp.c
+++ b/commands/dhcp.c
@@ -24,7 +24,7 @@ static int do_dhcp(int argc, char *argv[])
struct eth_device *edev;
const char *edevname;
- while ((opt = getopt(argc, argv, "H:v:c:u:U:r:")) > 0) {
+ while ((opt = getopt(argc, argv, "H:v:c:u:U:r:o:")) > 0) {
switch (opt) {
case 'H':
dhcp_param.hostname = optarg;
@@ -44,6 +44,9 @@ static int do_dhcp(int argc, char *argv[])
case 'r':
dhcp_param.retries = simple_strtoul(optarg, NULL, 10);
break;
+ case 'o':
+ dhcp_param.option224 = optarg;
+ break;
default:
return COMMAND_ERROR_USAGE;
}
@@ -72,13 +75,14 @@ BAREBOX_CMD_HELP_OPT("-v ID\t", "DHCP Vendor ID (code 60) submitted in DHCP requ
BAREBOX_CMD_HELP_OPT("-c ID\t", "DHCP Client ID (code 61) submitted in DHCP requests")
BAREBOX_CMD_HELP_OPT("-u UUID\t", "DHCP Client UUID (code 97) submitted in DHCP requests")
BAREBOX_CMD_HELP_OPT("-U CLASS", "DHCP User class (code 77) submitted in DHCP requests")
-BAREBOX_CMD_HELP_OPT("-r RETRY", "retry limit (default 20)");
+BAREBOX_CMD_HELP_OPT("-r RETRY", "retry limit (default 20)")
+BAREBOX_CMD_HELP_OPT("-o PRIVATE DATA", "private data (code 224) submitted in DHCP requests");
BAREBOX_CMD_HELP_END
BAREBOX_CMD_START(dhcp)
.cmd = do_dhcp,
BAREBOX_CMD_DESC("DHCP client to obtain IP or boot params")
- BAREBOX_CMD_OPTS("[-HvcuUr] [device]")
+ BAREBOX_CMD_OPTS("[-HvcuUro] [device]")
BAREBOX_CMD_GROUP(CMD_GRP_NET)
BAREBOX_CMD_HELP(cmd_dhcp_help)
BAREBOX_CMD_COMPLETE(eth_complete)
diff --git a/commands/i2c.c b/commands/i2c.c
index f0d16af..2f7f820 100644
--- a/commands/i2c.c
+++ b/commands/i2c.c
@@ -145,8 +145,12 @@ static int do_i2c_write(int argc, char *argv[])
ret = 0;
if (verbose) {
- printf("wrote %i bytes starting at reg 0x%04x to i2cdev 0x%02x on bus %i\n",
- count, reg, addr, adapter->nr);
+ if (reg >= 0)
+ printf("wrote %i bytes starting at reg 0x%04x to i2cdev 0x%02x on bus %i\n",
+ count, reg, addr, adapter->nr);
+ else
+ printf("sent %i bytes in master send mode to i2cdev 0x%02x on bus %i\n",
+ count, addr, adapter->nr);
for (i = 0; i < count; i++)
printf("0x%02x ", *(buf + i));
printf("\n");
@@ -161,7 +165,7 @@ BAREBOX_CMD_HELP_START(i2c_write)
BAREBOX_CMD_HELP_TEXT("Options:")
BAREBOX_CMD_HELP_OPT ("-b BUS\t", "i2c bus number (default 0)")
BAREBOX_CMD_HELP_OPT ("-a ADDR\t", "i2c device address")
-BAREBOX_CMD_HELP_OPT ("-r START", "start register")
+BAREBOX_CMD_HELP_OPT ("-r START", "start register (optional, master send mode if none given)")
BAREBOX_CMD_HELP_OPT ("-w\t", "use word (16 bit) wide access")
BAREBOX_CMD_HELP_OPT ("-v\t", "verbose")
BAREBOX_CMD_HELP_END
@@ -204,7 +208,7 @@ static int do_i2c_read(int argc, char *argv[])
}
}
- if ((addr < 0) || (reg < 0) || (count < 1) || (addr > 0x7F))
+ if ((addr < 0) || (count < 1) || (addr > 0x7F))
return COMMAND_ERROR_USAGE;
adapter = i2c_get_adapter(bus);
@@ -217,12 +221,21 @@ static int do_i2c_read(int argc, char *argv[])
client.addr = addr;
buf = xmalloc(count);
- ret = i2c_read_reg(&client, reg | wide, buf, count);
+ if (reg >= 0)
+ ret = i2c_read_reg(&client, reg | wide, buf, count);
+ else
+ ret = i2c_master_recv(&client, buf, count);
if (ret == count) {
int i;
- if (verbose)
- printf("read %i bytes starting at reg 0x%04x from i2cdev 0x%02x on bus %i\n",
- count, reg, addr, adapter->nr);
+ if (verbose) {
+ if (reg >= 0)
+ printf("read %i bytes starting at reg 0x%04x from i2cdev 0x%02x on bus %i\n",
+ count, reg, addr, adapter->nr);
+ else
+ printf("received %i bytes in master receive mode from i2cdev 0x%02x on bus %i\n",
+ count, addr, adapter->nr);
+ }
+
for (i = 0; i < count; i++)
printf("0x%02x ", *(buf + i));
printf("\n");
@@ -237,7 +250,7 @@ BAREBOX_CMD_HELP_START(i2c_read)
BAREBOX_CMD_HELP_TEXT("Options:")
BAREBOX_CMD_HELP_OPT("-b BUS\t", "i2c bus number (default 0)")
BAREBOX_CMD_HELP_OPT("-a ADDR\t", "i2c device address")
-BAREBOX_CMD_HELP_OPT("-r START", "start register")
+BAREBOX_CMD_HELP_OPT("-r START", "start register (optional, master receive mode if none given)")
BAREBOX_CMD_HELP_OPT("-w\t", "use word (16 bit) wide access")
BAREBOX_CMD_HELP_OPT("-c COUNT", "byte count")
BAREBOX_CMD_HELP_OPT("-v\t", "verbose")
diff --git a/commands/nand.c b/commands/nand.c
index b065a66..c57b394 100644
--- a/commands/nand.c
+++ b/commands/nand.c
@@ -41,7 +41,7 @@ static int do_nand(int argc, char *argv[])
int command = 0;
loff_t badblock = 0;
int fd;
- int ret;
+ int ret = 0;
struct mtd_info_user mtdinfo;
while((opt = getopt(argc, argv, "adb:g:i")) > 0) {
@@ -88,13 +88,18 @@ static int do_nand(int argc, char *argv[])
optind++;
}
+
+ goto out_ret;
}
if (command == NAND_DEL) {
while (optind < argc) {
- dev_remove_bb_dev(basename(argv[optind]));
+ if (dev_remove_bb_dev(basename(argv[optind])))
+ return 1;
optind++;
}
+
+ goto out_ret;
}
fd = open(argv[optind], O_RDWR);
@@ -149,10 +154,10 @@ static int do_nand(int argc, char *argv[])
printf("No bad blocks\n");
}
- ret = 0;
out:
close(fd);
+out_ret:
return ret;
}
diff --git a/commands/of_property.c b/commands/of_property.c
index d0b923f..31e9b71 100644
--- a/commands/of_property.c
+++ b/commands/of_property.c
@@ -270,9 +270,8 @@ static int do_of_property_set_now(struct device_node *root, const char *path,
free(pp->value);
pp->value_const = NULL;
- /* limit property data to the actual size */
if (len)
- pp->value = xrealloc(data, len);
+ pp->value = xmemdup(data, len);
else
pp->value = NULL;
diff --git a/common/Makefile b/common/Makefile
index b6284c2..13920cc 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_DDR_SPD) += ddr_spd.o
obj-$(CONFIG_ENV_HANDLING) += environment.o
obj-$(CONFIG_ENVIRONMENT_VARIABLES) += env.o
obj-$(CONFIG_FILETYPE) += filetype.o
+CFLAGS_filetype.o = -I$(srctree)/arch/
obj-$(CONFIG_FLEXIBLE_BOOTARGS) += bootargs.o
obj-$(CONFIG_GLOBALVAR) += globalvar.o
obj-$(CONFIG_GREGORIAN_CALENDER) += date.o
diff --git a/common/bbu.c b/common/bbu.c
index 11e44f4..3974bf6 100644
--- a/common/bbu.c
+++ b/common/bbu.c
@@ -151,7 +151,7 @@ bool barebox_update_handler_exists(struct bbu_data *data)
if (!data->handler_name)
return false;
- return !bbu_find_handler(data->handler_name);
+ return bbu_find_handler(data->handler_name) != NULL;
}
static int bbu_check_of_compat(struct bbu_data *data)
@@ -260,13 +260,13 @@ int barebox_update(struct bbu_data *data)
return ret;
ret = handler->handler(handler, data);
- if (ret == -EINTR)
- printf("update aborted\n");
-
- if (!ret)
- printf("update succeeded\n");
+ if (ret) {
+ printf("update %s\n", (ret == -EINTR) ? "aborted" : "failed");
+ return ret;
+ }
- return ret;
+ printf("update succeeded\n");
+ return 0;
}
/*
diff --git a/common/block.c b/common/block.c
index 219b943..8d0de42 100644
--- a/common/block.c
+++ b/common/block.c
@@ -44,13 +44,17 @@ struct chunk {
static int writebuffer_flush(struct block_device *blk)
{
struct chunk *chunk;
+ int ret;
if (!IS_ENABLED(CONFIG_BLOCK_WRITE))
return 0;
list_for_each_entry(chunk, &blk->buffered_blocks, list) {
if (chunk->dirty) {
- blk->ops->write(blk, chunk->data, chunk->block_start, blk->rdbufsize);
+ ret = blk->ops->write(blk, chunk->data, chunk->block_start, blk->rdbufsize);
+ if (ret < 0)
+ return ret;
+
chunk->dirty = 0;
}
}
@@ -107,6 +111,7 @@ static void *block_get_cached(struct block_device *blk, int block)
static struct chunk *get_chunk(struct block_device *blk)
{
struct chunk *chunk;
+ int ret;
if (list_empty(&blk->idle_blocks)) {
/* use last entry which is the most unused */
@@ -114,8 +119,11 @@ static struct chunk *get_chunk(struct block_device *blk)
if (chunk->dirty) {
size_t num_blocks = min(blk->rdbufsize,
blk->num_blocks - chunk->block_start);
- blk->ops->write(blk, chunk->data, chunk->block_start,
- num_blocks);
+ ret = blk->ops->write(blk, chunk->data, chunk->block_start,
+ num_blocks);
+ if (ret < 0)
+ return ERR_PTR(ret);
+
chunk->dirty = 0;
}
@@ -140,6 +148,9 @@ static int block_cache(struct block_device *blk, int block)
int ret;
chunk = get_chunk(blk);
+ if (IS_ERR(chunk))
+ return PTR_ERR(chunk);
+
chunk->block_start = block & ~blk->blkmask;
debug("%s: %d to %d\n", __func__, chunk->block_start,
diff --git a/common/bootsource.c b/common/bootsource.c
index e68338f..4ef8d8a 100644
--- a/common/bootsource.c
+++ b/common/bootsource.c
@@ -82,6 +82,7 @@ char *bootsource_get_alias_name(void)
stem = bootsource_str[BOOTSOURCE_I2C];
break;
case BOOTSOURCE_SPI_EEPROM:
+ case BOOTSOURCE_SPI_NOR:
stem = bootsource_str[BOOTSOURCE_SPI];
break;
case BOOTSOURCE_SERIAL: /* FALLTHROUGH */
diff --git a/common/filetype.c b/common/filetype.c
index c5f2384..f8b6bc8 100644
--- a/common/filetype.c
+++ b/common/filetype.c
@@ -29,6 +29,8 @@
#include <image-sparse.h>
#include <elf.h>
+#include <arm/mach-imx/include/mach/imx-header.h>
+
struct filetype_str {
const char *name; /* human readable filetype */
const char *shortname; /* short string without spaces for shell scripts */
@@ -71,6 +73,8 @@ static const struct filetype_str filetype_str[] = {
[filetype_android_sparse] = { "Android sparse image", "sparse" },
[filetype_arm64_linux_image] = { "ARM aarch64 Linux image", "aarch64-linux" },
[filetype_elf] = { "ELF", "elf" },
+ [filetype_imx_image_v1] = { "i.MX image (v1)", "imx-image-v1" },
+ [filetype_imx_image_v2] = { "i.MX image (v2)", "imx-image-v2" },
};
const char *file_type_to_string(enum filetype f)
@@ -250,6 +254,7 @@ enum filetype file_detect_type(const void *_buf, size_t bufsize)
const u64 *buf64 = _buf;
const u8 *buf8 = _buf;
const u16 *buf16 = _buf;
+ const struct imx_flash_header *imx_flash_header = _buf;
enum filetype type;
if (bufsize < 9)
@@ -361,6 +366,12 @@ enum filetype file_detect_type(const void *_buf, size_t bufsize)
if (strncmp(buf8, ELFMAG, 4) == 0)
return filetype_elf;
+ if (imx_flash_header->dcd_barker == DCD_BARKER)
+ return filetype_imx_image_v1;
+
+ if (is_imx_flash_header_v2(_buf))
+ return filetype_imx_image_v2;
+
return filetype_unknown;
}
diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
index 9512343..bbfd95a 100644
--- a/drivers/clk/imx/clk-sccg-pll.c
+++ b/drivers/clk/imx/clk-sccg-pll.c
@@ -121,11 +121,9 @@ static void clk_pll1_unprepare(struct clk *clk)
{
struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
u32 val;
-printf("%s %p\n", __func__, pll);
val = readl(pll->base);
val |= (1 << PLL_PD);
writel(val, pll->base);
-printf("fuschi\n");
}
static unsigned long clk_pll2_recalc_rate(struct clk *clk,
diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index 51c267e..39a9056 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -81,8 +81,7 @@ static void rng_done(struct device_d *jrdev, u32 *desc, u32 err, void *context)
{
struct buf_data *bd;
- bd = (struct buf_data *)((char *)desc -
- offsetof(struct buf_data, hw_desc));
+ bd = container_of(desc, struct buf_data, hw_desc[0]);
if (err)
caam_jr_strstatus(jrdev, err);
@@ -243,11 +242,7 @@ static int caam_init_rng(struct caam_rng_ctx *ctx, struct device_d *jrdev)
if (err)
return err;
- err = caam_init_buf(ctx, 1);
- if (err)
- return err;
-
- return 0;
+ return caam_init_buf(ctx, 1);
}
int caam_rng_probe(struct device_d *dev, struct device_d *jrdev)
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 4deed8a..9e62bd6 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -20,6 +20,9 @@
#include "error.h"
#include "ctrl.h"
+bool caam_little_end;
+EXPORT_SYMBOL(caam_little_end);
+
/*
* Descriptor to instantiate RNG State Handle 0 in normal mode and
* load the JDKEK, TDKEK and TDSK registers
@@ -83,10 +86,10 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc,
deco = ctrlpriv->deco;
if (ctrlpriv->virt_en == 1) {
- setbits32(&ctrl->deco_rsr, DECORSR_JR0);
+ clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
start = get_time_ns();
- while (!(readl(&ctrl->deco_rsr) & DECORSR_VALID)) {
+ while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID)) {
if (is_timeout(start, 100 * MSECOND)) {
dev_err(ctrldev, "DECO timed out\n");
return -ETIMEDOUT;
@@ -94,19 +97,19 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc,
}
}
- setbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
+ clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
start = get_time_ns();
- while (!(readl(&ctrl->deco_rq) & DECORR_DEN0)) {
+ while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0)) {
if (is_timeout(start, 100 * MSECOND)) {
dev_err(ctrldev, "failed to acquire DECO 0\n");
- clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
+ clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
return -ETIMEDOUT;
}
}
for (i = 0; i < desc_len(desc); i++)
- writel(*(desc + i), &deco->descbuf[i]);
+ wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
flags = DECO_JQCR_WHL;
/*
@@ -117,10 +120,10 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc,
flags |= DECO_JQCR_FOUR;
/* Instruct the DECO to execute it */
- writel(flags, &deco->jr_ctl_hi);
+ clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
start = get_time_ns();
- while ((deco_dbg_reg = readl(&deco->desc_dbg)) &
+ while ((deco_dbg_reg = rd_reg32(&deco->desc_dbg)) &
DESC_DBG_DECO_STAT_VALID) {
/*
* If an error occured in the descriptor, then
@@ -131,14 +134,14 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc,
break;
}
- *status = readl(&deco->op_status_hi) &
+ *status = rd_reg32(&deco->op_status_hi) &
DECO_OP_STATUS_HI_ERR_MASK;
if (ctrlpriv->virt_en == 1)
- clrbits32(&ctrl->deco_rsr, DECORSR_JR0);
+ clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
/* Mark the DECO as free */
- clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
+ clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
if (is_timeout(start, 100 * MSECOND))
return -EAGAIN;
@@ -170,7 +173,7 @@ static int instantiate_rng(struct device_d *ctrldev, int state_handle_mask,
{
struct caam_drv_private *ctrlpriv = ctrldev->priv;
struct caam_ctrl __iomem *ctrl;
- u32 *desc, status, rdsta_val;
+ u32 *desc, status = 0, rdsta_val;
int ret = 0, sh_idx;
ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
@@ -199,11 +202,15 @@ static int instantiate_rng(struct device_d *ctrldev, int state_handle_mask,
* without any error (HW optimizations for later
* CAAM eras), then try again.
*/
- rdsta_val = readl(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
- if (status || !(rdsta_val & (1 << sh_idx)))
- ret = -EAGAIN;
if (ret)
break;
+
+ rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
+ if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
+ !(rdsta_val & (1 << sh_idx))) {
+ ret = -EAGAIN;
+ break;
+ }
dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
/* Clear the contents before recreating the descriptor */
memset(desc, 0x00, CAAM_CMD_SZ * 7);
@@ -218,9 +225,11 @@ static void caam_remove(struct device_d *dev)
/* shut clocks off before finalizing shutdown */
clk_disable(ctrlpriv->caam_ipg);
- clk_disable(ctrlpriv->caam_mem);
+ if (ctrlpriv->caam_mem)
+ clk_disable(ctrlpriv->caam_mem);
clk_disable(ctrlpriv->caam_aclk);
- clk_disable(ctrlpriv->caam_emi_slow);
+ if (ctrlpriv->caam_emi_slow)
+ clk_disable(ctrlpriv->caam_emi_slow);
}
/*
@@ -240,7 +249,7 @@ static void kick_trng(struct device_d *ctrldev, int ent_delay)
r4tst = &ctrl->r4tst[0];
/* put RNG4 into program mode */
- setbits32(&r4tst->rtmctl, RTMCTL_PRGM);
+ clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM);
/*
* Performance-wise, it does not make sense to
@@ -250,40 +259,79 @@ static void kick_trng(struct device_d *ctrldev, int ent_delay)
* time trying to set the values controlling the sample
* frequency, the function simply returns.
*/
- val = (readl(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
+ val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
>> RTSDCTL_ENT_DLY_SHIFT;
- if (ent_delay <= val) {
- /* put RNG4 into run mode */
- clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
- return;
- }
+ if (ent_delay <= val)
+ goto start_rng;
- val = readl(&r4tst->rtsdctl);
+ val = rd_reg32(&r4tst->rtsdctl);
val = (val & ~RTSDCTL_ENT_DLY_MASK) |
(ent_delay << RTSDCTL_ENT_DLY_SHIFT);
- writel(val, &r4tst->rtsdctl);
+ wr_reg32(&r4tst->rtsdctl, val);
/* min. freq. count, equal to 1/4 of the entropy sample length */
- writel(ent_delay >> 2, &r4tst->rtfrqmin);
+ wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
/* disable maximum frequency count */
- writel(RTFRQMAX_DISABLE, &r4tst->rtfrqmax);
+ wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
/* read the control register */
- val = readl(&r4tst->rtmctl);
+ val = rd_reg32(&r4tst->rtmctl);
+start_rng:
/*
* select raw sampling in both entropy shifter
- * and statistical checker
+ * and statistical checker; ; put RNG4 into run mode
*/
- setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC);
- /* put RNG4 into run mode */
- clrbits32(&val, RTMCTL_PRGM);
- /* write back the control register */
- writel(val, &r4tst->rtmctl);
+ clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
+}
+
+static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
+{
+ static const struct {
+ u16 ip_id;
+ u8 maj_rev;
+ u8 era;
+ } id[] = {
+ {0x0A10, 1, 1},
+ {0x0A10, 2, 2},
+ {0x0A12, 1, 3},
+ {0x0A14, 1, 3},
+ {0x0A14, 2, 4},
+ {0x0A16, 1, 4},
+ {0x0A10, 3, 4},
+ {0x0A11, 1, 4},
+ {0x0A18, 1, 4},
+ {0x0A11, 2, 5},
+ {0x0A12, 2, 5},
+ {0x0A13, 1, 5},
+ {0x0A1C, 1, 5}
+ };
+ u32 ccbvid, id_ms;
+ u8 maj_rev, era;
+ u16 ip_id;
+ int i;
+
+ ccbvid = rd_reg32(&ctrl->perfmon.ccb_id);
+ era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
+ if (era) /* This is '0' prior to CAAM ERA-6 */
+ return era;
+
+ id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms);
+ ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
+ maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
+
+ for (i = 0; i < ARRAY_SIZE(id); i++)
+ if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
+ return id[i].era;
+
+ return -ENOTSUPP;
}
/**
* caam_get_era() - Return the ERA of the SEC on SoC, based
- * on "sec-era" propery in the DTS. This property is updated by u-boot.
+ * on "sec-era" optional property in the DTS. This property is updated
+ * by u-boot.
+ * In case this property is not passed an attempt to retrieve the CAAM
+ * era via register reads will be made.
**/
-int caam_get_era(void)
+static int caam_get_era(struct caam_ctrl __iomem *ctrl)
{
struct device_node *caam_node;
int ret;
@@ -292,9 +340,11 @@ int caam_get_era(void)
caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
- return IS_ERR_VALUE(ret) ? -ENOTSUPP : prop;
+ if (!ret)
+ return prop;
+ else
+ return caam_get_era_from_hw(ctrl);
}
-EXPORT_SYMBOL(caam_get_era);
/* Probe routine for CAAM top (controller) level */
static int caam_probe(struct device_d *dev)
@@ -322,11 +372,15 @@ static int caam_probe(struct device_d *dev)
return -ENODEV;
}
- ctrlpriv->caam_mem = clk_get(dev, "mem");
- if (IS_ERR(ctrlpriv->caam_mem)) {
- ret = PTR_ERR(ctrlpriv->caam_mem);
- dev_err(dev, "can't identify CAAM secure mem clk: %d\n", ret);
- return -ENODEV;
+ if (!of_machine_is_compatible("fsl,imx7d") &&
+ !of_machine_is_compatible("fsl,imx7s")) {
+ ctrlpriv->caam_mem = clk_get(dev, "mem");
+ if (IS_ERR(ctrlpriv->caam_mem)) {
+ ret = PTR_ERR(ctrlpriv->caam_mem);
+ dev_err(dev,
+ "can't identify CAAM mem clk: %d\n", ret);
+ return -ENODEV;
+ }
}
ctrlpriv->caam_aclk = clk_get(dev, "aclk");
@@ -337,12 +391,16 @@ static int caam_probe(struct device_d *dev)
return -ENODEV;
}
- ctrlpriv->caam_emi_slow = clk_get(dev, "emi_slow");
- if (IS_ERR(ctrlpriv->caam_emi_slow)) {
- ret = PTR_ERR(ctrlpriv->caam_emi_slow);
- dev_err(dev,
- "can't identify CAAM emi slow clk: %d\n", ret);
- return -ENODEV;
+ if (!of_machine_is_compatible("fsl,imx6ul") &&
+ !of_machine_is_compatible("fsl,imx7d") &&
+ !of_machine_is_compatible("fsl,imx7s")) {
+ ctrlpriv->caam_emi_slow = clk_get(dev, "emi_slow");
+ if (IS_ERR(ctrlpriv->caam_emi_slow)) {
+ ret = PTR_ERR(ctrlpriv->caam_emi_slow);
+ dev_err(dev,
+ "can't identify CAAM emi slow clk: %d\n", ret);
+ return -ENODEV;
+ }
}
ret = clk_enable(ctrlpriv->caam_ipg);
@@ -351,11 +409,13 @@ static int caam_probe(struct device_d *dev)
return -ENODEV;
}
- ret = clk_enable(ctrlpriv->caam_mem);
- if (ret < 0) {
- dev_err(dev, "can't enable CAAM secure mem clock: %d\n",
- ret);
- return -ENODEV;
+ if (ctrlpriv->caam_mem) {
+ ret = clk_enable(ctrlpriv->caam_mem);
+ if (ret < 0) {
+ dev_err(dev, "can't enable CAAM secure mem clock: %d\n",
+ ret);
+ return -ENODEV;
+ }
}
ret = clk_enable(ctrlpriv->caam_aclk);
@@ -364,11 +424,13 @@ static int caam_probe(struct device_d *dev)
return -ENODEV;
}
- ret = clk_enable(ctrlpriv->caam_emi_slow);
- if (ret < 0) {
- dev_err(dev, "can't enable CAAM emi slow clock: %d\n",
- ret);
- return -ENODEV;
+ if (ctrlpriv->caam_emi_slow) {
+ ret = clk_enable(ctrlpriv->caam_emi_slow);
+ if (ret < 0) {
+ dev_err(dev, "can't enable CAAM emi slow clock: %d\n",
+ ret);
+ return -ENODEV;
+ }
}
/* Get configuration properties from device tree */
@@ -378,8 +440,12 @@ static int caam_probe(struct device_d *dev)
dev_err(dev, "caam: of_iomap() failed\n");
return -ENOMEM;
}
+
+ caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
+ (CSTA_PLEND | CSTA_ALT_PLEND));
+
/* Finding the page size for using the CTPR_MS register */
- comp_params = readl(&ctrl->perfmon.comp_parms_ms);
+ comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
/* Allocating the BLOCK_OFFSET based on the supported page size on
@@ -390,19 +456,19 @@ static int caam_probe(struct device_d *dev)
else
BLOCK_OFFSET = PG_SIZE_64K;
- ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
- ctrlpriv->assure = (struct caam_assurance __force *)
- ((uint8_t *)ctrl +
+ ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
+ ctrlpriv->assure = (struct caam_assurance __iomem __force *)
+ ((__force uint8_t *)ctrl +
BLOCK_OFFSET * ASSURE_BLOCK_NUMBER);
- ctrlpriv->deco = (struct caam_deco __force *)
- ((uint8_t *)ctrl +
+ ctrlpriv->deco = (struct caam_deco __iomem __force *)
+ ((__force uint8_t *)ctrl +
BLOCK_OFFSET * DECO_BLOCK_NUMBER);
/*
* Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
* long pointers in master configuration register
*/
- clrsetbits_be32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_ARCACHE_MASK,
+ clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_ARCACHE_MASK,
MCFGR_AWCACHE_CACH | MCFGR_ARCACHE_MASK |
MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ?
MCFGR_LONG_PTR : 0));
@@ -411,7 +477,7 @@ static int caam_probe(struct device_d *dev)
* Read the Compile Time paramters and SCFGR to determine
* if Virtualization is enabled for this platform
*/
- scfgr = readl(&ctrl->scfgr);
+ scfgr = rd_reg32(&ctrl->scfgr);
ctrlpriv->virt_en = 0;
if (comp_params & CTPR_MS_VIRT_EN_INCL) {
@@ -429,9 +495,9 @@ static int caam_probe(struct device_d *dev)
}
if (ctrlpriv->virt_en == 1)
- setbits32(&ctrl->jrstart, JRSTART_JR0_START |
- JRSTART_JR1_START | JRSTART_JR2_START |
- JRSTART_JR3_START);
+ clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
+ JRSTART_JR1_START | JRSTART_JR2_START |
+ JRSTART_JR3_START);
/*
* ERRATA: mx6 devices have an issue wherein AXI bus transactions
@@ -442,8 +508,8 @@ static int caam_probe(struct device_d *dev)
* to a depth of 1 (from it's default of 4) to preclude this situation
* from occurring.
*/
- writel((readl(&ctrl->mcr) & ~(MCFGR_AXIPIPE_MASK)) |
- ((1 << MCFGR_AXIPIPE_SHIFT) & MCFGR_AXIPIPE_MASK), &ctrl->mcr);
+ wr_reg32(&ctrl->mcr, (rd_reg32(&ctrl->mcr) & ~(MCFGR_AXIPIPE_MASK)) |
+ ((1 << MCFGR_AXIPIPE_SHIFT) & MCFGR_AXIPIPE_MASK));
/*
* Detect and enable JobRs
@@ -476,8 +542,8 @@ static int caam_probe(struct device_d *dev)
}
ctrlpriv->jrpdev[ring] = jrdev;
- ctrlpriv->jr[ring] = (struct caam_job_ring __force *)
- ((uint8_t *)ctrl +
+ ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
+ ((__force uint8_t *)ctrl +
(ring + JR_BLOCK_NUMBER) *
BLOCK_OFFSET);
ctrlpriv->total_jobrs++;
@@ -486,15 +552,13 @@ static int caam_probe(struct device_d *dev)
}
/* Check to see if QI present. If so, enable */
- ctrlpriv->qi_present =
- !!(readl(&ctrl->perfmon.comp_parms_ms) &
- CTPR_MS_QI_MASK);
+ ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
if (ctrlpriv->qi_present) {
- ctrlpriv->qi = (struct caam_queue_if __force *)
- ((uint8_t *)ctrl +
+ ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
+ ((__force uint8_t *)ctrl +
BLOCK_OFFSET * QI_BLOCK_NUMBER);
/* This is all that's required to physically enable QI */
- writel(QICTL_DQEN, &ctrlpriv->qi->qi_control_lo);
+ wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
}
/* If no QI and no rings specified, quit and go home */
@@ -504,7 +568,7 @@ static int caam_probe(struct device_d *dev)
return -ENOMEM;
}
- cha_vid_ls = readl(&ctrl->perfmon.cha_id_ls);
+ cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
/*
* If SEC has RNG version >= 4 and RNG state handle has not been
@@ -512,7 +576,7 @@ static int caam_probe(struct device_d *dev)
*/
if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
ctrlpriv->rng4_sh_init =
- readl(&ctrl->r4tst[0].rdsta);
+ rd_reg32(&ctrl->r4tst[0].rdsta);
/*
* If the secure keys (TDKEK, JDKEK, TDSK), were already
* generated, signal this to the function that is instantiating
@@ -523,7 +587,7 @@ static int caam_probe(struct device_d *dev)
ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
do {
int inst_handles =
- readl(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
+ rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
/*
* If either SH were instantiated by somebody else
* (e.g. u-boot) then it is assumed that the entropy
@@ -559,7 +623,7 @@ static int caam_probe(struct device_d *dev)
ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
/* Enable RDB bit so that RNG works faster */
- setbits32(&ctrl->scfgr, SCFGR_RDBENABLE);
+ clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
}
if (IS_ENABLED(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG)) {
@@ -572,12 +636,12 @@ static int caam_probe(struct device_d *dev)
}
/* NOTE: RTIC detection ought to go here, around Si time */
- caam_id = (u64)readl(&ctrl->perfmon.caam_id_ms) << 32 |
- (u64)readl(&ctrl->perfmon.caam_id_ls);
+ caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
+ (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
/* Report "alive" for developer to see */
dev_dbg(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
- caam_get_era());
+ caam_get_era(ctrl));
dev_dbg(dev, "job rings = %d, qi = %d\n",
ctrlpriv->total_jobrs, ctrlpriv->qi_present);
diff --git a/drivers/crypto/caam/ctrl.h b/drivers/crypto/caam/ctrl.h
index cac5402..22b6ad5 100644
--- a/drivers/crypto/caam/ctrl.h
+++ b/drivers/crypto/caam/ctrl.h
@@ -8,6 +8,5 @@
#define CTRL_H
/* Prototypes for backend-level services exposed to APIs */
-int caam_get_era(void);
#endif /* CTRL_H */
diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index a12eb86..ee873c0 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -20,19 +20,7 @@
#define SEC4_SG_BPID_MASK 0x000000ff
#define SEC4_SG_BPID_SHIFT 16
#define SEC4_SG_LEN_MASK 0x3fffffff /* Excludes EXT and FINAL */
-#define SEC4_SG_OFFS_MASK 0x00001fff
-
-struct sec4_sg_entry {
-#ifdef CONFIG_64BIT
- u64 ptr;
-#else
- u32 reserved;
- u32 ptr;
-#endif
- u32 len;
- u16 buf_pool_id;
- u16 offset;
-};
+#define SEC4_SG_OFFSET_MASK 0x00001fff
/* Max size of any CAAM descriptor in 32-bit words, inclusive of header */
#define MAX_CAAM_DESCSIZE 64
@@ -96,8 +84,8 @@ struct sec4_sg_entry {
#define HDR_ZRO 0x00008000
/* Start Index or SharedDesc Length */
-#define HDR_START_IDX_MASK 0x3f
#define HDR_START_IDX_SHIFT 16
+#define HDR_START_IDX_MASK (0x3f << HDR_START_IDX_SHIFT)
/* If shared descriptor header, 6-bit length */
#define HDR_DESCLEN_SHR_MASK 0x3f
@@ -127,10 +115,10 @@ struct sec4_sg_entry {
#define HDR_PROP_DNR 0x00000800
/* JobDesc/SharedDesc share property */
-#define HDR_SD_SHARE_MASK 0x03
#define HDR_SD_SHARE_SHIFT 8
-#define HDR_JD_SHARE_MASK 0x07
+#define HDR_SD_SHARE_MASK (0x03 << HDR_SD_SHARE_SHIFT)
#define HDR_JD_SHARE_SHIFT 8
+#define HDR_JD_SHARE_MASK (0x07 << HDR_JD_SHARE_SHIFT)
#define HDR_SHARE_NEVER (0x00 << HDR_SD_SHARE_SHIFT)
#define HDR_SHARE_WAIT (0x01 << HDR_SD_SHARE_SHIFT)
@@ -241,7 +229,7 @@ struct sec4_sg_entry {
#define LDST_SRCDST_WORD_DECO_MATH2 (0x0a << LDST_SRCDST_SHIFT)
#define LDST_SRCDST_WORD_DECO_AAD_SZ (0x0b << LDST_SRCDST_SHIFT)
#define LDST_SRCDST_WORD_DECO_MATH3 (0x0b << LDST_SRCDST_SHIFT)
-#define LDST_SRCDST_WORD_CLASS1_ICV_SZ (0x0c << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_CLASS1_IV_SZ (0x0c << LDST_SRCDST_SHIFT)
#define LDST_SRCDST_WORD_ALTDS_CLASS1 (0x0f << LDST_SRCDST_SHIFT)
#define LDST_SRCDST_WORD_PKHA_A_SZ (0x10 << LDST_SRCDST_SHIFT)
#define LDST_SRCDST_WORD_PKHA_B_SZ (0x11 << LDST_SRCDST_SHIFT)
@@ -406,10 +394,7 @@ struct sec4_sg_entry {
#define FIFOST_TYPE_PKHA_N (0x08 << FIFOST_TYPE_SHIFT)
#define FIFOST_TYPE_PKHA_A (0x0c << FIFOST_TYPE_SHIFT)
#define FIFOST_TYPE_PKHA_B (0x0d << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_AF_SBOX_CCM_JKEK (0x10 << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_AF_SBOX_CCM_TKEK (0x11 << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_KEY_CCM_JKEK (0x14 << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_KEY_CCM_TKEK (0x15 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_AF_SBOX_JKEK (0x20 << FIFOST_TYPE_SHIFT)
#define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT)
#define FIFOST_TYPE_PKHA_E_JKEK (0x22 << FIFOST_TYPE_SHIFT)
#define FIFOST_TYPE_PKHA_E_TKEK (0x23 << FIFOST_TYPE_SHIFT)
@@ -1131,8 +1116,8 @@ struct sec4_sg_entry {
/* For non-protocol/alg-only op commands */
#define OP_ALG_TYPE_SHIFT 24
#define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT)
-#define OP_ALG_TYPE_CLASS1 2
-#define OP_ALG_TYPE_CLASS2 4
+#define OP_ALG_TYPE_CLASS1 (2 << OP_ALG_TYPE_SHIFT)
+#define OP_ALG_TYPE_CLASS2 (4 << OP_ALG_TYPE_SHIFT)
#define OP_ALG_ALGSEL_SHIFT 16
#define OP_ALG_ALGSEL_MASK (0xff << OP_ALG_ALGSEL_SHIFT)
@@ -1273,7 +1258,7 @@ struct sec4_sg_entry {
#define OP_ALG_PKMODE_MOD_PRIMALITY 0x00f
/* PKHA mode copy-memory functions */
-#define OP_ALG_PKMODE_SRC_REG_SHIFT 13
+#define OP_ALG_PKMODE_SRC_REG_SHIFT 17
#define OP_ALG_PKMODE_SRC_REG_MASK (7 << OP_ALG_PKMODE_SRC_REG_SHIFT)
#define OP_ALG_PKMODE_DST_REG_SHIFT 10
#define OP_ALG_PKMODE_DST_REG_MASK (7 << OP_ALG_PKMODE_DST_REG_SHIFT)
@@ -1469,7 +1454,7 @@ struct sec4_sg_entry {
#define MATH_SRC1_REG2 (0x02 << MATH_SRC1_SHIFT)
#define MATH_SRC1_REG3 (0x03 << MATH_SRC1_SHIFT)
#define MATH_SRC1_IMM (0x04 << MATH_SRC1_SHIFT)
-#define MATH_SRC1_DPOVRD (0x07 << MATH_SRC0_SHIFT)
+#define MATH_SRC1_DPOVRD (0x07 << MATH_SRC1_SHIFT)
#define MATH_SRC1_INFIFO (0x0a << MATH_SRC1_SHIFT)
#define MATH_SRC1_OUTFIFO (0x0b << MATH_SRC1_SHIFT)
#define MATH_SRC1_ONE (0x0c << MATH_SRC1_SHIFT)
diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index 9f79fd7..0d5778b 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -4,7 +4,11 @@
* Copyright 2008-2012 Freescale Semiconductor, Inc.
*/
+#ifndef DESC_CONSTR_H
+#define DESC_CONSTR_H
+
#include "desc.h"
+#include "regs.h"
#define IMMEDIATE (1 << 23)
#define CAAM_CMD_SZ sizeof(u32)
@@ -30,38 +34,39 @@
LDST_SRCDST_WORD_DECOCTRL | \
(LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
-static inline int desc_len(u32 *desc)
+static inline int desc_len(u32 * const desc)
{
- return *desc & HDR_DESCLEN_MASK;
+ return caam32_to_cpu(*desc) & HDR_DESCLEN_MASK;
}
-static inline int desc_bytes(void *desc)
+static inline int desc_bytes(void * const desc)
{
return desc_len(desc) * CAAM_CMD_SZ;
}
-static inline u32 *desc_end(u32 *desc)
+static inline u32 *desc_end(u32 * const desc)
{
return desc + desc_len(desc);
}
-static inline void *sh_desc_pdb(u32 *desc)
+static inline void *sh_desc_pdb(u32 * const desc)
{
return desc + 1;
}
-static inline void init_desc(u32 *desc, u32 options)
+static inline void init_desc(u32 * const desc, u32 options)
{
- *desc = (options | HDR_ONE) + 1;
+ *desc = cpu_to_caam32((options | HDR_ONE) + 1);
}
-static inline void init_sh_desc(u32 *desc, u32 options)
+static inline void init_sh_desc(u32 * const desc, u32 options)
{
PRINT_POS;
init_desc(desc, CMD_SHARED_DESC_HDR | options);
}
-static inline void init_sh_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
+static inline void init_sh_desc_pdb(u32 * const desc, u32 options,
+ size_t pdb_bytes)
{
u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
@@ -69,22 +74,23 @@ static inline void init_sh_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
options);
}
-static inline void init_job_desc(u32 *desc, u32 options)
+static inline void init_job_desc(u32 * const desc, u32 options)
{
init_desc(desc, CMD_DESC_HDR | options);
}
-static inline void append_ptr(u32 *desc, dma_addr_t ptr)
+static inline void append_ptr(u32 * const desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
- *offset = ptr;
+ *offset = cpu_to_caam_dma(ptr);
- (*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
+ (*desc) = cpu_to_caam32(caam32_to_cpu(*desc) +
+ CAAM_PTR_SZ / CAAM_CMD_SZ);
}
-static inline void init_job_desc_shared(u32 *desc, dma_addr_t ptr, int len,
- u32 options)
+static inline void init_job_desc_shared(u32 * const desc, dma_addr_t ptr,
+ int len, u32 options)
{
PRINT_POS;
init_job_desc(desc, HDR_SHARED | options |
@@ -92,46 +98,53 @@ static inline void init_job_desc_shared(u32 *desc, dma_addr_t ptr, int len,
append_ptr(desc, ptr);
}
-static inline void append_data(u32 *desc, void *data, int len)
+static inline void append_data(u32 * const desc, const void *data, int len)
{
u32 *offset = desc_end(desc);
if (len) /* avoid sparse warning: memcpy with byte count of 0 */
memcpy(offset, data, len);
- (*desc) += (len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
+ (*desc) = cpu_to_caam32(caam32_to_cpu(*desc) +
+ (len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ);
}
-static inline void append_cmd(u32 *desc, u32 command)
+static inline void append_cmd(u32 * const desc, u32 command)
{
u32 *cmd = desc_end(desc);
- *cmd = command;
+ *cmd = cpu_to_caam32(command);
- (*desc)++;
+ (*desc) = cpu_to_caam32(caam32_to_cpu(*desc) + 1);
}
#define append_u32 append_cmd
-static inline void append_u64(u32 *desc, u64 data)
+static inline void append_u64(u32 * const desc, u64 data)
{
u32 *offset = desc_end(desc);
- *offset = upper_32_bits(data);
- *(++offset) = lower_32_bits(data);
+ /* Only 32-bit alignment is guaranteed in descriptor buffer */
+ if (caam_little_end) {
+ *offset = cpu_to_caam32(lower_32_bits(data));
+ *(++offset) = cpu_to_caam32(upper_32_bits(data));
+ } else {
+ *offset = cpu_to_caam32(upper_32_bits(data));
+ *(++offset) = cpu_to_caam32(lower_32_bits(data));
+ }
- (*desc) += 2;
+ (*desc) = cpu_to_caam32(caam32_to_cpu(*desc) + 2);
}
/* Write command without affecting header, and return pointer to next word */
-static inline u32 *write_cmd(u32 *desc, u32 command)
+static inline u32 *write_cmd(u32 * const desc, u32 command)
{
- *desc = command;
+ *desc = cpu_to_caam32(command);
return desc + 1;
}
-static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
+static inline void append_cmd_ptr(u32 * const desc, dma_addr_t ptr, int len,
u32 command)
{
append_cmd(desc, command | len);
@@ -139,7 +152,7 @@ static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
}
/* Write length after pointer, rather than inside command */
-static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr,
+static inline void append_cmd_ptr_extlen(u32 * const desc, dma_addr_t ptr,
unsigned int len, u32 command)
{
append_cmd(desc, command);
@@ -148,7 +161,7 @@ static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr,
append_cmd(desc, len);
}
-static inline void append_cmd_data(u32 *desc, void *data, int len,
+static inline void append_cmd_data(u32 * const desc, const void *data, int len,
u32 command)
{
append_cmd(desc, command | IMMEDIATE | len);
@@ -156,7 +169,7 @@ static inline void append_cmd_data(u32 *desc, void *data, int len,
}
#define APPEND_CMD_RET(cmd, op) \
-static inline u32 *append_##cmd(u32 *desc, u32 options) \
+static inline u32 *append_##cmd(u32 * const desc, u32 options) \
{ \
u32 *cmd = desc_end(desc); \
PRINT_POS; \
@@ -166,20 +179,23 @@ static inline u32 *append_##cmd(u32 *desc, u32 options) \
APPEND_CMD_RET(jump, JUMP)
APPEND_CMD_RET(move, MOVE)
-static inline void set_jump_tgt_here(u32 *desc, u32 *jump_cmd)
+static inline void set_jump_tgt_here(u32 * const desc, u32 *jump_cmd)
{
- *jump_cmd = *jump_cmd | (desc_len(desc) - (jump_cmd - desc));
+ *jump_cmd = cpu_to_caam32(caam32_to_cpu(*jump_cmd) |
+ (desc_len(desc) - (jump_cmd - desc)));
}
-static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd)
+static inline void set_move_tgt_here(u32 * const desc, u32 *move_cmd)
{
- *move_cmd &= ~MOVE_OFFSET_MASK;
- *move_cmd = *move_cmd | ((desc_len(desc) << (MOVE_OFFSET_SHIFT + 2)) &
- MOVE_OFFSET_MASK);
+ u32 val = caam32_to_cpu(*move_cmd);
+
+ val &= ~MOVE_OFFSET_MASK;
+ val |= (desc_len(desc) << (MOVE_OFFSET_SHIFT + 2)) & MOVE_OFFSET_MASK;
+ *move_cmd = cpu_to_caam32(val);
}
#define APPEND_CMD(cmd, op) \
-static inline void append_##cmd(u32 *desc, u32 options) \
+static inline void append_##cmd(u32 * const desc, u32 options) \
{ \
PRINT_POS; \
append_cmd(desc, CMD_##op | options); \
@@ -187,7 +203,8 @@ static inline void append_##cmd(u32 *desc, u32 options) \
APPEND_CMD(operation, OPERATION)
#define APPEND_CMD_LEN(cmd, op) \
-static inline void append_##cmd(u32 *desc, unsigned int len, u32 options) \
+static inline void append_##cmd(u32 * const desc, unsigned int len, \
+ u32 options) \
{ \
PRINT_POS; \
append_cmd(desc, CMD_##op | len | options); \
@@ -199,8 +216,8 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD)
APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE)
#define APPEND_CMD_PTR(cmd, op) \
-static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \
- u32 options) \
+static inline void append_##cmd(u32 * const desc, dma_addr_t ptr, \
+ unsigned int len, u32 options) \
{ \
PRINT_POS; \
append_cmd_ptr(desc, ptr, len, CMD_##op | options); \
@@ -210,8 +227,8 @@ APPEND_CMD_PTR(load, LOAD)
APPEND_CMD_PTR(fifo_load, FIFO_LOAD)
APPEND_CMD_PTR(fifo_store, FIFO_STORE)
-static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
- u32 options)
+static inline void append_store(u32 * const desc, dma_addr_t ptr,
+ unsigned int len, u32 options)
{
u32 cmd_src;
@@ -228,7 +245,8 @@ static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
}
#define APPEND_SEQ_PTR_INTLEN(cmd, op) \
-static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \
+static inline void append_seq_##cmd##_ptr_intlen(u32 * const desc, \
+ dma_addr_t ptr, \
unsigned int len, \
u32 options) \
{ \
@@ -242,7 +260,7 @@ APPEND_SEQ_PTR_INTLEN(in, IN)
APPEND_SEQ_PTR_INTLEN(out, OUT)
#define APPEND_CMD_PTR_TO_IMM(cmd, op) \
-static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
+static inline void append_##cmd##_as_imm(u32 * const desc, const void *data, \
unsigned int len, u32 options) \
{ \
PRINT_POS; \
@@ -252,7 +270,7 @@ APPEND_CMD_PTR_TO_IMM(load, LOAD);
APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD);
#define APPEND_CMD_PTR_EXTLEN(cmd, op) \
-static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \
+static inline void append_##cmd##_extlen(u32 * const desc, dma_addr_t ptr, \
unsigned int len, u32 options) \
{ \
PRINT_POS; \
@@ -266,7 +284,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR)
* the size of its type
*/
#define APPEND_CMD_PTR_LEN(cmd, op, type) \
-static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \
+static inline void append_##cmd(u32 * const desc, dma_addr_t ptr, \
type len, u32 options) \
{ \
PRINT_POS; \
@@ -283,7 +301,7 @@ APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_PTR, u32)
* from length of immediate data provided, e.g., split keys
*/
#define APPEND_CMD_PTR_TO_IMM2(cmd, op) \
-static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
+static inline void append_##cmd##_as_imm(u32 * const desc, const void *data, \
unsigned int data_len, \
unsigned int len, u32 options) \
{ \
@@ -294,7 +312,7 @@ static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
APPEND_CMD_PTR_TO_IMM2(key, KEY);
#define APPEND_CMD_RAW_IMM(cmd, op, type) \
-static inline void append_##cmd##_imm_##type(u32 *desc, type immediate, \
+static inline void append_##cmd##_imm_##type(u32 * const desc, type immediate, \
u32 options) \
{ \
PRINT_POS; \
@@ -367,7 +385,7 @@ do { \
if (upper) \
append_u64(desc, data); \
else \
- append_u32(desc, data); \
+ append_u32(desc, lower_32_bits(data)); \
} while (0)
#define append_math_add_imm_u64(desc, dest, src0, src1, data) \
@@ -388,3 +406,5 @@ do { \
APPEND_MATH_IMM_u64(LSHIFT, desc, dest, src0, src1, data)
#define append_math_rshift_imm_u64(desc, dest, src0, src1, data) \
APPEND_MATH_IMM_u64(RSHIFT, desc, dest, src0, src1, data)
+
+#endif /* DESC_CONSTR_H */
diff --git a/drivers/crypto/caam/error.c b/drivers/crypto/caam/error.c
index 9c87537..766875b 100644
--- a/drivers/crypto/caam/error.c
+++ b/drivers/crypto/caam/error.c
@@ -150,10 +150,9 @@ static void report_ccb_status(struct device_d *jrdev, const u32 status,
strlen(rng_err_id_list[err_id])) {
/* RNG-only error */
err_str = rng_err_id_list[err_id];
- } else if (err_id < ARRAY_SIZE(err_id_list))
+ } else {
err_str = err_id_list[err_id];
- else
- snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
+ }
/*
* CCB ICV check failures are part of normal operation life;
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index 8f169d4..b602a7b 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -21,43 +21,16 @@
#include "desc.h"
#include "intern.h"
-/*
- * The DMA address registers in the JR are a pair of 32-bit registers.
- * The layout is:
- *
- * base + 0x0000 : most-significant 32 bits
- * base + 0x0004 : least-significant 32 bits
- *
- * The 32-bit version of this core therefore has to write to base + 0x0004
- * to set the 32-bit wide DMA address. This seems to be independent of the
- * endianness of the written/read data.
- */
-
-#define REG64_MS32(reg) ((u32 __iomem *)(reg))
-#define REG64_LS32(reg) ((u32 __iomem *)(reg) + 1)
-
-static inline void wr_reg64(u64 __iomem *reg, u64 data)
-{
- writel(data >> 32, REG64_MS32(reg));
- writel(data, REG64_LS32(reg));
-}
-
-static inline u64 rd_reg64(u64 __iomem *reg)
-{
- return ((u64)readl(REG64_MS32(reg)) << 32 |
- (u64)readl(REG64_LS32(reg)));
-}
-
static int caam_reset_hw_jr(struct device_d *dev)
{
struct caam_drv_private_jr *jrp = dev->priv;
uint64_t start;
/* initiate flush (required prior to reset) */
- writel(JRCR_RESET, &jrp->rregs->jrcommand);
+ wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
start = get_time_ns();
- while ((readl(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) ==
+ while ((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) ==
JRINT_ERR_HALT_INPROGRESS) {
if (is_timeout(start, 100 * MSECOND)) {
dev_err(dev, "job ring %d timed out on flush\n",
@@ -67,10 +40,10 @@ static int caam_reset_hw_jr(struct device_d *dev)
}
/* initiate reset */
- writel(JRCR_RESET, &jrp->rregs->jrcommand);
+ wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
start = get_time_ns();
- while (readl(&jrp->rregs->jrcommand) & JRCR_RESET) {
+ while (rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) {
if (is_timeout(start, 100 * MSECOND)) {
dev_err(dev, "job ring %d timed out on reset\n",
jrp->ridx);
@@ -90,7 +63,7 @@ static int caam_jr_dequeue(struct caam_drv_private_jr *jrp)
void *userarg;
int found;
- while (readl(&jrp->rregs->outring_used)) {
+ while (rd_reg32(&jrp->rregs->outring_used)) {
head = jrp->head;
sw_idx = tail = jrp->tail;
@@ -102,7 +75,7 @@ static int caam_jr_dequeue(struct caam_drv_private_jr *jrp)
sw_idx = (tail + i) & (JOBR_DEPTH - 1);
if (jrp->outring[hw_idx].desc ==
- jrp->entinfo[sw_idx].desc_addr_dma) {
+ caam_dma_to_cpu(jrp->entinfo[sw_idx].desc_addr_dma)) {
found = 1;
break; /* found */
}
@@ -120,12 +93,12 @@ static int caam_jr_dequeue(struct caam_drv_private_jr *jrp)
usercall = jrp->entinfo[sw_idx].callbk;
userarg = jrp->entinfo[sw_idx].cbkarg;
userdesc = jrp->entinfo[sw_idx].desc_addr_virt;
- userstatus = jrp->outring[hw_idx].jrstatus;
+ userstatus = caam32_to_cpu(jrp->outring[hw_idx].jrstatus);
barrier();
/* set done */
- writel(1, &jrp->rregs->outring_rmvd);
+ wr_reg32(&jrp->rregs->outring_rmvd, 1);
jrp->out_ring_read_index = (jrp->out_ring_read_index + 1) &
(JOBR_DEPTH - 1);
@@ -158,7 +131,7 @@ static int caam_jr_interrupt(struct caam_drv_private_jr *jrp)
u32 irqstate;
start = get_time_ns();
- while (!(irqstate = readl(&jrp->rregs->jrintstatus))) {
+ while (!(irqstate = rd_reg32(&jrp->rregs->jrintstatus))) {
if (is_timeout(start, 100 * MSECOND)) {
dev_err(jrp->dev, "timeout waiting for interrupt\n");
return -ETIMEDOUT;
@@ -176,7 +149,7 @@ static int caam_jr_interrupt(struct caam_drv_private_jr *jrp)
}
/* Have valid interrupt at this point, just ACK and trigger */
- writel(irqstate, &jrp->rregs->jrintstatus);
+ wr_reg32(&jrp->rregs->jrintstatus, irqstate);
return caam_jr_dequeue(jrp);
}
@@ -218,7 +191,7 @@ int caam_jr_enqueue(struct device_d *dev, u32 *desc,
struct caam_jrentry_info *head_entry;
int head, tail, desc_size;
- desc_size = (*desc & HDR_JD_LENGTH_MASK) * sizeof(u32);
+ desc_size = (caam32_to_cpu(*desc) & HDR_JD_LENGTH_MASK) * sizeof(u32);
if (!dev->priv)
return -ENODEV;
@@ -227,7 +200,7 @@ int caam_jr_enqueue(struct device_d *dev, u32 *desc,
head = jrp->head;
tail = jrp->tail;
- if (!readl(&jrp->rregs->inpring_avail) ||
+ if (!rd_reg32(&jrp->rregs->inpring_avail) ||
CIRC_SPACE(head, tail, JOBR_DEPTH) <= 0) {
return -EBUSY;
}
@@ -242,7 +215,8 @@ int caam_jr_enqueue(struct device_d *dev, u32 *desc,
if (!jrp->inpring)
return -EIO;
- jrp->inpring[jrp->inp_ring_write_index] = (dma_addr_t)desc;
+ jrp->inpring[jrp->inp_ring_write_index] =
+ cpu_to_caam_dma((dma_addr_t)desc);
barrier();
@@ -251,9 +225,9 @@ int caam_jr_enqueue(struct device_d *dev, u32 *desc,
jrp->head = (head + 1) & (JOBR_DEPTH - 1);
barrier();
- writel(1, &jrp->rregs->inpring_jobadd);
+ wr_reg32(&jrp->rregs->inpring_jobadd, 1);
- clrbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK);
+ clrsetbits_32(&jrp->rregs->rconfig_lo, JRCFG_IMSK, 0);
return caam_jr_interrupt(jrp);
}
@@ -301,8 +275,8 @@ static int caam_jr_init(struct device_d *dev)
wr_reg64(&jrp->rregs->inpring_base, dma_inpring);
wr_reg64(&jrp->rregs->outring_base, dma_outring);
- writel(JOBR_DEPTH, &jrp->rregs->inpring_size);
- writel(JOBR_DEPTH, &jrp->rregs->outring_size);
+ wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH);
+ wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH);
jrp->ringsize = JOBR_DEPTH;
@@ -335,7 +309,7 @@ int caam_jr_probe(struct device_d *dev)
if (IS_ERR(ctrl))
return PTR_ERR(ctrl);
- jrpriv->rregs = (struct caam_job_ring __force *)ctrl;
+ jrpriv->rregs = (struct caam_job_ring __iomem __force *)ctrl;
/* Now do the platform independent part */
error = caam_jr_init(dev); /* now turn on hardware */
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index b8ca5e3..6c9d6d7 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -10,9 +10,118 @@
#include <linux/types.h>
#include <io.h>
-/* These are common macros for Power, put here for ARMs */
-#define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr))
-#define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr))
+extern bool caam_little_end;
+
+#define caam_to_cpu(len) \
+static inline u##len caam##len ## _to_cpu(u##len val) \
+{ \
+ if (caam_little_end) \
+ return le##len ## _to_cpu(val); \
+ else \
+ return be##len ## _to_cpu(val); \
+}
+
+#define cpu_to_caam(len) \
+static inline u##len cpu_to_caam##len(u##len val) \
+{ \
+ if (caam_little_end) \
+ return cpu_to_le##len(val); \
+ else \
+ return cpu_to_be##len(val); \
+}
+
+caam_to_cpu(16)
+caam_to_cpu(32)
+caam_to_cpu(64)
+cpu_to_caam(16)
+cpu_to_caam(32)
+cpu_to_caam(64)
+
+static inline void wr_reg32(void __iomem *reg, u32 data)
+{
+ if (caam_little_end)
+ iowrite32(data, reg);
+ else
+ iowrite32be(data, reg);
+}
+
+static inline u32 rd_reg32(void __iomem *reg)
+{
+ if (caam_little_end)
+ return ioread32(reg);
+
+ return ioread32be(reg);
+}
+
+static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set)
+{
+ if (caam_little_end)
+ iowrite32((ioread32(reg) & ~clear) | set, reg);
+ else
+ iowrite32be((ioread32be(reg) & ~clear) | set, reg);
+}
+
+/*
+ * The DMA address registers in the JR are a pair of 32-bit registers.
+ * The layout is:
+ *
+ * base + 0x0000 : most-significant 32 bits
+ * base + 0x0004 : least-significant 32 bits
+ *
+ * The 32-bit version of this core therefore has to write to base + 0x0004
+ * to set the 32-bit wide DMA address. This seems to be independent of the
+ * endianness of the written/read data.
+ */
+
+#ifdef CONFIG_64BIT
+static inline void wr_reg64(void __iomem *reg, u64 data)
+{
+ if (caam_little_end)
+ iowrite64(data, reg);
+ else
+ iowrite64be(data, reg);
+}
+
+static inline void rd_reg64(void __iomem *reg)
+{
+ if (caam_little_end)
+ ioread64(reg);
+ else
+ ioread64be(reg);
+}
+#else /* CONFIG_64BIT */
+static inline void wr_reg64(void __iomem *reg, u64 data)
+{
+ wr_reg32((u32 __iomem *)(reg), data >> 32);
+ wr_reg32((u32 __iomem *)(reg) + 1, data);
+}
+
+static inline u64 rd_reg64(void __iomem *reg)
+{
+ return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
+ (u64)rd_reg32((u32 __iomem *)(reg) + 1));
+}
+#endif /* CONFIG_64BIT */
+
+static inline u64 cpu_to_caam_dma64(dma_addr_t value)
+{
+ return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) |
+ (u64)cpu_to_caam32(upper_32_bits(value)));
+}
+
+static inline u64 caam_dma64_to_cpu(u64 value)
+{
+ return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) |
+ (u64)caam32_to_cpu(upper_32_bits(value)));
+}
+
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+#define cpu_to_caam_dma(value) cpu_to_caam_dma64(value)
+#define caam_dma_to_cpu(value) caam_dma64_to_cpu(value)
+#else
+#define cpu_to_caam_dma(value) cpu_to_caam32(value)
+#define caam_dma_to_cpu(value) caam32_to_cpu(value)
+#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
/*
* jr_outentry
@@ -190,17 +299,25 @@ struct caam_perfmon {
u32 faultliodn; /* FALR - Fault Address LIODN */
u32 faultdetail; /* FADR - Fault Addr Detail */
u32 rsvd3;
+#define CSTA_PLEND BIT(10)
+#define CSTA_ALT_PLEND BIT(18)
u32 status; /* CSTA - CAAM Status */
u32 smpart; /* Secure Memory Partition Parameters */
u32 smvid; /* Secure Memory Version ID */
/* Component Instantiation Parameters fe0-fff */
u32 rtic_id; /* RVID - RTIC Version ID */
+#define CCBVID_ERA_MASK 0xff000000
+#define CCBVID_ERA_SHIFT 24
u32 ccb_id; /* CCBVID - CCB Version ID */
u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/
u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/
u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */
u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/
+#define SECVID_MS_IPID_MASK 0xffff0000
+#define SECVID_MS_IPID_SHIFT 16
+#define SECVID_MS_MAJ_REV_MASK 0x0000ff00
+#define SECVID_MS_MAJ_REV_SHIFT 8
u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */
u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */
};
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index 3c95230..53e8c76 100644
--- a/drivers/gpio/gpio-pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -468,9 +468,44 @@ static int pca953x_probe(struct device_d *dev)
return 0;
}
+/* convenience to stop overlong match-table lines */
+#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
+#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
+
+static const struct of_device_id pca953x_dt_ids[] = {
+ { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
+ { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
+ { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
+ { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
+ { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
+ { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
+ { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
+ { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
+ { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
+ { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
+ { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
+ { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
+ { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
+ { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
+
+ { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
+ { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
+ { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
+ { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
+
+ { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
+ { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
+ { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
+ { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
+
+ { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
+ { }
+};
+
static struct driver_d pca953x_driver = {
.name = "pca953x",
.probe = pca953x_probe,
+ .of_compatible = DRV_OF_COMPAT(pca953x_dt_ids),
.id_table = pca953x_id,
};
diff --git a/drivers/hab/hab.c b/drivers/hab/hab.c
index 0d71f5b..03bb65e 100644
--- a/drivers/hab/hab.c
+++ b/drivers/hab/hab.c
@@ -161,6 +161,12 @@ static int imx_hab_permanent_write_enable_ocotp(int enable)
static int imx_hab_lockdown_device_ocotp(void)
{
+ int ret;
+
+ ret = imx_ocotp_write_field(OCOTP_DIR_BT_DIS, 1);
+ if (ret < 0)
+ return ret;
+
return imx_ocotp_write_field(OCOTP_SEC_CONFIG_1, 1);
}
diff --git a/drivers/hab/habv4.c b/drivers/hab/habv4.c
index ae43bdf..28fd42e 100644
--- a/drivers/hab/habv4.c
+++ b/drivers/hab/habv4.c
@@ -27,13 +27,28 @@
#define HABV4_RVT_IMX28 0xffff8af8
#define HABV4_RVT_IMX6_OLD 0x00000094
#define HABV4_RVT_IMX6_NEW 0x00000098
-#define HABV4_RVT_IMX6UL 0x00000100
+#define HABV4_RVT_IMX6UL 0x00000100
+
+struct __packed hab_hdr {
+ uint8_t tag; /* Tag field */
+ __be16 len; /* Length field in bytes (big-endian) */
+ uint8_t par; /* Parameters field */
+};
+
+struct __packed hab_event_record {
+ struct hab_hdr hdr;
+ uint8_t status; /* Status -> enum hab_status*/
+ uint8_t reason; /* Reason -> enum hab_reason */
+ uint8_t context; /* Context -> enum hab_context */
+ uint8_t engine; /* Engine -> enum hab_engine */
+ uint8_t data[0]; /* Record Data */
+};
enum hab_tag {
HAB_TAG_IVT = 0xd1, /* Image Vector Table */
HAB_TAG_DCD = 0xd2, /* Device Configuration Data */
HAB_TAG_CSF = 0xd4, /* Command Sequence File */
- HAB_TAG_CRT = 0xd7, /* Certificate */
+ HAB_TAG_CRT = 0xd7, /* Certificate */
HAB_TAG_SIG = 0xd8, /* Signature */
HAB_TAG_EVT = 0xdb, /* Event */
HAB_TAG_RVT = 0xdd, /* ROM Vector Table */
@@ -69,6 +84,66 @@ enum hab_state {
HAB_STATE_NONE = 0xf0, /* No security state machine */
};
+enum hab_reason {
+ HAB_REASON_RSN_ANY = 0x00, /* Match any reason */
+ HAB_REASON_UNS_COMMAND = 0x03, /* Unsupported command */
+ HAB_REASON_INV_IVT = 0x05, /* Invalid ivt */
+ HAB_REASON_INV_COMMAND = 0x06, /* Invalid command: command malformed */
+ HAB_REASON_UNS_STATE = 0x09, /* Unsuitable state */
+ HAB_REASON_UNS_ENGINE = 0x0a, /* Unsupported engine */
+ HAB_REASON_INV_ASSERTION = 0x0c, /* Invalid assertion */
+ HAB_REASON_INV_INDEX = 0x0f, /* Invalid index: access denied */
+ HAB_REASON_INV_CSF = 0x11, /* Invalid csf */
+ HAB_REASON_UNS_ALGORITHM = 0x12, /* Unsupported algorithm */
+ HAB_REASON_UNS_PROTOCOL = 0x14, /* Unsupported protocol */
+ HAB_REASON_INV_SIZE = 0x17, /* Invalid data size */
+ HAB_REASON_INV_SIGNATURE = 0x18, /* Invalid signature */
+ HAB_REASON_UNS_KEY = 0x1b, /* Unsupported key type/parameters */
+ HAB_REASON_INV_KEY = 0x1d, /* Invalid key */
+ HAB_REASON_INV_RETURN = 0x1e, /* Failed callback function */
+ HAB_REASON_INV_CERTIFICATE = 0x21, /* Invalid certificate */
+ HAB_REASON_INV_ADDRESS = 0x22, /* Invalid address: access denied */
+ HAB_REASON_UNS_ITEM = 0x24, /* Unsupported configuration item */
+ HAB_REASON_INV_DCD = 0x27, /* Invalid dcd */
+ HAB_REASON_INV_CALL = 0x28, /* Function called out of sequence */
+ HAB_REASON_OVR_COUNT = 0x2b, /* Expired poll count */
+ HAB_REASON_OVR_STORAGE = 0x2d, /* Exhausted storage region */
+ HAB_REASON_MEM_FAIL = 0x2e, /* Memory failure */
+ HAB_REASON_ENG_FAIL = 0x30, /* Engine failure */
+};
+
+enum hab_context {
+ HAB_CONTEXT_ANY = 0x00, /* Match any context */
+ HAB_CONTEXT_AUTHENTICATE = 0x0a, /* Logged in hab_rvt.authenticate_image() */
+ HAB_CONTEXT_TARGET = 0x33, /* Event logged in hab_rvt.check_target() */
+ HAB_CONTEXT_ASSERT = 0xa0, /* Event logged in hab_rvt.assert() */
+ HAB_CONTEXT_COMMAND = 0xc0, /* Event logged executing csf/dcd command */
+ HAB_CONTEXT_CSF = 0xcf, /* Event logged in hab_rvt.run_csf() */
+ HAB_CONTEXT_AUT_DAT = 0xdb, /* Authenticated data block */
+ HAB_CONTEXT_DCD = 0xdd, /* Event logged in hab_rvt.run_dcd() */
+ HAB_CONTEXT_ENTRY = 0xe1, /* Event logged in hab_rvt.entry() */
+ HAB_CONTEXT_EXIT = 0xee, /* Event logged in hab_rvt.exit() */
+ HAB_CONTEXT_FAB = 0xff, /* Event logged in hab_fab_test() */
+};
+
+enum hab_engine {
+ HAB_ENGINE_ANY = 0x00, /* Select first compatible engine */
+ HAB_ENGINE_SCC = 0x03, /* Security controller */
+ HAB_ENGINE_RTIC = 0x05, /* Run-time integrity checker */
+ HAB_ENGINE_SAHARA = 0x06, /* Crypto accelerator */
+ HAB_ENGINE_CSU = 0x0a, /* Central Security Unit */
+ HAB_ENGINE_SRTC = 0x0c, /* Secure clock */
+ HAB_ENGINE_DCP = 0x1b, /* Data Co-Processor */
+ HAB_ENGINE_CAAM = 0x1d, /* CAAM */
+ HAB_ENGINE_SNVS = 0x1e, /* Secure Non-Volatile Storage */
+ HAB_ENGINE_OCOTP = 0x21, /* Fuse controller */
+ HAB_ENGINE_DTCP = 0x22, /* DTCP co-processor */
+ HAB_ENGINE_HDCP = 0x24, /* HDCP co-processor */
+ HAB_ENGINE_ROM = 0x36, /* Protected ROM area */
+ HAB_ENGINE_RTL = 0x77, /* RTL simulation engine */
+ HAB_ENGINE_SW = 0xff, /* Software engine */
+};
+
enum hab_target {
HAB_TARGET_MEMORY = 0x0f, /* Check memory white list */
HAB_TARGET_PERIPHERAL = 0xf0, /* Check peripheral white list*/
@@ -157,29 +232,165 @@ static const char *habv4_get_state_str(enum hab_state state)
return "<unknown>";
}
+static const char *habv4_get_reason_str(enum hab_reason reason)
+{
+ switch (reason) {
+ case HAB_REASON_RSN_ANY:
+ return "Match any reason"; break;
+ case HAB_REASON_UNS_COMMAND:
+ return "Unsupported command"; break;
+ case HAB_REASON_INV_IVT:
+ return "Invalid ivt"; break;
+ case HAB_REASON_INV_COMMAND:
+ return "Invalid command: command malformed"; break;
+ case HAB_REASON_UNS_STATE:
+ return "Unsuitable state"; break;
+ case HAB_REASON_UNS_ENGINE:
+ return "Unsupported engine"; break;
+ case HAB_REASON_INV_ASSERTION:
+ return "Invalid assertion"; break;
+ case HAB_REASON_INV_INDEX:
+ return "Invalid index: access denied"; break;
+ case HAB_REASON_INV_CSF:
+ return "Invalid csf"; break;
+ case HAB_REASON_UNS_ALGORITHM:
+ return "Unsupported algorithm"; break;
+ case HAB_REASON_UNS_PROTOCOL:
+ return "Unsupported protocol"; break;
+ case HAB_REASON_INV_SIZE:
+ return "Invalid data size"; break;
+ case HAB_REASON_INV_SIGNATURE:
+ return "Invalid signature"; break;
+ case HAB_REASON_UNS_KEY:
+ return "Unsupported key type/parameters"; break;
+ case HAB_REASON_INV_KEY:
+ return "Invalid key"; break;
+ case HAB_REASON_INV_RETURN:
+ return "Failed callback function"; break;
+ case HAB_REASON_INV_CERTIFICATE:
+ return "Invalid certificate"; break;
+ case HAB_REASON_INV_ADDRESS:
+ return "Invalid address: access denied"; break;
+ case HAB_REASON_UNS_ITEM:
+ return "Unsupported configuration item"; break;
+ case HAB_REASON_INV_DCD:
+ return "Invalid dcd"; break;
+ case HAB_REASON_INV_CALL:
+ return "Function called out of sequence"; break;
+ case HAB_REASON_OVR_COUNT:
+ return "Expired poll count"; break;
+ case HAB_REASON_OVR_STORAGE:
+ return "Exhausted storage region"; break;
+ case HAB_REASON_MEM_FAIL:
+ return "Memory failure"; break;
+ case HAB_REASON_ENG_FAIL:
+ return "Engine failure"; break;
+ }
+
+ return "<unknown>";
+}
+
+static const char *habv4_get_context_str(enum hab_context context)
+{
+ switch (context){
+ case HAB_CONTEXT_ANY:
+ return "Match any context"; break;
+ case HAB_CONTEXT_AUTHENTICATE:
+ return "Logged in hab_rvt.authenticate_image()"; break;
+ case HAB_CONTEXT_TARGET:
+ return "Event logged in hab_rvt.check_target()"; break;
+ case HAB_CONTEXT_ASSERT:
+ return "Event logged in hab_rvt.assert()"; break;
+ case HAB_CONTEXT_COMMAND:
+ return "Event logged executing csf/dcd command"; break;
+ case HAB_CONTEXT_CSF:
+ return "Event logged in hab_rvt.run_csf()"; break;
+ case HAB_CONTEXT_AUT_DAT:
+ return "Authenticated data block"; break;
+ case HAB_CONTEXT_DCD:
+ return "Event logged in hab_rvt.run_dcd()"; break;
+ case HAB_CONTEXT_ENTRY:
+ return "Event logged in hab_rvt.entry()"; break;
+ case HAB_CONTEXT_EXIT:
+ return "Event logged in hab_rvt.exit()"; break;
+ case HAB_CONTEXT_FAB:
+ return "Event logged in hab_fab_test()"; break;
+ }
+
+ return "<unknown>";
+}
+
+static const char *habv4_get_engine_str(enum hab_engine engine)
+{
+ switch (engine){
+ case HAB_ENGINE_ANY:
+ return "Select first compatible engine"; break;
+ case HAB_ENGINE_SCC:
+ return "Security controller"; break;
+ case HAB_ENGINE_RTIC:
+ return "Run-time integrity checker"; break;
+ case HAB_ENGINE_SAHARA:
+ return "Crypto accelerator"; break;
+ case HAB_ENGINE_CSU:
+ return "Central Security Unit"; break;
+ case HAB_ENGINE_SRTC:
+ return "Secure clock"; break;
+ case HAB_ENGINE_DCP:
+ return "Data Co-Processor"; break;
+ case HAB_ENGINE_CAAM:
+ return "CAAM"; break;
+ case HAB_ENGINE_SNVS:
+ return "Secure Non-Volatile Storage"; break;
+ case HAB_ENGINE_OCOTP:
+ return "Fuse controller"; break;
+ case HAB_ENGINE_DTCP:
+ return "DTCP co-processor"; break;
+ case HAB_ENGINE_HDCP:
+ return "HDCP co-processor"; break;
+ case HAB_ENGINE_ROM:
+ return "Protected ROM area"; break;
+ case HAB_ENGINE_RTL:
+ return "RTL simulation engine"; break;
+ case HAB_ENGINE_SW:
+ return "Software engine"; break;
+ }
+
+ return "<unknown>";
+}
+
+static void habv4_display_event_record(struct hab_event_record *record)
+{
+ pr_err("Status: %s (0x%02x)\n", habv4_get_status_str(record->status), record->status);
+ pr_err("Reason: %s (0x%02x)\n", habv4_get_reason_str(record->reason), record->reason);
+ pr_err("Context: %s (0x%02x)\n", habv4_get_context_str(record->context), record->context);
+ pr_err("Engine: %s (0x%02x)\n", habv4_get_engine_str(record->engine), record->engine);
+}
+
static void habv4_display_event(uint8_t *data, uint32_t len)
{
unsigned int i;
if (data && len) {
for (i = 0; i < len; i++) {
- if (i == 0)
- printf(" %02x", data[i]);
- else if ((i % 8) == 0)
- printf("\n %02x", data[i]);
+ if ((i % 8) == 0)
+ pr_err(" %02x", data[i]);
else if ((i % 4) == 0)
- printf(" %02x", data[i]);
+ pr_cont(" %02x", data[i]);
+ else if ((i % 8) == 7)
+ pr_cont(" %02x\n", data[i]);
else
- printf(" %02x", data[i]);
+ pr_cont(" %02x", data[i]);
}
+ pr_cont("\n");
}
- printf("\n\n");
+
+ habv4_display_event_record((struct hab_event_record *)data);
}
static int habv4_get_status(const struct habv4_rvt *rvt)
{
uint8_t data[256];
- uint32_t len = sizeof(data);
+ uint32_t len;
uint32_t index = 0;
enum hab_status status;
enum hab_config config = 0x0;
@@ -200,9 +411,20 @@ static int habv4_get_status(const struct habv4_rvt *rvt)
return 0;
}
+ len = sizeof(data);
+ while (rvt->report_event(HAB_STATUS_WARNING, index, data, &len) == HAB_STATUS_SUCCESS) {
+ pr_err("-------- HAB warning Event %d --------\n", index);
+ pr_err("event data:\n");
+
+ habv4_display_event(data, len);
+ len = sizeof(data);
+ index++;
+ }
+
+ len = sizeof(data);
while (rvt->report_event(HAB_STATUS_FAILURE, index, data, &len) == HAB_STATUS_SUCCESS) {
- printf("-------- HAB Event %d --------\n"
- "event data:\n", index);
+ pr_err("-------- HAB failure Event %d --------\n", index);
+ pr_err("event data:\n");
habv4_display_event(data, len);
len = sizeof(data);
@@ -210,6 +432,7 @@ static int habv4_get_status(const struct habv4_rvt *rvt)
}
/* Check reason for stopping */
+ len = sizeof(data);
if (rvt->report_event(HAB_STATUS_ANY, index, NULL, &len) == HAB_STATUS_SUCCESS)
pr_err("ERROR: Recompile with larger event data buffer (at least %d bytes)\n\n", len);
diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig
index 50f0d8f..2a5920a 100644
--- a/drivers/led/Kconfig
+++ b/drivers/led/Kconfig
@@ -31,4 +31,13 @@ config LED_TRIGGERS
This allows to assign certain triggers like heartbeat or network
activity to LEDs.
+config LED_PCA955X
+ bool "LED Support for PCA955x I2C chips"
+ depends on I2C
+ help
+ This option enables support for LEDs connected to PCA955x
+ LED driver chips accessed via the I2C bus. Supported
+ devices include PCA9550, PCA9551, PCA9552, and PCA9553.
+
+
endif
diff --git a/drivers/led/Makefile b/drivers/led/Makefile
index 619bbcf..35693a7 100644
--- a/drivers/led/Makefile
+++ b/drivers/led/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_LED) += core.o
obj-$(CONFIG_LED_GPIO) += led-gpio.o
obj-$(CONFIG_LED_PWM) += led-pwm.o
obj-$(CONFIG_LED_TRIGGERS) += led-triggers.o
+obj-$(CONFIG_LED_PCA955X) += led-pca955x.o
diff --git a/drivers/led/core.c b/drivers/led/core.c
index 6f66de0..a388e6b 100644
--- a/drivers/led/core.c
+++ b/drivers/led/core.c
@@ -127,7 +127,7 @@ static void led_blink_func(struct poller_struct *poller)
struct led *led;
list_for_each_entry(led, &leds, list) {
- bool on;
+ int on;
if (!led->blink && !led->flash)
continue;
@@ -137,6 +137,8 @@ static void led_blink_func(struct poller_struct *poller)
}
on = !(led->blink_next_state % 2);
+ if (on)
+ on = led->max_value;
led->blink_next_event = get_time_ns() +
(led->blink_states[led->blink_next_state] * MSECOND);
diff --git a/drivers/led/led-pca955x.c b/drivers/led/led-pca955x.c
new file mode 100644
index 0000000..9c4f796
--- /dev/null
+++ b/drivers/led/led-pca955x.c
@@ -0,0 +1,421 @@
+/*
+ * Copyright 2007-2008 Extreme Engineering Solutions, Inc.
+ * Author: Nate Case <ncase@xes-inc.com>
+ *
+ * Copyright (C) 2018 WAGO Kontakttechnik GmbH & Co. KG <http://global.wago.com>
+ * Author: Oleg Karfich <oleg.karfich@wago.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * This code was ported from linux-4.18 kernel driver.
+ * Orginal code with it's copyright info can be found in
+ * drivers/leds/leds-pca955x.c
+ *
+ * LED driver for various PCA955x I2C LED drivers
+ *
+ * Supported devices:
+ *
+ * Device Description 7-bit slave address
+ * ------ ----------- -------------------
+ * PCA9550 2-bit driver 0x60 .. 0x61
+ * PCA9551 8-bit driver 0x60 .. 0x67
+ * PCA9552 16-bit driver 0x60 .. 0x67
+ * PCA9553/01 4-bit driver 0x62
+ * PCA9553/02 4-bit driver 0x63
+ *
+ * Philips PCA955x LED driver chips follow a register map as shown below:
+ *
+ * Control Register Description
+ * ---------------- -----------
+ * 0x0 Input register 0
+ * ..
+ * NUM_INPUT_REGS - 1 Last Input register X
+ *
+ * NUM_INPUT_REGS Frequency prescaler 0
+ * NUM_INPUT_REGS + 1 PWM register 0
+ * NUM_INPUT_REGS + 2 Frequency prescaler 1
+ * NUM_INPUT_REGS + 3 PWM register 1
+ *
+ * NUM_INPUT_REGS + 4 LED selector 0
+ * NUM_INPUT_REGS + 4
+ * + NUM_LED_REGS - 1 Last LED selector
+ *
+ * where NUM_INPUT_REGS and NUM_LED_REGS vary depending on how many
+ * bits the chip supports.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <led.h>
+#include <malloc.h>
+#include <i2c/i2c.h>
+#include <of_device.h>
+
+/* LED select registers determine the source that drives LED outputs */
+#define PCA955X_LS_LED_ON 0x0 /* Output LOW */
+#define PCA955X_LS_LED_OFF 0x1 /* Output HI-Z */
+#define PCA955X_LS_BLINK0 0x2 /* Blink at PWM0 rate */
+#define PCA955X_LS_BLINK1 0x3 /* Blink at PWM1 rate */
+
+enum led_brightness {
+ LED_OFF = 0,
+ LED_HALF = 127,
+ LED_FULL = 255,
+};
+
+enum pca955x_type {
+ pca9550,
+ pca9551,
+ pca9552,
+ pca9553,
+};
+
+struct pca955x_chipdef {
+ int bits;
+ u8 slv_addr; /* 7-bit slave address mask */
+ int slv_addr_shift; /* Number of bits to ignore */
+};
+
+static struct pca955x_chipdef pca955x_chipdefs[] = {
+ [pca9550] = {
+ .bits = 2,
+ .slv_addr = /* 110000x */ 0x60,
+ .slv_addr_shift = 1,
+ },
+ [pca9551] = {
+ .bits = 8,
+ .slv_addr = /* 1100xxx */ 0x60,
+ .slv_addr_shift = 3,
+ },
+ [pca9552] = {
+ .bits = 16,
+ .slv_addr = /* 1100xxx */ 0x60,
+ .slv_addr_shift = 3,
+ },
+ [pca9553] = {
+ .bits = 4,
+ .slv_addr = /* 110001x */ 0x62,
+ .slv_addr_shift = 1,
+ },
+};
+
+static const struct platform_device_id led_pca955x_id[] = {
+ { "pca9550", pca9550 },
+ { "pca9551", pca9551 },
+ { "pca9552", pca9552 },
+ { "pca9553", pca9553 },
+ { }
+};
+
+struct pca955x {
+ struct pca955x_led *leds;
+ struct pca955x_chipdef *chipdef;
+ struct i2c_client *client;
+};
+
+struct pca955x_led {
+ struct pca955x *pca955x;
+ struct led led_cdev;
+ int led_num; /* 0 .. 15 potentially */
+ char name[32];
+};
+
+struct pca955x_platform_data {
+ struct pca955x_led *leds;
+ int num_leds;
+};
+
+/* 8 bits per input register */
+static inline int pca95xx_num_input_regs(int bits)
+{
+ return (bits + 7) / 8;
+}
+
+/*
+ * Return an LED selector register value based on an existing one, with
+ * the appropriate 2-bit state value set for the given LED number (0-3).
+ */
+static inline u8 pca955x_ledsel(u8 oldval, int led_num, int state)
+{
+ return (oldval & (~(0x3 << (led_num << 1)))) |
+ ((state & 0x3) << (led_num << 1));
+}
+
+/*
+ * Write to frequency prescaler register, used to program the
+ * period of the PWM output. period = (PSCx + 1) / 38
+ */
+static int pca955x_write_psc(struct i2c_client *client, int n, u8 val)
+{
+ struct pca955x *pca955x = i2c_get_clientdata(client);
+ int ret;
+
+ ret = i2c_smbus_write_byte_data(client,
+ pca95xx_num_input_regs(pca955x->chipdef->bits) + 2*n,
+ val);
+ if (ret < 0)
+ dev_err(&client->dev, "%s: reg 0x%x, val 0x%x, err %d\n",
+ __func__, n, val, ret);
+ return ret;
+}
+
+/*
+ * Write to PWM register, which determines the duty cycle of the
+ * output. LED is OFF when the count is less than the value of this
+ * register, and ON when it is greater. If PWMx == 0, LED is always OFF.
+ *
+ * Duty cycle is (256 - PWMx) / 256
+ */
+static int pca955x_write_pwm(struct i2c_client *client, int n, u8 val)
+{
+ struct pca955x *pca955x = i2c_get_clientdata(client);
+ int ret;
+
+ ret = i2c_smbus_write_byte_data(client,
+ pca95xx_num_input_regs(pca955x->chipdef->bits) + 1 + 2*n,
+ val);
+ if (ret < 0)
+ dev_err(&client->dev, "%s: reg 0x%x, val 0x%x, err %d\n",
+ __func__, n, val, ret);
+ return ret;
+}
+
+/*
+ * Write to LED selector register, which determines the source that
+ * drives the LED output.
+ */
+static int pca955x_write_ls(struct i2c_client *client, int n, u8 val)
+{
+ struct pca955x *pca955x = i2c_get_clientdata(client);
+ int ret;
+
+ ret = i2c_smbus_write_byte_data(client,
+ pca95xx_num_input_regs(pca955x->chipdef->bits) + 4 + n,
+ val);
+ if (ret < 0)
+ dev_err(&client->dev, "%s: reg 0x%x, val 0x%x, err %d\n",
+ __func__, n, val, ret);
+ return ret;
+}
+
+/*
+ * Read the LED selector register, which determines the source that
+ * drives the LED output.
+ */
+static int pca955x_read_ls(struct i2c_client *client, int n, u8 *val)
+{
+ struct pca955x *pca955x = i2c_get_clientdata(client);
+ int ret;
+
+ ret = i2c_smbus_read_byte_data(client,
+ pca95xx_num_input_regs(pca955x->chipdef->bits) + 4 + n);
+ if (ret < 0) {
+ dev_err(&client->dev, "%s: reg 0x%x, err %d\n",
+ __func__, n, ret);
+ return ret;
+ }
+ *val = (u8)ret;
+ return 0;
+}
+
+static void pca955x_led_set(struct led *led_cdev, unsigned int value)
+{
+ struct pca955x_led *pca955x_led;
+ struct pca955x *pca955x;
+ u8 ls;
+ int chip_ls; /* which LSx to use (0-3 potentially) */
+ int ls_led; /* which set of bits within LSx to use (0-3) */
+ int ret;
+
+ pca955x_led = container_of(led_cdev, struct pca955x_led, led_cdev);
+ pca955x = pca955x_led->pca955x;
+
+ chip_ls = pca955x_led->led_num / 4;
+ ls_led = pca955x_led->led_num % 4;
+
+ ret = pca955x_read_ls(pca955x->client, chip_ls, &ls);
+ if (ret)
+ return;
+
+ switch (value) {
+ case LED_FULL:
+ ls = pca955x_ledsel(ls, ls_led, PCA955X_LS_LED_ON);
+ break;
+ case LED_OFF:
+ ls = pca955x_ledsel(ls, ls_led, PCA955X_LS_LED_OFF);
+ break;
+ case LED_HALF:
+ ls = pca955x_ledsel(ls, ls_led, PCA955X_LS_BLINK0);
+ break;
+ default:
+ /*
+ * Use PWM1 for all other values. This has the unwanted
+ * side effect of making all LEDs on the chip share the
+ * same brightness level if set to a value other than
+ * OFF, HALF, or FULL. But, this is probably better than
+ * just turning off for all other values.
+ */
+ ret = pca955x_write_pwm(pca955x->client, 1, 255 - value);
+ if (ret)
+ return;
+ ls = pca955x_ledsel(ls, ls_led, PCA955X_LS_BLINK1);
+ break;
+ }
+
+ pca955x_write_ls(pca955x->client, chip_ls, ls);
+}
+
+static struct pca955x_platform_data *
+led_pca955x_pdata_of_init(struct device_node *np, struct pca955x *pca955x)
+{
+ struct device_node *child;
+ struct pca955x_chipdef *chip = pca955x->chipdef;
+ struct pca955x_platform_data *pdata;
+ int count, err;
+
+ count = of_get_child_count(np);
+ if (!count || count > chip->bits)
+ return ERR_PTR(-ENODEV);
+
+ pdata = xzalloc(sizeof(*pdata));
+ if (!pdata)
+ return ERR_PTR(-ENOMEM);
+
+ pdata->leds = xzalloc(chip->bits * sizeof(struct pca955x_led));
+ if (!pdata->leds)
+ return ERR_PTR(-ENOMEM);
+
+ for_each_child_of_node(np, child) {
+ struct pca955x_led *pca955x_led;
+ const char *name;
+ u32 reg;
+ int res;
+
+ res = of_property_read_u32(child, "reg", &reg);
+ if ((res != 0) || (reg >= chip->bits))
+ continue;
+
+ pca955x_led = &pdata->leds[reg];
+ pca955x_led->led_num = reg;
+ pca955x_led->pca955x = pca955x;
+
+ if (of_property_read_string(child, "label", &name))
+ name = child->name;
+
+ snprintf(pca955x_led->name, sizeof(pca955x_led->name),
+ "%s", name);
+
+ pca955x_led->led_cdev.name = pca955x_led->name;
+ pca955x_led->led_cdev.set = pca955x_led_set;
+ pca955x_led->led_cdev.num = pca955x_led->led_num;
+ pca955x_led->led_cdev.max_value = 255;
+
+ err = led_register(&pca955x_led->led_cdev);
+ if (err)
+ return ERR_PTR(err);
+
+ /* Turn off LED */
+ pca955x_led_set(&pca955x_led->led_cdev, LED_OFF);
+
+ led_of_parse_trigger(&pca955x_led->led_cdev, child);
+ }
+
+ pdata->num_leds = count;
+
+ return pdata;
+}
+
+static const struct of_device_id of_pca955x_match[] = {
+ { .compatible = "nxp,pca9550", .data = (void *)pca9550 },
+ { .compatible = "nxp,pca9551", .data = (void *)pca9551 },
+ { .compatible = "nxp,pca9552", .data = (void *)pca9552 },
+ { .compatible = "nxp,pca9553", .data = (void *)pca9553 },
+ {},
+};
+
+static int led_pca955x_probe(struct device_d *dev)
+{
+ struct pca955x *pca955x;
+ struct pca955x_led *pca955x_led;
+ struct pca955x_chipdef *chip;
+ struct i2c_client *client;
+ int err;
+ struct pca955x_platform_data *pdata;
+
+ chip = &pca955x_chipdefs[dev->id_entry->driver_data];
+ client = to_i2c_client(dev);
+
+ /* Make sure the slave address / chip type combo given is possible */
+ if ((client->addr & ~((1 << chip->slv_addr_shift) - 1)) !=
+ chip->slv_addr) {
+ dev_err(dev, "invalid slave address %02x\n", client->addr);
+ return -ENODEV;
+ }
+
+ dev_info(dev, "leds-pca955x: Using %s %d-bit LED driver at "
+ "slave address 0x%02x\n",
+ client->dev.name, chip->bits, client->addr);
+
+ pca955x = xzalloc(sizeof(*pca955x));
+ if (!pca955x)
+ return -ENOMEM;
+
+ pca955x->leds = xzalloc(chip->bits * sizeof(*pca955x_led));
+ if (!pca955x->leds)
+ return -ENOMEM;
+
+ i2c_set_clientdata(client, pca955x);
+
+ pca955x->client = client;
+ pca955x->chipdef = chip;
+
+ pdata = led_pca955x_pdata_of_init(dev->device_node, pca955x);
+ if (IS_ERR(pdata))
+ return PTR_ERR(pdata);
+
+ if (pdata->num_leds != chip->bits)
+ dev_warn(dev, "board info claims %d LEDs on a %d-bit chip\n",
+ pdata->num_leds, chip->bits);
+
+ /* PWM0 is used for half brightness or 50% duty cycle */
+ err = pca955x_write_pwm(client, 0, 255 - LED_HALF);
+ if (err)
+ return err;
+
+ /* PWM1 is used for variable brightness, default to OFF */
+ err = pca955x_write_pwm(client, 1, 0);
+ if (err)
+ return err;
+
+ /* Set to fast frequency so we do not see flashing */
+ err = pca955x_write_psc(client, 0, 0);
+ if (err)
+ return err;
+ err = pca955x_write_psc(client, 1, 0);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static struct driver_d led_pca955x_driver = {
+ .name = "led-pca955x",
+ .probe = led_pca955x_probe,
+ .id_table = led_pca955x_id,
+ .of_compatible = DRV_OF_COMPAT(of_pca955x_match),
+};
+
+static int __init led_pca955x_init(void)
+{
+ return i2c_driver_register(&led_pca955x_driver);
+}
+device_initcall(led_pca955x_init);
diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index db96a81..7f22856 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -303,7 +303,7 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
dma = dma_map_single(host->dev, ptr, num_bytes, dir);
if (dma_mapping_error(host->dev, dma))
- return -EIO;
+ return -EFAULT;
}
err = esdhc_setup_data(mci, data, dma);
@@ -629,6 +629,8 @@ static int fsl_esdhc_probe(struct device_d *dev)
host->socdata = &esdhc_imx25_data;
}
+ dma_set_mask(dev, DMA_BIT_MASK(32));
+
host->clk = clk_get(dev, "per");
if (IS_ERR(host->clk))
return PTR_ERR(host->clk);
diff --git a/drivers/mfd/rave-sp.c b/drivers/mfd/rave-sp.c
index d55e913..469ce4c 100644
--- a/drivers/mfd/rave-sp.c
+++ b/drivers/mfd/rave-sp.c
@@ -57,16 +57,6 @@
#define RAVE_SP_TX_BUFFER_SIZE \
(RAVE_SP_STX_ETX_SIZE + 2 * RAVE_SP_RX_BUFFER_SIZE)
-#define RAVE_SP_BOOT_SOURCE_GET 0
-#define RAVE_SP_BOOT_SOURCE_SET 1
-
-#define RAVE_SP_RDU2_BOARD_TYPE_RMB 0
-#define RAVE_SP_RDU2_BOARD_TYPE_DEB 1
-
-#define RAVE_SP_BOOT_SOURCE_SD 0
-#define RAVE_SP_BOOT_SOURCE_EMMC 1
-#define RAVE_SP_BOOT_SOURCE_NOR 2
-
/**
* enum rave_sp_deframer_state - Possible state for de-framer
*
@@ -122,13 +112,46 @@ struct rave_sp_checksum {
void (*subroutine)(const u8 *, size_t, u8 *);
};
+struct rave_sp_version {
+ u8 hardware;
+ __le16 major;
+ u8 minor;
+ u8 letter[2];
+} __packed;
+
+struct rave_sp_status {
+ struct rave_sp_version bootloader_version;
+ struct rave_sp_version firmware_version;
+ u16 rdu_eeprom_flag;
+ u16 dds_eeprom_flag;
+ u8 pic_flag;
+ u8 orientation;
+ u32 etc;
+ s16 temp[2];
+ u8 backlight_current[3];
+ u8 dip_switch;
+ u8 host_interrupt;
+ u16 voltage_28;
+ u8 i2c_device_status;
+ u8 power_status;
+ u8 general_status;
+#define RAVE_SP_STATUS_GS_FIRMWARE_MODE BIT(1)
+
+ u8 deprecated1;
+ u8 power_led_status;
+ u8 deprecated2;
+ u8 periph_power_shutoff;
+} __packed;
+
/**
* struct rave_sp_variant_cmds - Variant specific command routines
*
* @translate: Generic to variant specific command mapping routine
+ * @get_status: Variant specific implementation of CMD_GET_STATUS
*/
struct rave_sp_variant_cmds {
int (*translate)(enum rave_sp_command);
+ int (*get_status)(struct rave_sp *sp, struct rave_sp_status *);
};
/**
@@ -171,37 +194,6 @@ struct rave_sp {
const char *part_number_bootloader;
};
-struct rave_sp_version {
- u8 hardware;
- __le16 major;
- u8 minor;
- u8 letter[2];
-} __packed;
-
-struct rave_sp_status {
- struct rave_sp_version bootloader_version;
- struct rave_sp_version firmware_version;
- u16 rdu_eeprom_flag;
- u16 dds_eeprom_flag;
- u8 pic_flag;
- u8 orientation;
- u32 etc;
- s16 temp[2];
- u8 backlight_current[3];
- u8 dip_switch;
- u8 host_interrupt;
- u16 voltage_28;
- u8 i2c_device_status;
- u8 power_status;
- u8 general_status;
-#define RAVE_SP_STATUS_GS_FIRMWARE_MODE BIT(1)
-
- u8 deprecated1;
- u8 power_led_status;
- u8 deprecated2;
- u8 periph_power_shutoff;
-} __packed;
-
static bool rave_sp_id_is_event(u8 code)
{
return (code & 0xF0) == RAVE_SP_EVNT_BASE;
@@ -596,12 +588,16 @@ static int rave_sp_default_cmd_translate(enum rave_sp_command command)
return 0x14;
case RAVE_SP_CMD_SW_WDT:
return 0x1C;
+ case RAVE_SP_CMD_PET_WDT:
+ return 0x1D;
case RAVE_SP_CMD_RESET:
return 0x1E;
case RAVE_SP_CMD_RESET_REASON:
return 0x1F;
case RAVE_SP_CMD_BOOTLOADER:
return 0x2A;
+ case RAVE_SP_CMD_RMB_EEPROM:
+ return 0x20;
default:
return -EINVAL;
}
@@ -623,18 +619,45 @@ static const char *devm_rave_sp_version(struct device_d *dev,
version->letter[1]);
}
-static int rave_sp_get_status(struct rave_sp *sp)
+
+static int rave_sp_rdu1_get_status(struct rave_sp *sp,
+ struct rave_sp_status *status)
{
- struct device_d *dev = sp->serdev->dev;
u8 cmd[] = {
[0] = RAVE_SP_CMD_STATUS,
[1] = 0
};
+
+ return rave_sp_exec(sp, cmd, sizeof(cmd), status, sizeof(*status));
+}
+
+static int rave_sp_emulated_get_status(struct rave_sp *sp,
+ struct rave_sp_status *status)
+{
+ u8 cmd[] = {
+ [0] = RAVE_SP_CMD_GET_FIRMWARE_VERSION,
+ [1] = 0,
+ };
+ int ret;
+
+ ret = rave_sp_exec(sp, cmd, sizeof(cmd), &status->firmware_version,
+ sizeof(status->firmware_version));
+ if (ret)
+ return ret;
+
+ cmd[0] = RAVE_SP_CMD_GET_BOOTLOADER_VERSION;
+ return rave_sp_exec(sp, cmd, sizeof(cmd), &status->bootloader_version,
+ sizeof(status->bootloader_version));
+}
+
+static int rave_sp_get_status(struct rave_sp *sp)
+{
+ struct device_d *dev = sp->serdev->dev;
struct rave_sp_status status;
const char *mode;
int ret;
- ret = rave_sp_exec(sp, cmd, sizeof(cmd), &status, sizeof(status));
+ ret = sp->variant->cmd.get_status(sp, &status);
if (ret)
return ret;
@@ -663,9 +686,10 @@ static const struct rave_sp_checksum rave_sp_checksum_ccitt = {
};
static const struct rave_sp_variant rave_sp_legacy = {
- .checksum = &rave_sp_checksum_8b2c,
+ .checksum = &rave_sp_checksum_ccitt,
.cmd = {
.translate = rave_sp_default_cmd_translate,
+ .get_status = rave_sp_emulated_get_status,
},
};
@@ -673,6 +697,7 @@ static const struct rave_sp_variant rave_sp_rdu1 = {
.checksum = &rave_sp_checksum_8b2c,
.cmd = {
.translate = rave_sp_rdu1_cmd_translate,
+ .get_status = rave_sp_rdu1_get_status,
},
};
@@ -680,6 +705,7 @@ static const struct rave_sp_variant rave_sp_rdu2 = {
.checksum = &rave_sp_checksum_ccitt,
.cmd = {
.translate = rave_sp_rdu2_cmd_translate,
+ .get_status = rave_sp_emulated_get_status,
},
};
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index b633a3a..1aa096f 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -83,6 +83,7 @@ config DRIVER_NET_DESIGNWARE_SOCFPGA
bool "Designware Universal MAC ethernet driver for SoCFPGA platforms"
depends on ARCH_SOCFPGA
select MFD_SYSCON
+ select RESET_CONTROLLER
help
This option enables support for the Synopsys
Designware Core Univesal MAC 10M/100M/1G ethernet IP on SoCFPGA.
diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
index 98711ba..94a159e 100644
--- a/drivers/net/fec_imx.c
+++ b/drivers/net/fec_imx.c
@@ -482,7 +482,7 @@ static int fec_send(struct eth_device *dev, void *eth_data, int data_length)
dma = dma_map_single(fec->dev, eth_data, data_length, DMA_TO_DEVICE);
if (dma_mapping_error(fec->dev, dma))
- return -EIO;
+ return -EFAULT;
writel((uint32_t)(dma), &fec->tbd_base[fec->tbd_index].data_pointer);
@@ -762,6 +762,8 @@ static int fec_probe(struct device_d *dev)
edev->set_ethaddr = fec_set_hwaddr;
edev->parent = dev;
+ dma_set_mask(dev, DMA_BIT_MASK(32));
+
ret = fec_clk_get(fec);
if (ret < 0)
goto err_free;
diff --git a/drivers/pinctrl/imx-iomux-v3.c b/drivers/pinctrl/imx-iomux-v3.c
index d176199..0ab9704 100644
--- a/drivers/pinctrl/imx-iomux-v3.c
+++ b/drivers/pinctrl/imx-iomux-v3.c
@@ -87,7 +87,7 @@ static int imx_iomux_v3_set_state(struct pinctrl_device *pdev, struct device_nod
const bool share_conf = iomux->flags & SHARE_CONF;
int npins, size, i, fsl_pin_size;
const char *name;
- u32 share_conf_val;
+ u32 share_conf_val = 0;
dev_dbg(iomux->pinctrl.dev, "set state: %s\n", np->full_name);
diff --git a/dts/Bindings/arm/adapteva.txt b/dts/Bindings/arm/adapteva.txt
deleted file mode 100644
index 1d8af9e..0000000
--- a/dts/Bindings/arm/adapteva.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Adapteva Platforms Device Tree Bindings
----------------------------------------
-
-Parallella board
-
-Required root node properties:
- - compatible = "adapteva,parallella";
diff --git a/dts/Bindings/arm/amlogic.txt b/dts/Bindings/arm/amlogic.txt
index 6988056..b5c2b5c 100644
--- a/dts/Bindings/arm/amlogic.txt
+++ b/dts/Bindings/arm/amlogic.txt
@@ -41,6 +41,14 @@ Boards with the Amlogic Meson GXL S905D SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s905d", "amlogic,meson-gxl";
+Boards with the Amlogic Meson GXL S805X SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,s805x", "amlogic,meson-gxl";
+
+Boards with the Amlogic Meson GXL S905W SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,s905w", "amlogic,meson-gxl";
+
Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s912", "amlogic,meson-gxm";
@@ -79,6 +87,11 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,p230" (Meson gxl s905d)
- "amlogic,p231" (Meson gxl s905d)
+ - "amlogic,p241" (Meson gxl s805x)
+
+ - "amlogic,p281" (Meson gxl s905w)
+ - "oranth,tx3-mini" (Meson gxl s905w)
+
- "amlogic,q200" (Meson gxm s912)
- "amlogic,q201" (Meson gxm s912)
- "khadas,vim2" (Meson gxm s912)
diff --git a/dts/Bindings/arm/atmel-pmc.txt b/dts/Bindings/arm/atmel-pmc.txt
deleted file mode 100644
index 795cc78..0000000
--- a/dts/Bindings/arm/atmel-pmc.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Power Management Controller (PMC)
-
-Required properties:
-- compatible: Should be "atmel,<chip>-pmc".
- <chip> can be: at91rm9200, at91sam9260, at91sam9g45, at91sam9n12,
- at91sam9x5, sama5d3
-
-- reg: Should contain PMC registers location and length
-
-Examples:
- pmc: pmc@fffffc00 {
- compatible = "atmel,at91rm9200-pmc";
- reg = <0xfffffc00 0x100>;
- };
diff --git a/dts/Bindings/arm/bcm/brcm,brcmstb.txt b/dts/Bindings/arm/bcm/brcm,brcmstb.txt
index c052caa..104cc9b 100644
--- a/dts/Bindings/arm/bcm/brcm,brcmstb.txt
+++ b/dts/Bindings/arm/bcm/brcm,brcmstb.txt
@@ -189,7 +189,11 @@ Power-Down (SRPD), among other things.
Required properties:
- compatible : should contain one of these
+ "brcm,brcmstb-memc-ddr-rev-b.2.1"
"brcm,brcmstb-memc-ddr-rev-b.2.2"
+ "brcm,brcmstb-memc-ddr-rev-b.2.3"
+ "brcm,brcmstb-memc-ddr-rev-b.3.0"
+ "brcm,brcmstb-memc-ddr-rev-b.3.1"
"brcm,brcmstb-memc-ddr"
- reg : the MEMC DDR register range
diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt
index 15ac8e8..5d1ad09 100644
--- a/dts/Bindings/arm/coresight.txt
+++ b/dts/Bindings/arm/coresight.txt
@@ -39,6 +39,8 @@ its hardware characteristcs.
- System Trace Macrocell:
"arm,coresight-stm", "arm,primecell"; [1]
+ - Coresight Address Translation Unit (CATU)
+ "arm,coresight-catu", "arm,primecell";
* reg: physical base address and length of the register
set(s) of the component.
@@ -84,8 +86,15 @@ its hardware characteristcs.
* Optional property for TMC:
* arm,buffer-size: size of contiguous buffer space for TMC ETR
- (embedded trace router)
+ (embedded trace router). This property is obsolete. The buffer size
+ can be configured dynamically via buffer_size property in sysfs.
+ * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
+ use the SG mode on this system.
+
+* Optional property for CATU :
+ * interrupts : Exactly one SPI may be listed for reporting the address
+ error
Example:
@@ -118,6 +127,35 @@ Example:
};
};
+ etr@20070000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x20070000 0 0x1000>;
+
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* input port */
+ port@0 {
+ reg = <0>;
+ etr_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator2_out_port0>;
+ };
+ };
+
+ /* CATU link represented by output port */
+ port@1 {
+ reg = <1>;
+ etr_out_port: endpoint {
+ remote-endpoint = <&catu_in_port>;
+ };
+ };
+ };
+ };
+
2. Links
replicator {
/* non-configurable replicators don't show up on the
@@ -247,5 +285,23 @@ Example:
};
};
+5. CATU
+
+ catu@207e0000 {
+ compatible = "arm,coresight-catu", "arm,primecell";
+ reg = <0 0x207e0000 0 0x1000>;
+
+ clocks = <&oscclk6a>;
+ clock-names = "apb_pclk";
+
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ port {
+ catu_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&etr_out_port>;
+ };
+ };
+ };
+
[1]. There is currently two version of STM: STM32 and STM500. Both
have the same HW interface and as such don't need an explicit binding name.
diff --git a/dts/Bindings/arm/cpu-capacity.txt b/dts/Bindings/arm/cpu-capacity.txt
index 7809fbe..9b5685a 100644
--- a/dts/Bindings/arm/cpu-capacity.txt
+++ b/dts/Bindings/arm/cpu-capacity.txt
@@ -94,7 +94,7 @@ cpus {
};
idle-states {
- entry-method = "arm,psci";
+ entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt
index 29e1dc5..96dfccc 100644
--- a/dts/Bindings/arm/cpus.txt
+++ b/dts/Bindings/arm/cpus.txt
@@ -183,6 +183,7 @@ described below.
"marvell,sheeva-v5"
"nvidia,tegra132-denver"
"nvidia,tegra186-denver"
+ "nvidia,tegra194-carmel"
"qcom,krait"
"qcom,kryo"
"qcom,kryo385"
@@ -219,6 +220,7 @@ described below.
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
"renesas,apmu"
+ "renesas,r9a06g032-smp"
"rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"
diff --git a/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt b/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt
index 669808b..6dd6f39 100644
--- a/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt
+++ b/dts/Bindings/arm/freescale/fsl,vf610-mscm-ir.txt
@@ -18,9 +18,6 @@ Required properties:
assignment of the interrupt router is required.
Flags get passed only when using GIC as parent. Flags
encoding as documented by the GIC bindings.
-- interrupt-parent: Should be the phandle for the interrupt controller of
- the CPU the device tree is intended to be used on. This
- is either the node of the GIC or NVIC controller.
Example:
mscm_ir: interrupt-controller@40001800 {
diff --git a/dts/Bindings/arm/freescale/m4if.txt b/dts/Bindings/arm/freescale/m4if.txt
new file mode 100644
index 0000000..93bd7b8
--- /dev/null
+++ b/dts/Bindings/arm/freescale/m4if.txt
@@ -0,0 +1,12 @@
+* Freescale Multi Master Multi Memory Interface (M4IF) module
+
+Required properties:
+- compatible : Should be "fsl,imx51-m4if"
+- reg : Address and length of the register set for the device
+
+Example:
+
+m4if: m4if@83fd8000 {
+ compatible = "fsl,imx51-m4if";
+ reg = <0x83fd8000 0x1000>;
+};
diff --git a/dts/Bindings/arm/freescale/tigerp.txt b/dts/Bindings/arm/freescale/tigerp.txt
new file mode 100644
index 0000000..19e2aad
--- /dev/null
+++ b/dts/Bindings/arm/freescale/tigerp.txt
@@ -0,0 +1,12 @@
+* Freescale Tigerp platform module
+
+Required properties:
+- compatible : Should be "fsl,imx51-tigerp"
+- reg : Address and length of the register set for the device
+
+Example:
+
+tigerp: tigerp@83fa0000 {
+ compatible = "fsl,imx51-tigerp";
+ reg = <0x83fa0000 0x28>;
+};
diff --git a/dts/Bindings/arm/fsl.txt b/dts/Bindings/arm/fsl.txt
index cdb9dd7..8a1baa2 100644
--- a/dts/Bindings/arm/fsl.txt
+++ b/dts/Bindings/arm/fsl.txt
@@ -53,6 +53,10 @@ i.MX6 Quad SABRE Automotive Board
Required root node properties:
- compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+i.MX6SLL EVK board
+Required root node properties:
+ - compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
+
Generic i.MX boards
-------------------
diff --git a/dts/Bindings/arm/idle-states.txt b/dts/Bindings/arm/idle-states.txt
index 7a59133..2c73847 100644
--- a/dts/Bindings/arm/idle-states.txt
+++ b/dts/Bindings/arm/idle-states.txt
@@ -237,8 +237,8 @@ processor idle states, defined as device tree nodes, are listed.
Value type: <stringlist>
Usage and definition depend on ARM architecture version.
# On ARM v8 64-bit this property is required and must
- be one of:
- - "psci" (see bindings in [2])
+ be:
+ - "psci"
# On ARM 32-bit systems this property is optional
The nodes describing the idle states (state) can only be defined within the
diff --git a/dts/Bindings/arm/insignal-boards.txt b/dts/Bindings/arm/insignal-boards.txt
deleted file mode 100644
index 524c3dc..0000000
--- a/dts/Bindings/arm/insignal-boards.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-* Insignal's Exynos4210 based Origen evaluation board
-
-Origen low-cost evaluation board is based on Samsung's Exynos4210 SoC.
-
-Required root node properties:
- - compatible = should be one or more of the following.
- (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
- (b) "samsung,exynos4210" - for boards based on Exynos4210 SoC.
diff --git a/dts/Bindings/arm/marvell/ap806-system-controller.txt b/dts/Bindings/arm/marvell/ap806-system-controller.txt
index 0b88744..3fd21bb 100644
--- a/dts/Bindings/arm/marvell/ap806-system-controller.txt
+++ b/dts/Bindings/arm/marvell/ap806-system-controller.txt
@@ -2,14 +2,17 @@ Marvell Armada AP806 System Controller
======================================
The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
-SoCs. It contains a system controller, which provides a number
-registers giving access to numerous features: clocks, pin-muxing and
-many other SoC configuration items. This DT binding allows to describe
-this system controller.
+SoCs. It contains system controllers, which provide several registers
+giving access to numerous features: clocks, pin-muxing and many other
+SoC configuration items. This DT binding allows to describe these
+system controllers.
For the top level node:
- compatible: must be: "syscon", "simple-mfd";
- - reg: register area of the AP806 system controller
+ - reg: register area of the AP806 system controller
+
+SYSTEM CONTROLLER 0
+===================
Clocks:
-------
@@ -98,3 +101,38 @@ ap_syscon: system-controller@6f4000 {
gpio-ranges = <&ap_pinctrl 0 0 19>;
};
};
+
+SYSTEM CONTROLLER 1
+===================
+
+Thermal:
+--------
+
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/thermal/thermal.txt
+
+The thermal IP can probe the temperature all around the processor. It
+may feature several channels, each of them wired to one sensor.
+
+Required properties:
+- compatible: must be one of:
+ * marvell,armada-ap806-thermal
+- reg: register range associated with the thermal functions.
+
+Optional properties:
+- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
+ to this IP and represents the channel ID. There is one sensor per
+ channel. O refers to the thermal IP internal channel, while positive
+ IDs refer to each CPU.
+
+Example:
+ap_syscon1: system-controller@6f8000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f8000 0x1000>;
+
+ ap_thermal: thermal-sensor@80 {
+ compatible = "marvell,armada-ap806-thermal";
+ reg = <0x80 0x10>;
+ #thermal-sensor-cells = <1>;
+ };
+};
diff --git a/dts/Bindings/arm/marvell/armada-37xx.txt b/dts/Bindings/arm/marvell/armada-37xx.txt
index 35c3c34..eddde4f 100644
--- a/dts/Bindings/arm/marvell/armada-37xx.txt
+++ b/dts/Bindings/arm/marvell/armada-37xx.txt
@@ -33,3 +33,18 @@ nb_pm: syscon@14000 {
compatible = "marvell,armada-3700-nb-pm", "syscon";
reg = <0x14000 0x60>;
}
+
+AVS
+---
+
+For AVS an other component is needed:
+
+Required properties:
+- compatible : should contain "marvell,armada-3700-avs", "syscon";
+- reg : the register start and length for the AVS
+
+Example:
+avs: avs@11500 {
+ compatible = "marvell,armada-3700-avs", "syscon";
+ reg = <0x11500 0x40>;
+}
diff --git a/dts/Bindings/arm/marvell/cp110-system-controller0.txt b/dts/Bindings/arm/marvell/cp110-system-controller.txt
index 29cdbae..81ce742 100644
--- a/dts/Bindings/arm/marvell/cp110-system-controller0.txt
+++ b/dts/Bindings/arm/marvell/cp110-system-controller.txt
@@ -1,15 +1,18 @@
-Marvell Armada CP110 System Controller 0
-========================================
+Marvell Armada CP110 System Controller
+======================================
The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
-SoCs. It contains two sets of system control registers, System
-Controller 0 and System Controller 1. This Device Tree binding allows
-to describe the first system controller, which provides registers to
-configure various aspects of the SoC.
+SoCs. It contains system controllers, which provide several registers
+giving access to numerous features: clocks, pin-muxing and many other
+SoC configuration items. This DT binding allows to describe these
+system controllers.
For the top level node:
- compatible: must be: "syscon", "simple-mfd";
- - reg: register area of the CP110 system controller 0
+ - reg: register area of the CP110 system controller
+
+SYSTEM CONTROLLER 0
+===================
Clocks:
-------
@@ -163,26 +166,60 @@ Required properties:
Example:
-cpm_syscon0: system-controller@440000 {
+CP110_LABEL(syscon0): system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
- cpm_clk: clock {
+ CP110_LABEL(clk): clock {
compatible = "marvell,cp110-clock";
#clock-cells = <2>;
};
- cpm_pinctrl: pinctrl {
+ CP110_LABEL(pinctrl): pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
};
- cpm_gpio1: gpio@100 {
+ CP110_LABEL(gpio1): gpio@100 {
compatible = "marvell,armada-8k-gpio";
offset = <0x100>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&cpm_pinctrl 0 0 32>;
+ gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
};
};
+
+SYSTEM CONTROLLER 1
+===================
+
+Thermal:
+--------
+
+The thermal IP can probe the temperature all around the processor. It
+may feature several channels, each of them wired to one sensor.
+
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/thermal/thermal.txt
+
+Required properties:
+- compatible: must be one of:
+ * marvell,armada-cp110-thermal
+- reg: register range associated with the thermal functions.
+
+Optional properties:
+- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
+ to this IP and represents the channel ID. There is one sensor per
+ channel. O refers to the thermal IP internal channel.
+
+Example:
+CP110_LABEL(syscon1): system-controller@6f8000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f8000 0x1000>;
+
+ CP110_LABEL(thermal): thermal-sensor@70 {
+ compatible = "marvell,armada-cp110-thermal";
+ reg = <0x70 0x10>;
+ #thermal-sensor-cells = <1>;
+ };
+};
diff --git a/dts/Bindings/arm/mediatek.txt b/dts/Bindings/arm/mediatek.txt
index 7d21ab3..8f260e5 100644
--- a/dts/Bindings/arm/mediatek.txt
+++ b/dts/Bindings/arm/mediatek.txt
@@ -11,6 +11,7 @@ compatible: Must contain one of
"mediatek,mt6589"
"mediatek,mt6592"
"mediatek,mt6755"
+ "mediatek,mt6765"
"mediatek,mt6795"
"mediatek,mt6797"
"mediatek,mt7622"
@@ -41,12 +42,18 @@ Supported boards:
- Evaluation phone for MT6755(Helio P10):
Required root node properties:
- compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
+- Evaluation board for MT6765(Helio P22):
+ Required root node properties:
+ - compatible = "mediatek,mt6765-evb", "mediatek,mt6765";
- Evaluation board for MT6795(Helio X10):
Required root node properties:
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
- Evaluation board for MT6797(Helio X20):
Required root node properties:
- compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
+- Mediatek X20 Development Board:
+ Required root node properties:
+ - compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
@@ -59,9 +66,6 @@ Supported boards:
- Reference board for MT7623n with eMMC:
Required root node properties:
- compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
-- Reference board for MT7623n with NAND:
- Required root node properties:
- - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
- Bananapi BPI-R2 board:
- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
- MTK mt8127 tablet moose EVB:
diff --git a/dts/Bindings/arm/msm/qcom,llcc.txt b/dts/Bindings/arm/msm/qcom,llcc.txt
new file mode 100644
index 0000000..5e85749
--- /dev/null
+++ b/dts/Bindings/arm/msm/qcom,llcc.txt
@@ -0,0 +1,26 @@
+== Introduction==
+
+LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
+that can be shared by multiple clients. Clients here are different cores in the
+SOC, the idea is to minimize the local caches at the clients and migrate to
+common pool of memory. Cache memory is divided into partitions called slices
+which are assigned to clients. Clients can query the slice details, activate
+and deactivate them.
+
+Properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,sdm845-llcc"
+
+- reg:
+ Usage: required
+ Value Type: <prop-encoded-array>
+ Definition: Start address and the the size of the register region.
+
+Example:
+
+ cache-controller@1100000 {
+ compatible = "qcom,sdm845-llcc";
+ reg = <0x1100000 0x250000>;
+ };
diff --git a/dts/Bindings/arm/omap/crossbar.txt b/dts/Bindings/arm/omap/crossbar.txt
index ecb360e..4cd5d87 100644
--- a/dts/Bindings/arm/omap/crossbar.txt
+++ b/dts/Bindings/arm/omap/crossbar.txt
@@ -10,7 +10,6 @@ Required properties:
- compatible : Should be "ti,irq-crossbar"
- reg: Base address and the size of the crossbar registers.
- interrupt-controller: indicates that this block is an interrupt controller.
-- interrupt-parent: the interrupt controller this block is connected to.
- ti,max-irqs: Total number of irqs available at the parent interrupt controller.
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
- ti,reg-size: Size of a individual register in bytes. Every individual
diff --git a/dts/Bindings/arm/omap/l4.txt b/dts/Bindings/arm/omap/l4.txt
index b4f8a16..6816adc 100644
--- a/dts/Bindings/arm/omap/l4.txt
+++ b/dts/Bindings/arm/omap/l4.txt
@@ -7,6 +7,7 @@ Required properties:
Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
+ Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus
Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
@@ -15,11 +16,21 @@ Required properties:
Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus
Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus
- ranges : contains the IO map range for the bus
+- reg : registers link agent and interconnect agent and access protection
+- reg-names : "la" for link agent, "ia0" to "ia3" for one to three
+ interconnect agent instances, "ap" for access if it exists
Examples:
-l4: l4@48000000 {
- compatible "ti,omap2-l4", "simple-bus";
+l4: interconnect@48000000 {
+ compatible "ti,omap4-l4-per", "simple-bus";
+ reg = <0x48000000 0x800>,
+ <0x48000800 0x800>,
+ <0x48001000 0x400>,
+ <0x48001400 0x400>,
+ <0x48001800 0x400>,
+ <0x48001c00 0x400>;
+ reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48000000 0x100000>;
diff --git a/dts/Bindings/arm/rockchip.txt b/dts/Bindings/arm/rockchip.txt
index 1c1d62d..acfd3c7 100644
--- a/dts/Bindings/arm/rockchip.txt
+++ b/dts/Bindings/arm/rockchip.txt
@@ -1,5 +1,10 @@
Rockchip platforms device tree bindings
---------------------------------------
+
+- 96boards RK3399 Ficus (ROCK960 Enterprise Edition)
+ Required root node properties:
+ - compatible = "vamrs,ficus", "rockchip,rk3399";
+
- Amarula Vyasa RK3288 board
Required root node properties:
- compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
@@ -66,6 +71,15 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "geekbuying,geekbox", "rockchip,rk3368";
+- Google Bob (Asus Chromebook Flip C101PA):
+ Required root node properties:
+ compatible = "google,bob-rev13", "google,bob-rev12",
+ "google,bob-rev11", "google,bob-rev10",
+ "google,bob-rev9", "google,bob-rev8",
+ "google,bob-rev7", "google,bob-rev6",
+ "google,bob-rev5", "google,bob-rev4",
+ "google,bob", "google,gru", "rockchip,rk3399";
+
- Google Brain (dev-board):
Required root node properties:
- compatible = "google,veyron-brain-rev0", "google,veyron-brain",
diff --git a/dts/Bindings/arm/samsung/pmu.txt b/dts/Bindings/arm/samsung/pmu.txt
index 1668578..433bfd7 100644
--- a/dts/Bindings/arm/samsung/pmu.txt
+++ b/dts/Bindings/arm/samsung/pmu.txt
@@ -40,9 +40,6 @@ following properties:
- #interrupt-cells: must be identical to the that of the parent interrupt
controller.
-- interrupt-parent: a phandle indicating which interrupt controller
- this PMU signals interrupts to.
-
Optional nodes:
diff --git a/dts/Bindings/arm/samsung/samsung-boards.txt b/dts/Bindings/arm/samsung/samsung-boards.txt
index 6970f30..56021bf 100644
--- a/dts/Bindings/arm/samsung/samsung-boards.txt
+++ b/dts/Bindings/arm/samsung/samsung-boards.txt
@@ -1,7 +1,10 @@
-* Samsung's Exynos SoC based boards
+* Samsung's Exynos and S5P SoC based boards
Required root node properties:
- compatible = should be one or more of the following.
+ - "samsung,aries" - for S5PV210-based Samsung Aries board.
+ - "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board.
+ - "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board.
- "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
- "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
- "samsung,monk" - for Exynos3250-based Samsung Simband board.
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
index d8cf740..89b4a38 100644
--- a/dts/Bindings/arm/shmobile.txt
+++ b/dts/Bindings/arm/shmobile.txt
@@ -51,7 +51,8 @@ SoCs:
compatible = "renesas,r8a77990"
- R-Car D3 (R8A77995)
compatible = "renesas,r8a77995"
-
+ - RZ/N1D (R9A06G032)
+ compatible = "renesas,r9a06g032"
Boards:
@@ -112,6 +113,8 @@ Boards:
compatible = "renesas,porter", "renesas,r8a7791"
- RSKRZA1 (YR0K77210C000BE)
compatible = "renesas,rskrza1", "renesas,r7s72100"
+ - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
+ compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"
- Salvator-X (RTP0RC7795SIPB0010S)
compatible = "renesas,salvator-x", "renesas,r8a7795"
- Salvator-X (RTP0RC7796SIPB0011S)
diff --git a/dts/Bindings/arm/ti/k3.txt b/dts/Bindings/arm/ti/k3.txt
new file mode 100644
index 0000000..6a059ca
--- /dev/null
+++ b/dts/Bindings/arm/ti/k3.txt
@@ -0,0 +1,23 @@
+Texas Instruments K3 Multicore SoC architecture device tree bindings
+--------------------------------------------------------------------
+
+Platforms based on Texas Instruments K3 Multicore SoC architecture
+shall follow the following scheme:
+
+SoCs
+----
+
+Each device tree root node must specify which exact SoC in K3 Multicore SoC
+architecture it uses, using one of the following compatible values:
+
+- AM654
+ compatible = "ti,am654";
+
+Boards
+------
+
+In addition, each device tree root node must specify which one or more
+of the following board-specific compatible values:
+
+- AM654 EVM
+ compatible = "ti,am654-evm", "ti,am654";
diff --git a/dts/Bindings/arm/xilinx.txt b/dts/Bindings/arm/xilinx.txt
index b9043bc..26fe5ec 100644
--- a/dts/Bindings/arm/xilinx.txt
+++ b/dts/Bindings/arm/xilinx.txt
@@ -8,18 +8,38 @@ Required root node properties:
Additional compatible strings:
-- Xilinx internal board cc108
+- Adapteva Parallella board
+ "adapteva,parallella"
+
+- Avnet MicroZed board
+ "avnet,zynq-microzed"
+ "xlnx,zynq-microzed"
+
+- Avnet ZedBoard board
+ "avnet,zynq-zed"
+ "xlnx,zynq-zed"
+
+- Digilent Zybo board
+ "digilent,zynq-zybo"
+
+- Digilent Zybo Z7 board
+ "digilent,zynq-zybo-z7"
+
+- Xilinx CC108 internal board
"xlnx,zynq-cc108"
-- Xilinx internal board zc770 with different FMC cards
+- Xilinx ZC702 internal board
+ "xlnx,zynq-zc702"
+
+- Xilinx ZC706 internal board
+ "xlnx,zynq-zc706"
+
+- Xilinx ZC770 internal board, with different FMC cards
"xlnx,zynq-zc770-xm010"
"xlnx,zynq-zc770-xm011"
"xlnx,zynq-zc770-xm012"
"xlnx,zynq-zc770-xm013"
-- Digilent Zybo Z7 board
- "digilent,zynq-zybo-z7"
-
---------------------------------------------------------------
Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings
diff --git a/dts/Bindings/ata/ahci-platform.txt b/dts/Bindings/ata/ahci-platform.txt
index c760ecb..5d5bd45 100644
--- a/dts/Bindings/ata/ahci-platform.txt
+++ b/dts/Bindings/ata/ahci-platform.txt
@@ -17,7 +17,6 @@ Required properties:
- "marvell,armada-380-ahci"
- "marvell,armada-3700-ahci"
- "snps,dwc-ahci"
- - "snps,exynos5440-ahci"
- "snps,spear-ahci"
- "generic-ahci"
- interrupts : <interrupt mapping for SATA IRQ>
@@ -30,6 +29,7 @@ compatible:
Optional properties:
- dma-coherent : Present if dma operations are coherent
- clocks : a list of phandle + clock specifier pairs
+- resets : a list of phandle + reset specifier pairs
- target-supply : regulator for SATA target power
- phys : reference to the SATA PHY node
- phy-names : must be "sata-phy"
diff --git a/dts/Bindings/ata/fsl-sata.txt b/dts/Bindings/ata/fsl-sata.txt
index b46bcf4..fd63bb3 100644
--- a/dts/Bindings/ata/fsl-sata.txt
+++ b/dts/Bindings/ata/fsl-sata.txt
@@ -16,7 +16,6 @@ Required properties:
4 for controller @ 0x1b000
Optional properties:
-- interrupt-parent : optional, if needed for interrupt mapping
- reg : <registers mapping>
Example:
diff --git a/dts/Bindings/ata/pata-arasan.txt b/dts/Bindings/ata/pata-arasan.txt
index 2aff154..872edc1 100644
--- a/dts/Bindings/ata/pata-arasan.txt
+++ b/dts/Bindings/ata/pata-arasan.txt
@@ -3,8 +3,6 @@
Required properties:
- compatible: "arasan,cf-spear1340"
- reg: Address range of the CF registers
-- interrupt-parent: Should be the phandle for the interrupt controller
- that services interrupts for this device
- interrupt: Should contain the CF interrupt number
- clock-frequency: Interface clock rate, in Hz, one of
25000000
diff --git a/dts/Bindings/ata/sata_rcar.txt b/dts/Bindings/ata/sata_rcar.txt
index e20eac7..4268e17 100644
--- a/dts/Bindings/ata/sata_rcar.txt
+++ b/dts/Bindings/ata/sata_rcar.txt
@@ -8,6 +8,7 @@ Required properties:
- "renesas,sata-r8a7791" for R-Car M2-W
- "renesas,sata-r8a7793" for R-Car M2-N
- "renesas,sata-r8a7795" for R-Car H3
+ - "renesas,sata-r8a77965" for R-Car M3-N
- "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device
- "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device
- "renesas,rcar-sata" is deprecated
diff --git a/dts/Bindings/board/fsl-board.txt b/dts/Bindings/board/fsl-board.txt
index fb7b03e..eb52f6b 100644
--- a/dts/Bindings/board/fsl-board.txt
+++ b/dts/Bindings/board/fsl-board.txt
@@ -29,7 +29,6 @@ Required properties:
- reg: should contain the address and the length of the FPGA register set.
Optional properties:
-- interrupt-parent: should specify phandle for the interrupt controller.
- interrupts: should specify event (wakeup) IRQ.
Example (P1022DS):
diff --git a/dts/Bindings/bus/brcm,gisb-arb.txt b/dts/Bindings/bus/brcm,gisb-arb.txt
index 8a6c3c2..729def6 100644
--- a/dts/Bindings/bus/brcm,gisb-arb.txt
+++ b/dts/Bindings/bus/brcm,gisb-arb.txt
@@ -9,8 +9,6 @@ Required properties:
"brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
"brcm,bcm7038-gisb-arb" for 130nm chips
- reg: specifies the base physical address and size of the registers
-- interrupt-parent: specifies the phandle to the parent interrupt controller
- this arbiter gets interrupt line from
- interrupts: specifies the two interrupts (timeout and TEA) to be used from
the parent interrupt controller
diff --git a/dts/Bindings/bus/sun50i-de2-bus.txt b/dts/Bindings/bus/sun50i-de2-bus.txt
new file mode 100644
index 0000000..87dfb33
--- /dev/null
+++ b/dts/Bindings/bus/sun50i-de2-bus.txt
@@ -0,0 +1,37 @@
+Device tree bindings for Allwinner A64 DE2 bus
+
+The Allwinner A64 DE2 is on a special bus, which needs a SRAM region (SRAM C)
+to be claimed for enabling the access.
+
+Required properties:
+
+ - compatible: Should contain "allwinner,sun50i-a64-de2"
+ - reg: A resource specifier for the register space
+ - #address-cells: Must be set to 1
+ - #size-cells: Must be set to 1
+ - ranges: Must be set up to map the address space inside the
+ DE2, for the sub-blocks of DE2.
+ - allwinner,sram: the SRAM that needs to be claimed
+
+Example:
+
+ de2@1000000 {
+ compatible = "allwinner,sun50i-a64-de2";
+ reg = <0x1000000 0x400000>;
+ allwinner,sram = <&de2_sram 1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000000 0x400000>;
+
+ display_clocks: clock@0 {
+ compatible = "allwinner,sun50i-a64-de2-clk";
+ reg = <0x0 0x100000>;
+ clocks = <&ccu CLK_DE>,
+ <&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ };
diff --git a/dts/Bindings/bus/ti-sysc.txt b/dts/Bindings/bus/ti-sysc.txt
index d8ed5b7..91dc233 100644
--- a/dts/Bindings/bus/ti-sysc.txt
+++ b/dts/Bindings/bus/ti-sysc.txt
@@ -36,6 +36,7 @@ Required standard properties:
"ti,sysc-omap-aes"
"ti,sysc-mcasp"
"ti,sysc-usb-host-fs"
+ "ti,sysc-dra7-mcan"
- reg shall have register areas implemented for the interconnect
target module in question such as revision, sysc and syss
diff --git a/dts/Bindings/clock/actions,s900-cmu.txt b/dts/Bindings/clock/actions,owl-cmu.txt
index 93e4fb8..d1e60d2 100644
--- a/dts/Bindings/clock/actions,s900-cmu.txt
+++ b/dts/Bindings/clock/actions,owl-cmu.txt
@@ -1,12 +1,14 @@
-* Actions S900 Clock Management Unit (CMU)
+* Actions Semi Owl Clock Management Unit (CMU)
-The Actions S900 clock management unit generates and supplies clock to various
-controllers within the SoC. The clock binding described here is applicable to
-S900 SoC.
+The Actions Semi Owl Clock Management Unit generates and supplies clock
+to various controllers within the SoC. The clock binding described here is
+applicable to S900 and S700 SoC's.
Required Properties:
-- compatible: should be "actions,s900-cmu"
+- compatible: should be one of the following,
+ "actions,s900-cmu"
+ "actions,s700-cmu"
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: Reference to the parent clocks ("hosc", "losc")
@@ -15,16 +17,16 @@ Required Properties:
Each clock is assigned an identifier, and client nodes can use this identifier
to specify the clock which they consume.
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/actions,s900-cmu.h header and can be used in device
-tree sources.
+All available clocks are defined as preprocessor macros in corresponding
+dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h header and can be
+used in device tree sources.
External clocks:
The hosc clock used as input for the plls is generated outside the SoC. It is
expected that it is defined using standard clock bindings as "hosc".
-Actions S900 CMU also requires one more clock:
+Actions Semi S900 CMU also requires one more clock:
- "losc" - internal low frequency oscillator
Example: Clock Management Unit node:
diff --git a/dts/Bindings/clock/amlogic,axg-audio-clkc.txt b/dts/Bindings/clock/amlogic,axg-audio-clkc.txt
new file mode 100644
index 0000000..61777ad
--- /dev/null
+++ b/dts/Bindings/clock/amlogic,axg-audio-clkc.txt
@@ -0,0 +1,56 @@
+* Amlogic AXG Audio Clock Controllers
+
+The Amlogic AXG audio clock controller generates and supplies clock to the
+other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
+devices.
+
+Required Properties:
+
+- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D
+- reg : physical base address of the clock controller and length of
+ memory mapped region.
+- clocks : a list of phandle + clock-specifier pairs for the clocks listed
+ in clock-names.
+- clock-names : must contain the following:
+ * "pclk" - Main peripheral bus clock
+ may contain the following:
+ * "mst_in[0-7]" - 8 input plls to generate clock signals
+ * "slv_sclk[0-9]" - 10 slave bit clocks provided by external
+ components.
+ * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
+ components.
+- resets : phandle of the internal reset line
+- #clock-cells : should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
+used in device tree sources.
+
+Example:
+
+clkc_audio: clock-controller@0 {
+ compatible = "amlogic,axg-audio-clkc";
+ reg = <0x0 0x0 0x0 0xb4>;
+ #clock-cells = <1>;
+
+ clocks = <&clkc CLKID_AUDIO>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL3>,
+ <&clkc CLKID_HIFI_PLL>,
+ <&clkc CLKID_FCLK_DIV3>,
+ <&clkc CLKID_FCLK_DIV4>,
+ <&clkc CLKID_GP0_PLL>;
+ clock-names = "pclk",
+ "mst_in0",
+ "mst_in1",
+ "mst_in2",
+ "mst_in3",
+ "mst_in4",
+ "mst_in5",
+ "mst_in6",
+ "mst_in7";
+ resets = <&reset RESET_AUDIO>;
+};
diff --git a/dts/Bindings/clock/at91-clock.txt b/dts/Bindings/clock/at91-clock.txt
index 51c259a..8f8f950 100644
--- a/dts/Bindings/clock/at91-clock.txt
+++ b/dts/Bindings/clock/at91-clock.txt
@@ -17,14 +17,13 @@ Required properties:
"atmel,at91sam9x5-clk-slow-rc-osc":
at91 internal slow RC oscillator
- "atmel,at91rm9200-pmc" or
- "atmel,at91sam9g45-pmc" or
- "atmel,at91sam9n12-pmc" or
- "atmel,at91sam9x5-pmc" or
- "atmel,sama5d3-pmc":
+ "atmel,<chip>-pmc":
at91 PMC (Power Management Controller)
All at91 specific clocks (clocks defined below) must be child
node of the PMC node.
+ <chip> can be: at91rm9200, at91sam9260, at91sam9261,
+ at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9x5,
+ sama5d2, sama5d3 or sama5d4.
"atmel,at91sam9x5-clk-slow" (under sckc node)
or
@@ -91,6 +90,9 @@ Required properties:
at91 audio pll output on AUDIOPLLCLK that feeds the PMC
and can be used by peripheral clock or generic clock
+ "atmel,sama5d2-clk-i2s-mux" (under pmc node):
+ at91 I2S clock source selection
+
Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
@@ -180,7 +182,6 @@ For example:
};
Required properties for main clock internal RC oscillator:
-- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<0>".
- clock-frequency : define the internal RC oscillator frequency.
@@ -197,7 +198,6 @@ For example:
};
Required properties for main clock oscillator:
-- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<0>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall encode the main osc source clk sources (see atmel datasheet).
@@ -218,7 +218,6 @@ For example:
};
Required properties for main clock:
-- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<0>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall encode the main clk sources (see atmel datasheet).
@@ -233,7 +232,6 @@ For example:
};
Required properties for master clock:
-- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<3>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the master clock sources (see atmel datasheet) phandles.
@@ -292,7 +290,6 @@ For example:
Required properties for pll clocks:
-- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<1>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the main clock phandle.
@@ -348,7 +345,6 @@ For example:
};
Required properties for programmable clocks:
-- interrupt-parent : must reference the PMC node.
- #size-cells : shall be 0 (reg is used to encode clk id).
- #address-cells : shall be 1 (reg is used to encode clk id).
- clocks : shall be the programmable clock source phandles.
@@ -451,7 +447,6 @@ For example:
Required properties for utmi clock:
-- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the main clock source phandle.
@@ -507,3 +502,35 @@ For example:
atmel,clk-output-range = <0 83000000>;
};
};
+
+Required properties for I2S mux clocks:
+- #size-cells : shall be 0 (reg is used to encode I2S bus id).
+- #address-cells : shall be 1 (reg is used to encode I2S bus id).
+- name: device tree node describing a specific mux clock.
+ * #clock-cells : from common clock binding; shall be set to 0.
+ * clocks : shall be the mux clock parent phandles; shall be 2 phandles:
+ peripheral and generated clock; the first phandle shall belong to the
+ peripheral clock and the second one shall belong to the generated
+ clock; "clock-indices" property can be user to specify
+ the correct order.
+ * reg: I2S bus id of the corresponding mux clock.
+ e.g. reg = <0>; for i2s0, reg = <1>; for i2s1
+
+For example:
+ i2s_clkmux {
+ compatible = "atmel,sama5d2-clk-i2s-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2s0muxck: i2s0_muxclk {
+ clocks = <&i2s0_clk>, <&i2s0_gclk>;
+ #clock-cells = <0>;
+ reg = <0>;
+ };
+
+ i2s1muxck: i2s1_muxclk {
+ clocks = <&i2s1_clk>, <&i2s1_gclk>;
+ #clock-cells = <0>;
+ reg = <1>;
+ };
+ };
diff --git a/dts/Bindings/clock/exynos5440-clock.txt b/dts/Bindings/clock/exynos5440-clock.txt
deleted file mode 100644
index c7d227c..0000000
--- a/dts/Bindings/clock/exynos5440-clock.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* Samsung Exynos5440 Clock Controller
-
-The Exynos5440 clock controller generates and supplies clock to various
-controllers within the Exynos5440 SoC.
-
-Required Properties:
-
-- compatible: should be "samsung,exynos5440-clock".
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos5440.h header and can be used in device
-tree sources.
-
-Example: An example of a clock controller node is listed below.
-
- clock: clock-controller@10010000 {
- compatible = "samsung,exynos5440-clock";
- reg = <0x160000 0x10000>;
- #clock-cells = <1>;
- };
diff --git a/dts/Bindings/clock/maxim,max9485.txt b/dts/Bindings/clock/maxim,max9485.txt
new file mode 100644
index 0000000..61bec11
--- /dev/null
+++ b/dts/Bindings/clock/maxim,max9485.txt
@@ -0,0 +1,59 @@
+Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
+
+This device exposes 4 clocks in total:
+
+- MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
+- MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
+ frequencies
+- MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
+
+MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
+requests.
+
+Required properties:
+- compatible: "maxim,max9485"
+- clocks: Input clock, must provice 27.000 MHz
+- clock-names: Must be set to "xclk"
+- #clock-cells: From common clock binding; shall be set to 1
+
+Optional properties:
+- reset-gpios: GPIO descriptor connected to the #RESET input pin
+- vdd-supply: A regulator node for Vdd
+- clock-output-names: Name of output clocks, as defined in common clock
+ bindings
+
+If not explicitly set, the output names are "mclkout", "clkout", "clkout1"
+and "clkout2".
+
+Clocks are defined as preprocessor macros in the dt-binding header.
+
+Example:
+
+ #include <dt-bindings/clock/maxim,max9485.h>
+
+ xo-27mhz: xo-27mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ &i2c0 {
+ max9485: audio-clock@63 {
+ reg = <0x63>;
+ compatible = "maxim,max9485";
+ clock-names = "xclk";
+ clocks = <&xo-27mhz>;
+ reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+ vdd-supply = <&3v3-reg>;
+ #clock-cells = <1>;
+ };
+ };
+
+ // Clock consumer node
+
+ foo@0 {
+ compatible = "bar,foo";
+ /* ... */
+ clock-names = "foo-input-clk";
+ clocks = <&max9485 MAX9485_CLKOUT1>;
+ };
diff --git a/dts/Bindings/clock/qcom,dispcc.txt b/dts/Bindings/clock/qcom,dispcc.txt
new file mode 100644
index 0000000..d639e18
--- /dev/null
+++ b/dts/Bindings/clock/qcom,dispcc.txt
@@ -0,0 +1,19 @@
+Qualcomm Technologies, Inc. Display Clock Controller Binding
+------------------------------------------------------------
+
+Required properties :
+
+- compatible : shall contain "qcom,sdm845-dispcc"
+- reg : shall contain base register location and length.
+- #clock-cells : from common clock binding, shall contain 1.
+- #reset-cells : from common reset binding, shall contain 1.
+- #power-domain-cells : from generic power domain binding, shall contain 1.
+
+Example:
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sdm845-dispcc";
+ reg = <0xaf00000 0x100000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/renesas,r9a06g032-sysctrl.txt b/dts/Bindings/clock/renesas,r9a06g032-sysctrl.txt
new file mode 100644
index 0000000..d60b997
--- /dev/null
+++ b/dts/Bindings/clock/renesas,r9a06g032-sysctrl.txt
@@ -0,0 +1,43 @@
+* Renesas R9A06G032 SYSCTRL
+
+Required Properties:
+
+ - compatible: Must be:
+ - "renesas,r9a06g032-sysctrl"
+ - reg: Base address and length of the SYSCTRL IO block.
+ - #clock-cells: Must be 1
+ - clocks: References to the parent clocks:
+ - external 40mhz crystal.
+ - external (optional) 32.768khz
+ - external (optional) jtag input
+ - external (optional) RGMII_REFCLK
+ - clock-names: Must be:
+ clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+
+Examples
+--------
+
+ - SYSCTRL node:
+
+ sysctrl: system-controller@4000c000 {
+ compatible = "renesas,r9a06g032-sysctrl";
+ reg = <0x4000c000 0x1000>;
+ #clock-cells = <1>;
+
+ clocks = <&ext_mclk>, <&ext_rtc_clk>,
+ <&ext_jtag_clk>, <&ext_rgmii_ref>;
+ clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+ };
+
+ - Other nodes can use the clocks provided by SYSCTRL as in:
+
+ #include <dt-bindings/clock/r9a06g032-sysctrl.h>
+ uart0: serial@40060000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x40060000 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&sysctrl R9A06G032_CLK_UART0>;
+ clock-names = "baudclk";
+ };
diff --git a/dts/Bindings/clock/rockchip,px30-cru.txt b/dts/Bindings/clock/rockchip,px30-cru.txt
new file mode 100644
index 0000000..39f0c1a
--- /dev/null
+++ b/dts/Bindings/clock/rockchip,px30-cru.txt
@@ -0,0 +1,65 @@
+* Rockchip PX30 Clock and Reset Unit
+
+The PX30 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
+- compatible: CRU should be "rockchip,px30-cru"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+ If missing, pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "i2sx_clkin" - external I2S clock - optional,
+ - "gmac_clkin" - external GMAC clock - optional
+
+Example: Clock controller node:
+
+ pmucru: clock-controller@ff2bc000 {
+ compatible = "rockchip,px30-pmucru";
+ reg = <0x0 0xff2bc000 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@ff2b0000 {
+ compatible = "rockchip,px30-cru";
+ reg = <0x0 0xff2b0000 0x0 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart0: serial@ff030000 {
+ compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff030000 0x0 0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
diff --git a/dts/Bindings/clock/sun8i-de2.txt b/dts/Bindings/clock/sun8i-de2.txt
index f2fa87c..e94582e 100644
--- a/dts/Bindings/clock/sun8i-de2.txt
+++ b/dts/Bindings/clock/sun8i-de2.txt
@@ -6,6 +6,7 @@ Required properties :
- "allwinner,sun8i-a83t-de2-clk"
- "allwinner,sun8i-h3-de2-clk"
- "allwinner,sun8i-v3s-de2-clk"
+ - "allwinner,sun50i-a64-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
- reg: Must contain the registers base address and length
diff --git a/dts/Bindings/connector/usb-connector.txt b/dts/Bindings/connector/usb-connector.txt
index e1463f1..8855bfc 100644
--- a/dts/Bindings/connector/usb-connector.txt
+++ b/dts/Bindings/connector/usb-connector.txt
@@ -15,6 +15,33 @@ Optional properties:
- type: size of the connector, should be specified in case of USB-A, USB-B
non-fullsize connectors: "mini", "micro".
+Optional properties for usb-c-connector:
+- power-role: should be one of "source", "sink" or "dual"(DRP) if typec
+ connector has power support.
+- try-power-role: preferred power role if "dual"(DRP) can support Try.SNK
+ or Try.SRC, should be "sink" for Try.SNK or "source" for Try.SRC.
+- data-role: should be one of "host", "device", "dual"(DRD) if typec
+ connector supports USB data.
+
+Required properties for usb-c-connector with power delivery support:
+- source-pdos: An array of u32 with each entry providing supported power
+ source data object(PDO), the detailed bit definitions of PDO can be found
+ in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2
+ Source_Capabilities Message, the order of each entry(PDO) should follow
+ the PD spec chapter 6.4.1. Required for power source and power dual role.
+ User can specify the source PDO array via PDO_FIXED/BATT/VAR() defined in
+ dt-bindings/usb/pd.h.
+- sink-pdos: An array of u32 with each entry providing supported power
+ sink data object(PDO), the detailed bit definitions of PDO can be found
+ in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
+ Sink Capabilities Message, the order of each entry(PDO) should follow
+ the PD spec chapter 6.4.1. Required for power sink and power dual role.
+ User can specify the sink PDO array via PDO_FIXED/BATT/VAR() defined in
+ dt-bindings/usb/pd.h.
+- op-sink-microwatt: Sink required operating power in microwatt, if source
+ can't offer the power, Capability Mismatch is set. Required for power
+ sink and power dual role.
+
Required nodes:
- any data bus to the connector should be modeled using the OF graph bindings
specified in bindings/graph.txt, unless the bus is between parent node and
@@ -73,3 +100,20 @@ ccic: s2mm005@33 {
};
};
};
+
+3. USB-C connector attached to a typec port controller(ptn5110), which has
+power delivery support and enables drp.
+
+typec: ptn5110@50 {
+ ...
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 12000, 2000)>;
+ op-sink-microwatt = <10000000>;
+ };
+};
diff --git a/dts/Bindings/cpufreq/brcm,stb-avs-cpu-freq.txt b/dts/Bindings/cpufreq/brcm,stb-avs-cpu-freq.txt
index af23857..73470ec 100644
--- a/dts/Bindings/cpufreq/brcm,stb-avs-cpu-freq.txt
+++ b/dts/Bindings/cpufreq/brcm,stb-avs-cpu-freq.txt
@@ -29,8 +29,6 @@ Required properties:
- reg: Specifies base physical address and size of the registers.
- interrupts: The interrupt that the AVS CPU will use to interrupt the host
when a command completed.
-- interrupt-parent: The interrupt controller the above interrupt is routed
- through.
- interrupt-names: The name of the interrupt used to interrupt the host.
Optional properties:
diff --git a/dts/Bindings/cpufreq/cpufreq-exynos5440.txt b/dts/Bindings/cpufreq/cpufreq-exynos5440.txt
deleted file mode 100644
index caff1a5..0000000
--- a/dts/Bindings/cpufreq/cpufreq-exynos5440.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-
-Exynos5440 cpufreq driver
--------------------
-
-Exynos5440 SoC cpufreq driver for CPU frequency scaling.
-
-Required properties:
-- interrupts: Interrupt to know the completion of cpu frequency change.
-- operating-points: Table of frequencies and voltage CPU could be transitioned into,
- in the decreasing order. Frequency should be in KHz units and voltage
- should be in microvolts.
-
-Optional properties:
-- clock-latency: Clock monitor latency in microsecond.
-
-All the required listed above must be defined under node cpufreq.
-
-Example:
---------
- cpufreq@160000 {
- compatible = "samsung,exynos5440-cpufreq";
- reg = <0x160000 0x1000>;
- interrupts = <0 57 0>;
- operating-points = <
- 1000000 975000
- 800000 925000>;
- clock-latency = <100000>;
- };
diff --git a/dts/Bindings/crypto/amd-ccp.txt b/dts/Bindings/crypto/amd-ccp.txt
index 8c61183..d87579d 100644
--- a/dts/Bindings/crypto/amd-ccp.txt
+++ b/dts/Bindings/crypto/amd-ccp.txt
@@ -3,8 +3,6 @@
Required properties:
- compatible: Should be "amd,ccp-seattle-v1a"
- reg: Address and length of the register set for the device
-- interrupt-parent: Should be the phandle for the interrupt controller
- that services interrupts for this device
- interrupts: Should contain the CCP interrupt
Optional properties:
diff --git a/dts/Bindings/crypto/arm-cryptocell.txt b/dts/Bindings/crypto/arm-cryptocell.txt
index c2598ab..999fb2a 100644
--- a/dts/Bindings/crypto/arm-cryptocell.txt
+++ b/dts/Bindings/crypto/arm-cryptocell.txt
@@ -7,8 +7,6 @@ Required properties:
- interrupts: Interrupt number for the device.
Optional properties:
-- interrupt-parent: The phandle for the interrupt controller that services
- interrupts for this device.
- clocks: Reference to the crypto engine clock.
- dma-coherent: Present if dma operations are coherent.
diff --git a/dts/Bindings/crypto/fsl-sec2.txt b/dts/Bindings/crypto/fsl-sec2.txt
index f0d926b..125f155 100644
--- a/dts/Bindings/crypto/fsl-sec2.txt
+++ b/dts/Bindings/crypto/fsl-sec2.txt
@@ -50,11 +50,6 @@ remaining bits are reserved for future SEC EUs.
..and so on and so forth.
-Optional properties:
-
-- interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
-
Example:
/* MPC8548E */
diff --git a/dts/Bindings/crypto/fsl-sec4.txt b/dts/Bindings/crypto/fsl-sec4.txt
index 3c1f3a2..2fe245c 100644
--- a/dts/Bindings/crypto/fsl-sec4.txt
+++ b/dts/Bindings/crypto/fsl-sec4.txt
@@ -99,13 +99,6 @@ PROPERTIES
of the specifier is defined by the binding document
describing the node's interrupt parent.
- - interrupt-parent
- Usage: (required if interrupt property is defined)
- Value type: <phandle>
- Definition: A single <phandle> value that points
- to the interrupt parent to which the child domain
- is being mapped.
-
- clocks
Usage: required if SEC 4.0 requires explicit enablement of clocks
Value type: <prop_encoded-array>
@@ -199,13 +192,6 @@ Job Ring (JR) Node
of the specifier is defined by the binding document
describing the node's interrupt parent.
- - interrupt-parent
- Usage: (required if interrupt property is defined)
- Value type: <phandle>
- Definition: A single <phandle> value that points
- to the interrupt parent to which the child domain
- is being mapped.
-
EXAMPLE
jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
@@ -370,13 +356,6 @@ Secure Non-Volatile Storage (SNVS) Node
of the specifier is defined by the binding document
describing the node's interrupt parent.
- - interrupt-parent
- Usage: (required if interrupt property is defined)
- Value type: <phandle>
- Definition: A single <phandle> value that points
- to the interrupt parent to which the child domain
- is being mapped.
-
EXAMPLE
sec_mon@314000 {
compatible = "fsl,sec-v4.0-mon", "syscon";
diff --git a/dts/Bindings/crypto/hisilicon,hip07-sec.txt b/dts/Bindings/crypto/hisilicon,hip07-sec.txt
new file mode 100644
index 0000000..78d2db9
--- /dev/null
+++ b/dts/Bindings/crypto/hisilicon,hip07-sec.txt
@@ -0,0 +1,67 @@
+* Hisilicon hip07 Security Accelerator (SEC)
+
+Required properties:
+- compatible: Must contain one of
+ - "hisilicon,hip06-sec"
+ - "hisilicon,hip07-sec"
+- reg: Memory addresses and lengths of the memory regions through which
+ this device is controlled.
+ Region 0 has registers to control the backend processing engines.
+ Region 1 has registers for functionality common to all queues.
+ Regions 2-18 have registers for the 16 individual queues which are isolated
+ both in hardware and within the driver.
+- interrupts: Interrupt specifiers.