diff options
151 files changed, 1632 insertions, 534 deletions
diff --git a/Documentation/boards/stm32mp.rst b/Documentation/boards/stm32mp.rst index 6d97b0d6d4..de793ab3c9 100644 --- a/Documentation/boards/stm32mp.rst +++ b/Documentation/boards/stm32mp.rst @@ -35,7 +35,7 @@ The resulting images will be placed under ``images/``: Flashing barebox ---------------- -An appropriate image for the boot media can be generated with following +An appropriate image for a SD-Card can be generated with following ``genimage(1)`` config:: image @STM32MP_BOARD@.img { @@ -61,7 +61,22 @@ An appropriate image for the boot media can be generated with following } } -Image can then be flashed on e.g. a SD-Card. +For eMMC, the boot partitions are used as the FSBL partitions and so the user +partitions may look like this: + + image @STM32MP_BOARD@.img { + partition ssbl { + image = "barebox-@STM32MP_BOARD@.img" + size = 1M + } + partition barebox-environment { + image = "/dev/null" + size = 1M + } + } + +The fsbl1 and fsbl2 can be flashed by writing to barebox ``/dev/mmcX.boot0`` and +``/dev/mmcX.boot1`` respectively or from a booted operating system. Boot source selection --------------------- diff --git a/Documentation/user/booting-linux.rst b/Documentation/user/booting-linux.rst index 12cd505e71..983b56deef 100644 --- a/Documentation/user/booting-linux.rst +++ b/Documentation/user/booting-linux.rst @@ -158,7 +158,7 @@ Bootloader Spec barebox supports booting according to the bootloader spec: -http://www.freedesktop.org/wiki/Specifications/BootLoaderSpec/ +https://systemd.io/BOOT_LOADER_SPECIFICATION/ It follows another philosophy than the :ref:`boot_entries`. With Boot Entries booting is completely configured in the bootloader. Bootloader Spec Entries @@ -232,10 +232,6 @@ device where the entry is found on. This makes it possible to use the same rootf image on different devices without having to specify a different root= option each time. -Additionally to the options defined in the original spec, Barebox has the -``devicetree-overlay`` option. This is a string value that refer to overlays -that will be applied to the device tree before passing it to Linux. - Network boot ------------ @@ -1,5 +1,5 @@ VERSION = 2020 -PATCHLEVEL = 02 +PATCHLEVEL = 03 SUBLEVEL = 0 EXTRAVERSION = NAME = None diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 14538af53b..9fe458e0a3 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -113,6 +113,7 @@ obj-$(CONFIG_MACH_RPI_COMMON) += raspberry-pi/ obj-$(CONFIG_MACH_SABRELITE) += freescale-mx6-sabrelite/ obj-$(CONFIG_MACH_SABRESD) += freescale-mx6-sabresd/ obj-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += freescale-mx6sx-sabresdb/ +obj-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += sama5d27-giantboard/ obj-$(CONFIG_MACH_SAMA5D27_SOM1) += sama5d27-som1/ obj-$(CONFIG_MACH_SAMA5D3XEK) += sama5d3xek/ obj-$(CONFIG_MACH_SAMA5D3_XPLAINED) += sama5d3_xplained/ diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c index c16316d4a1..95159bbbb1 100644 --- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c @@ -130,7 +130,7 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) - imx25_barebox_boot_nand_external(0); + imx25_barebox_boot_nand_external(); out: imx25_barebox_entry(NULL); diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index ab5235f7f0..4bb41b0f42 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -135,7 +135,7 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint r |= 0x1 << 28; writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - imx35_barebox_boot_nand_external(0); + imx35_barebox_boot_nand_external(); } out: diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c index 0d7cfb618c..60dd567298 100644 --- a/arch/arm/boards/guf-cupid/lowlevel.c +++ b/arch/arm/boards/guf-cupid/lowlevel.c @@ -308,7 +308,7 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint r0 |= 0x1 << 28; writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - imx35_barebox_boot_nand_external(0); + imx35_barebox_boot_nand_external(); } out: diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c index 20f48be7dd..3ae70eca30 100644 --- a/arch/arm/boards/guf-neso/lowlevel.c +++ b/arch/arm/boards/guf-neso/lowlevel.c @@ -89,7 +89,7 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) - imx27_barebox_boot_nand_external(0); + imx27_barebox_boot_nand_external(); out: imx27_barebox_entry(NULL); diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c index f79cd91640..6c34944f74 100644 --- a/arch/arm/boards/karo-tx25/lowlevel.c +++ b/arch/arm/boards/karo-tx25/lowlevel.c @@ -74,7 +74,24 @@ static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl, writel(esdctl, esdctlreg); } -static void __bare_init karo_tx25_common_init(void *fdt) +extern char __dtb_imx25_karo_tx25_start[]; + +static void __noreturn karo_tx25_start(void) +{ + void *fdt; + + fdt = __dtb_imx25_karo_tx25_start + get_runtime_offset(); + + imx25_barebox_entry(fdt); +} + +static void __noreturn karo_tx25_load_nand(void) +{ + imx25_nand_load_image(); + karo_tx25_start(); +} + +static void __bare_init karo_tx25_common_init(void) { uint32_t r; @@ -138,7 +155,7 @@ static void __bare_init karo_tx25_common_init(void *fdt) /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); if (r > 0x80000000 && r < 0xa0000000) - goto out; + karo_tx25_start(); /* set to 3.3v SDRAM */ writel(0x800, MX25_IOMUXC_BASE_ADDR + 0x454); @@ -156,21 +173,12 @@ static void __bare_init karo_tx25_common_init(void *fdt) setup_sdram(0x80000000, ESDCTLVAL, ESDCFGVAL); setup_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL); - imx25_barebox_boot_nand_external(fdt); - -out: - imx25_barebox_entry(fdt); + imx25_nand_relocate_to_sdram(karo_tx25_load_nand); } -extern char __dtb_imx25_karo_tx25_start[]; - ENTRY_FUNCTION(start_imx25_karo_tx25, r0, r1, r2) { - void *fdt; - arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE); - fdt = __dtb_imx25_karo_tx25_start + get_runtime_offset(); - - karo_tx25_common_init(fdt); + karo_tx25_common_init(); } diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c index bd46df0962..40d39680fd 100644 --- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c @@ -77,7 +77,24 @@ static void sdram_init(int sdram) MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); } -static void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int sdram) +extern char __dtb_imx27_phytec_phycard_s_rdk_bb_start[]; + +static void __noreturn phytec_phycard_imx27_start(void) +{ + void *fdt; + + fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset(); + + imx27_barebox_entry(fdt); +} + +static void __noreturn phytec_phycard_imx27_load_nand(void) +{ + imx27_nand_load_image(); + phytec_phycard_imx27_start(); +} + +static noinline void __bare_init phytec_phycard_imx27_common_init(int sdram) { unsigned long r; @@ -92,7 +109,7 @@ static void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); if (r > 0xa0000000 && r < 0xc0000000) - imx27_barebox_entry(fdt); + phytec_phycard_imx27_start(); /* 399 MHz */ writel(IMX_PLL_PD(0) | @@ -117,29 +134,20 @@ static void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int sdram_init(sdram); - imx27_barebox_boot_nand_external(fdt); + imx27_nand_relocate_to_sdram(phytec_phycard_imx27_load_nand); + phytec_phycard_imx27_start(); } -extern char __dtb_imx27_phytec_phycard_s_rdk_bb_start[]; - ENTRY_FUNCTION(start_phytec_phycard_imx27_64mb, r0, r1, r2) { - void *fdt; - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE); - fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset(); - - phytec_phycard_imx27_common_init(fdt, PHYCARD_MICRON_64MB); + phytec_phycard_imx27_common_init(PHYCARD_MICRON_64MB); } ENTRY_FUNCTION(start_phytec_phycard_imx27_128mb, r0, r1, r2) { - void *fdt; - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE); - fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset(); - - phytec_phycard_imx27_common_init(fdt, PHYCARD_MICRON_128MB); + phytec_phycard_imx27_common_init(PHYCARD_MICRON_128MB); } diff --git a/arch/arm/boards/phytec-phycore-imx27/lowlevel.c b/arch/arm/boards/phytec-phycore-imx27/lowlevel.c index a9e296a0af..b3bebdb6df 100644 --- a/arch/arm/boards/phytec-phycore-imx27/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx27/lowlevel.c @@ -33,7 +33,24 @@ #define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) -static void __bare_init __naked noinline phytec_phycorce_imx27_common_init(void *fdt) +extern char __dtb_imx27_phytec_phycore_rdk_start[]; + +static void __noreturn phytec_phycore_imx27_start(void) +{ + void *fdt; + + fdt = __dtb_imx27_phytec_phycore_rdk_start + get_runtime_offset(); + + imx27_barebox_entry(fdt); +} + +static void __noreturn phytec_phycore_imx27_load_nand(void) +{ + imx27_nand_load_image(); + phytec_phycore_imx27_start(); +} + +static void __bare_init noinline phytec_phycore_imx27_common_init(void) { uint32_t r; int i; @@ -49,7 +66,7 @@ static void __bare_init __naked noinline phytec_phycorce_imx27_common_init(void /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); if (r > 0xa0000000 && r < 0xb0000000) - goto out; + phytec_phycore_imx27_start(); /* re-program the PLL prior(!) starting the SDRAM controller */ writel(MPCTL0_VAL, MX27_CCM_BASE_ADDR + MX27_MPCTL0); @@ -93,22 +110,13 @@ static void __bare_init __naked noinline phytec_phycorce_imx27_common_init(void ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) - imx27_barebox_boot_nand_external(fdt); - -out: - imx27_barebox_entry(fdt); + imx27_nand_relocate_to_sdram(phytec_phycore_imx27_load_nand); + phytec_phycore_imx27_start(); } -extern char __dtb_imx27_phytec_phycore_rdk_start[]; - ENTRY_FUNCTION(start_phytec_phycore_imx27, r0, r1, r2) { - void *fdt; - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE); - fdt = __dtb_imx27_phytec_phycore_rdk_start + get_runtime_offset(); - - phytec_phycorce_imx27_common_init(fdt); + phytec_phycore_imx27_common_init(); } diff --git a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c index b5f333987a..98e1e8711d 100644 --- a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c @@ -127,7 +127,7 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint #endif if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) - imx31_barebox_boot_nand_external(0); + imx31_barebox_boot_nand_external(); else imx31_barebox_entry(NULL); } diff --git a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c index b80dafec16..9768009be8 100644 --- a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c @@ -186,7 +186,7 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint r |= 0x1 << 28; writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - imx35_barebox_boot_nand_external(0); + imx35_barebox_boot_nand_external(); } out: diff --git a/arch/arm/boards/sama5d27-giantboard/Makefile b/arch/arm/boards/sama5d27-giantboard/Makefile new file mode 100644 index 0000000000..b08c4a93ca --- /dev/null +++ b/arch/arm/boards/sama5d27-giantboard/Makefile @@ -0,0 +1 @@ +lwl-y += lowlevel.o diff --git a/arch/arm/boards/sama5d27-giantboard/lowlevel.c b/arch/arm/boards/sama5d27-giantboard/lowlevel.c new file mode 100644 index 0000000000..0236c424c1 --- /dev/null +++ b/arch/arm/boards/sama5d27-giantboard/lowlevel.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Ahmad Fatoum, Pengutronix + */ + +#include <common.h> +#include <init.h> + +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/at91_pmc_ll.h> + +#include <mach/hardware.h> +#include <mach/iomux.h> +#include <debug_ll.h> +#include <mach/at91_dbgu.h> + +/* PCK = 492MHz, MCK = 164MHz */ +#define MASTER_CLOCK 164000000 + +static inline void sama5d2_pmc_enable_periph_clock(int clk) +{ + at91_pmc_sam9x5_enable_periph_clock(IOMEM(SAMA5D2_BASE_PMC), clk); +} + +static void dbgu_init(void) +{ + unsigned mck = MASTER_CLOCK / 2; + + sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_PIOD); + + at91_mux_pio4_set_A_periph(IOMEM(SAMA5D2_BASE_PIOD), + pin_to_mask(AT91_PIN_PD3)); /* DBGU TXD */ + + sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_UART1); + + at91_dbgu_setup_ll(IOMEM(SAMA5D2_BASE_UART1), mck, 115200); + + putc_ll('>'); +} + +extern char __dtb_z_at91_sama5d27_giantboard_start[]; + +static noinline void giantboard_entry(void) +{ + void *fdt; + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + dbgu_init(); + + fdt = __dtb_z_at91_sama5d27_giantboard_start + get_runtime_offset(); + + barebox_arm_entry(SAMA5_DDRCS, SZ_128M, fdt); +} + +ENTRY_FUNCTION(start_sama5d27_giantboard, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + + arm_setup_stack(SAMA5D2_SRAM_BASE + SAMA5D2_SRAM_SIZE); + + giantboard_entry(); +} diff --git a/arch/arm/boards/sama5d27-som1/lowlevel.c b/arch/arm/boards/sama5d27-som1/lowlevel.c index 7df5a4772d..62d35be912 100644 --- a/arch/arm/boards/sama5d27-som1/lowlevel.c +++ b/arch/arm/boards/sama5d27-som1/lowlevel.c @@ -22,8 +22,10 @@ /* PCK = 492MHz, MCK = 164MHz */ #define MASTER_CLOCK 164000000 -#define sama5d2_pmc_enable_periph_clock(clk) \ - at91_pmc_sam9x5_enable_periph_clock(IOMEM(SAMA5D2_BASE_PMC), clk) +static inline void sama5d2_pmc_enable_periph_clock(int clk) +{ + at91_pmc_sam9x5_enable_periph_clock(IOMEM(SAMA5D2_BASE_PMC), clk); +} static void ek_turn_led(unsigned color) { @@ -63,14 +65,10 @@ static void ek_dbgu_init(void) extern char __dtb_z_at91_sama5d27_som1_ek_start[]; -ENTRY_FUNCTION(start_sama5d27_som1_ek, r0, r1, r2) +static noinline void som1_entry(void) { void *fdt; - arm_cpu_lowlevel_init(); - - arm_setup_stack(SAMA5D2_SRAM_BASE + SAMA5D2_SRAM_SIZE - 16); - if (IS_ENABLED(CONFIG_DEBUG_LL)) ek_dbgu_init(); @@ -79,3 +77,12 @@ ENTRY_FUNCTION(start_sama5d27_som1_ek, r0, r1, r2) ek_turn_led(RGB_LED_GREEN); barebox_arm_entry(SAMA5_DDRCS, SZ_128M, fdt); } + +ENTRY_FUNCTION(start_sama5d27_som1_ek, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + + arm_setup_stack(SAMA5D2_SRAM_BASE + SAMA5D2_SRAM_SIZE); + + som1_entry(); +} diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S index 3b52644e43..203a4afc47 100644 --- a/arch/arm/cpu/lowlevel.S +++ b/arch/arm/cpu/lowlevel.S @@ -57,8 +57,10 @@ THUMB( orr r12, r12, #PSR_T_BIT ) bic r12, r12, #(CR_M | CR_C | CR_B) bic r12, r12, #(CR_S | CR_R | CR_V) +#ifndef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND /* enable instruction cache */ orr r12, r12, #CR_I +#endif #if __LINUX_ARM_ARCH__ >= 6 orr r12, r12, #CR_U diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b1c9a2c790..ddfe64e83b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -138,6 +138,7 @@ lwl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \ lwl-dtb-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o lwl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o lwl-dtb-$(CONFIG_MACH_SAMA5D27_SOM1) += at91-sama5d27_som1_ek.dtb.o +lwl-dtb-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += at91-sama5d27_giantboard.dtb.o lwl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o lwl-dtb-$(CONFIG_MACH_XILINX_ZCU104) += zynqmp-zcu104-revA.dtb.o diff --git a/arch/arm/dts/at91-sama5d27_giantboard.dts b/arch/arm/dts/at91-sama5d27_giantboard.dts new file mode 100644 index 0000000000..940379e430 --- /dev/null +++ b/arch/arm/dts/at91-sama5d27_giantboard.dts @@ -0,0 +1,299 @@ +// SPDX-License-Identifer: GPL-2.0-or-later OR X11 +/* + * at91-sama5d27_giantboard.dts - Device Tree file for SAMA5D27 Giant Board + * + * Copyright (c) 2017, Microchip Technology Inc. + * 2016 Nicolas Ferre <nicolas.ferre@atmel.com> + * 2017 Cristian Birsan <cristian.birsan@microchip.com> + * 2017 Claudiu Beznea <claudiu.beznea@microchip.com> + * 2019 Ahmad Fatoum <a.fatoum@pengutronix.de> + */ + +/dts-v1/; + +#include <arm/sama5d2.dtsi> +#include <arm/sama5d2-pinfunc.h> +#include <dt-bindings/mfd/atmel-flexcom.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/regulator/active-semi,8945a-regulator.h> + +/ { + model = "Giant Board"; + compatible = "groboards,sama5d27-giantboard", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + + chosen { + stdout-path = &uart1; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + + orange { + label = "orange"; + gpios = <&pioA PIN_PA6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + }; + + memory { + reg = <0x20000000 0x8000000>; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&main_xtal { + clock-frequency = <24000000>; +}; + +&usb0 { + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0_default>; + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&shutdown_controller { + atmel,shdwc-debouncer = <976>; + atmel,wakeup-rtc-timer; + + input@0 { + reg = <0>; + atmel,wakeup-type = "low"; + }; +}; + +&watchdog { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + dmas = <0>, <0>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + dmas = <0>, <0>; + i2c-sda-hold-time-ns = <350>; + status = "okay"; + + pmic@5b { + compatible = "active-semi,act8945a"; + reg = <0x5b>; + active-semi,vsel-low; + + regulators { + vdd_1v8_reg: REG_DCDC1 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>, + <ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt=<1850000>; + regulator-suspend-max-microvolt=<1850000>; + regulator-changeable-in-suspend; + regulator-mode=<ACT8945A_REGULATOR_MODE_LOWPOWER>; + }; + }; + + vdd_1v2_reg: REG_DCDC2 { + regulator-name = "VDD_1V2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>, + <ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_3v3_reg: REG_DCDC3 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>, + <ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_fuse_reg: REG_LDO1 { + regulator-name = "VDD_FUSE"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>, + <ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_3v3_lp_reg: REG_LDO2 { + regulator-name = "VDD_3V3_LP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>, + <ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_led_reg: REG_LDO3 { + regulator-name = "VDD_LED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>, + <ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_sdhc_1v8_reg: REG_LDO4 { + regulator-name = "VDD_SDHC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>, + <ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + charger { + compatible = "active-semi,act8945a-charger"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; + interrupt-parent = <&pioA>; + interrupts = <PIN_PB13 IRQ_TYPE_EDGE_RISING>; + + active-semi,chglev-gpios = <&pioA PIN_PA12 GPIO_ACTIVE_HIGH>; + active-semi,lbo-gpios = <&pioA PIN_PC8 GPIO_ACTIVE_LOW>; + active-semi,input-voltage-threshold-microvolt = <6600>; + active-semi,precondition-timeout = <40>; + active-semi,total-timeout = <3>; + }; + }; +}; + +&adc { + vddana-supply = <&vdd_3v3_reg>; + vref-supply = <&vdd_3v3_reg>; + status = "disabled"; +}; + +&pioA { + pinctrl_i2c0_default: i2c0_default { + pinmux = <PIN_PB31__TWD0>, + <PIN_PC0__TWCK0>; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PD4__TWD1>, + <PIN_PD5__TWCK1>; + bias-disable; + }; + + pinctrl_led_gpio_default: led_gpio_default { + pinmux = <PIN_PA6__GPIO>; + bias-pull-down; + }; + + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_data { + pinmux = <PIN_PA28__SDMMC1_CMD>, + <PIN_PA18__SDMMC1_DAT0>, + <PIN_PA19__SDMMC1_DAT1>, + <PIN_PA20__SDMMC1_DAT2>, + <PIN_PA21__SDMMC1_DAT3>; + bias-pull-up; + }; + + conf-ck_cd { + pinmux = <PIN_PA22__SDMMC1_CK>, + <PIN_PA30__SDMMC1_CD>; + bias-disable; + }; + }; + + pinctrl_spi0_default: spi0_default { + pinmux = <PIN_PA14__SPI0_SPCK>, + <PIN_PA15__SPI0_MOSI>, + <PIN_PA16__SPI0_MISO>; + bias-disable; + }; + + pinctrl_uart1_default: uart1_default { + pinmux = <PIN_PD2__URXD1>, + <PIN_PD3__UTXD1>; + bias-disable; + }; + + pinctrl_charger_chglev: charger_chglev { + pinmux = <PIN_PA12__GPIO>; + bias-disable; + }; + + pinctrl_charger_irq: charger_irq { + pinmux = <PIN_PB13__GPIO>; + bias-disable; + }; + + pinctrl_charger_lbo: charger_lbo { + pinmux = <PIN_PC8__GPIO>; + bias-pull-up; + }; +}; diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp151.dtsi index e416c89856..e416c89856 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi diff --git a/arch/arm/dts/stm32mp157a-dk1.dtsi b/arch/arm/dts/stm32mp157a-dk1.dtsi index 6be208f32e..baaf60b18f 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1.dtsi @@ -4,7 +4,7 @@ * Author: Alexandre Torgue <alexandre.torgue@st.com>. */ -#include "stm32mp157c.dtsi" +#include "stm32mp151.dtsi" #include <dt-bindings/gpio/gpio.h> / { diff --git a/arch/arm/lib64/armlinux.c b/arch/arm/lib64/armlinux.c index 31bd987f10..bcff770793 100644 --- a/arch/arm/lib64/armlinux.c +++ b/arch/arm/lib64/armlinux.c @@ -33,6 +33,8 @@ static int do_bootm_linux(struct image_data *data) { + const void *kernel_header = + data->os_fit ? data->fit_kernel : data->os_header; void (*fn)(unsigned long dtb, unsigned long x1, unsigned long x2, unsigned long x3); resource_size_t start, end; @@ -41,8 +43,8 @@ static int do_bootm_linux(struct image_data *data) int ret; void *fdt; - text_offset = le64_to_cpup(data->os_header + 8); - image_size = le64_to_cpup(data->os_header + 16); + text_offset = le64_to_cpup(kernel_header + 8); + image_size = le64_to_cpup(kernel_header+ 16); ret = memory_bank_first_find_space(&start, &end); if (ret) @@ -101,6 +103,12 @@ static struct image_handler aarch64_linux_handler = { .filetype = filetype_arm64_linux_image, }; +static struct image_handler aarch64_fit_handler = { + .name = "FIT image", + .bootm = do_bootm_linux, + .filetype = filetype_oftree, +}; + static int do_bootm_barebox(struct image_data *data) { void (*fn)(unsigned long x0, unsigned long x1, unsigned long x2, @@ -144,6 +152,9 @@ static int aarch64_register_image_handler(void) register_image_handler(&aarch64_linux_handler); register_image_handler(&aarch64_barebox_handler); + if (IS_ENABLED(CONFIG_FITIMAGE)) + register_image_handler(&aarch64_fit_handler); + return 0; } late_initcall(aarch64_register_image_handler); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 5267102bf9..eb14cd2c28 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -41,12 +41,16 @@ config AT91SAM926X_BOARD_INIT config AT91SAM9_SMC bool +config HAVE_AT91SAM9_RST + bool + config SOC_AT91SAM9 bool select CPU_ARM926T select AT91SAM9_SMC select CLOCKSOURCE_ATMEL_PIT select PINCTRL + select HAVE_AT91SAM9_RST select HAVE_AT91_SMD select HAVE_AT91_USB_CLK select HAVE_AT91_UTMI @@ -54,6 +58,7 @@ config SOC_AT91SAM9 config SOC_SAMA5 bool + select HAVE_AT91SAM9_RST select CPU_V7 config SOC_SAMA5D2 @@ -582,6 +587,14 @@ config MACH_SAMA5D27_SOM1 help Select this if you are using Microchip's sama5d27 SoM evaluation kit +config MACH_SAMA5D27_GIANTBOARD + bool "Groboards SAMA5D27 Giant Board" + select SOC_SAMA5D2 + select OFDEVICE + select COMMON_CLK_OF_PROVIDER + help + Select this if you are using the Groboards sama5d27 Giantboard + endif comment "AT91 Board Options" diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 66d0b700f6..89aff54b8a 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -13,6 +13,7 @@ obj-y += at91sam9_reset.o obj-y += at91sam9g45_reset.o obj-$(CONFIG_AT91SAM9_SMC) += sam9_smc.o +obj-$(CONFIG_HAVE_AT91SAM9_RST) += at91sam9_rst.o # CPU-specific support obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o diff --git a/arch/arm/mach-at91/at91sam9_rst.c b/arch/arm/mach-at91/at91sam9_rst.c new file mode 100644 index 0000000000..8f03576e69 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9_rst.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Pengutronix, Ahmad Fatoum <a.fatoum@pengutronix.de> + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <restart.h> +#include <linux/clk.h> +#include <mach/at91_rstc.h> + +struct at91sam9x_rst { + struct restart_handler restart; + void __iomem *base; +}; + +static void __noreturn at91sam9x_restart_soc(struct restart_handler *rst) +{ + struct at91sam9x_rst *priv = container_of(rst, struct at91sam9x_rst, restart); + + writel(AT91_RSTC_PROCRST + | AT91_RSTC_PERRST + | AT91_RSTC_EXTRST + | AT91_RSTC_KEY, + priv->base + AT91_RSTC_CR); + + hang(); +} + +static int at91sam9x_rst_probe(struct device_d *dev) +{ + struct at91sam9x_rst *priv; + struct resource *iores; + struct clk *clk; + + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + dev_err(dev, "could not get reset memory region\n"); + return PTR_ERR(iores); + } + + priv = xzalloc(sizeof(*priv)); + priv->base = IOMEM(iores->start); + + clk = clk_get(dev, NULL); + if (IS_ERR(clk)) { + release_region(iores); + free(priv); + return PTR_ERR(clk); + } + + clk_enable(clk); + + priv->restart.name = "at91sam9x-rst"; + priv->restart.restart = at91sam9x_restart_soc; + + return restart_handler_register(&priv->restart); +} + +static const __maybe_unused struct of_device_id at91sam9x_rst_dt_ids[] = { + { .compatible = "atmel,at91sam9g45-rstc", }, + { .compatible = "atmel,sama5d3-rstc", }, + { /* sentinel */ }, +}; + +static struct driver_d at91sam9x_rst_driver = { + .name = "at91sam9x-rst", + .of_compatible = DRV_OF_COMPAT(at91sam9x_rst_dt_ids), + .probe = at91sam9x_rst_probe, +}; +device_platform_driver(at91sam9x_rst_driver); diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c index c4d61aa786..123589c071 100644 --- a/arch/arm/mach-imx/external-nand-boot.c +++ b/arch/arm/mach-imx/external-nand-boot.c @@ -134,12 +134,13 @@ static noinline void __bare_init imx_nandboot_get_page(void *regs, int v1, imx_nandboot_send_page(regs, v1, NFC_OUTPUT, pagesize_2k); } -static void __bare_init imx_nand_load_image(void *dest, int v1, int size, +static void __bare_init imx_nand_load_image(void *dest, int v1, void __iomem *base, int pagesize_2k) { u32 tmp, page, block, blocksize, pagesize, badblocks; int bbt = 0; void *regs, *spare0; + int size = *(uint32_t *)(dest + 0x2c); if (pagesize_2k) { pagesize = 2048; @@ -239,143 +240,188 @@ static void __bare_init imx_nand_load_image(void *dest, int v1, int size, } } -static void BARE_INIT_FUNCTION(imx25_nand_load_image)(void *dest, int size, - void __iomem *base, int pagesize_2k) +void BARE_INIT_FUNCTION(imx25_nand_load_image)(void) { - imx_nand_load_image(dest, 0, size, base, pagesize_2k); + void *sdram = (void *)MX25_CSD0_BASE_ADDR; + void __iomem *nfc_base = IOMEM(MX25_NFC_BASE_ADDR); + bool pagesize_2k; + + if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 8)) + pagesize_2k = true; + else + pagesize_2k = false; + + imx_nand_load_image(sdram, 0, nfc_base, pagesize_2k); } -static void BARE_INIT_FUNCTION(imx27_nand_load_image)(void *dest, int size, - void __iomem *base, int pagesize_2k) +void BARE_INIT_FUNCTION(imx27_nand_load_image)(void) { - imx_nand_load_image(dest, 1, size, base, pagesize_2k); + void *sdram = (void *)MX27_CSD0_BASE_ADDR; + void __iomem *nfc_base = IOMEM(MX27_NFC_BASE_ADDR); + bool pagesize_2k; + + if (readl(MX27_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5)) + pagesize_2k = true; + else + pagesize_2k = false; + + imx_nand_load_image(sdram, 1, nfc_base, pagesize_2k); } -static void BARE_INIT_FUNCTION(imx31_nand_load_image)(void *dest, int size, - void __iomem *base, int pagesize_2k) +void BARE_INIT_FUNCTION(imx31_nand_load_image)(void) { - imx_nand_load_image(dest, 1, size, base, pagesize_2k); + void *sdram = (void *)MX31_CSD0_BASE_ADDR; + void __iomem *nfc_base = IOMEM(MX31_NFC_BASE_ADDR); + bool pagesize_2k; + + if (readl(MX31_CCM_BASE_ADDR + MX31_CCM_RCSR) & MX31_RCSR_NFMS) + pagesize_2k = true; + else + pagesize_2k = false; + + imx_nand_load_image(sdram, 1, nfc_base, pagesize_2k); } -static void BARE_INIT_FUNCTION(imx35_nand_load_image)(void *dest, int size, - void __iomem *base, int pagesize_2k) +void BARE_INIT_FUNCTION(imx35_nand_load_image)(void) { - imx_nand_load_image(dest, 0, size, base, pagesize_2k); + void *sdram = (void *)MX35_CSD0_BASE_ADDR; + void __iomem *nfc_base = IOMEM(MX35_NFC_BASE_ADDR); + bool pagesize_2k; + + if (readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR) & (1 << 8)) + pagesize_2k = true; + else + pagesize_2k = false; + + imx_nand_load_image(sdram, 0, nfc_base, pagesize_2k); } -static inline int imx25_pagesize_2k(void) +/* + * relocate_to_sdram - move ourselves out of NFC SRAM + * + * @nfc_base: base address of the NFC controller + * @sdram: SDRAM base address where we move ourselves to + * @fn: Function we continue with when running in SDRAM + * + * This function moves ourselves out of NFC SRAM to SDRAM. In case we a currently + * not running in NFC SRAM this function returns. If running in NFC SRAM, this + * function will not return, but call @fn instead. + */ +static void BARE_INIT_FUNCTION(relocate_to_sdram)(unsigned long nfc_base, + unsigned long sdram, + void __noreturn (*fn)(void)) { - if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 8)) - return 1; - else - return 0; + unsigned long __fn; + u32 r; + u32 *src, *trg; + int i; + + /* skip NAND boot if not running from NFC space */ + r = get_pc(); + if (r < nfc_base || r > nfc_base + 0x800) + return; + + src = (unsigned int *)nfc_base; + trg = (unsigned int *)sdram; + + /* + * Copy initial binary portion from NFC SRAM to beginning of + * SDRAM + */ + for (i = 0; i < 0x800 / sizeof(int); i++) + *trg++ = *src++; + + /* The next function we jump to */ + __fn = (unsigned long)fn; + /* mask out TEXT_BASE */ + __fn &= 0x7ff; + /* + * and add sdram base instead where we copied the initial + * binary above + */ + __fn += sdram; + + fn = (void *)__fn; + + fn(); } -static inline int imx27_pagesize_2k(void) +void BARE_INIT_FUNCTION(imx25_nand_relocate_to_sdram)(void __noreturn (*fn)(void)) { - if (readl(MX27_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5)) - return 1; - else - return 0; + unsigned long nfc_base = MX25_NFC_BASE_ADDR; + unsigned long sdram = MX25_CSD0_BASE_ADDR; + + relocate_to_sdram(nfc_base, sdram, fn); } -static inline int imx31_pagesize_2k(void) +static void __noreturn BARE_INIT_FUNCTION(imx25_boot_nand_external_cont)(void) { - if (readl(MX31_CCM_BASE_ADDR + MX31_CCM_RCSR) & MX31_RCSR_NFMS) - return 1; - else - return 0; + imx25_nand_load_image(); + imx25_barebox_entry(NULL); } -static inline int imx35_pagesize_2k(void) +void __noreturn BARE_INIT_FUNCTION(imx25_barebox_boot_nand_external)(void) { - if (readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR) & (1 << 8)) - return 1; - else - return 0; + imx25_nand_relocate_to_sdram(imx25_boot_nand_external_cont); + imx25_barebox_entry(NULL); } -/* - * SoC specific entries for booting in external NAND mode. To be called from - * the board specific entry code. This is safe to call even if not booting from - * NAND. In this case the booting is continued without loading an image from - * NAND. This function needs a stack to be set up. - */ +void BARE_INIT_FUNCTION(imx27_nand_relocate_to_sdram)(void __noreturn (*fn)(void)) +{ + unsigned long nfc_base = MX27_NFC_BASE_ADDR; + unsigned long sdram = MX27_CSD0_BASE_ADDR; + + relocate_to_sdram(nfc_base, sdram, fn); +} + +static void __noreturn BARE_INIT_FUNCTION(imx27_boot_nand_external_cont)(void) +{ + imx27_nand_load_image(); + imx27_barebox_entry(NULL); +} + +void __noreturn BARE_INIT_FUNCTION(imx27_barebox_boot_nand_external)(void) +{ + imx27_nand_relocate_to_sdram(imx27_boot_nand_external_cont); + imx27_barebox_entry(NULL); +} -#define DEFINE_EXTERNAL_NAND_ENTRY(soc) \ - \ -static void __noreturn BARE_INIT_FUNCTION(imx##soc##_boot_nand_external_cont) \ - (void *boarddata) \ -{ \ - unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \ - void *sdram = (void *)MX##soc##_CSD0_BASE_ADDR; \ - uint32_t image_size, r; \ - \ - image_size = *(uint32_t *)(sdram + 0x2c); \ - \ - r = get_cr(); \ - r |= CR_I; \ - set_cr(r); \ - \ - imx##soc##_nand_load_image(sdram, \ - image_size, \ - (void *)nfc_base, \ - imx##soc##_pagesize_2k()); \ - \ - imx##soc##_barebox_entry(boarddata); \ -} \ - \ -void __noreturn BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external) \ - (void *bd) \ -{ \ - unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \ - unsigned long sdram = MX##soc##_CSD0_BASE_ADDR; \ - unsigned long boarddata = (unsigned long)bd; \ - unsigned long __fn; \ - u32 r; \ - u32 *src, *trg; \ - int i; \ - void __noreturn (*fn)(void *); \ - \ - r = get_cr(); \ - r &= ~CR_I; \ - set_cr(r); \ - /* skip NAND boot if not running from NFC space */ \ - r = get_pc(); \ - if (r < nfc_base || r > nfc_base + 0x800) \ - imx##soc##_barebox_entry(bd); \ - \ - src = (unsigned int *)nfc_base; \ - trg = (unsigned int *)sdram; \ - \ - /* \ - * Copy initial binary portion from NFC SRAM to beginning of \ - * SDRAM \ - */ \ - for (i = 0; i < 0x800 / sizeof(int); i++) \ - *trg++ = *src++; \ - \ - /* The next function we jump to */ \ - __fn = (unsigned long)imx##soc##_boot_nand_external_cont; \ - /* mask out TEXT_BASE */ \ - __fn &= 0x7ff; \ - /* \ - * and add sdram base instead where we copied the initial \ - * binary above \ - */ \ - __fn += sdram; \ - \ - fn = (void *)__fn; \ - \ - if (boarddata > nfc_base && boarddata < nfc_base + SZ_512K) { \ - boarddata &= SZ_512K - 1; \ - boarddata += sdram; \ - } \ - \ - fn((void *)boarddata); \ +void BARE_INIT_FUNCTION(imx31_nand_relocate_to_sdram)(void __noreturn (*fn)(void)) +{ + unsigned long nfc_base = MX31_NFC_BASE_ADDR; + unsigned long sdram = MX31_CSD0_BASE_ADDR; + + relocate_to_sdram(nfc_base, sdram, fn); +} + +static void __noreturn BARE_INIT_FUNCTION(imx31_boot_nand_external_cont)(void) +{ + imx31_nand_load_image(); + imx31_barebox_entry(NULL); } -DEFINE_EXTERNAL_NAND_ENTRY(25) -DEFINE_EXTERNAL_NAND_ENTRY(27) -DEFINE_EXTERNAL_NAND_ENTRY(31) -DEFINE_EXTERNAL_NAND_ENTRY(35) +void __noreturn BARE_INIT_FUNCTION(imx31_barebox_boot_nand_external)(void) +{ + imx31_nand_relocate_to_sdram(imx31_boot_nand_external_cont); + imx31_barebox_entry(NULL); +} + +void BARE_INIT_FUNCTION(imx35_nand_relocate_to_sdram)(void __noreturn (*fn)(void)) +{ + unsigned long nfc_base = MX35_NFC_BASE_ADDR; + unsigned long sdram = MX35_CSD0_BASE_ADDR; + + relocate_to_sdram(nfc_base, sdram, fn); +} + +static void __noreturn BARE_INIT_FUNCTION(imx35_boot_nand_external_cont)(void) +{ + imx35_nand_load_image(); + imx35_barebox_entry(NULL); +} + +void __noreturn BARE_INIT_FUNCTION(imx35_barebox_boot_nand_external)(void) +{ + imx35_nand_relocate_to_sdram(imx35_boot_nand_external_cont); + imx35_barebox_entry(NULL); +} diff --git a/arch/arm/mach-imx/include/mach/imx-nand.h b/arch/arm/mach-imx/include/mach/imx-nand.h index 0adba0989a..f34799a011 100644 --- a/arch/arm/mach-imx/include/mach/imx-nand.h +++ b/arch/arm/mach-imx/include/mach/imx-nand.h @@ -3,11 +3,20 @@ #include <linux/mtd/mtd.h> -void imx21_barebox_boot_nand_external(void *boarddata); -void imx25_barebox_boot_nand_external(void *boarddata); -void imx27_barebox_boot_nand_external(void *boarddata); -void imx31_barebox_boot_nand_external(void *boarddata); -void imx35_barebox_boot_nand_external(void *boarddata); +void imx25_nand_load_image(void); +void imx27_nand_load_image(void); +void imx31_nand_load_image(void); +void imx35_nand_load_image(void); + +void imx25_nand_relocate_to_sdram(void __noreturn (*fn)(void)); +void imx27_nand_relocate_to_sdram(void __noreturn (*fn)(void)); +void imx31_nand_relocate_to_sdram(void __noreturn (*fn)(void)); +void imx35_nand_relocate_to_sdram(void __noreturn (*fn)(void)); + +void imx25_barebox_boot_nand_external(void); +void imx27_barebox_boot_nand_external(void); +void imx31_barebox_boot_nand_external(void); +void imx35_barebox_boot_nand_external(void); void imx_nand_set_layout(int writesize, int datawidth); struct imx_nand_platform_data { diff --git a/commands/boot.c b/commands/boot.c index aeaba3992e..aaa20faae9 100644 --- a/commands/boot.c +++ b/commands/boot.c @@ -97,7 +97,7 @@ static int do_boot(int argc, char *argv[]) bootentries_for_each_entry(entries, entry) { ret = boot_entry(entry, verbose, dryrun); if (!ret) - break; + goto out; } bootentries_free(entries); diff --git a/common/block.c b/common/block.c index 97cf5dc4de..02be80d7cc 100644 --- a/common/block.c +++ b/common/block.c @@ -36,7 +36,7 @@ struct chunk { struct list_head list; }; -#define BUFSIZE (PAGE_SIZE * 4) +#define BUFSIZE (PAGE_SIZE * 16) static int writebuffer_io_len(struct block_device *blk, struct chunk *chunk) { @@ -161,6 +161,14 @@ static int block_cache(struct block_device *blk, int block) dev_dbg(blk->dev, "%s: %d to %d\n", __func__, chunk->block_start, chunk->num); + if (chunk->block_start * BLOCKSIZE(blk) >= blk->discard_start && + chunk->block_start * BLOCKSIZE(blk) + writebuffer_io_len(blk, chunk) + <= blk->discard_start + blk->discard_size) { + memset(chunk->data, 0, writebuffer_io_len(blk, chunk)); + list_add(&chunk->list, &blk->buffered_blocks); + return 0; + } + ret = blk->ops->read(blk, chunk->data, chunk->block_start, writebuffer_io_len(blk, chunk)); if (ret) { @@ -337,11 +345,23 @@ static int block_op_flush(struct cdev *cdev) { struct block_device *blk = cdev->priv; + blk->discard_start = blk->discard_size = 0; + return writebuffer_flush(blk); } static int block_op_close(struct cdev *cdev) __alias(block_op_flush); +static int block_op_discard_range(struct cdev *cdev, loff_t count, loff_t offset) +{ + struct block_device *blk = cdev->priv; + + blk->discard_start = offset; + blk->discard_size = count; + + return 0; +} + static struct cdev_operations block_ops = { .read = block_op_read, #ifdef CONFIG_BLOCK_WRITE @@ -349,6 +369,7 @@ static struct cdev_operations block_ops = { #endif .close = block_op_close, .flush = block_op_flush, + .discard_range = block_op_discard_range, }; int blockdevice_register(struct block_device *blk) @@ -370,7 +391,7 @@ int blockdevice_register(struct block_device *blk) dev_dbg(blk->dev, "rdbufsize: %d blockbits: %d blkmask: 0x%08x\n", blk->rdbufsize, blk->blockbits, blk->blkmask); - for (i = 0; i < 32; i++) { + for (i = 0; i < 8; i++) { struct chunk *chunk = xzalloc(sizeof(*chunk)); chunk->data = dma_alloc(BUFSIZE); chunk->num = i; diff --git a/drivers/base/regmap/Makefile b/drivers/base/regmap/Makefile index 4dc3d8c510..ab2387037d 100644 --- a/drivers/base/regmap/Makefile +++ b/drivers/base/regmap/Makefile @@ -1 +1,2 @@ -obj-y += regmap.o
\ No newline at end of file +obj-y += regmap.o +obj-y += regmap-mmio.o diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h index 52df5290a1..5b19459828 100644 --- a/drivers/base/regmap/internal.h +++ b/drivers/base/regmap/internal.h @@ -1,5 +1,10 @@ +#ifndef REGMAP_INTERNAL_H_ +#define REGMAP_INTERNAL_H_ #include <linux/list.h> +#include <driver.h> + +struct regmap_bus; struct regmap { struct device_d *dev; @@ -15,4 +20,6 @@ struct regmap { unsigned int max_register; struct cdev cdev; -};
\ No newline at end of file +}; + +#endif diff --git a/drivers/base/regmap/regmap-mmio.c b/drivers/base/regmap/regmap-mmio.c new file mode 100644 index 0000000000..f8d2cda843 --- /dev/null +++ b/drivers/base/regmap/regmap-mmio.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Register map access API - MMIO support +// +// Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + +#include <linux/clk.h> +#include <linux/err.h> +#include <io.h> +#include <regmap.h> + +#include "internal.h" + +struct regmap_mmio_context { + void __iomem *regs; + unsigned val_bytes; + + struct clk *clk; + + void (*reg_write)(struct regmap_mmio_context *ctx, + unsigned int reg, unsigned int val); + unsigned int (*reg_read)(struct regmap_mmio_context *ctx, + unsigned int reg); +}; + +static int regmap_mmio_regbits_check(size_t reg_bits) +{ + switch (reg_bits) { + case 8: + case 16: + case 32: +#ifdef CONFIG_64BIT + case 64: +#endif + return 0; + default: + return -EINVAL; + } +} + +static int regmap_mmio_get_min_stride(size_t val_bits) +{ + int min_stride; + + switch (val_bits) { + case 8: + /* The core treats 0 as 1 */ + min_stride = 0; + return 0; + case 16: + min_stride = 2; + break; + case 32: + min_stride = 4; + break; +#ifdef CONFIG_64BIT + case 64: + min_stride = 8; + break; +#endif + default: + return -EINVAL; + } + + return min_stride; +} + +static void regmap_mmio_write8(struct regmap_mmio_context *ctx, + unsigned int reg, + unsigned int val) +{ + writeb(val, ctx->regs + reg); +} + +static void regmap_mmio_write16le(struct regmap_mmio_context *ctx, + unsigned int reg, + unsigned int val) +{ + writew(val, ctx->regs + reg); +} + +static void regmap_mmio_write32le(struct regmap_mmio_context *ctx, + unsigned int reg, + unsigned int val) +{ + writel(val, ctx->regs + reg); +} + +#ifdef CONFIG_64BIT +static void regmap_mmio_write64le(struct regmap_mmio_context *ctx, + unsigned int reg, + unsigned int val) +{ + writeq(val, ctx->regs + reg); +} +#endif + +static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val) +{ + struct regmap_mmio_context *ctx = context; + int ret; + + ret = clk_enable(ctx->clk); + if (ret < 0) + return ret; + + ctx->reg_write(ctx, reg, val); + + clk_disable(ctx->clk); + + return 0; +} + +static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx, + unsigned int reg) +{ + return readb(ctx->regs + reg); +} + +static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx, + unsigned int reg) +{ + return readw(ctx->regs + reg); +} + +static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx, + unsigned int reg) +{ + return readl(ctx->regs + reg); +} + +#ifdef CONFIG_64BIT +static unsigned int regmap_mmio_read64le(struct regmap_mmio_context *ctx, + unsigned int reg) +{ + return readq(ctx->regs + reg); +} +#endif + +static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val) +{ + struct regmap_mmio_context *ctx = context; + int ret; + + ret = clk_enable(ctx->clk); + if (ret < 0) + return ret; + + *val = ctx->reg_read(ctx, reg); + + clk_disable(ctx->clk); + + return 0; +} + +static const struct regmap_bus regmap_mmio = { + .reg_write = regmap_mmio_write, + .reg_read = regmap_mmio_read, +}; + +static struct regmap_mmio_context *regmap_mmio_gen_context(void __iomem *regs, + const struct regmap_config *config) +{ + struct regmap_mmio_context *ctx; + int min_stride; + int ret; + + ret = regmap_mmio_regbits_check(config->reg_bits); + if (ret) + return ERR_PTR(ret); + + if (config->pad_bits) + return ERR_PTR(-EINVAL); + + min_stride = regmap_mmio_get_min_stride(config->val_bits); + if (min_stride < 0) + return ERR_PTR(min_stride); + + if (config->reg_stride < min_stride) + return ERR_PTR(-EINVAL); + + ctx = xzalloc(sizeof(*ctx)); + + ctx->regs = regs; + ctx->val_bytes = config->val_bits / 8; + + switch (config->val_bits) { + case 8: + ctx->reg_read = regmap_mmio_read8; + ctx->reg_write = regmap_mmio_write8; + break; + case 16: + ctx->reg_read = regmap_mmio_read16le; + ctx->reg_write = regmap_mmio_write16le; + break; + case 32: + ctx->reg_read = regmap_mmio_read32le; + ctx->reg_write = regmap_mmio_write32le; + break; + default: + ret = -EINVAL; + goto err_free; + } + + return ctx; + +err_free: + kfree(ctx); + + return ERR_PTR(ret); +} + +struct regmap *regmap_init_mmio_clk(struct device_d *dev, + const char *clk_id, + void __iomem *regs, + const struct regmap_config *config) +{ + struct regmap_mmio_context *ctx; + + ctx = regmap_mmio_gen_context(regs, config); + if (IS_ERR(ctx)) + return ERR_CAST(ctx); + + if (clk_id) { + ctx->clk = clk_get(dev, clk_id); + if (IS_ERR(ctx->clk)) { + kfree(ctx); + return ERR_CAST(ctx->clk); + } + } + + return regmap_init(dev, ®map_mmio, ctx, config); +} + +struct regmap *of_regmap_init_mmio_clk(struct device_node *np, + const char *clk_id, + void __iomem *regs, + const struct regmap_config *config) +{ + struct regmap_mmio_context *ctx; + + ctx = regmap_mmio_gen_context(regs, config); + if (IS_ERR(ctx)) + return ERR_CAST(ctx); + + if (clk_id) { + ctx->clk = of_clk_get_by_name(np, clk_id); + if (IS_ERR(ctx->clk)) { + kfree(ctx); + return ERR_CAST(ctx->clk); + } + } + + return regmap_init(NULL, ®map_mmio, ctx, config); +} + +int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk) +{ + struct regmap_mmio_context *ctx = map->bus_context; + + ctx->clk = clk; + + return 0; +} + +void regmap_mmio_detach_clk(struct regmap *map) +{ + struct regmap_mmio_context *ctx = map->bus_context; + + ctx->clk = NULL; +} diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index ea3304bc7c..b27ad6d249 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -84,12 +84,14 @@ void clk_disable(struct clk *clk) if (!clk->enable_count) return; + if (clk->enable_count == 1 && clk->flags & CLK_IS_CRITICAL) { + pr_warn("Disabling critical clock %s\n", clk->name); + return; + } + clk->enable_count--; if (!clk->enable_count) { - if (clk->flags & CLK_IS_CRITICAL) - return; - if (clk->ops->disable) clk->ops->disable(clk); @@ -282,6 +284,9 @@ int clk_register(struct clk *clk) list_add_tail(&clk->list, &clks); + if (clk->flags & CLK_IS_CRITICAL) + clk_enable(clk); + return 0; } @@ -627,12 +632,40 @@ int of_clk_init(struct device_node *root, const struct of_device_id *matches) } #endif +static const char *clk_hw_stat(struct clk *clk) +{ + if (clk->ops->is_enabled) { + if (clk->ops->is_enabled(clk)) + return "enabled"; + else + return "disabled"; + } + + if (!clk->ops->enable) + return "always enabled"; + + return "unknown"; +} + static void dump_one(struct clk *clk, int verbose, int indent) { struct clk *c; + int enabled = clk_is_enabled(clk); + const char *hwstat, *stat; + + hwstat = clk_hw_stat(clk); + + if (enabled == 0) + stat = "disabled"; + else + stat = "enabled"; + + printf("%*s%s (rate %lu, enable_count: %d, %s)\n", indent * 4, "", + clk->name, + clk_get_rate(clk), + clk->enable_count, + hwstat); - printf("%*s%s (rate %lu, %sabled)\n", indent * 4, "", clk->name, clk_get_rate(clk), - clk_is_enabled(clk) ? "en" : "dis"); if (verbose) { if (clk->num_parents > 1) { diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index cfa77360b3..27674af54c 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -86,7 +86,7 @@ static int gpioinfo_request(struct gpio_info *gi, const char *label) done: if (ret) - pr_err("_gpio_request: gpio-%ld (%s) status %d\n", + pr_err("_gpio_request: gpio-%td (%s) status %d\n", gi - gpio_desc, label ? : "?", ret); return ret; diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c index 8099419378..f1e6559d71 100644 --- a/drivers/mfd/syscon.c +++ b/drivers/mfd/syscon.c @@ -19,6 +19,7 @@ #include <xfuncs.h> #include <of_address.h> #include <linux/err.h> +#include <linux/clk.h> #include <mfd/syscon.h> @@ -31,34 +32,13 @@ struct syscon { struct regmap *regmap; }; -static int syscon_reg_write(void *context, unsigned int reg, - unsigned int val) -{ - struct syscon *syscon = context; - writel(val, syscon->base + reg); - return 0; -} - -static int syscon_reg_read(void *context, unsigned int reg, - unsigned int *val) -{ - struct syscon *syscon = context; - *val = readl(syscon->base + reg); - return 0; -} - -static const struct regmap_bus syscon_regmap_bus = { - .reg_write = syscon_reg_write, - .reg_read = syscon_reg_read, -}; - static const struct regmap_config syscon_regmap_config = { .reg_bits = 32, .val_bits = 32, .reg_stride = 4, }; -static struct syscon *of_syscon_register(struct device_node *np) +static struct syscon *of_syscon_register(struct device_node *np, bool check_clk) { int ret; struct syscon *syscon; @@ -79,10 +59,23 @@ static struct syscon *of_syscon_register(struct device_node *np) list_add_tail(&syscon->list, &syscon_list); - syscon->regmap = regmap_init(NULL, - &syscon_regmap_bus, - syscon, - &syscon_regmap_config); + syscon->regmap = of_regmap_init_mmio_clk(np, NULL, syscon->base, + &syscon_regmap_config); + + if (check_clk) { + struct clk *clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + /* clock is optional */ + if (ret != -ENOENT) + goto err_map; + } else { + ret = regmap_mmio_attach_clk(syscon->regmap, clk); + if (ret) + goto err_map; + } + } + return syscon; err_map: @@ -101,7 +94,7 @@ static struct syscon *node_to_syscon(struct device_node *np) } if (!syscon) - syscon = of_syscon_register(np); + syscon = of_syscon_register(np, true); if (IS_ERR(syscon)) return ERR_CAST(syscon); diff --git a/drivers/net/designware_stm32.c b/drivers/net/designware_stm32.c index 4c682a5dac..1e0cdfa695 100644 --- a/drivers/net/designware_stm32.c +++ b/drivers/net/designware_stm32.c @@ -57,12 +57,11 @@ static inline struct eqos_stm32 *to_stm32(struct eqos *eqos) return eqos->priv; } -enum { CLK_STMMACETH, CLK_MAX_RX, CLK_MAX_TX, CLK_SYSCFG, }; +enum { CLK_STMMACETH, CLK_MAX_RX, CLK_MAX_TX, }; static const struct clk_bulk_data stm32_clks[] = { [CLK_STMMACETH] = { .id = "stmmaceth" }, [CLK_MAX_RX] = { .id = "mac-clk-rx" }, [CLK_MAX_TX] = { .id = "mac-clk-tx" }, - [CLK_SYSCFG] = { .id = "syscfg-clk" }, }; static unsigned long eqos_get_csr_clk_rate_stm32(struct eqos *eqos) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index d4f411b4ad..2cd58df931 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -87,8 +87,8 @@ static int pcs_set_state(struct pinctrl_device *pdev, struct device_node *np) for (i = 0; i < rows; i++) { offset = be32_to_cpup(mux + index++); - mask = be32_to_cpup(mux + index++); val = be32_to_cpup(mux + index++); + mask = be32_to_cpup(mux + index++); reg = pcs->read(pcs->base + offset); reg &= ~mask; reg |= val; diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index 8874775f17..466bbe527b 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -406,6 +406,9 @@ static int usb_device_list_scan(void) if (ret) goto out; } + + /* Avoid hammering the HUB with port scans */ + mdelay(25); } out: diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 0a3aff3cf0..426ee9db0b 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -957,6 +957,8 @@ static int fastboot_handle_sparse(struct f_fastboot *f_fb, if (ret) goto out; } else { + discard_range(fd, retlen, pos); + pos = lseek(fd, pos, SEEK_SET); if (pos == -1) { ret = -errno; diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index 4c11e6580c..b84da5516c 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -1136,8 +1136,9 @@ fail2: musb_platform_exit(musb); fail1: - dev_err(musb->controller, - "musb_init_controller failed with status %d\n", status); + if (status != -EPROBE_DEFER) + dev_err(musb->controller, + "musb_init_controller failed with status %d\n", status); musb_free(musb); diff --git a/drivers/usb/musb/musb_dsps.c b/drivers/usb/musb/musb_dsps.c index 3b76b6cc61..d54a663e9d 100644 --- a/drivers/usb/musb/musb_dsps.c +++ b/drivers/usb/musb/musb_dsps.c @@ -39,7 +39,6 @@ #include <linux/barebox-wrapper.h> #include "musb_core.h" -#include "phy-am335x.h" static __maybe_unused struct of_device_id musb_dsps_dt_ids[]; @@ -217,10 +216,6 @@ static int dsps_musb_init(struct musb *musb) const struct dsps_musb_wrapper *wrp = glue->wrp; u32 rev, val, mode; - musb->xceiv = am335x_get_usb_phy(); - if (IS_ERR(musb->xceiv)) - return PTR_ERR(musb->xceiv); - /* Returns zero if e.g. not clocked */ rev = dsps_readl(musb->ctrl_base, wrp->revision); if (!rev) @@ -319,11 +314,13 @@ static int dsps_set_mode(void *ctx, enum usb_dr_mode mode) static int dsps_probe(struct device_d *dev) { - struct resource *iores; + struct resource *iores[2]; struct musb_hdrc_platform_data *pdata; struct musb_hdrc_config *config; struct device_node *dn = dev->device_node; const struct dsps_musb_wrapper *wrp; + struct device_node *phy_node; + struct device_d *phy_dev; struct dsps_glue *glue; int ret; @@ -337,6 +334,14 @@ static int dsps_probe(struct device_d *dev) return -ENODEV; } + phy_node = of_parse_phandle(dn, "phys", 0); + if (!phy_node) + return -ENODEV; + + phy_dev = of_find_device_by_node(phy_node); + if (!phy_dev || !phy_dev->priv) + return -EPROBE_DEFER; + /* allocate glue */ glue = kzalloc(sizeof(*glue), GFP_KERNEL); if (!glue) { @@ -349,17 +354,22 @@ static int dsps_probe(struct device_d *dev) pdata = &glue->pdata; - iores = dev_request_mem_resource(dev, 0); - if (IS_ERR(iores)) - return PTR_ERR(iores); - glue->musb.mregs = IOMEM(iores->start); + iores[0] = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores[0])) { + ret = PTR_ERR(iores[0]); + goto free_glue; + } + glue->musb.mregs = IOMEM(iores[0]->start); - iores = dev_request_mem_resource(dev, 1); - if (IS_ERR(iores)) - return PTR_ERR(iores); - glue->musb.ctrl_base = IOMEM(iores->start); + iores[1] = dev_request_mem_resource(dev, 1); + if (IS_ERR(iores[1])) { + ret = PTR_ERR(iores[1]); + goto release_iores0; + } + glue->musb.ctrl_base = IOMEM(iores[1]->start); glue->musb.controller = dev; + glue->musb.xceiv = phy_dev->priv; config = &glue->config; @@ -377,11 +387,24 @@ static int dsps_probe(struct device_d *dev) if (pdata->mode == MUSB_PORT_MODE_DUAL_ROLE) { ret = usb_register_otg_device(dev, dsps_set_mode, glue); if (ret) - return ret; + goto release_iores1; return 0; } - return musb_init_controller(&glue->musb, pdata); + ret = musb_init_controller(&glue->musb, pdata); + if (ret) + goto release_iores1; + + return 0; + +release_iores1: + release_region(iores[1]); +release_iores0: + release_region(iores[0]); +free_glue: + free(glue); + + return ret; } static const struct dsps_musb_wrapper am33xx_driver_data = { diff --git a/drivers/usb/musb/phy-am335x-control.c b/drivers/usb/musb/phy-am335x-control.c index c84525ec7e..41a3689ed3 100644 --- a/drivers/usb/musb/phy-am335x-control.c +++ b/drivers/usb/musb/phy-am335x-control.c @@ -109,15 +109,15 @@ struct phy_control *am335x_get_phy_control(struct device_d *dev) node = of_parse_phandle(dev->device_node, "ti,ctrl_mod", 0); if (!node) - return NULL; + return ERR_PTR(-ENOENT); dev = of_find_device_by_node(node); if (!dev) - return NULL; + return ERR_PTR(-EPROBE_DEFER); ctrl_usb = dev->priv; if (!ctrl_usb) - return NULL; + return ERR_PTR(-EPROBE_DEFER); return &ctrl_usb->phy_ctrl; } @@ -141,13 +141,17 @@ static int am335x_control_usb_probe(struct device_d *dev) ctrl_usb->dev = dev; iores = dev_request_mem_resource(dev, 0); - if (IS_ERR(iores)) - return PTR_ERR(iores); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); + goto free_ctrl; + } ctrl_usb->phy_reg = IOMEM(iores->start); iores = dev_request_mem_resource(dev, 1); - if (IS_ERR(iores)) - return PTR_ERR(iores); + if (IS_ERR(iores)) { + ret = PTR_ERR(iores); + goto release_resource; + } ctrl_usb->wkup = IOMEM(iores->start); spin_lock_init(&ctrl_usb->lock); @@ -155,6 +159,13 @@ static int am335x_control_usb_probe(struct device_d *dev) dev->priv = ctrl_usb; return 0; + +release_resource: + release_region(iores); +free_ctrl: + free(ctrl_usb); + + return 0; }; static struct driver_d am335x_control_driver = { diff --git a/drivers/usb/musb/phy-am335x.c b/drivers/usb/musb/phy-am335x.c index df31255d89..f2e870d7ee 100644 --- a/drivers/usb/musb/phy-am335x.c +++ b/drivers/usb/musb/phy-am335x.c @@ -5,7 +5,6 @@ #include <linux/err.h> #include "am35x-phy-control.h" #include "musb_core.h" -#include "phy-am335x.h" struct am335x_usbphy { void __iomem *base; @@ -14,13 +13,6 @@ struct am335x_usbphy { struct usb_phy phy; }; -static struct am335x_usbphy *am_usbphy; - -struct usb_phy *am335x_get_usb_phy(void) -{ - return &am_usbphy->phy; -} - static int am335x_init(struct usb_phy *phy) { struct am335x_usbphy *am_usbphy = container_of(phy, struct am335x_usbphy, phy); @@ -31,6 +23,7 @@ static int am335x_init(struct usb_phy *phy) static int am335x_phy_probe(struct device_d *dev) { + struct am335x_usbphy *am_usbphy; struct resource *iores; int ret; @@ -44,22 +37,27 @@ static int am335x_phy_probe(struct device_d *dev) am_usbphy->base = IOMEM(iores->start); am_usbphy->phy_ctrl = am335x_get_phy_control(dev); - if (!am_usbphy->phy_ctrl) - return -ENODEV; + if (IS_ERR(am_usbphy->phy_ctrl)) { + ret = PTR_ERR(am_usbphy->phy_ctrl); + goto err_release; + } am_usbphy->id = of_alias_get_id(dev->device_node, "phy"); if (am_usbphy->id < 0) { dev_err(dev, "Missing PHY id: %d\n", am_usbphy->id); - return am_usbphy->id; + ret = am_usbphy->id; + goto err_release; } am_usbphy->phy.init = am335x_init; - dev->priv = am_usbphy; + dev->priv = &am_usbphy->phy; dev_info(dev, "am_usbphy %p enabled\n", &am_usbphy->phy); return 0; +err_release: + release_region(iores); err_free: free(am_usbphy); diff --git a/drivers/usb/musb/phy-am335x.h b/drivers/usb/musb/phy-am335x.h deleted file mode 100644 index 27da2e3b10..0000000000 --- a/drivers/usb/musb/phy-am335x.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _PHY_AM335x_H_ -#define _PHY_AM335x_H_ - -struct usb_phy *am335x_get_usb_phy(void); - -#endif diff --git a/dts/Bindings/arm/arm,scmi.txt b/dts/Bindings/arm/arm,scmi.txt index f493d69e61..dc102c4e4a 100644 --- a/dts/Bindings/arm/arm,scmi.txt +++ b/dts/Bindings/arm/arm,scmi.txt @@ -102,7 +102,7 @@ Required sub-node properties: [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Documentation/devicetree/bindings/power/power-domain.yaml [3] Documentation/devicetree/bindings/thermal/thermal.txt -[4] Documentation/devicetree/bindings/sram/sram.txt +[4] Documentation/devicetree/bindings/sram/sram.yaml [5] Documentation/devicetree/bindings/reset/reset.txt Example: diff --git a/dts/Bindings/arm/arm,scpi.txt b/dts/Bindings/arm/arm,scpi.txt index 7b83ef43b4..dd04d9d9a1 100644 --- a/dts/Bindings/arm/arm,scpi.txt +++ b/dts/Bindings/arm/arm,scpi.txt @@ -109,7 +109,7 @@ Required properties: [0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Documentation/devicetree/bindings/thermal/thermal.txt -[3] Documentation/devicetree/bindings/sram/sram.txt +[3] Documentation/devicetree/bindings/sram/sram.yaml [4] Documentation/devicetree/bindings/power/power-domain.yaml Example: diff --git a/dts/Bindings/arm/bcm/brcm,bcm63138.txt b/dts/Bindings/arm/bcm/brcm,bcm63138.txt index b82b6a0ae6..8c7a4908a8 100644 --- a/dts/Bindings/arm/bcm/brcm,bcm63138.txt +++ b/dts/Bindings/arm/bcm/brcm,bcm63138.txt @@ -62,7 +62,7 @@ Timer node: Syscon reboot node: -See Documentation/devicetree/bindings/power/reset/syscon-reboot.txt for the +See Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml for the detailed list of properties, the two values defined below are specific to the BCM6328-style timer: diff --git a/dts/Bindings/arm/cpus.yaml b/dts/Bindings/arm/cpus.yaml index 7a9c3ce2db..0d5b61056b 100644 --- a/dts/Bindings/arm/cpus.yaml +++ b/dts/Bindings/arm/cpus.yaml @@ -216,7 +216,7 @@ properties: $ref: '/schemas/types.yaml#/definitions/phandle-array' description: | List of phandles to idle state nodes supported - by this cpu (see ./idle-states.txt). + by this cpu (see ./idle-states.yaml). capacity-dmips-mhz: $ref: '/schemas/types.yaml#/definitions/uint32' diff --git a/dts/Bindings/arm/fsl.yaml b/dts/Bindings/arm/fsl.yaml index a8e0b4a813..0e17e1f6fb 100644 --- a/dts/Bindings/arm/fsl.yaml +++ b/dts/Bindings/arm/fsl.yaml @@ -160,7 +160,7 @@ properties: items: - enum: - armadeus,imx6dl-apf6 # APF6 (Solo) SoM - - armadeus,imx6dl-apf6dldev # APF6 (Solo) SoM on APF6Dev board + - armadeus,imx6dl-apf6dev # APF6 (Solo) SoM on APF6Dev board - eckelmann,imx6dl-ci4x10 - emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM - emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base diff --git a/dts/Bindings/arm/hisilicon/hi3519-sysctrl.txt b/dts/Bindings/arm/hisilicon/hi3519-sysctrl.txt index 115c5be0bd..8defacc44d 100644 --- a/dts/Bindings/arm/hisilicon/hi3519-sysctrl.txt +++ b/dts/Bindings/arm/hisilicon/hi3519-sysctrl.txt @@ -1,7 +1,7 @@ * Hisilicon Hi3519 System Controller Block This bindings use the following binding: -Documentation/devicetree/bindings/mfd/syscon.txt +Documentation/devicetree/bindings/mfd/syscon.yaml Required properties: - compatible: "hisilicon,hi3519-sysctrl". diff --git a/dts/Bindings/arm/msm/qcom,idle-state.txt b/dts/Bindings/arm/msm/qcom,idle-state.txt index 06df04cc82..6ce0b212ec 100644 --- a/dts/Bindings/arm/msm/qcom,idle-state.txt +++ b/dts/Bindings/arm/msm/qcom,idle-state.txt @@ -81,4 +81,4 @@ Example: }; }; -[1]. Documentation/devicetree/bindings/arm/idle-states.txt +[1]. Documentation/devicetree/bindings/arm/idle-states.yaml diff --git a/dts/Bindings/arm/omap/mpu.txt b/dts/Bindings/arm/omap/mpu.txt index f301e636fd..e41490e697 100644 --- a/dts/Bindings/arm/omap/mpu.txt +++ b/dts/Bindings/arm/omap/mpu.txt @@ -17,7 +17,7 @@ am335x and am437x only: - pm-sram: Phandles to ocmcram nodes to be used for power management. First should be type 'protect-exec' for the driver to use to copy and run PM functions, second should be regular pool to be used for - data region for code. See Documentation/devicetree/bindings/sram/sram.txt + data region for code. See Documentation/devicetree/bindings/sram/sram.yaml for more details. Examples: diff --git a/dts/Bindings/arm/psci.yaml b/dts/Bindings/arm/psci.yaml index 8ef85420b2..5e66934455 100644 --- a/dts/Bindings/arm/psci.yaml +++ b/dts/Bindings/arm/psci.yaml @@ -100,13 +100,14 @@ properties: bindings in [1]) must specify this property. [1] Kernel documentation - ARM idle states bindings - Documentation/devicetree/bindings/arm/idle-states.txt - - "#power-domain-cells": - description: - The number of cells in a PM domain specifier as per binding in [3]. - Must be 0 as to represent a single PM domain. + Documentation/devicetree/bindings/arm/idle-states.yaml +patternProperties: + "^power-domain-": + allOf: + - $ref: "../power/power-domain.yaml#" + type: object + description: | ARM systems can have multiple cores, sometimes in an hierarchical arrangement. This often, but not always, maps directly to the processor power topology of the system. Individual nodes in a topology have their @@ -122,14 +123,8 @@ properties: helps to implement support for OSI mode and OS implementations may choose to mandate it. - [3] Documentation/devicetree/bindings/power/power_domain.txt - [4] Documentation/devicetree/bindings/power/domain-idle-state.txt - - power-domains: - $ref: '/schemas/types.yaml#/definitions/phandle-array' - description: - List of phandles and PM domain specifiers, as defined by bindings of the - PM domain provider. + [3] Documentation/devicetree/bindings/power/power-domain.yaml + [4] Documentation/devicetree/bindings/power/domain-idle-state.yaml required: - compatible @@ -199,7 +194,7 @@ examples: CPU0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0>; enable-method = "psci"; power-domains = <&CPU_PD0>; @@ -208,7 +203,7 @@ examples: CPU1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x100>; enable-method = "psci"; power-domains = <&CPU_PD1>; @@ -224,6 +219,9 @@ examples: exit-latency-us = <10>; min-residency-us = <100>; }; + }; + + domain-idle-states { CLUSTER_RET: cluster-retention { compatible = "domain-idle-state"; @@ -247,19 +245,19 @@ examples: compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu-pd0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; domain-idle-states = <&CPU_PWRDN>; power-domains = <&CLUSTER_PD>; }; - CPU_PD1: cpu-pd1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; domain-idle-states = <&CPU_PWRDN>; power-domains = <&CLUSTER_PD>; }; - CLUSTER_PD: cluster-pd { + CLUSTER_PD: power-domain-cluster { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; }; diff --git a/dts/Bindings/arm/stm32/st,mlahb.yaml b/dts/Bindings/arm/stm32/st,mlahb.yaml index 68917bb7c7..55f7938c48 100644 --- a/dts/Bindings/arm/stm32/st,mlahb.yaml +++ b/dts/Bindings/arm/stm32/st,mlahb.yaml @@ -52,7 +52,7 @@ required: examples: - | - mlahb: ahb { + mlahb: ahb@38000000 { compatible = "st,mlahb", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/Bindings/bus/allwinner,sun8i-a23-rsb.yaml b/dts/Bindings/bus/allwinner,sun8i-a23-rsb.yaml index 9fe11ceecd..8097361934 100644 --- a/dts/Bindings/bus/allwinner,sun8i-a23-rsb.yaml +++ b/dts/Bindings/bus/allwinner,sun8i-a23-rsb.yaml @@ -70,7 +70,6 @@ examples: #size-cells = <0>; pmic@3e3 { - compatible = "..."; reg = <0x3e3>; /* ... */ diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-osc-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-osc-clk.yaml index 69cfa4a3d5..c604822cda 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-osc-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-osc-clk.yaml @@ -40,7 +40,7 @@ additionalProperties: false examples: - | - osc24M: clk@01c20050 { + osc24M: clk@1c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-osc-clk"; reg = <0x01c20050 0x4>; diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-gt-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-gt-clk.yaml index 07f38def7d..43963c3062 100644 --- a/dts/Bindings/clock/allwinner,sun9i-a80-gt-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun9i-a80-gt-clk.yaml @@ -41,7 +41,7 @@ additionalProperties: false examples: - | - clk@0600005c { + clk@600005c { #clock-cells = <0>; compatible = "allwinner,sun9i-a80-gt-clk"; reg = <0x0600005c 0x4>; diff --git a/dts/Bindings/clock/qcom,gcc-apq8064.yaml b/dts/Bindings/clock/qcom,gcc-apq8064.yaml index 17f87178f6..3647007f82 100644 --- a/dts/Bindings/clock/qcom,gcc-apq8064.yaml +++ b/dts/Bindings/clock/qcom,gcc-apq8064.yaml @@ -42,7 +42,7 @@ properties: be part of GCC and hence the TSENS properties can also be part of the GCC/clock-controller node. For more details on the TSENS properties please refer - Documentation/devicetree/bindings/thermal/qcom-tsens.txt + Documentation/devicetree/bindings/thermal/qcom-tsens.yaml nvmem-cell-names: minItems: 1 diff --git a/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml b/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml index 86ad617d23..5ff9cf26ca 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml @@ -43,9 +43,13 @@ properties: - enum: - allwinner,sun8i-h3-tcon-tv - allwinner,sun50i-a64-tcon-tv - - allwinner,sun50i-h6-tcon-tv - const: allwinner,sun8i-a83t-tcon-tv + - items: + - enum: + - allwinner,sun50i-h6-tcon-tv + - const: allwinner,sun8i-r40-tcon-tv + reg: maxItems: 1 diff --git a/dts/Bindings/display/allwinner,sun4i-a10-tv-encoder.yaml b/dts/Bindings/display/allwinner,sun4i-a10-tv-encoder.yaml index 5d5d396651..6009324be9 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-tv-encoder.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-tv-encoder.yaml @@ -49,11 +49,7 @@ examples: resets = <&tcon_ch0_clk 0>; port { - #address-cells = <1>; - #size-cells = <0>; - - tve0_in_tcon0: endpoint@0 { - reg = <0>; + tve0_in_tcon0: endpoint { remote-endpoint = <&tcon0_out_tve0>; }; }; diff --git a/dts/Bindings/display/bridge/anx6345.yaml b/dts/Bindings/display/bridge/anx6345.yaml index 6d72b3d11f..c211038699 100644 --- a/dts/Bindings/display/bridge/anx6345.yaml +++ b/dts/Bindings/display/bridge/anx6345.yaml @@ -79,21 +79,15 @@ examples: #size-cells = <0>; anx6345_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - anx6345_in_tcon0: endpoint@0 { - reg = <0>; + anx6345_in_tcon0: endpoint { remote-endpoint = <&tcon0_out_anx6345>; }; }; anx6345_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; - anx6345_out_panel: endpoint@0 { - reg = <0>; + anx6345_out_panel: endpoint { remote-endpoint = <&panel_in_edp>; }; }; diff --git a/dts/Bindings/display/panel/leadtek,ltk500hd1829.yaml b/dts/Bindings/display/panel/leadtek,ltk500hd1829.yaml index 4ebcea7d0c..a614644c98 100644 --- a/dts/Bindings/display/panel/leadtek,ltk500hd1829.yaml +++ b/dts/Bindings/display/panel/leadtek,ltk500hd1829.yaml @@ -37,6 +37,8 @@ examples: dsi@ff450000 { #address-cells = <1>; #size-cells = <0>; + reg = <0xff450000 0x1000>; + panel@0 { compatible = "leadtek,ltk500hd1829"; reg = <0>; diff --git a/dts/Bindings/display/panel/xinpeng,xpp055c272.yaml b/dts/Bindings/display/panel/xinpeng,xpp055c272.yaml index 186e5e1c8f..22c91beb05 100644 --- a/dts/Bindings/display/panel/xinpeng,xpp055c272.yaml +++ b/dts/Bindings/display/panel/xinpeng,xpp055c272.yaml @@ -37,6 +37,8 @@ examples: dsi@ff450000 { #address-cells = <1>; #size-cells = <0>; + reg = <0xff450000 0x1000>; + panel@0 { compatible = "xinpeng,xpp055c272"; reg = <0>; diff --git a/dts/Bindings/display/simple-framebuffer.yaml b/dts/Bindings/display/simple-framebuffer.yaml index 678776b601..1db608c9ee 100644 --- a/dts/Bindings/display/simple-framebuffer.yaml +++ b/dts/Bindings/display/simple-framebuffer.yaml @@ -174,10 +174,6 @@ examples: }; }; - soc@1c00000 { - lcdc0: lcdc@1c0c000 { - compatible = "allwinner,sun4i-a10-lcdc"; - }; - }; + lcdc0: lcdc { }; ... diff --git a/dts/Bindings/display/tilcdc/tilcdc.txt b/dts/Bindings/display/tilcdc/tilcdc.txt index 7bf1bb4448..aac617acb6 100644 --- a/dts/Bindings/display/tilcdc/tilcdc.txt +++ b/dts/Bindings/display/tilcdc/tilcdc.txt @@ -37,7 +37,7 @@ Optional nodes: supports a single port with a single endpoint. - See also Documentation/devicetree/bindings/display/tilcdc/panel.txt and - Documentation/devicetree/bindings/display/tilcdc/tfp410.txt for connecting + Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt for connecting tfp410 DVI encoder or lcd panel to lcdc [1] There is an errata about AM335x color wiring. For 16-bit color mode diff --git a/dts/Bindings/dma/ti/k3-udma.yaml b/dts/Bindings/dma/ti/k3-udma.yaml index 8b5c346f23..34780d7535 100644 --- a/dts/Bindings/dma/ti/k3-udma.yaml +++ b/dts/Bindings/dma/ti/k3-udma.yaml @@ -143,7 +143,7 @@ examples: #size-cells = <2>; dma-coherent; dma-ranges; - ranges; + ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>; ti,sci-dev-id = <118>; @@ -169,16 +169,4 @@ examples: ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */ }; }; - - mcasp0: mcasp@02B00000 { - dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; - dma-names = "tx", "rx"; - }; - - crypto: crypto@4E00000 { - compatible = "ti,sa2ul-crypto"; - - dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, <&main_udmap 0x4001>; - dma-names = "tx", "rx1", "rx2"; - }; }; diff --git a/dts/Bindings/gpu/arm,mali-bifrost.yaml b/dts/Bindings/gpu/arm,mali-bifrost.yaml index 4ea6a87896..e8b99adcb1 100644 --- a/dts/Bindings/gpu/arm,mali-bifrost.yaml +++ b/dts/Bindings/gpu/arm,mali-bifrost.yaml @@ -84,31 +84,31 @@ examples: gpu_opp_table: opp_table0 { compatible = "operating-points-v2"; - opp@533000000 { + opp-533000000 { opp-hz = /bits/ 64 <533000000>; opp-microvolt = <1250000>; }; - opp@450000000 { + opp-450000000 { opp-hz = /bits/ 64 <450000000>; opp-microvolt = <1150000>; }; - opp@400000000 { + opp-400000000 { opp-hz = /bits/ 64 <400000000>; opp-microvolt = <1125000>; }; - opp@350000000 { + opp-350000000 { opp-hz = /bits/ 64 <350000000>; opp-microvolt = <1075000>; }; - opp@266000000 { + opp-266000000 { opp-hz = /bits/ 64 <266000000>; opp-microvolt = <1025000>; }; - opp@160000000 { + opp-160000000 { opp-hz = /bits/ 64 <160000000>; opp-microvolt = <925000>; }; - opp@100000000 { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; opp-microvolt = <912500>; }; diff --git a/dts/Bindings/gpu/arm,mali-midgard.yaml b/dts/Bindings/gpu/arm,mali-midgard.yaml index 36f59b3ade..8d966f3ff3 100644 --- a/dts/Bindings/gpu/arm,mali-midgard.yaml +++ b/dts/Bindings/gpu/arm,mali-midgard.yaml @@ -138,31 +138,31 @@ examples: gpu_opp_table: opp_table0 { compatible = "operating-points-v2"; - opp@533000000 { + opp-533000000 { opp-hz = /bits/ 64 <533000000>; opp-microvolt = <1250000>; }; - opp@450000000 { + opp-450000000 { opp-hz = /bits/ 64 <450000000>; opp-microvolt = <1150000>; }; - opp@400000000 { + opp-400000000 { opp-hz = /bits/ 64 <400000000>; opp-microvolt = <1125000>; }; - opp@350000000 { + opp-350000000 { opp-hz = /bits/ 64 <350000000>; opp-microvolt = <1075000>; }; - opp@266000000 { + opp-266000000 { opp-hz = /bits/ 64 <266000000>; opp-microvolt = <1025000>; }; - opp@160000000 { + opp-160000000 { opp-hz = /bits/ 64 <160000000>; opp-microvolt = <925000>; }; - opp@100000000 { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; opp-microvolt = <912500>; }; diff --git a/dts/Bindings/iio/adc/samsung,exynos-adc.yaml b/dts/Bindings/iio/adc/samsung,exynos-adc.yaml index f46de17c08..cc3c8ea6a8 100644 --- a/dts/Bindings/iio/adc/samsung,exynos-adc.yaml +++ b/dts/Bindings/iio/adc/samsung,exynos-adc.yaml @@ -123,7 +123,7 @@ examples: samsung,syscon-phandle = <&pmu_system_controller>; /* NTC thermistor is a hwmon device */ - ncp15wb473@0 { + ncp15wb473 { compatible = "murata,ncp15wb473"; pullup-uv = <1800000>; pullup-ohm = <47000>; diff --git a/dts/Bindings/input/ilitek,ili2xxx.txt b/dts/Bindings/input/ilitek,ili2xxx.txt index dc194b2c15..cdcaa3f52d 100644 --- a/dts/Bindings/input/ilitek,ili2xxx.txt +++ b/dts/Bindings/input/ilitek,ili2xxx.txt @@ -1,9 +1,10 @@ -Ilitek ILI210x/ILI2117/ILI251x touchscreen controller +Ilitek ILI210x/ILI2117/ILI2120/ILI251x touchscreen controller Required properties: - compatible: ilitek,ili210x for ILI210x ilitek,ili2117 for ILI2117 + ilitek,ili2120 for ILI2120 ilitek,ili251x for ILI251x - reg: The I2C address of the device diff --git a/dts/Bindings/input/touchscreen/goodix.yaml b/dts/Bindings/input/touchscreen/goodix.yaml index d7c3262b24..c99ed3934d 100644 --- a/dts/Bindings/input/touchscreen/goodix.yaml +++ b/dts/Bindings/input/touchscreen/goodix.yaml @@ -62,7 +62,7 @@ required: examples: - | - i2c@00000000 { + i2c { #address-cells = <1>; #size-cells = <0>; gt928@5d { diff --git a/dts/Bindings/input/twl4030-pwrbutton.txt b/dts/Bindings/input/twl4030-pwrbutton.txt index c864a46cdd..f5021214ed 100644 --- a/dts/Bindings/input/twl4030-pwrbutton.txt +++ b/dts/Bindings/input/twl4030-pwrbutton.txt @@ -1,7 +1,7 @@ Texas Instruments TWL family (twl4030) pwrbutton module This module is part of the TWL4030. For more details about the whole -chip see Documentation/devicetree/bindings/mfd/twl-familly.txt. +chip see Documentation/devicetree/bindings/mfd/twl-family.txt. This module provides a simple power button event via an Interrupt. diff --git a/dts/Bindings/leds/common.yaml b/dts/Bindings/leds/common.yaml index d97d099b87..c60b994fe1 100644 --- a/dts/Bindings/leds/common.yaml +++ b/dts/Bindings/leds/common.yaml @@ -85,7 +85,7 @@ properties: # LED will act as a back-light, controlled by the framebuffer system - backlight # LED will turn on (but for leds-gpio see "default-state" property in - # Documentation/devicetree/bindings/leds/leds-gpio.txt) + # Documentation/devicetree/bindings/leds/leds-gpio.yaml) - default-on # LED "double" flashes at a load average based rate - heartbeat diff --git a/dts/Bindings/leds/register-bit-led.txt b/dts/Bindings/leds/register-bit-led.txt index cf1ea403ba..c7af6f70a9 100644 --- a/dts/Bindings/leds/register-bit-led.txt +++ b/dts/Bindings/leds/register-bit-led.txt @@ -5,7 +5,7 @@ where single bits in a certain register can turn on/off a single LED. The register bit LEDs appear as children to the syscon device, with the proper compatible string. For the syscon bindings see: -Documentation/devicetree/bindings/mfd/syscon.txt +Documentation/devicetree/bindings/mfd/syscon.yaml Each LED is represented as a sub-node of the syscon device. Each node's name represents the name of the corresponding LED. diff --git a/dts/Bindings/media/allwinner,sun4i-a10-csi.yaml b/dts/Bindings/media/allwinner,sun4i-a10-csi.yaml index 9af873b43a..8453ee340b 100644 --- a/dts/Bindings/media/allwinner,sun4i-a10-csi.yaml +++ b/dts/Bindings/media/allwinner,sun4i-a10-csi.yaml @@ -33,24 +33,40 @@ properties: maxItems: 1 clocks: - minItems: 2 - maxItems: 3 - items: - - description: The CSI interface clock - - description: The CSI ISP clock - - description: The CSI DRAM clock + oneOf: + - items: + - description: The CSI interface clock + - description: The CSI DRAM clock + + - items: + - description: The CSI interface clock + - description: The CSI ISP clock + - description: The CSI DRAM clock clock-names: - minItems: 2 - maxItems: 3 - items: - - const: bus - - const: isp - - const: ram + oneOf: + - items: + - const: bus + - const: ram + + - items: + - const: bus + - const: isp + - const: ram resets: maxItems: 1 + # FIXME: This should be made required eventually once every SoC will + # have the MBUS declared. + interconnects: + maxItems: 1 + + # FIXME: This should be made required eventually once every SoC will + # have the MBUS declared. + interconnect-names: + const: dma-mem + # See ./video-interfaces.txt for details port: type: object diff --git a/dts/Bindings/media/ti,cal.yaml b/dts/Bindings/media/ti,cal.yaml index 1ea7841795..5e06662928 100644 --- a/dts/Bindings/media/ti,cal.yaml +++ b/dts/Bindings/media/ti,cal.yaml @@ -177,7 +177,7 @@ examples: }; }; - i2c5: i2c@4807c000 { + i2c { clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/memory-controllers/nvidia,tegra124-emc.yaml b/dts/Bindings/memory-controllers/nvidia,tegra124-emc.yaml index dd1843489a..3e0a8a92d6 100644 --- a/dts/Bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/dts/Bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -347,6 +347,7 @@ examples: interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; #iommu-cells = <1>; + #reset-cells = <1>; }; external-memory-controller@7001b000 { @@ -363,20 +364,23 @@ examples: timing-0 { clock-frequency = <12750000>; - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; nvidia,emc-auto-cal-config = <0xa1430000>; nvidia,emc-auto-cal-config2 = <0x00000000>; nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; nvidia,emc-mode-1 = <0x80100003>; nvidia,emc-mode-2 = <0x80200008>; nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < 0x00000000 /* EMC_RC */ diff --git a/dts/Bindings/memory-controllers/ti/emif.txt b/dts/Bindings/memory-controllers/ti/emif.txt index 44d71469c9..63f674ffeb 100644 --- a/dts/Bindings/memory-controllers/ti/emif.txt +++ b/dts/Bindings/memory-controllers/ti/emif.txt @@ -32,7 +32,7 @@ Required only for "ti,emif-am3352" and "ti,emif-am4372": - sram : Phandles for generic sram driver nodes, first should be type 'protect-exec' for the driver to use to copy and run PM functions, second should be regular pool to be used for - data region for code. See Documentation/devicetree/bindings/sram/sram.txt + data region for code. See Documentation/devicetree/bindings/sram/sram.yaml for more details. Optional properties: diff --git a/dts/Bindings/mfd/max77650.yaml b/dts/Bindings/mfd/max77650.yaml index 4a70f875a6..4803857893 100644 --- a/dts/Bindings/mfd/max77650.yaml +++ b/dts/Bindings/mfd/max77650.yaml @@ -97,14 +97,14 @@ examples: regulators { compatible = "maxim,max77650-regulator"; - max77650_ldo: regulator@0 { + max77650_ldo: regulator-ldo { regulator-compatible = "ldo"; regulator-name = "max77650-ldo"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <2937500>; }; - max77650_sbb0: regulator@1 { + max77650_sbb0: regulator-sbb0 { regulator-compatible = "sbb0"; regulator-name = "max77650-sbb0"; regulator-min-microvolt = <800000>; diff --git a/dts/Bindings/mfd/tps65910.txt b/dts/Bindings/mfd/tps65910.txt index 4f62143afd..a5ced46bbd 100644 --- a/dts/Bindings/mfd/tps65910.txt +++ b/dts/Bindings/mfd/tps65910.txt @@ -26,8 +26,8 @@ Required properties: ldo6, ldo7, ldo8 - xxx-supply: Input voltage supply regulator. - These entries are require if regulators are enabled for a device. Missing of these - properties can cause the regulator registration fails. + These entries are required if regulators are enabled for a device. Missing these + properties can cause the regulator registration to fail. If some of input supply is powered through battery or always-on supply then also it is require to have these parameters with proper node handle of always on power supply. diff --git a/dts/Bindings/mfd/twl-familly.txt b/dts/Bindings/mfd/twl-family.txt index 56f244b5d8..56f244b5d8 100644 --- a/dts/Bindings/mfd/twl-familly.txt +++ b/dts/Bindings/mfd/twl-family.txt diff --git a/dts/Bindings/mfd/zii,rave-sp.txt b/dts/Bindings/mfd/zii,rave-sp.txt index 088eff9ddb..e0f901edc0 100644 --- a/dts/Bindings/mfd/zii,rave-sp.txt +++ b/dts/Bindings/mfd/zii,rave-sp.txt @@ -20,7 +20,7 @@ RAVE SP consists of the following sub-devices: Device Description ------ ----------- rave-sp-wdt : Watchdog -rave-sp-nvmem : Interface to onborad EEPROM +rave-sp-nvmem : Interface to onboard EEPROM rave-sp-backlight : Display backlight rave-sp-hwmon : Interface to onboard hardware sensors rave-sp-leds : Interface to onboard LEDs diff --git a/dts/Bindings/misc/fsl,qoriq-mc.txt b/dts/Bindings/misc/fsl,qoriq-mc.txt index bb7e896cb6..9134e9bcca 100644 --- a/dts/Bindings/misc/fsl,qoriq-mc.txt +++ b/dts/Bindings/misc/fsl,qoriq-mc.txt @@ -26,7 +26,7 @@ For generic IOMMU bindings, see Documentation/devicetree/bindings/iommu/iommu.txt. For arm-smmu binding, see: -Documentation/devicetree/bindings/iommu/arm,smmu.txt. +Documentation/devicetree/bindings/iommu/arm,smmu.yaml. Required properties: diff --git a/dts/Bindings/mmc/mmc-controller.yaml b/dts/Bindings/mmc/mmc-controller.yaml index 3c0df4016a..8fded83c51 100644 --- a/dts/Bindings/mmc/mmc-controller.yaml +++ b/dts/Bindings/mmc/mmc-controller.yaml @@ -370,6 +370,7 @@ examples: mmc3: mmc@1c12000 { #address-cells = <1>; #size-cells = <0>; + reg = <0x1c12000 0x200>; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins_a>; vmmc-supply = <®_vmmc3>; diff --git a/dts/Bindings/mmc/ti-omap-hsmmc.txt b/dts/Bindings/mmc/ti-omap-hsmmc.txt index 19f5508a75..4a9145ef15 100644 --- a/dts/Bindings/mmc/ti-omap-hsmmc.txt +++ b/dts/Bindings/mmc/ti-omap-hsmmc.txt @@ -124,7 +124,7 @@ not every application needs SDIO irq, e.g. MMC cards. pinctrl-1 = <&mmc1_idle>; pinctrl-2 = <&mmc1_sleep>; ... - interrupts-extended = <&intc 64 &gpio2 28 GPIO_ACTIVE_LOW>; + interrupts-extended = <&intc 64 &gpio2 28 IRQ_TYPE_LEVEL_LOW>; }; mmc1_idle : pinmux_cirq_pin { diff --git a/dts/Bindings/mtd/cadence-nand-controller.txt b/dts/Bindings/mtd/cadence-nand-controller.txt index f3893c4d3c..d2eada5044 100644 --- a/dts/Bindings/mtd/cadence-nand-controller.txt +++ b/dts/Bindings/mtd/cadence-nand-controller.txt @@ -27,7 +27,7 @@ Required properties of NAND chips: - reg: shall contain the native Chip Select ids from 0 to max supported by the cadence nand flash controller -See Documentation/devicetree/bindings/mtd/nand.txt for more details on +See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on generic bindings. Example: diff --git a/dts/Bindings/net/brcm,bcm7445-switch-v4.0.txt b/dts/Bindings/net/brcm,bcm7445-switch-v4.0.txt index 48a7f916c5..88b57b0ca1 100644 --- a/dts/Bindings/net/brcm,bcm7445-switch-v4.0.txt +++ b/dts/Bindings/net/brcm,bcm7445-switch-v4.0.txt @@ -45,7 +45,7 @@ Optional properties: switch queue - resets: a single phandle and reset identifier pair. See - Documentation/devicetree/binding/reset/reset.txt for details. + Documentation/devicetree/bindings/reset/reset.txt for details. - reset-names: If the "reset" property is specified, this property should have the value "switch" to denote the switch reset line. diff --git a/dts/Bindings/net/fsl-fman.txt b/dts/Bindings/net/fsl-fman.txt index 250f8d8cdc..c00fb0d22c 100644 --- a/dts/Bindings/net/fsl-fman.txt +++ b/dts/Bindings/net/fsl-fman.txt @@ -110,6 +110,13 @@ PROPERTIES Usage: required Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt +- fsl,erratum-a050385 + Usage: optional + Value type: boolean + Definition: A boolean property. Indicates the presence of the + erratum A050385 which indicates that DMA transactions that are + split can result in a FMan lock. + ============================================================================= FMan MURAM Node diff --git a/dts/Bindings/net/mdio.yaml b/dts/Bindings/net/mdio.yaml index 5d08d2ffd4..50c3397a82 100644 --- a/dts/Bindings/net/mdio.yaml +++ b/dts/Bindings/net/mdio.yaml @@ -56,7 +56,6 @@ patternProperties: examples: - | davinci_mdio: mdio@5c030000 { - compatible = "ti,davinci_mdio"; reg = <0x5c030000 0x1000>; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/nvmem/nvmem.yaml b/dts/Bindings/nvmem/nvmem.yaml index b43c6c6529..65980224d5 100644 --- a/dts/Bindings/nvmem/nvmem.yaml +++ b/dts/Bindings/nvmem/nvmem.yaml @@ -76,6 +76,8 @@ examples: qfprom: eeprom@700000 { #address-cells = <1>; #size-cells = <1>; + reg = <0x00700000 0x100000>; + wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; /* ... */ diff --git a/dts/Bindings/phy/allwinner,sun4i-a10-usb-phy.yaml b/dts/Bindings/phy/allwinner,sun4i-a10-usb-phy.yaml index 020ef9e4c4..94ac23687b 100644 --- a/dts/Bindings/phy/allwinner,sun4i-a10-usb-phy.yaml +++ b/dts/Bindings/phy/allwinner,sun4i-a10-usb-phy.yaml @@ -86,7 +86,7 @@ examples: #include <dt-bindings/clock/sun4i-a10-ccu.h> #include <dt-bindings/reset/sun4i-a10-ccu.h> - usbphy: phy@01c13400 { + usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun4i-a10-usb-phy"; reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; diff --git a/dts/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml b/dts/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml index bb690e20c3..135c7dfbc1 100644 --- a/dts/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml +++ b/dts/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml @@ -17,7 +17,7 @@ description: |+ "aspeed,ast2400-scu", "syscon", "simple-mfd" Refer to the the bindings described in - Documentation/devicetree/bindings/mfd/syscon.txt + Documentation/devicetree/bindings/mfd/syscon.yaml properties: compatible: diff --git a/dts/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/dts/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml index f7f5d57f2c..824f7fd1d5 100644 --- a/dts/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml +++ b/dts/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml @@ -18,7 +18,7 @@ description: |+ "aspeed,g5-scu", "syscon", "simple-mfd" Refer to the the bindings described in - Documentation/devicetree/bindings/mfd/syscon.txt + Documentation/devicetree/bindings/mfd/syscon.yaml properties: compatible: diff --git a/dts/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/dts/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml index 3749fa233e..ac8d1c30a8 100644 --- a/dts/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/dts/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -17,7 +17,7 @@ description: |+ "aspeed,ast2600-scu", "syscon", "simple-mfd" Refer to the the bindings described in - Documentation/devicetree/bindings/mfd/syscon.txt + Documentation/devicetree/bindings/mfd/syscon.yaml properties: compatible: diff --git a/dts/Bindings/pinctrl/st,stm32-pinctrl.yaml b/dts/Bindings/pinctrl/st,stm32-pinctrl.yaml index 754ea7ab04..ef4de32cb1 100644 --- a/dts/Bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/dts/Bindings/pinctrl/st,stm32-pinctrl.yaml @@ -248,7 +248,7 @@ examples: }; //Example 3 pin groups - pinctrl@60020000 { + pinctrl { usart1_pins_a: usart1-0 { pins1 { pinmux = <STM32_PINMUX('A', 9, AF7)>; diff --git a/dts/Bindings/power/amlogic,meson-ee-pwrc.yaml b/dts/Bindings/power/amlogic,meson-ee-pwrc.yaml index aab70e8b68..d3098c924b 100644 --- a/dts/Bindings/power/amlogic,meson-ee-pwrc.yaml +++ b/dts/Bindings/power/amlogic,meson-ee-pwrc.yaml @@ -18,7 +18,7 @@ description: |+ "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon" Refer to the the bindings described in - Documentation/devicetree/bindings/mfd/syscon.txt + Documentation/devicetree/bindings/mfd/syscon.yaml properties: compatible: diff --git a/dts/Bindings/power/domain-idle-state.txt b/dts/Bindings/power/domain-idle-state.txt deleted file mode 100644 index eefc7ed22c..0000000000 --- a/dts/Bindings/power/domain-idle-state.txt +++ /dev/null @@ -1,33 +0,0 @@ -PM Domain Idle State Node: - -A domain idle state node represents the state parameters that will be used to -select the state when there are no active components in the domain. - -The state node has the following parameters - - -- compatible: - Usage: Required - Value type: <string> - Definition: Must be "domain-idle-state". - -- entry-latency-us - Usage: Required - Value type: <prop-encoded-array> - Definition: u32 value representing worst case latency in - microseconds required to enter the idle state. - The exit-latency-us duration may be guaranteed - only after entry-latency-us has passed. - -- exit-latency-us - Usage: Required - Value type: <prop-encoded-array> - Definition: u32 value representing worst case latency - in microseconds required to exit the idle state. - -- min-residency-us - Usage: Required - Value type: <prop-encoded-array> - Definition: u32 value representing minimum residency duration - in microseconds after which the idle state will yield - power benefits after overcoming the overhead in entering -i the idle state. diff --git a/dts/Bindings/power/domain-idle-state.yaml b/dts/Bindings/power/domain-idle-state.yaml new file mode 100644 index 0000000000..dfba1af9ab --- /dev/null +++ b/dts/Bindings/power/domain-idle-state.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/domain-idle-state.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PM Domain Idle States binding description + +maintainers: + - Ulf Hansson <ulf.hansson@linaro.org> + +description: + A domain idle state node represents the state parameters that will be used to + select the state when there are no active components in the PM domain. + +properties: + $nodename: + const: domain-idle-states + +patternProperties: + "^(cpu|cluster|domain)-": + type: object + description: + Each state node represents a domain idle state description. + + properties: + compatible: + const: domain-idle-state + + entry-latency-us: + description: + The worst case latency in microseconds required to enter the idle + state. Note that, the exit-latency-us duration may be guaranteed only + after the entry-latency-us has passed. + + exit-latency-us: + description: + The worst case latency in microseconds required to exit the idle + state. + + min-residency-us: + description: + The minimum residency duration in microseconds after which the idle + state will yield power benefits, after overcoming the overhead while + entering the idle state. + + required: + - compatible + - entry-latency-us + - exit-latency-us + - min-residency-us + +examples: + - | + + domain-idle-states { + domain_retention: domain-retention { + compatible = "domain-idle-state"; + entry-latency-us = <20>; + exit-latency-us = <40>; + min-residency-us = <80>; + }; + }; +... diff --git a/dts/Bindings/power/power-domain.yaml b/dts/Bindings/power/power-domain.yaml index 455b573293..6047aacd77 100644 --- a/dts/Bindings/power/power-domain.yaml +++ b/dts/Bindings/power/power-domain.yaml @@ -25,22 +25,20 @@ description: |+ properties: $nodename: - pattern: "^(power-controller|power-domain)(@.*)?$" + pattern: "^(power-controller|power-domain)([@-].*)?$" domain-idle-states: $ref: /schemas/types.yaml#/definitions/phandle-array - description: - A phandle of an idle-state that shall be soaked into a generic domain - power state. The idle state definitions are compatible with - domain-idle-state specified in - Documentation/devicetree/bindings/power/domain-idle-state.txt - phandles that are not compatible with domain-idle-state will be ignored. - The domain-idle-state property reflects the idle state of this PM domain - and not the idle states of the devices or sub-domains in the PM domain. - Devices and sub-domains have their own idle-states independent - of the parent domain's idle states. In the absence of this property, - the domain would be considered as capable of being powered-on - or powered-off. + description: | + Phandles of idle states that defines the available states for the + power-domain provider. The idle state definitions are compatible with the + domain-idle-state bindings, specified in ./domain-idle-state.yaml. + + Note that, the domain-idle-state property reflects the idle states of this + PM domain and not the idle states of the devices or sub-domains in the PM + domain. Devices and sub-domains have their own idle states independent of + the parent domain's idle states. In the absence of this property, the + domain would be considered as capable of being powered-on or powered-off. operating-points-v2: $ref: /schemas/types.yaml#/definitions/phandle-array diff --git a/dts/Bindings/power/power_domain.txt b/dts/Bindings/power/power_domain.txt index 5b09b2deb4..08497ef26c 100644 --- a/dts/Bindings/power/power_domain.txt +++ b/dts/Bindings/power/power_domain.txt @@ -109,4 +109,4 @@ Example: required-opps = <&domain1_opp_1>; }; -[1]. Documentation/devicetree/bindings/power/domain-idle-state.txt +[1]. Documentation/devicetree/bindings/power/domain-idle-state.yaml diff --git a/dts/Bindings/regulator/qcom,spmi-regulator.txt b/dts/Bindings/regulator/qcom,spmi-regulator.txt index f5cdac8b28..8b005192f6 100644 --- a/dts/Bindings/regulator/qcom,spmi-regulator.txt +++ b/dts/Bindings/regulator/qcom,spmi-regulator.txt @@ -161,7 +161,7 @@ The regulator node houses sub-nodes for each regulator within the device. Each sub-node is identified using the node's name, with valid values listed for each of the PMICs below. -pm8005: +pm8004: s2, s5 pm8005: diff --git a/dts/Bindings/regulator/regulator.yaml b/dts/Bindings/regulator/regulator.yaml index 92ff2e8ad5..91a39a3300 100644 --- a/dts/Bindings/regulator/regulator.yaml +++ b/dts/Bindings/regulator/regulator.yaml @@ -191,7 +191,7 @@ patternProperties: examples: - | - xyzreg: regulator@0 { + xyzreg: regulator { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <2500000>; regulator-always-on; diff --git a/dts/Bindings/reset/intel,rcu-gw.yaml b/dts/Bindings/reset/intel,rcu-gw.yaml index 246dea8a2e..8ac4372826 100644 --- a/dts/Bindings/reset/intel,rcu-gw.yaml +++ b/dts/Bindings/reset/intel,rcu-gw.yaml @@ -23,7 +23,11 @@ properties: description: Global reset register offset and bit offset. allOf: - $ref: /schemas/types.yaml#/definitions/uint32-array - - maxItems: 2 + items: + - description: Register offset + - description: Register bit offset + minimum: 0 + maximum: 31 "#reset-cells": minimum: 2 diff --git a/dts/Bindings/reset/st,stm32mp1-rcc.txt b/dts/Bindings/reset/st,stm32mp1-rcc.txt index b4edaf7c7f..2880d5dda9 100644 --- a/dts/Bindings/reset/st,stm32mp1-rcc.txt +++ b/dts/Bindings/reset/st,stm32mp1-rcc.txt @@ -3,4 +3,4 @@ STMicroelectronics STM32MP1 Peripheral Reset Controller The RCC IP is both a reset and a clock controller. -Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt +Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml diff --git a/dts/Bindings/sound/st,stm32-sai.txt b/dts/Bindings/sound/st,stm32-sai.txt index 944743dd92..c42b91e525 100644 --- a/dts/Bindings/sound/st,stm32-sai.txt +++ b/dts/Bindings/sound/st,stm32-sai.txt @@ -36,7 +36,7 @@ SAI subnodes required properties: - clock-names: Must contain "sai_ck". Must also contain "MCLK", if SAI shares a master clock, with a SAI set as MCLK clock provider. - - dmas: see Documentation/devicetree/bindings/dma/stm32-dma.txt + - dmas: see Documentation/devicetree/bindings/dma/st,stm32-dma.yaml - dma-names: identifier string for each DMA request line "tx": if sai sub-block is configured as playback DAI "rx": if sai sub-block is configured as capture DAI diff --git a/dts/Bindings/sound/st,stm32-spdifrx.txt b/dts/Bindings/sound/st,stm32-spdifrx.txt index 33826f2459..ca9101777c 100644 --- a/dts/Bindings/sound/st,stm32-spdifrx.txt +++ b/dts/Bindings/sound/st,stm32-spdifrx.txt @@ -10,7 +10,7 @@ Required properties: - clock-names: must contain "kclk" - interrupts: cpu DAI interrupt line - dmas: DMA specifiers for audio data DMA and iec control flow DMA - See STM32 DMA bindings, Documentation/devicetree/bindings/dma/stm32-dma.txt + See STM32 DMA bindings, Documentation/devicetree/bindings/dma/st,stm32-dma.yaml - dma-names: two dmas have to be defined, "rx" and "rx-ctrl" Optional properties: diff --git a/dts/Bindings/spi/st,stm32-spi.yaml b/dts/Bindings/spi/st,stm32-spi.yaml index f0d979664f..e49ecbf715 100644 --- a/dts/Bindings/spi/st,stm32-spi.yaml +++ b/dts/Bindings/spi/st,stm32-spi.yaml @@ -49,7 +49,7 @@ properties: dmas: description: | DMA specifiers for tx and rx dma. DMA fifo mode must be used. See - the STM32 DMA bindings Documentation/devicetree/bindings/dma/stm32-dma.txt. + the STM32 DMA bindings Documentation/devicetree/bindings/dma/st,stm32-dma.yaml. items: - description: rx DMA channel - description: tx DMA channel diff --git a/dts/Bindings/sram/allwinner,sun4i-a10-system-control.yaml b/dts/Bindings/sram/allwinner,sun4i-a10-system-control.yaml index 80bac7a182..4b55094365 100644 --- a/dts/Bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/dts/Bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -125,7 +125,7 @@ examples: #size-cells = <1>; ranges; - sram_a: sram@00000000 { + sram_a: sram@0 { compatible = "mmio-sram"; reg = <0x00000000 0xc000>; #address-cells = <1>; diff --git a/dts/Bindings/thermal/brcm,avs-ro-thermal.yaml b/dts/Bindings/thermal/brcm,avs-ro-thermal.yaml index d9fdf4809a..f3e68ed03a 100644 --- a/dts/Bindings/thermal/brcm,avs-ro-thermal.yaml +++ b/dts/Bindings/thermal/brcm,avs-ro-thermal.yaml @@ -17,7 +17,7 @@ description: |+ "brcm,bcm2711-avs-monitor", "syscon", "simple-mfd" Refer to the the bindings described in - Documentation/devicetree/bindings/mfd/syscon.txt + Documentation/devicetree/bindings/mfd/syscon.yaml properties: compatible: diff --git a/dts/Bindings/timer/allwinner,sun4i-a10-timer.yaml b/dts/Bindings/timer/allwinner,sun4i-a10-timer.yaml index 23e989e097..d918cee100 100644 --- a/dts/Bindings/timer/allwinner,sun4i-a10-timer.yaml +++ b/dts/Bindings/timer/allwinner,sun4i-a10-timer.yaml @@ -87,7 +87,7 @@ additionalProperties: false examples: - | - timer { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x400>; interrupts = <22>, diff --git a/dts/COPYING b/dts/COPYING index da4cb28feb..a635a38ef9 100644 --- a/dts/COPYING +++ b/dts/COPYING @@ -16,3 +16,5 @@ In addition, other licenses may also apply. Please see: Documentation/process/license-rules.rst for more details. + +All contributions to the Linux Kernel are subject to this COPYING file. diff --git a/dts/include/dt-bindings/clock/imx8mn-clock.h b/dts/include/dt-bindings/clock/imx8mn-clock.h index 0f2b8423ce..65ac6eb6c7 100644 --- a/dts/include/dt-bindings/clock/imx8mn-clock.h +++ b/dts/include/dt-bindings/clock/imx8mn-clock.h @@ -122,8 +122,8 @@ #define IMX8MN_CLK_I2C1 105 #define IMX8MN_CLK_I2C2 106 #define IMX8MN_CLK_I2C3 107 -#define IMX8MN_CLK_I2C4 118 -#define IMX8MN_CLK_UART1 119 +#define IMX8MN_CLK_I2C4 108 +#define IMX8MN_CLK_UART1 109 #define IMX8MN_CLK_UART2 110 #define IMX8MN_CLK_UART3 111 #define IMX8MN_CLK_UART4 112 diff --git a/dts/src/arm/am437x-idk-evm.dts b/dts/src/arm/am437x-idk-evm.dts index f3ced6df0c..9f66f96d09 100644 --- a/dts/src/arm/am437x-idk-evm.dts +++ b/dts/src/arm/am437x-idk-evm.dts @@ -526,11 +526,11 @@ * Supply voltage supervisor on board will not allow opp50 so * disable it and set opp100 as suspend OPP. */ - opp50@300000000 { + opp50-300000000 { status = "disabled"; }; - opp100@600000000 { + opp100-600000000 { opp-suspend; }; }; diff --git a/dts/src/arm/bcm2711-rpi-4-b.dts b/dts/src/arm/bcm2711-rpi-4-b.dts index 1b5a835f66..efea891b1a 100644 --- a/dts/src/arm/bcm2711-rpi-4-b.dts +++ b/dts/src/arm/bcm2711-rpi-4-b.dts @@ -21,6 +21,7 @@ aliases { ethernet0 = &genet; + pcie0 = &pcie0; }; leds { @@ -31,6 +32,8 @@ pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; }; }; diff --git a/dts/src/arm/bcm2837-rpi-3-a-plus.dts b/dts/src/arm/bcm2837-rpi-3-a-plus.dts index 66ab35eccb..28be0332c1 100644 --- a/dts/src/arm/bcm2837-rpi-3-a-plus.dts +++ b/dts/src/arm/bcm2837-rpi-3-a-plus.dts @@ -26,6 +26,8 @@ pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; }; }; }; diff --git a/dts/src/arm/bcm2837-rpi-3-b-plus.dts b/dts/src/arm/bcm2837-rpi-3-b-plus.dts index 74ed6d0478..3734314864 100644 --- a/dts/src/arm/bcm2837-rpi-3-b-plus.dts +++ b/dts/src/arm/bcm2837-rpi-3-b-plus.dts @@ -27,6 +27,8 @@ pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; }; }; diff --git a/dts/src/arm/dra7-evm.dts b/dts/src/arm/dra7-evm.dts index de7f85efaa..af06a55d1c 100644 --- a/dts/src/arm/dra7-evm.dts +++ b/dts/src/arm/dra7-evm.dts @@ -61,10 +61,10 @@ regulator-max-microvolt = <1800000>; }; - evm_3v3: fixedregulator-evm3v3 { + vsys_3v3: fixedregulator-vsys3v3 { /* Output of Cntlr A of TPS43351-Q1 on dra7-evm */ compatible = "regulator-fixed"; - regulator-name = "evm_3v3"; + regulator-name = "vsys_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&evm_12v0>; diff --git a/dts/src/arm/dra7-l4.dtsi b/dts/src/arm/dra7-l4.dtsi index fc41883489..2119a78e9c 100644 --- a/dts/src/arm/dra7-l4.dtsi +++ b/dts/src/arm/dra7-l4.dtsi @@ -3474,6 +3474,7 @@ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>; clock-names = "fck"; interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; }; }; @@ -3501,6 +3502,7 @@ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>; clock-names = "fck"; interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; }; }; @@ -3528,6 +3530,7 @@ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; clock-names = "fck"; interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; }; }; @@ -3555,6 +3558,7 @@ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; clock-names = "fck"; interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; }; }; diff --git a/dts/src/arm/dra7.dtsi b/dts/src/arm/dra7.dtsi index d78b684e7f..4305051bb7 100644 --- a/dts/src/arm/dra7.dtsi +++ b/dts/src/arm/dra7.dtsi @@ -184,6 +184,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x20013000 0x13000 0 0xffed000>; + dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>; bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; @@ -238,6 +239,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x30013000 0x13000 0 0xffed000>; + dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>; bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; diff --git a/dts/src/arm/dra76x.dtsi b/dts/src/arm/dra76x.dtsi index 2f7539afef..42b8a205b6 100644 --- a/dts/src/arm/dra76x.dtsi +++ b/dts/src/arm/dra76x.dtsi @@ -128,3 +128,8 @@ &usb4_tm { status = "disabled"; }; + +&mmc3 { + /* dra76x is not affected by i887 */ + max-frequency = <96000000>; +}; diff --git a/dts/src/arm/dra7xx-clocks.dtsi b/dts/src/arm/dra7xx-clocks.dtsi index 55cef4cac5..dc0a93bccb 100644 --- a/dts/src/arm/dra7xx-clocks.dtsi +++ b/dts/src/arm/dra7xx-clocks.dtsi @@ -796,16 +796,6 @@ clock-div = <1>; }; - ipu1_gfclk_mux: ipu1_gfclk_mux@520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; - ti,bit-shift = <24>; - reg = <0x0520>; - assigned-clocks = <&ipu1_gfclk_mux>; - assigned-clock-parents = <&dpll_core_h22x2_ck>; - }; - dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; @@ -1564,6 +1554,8 @@ compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; + assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>; + assigned-clock-parents = <&dpll_core_h22x2_ck>; }; ipu_clkctrl: ipu-clkctrl@50 { diff --git a/dts/src/arm/imx6dl-colibri-eval-v3.dts b/dts/src/arm/imx6dl-colibri-eval-v3.dts index cd075621de..84fcc203a2 100644 --- a/dts/src/arm/imx6dl-colibri-eval-v3.dts +++ b/dts/src/arm/imx6dl-colibri-eval-v3.dts @@ -275,7 +275,7 @@ /* SRAM on Colibri nEXT_CS0 */ sram@0,0 { - compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram"; + compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram"; reg = <0 0 0x00010000>; #address-cells = <1>; #size-cells = <1>; @@ -286,7 +286,7 @@ /* SRAM on Colibri nEXT_CS1 */ sram@1,0 { - compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram"; + compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram"; reg = <1 0 0x00010000>; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/src/arm/imx6qdl-phytec-phycore-som.dtsi b/dts/src/arm/imx6qdl-phytec-phycore-som.dtsi index 978dc1c2ff..4d18952658 100644 --- a/dts/src/arm/imx6qdl-phytec-phycore-som.dtsi +++ b/dts/src/arm/imx6qdl-phytec-phycore-som.dtsi @@ -192,7 +192,6 @@ pinctrl-0 = <&pinctrl_usdhc4>; bus-width = <8>; non-removable; - vmmc-supply = <&vdd_emmc_1p8>; status = "disabled"; }; diff --git a/dts/src/arm/imx7-colibri.dtsi b/dts/src/arm/imx7-colibri.dtsi index d05be3f0e2..04717cf69d 100644 --- a/dts/src/arm/imx7-colibri.dtsi +++ b/dts/src/arm/imx7-colibri.dtsi @@ -336,7 +336,6 @@ assigned-clock-rates = <400000000>; bus-width = <8>; fsl,tuning-step = <2>; - max-frequency = <100000000>; vmmc-supply = <®_module_3v3>; vqmmc-supply = <®_DCDC3>; non-removable; diff --git a/dts/src/arm/imx7d.dtsi b/dts/src/arm/imx7d.dtsi index 92f6d0c2a7..4c22828df5 100644 --- a/dts/src/arm/imx7d.dtsi +++ b/dts/src/arm/imx7d.dtsi @@ -44,7 +44,7 @@ opp-hz = /bits/ 64 <792000000>; opp-microvolt = <1000000>; clock-latency-ns = <150000>; - opp-supported-hw = <0xd>, <0xf>; + opp-supported-hw = <0xd>, <0x7>; opp-suspend; }; @@ -52,7 +52,7 @@ opp-hz = /bits/ 64 <996000000>; opp-microvolt = <1100000>; clock-latency-ns = <150000>; - opp-supported-hw = <0xc>, <0xf>; + opp-supported-hw = <0xc>, <0x7>; opp-suspend; }; @@ -60,7 +60,7 @@ opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1225000>; clock-latency-ns = <150000>; - opp-supported-hw = <0x8>, <0xf>; + opp-supported-hw = <0x8>, <0x3>; opp-suspend; }; }; diff --git a/dts/src/arm/ls1021a.dtsi b/dts/src/arm/ls1021a.dtsi index 0855b1fe98..760a68c163 100644 --- a/dts/src/arm/ls1021a.dtsi +++ b/dts/src/arm/ls1021a.dtsi @@ -747,7 +747,7 @@ }; mdio0: mdio@2d24000 { - compatible = "fsl,etsec2-mdio"; + compatible = "gianfar"; device_type = "mdio"; #address-cells = <1>; #size-cells = <0>; @@ -756,7 +756,7 @@ }; mdio1: mdio@2d64000 { - compatible = "fsl,etsec2-mdio"; + compatible = "gianfar"; device_type = "mdio"; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm/motorola-mapphone-common.dtsi b/dts/src/arm/motorola-mapphone-common.dtsi index 85665506f4..b6e82b165f 100644 --- a/dts/src/arm/motorola-mapphone-common.dtsi +++ b/dts/src/arm/motorola-mapphone-common.dtsi @@ -182,6 +182,14 @@ pwm-names = "enable", "direction"; direction-duty-cycle-ns = <10000000>; }; + + backlight: backlight { + compatible = "led-backlight"; + + leds = <&backlight_led>; + brightness-levels = <31 63 95 127 159 191 223 255>; + default-brightness-level = <6>; + }; }; &dss { @@ -205,6 +213,8 @@ vddi-supply = <&lcd_regulator>; reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ + backlight = <&backlight>; + width-mm = <50>; height-mm = <89>; @@ -393,12 +403,11 @@ ramp-up-us = <1024>; ramp-down-us = <8193>; - led@0 { + backlight_led: led@0 { reg = <0>; led-sources = <2>; ti,led-mode = <0>; label = ":backlight"; - linux,default-trigger = "backlight"; }; led@1 { diff --git a/dts/src/arm/r8a7779.dtsi b/dts/src/arm/r8a7779.dtsi index beb9885e6f..c0999e27e9 100644 --- a/dts/src/arm/r8a7779.dtsi +++ b/dts/src/arm/r8a7779.dtsi @@ -377,7 +377,7 @@ }; sata: sata@fc600000 { - compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; + compatible = "renesas,sata-r8a7779"; reg = <0xfc600000 0x200000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7779_CLK_SATA>; diff --git a/dts/src/arm/stih410-b2260.dts b/dts/src/arm/stih410-b2260.dts index 4fbd8e9eb5..e2bb597831 100644 --- a/dts/src/arm/stih410-b2260.dts +++ b/dts/src/arm/stih410-b2260.dts @@ -178,9 +178,6 @@ phy-mode = "rgmii"; pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; - snps,phy-bus-name = "stmmac"; - snps,phy-bus-id = <0>; - snps,phy-addr = <0>; snps,reset-gpio = <&pio0 7 0>; snps,reset-active-low; snps,reset-delays-us = <0 10000 1000000>; diff --git a/dts/src/arm/stihxxx-b2120.dtsi b/dts/src/arm/stihxxx-b2120.dtsi index 60e11045ad..d051f080e5 100644 --- a/dts/src/arm/stihxxx-b2120.dtsi +++ b/dts/src/arm/stihxxx-b2120.dtsi @@ -46,7 +46,7 @@ /* DAC */ format = "i2s"; mclk-fs = <256>; - frame-inversion = <1>; + frame-inversion; cpu { sound-dai = <&sti_uni_player2>; }; diff --git a/dts/src/arm64/amlogic/meson-gxm-khadas-vim2.dts b/dts/src/arm64/amlogic/meson-gxm-khadas-vim2.dts index f82f25c1a5..d5dc12878d 100644 --- a/dts/src/arm64/amlogic/meson-gxm-khadas-vim2.dts +++ b/dts/src/arm64/amlogic/meson-gxm-khadas-vim2.dts @@ -327,7 +327,7 @@ #size-cells = <0>; bus-width = <4>; - max-frequency = <50000000>; + max-frequency = <60000000>; non-removable; disable-wp; diff --git a/dts/src/arm64/amlogic/meson-sm1-sei610.dts b/dts/src/arm64/amlogic/meson-sm1-sei610.dts index a8bb3fa9fe..cb1b48f5b8 100644 --- a/dts/src/arm64/amlogic/meson-sm1-sei610.dts +++ b/dts/src/arm64/amlogic/meson-sm1-sei610.dts @@ -593,6 +593,7 @@ compatible = "brcm,bcm43438-bt"; interrupt-parent = <&gpio_intc>; interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wakeup"; shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; max-speed = <2000000>; clocks = <&wifi32k>; diff --git a/dts/src/arm64/arm/fvp-base-revc.dts b/dts/src/arm64/arm/fvp-base-revc.dts index 62ab0d54ff..335fff7624 100644 --- a/dts/src/arm64/arm/fvp-base-revc.dts +++ b/dts/src/arm64/arm/fvp-base-revc.dts @@ -161,10 +161,10 @@ bus-range = <0x0 0x1>; reg = <0x0 0x40000000 0x0 0x10000000>; ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; msi-map = <0x0 &its 0x0 0x10000>; iommu-map = <0x0 &smmu 0x0 0x10000>; diff --git a/dts/src/arm64/freescale/fsl-ls1043-post.dtsi b/dts/src/arm64/freescale/fsl-ls1043-post.dtsi index 6082ae0221..d237162a87 100644 --- a/dts/src/arm64/freescale/fsl-ls1043-post.dtsi +++ b/dts/src/arm64/freescale/fsl-ls1043-post.dtsi @@ -20,6 +20,8 @@ }; &fman0 { + fsl,erratum-a050385; + /* these aliases provide the FMan ports mapping */ enet0: ethernet@e0000 { }; diff --git a/dts/src/arm64/freescale/imx8qxp-mek.dts b/dts/src/arm64/freescale/imx8qxp-mek.dts index d3d26cca7d..13460a360c 100644 --- a/dts/src/arm64/freescale/imx8qxp-mek.dts +++ b/dts/src/arm64/freescale/imx8qxp-mek.dts @@ -52,11 +52,6 @@ compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; }; }; diff --git a/dts/src/arm64/intel/socfpga_agilex.dtsi b/dts/src/arm64/intel/socfpga_agilex.dtsi index e1d357eaad..d8c44d3ca1 100644 --- a/dts/src/arm64/intel/socfpga_agilex.dtsi +++ b/dts/src/arm64/intel/socfpga_agilex.dtsi @@ -102,7 +102,7 @@ }; gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; reg = <0xff800000 0x2000>; interrupts = <0 90 4>; interrupt-names = "macirq"; @@ -118,7 +118,7 @@ }; gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; reg = <0xff802000 0x2000>; interrupts = <0 91 4>; interrupt-names = "macirq"; @@ -134,7 +134,7 @@ }; gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; reg = <0xff804000 0x2000>; interrupts = <0 92 4>; interrupt-names = "macirq"; diff --git a/dts/src/mips/ingenic/ci20.dts b/dts/src/mips/ingenic/ci20.dts index 37b93166bf..c340f947ba 100644 --- a/dts/src/mips/ingenic/ci20.dts +++ b/dts/src/mips/ingenic/ci20.dts @@ -4,6 +4,8 @@ #include "jz4780.dtsi" #include <dt-bindings/clock/ingenic,tcu.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/regulator/active-semi,8865-regulator.h> / { compatible = "img,ci20", "ingenic,jz4780"; @@ -163,63 +165,71 @@ regulators { vddcore: SUDCDC1 { - regulator-name = "VDDCORE"; + regulator-name = "DCDC_REG1"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; }; vddmem: SUDCDC2 { - regulator-name = "VDDMEM"; + regulator-name = "DCDC_REG2"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; regulator-always-on; }; vcc_33: SUDCDC3 { - regulator-name = "VCC33"; + regulator-name = "DCDC_REG3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; vcc_50: SUDCDC4 { - regulator-name = "VCC50"; + regulator-name = "SUDCDC_REG4"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; }; vcc_25: LDO_REG5 { - regulator-name = "VCC25"; + regulator-name = "LDO_REG5"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; }; wifi_io: LDO_REG6 { - regulator-name = "WIFIIO"; + regulator-name = "LDO_REG6"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; }; vcc_28: LDO_REG7 { - regulator-name = "VCC28"; + regulator-name = "LDO_REG7"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; }; vcc_15: LDO_REG8 { - regulator-name = "VCC15"; + regulator-name = "LDO_REG8"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; regulator-always-on; }; - vcc_18: LDO_REG9 { - regulator-name = "VCC18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + vrtc_18: LDO_REG9 { + regulator-name = "LDO_REG9"; + /* Despite the datasheet stating 3.3V + * for REG9 and the driver expecting that, + * REG9 outputs 1.8V. + * Likely the CI20 uses a proprietary + * factory programmed chip variant. + * Since this is a simple on/off LDO the + * exact values do not matter. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; }; vcc_11: LDO_REG10 { - regulator-name = "VCC11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; + regulator-name = "LDO_REG10"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; regulator-always-on; }; }; @@ -261,7 +271,9 @@ rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; - interrupts = <110>; + + interrupt-parent = <&gpf>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/dts/src/mips/ingenic/jz4740.dtsi b/dts/src/mips/ingenic/jz4740.dtsi index 5accda2767..a3301bab92 100644 --- a/dts/src/mips/ingenic/jz4740.dtsi +++ b/dts/src/mips/ingenic/jz4740.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include <dt-bindings/clock/jz4740-cgu.h> +#include <dt-bindings/clock/ingenic,tcu.h> / { #address-cells = <1>; @@ -45,14 +46,6 @@ #clock-cells = <1>; }; - watchdog: watchdog@10002000 { - compatible = "ingenic,jz4740-watchdog"; - reg = <0x10002000 0x10>; - - clocks = <&cgu JZ4740_CLK_RTC>; - clock-names = "rtc"; - }; - tcu: timer@10002000 { compatible = "ingenic,jz4740-tcu", "simple-mfd"; reg = <0x10002000 0x1000>; @@ -73,6 +66,14 @@ interrupt-parent = <&intc>; interrupts = <23 22 21>; + + watchdog: watchdog@0 { + compatible = "ingenic,jz4740-watchdog"; + reg = <0x0 0xc>; + + clocks = <&tcu TCU_CLK_WDT>; + clock-names = "wdt"; + }; }; rtc_dev: rtc@10003000 { diff --git a/dts/src/mips/ingenic/jz4780.dtsi b/dts/src/mips/ingenic/jz4780.dtsi index f928329b03..bb89653d16 100644 --- a/dts/src/mips/ingenic/jz4780.dtsi +++ b/dts/src/mips/ingenic/jz4780.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include <dt-bindings/clock/jz4780-cgu.h> +#include <dt-bindings/clock/ingenic,tcu.h> #include <dt-bindings/dma/jz4780-dma.h> / { @@ -67,6 +68,14 @@ interrupt-parent = <&intc>; interrupts = <27 26 25>; + + watchdog: watchdog@0 { + compatible = "ingenic,jz4780-watchdog"; + reg = <0x0 0xc>; + + clocks = <&tcu TCU_CLK_WDT>; + clock-names = "wdt"; + }; }; rtc_dev: rtc@10003000 { @@ -348,14 +357,6 @@ status = "disabled"; }; - watchdog: watchdog@10002000 { - compatible = "ingenic,jz4780-watchdog"; - reg = <0x10002000 0x10>; - - clocks = <&cgu JZ4780_CLK_RTCLK>; - clock-names = "rtc"; - }; - nemc: nemc@13410000 { compatible = "ingenic,jz4780-nemc"; reg = <0x13410000 0x10000>; diff --git a/dts/src/mips/ingenic/x1000.dtsi b/dts/src/mips/ingenic/x1000.dtsi index 4994c695a1..147f7d5c24 100644 --- a/dts/src/mips/ingenic/x1000.dtsi +++ b/dts/src/mips/ingenic/x1000.dtsi @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/clock/ingenic,tcu.h> #include <dt-bindings/clock/x1000-cgu.h> #include <dt-bindings/dma/x1000-dma.h> @@ -72,7 +73,7 @@ compatible = "ingenic,x1000-watchdog", "ingenic,jz4780-watchdog"; reg = <0x0 0x10>; - clocks = <&cgu X1000_CLK_RTCLK>; + clocks = <&tcu TCU_CLK_WDT>; clock-names = "wdt"; }; }; @@ -158,7 +159,6 @@ i2c0: i2c-controller@10050000 { compatible = "ingenic,x1000-i2c"; reg = <0x10050000 0x1000>; - #address-cells = <1>; #size-cells = <0>; @@ -173,7 +173,6 @@ i2c1: i2c-controller@10051000 { compatible = "ingenic,x1000-i2c"; reg = <0x10051000 0x1000>; - #address-cells = <1>; #size-cells = <0>; @@ -188,7 +187,6 @@ i2c2: i2c-controller@10052000 { compatible = "ingenic,x1000-i2c"; reg = <0x10052000 0x1000>; - #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/riscv/sifive/hifive-unleashed-a00.dts b/dts/src/riscv/sifive/hifive-unleashed-a00.dts index 609198cb11..4a2729f5ca 100644 --- a/dts/src/riscv/sifive/hifive-unleashed-a00.dts +++ b/dts/src/riscv/sifive/hifive-unleashed-a00.dts @@ -2,6 +2,7 @@ /* Copyright (c) 2018-2019 SiFive, Inc */ #include "fu540-c000.dtsi" +#include <dt-bindings/gpio/gpio.h> /* Clock frequency (in Hz) of the PCB crystal for rtcclk */ #define RTCCLK_FREQ 1000000 @@ -41,6 +42,10 @@ clock-frequency = <RTCCLK_FREQ>; clock-output-names = "rtcclk"; }; + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + }; }; &uart0 { diff --git a/fs/devfs.c b/fs/devfs.c index d088c1a66c..e1893d1bd0 100644 --- a/fs/devfs.c +++ b/fs/devfs.c @@ -94,6 +94,26 @@ static int devfs_protect(struct device_d *_dev, FILE *f, size_t count, loff_t of return cdev->ops->protect(cdev, count, offset + cdev->offset, prot); } +static int devfs_discard_range(struct device_d *dev, FILE *f, loff_t count, + loff_t offset) +{ + struct cdev *cdev = f->priv; + + if (!cdev->ops->discard_range) + return -ENOSYS; + + if (cdev->flags & DEVFS_PARTITION_READONLY) + return -EPERM; + + if (offset >= cdev->size) + return 0; + + if (count + offset > cdev->size) + count = cdev->size - offset; + + return cdev->ops->discard_range(cdev, count, offset + cdev->offset); +} + static int devfs_memmap(struct device_d *_dev, FILE *f, void **map, int flags) { struct cdev *cdev = f->priv; @@ -329,6 +349,7 @@ static struct fs_driver_d devfs_driver = { .truncate = devfs_truncate, .erase = devfs_erase, .protect = devfs_protect, + .discard_range = devfs_discard_range, .memmap = devfs_memmap, .flags = FS_DRIVER_NO_DEV, .drv = { @@ -497,6 +497,31 @@ int protect(int fd, size_t count, loff_t offset, int prot) } EXPORT_SYMBOL(protect); +int discard_range(int fd, loff_t count, loff_t offset) +{ + struct fs_driver_d *fsdrv; + FILE *f = fd_to_file(fd); + int ret; + + if (IS_ERR(f)) + return -errno; + if (offset >= f->size) + return 0; + if (count > f->size - offset) + count = f->size - offset; + + fsdrv = f->fsdev->driver; + if (fsdrv->discard_range) + ret = fsdrv->discard_range(&f->fsdev->dev, f, count, offset); + else + ret = -ENOSYS; + + if (ret) + errno = -ret; + + return ret; +} + int protect_file(const char *file, int prot) { int fd, ret; diff --git a/images/Makefile.at91 b/images/Makefile.at91 index f321bdec36..448d71fb98 100644 --- a/images/Makefile.at91 +++ b/images/Makefile.at91 @@ -17,3 +17,7 @@ image-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb.img pblb-$(CONFIG_MACH_SAMA5D27_SOM1) += start_sama5d27_som1_ek FILE_barebox-sama5d27-som1-ek.img = start_sama5d27_som1_ek.pblb image-$(CONFIG_MACH_SAMA5D27_SOM1) += barebox-sama5d27-som1-ek.img + +pblb-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += start_sama5d27_giantboard +FILE_barebox-groboards-sama5d27-giantboard.img = start_sama5d27_giantboard.pblb +image-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += barebox-groboards-sama5d27-giantboard.img diff --git a/include/block.h b/include/block.h index bd87efdc62..a1de266194 100644 --- a/include/block.h +++ b/include/block.h @@ -24,6 +24,9 @@ struct block_device { int rdbufsize; int blkmask; + loff_t discard_start; + loff_t discard_size; + struct list_head buffered_blocks; struct list_head idle_blocks; diff --git a/include/driver.h b/include/driver.h index 6176e6a05f..fac3953ef4 100644 --- a/include/driver.h +++ b/include/driver.h @@ -431,6 +431,7 @@ struct cdev_operations { int (*flush)(struct cdev*); int (*erase)(struct cdev*, loff_t count, loff_t offset); int (*protect)(struct cdev*, size_t count, loff_t offset, int prot); + int (*discard_range)(struct cdev*, loff_t count, loff_t offset); int (*memmap)(struct cdev*, void **map, int flags); int (*truncate)(struct cdev*, size_t size); }; diff --git a/include/fs.h b/include/fs.h index 04ec1329e1..5811199c01 100644 --- a/include/fs.h +++ b/include/fs.h @@ -61,6 +61,8 @@ struct fs_driver_d { loff_t offset); int (*protect)(struct device_d *dev, FILE *f, size_t count, loff_t offset, int prot); + int (*discard_range)(struct device_d *dev, FILE *f, loff_t count, + loff_t offset); int (*memmap)(struct device_d *dev, FILE *f, void **map, int flags); @@ -128,6 +130,7 @@ int umount_by_cdev(struct cdev *cdev); #define ERASE_SIZE_ALL ((loff_t) - 1) int erase(int fd, loff_t count, loff_t offset); int protect(int fd, size_t count, loff_t offset, int prot); +int discard_range(int fd, loff_t count, loff_t offset); int protect_file(const char *file, int prot); void *memmap(int fd, int flags); diff --git a/include/regmap.h b/include/regmap.h index 718bb51979..3bcd9fe038 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -45,6 +45,56 @@ struct regmap *regmap_init(struct device_d *dev, const struct regmap_bus *bus, void *bus_context, const struct regmap_config *config); + +struct clk; + +/** + * of_regmap_init_mmio_clk() - Initialise register map with register clock + * + * @np: Device node that will be interacted with + * @clk_id: register clock consumer ID + * @regs: Pointer to memory-mapped IO region + * @config: Configuration for register map + * + * The return value will be an ERR_PTR() on error or a valid pointer to + * a struct regmap. + */ +struct regmap *of_regmap_init_mmio_clk(struct device_node *np, const char *clk_id, + void __iomem *regs, + const struct regmap_config *config); + +/** + * regmap_init_mmio_clk() - Initialise register map with register clock + * + * @dev: Device that will be interacted with + * @clk_id: register clock consumer ID + * @regs: Pointer to memory-mapped IO region + * @config: Configuration for register map + * + * The return value will be an ERR_PTR() on error or a valid pointer to + * a struct regmap. + */ +struct regmap *regmap_init_mmio_clk(struct device_d *dev, const char *clk_id, + void __iomem *regs, + const struct regmap_config *config); + +/** + * regmap_init_mmio() - Initialise register map + * + * @dev: Device that will be interacted with + * @regs: Pointer to memory-mapped IO region + * @config: Configuration for register map + * + * The return value will be an ERR_PTR() on error or a valid pointer to + * a struct regmap. + */ +#define regmap_init_mmio(dev, regs, config) \ + regmap_init_mmio_clk(dev, NULL, regs, config) + + +int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk); +void regmap_mmio_detach_clk(struct regmap *map); + void regmap_exit(struct regmap *map); struct regmap *dev_get_regmap(struct device_d *dev, const char *name); diff --git a/lib/libfile.c b/lib/libfile.c index 5a1817e32a..dbeed12ccd 100644 --- a/lib/libfile.c +++ b/lib/libfile.c @@ -367,6 +367,8 @@ int copy_file(const char *src, const char *dst, int verbose) goto out; } + discard_range(dstfd, srcstat.st_size, 0); + if (verbose) { if (stat(src, &srcstat) < 0) srcstat.st_size = 0; diff --git a/scripts/bareboximd.c b/scripts/bareboximd.c index cf1b8f693a..e5000e0aea 100644 --- a/scripts/bareboximd.c +++ b/scripts/bareboximd.c @@ -16,10 +16,6 @@ * */ -#define __ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) -#define ALIGN(x, a) __ALIGN_MASK(x, (typeof(x))(a) - 1) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - #include <stdio.h> #include <sys/types.h> #include <stdint.h> diff --git a/scripts/include/linux/kernel.h b/scripts/include/linux/kernel.h index 5d94e984f1..dc2e64e164 100644 --- a/scripts/include/linux/kernel.h +++ b/scripts/include/linux/kernel.h @@ -6,6 +6,8 @@ #include <stdlib.h> #include <assert.h> +#define __ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) +#define ALIGN(x, a) __ALIGN_MASK(x, (typeof(x))(a) - 1) #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) |