summaryrefslogtreecommitdiffstats
path: root/Documentation
diff options
context:
space:
mode:
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/boards/imx.rst3
-rw-r--r--Documentation/boards/imx/amazon-kindle-4-5.rst6
-rw-r--r--Documentation/boards/imx/nxp-imx8mq-evk.rst24
-rw-r--r--Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg86
-rw-r--r--Documentation/boards/imx/zii-imx8mq-dev/readme.rst24
-rw-r--r--Documentation/devicetree/bindings/barebox/barebox,state.rst2
-rw-r--r--Documentation/user/state.rst1
7 files changed, 134 insertions, 12 deletions
diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst
index 2e6a30fd2f..27d0123c87 100644
--- a/Documentation/boards/imx.rst
+++ b/Documentation/boards/imx.rst
@@ -201,6 +201,7 @@ or ``imx_defconfig`` instead.
.. toctree::
:glob:
- :maxdepth: 1
+ :maxdepth: 2
imx/*
+ imx/*/*
diff --git a/Documentation/boards/imx/amazon-kindle-4-5.rst b/Documentation/boards/imx/amazon-kindle-4-5.rst
index 58f38a058e..26f072e28d 100644
--- a/Documentation/boards/imx/amazon-kindle-4-5.rst
+++ b/Documentation/boards/imx/amazon-kindle-4-5.rst
@@ -36,13 +36,15 @@ USB bootloader mode by the SoC microcode:
1. Connect the Kindle to your host computer with a USB cable.
2. Power down the device by holding the power button until the power LED goes
dark (about 10 seconds).
-4. Hold the power button, and hold down a device-specific special key:
+3. Hold the power button, and hold down a device-specific special key:
+
* the fiveway down button on the model D01100
* the home button on model D01200
+
4. Then release the power button, but still hold the special key.
5. A new USB device named ``NS Blank CODEX`` should appear on your host computer.
You can now release the special button.
-7. Finally, upload barebox to the Kindle by using:
+6. Finally, upload barebox to the Kindle by using:
.. code-block:: console
diff --git a/Documentation/boards/imx/nxp-imx8mq-evk.rst b/Documentation/boards/imx/nxp-imx8mq-evk.rst
index dfe004e0e4..8bad9455a5 100644
--- a/Documentation/boards/imx/nxp-imx8mq-evk.rst
+++ b/Documentation/boards/imx/nxp-imx8mq-evk.rst
@@ -8,17 +8,17 @@ Board comes with:
Not including booting via serial, the device can boot from either SD or eMMC.
-Downloading DDR PHY Firmware
-----------------------------
+Downloading DDR PHY and HDMI/eDP Firmware
+-----------------------------------------
As a part of DDR intialization routine NXP i.MX8MQ EVK requires and
uses several binary firmware blobs that are distributed under a
separate EULA and cannot be included in Barebox. In order to obtain
them do the following::
- wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.2.bin
- chmod +x firmware-imx-7.2.bin
- ./firmware-imx-7.2.bin
+ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
+ chmod +x firmware-imx-8.0.bin
+ ./firmware-imx-8.0.bin
Executing that file should produce a EULA acceptance dialog as well as
result in the following files:
@@ -36,8 +36,18 @@ As a last step of this process those files need to be placed in
lpddr4_pmu_train_2d_dmem.bin \
lpddr4_pmu_train_2d_imem.bin; \
do \
- cp firmware-imx-7.2/firmware/ddr/synopsys/${f} \
- firmware/imx/${f}; \
+ cp firmware-imx-8.0/firmware/ddr/synopsys/${f} \
+ firmware/${f}; \
+ done
+
+You will also need to copy the HDMITX controller firmware in order to
+use the HDMI and/or eDP display output::
+
+ for f in signed_dp_imx8m.bin \
+ signed_hdmi_imx8m.bin; \
+ do \
+ cp firmware-imx-8.0/firmware/hdmi/cadence/${f} \
+ firmware/${f}; \
done
DDR Configuration Code
diff --git a/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg b/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg
new file mode 100644
index 0000000000..31f94227e6
--- /dev/null
+++ b/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg
@@ -0,0 +1,86 @@
+interface ftdi
+ftdi_vid_pid 0x0403 0x6011
+
+ftdi_layout_init 0x0038 0x003b
+ftdi_layout_signal nSRST -data 0x0010
+ftdi_layout_signal LED -data 0x0020
+
+# Board has a standard ARM-20 JTAG connector with
+# nSRST available.
+reset_config srst_only srst_push_pull connect_deassert_srst
+
+# select JTAG
+transport select jtag
+
+# set a slow default JTAG clock, can be overridden later
+adapter_khz 1000
+
+# delay after SRST goes inactive
+adapter_nsrst_delay 70
+
+# board has an i.MX8MQ with 4 Cortex-A53 cores
+set CHIPNAME imx8mq
+set CHIPCORES 4
+
+# source SoC configuration
+source [find target/imx8m.cfg]
+source [find mem_helper.tcl]
+
+proc ddr_init { } {
+ #
+ # We use the same start address as is configured in our i.MX boot
+ # header (address originally taken from U-Boot).
+ #
+ set IMX8MQ_TCM_BASE_ADDR 0x007e1000
+ set IMX8MQ_TCM_MAX_SIZE 0x3f000
+ #
+ # Header word at offset 0x28 is not used on AArch64 and is just
+ # filled with placeholder value 0xffff_ffff, see
+ # arch/arm/include/asm/barebox-arm-head.h for more details
+ #
+ set RDU3_TCM_MAIC_LOCATION [expr $IMX8MQ_TCM_BASE_ADDR + 0x28]
+ set RDU3_TCM_MAGIC_REQUEST 0xdeadbeef
+ set RDU3_TCM_MAGIC_REPLY 0xbaadf00d
+
+ echo "==== Uploading DDR helper ===="
+
+ halt
+ load_image images/start_zii_imx8mq_dev.pblb \
+ $IMX8MQ_TCM_BASE_ADDR \
+ bin \
+ $IMX8MQ_TCM_BASE_ADDR \
+ $IMX8MQ_TCM_MAX_SIZE
+
+ echo "==== Running DDR helper ===="
+
+ mww phys $RDU3_TCM_MAIC_LOCATION $RDU3_TCM_MAGIC_REQUEST
+ resume $IMX8MQ_TCM_BASE_ADDR
+
+ echo "==== Waiting for DDR helper to finish ===="
+
+ if {[catch {wait_halt} errmsg] ||
+ [mrw $RDU3_TCM_MAIC_LOCATION] != $RDU3_TCM_MAGIC_REPLY} {
+ echo "==== DDR initialization FAILED ===="
+ } else {
+ echo "==== DDR is ready ===="
+ }
+}
+
+proc start_barebox {} {
+ #
+ # We have to place our image at MX8MQ_ATF_BL33_BASE_ADDR in order
+ # to be able to initialize ATF firmware since that's where it
+ # expects entry point to BL33 would be
+ #
+ set MX8MQ_ATF_BL33_BASE_ADDR 0x40200000
+
+ echo "==== Starting Barebox ===="
+ load_image images/start_zii_imx8mq_dev.pblb $MX8MQ_ATF_BL33_BASE_ADDR bin
+ resume $MX8MQ_ATF_BL33_BASE_ADDR
+}
+
+# proc board_init { } {
+# ddr_init
+# }
+
+# ${_TARGETNAME}.0 configure -event reset-init { board_init }
diff --git a/Documentation/boards/imx/zii-imx8mq-dev/readme.rst b/Documentation/boards/imx/zii-imx8mq-dev/readme.rst
new file mode 100644
index 0000000000..dc031e4af4
--- /dev/null
+++ b/Documentation/boards/imx/zii-imx8mq-dev/readme.rst
@@ -0,0 +1,24 @@
+ZII i.MX8MQ Based Boards
+========================
+
+Building Barebox
+----------------
+
+To build Barebox of ZII i.MX8MQ based board do the following:
+
+.. code-block:: sh
+
+ make ARCH=arm CROSS_COMPILE=<AArch64 toolchain prefix> mrproper
+ make ARCH=arm CROSS_COMPILE=<AArch64 toolchain prefix> imx_v8_defconfig
+ make ARCH=arm CROSS_COMPILE=<AArch64 toolchain prefix>
+
+Uploading Barebox via JTAG
+--------------------------
+
+Barebox can be bootstrapped via JTAG using OpenOCD (latest master) as
+follows:
+
+.. code-block:: sh
+
+ cd barebox
+ openocd -f Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg --command "init; ddr_init; start_barebox"
diff --git a/Documentation/devicetree/bindings/barebox/barebox,state.rst b/Documentation/devicetree/bindings/barebox/barebox,state.rst
index 2893937820..390e148a28 100644
--- a/Documentation/devicetree/bindings/barebox/barebox,state.rst
+++ b/Documentation/devicetree/bindings/barebox/barebox,state.rst
@@ -52,7 +52,7 @@ Optional Properties
``circular`` or ``noncircular``. If the backend memory needs to be erased
prior a write it defaults to the ``circular`` storage backend type, for backend
memories like RAMs or EEPROMs it defaults to the ``direct`` storage backend type.
-* ``algo``: A HMAC algorithm used to detect manipulation of the data
+* ``algo``: An HMAC algorithm used to detect manipulation of the data
or header, sensible values follow this pattern ``hmac(<HASH>)``,
e.g. ``hmac(sha256)``. Only available for the ``backend-type`` ``raw``.
* ``keep-previous-content``: Check if a the bucket meta magic field contains
diff --git a/Documentation/user/state.rst b/Documentation/user/state.rst
index 89129add77..07743df0cb 100644
--- a/Documentation/user/state.rst
+++ b/Documentation/user/state.rst
@@ -647,7 +647,6 @@ within the EEPROM.
};
};
};
-};
With this 'backend' definition it's possible to define the *state* variable set
content, its backend-type and *state* variable layout.