diff options
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/boards/imx.rst | 1 | ||||
-rw-r--r-- | Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg | 86 | ||||
-rw-r--r-- | Documentation/boards/imx/zii-imx8mq-dev/readme.rst | 24 |
3 files changed, 111 insertions, 0 deletions
diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst index 6606b88ac7..27d0123c87 100644 --- a/Documentation/boards/imx.rst +++ b/Documentation/boards/imx.rst @@ -204,3 +204,4 @@ or ``imx_defconfig`` instead. :maxdepth: 2 imx/* + imx/*/* diff --git a/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg b/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg new file mode 100644 index 0000000000..31f94227e6 --- /dev/null +++ b/Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg @@ -0,0 +1,86 @@ +interface ftdi +ftdi_vid_pid 0x0403 0x6011 + +ftdi_layout_init 0x0038 0x003b +ftdi_layout_signal nSRST -data 0x0010 +ftdi_layout_signal LED -data 0x0020 + +# Board has a standard ARM-20 JTAG connector with +# nSRST available. +reset_config srst_only srst_push_pull connect_deassert_srst + +# select JTAG +transport select jtag + +# set a slow default JTAG clock, can be overridden later +adapter_khz 1000 + +# delay after SRST goes inactive +adapter_nsrst_delay 70 + +# board has an i.MX8MQ with 4 Cortex-A53 cores +set CHIPNAME imx8mq +set CHIPCORES 4 + +# source SoC configuration +source [find target/imx8m.cfg] +source [find mem_helper.tcl] + +proc ddr_init { } { + # + # We use the same start address as is configured in our i.MX boot + # header (address originally taken from U-Boot). + # + set IMX8MQ_TCM_BASE_ADDR 0x007e1000 + set IMX8MQ_TCM_MAX_SIZE 0x3f000 + # + # Header word at offset 0x28 is not used on AArch64 and is just + # filled with placeholder value 0xffff_ffff, see + # arch/arm/include/asm/barebox-arm-head.h for more details + # + set RDU3_TCM_MAIC_LOCATION [expr $IMX8MQ_TCM_BASE_ADDR + 0x28] + set RDU3_TCM_MAGIC_REQUEST 0xdeadbeef + set RDU3_TCM_MAGIC_REPLY 0xbaadf00d + + echo "==== Uploading DDR helper ====" + + halt + load_image images/start_zii_imx8mq_dev.pblb \ + $IMX8MQ_TCM_BASE_ADDR \ + bin \ + $IMX8MQ_TCM_BASE_ADDR \ + $IMX8MQ_TCM_MAX_SIZE + + echo "==== Running DDR helper ====" + + mww phys $RDU3_TCM_MAIC_LOCATION $RDU3_TCM_MAGIC_REQUEST + resume $IMX8MQ_TCM_BASE_ADDR + + echo "==== Waiting for DDR helper to finish ====" + + if {[catch {wait_halt} errmsg] || + [mrw $RDU3_TCM_MAIC_LOCATION] != $RDU3_TCM_MAGIC_REPLY} { + echo "==== DDR initialization FAILED ====" + } else { + echo "==== DDR is ready ====" + } +} + +proc start_barebox {} { + # + # We have to place our image at MX8MQ_ATF_BL33_BASE_ADDR in order + # to be able to initialize ATF firmware since that's where it + # expects entry point to BL33 would be + # + set MX8MQ_ATF_BL33_BASE_ADDR 0x40200000 + + echo "==== Starting Barebox ====" + load_image images/start_zii_imx8mq_dev.pblb $MX8MQ_ATF_BL33_BASE_ADDR bin + resume $MX8MQ_ATF_BL33_BASE_ADDR +} + +# proc board_init { } { +# ddr_init +# } + +# ${_TARGETNAME}.0 configure -event reset-init { board_init } diff --git a/Documentation/boards/imx/zii-imx8mq-dev/readme.rst b/Documentation/boards/imx/zii-imx8mq-dev/readme.rst new file mode 100644 index 0000000000..dc031e4af4 --- /dev/null +++ b/Documentation/boards/imx/zii-imx8mq-dev/readme.rst @@ -0,0 +1,24 @@ +ZII i.MX8MQ Based Boards +======================== + +Building Barebox +---------------- + +To build Barebox of ZII i.MX8MQ based board do the following: + +.. code-block:: sh + + make ARCH=arm CROSS_COMPILE=<AArch64 toolchain prefix> mrproper + make ARCH=arm CROSS_COMPILE=<AArch64 toolchain prefix> imx_v8_defconfig + make ARCH=arm CROSS_COMPILE=<AArch64 toolchain prefix> + +Uploading Barebox via JTAG +-------------------------- + +Barebox can be bootstrapped via JTAG using OpenOCD (latest master) as +follows: + +.. code-block:: sh + + cd barebox + openocd -f Documentation/boards/imx/zii-imx8mq-dev/openocd.cfg --command "init; ddr_init; start_barebox" |