diff options
Diffstat (limited to 'arch/arm/boards/at91rm9200ek/lowlevel.c')
| -rw-r--r-- | arch/arm/boards/at91rm9200ek/lowlevel.c | 44 |
1 files changed, 23 insertions, 21 deletions
diff --git a/arch/arm/boards/at91rm9200ek/lowlevel.c b/arch/arm/boards/at91rm9200ek/lowlevel.c index a85a22e797..a5c9058552 100644 --- a/arch/arm/boards/at91rm9200ek/lowlevel.c +++ b/arch/arm/boards/at91rm9200ek/lowlevel.c @@ -18,41 +18,43 @@ void static inline access_sdram(void) { - writel(0x00000000, AT91_SDRAM_BASE); + writel(0x00000000, AT91_CHIPSELECT_1); } void __naked __bare_init barebox_arm_reset_vector(void) { u32 r; int i; + void __iomem *mc = IOMEM(AT91RM9200_BASE_MC); + void __iomem *pmc = IOMEM(AT91RM9200_BASE_PMC); arm_cpu_lowlevel_init(); /* * PMC Check if the PLL is already initialized */ - r = at91_pmc_read(AT91_PMC_MCKR); + r = __raw_readl(pmc + AT91_PMC_MCKR); if (r & AT91_PMC_CSS) goto end; /* * Enable the Main Oscillator */ - at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL); + __raw_writel(CONFIG_SYS_MOR_VAL, pmc + AT91_CKGR_MOR); do { - r = at91_pmc_read(AT91_PMC_SR); + r = __raw_readl(pmc + AT91_PMC_SR); } while (!(r & AT91_PMC_MOSCS)); /* * EBI_CFGR */ - at91_sys_write(AT91_EBI_CFGR, CONFIG_SYS_EBI_CFGR_VAL); + __raw_writel(CONFIG_SYS_EBI_CFGR_VAL, mc + AT91RM9200_EBI_CFGR); /* * SMC2_CSR[0]: 16bit, 2 TDF, 4 WS */ - at91_sys_write(AT91_SMC_CSR(0), CONFIG_SYS_SMC_CSR0_VAL); + __raw_writel(CONFIG_SYS_SMC_CSR0_VAL, mc + AT91RM9200_SMC_CSR(0)); /* * Init Clocks @@ -61,24 +63,24 @@ void __naked __bare_init barebox_arm_reset_vector(void) /* * PLLAR: x MHz for PCK */ - at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL); + __raw_writel(CONFIG_SYS_PLLAR_VAL, pmc + AT91_CKGR_PLLAR); do { - r = at91_pmc_read(AT91_PMC_SR); + r = __raw_readl(pmc + AT91_PMC_SR); } while (!(r & AT91_PMC_LOCKA)); /* * PCK/x = MCK Master Clock from SLOW */ - at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL1); + __raw_writel(CONFIG_SYS_MCKR2_VAL1, pmc + AT91_PMC_MCKR); /* * PCK/x = MCK Master Clock from PLLA */ - at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL2); + __raw_writel(CONFIG_SYS_MCKR2_VAL2, pmc + AT91_PMC_MCKR); do { - r = at91_pmc_read(AT91_PMC_SR); + r = __raw_readl(pmc + AT91_PMC_SR); } while (!(r & AT91_PMC_MCKRDY)); /* @@ -86,38 +88,38 @@ void __naked __bare_init barebox_arm_reset_vector(void) */ /* PIOC_ASR: Configure PIOC as peripheral (D16/D31) */ - __raw_writel(CONFIG_SYS_PIOC_ASR_VAL, AT91_BASE_PIOC + PIO_ASR); + __raw_writel(CONFIG_SYS_PIOC_ASR_VAL, AT91RM9200_BASE_PIOC + PIO_ASR); /* PIOC_BSR */ - __raw_writel(CONFIG_SYS_PIOC_BSR_VAL, AT91_BASE_PIOC + PIO_BSR); + __raw_writel(CONFIG_SYS_PIOC_BSR_VAL, AT91RM9200_BASE_PIOC + PIO_BSR); /* PIOC_PDR */ - __raw_writel(CONFIG_SYS_PIOC_PDR_VAL, AT91_BASE_PIOC + PIO_PDR); + __raw_writel(CONFIG_SYS_PIOC_PDR_VAL, AT91RM9200_BASE_PIOC + PIO_PDR); /* EBI_CSA : CS1=SDRAM */ - at91_sys_write(AT91_EBI_CSA, CONFIG_SYS_EBI_CSA_VAL); + __raw_writel(CONFIG_SYS_EBI_CSA_VAL, mc + AT91RM9200_EBI_CSA); /* SDRC_CR */ - at91_sys_write(AT91_SDRAMC_CR, CONFIG_SYS_SDRC_CR_VAL); + __raw_writel(CONFIG_SYS_SDRC_CR_VAL, mc + AT91RM9200_SDRAMC_CR); /* SDRC_MR : Precharge All */ - at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE); + __raw_writel(AT91RM9200_SDRAMC_MODE_PRECHARGE, mc + AT91RM9200_SDRAMC_MR); /* access SDRAM */ access_sdram(); /* SDRC_MR : refresh */ - at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH); + __raw_writel(AT91RM9200_SDRAMC_MODE_REFRESH, mc + AT91RM9200_SDRAMC_MR); /* access SDRAM 8 times */ for (i = 0; i < 8; i++) access_sdram(); /* SDRC_MR : Load Mode Register */ - at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR); + __raw_writel(AT91RM9200_SDRAMC_MODE_LMR, mc + AT91RM9200_SDRAMC_MR); /* access SDRAM */ access_sdram(); /* SDRC_TR : Write refresh rate */ - at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL); + __raw_writel(CONFIG_SYS_SDRC_TR_VAL, mc + AT91RM9200_SDRAMC_TR); /* access SDRAM */ access_sdram(); /* SDRC_MR : Normal Mode */ - at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL); + __raw_writel(AT91RM9200_SDRAMC_MODE_NORMAL, mc + AT91RM9200_SDRAMC_MR); /* access SDRAM */ access_sdram(); |