diff options
Diffstat (limited to 'arch/arm/boards/avnet-zedboard/lowlevel.c')
| -rw-r--r-- | arch/arm/boards/avnet-zedboard/lowlevel.c | 100 |
1 files changed, 76 insertions, 24 deletions
diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c index cf3c4ebd0c..6e5a17d7ef 100644 --- a/arch/arm/boards/avnet-zedboard/lowlevel.c +++ b/arch/arm/boards/avnet-zedboard/lowlevel.c @@ -1,34 +1,33 @@ -/* - * - * (c) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> + #include <common.h> #include <io.h> #include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> -#include <mach/zynq7000-regs.h> +#include <mach/zynq/init.h> +#include <mach/zynq/zynq7000-regs.h> +#include <serial/cadence.h> #define DCI_DONE (1 << 13) #define PLL_ARM_LOCK (1 << 0) #define PLL_DDR_LOCK (1 << 1) #define PLL_IO_LOCK (1 << 2) -void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +extern char __dtb_z_zynq_zed_start[]; + +static void avnet_zedboard_ps7_init(void) { + /* + * Read OCM mapping configuration, if only the upper 64 KByte are + * mapped to the high address, it's very likely that we just got control + * from the BootROM. If the mapping is changed something other than the + * BootROM was running before us. Skip PS7 init to avoid cutting the + * branch we are sitting on in that case. + */ + if ((readl(0xf8000910) & 0xf) != 0x8) + return; + /* open sesame */ writel(0x0000DF0D, ZYNQ_SLCR_UNLOCK); @@ -229,13 +228,22 @@ void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) /* UART1 pinmux */ writel(0x000002E1, ZYNQ_MIO_BASE + 0xC8); writel(0x000002E0, ZYNQ_MIO_BASE + 0xCC); + /* QSPI pinmux */ + writel(0x00001602, ZYNQ_MIO_BASE + 0x04); + writel(0x00000702, ZYNQ_MIO_BASE + 0x08); + writel(0x00000702, ZYNQ_MIO_BASE + 0x0c); + writel(0x00000702, ZYNQ_MIO_BASE + 0x10); + writel(0x00000702, ZYNQ_MIO_BASE + 0x14); + writel(0x00000702, ZYNQ_MIO_BASE + 0x18); + writel(0x00000602, ZYNQ_MIO_BASE + 0x20); /* poor mans clkctrl */ writel(0x00001403, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_UART_CLK_CTRL); + writel(0x00000101, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_LQSPI_CLK_CTRL); /* GEM0 */ writel(0x00000001, 0xf8000138); - writel(0x00500801, 0xf8000140); + writel(0x00100801, 0xf8000140); writel(0x00000302, 0xf8000740); writel(0x00000302, 0xf8000744); writel(0x00000302, 0xf8000748); @@ -248,14 +256,58 @@ void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) writel(0x00001303, 0xf8000764); writel(0x00001303, 0xf8000768); writel(0x00001303, 0xf800076C); - writel(0x00001280, 0xf80007D0); - writel(0x00001280, 0xf80007D4); + writel(0x00000280, 0xf80007D0); + writel(0x00000280, 0xf80007D4); writel(0x00000001, 0xf8000B00); + /* FPGA Clock Control */ + writel(0x00101400, 0xf8000170); + writel(0x00101400, 0xf8000180); + writel(0x00101400, 0xf8000190); + writel(0x00101400, 0xf80001a0); + + /* PCAP Clock Control */ + writel(0x00000501, 0xf8000168); + /* lock up. secure, secure */ writel(0x0000767B, ZYNQ_SLCR_LOCK); +} + +static void avnet_zedboard_pbl_console_init(void) +{ + relocate_to_current_adr(); + setup_c(); + barrier(); + + cadence_uart_init((void *)ZYNQ_UART1_BASE_ADDR); + pbl_set_putc(cadence_uart_putc, (void *)ZYNQ_UART1_BASE_ADDR); + + pr_debug("\nAvnet ZedBoard PBL\n"); +} + +ENTRY_FUNCTION(start_avnet_zedboard, r0, r1, r2) +{ + + void *fdt = __dtb_z_zynq_zed_start + get_runtime_offset(); + + /* MIO_07 in GPIO Mode 3.3V VIO, can be uncomented because it is the default value */ + writel(0x0000DF0D, ZYNQ_SLCR_UNLOCK); + writel(0x00000600, 0xF800071C ); + writel(0x0000767B, ZYNQ_SLCR_LOCK); + + /* turns on the LED MIO_07 */ + writel((1<<7), 0xe000a204 ); // Direction + writel((1<<7), 0xe000a208 ); // Output enable + writel((1<<7), 0xe000a040 ); // DATA Register arm_cpu_lowlevel_init(); - barebox_arm_entry(0, SZ_512M, NULL); + zynq_cpu_lowlevel_init(); + + avnet_zedboard_ps7_init(); + + if (IS_ENABLED(CONFIG_PBL_CONSOLE)) + avnet_zedboard_pbl_console_init(); + + barebox_arm_entry(0, SZ_512M, fdt); } |