diff options
Diffstat (limited to 'arch/arm/boards/avnet-zedboard')
| -rw-r--r-- | arch/arm/boards/avnet-zedboard/Makefile | 3 | ||||
| -rw-r--r-- | arch/arm/boards/avnet-zedboard/board.c | 43 | ||||
| -rw-r--r-- | arch/arm/boards/avnet-zedboard/flash_header.c | 62 | ||||
| -rw-r--r-- | arch/arm/boards/avnet-zedboard/lowlevel.c | 100 | ||||
| -rw-r--r-- | arch/arm/boards/avnet-zedboard/zedboard.zynqcfg | 24 |
5 files changed, 106 insertions, 126 deletions
diff --git a/arch/arm/boards/avnet-zedboard/Makefile b/arch/arm/boards/avnet-zedboard/Makefile index a2c3104e6c..da63d2625f 100644 --- a/arch/arm/boards/avnet-zedboard/Makefile +++ b/arch/arm/boards/avnet-zedboard/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o -lwl-y += flash_header.o diff --git a/arch/arm/boards/avnet-zedboard/board.c b/arch/arm/boards/avnet-zedboard/board.c index 722bda302e..15332189ca 100644 --- a/arch/arm/boards/avnet-zedboard/board.c +++ b/arch/arm/boards/avnet-zedboard/board.c @@ -1,54 +1,19 @@ -/* - * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> #include <asm/armlinux.h> #include <common.h> #include <environment.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include <init.h> -#include <mach/devices.h> -#include <mach/zynq7000-regs.h> +#include <mach/zynq/zynq7000-regs.h> #include <linux/sizes.h> -static int zedboard_mem_init(void) -{ - arm_add_mem_device("ram0", 0, SZ_512M); - - return 0; -} -mem_initcall(zedboard_mem_init); - -static struct macb_platform_data macb_pdata = { - .phy_interface = PHY_INTERFACE_MODE_RGMII, - .phy_addr = 0x0, -}; - -static int zedboard_device_init(void) -{ - zynq_add_eth0(&macb_pdata); - - return 0; -} -device_initcall(zedboard_device_init); static int zedboard_console_init(void) { - barebox_set_model("Avnet ZedBoard"); barebox_set_hostname("zedboard"); - zynq_add_uart1(); - return 0; } console_initcall(zedboard_console_init); diff --git a/arch/arm/boards/avnet-zedboard/flash_header.c b/arch/arm/boards/avnet-zedboard/flash_header.c deleted file mode 100644 index d9eb35b0d5..0000000000 --- a/arch/arm/boards/avnet-zedboard/flash_header.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (C) 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <asm/byteorder.h> -#include <mach/zynq-flash-header.h> -#include <mach/zynq7000-regs.h> -#include <asm/barebox-arm-head.h> - -#define REG(a, v) { .addr = cpu_to_le32(a), .val = cpu_to_le32(v), } - -struct zynq_reg_entry __ps7reg_entry_section reg_entry[] = { - REG(ZYNQ_SLCR_UNLOCK, 0x0000DF0D), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_CLK_621_TRUE, 0x00000001), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_APER_CLK_CTRL, 0x01FC044D), - - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028008), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CFG, 0x000FA220), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028010), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028011), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028010), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028000), - - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E008), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CFG, 0x001452C0), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E010), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E011), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E010), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E000), - - REG(0xf8000150, 0x00000a03), - - /* stop */ - REG(0xFFFFFFFF, 0x00000000), -}; - -struct zynq_flash_header __flash_header_section flash_header = { - .width_det = WIDTH_DETECTION_MAGIC, - .image_id = IMAGE_IDENTIFICATION, - .enc_stat = 0x0, - .user = 0x0, - .flash_offset = 0x8c0, - .length = (unsigned int)&_barebox_image_size, - .res0 = 0x0, - .start_of_exec = 0x0, - .total_len = (unsigned int)&_barebox_image_size, - .res1 = 0x1, - .checksum = 0x0, - .res2 = 0x0, -}; diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c index cf3c4ebd0c..6e5a17d7ef 100644 --- a/arch/arm/boards/avnet-zedboard/lowlevel.c +++ b/arch/arm/boards/avnet-zedboard/lowlevel.c @@ -1,34 +1,33 @@ -/* - * - * (c) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> + #include <common.h> #include <io.h> #include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> -#include <mach/zynq7000-regs.h> +#include <mach/zynq/init.h> +#include <mach/zynq/zynq7000-regs.h> +#include <serial/cadence.h> #define DCI_DONE (1 << 13) #define PLL_ARM_LOCK (1 << 0) #define PLL_DDR_LOCK (1 << 1) #define PLL_IO_LOCK (1 << 2) -void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +extern char __dtb_z_zynq_zed_start[]; + +static void avnet_zedboard_ps7_init(void) { + /* + * Read OCM mapping configuration, if only the upper 64 KByte are + * mapped to the high address, it's very likely that we just got control + * from the BootROM. If the mapping is changed something other than the + * BootROM was running before us. Skip PS7 init to avoid cutting the + * branch we are sitting on in that case. + */ + if ((readl(0xf8000910) & 0xf) != 0x8) + return; + /* open sesame */ writel(0x0000DF0D, ZYNQ_SLCR_UNLOCK); @@ -229,13 +228,22 @@ void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) /* UART1 pinmux */ writel(0x000002E1, ZYNQ_MIO_BASE + 0xC8); writel(0x000002E0, ZYNQ_MIO_BASE + 0xCC); + /* QSPI pinmux */ + writel(0x00001602, ZYNQ_MIO_BASE + 0x04); + writel(0x00000702, ZYNQ_MIO_BASE + 0x08); + writel(0x00000702, ZYNQ_MIO_BASE + 0x0c); + writel(0x00000702, ZYNQ_MIO_BASE + 0x10); + writel(0x00000702, ZYNQ_MIO_BASE + 0x14); + writel(0x00000702, ZYNQ_MIO_BASE + 0x18); + writel(0x00000602, ZYNQ_MIO_BASE + 0x20); /* poor mans clkctrl */ writel(0x00001403, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_UART_CLK_CTRL); + writel(0x00000101, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_LQSPI_CLK_CTRL); /* GEM0 */ writel(0x00000001, 0xf8000138); - writel(0x00500801, 0xf8000140); + writel(0x00100801, 0xf8000140); writel(0x00000302, 0xf8000740); writel(0x00000302, 0xf8000744); writel(0x00000302, 0xf8000748); @@ -248,14 +256,58 @@ void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) writel(0x00001303, 0xf8000764); writel(0x00001303, 0xf8000768); writel(0x00001303, 0xf800076C); - writel(0x00001280, 0xf80007D0); - writel(0x00001280, 0xf80007D4); + writel(0x00000280, 0xf80007D0); + writel(0x00000280, 0xf80007D4); writel(0x00000001, 0xf8000B00); + /* FPGA Clock Control */ + writel(0x00101400, 0xf8000170); + writel(0x00101400, 0xf8000180); + writel(0x00101400, 0xf8000190); + writel(0x00101400, 0xf80001a0); + + /* PCAP Clock Control */ + writel(0x00000501, 0xf8000168); + /* lock up. secure, secure */ writel(0x0000767B, ZYNQ_SLCR_LOCK); +} + +static void avnet_zedboard_pbl_console_init(void) +{ + relocate_to_current_adr(); + setup_c(); + barrier(); + + cadence_uart_init((void *)ZYNQ_UART1_BASE_ADDR); + pbl_set_putc(cadence_uart_putc, (void *)ZYNQ_UART1_BASE_ADDR); + + pr_debug("\nAvnet ZedBoard PBL\n"); +} + +ENTRY_FUNCTION(start_avnet_zedboard, r0, r1, r2) +{ + + void *fdt = __dtb_z_zynq_zed_start + get_runtime_offset(); + + /* MIO_07 in GPIO Mode 3.3V VIO, can be uncomented because it is the default value */ + writel(0x0000DF0D, ZYNQ_SLCR_UNLOCK); + writel(0x00000600, 0xF800071C ); + writel(0x0000767B, ZYNQ_SLCR_LOCK); + + /* turns on the LED MIO_07 */ + writel((1<<7), 0xe000a204 ); // Direction + writel((1<<7), 0xe000a208 ); // Output enable + writel((1<<7), 0xe000a040 ); // DATA Register arm_cpu_lowlevel_init(); - barebox_arm_entry(0, SZ_512M, NULL); + zynq_cpu_lowlevel_init(); + + avnet_zedboard_ps7_init(); + + if (IS_ENABLED(CONFIG_PBL_CONSOLE)) + avnet_zedboard_pbl_console_init(); + + barebox_arm_entry(0, SZ_512M, fdt); } diff --git a/arch/arm/boards/avnet-zedboard/zedboard.zynqcfg b/arch/arm/boards/avnet-zedboard/zedboard.zynqcfg new file mode 100644 index 0000000000..c6a96aec7b --- /dev/null +++ b/arch/arm/boards/avnet-zedboard/zedboard.zynqcfg @@ -0,0 +1,24 @@ +#include <zynq/zynq7000-header-regs.h> + +wm 32 ZYNQ_SLCR_UNLOCK 0x0000DF0D +wm 32 ZYNQ_CLK_621_TRUE 0x00000001 +wm 32 ZYNQ_APER_CLK_CTRL 0x01FC044D + +wm 32 ZYNQ_ARM_PLL_CTRL 0x00028008 +wm 32 ZYNQ_ARM_PLL_CFG 0x000FA220 +wm 32 ZYNQ_ARM_PLL_CTRL 0x00028010 +wm 32 ZYNQ_ARM_PLL_CTRL 0x00028011 +wm 32 ZYNQ_ARM_PLL_CTRL 0x00028010 +wm 32 ZYNQ_ARM_PLL_CTRL 0x00028000 + +wm 32 ZYNQ_IO_PLL_CTRL 0x0001E008 +wm 32 ZYNQ_IO_PLL_CFG 0x001452C0 +wm 32 ZYNQ_IO_PLL_CTRL 0x0001E010 +wm 32 ZYNQ_IO_PLL_CTRL 0x0001E011 +wm 32 ZYNQ_IO_PLL_CTRL 0x0001E010 +wm 32 ZYNQ_IO_PLL_CTRL 0x0001E000 + +wm 32 ZYNQ_SDIO_CLK_CTRL 0x00000a03 + +/* stop */ +wm 32 0xFFFFFFFF 0x00000000 |