diff options
Diffstat (limited to 'arch/arm/boards/eukrea_cpuimx27')
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx27/Makefile | 3 | ||||
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx27/config.h | 26 | ||||
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx27/env/bin/_update | 36 | ||||
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx27/env/bin/boot | 51 | ||||
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx27/env/bin/hush_hack | 1 | ||||
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx27/env/bin/init | 37 | ||||
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx27/env/bin/update_kernel | 15 | ||||
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx27/env/bin/update_root | 16 | ||||
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx27/env/config | 31 | ||||
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c | 370 | ||||
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.dox | 11 | ||||
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S | 141 |
12 files changed, 738 insertions, 0 deletions
diff --git a/arch/arm/boards/eukrea_cpuimx27/Makefile b/arch/arm/boards/eukrea_cpuimx27/Makefile new file mode 100644 index 0000000000..5d958fa9aa --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/Makefile @@ -0,0 +1,3 @@ + +obj-y += lowlevel_init.o +obj-y += eukrea_cpuimx27.o diff --git a/arch/arm/boards/eukrea_cpuimx27/config.h b/arch/arm/boards/eukrea_cpuimx27/config.h new file mode 100644 index 0000000000..ec6f2123bf --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/config.h @@ -0,0 +1,26 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * @file + * @brief Global defintions for the ARM Eukrea cpuimx27 board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/_update b/arch/arm/boards/eukrea_cpuimx27/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/boot b/arch/arm/boards/eukrea_cpuimx27/env/bin/boot new file mode 100644 index 0000000000..7272e56763 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/boot @@ -0,0 +1,51 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xnand ]; then + root=nand + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$1 = xnor ]; then + root=nor + kernel=nor +fi + +if [ x$root = xnet ]; then + if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" + else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" + fi +else + bootargs="$bootargs ip=off" +fi + +if [ x$root = xnand ]; then + bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" +elif [ x$root = xnor ]; then + bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +elif [ $kernel = nor ]; then + bootm /dev/nor0.kernel +else + bootm /dev/nand0.kernel.bb +fi + diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/hush_hack b/arch/arm/boards/eukrea_cpuimx27/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/init b/arch/arm/boards/eukrea_cpuimx27/env/bin/init new file mode 100644 index 0000000000..3bfd194913 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/init @@ -0,0 +1,37 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +if [ -e /dev/nor0 ]; then + addpart /dev/nor0 $nor_parts +fi + +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel nand|nor [<imagename>] to update kernel into flash" + echo "type update_root nand|nor [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/update_kernel b/arch/arm/boards/eukrea_cpuimx27/env/bin/update_kernel new file mode 100644 index 0000000000..05c822d860 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/update_kernel @@ -0,0 +1,15 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.kernel.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.kernel +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/update_root b/arch/arm/boards/eukrea_cpuimx27/env/bin/update_root new file mode 100644 index 0000000000..eaf36ebcea --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/update_root @@ -0,0 +1,16 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.root.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.root +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 + diff --git a/arch/arm/boards/eukrea_cpuimx27/env/config b/arch/arm/boards/eukrea_cpuimx27/env/config new file mode 100644 index 0000000000..505ada39c7 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/env/config @@ -0,0 +1,31 @@ +#!/bin/sh + +# can be either 'net', 'nor' or 'nand'' +kernel=nor +root=nor + +uimage=mx27/uImage +jffs2=mx27/rootfs.jffs2 + +autoboot_timeout=1 + +# DVI-SVGA DVI-VGA CMO-QVGA +video="CMO-QVGA" +bootargs="console=ttymxc0,115200 fec_mac=$eth0.ethaddr video=mxcfb:$video" + +nor_parts="256k(barebox)ro,128k(bareboxenv),2176k(kernel),-(root)" +rootpart_nor="/dev/mtdblock3" + +nand_parts="-(nand)" +rootpart_nand="" + +nfsroot="" + +# use 'dhcp' to do dhcp in barebox and in kernel +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c new file mode 100644 index 0000000000..1937d21c85 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c @@ -0,0 +1,370 @@ +/* + * Copyright (C) 2009 Eric Benard, Eukrea Electromatique + * Based on pcm038.c which is : + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <errno.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <mach/imx-regs.h> +#include <fec.h> +#include <notifier.h> +#include <mach/gpio.h> +#include <asm/armlinux.h> +#include <asm/mach-types.h> +#include <mach/pmic.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <nand.h> +#include <command.h> +#include <asm/io.h> +#include <mach/imx-nand.h> +#include <mach/imx-pll.h> +#include <mach/imxfb.h> +#include <ns16550.h> +#include <asm/mmu.h> +#include <i2c/i2c.h> +#include <i2c/lp3972.h> +#include <mach/iomux-mx27.h> + +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = 0xC0000000, + .size = 32 * 1024 * 1024, +}; +#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB +static struct device_d cfi_dev1 = { + .name = "cfi_flash", + .map_base = 0xC2000000, + .size = 32 * 1024 * 1024, +}; +#endif + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB +#define SDRAM0 256 +#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB +#define SDRAM0 128 +#endif + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = 0xa0000000, + .size = SDRAM0 * 1024 * 1024, + .platform_data = &ram_pdata, +}; + +static struct fec_platform_data fec_info = { + .xcv_type = MII100, + .phy_addr = 1, +}; + +static struct device_d fec_dev = { + .name = "fec_imx", + .map_base = 0x1002b000, + .platform_data = &fec_info, +}; + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = 0xd8000000, + .platform_data = &nand_info, +}; + +#ifdef CONFIG_DRIVER_SERIAL_NS16550 +unsigned int quad_uart_read(unsigned long base, unsigned char reg_idx) +{ + unsigned int reg_addr = (unsigned int)base; + reg_addr += reg_idx << 1; + return 0xff & readw(reg_addr); +} +EXPORT_SYMBOL(quad_uart_read); + +void quad_uart_write(unsigned int val, unsigned long base, + unsigned char reg_idx) +{ + unsigned int reg_addr = (unsigned int)base; + reg_addr += reg_idx << 1; + writew(0xff & val, reg_addr); +} +EXPORT_SYMBOL(quad_uart_write); + +static struct NS16550_plat quad_uart_serial_plat = { + .clock = 14745600, + .f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR, + .reg_read = quad_uart_read, + .reg_write = quad_uart_write, +}; + +#ifdef CONFIG_EUKREA_CPUIMX27_QUART1 +#define QUART_OFFSET 0x200000 +#elif defined CONFIG_EUKREA_CPUIMX27_QUART2 +#define QUART_OFFSET 0x400000 +#elif defined CONFIG_EUKREA_CPUIMX27_QUART3 +#define QUART_OFFSET 0x800000 +#elif defined CONFIG_EUKREA_CPUIMX27_QUART4 +#define QUART_OFFSET 0x1000000 +#endif + +static struct device_d quad_uart_serial_device = { + .name = "serial_ns16550", + .map_base = IMX_CS3_BASE + QUART_OFFSET, + .size = 0xF, + .platform_data = (void *)&quad_uart_serial_plat, +}; +#endif + +static struct i2c_board_info i2c_devices[] = { + { + I2C_BOARD_INFO("lp3972", 0x34), + }, +}; + +static struct device_d i2c_dev = { + .name = "i2c-imx", + .map_base = IMX_I2C1_BASE, +}; + +#ifdef CONFIG_MMU +static void eukrea_cpuimx27_mmu_init(void) +{ + mmu_init(); + + arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED); + arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED); + + setup_dma_coherent(0x10000000); + +#if TEXT_BASE & (0x100000 - 1) +#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary +#else + arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED); +#endif + mmu_enable(); +} +#else +static void eukrea_cpuimx27_mmu_init(void) +{ +} +#endif + +#ifdef CONFIG_DRIVER_VIDEO_IMX +static struct imx_fb_videomode imxfb_mode = { + .mode = { + .name = "CMO-QVGA", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = 156000, + .hsync_len = 30, + .left_margin = 38, + .right_margin = 20, + .vsync_len = 3, + .upper_margin = 15, + .lower_margin = 4, + }, + .pcr = 0xFAD08B80, + .bpp = 16,}; + +static struct imx_fb_platform_data eukrea_cpuimx27_fb_data = { + .mode = &imxfb_mode, + .pwmr = 0x00A903FF, + .lscr1 = 0x00120300, + .dmacr = 0x00020010, +}; + +static struct device_d imxfb_dev = { + .name = "imxfb", + .map_base = 0x10021000, + .size = 0x1000, + .platform_data = &eukrea_cpuimx27_fb_data, +}; +#endif + +static int eukrea_cpuimx27_devices_init(void) +{ + char *envdev = "no"; + int i; + + unsigned int mode[] = { + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC | GPIO_PUEN, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + PD17_PF_I2C_DATA, + PD18_PF_I2C_CLK, +#ifdef CONFIG_DRIVER_SERIAL_IMX + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, +#endif +#ifdef CONFIG_DRIVER_VIDEO_IMX + PA5_PF_LSCLK, + PA6_PF_LD0, + PA7_PF_LD1, + PA8_PF_LD2, + PA9_PF_LD3, + PA10_PF_LD4, + PA11_PF_LD5, + PA12_PF_LD6, + PA13_PF_LD7, + PA14_PF_LD8, + PA15_PF_LD9, + PA16_PF_LD10, + PA17_PF_LD11, + PA18_PF_LD12, + PA19_PF_LD13, + PA20_PF_LD14, + PA21_PF_LD15, + PA22_PF_LD16, + PA23_PF_LD17, + PA28_PF_HSYNC, + PA29_PF_VSYNC, + PA31_PF_OE_ACD, + GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT, +#endif + }; + + eukrea_cpuimx27_mmu_init(); + + /* configure 16 bit nor flash on cs0 */ + CS0U = 0x00008F03; + CS0L = 0xA0330D01; + CS0A = 0x002208C0; + + /* initialize gpios */ + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + + register_device(&cfi_dev); +#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB + register_device(&cfi_dev1); +#endif + register_device(&nand_dev); + register_device(&sdram_dev); + + PCCR0 |= PCCR0_I2C1_EN; + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); + register_device(&i2c_dev); + + devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); + protect_file("/dev/env0", 1); + envdev = "NOR"; + + printf("Using environment in %s Flash\n", envdev); + +#ifdef CONFIG_DRIVER_VIDEO_IMX + register_device(&imxfb_dev); + gpio_direction_output(GPIO_PORTE | 5, 0); + gpio_set_value(GPIO_PORTE | 5, 1); +#endif + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0xa0000100); + armlinux_set_architecture(MACH_TYPE_CPUIMX27); + + return 0; +} + +device_initcall(eukrea_cpuimx27_devices_init); + +#ifdef CONFIG_DRIVER_SERIAL_IMX +static struct device_d eukrea_cpuimx27_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 4096, +}; +#endif + +static int eukrea_cpuimx27_console_init(void) +{ +#ifdef CONFIG_DRIVER_SERIAL_IMX + register_device(&eukrea_cpuimx27_serial_device); +#endif + /* configure 8 bit UART on cs3 */ + FMCR &= ~0x2; + CS3U = 0x0000D603; + CS3L = 0x0D1D0D01; + CS3A = 0x00D20000; +#ifdef CONFIG_DRIVER_SERIAL_NS16550 + register_device(&quad_uart_serial_device); +#endif + return 0; +} + +console_initcall(eukrea_cpuimx27_console_init); + +static int eukrea_cpuimx27_late_init(void) +{ +#ifdef CONFIG_DRIVER_I2C_LP3972 + struct i2c_client *client; + u8 reg[1]; +#endif + console_flush(); + register_device(&fec_dev); + +#ifdef CONFIG_DRIVER_I2C_LP3972 + client = lp3972_get_client(); + if (!client) + return -ENODEV; + reg[0] = 0xa0; + i2c_write_reg(client, 0x39, reg, sizeof(reg)); +#endif + return 0; +} + +late_initcall(eukrea_cpuimx27_late_init); + +#ifdef CONFIG_NAND_IMX_BOOT +void __bare_init nand_boot(void) +{ + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); +} +#endif + diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.dox b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.dox new file mode 100644 index 0000000000..6c2bfede22 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.dox @@ -0,0 +1,11 @@ +/** @page eukrea_cpuimx27 Eukrea's CPUIMX27 + +This CPU card is based on a Freescale i.MX27 CPU. The card is shipped with: + +- up to 64MiB NOR type Flash Memory +- up to 256MiB synchronous dynamic RAM +- up to 512MiB NAND type Flash Memory +- MII 10/100 ethernet PHY +- optional 16554 Quad UART on CS3 + +*/ diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S new file mode 100644 index 0000000000..5295a8a227 --- /dev/null +++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S @@ -0,0 +1,141 @@ +#include <config.h> +#include <mach/imx-regs.h> + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + +#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB +#define ROWS0 ESDCTL_ROW14 +#define CFG0 0x0029572D +#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB +#define ROWS0 ESDCTL_ROW13 +#define CFG0 0x00095728 +#endif + +#define ESDCTL0_VAL (ESDCTL0_SDE | ROWS0 | ESDCTL0_COL10) + +.macro sdram_init + /* + * DDR on CSD0 + */ + writel(0x0000000C, ESDMISC) /* Enable DDR SDRAM operation */ + + writel(0x55555555, DSCR(3)) /* Set the driving strength */ + writel(0x55555555, DSCR(5)) + writel(0x55555555, DSCR(6)) + writel(0x00005005, DSCR(7)) + writel(0x15555555, DSCR(8)) + + writel(0x00000004, ESDMISC) /* Initial reset */ + writel(CFG0, ESDCFG0) + + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */ + writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0) + + ldr r0, =0xa0000f00 + mov r1, #0 + mov r2, #8 +1: + str r1, [r0] + subs r2, #1 + bne 1b + + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0) + ldr r0, =0xA0000033 + mov r1, #0xda + strb r1, [r0] +#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB + ldr r0, =0xA2000000 +#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB + ldr r0, =0xA1000000 +#endif + mov r1, #0xff + strb r1, [r0] + writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0) +.endm + + .section ".text_bare_init","ax" + +.globl board_init_lowlevel +board_init_lowlevel: + + mov r10, lr + + /* ahb lite ip interface */ + writel(0x20040304, AIPI1_PSR0) + writel(0xDFFBFCFB, AIPI1_PSR1) + writel(0x00000000, AIPI2_PSR0) + writel(0xFFFFFFFF, AIPI2_PSR1) + + /* disable mpll/spll */ + ldr r0, =CSCR + ldr r1, [r0] + bic r1, r1, #0x03 + str r1, [r0] + + /* + * pll clock initialization - see section 3.4.3 of the i.MX27 manual + */ + writel(0x00331C23, MPCTL0) /* MPLL = 399 MHz */ + writel(0x040C2403, SPCTL0) /* SPLL = 240 MHz */ + writel(0x33F38107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) + + /* add some delay here */ + mov r1, #0x1000 +1: subs r1, r1, #0x1 + bne 1b + + /* clock gating enable */ + writel(0x00050f08, GPCR) + + /* peripheral clock divider */ + writel(0x130400c3, PCDR0) /* FIXME */ + writel(0x09030208, PCDR1) /* PERDIV1=08 @133 MHz */ + /* PERDIV1=04 @266 MHz */ + + /* skip sdram initialization if we run from ram */ + cmp pc, #0xa0000000 + bls 1f + cmp pc, #0xc0000000 + bhi 1f + + mov pc,r10 +1: + sdram_init + +#ifdef CONFIG_NAND_IMX_BOOT + ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */ + + ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ + ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */ + + /* skip NAND boot if not running from NFC space */ + cmp pc, r0 + bls ret + cmp pc, r2 + bhi ret + + /* Move ourselves out of NFC SRAM */ + ldr r1, =TEXT_BASE + +copy_loop: + ldmia r0!, {r3-r9} /* copy from source address [r0] */ + stmia r1!, {r3-r9} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + ldr pc, =1f /* Jump to SDRAM */ +1: + bl nand_boot /* Load barebox from NAND Flash */ + + ldr r1, =IMX_NFC_BASE - TEXT_BASE + sub r10, r10, r1 /* adjust return address from NFC SRAM */ + /* to SDRAM */ + +#endif /* CONFIG_NAND_IMX_BOOT */ + +ret: + mov pc,r10 |