diff options
Diffstat (limited to 'arch/arm/boards/freescale-mx25-3-stack')
11 files changed, 836 insertions, 0 deletions
diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c new file mode 100644 index 0000000000..a77a02d498 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c @@ -0,0 +1,354 @@ +/* + * (C) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <init.h> +#include <driver.h> +#include <environment.h> +#include <mach/imx-regs.h> +#include <asm/armlinux.h> +#include <mach/gpio.h> +#include <asm/io.h> +#include <partition.h> +#include <asm/mach-types.h> +#include <mach/imx-nand.h> +#include <fec.h> +#include <nand.h> +#include <mach/imx-flash-header.h> +#include <mach/iomux-mx25.h> +#include <linux/err.h> +#include <i2c/i2c.h> +#include <i2c/mc34704.h> + +extern unsigned long _stext; + +void __naked __flash_header_start go(void) +{ + __asm__ __volatile__("b exception_vectors\n"); +} + +struct imx_dcd_entry __dcd_entry_0x400 dcd_entry[] = { + { .ptr_type = 4, .addr = 0xb8002050, .val = 0x0000d843, }, + { .ptr_type = 4, .addr = 0xb8002054, .val = 0x22252521, }, + { .ptr_type = 4, .addr = 0xb8002058, .val = 0x22220a00, }, +#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2 + { .ptr_type = 4, .addr = 0xb8001004, .val = 0x0076e83a, }, + { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000304, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, + { .ptr_type = 4, .addr = 0x80000f00, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, + { .ptr_type = 1, .addr = 0x82000000, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x83000000, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x81000400, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x80000333, .val = 0xda, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, + { .ptr_type = 4, .addr = 0x80000400, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2210000, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, + { .ptr_type = 1, .addr = 0x80000233, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x81000780, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x81000400, .val = 0xda, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, }, +#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR + { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92100000, }, + { .ptr_type = 1, .addr = 0x80000400, .val = 0x21, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2100000, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2100000, }, + { .ptr_type = 1, .addr = 0x80000033, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x81000000, .val = 0xff, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216880, }, + { .ptr_type = 4, .addr = 0xb8001004, .val = 0x00295729, }, +#else +#error "Unsupported SDRAM type" +#endif + { .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, }, +}; + +#define APP_DEST 0x80000000 + +struct imx_flash_header __flash_header_0x400 mx25_3ds_header = { + .app_code_jump_vector = APP_DEST + 0x1000, + .app_code_barker = APP_CODE_BARKER, + .app_code_csf = 0, + .dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd), + .super_root_key = 0, + .dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker), + .app_dest = APP_DEST, + .dcd_barker = DCD_BARKER, + .dcd_block_len = sizeof (dcd_entry), +}; + +extern unsigned long __bss_start; + +unsigned long __image_len_0x400 barebox_len = 0x40000; + +static struct fec_platform_data fec_info = { + .xcv_type = RMII, + .phy_addr = 1, +}; + +static struct device_d fec_dev = { + .name = "fec_imx", + .map_base = IMX_FEC_BASE, + .platform_data = &fec_info, +}; + +static struct memory_platform_data sdram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram0_dev = { + .name = "mem", + .map_base = IMX_SDRAM_CS0, +#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2 + .size = 64 * 1024 * 1024, +#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR + .size = 128 * 1024 * 1024, +#else +#error "Unsupported SDRAM type" +#endif + .platform_data = &sdram_pdata, +}; + +static struct memory_platform_data sram_pdata = { + .name = "sram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sram0_dev = { + .name = "mem", + .map_base = 0x78000000, + .size = 128 * 1024, + .platform_data = &sram_pdata, +}; + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, +}; + +static struct device_d nand_dev = { + .name = "imx_nand", + .map_base = IMX_NFC_BASE, + .platform_data = &nand_info, +}; + +#ifdef CONFIG_USB +static void imx25_usb_init(void) +{ + unsigned int tmp; + + /* Host 2 */ + tmp = readl(IMX_OTG_BASE + 0x600); + tmp &= ~(3 << 21); + tmp |= (2 << 21) | (1 << 4) | (1 << 5); + writel(tmp, IMX_OTG_BASE + 0x600); + + tmp = readl(IMX_OTG_BASE + 0x584); + tmp |= 3 << 30; + writel(tmp, IMX_OTG_BASE + 0x584); + + /* Set to Host mode */ + tmp = readl(IMX_OTG_BASE + 0x5a8); + writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8); +} + +static struct device_d usbh2_dev = { + .name = "ehci", + .map_base = IMX_OTG_BASE + 0x400, + .size = 0x200, +}; +#endif + +static struct i2c_board_info i2c_devices[] = { + { + I2C_BOARD_INFO("mc34704", 0x54), + }, +}; + +static struct device_d i2c_dev = { + .name = "i2c-imx", + .map_base = IMX_I2C1_BASE, +}; + +static int imx25_3ds_pmic_init(void) +{ + struct mc34704 *pmic; + + pmic = mc34704_get(); + if (pmic == NULL) + return -EIO; + + return mc34704_reg_write(pmic, 0x2, 0x9); +} + +static int imx25_3ds_fec_init(void) +{ + int ret; + + ret = imx25_3ds_pmic_init(); + if (ret < 0) + return ret; + + /* + * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. + * Assert FEC_RESET_B, then power up the PHY by asserting + * FEC_ENABLE, at the same time lifting FEC_RESET_B. + * + * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17 + * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12 + */ + writel(0x8, IMX_IOMUXC_BASE + 0x0238); /* open drain */ + writel(0x0, IMX_IOMUXC_BASE + 0x028C); /* cmos, no pu/pd */ + +#define FEC_ENABLE_GPIO 35 +#define FEC_RESET_B_GPIO 104 + + /* make the pins output */ + gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */ + gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */ + udelay(2); + + /* turn on power & lift reset */ + gpio_set_value(FEC_ENABLE_GPIO, 1); + gpio_set_value(FEC_RESET_B_GPIO, 1); + + return 0; +} +late_initcall(imx25_3ds_fec_init); + +static int imx25_devices_init(void) +{ +#ifdef CONFIG_USB + /* USB does not work yet. Don't know why. Maybe + * the CPLD has to be initialized. + */ + imx25_usb_init(); + register_device(&usbh2_dev); +#endif + + register_device(&fec_dev); + + if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14)) + nand_info.width = 2; + + register_device(&nand_dev); + + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + + devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + register_device(&sdram0_dev); + register_device(&sram0_dev); + + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); + register_device(&i2c_dev); + + armlinux_add_dram(&sdram0_dev); + armlinux_set_bootparams((void *)0x80000100); + armlinux_set_architecture(MACH_TYPE_MX25_3DS); + + return 0; +} + +device_initcall(imx25_devices_init); + +static struct device_d imx25_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 16 * 1024, +}; + +static struct pad_desc imx25_pads[] = { + MX25_PAD_FEC_MDC__MDC, + MX25_PAD_FEC_MDIO__MDIO, + MX25_PAD_FEC_RDATA0__RDATA0, + MX25_PAD_FEC_RDATA1__RDATA1, + MX25_PAD_FEC_RX_DV__RX_DV, + MX25_PAD_FEC_TDATA0__TDATA0, + MX25_PAD_FEC_TDATA1__TDATA1, + MX25_PAD_FEC_TX_CLK__TX_CLK, + MX25_PAD_FEC_TX_EN__TX_EN, + MX25_PAD_POWER_FAIL__POWER_FAIL_INT, + MX25_PAD_A17__GPIO3, + MX25_PAD_D12__GPIO8, + /* UART1 */ + MX25_PAD_UART1_RXD__RXD_MUX, + MX25_PAD_UART1_TXD__TXD_MUX, + MX25_PAD_UART1_RTS__RTS, + MX25_PAD_UART1_CTS__CTS, + /* USBH2 */ + MX25_PAD_D9__USBH2_PWR, + MX25_PAD_D8__USBH2_OC, + MX25_PAD_LD0__USBH2_CLK, + MX25_PAD_LD1__USBH2_DIR, + MX25_PAD_LD2__USBH2_STP, + MX25_PAD_LD3__USBH2_NXT, + MX25_PAD_LD4__USBH2_DATA0, + MX25_PAD_LD5__USBH2_DATA1, + MX25_PAD_LD6__USBH2_DATA2, + MX25_PAD_LD7__USBH2_DATA3, + MX25_PAD_HSYNC__USBH2_DATA4, + MX25_PAD_VSYNC__USBH2_DATA5, + MX25_PAD_LSCLK__USBH2_DATA6, + MX25_PAD_OE_ACD__USBH2_DATA7, + /* i2c */ + MX25_PAD_I2C1_CLK__SCL, + MX25_PAD_I2C1_DAT__SDA, +}; + +static int imx25_console_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(imx25_pads, ARRAY_SIZE(imx25_pads)); + + writel(0x03010101, 0x53f80024); + + register_device(&imx25_serial_device); + return 0; +} + +console_initcall(imx25_console_init); + +#ifdef CONFIG_NAND_IMX_BOOT +void __bare_init nand_boot(void) +{ + imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); +} +#endif + +static int imx25_core_setup(void) +{ + writel(0x01010103, IMX_CCM_BASE + CCM_PCDR2); + return 0; + +} +core_initcall(imx25_core_setup); + diff --git a/arch/arm/boards/freescale-mx25-3-stack/Makefile b/arch/arm/boards/freescale-mx25-3-stack/Makefile new file mode 100644 index 0000000000..ab853e0d6b --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/Makefile @@ -0,0 +1,24 @@ +# +# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +obj-y += lowlevel_init.o +obj-y += 3stack.o diff --git a/arch/arm/boards/freescale-mx25-3-stack/config.h b/arch/arm/boards/freescale-mx25-3-stack/config.h new file mode 100644 index 0000000000..f35e8a0557 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/config.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Definitions related to passing arguments to kernel. + */ + +#define CONFIG_MX25_HCLK_FREQ 24000000 + +#endif + +/* nothing to do here yet */ diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/_update b/arch/arm/boards/freescale-mx25-3-stack/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/boot b/arch/arm/boards/freescale-mx25-3-stack/env/bin/boot new file mode 100644 index 0000000000..7bbff2d1f6 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/env/bin/boot @@ -0,0 +1,47 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xnand ]; then + root=nand + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$1 = xnor ]; then + root=nor + kernel=nor +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xnand ]; then + bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" +elif [ x$root = xnor ]; then + bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +elif [ $kernel = nor ]; then + bootm /dev/nor0.kernel +else + bootm /dev/nand0.kernel.bb +fi + diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/hush_hack b/arch/arm/boards/freescale-mx25-3-stack/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/init b/arch/arm/boards/freescale-mx25-3-stack/env/bin/init new file mode 100644 index 0000000000..0600b9e661 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/env/bin/init @@ -0,0 +1,30 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +if [ -e /dev/nor0 ]; then + addpart /dev/nor0 $nor_parts +fi + +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel nand|nor [<imagename>] to update kernel into flash" + echo "type update_root nand|nor [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_kernel b/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_kernel new file mode 100644 index 0000000000..05c822d860 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_kernel @@ -0,0 +1,15 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.kernel.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.kernel +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_root b/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_root new file mode 100644 index 0000000000..eaf36ebcea --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_root @@ -0,0 +1,16 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.root.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.root +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 + diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/config b/arch/arm/boards/freescale-mx25-3-stack/env/config new file mode 100644 index 0000000000..a5e492e339 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/env/config @@ -0,0 +1,29 @@ +#!/bin/sh + +# can be either 'net', 'nor' or 'nand'' +kernel=net +root=net + +uimage=uImage-pcm043 +jffs2=root-pcm043.jffs2 + +autoboot_timeout=3 + +nfsroot="/ptx/work/octopus/rsc/svn/oselas/bsp/phytec/phyCORE-i.MX27/OSELAS.BSP-Phytec-phyCORE-i.MX27-trunk/root" +bootargs="console=ttymxc0,115200" + +nor_parts="256k(barebox)ro,128k(bareboxenv),2048k(kernel),-(root)" +rootpart_nor="/dev/mtdblock3" + +nand_parts="256k(barebox)ro,128k(bareboxenv),2048k(kernel),108416k(root),-(kernel1)" +rootpart_nand="/dev/mtdblock7" + +# use 'dhcp' to do dhcp in barebox and in kernel +#ip=dhcp + +# or set your networking parameters here +eth0.ipaddr=192.168.3.11 +eth0.netmask=255.255.255.0 +#eth0.gateway=a.b.c.d +eth0.serverip=192.168.3.10 +eth0.ethaddr=00:50:c2:8c:e6:0e diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S new file mode 100644 index 0000000000..73bb14723e --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S @@ -0,0 +1,253 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <mach/imx-regs.h> +#include <mach/imx-pll.h> +#include <mach/esdctl.h> + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + +#define writeb(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + strb r1, [r0]; + +/* Assuming 24MHz input clock */ +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 (IMX_PLL_PD(1) | IMX_PLL_MFD(0) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) +#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) + +.section ".text_bare_init","ax" + +ARM_PPMRR: .word 0x40000015 +L2CACHE_PARAM: .word 0x00030024 +CCM_CCMR_W: .word 0x003F4208 +CCM_PDR0_W: .word 0x00801000 +MPCTL_PARAM_399_W: .word MPCTL_PARAM_399 +MPCTL_PARAM_532_W: .word MPCTL_PARAM_532 +PPCTL_PARAM_W: .word PPCTL_PARAM_300 +CCM_BASE_ADDR_W: .word IMX_CCM_BASE + +.globl board_init_lowlevel +board_init_lowlevel: + mov r10, lr + +#define MX25_CCM_MCR 0x64 + + ldr r0, CCM_BASE_ADDR_W + /* default CLKO to 1/32 of the ARM core */ + ldr r1, [r0, #MX25_CCM_MCR] + bic r1, r1, #0x00F00000 + bic r1, r1, #0x7F000000 + mov r2, #0x5F000000 + add r2, r2, #0x00200000 + orr r1, r1, r2 + str r1, [r0, #MX25_CCM_MCR] + + /* enable all the clocks */ + writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0) + writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1) + writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2) + writel(0x0000FEFF, IMX_CCM_BASE + MX25_CCM_MCR) + + /* Skip SDRAM initialization if we run from RAM */ + cmp pc, #0x80000000 + bls 1f + cmp pc, #0x90000000 + bhi 1f + + mov pc, lr + +1: + ldr r0, ESDCTL_BASE_W + mov r3, #0x2000 + str r3, [r0, #0x0] + str r3, [r0, #0x8] + + mov r12, #0x00 + mov r2, #0x1 /* mDDR */ + mov r1, #IMX_SDRAM_CS0 + bl setup_sdram_bank +// cmp r3, #0x0 +// orreq r12, r12, #1 +// eorne r2, r2, #0x1 +// blne setup_sdram_bank + + ldr r3, ESDCTL_DELAY5 + str r3, [r0, #0x30] + +#ifdef CONFIG_NAND_IMX_BOOT + ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */ + + ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */ + ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */ + + /* skip NAND boot if not running from NFC space */ + cmp pc, r0 + bls ret + cmp pc, r2 + bhi ret + + /* Move ourselves out of NFC SRAM */ + ldr r1, =TEXT_BASE + +copy_loop: + ldmia r0!, {r3-r9} /* copy from source address [r0] */ + stmia r1!, {r3-r9} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + ldr pc, =1f /* Jump to SDRAM */ +1: + bl nand_boot /* Load barebox from NAND Flash */ + + ldr r1, =IMX_NFC_BASE - TEXT_BASE + sub r10, r10, r1 /* adjust return address from NFC SRAM */ + /* to SDRAM */ + +#endif /* CONFIG_NAND_IMX_BOOT */ + +ret: + mov pc, r10 + +/* + * r0: control base, r1: ram bank base + * r2: ddr type(0:DDR2, 1:MDDR) r3, r4: working + */ +setup_sdram_bank: + mov r3, #0xE /* 0xA + 0x4 */ + tst r2, #0x1 + orreq r3, r3, #0x300 /* DDR2 */ + str r3, [r0, #0x10] + bic r3, r3, #0x00A + str r3, [r0, #0x10] + beq 2f + + mov r3, #0x20000 +1: subs r3, r3, #1 + bne 1b + +2: adr r4, ESDCTL_CONFIG + tst r2, #0x1 + ldreq r3, [r4, #0x0] + ldrne r3, [r4, #0x4] + cmp r1, #IMX_SDRAM_CS1 + strlo r3, [r0, #0x4] + strhs r3, [r0, #0xC] + + ldr r3, ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, RAM_PARAM1_MDDR + strb r3, [r1, r4] + + tst r2, #0x1 + bne skip_set_mode + + cmp r1, #IMX_SDRAM_CS1 + ldr r3, ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, RAM_PARAM4_MDDR + strb r3, [r1, r4] + ldr r4, RAM_PARAM5_MDDR + strb r3, [r1, r4] + ldr r4, RAM_PARAM3_MDDR + strb r3, [r1, r4] + ldr r4, RAM_PARAM2_MDDR + strb r3, [r1, r4] + + ldr r3, ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, RAM_PARAM1_MDDR + strb r3, [r1, r4] + +skip_set_mode: + cmp r1, #IMX_SDRAM_CS1 + ldr r3, ESDCTL_0xA2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + strb r3, [r1] + strb r3, [r1] + + ldr r3, ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + adr r4, RAM_PARAM6_MDDR + tst r2, #0x1 + ldreq r4, [r4, #0x0] + ldrne r4, [r4, #0x4] + mov r3, #0xDA + strb r3, [r1, r4] + ldreq r4, RAM_PARAM7_MDDR + streqb r3, [r1, r4] + adr r4, RAM_PARAM3_MDDR + ldreq r4, [r4, #0x0] + ldrne r4, [r4, #0x4] + strb r3, [r1, r4] + + cmp r1, #IMX_SDRAM_CS1 + ldr r3, ESDCTL_0x82226080 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + + tst r2, #0x1 + moveq r4, #0x20000 + movne r4, #0x200 +1: subs r4, r4, #1 + bne 1b + + str r3, [r1, #0x100] + ldr r4, [r1, #0x100] + cmp r3, r4 + movne r3, #1 + moveq r3, #0 + + mov pc, lr + +RAM_PARAM1_MDDR: .word 0x00000400 +RAM_PARAM2_MDDR: .word 0x00000333 +RAM_PARAM3_MDDR: .word 0x02000400 + .word 0x02000000 +RAM_PARAM4_MDDR: .word 0x04000000 +RAM_PARAM5_MDDR: .word 0x06000000 +RAM_PARAM6_MDDR: .word 0x00000233 + .word 0x00000033 +RAM_PARAM7_MDDR: .word 0x02000780 +ESDCTL_0x92220000: .word 0x92210000 +ESDCTL_0xA2220000: .word 0xA2210000 +ESDCTL_0xB2220000: .word 0xB2210000 +ESDCTL_0x82226080: .word 0x82216080 +ESDCTL_CONFIG: .word 0x007FFC3F + .word 0x007FFC3F +ESDCTL_DELAY5: .word 0x00F49F00 +ESDCTL_BASE_W: .word IMX_ESD_BASE + |