diff options
Diffstat (limited to 'arch/arm/boards/imx27ads')
| -rw-r--r-- | arch/arm/boards/imx27ads/Makefile | 3 | ||||
| -rw-r--r-- | arch/arm/boards/imx27ads/config.h | 26 | ||||
| -rw-r--r-- | arch/arm/boards/imx27ads/env/bin/_update | 36 | ||||
| -rw-r--r-- | arch/arm/boards/imx27ads/env/bin/boot | 38 | ||||
| -rw-r--r-- | arch/arm/boards/imx27ads/env/bin/init | 20 | ||||
| -rw-r--r-- | arch/arm/boards/imx27ads/env/bin/update_kernel | 8 | ||||
| -rw-r--r-- | arch/arm/boards/imx27ads/env/bin/update_root | 8 | ||||
| -rw-r--r-- | arch/arm/boards/imx27ads/env/config | 25 | ||||
| -rw-r--r-- | arch/arm/boards/imx27ads/imx27ads.c | 162 | ||||
| -rw-r--r-- | arch/arm/boards/imx27ads/imx27ads.dox | 5 | ||||
| -rw-r--r-- | arch/arm/boards/imx27ads/lowlevel_init.S | 172 |
11 files changed, 503 insertions, 0 deletions
diff --git a/arch/arm/boards/imx27ads/Makefile b/arch/arm/boards/imx27ads/Makefile new file mode 100644 index 0000000000..bdc905f0ef --- /dev/null +++ b/arch/arm/boards/imx27ads/Makefile @@ -0,0 +1,3 @@ + +obj-y += lowlevel_init.o +obj-y += imx27ads.o diff --git a/arch/arm/boards/imx27ads/config.h b/arch/arm/boards/imx27ads/config.h new file mode 100644 index 0000000000..b54a3c53d4 --- /dev/null +++ b/arch/arm/boards/imx27ads/config.h @@ -0,0 +1,26 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * @file + * @brief Global defintions for the Freescale imx27ads ARM board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/imx27ads/env/bin/_update b/arch/arm/boards/imx27ads/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/arm/boards/imx27ads/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/imx27ads/env/bin/boot b/arch/arm/boards/imx27ads/env/bin/boot new file mode 100644 index 0000000000..3859dc113b --- /dev/null +++ b/arch/arm/boards/imx27ads/env/bin/boot @@ -0,0 +1,38 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xflash ]; then + root=flash + kernel=flash +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xflash ]; then + bootargs="$bootargs root=$rootpart rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +else + bootm /dev/nor0.kernel +fi + diff --git a/arch/arm/boards/imx27ads/env/bin/init b/arch/arm/boards/imx27ads/env/bin/init new file mode 100644 index 0000000000..48e2139f7d --- /dev/null +++ b/arch/arm/boards/imx27ads/env/bin/init @@ -0,0 +1,20 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +addpart /dev/nor0 $mtdparts + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel [<imagename>] to update kernel into flash" + echo "type udate_root [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot
\ No newline at end of file diff --git a/arch/arm/boards/imx27ads/env/bin/update_kernel b/arch/arm/boards/imx27ads/env/bin/update_kernel new file mode 100644 index 0000000000..1ad95fc5d6 --- /dev/null +++ b/arch/arm/boards/imx27ads/env/bin/update_kernel @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$uimage +part=/dev/nor0.kernel + +. /env/bin/_update $1 diff --git a/arch/arm/boards/imx27ads/env/bin/update_root b/arch/arm/boards/imx27ads/env/bin/update_root new file mode 100644 index 0000000000..b757a5b922 --- /dev/null +++ b/arch/arm/boards/imx27ads/env/bin/update_root @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$jffs2 +part=/dev/nor0.root + +. /env/bin/_update $1 diff --git a/arch/arm/boards/imx27ads/env/config b/arch/arm/boards/imx27ads/env/config new file mode 100644 index 0000000000..f18a86b7c1 --- /dev/null +++ b/arch/arm/boards/imx27ads/env/config @@ -0,0 +1,25 @@ +#!/bin/sh + +# can be either 'net' or 'flash' +kernel=net +root=net + +# use 'dhcp' todo dhcp in barebox and in kernel +ip=dhcp + +eth0.ipaddr=192.168.23.164 +eth0.netmask=255.255.255.0 +eth0.gateway=192.168.23.2 +eth0.serverip=192.168.23.2 + +uimage=uImage-mx27ads +jffs2=root-mx27ads.jffs2 + +autoboot_timeout=3 + +nfsroot="/tmp/imx27ads" +bootargs="console=ttymxc0,115200" + +mtdparts="128k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)" +rootpart="/dev/mtdblock3" + diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c new file mode 100644 index 0000000000..6f31520ffa --- /dev/null +++ b/arch/arm/boards/imx27ads/imx27ads.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <mach/imx-regs.h> +#include <asm/armlinux.h> +#include <asm/io.h> +#include <fec.h> +#include <mach/gpio.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <asm/mach-types.h> +#include <mach/iomux-mx27.h> + +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = 0xC0000000, + .size = 32 * 1024 * 1024, +}; + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .name = "mem", + .map_base = 0xa0000000, + .size = 128 * 1024 * 1024, + .platform_data = &ram_pdata, +}; + +static struct fec_platform_data fec_info = { + .xcv_type = MII100, + .phy_addr = 1, +}; + +static struct device_d fec_dev = { + .name = "fec_imx", + .map_base = 0x1002b000, + .platform_data = &fec_info, +}; + +static int imx27ads_timing_init(void) +{ + /* configure cpld on cs4 */ + CS4U = 0x0000DCF6; + CS4L = 0x444A4541; + CS4A = 0x44443302; + + /* configure synchronous mode for + * 16 bit nor flash on cs0 */ + CS0U = 0x0000CC03; + CS0L = 0xa0330D01; + CS0A = 0x00220800; + + writew(0x00f0, 0xc0000000); + writew(0x00aa, 0xc0000aaa); + writew(0x0055, 0xc0000554); + writew(0x00d0, 0xc0000aaa); + writew(0x66ca, 0xc0000aaa); + writew(0x00f0, 0xc0000000); + + CS0U = 0x23524E80; + CS0L = 0x10000D03; + CS0A = 0x00720900; + + /* Select FEC data through data path */ + writew(0x0020, IMX_CS4_BASE + 0x10); + + /* Enable CPLD FEC data path */ + writew(0x0010, IMX_CS4_BASE + 0x14); + + return 0; +} + +core_initcall(imx27ads_timing_init); + +static int mx27ads_devices_init(void) +{ + int i; + unsigned int mode[] = { + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC | GPIO_PUEN, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + }; + + /* initizalize gpios */ + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + + register_device(&cfi_dev); + register_device(&sdram_dev); + register_device(&fec_dev); + + devfs_add_partition("nor0", 0x00000, 0x20000, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x20000, 0x20000, PARTITION_FIXED, "env0"); + protect_file("/dev/env0", 1); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0xa0000100); + armlinux_set_architecture(MACH_TYPE_MX27ADS); + + return 0; +} + +device_initcall(mx27ads_devices_init); + +static struct device_d mx27ads_serial_device = { + .name = "imx_serial", + .map_base = IMX_UART1_BASE, + .size = 4096, +}; + +static int mx27ads_console_init(void) +{ + register_device(&mx27ads_serial_device); + return 0; +} + +console_initcall(mx27ads_console_init); + diff --git a/arch/arm/boards/imx27ads/imx27ads.dox b/arch/arm/boards/imx27ads/imx27ads.dox new file mode 100644 index 0000000000..e14d8e3fab --- /dev/null +++ b/arch/arm/boards/imx27ads/imx27ads.dox @@ -0,0 +1,5 @@ +/** @page imx27ads Freescale i.MX27ads + +This is the Freescale evaluation board for the i.MX27 Processor + +*/ diff --git a/arch/arm/boards/imx27ads/lowlevel_init.S b/arch/arm/boards/imx27ads/lowlevel_init.S new file mode 100644 index 0000000000..df12aead00 --- /dev/null +++ b/arch/arm/boards/imx27ads/lowlevel_init.S @@ -0,0 +1,172 @@ +/* + * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia + * Applications Processor Reference Manual, Rev. 0.2". + * + */ + +#include <config.h> +#include <mach/imx-regs.h> + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + +#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0)) + +.macro sdram_init_sha + /* + * DDR on CSD0 + */ + writel(0x00000008, 0xD8001010) + writel(0x55555555, 0x10027828) + writel(0x55555555, 0x10027830) + writel(0x55555555, 0x10027834) + writel(0x00005005, 0x10027838) + writel(0x15555555, 0x1002783C) + writel(0x00000004, 0xD8001010) + writel(0x006ac73a, 0xD8001004) + writel(0x92100000, 0xD8001000) + writel(0x00000000, 0xA0000F00) + writel(0xA2100000, 0xD8001000) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0xA2200000, 0xD8001000) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0xb2100000, 0xD8001000) + ldr r0, =0xA0000033 + mov r1, #0xda + strb r1, [r0] + ldr r0, =0xA1000000 + mov r1, #0xff + strb r1, [r0] + writel(0x82226080, 0xD8001000) +.endm + +.macro sdram_init_mx27_manual + /* + * sdram init sequence, as defined in 18.5.4 of the i.MX27 reference manual + */ +1: + ldr r2, =ESD_ESDCTL0 /* base address of registers */ + ldr r3, =PRE_ALL_CMD /* SMODE=001 */ + str r3,(r2,#0x0) /* put CSD0 in precharge command mode */ + ldr r4, =SDRAM_CSD0 /* CSD0 precharge address (A10=1) */ + str r1,(r4,#0x0) /* precharge CSD0 all banks */ + ldr r3, =AUTO_REF_CMD /* SMODE=010 */ + str r3,(r2,#0x0) /* put array 0 in auto-refresh mode */ + ldr r4, =SDRAM_CSD0_BASE /* CSD0 base address */ + ldr r6,=0x7 /* load loop counter */ +1: ldr r5,(r4,#0x0) /* run auto-refresh cycle to array 0 */ + subs r6,r6,#1 /* decrease counter value */ + bne 1b + ldr r3, =SET_MODE_REG_CMD /* SMODE=011 */ + str r3,(r2,#0x0) /* setup CSD0 for mode register write */ + ldr r3, =MODE_REG_VAL0 /* array 0 mode register value */ + ldrb r5,(r3,#0x0) /* New mode register value on address bus */ + ldr r3, =NORMAL_MODE /* SMODE=000 */ + str r3,(r2,#0x0) /* setup CSD0 for normal operation */ + +ESD_ESDCTL0 .long 0xD8001000 // system/external device dependent data +SDRAM_CSD0 .long 0x00000000 // system/external device dependent data +SDRAM_CSD0_BASE .long 0x00000000 // system/external device dependent data +PRE_ALL_CMD .long 0x00000000 // system/external device dependent data (SMODE=001) +AUTO_REF_CMD .long 0x00000000 // system/external device dependent data (SMODE=010) +SET_MODE_REG_CMD .long 0x00000000 // system/external device dependent data (SMODE=011) +MODE_REG_VAL0 .long 0x00000000 // system/external device dependent data +NORMAL_MODE .long 0x00000000 // system/external device dependent data (SMODE=000) +.endm + +.macro sdram_init_barebox + /* configure 16 bit nor flash on cs0 */ + writel(0x0000CC03, 0xd8002000) + writel(0xa0330D01, 0xd8002004) + writel(0x00220800, 0xd8002008) + + /* ddr on csd0 - initial reset */ + writel(0x00000008, 0xD8001010) + + /* configure ddr on csd0 - wait 5000 cycles */ + writel(0x00000004, 0xD8001010) + writel(0x006ac73a, 0xD8001004) + writel(0x92100000, 0xD8001000) + writel(0x12344321, 0xA0000f00) + writel(0xa2100000, 0xD8001000) + writel(0x12344321, 0xA0000000) + writel(0x12344321, 0xA0000000) + writel(0xb2100000, 0xD8001000) + ldr r0, =0xA0000033 + mov r1, #0xda + strb r1, [r0] + ldr r0, =0xA1000000 + mov r1, #0xff + strb r1, [r0] + writel(0x82226080, 0xD8001000) + writel(0xDEADBEEF, 0xA0000000) + writel(0x0000000c, 0xD8001010) +.endm + +.globl board_init_lowlevel +board_init_lowlevel: + + mov r10, lr + + /* ahb lite ip interface */ + writel(0x20040304, AIPI1_PSR0) + writel(0xDFFBFCFB, AIPI1_PSR1) + writel(0x00000000, AIPI2_PSR0) + writel(0xFFFFFFFF, AIPI2_PSR1) + + /* disable mpll/spll */ + ldr r0, =CSCR + ldr r1, [r0] + bic r1, r1, #0x03 + str r1, [r0] + + /* + * pll clock initialization - see section 3.4.3 of the i.MX27 manual + * + * FIXME: Using the 399*2 MHz values from table 3-8 doens't work + * with 1.2 V core voltage! Find out if this is + * documented somewhere. + */ + writel(0x00191403, MPCTL0) /* MPLL = 199.5*2 MHz */ + writel(0x040C2403, SPCTL0) /* SPLL = FIXME (needs review) */ + + /* + * ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz + * AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz + * System clock (HCLK) = 133 MHz + */ + writel(0x33F30307 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) + + /* add some delay here */ + mov r1, #0x1000 +1: subs r1, r1, #0x1 + bne 1b + + /* clock gating enable */ + writel(0x00050f08, GPCR) + + /* peripheral clock divider */ + writel(0x23C8F403, PCDR0) /* FIXME */ + writel(0x09030913, PCDR1) /* PERDIV1=08 @133 MHz */ + /* PERDIV1=04 @266 MHz * + * / + /* skip sdram initialization if we run from ram */ + cmp pc, #0xa0000000 + bls 1f + cmp pc, #0xc0000000 + bhi 1f + + mov pc,r10 +1: + sdram_init_sha + + mov pc,r10 + |