diff options
Diffstat (limited to 'arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg')
| -rw-r--r-- | arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg index 7e244edfd3..bd869ec29e 100644 --- a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg +++ b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg @@ -1,12 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + /* MDMISC mirroring interleaved (row/bank/col) */ wm 32 MX6_MMDC_P0_MDMISC 0x00000742 -check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002 +check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 -check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 wm 32 MX6_MMDC_P0_MDCTL 0x831a0000 -check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333 wm 32 MX6_MMDC_P0_MDCFG1 0x926e8a63 @@ -34,7 +36,7 @@ wm 32 MX6_MMDC_P0_MDSCR 0x04008010 wm 32 MX6_MMDC_P0_MDSCR 0x04008040 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390001 -check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1380000 wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001e001e @@ -62,11 +64,11 @@ wm 32 MX6_MMDC_P1_MPWRDLCTL 0x40404040 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000 -check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x80000000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000 wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000 -check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x80000000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000 wm 32 MX6_MMDC_P0_MPDGCTRL0 0x50800000 -check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x10001000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x10001000 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 @@ -81,16 +83,16 @@ wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f -check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x00008033 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b wm 32 MX6_MMDC_P0_MDREF 0x00001800 @@ -98,4 +100,4 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00001006 wm 32 MX6_MMDC_P0_MDPDC 0x0002556d wm 32 MX6_MMDC_P1_MDPDC 0x0002556d wm 32 MX6_MMDC_P0_MDSCR 0x00000000 -check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 |