diff options
Diffstat (limited to 'arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg')
| -rw-r--r-- | arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg index 889416b849..bbb9e01022 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg @@ -1,9 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx6 loadaddr 0x20000000 ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> wm 32 0x020e00a4 0x00000016 wm 32 0x020e00c4 0x00000011 @@ -128,11 +130,11 @@ wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 wm 32 MX6_MMDC_P0_MDMISC 0x00000742 -check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002 +check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 -check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 wm 32 MX6_MMDC_P0_MDCTL 0x841a0000 -check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 wm 32 MX6_MMDC_P0_MDCFG0 0x898f78f4 wm 32 MX6_MMDC_P0_MDCFG1 0xff328e64 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db @@ -155,7 +157,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001 wm 32 MX6_MMDC_P0_MDSCR 0x04008010 wm 32 MX6_MMDC_P0_MDSCR 0x04008040 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 -check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000 wm 32 MX6_MMDC_P0_MDSCR 0x00048033 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 @@ -169,18 +171,18 @@ wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f -check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x00008033 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b wm 32 MX6_MMDC_P0_MDREF 0x00001800 wm 32 MX6_MMDC_P0_MAPSR 0x00001000 wm 32 MX6_MMDC_P0_MDPDC 0x00025576 wm 32 MX6_MMDC_P0_MDSCR 0x00000000 -check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 |