diff options
Diffstat (limited to 'arch/arm/boards/mmccpu')
| -rw-r--r-- | arch/arm/boards/mmccpu/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/boards/mmccpu/config.h | 141 | ||||
| -rw-r--r-- | arch/arm/boards/mmccpu/env/bin/_update | 36 | ||||
| -rw-r--r-- | arch/arm/boards/mmccpu/env/bin/boot | 47 | ||||
| -rw-r--r-- | arch/arm/boards/mmccpu/env/bin/hush_hack | 1 | ||||
| -rw-r--r-- | arch/arm/boards/mmccpu/env/bin/init | 37 | ||||
| -rw-r--r-- | arch/arm/boards/mmccpu/env/bin/update_kernel | 15 | ||||
| -rw-r--r-- | arch/arm/boards/mmccpu/env/bin/update_root | 16 | ||||
| -rw-r--r-- | arch/arm/boards/mmccpu/env/config | 30 | ||||
| -rw-r--r-- | arch/arm/boards/mmccpu/init.c | 85 |
10 files changed, 409 insertions, 0 deletions
diff --git a/arch/arm/boards/mmccpu/Makefile b/arch/arm/boards/mmccpu/Makefile new file mode 100644 index 0000000000..eb072c0161 --- /dev/null +++ b/arch/arm/boards/mmccpu/Makefile @@ -0,0 +1 @@ +obj-y += init.o diff --git a/arch/arm/boards/mmccpu/config.h b/arch/arm/boards/mmccpu/config.h new file mode 100644 index 0000000000..1133b8f040 --- /dev/null +++ b/arch/arm/boards/mmccpu/config.h @@ -0,0 +1,141 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MASTER_CLOCK 99532800 /* peripheral = main / 2 */ + +/* values */ +#define MASTER_PLL_MUL 54 +#define MASTER_PLL_DIV 4 + +/* clocks */ +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOSCEN | \ + (255 << 8)) /* Main Oscillator Start-up Time */ +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_OUT | \ + AT91_PMC_PLLCOUNT | /* PLL Counter */ \ + (2 << 28) | /* PLL Clock Frequency Range */ \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_CSS_SLOW | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_CSS_PLLA | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) + +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +/* no pull-up for D[31:16] */ +#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 1.8V memories */ +#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ + (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V | \ + AT91_MATRIX_EBI0_CS1A_SDRAMC | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA) + +/* SDRAM */ +/* SDRAMC_MR Mode register */ +#define CONFIG_SYS_SDRC_MR_VAL1 0 +/* SDRAMC_TR - Refresh Timer register */ +#define CONFIG_SYS_SDRC_TR_VAL1 0x13c +/* SDRAMC_CR - Configuration register*/ +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_3 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* tWR - Write Recovery Delay */ \ + (8 << 12) | /* tRC - Row Cycle Delay */ \ + (2 << 16) | /* tRP - Row Precharge Delay */ \ + (2 << 20) | /* tRCD - Row to Column Delay */ \ + (5 << 24) | /* tRAS - Active to Precharge Delay */ \ + (12 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ + +/* Memory Device Register -> SDRAM */ +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 780 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup CS0 (NOR Flash) - 16-bit */ +#if 1 +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \ + AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \ + AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(6)) +#elif 0 /* slow setup */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \ + AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \ + AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(1)) +#else /* RONETIX' original values */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(6)) +#endif + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_PROCRST | \ + AT91_RSTC_RSTTYP_WAKEUP | \ + AT91_RSTC_RSTTYP_WATCHDOG) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ + AT91_WDT_WDV | \ + AT91_WDT_WDDIS | \ + AT91_WDT_WDD) + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/mmccpu/env/bin/_update b/arch/arm/boards/mmccpu/env/bin/_update new file mode 100644 index 0000000000..014bce3512 --- /dev/null +++ b/arch/arm/boards/mmccpu/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/mmccpu/env/bin/boot b/arch/arm/boards/mmccpu/env/bin/boot new file mode 100644 index 0000000000..533dea7618 --- /dev/null +++ b/arch/arm/boards/mmccpu/env/bin/boot @@ -0,0 +1,47 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xnand ]; then + root=nand + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$1 = xnor ]; then + root=nor + kernel=nor +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xnand ]; then + bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" +elif [ x$root = xnor ]; then + bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +elif [ $kernel = nor ]; then + bootm /dev/nor0.kernel +else + bootm /dev/nand0.kernel.bb +fi + diff --git a/arch/arm/boards/mmccpu/env/bin/hush_hack b/arch/arm/boards/mmccpu/env/bin/hush_hack new file mode 100644 index 0000000000..5fffa92ecd --- /dev/null +++ b/arch/arm/boards/mmccpu/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/arch/arm/boards/mmccpu/env/bin/init b/arch/arm/boards/mmccpu/env/bin/init new file mode 100644 index 0000000000..ac84bd596f --- /dev/null +++ b/arch/arm/boards/mmccpu/env/bin/init @@ -0,0 +1,37 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +if [ -e /dev/nor0 ]; then + addpart /dev/nor0 $nor_parts +fi + +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel nor [<imagename>] to update kernel into flash" + echo "type update_root nor [<imagename>] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/mmccpu/env/bin/update_kernel b/arch/arm/boards/mmccpu/env/bin/update_kernel new file mode 100644 index 0000000000..05c822d860 --- /dev/null +++ b/arch/arm/boards/mmccpu/env/bin/update_kernel @@ -0,0 +1,15 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.kernel.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.kernel +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 diff --git a/arch/arm/boards/mmccpu/env/bin/update_root b/arch/arm/boards/mmccpu/env/bin/update_root new file mode 100644 index 0000000000..a75137237b --- /dev/null +++ b/arch/arm/boards/mmccpu/env/bin/update_root @@ -0,0 +1,16 @@ +#!/bin/sh + +. /env/config + +image=$jffs2 +if [ x$1 = xnand ]; then + part=/dev/nand0.root.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.root +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 + diff --git a/arch/arm/boards/mmccpu/env/config b/arch/arm/boards/mmccpu/env/config new file mode 100644 index 0000000000..5367cd9f56 --- /dev/null +++ b/arch/arm/boards/mmccpu/env/config @@ -0,0 +1,30 @@ +#!/bin/sh + +# can be either 'net', 'nor' or 'nand'' +kernel=nor +root=nor + +uimage=uImage-mmccpu +jffs2=root-mmccpu.jffs2 + +autoboot_timeout=3 + +nfsroot="/home/kschwinne/src/pengutronix/OSELAS.BSP-Bucyrus-Grabowski-trunk/platform-Bucyrus-mmccpu/root" + +bootargs="console=ttyS0,115200 mmccpu=p299" + +#nor_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)" +nor_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),10240k(root),10240k(rootbu),-(data)" +rootpart_nor="/dev/mtdblock3" + +#nand_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)" +#rootpart_nand="/dev/mtdblock7" + +# use 'dhcp' to do dhcp in barebox and in kernel +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d diff --git a/arch/arm/boards/mmccpu/init.c b/arch/arm/boards/mmccpu/init.c new file mode 100644 index 0000000000..e010a83104 --- /dev/null +++ b/arch/arm/boards/mmccpu/init.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <fec.h> +#include <asm/armlinux.h> +#include <asm/mach-types.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <asm/io.h> +#include <asm/hardware.h> +#include <nand.h> +#include <linux/mtd/nand.h> +#include <mach/at91_pmc.h> +#include <mach/board.h> +#include <mach/gpio.h> +#include <mach/io.h> + +static struct device_d cfi_dev = { + .name = "cfi_flash", + .map_base = AT91_CHIPSELECT_0, + .size = 0, /* zero means autodetect size */ +}; + +static struct at91_ether_platform_data macb_pdata = { + .flags = AT91SAM_ETHER_MII | AT91SAM_ETHER_FORCE_LINK, + .phy_addr = 4, +}; + +static int mmccpu_devices_init(void) +{ + /* + * PB27 enables the 50MHz oscillator for Ethernet PHY + * 1 - enable + * 0 - disable + */ + at91_set_gpio_output(AT91_PIN_PB27, 1); + at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + + at91_add_device_sdram(128 * 1024 * 1024); + at91_add_device_eth(&macb_pdata); + register_device(&cfi_dev); + + devfs_add_partition("nor0", 0x00000, 256 * 1024, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x40000, 128 * 1024, PARTITION_FIXED, "env0"); + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); + armlinux_set_architecture(MACH_TYPE_MMCCPU); + + return 0; +} + +device_initcall(mmccpu_devices_init); + +static int mmccpu_console_init(void) +{ + at91_register_uart(0, 0); + return 0; +} + +console_initcall(mmccpu_console_init); |