1 files changed, 27 insertions, 67 deletions

diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
index 9d060fb589..d1a517dddb 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
@@ -1,91 +1,63 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0
 
 #include <common.h>
+#include <firmware.h>
 #include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
-#include <mach/imx8-ccm-regs.h>
-#include <mach/iomux-mx8.h>
-#include <mach/imx8-ddrc.h>
-#include <mach/xload.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/iomux-mx8mq.h>
+#include <soc/imx8m/ddr.h>
+#include <mach/imx/xload.h>
 #include <io.h>
 #include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
 #include <asm/cache.h>
 #include <asm/sections.h>
 #include <asm/mmu.h>
-#include <mach/atf.h>
-#include <mach/esdctl.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/esdctl.h>
 
 #include "ddr.h"
 
-extern char __dtb_imx8mq_evk_start[];
+extern char __dtb_z_imx8mq_evk_start[];
 
 #define UART_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
 
 static void setup_uart(void)
 {
-	void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR);
-	void __iomem *ccm   = IOMEM(MX8MQ_CCM_BASE_ADDR);
+	void __iomem *uart = IOMEM(MX8M_UART1_BASE_ADDR);
 
-	writel(CCM_CCGR_SETTINGn_NEEDED(0),
-	       ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1));
-	writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__25M_REF_CLK,
-	       ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT));
-	writel(CCM_CCGR_SETTINGn_NEEDED(0),
-	       ccm + CCM_CCGRn_SET(CCM_CCGR_UART1));
+	imx8m_early_setup_uart_clock();
 
-	imx_setup_pad(iomux, IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL);
+	imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL);
+	imx8m_uart_setup(uart);
 
-	imx8_uart_setup_ll();
+	pbl_set_putc(imx_uart_putc, uart);
 
 	putc_ll('>');
 }
 
-static void nxp_imx8mq_evk_sram_setup(void)
-{
-	ddr_init();
-}
-
 /*
  * Power-on execution flow of start_nxp_imx8mq_evk() might not be
  * obvious for a very first read, so here's, hopefully helpful,
  * summary:
  *
  * 1. MaskROM uploads PBL into OCRAM and that's where this function is
- *    executed for the first time
- *
- * 2. DDR is initialized and the TF-A trampoline is installed in the
- *    DRAM.
+ *    executed for the first time. At entry the exception level is EL3.
  *
- * 3. TF-A is executed and exits into the trampoline in RAM, which enters the
- *    PBL for the second time. DRAM setup done is indicated by a one in register
- *    x0 by the trampoline
+ * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL
+ *    part is copied from OCRAM to the TF-A return address in DRAM.
  *
- * 4. The piggydata is loaded from the SD card and copied to the expected
- *    location in the DRAM.
+ * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us
+ *    from EL3 to EL2.
  *
- * 5. Standard barebox boot flow continues
+ * 4. Standard barebox boot flow continues
  */
 static __noreturn noinline void nxp_imx8mq_evk_start(void)
 {
-	enum bootsource src = BOOTSOURCE_UNKNOWN;
-	int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
-	int ret = -ENOTSUPP;
-	const u8 *bl31;
-	size_t bl31_size;
-
-	if (IS_ENABLED(CONFIG_DEBUG_LL))
-		setup_uart();
+	setup_uart();
 
 	/*
 	 * If we are in EL3 we are running for the first time and need to
@@ -93,27 +65,15 @@ static __noreturn noinline void nxp_imx8mq_evk_start(void)
 	 * to DRAM in EL2.
 	 */
 	if (current_el() == 3) {
-		nxp_imx8mq_evk_sram_setup();
-		get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size);
-		/*
-		 * On completion the TF-A will jump to MX8MQ_ATF_BL33_BASE_ADDR in
-		 * EL2. Copy ourselves there.
-		 */
-		memcpy((void *)MX8MQ_ATF_BL33_BASE_ADDR, _text, __bss_start - _text);
-		imx8mq_atf_load_bl31(bl31, bl31_size);
-		/* not reached */
-	}
+		ddr_init();
 
-	imx8_get_boot_source(&src, &instance);
+		imx8mq_load_and_start_image_via_tfa();
+	}
 
-	if (src == BOOTSOURCE_MMC)
-		ret = imx8_esdhc_load_piggy(instance);
-	else
-		BUG_ON(ret);
 	/*
 	 * Standard entry we hit once we initialized both DDR and ATF
 	 */
-	imx8mq_barebox_entry(__dtb_imx8mq_evk_start);
+	imx8mq_barebox_entry(__dtb_z_imx8mq_evk_start);
 }
 
 ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)